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Support newer LLVM versions
Supports up to LLVM 13. - `llvm::make_unique` -> `std::make_unique`. - `Register`, referring to `llvm::opt_sched::Register`, is now explicit in most places. - `llvm::StringRef`'s conversion to `std::string` is now explicit. This exposes some inefficiencies with what we're doing.
1 parent c97ee87 commit de1b39a

15 files changed

+50
-46
lines changed

‎.gitignore‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
/build
2-
/.vscode
1+
build
2+
.vscode
33
__pycache__
44
*.pyc

‎include/opt-sched/Scheduler/lnkd_lst.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -178,9 +178,9 @@ template <class EntryType>
178178
std::unique_ptr<EntryAllocator<typename EntryType::value_type>>
179179
makeDynamicOrArenaAllocator(int MaxSize) {
180180
if (MaxSize == INVALID_VALUE)
181-
return llvm::make_unique<DynamicEntryAllocator<EntryType>>();
181+
return std::make_unique<DynamicEntryAllocator<EntryType>>();
182182
else
183-
return llvm::make_unique<ArenaEntryAllocator<EntryType>>(MaxSize);
183+
return std::make_unique<ArenaEntryAllocator<EntryType>>(MaxSize);
184184
}
185185

186186
template <class T> class LinkedList;

‎lib/Scheduler/aco.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -283,7 +283,7 @@ std::unique_ptr<InstSchedule>
283283
ACOScheduler::FindOneSchedule(InstCount TargetRPCost) {
284284
SchedInstruction *lastInst = NULL;
285285
std::unique_ptr<InstSchedule> schedule =
286-
llvm::make_unique<InstSchedule>(machMdl_, dataDepGraph_, true);
286+
std::make_unique<InstSchedule>(machMdl_, dataDepGraph_, true);
287287
InstCount maxPriority = rdyLst_->MaxPriority();
288288
if (maxPriority == 0)
289289
maxPriority = 1; // divide by 0 is bad
@@ -671,7 +671,7 @@ void PrintSchedule(InstSchedule *schedule) {
671671
void ACOScheduler::setInitialSched(InstSchedule *Sched) {
672672
if (Sched) {
673673
InitialSchedule =
674-
llvm::make_unique<InstSchedule>(machMdl_, dataDepGraph_, VrfySched_);
674+
std::make_unique<InstSchedule>(machMdl_, dataDepGraph_, VrfySched_);
675675
InitialSchedule->Copy(Sched);
676676
}
677677
}

‎lib/Scheduler/bb_spill.cpp‎

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -199,7 +199,7 @@ static InstCount ComputeSLILStaticLowerBound(int64_t regTypeCnt_,
199199
// between the recursive successor list of this instruction and the
200200
// recursive predecessors of the dependent instruction.
201201
auto recSuccBV = inst->GetRcrsvNghbrBitVector(DIR_FRWRD);
202-
for (Register *def : inst->GetDefs()) {
202+
for (opt_sched::Register *def : inst->GetDefs()) {
203203
for (const auto &dependentInst : def->GetUseList()) {
204204
auto recPredBV = const_cast<SchedInstruction *>(dependentInst)
205205
->GetRcrsvNghbrBitVector(DIR_BKWRD);
@@ -225,14 +225,15 @@ static InstCount ComputeSLILStaticLowerBound(int64_t regTypeCnt_,
225225
// based on the instructions that use more than one register (defined by
226226
// different instructions).
227227
int commonUseLowerBound = closureLowerBound;
228-
std::vector<std::pair<const SchedInstruction *, Register *>> usedInsts;
228+
std::vector<std::pair<const SchedInstruction *, opt_sched::Register *>>
229+
usedInsts;
229230
for (int i = 0; i < dataDepGraph_->GetInstCnt(); ++i) {
230231
const auto &inst = dataDepGraph_->GetInstByIndx(i);
231232

232233
// Get a list of instructions that define the registers, in array form.
233234
usedInsts.clear();
234235
llvm::transform(inst->GetUses(), std::back_inserter(usedInsts),
235-
[&](Register *reg) {
236+
[&](opt_sched::Register *reg) {
236237
assert(reg->GetDefList().size() == 1 &&
237238
"Number of defs for register is not 1!");
238239
return std::make_pair(*(reg->GetDefList().begin()), reg);
@@ -477,7 +478,7 @@ void BBWithSpill::UpdateSpillInfoForSchdul_(SchedInstruction *inst,
477478
#endif
478479

479480
// Update Live regs after uses
480-
for (Register *use : inst->GetUses()) {
481+
for (opt_sched::Register *use : inst->GetUses()) {
481482
regType = use->GetType();
482483
regNum = use->GetNum();
483484
physRegNum = use->GetPhysicalNumber();
@@ -519,7 +520,7 @@ void BBWithSpill::UpdateSpillInfoForSchdul_(SchedInstruction *inst,
519520
}
520521

521522
// Update Live regs after defs
522-
for (Register *def : inst->GetDefs()) {
523+
for (opt_sched::Register *def : inst->GetDefs()) {
523524
regType = def->GetType();
524525
regNum = def->GetNum();
525526
physRegNum = def->GetPhysicalNumber();
@@ -575,7 +576,7 @@ void BBWithSpill::UpdateSpillInfoForSchdul_(SchedInstruction *inst,
575576
sumOfLiveIntervalLengths_[i] += liveRegs_[i].GetOneCnt();
576577
for (int j = 0; j < liveRegs_[i].GetSize(); ++j) {
577578
if (liveRegs_[i].GetBit(j)) {
578-
const Register *reg = regFiles_[i].GetReg(j);
579+
const opt_sched::Register *reg = regFiles_[i].GetReg(j);
579580
if (!reg->IsInInterval(inst) && !reg->IsInPossibleInterval(inst)) {
580581
++dynamicSlilLowerBound_;
581582
}
@@ -636,7 +637,7 @@ void BBWithSpill::UpdateSpillInfoForUnSchdul_(SchedInstruction *inst) {
636637
for (int i = 0; i < regTypeCnt_; ++i) {
637638
for (int j = 0; j < liveRegs_[i].GetSize(); ++j) {
638639
if (liveRegs_[i].GetBit(j)) {
639-
const Register *reg = regFiles_[i].GetReg(j);
640+
const opt_sched::Register *reg = regFiles_[i].GetReg(j);
640641
sumOfLiveIntervalLengths_[i]--;
641642
if (!reg->IsInInterval(inst) && !reg->IsInPossibleInterval(inst)) {
642643
--dynamicSlilLowerBound_;
@@ -649,7 +650,7 @@ void BBWithSpill::UpdateSpillInfoForUnSchdul_(SchedInstruction *inst) {
649650
}
650651

651652
// Update Live regs
652-
for (Register *def : inst->GetDefs()) {
653+
for (opt_sched::Register *def : inst->GetDefs()) {
653654
regType = def->GetType();
654655
regNum = def->GetNum();
655656
physRegNum = def->GetPhysicalNumber();
@@ -674,7 +675,7 @@ void BBWithSpill::UpdateSpillInfoForUnSchdul_(SchedInstruction *inst) {
674675
//}
675676
}
676677

677-
for (Register *use : inst->GetUses()) {
678+
for (opt_sched::Register *use : inst->GetUses()) {
678679
regType = use->GetType();
679680
regNum = use->GetNum();
680681
physRegNum = use->GetPhysicalNumber();
@@ -1091,8 +1092,8 @@ bool BBWithSpill::ChkInstLglty(SchedInstruction *inst) {
10911092
/*
10921093
int16_t regType;
10931094
int defCnt, physRegNum;
1094-
Register **defs;
1095-
Register *def, *liveDef;
1095+
opt_sched::Register **defs;
1096+
opt_sched::Register *def, *liveDef;
10961097
10971098
#ifdef IS_DEBUG_CHECK
10981099
Logger::Info("Checking inst %d %s", inst->GetNum(), inst->GetOpCode());
@@ -1111,7 +1112,7 @@ bool BBWithSpill::ChkInstLglty(SchedInstruction *inst) {
11111112
}
11121113
11131114
// Update Live regs
1114-
for (Register *def : inst->GetDefs()) {
1115+
for (opt_sched::Register *def : inst->GetDefs()) {
11151116
regType = def->GetType();
11161117
physRegNum = def->GetPhysicalNumber();
11171118

‎lib/Scheduler/data_dep.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -197,7 +197,7 @@ DataDepGraph::DataDepGraph(MachineModel *machMdl, LATENCY_PRECISION ltncyPrcsn)
197197
entryInstCnt_ = 0;
198198
exitInstCnt_ = 0;
199199

200-
RegFiles = llvm::make_unique<RegisterFile[]>(machMdl_->GetRegTypeCnt());
200+
RegFiles = std::make_unique<RegisterFile[]>(machMdl_->GetRegTypeCnt());
201201
}
202202

203203
DataDepGraph::~DataDepGraph() {

‎lib/Scheduler/graph_trans_ilp.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -158,7 +158,7 @@ StaticNodeSupILPTrans::DataAlloc::DataAlloc(DataDepGraph &DDG)
158158
SuperiorNodesList(
159159
createSuperiorNodesList(wrapAs2D(SuperiorArray, DDG.GetNodeCnt()))),
160160
AddedEdges(), Stats(),
161-
Data_(llvm::make_unique<Data>(Data{
161+
Data_(std::make_unique<Data>(Data{
162162
DDG,
163163
wrapAs2D(this->DistanceTable, DDG.GetNodeCnt()),
164164
wrapAs2D(this->SuperiorArray, DDG.GetNodeCnt()),

‎lib/Scheduler/register.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,7 @@ void RegisterFile::ResetCrntLngths() {
165165

166166
Register *RegisterFile::getNext() {
167167
size_t RegNum = Regs.size();
168-
auto Reg = llvm::make_unique<Register>();
168+
auto Reg = std::make_unique<Register>();
169169
Reg->SetType(regType_);
170170
Reg->SetNum(RegNum);
171171
Regs.push_back(std::move(Reg));
@@ -178,7 +178,7 @@ void RegisterFile::SetRegCnt(int regCnt) {
178178

179179
Regs.resize(regCnt);
180180
for (int i = 0; i < getCount(); i++) {
181-
auto Reg = llvm::make_unique<Register>();
181+
auto Reg = std::make_unique<Register>();
182182
Reg->SetType(regType_);
183183
Reg->SetNum(i);
184184
Regs[i] = std::move(Reg);

‎lib/Scheduler/sched_region.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,7 @@ static bool isBbEnabled(Config &schedIni, Milliseconds rgnTimeout) {
146146

147147
static void dumpDDG(DataDepGraph *DDG, llvm::StringRef DDGDumpPath,
148148
llvm::StringRef Suffix = "") {
149-
std::string Path = DDGDumpPath;
149+
std::string Path(DDGDumpPath);
150150
Path += DDG->GetDagID();
151151

152152
if (!Suffix.empty()) {

‎lib/Wrapper/AMDGPU/GCNOptSched.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ static cl::opt<bool>
2222

2323
static ScheduleDAGInstrs *createOptSchedGCN(MachineSchedContext *C) {
2424
ScheduleDAGMILive *DAG = new ScheduleDAGOptSchedGCN(
25-
C, llvm::make_unique<GCNMaxOccupancySchedStrategy>(C));
25+
C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
2626
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
2727
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
2828
return DAG;

‎lib/Wrapper/AMDGPU/OptSchedDDGWrapperGCN.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ namespace {
2929

3030
std::unique_ptr<SubRegSet>
3131
createSubRegSet(unsigned Reg, const MachineRegisterInfo &MRI, int16_t Type) {
32-
return llvm::make_unique<SubRegSet>(
32+
return std::make_unique<SubRegSet>(
3333
MRI.getMaxLaneMaskForVReg(Reg).getNumLanes(), Type);
3434
}
3535

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