Changes for new chipflow-lib software generator infrastructure

Author: robtaylor

mcu_soc/chipflow.toml

@@ -6,7 +6,6 @@ soc = "design.design:MySoC"
 
 [chipflow.steps]
 board = "design.steps.board:MyBoardStep"
-software = "design.steps.software:MySoftwareStep"
 
 [chipflow.silicon]
 process = "ihp_sg13g2"

mcu_soc/design/design.py

@@ -1,7 +1,5 @@
-from pprint import pformat
 
-from chipflow_lib.platforms.sim import SimPlatform
-from chipflow_lib.software.soft_gen import SoftwareGenerator
+from pathlib import Path
 
 from amaranth import Module
 from amaranth.lib import wiring
@@ -15,7 +13,12 @@
 from amaranth_soc.wishbone.sram import WishboneSRAM
 from chipflow_digital_ip.io import GPIOPeripheral, UARTPeripheral, SPIPeripheral, I2CPeripheral
 from chipflow_digital_ip.processors import CV32E40P, OBIDebugModule
-from chipflow_lib.platforms import GPIOSignature, UARTSignature, SPISignature, I2CSignature, QSPIFlashSignature, JTAGSignature, attach_simulation_data
+from chipflow_lib.platforms import (
+        GPIOSignature, UARTSignature, SPISignature, I2CSignature,
+        QSPIFlashSignature, JTAGSignature,
+        attach_data, SoftwareBuild
+        )
+
 from .ips.pwm import PWMPins, PWMPeripheral
 # from .ips.pdm import PDMPeripheral
 
@@ -99,13 +102,6 @@ def elaborate(self, platform):
 
         connect(m, wb_arbiter.bus, wb_decoder.bus)
 
-        # Software
-
-        sw = SoftwareGenerator(rom_start=self.bios_start, rom_size=0x00100000,
-                               # place BIOS data in SRAM
-                               ram_start=self.mem_sram_base, ram_size=self.sram_size)
-
-
         # CPU
 
         cpu = CV32E40P(config="default", reset_vector=self.bios_start, dm_haltaddress=self.debug_base+0x800)
@@ -133,15 +129,12 @@ def elaborate(self, platform):
         # SPI flash
 
         spiflash = QSPIFlash(addr_width=24, data_width=32)
-        wb_decoder .add(spiflash.wb_bus, addr=self.mem_spiflash_base)
+        wb_decoder.add(spiflash.wb_bus, name="spiflash", addr=self.mem_spiflash_base)
         csr_decoder.add(spiflash.csr_bus, name="spiflash", addr=self.csr_spiflash_base - self.csr_base)
         m.submodules.spiflash = spiflash
 
-        print(f"spiflash = {spiflash}")
         connect(m, flipped(self.flash), spiflash.pins)
 
-        sw.add_periph("spiflash",   "SPIFLASH", self.csr_spiflash_base)
-
         # SRAM
 
         sram = WishboneSRAM(size=self.sram_size, data_width=32, granularity=8)
@@ -155,7 +148,6 @@ def elaborate(self, platform):
 
             base_addr = self.csr_user_spi_base + i * self.periph_offset
             csr_decoder.add(user_spi.bus, name=f"user_spi_{i}", addr=base_addr  - self.csr_base)
-            sw.add_periph("spi", f"USER_SPI_{i}", base_addr)
 
             # FIXME: These assignments will disappear once we have a relevant peripheral available
             pins = getattr(self, f"user_spi_{i}")
@@ -168,7 +160,6 @@ def elaborate(self, platform):
             gpio = GPIOPeripheral(pin_count=self.gpio_width)
             base_addr = self.csr_gpio_base + i * self.periph_offset
             csr_decoder.add(gpio.bus, name=f"gpio_{i}", addr=base_addr - self.csr_base)
-            sw.add_periph("gpio", f"GPIO_{i}", base_addr)
 
             pins = getattr(self, f"gpio_{i}")
             connect(m, flipped(pins), gpio.pins)
@@ -179,7 +170,6 @@ def elaborate(self, platform):
             uart = UARTPeripheral(init_divisor=int(25e6//115200), addr_width=5)
             base_addr = self.csr_uart_base + i * self.periph_offset
             csr_decoder.add(uart.bus, name=f"uart_{i}", addr=base_addr - self.csr_base)
-            sw.add_periph("uart", f"UART_{i}", base_addr)
 
             pins = getattr(self, f"uart_{i}")
             connect(m, flipped(pins), uart.pins)
@@ -192,7 +182,6 @@ def elaborate(self, platform):
 
             base_addr = self.csr_i2c_base + i * self.periph_offset
             csr_decoder.add(i2c.bus, name=f"i2c_{i}", addr=base_addr - self.csr_base)
-            sw.add_periph("i2c", f"I2C_{i}", base_addr)
 
             i2c_pins = getattr(self, f"i2c_{i}")
             connect(m, flipped(i2c_pins), i2c.i2c_pins)
@@ -205,7 +194,6 @@ def elaborate(self, platform):
             base_addr = self.csr_motor_base + i * self.motor_offset
             csr_decoder.add(motor_pwm.bus, name=f"motor_pwm{i}", addr=base_addr - self.csr_base)
 
-            sw.add_periph("motor_pwm", f"MOTOR_PWM{i}", base_addr)
             setattr(m.submodules, f"motor_pwm{i}", motor_pwm)
 
         # # pdm_ao
@@ -214,7 +202,6 @@ def elaborate(self, platform):
         #     base_addr = self.csr_pdm_ao_base + i * self.pdm_ao_offset
         #     csr_decoder.add(pdm.bus, name=f"pdm{i}", addr=base_addr  - self.csr_base)
         # 
-        #     sw.add_periph("pdm", f"PDM{i}", base_addr)
         #     setattr(m.submodules, f"pdm{i}", pdm)
         #     m.d.comb += getattr(self, f"pdm_ao_{i}").eq(pdm.pdm_ao)
 
@@ -236,16 +223,12 @@ def elaborate(self, platform):
 
         # m.submodules.jtag_provider = platform.providers.JTAGProvider(debug)
 
-        sw.add_periph("soc_id",     "SOC_ID",   self.csr_soc_id_base)
-        #sw.add_periph("gpio",       "BTN_GPIO", self.csr_btn_gpio_base)
+        sw = SoftwareBuild(sources=Path('design/software').glob('*.c'),
+                           offset=self.bios_start)
 
-        sw.generate("build/software/generated")
-        attach_simulation_data(self.flash, file_name="build/software/software.bin", offset=self.bios_start)
+        # you need to attach data to both the internal and external interfaces
+        attach_data(self.flash, m.submodules.spiflash, sw)
 
-        print(f"CSR resources :\n{pformat(list(csr_decoder.bus.memory_map.all_resources()), indent=2)}")
-        print(f"CSR memory map:\n{pformat(csr_decoder.bus.memory_map._namespace._assignments, indent=2)}")
-        print(f"CSR decoder subs:\n{pformat(csr_decoder._subs, indent=2)}")
-        print(f"Wishbone memory map:\n{pformat(wb_decoder.bus.memory_map._namespace._assignments, indent=2)}")
         return m
 
 

mcu_soc/design/software/drivers/motor_pwm.h renamed to mcu_soc/design/ips/drivers/motor_pwm.h

@@ -5,7 +5,8 @@
 from amaranth.lib.wiring import In, Out, flipped, connect
 from amaranth_soc import csr
 
-from chipflow_lib.platforms import OutputIOSignature
+from chipflow_lib.platforms import OutputIOSignature, SoftwareDriverSignature
+
 
 __all__ = ["PDMPeripheral"]
 
@@ -34,10 +35,16 @@ def __init__(self, *, bitwidth):
 
         self._bridge = csr.Bridge(regs.as_memory_map())
 
-        super().__init__({
-            "bus": In(csr.Signature(addr_width=addr_width, data_width=data_width)),
-            "pdm": Out(self.WiringSignature)
-            })
+        super().__init__(
+            SoftwareDriverSignature(
+                members={
+                    "bus": In(csr.Signature(addr_width=addr_width, data_width=data_width)),
+                    "pdm": Out(self.WiringSignature)
+                },
+                component=self,
+                regs_struct='pdm_regs_t',
+                h_files=['drivers/pdm.h'])
+            )
 
         self.bus.memory_map = self._bridge.bus.memory_map
 
@@ -48,7 +55,7 @@ def bitwidth(self):
     def elaborate(self, platform):
         m = Module()
         m.submodules.bridge = self._bridge
-        maxval = Const(int((2**self._bitwidth)-1), unsigned(self._bitwidth))        
+        maxval = Const(int((2**self._bitwidth)-1), unsigned(self._bitwidth))
         error = Signal(unsigned(self._bitwidth), init=0x0)
         error_0 = Signal(unsigned(self._bitwidth), init=0x0)
         error_1 = Signal(unsigned(self._bitwidth), init=0x0)

mcu_soc/design/software/drivers/pdm.h renamed to mcu_soc/design/ips/drivers/pdm.h

@@ -6,7 +6,7 @@
 from amaranth.lib.cdc import FFSynchronizer
 from amaranth_soc import csr
 
-from chipflow_lib.platforms import OutputIOSignature, InputIOSignature
+from chipflow_lib.platforms import OutputIOSignature, InputIOSignature, SoftwareDriverSignature
 
 __all__ = ["PWMPeripheral", "PWMPins"]
 
@@ -42,17 +42,17 @@ class Conf(csr.Register, access="rw"):
         """
         en: csr.Field(csr.action.RW, unsigned(1))
         dir: csr.Field(csr.action.RW, unsigned(1))
- 
+
     class Stop_int(csr.Register, access="rw"):
         """Stop_int register
         """
-        stopped: csr.Field(csr.action.RW1C, unsigned(1))   
-            
+        stopped: csr.Field(csr.action.RW1C, unsigned(1))
+
     class Status(csr.Register, access="r"):
         """Status register
         """
-        stop_pin: csr.Field(csr.action.R, unsigned(1))   
-      
+        stop_pin: csr.Field(csr.action.R, unsigned(1))
+
     """pwm peripheral."""
     def __init__(self, *, pins):
         self.pins = pins
@@ -67,17 +67,24 @@ def __init__(self, *, pins):
 
         self._bridge = csr.Bridge(regs.as_memory_map())
 
-        super().__init__({
-            "bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
-        })
+        super().__init__(
+            SoftwareDriverSignature(
+                members={
+                    "bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
+                },
+                component=self,
+                regs_struct='motor_pwm_regs_t',
+                h_files=['drivers/motor_pwm.h'])
+            )
+
         self.bus.memory_map = self._bridge.bus.memory_map
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.bridge = self._bridge       
+        m.submodules.bridge = self._bridge
         count = Signal(unsigned(16), init=0x0)
         connect(m, flipped(self.bus), self._bridge.bus)
-        
+
         #synchronizer
         stop = Signal()
         m.submodules += FFSynchronizer(i=self.pins.stop.i, o=stop)
@@ -87,12 +94,12 @@ def elaborate(self, platform):
             m.d.sync += count.eq(count+1)
         with m.Else():
             m.d.sync += count.eq(0)
-            
+
         with m.If((self._numr.f.val.data > 0) & (count <= self._numr.f.val.data) & (self._conf.f.en.data == 1) & (self._stop_int.f.stopped.data == 0 )):
             m.d.comb += self.pins.pwm.o.eq(1)
         with m.Else():
             m.d.comb += self.pins.pwm.o.eq(0)
-            
+
         with m.If(count >= self._denom.f.val.data):
             m.d.sync += count.eq(0)
 

mcu_soc/design/ips/pdm.py

@@ -1,4 +1,4 @@
-from chipflow_lib.software.soft_gen import SoftwareGenerator
+from pathlib import Path
 
 from amaranth import Module
 from amaranth.lib import wiring
@@ -15,7 +15,8 @@
 
 from minerva.core import Minerva
 
-from chipflow_lib.platforms import Sky130DriveMode, GPIOSignature, UARTSignature, QSPIFlashSignature, attach_simulation_data
+from chipflow_lib.platforms import Sky130DriveMode, GPIOSignature, UARTSignature, QSPIFlashSignature, attach_data, SoftwareBuild
+
 
 __all__ = ["MySoC"]
 
@@ -64,13 +65,6 @@ def elaborate(self, platform):
 
         connect(m, wb_arbiter.bus, wb_decoder.bus)
 
-        # Software
-
-        sw = SoftwareGenerator(rom_start=self.bios_start, rom_size=0x00100000,
-                               # place BIOS data in SRAM
-                               ram_start=self.mem_sram_base, ram_size=self.sram_size)
-
-
         # CPU
 
         cpu = Minerva(reset_address=self.bios_start, with_muldiv=True)
@@ -82,14 +76,12 @@ def elaborate(self, platform):
         # QSPI Flash
 
         spiflash = QSPIFlash(addr_width=24, data_width=32)
-        wb_decoder .add(spiflash.wb_bus, addr=self.mem_spiflash_base)
+        wb_decoder .add(spiflash.wb_bus, name="spiflash", addr=self.mem_spiflash_base)
         csr_decoder.add(spiflash.csr_bus, name="spiflash", addr=self.csr_spiflash_base - self.csr_base)
         m.submodules.spiflash = spiflash
 
         connect(m, flipped(self.flash), spiflash.pins)
 
-        sw.add_periph("spiflash",   "SPIFLASH", self.csr_spiflash_base)
-
         # SRAM
 
         sram = WishboneSRAM(size=self.sram_size, data_width=32, granularity=8)
@@ -98,25 +90,22 @@ def elaborate(self, platform):
         m.submodules.sram = sram
 
         # GPIOs
-        m.submodules.gpio0 = gpio0 = GPIOPeripheral(pin_count=8)
-        csr_decoder.add(gpio0.bus, name="gpio_0", addr=self.csr_gpio_base - self.csr_base)
-        sw.add_periph("gpio", "GPIO_0", self.csr_gpio_base)
+        m.submodules.gpio_0 = gpio_0 = GPIOPeripheral(pin_count=8)
+        csr_decoder.add(gpio_0.bus, name="gpio_0", addr=self.csr_gpio_base - self.csr_base)
 
-        connect(m, flipped(self.gpio_0), gpio0.pins)
+        connect(m, flipped(self.gpio_0), gpio_0.pins)
 
         m.submodules.gpio_open_drain = gpio_open_drain = GPIOPeripheral(pin_count=4)
         csr_decoder.add(gpio_open_drain.bus, name="gpio_open_drain", addr=self.csr_gpio_base + self.periph_offset - self.csr_base)
-        sw.add_periph("gpio", "GPIO_OPEN_DRAIN", self.csr_gpio_base + self.periph_offset)
 
         connect(m, flipped(self.gpio_open_drain), gpio_open_drain.pins)
 
 
         # UART
-        m.submodules.uart = uart = UARTPeripheral(init_divisor=int(25e6//115200), addr_width=5)
-        csr_decoder.add(uart.bus, name="uart_0", addr=self.csr_uart_base - self.csr_base)
-        sw.add_periph("uart", "UART_0", self.csr_uart_base)
+        m.submodules.uart_0 = uart_0 = UARTPeripheral(init_divisor=int(25e6//115200), addr_width=5)
+        csr_decoder.add(uart_0.bus, name="uart_0", addr=self.csr_uart_base - self.csr_base)
 
-        connect(m, flipped(self.uart_0), uart.pins)
+        connect(m, flipped(self.uart_0), uart_0.pins)
 
         # SoC ID
 
@@ -132,10 +121,11 @@ def elaborate(self, platform):
 
         m.submodules.wb_to_csr = wb_to_csr
 
-        sw.add_periph("soc_id",     "SOC_ID",   self.csr_soc_id_base)
+        sw = SoftwareBuild(sources=Path('design/software').glob('*.c'),
+                           offset=self.bios_start)
 
-        sw.generate("build/software/generated")
-        attach_simulation_data(self.flash, file_name="build/software/software.bin", offset=self.bios_start)
+        # you need to attach data to both the internal and external interfaces
+        attach_data(self.flash, m.submodules.spiflash, sw)
         return m