Allow configuration of number of simulation steps

Author: robtaylor

chipflow_lib/common/sim/main.cc.jinja

@@ -70,7 +70,7 @@ int main(int argc, char **argv) {
     top.{{reset}}.set(true);
     {% endfor %}
 
-    for (int i = 0; i < 3000000; i++)
+    for (int i = 0; i < {{num_steps}}; i++)
         tick();
 
     close_event_log();

chipflow_lib/config_models.py

@@ -19,13 +19,16 @@ class SiliconConfig(BaseModel):
     debug: Optional[Dict[str, bool]] = None
     # This is still kept around to allow forcing pad locations.
 
+class SimulationConfig(BaseModel):
+    num_steps: int = 3000000
 
 class ChipFlowConfig(BaseModel):
     """Root configuration for chipflow.toml."""
     project_name: str
     top: Dict[str, Any] = {}
     steps: Optional[Dict[str, str]] = None
     silicon: Optional[SiliconConfig] = None
+    simulation: SimulationConfig = SimulationConfig()
     clock_domains: Optional[List[str]] = None
 
 

chipflow_lib/platforms/sim.py

@@ -237,7 +237,8 @@ def build(self, e, top):
                     interfaces = [exp for exp in self._top_sim.keys()],
                     clocks = [cxxrtlmangle(f"io${clk}$i") for clk in self._clocks.keys()],
                     resets = [cxxrtlmangle(f"io${rst}$i") for rst in self._resets.keys()],
-                    data_load = data_load
+                    data_load = data_load,
+                    num_steps = self._config.chipflow.simulation.num_steps,
                 ),
                 file=main_file)