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1 parent f35273f commit 5fd1446Copy full SHA for 5fd1446
amaranth_soc/csr/reg.py
@@ -446,7 +446,6 @@ class Register(wiring.Component):
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def __init_subclass__(cls, *, access=None, **kwargs):
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if access is not None:
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cls._access = Element.Access(access)
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- cls.__doc__ = cls._doc_template.format(parameters="")
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super().__init_subclass__(**kwargs)
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def __init__(self, fields=None, access=None):
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