From e7e0e57eb1db3adb286616c8a593619270ca6419 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 28 Nov 2022 08:45:14 -0800 Subject: [PATCH] Enable RoCC instructions after context switches --- arch/riscv/include/asm/switch_to.h | 3 +++ arch/riscv/kernel/process.c | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 407bcc96a71093..cfd3df93948a2c 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -42,6 +42,9 @@ static inline void fstate_restore(struct task_struct *task, __fstate_restore(task); __fstate_clean(regs); } +#ifdef CONFIG_RISCV_ROCC + regs->status |= SR_XS_INITIAL; +#endif } static inline void __switch_to_aux(struct task_struct *prev, diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 7a7df8c27d5bb2..1e192ce0ad64ab 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -68,9 +68,6 @@ void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp) { regs->status = SR_PIE; -#ifdef CONFIG_RISCV_ROCC - regs->status |= SR_XS_INITIAL; -#endif if (has_fpu) { regs->status |= SR_FS_INITIAL; /* @@ -79,6 +76,9 @@ void start_thread(struct pt_regs *regs, unsigned long pc, */ fstate_restore(current, regs); } +#ifdef CONFIG_RISCV_ROCC + regs->status |= SR_XS_INITIAL; +#endif regs->epc = pc; regs->sp = sp; set_fs(USER_DS);