ports/cheriot-rtos: Merge pull request #2 from JakeTrevor/cheriot-dev

Added I2C and UART implementations for sonata.

Author: djlowther

ports/cheriot-rtos/Makefile

@@ -51,36 +51,42 @@ SRC_C = mp_entry.c \
 	shared/runtime/pyexec.c \
 	$(BUILD)/_frozen_mpy.c \
 	machine_pin.c \
-	machine_spi.c
+	machine_spi.c \
+	machine_i2c.c
 
-SRC_CXX =
+SRC_CXX = 
 
-SRC_QSTR += shared/readline/readline.c shared/runtime/pyexec.c mp_entry.c machine_pin.c machine_spi.c
+SRC_QSTR += shared/readline/readline.c shared/runtime/pyexec.c mp_entry.c machine_pin.c machine_spi.c machine_i2c.c
 
 SRC_HAL_C = shared/runtime/stdout_helpers.c
-SRC_HAL_CXX = uart_core.cpp
+SRC_HAL_CXX = uart_core.cpp hal/i2c.cpp hal/uart.cpp hal/timer.cpp
 
 SRC_MAIN_C =
 SRC_MAIN_CXX = main.cpp 
 
-OBJ += $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
-OBJ += $(addprefix $(BUILD)/, $(SRC_CXX:.cpp=.o))
-OBJ += $(PY_O)
+OBJ_VM += $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
+OBJ_VM += $(addprefix $(BUILD)/, $(SRC_CXX:.cpp=.o))
+OBJ_VM += $(PY_O)
 
 OBJ_HAL += $(addprefix $(BUILD)/, $(SRC_HAL_C:.c=.o))
 OBJ_HAL += $(addprefix $(BUILD)/, $(SRC_HAL_CXX:.cpp=.o))
 
 OBJ_MAIN += $(addprefix $(BUILD)/, $(SRC_MAIN_C:.c=.o))
 OBJ_MAIN += $(addprefix $(BUILD)/, $(SRC_MAIN_CXX:.cpp=.o))
+ 
+OBJ += $(OBJ_VM) 
+OBJ += $(OBJ_HAL)
+OBJ += $(OBJ_MAIN)
 
-$(OBJ): CFLAGS += -DMP_VM_COMP -cheri-compartment=mp_vm
+$(OBJ_VM): CFLAGS += -DMP_VM_COMP -cheri-compartment=mp_vm
 $(OBJ_HAL): CFLAGS += -cheri-compartment=mp_hal
 $(OBJ_MAIN): CFLAGS += -cheri-compartment=main
 $(BUILD)/mp_entry.o: CFLAGS += -UCHERIOT_NO_AMBIENT_MALLOC
+$(BUILD)/hal/i2c.o: CFLAGS += -Wno-unused-variable
 
 all: $(BUILD)/micropython.uf2
 
-all_objects : $(OBJ) $(OBJ_HAL) $(OBJ_MAIN)
+all_objects : $(OBJ_VM) $(OBJ_HAL) $(OBJ_MAIN)
 .PHONY: all all_objects
 
 $(BUILD)/_frozen_mpy.c: $(TOP)/tests/frozen/frozentest.mpy $(BUILD)/genhdr/qstrdefs.generated.h
@@ -90,7 +96,7 @@ $(BUILD)/_frozen_mpy.c: $(TOP)/tests/frozen/frozentest.mpy $(BUILD)/genhdr/qstrd
 $(BUILD)/xmake.lua: xmake.lua.top xmake.lua.bottom 
 	cat xmake.lua.top > $@
 	echo "compartment(\"mp_vm\")" >> $@
-	for OFILE in $(patsubst $(BUILD)/%,%,$(OBJ)) ; do echo "    add_files(\"$$OFILE\", {rule = \"utils.merge.object\"})" >> $@ ; done
+	for OFILE in $(patsubst $(BUILD)/%,%,$(OBJ_VM)) ; do echo "    add_files(\"$$OFILE\", {rule = \"utils.merge.object\"})" >> $@ ; done
 	echo "compartment(\"mp_hal\")" >> $@
 	for OFILE in $(patsubst $(BUILD)/%,%,$(OBJ_HAL)) ; do echo "    add_files(\"$$OFILE\", {rule = \"utils.merge.object\"})" >> $@ ; done
 	echo "compartment(\"main\")" >> $@

ports/cheriot-rtos/hal/i2c.cpp

@@ -0,0 +1,35 @@
+#include <stdio.h>
+#include <platform-i2c.hh>
+
+#include "mphalport.h"
+
+void MP_HAL_FUNC i2c_setup(volatile OpenTitanI2c *i2c, uint32_t freq_kHz) {
+    i2c->reset_fifos();
+    i2c->host_mode_set();
+    i2c->speed_set(freq_kHz);
+}
+
+bool MP_HAL_FUNC i2c_blocking_read(volatile OpenTitanI2c *i2c, uint8_t addr, uint8_t *buf, uint32_t len) {
+    return i2c->blocking_read(addr, buf, len);
+}
+
+bool MP_HAL_FUNC i2c_check_success(volatile OpenTitanI2c *i2c) {
+    while (!i2c->format_is_empty()) {
+    }
+    if (i2c->interrupt_is_asserted(OpenTitanI2cInterrupt::Nak)) {
+        i2c->interrupt_clear(OpenTitanI2cInterrupt::Nak);
+        return false;
+    }
+    return true;
+}
+
+bool MP_HAL_FUNC i2c_blocking_write(volatile OpenTitanI2c *i2c, uint8_t addr, uint8_t *buf, uint32_t len, bool skipStop) {
+    i2c->blocking_write(addr, buf, len, skipStop);
+    return i2c_check_success(i2c);
+}
+
+
+bool MP_HAL_FUNC i2c_send_address(volatile OpenTitanI2c *i2c, uint8_t addr) {
+    i2c->blocking_write_byte(OpenTitanI2c::FormatDataStart | OpenTitanI2c::FormatDataStop | (addr << 1) | 1u);
+    return i2c_check_success(i2c);
+}

ports/cheriot-rtos/hal/timer.cpp

@@ -0,0 +1,83 @@
+#include <cheri.hh>
+#include <stdint.h>
+#include <utils.hh>
+
+#include "mphalport.h"
+
+class StandardClint : private utils::NoCopyNoMove
+{
+public:
+/**
+	 * Initialise the interface.
+	 */
+static void init() {
+    // This needs to be csr_read(mhartid) if we support multicore
+    // systems, but we don't plan to any time soon.
+    constexpr uint32_t HartId = 0;
+
+    auto setField = [&](auto &field, size_t offset, size_t size) {
+            CHERI::Capability capability{MMIO_CAPABILITY(uint32_t, clint)};
+            capability.address() += offset;
+            capability.bounds() = size;
+            field = capability;
+        };
+    setField(pmtimer, StandardClint::ClintMtime, 2 * sizeof(uint32_t));
+    setField(pmtimercmp,
+        StandardClint::ClintMtimecmp + HartId * 8,
+        2 * sizeof(uint32_t));
+}
+
+static uint64_t time() {
+    // The timer is little endian, so the high 32 bits are after the low 32
+    // bits. We can't do atomic 64-bit loads and so we have to read these
+    // separately.
+    volatile uint32_t *timerHigh = pmtimer + 1;
+    uint32_t timeLow, timeHigh;
+
+    // Read the current time. Loop until the high 32 bits are stable.
+    do
+    {
+        timeHigh = *timerHigh;
+        timeLow = *pmtimer;
+    } while (timeHigh != *timerHigh);
+    return (uint64_t(timeHigh) << 32) | timeLow;
+}
+
+private:
+#ifdef IBEX_SAFE
+/**
+	 * The Ibex-SAFE platform doesn't implement a complete CLINT, only the
+	 * timer part (which is all that we use).  Its offsets within the CLINT
+	 * region are different.
+	 */
+static constexpr size_t ClintMtime = 0x10;
+static constexpr size_t ClintMtimecmp = 0x18;
+#else
+/**
+	 * The standard RISC-V CLINT is a large memory-mapped device and places the
+	 * timers a long way in.
+	 */
+static constexpr size_t ClintMtimecmp = 0x4000U;
+static constexpr size_t ClintMtime = 0xbff8U;
+#endif
+
+static inline volatile uint32_t *pmtimercmp;
+static inline volatile uint32_t *pmtimer;
+};
+
+using TimerCore = StandardClint;
+
+
+uint64_t MP_HAL_FUNC get_time() {
+    StandardClint::init();
+    return StandardClint::time();
+}
+
+// void MP_HAL_FUNC set_next(uint64_t next_time) {
+//     StandardClint::init();
+//     StandardClint::setnext(next_time);
+// }
+
+// void MP_HAL_FUNC clear() {
+//     StandardClient::clear();
+// }

ports/cheriot-rtos/hal/timer.h

@@ -0,0 +1,7 @@
+#include "py/obj.h"
+#include "mphalport.h"
+
+#define CLOCK_FREQ_KHZ (50000)
+#define MS_TO_CLOCK_CYCLES(x) (x * CLOCK_FREQ_KHZ) // clock 50mHz
+
+uint64_t MP_HAL_FUNC get_time();

ports/cheriot-rtos/hal/uart.cpp

@@ -0,0 +1,41 @@
+#include <platform-uart.hh>
+
+#include "mphalport.h"
+#include "timer.h"
+
+uint8_t MP_HAL_FUNC uart_get_rx_level(volatile OpenTitanUart *block) {
+    return block->receive_fifo_level();
+}
+
+uint8_t MP_HAL_FUNC uart_get_tx_level(volatile OpenTitanUart *block) {
+    return block->transmit_fifo_level();
+}
+
+bool MP_HAL_FUNC uart_is_readable(volatile OpenTitanUart *block) {
+    return block->can_read();
+}
+
+bool MP_HAL_FUNC uart_is_writable(volatile OpenTitanUart *block) {
+    return block->can_write();
+}
+
+bool MP_HAL_FUNC uart_timeout_read(volatile OpenTitanUart *block, uint8_t *out, uint32_t timeout_ms) {
+    uint32_t t_end = get_time() + MS_TO_CLOCK_CYCLES(timeout_ms);
+
+    while (!block->can_read()) {
+        if (get_time() > t_end) {
+            return false;
+        }
+    }
+
+    *out = block->readData;
+    return true;
+}
+
+void MP_HAL_FUNC uart_blocking_write(volatile OpenTitanUart *block, uint8_t data) {
+    block->blocking_write(data);
+}
+
+void MP_HAL_FUNC uart_init(volatile OpenTitanUart *block, uint32_t baudrate) {
+    block->init(baudrate);
+}

ports/cheriot-rtos/machine_i2c.c

@@ -0,0 +1,123 @@
+#include <stdio.h>
+
+#include "py/obj.h"
+#include "py/runtime.h"
+#include "extmod/modmachine.h"
+
+#include "mphalport.h"
+
+#define I2C_DEFAULT_FREQ (400000)
+
+#define SPI_0_ADDR (0x80200000)
+#define SPI_1_ADDR (0x80201000)
+
+
+typedef struct _machine_i2c_obj_t {
+    mp_obj_base_t base;
+    volatile open_titan_i2c_t *i2c_block;
+} machine_i2c_obj_t;
+
+
+static void machine_i2c_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
+    machine_i2c_obj_t *self = (machine_i2c_obj_t *)MP_OBJ_TO_PTR(self_in);
+    const char *name;
+
+    switch ((ptraddr_t)self->i2c_block) {
+        case SPI_0_ADDR:
+            name = "0";
+            break;
+        case SPI_1_ADDR:
+            name = "1";
+            break;
+        default:
+            name = "Unknown SPI device";
+            break;
+    }
+
+    mp_printf(print, "I2C(%s)", name);
+}
+
+
+static volatile open_titan_i2c_t *get_i2c_block(uint32_t id) {
+    switch (id) {
+        case 0:
+            return MMIO_CAPABILITY(open_titan_i2c_t, i2c0);
+        case 1:
+            return MMIO_CAPABILITY(open_titan_i2c_t, i2c1);
+        default:
+            mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Unknown i2c device \"%d\""), id);
+    }
+}
+
+mp_obj_t machine_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    enum { ARG_id, ARG_freq, ARG_scl, ARG_sda, ARG_timeout };
+    static const mp_arg_t allowed_args[] = {
+        {MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_INT},
+        {MP_QSTR_freq, MP_ARG_INT, {.u_int = I2C_DEFAULT_FREQ}},
+        {MP_QSTR_scl, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL}},
+        {MP_QSTR_sda, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL}},
+        {MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1}},
+    };
+
+    // Parse args.
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args),
+        allowed_args, args);
+
+    if (args[ARG_timeout].u_obj != -1) {
+        mp_raise_NotImplementedError(
+            MP_ERROR_TEXT("explicit choice of timeout is not implemented"));
+    }
+
+
+    if ((args[ARG_scl].u_obj != MP_OBJ_NULL) ||
+        (args[ARG_sda].u_obj != MP_OBJ_NULL)) {
+        mp_raise_NotImplementedError(
+            MP_ERROR_TEXT("explicit choice of sck/sda is not implemented"));
+    }
+
+    volatile open_titan_i2c_t *block = get_i2c_block(args[ARG_id].u_int);
+    uint32_t freq_kHz = args[ARG_freq].u_int / 1000;
+
+    i2c_setup(block, freq_kHz);
+
+    machine_i2c_obj_t *self = m_new_obj(machine_i2c_obj_t);
+    self->i2c_block = block;
+    self->base.type = &machine_i2c_type;
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+
+static int machine_i2c_transfer_single(mp_obj_base_t *self_in, uint16_t addr, size_t len, uint8_t *buf, unsigned int flags) {
+    machine_i2c_obj_t *self = (machine_i2c_obj_t *)MP_OBJ_TO_PTR(self_in);
+    bool stop = 0 != (flags & MP_MACHINE_I2C_FLAG_STOP);
+
+    bool success;
+
+    if (len == 0) {
+        success = i2c_send_address(self->i2c_block, addr);
+
+    } else if (flags & MP_MACHINE_I2C_FLAG_READ) {
+        success = i2c_blocking_read(self->i2c_block, addr, buf, len);
+
+    } else {
+        success = i2c_blocking_write(self->i2c_block, addr, buf, len, !stop);
+    }
+    return success ? len : -5;
+}
+
+static const mp_machine_i2c_p_t machine_i2c_p = {
+    .transfer = mp_machine_i2c_transfer_adaptor,
+    .transfer_single = machine_i2c_transfer_single,
+};
+
+MP_DEFINE_CONST_OBJ_TYPE(
+    machine_i2c_type,
+    MP_QSTR_I2C,
+    MP_TYPE_FLAG_NONE,
+    make_new, machine_i2c_make_new,
+    print, machine_i2c_print,
+    protocol, &machine_i2c_p,
+    locals_dict, &mp_machine_i2c_locals_dict
+    );