Framework for chips with slight differences #32
Description
I have some W25N01GV chips that I've been playing with. These are still 25-series, but they're NAND flash and have a slightly different instruction set.
This crate provides an excellent starting point for those chips, but doesn't work without tweaking. For example, initialization returns an error because of an invalid status register (the command buffer needs to be changed to [0x05, 0xC0, 0x00] instead of [0x05, 0x00], and the result is read from the 3rd bit), and the JEDEC id response is offset by one byte as well.
I'm happy to make a PR with whatever I get working, although it looks like there's no support for different protocols at the moment. #4 and #8 touch on this, and #10 and #25 propose two different approaches, but neither is merged, so it's unclear how to best proceed.