diff --git a/ports/m32c/README b/ports/m32c/README new file mode 100644 index 00000000..e3b6961e --- /dev/null +++ b/ports/m32c/README @@ -0,0 +1,159 @@ +--------------------------------------------------------------------------- + +Library: Atomthreads M32C/80 Port +Author: Juan Angel Hernandez Hernandez +License: BSD Revised + +--------------------------------------------------------------------------- + +M32C/80 PORT + +This folder contains a port of the Atomthreads real time kernel for the +M32C/80 processor architecture. + +All of the cross-platform kernel code is contained in the top-level +'kernel' folder, while ports to specific CPU architectures are contained in +the 'ports' folder tree. + +Atomthreads includes a suite of automated tests which prove the key OS +functionality, and can be used with any architecture ports. + + +--------------------------------------------------------------------------- + +FILES IN THE m32c port folder + + * atomport.c: Contains the main C code that forms the portion of the core + M32C/80 architecture port that can be implemented in C. + * atomport-asm.A30: Contains the main assembler code that forms the portion + of the core M32C/80 architecture port that must be implemented in assembler. + * tests-main.c: Contains a sample Atomthreads application starting at + main() that initialises the operating system and runs the automated test + suite applications. You will normally make your own main() function + suitable for your application, possibly using this as a basis. + * atomport.h: Port-specific header required by the kernel for each port. + * atomport-private.h: Port-specific header required by atomport.c + + +--------------------------------------------------------------------------- + +PREREQUISITES + +The port works with the Renesas HEW tools. +Tools: +*High-performance Embedded Workshop (HEW) V 4.09.00.007 +*M3T-NC308WA compiler. + +Since Renesas HEW only works with absolute paths, if you cloned this repository +to c: the code will compile and load without doing any extra steps. +If you cloned to another different path do the following: +-Click on Build->Renesas M32C standard toolchain, a window shall show up. +-On the C tab, select: + Category: Source, + Show entries For: Include file directories +Click add, and add the following paths: + -\your clone path\atomthreads\kernel + -\your clone path\atomthreads\tests + -\your clone path\atomthreads\ports\m32c + +--------------------------------------------------------------------------- + +BUILDING AND PROGRAMMING TO THE TARGET DEVICE + +In this port the target is a simulator. But you can also change the target and +download the code to a development kit. +Open the file: +\atomthreads\ports\m32c\hew_tests\hew_tst_sem1\hew_tst_sem1.hws + +Click Ok on the Init window +Click Build->Build All +And the code will automatically be loaded into the simulator target. + +--------------------------------------------------------------------------- + +HEW SIMULATOR SPECIFICS + +The virtual timer interrupt and the virtual UART, are already setup when you +load the project. For the virtual led, you need to open the LED.pnl file so +the led can show up. + +*Virtual Timer Interrupt: + The virtual interrupt is set in View->CPU->I/O Timing Setting. + Defaults for this port: + -Interval: 10 msec + -Vector 23 (timer B2) + -Priority: 1 (Possible values are 0-7) + +*Virtual UART: + The virtual UART is set in View->CPU->OutputPort Then click on the "Set" + icon. + Defaults for this port: + -Printf - UART1 + -Output Format: + *Window TEXT + *File TEXT + +*Virtual LED: + The virtual LED is set in View->Graphic->GUI I/O + Click on the folder icon that says "Load" when you do a mouseover. Open the + file called led.pnl + The path of the led.pnl file is: + \atomthreads\ports\m32c\hew_tests\led.pnl + +--------------------------------------------------------------------------- + +RUNNING THE AUTOMATED TESTS WITH THE HEW SIMULATOR + +Atomthreads contains a set of generic kernel tests which can be run on any +port to prove that all core functionality is working on your target. In +order to accommodate a full testing regime, a large number of test threads +are spawned which on ATmega platforms requires at least 1KB and possibly +more RAM. Bear this in mind if you wish to run all of the automated tests +on your target platform. + +The full set of tests can be found in the top-level 'tests' folder. Each of +these tests has to be built as an independent HEW project. In this port a +HEW project using sem1.c is provided. To run the rest of the tests remove +sem1.c and then add any other test file to the project. + + +Example 1. Test results with a breakpoint: +-Open: \atomthreads\ports\m32c\hew_tests\hew_tst_sem1\hew_tst_sem1.hws +-Click Ok on the Init window +-Click Build->Build All +-The code will automatically be loaded into the simulator target. +-Put a breakpoint at the end of the test in tests-main.c +-Click on Debug->Reset Go. When the test finishes you shall see the virtual + UART, test result output. + +Example 2. Test results with a virtual led flashing: +-Open: \atomthreads\ports\m32c\hew_tests\hew_tst_sem1\hew_tst_sem1.hws +-Click Ok on the Init window +-Click Build->Build All +-The code will automatically be loaded into the simulator target. +-On the View->Graphic->GUI I/O window click on the folder icon called "Load" + and open the led.pnl file. The path of the led.pnl file is: + \atomthreads\ports\m32c\hew_tests\led.pnl +-Click on Debug->Reset Go. When the test finishes you shall see the led flash. +-When the led is flashing click "Stop" in the simulator and the virtual UART + output will print the result of the test. + + +--------------------------------------------------------------------------- + +WRITING APPLICATIONS + +The easiest way to start a new application which utilises the Atomthreads +scheduler is to base your main application startup on tests-main.c. This +initialises the OS, sets up a UART and calls out to the test module entry +functions. You can generally simply replace the call to the test modules by +a call to your own application startup code. + + +--------------------------------------------------------------------------- + +PORTING TO NEW PLATFORMS + +Follow the very useful porting guide that you can find in atomthreads.com/ + +--------------------------------------------------------------------------- diff --git a/ports/m32c/atomport-asm.A30 b/ports/m32c/atomport-asm.A30 new file mode 100644 index 00000000..06e69957 --- /dev/null +++ b/ports/m32c/atomport-asm.A30 @@ -0,0 +1,73 @@ +;/* +; * Copyright (c) 2014, Juan Angel Hernandez Hdez. for Atomthreads Project. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted provided that the following conditions +; * are met: +; * +; * 1. Redistributions of source code must retain the above copyright +; * notice, this list of conditions and the following disclaimer. +; * 2. Redistributions in binary form must reproduce the above copyright +; * notice, this list of conditions and the following disclaimer in the +; * documentation and/or other materials provided with the distribution. +; * 3. No personal names or organizations' names associated with the +; * Atomthreads project may be used to endorse or promote products +; * derived from this software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS +; * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +; * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +; * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE +; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; * POSSIBILITY OF SUCH DAMAGE. +; */ + + +;/** +; * \b _timer_b2 +; * +; * Timer B2 interrupt service routine. +; * On interrupt, the U flag is cleared meaning that the interrupt stack (IStack) +; * is selected. FLG and PC are saved on IStack, this routine then cuts and pastes +; * FLG and PC from IStack to UStack (User stack) so that all data relevant to a +; * thread is kept on the same stack area. This also makes the IStack available to +; * use for interrupt nesting. +; * +; * @return None +; */ + + .GLB _atomIntEnter + .GLB _atomTimerTick + .GLB $atomIntExit + .GLB __timer_b2 + .FB 0 + + .SECTION program,CODE,ALIGN + .align + .GLB __timer_b2 + .rvector 23, __timer_b2 +__timer_b2: + PUSHC FB ;Save FB temporary on I stack. + FSET U ;Select user stack + PUSHC ISP ;Save ISP in U stack + POPC FB ;POP ISP to FB + PUSH.W 8H[FB] ;Copy FLG from Istack to Ustack + PUSH.L 4H[FB] ;Copy TskX ReturnAddress from Istack to Ustack + FCLR U ;Select Istack + POPC FB ;restore original value of FB + ADD.L #6,SP ;Clean Istack, so it is free for interrupts. + FSET U ;Carry on, on Ustack + + JSR.A _atomIntEnter + JSR.A _atomTimerTick + + MOV.B:Q #1H,R0L ;Pass the TRUE parameter + JSR.A $atomIntExit + REIT +.END diff --git a/ports/m32c/atomport-private.h b/ports/m32c/atomport-private.h new file mode 100644 index 00000000..5ab9633b --- /dev/null +++ b/ports/m32c/atomport-private.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2014, Juan Angel Hernandez Hdez. for Atomthreads Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_PRIVATE_H +#define __ATOM_PORT_PRIVATE_H + +/* Enumeration for interrupt level */ +typedef enum +{ + INTERRUPT_LVL_0 = 0x00, + INTERRUPT_LVL_1 = 0x01, + INTERRUPT_LVL_2 = 0x02, + INTERRUPT_LVL_3 = 0x03, + INTERRUPT_LVL_4 = 0x04, + INTERRUPT_LVL_5 = 0x05, + INTERRUPT_LVL_6 = 0x06, + INTERRUPT_LVL_7 = 0x07 +} teINTERRUPT_PRIORITY_LEVEL; + +/* CPU Frequency */ +#define M32C_OSC_FREQUENCY 20000000L +#define PRESCALE_VALUE 8 + +/* 1MS tick defines */ +#define COUNT_10MS (M32C_OSC_FREQUENCY/PRESCALE_VALUE)/100 + +/* Using simulator */ +#define HEW_SIMULATOR + +/* Function prototypes */ +void init_timerb2(void); +void init_pin_P0_0(void); +void toggle_pin_P0_0(void); + +/* Timer B2 registers */ +#pragma ADDRESS TB2MR 035Dh +#pragma ADDRESS TB2 0354h +#pragma ADDRESS TB2IC 0096h +uint8_t TB2MR; +uint16_t TB2; +uint8_t TB2IC; + +/* TIMER B2 (software int 23) */ +#pragma interrupt _timer_b2(vect=23) + +/* LED pin */ +#pragma ADDRESS PD0 03E2h //Input or output 0:Input 1:Output +#pragma ADDRESS P0 03E0h //R/W +uint8_t PD0; +uint8_t P0; + +#endif /* __ATOM_PORT_PRIVATE_H */ diff --git a/ports/m32c/atomport-tests.h b/ports/m32c/atomport-tests.h new file mode 100644 index 00000000..c7557ac6 --- /dev/null +++ b/ports/m32c/atomport-tests.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_TESTS_H +#define __ATOM_PORT_TESTS_H + +/* Include Atomthreads kernel API */ +#include "atom.h" + +/* Prerequisite include for ATOMLOG() macro (via printf) */ +#include + +/* Logger macro for viewing test results */ +#define ATOMLOG printf + +/* + * String location macro: for platforms which need to place strings in + * alternative locations, e.g. on avr-gcc strings can be placed in + * program space, saving SRAM. On most platforms this can expand to + * empty. + */ +#define _STR(x) x + +/* Default thread stack size (in bytes) */ +#define TEST_THREAD_STACK_SIZE 264 + +/* Uncomment to enable logging of stack usage to UART */ +/* #define TESTS_LOG_STACK_USAGE */ + + +#endif /* __ATOM_PORT_TESTS_H */ + diff --git a/ports/m32c/atomport.c b/ports/m32c/atomport.c new file mode 100644 index 00000000..a0c842a9 --- /dev/null +++ b/ports/m32c/atomport.c @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2014, Juan Angel Hernandez Hdez. for Atomthreads Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "atom.h" +#include "atomport-private.h" + +ATOM_TCB *asm_shell_new_tcb_ptr; +ATOM_TCB *asm_shell_old_tcb; +ATOM_TCB *asm_shell_new_tcb; + +/** Forward declarations */ +static void thread_shell (void); + + +/** + * \b thread_shell + * + * Shell routine which is used to call all thread entry points. + * + * This routine is called whenever a new thread is starting, and + * provides a simple wrapper around the thread entry point that + * allows us to carry out any actions we want to do on thread's + * first starting up, or returning after completion. + * + * We mainly just want to make sure interrupts are enabled when a + * thread is run for the first time. This can be done via stack + * restores when threads are first run, but it's handy to have this + * wrapper anyway to run some common code if threads run to + * completion. + * + * A thread shell is also handy for providing port users with a place + * to do any other initialisation that must be done for each thread + * (e.g. opening stdio files etc). + * + * @return None + */ +static void thread_shell (void) +{ + ATOM_TCB *curr_tcb; + + /* Get the TCB of the thread being started */ + curr_tcb = atomCurrentContext(); + + /** + * Enable interrupts - these will not be enabled when a thread + * is first restored. + */ + asm("FSET I"); + + /* Call the thread entry point */ + if (curr_tcb && curr_tcb->entry_point) + { + curr_tcb->entry_point(curr_tcb->entry_param); + } + + /* Thread has run to completion: remove it from the ready list */ + curr_tcb->suspended = TRUE; + atomSched (FALSE); +} + + +/** + * \b archThreadContextInit + * + * Architecture-specific thread context initialisation routine. + * + * This function must set up a thread's context ready for restoring + * and running the thread via archFirstThreadRestore() or + * archContextSwitch(). + * + * The layout required to fill the correct register values is + * described in archContextSwitch(). + * + * @param[in] tcb_ptr Pointer to the TCB of the thread being created + * @param[in] stack_top Pointer to the top of the new thread's stack + * @param[in] entry_point Pointer to the thread entry point function + * @param[in] entry_param Parameter to be passed to the thread entry point + * + * @return None + */ +void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(uint32_t), uint32_t entry_param) +{ + uint16_t *stack_ptr; + + /** Start at stack top */ + stack_ptr = (uint16_t*)stack_top; + + /** + * After restoring all of the context registers, the thread restore + * routines will perform a RTS or REIT which expect to find the + * address of the calling routine on the stack. In this case (the + * first time a thread is run) we "return" to the entry point for + * the thread. That is, we store the thread entry point in the + * place that RTS or REIT will look for the return address: the + * stack. + * + * Note that we are using the thread_shell() routine to start all + * threads, so we actually store the address of thread_shell() + * here. Other ports may store the real thread entry point here + * and call it directly from the thread restore routines. + * + * Because we are filling the stack from top to bottom, this goes + * on the stack first (at the top). + */ + + /* | Ret ADD High PC (H) | */ + *stack_ptr-- = ((uint32_t)thread_shell >> 16L); + /* | Ret ADD Low PC (L) | */ + *stack_ptr-- = (uint16_t)((uint32_t)thread_shell & 0x0000FFFFL); + /* | FB | */ + *stack_ptr-- = (uint16_t)0xFBFB; + *stack_ptr-- = (uint16_t)0xFBFB; + /* | FLG | */ + *stack_ptr-- = (uint16_t)0x00C0; //User stack pointer activated and interrupts enabled + /* | SB | */ + *stack_ptr-- = (uint16_t)0x3B3B; + *stack_ptr-- = (uint16_t)0x3B3B; + /* | A1 | */ + *stack_ptr-- = (uint16_t)0xA1A1; + *stack_ptr-- = (uint16_t)0xA1A1; + /* | A0 | */ + *stack_ptr-- = (uint16_t)0xA0A0; + *stack_ptr-- = (uint16_t)0xA0A0; + /* | R3 | */ + *stack_ptr-- = (uint16_t)0x3333; + /* | R2 | */ + *stack_ptr-- = (uint16_t)0x2222; + /* | R1 | */ + *stack_ptr-- = (uint16_t)0x1111; + /* | R0 | */ + *stack_ptr = (uint16_t)0x0000; + + + /** + * All thread context has now been initialised. Save the current + * stack pointer to the thread's TCB so it knows where to start + * looking when the thread is started. + */ + tcb_ptr->sp_save_ptr = stack_ptr; + +} + +/** + * \b archFirstThreadRestore + * + * Architecture-specific function to restore and start the first thread. + * This is called by atomOSStart() when the OS is starting. + * + * This function will be largely similar to the latter half of + * archContextSwitch(). Its job is to restore the context for the + * first thread, and finally enable interrupts (although we actually + * enable interrupts in thread_shell() for new threads in this port + * rather than doing it explicitly here). + * + * It expects to see the context saved in the same way as if the + * thread has been previously scheduled out, and had its context + * saved. That is, archThreadContextInit() will have been called + * first (via atomThreadCreate()) to create a "fake" context save + * area, containing the relevant register-save values for a thread + * restore. + * + * Note that you can create more than one thread before starting + * the OS - only one thread is restored using this function, so + * all other threads are actually restored by archContextSwitch(). + * This is another reminder that the initial context set up by + * archThreadContextInit() must look the same whether restored by + * archFirstThreadRestore() or archContextSwitch(). + * + * @param[in] new_tcb_ptr Pointer to the thread being scheduled in + * + * @return None + * + * void archFirstThreadRestore (ATOM_TCB *new_tcb_ptr) + */ +void archFirstThreadRestore(ATOM_TCB *new_tcb_ptr) +{ + asm_shell_new_tcb_ptr = new_tcb_ptr; + + asm("MOV.L _asm_shell_new_tcb_ptr,A0"); + asm("LDC [A0],SP"); + asm("POPM R0,R1,R2,R3,A0,A1,SB"); + asm("POPC FLG"); + asm("POPC FB"); + asm("RTS"); +} + +/* + * \b archContextSwitch + * + * Architecture-specific context switch routine. + * + * Note that interrupts are always locked out when this routine is + * called. For cooperative switches, the scheduler will have entered + * a critical region. For preemptions (called from an ISR), the + * ISR will have disabled interrupts on entry. + * + * @param[in] old_tcb_ptr Pointer to the thread being scheduled out + * @param[in] new_tcb_ptr Pointer to the thread being scheduled in + * + * @return None + * + * void archContextSwitch (ATOM_TCB *old_tcb_ptr, ATOM_TCB *new_tcb_ptr) + */ +void archContextSwitch(ATOM_TCB *old_tcb, ATOM_TCB *new_tcb) +{ + asm_shell_old_tcb = old_tcb; + asm_shell_new_tcb = new_tcb; + + /* Save context */ + asm("PUSHC FLG"); + asm("PUSHM R0,R1,R2,R3,A0,A1,SB"); + asm("MOV.L _asm_shell_old_tcb,A0"); + asm("STC SP,[A0]"); + + /* Restore Context */ + asm("MOV.L _asm_shell_new_tcb,A0"); + asm("LDC [A0],SP"); + asm("POPM R0,R1,R2,R3,A0,A1,SB"); + asm("POPC FLG"); + asm("POPC FB"); + asm("RTS"); +} + +/** + * \b init_timerb2 + * + * Initiate 1MS timer. Not used in simulator mode. + * + * @return None + */ +void init_timerb2(void) +{ +#ifndef HEW_SIMULATOR + TB2MR = 0x40; // M32C_OSC_FREQUENCY/8 + TB2 = COUNT_10MS; + TB2IC = INTERRUPT_LVL_1; +#endif +} + +void init_pin_P0_0(void) +{ + PD0 = 0xFF; //All outputs. + P0 = 0x00; //Outputs low. +} + +void toggle_pin_P0_0(void) +{ + P0 ^= 1 << 0; +} diff --git a/ports/m32c/atomport.h b/ports/m32c/atomport.h new file mode 100644 index 00000000..2126fefe --- /dev/null +++ b/ports/m32c/atomport.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2014, Juan Angel Hernandez Hdez. for Atomthreads Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ATOM_PORT_H +#define __ATOM_PORT_H + +/* Portable uint8_t and friends available from stdint.h on this platform */ +#include "stdint.h" + +/* Definition of NULL is available from stddef.h on this platform */ +#include + +/* Required number of system ticks per second (normally 100 for 10ms tick) */ +#define SYSTEM_TICKS_PER_SEC 100 + +/* Size of each stack entry / stack alignment size (8 bits on AVR) */ +#define STACK_ALIGN_SIZE sizeof(uint16_t) + +/** + * Architecture-specific types. + * Most of these are available from stdint.h on this platform, which is + * included above. + */ +#define POINTER void * + +/* Critical region protection */ +#define CRITICAL_STORE uint8_t dummy_to_avoid_warning=0 +#define CRITICAL_START() asm("FCLR I"); //if(dummy_to_avoid_warning){} +#define CRITICAL_END() asm("FSET I") + +/* Uncomment to enable stack-checking */ +/* #define ATOM_STACK_CHECKING */ + + +#endif /* __ATOM_PORT_H */ diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1.Hbp b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1.Hbp new file mode 100644 index 00000000..ff4ea30f --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1.Hbp @@ -0,0 +1,2 @@ +[Setting] +ToolChain=0 diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1.hws b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1.hws new file mode 100644 index 00000000..c65c25ef --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1.hws @@ -0,0 +1,40 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"11.0" +[WORKSPACE_DETAILS] +"hew_tst_sem1" "C:\atomthreads\ports\m32c\hew_tests\hew_tst_sem1" "C:\atomthreads\ports\m32c\hew_tests\hew_tst_sem1\hew_tst_sem1.hws" "M16C/80,M32C" "Renesas M32C Standard" +[SHARED_WORKSPACE_CONTROL_STATUS] +"" "" "" +"" "" "" +[PROJECTS] +"hew_tst_sem1" "C:\atomthreads\ports\m32c\hew_tests\hew_tst_sem1\hew_tst_sem1" "C:\atomthreads\ports\m32c\hew_tests\hew_tst_sem1\hew_tst_sem1\hew_tst_sem1.hwp" 0 +[INFORMATION] +"No workspace information available" +[SCRAP] +[PROJECT_DEPENDENCY] +[WORKSPACE_PROPERTIES] +[HELP_FILES] +[GENERAL_DATA_PROJECT] +[USERMENUTOOLS] +[CUSTOMPLACEHOLDERS] +[MAKEFILE_BUILD_INFO] +"$(WORKSPDIR)\make\$(PROJECTNAME)_$(CONFIGNAME).mak" "" "$(WORKSPDIR)\make" 0 0 0 +[VD_CONFIGURATION_OPTIONS] +"ACTIVE_DESKTOP" "0" +[VD_CONFIGURATIONS] +"0" "Default1" "1" +"1" "Default2" "1" +"2" "Default3" "1" +"3" "Default4" "1" +[OPTIONS_DEBUG_TAB] +0 0 0 0 0 +[VCS] +"" "" "" 0 +[VCS_PROJECT] +[MAKEFILE_ENV_STRINGS] +[MAKEFILE_ENV_FLAGS] +1 0 0 +[MAKEFILE_CLEAN_INFO] +"" +[END] diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1.tws b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1.tws new file mode 100644 index 00000000..5f750ff6 --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1.tws @@ -0,0 +1,17 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.2" +[CURRENT_PROJECT] +"hew_tst_sem1" +[GENERAL_DATA] +[BREAKPOINTS] +[OPEN_WORKSPACE_FILES] +"C:\atomthreads\kernel\atomkernel.c" +"C:\atomthreads\ports\m32c\hew_tests\hew_tst_sem1\hew_tst_sem1\resetprg.c" +[WORKSPACE_FILE_STATES] +"C:\atomthreads\kernel\atomkernel.c" 0 0 1114 570 0 1 +"C:\atomthreads\ports\m32c\hew_tests\hew_tst_sem1\hew_tst_sem1\resetprg.c" -8 -30 1114 570 1 0 +[LOADED_PROJECTS] +"hew_tst_sem1" +[END] diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/DefaultSession.hsf b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/DefaultSession.hsf new file mode 100644 index 00000000..8b2bf658 --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/DefaultSession.hsf @@ -0,0 +1,99 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" "" +"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" +[LANGUAGE] +"English" +[CONFIG_INFO_VD1] +1 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +"Help" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 412 534 373 350 200 18 0 "36756|36757|36758|36759|<>|36746|36747|<>|39531|<>|39500|39534|<>|36687" "0.0" +"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 218 534 373 350 200 18 0 "" "0.0" +"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 2 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 2 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +[TARGET_NAME] +"" "" 1182035557 +[STATUSBAR_STATEINFO_VD1] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD2] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD3] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD4] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD1] +[STATUSBAR_DEBUGGER_PANESTATE_VD2] +[STATUSBAR_DEBUGGER_PANESTATE_VD3] +[STATUSBAR_DEBUGGER_PANESTATE_VD4] +[DEBUGGER_OPTIONS] +"" +[DOWNLOAD_MODULES] +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION] +"FALSE" +[LIMIT_DISASSEMBLY_MEMORY_ACCESS] +"FALSE" +[DISABLE_MEMORY_ACCESS_DURING_EXECUTION] +"FALSE" +[DEBUGGER_OPTIONS_PROPERTIES] +"1" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"" +[FLASH_DETAILS] +"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/SIM308.INI b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/SIM308.INI new file mode 100644 index 00000000..0ba365ca --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/SIM308.INI @@ -0,0 +1,2 @@ +[INIT] +ATEXIT=1 diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/SessionM32C_Simulator.hsf b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/SessionM32C_Simulator.hsf new file mode 100644 index 00000000..d1f37a3d --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/SessionM32C_Simulator.hsf @@ -0,0 +1,261 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"FIRST_CONNECTION_TAG" "NO" +"RESET_CPU_AFTER_DOWNLOAD_TAG" "VARIANT_TRUE_STORE_TAG" +"{06B7701B-5400-4F73-A98D-DFB20141B565}PDTaskTraceCtrlAnalyzeViews" "0" +"{06B7701B-5400-4F73-A98D-DFB20141B565}PDTaskTraceCtrlTraceViews" "0" +"{18AEA759-3561-4CC5-9908-97D74B956935}PDCoverageCtrlViews" "0" +"{1D0B3B27-B01D-4E8C-8848-E2E7F5EEFD73}PDOutputPortCtrlViews" "1" +"{1D0B3B27-B01D-4E8C-8848-E2E7F5EEFD73}PDOutputPortWnd0OportColumn" "0,0,0,0,16,16,16,16,16,16,16,16,1,1,1,0" +"{1D0B3B27-B01D-4E8C-8848-E2E7F5EEFD73}PDOutputPortWnd0OportData" "1, 1, 1" +"{1D0B3B27-B01D-4E8C-8848-E2E7F5EEFD73}PDOutputPortWnd0OportTempDir" "C:\Users\hernajua\AppData\Local\Temp" +"{1D0B3B27-B01D-4E8C-8848-E2E7F5EEFD73}PDOutputPortWnd0OportType" "1" +"{1D0B3B27-B01D-4E8C-8848-E2E7F5EEFD73}PDOutputPortWndInstanceKey0" "{WK_00000001_PDOUTPUTPORT}hew_tst_sem1SessionM32C_Simulator" +"{210D75A5-E8B6-462A-A69C-EFB481B02BD1}PDScriptCtrlViews" "0" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "0" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "1" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlWindowProperties" "17" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineWndInstanceKey0" "{WK_00000001_CmdLine}" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_DEST_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_MOVE_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_MOVE_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SEARCH_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SEARCH_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SET_DEST_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_TEST_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_TEST_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorCtrlViews" "1" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndRRAM Monitor AreaCount" "1" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndRRAM Monitor AreaSize0" "1" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndRRAM Monitor AreaStart0" "00000400" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0DataLength" "1" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0DispAddressTopPane" "1024" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0DispCode" "42208" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0DispColumnCount" "16" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0IsDispCode" "1" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0IsDispFloat" "0" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0IsDispLabel" "0" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0IsDispRegister" "0" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0LabelWidth" "96" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0Radix" "16" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0RegisterWidth" "96" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0Sampling" "100" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0ScrollEndAddress" "2047" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewA0ScrollStartAddress" "1024" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewAInstanceKey0" "{WK_00000001_RAMMONITOR}hew_tst_sem1SessionM32C_Simulator" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0DataLength" "1" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0DispAddressTopPane" "1024" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0DispCode" "42208" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0DispColumnCount" "16" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0IsDispCode" "1" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0IsDispFloat" "0" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0IsDispLabel" "0" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0IsDispRegister" "0" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0LabelWidth" "96" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0Radix" "16" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0RegisterWidth" "96" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0Sampling" "100" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0ScrollEndAddress" "2047" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewB0ScrollStartAddress" "1024" +"{348532CE-10A4-4D46-B946-95A8279582D2}RamMonitorWndViewBInstanceKey0" "{WK_00000001_RAMMONITOR}hew_tst_sem1SessionM32C_SimulatorViewB" +"{55384715-F881-421C-A548-D7D1ABE158E1}PDMRCtrlViews" "0" +"{5A6890B2-17C2-4AB3-B941-0F899F6A3D76}PDSwbreakwinCtrlViews" "0" +"{5F04F1E1-BD88-46BA-A9C2-A5DDBFED8D0C}PDMRTraceCtrlAnalyzeViews" "0" +"{5F04F1E1-BD88-46BA-A9C2-A5DDBFED8D0C}PDMRTraceCtrlTraceViews" "0" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" "" +"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" +"{811C3B34-DDC2-42E9-8FA8-7AEAA822FF18}PDDataTraceCtrlViews" "0" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_ADDRESS_NAME" "" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_ADDRESS" ",,,," +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_SAMPLING_RATE" "1000" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ColumnWidth" "51,61,36" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_COUNT" "36" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideFLAGs" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideRadix" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0LastFileName" "" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16," +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndInstanceKey0" "{WK_00000001_REGISTERS}hew_tst_sem1SessionM32C_Simulator" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ColumnWidth" "51,61,36" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_COUNT" "36" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideFLAGs" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideRadix" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0LastFileName" "" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16," +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewBInstanceKey0" "{WK_00000001_REGISTERS}hew_tst_sem1SessionM32C_SimulatorViewB" +"{98DFB68C-498C-4346-A6B8-C7260C534267}PDTraceCtrlViews" "0" +"{99F424FE-E727-45AE-AE1F-11E29DEF272C}ECX_GuiIO_SAMPLING_RATE" "1000" +"{99F424FE-E727-45AE-AE1F-11E29DEF272C}PDGuiIOCtrlPDGuiIOLastSaveDirectory" "C:\atomthreads\ports\m32c\hew_tests\led.pnl" +"{99F424FE-E727-45AE-AE1F-11E29DEF272C}PDGuiIOCtrlViews" "1" +"{99F424FE-E727-45AE-AE1F-11E29DEF272C}PDGuiIOWndInstanceKey0" "{WK_00000001_PDGUIIO}hew_tst_sem1SessionM32C_Simulator" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_ADDRESS_NAME" "" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,," +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,," +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_PALETTE_NAME" "" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_REDRAW_CONTINUOUSLY" "0,2" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_SAMPLEING_RATE" "1000" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" +"{B13462A1-157A-4D86-9BA3-66117A68F1A2}FirstLoadOnV103" "0" +"{BFEEE25F-801F-44A7-A6F1-D8C60837CD32}PDHWBreakCtrlViews" "0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataInputAddrDataNum" "0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataInputColor" "8421504,65535,16777215,0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataInputCycleDataNum" "0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataInputIntrDataNum" "0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataInputMode" "0, 0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataInputView" "0,20,1,20,1,20,0,0,0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataIntrAddrDataNum" "0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataIntrColor" "8421504,65535,16777215,0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataIntrCycleDataNum" "0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataIntrMode" "0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataIntrView" "0,20,1,20,0,0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataIoScriptFileNum" "0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataOutputColor" "8421504,65535,16777215,0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataOutputCycleDataNum" "0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataOutputMode" "0, 0" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataSimpleTimer0" "E 00000017 1 10 m" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataSimpleTimerNum" "1" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}EcxPDIOTimingDataTimerTempDir" "C:\Users\hernajua\AppData\Local\Temp" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}PDIOTimingCtrlViews" "1" +"{C27248CC-BDC9-414E-A340-12AFD36A7AF8}PDIOTimingWndInstanceKey0" "{WK_00000001_PDIOTIMING}hew_tst_sem1SessionM32C_Simulator" +"{C62E6398-F79C-4FAB-801E-8B1A464777C3}CWatchCtrlViews" "0" +"{C62E6398-F79C-4FAB-801E-8B1A464777C3}CWatchWnd_InitialRadix" "Default" +"{C62E6398-F79C-4FAB-801E-8B1A464777C3}CWatchWnd_TAB" "Global,File Local,Local," +"{D465B72E-4328-4D5D-B49F-992C2C8B1EE9}ASMWatchCtrlViews" "0" +"{D465B72E-4328-4D5D-B49F-992C2C8B1EE9}ASMWatchWnd_AddressArea" "1" +"{D465B72E-4328-4D5D-B49F-992C2C8B1EE9}ASMWatchWnd_PointNum" "0" +"{D465B72E-4328-4D5D-B49F-992C2C8B1EE9}ASMWatchWnd_RramEnable" "1" +"{D465B72E-4328-4D5D-B49F-992C2C8B1EE9}ASMWatchWnd_Sampling" "100" +"{D465B72E-4328-4D5D-B49F-992C2C8B1EE9}ASMWatchWnd_SizeArea" "1" +"{D465B72E-4328-4D5D-B49F-992C2C8B1EE9}ECX_ASMWATCH_DLG_BIT_ADDR" "" +"{D465B72E-4328-4D5D-B49F-992C2C8B1EE9}ECX_ASMWATCH_DLG_SYMBOL_ADDR" "" +"{E6D16242-FB42-44CE-B289-ED9FE8563816}MR308DXCtrlViews" "0" +"{EEDC9301-6FBE-11D5-8613-00A024591A38}StackTraceCtrlViews" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlIOFile" "" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlSaveFileDir" "$(CONFIGDIR)" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlSaveFileName" "" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlViews" "0" +[LANGUAGE] +"English" +[CONFIG_INFO_VD1] +1 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +"Help" "TOOLBAR 0" 59419 2 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_00000001_CmdLine}" "WINDOW" 59422 0 2 "0.01" 412 0 0 350 200 17 0 "32771|32772|32778|<>|32773|32774|<>|32820|<>|32801|32824" "0.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 1 "0.21" 412 534 373 350 200 18 0 "36756|36757|36758|36759|<>|36746|36747|<>|39531|<>|39500|39534|<>|36687" "0.0" +"{WK_00000001_PDGUIIO}hew_tst_sem1SessionM32C_Simulator" "WINDOW" 59422 0 0 "0.18" 412 0 0 350 200 18 0 "45607|45602|<>|45605|45609|45606|45610|<>|<>|45601|45600|<>" "0.0" +"{WK_00000001_PDIOTIMING}hew_tst_sem1SessionM32C_Simulator" "WINDOW" 59422 0 5 "0.24" 412 0 0 350 200 18 0 "32771|32772|32773|<>|32774|<>|32775|32776|32778|<>|32777|32801" "0.0" +"{WK_00000001_PDOUTPUTPORT}hew_tst_sem1SessionM32C_Simulator" "WINDOW" 59422 0 3 "0.15" 412 0 0 350 200 18 0 "45717|45722|45718|45719|45720|45721" "0.0" +"{WK_00000001_RAMMONITOR}hew_tst_sem1SessionM32C_Simulator" "WINDOW" 59422 0 4 "0.23" 412 0 0 350 200 18 0 "45930|45931|<>|42302|42303|42300|<>|42202|42203|42204|42233|<>|42206|42205|42230|42229|42207|<>|42208|42209|42210|42227|42228|42231|42232|<>" "0.0" +"{WK_00000001_REGISTERS}hew_tst_sem1SessionM32C_Simulator" "WINDOW" 59421 0 0 "1.00" 208 0 0 350 200 18 0 "" "0.0" +"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 255 534 373 350 200 18 0 "" "0.0" +"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 2 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 2 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000011_CPU}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000013_SYMBOL}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000014_CODE}" "TOOLBAR 0" 59419 2 8 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000016_GRAPHIC}" "TOOLBAR 0" 59419 2 7 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000021_TRACE}" "TOOLBAR 0" 59419 2 10 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000022_BREAK}" "TOOLBAR 0" 59419 2 9 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000023_RTOS}" "TOOLBAR 0" 59419 2 11 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +"C:\atomthreads\kernel\atomkernel.c" +"C:\atomthreads\ports\m32c\hew_tests\hew_tst_sem1\hew_tst_sem1\resetprg.c" +[TARGET_NAME] +"M32C Simulator" "" 0 +[STATUSBAR_STATEINFO_VD1] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD2] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD3] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD4] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD1] +[STATUSBAR_DEBUGGER_PANESTATE_VD2] +[STATUSBAR_DEBUGGER_PANESTATE_VD3] +[STATUSBAR_DEBUGGER_PANESTATE_VD4] +[DEBUGGER_OPTIONS] +"Unknown Options" +[DOWNLOAD_MODULES] +"$(CONFIGDIR)\$(PROJECTNAME).x30" 0 "IEEE695_RENESAS" 0 0 1 0 +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"TRUE" +[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION] +"FALSE" +[LIMIT_DISASSEMBLY_MEMORY_ACCESS] +"FALSE" +[DISABLE_MEMORY_ACCESS_DURING_EXECUTION] +"FALSE" +[DEBUGGER_OPTIONS_PROPERTIES] +"1" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"IEEE695_RENESAS" +[FLASH_DETAILS] +"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/SessionM32C_Simulator.ini b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/SessionM32C_Simulator.ini new file mode 100644 index 00000000..f37b7d93 --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/SessionM32C_Simulator.ini @@ -0,0 +1,13 @@ +[OTHER] +FMT=5 +OMF=14 +DISP_DA_FMT=1 +HIDE=0 +LOADFILE=C:\atomthreads\ports\m32c\hew_tests\hew_tst_sem1\hew_tst_sem1\Debug\hew_tst_sem1.x30 +LOADMODE=4 +[MCU] +PATH=C:\Program Files (x86)\Renesas\Hew\Tools\Renesas\DebugComp\Platform\PDTarget\PD308SIM\McuFiles\M32c8x.mcu +NAME=M32c8x.mcu +[INIT] +MCUCYCLE=20 +MCUDIVIDING=1 diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/cregdef.h b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/cregdef.h new file mode 100644 index 00000000..2bfc97bc --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/cregdef.h @@ -0,0 +1,38 @@ +/***********************************************************************/ +/* */ +/* FILE :cregdef.h */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :define the internal registers of MCU. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ + +/********************************************************************* + * STARTUP for M32C/9X + * Copyright (C) 2004 (2010) Renesas Electronics Corporation. + * and Renesas Solutions Corporation. All rights reserved. + * + * cregdef.h : defined control register + * + * note: Do not modify + * + * $Date: 2005/11/01 04:35:51 $ + * $Revision: 1.6 $ + *********************************************************************/ + +#pragma CREG _flg_ flg +#pragma CREG _isp_ isp +#pragma CREG _sp_ sp +#pragma CREG _sb_ sb +#pragma CREG _fb_ fb +#pragma CREG _intb_ intb +_UINT _flg_; +_UBYTE _far * _sb_; +_UBYTE _far * _fb_; +_UINT *_sp_; +_UINT *_isp_; +_UBYTE _far *_intb_; + + diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/fvector.c b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/fvector.c new file mode 100644 index 00000000..fbc33ebe --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/fvector.c @@ -0,0 +1,42 @@ +/***********************************************************************/ +/* */ +/* FILE :fvector.c */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :define the fixed vector table. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ + +/******************************************************************** + * M16C/M32C + * Copyright (C) 2004 (2010) Renesas Electronics Corporation. + * and Renesas Solutions Corporation. All rights reserved. + * + * resetprg.c : startup file + * + * Function:initialize each function + * + * $Date: 2005/11/01 04:35:50 $ + * $Revision: 1.7 $ + ********************************************************************/ +#include "vector.h" +#pragma sectaddress fvector,ROMDATA Fvectaddr + +//////////////////////////////////////////////////////////////////// + +#pragma interrupt/v _dummy_int //udi +#pragma interrupt/v _dummy_int //over_flow +#pragma interrupt/v _dummy_int //brki +#pragma interrupt/v _dummy_int //address_match +#pragma interrupt/v _dummy_int //single_step +#pragma interrupt/v _dummy_int //wdt +#pragma interrupt/v _dummy_int //dbc +#pragma interrupt/v _dummy_int //nmi +#pragma interrupt/v start //reset + + +#pragma interrupt _dummy_int() +void _dummy_int(void){} + diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/heapdef.h b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/heapdef.h new file mode 100644 index 00000000..384bb9a0 --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/heapdef.h @@ -0,0 +1,48 @@ +/***********************************************************************/ +/* */ +/* FILE :heapdef.h */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :initialize the heap area. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ +/********************************************************************* +* +* Device : M32C/80,M16C/80,M16C/70 +* +* File Name : heapdef.h +* +* Abstract : heap size definition +* +* History : 1.90 (2010-03-01) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2004 (2010) Renesas Electronics Corporation. +* and Renesas Solutions Corporation. All rights reserved. +* +*********************************************************************/ +#ifdef __HEAP__ +extern _UBYTE _far * _mnext; +extern _UDWORD _msize; +////////////////////////////////////////// +// It's size of heap +// When you want to change size of heap, +// please change this line. +// When you change this line, +// you must modify the value using hex character. + +#ifndef __HEAPSIZE__ +#define __HEAPSIZE__ 0x300UL +#endif +extern _UBYTE heap_area[__HEAPSIZE__]; +_inline void heap_init(void); +_inline void heap_init(void) +{ + _mnext = &heap_area[0]; + _msize = __HEAPSIZE__; +} + +#endif diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/hew_tst_sem1.hwp b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/hew_tst_sem1.hwp new file mode 100644 index 00000000..a8a19f4c --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/hew_tst_sem1.hwp @@ -0,0 +1,272 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.8" +[PROJECT_DETAILS] +"hew_tst_sem1" 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+[SESSION_DATA_CONFIGURATION_SESSION_Release_SessionM32C_Simulator] +"MEMORY_MAPPING_OPTIONS" "Unknown Options" +[EXT_DEBUGGER_INFO] +0 "" "" "" "" +[END] diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/hew_tst_sem1.nav b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/hew_tst_sem1.nav new file mode 100644 index 00000000..f6eded40 Binary files /dev/null and b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/hew_tst_sem1.nav differ diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/hew_tst_sem1.tps b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/hew_tst_sem1.tps new file mode 100644 index 00000000..d33b07c8 --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/hew_tst_sem1.tps @@ -0,0 +1,40 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.1" +[SESSIONS_] +"DefaultSession" +"SessionM32C_Simulator" +[CONFIGURATIONS] +"Debug" +"Debug_M32C_Simulator" +"Release" +[CURRENT_CONFIGURATION] +"Debug" +[CURRENT_SESSION] +"SessionM32C_Simulator" +[GENERAL_DATA_PROJECT] +[GENERAL_DATA_CONFIGURATION_Debug] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Debug] +"DefaultSession" +"SessionM32C_Simulator" +[GENERAL_DATA_CONFIGURATION_Debug_M32C_Simulator] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Debug_M32C_Simulator] +"DefaultSession" +"SessionM32C_Simulator" +[GENERAL_DATA_CONFIGURATION_Release] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Release] +"DefaultSession" +"SessionM32C_Simulator" +[GENERAL_DATA_SESSION_SessionM32C_Simulator] +[GENERAL_DATA_SESSION_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_SessionM32C_Simulator] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_M32C_Simulator_SessionM32C_Simulator] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_M32C_Simulator_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SessionM32C_Simulator] +[END] diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/initsct.c b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/initsct.c new file mode 100644 index 00000000..f320e83e --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/initsct.c @@ -0,0 +1,70 @@ +/***********************************************************************/ +/* */ +/* FILE :initsct.c */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :initialize each sections. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ +/********************************************************************* +* +* Device : M32C/80,M16C/80/70 +* +* File Name : initsct.c +* +* Abstract : initialize each sections. +* +* History : 1.70 (2009-12-08) +* : 1.71 (2010-03-01) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2009 (2010) Renesas Electronics Corporation. +* and Renesas Solutions Corporation. All rights reserved. +* +*********************************************************************/ + +#include "initsct.h" +void initsct(void); + +void initsct(void) +{ + sclear("bss_SE","data","align"); + sclear("bss_SO","data","noalign"); + sclear("bss_NE","data","align"); + sclear("bss_NO","data","noalign"); + sclear("bss_FE","data","align"); + sclear("bss_FO","data","noalign"); + + /* clear bss for NSD */ + sclear("bss_MON1_E","data","align"); + sclear("bss_MON2_E","data","align"); + sclear("bss_MON3_E","data","align"); + sclear("bss_MON4_E","data","align"); + sclear("bss_MON1_O","data","noalign"); + sclear("bss_MON2_O","data","noalign"); + sclear("bss_MON3_O","data","noalign"); + sclear("bss_MON4_O","data","noalign"); + + // add new sections. refer to the above-mentioned. + + scopy("data_SE","data","align"); + scopy("data_SO","data","noalign"); + scopy("data_NE","data","align"); + scopy("data_NO","data","noalign"); + + /* copy data section for NSD */ + scopy("data_MON1_E","data","align"); + scopy("data_MON2_E","data","align"); + scopy("data_MON3_E","data","align"); + scopy("data_MON4_E","data","align"); + scopy("data_MON1_O","data","noalign"); + scopy("data_MON2_O","data","noalign"); + scopy("data_MON3_O","data","noalign"); + scopy("data_MON4_O","data","noalign"); + scopy("data_FE","data","align"); + scopy("data_FO","data","noalign"); + +} diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/initsct.h b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/initsct.h new file mode 100644 index 00000000..91140e2b --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/initsct.h @@ -0,0 +1,66 @@ +/***********************************************************************/ +/* */ +/* FILE :initsct.h */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :define the macro for initialization of sections. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ +/********************************************************************* +* +* Device : M32C/80,M16C/80/70 +* +* File Name : initsct.h +* +* Abstract : define the macro for initialization of sections.(Do not modify) +* +* History : 1.80 (2009-12-08) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2009 (2010) Renesas Electronics Corporation. +* and Renesas Solutions Corporation. All rights reserved. +* +*********************************************************************/ + +#pragma section program interrupt +#define sclear(X,Y,Z) _asm(" .initsct "X","Y","Z"\n"\ + " mov.b #00H,R0L\n"\ + " mov.l #(topof "X") ,A1\n"\ + " mov.w #sizeof "X",R3\n"\ + " sstr.b"); + +#define sclear_f(X,Y,Z) _asm(" .initsct "X","Y","Z"\n"\ + " push.w #(sizeof "X")>>16\n"\ + " push.w #(sizeof "X")&0ffffH\n"\ + " pusha (topof "X")\n"\ + " .stk 8\n"\ + " .glb _bzero\n"\ + " .call _bzero,G\n"\ + " jsr.a _bzero\n"\ + " add.l #8H,sp\n"\ + " .stk -8"); + + +#define scopy(X,Y,Z) _asm(" .initsct "X","Y","Z"\n"\ + " .initsct "X"I,rom"Y",noalign\n"\ + " mov.l #(topof "X"I),A0\n"\ + " mov.l #(topof "X"),A1\n"\ + " mov.w #sizeof "X",R3\n"\ + " smovf.b"); + +#define scopy_f(X,Y,Z) _asm(" .initsct "X","Y","Z"\n"\ + " .initsct "X"I,rom"Y",noalign\n"\ + " push.w #(sizeof "X") >> 16\n"\ + " push.w #(sizeof "X") & 0ffffH\n"\ + " pusha (topof "X")\n"\ + " pusha (topof "X"I)\n"\ + " .stk 12\n"\ + " .glb _bcopy\n"\ + " .call _bcopy,G\n"\ + " jsr.a _bcopy\n"\ + " add.l #8H,sp\n"\ + " .stk -12"); + diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/intprg.c b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/intprg.c new file mode 100644 index 00000000..f621ddab --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/intprg.c @@ -0,0 +1,224 @@ +/***********************************************************************/ +/* */ +/* FILE :intprg.c */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :interrupt program. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ + +/*************************************************************************** + * COMPILER for M16C/80,M32C/80 + * Copyright (C) 2004 (2010) Renesas Electronics Corporation. + * and Renesas Solutions Corporation. All rights reserved. * + * intprg.c : define variable vector table for M32C/80 + * + * + * $Date: 2005/11/24 07:15:36 $ + * $Revision: 1.4 $ + **************************************************************************/ + +// BRK (software int 0) +#pragma interrupt _brk(vect=0) +void _brk(void){} + +// vector 1 reserved +// vector 2 reserved +// vector 3 reserved +// vector 4 reserved +// vector 5 reserved +// vector 6 reserved +// vector 7 reserved + +// DMA0 (software int 8) +#pragma interrupt _dma0(vect=8) +void _dma0(void){} + +// DMA1 (software int 9) +#pragma interrupt _dma1(vect=9) +void _dma1(void){} + +// DMA2 (software int 10) +#pragma interrupt _dma2(vect=10) +void _dma2(void){} + +// DMA3 (software int 11) +#pragma interrupt _dma3(vect=11) +void _dma3(void){} + +// TIMER A0 (software int 12) +#pragma interrupt _timer_a0(vect=12) +void _timer_a0(void){} + +// TIMER A1 (software int 13) +#pragma interrupt _timer_a1(vect=13) +void _timer_a1(void){} + +// TIMER A2 (software int 14) +#pragma interrupt _timer_a2(vect=14) +void _timer_a2(void){} + +// TIMER A3 (software int 15) +#pragma interrupt _timer_a3(vect=15) +void _timer_a3(void){} + +// TIMER A4 (software int 16) +#pragma interrupt _timer_a4(vect=16) +void _timer_a4(void){} + +#if defined (__STANDARD_IO__) && (defined(__FOUSB__) || defined(__E8__)) +// uart0 can't be used +#else +// uart0 trance/NACK (software int 17) +#pragma interrupt _uart0_trance(vect=17) +void _uart0_trance(void){} +#endif + +// uart0 receive/ACK (software int 18) +#pragma interrupt _uart0_receive(vect=18) +void _uart0_receive(void){} + +#if defined(__STANDARD_IO__) || defined(__FOUSB__) || defined(__E8__) +// uart1 can't be used +#else +// uart1 trance/NACK (software int 19) +#pragma interrupt _uart1_trance(vect=19) +void _uart1_trance(void){} +#endif + +// uart1 receive/ACK (software int 20) +#pragma interrupt _uart1_receive(vect=20) +void _uart1_receive(void){} + +// TIMER B0 (software int 21) +#pragma interrupt _timer_b0(vect=21) +void _timer_b0(void){} + +// TIMER B1 (software int 22) +#pragma interrupt _timer_b1(vect=22) +void _timer_b1(void){} + +#if 0 +// TIMER B2 (software int 23) +#pragma interrupt _timer_b2(vect=23) +void _timer_b2(void){} +#endif + +// TIMER B3 (software int 24) +#pragma interrupt _timer_b3(vect=24) +void _timer_b3(void){} + +// TIMER B4 (software int 25) +#pragma interrupt _timer_b4(vect=25) +void _timer_b4(void){} + +// INT5 (software int 26) +#pragma interrupt _int5(vect=26) +void _int5(void){} + +// INT4 (software int 27) +#pragma interrupt _int4(vect=27) +void _int4(void){} + +// INT3 (software int 28) +#pragma interrupt _int3(vect=28) +void _int3(void){} + +// INT2 (software int 29) +#pragma interrupt _int2(vect=29) +void _int2(void){} + +// INT1 (software int 30) +#pragma interrupt _int1(vect=30) +void _int1(void){} + +// INT0 (software int 31) +#pragma interrupt _int0(vect=31) +void _int0(void){} + +// Timer B5 (software int 32) +#pragma interrupt _timer_b5(vect=32) +void _timer_b5(void){} + +// uart2 trance/NACK (software int 33) +#pragma interrupt _uart2_trance(vect=33) +void _uart2_trance(void){} + +// uart2 receive/ACK (software int 34) +#pragma interrupt _uart2_receive(vect=34) +void _uart2_receive(void){} + +// uart3 trance/NACK (software int 35) +#pragma interrupt _uart3_trance(vect=35) +void _uart3_trance(void){} + +// uart3 receive/ACK (software int 36) +#pragma interrupt _uart3_receive(vect=36) +void _uart3_receive(void){} + +// uart4 trance/NACK (software int 37) +#pragma interrupt _uart4_trance(vect=37) +void _uart4_trance(void){} + +// uart4 receive/ACK (software int 38) +#pragma interrupt _uart4_receive(vect=38) +void _uart4_receive(void){} + +// Bus Collision/start/stop condition(uart2) (software int 39) +#pragma interrupt _bus_collision_u2(vect=39) +void _bus_collision_u2(void){} + +// Bus Collision/start/stop condition(uart3 or uart0) (software int 40) +#pragma interrupt _bus_collision_u3(vect=40) +void _bus_collision_u3(void){} + +// Bus Collision/start/stop condition(uart4 or uart1) (software int 41) +#pragma interrupt _bus_collision_u4(vect=41) +void _bus_collision_u4(void){} + +// A-D (software int 42) +#pragma interrupt _ad_converter(vect=42) +void _ad_converter(void){} + +// input key (software int 43) +#pragma interrupt _input_key(vect=43) +void _input_key(void){} + +// intelligent I/O interrupt 0 (software int 44) +#pragma interrupt _intelligent_io_int0(vect=44) +void _intelligent_io_int0(void){} + +// intelligent I/O interrupt 1 (software int 45) +#pragma interrupt _intelligent_io_int1(vect=45) +void _intelligent_io_int1(void){} + +// intelligent I/O interrupt 2 (software int 46) +#pragma interrupt _intelligent_io_int2(vect=46) +void _intelligent_io_int2(void){} + +// intelligent I/O interrupt 3 (software int 47) +#pragma interrupt _intelligent_io_int3(vect=47) +void _intelligent_io_int3(void){} + +// intelligent I/O interrupt 4 (software int 48) +#pragma interrupt _intelligent_io_int4(vect=48) +void _intelligent_io_int4(void){} + +// software int 49 for user +// software int 50 for user +// software int 51 for user +// software int 52 for user +// software int 53 for user +// software int 54 for user +// software int 55 for user or MR308 +// software int 56 for user +// software int 57 for user +// software int 58 for user or MR308 +// software int 59 for user or MR308 +// software int 60 for user or MR308 +// software int 61 for user or MR308 +// software int 62 for user or MR308 +// software int 63 for user or MR308 + diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/resetprg.c b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/resetprg.c new file mode 100644 index 00000000..48d61ba9 --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/resetprg.c @@ -0,0 +1,87 @@ +/***********************************************************************/ +/* */ +/* FILE :resetprg.c */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :initialize for C language. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ + +/********************************************************************* + * STARTUP for M32C + * Copyright (C) 2004 (2010) Renesas Electronics Corporation. + * and Renesas Solutions Corporation. All rights reserved. * + * + * restprg.c : startup file + * + * Function:initialize each function + * + * $Date: 2006/06/16 03:10:49 $ + * $Revision: 1.16 $ + ********************************************************************/ +#include "resetprg.h" +//////////////////////////////////////////// +// declare sfr register +#pragma ADDRESS protect 0AH +#pragma ADDRESS pmode0 04H +#pragma ADDRESS _SB__ 0400H +_UBYTE protect,pmode0; +_UBYTE _SB__; + +DEF_SBREGISTER; + +#pragma entry start +void start(void); +extern void initsct(void); +extern void _init(void); +void exit(void); +void main(void); + +#pragma section program interrupt +#pragma inline set_cpu() +void set_cpu(void) +{ + _isp_ = &_istack_top; // set interrupt stack pointer + protect = 0x02; // change protect mode register + pmode0 = 0x00; // set processor mode register + protect = 0x00; // change protect mode register + _flg_ = 0x0080; // set flag register + _sp_ = &_stack_top; // set user stack pointer + _sb_ = (char _far *)0x400; // 400H fixation (Do not change) + _asm(" fset b"); + _sb_ = (char _far *)0x400; + _asm(" fclr b"); + _intb_ = (char _far *)VECTOR_ADR; // set variable vector's address + +} + +void start(void) +{ + set_cpu(); // initialize mcu + initsct(); // initlalize each sections + _sp_ = &_stack_top; // set user stack pointer +#ifdef __HEAP__ + heap_init(); // initialize heap +#endif +#ifdef __STANDARD_IO__ + _init(); // initialize standard I/O +#endif + _fb_ = 0; // initialize FB registe for debugger + main(); // call main routine + + exit(); // infinite loop +} + +void exit(void) +{ + while(1); +} + + +//////////////////////////////////////////////////// +// declaration dummy function as interrupt routine +#pragma INTERRUPT dummy() +void dummy(void){} + diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/resetprg.h b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/resetprg.h new file mode 100644 index 00000000..0b017445 --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/resetprg.h @@ -0,0 +1,35 @@ +/***********************************************************************/ +/* */ +/* FILE :resetprg.h */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :include some headder files. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ + +/*********************************************************************** + * startup for M32C/90,M32C/80,M16C/80,M16C/70 + * Copyright (C) 2004 (2010) Renesas Electronics Corporation. + * and Renesas Solutions Corporation. All rights reserved. + * + * resetprg.h : include any headder files + * + * Function: include any Headder files and prototype difinition + * + * $Date: 2005/11/25 10:26:31 $ + * $Revision: 1.9 $ + **********************************************************************/ +/////////////////////////////////////////////// +// include some header files. +// declare prototype difinition +// +#include "typedefine.h" +#include "heapdef.h" +#include "cregdef.h" +#include "stackdef.h" +#include "vector.h" + +#define DEF_SBREGISTER _asm(" .glb __SB__\n"\ + "__SB__ .equ 0400H") diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/sfr32c80.h b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/sfr32c80.h new file mode 100644 index 00000000..f7da2bda --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/sfr32c80.h @@ -0,0 +1,3688 @@ +/***********************************************************************/ +/* */ +/* FILE :sfr32c80.h */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :define the sfr register. (for C language) */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ + +/************************************************************************************ +* * +* File name : sfr32c80.h * +* Contents : Definition of M32C/80 Group SFR * +* * +* Copyright (C) 2003 (2010) Renesas Electronics Corporation. * +* and Renesas Solutions Corporation. All rights reserved. * +* * +* Note : * +* * +* Version : Ver 0.01 (05-12-08) Preliminary * +* These data made based on M32C/80 Group H/W Manual Rev.1.0 * +* * +*************************************************************************************/ +/* + note: + This data is a freeware that SFR for M32C/80 group are described. + RENESAS ELECTRONICS CORPORATION and RENESAS SOLUTIONS CORPORATION assume + no responsibility for any damage that occurred by this data. +*/ + +/************************************************************************ +* declare SFR address * +************************************************************************/ +#pragma ADDRESS pm0_addr 0004H /* Processor mode register 0 */ +#pragma ADDRESS pm1_addr 0005H /* Processor mode register 1 */ +#pragma ADDRESS cm0_addr 0006H /* System clock control register 0 */ +#pragma ADDRESS cm1_addr 0007H /* System clock control register 1 */ + +#pragma ADDRESS aier_addr 0009H /* Address match interrupt enable register */ +#pragma ADDRESS prcr_addr 000aH /* Protect register */ +#pragma ADDRESS ds_addr 000bH /* External data bus width control register */ +#pragma ADDRESS mcd_addr 000cH /* Main clock division register */ +#pragma ADDRESS cm2_addr 000dH /* Oscillation stop detect register */ +#pragma ADDRESS wdts_addr 000eH /* Watchdog timer start register */ +#pragma ADDRESS wdc_addr 000fH /* Watchdog timer control register */ +#pragma ADDRESS rmad0_addr 0010H /* Address match interrupt register 0 */ +#pragma ADDRESS pm2_addr 0013H /* Processor mode register 2 */ +#pragma ADDRESS rmad1_addr 0014H /* Address match interrupt register 1 */ +#pragma ADDRESS vcr2_addr 0017H /* Voltage detection register 2 */ +#pragma ADDRESS rmad2_addr 0018H /* Address match interrupt register 2 */ +#pragma ADDRESS vcr1_addr 001bH /* Voltage detection register 1 */ +#pragma ADDRESS rmad3_addr 001cH /* Address match interrupt register 3 */ + +#pragma ADDRESS plc_addr 0026H /* PLL control register */ +#pragma ADDRESS plc0_addr 0026H /* PLL control register 0 */ +#pragma ADDRESS plc1_addr 0027H /* PLL control register 1 */ +#pragma ADDRESS rmad4_addr 0028H /* Address match interrupt register 4 */ + +#pragma ADDRESS rmad5_addr 002CH /* Address match interrupt register 5 */ + +#pragma ADDRESS rmad6_addr 0038H /* Address match interrupt register 6 */ +#pragma ADDRESS rmad7_addr 003CH /* Address match interrupt register 7 */ + +#pragma ADDRESS ewcr0_addr 0048H /* External space wait control register 0 */ +#pragma ADDRESS ewcr1_addr 0049H /* External space wait control register 1 */ +#pragma ADDRESS ewcr2_addr 004AH /* External space wait control register 2 */ +#pragma ADDRESS ewcr3_addr 004BH /* External space wait control register 3 */ + +#pragma ADDRESS dm0ic_addr 0068H /* DMA0 interrupt control register */ +#pragma ADDRESS tb5ic_addr 0069H /* Timer B5 interrupt register */ +#pragma ADDRESS dm2ic_addr 006aH /* DMA2 interrupt register */ +#pragma ADDRESS s2ric_addr 006bH /* UART2 receive/ack interrupt control register */ +#pragma ADDRESS ta0ic_addr 006cH /* Timer A0 interrupt control register */ +#pragma ADDRESS s3ric_addr 006dH /* UART3 receive/ack interrupt control register */ +#pragma ADDRESS ta2ic_addr 006eH /* Timer A2 interrupt control register */ +#pragma ADDRESS s4ric_addr 006fH /* UART4 receive/ack interrupt control register */ +#pragma ADDRESS ta4ic_addr 0070H /* Timer A4 interrupt control register */ +#pragma ADDRESS bcn0ic_addr 0071H /* Bus collision (UART0) interrupt control register */ +#pragma ADDRESS bcn3ic_addr 0071H /* Bus collision (UART3) interrupt control register */ +#pragma ADDRESS s0ric_addr 0072H /* UART0 receive interrupt control register */ +#pragma ADDRESS ad0ic_addr 0073H /* A/D0 conversion interrupt control register */ +#pragma ADDRESS s1ric_addr 0074H /* UART1 receive interrupt control register */ +#pragma ADDRESS iio0ic_addr 0075H /* Intelligent I/O interrupt control register 0 */ +#pragma ADDRESS tb1ic_addr 0076H /* Timer B1 interrupt control register */ +#pragma ADDRESS iio2ic_addr 0077H /* Intelligent I/O interrupt control register 2 */ +#pragma ADDRESS tb3ic_addr 0078H /* Timer B3 interrupt control register */ +#pragma ADDRESS iio4ic_addr 0079H /* Intelligent I/O interrupt control register 4 */ +#pragma ADDRESS int5ic_addr 007aH /* INT5~ interrupt control register */ + +#pragma ADDRESS int3ic_addr 007cH /* INT3~ interrupt control register */ +#pragma ADDRESS int1ic_addr 007eH /* INT1~ interrupt control register */ + +#pragma ADDRESS dm1ic_addr 0088H /* DMA1 interrupt control register */ +#pragma ADDRESS s2tic_addr 0089H /* UART2 transmit/nack interrupt control register */ +#pragma ADDRESS dm3ic_addr 008aH /* DMA3 interrupt control register */ +#pragma ADDRESS s3tic_addr 008bH /* UART3 transmit/nack interrupt control register */ +#pragma ADDRESS ta1ic_addr 008cH /* Timer A1 interrupt control register */ +#pragma ADDRESS s4tic_addr 008dH /* UART4 transmit/nack interrupt control register */ +#pragma ADDRESS ta3ic_addr 008eH /* Timer A3 interrupt control register */ +#pragma ADDRESS bcn2ic_addr 008fH /* Bus collision (UART2) interrupt control register */ +#pragma ADDRESS s0tic_addr 0090H /* UART0 transmit interrupt control register */ +#pragma ADDRESS bcn1ic_addr 0091H /* Bus collision (UART1) interrupt control register*/ +#pragma ADDRESS bcn4ic_addr 0091H /* Bus collision (UART4) interrupt control register */ +#pragma ADDRESS s1tic_addr 0092H /* UART1 transmit interrupt control register */ +#pragma ADDRESS kupic_addr 0093H /* Key input interrupt control register */ +#pragma ADDRESS tb0ic_addr 0094H /* Timer B0 interrupt control register */ +#pragma ADDRESS iio1ic_addr 0095H /* Intelligent I/O interrupt control register 1 */ +#pragma ADDRESS tb2ic_addr 0096H /* Timer B2 interrupt control register */ +#pragma ADDRESS iio3ic_addr 0097H /* Intelligent I/O interrupt control register 3 */ +#pragma ADDRESS tb4ic_addr 0098H /* Timer B4 interrupt control register */ +#pragma ADDRESS int4ic_addr 009aH /* INT4~ interrupt control register */ + +#pragma ADDRESS int2ic_addr 009cH /* INT2~ interrupt control register */ +#pragma ADDRESS int0ic_addr 009eH /* INT0~ interrupt control register */ +#pragma ADDRESS rlvl_addr 009fH /* Exit priority register */ +#pragma ADDRESS iio0ir_addr 00a0H /* Interrupt request register 0 */ +#pragma ADDRESS iio1ir_addr 00a1H /* Interrupt request register 1 */ +#pragma ADDRESS iio2ir_addr 00a2H /* Interrupt request register 2 */ +#pragma ADDRESS iio3ir_addr 00a3H /* Interrupt request register 3 */ +#pragma ADDRESS iio4ir_addr 00a4H /* Interrupt request register 4 */ +#pragma ADDRESS iio5ir_addr 00a5H /* Interrupt request register 5 */ + +#pragma ADDRESS iio0ie_addr 00b0H /* Interrupt enable register 0 */ +#pragma ADDRESS iio1ie_addr 00b1H /* Interrupt enable register 1 */ +#pragma ADDRESS iio2ie_addr 00b2H /* Interrupt enable register 2 */ +#pragma ADDRESS iio3ie_addr 00b3H /* Interrupt enable register 3 */ +#pragma ADDRESS iio4ie_addr 00b4H /* Interrupt enable register 4 */ + +#pragma ADDRESS g0rb_addr 00e8H /* SI/O receive buffer register 0 */ +#pragma ADDRESS g0tb_addr 00eaH /* Transmit buffer register 0 */ +#pragma ADDRESS g0dr_addr 00eaH /* Receive data register 0 */ + +#pragma ADDRESS g0ri_addr 00ecH /* Receive input register 0 */ +#pragma ADDRESS g0mr_addr 00edH /* SI/O communication control register 0 */ +#pragma ADDRESS g0to_addr 00eeH /* Transmit output register 0 */ +#pragma ADDRESS g0cr_addr 00efH /* SI/O communication control register 0 */ +#pragma ADDRESS g0cmp0_addr 00f0H /* Data compare register 00 */ +#pragma ADDRESS g0cmp1_addr 00f1H /* Data compare register 01 */ +#pragma ADDRESS g0cmp2_addr 00f2H /* Data compare register 02 */ +#pragma ADDRESS g0cmp3_addr 00f3H /* Data compare register 03 */ +#pragma ADDRESS g0msk0_addr 00f4H /* Data mask register 00 */ +#pragma ADDRESS g0msk1_addr 00f5H /* Data mask register 01 */ +#pragma ADDRESS ccs_addr 00f6H /* Communication clock select register */ + +#pragma ADDRESS g0rcrc_addr 00f8H /* Receive CRC code register 0 */ +#pragma ADDRESS g0tcrc_addr 00faH /* Transmit CRC code register 0 */ +#pragma ADDRESS g0emr_addr 00fcH /* SI/O expansion mode register 0 */ +#pragma ADDRESS g0erc_addr 00fdH /* SI/O expansion receive control register 0 */ +#pragma ADDRESS g0irf_addr 00feH /* SI/O special communication interrupt detect register 0 */ +#pragma ADDRESS g0etc_addr 00ffH /* SI/O expansion transmit control register 0 */ + +#pragma ADDRESS g1rb_addr 0128H /* SI/O receive buffer register 1 */ +#pragma ADDRESS g1tb_addr 012aH /* Transmit buffer register 1 */ +#pragma ADDRESS g1dr_addr 012aH /* Receive data register 1 */ + +#pragma ADDRESS g1ri_addr 012cH /* Receive input register 1 */ +#pragma ADDRESS g1mr_addr 012dH /* SI/O communication mode register 1 */ +#pragma ADDRESS g1to_addr 012eH /* Transmit output register 1 */ +#pragma ADDRESS g1cr_addr 012fH /* SI/O communication control register 1 */ +#pragma ADDRESS g1cmp0_addr 0130H /* Data compare register 10 */ +#pragma ADDRESS g1cmp1_addr 0131H /* Data compare register 11 */ +#pragma ADDRESS g1cmp2_addr 0132H /* Data compare register 12 */ +#pragma ADDRESS g1cmp3_addr 0133H /* Data compare register 13 */ +#pragma ADDRESS g1msk0_addr 0134H /* Data mask register 10 */ +#pragma ADDRESS g1msk1_addr 0135H /* Data mask register 11 */ + +#pragma ADDRESS g1rcrc_addr 0138H /* Receive CRC code register 1 */ +#pragma ADDRESS g1tcrc_addr 013aH /* Transmit CRC code register 1 */ +#pragma ADDRESS g1emr_addr 013cH /* SI/O extended mode register 1 */ +#pragma ADDRESS g1erc_addr 013dH /* SI/O extended receive control register 1 */ +#pragma ADDRESS g1irf_addr 013eH /* SI/O special communication interrupt detect register 1 */ +#pragma ADDRESS g1etc_addr 013fH /* SI/O extended transmit control register 1 */ + +/************************************************************************ +* * +************************************************************************/ +#pragma ADDRESS x0r_addr 02c0H /* X0 register */ +#pragma ADDRESS y0r_addr 02c0H /* Y0 register */ +#pragma ADDRESS x1r_addr 02c2H /* X1 register */ +#pragma ADDRESS y1r_addr 02c2H /* Y1 register */ +#pragma ADDRESS x2r_addr 02c4H /* X2 register */ +#pragma ADDRESS y2r_addr 02c4H /* Y2 register */ +#pragma ADDRESS x3r_addr 02c6H /* X3 register */ +#pragma ADDRESS y3r_addr 02c6H /* Y3 register */ +#pragma ADDRESS x4r_addr 02c8H /* X4 register */ +#pragma ADDRESS y4r_addr 02c8H /* Y4 register */ +#pragma ADDRESS x5r_addr 02caH /* X5 register */ +#pragma ADDRESS y5r_addr 02caH /* Y5 register */ +#pragma ADDRESS x6r_addr 02ccH /* X6 register */ +#pragma ADDRESS y6r_addr 02ccH /* Y6 register */ +#pragma ADDRESS x7r_addr 02ceH /* X7 register */ +#pragma ADDRESS y7r_addr 02ceH /* Y7 register */ +#pragma ADDRESS x8r_addr 02d0H /* X8 register */ +#pragma ADDRESS y8r_addr 02d0H /* Y8 register */ +#pragma ADDRESS x9r_addr 02d2H /* X9 register */ +#pragma ADDRESS y9r_addr 02d2H /* Y9 register */ +#pragma ADDRESS x10r_addr 02d4H /* X10 register */ +#pragma ADDRESS y10r_addr 02d4H /* Y10 register */ +#pragma ADDRESS x11r_addr 02d6H /* X11 register */ +#pragma ADDRESS y11r_addr 02d6H /* Y11 register */ +#pragma ADDRESS x12r_addr 02d8H /* X12 register */ +#pragma ADDRESS y12r_addr 02d8H /* Y12 register */ +#pragma ADDRESS x13r_addr 02daH /* X13 register */ +#pragma ADDRESS y13r_addr 02daH /* Y13 register */ +#pragma ADDRESS x14r_addr 02dcH /* X14 register */ +#pragma ADDRESS y14r_addr 02dcH /* Y14 register */ +#pragma ADDRESS x15r_addr 02deH /* X15 register */ +#pragma ADDRESS y15r_addr 02deH /* Y15 register */ +#pragma ADDRESS xyc_addr 02e0H /* X-Y control register */ + +#pragma ADDRESS u1smr4_addr 02e4H /* UART1 special mode register 4 */ +#pragma ADDRESS u1smr3_addr 02e5H /* UART1 special mode register 3 */ +#pragma ADDRESS u1smr2_addr 02e6H /* UART1 special mode register 2 */ +#pragma ADDRESS u1smr_addr 02e7H /* UART1 special mode register */ +#pragma ADDRESS u1mr_addr 02e8H /* UART1 transmit/receive mode register */ +#pragma ADDRESS u1brg_addr 02e9H /* UART1 bit rate generator */ +#pragma ADDRESS u1tb_addr 02eaH /* UART1 transmit buffer register */ +#pragma ADDRESS u1c0_addr 02ecH /* UART1 transmit/receive control register 0 */ +#pragma ADDRESS u1c1_addr 02edH /* UART1 transmit/receive control register 1 */ +#pragma ADDRESS u1rb_addr 02eeH /* UART1 receive buffer register */ + +#pragma ADDRESS u4smr4_addr 02f4H /* UART4 special mode register 4 */ +#pragma ADDRESS u4smr3_addr 02f5H /* UART4 special mode register 3 */ +#pragma ADDRESS u4smr2_addr 02f6H /* UART4 special mode register 2 */ +#pragma ADDRESS u4smr_addr 02f7H /* UART4 special mode register */ +#pragma ADDRESS u4mr_addr 02f8H /* UART4 transmit/receive mode register */ +#pragma ADDRESS u4brg_addr 02f9H /* UART4 bit rate generator */ +#pragma ADDRESS u4tb_addr 02faH /* UART4 transmit buffer register */ +#pragma ADDRESS u4c0_addr 02fcH /* UART4 transmit/receive control register 0 */ +#pragma ADDRESS u4c1_addr 02fdH /* UART4 transmit/receive control register 1 */ +#pragma ADDRESS u4rb_addr 02feH /* UART4 receive buffer register */ + +#pragma ADDRESS tbsr_addr 0300H /* Timer B3,4,5 count start flag */ + +#pragma ADDRESS ta11_addr 0302H /* Timer A1-1 register */ +#pragma ADDRESS ta21_addr 0304H /* Timer A2-1 register */ +#pragma ADDRESS ta41_addr 0306H /* Timer A4-1 register */ +#pragma ADDRESS invc0_addr 0308H /* Three-phase PWM control register 0 */ +#pragma ADDRESS invc1_addr 0309H /* Three-phase PWM control register 1 */ +#pragma ADDRESS idb0_addr 030aH /* Three-phase output buffer register 0 */ +#pragma ADDRESS idb1_addr 030bH /* Three-phase output buffer register 1 */ +#pragma ADDRESS dtt_addr 030cH /* Dead time timer */ +#pragma ADDRESS ictb2_addr 030dH /* Timer B2 interrupt occurences frequency set counter */ + +#pragma ADDRESS tb3_addr 0310H /* Timer B3 register */ +#pragma ADDRESS tb4_addr 0312H /* Timer B4 register */ +#pragma ADDRESS tb5_addr 0314H /* Timer B5 register */ + +#pragma ADDRESS tb3mr_addr 031bH /* Timer B3 mode register */ +#pragma ADDRESS tb4mr_addr 031cH /* Timer B4 mode register */ +#pragma ADDRESS tb5mr_addr 031dH /* Timer B5 mode register */ + +#pragma ADDRESS ifsr_addr 031fH /* External interrupt request cause select register */ + +#pragma ADDRESS u3smr4_addr 0324H /* UART3 special mode register 4 */ +#pragma ADDRESS u3smr3_addr 0325H /* UART3 special mode register 3 */ +#pragma ADDRESS u3smr2_addr 0326H /* UART3 special mode register 2 */ +#pragma ADDRESS u3smr_addr 0327H /* UART3 special mode register */ +#pragma ADDRESS u3mr_addr 0328H /* UART3 transmit/receive mode register */ +#pragma ADDRESS u3brg_addr 0329H /* UART3 bit rate generator */ +#pragma ADDRESS u3tb_addr 032aH /* UART3 transmit buffer register */ +#pragma ADDRESS u3c0_addr 032cH /* UART3 transmit/receive control register 0 */ +#pragma ADDRESS u3c1_addr 032dH /* UART3 transmit/receive control register 1 */ +#pragma ADDRESS u3rb_addr 032eH /* UART3 receive buffer register */ + +#pragma ADDRESS u2smr4_addr 0334H /* UART2 special mode register 4 */ +#pragma ADDRESS u2smr3_addr 0335H /* UART2 special mode register 3 */ +#pragma ADDRESS u2smr2_addr 0336H /* UART2 special mode register 2 */ +#pragma ADDRESS u2smr_addr 0337H /* UART2 special mode register */ +#pragma ADDRESS u2mr_addr 0338H /* UART2 transmit/receive mode register */ +#pragma ADDRESS u2brg_addr 0339H /* UART2 bit rate generator */ +#pragma ADDRESS u2tb_addr 033aH /* UART2 transmit buffer register */ +#pragma ADDRESS u2c0_addr 033cH /* UART2 transmit/receive control register 0 */ +#pragma ADDRESS u2c1_addr 033dH /* UART2 transmit/receive control register 1 */ +#pragma ADDRESS u2rb_addr 033eH /* UART2 receive buffer register */ +#pragma ADDRESS tabsr_addr 0340H /* Count start flag */ +#pragma ADDRESS cpsrf_addr 0341H /* Clock prescaler reset flag */ +#pragma ADDRESS onsf_addr 0342H /* One-shot start flag */ +#pragma ADDRESS trgsr_addr 0343H /* Trigger select register */ +#pragma ADDRESS udf_addr 0344H /* Up/down flag */ + +#pragma ADDRESS ta0_addr 0346H /* Timer A0 register */ +#pragma ADDRESS ta1_addr 0348H /* Timer A1 register */ +#pragma ADDRESS ta2_addr 034aH /* Timer A2 register */ +#pragma ADDRESS ta3_addr 034cH /* Timer A3 register */ +#pragma ADDRESS ta4_addr 034eH /* Timer A4 register */ +#pragma ADDRESS tb0_addr 0350H /* Timer B0 register */ +#pragma ADDRESS tb1_addr 0352H /* Timer B1 register */ +#pragma ADDRESS tb2_addr 0354H /* Timer B2 register */ +#pragma ADDRESS ta0mr_addr 0356H /* Timer A0 mode register */ +#pragma ADDRESS ta1mr_addr 0357H /* Timer A1 mode register */ +#pragma ADDRESS ta2mr_addr 0358H /* Timer A2 mode register */ +#pragma ADDRESS ta3mr_addr 0359H /* Timer A3 mode register */ +#pragma ADDRESS ta4mr_addr 035aH /* Timer A4 mode register */ +#pragma ADDRESS tb0mr_addr 035bH /* Timer B0 mode register */ +#pragma ADDRESS tb1mr_addr 035cH /* Timer B1 mode register */ +#pragma ADDRESS tb2mr_addr 035dH /* Timer B2 mode register */ +#pragma ADDRESS tb2sc_addr 035eH /* Timer B2 special mode register */ +#pragma ADDRESS tcspr_addr 035fH /* Count source prescaler register */ + +#pragma ADDRESS u0smr4_addr 0364H /* UART0 special mode register 4 */ +#pragma ADDRESS u0smr3_addr 0365H /* UART0 special mode register 3 */ +#pragma ADDRESS u0smr2_addr 0366H /* UART0 special mode register 2 */ +#pragma ADDRESS u0smr_addr 0367H /* UART0 special mode register */ +#pragma ADDRESS u0mr_addr 0368H /* UART0 transmit/receive mode register */ +#pragma ADDRESS u0brg_addr 0369H /* UART0 bit rate generator */ +#pragma ADDRESS u0tb_addr 036aH /* UART0 transmit buffer register */ +#pragma ADDRESS u0c0_addr 036cH /* UART0 transmit/receive control register 0 */ +#pragma ADDRESS u0c1_addr 036dH /* UART0 transmit/receive control register 1 */ +#pragma ADDRESS u0rb_addr 036eH /* UART0 receive buffer register */ + +#pragma ADDRESS dm0sl_addr 0378H /* DMA0 cause select register */ +#pragma ADDRESS dm1sl_addr 0379H /* DMA1 cause select register */ +#pragma ADDRESS dm2sl_addr 037aH /* DMA1 cause select register */ +#pragma ADDRESS dm3sl_addr 037bH /* DMA1 cause select register */ +#pragma ADDRESS crcd_addr 037cH /* CRC data register */ +#pragma ADDRESS crcin_addr 037eH /* CRC input register */ + +#pragma ADDRESS ad00_addr 0380H /* A/D0 register 0 */ +#pragma ADDRESS ad01_addr 0382H /* A/D0 register 1 */ +#pragma ADDRESS ad02_addr 0384H /* A/D0 register 2 */ +#pragma ADDRESS ad03_addr 0386H /* A/D0 register 3 */ +#pragma ADDRESS ad04_addr 0388H /* A/D0 register 4 */ +#pragma ADDRESS ad05_addr 038aH /* A/D0 register 5 */ +#pragma ADDRESS ad06_addr 038cH /* A/D0 register 6 */ +#pragma ADDRESS ad07_addr 038eH /* A/D0 register 7 */ + +#pragma ADDRESS ad0con2_addr 0394H /* A/D0 control register 2 */ +#pragma ADDRESS ad0con3_addr 0395H /* A/D0 control register 3 */ +#pragma ADDRESS ad0con0_addr 0396H /* A/D0 control register 0 */ +#pragma ADDRESS ad0con1_addr 0397H /* A/D0 control register 1 */ +#pragma ADDRESS da0_addr 0398H /* D/A register 0 */ + +#pragma ADDRESS da1_addr 039aH /* D/A register 1 */ + +#pragma ADDRESS dacon_addr 039cH /* D/A control register */ + +#pragma ADDRESS psd1_addr 03a7H /* Function select register D1 */ + +#pragma ADDRESS psc3_addr 03adH /* Function select register C3 */ + +#pragma ADDRESS psc_addr 03afH /* Function select register C */ +#pragma ADDRESS ps0_addr 03b0H /* Function select register A0 */ +#pragma ADDRESS ps1_addr 03b1H /* Function select register A1 */ +#pragma ADDRESS psl0_addr 03b2H /* Function select register B0 */ +#pragma ADDRESS psl1_addr 03b3H /* Function select register B1 */ +#pragma ADDRESS ps2_addr 03b4H /* Function select register A2 */ +#pragma ADDRESS ps3_addr 03b5H /* Function select register A3 */ +#pragma ADDRESS psl2_addr 03b6H /* Function select register B2 */ +#pragma ADDRESS psl3_addr 03b7H /* Function select register B3 */ + +#pragma ADDRESS p6_addr 03c0H /* Port P6 register */ +#pragma ADDRESS p7_addr 03c1H /* Port P7 register */ +#pragma ADDRESS pd6_addr 03c2H /* Port P6 direction register */ +#pragma ADDRESS pd7_addr 03c3H /* Port P7 direction register */ +#pragma ADDRESS p8_addr 03c4H /* Port P8 register */ +#pragma ADDRESS p9_addr 03c5H /* Port P9 register */ +#pragma ADDRESS pd8_addr 03c6H /* Port P8 direction register */ +#pragma ADDRESS pd9_addr 03c7H /* Port P9 direction register */ +#pragma ADDRESS p10_addr 03c8H /* Port P10 register */ +#pragma ADDRESS pd10_addr 03caH /* Port P10 direction register */ + +#pragma ADDRESS pur3_addr 03dbH /* Pull-up control register 3 */ +#pragma ADDRESS pur4_addr 03dcH /* Pull-up control register 4 */ + +#pragma ADDRESS p0_addr 03e0H /* Port P0 register */ +#pragma ADDRESS p1_addr 03e1H /* Port P1 register */ +#pragma ADDRESS pd0_addr 03e2H /* Port P0 direction register */ +#pragma ADDRESS pd1_addr 03e3H /* Port P1 direction register */ +#pragma ADDRESS p2_addr 03e4H /* Port P2 register */ +#pragma ADDRESS p3_addr 03e5H /* Port P3 register */ +#pragma ADDRESS pd2_addr 03e6H /* Port P2 direction register */ +#pragma ADDRESS pd3_addr 03e7H /* Port P3 direction register */ +#pragma ADDRESS p4_addr 03e8H /* Port P4 register */ +#pragma ADDRESS p5_addr 03e9H /* Port P5 register */ +#pragma ADDRESS pd4_addr 03eaH /* Port P4 direction register */ +#pragma ADDRESS pd5_addr 03ebH /* Port P5 direction register */ + +#pragma ADDRESS pur0_addr 03f0H /* Pull-up control register 0 */ +#pragma ADDRESS pur1_addr 03f1H /* Pull-up control register 1 */ + +#pragma ADDRESS pcr_addr 03ffH /* Port control register */ + +/******************************************************* +* declare SFR char * +********************************************************/ +unsigned char da0_addr; /* D/A register 0 */ +#define da0 da0_addr + +unsigned char da1_addr; /* D/A register 1 */ +#define da1 da1_addr + +/******************************************************** +* declare SFR short * +********************************************************/ +/*--------------------------------------------------------------------- + Timer registers ; Read and write to this register in 16-bit units. +-----------------------------------------------------------------------*/ +unsigned short ta11_addr; /* Timer A1-1 register */ +#define ta11 ta11_addr + +unsigned short ta21_addr; /* Timer A2-1 register */ +#define ta21 ta21_addr + +unsigned short ta41_addr; /* Timer A4-1 register */ +#define ta41 ta41_addr + +unsigned short tb3_addr; /* Timer B3 register */ +#define tb3 tb3_addr + +unsigned short tb4_addr; /* Timer B4 register */ +#define tb4 tb4_addr + +unsigned short tb5_addr; /* Timer B5 register */ +#define tb5 tb5_addr + +unsigned short ta0_addr; /* Timer A0 register */ +#define ta0 ta0_addr + +unsigned short ta1_addr; /* Timer A1 register */ +#define ta1 ta1_addr + +unsigned short ta2_addr; /* Timer A2 register */ +#define ta2 ta2_addr + +unsigned short ta3_addr; /* Timer A3 register */ +#define ta3 ta3_addr + +unsigned short ta4_addr; /* Timer A4 register */ +#define ta4 ta4_addr + +unsigned short tb0_addr; /* Timer B0 register */ +#define tb0 tb0_addr + +unsigned short tb1_addr; /* Timer B1 register */ +#define tb1 tb1_addr + +unsigned short tb2_addr; /* Timer B2 register */ +#define tb2 tb2_addr + +/*--------------------------------------------------------------------- + IIO registers ; Read and write to this register in 16-bit units. +-----------------------------------------------------------------------*/ + +/******************************************************** +* group 0 and 1 * +********************************************************/ +#define g0tcrc g0tcrc_addr.word /* Transmit CRC Code Register 0 */ +#define g0tcrcl g0tcrc_addr.byte.low +#define g0tcrch g0tcrc_addr.byte.high + +#define g1tcrc g1tcrc_addr.word /* Transmit CRC Code Register 1 */ +#define g1tcrcl g1tcrc_addr.byte.low +#define g1tcrch g1tcrc_addr.byte.high + +#define g0rcrc g0rcrc_addr.word /* Receive CRC Code Register 0 */ +#define g0rcrcl g0rcrc_addr.byte.low +#define g0rcrch g0rcrc_addr.byte.high + +#define g1rcrc g1rcrc_addr.word /* Receive CRC Code Register 1 */ +#define g1rcrcl g1rcrc_addr.byte.low +#define g1rcrch g1rcrc_addr.byte.high + +/*------------------------------------------------------ + SI/O receive buffer register +------------------------------------------------------*/ + +/*------------------------------------------------------ + SI/O Receive Buffer Register 0 +------------------------------------------------------*/ +#define g0rb g0rb_addr.word +#define g0rbl g0rb_addr.byte.low +#define g0rbh g0rb_addr.byte.high +#define oer_g0rb g0rb_addr.bit.b12 /* Overrun error flag */ + +/*------------------------------------------------------ + SI/O Receive Buffer Register 1 +------------------------------------------------------*/ +#define g1rb g1rb_addr.word +#define g1rbl g1rb_addr.byte.low +#define g1rbh g1rb_addr.byte.high +#define oer_g1rb g1rb_addr.bit.b12 /* Overrun error flag */ +#define fer_g1rb g1rb_addr.bit.b13 /* Framing error flag */ +#define per_g1rb g1rb_addr.bit.b14 /* Parity error flag */ + + +/******************************************************** +* declare SFR bit * +********************************************************/ +struct bit_def { + char b0:1; + char b1:1; + char b2:1; + char b3:1; + char b4:1; + char b5:1; + char b6:1; + char b7:1; +}; +union byte_def{ + struct bit_def bit; + char byte; +}; + +/*------------------------------------------------------ + External Space Wait Control Register 0 +------------------------------------------------------*/ +union byte_def ewcr0_addr; +#define ewcr0 ewcr0_addr.byte + +#define ewcr000 ewcr0_addr.bit.b0 /* (b4-b0) Bus cycle select bit */ +#define ewcr001 ewcr0_addr.bit.b1 +#define ewcr002 ewcr0_addr.bit.b2 +#define ewcr003 ewcr0_addr.bit.b3 +#define ewcr004 ewcr0_addr.bit.b4 + /* (b5) Nothing is assigned */ +#define ewcr006 ewcr0_addr.bit.b6 /* Recovery cycle addition select bit */ + /* (b7) Nothing is assigned */ + +/*------------------------------------------------------ + External Space Wait Control Register 1 +------------------------------------------------------*/ +union byte_def ewcr1_addr; +#define ewcr1 ewcr1_addr.byte + +#define ewcr100 ewcr1_addr.bit.b0 /* (b4-b0) Bus cycle select bit */ +#define ewcr101 ewcr1_addr.bit.b1 +#define ewcr102 ewcr1_addr.bit.b2 +#define ewcr103 ewcr1_addr.bit.b3 +#define ewcr104 ewcr1_addr.bit.b4 + /* (b5) Nothing is assigned */ +#define ewcr106 ewcr1_addr.bit.b6 /* Recovery cycle addition select bit */ + /* (b7) Nothing is assigned */ + +/*------------------------------------------------------ + External Space Wait Control Register 2 +------------------------------------------------------*/ +union byte_def ewcr2_addr; +#define ewcr2 ewcr2_addr.byte + +#define ewcr200 ewcr2_addr.bit.b0 /* (b4-b0) Bus cycle select bit */ +#define ewcr201 ewcr2_addr.bit.b1 +#define ewcr202 ewcr2_addr.bit.b2 +#define ewcr203 ewcr2_addr.bit.b3 +#define ewcr204 ewcr2_addr.bit.b4 + /* (b5) Nothing is assigned */ +#define ewcr206 ewcr2_addr.bit.b6 /* Recovery cycle addition select bit */ + /* (b7) Nothing is assigned */ + +/*------------------------------------------------------ + External Space Wait Control Register 3 +------------------------------------------------------*/ +union byte_def ewcr3_addr; +#define ewcr3 ewcr3_addr.byte + +#define ewcr300 ewcr3_addr.bit.b0 /* (b4-b0) Bus cycle select bit */ +#define ewcr301 ewcr3_addr.bit.b1 +#define ewcr302 ewcr3_addr.bit.b2 +#define ewcr303 ewcr3_addr.bit.b3 +#define ewcr304 ewcr3_addr.bit.b4 + /* (b5) Nothing is assigned */ +#define ewcr306 ewcr3_addr.bit.b6 /* Recovery cycle addition select bit */ + /* (b7) Nothing is assigned */ + +/*------------------------------------------------------ + Processor mode register 0 +------------------------------------------------------*/ +union byte_def pm0_addr; +#define pm0 pm0_addr.byte + +#define pm00 pm0_addr.bit.b0 /* Processor mode bit */ +#define pm01 pm0_addr.bit.b1 /* Processor mode bit */ +#define pm02 pm0_addr.bit.b2 /* R/W mode select bit */ +#define pm03 pm0_addr.bit.b3 /* Software reset bit */ +#define pm04 pm0_addr.bit.b4 /* Multiplexed bus space select bit */ +#define pm05 pm0_addr.bit.b5 /* Multiplexed bus space select bit */ + /* (b6) Reserved bit (Set to 0) */ +#define pm07 pm0_addr.bit.b7 /* BCLK output function select bit */ + +/*------------------------------------------------------ + Processor mode register 1 +------------------------------------------------------*/ +union byte_def pm1_addr; +#define pm1 pm1_addr.byte + +#define pm10 pm1_addr.bit.b0 /* External memory area mode bit */ +#define pm11 pm1_addr.bit.b1 /* External memory area mode bit */ +#define pm12 pm1_addr.bit.b2 /* Internal memory wait bit */ +#define pm13 pm1_addr.bit.b3 /* SFR wait bit */ +#define pm14 pm1_addr.bit.b4 /* ALE pin select bit */ +#define pm15 pm1_addr.bit.b5 /* ALE pin select bit */ + /* (b7-b6) Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + Processor mode register 2 +------------------------------------------------------*/ +union byte_def pm2_addr; +#define pm2 pm2_addr.byte + /* (b0) Reserved bit (Set to 0) */ +#define pm21 pm2_addr.bit.b1 /* System clock protect bit */ +#define pm22 pm2_addr.bit.b2 /* WDT count source protect bit */ + /* (b3) Reserved bit (Set to 0) */ +#define pm24 pm2_addr.bit.b4 /* (b4) CPU clock select bit3 */ +#define pm25 pm2_addr.bit.b5 /* (b5) CAN clock select bit */ +#define pm26 pm2_addr.bit.b6 /* (b7-b6) f2n count source select bit */ +#define pm27 pm2_addr.bit.b7 + +/*------------------------------------------------------ + System clock control register 0 +------------------------------------------------------*/ +union byte_def cm0_addr; +#define cm0 cm0_addr.byte + +#define cm00 cm0_addr.bit.b0 /* Clock output function select bit */ +#define cm01 cm0_addr.bit.b1 /* Clock output function select bit */ +#define cm02 cm0_addr.bit.b2 /* WAIT peripheral function clock stop bit */ +#define cm03 cm0_addr.bit.b3 /* Xcin-Xcout drive capacity select bit */ +#define cm04 cm0_addr.bit.b4 /* Port Xc select bit */ +#define cm05 cm0_addr.bit.b5 /* Main clock stop bit */ +#define cm06 cm0_addr.bit.b6 /* WDT function select bit */ +#define cm07 cm0_addr.bit.b7 /* CPU clock select bit0 */ + +/*------------------------------------------------------ + System clock control register 1 +------------------------------------------------------*/ +union byte_def cm1_addr; +#define cm1 cm1_addr.byte + +#define cm10 cm1_addr.bit.b0 /* All clock stop control bit */ + /* (b4-b1) Reserved bit (Set to 0) */ + /* (b5) Reserved bit (Set to 1) */ + /* (b6) Reserved bit (Set to 0) */ +#define cm17 cm1_addr.bit.b7 /* CPU clock select bit1 */ + +/*------------------------------------------------------ + Oscillation stop detect register +------------------------------------------------------*/ +union byte_def cm2_addr; +#define cm2 cm2_addr.byte + +#define cm20 cm2_addr.bit.b0 /* Oscillation stop detect enable bit */ +#define cm21 cm2_addr.bit.b1 /* CPU clock select bit2 */ +#define cm22 cm2_addr.bit.b2 /* Oscillation stop detect flag */ +#define cm23 cm2_addr.bit.b3 /* Main clock monitor flag */ + /* (b7-b4) Reserved bit (Set to 0) */ + + +/*------------------------------------------------------ + Address match interrupt enable register +------------------------------------------------------*/ +union byte_def aier_addr; +#define aier aier_addr.byte + +#define aier0 aier_addr.bit.b0 /* Address match interrupt 0 enable bit */ +#define aier1 aier_addr.bit.b1 /* Address match interrupt 1 enable bit */ +#define aier2 aier_addr.bit.b2 /* Address match interrupt 2 enable bit */ +#define aier3 aier_addr.bit.b3 /* Address match interrupt 3 enable bit */ +#define aier4 aier_addr.bit.b4 /* Address match interrupt 4 enable bit */ +#define aier5 aier_addr.bit.b5 /* Address match interrupt 5 enable bit */ +#define aier6 aier_addr.bit.b6 /* Address match interrupt 6 enable bit */ +#define aier7 aier_addr.bit.b7 /* Address match interrupt 7 enable bit */ + +/*------------------------------------------------------ + X-Y control register +------------------------------------------------------*/ +union byte_def xyc_addr; +#define xyc xyc_addr.byte + +#define xyc0 xyc_addr.bit.b0 /* Read-mode set bit */ +#define xyc1 xyc_addr.bit.b1 /* Write-mode set bit */ + /* (b7-b2) Nothing is assigned */ + +/*------------------------------------------------------ + Protect register +------------------------------------------------------*/ +union byte_def prcr_addr; +#define prcr prcr_addr.byte + +#define prc0 prcr_addr.bit.b0 /* Protect bit0 */ +#define prc1 prcr_addr.bit.b1 /* Protect bit1 */ +#define prc2 prcr_addr.bit.b2 /* Protect bit2 */ +#define prc3 prcr_addr.bit.b3 /* Protect bit3 */ + /* (b7-b4) Nothing is assigned */ + +/*------------------------------------------------------ + External data bus width control register +------------------------------------------------------*/ +union byte_def ds_addr; +#define ds ds_addr.byte + +#define ds0 ds_addr.bit.b0 /* External space 0 data bus width select bit */ +#define ds1 ds_addr.bit.b1 /* External space 1 data bus width select bit */ +#define ds2 ds_addr.bit.b2 /* External space 2 data bus width select bit */ +#define ds3 ds_addr.bit.b3 /* External space 3 data bus width select bit */ + /* (b7-b4) Nothing is assigned */ + +/*------------------------------------------------------ + Main clock division register +------------------------------------------------------*/ +union byte_def mcd_addr; +#define mcd mcd_addr.byte + +#define mcd0 mcd_addr.bit.b0 /* (b4-b0) Main clock division select bit */ +#define mcd1 mcd_addr.bit.b1 +#define mcd2 mcd_addr.bit.b2 +#define mcd3 mcd_addr.bit.b3 +#define mcd4 mcd_addr.bit.b4 + /* (b7-b5) Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + Count source prescaler register +------------------------------------------------------*/ +union byte_def tcspr_addr; +#define tcspr tcspr_addr.byte + +#define cnt0 tcspr_addr.bit.b0 /* (b3-b0) Divide ratio select bit */ +#define cnt1 tcspr_addr.bit.b1 +#define cnt2 tcspr_addr.bit.b2 +#define cnt3 tcspr_addr.bit.b3 + /* (b6-b4) Reserved bit (Set to 0) */ +#define cst tcspr_addr.bit.b7 /* Operation enable bit */ + +/*------------------------------------------------------ + Exit priority register +------------------------------------------------------*/ +union byte_def rlvl_addr; +#define rlvl rlvl_addr.byte + +#define rlvl0 rlvl_addr.bit.b0 /* (b2-b0) Interrupt priority set bits to exit STOP/WAIT mode */ +#define rlvl1 rlvl_addr.bit.b1 +#define rlvl2 rlvl_addr.bit.b2 +#define fsit rlvl_addr.bit.b3 /* High-speed interrupt set bit */ + /* (b4) Nothing is assigned */ +#define dmaii rlvl_addr.bit.b5 /* DMAC II select bit */ + /* (b7-b6) Nothing is assigned */ + +/*------------------------------------------------------ + External interrupt request cause select register +------------------------------------------------------*/ +union byte_def ifsr_addr; +#define ifsr ifsr_addr.byte + +#define ifsr0 ifsr_addr.bit.b0 /* INT0 interrupt polarity select bit */ +#define ifsr1 ifsr_addr.bit.b1 /* INT1 interrupt polarity select bit */ +#define ifsr2 ifsr_addr.bit.b2 /* INT2 interrupt polarity select bit */ +#define ifsr3 ifsr_addr.bit.b3 /* INT3 interrupt polarity select bit */ +#define ifsr4 ifsr_addr.bit.b4 /* INT4 interrupt polarity select bit */ +#define ifsr5 ifsr_addr.bit.b5 /* INT5 interrupt polarity select bit */ +#define ifsr6 ifsr_addr.bit.b6 /* UART0,3 interrupt cause select bit */ +#define ifsr7 ifsr_addr.bit.b7 /* UART1,4 interrupt cause select bit */ + +/*------------------------------------------------------ + Timer B2 special mode register +------------------------------------------------------*/ +union byte_def tb2sc_addr; +#define tb2sc tb2sc_addr.byte + +#define pwcon tb2sc_addr.bit.b0 /* Timer B2 reload timing switching bit */ + /* (b7-b1) Nothing is assigned */ + +/*------------------------------------------------------ + Watchdog timer start register +------------------------------------------------------*/ +union byte_def wdts_addr; +#define wdts wdts_addr.byte + +/*------------------------------------------------------ + CRC input register +------------------------------------------------------*/ +union byte_def crcin_addr; +#define crcin crcin_addr.byte + +/*------------------------------------------------------ + Watchdog timer control register +------------------------------------------------------*/ +union byte_def wdc_addr; +#define wdc wdc_addr.byte + + /* (b4-b0) High-order bits of the watchdog timer */ +#define wdc5 wdc_addr.bit.b5 /* Cold start/warm start detect flag */ + /* (b6) Reserved bit (Set to 0) */ +#define wdc7 wdc_addr.bit.b7 /* Prescaler select bit */ + +/*------------------------------------------------------ + Voltage detection register 1 +------------------------------------------------------*/ +union byte_def vcr1_addr; +#define vcr1 vcr1_addr.byte + /* (b2-b0) Reserved bit (Set to 0) */ +#define vc13 vcr1_addr.bit.b3 /* Voltage down monitor flag */ + /* (b7-b4) Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + Voltage detection register 2 +------------------------------------------------------*/ +union byte_def vcr2_addr; +#define vcr2 vcr2_addr.byte + /* (b5-b0) Reserved bit (Set to 0) */ +#define vc26 vcr2_addr.bit.b6 /* Reset level monitor bit */ +#define vc27 vcr2_addr.bit.b7 /* Voltage down monitor bit */ + +/*------------------------------------------------------ + Count start flag +------------------------------------------------------*/ +union byte_def tabsr_addr; +#define tabsr tabsr_addr.byte + +#define ta0s tabsr_addr.bit.b0 /* Timer A0 count start flag */ +#define ta1s tabsr_addr.bit.b1 /* Timer A1 count start flag */ +#define ta2s tabsr_addr.bit.b2 /* Timer A2 count start flag */ +#define ta3s tabsr_addr.bit.b3 /* Timer A3 count start flag */ +#define ta4s tabsr_addr.bit.b4 /* Timer A4 count start flag */ +#define tb0s tabsr_addr.bit.b5 /* Timer B0 count start flag */ +#define tb1s tabsr_addr.bit.b6 /* Timer B1 count start flag */ +#define tb2s tabsr_addr.bit.b7 /* Timer B2 count start flag */ + +/*------------------------------------------------------ + Timer B3,4,5 count start flag +------------------------------------------------------*/ +union byte_def tbsr_addr; +#define tbsr tbsr_addr.byte + /* (b4-b0) Nothing is assigned */ +#define tb3s tbsr_addr.bit.b5 /* Timer B3 count start flag */ +#define tb4s tbsr_addr.bit.b6 /* Timer B4 count start flag */ +#define tb5s tbsr_addr.bit.b7 /* Timer B5 count start flag */ + +/*------------------------------------------------------ + Three-phase PWM control register 0 +------------------------------------------------------*/ +union byte_def invc0_addr; +#define invc0 invc0_addr.byte + +#define inv00 invc0_addr.bit.b0 /* Interrupt enable output polarity select bit */ +#define inv01 invc0_addr.bit.b1 /* Interrupt enable output specification bit */ +#define inv02 invc0_addr.bit.b2 /* Mode select bit */ +#define inv03 invc0_addr.bit.b3 /* Output control bit */ +#define inv04 invc0_addr.bit.b4 /* Positive & negative phases concurrent active disable function enable bit */ +#define inv05 invc0_addr.bit.b5 /* Positive & negative phases concurrent active output detect flag */ +#define inv06 invc0_addr.bit.b6 /* Modulation mode select bit */ +#define inv07 invc0_addr.bit.b7 /* Software trigger select bit */ + +/*------------------------------------------------------ + Three-phase PWM control register 1 +------------------------------------------------------*/ +union byte_def invc1_addr; +#define invc1 invc1_addr.byte + +#define inv10 invc1_addr.bit.b0 /* Timer A1,A2 and A4 start trigger select bit */ +#define inv11 invc1_addr.bit.b1 /* Timer A1-1,A2-1,A4-1 control bit */ +#define inv12 invc1_addr.bit.b2 /* Dead time timer count source select bit */ +#define inv13 invc1_addr.bit.b3 /* Carrier wave detect flag */ +#define inv14 invc1_addr.bit.b4 /* Output polarity control bit */ +#define inv15 invc1_addr.bit.b5 /* Dead time disable bit */ +#define inv16 invc1_addr.bit.b6 /* Dead time timer trigger select bit */ + /* (b7) Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + Three-phase output buffer register 0 +------------------------------------------------------*/ +union byte_def idb0_addr; +#define idb0 idb0_addr.byte + +#define du0 idb0_addr.bit.b0 /* U-phase output buffer 0 */ +#define dub0 idb0_addr.bit.b1 /* ~U-phase output buffer 0 */ +#define dv0 idb0_addr.bit.b2 /* V-phase output buffer 0 */ +#define dvb0 idb0_addr.bit.b3 /* ~V-phase output buffer 0 */ +#define dw0 idb0_addr.bit.b4 /* W-phase output buffer 0 */ +#define dwb0 idb0_addr.bit.b5 /* ~W-phase output buffer 0 */ + /* (b7-b6) Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + Three-phase output buffer register 1 +------------------------------------------------------*/ +union byte_def idb1_addr; +#define idb1 idb1_addr.byte + +#define du1 idb1_addr.bit.b0 /* U-phase output buffer 1 */ +#define dub1 idb1_addr.bit.b1 /* ~U-phase output buffer 1 */ +#define dv1 idb1_addr.bit.b2 /* V-phase output buffer 1 */ +#define dvb1 idb1_addr.bit.b3 /* ~V-phase output buffer 1 */ +#define dw1 idb1_addr.bit.b4 /* W-phase output buffer 1 */ +#define dwb1 idb1_addr.bit.b5 /* ~W-phase output buffer 1 */ + /* (b7-b6) Reserved bit (Set to 0) */ + + +/*------------------------------------------------------ + Dead time timer + (1) The MOV instruction should be used to set the DTT register +------------------------------------------------------*/ +union byte_def dtt_addr; +#define dtt dtt_addr.byte + +/*------------------------------------------------------ + Timer B2 interrupt generation frequency set counter + (1) The MOV instruction should be used to the ICTB2 register +------------------------------------------------------*/ +union byte_def ictb2_addr; +#define ictb2 ictb2_addr.byte /* (b3-b0) function */ + /* (b7-b4) Nothing is assigned */ + +/*------------------------------------------------------ + One-shot start flag +------------------------------------------------------*/ +union byte_def onsf_addr; +#define onsf onsf_addr.byte + +#define ta0os onsf_addr.bit.b0 /* Timer A0 one-shot start flag */ +#define ta1os onsf_addr.bit.b1 /* Timer A1 one-shot start flag */ +#define ta2os onsf_addr.bit.b2 /* Timer A2 one-shot start flag */ +#define ta3os onsf_addr.bit.b3 /* Timer A3 one-shot start flag */ +#define ta4os onsf_addr.bit.b4 /* Timer A4 one-shot start flag */ +#define tazie onsf_addr.bit.b5 /* Z-phase input enable bit */ +#define ta0tgl onsf_addr.bit.b6 /* Timer A0 event/trigger select bit */ +#define ta0tgh onsf_addr.bit.b7 /* Timer A0 event/trigger select bit */ + +/*------------------------------------------------------ + Clock prescaler reset flag +------------------------------------------------------*/ +union byte_def cpsrf_addr; +#define cpsrf cpsrf_addr.byte + /* (b6-b0) Nothing is assigned */ +#define cpsr cpsrf_addr.bit.b7 /* Clock prescaler reset flag */ + +/*------------------------------------------------------ + Trigger select register +------------------------------------------------------*/ +union byte_def trgsr_addr; +#define trgsr trgsr_addr.byte + +#define ta1tgl trgsr_addr.bit.b0 /* Timer A1 event/trigger select bit */ +#define ta1tgh trgsr_addr.bit.b1 /* Timer A1 event/trigger select bit */ +#define ta2tgl trgsr_addr.bit.b2 /* Timer A2 event/trigger select bit */ +#define ta2tgh trgsr_addr.bit.b3 /* Timer A2 event/trigger select bit */ +#define ta3tgl trgsr_addr.bit.b4 /* Timer A3 event/trigger select bit */ +#define ta3tgh trgsr_addr.bit.b5 /* Timer A3 event/trigger select bit */ +#define ta4tgl trgsr_addr.bit.b6 /* Timer A4 event/trigger select bit */ +#define ta4tgh trgsr_addr.bit.b7 /* Timer A4 event/trigger select bit */ + +/*------------------------------------------------------ + Up Down Flag + (1) The MOV instruction should be used to set the UDF register +------------------------------------------------------*/ +union byte_def udf_addr; /* Up/down flag */ +#define udf udf_addr.byte + +#define ta0ud udf_addr.bit.b0 /* Timer A0 up/down flag */ +#define ta1ud udf_addr.bit.b1 /* Timer A1 up/down flag */ +#define ta2ud udf_addr.bit.b2 /* Timer A2 up/down flag */ +#define ta3ud udf_addr.bit.b3 /* Timer A3 up/down flag */ +#define ta4ud udf_addr.bit.b4 /* Timer A4 up/down flag */ +#define ta2p udf_addr.bit.b5 /* Timer A2 2-phase pulse signal processing function select bit */ +#define ta3p udf_addr.bit.b6 /* Timer A3 2-phase pulse signal processing function select bit */ +#define ta4p udf_addr.bit.b7 /* Timer A4 2-phase pulse signal processing function select bit */ + +/*------------------------------------------------------ + UARTi transmit/receive control register 1 (i=0,1,2,3,4) +------------------------------------------------------*/ +/*------------------------------------------------------ + u0c1 +------------------------------------------------------*/ +union byte_def u0c1_addr; +#define u0c1 u0c1_addr.byte +#define te_u0c1 u0c1_addr.bit.b0 /* Transmit enable bit */ +#define ti_u0c1 u0c1_addr.bit.b1 /* Transmit buffer empty flag */ +#define re_u0c1 u0c1_addr.bit.b2 /* Receive enable bit */ +#define ri_u0c1 u0c1_addr.bit.b3 /* Receive complete flag */ +#define u0irs_u0c1 u0c1_addr.bit.b4 /* UARTi transmit interrupt cause select bit */ +#define u0rrm_u0c1 u0c1_addr.bit.b5 /* UARTi continuous receive mode enable bit */ +#define u0lch_u0c1 u0c1_addr.bit.b6 /* Data logic select bit */ +#define sclkstpb_u0c1 u0c1_addr.bit.b7 /* Clock divide synchronizing stop bit */ +#define u0ere_u0c1 u0c1_addr.bit.b7 /* Error signal output enable bit */ + +/*------------------------------------------------------ + u1c1 +------------------------------------------------------*/ +union byte_def u1c1_addr; +#define u1c1 u1c1_addr.byte +#define te_u1c1 u1c1_addr.bit.b0 +#define ti_u1c1 u1c1_addr.bit.b1 +#define re_u1c1 u1c1_addr.bit.b2 +#define ri_u1c1 u1c1_addr.bit.b3 +#define u1irs_u1c1 u1c1_addr.bit.b4 +#define u1rrm_u1c1 u1c1_addr.bit.b5 +#define u1lch_u1c1 u1c1_addr.bit.b6 +#define sclkstpb_u1c1 u1c1_addr.bit.b7 +#define u1ere_u1c1 u1c1_addr.bit.b7 + +/*------------------------------------------------------ + u2c1 +------------------------------------------------------*/ +union byte_def u2c1_addr; +#define u2c1 u2c1_addr.byte +#define te_u2c1 u2c1_addr.bit.b0 +#define ti_u2c1 u2c1_addr.bit.b1 +#define re_u2c1 u2c1_addr.bit.b2 +#define ri_u2c1 u2c1_addr.bit.b3 +#define u2irs_u2c1 u2c1_addr.bit.b4 +#define u2rrm_u2c1 u2c1_addr.bit.b5 +#define u2lch_u2c1 u2c1_addr.bit.b6 +#define sclkstpb_u2c1 u2c1_addr.bit.b7 +#define u2ere_u2c1 u2c1_addr.bit.b7 + +/*------------------------------------------------------ + u3c1 +------------------------------------------------------*/ +union byte_def u3c1_addr; +#define u3c1 u3c1_addr.byte +#define te_u3c1 u3c1_addr.bit.b0 +#define ti_u3c1 u3c1_addr.bit.b1 +#define re_u3c1 u3c1_addr.bit.b2 +#define ri_u3c1 u3c1_addr.bit.b3 +#define u3irs_u3c1 u3c1_addr.bit.b4 +#define u3rrm_u3c1 u3c1_addr.bit.b5 +#define u3lch_u3c1 u3c1_addr.bit.b6 +#define sclkstpb_u3c1 u3c1_addr.bit.b7 +#define u3ere_u3c1 u3c1_addr.bit.b7 + +/*------------------------------------------------------ + u4c1 +------------------------------------------------------*/ +union byte_def u4c1_addr; +#define u4c1 u4c1_addr.byte +#define te_u4c1 u4c1_addr.bit.b0 +#define ti_u4c1 u4c1_addr.bit.b1 +#define re_u4c1 u4c1_addr.bit.b2 +#define ri_u4c1 u4c1_addr.bit.b3 +#define u4irs_u4c1 u4c1_addr.bit.b4 +#define u4rrm_u4c1 u4c1_addr.bit.b5 +#define u4lch_u4c1 u4c1_addr.bit.b6 +#define sclkstpb_u4c1 u4c1_addr.bit.b7 +#define u4ere_u4c1 u4c1_addr.bit.b7 + +/*------------------------------------------------------ + A/D0 control register 0 +------------------------------------------------------*/ +union byte_def ad0con0_addr; +#define ad0con0 ad0con0_addr.byte + +#define ch0_ad0con0 ad0con0_addr.bit.b0 /* Analog input pin select bit */ +#define ch1_ad0con0 ad0con0_addr.bit.b1 /* Analog input pin select bit */ +#define ch2_ad0con0 ad0con0_addr.bit.b2 /* Analog input pin select bit */ +#define md0_ad0con0 ad0con0_addr.bit.b3 /* A/D operation mode select bit 0 */ +#define md1_ad0con0 ad0con0_addr.bit.b4 /* A/D operation mode select bit 0 */ +#define trg_ad0con0 ad0con0_addr.bit.b5 /* Trigger select bit */ +#define adst_ad0con0 ad0con0_addr.bit.b6 /* A/D conversion start flag */ +#define cks0_ad0con0 ad0con0_addr.bit.b7 /* Frequency select bit 0 */ + +/*------------------------------------------------------ + A/D0 control register 1 +------------------------------------------------------*/ +union byte_def ad0con1_addr; +#define ad0con1 ad0con1_addr.byte + +#define scan0_ad0con1 ad0con1_addr.bit.b0 /* A/D sweep pin select bit */ +#define scan1_ad0con1 ad0con1_addr.bit.b1 /* A/D sweep pin select bit */ +#define md2_ad0con1 ad0con1_addr.bit.b2 /* A/D operation mode select bit 1 */ +#define bits_ad0con1 ad0con1_addr.bit.b3 /* 8/10-bit mode select bit */ +#define cks1_ad0con1 ad0con1_addr.bit.b4 /* Frequency select bit 1 */ +#define vcut_ad0con1 ad0con1_addr.bit.b5 /* Vref connection bit */ +#define opa0_ad0con1 ad0con1_addr.bit.b6 /* External op-amp connection mode bit */ +#define opa1_ad0con1 ad0con1_addr.bit.b7 /* External op-amp connection mode bit */ + +/*------------------------------------------------------ + A/D0 control register 2 +------------------------------------------------------*/ +union byte_def ad0con2_addr; +#define ad0con2 ad0con2_addr.byte + +#define smp_ad0con2 ad0con2_addr.bit.b0 /* A/D conversion method select bit */ +#define aps0_ad0con2 ad0con2_addr.bit.b1 /* Analog input port select bit */ +#define aps1_ad0con2 ad0con2_addr.bit.b2 /* Analog input port select bit */ + /* (b4-b3) Nothing is assigned */ +#define trg0_ad0con2 ad0con2_addr.bit.b5 /* External trigger request cause select bit */ + /* (b7-b6) Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + A/D0 Control Register 3 +------------------------------------------------------*/ +union byte_def ad0con3_addr; +#define ad0con3 ad0con3_addr.byte + +#define dus_ad0con3 ad0con3_addr.bit.b0 /* DMAC operation select bit */ +#define mss_ad0con3 ad0con3_addr.bit.b1 /* Multi-port sweep mode select bit */ +#define cks2_ad0con3 ad0con3_addr.bit.b2 /* Frequency select bit */ +#define msf0_ad0con3 ad0con3_addr.bit.b3 /* Multi-port sweep status flag */ +#define msf1_ad0con3 ad0con3_addr.bit.b4 /* Multi-port sweep status flag */ + /* (b7-b5):Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + D/A control register +------------------------------------------------------*/ +union byte_def dacon_addr; +#define dacon dacon_addr.byte + +#define da0e dacon_addr.bit.b0 /* D/A0 output enable bit */ +#define da1e dacon_addr.bit.b1 /* D/A1 output enable bit */ + /* (b7-b2) Nothing is assigned */ + +/*------------------------------------------------------ + SI/O Communication Mode Register 0 +------------------------------------------------------*/ +union byte_def g0mr_addr; +#define g0mr g0mr_addr.byte + +#define gmd0_g0mr g0mr_addr.bit.b0 /* (b1-b0) Communication mode select bit */ +#define gmd1_g0mr g0mr_addr.bit.b1 +#define ckdir_g0mr g0mr_addr.bit.b2 /* Internal/external clock select bit */ + /* (b5-b3) Reserved bit (Set to 0) */ +#define uform_g0mr g0mr_addr.bit.b6 /* Transfer direction select bit */ +#define irs_g0mr g0mr_addr.bit.b7 /* Transmit interrupt cause select bit */ + +/*------------------------------------------------------ + SI/O Communication Control Register 0 +------------------------------------------------------*/ +union byte_def g0cr_addr; +#define g0cr g0cr_addr.byte + +#define ti_g0cr g0cr_addr.bit.b0 /* Transmit buffer empty flag */ +#define txept_g0cr g0cr_addr.bit.b1 /* Transmit register empty flag */ +#define ri_g0cr g0cr_addr.bit.b2 /* Receive complete flag */ + /* (b3) Nothing is assigned */ +#define te_g0cr g0cr_addr.bit.b4 /* Transmit enable bit */ +#define re_g0cr g0cr_addr.bit.b5 /* Receive enable bit */ +#define ipol_g0cr g0cr_addr.bit.b6 /* ISRxD input polarity switch bit */ +#define opol_g0cr g0cr_addr.bit.b7 /* ISTxD output polarity switch bit */ + + +/*------------------------------------------------------ + SI/O Expansion Mode Register 0 +------------------------------------------------------*/ +union byte_def g0emr_addr; +#define g0emr g0emr_addr.byte + /* (b0) Reserved bit (Set to 0) */ +#define crcv_g0emr g0emr_addr.bit.b1 /* CRC default value select bit */ +#define acrc_g0emr g0emr_addr.bit.b2 /* CRC reset select bit */ +#define bsint_g0emr g0emr_addr.bit.b3 /* Bit stuffing error interrupt select bit */ +#define rxsl_g0emr g0emr_addr.bit.b4 /* Receive source switch bit */ +#define txsl_g0emr g0emr_addr.bit.b5 /* Transmit source switch bit */ +#define crc0_g0emr g0emr_addr.bit.b6 /* CRC generation polynomial select bit */ +#define crc1_g0emr g0emr_addr.bit.b7 /* CRC generation polynomial select bit */ + +/*------------------------------------------------------ + SI/O Expansion Transmit Control Register 0 +------------------------------------------------------*/ +union byte_def g0etc_addr; +#define g0etc g0etc_addr.byte + /* (b2-b0) Reserved bit (Set to 0) */ + /* (b3) Reserved bit (Set to 0) */ +#define tcrce_g0etc g0etc_addr.bit.b4 /* Transmit CRC enable bit */ + /* (b5) Reserved bit (Set to 0) */ +#define tbsf0_g0etc g0etc_addr.bit.b6 /* Transmit bit stuffing "1" insert select bit */ +#define tbsf1_g0etc g0etc_addr.bit.b7 /* Transmit bit stuffing "0" insert select bit */ + +/*------------------------------------------------------ + SI/O Expansion Receive Control Register 0 +------------------------------------------------------*/ +union byte_def g0erc_addr; +#define g0erc g0erc_addr.byte +#define cmp0e_g0erc g0erc_addr.bit.b0 /* Data compare function 0 select bit */ +#define cmp1e_g0erc g0erc_addr.bit.b1 /* Data compare function 1 select bit */ +#define cmp2e_g0erc g0erc_addr.bit.b2 /* Data compare function 2 select bit */ +#define cmp3e_g0erc g0erc_addr.bit.b3 /* Data compare function 3 select bit */ +#define rcrce_g0erc g0erc_addr.bit.b4 /* Receive CRC enable bit */ +#define rshte_g0erc g0erc_addr.bit.b5 /* Receive shift operation enable bit */ +#define rbsf0_g0erc g0erc_addr.bit.b6 /* Receive bit stuffing "1" delete select bit */ +#define rbsf1_g0erc g0erc_addr.bit.b7 /* Receive bit stuffing "0" delete select bit */ + +/*------------------------------------------------------ + SI/O Special Communication Interrupt Detect Register 0 +------------------------------------------------------*/ +union byte_def g0irf_addr; +#define g0irf g0irf_addr.byte + /* (b1-b0) Reserved bit (Set to 0) */ +#define bserr_g0irf g0irf_addr.bit.b2 /* Bit stuffing error detect flag */ + /* (b3) Reserved bit (Set to 0) */ +#define irf0_g0irf g0irf_addr.bit.b4 /* Interrupt cause determination flag 0 */ +#define irf1_g0irf g0irf_addr.bit.b5 /* Interrupt cause determination flag 1 */ +#define irf2_g0irf g0irf_addr.bit.b6 /* Interrupt cause determination flag 2 */ +#define irf3_g0irf g0irf_addr.bit.b7 /* Interrupt cause determination flag 3 */ + +/*------------------------------------------------------ + Receive Data Register 0 +------------------------------------------------------*/ +union byte_def g0dr_addr; +#define g0dr g0dr_addr.byte + +/*------------------------------------------------------ + Transmit Buffer Register 0 +------------------------------------------------------*/ +union byte_def g0tb_addr; +#define g0tb g0tb_addr.byte + +/*------------------------------------------------------ + Data Compare Register 00 +------------------------------------------------------*/ +union byte_def g0cmp0_addr; +#define g0cmp0 g0cmp0_addr.byte + +/*------------------------------------------------------ + Data Compare Register 01 +------------------------------------------------------*/ +union byte_def g0cmp1_addr; +#define g0cmp1 g0cmp1_addr.byte + +/*------------------------------------------------------ + Data Compare Register 02 +------------------------------------------------------*/ +union byte_def g0cmp2_addr; +#define g0cmp2 g0cmp2_addr.byte + +/*------------------------------------------------------ + Data Compare Register 03 +------------------------------------------------------*/ +union byte_def g0cmp3_addr; +#define g0cmp3 g0cmp3_addr.byte + +/*------------------------------------------------------ + Data Mask Register 00 +------------------------------------------------------*/ +union byte_def g0msk0_addr; +#define g0msk0 g0msk0_addr.byte + +/*------------------------------------------------------ + Data Mask Register 01 +------------------------------------------------------*/ +union byte_def g0msk1_addr; +#define g0msk1 g0msk1_addr.byte + +/*------------------------------------------------------ + Communication Clock Select Register +------------------------------------------------------*/ +union byte_def ccs_addr; +#define ccs ccs_addr.byte + +#define ccs0 ccs_addr.bit.b0 /* Communication unit 0 clock select bit */ +#define ccs1 ccs_addr.bit.b1 /* Communication unit 0 clock select bit */ +#define ccs2 ccs_addr.bit.b2 /* Communication unit 1 clock select bit */ +#define ccs3 ccs_addr.bit.b3 /* Communication unit 1 clock select bit */ + /* (b7-b4) Nothing is assigned */ + +/*------------------------------------------------------ + Transmit Output Register 0 +------------------------------------------------------*/ +union byte_def g0to_addr; +#define g0to g0to_addr.byte + +/*------------------------------------------------------ + Receive Input Register 0 +------------------------------------------------------*/ +union byte_def g0ri_addr; +#define g0ri g0ri_addr.byte + +/*------------------------------------------------------ + SI/O Communication Mode Register 1 +------------------------------------------------------*/ +union byte_def g1mr_addr; +#define g1mr g1mr_addr.byte +#define gmd0_g1mr g1mr_addr.bit.b0 /* (b1-b0) Communication mode select bit */ +#define gmd1_g1mr g1mr_addr.bit.b1 +#define ckdir_g1mr g1mr_addr.bit.b2 /* Internal/external clock select bit */ +#define stps_g1mr g1mr_addr.bit.b3 /* Stop bit length select bit */ +#define pry_g1mr g1mr_addr.bit.b4 /* Odd/Even parity select bit */ +#define prye_g1mr g1mr_addr.bit.b5 /* Parity enable bit */ +#define uform_g1mr g1mr_addr.bit.b6 /* Transfer direction select bit */ +#define irs_g1mr g1mr_addr.bit.b7 /* Transmit interrupt cause select bit */ + +/*------------------------------------------------------ + SI/O Communication Control Register 1 +------------------------------------------------------*/ +union byte_def g1cr_addr; +#define g1cr g1cr_addr.byte +#define ti_g1cr g1cr_addr.bit.b0 /* Transmit buffer empty flag */ +#define txept_g1cr g1cr_addr.bit.b1 /* Transmit register empty flag */ +#define ri_g1cr g1cr_addr.bit.b2 /* Receive complete flag */ + /* (b3) Nothing is assigned */ +#define te_g1cr g1cr_addr.bit.b4 /* Transmit enable bit */ +#define re_g1cr g1cr_addr.bit.b5 /* Receive enable bit */ +#define ipol_g1cr g1cr_addr.bit.b6 /* ISRxD input polarity switch bit */ +#define opol_g1cr g1cr_addr.bit.b7 /* ISTxD output polarity switch bit */ + +/*------------------------------------------------------ + SI/O Expansion Mode Register 1 +------------------------------------------------------*/ +union byte_def g1emr_addr; +#define g1emr g1emr_addr.byte +#define smode_g1emr g1emr_addr.bit.b0 /* Synchronouse mode select bit */ +#define crcv_g1emr g1emr_addr.bit.b1 /* CRC initial value select bit */ +#define acrc_g1emr g1emr_addr.bit.b2 /* CRC initialization select bit */ +#define bsint_g1emr g1emr_addr.bit.b3 /* Bit stuffing error interrupt select bit */ +#define rxsl_g1emr g1emr_addr.bit.b4 /* Receive source switch bit */ +#define txsl_g1emr g1emr_addr.bit.b5 /* Transmit source switch bit */ +#define crc0_g1emr g1emr_addr.bit.b6 /* CRC generation polynomial select bit */ +#define crc1_g1emr g1emr_addr.bit.b7 /* CRC generation polynomial select bit */ + +/*------------------------------------------------------ + SI/O Expansion Transmit Control Register 1 +------------------------------------------------------*/ +union byte_def g1etc_addr; +#define g1etc g1etc_addr.byte + /* (b2-b0) Reserved bit (Set to 0) */ +#define sof_g1etc g1etc_addr.bit.b3 /* SOF transmit request bit */ +#define tcrce_g1etc g1etc_addr.bit.b4 /* Transmit CRC enable bit */ +#define abte_g1etc g1etc_addr.bit.b5 /* Arbitration enable bit */ +#define tbsf0_g1etc g1etc_addr.bit.b6 /* Transmit bit stuffing "1" insert select bit */ +#define tbsf1_g1etc g1etc_addr.bit.b7 /* Transmit bit stuffing "0" insert select bit */ + +/*------------------------------------------------------ + SI/O Expansion Receive Control Register 1 +------------------------------------------------------*/ +union byte_def g1erc_addr; +#define g1erc g1erc_addr.byte +#define cmp0e_g1erc g1erc_addr.bit.b0 /* Data compare function 0 select bit */ +#define cmp1e_g1erc g1erc_addr.bit.b1 /* Data compare function 1 select bit */ +#define cmp2e_g1erc g1erc_addr.bit.b2 /* Data compare function 2 select bit */ +#define cmp3e_g1erc g1erc_addr.bit.b3 /* Data compare function 3 select bit */ +#define rcrce_g1erc g1erc_addr.bit.b4 /* Receive CRC enable bit */ +#define rshte_g1erc g1erc_addr.bit.b5 /* Receive shift operation enable bit */ +#define rbsf0_g1erc g1erc_addr.bit.b6 /* Receive bit stuffing "1" delete select bit */ +#define rbsf1_g1erc g1erc_addr.bit.b7 /* Receive bit stuffing "0" delete select bit */ + +/*------------------------------------------------------ + SI/O Special Communication Interrupt Detect Register 1 +------------------------------------------------------*/ +union byte_def g1irf_addr; +#define g1irf g1irf_addr.byte + /* (b1-b0) Reserved bit (Set to 0) */ +#define bserr_g1irf g1irf_addr.bit.b2 /* Bit stuffing error detect flag */ +#define abt_g1irf g1irf_addr.bit.b3 /* Arbitration lost detect flag */ +#define irf0_g1irf g1irf_addr.bit.b4 /* Interrupt cause determination flag 0 */ +#define irf1_g1irf g1irf_addr.bit.b5 /* Interrupt cause determination flag 1 */ +#define irf2_g1irf g1irf_addr.bit.b6 /* Interrupt cause determination flag 2 */ +#define irf3_g1irf g1irf_addr.bit.b7 /* Interrupt cause determination flag 3 */ + +/*------------------------------------------------------ + Receive Data Register 1 +------------------------------------------------------*/ +union byte_def g1dr_addr; +#define g1dr g1dr_addr.byte + + +/*------------------------------------------------------ + Transmit Buffer Register 1 +------------------------------------------------------*/ +union byte_def g1tb_addr; +#define g1tb g1tb_addr.byte + +/*------------------------------------------------------ + Data Compare Register 10 +------------------------------------------------------*/ +union byte_def g1cmp0_addr; +#define g1cmp0 g1cmp0_addr.byte + +/*------------------------------------------------------ + Data Compare Register 11 +------------------------------------------------------*/ +union byte_def g1cmp1_addr; +#define g1cmp1 g1cmp1_addr.byte + +/*------------------------------------------------------ + Data Compare Register 12 +------------------------------------------------------*/ +union byte_def g1cmp2_addr; +#define g1cmp2 g1cmp2_addr.byte + +/*------------------------------------------------------ + Data Compare Register 13 +------------------------------------------------------*/ +union byte_def g1cmp3_addr; +#define g1cmp3 g1cmp3_addr.byte + +/*------------------------------------------------------ + Data Mask Register 10 +------------------------------------------------------*/ +union byte_def g1msk0_addr; +#define g1msk0 g1msk0_addr.byte + +/*------------------------------------------------------ + Data Mask Register 11 +------------------------------------------------------*/ +union byte_def g1msk1_addr; +#define g1msk1 g1msk1_addr.byte + +/*------------------------------------------------------ + Transmit Output Register 1 +------------------------------------------------------*/ +union byte_def g1to_addr; +#define g1to g1to_addr.byte + +/*------------------------------------------------------ + Receive Input Register 0 +------------------------------------------------------*/ +union byte_def g1ri_addr; +#define g1ri g1ri_addr.byte + + +/*------------------------------------------------------ + PLL Control Register 0 +------------------------------------------------------*/ +#define plc plc_addr.word + +union byte_def plc0_addr; +#define plc0 plc0_addr.byte + +#define plc00 plc0_addr.bit.b0 /* (b2-b0) Programmable counter select bit */ +#define plc01 plc0_addr.bit.b1 +#define plc02 plc0_addr.bit.b2 + /* (b3) Reserved bit (Set to 0) */ + /* (b4) Reserved bit (Set to 1) */ + /* (b5) Reserved bit (Set to 0) */ + /* (b6) Reserved bit (Set to 1) */ +#define plc07 plc0_addr.bit.b7 /* Operation enable bit */ + +/*------------------------------------------------------ + PLL Control Register 1 +------------------------------------------------------*/ +union byte_def plc1_addr; +#define plc1 plc1_addr.byte + /* (b0) Reserved bit (Set to 0) */ + /* (b1) Reserved bit (Set to 1) */ +#define plc12 plc1_addr.bit.b2 /* PLL clock division switch bit */ + /* (b3) Reserved bit (Set to 0) */ + /* (b4) Reserved bit (Set to 0) */ + /* (b7-b5) Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + Port P0 +------------------------------------------------------*/ +union byte_def p0_addr; +#define p0 p0_addr.byte + +#define p0_0 p0_addr.bit.b0 /* Port P0 bit0 */ +#define p0_1 p0_addr.bit.b1 /* Port P0 bit1 */ +#define p0_2 p0_addr.bit.b2 /* Port P0 bit2 */ +#define p0_3 p0_addr.bit.b3 /* Port P0 bit3 */ +#define p0_4 p0_addr.bit.b4 /* Port P0 bit4 */ +#define p0_5 p0_addr.bit.b5 /* Port P0 bit5 */ +#define p0_6 p0_addr.bit.b6 /* Port P0 bit6 */ +#define p0_7 p0_addr.bit.b7 /* Port P0 bit7 */ + +/*------------------------------------------------------ + Port P0 direction register +------------------------------------------------------*/ +union byte_def pd0_addr; +#define pd0 pd0_addr.byte + +#define pd0_0 pd0_addr.bit.b0 /* P0 direction register bit0 */ +#define pd0_1 pd0_addr.bit.b1 /* P0 direction register bit1 */ +#define pd0_2 pd0_addr.bit.b2 /* P0 direction register bit2 */ +#define pd0_3 pd0_addr.bit.b3 /* P0 direction register bit3 */ +#define pd0_4 pd0_addr.bit.b4 /* P0 direction register bit4 */ +#define pd0_5 pd0_addr.bit.b5 /* P0 direction register bit5 */ +#define pd0_6 pd0_addr.bit.b6 /* P0 direction register bit6 */ +#define pd0_7 pd0_addr.bit.b7 /* P0 direction register bit7 */ + +/*------------------------------------------------------ + Port P1 +------------------------------------------------------*/ +union byte_def p1_addr; +#define p1 p1_addr.byte + +#define p1_0 p1_addr.bit.b0 /* Port P1 bit0 */ +#define p1_1 p1_addr.bit.b1 /* Port P1 bit1 */ +#define p1_2 p1_addr.bit.b2 /* Port P1 bit2 */ +#define p1_3 p1_addr.bit.b3 /* Port P1 bit3 */ +#define p1_4 p1_addr.bit.b4 /* Port P1 bit4 */ +#define p1_5 p1_addr.bit.b5 /* Port P1 bit5 */ +#define p1_6 p1_addr.bit.b6 /* Port P1 bit6 */ +#define p1_7 p1_addr.bit.b7 /* Port P1 bit7 */ + +/*------------------------------------------------------ + Port P1 direction register +------------------------------------------------------*/ +union byte_def pd1_addr; +#define pd1 pd1_addr.byte + +#define pd1_0 pd1_addr.bit.b0 /* P1 direction register bit0 */ +#define pd1_1 pd1_addr.bit.b1 /* P1 direction register bit1 */ +#define pd1_2 pd1_addr.bit.b2 /* P1 direction register bit2 */ +#define pd1_3 pd1_addr.bit.b3 /* P1 direction register bit3 */ +#define pd1_4 pd1_addr.bit.b4 /* P1 direction register bit4 */ +#define pd1_5 pd1_addr.bit.b5 /* P1 direction register bit5 */ +#define pd1_6 pd1_addr.bit.b6 /* P1 direction register bit6 */ +#define pd1_7 pd1_addr.bit.b7 /* P1 direction register bit7 */ + +/*------------------------------------------------------ + Port P2 +------------------------------------------------------*/ +union byte_def p2_addr; +#define p2 p2_addr.byte + +#define p2_0 p2_addr.bit.b0 /* Port P2 bit0 */ +#define p2_1 p2_addr.bit.b1 /* Port P2 bit1 */ +#define p2_2 p2_addr.bit.b2 /* Port P2 bit2 */ +#define p2_3 p2_addr.bit.b3 /* Port P2 bit3 */ +#define p2_4 p2_addr.bit.b4 /* Port P2 bit4 */ +#define p2_5 p2_addr.bit.b5 /* Port P2 bit5 */ +#define p2_6 p2_addr.bit.b6 /* Port P2 bit6 */ +#define p2_7 p2_addr.bit.b7 /* Port P2 bit7 */ + +/*------------------------------------------------------ + Port P2 direction register +------------------------------------------------------*/ +union byte_def pd2_addr; +#define pd2 pd2_addr.byte + +#define pd2_0 pd2_addr.bit.b0 /* P2 direction register bit0 */ +#define pd2_1 pd2_addr.bit.b1 /* P2 direction register bit1 */ +#define pd2_2 pd2_addr.bit.b2 /* P2 direction register bit2 */ +#define pd2_3 pd2_addr.bit.b3 /* P2 direction register bit3 */ +#define pd2_4 pd2_addr.bit.b4 /* P2 direction register bit4 */ +#define pd2_5 pd2_addr.bit.b5 /* P2 direction register bit5 */ +#define pd2_6 pd2_addr.bit.b6 /* P2 direction register bit6 */ +#define pd2_7 pd2_addr.bit.b7 /* P2 direction register bit7 */ + +/*------------------------------------------------------ + Port P3 +------------------------------------------------------*/ +union byte_def p3_addr; +#define p3 p3_addr.byte + +#define p3_0 p3_addr.bit.b0 /* Port P3 bit0 */ +#define p3_1 p3_addr.bit.b1 /* Port P3 bit1 */ +#define p3_2 p3_addr.bit.b2 /* Port P3 bit2 */ +#define p3_3 p3_addr.bit.b3 /* Port P3 bit3 */ +#define p3_4 p3_addr.bit.b4 /* Port P3 bit4 */ +#define p3_5 p3_addr.bit.b5 /* Port P3 bit5 */ +#define p3_6 p3_addr.bit.b6 /* Port P3 bit6 */ +#define p3_7 p3_addr.bit.b7 /* Port P3 bit7 */ + +/*------------------------------------------------------ + Port P3 direction register +------------------------------------------------------*/ +union byte_def pd3_addr; +#define pd3 pd3_addr.byte + +#define pd3_0 pd3_addr.bit.b0 /* P3 direction register bit0 */ +#define pd3_1 pd3_addr.bit.b1 /* P3 direction register bit1 */ +#define pd3_2 pd3_addr.bit.b2 /* P3 direction register bit2 */ +#define pd3_3 pd3_addr.bit.b3 /* P3 direction register bit3 */ +#define pd3_4 pd3_addr.bit.b4 /* P3 direction register bit4 */ +#define pd3_5 pd3_addr.bit.b5 /* P3 direction register bit5 */ +#define pd3_6 pd3_addr.bit.b6 /* P3 direction register bit6 */ +#define pd3_7 pd3_addr.bit.b7 /* P3 direction register bit7 */ + +/*------------------------------------------------------ + Port P4 +------------------------------------------------------*/ +union byte_def p4_addr; +#define p4 p4_addr.byte + +#define p4_0 p4_addr.bit.b0 /* Port P4 bit0 */ +#define p4_1 p4_addr.bit.b1 /* Port P4 bit1 */ +#define p4_2 p4_addr.bit.b2 /* Port P4 bit2 */ +#define p4_3 p4_addr.bit.b3 /* Port P4 bit3 */ +#define p4_4 p4_addr.bit.b4 /* Port P4 bit4 */ +#define p4_5 p4_addr.bit.b5 /* Port P4 bit5 */ +#define p4_6 p4_addr.bit.b6 /* Port P4 bit6 */ +#define p4_7 p4_addr.bit.b7 /* Port P4 bit7 */ + +/*------------------------------------------------------ + Port P4 direction register +------------------------------------------------------*/ +union byte_def pd4_addr; +#define pd4 pd4_addr.byte + +#define pd4_0 pd4_addr.bit.b0 /* P4 direction register bit0 */ +#define pd4_1 pd4_addr.bit.b1 /* P4 direction register bit1 */ +#define pd4_2 pd4_addr.bit.b2 /* P4 direction register bit2 */ +#define pd4_3 pd4_addr.bit.b3 /* P4 direction register bit3 */ +#define pd4_4 pd4_addr.bit.b4 /* P4 direction register bit4 */ +#define pd4_5 pd4_addr.bit.b5 /* P4 direction register bit5 */ +#define pd4_6 pd4_addr.bit.b6 /* P4 direction register bit6 */ +#define pd4_7 pd4_addr.bit.b7 /* P4 direction register bit7 */ + +/*------------------------------------------------------ + Port P5 +------------------------------------------------------*/ +union byte_def p5_addr; +#define p5 p5_addr.byte + +#define p5_0 p5_addr.bit.b0 /* Port P5 bit0 */ +#define p5_1 p5_addr.bit.b1 /* Port P5 bit1 */ +#define p5_2 p5_addr.bit.b2 /* Port P5 bit2 */ +#define p5_3 p5_addr.bit.b3 /* Port P5 bit3 */ +#define p5_4 p5_addr.bit.b4 /* Port P5 bit4 */ +#define p5_5 p5_addr.bit.b5 /* Port P5 bit5 */ +#define p5_6 p5_addr.bit.b6 /* Port P5 bit6 */ +#define p5_7 p5_addr.bit.b7 /* Port P5 bit7 */ + +/*------------------------------------------------------ + Port P5 direction register +------------------------------------------------------*/ +union byte_def pd5_addr; +#define pd5 pd5_addr.byte + +#define pd5_0 pd5_addr.bit.b0 /* P5 direction register bit0 */ +#define pd5_1 pd5_addr.bit.b1 /* P5 direction register bit1 */ +#define pd5_2 pd5_addr.bit.b2 /* P5 direction register bit2 */ +#define pd5_3 pd5_addr.bit.b3 /* P5 direction register bit3 */ +#define pd5_4 pd5_addr.bit.b4 /* P5 direction register bit4 */ +#define pd5_5 pd5_addr.bit.b5 /* P5 direction register bit5 */ +#define pd5_6 pd5_addr.bit.b6 /* P5 direction register bit6 */ +#define pd5_7 pd5_addr.bit.b7 /* P5 direction register bit7 */ + +/*------------------------------------------------------ + Port P6 +------------------------------------------------------*/ +union byte_def p6_addr; +#define p6 p6_addr.byte + +#define p6_0 p6_addr.bit.b0 /* Port P6 bit0 */ +#define p6_1 p6_addr.bit.b1 /* Port P6 bit1 */ +#define p6_2 p6_addr.bit.b2 /* Port P6 bit2 */ +#define p6_3 p6_addr.bit.b3 /* Port P6 bit3 */ +#define p6_4 p6_addr.bit.b4 /* Port P6 bit4 */ +#define p6_5 p6_addr.bit.b5 /* Port P6 bit5 */ +#define p6_6 p6_addr.bit.b6 /* Port P6 bit6 */ +#define p6_7 p6_addr.bit.b7 /* Port P6 bit7 */ + +/*------------------------------------------------------ + Port P6 direction register +------------------------------------------------------*/ +union byte_def pd6_addr; +#define pd6 pd6_addr.byte + +#define pd6_0 pd6_addr.bit.b0 /* P6 direction register bit0 */ +#define pd6_1 pd6_addr.bit.b1 /* P6 direction register bit1 */ +#define pd6_2 pd6_addr.bit.b2 /* P6 direction register bit2 */ +#define pd6_3 pd6_addr.bit.b3 /* P6 direction register bit3 */ +#define pd6_4 pd6_addr.bit.b4 /* P6 direction register bit4 */ +#define pd6_5 pd6_addr.bit.b5 /* P6 direction register bit5 */ +#define pd6_6 pd6_addr.bit.b6 /* P6 direction register bit6 */ +#define pd6_7 pd6_addr.bit.b7 /* P6 direction register bit7 */ + +/*------------------------------------------------------ + Port P7 +------------------------------------------------------*/ +union byte_def p7_addr; +#define p7 p7_addr.byte + +#define p7_0 p7_addr.bit.b0 /* Port P7 bit0 */ +#define p7_1 p7_addr.bit.b1 /* Port P7 bit1 */ +#define p7_2 p7_addr.bit.b2 /* Port P7 bit2 */ +#define p7_3 p7_addr.bit.b3 /* Port P7 bit3 */ +#define p7_4 p7_addr.bit.b4 /* Port P7 bit4 */ +#define p7_5 p7_addr.bit.b5 /* Port P7 bit5 */ +#define p7_6 p7_addr.bit.b6 /* Port P7 bit6 */ +#define p7_7 p7_addr.bit.b7 /* Port P7 bit7 */ + +/*------------------------------------------------------ + Port P7 direction register +------------------------------------------------------*/ +union byte_def pd7_addr; +#define pd7 pd7_addr.byte + +#define pd7_0 pd7_addr.bit.b0 /* P7 direction register bit0 */ +#define pd7_1 pd7_addr.bit.b1 /* P7 direction register bit1 */ +#define pd7_2 pd7_addr.bit.b2 /* P7 direction register bit2 */ +#define pd7_3 pd7_addr.bit.b3 /* P7 direction register bit3 */ +#define pd7_4 pd7_addr.bit.b4 /* P7 direction register bit4 */ +#define pd7_5 pd7_addr.bit.b5 /* P7 direction register bit5 */ +#define pd7_6 pd7_addr.bit.b6 /* P7 direction register bit6 */ +#define pd7_7 pd7_addr.bit.b7 /* P7 direction register bit7 */ + +/*------------------------------------------------------ + Port P8 +------------------------------------------------------*/ +union byte_def p8_addr; +#define p8 p8_addr.byte + +#define p8_0 p8_addr.bit.b0 /* Port P8 bit0 */ +#define p8_1 p8_addr.bit.b1 /* Port P8 bit1 */ +#define p8_2 p8_addr.bit.b2 /* Port P8 bit2 */ +#define p8_3 p8_addr.bit.b3 /* Port P8 bit3 */ +#define p8_4 p8_addr.bit.b4 /* Port P8 bit4 */ +#define p8_5 p8_addr.bit.b5 /* Port P8 bit5 */ +#define p8_6 p8_addr.bit.b6 /* Port P8 bit6 */ +#define p8_7 p8_addr.bit.b7 /* Port P8 bit7 */ + +/*------------------------------------------------------ + Port P8 direction register +------------------------------------------------------*/ +union byte_def pd8_addr; +#define pd8 pd8_addr.byte + +#define pd8_0 pd8_addr.bit.b0 /* P8 direction register bit0 */ +#define pd8_1 pd8_addr.bit.b1 /* P8 direction register bit1 */ +#define pd8_2 pd8_addr.bit.b2 /* P8 direction register bit2 */ +#define pd8_3 pd8_addr.bit.b3 /* P8 direction register bit3 */ +#define pd8_4 pd8_addr.bit.b4 /* P8 direction register bit4 */ + /* (b5) Nothing is assigned */ +#define pd8_6 pd8_addr.bit.b6 /* P8 direction register bit6 */ +#define pd8_7 pd8_addr.bit.b7 /* P8 direction register bit7 */ + +/*------------------------------------------------------ + Port P9 +------------------------------------------------------*/ +union byte_def p9_addr; +#define p9 p9_addr.byte + +#define p9_0 p9_addr.bit.b0 /* Port P9 bit0 */ +#define p9_1 p9_addr.bit.b1 /* Port P9 bit1 */ +#define p9_2 p9_addr.bit.b2 /* Port P9 bit2 */ +#define p9_3 p9_addr.bit.b3 /* Port P9 bit3 */ +#define p9_4 p9_addr.bit.b4 /* Port P9 bit4 */ +#define p9_5 p9_addr.bit.b5 /* Port P9 bit5 */ +#define p9_6 p9_addr.bit.b6 /* Port P9 bit6 */ +#define p9_7 p9_addr.bit.b7 /* Port P9 bit7 */ + +/*------------------------------------------------------ + Port P9 direction register +------------------------------------------------------*/ +union byte_def pd9_addr; +#define pd9 pd9_addr.byte + +#define pd9_0 pd9_addr.bit.b0 /* P9 direction register bit0 */ +#define pd9_1 pd9_addr.bit.b1 /* P9 direction register bit1 */ +#define pd9_2 pd9_addr.bit.b2 /* P9 direction register bit2 */ +#define pd9_3 pd9_addr.bit.b3 /* P9 direction register bit3 */ +#define pd9_4 pd9_addr.bit.b4 /* P9 direction register bit4 */ +#define pd9_5 pd9_addr.bit.b5 /* P9 direction register bit5 */ +#define pd9_6 pd9_addr.bit.b6 /* P9 direction register bit6 */ +#define pd9_7 pd9_addr.bit.b7 /* P9 direction register bit7 */ + +/*------------------------------------------------------ + Port P10 +------------------------------------------------------*/ +union byte_def p10_addr; +#define p10 p10_addr.byte + +#define p10_0 p10_addr.bit.b0 /* Port P10 bit0 */ +#define p10_1 p10_addr.bit.b1 /* Port P10 bit1 */ +#define p10_2 p10_addr.bit.b2 /* Port P10 bit2 */ +#define p10_3 p10_addr.bit.b3 /* Port P10 bit3 */ +#define p10_4 p10_addr.bit.b4 /* Port P10 bit4 */ +#define p10_5 p10_addr.bit.b5 /* Port P10 bit5 */ +#define p10_6 p10_addr.bit.b6 /* Port P10 bit6 */ +#define p10_7 p10_addr.bit.b7 /* Port P10 bit7 */ + +/*------------------------------------------------------ + Port P10 direction register +------------------------------------------------------*/ +union byte_def pd10_addr; +#define pd10 pd10_addr.byte + +#define pd10_0 pd10_addr.bit.b0 /* P10 direction register bit0 */ +#define pd10_1 pd10_addr.bit.b1 /* P10 direction register bit1 */ +#define pd10_2 pd10_addr.bit.b2 /* P10 direction register bit2 */ +#define pd10_3 pd10_addr.bit.b3 /* P10 direction register bit3 */ +#define pd10_4 pd10_addr.bit.b4 /* P10 direction register bit4 */ +#define pd10_5 pd10_addr.bit.b5 /* P10 direction register bit5 */ +#define pd10_6 pd10_addr.bit.b6 /* P10 direction register bit6 */ +#define pd10_7 pd10_addr.bit.b7 /* P10 direction register bit7 */ + +/*------------------------------------------------------ + Pull-up control register 0 +------------------------------------------------------*/ +union byte_def pur0_addr; +#define pur0 pur0_addr.byte + +#define pu00 pur0_addr.bit.b0 /* Pull-up P00 to P03 */ +#define pu01 pur0_addr.bit.b1 /* Pull-up P04 to P07 */ +#define pu02 pur0_addr.bit.b2 /* Pull-up P10 to P13 */ +#define pu03 pur0_addr.bit.b3 /* Pull-up P14 to P17 */ +#define pu04 pur0_addr.bit.b4 /* Pull-up P20 to P23 */ +#define pu05 pur0_addr.bit.b5 /* Pull-up P24 to P27 */ +#define pu06 pur0_addr.bit.b6 /* Pull-up P30 to P33 */ +#define pu07 pur0_addr.bit.b7 /* Pull-up P34 to P37 */ + +/*------------------------------------------------------ + Pull-up control register 1 +------------------------------------------------------*/ +union byte_def pur1_addr; +#define pur1 pur1_addr.byte + +#define pu10 pur1_addr.bit.b0 /* Pull-up P40 to P43 */ +#define pu11 pur1_addr.bit.b1 /* Pull-up P44 to P47 */ +#define pu12 pur1_addr.bit.b2 /* Pull-up P50 to P53 */ +#define pu13 pur1_addr.bit.b3 /* Pull-up P54 to P57 */ + /* (b7-b4) Nothing is assigned */ + +/*------------------------------------------------------ + Pull-up control register 3 +------------------------------------------------------*/ +union byte_def pur3_addr; +#define pur3 pur3_addr.byte + +#define pu30 pur3_addr.bit.b0 /* Pull-up P100 to P103 */ +#define pu31 pur3_addr.bit.b1 /* Pull-up P104 to P107 */ +#define pu32 pur3_addr.bit.b2 /* Pull-up P110 to P113 */ +#define pu33 pur3_addr.bit.b3 /* Pull-up P114 */ +#define pu34 pur3_addr.bit.b4 /* Pull-up P120 to P123 */ +#define pu35 pur3_addr.bit.b5 /* Pull-up P124 to P127 */ +#define pu36 pur3_addr.bit.b6 /* Pull-up P130 to P133 */ +#define pu37 pur3_addr.bit.b7 /* Pull-up P134 to P137 */ + +/*------------------------------------------------------ + Pull-up control register 4 +------------------------------------------------------*/ +union byte_def pur4_addr; +#define pur4 pur4_addr.byte + +#define pu40 pur4_addr.bit.b0 /* Pull-up P140 to P143 */ +#define pu41 pur4_addr.bit.b1 /* Pull-up P144 to P146 */ +#define pu42 pur4_addr.bit.b2 /* Pull-up P150 to P153 */ +#define pu43 pur4_addr.bit.b3 /* Pull-up P154 to P157 */ + /* (b7-b4) Nothing is assigned */ + +/*------------------------------------------------------ + Port control register +------------------------------------------------------*/ +union byte_def pcr_addr; +#define pcr pcr_addr.byte + +#define pcr0 pcr_addr.bit.b0 /* Port P1 control bit */ + /* (b2-b1) Reserved bit (Set to 0) */ + /* (b7-b3) Nothing is assigned */ + + +/*------------------------------------------------------ + Function select register A0 +------------------------------------------------------*/ +union byte_def ps0_addr; +#define ps0 ps0_addr.byte + +#define ps0_0 ps0_addr.bit.b0 /* Port P60 output function select bit */ +#define ps0_1 ps0_addr.bit.b1 /* Port P61 output function select bit */ +#define ps0_2 ps0_addr.bit.b2 /* Port P62 output function select bit */ +#define ps0_3 ps0_addr.bit.b3 /* Port P63 output function select bit */ +#define ps0_4 ps0_addr.bit.b4 /* Port P64 output function select bit */ +#define ps0_5 ps0_addr.bit.b5 /* Port P65 output function select bit */ +#define ps0_6 ps0_addr.bit.b6 /* Port P66 output function select bit */ +#define ps0_7 ps0_addr.bit.b7 /* Port P67 output function select bit */ + +/*------------------------------------------------------ + Function select register A1 +------------------------------------------------------*/ +union byte_def ps1_addr; +#define ps1 ps1_addr.byte + +#define ps1_0 ps1_addr.bit.b0 /* Port P70 output function select bit */ +#define ps1_1 ps1_addr.bit.b1 /* Port P71 output function select bit */ +#define ps1_2 ps1_addr.bit.b2 /* Port P72 output function select bit */ +#define ps1_3 ps1_addr.bit.b3 /* Port P73 output function select bit */ +#define ps1_4 ps1_addr.bit.b4 /* Port P74 output function select bit */ +#define ps1_5 ps1_addr.bit.b5 /* Port P75 output function select bit */ +#define ps1_6 ps1_addr.bit.b6 /* Port P76 output function select bit */ +#define ps1_7 ps1_addr.bit.b7 /* Port P77 output function select bit */ + +/*------------------------------------------------------ + Function select register A2 +------------------------------------------------------*/ +union byte_def ps2_addr; +#define ps2 ps2_addr.byte + +#define ps2_0 ps2_addr.bit.b0 /* Port P80 output function select bit */ +#define ps2_1 ps2_addr.bit.b1 /* Port P81 output function select bit */ +#define ps2_2 ps2_addr.bit.b2 /* Port P82 output function select bit */ + /* (b4-b3) Reserved bit (Set to 0) */ + /* (b5) Nothing is assigned */ + /* (b7-b6) Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + Function select register A3 +------------------------------------------------------*/ +union byte_def ps3_addr; +#define ps3 ps3_addr.byte + +#define ps3_0 ps3_addr.bit.b0 /* Port P90 output function select bit */ +#define ps3_1 ps3_addr.bit.b1 /* Port P91 output function select bit */ +#define ps3_2 ps3_addr.bit.b2 /* Port P92 output function select bit */ +#define ps3_3 ps3_addr.bit.b3 /* Port P93 output function select bit */ +#define ps3_4 ps3_addr.bit.b4 /* Port P94 output function select bit */ +#define ps3_5 ps3_addr.bit.b5 /* Port P95 output function select bit */ +#define ps3_6 ps3_addr.bit.b6 /* Port P96 output function select bit */ +#define ps3_7 ps3_addr.bit.b7 /* Port P97 output function select bit */ + +/*------------------------------------------------------ + Function select register B0 +------------------------------------------------------*/ +union byte_def psl0_addr; +#define psl0 psl0_addr.byte + /* (b1-b0) Reserved bit (Set to 0) */ +#define psl0_2 psl0_addr.bit.b2 /* Port P62 output peripheral function select bit */ + /* (b3) Reserved bit (Set to 0) */ +#define psl0_4 psl0_addr.bit.b4 /* Port P64 output peripheral function select bit */ + /* (b5) Reserved bit (Set to 0) */ +#define psl0_6 psl0_addr.bit.b6 /* Port P66 output peripheral function select bit */ + /* (b7) Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + Function select register B1 +------------------------------------------------------*/ +union byte_def psl1_addr; +#define psl1 psl1_addr.byte + +#define psl1_0 psl1_addr.bit.b0 /* Port P70 output peripheral function select bit */ +#define psl1_1 psl1_addr.bit.b1 /* Port P71 output peripheral function select bit */ +#define psl1_2 psl1_addr.bit.b2 /* Port P72 output peripheral function select bit */ +#define psl1_3 psl1_addr.bit.b3 /* Port P73 output peripheral function select bit */ +#define psl1_4 psl1_addr.bit.b4 /* Port P74 output peripheral function select bit */ +#define psl1_5 psl1_addr.bit.b5 /* Port P75 output peripheral function select bit */ +#define psl1_6 psl1_addr.bit.b6 /* Port P76 output peripheral function select bit */ +#define psl1_7 psl1_addr.bit.b7 /* Port P77 output peripheral function select bit */ + +/*------------------------------------------------------ + Function select register B2 +------------------------------------------------------*/ +union byte_def psl2_addr; +#define psl2 psl2_addr.byte + +#define psl2_0 psl2_addr.bit.b0 /* Port P80 output peripheral function select bit */ +#define psl2_1 psl2_addr.bit.b1 /* Port P81 output peripheral function select bit */ +#define psl2_2 psl2_addr.bit.b2 /* Port P82 output peripheral function select bit */ + /* (b4-b3) Reserved bit (Set to 0) */ + /* (b5) Nothing is assigned */ + /* (b7-b6) Reserved bit (Set to 0) */ + +/*------------------------------------------------------ + Function select register B3 +------------------------------------------------------*/ +union byte_def psl3_addr; +#define psl3 psl3_addr.byte + /* (b0) Reserved bit (Set to 0) */ +#define psl3_1 psl3_addr.bit.b1 /* Port P91 output peripheral function select bit */ +#define psl3_2 psl3_addr.bit.b2 /* Port P92 output peripheral function select bit */ +#define psl3_3 psl3_addr.bit.b3 /* Port P93 output peripheral function select bit */ +#define psl3_4 psl3_addr.bit.b4 /* Port P94 output peripheral function select bit */ +#define psl3_5 psl3_addr.bit.b5 /* Port P95 output peripheral function select bit */ +#define psl3_6 psl3_addr.bit.b6 /* Port P96 output peripheral function select bit */ +#define psl3_7 psl3_addr.bit.b7 /* Port P97 output peripheral function select bit */ + +/*------------------------------------------------------ + Function select register C +------------------------------------------------------*/ +union byte_def psc_addr; +#define psc psc_addr.byte + +#define psc_0 psc_addr.bit.b0 /* Port P70 output peripheral function select bit */ +#define psc_1 psc_addr.bit.b1 /* Port P71 output peripheral function select bit */ +#define psc_2 psc_addr.bit.b2 /* Port P72 output peripheral function select bit */ +#define psc_3 psc_addr.bit.b3 /* Port P73 output peripheral function select bit */ +#define psc_4 psc_addr.bit.b4 /* Port P74 output peripheral function select bit */ + /* (b5) Nothing is assigned */ +#define psc_6 psc_addr.bit.b6 /* Port P76 output peripheral function select bit */ +#define psc_7 psc_addr.bit.b7 /* Port Key input interrupt disable bit */ + +/*------------------------------------------------------ + Function Select Register C3 +------------------------------------------------------*/ +union byte_def psc3_addr; +#define psc3 psc3_addr.byte + /* (b5-b0) Nothing is assigned */ +#define psc3_6 psc3_addr.bit.b6 /* Port P96 output peripheral function select bit */ + /* (b7) Nothing is assigned */ + +/*------------------------------------------------------ + Function Select Register D1 +------------------------------------------------------*/ +union byte_def psd1_addr; +#define psd1 psd1_addr.byte + +#define psd1_0 psd1_addr.bit.b0 /* Port P70 output peripheral function select bit */ +#define psd1_1 psd1_addr.bit.b1 /* Port P71 output peripheral function select bit */ + /* (b5-b2) Nothing is assigned */ +#define psd1_6 psd1_addr.bit.b6 /* Port P76 output peripheral function select bit */ + /* (b7) Nothing is assigned */ + +/*------------------------------------------------------ + UARTi boud rate register (i=0,1,2,3,4) + (1) The MOV instruction should be used to set UiBRG register + (2) The UiBRG register should be set while stop data transmitting and receiveing +------------------------------------------------------*/ +union byte_def u0brg_addr; +#define u0brg u0brg_addr.byte + +union byte_def u1brg_addr; +#define u1brg u1brg_addr.byte + +union byte_def u2brg_addr; +#define u2brg u2brg_addr.byte + +union byte_def u3brg_addr; +#define u3brg u3brg_addr.byte + +union byte_def u4brg_addr; +#define u4brg u4brg_addr.byte + + + + +/******************************************************** +* declare SFR union * +********************************************************/ + +/*------------------------------------------------------ + Interrupt control registers +------------------------------------------------------*/ + +/*------------------------------------------------------ + ad0ic +------------------------------------------------------*/ +union byte_def ad0ic_addr; +#define ad0ic ad0ic_addr.byte + +#define ilvl0_ad0ic ad0ic_addr.bit.b0 +#define ilvl1_ad0ic ad0ic_addr.bit.b1 +#define ilvl2_ad0ic ad0ic_addr.bit.b2 +#define ir_ad0ic ad0ic_addr.bit.b3 + +/*------------------------------------------------------ + bcn0ic +------------------------------------------------------*/ +union byte_def bcn0ic_addr; +#define bcn0ic bcn0ic_addr.byte + +#define ilvl0_bcn0ic bcn0ic_addr.bit.b0 +#define ilvl1_bcn0ic bcn0ic_addr.bit.b1 +#define ilvl2_bcn0ic bcn0ic_addr.bit.b2 +#define ir_bcn0ic bcn0ic_addr.bit.b3 + +/*------------------------------------------------------ + bcn1ic +------------------------------------------------------*/ +union byte_def bcn1ic_addr; +#define bcn1ic bcn1ic_addr.byte + +#define ilvl0_bcn1ic bcn1ic_addr.bit.b0 +#define ilvl1_bcn1ic bcn1ic_addr.bit.b1 +#define ilvl2_bcn1ic bcn1ic_addr.bit.b2 +#define ir_bcn1ic bcn1ic_addr.bit.b3 + +/*------------------------------------------------------ + bcn2ic +------------------------------------------------------*/ +union byte_def bcn2ic_addr; +#define bcn2ic bcn2ic_addr.byte + +#define ilvl0_bcn2ic bcn2ic_addr.bit.b0 +#define ilvl1_bcn2ic bcn2ic_addr.bit.b1 +#define ilvl2_bcn2ic bcn2ic_addr.bit.b2 +#define ir_bcn2ic bcn2ic_addr.bit.b3 + +/*------------------------------------------------------ + bcn3ic +------------------------------------------------------*/ +union byte_def bcn3ic_addr; +#define bcn3ic bcn3ic_addr.byte + +#define ilvl0_bcn3ic bcn3ic_addr.bit.b0 +#define ilvl1_bcn3ic bcn3ic_addr.bit.b1 +#define ilvl2_bcn3ic bcn3ic_addr.bit.b2 +#define ir_bcn3ic bcn3ic_addr.bit.b3 + +/*------------------------------------------------------ + bcn4ic +------------------------------------------------------*/ +union byte_def bcn4ic_addr; +#define bcn4ic bcn4ic_addr.byte + +#define ilvl0_bcn4ic bcn4ic_addr.bit.b0 +#define ilvl1_bcn4ic bcn4ic_addr.bit.b1 +#define ilvl2_bcn4ic bcn4ic_addr.bit.b2 +#define ir_bcn4ic bcn4ic_addr.bit.b3 + +/*------------------------------------------------------ + dm0ic +------------------------------------------------------*/ +union byte_def dm0ic_addr; +#define dm0ic dm0ic_addr.byte + +#define ilvl0_dm0ic dm0ic_addr.bit.b0 +#define ilvl1_dm0ic dm0ic_addr.bit.b1 +#define ilvl2_dm0ic dm0ic_addr.bit.b2 +#define ir_dm0ic dm0ic_addr.bit.b3 + +/*------------------------------------------------------ + dm1ic +------------------------------------------------------*/ +union byte_def dm1ic_addr; +#define dm1ic dm1ic_addr.byte + +#define ilvl0_dm1ic dm1ic_addr.bit.b0 +#define ilvl1_dm1ic dm1ic_addr.bit.b1 +#define ilvl2_dm1ic dm1ic_addr.bit.b2 +#define ir_dm1ic dm1ic_addr.bit.b3 + +/*------------------------------------------------------ + dm2ic +------------------------------------------------------*/ +union byte_def dm2ic_addr; +#define dm2ic dm2ic_addr.byte + +#define ilvl0_dm2ic dm2ic_addr.bit.b0 +#define ilvl1_dm2ic dm2ic_addr.bit.b1 +#define ilvl2_dm2ic dm2ic_addr.bit.b2 +#define ir_dm2ic dm2ic_addr.bit.b3 + +/*------------------------------------------------------ + dm3ic +------------------------------------------------------*/ +union byte_def dm3ic_addr; +#define dm3ic dm3ic_addr.byte + +#define ilvl0_dm3ic dm3ic_addr.bit.b0 +#define ilvl1_dm3ic dm3ic_addr.bit.b1 +#define ilvl2_dm3ic dm3ic_addr.bit.b2 +#define ir_dm3ic dm3ic_addr.bit.b3 + + +/*------------------------------------------------------ + kupic +------------------------------------------------------*/ +union byte_def kupic_addr; +#define kupic kupic_addr.byte + +#define ilvl0_kupic kupic_addr.bit.b0 +#define ilvl1_kupic kupic_addr.bit.b1 +#define ilvl2_kupic kupic_addr.bit.b2 +#define ir_kupic kupic_addr.bit.b3 + +/*------------------------------------------------------ + ta0ic +------------------------------------------------------*/ +union byte_def ta0ic_addr; +#define ta0ic ta0ic_addr.byte + +#define ilvl0_ta0ic ta0ic_addr.bit.b0 +#define ilvl1_ta0ic ta0ic_addr.bit.b1 +#define ilvl2_ta0ic ta0ic_addr.bit.b2 +#define ir_ta0ic ta0ic_addr.bit.b3 + +/*------------------------------------------------------ + ta1ic +------------------------------------------------------*/ +union byte_def ta1ic_addr; +#define ta1ic ta1ic_addr.byte + +#define ilvl0_ta1ic ta1ic_addr.bit.b0 +#define ilvl1_ta1ic ta1ic_addr.bit.b1 +#define ilvl2_ta1ic ta1ic_addr.bit.b2 +#define ir_ta1ic ta1ic_addr.bit.b3 + +/*------------------------------------------------------ + ta2ic +------------------------------------------------------*/ +union byte_def ta2ic_addr; +#define ta2ic ta2ic_addr.byte +#define ilvl0_ta2ic ta2ic_addr.bit.b0 +#define ilvl1_ta2ic ta2ic_addr.bit.b1 +#define ilvl2_ta2ic ta2ic_addr.bit.b2 +#define ir_ta2ic ta2ic_addr.bit.b3 + +/*------------------------------------------------------ + ta3ic +------------------------------------------------------*/ +union byte_def ta3ic_addr; +#define ta3ic ta3ic_addr.byte + +#define ilvl0_ta3ic ta3ic_addr.bit.b0 +#define ilvl1_ta3ic ta3ic_addr.bit.b1 +#define ilvl2_ta3ic ta3ic_addr.bit.b2 +#define ir_ta3ic ta3ic_addr.bit.b3 + +/*------------------------------------------------------ + ta4ic +------------------------------------------------------*/ +union byte_def ta4ic_addr; +#define ta4ic ta4ic_addr.byte + +#define ilvl0_ta4ic ta4ic_addr.bit.b0 +#define ilvl1_ta4ic ta4ic_addr.bit.b1 +#define ilvl2_ta4ic ta4ic_addr.bit.b2 +#define ir_ta4ic ta4ic_addr.bit.b3 + +/*------------------------------------------------------ + tb0ic +------------------------------------------------------*/ +union byte_def tb0ic_addr; +#define tb0ic tb0ic_addr.byte + +#define ilvl0_tb0ic tb0ic_addr.bit.b0 +#define ilvl1_tb0ic tb0ic_addr.bit.b1 +#define ilvl2_tb0ic tb0ic_addr.bit.b2 +#define ir_tb0ic tb0ic_addr.bit.b3 + +/*------------------------------------------------------ + tb1ic +------------------------------------------------------*/ +union byte_def tb1ic_addr; +#define tb1ic tb1ic_addr.byte + +#define ilvl0_tb1ic tb1ic_addr.bit.b0 +#define ilvl1_tb1ic tb1ic_addr.bit.b1 +#define ilvl2_tb1ic tb1ic_addr.bit.b2 +#define ir_tb1ic tb1ic_addr.bit.b3 + +/*------------------------------------------------------ + tb2ic +------------------------------------------------------*/ +union byte_def tb2ic_addr; +#define tb2ic tb2ic_addr.byte + +#define ilvl0_tb2ic tb2ic_addr.bit.b0 +#define ilvl1_tb2ic tb2ic_addr.bit.b1 +#define ilvl2_tb2ic tb2ic_addr.bit.b2 +#define ir_tb2ic tb2ic_addr.bit.b3 + +/*------------------------------------------------------ + tb3ic +------------------------------------------------------*/ +union byte_def tb3ic_addr; +#define tb3ic tb3ic_addr.byte + +#define ilvl0_tb3ic tb3ic_addr.bit.b0 +#define ilvl1_tb3ic tb3ic_addr.bit.b1 +#define ilvl2_tb3ic tb3ic_addr.bit.b2 +#define ir_tb3ic tb3ic_addr.bit.b3 + +/*------------------------------------------------------ + tb4ic +------------------------------------------------------*/ +union byte_def tb4ic_addr; +#define tb4ic tb4ic_addr.byte + +#define ilvl0_tb4ic tb4ic_addr.bit.b0 +#define ilvl1_tb4ic tb4ic_addr.bit.b1 +#define ilvl2_tb4ic tb4ic_addr.bit.b2 +#define ir_tb4ic tb4ic_addr.bit.b3 + +/*------------------------------------------------------ + tb5ic +------------------------------------------------------*/ +union byte_def tb5ic_addr; +#define tb5ic tb5ic_addr.byte + +#define ilvl0_tb5ic tb5ic_addr.bit.b0 +#define ilvl1_tb5ic tb5ic_addr.bit.b1 +#define ilvl2_tb5ic tb5ic_addr.bit.b2 +#define ir_tb5ic tb5ic_addr.bit.b3 + +/*------------------------------------------------------ + s0tic +------------------------------------------------------*/ +union byte_def s0tic_addr; +#define s0tic s0tic_addr.byte + +#define ilvl0_s0tic s0tic_addr.bit.b0 +#define ilvl1_s0tic s0tic_addr.bit.b1 +#define ilvl2_s0tic s0tic_addr.bit.b2 +#define ir_s0tic s0tic_addr.bit.b3 + +/*------------------------------------------------------ + s1tic +------------------------------------------------------*/ +union byte_def s1tic_addr; +#define s1tic s1tic_addr.byte + +#define ilvl0_s1tic s1tic_addr.bit.b0 +#define ilvl1_s1tic s1tic_addr.bit.b1 +#define ilvl2_s1tic s1tic_addr.bit.b2 +#define ir_s1tic s1tic_addr.bit.b3 + +/*------------------------------------------------------ + s2tic +------------------------------------------------------*/ +union byte_def s2tic_addr; +#define s2tic s2tic_addr.byte + +#define ilvl0_s2tic s2tic_addr.bit.b0 +#define ilvl1_s2tic s2tic_addr.bit.b1 +#define ilvl2_s2tic s2tic_addr.bit.b2 +#define ir_s2tic s2tic_addr.bit.b3 + +/*------------------------------------------------------ + s3tic +------------------------------------------------------*/ +union byte_def s3tic_addr; +#define s3tic s3tic_addr.byte + +#define ilvl0_s3tic s3tic_addr.bit.b0 +#define ilvl1_s3tic s3tic_addr.bit.b1 +#define ilvl2_s3tic s3tic_addr.bit.b2 +#define ir_s3tic s3tic_addr.bit.b3 + +/*------------------------------------------------------ + s4tic +------------------------------------------------------*/ +union byte_def s4tic_addr; +#define s4tic s4tic_addr.byte + +#define ilvl0_s4tic s4tic_addr.bit.b0 +#define ilvl1_s4tic s4tic_addr.bit.b1 +#define ilvl2_s4tic s4tic_addr.bit.b2 +#define ir_s4tic s4tic_addr.bit.b3 + +/*------------------------------------------------------ + s0ric +------------------------------------------------------*/ +union byte_def s0ric_addr; +#define s0ric s0ric_addr.byte + +#define ilvl0_s0ric s0ric_addr.bit.b0 +#define ilvl1_s0ric s0ric_addr.bit.b1 +#define ilvl2_s0ric s0ric_addr.bit.b2 +#define ir_s0ric s0ric_addr.bit.b3 + +/*------------------------------------------------------ + s1ric +------------------------------------------------------*/ +union byte_def s1ric_addr; +#define s1ric s1ric_addr.byte + +#define ilvl0_s1ric s1ric_addr.bit.b0 +#define ilvl1_s1ric s1ric_addr.bit.b1 +#define ilvl2_s1ric s1ric_addr.bit.b2 +#define ir_s1ric s1ric_addr.bit.b3 + +/*------------------------------------------------------ + s2ric +------------------------------------------------------*/ +union byte_def s2ric_addr; +#define s2ric s2ric_addr.byte + +#define ilvl0_s2ric s2ric_addr.bit.b0 +#define ilvl1_s2ric s2ric_addr.bit.b1 +#define ilvl2_s2ric s2ric_addr.bit.b2 +#define ir_s2ric s2ric_addr.bit.b3 + +/*------------------------------------------------------ + s3ric +------------------------------------------------------*/ +union byte_def s3ric_addr; +#define s3ric s3ric_addr.byte + +#define ilvl0_s3ric s3ric_addr.bit.b0 +#define ilvl1_s3ric s3ric_addr.bit.b1 +#define ilvl2_s3ric s3ric_addr.bit.b2 +#define ir_s3ric s3ric_addr.bit.b3 + +/*------------------------------------------------------ + s4ric +------------------------------------------------------*/ +union byte_def s4ric_addr; +#define s4ric s4ric_addr.byte + +#define ilvl0_s4ric s4ric_addr.bit.b0 +#define ilvl1_s4ric s4ric_addr.bit.b1 +#define ilvl2_s4ric s4ric_addr.bit.b2 +#define ir_s4ric s4ric_addr.bit.b3 + +/*------------------------------------------------------ + iio0ic +------------------------------------------------------*/ +union byte_def iio0ic_addr; +#define iio0ic iio0ic_addr.byte + +#define ilvl0_iio0ic iio0ic_addr.bit.b0 +#define ilvl1_iio0ic iio0ic_addr.bit.b1 +#define ilvl2_iio0ic iio0ic_addr.bit.b2 +#define ir_iio0ic iio0ic_addr.bit.b3 + +/*------------------------------------------------------ + iio1ic +------------------------------------------------------*/ +union byte_def iio1ic_addr; +#define iio1ic iio1ic_addr.byte + +#define ilvl0_iio1ic iio1ic_addr.bit.b0 +#define ilvl1_iio1ic iio1ic_addr.bit.b1 +#define ilvl2_iio1ic iio1ic_addr.bit.b2 +#define ir_iio1ic iio1ic_addr.bit.b3 + +/*------------------------------------------------------ + iio2ic +------------------------------------------------------*/ +union byte_def iio2ic_addr; +#define iio2ic iio2ic_addr.byte + +#define ilvl0_iio2ic iio2ic_addr.bit.b0 +#define ilvl1_iio2ic iio2ic_addr.bit.b1 +#define ilvl2_iio2ic iio2ic_addr.bit.b2 +#define ir_iio2ic iio2ic_addr.bit.b3 + +/*------------------------------------------------------ + iio3ic +------------------------------------------------------*/ +union byte_def iio3ic_addr; +#define iio3ic iio3ic_addr.byte + +#define ilvl0_iio3ic iio3ic_addr.bit.b0 +#define ilvl1_iio3ic iio3ic_addr.bit.b1 +#define ilvl2_iio3ic iio3ic_addr.bit.b2 +#define ir_iio3ic iio3ic_addr.bit.b3 + +/*------------------------------------------------------ + iio4ic +------------------------------------------------------*/ +union byte_def iio4ic_addr; +#define iio4ic iio4ic_addr.byte + +#define ilvl0_iio4ic iio4ic_addr.bit.b0 +#define ilvl1_iio4ic iio4ic_addr.bit.b1 +#define ilvl2_iio4ic iio4ic_addr.bit.b2 +#define ir_iio4ic iio4ic_addr.bit.b3 + +/*------------------------------------------------------ + int0ic +------------------------------------------------------*/ +union byte_def int0ic_addr; +#define int0ic int0ic_addr.byte + +#define ilvl0_int0ic int0ic_addr.bit.b0 +#define ilvl1_int0ic int0ic_addr.bit.b1 +#define ilvl2_int0ic int0ic_addr.bit.b2 +#define ir_int0ic int0ic_addr.bit.b3 +#define pol_int0ic int0ic_addr.bit.b4 +#define lvs_int0ic int0ic_addr.bit.b5 + +/*------------------------------------------------------ + int1ic +------------------------------------------------------*/ +union byte_def int1ic_addr; +#define int1ic int1ic_addr.byte + +#define ilvl0_int1ic int1ic_addr.bit.b0 +#define ilvl1_int1ic int1ic_addr.bit.b1 +#define ilvl2_int1ic int1ic_addr.bit.b2 +#define ir_int1ic int1ic_addr.bit.b3 +#define pol_int1ic int1ic_addr.bit.b4 +#define lvs_int1ic int1ic_addr.bit.b5 + +/*------------------------------------------------------ + int2ic +------------------------------------------------------*/ +union byte_def int2ic_addr; +#define int2ic int2ic_addr.byte + +#define ilvl0_int2ic int2ic_addr.bit.b0 +#define ilvl1_int2ic int2ic_addr.bit.b1 +#define ilvl2_int2ic int2ic_addr.bit.b2 +#define ir_int2ic int2ic_addr.bit.b3 +#define pol_int2ic int2ic_addr.bit.b4 +#define lvs_int2ic int2ic_addr.bit.b5 + +/*------------------------------------------------------ + int3ic +------------------------------------------------------*/ +union byte_def int3ic_addr; +#define int3ic int3ic_addr.byte + +#define ilvl0_int3ic int3ic_addr.bit.b0 +#define ilvl1_int3ic int3ic_addr.bit.b1 +#define ilvl2_int3ic int3ic_addr.bit.b2 +#define ir_int3ic int3ic_addr.bit.b3 +#define pol_int3ic int3ic_addr.bit.b4 +#define lvs_int3ic int3ic_addr.bit.b5 + +/*------------------------------------------------------ + int4ic +------------------------------------------------------*/ +union byte_def int4ic_addr; +#define int4ic int4ic_addr.byte + +#define ilvl0_int4ic int4ic_addr.bit.b0 +#define ilvl1_int4ic int4ic_addr.bit.b1 +#define ilvl2_int4ic int4ic_addr.bit.b2 +#define ir_int4ic int4ic_addr.bit.b3 +#define pol_int4ic int4ic_addr.bit.b4 +#define lvs_int4ic int4ic_addr.bit.b5 + +/*------------------------------------------------------ + int5ic +------------------------------------------------------*/ +union byte_def int5ic_addr; +#define int5ic int5ic_addr.byte + +#define ilvl0_int5ic int5ic_addr.bit.b0 +#define ilvl1_int5ic int5ic_addr.bit.b1 +#define ilvl2_int5ic int5ic_addr.bit.b2 +#define ir_int5ic int5ic_addr.bit.b3 +#define pol_int5ic int5ic_addr.bit.b4 +#define lvs_int5ic int5ic_addr.bit.b5 + +/*------------------------------------------------------ + Interrupt Request Register +------------------------------------------------------*/ + +/*------------------------------------------------------ + iio0ir +------------------------------------------------------*/ +union byte_def iio0ir_addr; +#define iio0ir iio0ir_addr.byte + /* (b0) - */ + /* (b1) - */ +#define tm13r iio0ir_addr.bit.b2 /* II/O time measurement 3 interrupt */ +#define po13r iio0ir_addr.bit.b2 /* II/O waveform generation function 3 interrupt */ + /* (b3) - */ +#define g0rir iio0ir_addr.bit.b4 /* II/O communication unit 0 HDLC data processing function interrupt */ +#define sio0rr iio0ir_addr.bit.b5 /* II/O communication unit 0 receive interrupt */ + /* (b6) - */ +#define can10r iio0ir_addr.bit.b7 /* CAN1 communication function interrupt */ + +/*------------------------------------------------------ + iio1ir +------------------------------------------------------*/ +union byte_def iio1ir_addr; +#define iio1ir iio1ir_addr.byte + /* (b0) - */ + /* (b1) - */ +#define tm14r iio1ir_addr.bit.b2 /* II/O time measurement 4 interrupt */ +#define po14r iio1ir_addr.bit.b2 /* II/O waveform generation function 4 interrupt */ + /* (b3) - */ +#define g0tor iio1ir_addr.bit.b4 /* II/O communication unit 0 HDLC data processing function interrupt */ +#define sio0tr iio1ir_addr.bit.b5 /* II/O communication unit 0 transmit interrupt */ + /* (b6) - */ +#define can11r iio1ir_addr.bit.b7 /* CAN1 communication function interrupt */ + +/*------------------------------------------------------ + iio2ir +------------------------------------------------------*/ +union byte_def iio2ir_addr; +#define iio2ir iio2ir_addr.byte + /* (b0) - */ + /* (b1) - */ +#define tm12r iio2ir_addr.bit.b2 /* II/O time measurement 2 interrupt */ +#define po12r iio2ir_addr.bit.b2 /* II/O waveform generation function 2 interrupt */ + /* (b3) - */ +#define g1rir iio2ir_addr.bit.b4 /* II/O communication unit 1 HDLC data processing function interrupt */ +#define sio1rr iio2ir_addr.bit.b5 /* II/O communication unit 1 receive interrupt */ + /* (b6) - */ + /* (b7) - */ + +/*------------------------------------------------------ + iio3ir +------------------------------------------------------*/ +union byte_def iio3ir_addr; +#define iio3ir iio3ir_addr.byte + /* (b0) - */ + /* (b1) - */ +#define tm10r iio3ir_addr.bit.b2 /* II/O time measurement 0 interrupt */ +#define po10r iio3ir_addr.bit.b2 /* II/O waveform generation function 0 interrupt */ + /* (b3) - */ +#define g1tor iio3ir_addr.bit.b4 /* II/O communication unit 1 HDLC data processing function interrupt */ +#define sio1tr iio3ir_addr.bit.b5 /* II/O communication unit 0 transmit interrupt */ + /* (b6) - */ + /* (b7) - */ + +/*------------------------------------------------------ + iio4ir +------------------------------------------------------*/ +union byte_def iio4ir_addr; +#define iio4ir iio4ir_addr.byte + /* (b0) - */ + /* (b1) - */ +#define tm17r iio4ir_addr.bit.b2 /* II/O time measurement 7 interrupt */ +#define po17r iio4ir_addr.bit.b2 /* II/O waveform generation function 7 interrupt */ + /* (b3) - */ +#define bt1r iio4ir_addr.bit.b4 /* II/O communication base timer interrupt */ + /* (b5) - */ +#define srt1r iio4ir_addr.bit.b6 /* II/O special communication function interrupt */ +#define srt0r iio4ir_addr.bit.b7 /* II/O special communication function interrupt */ + +/*------------------------------------------------------ + iio5ir +------------------------------------------------------*/ +union byte_def iio5ir_addr; +#define iio5ir iio5ir_addr.byte + /* (b0) - */ + /* (b5-b1) - */ +#define can1wur iio5ir_addr.bit.b6 /* CAN1 wake-up interrupt */ +#define can12r iio5ir_addr.bit.b7 /* CAN1 communication function interrupt */ + +/*------------------------------------------------------ + Interrupt Enable Register +------------------------------------------------------*/ + +/*------------------------------------------------------ + iio0ie +------------------------------------------------------*/ +union byte_def iio0ie_addr; +#define iio0ie iio0ie_addr.byte +#define irlt_iio0ie iio0ie_addr.bit.b0 /* Interrupt request select bit */ + /* (b1) - */ +#define tm13e iio0ie_addr.bit.b2 /* II/O time measurement 3 interrupt */ +#define po13e iio0ie_addr.bit.b2 /* II/O waveform generation function 3 interrupt */ + /* (b3) - */ +#define g0rie iio0ie_addr.bit.b4 /* II/O communication unit 0 HDLC data processing function interrupt */ +#define sio0re iio0ie_addr.bit.b5 /* II/O communication unit 0 receive interrupt */ + /* (b6) - */ +#define can10e iio0ie_addr.bit.b7 /* CAN1 communication function interrupt */ + +/*------------------------------------------------------ + iio1ie +------------------------------------------------------*/ +union byte_def iio1ie_addr; +#define iio1ie iio1ie_addr.byte +#define irlt_iio1ie iio1ie_addr.bit.b0 /* Interrupt request select bit */ + /* (b1) - */ +#define tm14e iio1ie_addr.bit.b2 /* II/O time measurement 4 interrupt */ +#define po14e iio1ie_addr.bit.b2 /* II/O waveform generation function 4 interrupt */ + /* (b3) - */ +#define g0toe iio1ie_addr.bit.b4 /* II/O communication unit 0 HDLC data processing function interrupt */ +#define sio0te iio1ie_addr.bit.b5 /* II/O communication unit 0 receive interrupt */ + /* (b6) - */ +#define can11e iio1ie_addr.bit.b7 /* CAN1 communication function interrupt */ + +/*------------------------------------------------------ + iio2ie +------------------------------------------------------*/ +union byte_def iio2ie_addr; +#define iio2ie iio2ie_addr.byte +#define irlt_iio2ie iio2ie_addr.bit.b0 /* Interrupt request select bit */ + /* (b1) - */ +#define tm12e iio2ie_addr.bit.b2 /* II/O time measurement 2 interrupt */ +#define po12e iio2ie_addr.bit.b2 /* II/O waveform generation function 2 interrupt */ + /* (b3) - */ +#define g1rie iio2ie_addr.bit.b4 /* II/O communication unit 1 HDLC data processing function interrupt */ +#define sio1re iio2ie_addr.bit.b5 /* II/O communication unit 1 receive interrupt */ + /* (b6) - */ + /* (b7) - */ + +/*------------------------------------------------------ + iio3ie +------------------------------------------------------*/ +union byte_def iio3ie_addr; +#define iio3ie iio3ie_addr.byte +#define irlt_iio3ie iio3ie_addr.bit.b0 /* Interrupt request select bit */ + /* (b1) - */ +#define tm10e iio3ie_addr.bit.b2 /* II/O time measurement 0 interrupt */ +#define po10e iio3ie_addr.bit.b2 /* II/O waveform generation function 0 interrupt */ + /* (b3) - */ +#define g1toe iio3ie_addr.bit.b4 /* II/O communication unit 1 HDLC data processing function interrupt */ +#define sio1te iio3ie_addr.bit.b5 /* II/O communication unit 0 transmit interrupt */ + /* (b6) - */ + /* (b7) - */ + +/*------------------------------------------------------ + iio4ie +------------------------------------------------------*/ +union byte_def iio4ie_addr; +#define iio4ie iio4ie_addr.byte +#define irlt_iio4ie iio4ie_addr.bit.b0 /* Interrupt request select bit */ + /* (b1) - */ +#define tm17e iio4ie_addr.bit.b2 /* II/O time measurement 7 interrupt */ +#define po17e iio4ie_addr.bit.b2 /* II/O waveform generation function 7 interrupt */ + /* (b3) - */ +#define bt1e iio4ie_addr.bit.b4 /* II/O communication base timer interrupt */ + /* (b5) - */ +#define srt1e iio4ie_addr.bit.b6 /* II/O special communication function interrupt */ +#define srt0e iio4ie_addr.bit.b7 /* II/O special communication function interrupt */ + +/*------------------------------------------------------ + Timer mode registers +------------------------------------------------------*/ + +/*------------------------------------------------------ + ta0mr +------------------------------------------------------*/ +union byte_def ta0mr_addr; +#define ta0mr ta0mr_addr.byte + +#define tmod0_ta0mr ta0mr_addr.bit.b0 +#define tmod1_ta0mr ta0mr_addr.bit.b1 +#define mr1_ta0mr ta0mr_addr.bit.b3 +#define mr2_ta0mr ta0mr_addr.bit.b4 +#define mr3_ta0mr ta0mr_addr.bit.b5 +#define tck0_ta0mr ta0mr_addr.bit.b6 +#define tck1_ta0mr ta0mr_addr.bit.b7 + +/*------------------------------------------------------ + ta1mr +------------------------------------------------------*/ +union byte_def ta1mr_addr; +#define ta1mr ta1mr_addr.byte + +#define tmod0_ta1mr ta1mr_addr.bit.b0 +#define tmod1_ta1mr ta1mr_addr.bit.b1 +#define mr1_ta1mr ta1mr_addr.bit.b3 +#define mr2_ta1mr ta1mr_addr.bit.b4 +#define mr3_ta1mr ta1mr_addr.bit.b5 +#define tck0_ta1mr ta1mr_addr.bit.b6 +#define tck1_ta1mr ta1mr_addr.bit.b7 + +/*------------------------------------------------------ + ta2mr +------------------------------------------------------*/ +union byte_def ta2mr_addr; +#define ta2mr ta2mr_addr.byte + +#define tmod0_ta2mr ta2mr_addr.bit.b0 +#define tmod1_ta2mr ta2mr_addr.bit.b1 +#define mr1_ta2mr ta2mr_addr.bit.b3 +#define mr2_ta2mr ta2mr_addr.bit.b4 +#define mr3_ta2mr ta2mr_addr.bit.b5 +#define tck0_ta2mr ta2mr_addr.bit.b6 +#define tck1_ta2mr ta2mr_addr.bit.b7 + +/*------------------------------------------------------ + ta3mr +------------------------------------------------------*/ +union byte_def ta3mr_addr; +#define ta3mr ta3mr_addr.byte + +#define tmod0_ta3mr ta3mr_addr.bit.b0 +#define tmod1_ta3mr ta3mr_addr.bit.b1 +#define mr1_ta3mr ta3mr_addr.bit.b3 +#define mr2_ta3mr ta3mr_addr.bit.b4 +#define mr3_ta3mr ta3mr_addr.bit.b5 +#define tck0_ta3mr ta3mr_addr.bit.b6 +#define tck1_ta3mr ta3mr_addr.bit.b7 + +/*------------------------------------------------------ + ta4mr +------------------------------------------------------*/ +union byte_def ta4mr_addr; +#define ta4mr ta4mr_addr.byte + +#define tmod0_ta4mr ta4mr_addr.bit.b0 +#define tmod1_ta4mr ta4mr_addr.bit.b1 +#define mr1_ta4mr ta4mr_addr.bit.b3 +#define mr2_ta4mr ta4mr_addr.bit.b4 +#define mr3_ta4mr ta4mr_addr.bit.b5 +#define tck0_ta4mr ta4mr_addr.bit.b6 +#define tck1_ta4mr ta4mr_addr.bit.b7 + +/*------------------------------------------------------ + tb0mr + ------------------------------------------------------*/ +union byte_def tb0mr_addr; +#define tb0mr tb0mr_addr.byte + +#define tmod0_tb0mr tb0mr_addr.bit.b0 +#define tmod1_tb0mr tb0mr_addr.bit.b1 +#define mr0_tb0mr tb0mr_addr.bit.b2 +#define mr1_tb0mr tb0mr_addr.bit.b3 +#define mr2_tb0mr tb0mr_addr.bit.b4 +#define mr3_tb0mr tb0mr_addr.bit.b5 +#define tck0_tb0mr tb0mr_addr.bit.b6 +#define tck1_tb0mr tb0mr_addr.bit.b7 + +/*------------------------------------------------------ + tb1mr +------------------------------------------------------*/ +union byte_def tb1mr_addr; +#define tb1mr tb1mr_addr.byte + +#define tmod0_tb1mr tb1mr_addr.bit.b0 +#define tmod1_tb1mr tb1mr_addr.bit.b1 +#define mr0_tb1mr tb1mr_addr.bit.b2 +#define mr1_tb1mr tb1mr_addr.bit.b3 +#define mr2_tb1mr tb1mr_addr.bit.b4 +#define mr3_tb1mr tb1mr_addr.bit.b5 +#define tck0_tb1mr tb1mr_addr.bit.b6 +#define tck1_tb1mr tb1mr_addr.bit.b7 + +/*------------------------------------------------------ + tb2mr +------------------------------------------------------*/ +union byte_def tb2mr_addr; +#define tb2mr tb2mr_addr.byte + +#define tmod0_tb2mr tb2mr_addr.bit.b0 +#define tmod1_tb2mr tb2mr_addr.bit.b1 +#define mr0_tb2mr tb2mr_addr.bit.b2 +#define mr1_tb2mr tb2mr_addr.bit.b3 +#define mr2_tb2mr tb2mr_addr.bit.b4 +#define mr3_tb2mr tb2mr_addr.bit.b5 +#define tck0_tb2mr tb2mr_addr.bit.b6 +#define tck1_tb2mr tb2mr_addr.bit.b7 + +/*------------------------------------------------------ + tb3mr +------------------------------------------------------*/ +union byte_def tb3mr_addr; +#define tb3mr tb3mr_addr.byte + +#define tmod0_tb3mr tb3mr_addr.bit.b0 +#define tmod1_tb3mr tb3mr_addr.bit.b1 +#define mr0_tb3mr tb3mr_addr.bit.b2 +#define mr1_tb3mr tb3mr_addr.bit.b3 +#define mr2_tb3mr tb3mr_addr.bit.b4 +#define mr3_tb3mr tb3mr_addr.bit.b5 +#define tck0_tb3mr tb3mr_addr.bit.b6 +#define tck1_tb3mr tb3mr_addr.bit.b7 + +/*------------------------------------------------------ + tb4mr +------------------------------------------------------*/ +union byte_def tb4mr_addr; +#define tb4mr tb4mr_addr.byte + +#define tmod0_tb4mr tb4mr_addr.bit.b0 +#define tmod1_tb4mr tb4mr_addr.bit.b1 +#define mr0_tb4mr tb4mr_addr.bit.b2 +#define mr1_tb4mr tb4mr_addr.bit.b3 +#define mr2_tb4mr tb4mr_addr.bit.b4 +#define mr3_tb4mr tb4mr_addr.bit.b5 +#define tck0_tb4mr tb4mr_addr.bit.b6 +#define tck1_tb4mr tb4mr_addr.bit.b7 + +/*------------------------------------------------------ + tb5mr +------------------------------------------------------*/ +union byte_def tb5mr_addr; +#define tb5mr tb5mr_addr.byte + +#define tmod0_tb5mr tb5mr_addr.bit.b0 +#define tmod1_tb5mr tb5mr_addr.bit.b1 +#define mr0_tb5mr tb5mr_addr.bit.b2 +#define mr1_tb5mr tb5mr_addr.bit.b3 +#define mr2_tb5mr tb5mr_addr.bit.b4 +#define mr3_tb5mr tb5mr_addr.bit.b5 +#define tck0_tb5mr tb5mr_addr.bit.b6 +#define tck1_tb5mr tb5mr_addr.bit.b7 + +/*------------------------------------------------------ + UARTi transmit/receive mode registers +------------------------------------------------------*/ + +/*------------------------------------------------------ + u0mr +------------------------------------------------------*/ +union byte_def u0mr_addr; +#define u0mr u0mr_addr.byte + +#define smd0_u0mr u0mr_addr.bit.b0 /* Serial I/O mode select bit */ +#define smd1_u0mr u0mr_addr.bit.b1 /* Serial I/O mode select bit */ +#define smd2_u0mr u0mr_addr.bit.b2 /* Serial I/O mode select bit */ +#define ckdir_u0mr u0mr_addr.bit.b3 /* Internal/external clock select bit */ +#define stps_u0mr u0mr_addr.bit.b4 /* Stop bit length select bit */ +#define pry_u0mr u0mr_addr.bit.b5 /* Odd/even parity select bit */ +#define prye_u0mr u0mr_addr.bit.b6 /* Parity enable bit */ +#define iopol_u0mr u0mr_addr.bit.b7 /* TxD RxD I/O polarity switch bit */ + +/*------------------------------------------------------ + u1mr +------------------------------------------------------*/ +union byte_def u1mr_addr; +#define u1mr u1mr_addr.byte + +#define smd0_u1mr u1mr_addr.bit.b0 +#define smd1_u1mr u1mr_addr.bit.b1 +#define smd2_u1mr u1mr_addr.bit.b2 +#define ckdir_u1mr u1mr_addr.bit.b3 +#define stps_u1mr u1mr_addr.bit.b4 +#define pry_u1mr u1mr_addr.bit.b5 +#define prye_u1mr u1mr_addr.bit.b6 +#define iopol_u1mr u1mr_addr.bit.b7 + +/*------------------------------------------------------ + u2mr +------------------------------------------------------*/ +union byte_def u2mr_addr; +#define u2mr u2mr_addr.byte + +#define smd0_u2mr u2mr_addr.bit.b0 +#define smd1_u2mr u2mr_addr.bit.b1 +#define smd2_u2mr u2mr_addr.bit.b2 +#define ckdir_u2mr u2mr_addr.bit.b3 +#define stps_u2mr u2mr_addr.bit.b4 +#define pry_u2mr u2mr_addr.bit.b5 +#define prye_u2mr u2mr_addr.bit.b6 +#define iopol_u2mr u2mr_addr.bit.b7 + +/*------------------------------------------------------ + u3mr +------------------------------------------------------*/ +union byte_def u3mr_addr; +#define u3mr u3mr_addr.byte + +#define smd0_u3mr u3mr_addr.bit.b0 +#define smd1_u3mr u3mr_addr.bit.b1 +#define smd2_u3mr u3mr_addr.bit.b2 +#define ckdir_u3mr u3mr_addr.bit.b3 +#define stps_u3mr u3mr_addr.bit.b4 +#define pry_u3mr u3mr_addr.bit.b5 +#define prye_u3mr u3mr_addr.bit.b6 +#define iopol_u3mr u3mr_addr.bit.b7 + +/*------------------------------------------------------ + u4mr +------------------------------------------------------*/ +union byte_def u4mr_addr; +#define u4mr u4mr_addr.byte + +#define smd0_u4mr u4mr_addr.bit.b0 +#define smd1_u4mr u4mr_addr.bit.b1 +#define smd2_u4mr u4mr_addr.bit.b2 +#define ckdir_u4mr u4mr_addr.bit.b3 +#define stps_u4mr u4mr_addr.bit.b4 +#define pry_u4mr u4mr_addr.bit.b5 +#define prye_u4mr u4mr_addr.bit.b6 +#define iopol_u4mr u4mr_addr.bit.b7 + +/*------------------------------------------------------ + UARTi transmit/receive control register 0 (i=0,1,2,3,4) +------------------------------------------------------*/ + +/*------------------------------------------------------ + u0c0 +------------------------------------------------------*/ +union byte_def u0c0_addr; +#define u0c0 u0c0_addr.byte + +#define clk0_u0c0 u0c0_addr.bit.b0 /* BRG count source select bit */ +#define clk1_u0c0 u0c0_addr.bit.b1 /* BRG count source select bit */ +#define crs_u0c0 u0c0_addr.bit.b2 /* CTS~/RTS~ function select bit */ +#define txept_u0c0 u0c0_addr.bit.b3 /* Transmit register empty flag */ +#define crd_u0c0 u0c0_addr.bit.b4 /* CTS~/RTS~ disable bit */ +#define nch_u0c0 u0c0_addr.bit.b5 /* Data output select bit */ +#define ckpol_u0c0 u0c0_addr.bit.b6 /* CLK polarity select bit */ +#define uform_u0c0 u0c0_addr.bit.b7 /* Transfer format select bit */ + +/*------------------------------------------------------ + u1c0 +------------------------------------------------------*/ +union byte_def u1c0_addr; +#define u1c0 u1c0_addr.byte + +#define clk0_u1c0 u1c0_addr.bit.b0 +#define clk1_u1c0 u1c0_addr.bit.b1 +#define crs_u1c0 u1c0_addr.bit.b2 +#define txept_u1c0 u1c0_addr.bit.b3 +#define crd_u1c0 u1c0_addr.bit.b4 +#define nch_u1c0 u1c0_addr.bit.b5 +#define ckpol_u1c0 u1c0_addr.bit.b6 +#define uform_u1c0 u1c0_addr.bit.b7 + +/*------------------------------------------------------ + u2c0 +------------------------------------------------------*/ +union byte_def u2c0_addr; +#define u2c0 u2c0_addr.byte + +#define clk0_u2c0 u2c0_addr.bit.b0 +#define clk1_u2c0 u2c0_addr.bit.b1 +#define crs_u2c0 u2c0_addr.bit.b2 +#define txept_u2c0 u2c0_addr.bit.b3 +#define crd_u2c0 u2c0_addr.bit.b4 +#define ckpol_u2c0 u2c0_addr.bit.b6 +#define uform_u2c0 u2c0_addr.bit.b7 + +/*------------------------------------------------------ + u3c0 +------------------------------------------------------*/ +union byte_def u3c0_addr; +#define u3c0 u3c0_addr.byte + +#define clk0_u3c0 u3c0_addr.bit.b0 +#define clk1_u3c0 u3c0_addr.bit.b1 +#define crs_u3c0 u3c0_addr.bit.b2 +#define txept_u3c0 u3c0_addr.bit.b3 +#define crd_u3c0 u3c0_addr.bit.b4 +#define nch_u3c0 u3c0_addr.bit.b5 +#define ckpol_u3c0 u3c0_addr.bit.b6 +#define uform_u3c0 u3c0_addr.bit.b7 + +/*------------------------------------------------------ + u4c0 +------------------------------------------------------*/ +union byte_def u4c0_addr; +#define u4c0 u4c0_addr.byte + +#define clk0_u4c0 u4c0_addr.bit.b0 +#define clk1_u4c0 u4c0_addr.bit.b1 +#define crs_u4c0 u4c0_addr.bit.b2 +#define txept_u4c0 u4c0_addr.bit.b3 +#define crd_u4c0 u4c0_addr.bit.b4 +#define nch_u4c0 u4c0_addr.bit.b5 +#define ckpol_u4c0 u4c0_addr.bit.b6 +#define uform_u4c0 u4c0_addr.bit.b7 + +/*------------------------------------------------------ + UARTi receive buffer register (i=0,1,2,3,4) +------------------------------------------------------*/ + +/*------------------------------------------------------ + u0rb +------------------------------------------------------*/ +#define u0rb u0rb_addr.word +#define u0rbl u0rb_addr.byte.low +#define u0rbh u0rb_addr.byte.high + +#define abt_u0rb u0rb_addr.bit.b11 /* Arbitration lost detect flag */ +#define oer_u0rb u0rb_addr.bit.b12 /* Overrun error flag */ +#define fer_u0rb u0rb_addr.bit.b13 /* Framing error flag */ +#define per_u0rb u0rb_addr.bit.b14 /* Parity error flag */ +#define sum_u0rb u0rb_addr.bit.b15 /* Error sum flag */ + +/*------------------------------------------------------ + u1rb +------------------------------------------------------*/ +#define u1rb u1rb_addr.word +#define u1rbl u1rb_addr.byte.low +#define u1rbh u1rb_addr.byte.high + +#define abt_u1rb u1rb_addr.bit.b11 +#define oer_u1rb u1rb_addr.bit.b12 +#define fer_u1rb u1rb_addr.bit.b13 +#define per_u1rb u1rb_addr.bit.b14 +#define sum_u1rb u1rb_addr.bit.b15 + +/*------------------------------------------------------ + u2rb +------------------------------------------------------*/ +#define u2rb u2rb_addr.word +#define u2rbl u2rb_addr.byte.low +#define u2rbh u2rb_addr.byte.high + +#define abt_u2rb u2rb_addr.bit.b11 +#define oer_u2rb u2rb_addr.bit.b12 +#define fer_u2rb u2rb_addr.bit.b13 +#define per_u2rb u2rb_addr.bit.b14 +#define sum_u2rb u2rb_addr.bit.b15 + +/*------------------------------------------------------ + u3rb +------------------------------------------------------*/ +#define u3rb u3rb_addr.word +#define u3rbl u3rb_addr.byte.low +#define u3rbh u3rb_addr.byte.high + +#define abt_u3rb u3rb_addr.bit.b11 +#define oer_u3rb u3rb_addr.bit.b12 +#define fer_u3rb u3rb_addr.bit.b13 +#define per_u3rb u3rb_addr.bit.b14 +#define sum_u3rb u3rb_addr.bit.b15 + +/*------------------------------------------------------ + u4rb +------------------------------------------------------*/ +#define u4rb u4rb_addr.word +#define u4rbl u4rb_addr.byte.low +#define u4rbh u4rb_addr.byte.high + +#define abt_u4rb u4rb_addr.bit.b11 +#define oer_u4rb u4rb_addr.bit.b12 +#define fer_u4rb u4rb_addr.bit.b13 +#define per_u4rb u4rb_addr.bit.b14 +#define sum_u4rb u4rb_addr.bit.b15 + +/*------------------------------------------------------ + UARTi (i= 0,1,2,3,4) special mode registers +------------------------------------------------------*/ + +/*------------------------------------------------------ + u0smr +------------------------------------------------------*/ +union byte_def u0smr_addr; +#define u0smr u0smr_addr.byte + +#define iicm_u0smr u0smr_addr.bit.b0 /* IIC mode select bit */ +#define abc_u0smr u0smr_addr.bit.b1 /* Arbitration lost detect flag control bit */ +#define bbs_u0smr u0smr_addr.bit.b2 /* Bus busy flag */ +#define lsyn_u0smr u0smr_addr.bit.b3 /* SCLL sync output enable bit */ +#define abscs_u0smr u0smr_addr.bit.b4 /* Bus conflict detect sampling clock select bit */ +#define acse_u0smr u0smr_addr.bit.b5 /* Auto clear function select bit for transmit enable bit */ +#define sss_u0smr u0smr_addr.bit.b6 /* Transmit start condition select bit */ +#define sclkdiv_u0smr u0smr_addr.bit.b7 /* Clock divide synchronous bit */ + +/*------------------------------------------------------ + u1smr +------------------------------------------------------*/ +union byte_def u1smr_addr; +#define u1smr u1smr_addr.byte + +#define iicm_u1smr u1smr_addr.bit.b0 +#define abc_u1smr u1smr_addr.bit.b1 +#define bbs_u1smr u1smr_addr.bit.b2 +#define lsyn_u1smr u1smr_addr.bit.b3 +#define abscs_u1smr u1smr_addr.bit.b4 +#define acse_u1smr u1smr_addr.bit.b5 +#define sss_u1smr u1smr_addr.bit.b6 +#define sclkdiv_u1smr u1smr_addr.bit.b7 + +/*------------------------------------------------------ + u2smr +------------------------------------------------------*/ +union byte_def u2smr_addr; +#define u2smr u2smr_addr.byte + +#define iicm_u2smr u2smr_addr.bit.b0 +#define abc_u2smr u2smr_addr.bit.b1 +#define bbs_u2smr u2smr_addr.bit.b2 +#define lsyn_u2smr u2smr_addr.bit.b3 +#define abscs_u2smr u2smr_addr.bit.b4 +#define acse_u2smr u2smr_addr.bit.b5 +#define sss_u2smr u2smr_addr.bit.b6 +#define sclkdiv_u2smr u2smr_addr.bit.b7 + +/*------------------------------------------------------ + u3smr +------------------------------------------------------*/ +union byte_def u3smr_addr; +#define u3smr u3smr_addr.byte + +#define iicm_u3smr u3smr_addr.bit.b0 +#define abc_u3smr u3smr_addr.bit.b1 +#define bbs_u3smr u3smr_addr.bit.b2 +#define lsyn_u3smr u3smr_addr.bit.b3 +#define abscs_u3smr u3smr_addr.bit.b4 +#define acse_u3smr u3smr_addr.bit.b5 +#define sss_u3smr u3smr_addr.bit.b6 +#define sclkdiv_u3smr u3smr_addr.bit.b7 + +/*------------------------------------------------------ + u4smr +------------------------------------------------------*/ +union byte_def u4smr_addr; +#define u4smr u4smr_addr.byte + +#define iicm_u4smr u4smr_addr.bit.b0 +#define abc_u4smr u4smr_addr.bit.b1 +#define bbs_u4smr u4smr_addr.bit.b2 +#define lsyn_u4smr u4smr_addr.bit.b3 +#define abscs_u4smr u4smr_addr.bit.b4 +#define acse_u4smr u4smr_addr.bit.b5 +#define sss_u4smr u4smr_addr.bit.b6 +#define sclkdiv_u4smr u4smr_addr.bit.b7 + +/*------------------------------------------------------ + UARTi (i=0,1,2,3,4) special mode register 2 +------------------------------------------------------*/ + +/*------------------------------------------------------ + u0smr2 +------------------------------------------------------*/ +union byte_def u0smr2_addr; +#define u0smr2 u0smr2_addr.byte + +#define iicm2_u0smr2 u0smr2_addr.bit.b0 /* IIC mode select bit2 */ +#define csc_u0smr2 u0smr2_addr.bit.b1 /* Clock synchronous bit */ +#define swc_u0smr2 u0smr2_addr.bit.b2 /* SCL wait output bit */ +#define als_u0smr2 u0smr2_addr.bit.b3 /* SDA output stop bit */ +#define stc_u0smr2 u0smr2_addr.bit.b4 /* UARTi initialize bit */ +#define swc2_u0smr2 u0smr2_addr.bit.b5 /* SCL wait output bit2 */ +#define sdhi_u0smr2 u0smr2_addr.bit.b6 /* SDA output inhibit bit */ +#define su1him_u0smr2 u0smr2_addr.bit.b7 /* External clock synchronous enable bit */ + + +/*------------------------------------------------------ + u1smr2 +------------------------------------------------------*/ +union byte_def u1smr2_addr; +#define u1smr2 u1smr2_addr.byte + +#define iicm2_u1smr2 u1smr2_addr.bit.b0 +#define csc_u1smr2 u1smr2_addr.bit.b1 +#define swc_u1smr2 u1smr2_addr.bit.b2 +#define als_u1smr2 u1smr2_addr.bit.b3 +#define stc_u1smr2 u1smr2_addr.bit.b4 +#define swc2_u1smr2 u1smr2_addr.bit.b5 +#define sdhi_u1smr2 u1smr2_addr.bit.b6 +#define su1him_u1smr2 u1smr2_addr.bit.b7 + +/*------------------------------------------------------ + u2smr2 +------------------------------------------------------*/ +union byte_def u2smr2_addr; +#define u2smr2 u2smr2_addr.byte + +#define iicm2_u2smr2 u2smr2_addr.bit.b0 +#define csc_u2smr2 u2smr2_addr.bit.b1 +#define swc_u2smr2 u2smr2_addr.bit.b2 +#define als_u2smr2 u2smr2_addr.bit.b3 +#define stc_u2smr2 u2smr2_addr.bit.b4 +#define swc2_u2smr2 u2smr2_addr.bit.b5 +#define sdhi_u2smr2 u2smr2_addr.bit.b6 +#define su1him_u2smr2 u2smr2_addr.bit.b7 + +/*------------------------------------------------------ + u3smr2 +------------------------------------------------------*/ +union byte_def u3smr2_addr; +#define u3smr2 u3smr2_addr.byte + +#define iicm2_u3smr2 u3smr2_addr.bit.b0 +#define csc_u3smr2 u3smr2_addr.bit.b1 +#define swc_u3smr2 u3smr2_addr.bit.b2 +#define als_u3smr2 u3smr2_addr.bit.b3 +#define stc_u3smr2 u3smr2_addr.bit.b4 +#define swc2_u3smr2 u3smr2_addr.bit.b5 +#define sdhi_u3smr2 u3smr2_addr.bit.b6 +#define su1him_u3smr2 u3smr2_addr.bit.b7 + +/*------------------------------------------------------ + u4smr2 +------------------------------------------------------*/ +union byte_def u4smr2_addr; +#define u4smr2 u4smr2_addr.byte + +#define iicm2_u4smr2 u4smr2_addr.bit.b0 +#define csc_u4smr2 u4smr2_addr.bit.b1 +#define swc_u4smr2 u4smr2_addr.bit.b2 +#define als_u4smr2 u4smr2_addr.bit.b3 +#define stc_u4smr2 u4smr2_addr.bit.b4 +#define swc2_u4smr2 u4smr2_addr.bit.b5 +#define sdhi_u4smr2 u4smr2_addr.bit.b6 +#define su1him_u4smr2 u4smr2_addr.bit.b7 + +/*------------------------------------------------------ + UARTi (i=0,1,2,3,4) special mode register 3 +------------------------------------------------------*/ + +/*------------------------------------------------------ + u0smr3 +------------------------------------------------------*/ +union byte_def u0smr3_addr; +#define u0smr3 u0smr3_addr.byte + +#define sse_u0smr3 u0smr3_addr.bit.b0 /* SS pin function enable bit */ +#define ckph_u0smr3 u0smr3_addr.bit.b1 /* Clock-phase set bit */ +#define dinc_u0smr3 u0smr3_addr.bit.b2 /* Serial input port set bit */ +#define nodc_u0smr3 u0smr3_addr.bit.b3 /* Clock output select bit */ +#define err_u0smr3 u0smr3_addr.bit.b4 /* Fault error flag */ +#define dl0_u0smr3 u0smr3_addr.bit.b5 /* (b7-b5) SDAi digital delay time set bit */ +#define dl1_u0smr3 u0smr3_addr.bit.b6 +#define dl2_u0smr3 u0smr3_addr.bit.b7 + +/*------------------------------------------------------ + u1smr3 +------------------------------------------------------*/ +union byte_def u1smr3_addr; +#define u1smr3 u1smr3_addr.byte + +#define sse_u1smr3 u1smr3_addr.bit.b0 +#define ckph_u1smr3 u1smr3_addr.bit.b1 +#define dinc_u1smr3 u1smr3_addr.bit.b2 +#define nodc_u1smr3 u1smr3_addr.bit.b3 +#define err_u1smr3 u1smr3_addr.bit.b4 +#define dl0_u1smr3 u1smr3_addr.bit.b5 +#define dl1_u1smr3 u1smr3_addr.bit.b6 +#define dl2_u1smr3 u1smr3_addr.bit.b7 + +/*------------------------------------------------------ + u2smr3 +------------------------------------------------------*/ +union byte_def u2smr3_addr; +#define u2smr3 u2smr3_addr.byte + +#define sse_u2smr3 u2smr3_addr.bit.b0 +#define ckph_u2smr3 u2smr3_addr.bit.b1 +#define dinc_u2smr3 u2smr3_addr.bit.b2 +#define nodc_u2smr3 u2smr3_addr.bit.b3 +#define err_u2smr3 u2smr3_addr.bit.b4 +#define dl0_u2smr3 u2smr3_addr.bit.b5 +#define dl1_u2smr3 u2smr3_addr.bit.b6 +#define dl2_u2smr3 u2smr3_addr.bit.b7 + +/*------------------------------------------------------ + u3smr3 +------------------------------------------------------*/ +union byte_def u3smr3_addr; +#define u3smr3 u3smr3_addr.byte + +#define sse_u3smr3 u3smr3_addr.bit.b0 +#define ckph_u3smr3 u3smr3_addr.bit.b1 +#define dinc_u3smr3 u3smr3_addr.bit.b2 +#define nodc_u3smr3 u3smr3_addr.bit.b3 +#define err_u3smr3 u3smr3_addr.bit.b4 +#define dl0_u3smr3 u3smr3_addr.bit.b5 +#define dl1_u3smr3 u3smr3_addr.bit.b6 +#define dl2_u3smr3 u3smr3_addr.bit.b7 + +/*------------------------------------------------------ + u4smr3 +------------------------------------------------------*/ +union byte_def u4smr3_addr; +#define u4smr3 u4smr3_addr.byte + +#define sse_u4smr3 u4smr3_addr.bit.b0 +#define ckph_u4smr3 u4smr3_addr.bit.b1 +#define dinc_u4smr3 u4smr3_addr.bit.b2 +#define nodc_u4smr3 u4smr3_addr.bit.b3 +#define err_u4smr3 u4smr3_addr.bit.b4 +#define dl0_u4smr3 u4smr3_addr.bit.b5 +#define dl1_u4smr3 u4smr3_addr.bit.b6 +#define dl2_u4smr3 u4smr3_addr.bit.b7 + +/*------------------------------------------------------ + UARTi (i=0,1,2,3,4) special mode register 4 +------------------------------------------------------*/ + +/*------------------------------------------------------ + u0smr4 +------------------------------------------------------*/ +union byte_def u0smr4_addr; +#define u0smr4 u0smr4_addr.byte + +#define stareq_u0smr4 u0smr4_addr.bit.b0 /* Start condition generate bit */ +#define rstareq_u0smr4 u0smr4_addr.bit.b1 /* Restart condition generate bit */ +#define stpreq_u0smr4 u0smr4_addr.bit.b2 /* Stop condition generate bit */ +#define stspsel_u0smr4 u0smr4_addr.bit.b3 /* SCL, SDA output select bit */ +#define ackd_u0smr4 u0smr4_addr.bit.b4 /* ACK data bit */ +#define ackc_u0smr4 u0smr4_addr.bit.b5 /* ACK data output enable bit */ +#define sclhi_u0smr4 u0smr4_addr.bit.b6 /* SCL output stop enable bit */ +#define swc9_u0smr4 u0smr4_addr.bit.b7 /* SCL wait output bit */ + + +/*------------------------------------------------------ + u1smr4 +------------------------------------------------------*/ +union byte_def u1smr4_addr; +#define u1smr4 u1smr4_addr.byte + +#define stareq_u1smr4 u1smr4_addr.bit.b0 +#define rstareq_u1smr4 u1smr4_addr.bit.b1 +#define stpreq_u1smr4 u1smr4_addr.bit.b2 +#define stspsel_u1smr4 u1smr4_addr.bit.b3 +#define ackd_u1smr4 u1smr4_addr.bit.b4 +#define ackc_u1smr4 u1smr4_addr.bit.b5 +#define sclhi_u1smr4 u1smr4_addr.bit.b6 +#define swc9_u1smr4 u1smr4_addr.bit.b7 + + +/*------------------------------------------------------ + u2smr4 +------------------------------------------------------*/ +union byte_def u2smr4_addr; +#define u2smr4 u2smr4_addr.byte + +#define stareq_u2smr4 u2smr4_addr.bit.b0 +#define rstareq_u2smr4 u2smr4_addr.bit.b1 +#define stpreq_u2smr4 u2smr4_addr.bit.b2 +#define stspsel_u2smr4 u2smr4_addr.bit.b3 +#define ackd_u2smr4 u2smr4_addr.bit.b4 +#define ackc_u2smr4 u2smr4_addr.bit.b5 +#define sclhi_u2smr4 u2smr4_addr.bit.b6 +#define swc9_u2smr4 u2smr4_addr.bit.b7 + + +/*------------------------------------------------------ + u3smr4 +------------------------------------------------------*/ +union byte_def u3smr4_addr; +#define u3smr4 u3smr4_addr.byte + +#define stareq_u3smr4 u3smr4_addr.bit.b0 +#define rstareq_u3smr4 u3smr4_addr.bit.b1 +#define stpreq_u3smr4 u3smr4_addr.bit.b2 +#define stspsel_u3smr4 u3smr4_addr.bit.b3 +#define ackd_u3smr4 u3smr4_addr.bit.b4 +#define ackc_u3smr4 u3smr4_addr.bit.b5 +#define sclhi_u3smr4 u3smr4_addr.bit.b6 +#define swc9_u3smr4 u3smr4_addr.bit.b7 + +/*------------------------------------------------------ + u4smr4 +------------------------------------------------------*/ +union byte_def u4smr4_addr; +#define u4smr4 u4smr4_addr.byte + +#define stareq_u4smr4 u4smr4_addr.bit.b0 +#define rstareq_u4smr4 u4smr4_addr.bit.b1 +#define stpreq_u4smr4 u4smr4_addr.bit.b2 +#define stspsel_u4smr4 u4smr4_addr.bit.b3 +#define ackd_u4smr4 u4smr4_addr.bit.b4 +#define ackc_u4smr4 u4smr4_addr.bit.b5 +#define sclhi_u4smr4 u4smr4_addr.bit.b6 +#define swc9_u4smr4 u4smr4_addr.bit.b7 + +/*------------------------------------------------------ + DMAi request factor select register +------------------------------------------------------*/ + +/*------------------------------------------------------ + dm0sl +------------------------------------------------------*/ +union byte_def dm0sl_addr; +#define dm0sl dm0sl_addr.byte + +#define dsel0_dm0sl dm0sl_addr.bit.b0 /* DMA request cause select bit */ +#define dsel1_dm0sl dm0sl_addr.bit.b1 /* DMA request cause select bit */ +#define dsel2_dm0sl dm0sl_addr.bit.b2 /* DMA request cause select bit */ +#define dsel3_dm0sl dm0sl_addr.bit.b3 /* DMA request cause select bit */ +#define dsel4_dm0sl dm0sl_addr.bit.b4 /* DMA request cause select bit */ +#define dsr_dm0sl dm0sl_addr.bit.b5 /* Software DMA request bit */ +#define drq_dm0sl dm0sl_addr.bit.b7 /* DMA request bit */ + +/*------------------------------------------------------ + dm1sl +------------------------------------------------------*/ +union byte_def dm1sl_addr; +#define dm1sl dm1sl_addr.byte + +#define dsel0_dm1sl dm1sl_addr.bit.b0 +#define dsel1_dm1sl dm1sl_addr.bit.b1 +#define dsel2_dm1sl dm1sl_addr.bit.b2 +#define dsel3_dm1sl dm1sl_addr.bit.b3 +#define dsel4_dm1sl dm1sl_addr.bit.b4 +#define dsr_dm1sl dm1sl_addr.bit.b5 +#define drq_dm1sl dm1sl_addr.bit.b7 + +/*------------------------------------------------------ + dm2sl +------------------------------------------------------*/ +union byte_def dm2sl_addr; +#define dm2sl dm2sl_addr.byte + +#define dsel0_dm2sl dm2sl_addr.bit.b0 +#define dsel1_dm2sl dm2sl_addr.bit.b1 +#define dsel2_dm2sl dm2sl_addr.bit.b2 +#define dsel3_dm2sl dm2sl_addr.bit.b3 +#define dsel4_dm2sl dm2sl_addr.bit.b4 +#define dsr_dm2sl dm2sl_addr.bit.b5 +#define drq_dm2sl dm2sl_addr.bit.b7 + +/*------------------------------------------------------ + dm3sl +------------------------------------------------------*/ +union byte_def dm3sl_addr; +#define dm3sl dm3sl_addr.byte + +#define dsel0_dm3sl dm3sl_addr.bit.b0 +#define dsel1_dm3sl dm3sl_addr.bit.b1 +#define dsel2_dm3sl dm3sl_addr.bit.b2 +#define dsel3_dm3sl dm3sl_addr.bit.b3 +#define dsel4_dm3sl dm3sl_addr.bit.b4 +#define dsr_dm3sl dm3sl_addr.bit.b5 +#define drq_dm3sl dm3sl_addr.bit.b7 + +/******************************************************** +* declare SFR union * +********************************************************/ + +union{ + struct{ + char b0:1; + char b1:1; + char b2:1; + char b3:1; + char b4:1; + char b5:1; + char b6:1; + char b7:1; + char b8:1; + char b9:1; + char b10:1; + char b11:1; + char b12:1; + char b13:1; + char b14:1; + char b15:1; + char b16:1; + char b17:1; + char b18:1; + char b19:1; + char b20:1; + char b21:1; + char b22:1; + char b23:1; + }bit; + struct{ + char low; /* low 8 bit */ + char mid; /* mid 8 bit */ + char high; /* high 8 bit */ + char nc; /* non use */ + }byte; + unsigned long dword; +}rmad0_addr,rmad1_addr,rmad2_addr,rmad3_addr, + rmad4_addr,rmad5_addr,rmad6_addr,rmad7_addr; +#define rmad0 rmad0_addr.dword /* Address match interrupt register 0 32 bit */ +#define rmad0l rmad0_addr.byte.low /* Address match interrupt register 0 low 8 bit */ +#define rmad0m rmad0_addr.byte.mid /* Address match interrupt register 0 mid 8 bit */ +#define rmad0h rmad0_addr.byte.high /* Address match interrupt register 0 high 8 bit */ +#define rmad1 rmad1_addr.dword /* Address match interrupt register 1 32 bit */ +#define rmad1l rmad1_addr.byte.low /* Address match interrupt register 1 low 8 bit */ +#define rmad1m rmad1_addr.byte.mid /* Address match interrupt register 1 mid 8 bit */ +#define rmad1h rmad1_addr.byte.high /* Address match interrupt register 1 high 8 bit */ +#define rmad2 rmad2_addr.dword /* Address match interrupt register 2 32 bit */ +#define rmad2l rmad2_addr.byte.low /* Address match interrupt register 2 low 8 bit */ +#define rmad2m rmad2_addr.byte.mid /* Address match interrupt register 2 mid 8 bit */ +#define rmad2h rmad2_addr.byte.high /* Address match interrupt register 2 high 8 bit */ +#define rmad3 rmad3_addr.dword /* Address match interrupt register 3 32 bit */ +#define rmad3l rmad3_addr.byte.low /* Address match interrupt register 3 low 8 bit */ +#define rmad3m rmad3_addr.byte.mid /* Address match interrupt register 3 mid 8 bit */ +#define rmad3h rmad3_addr.byte.high /* Address match interrupt register 3 high 8 bit */ +#define rmad4 rmad4_addr.dword /* Address match interrupt register 4 32 bit */ +#define rmad4l rmad4_addr.byte.low /* Address match interrupt register 3 low 8 bit */ +#define rmad4m rmad4_addr.byte.mid /* Address match interrupt register 3 mid 8 bit */ +#define rmad4h rmad4_addr.byte.high /* Address match interrupt register 3 high 8 bit */ +#define rmad5 rmad5_addr.dword /* Address match interrupt register 5 32 bit */ +#define rmad5l rmad5_addr.byte.low /* Address match interrupt register 3 low 8 bit */ +#define rmad5m rmad5_addr.byte.mid /* Address match interrupt register 3 mid 8 bit */ +#define rmad5h rmad5_addr.byte.high /* Address match interrupt register 3 high 8 bit */ +#define rmad6 rmad6_addr.dword /* Address match interrupt register 6 32 bit */ +#define rmad6l rmad6_addr.byte.low /* Address match interrupt register 3 low 8 bit */ +#define rmad6m rmad6_addr.byte.mid /* Address match interrupt register 3 mid 8 bit */ +#define rmad6h rmad6_addr.byte.high /* Address match interrupt register 3 high 8 bit */ +#define rmad7 rmad7_addr.dword /* Address match interrupt register 7 32 bit */ +#define rmad7l rmad7_addr.byte.low /* Address match interrupt register 3 low 8 bit */ +#define rmad7m rmad7_addr.byte.mid /* Address match interrupt register 3 mid 8 bit */ +#define rmad7h rmad7_addr.byte.high /* Address match interrupt register 3 high 8 bit */ + + +union{ + struct{ + char b0:1; + char b1:1; + char b2:1; + char b3:1; + char b4:1; + char b5:1; + char b6:1; + char b7:1; + char b8:1; + char b9:1; + char b10:1; + char b11:1; + char b12:1; + char b13:1; + char b14:1; + char b15:1; + }bit; + struct{ + char low; /* low 8 bit */ + char high; /* high 8 bit */ + }byte; + unsigned short word; +}u0tb_addr,u1tb_addr,u2tb_addr,u3tb_addr,u4tb_addr,crcd_addr, + ad00_addr,ad01_addr,ad02_addr,ad03_addr,ad04_addr,ad05_addr,ad06_addr,ad07_addr, + x0r_addr,y0r_addr,x1r_addr,y1r_addr,x2r_addr,y2r_addr,x3r_addr,y3r_addr,x4r_addr,y4r_addr, + x5r_addr,y5r_addr,x6r_addr,y6r_addr,x7r_addr,y7r_addr,x8r_addr,y8r_addr, + x9r_addr,y9r_addr,x10r_addr,y10r_addr,x11r_addr,y11r_addr,x12r_addr,y12r_addr, + x13r_addr,y13r_addr,x14r_addr,y14r_addr,x15r_addr,y15r_addr, + + g0tcrc_addr,g1tcrc_addr,g0rcrc_addr,g1rcrc_addr, + g0rb_addr,g1rb_addr, + u0rb_addr,u1rb_addr,u2rb_addr,u3rb_addr,u4rb_addr, + plc_addr; + +/*------------------------------------------------------ + UARTi transmit buffer register (i=0,1,2,3,4) + (1) The MOV instruction should be used to set the UiTB register +------------------------------------------------------*/ +#define u0tb u0tb_addr.word /* UART0 Transmit buffer register 16 bit */ +#define u0tbl u0tb_addr.byte.low /* UART0 Transmit buffer register low 8 bit */ +#define u0tbh u0tb_addr.byte.high /* UART0 Transmit buffer register high 8 bit */ +#define u1tb u1tb_addr.word /* UART1 Transmit buffer register 16 bit */ +#define u1tbl u1tb_addr.byte.low /* UART1 Transmit buffer register low 8 bit */ +#define u1tbh u1tb_addr.byte.high /* UART1 Transmit buffer register high 8 bit */ +#define u2tb u2tb_addr.word /* UART2 Transmit buffer register 16 bit */ +#define u2tbl u2tb_addr.byte.low /* UART2 Transmit buffer register low 8 bit */ +#define u2tbh u2tb_addr.byte.high /* UART2 Transmit buffer register high 8 bit */ +#define u3tb u3tb_addr.word /* UART3 Transmit buffer register 16 bit */ +#define u3tbl u3tb_addr.byte.low /* UART3 Transmit buffer register low 8 bit */ +#define u3tbh u3tb_addr.byte.high /* UART3 Transmit buffer register high 8 bit */ +#define u4tb u4tb_addr.word /* UART4 Transmit buffer register 16 bit */ +#define u4tbl u4tb_addr.byte.low /* UART4 Transmit buffer register low 8 bit */ +#define u4tbh u4tb_addr.byte.high /* UART4 Transmit buffer register high 8 bit */ + +/*------------------------------------------------------ + CRC data register +------------------------------------------------------*/ +#define crcd crcd_addr.word /* CRC data register 16 bit */ +#define crcdl crcd_addr.byte.low /* CRC data register low 8 bit */ +#define crcdh crcd_addr.byte.high /* CRC data register high 8 bit */ + +/*------------------------------------------------------ + A/D0 register i (i=0 to7) +------------------------------------------------------*/ +#define ad00 ad00_addr.word /* A/D0 register 0 16 bit */ +#define ad00l ad00_addr.byte.low /* A/D0 register 0 low 8 bit */ +#define ad00h ad00_addr.byte.high /* A/D0 register 0 high 8 bit */ +#define ad01 ad01_addr.word /* A/D0 register 1 16 bit */ +#define ad01l ad01_addr.byte.low /* A/D0 register 1 low 8 bit */ +#define ad01h ad01_addr.byte.high /* A/D0 register 1 high 8 bit */ +#define ad02 ad02_addr.word /* A/D0 register 2 16 bit */ +#define ad02l ad02_addr.byte.low /* A/D0 register 2 low 8 bit */ +#define ad02h ad02_addr.byte.high /* A/D0 register 2 high 8 bit */ +#define ad03 ad03_addr.word /* A/D0 register 3 16 bit */ +#define ad03l ad03_addr.byte.low /* A/D0 register 3 low 8 bit */ +#define ad03h ad03_addr.byte.high /* A/D0 register 3 high 8 bit */ +#define ad04 ad04_addr.word /* A/D0 register 4 16 bit */ +#define ad04l ad04_addr.byte.low /* A/D0 register 4 low 8 bit */ +#define ad04h ad04_addr.byte.high /* A/D0 register 4 high 8 bit */ +#define ad05 ad05_addr.word /* A/D0 register 5 16 bit */ +#define ad05l ad05_addr.byte.low /* A/D0 register 5 low 8 bit */ +#define ad05h ad05_addr.byte.high /* A/D0 register 5 high 8 bit */ +#define ad06 ad06_addr.word /* A/D0 register 6 16 bit */ +#define ad06l ad06_addr.byte.low /* A/D0 register 6 low 8 bit */ +#define ad06h ad06_addr.byte.high /* A/D0 register 6 high 8 bit */ +#define ad07 ad07_addr.word /* A/D0 register 7 16 bit */ +#define ad07l ad07_addr.byte.low /* A/D0 register 7 low 8 bit */ +#define ad07h ad07_addr.byte.high /* A/D0 register 7 high 8 bit */ + + +#define x0r x0r_addr.word /* X-Y Conversion */ +#define x0rl x0r_addr.byte.low +#define x0rh x0r_addr.byte.high +#define y0r y0r_addr.word +#define y0rl y0r_addr.byte.low +#define y0rh y0r_addr.byte.high +#define x1r x1r_addr.word +#define x1rl x1r_addr.byte.low +#define x1rh x1r_addr.byte.high +#define y1r y1r_addr.word +#define y1rl y1r_addr.byte.low +#define y1rh y1r_addr.byte.high +#define x2r x2r_addr.word +#define x2rl x2r_addr.byte.low +#define x2rh x2r_addr.byte.high +#define y2r y2r_addr.word +#define y2rl y2r_addr.byte.low +#define y2rh y2r_addr.byte.high +#define x3r x3r_addr.word +#define x3rl x3r_addr.byte.low +#define x3rh x3r_addr.byte.high +#define y3r y3r_addr.word +#define y3rl y3r_addr.byte.low +#define y3rh y3r_addr.byte.high +#define x4r x4r_addr.word +#define x4rl x4r_addr.byte.low +#define x4rh x4r_addr.byte.high +#define y4r y4r_addr.word +#define y4rl y4r_addr.byte.low +#define y4rh y4r_addr.byte.high +#define x5r x5r_addr.word +#define x5rl x5r_addr.byte.low +#define x5rh x5r_addr.byte.high +#define y5r y5r_addr.word +#define y5rl y5r_addr.byte.low +#define y5rh y5r_addr.byte.high +#define x6r x6r_addr.word +#define x6rl x6r_addr.byte.low +#define x6rh x6r_addr.byte.high +#define y6r y6r_addr.word +#define y6rl y6r_addr.byte.low +#define y6rh y6r_addr.byte.high +#define x7r x7r_addr.word +#define x7rl x7r_addr.byte.low +#define x7rh x7r_addr.byte.high +#define y7r y7r_addr.word +#define y7rl y7r_addr.byte.low +#define y7rh y7r_addr.byte.high +#define x8r x8r_addr.word +#define x8rl x8r_addr.byte.low +#define x8rh x8r_addr.byte.high +#define y8r y8r_addr.word +#define y8rl y8r_addr.byte.low +#define y8rh y8r_addr.byte.high +#define x9r x9r_addr.word +#define x9rl x9r_addr.byte.low +#define x9rh x9r_addr.byte.high +#define y9r y9r_addr.word +#define y9rl y9r_addr.byte.low +#define y9rh y9r_addr.byte.high +#define x10r x10r_addr.word +#define x10rl x10r_addr.byte.low +#define x10rh x10r_addr.byte.high +#define y10r y10r_addr.word +#define y10rl y10r_addr.byte.low +#define y10rh y10r_addr.byte.high +#define x11r x11r_addr.word +#define x11rl x11r_addr.byte.low +#define x11rh x11r_addr.byte.high +#define y11r y11r_addr.word +#define y11rl y11r_addr.byte.low +#define y11rh y11r_addr.byte.high +#define x12r x12r_addr.word +#define x12rl x12r_addr.byte.low +#define x12rh x12r_addr.byte.high +#define y12r y12r_addr.word +#define y12rl y12r_addr.byte.low +#define y12rh y12r_addr.byte.high +#define x13r x13r_addr.word +#define x13rl x13r_addr.byte.low +#define x13rh x13r_addr.byte.high +#define y13r y13r_addr.word +#define y13rl y13r_addr.byte.low +#define y13rh y13r_addr.byte.high +#define x14r x14r_addr.word +#define x14rl x14r_addr.byte.low +#define x14rh x14r_addr.byte.high +#define y14r y14r_addr.word +#define y14rl y14r_addr.byte.low +#define y14rh y14r_addr.byte.high +#define x15r x15r_addr.word +#define x15rl x15r_addr.byte.low +#define x15rh x15r_addr.byte.high +#define y15r y15r_addr.word +#define y15rl y15r_addr.byte.low +#define y15rh y15r_addr.byte.high + + diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/sfr32c80.inc b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/sfr32c80.inc new file mode 100644 index 00000000..d5c2de1b --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/sfr32c80.inc @@ -0,0 +1,2718 @@ +;------------------------------------------------------------------------ +; | +; FILE :sfr32c80.inc | +; DATE :Thu, Feb 27, 2014 | +; DESCRIPTION :define the sfr register. (for Assembler language) | +; CPU GROUP :80 | +; | +; This file is generated by Renesas Project Generator (Ver.4.18). | +; NOTE:THIS IS A TYPICAL EXAMPLE. | +;------------------------------------------------------------------------ + +;**************************************************************************************** +;* * +;* File name : sfr32c80.inc * +;* Contents : Definition of M32C/80 Group SFR * +;* * +;* Copyright (C) 2003 (2010) Renesas Electronics Corporation. * +;* and Renesas Solutions Corporation. All rights reserved. * +;* * +;* Version : Ver 0.01 (05-12-08) Preliminary * +;* These data made based on M32C/80 Group H/W Manual Rev.0.30 * +;* * +;**************************************************************************************** +; +; note: +; This data is a freeware that SFR for M32C/80 group is described. +; RENESAS ELECTRONICS CORPORATION and RENESAS SOLUTIONS CORPORATION assume +; no responsibility for any damage that occurred by this data. +; +;-------------------------------------------------------------------- +; +; CPU +; +; +;-------------------------------------------------------------------- +; Processor Mode Register 0 adr:0004h +;-------------------------------------------------------------------- +pm0 .equ 0004h +pm00 .btequ 0,pm0 +pm01 .btequ 1,pm0 +pm02 .btequ 2,pm0 +pm03 .btequ 3,pm0 +pm04 .btequ 4,pm0 +pm05 .btequ 5,pm0 +pm07 .btequ 7,pm0 +;-------------------------------------------------------------------- +; Processor Mode Register 1 adr:0005h +;-------------------------------------------------------------------- +pm1 .equ 0005h +pm10 .btequ 0,pm1 +pm11 .btequ 1,pm1 +pm12 .btequ 2,pm1 +pm13 .btequ 3,pm1 +pm14 .btequ 4,pm1 +pm15 .btequ 5,pm1 +;-------------------------------------------------------------------- +; System Clock Control Register 0 adr:0006h +;-------------------------------------------------------------------- +cm0 .equ 0006h +cm00 .btequ 0,cm0 +cm01 .btequ 1,cm0 +cm02 .btequ 2,cm0 +cm03 .btequ 3,cm0 +cm04 .btequ 4,cm0 +cm05 .btequ 5,cm0 +cm06 .btequ 6,cm0 +cm07 .btequ 7,cm0 +;-------------------------------------------------------------------- +; System Clock Control Register 1 adr:0007h +;-------------------------------------------------------------------- +cm1 .equ 0007h +cm10 .btequ 0,cm1 +cm17 .btequ 7,cm1 +;-------------------------------------------------------------------- +; Address Match Interrupt Enable Register adr:0009h +;-------------------------------------------------------------------- +aier .equ 0009h +aier0 .btequ 0,aier +aier1 .btequ 1,aier +aier2 .btequ 2,aier +aier3 .btequ 3,aier +aier4 .btequ 4,aier +aier5 .btequ 5,aier +aier6 .btequ 6,aier +aier7 .btequ 7,aier +;-------------------------------------------------------------------- +; Protect Register adr:000ah +;-------------------------------------------------------------------- +prcr .equ 000ah +prc0 .btequ 0,prcr +prc1 .btequ 1,prcr +prc2 .btequ 2,prcr +prc3 .btequ 3,prcr +;-------------------------------------------------------------------- +; Outer Data-bus Width Register adr:000bh +;-------------------------------------------------------------------- +ds .equ 000bh +ds0 .btequ 0,ds +ds1 .btequ 1,ds +ds2 .btequ 2,ds +ds3 .btequ 3,ds +;-------------------------------------------------------------------- +; Main Clock Decode Register adr:000ch +;-------------------------------------------------------------------- +mcd .equ 000ch +mcd0 .btequ 0,mcd +mcd1 .btequ 1,mcd +mcd2 .btequ 2,mcd +mcd3 .btequ 3,mcd +mcd4 .btequ 4,mcd +;-------------------------------------------------------------------- +; Oscillation Stop Detection Register adr:000dh +;-------------------------------------------------------------------- +cm2 .equ 000dh +cm20 .btequ 0,cm2 +cm21 .btequ 1,cm2 +cm22 .btequ 2,cm2 +cm23 .btequ 3,cm2 +;-------------------------------------------------------------------- +; Watchdog Timer Register adr:000eh +;-------------------------------------------------------------------- +wdts .equ 000eh +;-------------------------------------------------------------------- +; Watchdog Timer Control Register adr:000fh +;-------------------------------------------------------------------- +wdc .equ 000fh +wdc5 .btequ 5,wdc +wdc7 .btequ 7,wdc +;-------------------------------------------------------------------- +; Address Match Interrupt Register 0 adr:0012h-0010h +;-------------------------------------------------------------------- +rmad0 .equ 0010h +rmad0l .equ rmad0 +rmad0m .equ rmad0+1 +rmad0h .equ rmad0+2 +;-------------------------------------------------------------------- +; Processor Mode Register 2 adr:0013h +;-------------------------------------------------------------------- +pm2 .equ 0013h +pm21 .btequ 1,pm2 +pm22 .btequ 2,pm2 +pm24 .btequ 4,pm2 +pm25 .btequ 5,pm2 +pm26 .btequ 6,pm2 +pm27 .btequ 7,pm2 +;-------------------------------------------------------------------- +; Address Match Interrupt Register 1 adr:0016h-0014h +;-------------------------------------------------------------------- +rmad1 .equ 0014h +rmad1l .equ rmad1 +rmad1m .equ rmad1+1 +rmad1h .equ rmad1+2 +;-------------------------------------------------------------------- +; VDC Control Register 2 adr:0017h +;-------------------------------------------------------------------- +vcr2 .equ 0017h +vc26 .btequ 6,vcr2 +vc27 .btequ 7,vcr2 +;-------------------------------------------------------------------- +; Address Match Interrupt Register 2 adr:001ah-0018h +;-------------------------------------------------------------------- +rmad2 .equ 0018h +rmad2l .equ rmad2 +rmad2m .equ rmad2+1 +rmad2h .equ rmad2+2 +;-------------------------------------------------------------------- +; VDC Control Register 1 adr:001bh +;-------------------------------------------------------------------- +vcr1 .equ 001bh +vc13 .btequ 3,vcr1 +;-------------------------------------------------------------------- +; Address Match Interrupt Register 3 adr:001eh-001ch +;-------------------------------------------------------------------- +rmad3 .equ 001ch +rmad3l .equ rmad3 +rmad3m .equ rmad3+1 +rmad3h .equ rmad3+2 +;-------------------------------------------------------------------- +; Pll Control Register adr:0026h +;-------------------------------------------------------------------- +plc .equ 0026h +;-------------------------------------------------------------------- +; Pll Control Register 0 adr:0026h +;-------------------------------------------------------------------- +plc0 .equ 0026h +plc00 .btequ 0,plc0 +plc01 .btequ 1,plc0 +plc02 .btequ 2,plc0 +plc07 .btequ 7,plc0 +;-------------------------------------------------------------------- +; Pll Control Register 1 adr:0027h +;-------------------------------------------------------------------- +plc1 .equ 0027h +plc12 .btequ 2,plc1 +;-------------------------------------------------------------------- +; Address Match Interrupt Register 4 adr:002ah-0028h +;-------------------------------------------------------------------- +rmad4 .equ 0028h +rmad4l .equ rmad4 +rmad4m .equ rmad4+1 +rmad4h .equ rmad4+2 +;-------------------------------------------------------------------- +; Address Match Interrupt Register 5 adr:002eh-002ch +;-------------------------------------------------------------------- +rmad5 .equ 002ch +rmad5l .equ rmad5 +rmad5m .equ rmad5+1 +rmad5h .equ rmad5+2 +;-------------------------------------------------------------------- +; Address Match Interrupt Register 6 adr:003ah-0038h +;-------------------------------------------------------------------- +rmad6 .equ 0038h +rmad6l .equ rmad6 +rmad6m .equ rmad6+1 +rmad6h .equ rmad6+2 +;-------------------------------------------------------------------- +; Address Match Interrupt Register 7 adr:003eh-003ch +;-------------------------------------------------------------------- +rmad7 .equ 003ch +rmad7l .equ rmad7 +rmad7m .equ rmad7+1 +rmad7h .equ rmad7+2 +;-------------------------------------------------------------------- +; External Area Wait Control Register 0 adr:0048h +;-------------------------------------------------------------------- +ewcr0 .equ 0048h +ewcr000 .btequ 0,ewcr0 +ewcr001 .btequ 1,ewcr0 +ewcr002 .btequ 2,ewcr0 +ewcr003 .btequ 3,ewcr0 +ewcr004 .btequ 4,ewcr0 +ewcr006 .btequ 6,ewcr0 +;-------------------------------------------------------------------- +; External Area Wait Control Register 1 adr:0049h +;-------------------------------------------------------------------- +ewcr1 .equ 0049h +ewcr100 .btequ 0,ewcr1 +ewcr101 .btequ 1,ewcr1 +ewcr102 .btequ 2,ewcr1 +ewcr103 .btequ 3,ewcr1 +ewcr104 .btequ 4,ewcr1 +ewcr106 .btequ 6,ewcr1 +;-------------------------------------------------------------------- +; External Area Wait Control Register 2 adr:004ah +;-------------------------------------------------------------------- +ewcr2 .equ 004ah +ewcr200 .btequ 0,ewcr2 +ewcr201 .btequ 1,ewcr2 +ewcr202 .btequ 2,ewcr2 +ewcr203 .btequ 3,ewcr2 +ewcr204 .btequ 4,ewcr2 +ewcr206 .btequ 6,ewcr2 +;-------------------------------------------------------------------- +; External Area Wait Control Register 3 adr:004bh +;-------------------------------------------------------------------- +ewcr3 .equ 004bh +ewcr300 .btequ 0,ewcr3 +ewcr301 .btequ 1,ewcr3 +ewcr302 .btequ 2,ewcr3 +ewcr303 .btequ 3,ewcr3 +ewcr304 .btequ 4,ewcr3 +ewcr306 .btequ 6,ewcr3 +;-------------------------------------------------------------------- +; +; +; Interrupt control Register +; +; +;-------------------------------------------------------------------- +; Dma0 Interrupt Control Register adr:0068h +;-------------------------------------------------------------------- +dm0ic .equ 0068h +ilvl0_dm0ic .btequ 0,dm0ic +ilvl1_dm0ic .btequ 1,dm0ic +ilvl2_dm0ic .btequ 2,dm0ic +ir_dm0ic .btequ 3,dm0ic +;-------------------------------------------------------------------- +; Timer B5 Interrupt Control Register adr:0069h +;-------------------------------------------------------------------- +tb5ic .equ 0069h +ilvl0_tb5ic .btequ 0,tb5ic +ilvl1_tb5ic .btequ 1,tb5ic +ilvl2_tb5ic .btequ 2,tb5ic +ir_tb5ic .btequ 3,tb5ic +;-------------------------------------------------------------------- +; Dma2 Interrupt Control Register adr:006ah +;-------------------------------------------------------------------- +dm2ic .equ 006ah +ilvl0_dm2ic .btequ 0,dm2ic +ilvl1_dm2ic .btequ 1,dm2ic +ilvl2_dm2ic .btequ 2,dm2ic +ir_dm2ic .btequ 3,dm2ic +;-------------------------------------------------------------------- +; Uart2 Receive/Ack Interrupt +; control Register adr:006bh +;-------------------------------------------------------------------- +s2ric .equ 006bh +ilvl0_s2ric .btequ 0,s2ric +ilvl1_s2ric .btequ 1,s2ric +ilvl2_s2ric .btequ 2,s2ric +ir_s2ric .btequ 3,s2ric +;-------------------------------------------------------------------- +; Timer a0 Interrupt Control Register adr:006ch +;-------------------------------------------------------------------- +ta0ic .equ 006ch +ilvl0_ta0ic .btequ 0,ta0ic +ilvl1_ta0ic .btequ 1,ta0ic +ilvl2_ta0ic .btequ 2,ta0ic +ir_ta0ic .btequ 3,ta0ic +;-------------------------------------------------------------------- +; uart3 receive/ack interrupt +; Control Register adr:006dh +;-------------------------------------------------------------------- +s3ric .equ 006dh +ilvl0_s3ric .btequ 0,s3ric +ilvl1_s3ric .btequ 1,s3ric +ilvl2_s3ric .btequ 2,s3ric +ir_s3ric .btequ 3,s3ric +;-------------------------------------------------------------------- +; timer a2 Interrupt Control Register adr:006eh +;-------------------------------------------------------------------- +ta2ic .equ 006eh +ilvl0_ta2ic .btequ 0,ta2ic +ilvl1_ta2ic .btequ 1,ta2ic +ilvl2_ta2ic .btequ 2,ta2ic +ir_ta2ic .btequ 3,ta2ic +;-------------------------------------------------------------------- +; uart4 receive/ack Interrupt +; Control Register adr:006fh +;-------------------------------------------------------------------- +s4ric .equ 006fh +ilvl0_s4ric .btequ 0,s4ric +ilvl1_s4ric .btequ 1,s4ric +ilvl2_s4ric .btequ 2,s4ric +ir_s4ric .btequ 3,s4ric +;-------------------------------------------------------------------- +; timer a4 Interrupt Control Register adr:0070h +;-------------------------------------------------------------------- +ta4ic .equ 0070h +ilvl0_ta4ic .btequ 0,ta4ic +ilvl1_ta4ic .btequ 1,ta4ic +ilvl2_ta4ic .btequ 2,ta4ic +ir_ta4ic .btequ 3,ta4ic +;-------------------------------------------------------------------- +; bus collision (uart3) interrupt +; Control Register adr:0071h +;-------------------------------------------------------------------- +bcn3ic .equ 0071h +ilvl0_bcn3ic .btequ 0,bcn3ic +ilvl1_bcn3ic .btequ 1,bcn3ic +ilvl2_bcn3ic .btequ 2,bcn3ic +ir_bcn3ic .btequ 3,bcn3ic +;-------------------------------------------------------------------- +; bus collision (uart0) interrupt +; Control Register adr:0071h +;-------------------------------------------------------------------- +bcn0ic .equ 0071h +ilvl0_bcn0ic .btequ 0,bcn0ic +ilvl1_bcn0ic .btequ 1,bcn0ic +ilvl2_bcn0ic .btequ 2,bcn0ic +ir_bcn0ic .btequ 3,bcn0ic +;-------------------------------------------------------------------- +; uart0 receive Interrupt Control Register adr:0072h +;-------------------------------------------------------------------- +s0ric .equ 0072h +ilvl0_s0ric .btequ 0,s0ric +ilvl1_s0ric .btequ 1,s0ric +ilvl2_s0ric .btequ 2,s0ric +ir_s0ric .btequ 3,s0ric +;-------------------------------------------------------------------- +; a/d0 Interrupt Control Register adr:0073h +;-------------------------------------------------------------------- +ad0ic .equ 0073h +ilvl0_ad0ic .btequ 0,ad0ic +ilvl1_ad0ic .btequ 1,ad0ic +ilvl2_ad0ic .btequ 2,ad0ic +ir_ad0ic .btequ 3,ad0ic +;-------------------------------------------------------------------- +; uart1 receive Interrupt Control Register adr:0074h +;-------------------------------------------------------------------- +s1ric .equ 0074h +ilvl0_s1ric .btequ 0,s1ric +ilvl1_s1ric .btequ 1,s1ric +ilvl2_s1ric .btequ 2,s1ric +ir_s1ric .btequ 3,s1ric +;-------------------------------------------------------------------- +; iio0 Interrupt Control Register adr:0075h +;-------------------------------------------------------------------- +iio0ic .equ 0075h +ilvl0_iio0ic .btequ 0,iio0ic +ilvl1_iio0ic .btequ 1,iio0ic +ilvl2_iio0ic .btequ 2,iio0ic +ir_iio0ic .btequ 3,iio0ic +;-------------------------------------------------------------------- +; timer b1 Interrupt Control Register adr:0076h +;-------------------------------------------------------------------- +tb1ic .equ 0076h +ilvl0_tb1ic .btequ 0,tb1ic +ilvl1_tb1ic .btequ 1,tb1ic +ilvl2_tb1ic .btequ 2,tb1ic +ir_tb1ic .btequ 3,tb1ic +;-------------------------------------------------------------------- +; iio2 Interrupt Control Register adr:0077h +;-------------------------------------------------------------------- +iio2ic .equ 0077h +ilvl0_iio2ic .btequ 0,iio2ic +ilvl1_iio2ic .btequ 1,iio2ic +ilvl2_iio2ic .btequ 2,iio2ic +ir_iio2ic .btequ 3,iio2ic +;-------------------------------------------------------------------- +; timer b3 Interrupt Control Register adr:0078h +;-------------------------------------------------------------------- +tb3ic .equ 0078h +ilvl0_tb3ic .btequ 0,tb3ic +ilvl1_tb3ic .btequ 1,tb3ic +ilvl2_tb3ic .btequ 2,tb3ic +ir_tb3ic .btequ 3,tb3ic +;-------------------------------------------------------------------- +; iio4 Interrupt Control Register adr:0079h +;-------------------------------------------------------------------- +iio4ic .equ 0079h +ilvl0_iio4ic .btequ 0,iio4ic +ilvl1_iio4ic .btequ 1,iio4ic +ilvl2_iio4ic .btequ 2,iio4ic +ir_iio4ic .btequ 3,iio4ic +;-------------------------------------------------------------------- +; int5 Interrupt Control Register adr:007ah +;-------------------------------------------------------------------- +int5ic .equ 007ah +ilvl0_int5ic .btequ 0,int5ic +ilvl1_int5ic .btequ 1,int5ic +ilvl2_int5ic .btequ 2,int5ic +ir_int5ic .btequ 3,int5ic +pol_int5ic .btequ 4,int5ic +lvs_int5ic .btequ 5,int5ic +;-------------------------------------------------------------------- +; int3 Interrupt Control Register adr:007ch +;-------------------------------------------------------------------- +int3ic .equ 007ch +ilvl0_int3ic .btequ 0,int3ic +ilvl1_int3ic .btequ 1,int3ic +ilvl2_int3ic .btequ 2,int3ic +ir_int3ic .btequ 3,int3ic +pol_int3ic .btequ 4,int3ic +lvs_int3ic .btequ 5,int3ic +;-------------------------------------------------------------------- +; int1 Interrupt Control Register adr:007eh +;-------------------------------------------------------------------- +int1ic .equ 007eh +ilvl0_int1ic .btequ 0,int1ic +ilvl1_int1ic .btequ 1,int1ic +ilvl2_int1ic .btequ 2,int1ic +ir_int1ic .btequ 3,int1ic +pol_int1ic .btequ 4,int1ic +lvs_int1ic .btequ 5,int1ic +;-------------------------------------------------------------------- +; dma1 Interrupt Control Register adr:0088h +;-------------------------------------------------------------------- +dm1ic .equ 0088h +ilvl0_dm1ic .btequ 0,dm1ic +ilvl1_dm1ic .btequ 1,dm1ic +ilvl2_dm1ic .btequ 2,dm1ic +ir_dm1ic .btequ 3,dm1ic +;-------------------------------------------------------------------- +; uart2 transmit/nack Interrupt +; Control Register adr:0089h +;-------------------------------------------------------------------- +s2tic .equ 0089h +ilvl0_s2tic .btequ 0,s2tic +ilvl1_s2tic .btequ 1,s2tic +ilvl2_s2tic .btequ 2,s2tic +ir_s2tic .btequ 3,s2tic +;-------------------------------------------------------------------- +; dma3 Interrupt Control Register adr:008ah +;-------------------------------------------------------------------- +dm3ic .equ 008ah +ilvl0_dm3ic .btequ 0,dm3ic +ilvl1_dm3ic .btequ 1,dm3ic +ilvl2_dm3ic .btequ 2,dm3ic +ir_dm3ic .btequ 3,dm3ic +;-------------------------------------------------------------------- +; uart3 transmit/nack Interrupt +; Control Register adr:008bh +;-------------------------------------------------------------------- +s3tic .equ 008bh +ilvl0_s3tic .btequ 0,s3tic +ilvl1_s3tic .btequ 1,s3tic +ilvl2_s3tic .btequ 2,s3tic +ir_s3tic .btequ 3,s3tic +;-------------------------------------------------------------------- +; timer a1 Interrupt Control Register adr:008ch +;-------------------------------------------------------------------- +ta1ic .equ 008ch +ilvl0_ta1ic .btequ 0,ta1ic +ilvl1_ta1ic .btequ 1,ta1ic +ilvl2_ta1ic .btequ 2,ta1ic +ir_ta1ic .btequ 3,ta1ic +;-------------------------------------------------------------------- +; uart4 transmit/nack Interrupt +; Control Register adr:008dh +;-------------------------------------------------------------------- +s4tic .equ 008dh +ilvl0_s4tic .btequ 0,s4tic +ilvl1_s4tic .btequ 1,s4tic +ilvl2_s4tic .btequ 2,s4tic +ir_s4tic .btequ 3,s4tic +;-------------------------------------------------------------------- +; timer a3 Interrupt Control Register adr:008eh +;-------------------------------------------------------------------- +ta3ic .equ 008eh +ilvl0_ta3ic .btequ 0,ta3ic +ilvl1_ta3ic .btequ 1,ta3ic +ilvl2_ta3ic .btequ 2,ta3ic +ir_ta3ic .btequ 3,ta3ic +;-------------------------------------------------------------------- +; bus collision (uart2) interrupt +; Control Register adr:008fh +;-------------------------------------------------------------------- +bcn2ic .equ 008fh +ilvl0_bcn2ic .btequ 0,bcn2ic +ilvl1_bcn2ic .btequ 1,bcn2ic +ilvl2_bcn2ic .btequ 2,bcn2ic +ir_bcn2ic .btequ 3,bcn2ic +;-------------------------------------------------------------------- +; uart0 transmit interrupt Control Register adr:0090h +;-------------------------------------------------------------------- +s0tic .equ 0090h +ilvl0_s0tic .btequ 0,s0tic +ilvl1_s0tic .btequ 1,s0tic +ilvl2_s0tic .btequ 2,s0tic +ir_s0tic .btequ 3,s0tic +;-------------------------------------------------------------------- +; bus collision (uart4) interrupt +; Control Register adr:0091h +;-------------------------------------------------------------------- +bcn4ic .equ 0091h +ilvl0_bcn4ic .btequ 0,bcn4ic +ilvl1_bcn4ic .btequ 1,bcn4ic +ilvl2_bcn4ic .btequ 2,bcn4ic +ir_bcn4ic .btequ 3,bcn4ic +;-------------------------------------------------------------------- +; bus collision (uart1) interrupt +; Control Register adr:0091h +;-------------------------------------------------------------------- +bcn1ic .equ 0091h +ilvl0_bcn1ic .btequ 0,bcn1ic +ilvl1_bcn1ic .btequ 1,bcn1ic +ilvl2_bcn1ic .btequ 2,bcn1ic +ir_bcn1ic .btequ 3,bcn1ic +;-------------------------------------------------------------------- +; uart1 transmit interrupt Control Register adr:0092h +;-------------------------------------------------------------------- +s1tic .equ 0092h +ilvl0_s1tic .btequ 0,s1tic +ilvl1_s1tic .btequ 1,s1tic +ilvl2_s1tic .btequ 2,s1tic +ir_s1tic .btequ 3,s1tic +;-------------------------------------------------------------------- +; key input interrupt Control Register adr:0093h +;-------------------------------------------------------------------- +kupic .equ 0093h +ilvl0_kupic .btequ 0,kupic +ilvl1_kupic .btequ 1,kupic +ilvl2_kupic .btequ 2,kupic +ir_kupic .btequ 3,kupic +;-------------------------------------------------------------------- +; timer b0 interrupt Control Register adr:0094h +;-------------------------------------------------------------------- +tb0ic .equ 0094h +ilvl0_tb0ic .btequ 0,tb0ic +ilvl1_tb0ic .btequ 1,tb0ic +ilvl2_tb0ic .btequ 2,tb0ic +ir_tb0ic .btequ 3,tb0ic +;-------------------------------------------------------------------- +; iio1 Interrupt Control Register adr:0095h +;-------------------------------------------------------------------- +iio1ic .equ 0095h +ilvl0_iio1ic .btequ 0,iio1ic +ilvl1_iio1ic .btequ 1,iio1ic +ilvl2_iio1ic .btequ 2,iio1ic +ir_iio1ic .btequ 3,iio1ic +;-------------------------------------------------------------------- +; timer b2 interrupt Control Register adr:0096h +;-------------------------------------------------------------------- +tb2ic .equ 0096h +ilvl0_tb2ic .btequ 0,tb2ic +ilvl1_tb2ic .btequ 1,tb2ic +ilvl2_tb2ic .btequ 2,tb2ic +ir_tb2ic .btequ 3,tb2ic +;-------------------------------------------------------------------- +; iio3 Interrupt Control Register adr:0097h +;-------------------------------------------------------------------- +iio3ic .equ 0097h +ilvl0_iio3ic .btequ 0,iio3ic +ilvl1_iio3ic .btequ 1,iio3ic +ilvl2_iio3ic .btequ 2,iio3ic +ir_iio3ic .btequ 3,iio3ic +;-------------------------------------------------------------------- +; timer b4 interrupt Control Register adr:0098h +;-------------------------------------------------------------------- +tb4ic .equ 0098h +ilvl0_tb4ic .btequ 0,tb4ic +ilvl1_tb4ic .btequ 1,tb4ic +ilvl2_tb4ic .btequ 2,tb4ic +ir_tb4ic .btequ 3,tb4ic +;-------------------------------------------------------------------- +; int4 interrupt Control Register adr:009ah +;-------------------------------------------------------------------- +int4ic .equ 009ah +ilvl0_int4ic .btequ 0,int4ic +ilvl1_int4ic .btequ 1,int4ic +ilvl2_int4ic .btequ 2,int4ic +ir_int4ic .btequ 3,int4ic +pol_int4ic .btequ 4,int4ic +lvs_int4ic .btequ 5,int4ic +;-------------------------------------------------------------------- +; int2 interrupt Control Register adr:009ch +;-------------------------------------------------------------------- +int2ic .equ 009ch +ilvl0_int2ic .btequ 0,int2ic +ilvl1_int2ic .btequ 1,int2ic +ilvl2_int2ic .btequ 2,int2ic +ir_int2ic .btequ 3,int2ic +pol_int2ic .btequ 4,int2ic +lvs_int2ic .btequ 5,int2ic +;-------------------------------------------------------------------- +; int0 interrupt Control Register adr:009eh +;-------------------------------------------------------------------- +int0ic .equ 009eh +ilvl0_int0ic .btequ 0,int0ic +ilvl1_int0ic .btequ 1,int0ic +ilvl2_int0ic .btequ 2,int0ic +ir_int0ic .btequ 3,int0ic +pol_int0ic .btequ 4,int0ic +lvs_int0ic .btequ 5,int0ic +;-------------------------------------------------------------------- +; Exit priority register adr:009fh +;-------------------------------------------------------------------- +rlvl .equ 009fh +rlvl0 .btequ 0,rlvl +rlvl1 .btequ 1,rlvl +rlvl2 .btequ 2,rlvl +fsit .btequ 3,rlvl +dmaii .btequ 5,rlvl +;-------------------------------------------------------------------- +; Interruption requirement Register 0 adr:00a0h +;-------------------------------------------------------------------- +iio0ir .equ 00a0h +tm13r .btequ 2,iio0ir +po13r .btequ 2,iio0ir +g0rir .btequ 4,iio0ir +sio0rr .btequ 5,iio0ir +can10r .btequ 7,iio0ir +;-------------------------------------------------------------------- +; Interruption requirement Register 1 adr:00a1h +;-------------------------------------------------------------------- +iio1ir .equ 00a1h +tm14r .btequ 2,iio1ir +po14r .btequ 2,iio1ir +g0tor .btequ 4,iio1ir +sio0tr .btequ 5,iio1ir +can11r .btequ 7,iio1ir +;-------------------------------------------------------------------- +; Interruption requirement Register 2 adr:00a2h +;-------------------------------------------------------------------- +iio2ir .equ 00a2h +tm12r .btequ 2,iio2ir +po12r .btequ 2,iio2ir +g1rir .btequ 4,iio2ir +sio1rr .btequ 5,iio2ir +;-------------------------------------------------------------------- +; Interruption requirement Register 3 adr:00a3h +;-------------------------------------------------------------------- +iio3ir .equ 00a3h +tm10r .btequ 2,iio3ir +po10r .btequ 2,iio3ir +g1tor .btequ 4,iio3ir +sio1tr .btequ 5,iio3ir +;-------------------------------------------------------------------- +; Interruption requirement Register 4 adr:00a4h +;-------------------------------------------------------------------- +iio4ir .equ 00a4h +tm17r .btequ 2,iio4ir +po17r .btequ 2,iio4ir +bt1r .btequ 4,iio4ir +srt1r .btequ 6,iio4ir +srt0r .btequ 7,iio4ir +;-------------------------------------------------------------------- +; Interruption requirement Register 5 adr:00a5h +;-------------------------------------------------------------------- +iio5ir .equ 00a5h +can1wur .btequ 6,iio5ir +can12r .btequ 7,iio5ir +;-------------------------------------------------------------------- +; Interruption permission Register 0 adr:00b0h +;-------------------------------------------------------------------- +iio0ie .equ 00b0h +irlt_iio0ie .btequ 0,iio0ie +tm13e .btequ 2,iio0ie +po13e .btequ 2,iio0ie +g0rie .btequ 4,iio0ie +sio0re .btequ 5,iio0ie +can10e .btequ 7,iio0ie +;-------------------------------------------------------------------- +; Interruption permission Register 1 adr:00b1h +;-------------------------------------------------------------------- +iio1ie .equ 00b1h +irlt_iio1ie .btequ 0,iio1ie +tm14e .btequ 2,iio1ie +po14e .btequ 2,iio1ie +g0toe .btequ 4,iio1ie +sio0te .btequ 5,iio1ie +can11e .btequ 7,iio1ie +;-------------------------------------------------------------------- +; Interruption permission Register 2 adr:00b2h +;-------------------------------------------------------------------- +iio2ie .equ 00b2h +irlt_iio2ie .btequ 0,iio2ie +tm12e .btequ 2,iio2ie +po12e .btequ 2,iio2ie +g1rie .btequ 4,iio2ie +sio1re .btequ 5,iio2ie +;-------------------------------------------------------------------- +; Interruption permission Register 3 adr:00b3h +;-------------------------------------------------------------------- +iio3ie .equ 00b3h +irlt_iio3ie .btequ 0,iio3ie +tm10e .btequ 2,iio3ie +po10e .btequ 2,iio3ie +g1toe .btequ 4,iio3ie +sio1te .btequ 5,iio3ie +;-------------------------------------------------------------------- +; Interruption permission Register 4 adr:00b4h +;-------------------------------------------------------------------- +iio4ie .equ 00b4h +irlt_iio4ie .btequ 0,iio4ie +tm17e .btequ 2,iio4ie +po17e .btequ 2,iio4ie +bt1e .btequ 4,iio4ie +srt1e .btequ 6,iio4ie +srt0e .btequ 7,iio4ie +;-------------------------------------------------------------------- +; +; +; intelligent i/o Register(group0) +; +; +;-------------------------------------------------------------------- +; group0 si/o receive buffer Register adr:00e8 +;-------------------------------------------------------------------- +g0rb .equ 00e8h +g0rbl .equ g0rb +g0rbh .equ g0rb+1 +oer_g0rb .btequ 4, g0rbh +;-------------------------------------------------------------------- +; group0 si/o transmitting +; buffer Register adr:00eah +;-------------------------------------------------------------------- +g0tb .equ 00eah +;-------------------------------------------------------------------- +; group0 receiving data Register adr:00eah +;-------------------------------------------------------------------- +g0dr .equ 00eah +;-------------------------------------------------------------------- +; group0 receiving input Register adr:00ech +;-------------------------------------------------------------------- +g0ri .equ 00ech +;-------------------------------------------------------------------- +; group0 si/o communication +; mode Register adr:00edh +;-------------------------------------------------------------------- +g0mr .equ 00edh +gmd0_g0mr .btequ 0,g0mr +gmd1_g0mr .btequ 1,g0mr +ckdir_g0mr .btequ 2,g0mr +uform_g0mr .btequ 6,g0mr +irs_g0mr .btequ 7,g0mr +;-------------------------------------------------------------------- +; group0 transmitting output Register adr:00eeh +;-------------------------------------------------------------------- +g0to .equ 00eeh +;-------------------------------------------------------------------- +; group0 si/o communication +; Control Register adr:00efh +;-------------------------------------------------------------------- +g0cr .equ 00efh +ti_g0cr .btequ 0,g0cr +txept_g0cr .btequ 1,g0cr +ri_g0cr .btequ 2,g0cr +te_g0cr .btequ 4,g0cr +re_g0cr .btequ 5,g0cr +ipol_g0cr .btequ 6,g0cr +opol_g0cr .btequ 7,g0cr +;-------------------------------------------------------------------- +; group0 data comparative Register 0 adr:00f0h +;-------------------------------------------------------------------- +g0cmp0 .equ 00f0h +;-------------------------------------------------------------------- +; group0 data comparative Register 1 adr:00f1h +;-------------------------------------------------------------------- +g0cmp1 .equ 00f1h +;-------------------------------------------------------------------- +; group0 data comparative Register 2 adr:00f2h +;-------------------------------------------------------------------- +g0cmp2 .equ 00f2h +;-------------------------------------------------------------------- +; group0 data comparative Register 3 adr:00f3h +;-------------------------------------------------------------------- +g0cmp3 .equ 00f3h +;-------------------------------------------------------------------- +; group0 data mask Register 0 adr:00f4h +;-------------------------------------------------------------------- +g0msk0 .equ 00f4h +;-------------------------------------------------------------------- +; group0 data mask Register 1 adr:00f5h +;-------------------------------------------------------------------- +g0msk1 .equ 00f5h +;-------------------------------------------------------------------- +; Communication Clock Select Register adr:00f6h +;-------------------------------------------------------------------- +ccs .equ 00f6h +ccs0 .btequ 0,ccs +ccs1 .btequ 1,ccs +ccs2 .btequ 2,ccs +ccs3 .btequ 3,ccs +;-------------------------------------------------------------------- +; group0 receive crc Register adr:00f9h-00f8h +;-------------------------------------------------------------------- +g0rcrc .equ 00f8h +g0rcrcl .equ g0rcrc +g0rcrch .equ g0rcrc+1 +;-------------------------------------------------------------------- +; group0 transmit crc Register adr:00fbh-00fah +;-------------------------------------------------------------------- +g0tcrc .equ 00fah +g0tcrcl .equ g0tcrc +g0tcrch .equ g0tcrc+1 +;-------------------------------------------------------------------- +; group0 function expansion +; mode Register adr:00fch +;-------------------------------------------------------------------- +g0emr .equ 00fch +crcv_g0emr .btequ 1,g0emr +acrc_g0emr .btequ 2,g0emr +bsint_g0emr .btequ 3,g0emr +rxsl_g0emr .btequ 4,g0emr +txsl_g0emr .btequ 5,g0emr +crc0_g0emr .btequ 6,g0emr +crc1_g0emr .btequ 7,g0emr +;-------------------------------------------------------------------- +; group0 expansion receive +; Control Register adr:00fdh +;-------------------------------------------------------------------- +g0erc .equ 00fdh +cmp0e_g0erc .btequ 0,g0erc +cmp1e_g0erc .btequ 1,g0erc +cmp2e_g0erc .btequ 2,g0erc +cmp3e_g0erc .btequ 3,g0erc +rcrce_g0erc .btequ 4,g0erc +rshte_g0erc .btequ 5,g0erc +rbsf0_g0erc .btequ 6,g0erc +rbsf1_g0erc .btequ 7,g0erc +;-------------------------------------------------------------------- +; group0 special communication Interruption +; distinction Register adr:00feh +;-------------------------------------------------------------------- +g0irf .equ 00feh +bserr_g0irf .btequ 2,g0irf +irf0_g0irf .btequ 4,g0irf +irf1_g0irf .btequ 5,g0irf +irf2_g0irf .btequ 6,g0irf +irf3_g0irf .btequ 7,g0irf +;-------------------------------------------------------------------- +; group0 si/o expansion transmitting +; Control Register adr:00ffh +;-------------------------------------------------------------------- +g0etc .equ 00ffh +tcrce_g0etc .btequ 4,g0etc +tbsf0_g0etc .btequ 6,g0etc +tbsf1_g0etc .btequ 7,g0etc +;-------------------------------------------------------------------- +; group1 si/o receive buffer Register adr:0129h-0128h +;-------------------------------------------------------------------- +g1rb .equ 0128h +g1rbl .equ g1rb +g1rbh .equ g1rb+1 +oer_g1rb .btequ 4,g1rbh +fer_g1rb .btequ 5,g1rbh +per_g1rb .btequ 6,g1rbh +;-------------------------------------------------------------------- +; group1 si/o transmitting +; buffer Register adr:012ah +;-------------------------------------------------------------------- +g1tb .equ 012ah +;-------------------------------------------------------------------- +; group1 receiving data Register adr:012ah +;-------------------------------------------------------------------- +g1dr .equ 012ah +;-------------------------------------------------------------------- +; group1 receiving input Register adr:012ch +;-------------------------------------------------------------------- +g1ri .equ 012ch +;-------------------------------------------------------------------- +; group1 si/o communication +; mode Register adr:012dh +;-------------------------------------------------------------------- +g1mr .equ 012dh +gmd0_g1mr .btequ 0,g1mr +gmd1_g1mr .btequ 1,g1mr +ckdir_g1mr .btequ 2,g1mr +stps_g1mr .btequ 3,g1mr +pry_g1mr .btequ 4,g1mr +prye_g1mr .btequ 5,g1mr +uform_g1mr .btequ 6,g1mr +irs_g1mr .btequ 7,g1mr +;-------------------------------------------------------------------- +; group1 transmitting output Register adr:012eh +;-------------------------------------------------------------------- +g1to .equ 012eh +;-------------------------------------------------------------------- +; group1 si/o communication +; Control Register adr:012fh +;-------------------------------------------------------------------- +g1cr .equ 012fh +ti_g1cr .btequ 0,g1cr +txept_g1cr .btequ 1,g1cr +ri_g1cr .btequ 2,g1cr +te_g1cr .btequ 4,g1cr +re_g1cr .btequ 5,g1cr +ipol_g1cr .btequ 6,g1cr +opol_g1cr .btequ 7,g1cr +;-------------------------------------------------------------------- +; group1 data comparative Register 0 adr:0130h +;-------------------------------------------------------------------- +g1cmp0 .equ 0130h +;-------------------------------------------------------------------- +; group1 data comparative Register 1 adr:0131h +;-------------------------------------------------------------------- +g1cmp1 .equ 0131h +;-------------------------------------------------------------------- +; group1 data comparative Register 2 adr:0132h +;-------------------------------------------------------------------- +g1cmp2 .equ 0132h +;-------------------------------------------------------------------- +; group1 data comparative Register 3 adr:0133h +;-------------------------------------------------------------------- +g1cmp3 .equ 0133h +;-------------------------------------------------------------------- +; group1 data mask Register 0 adr:0134h +;-------------------------------------------------------------------- +g1msk0 .equ 0134h +;-------------------------------------------------------------------- +; group1 data mask Register 1 adr:0135h +;-------------------------------------------------------------------- +g1msk1 .equ 0135h +;-------------------------------------------------------------------- +; group1 receive crc Register adr:0139h-0138h +;-------------------------------------------------------------------- +g1rcrc .equ 0138h +g1rcrcl .equ g1rcrc +g1rcrch .equ g1rcrc+1 +;-------------------------------------------------------------------- +; group1 transmit crc Register adr:013bh-013ah +;-------------------------------------------------------------------- +g1tcrc .equ 013ah +g1tcrcl .equ g1tcrc +g1tcrch .equ g1tcrc+1 +;-------------------------------------------------------------------- +; group1 function expansion +; mode Register adr:013ch +;-------------------------------------------------------------------- +g1emr .equ 013ch +smode_g1emr .btequ 0,g1emr +crcv_g1emr .btequ 1,g1emr +acrc_g1emr .btequ 2,g1emr +bsint_g1emr .btequ 3,g1emr +rxsl_g1emr .btequ 4,g1emr +txsl_g1emr .btequ 5,g1emr +crc0_g1emr .btequ 6,g1emr +crc1_g1emr .btequ 7,g1emr +;-------------------------------------------------------------------- +; group1 expansion receive +; Control Register adr:013dh +;-------------------------------------------------------------------- +g1erc .equ 013dh +cmp0e_g1erc .btequ 0,g1erc +cmp1e_g1erc .btequ 1,g1erc +cmp2e_g1erc .btequ 2,g1erc +cmp3e_g1erc .btequ 3,g1erc +rcrce_g1erc .btequ 4,g1erc +rshte_g1erc .btequ 5,g1erc +rbsf0_g1erc .btequ 6,g1erc +rbsf1_g1erc .btequ 7,g1erc +;-------------------------------------------------------------------- +; group1 special communication Interruption +; distinction Register adr:013eh +;-------------------------------------------------------------------- +g1irf .equ 013eh +bserr_g1irf .btequ 2,g1irf +abt_g1irf .btequ 3,g1irf +irf0_g1irf .btequ 4,g1irf +irf1_g1irf .btequ 5,g1irf +irf2_g1irf .btequ 6,g1irf +irf3_g1irf .btequ 7,g1irf +;-------------------------------------------------------------------- +; group1 si/o expansion transmitting +; Control Register adr:013fh +;-------------------------------------------------------------------- +g1etc .equ 013fh +sof_g1etc .btequ 3,g1etc +tcrce_g1etc .btequ 4,g1etc +abte_g1etc .btequ 5,g1etc +tbsf0_g1etc .btequ 6,g1etc +tbsf1_g1etc .btequ 7,g1etc + +;-------------------------------------------------------------------- +; +; +; x-y Register +; +; +;-------------------------------------------------------------------- +; x0 Register adr:02c1h-02c0h +;-------------------------------------------------------------------- +x0r .equ 02c0h +x0rl .equ x0r +x0rh .equ x0r+1 +;-------------------------------------------------------------------- +; y0 Register adr:02c1h-02c0h +;-------------------------------------------------------------------- +y0r .equ 02c0h +y0rl .equ y0r +y0rh .equ y0r+1 +;-------------------------------------------------------------------- +; x1 Register adr:02c3h-02c2h +;-------------------------------------------------------------------- +x1r .equ 02c2h +x1rl .equ x1r +x1rh .equ x1r+1 +;-------------------------------------------------------------------- +; y1 Register adr:02c3h-02c2h +;-------------------------------------------------------------------- +y1r .equ 02c2h +y1rl .equ y1r +y1rh .equ y1r+1 +;-------------------------------------------------------------------- +; x2 Register adr:02c5h-02c4h +;-------------------------------------------------------------------- +x2r .equ 02c4h +x2rl .equ x2r +x2rh .equ x2r+1 +;-------------------------------------------------------------------- +; y2 Register adr:02c5h-02c4h +;-------------------------------------------------------------------- +y2r .equ 02c4h +y2rl .equ y2r +y2rh .equ y2r+1 +;-------------------------------------------------------------------- +; x3 Register adr:02c7h-02c6h +;-------------------------------------------------------------------- +x3r .equ 02c6h +x3rl .equ x3r +x3rh .equ x3r+1 +;-------------------------------------------------------------------- +; y3 Register adr:02c7h-02c6h +;-------------------------------------------------------------------- +y3r .equ 02c6h +y3rl .equ y3r +y3rh .equ y3r+1 +;-------------------------------------------------------------------- +; x4 Register adr:02c9h-02c8h +;-------------------------------------------------------------------- +x4r .equ 02c8h +x4rl .equ x4r +x4rh .equ x4r+1 +;-------------------------------------------------------------------- +; y4 Register adr:02c9h-02c8h +;-------------------------------------------------------------------- +y4r .equ 02c8h +y4rl .equ y4r +y4rh .equ y4r+1 +;-------------------------------------------------------------------- +; x5 Register adr:02cbh-02cah +;-------------------------------------------------------------------- +x5r .equ 02cah +x5rl .equ x5r +x5rh .equ x5r+1 +;-------------------------------------------------------------------- +; y5 Register adr:02cbh-02cah +;-------------------------------------------------------------------- +y5r .equ 02cah +y5rl .equ y5r +y5rh .equ y5r+1 +;-------------------------------------------------------------------- +; x6 Register adr:02cdh-02cch +;-------------------------------------------------------------------- +x6r .equ 02cch +x6rl .equ x6r +x6rh .equ x6r+1 +;-------------------------------------------------------------------- +; y6 Register adr:02cdh-02cch +;-------------------------------------------------------------------- +y6r .equ 02cch +y6rl .equ y6r +y6rh .equ y6r+1 +;-------------------------------------------------------------------- +; x7 Register adr:02cfh-02ceh +;-------------------------------------------------------------------- +x7r .equ 02ceh +x7rl .equ x7r +x7rh .equ x7r+1 +;-------------------------------------------------------------------- +; y7 Register adr:02cfh-02ceh +;-------------------------------------------------------------------- +y7r .equ 02ceh +y7rl .equ y7r +y7rh .equ y7r+1 +;-------------------------------------------------------------------- +; x8 Register adr:02d1h-02d0h +;-------------------------------------------------------------------- +x8r .equ 02d0h +x8rl .equ x8r +x8rh .equ x8r+1 +;-------------------------------------------------------------------- +; y8 Register adr:02d1h-02d0h +;-------------------------------------------------------------------- +y8r .equ 02d0h +y8rl .equ y8r +y8rh .equ y8r+1 +;-------------------------------------------------------------------- +; x9 Register adr:02d3h-02d2h +;-------------------------------------------------------------------- +x9r .equ 02d2h +x9rl .equ x9r +x9rh .equ x9r+1 +;-------------------------------------------------------------------- +; y9 Register adr:02d3h-02d2h +;-------------------------------------------------------------------- +y9r .equ 02d2h +y9rl .equ y9r +y9rh .equ y9r+1 +;-------------------------------------------------------------------- +; x10 Register adr:02d5h-02d4h +;-------------------------------------------------------------------- +x10r .equ 02d4h +x10rl .equ x10r +x10rh .equ x10r+1 +;-------------------------------------------------------------------- +; y10 Register adr:02d5h-02d4h +;-------------------------------------------------------------------- +y10r .equ 02d4h +y10rl .equ y10r +y10rh .equ y10r+1 +;-------------------------------------------------------------------- +; x11 Register adr:02d7h-02d6h +;-------------------------------------------------------------------- +x11r .equ 02d6h +x11rl .equ x11r +x11rh .equ x11r+1 +;-------------------------------------------------------------------- +; y11 Register adr:02d7h-02d6h +;-------------------------------------------------------------------- +y11r .equ 02d6h +y11rl .equ y11r +y11rh .equ y11r+1 +;-------------------------------------------------------------------- +; x12 Register adr:02d9h-02d8h +;-------------------------------------------------------------------- +x12r .equ 02d8h +x12rl .equ x12r +x12rh .equ x12r+1 +;-------------------------------------------------------------------- +; y12 Register adr:02d9h-02d8h +;-------------------------------------------------------------------- +y12r .equ 02d8h +y12rl .equ y12r +y12rh .equ y12r+1 +;-------------------------------------------------------------------- +; x13 Register adr:02dbh-02dah +;-------------------------------------------------------------------- +x13r .equ 02dah +x13rl .equ x13r +x13rh .equ x13r+1 +;-------------------------------------------------------------------- +; y13 Register adr:02dbh-02dah +;-------------------------------------------------------------------- +y13r .equ 02dah +y13rl .equ y13r +y13rh .equ y13r+1 +;-------------------------------------------------------------------- +; x14 Register adr:02ddh-02dch +;-------------------------------------------------------------------- +x14r .equ 02dch +x14rl .equ x14r +x14rh .equ x14r+1 +;-------------------------------------------------------------------- +; y14 Register adr:02ddh-02dch +;-------------------------------------------------------------------- +y14r .equ 02dch +y14rl .equ y14r +y14rh .equ y14r+1 +;-------------------------------------------------------------------- +; x15 Register adr:02dfh-02deh +;-------------------------------------------------------------------- +x15r .equ 02deh +x15rl .equ x15r +x15rh .equ x15r+1 +;-------------------------------------------------------------------- +; y15 Register adr:02dfh-02deh +;-------------------------------------------------------------------- +y15r .equ 02deh +y15rl .equ y15r +y15rh .equ y15r+1 +;-------------------------------------------------------------------- +; x-y Control Register adr:02e0h +;-------------------------------------------------------------------- +xyc .equ 02e0h +xyc0 .btequ 0,xyc +xyc1 .btequ 1,xyc +;-------------------------------------------------------------------- +; +; +; uart1 +; +; +;-------------------------------------------------------------------- +; uart1 special mode Register 4 adr:02e4h +;-------------------------------------------------------------------- +u1smr4 .equ 02e4h +stareq_u1smr4 .btequ 0,u1smr4 +rstareq_u1smr4 .btequ 1,u1smr4 +stpreq_u1smr4 .btequ 2,u1smr4 +stspsel_u1smr4 .btequ 3,u1smr4 +ackd_u1smr4 .btequ 4,u1smr4 +ackc_u1smr4 .btequ 5,u1smr4 +sclhi_u1smr4 .btequ 6,u1smr4 +swc9_u1smr4 .btequ 7,u1smr4 +;-------------------------------------------------------------------- +; uart1 special mode Register 3 adr:02e5h +;-------------------------------------------------------------------- +u1smr3 .equ 02e5h +sse_u1smr3 .btequ 0,u1smr3 +ckph_u1smr3 .btequ 1,u1smr3 +dinc_u1smr3 .btequ 2,u1smr3 +nodc_u1smr3 .btequ 3,u1smr3 +err_u1smr3 .btequ 4,u1smr3 +dl0_u1smr3 .btequ 5,u1smr3 +dl1_u1smr3 .btequ 6,u1smr3 +dl2_u1smr3 .btequ 7,u1smr3 +;-------------------------------------------------------------------- +; uart1 special mode Register 2 adr:02e6h +;-------------------------------------------------------------------- +u1smr2 .equ 02e6h +iicm2_u1smr2 .btequ 0,u1smr2 +csc_u1smr2 .btequ 1,u1smr2 +swc_u1smr2 .btequ 2,u1smr2 +als_u1smr2 .btequ 3,u1smr2 +stc_u1smr2 .btequ 4,u1smr2 +swc2_u1smr2 .btequ 5,u1smr2 +sdhi_u1smr2 .btequ 6,u1smr2 +su1him_u1smr2 .btequ 7,u1smr2 +;-------------------------------------------------------------------- +; uart1 special mode Register adr:02e7h +;-------------------------------------------------------------------- +u1smr .equ 02e7h +iicm_u1smr .btequ 0,u1smr +abc_u1smr .btequ 1,u1smr +bbs_u1smr .btequ 2,u1smr +lsyn_u1smr .btequ 3,u1smr +abscs_u1smr .btequ 4,u1smr +acse_u1smr .btequ 5,u1smr +sss_u1smr .btequ 6,u1smr +sclkdiv_u1smr .btequ 7,u1smr +;-------------------------------------------------------------------- +; uart1 transmit receive mode Register adr:02e8h +;-------------------------------------------------------------------- +u1mr .equ 02e8h +smd0_u1mr .btequ 0,u1mr +smd1_u1mr .btequ 1,u1mr +smd2_u1mr .btequ 2,u1mr +ckdir_u1mr .btequ 3,u1mr +stps_u1mr .btequ 4,u1mr +pry_u1mr .btequ 5,u1mr +prye_u1mr .btequ 6,u1mr +iopol_u1mr .btequ 7,u1mr +;-------------------------------------------------------------------- +; uart1 bit rate generator adr:02e9h +;-------------------------------------------------------------------- +u1brg .equ 02e9h +;-------------------------------------------------------------------- +; uart1 transmit buffer Register adr:02ebh-02eah +;-------------------------------------------------------------------- +u1tb .equ 02eah +u1tbl .equ u1tb +u1tbh .equ u1tb+1 +;-------------------------------------------------------------------- +; uart1 transmit receive Control Register 0 adr:02ech +;-------------------------------------------------------------------- +u1c0 .equ 02ech +clk0_u1c0 .btequ 0,u1c0 +clk1_u1c0 .btequ 1,u1c0 +crs_u1c0 .btequ 2,u1c0 +txept_u1c0 .btequ 3,u1c0 +crd_u1c0 .btequ 4,u1c0 +nch_u1c0 .btequ 5,u1c0 +ckpol_u1c0 .btequ 6,u1c0 +uform_u1c0 .btequ 7,u1c0 +;-------------------------------------------------------------------- +; uart1 transmit receive Control Register 1 adr:02edh +;-------------------------------------------------------------------- +u1c1 .equ 02edh +te_u1c1 .btequ 0,u1c1 +ti_u1c1 .btequ 1,u1c1 +re_u1c1 .btequ 2,u1c1 +ri_u1c1 .btequ 3,u1c1 +u1irs_u1c1 .btequ 4,u1c1 +u1rrm_u1c1 .btequ 5,u1c1 +u1lch_u1c1 .btequ 6,u1c1 +sclkstpb_u1c1 .btequ 7,u1c1 +u1ere_u1c1 .btequ 7,u1c1 +;-------------------------------------------------------------------- +; uart1 receive buffer Register adr:02efh-02eeh +;-------------------------------------------------------------------- +u1rb .equ 02eeh +u1rbl .equ u1rb +u1rbh .equ u1rb+1 +abt_u1rb .btequ 3,u1rbh +oer_u1rb .btequ 4,u1rbh +fer_u1rb .btequ 5,u1rbh +per_u1rb .btequ 6,u1rbh +sum_u1rb .btequ 7,u1rbh +;-------------------------------------------------------------------- +; +; +; uart4 +; +; +;-------------------------------------------------------------------- +; uart4 special mode Register 4 adr:02f4h +;-------------------------------------------------------------------- +u4smr4 .equ 02f4h +stareq_u4smr4 .btequ 0,u4smr4 +rstareq_u4smr4 .btequ 1,u4smr4 +stpreq_u4smr4 .btequ 2,u4smr4 +stspsel_u4smr4 .btequ 3,u4smr4 +ackd_u4smr4 .btequ 4,u4smr4 +ackc_u4smr4 .btequ 5,u4smr4 +sclhi_u4smr4 .btequ 6,u4smr4 +swc9_u4smr4 .btequ 7,u4smr4 +;-------------------------------------------------------------------- +; uart4 special mode Register 3 adr:02f5h +;-------------------------------------------------------------------- +u4smr3 .equ 02f5h +sse_u4smr3 .btequ 0,u4smr3 +ckph_u4smr3 .btequ 1,u4smr3 +dinc_u4smr3 .btequ 2,u4smr3 +nodc_u4smr3 .btequ 3,u4smr3 +err_u4smr3 .btequ 4,u4smr3 +dl0_u4smr3 .btequ 5,u4smr3 +dl1_u4smr3 .btequ 6,u4smr3 +dl2_u4smr3 .btequ 7,u4smr3 +;-------------------------------------------------------------------- +; uart4 special mode Register 2 adr:02f6h +;-------------------------------------------------------------------- +u4smr2 .equ 02f6h +iicm2_u4smr2 .btequ 0,u4smr2 +csc_u4smr2 .btequ 1,u4smr2 +swc_u4smr2 .btequ 2,u4smr2 +als_u4smr2 .btequ 3,u4smr2 +stc_u4smr2 .btequ 4,u4smr2 +swc2_u4smr2 .btequ 5,u4smr2 +sdhi_u4smr2 .btequ 6,u4smr2 +su1him_u4smr2 .btequ 7,u4smr2 +;-------------------------------------------------------------------- +; uart4 special mode Register adr:02f7h +;-------------------------------------------------------------------- +u4smr .equ 02f7h +iicm_u4smr .btequ 0,u4smr +abc_u4smr .btequ 1,u4smr +bbs_u4smr .btequ 2,u4smr +lsyn_u4smr .btequ 3,u4smr +abscs_u4smr .btequ 4,u4smr +acse_u4smr .btequ 5,u4smr +sss_u4smr .btequ 6,u4smr +sclkdiv_u4smr .btequ 7,u4smr +;-------------------------------------------------------------------- +; uart4 transmit receive mode Register adr:02f8h +;-------------------------------------------------------------------- +u4mr .equ 02f8h +smd0_u4mr .btequ 0,u4mr +smd1_u4mr .btequ 1,u4mr +smd2_u4mr .btequ 2,u4mr +ckdir_u4mr .btequ 3,u4mr +stps_u4mr .btequ 4,u4mr +pry_u4mr .btequ 5,u4mr +prye_u4mr .btequ 6,u4mr +iopol_u4mr .btequ 7,u4mr +;-------------------------------------------------------------------- +; uart4 bit rate generator adr:02f9h +;-------------------------------------------------------------------- +u4brg .equ 02f9h +;-------------------------------------------------------------------- +; uart4 transmit buffer Register adr:02fbh-02fah +;-------------------------------------------------------------------- +u4tb .equ 02fah +u4tbl .equ u4tb +u4tbh .equ u4tb+1 +;-------------------------------------------------------------------- +; uart4 transmit receive Control Register 0 adr:02fch +;-------------------------------------------------------------------- +u4c0 .equ 02fch +clk0_u4c0 .btequ 0,u4c0 +clk1_u4c0 .btequ 1,u4c0 +crs_u4c0 .btequ 2,u4c0 +txept_u4c0 .btequ 3,u4c0 +crd_u4c0 .btequ 4,u4c0 +nch_u4c0 .btequ 5,u4c0 +ckpol_u4c0 .btequ 6,u4c0 +uform_u4c0 .btequ 7,u4c0 +;-------------------------------------------------------------------- +; uart4 transmit receive Control Register 1 adr:02fdh +;-------------------------------------------------------------------- +u4c1 .equ 02fdh +te_u4c1 .btequ 0,u4c1 +ti_u4c1 .btequ 1,u4c1 +re_u4c1 .btequ 2,u4c1 +ri_u4c1 .btequ 3,u4c1 +u4irs_u4c1 .btequ 4,u4c1 +u4rrm_u4c1 .btequ 5,u4c1 +u4lch_u4c1 .btequ 6,u4c1 +sclkstpb_u4c1 .btequ 7,u4c1 +u4ere_u4c1 .btequ 7,u4c1 +;-------------------------------------------------------------------- +; uart4 receive buffer Register adr:02ffh-02feh +;-------------------------------------------------------------------- +u4rb .equ 02feh +u4rbl .equ u4rb +u4rbh .equ u4rb+1 +abt_u4rb .btequ 3,u4rbh +oer_u4rb .btequ 4,u4rbh +fer_u4rb .btequ 5,u4rbh +per_u4rb .btequ 6,u4rbh +sum_u4rb .btequ 7,u4rbh +;-------------------------------------------------------------------- +; +; +; timer +; +; +;-------------------------------------------------------------------- +; timer b3,4,5 count start flag adr:0300h +;-------------------------------------------------------------------- +tbsr .equ 0300h +tb3s .btequ 5,tbsr +tb4s .btequ 6,tbsr +tb5s .btequ 7,tbsr +;-------------------------------------------------------------------- +; timer a1-1 Register adr:0303h-0302h +;-------------------------------------------------------------------- +ta11 .equ 0302h +;-------------------------------------------------------------------- +; timer a2-1 Register adr:0305h-0304h +;-------------------------------------------------------------------- +ta21 .equ 0304h +;-------------------------------------------------------------------- +; timer a4-1 Register adr:0307h-0306h +;-------------------------------------------------------------------- +ta41 .equ 0306h +;-------------------------------------------------------------------- +; three phase pwm Control Register 0 adr:0308h +;-------------------------------------------------------------------- +invc0 .equ 0308h +inv00 .btequ 0,invc0 +inv01 .btequ 1,invc0 +inv02 .btequ 2,invc0 +inv03 .btequ 3,invc0 +inv04 .btequ 4,invc0 +inv05 .btequ 5,invc0 +inv06 .btequ 6,invc0 +inv07 .btequ 7,invc0 +;-------------------------------------------------------------------- +; three phase pwm Control Register 1 adr:0309h +;-------------------------------------------------------------------- +invc1 .equ 0309h +inv10 .btequ 0,invc1 +inv11 .btequ 1,invc1 +inv12 .btequ 2,invc1 +inv13 .btequ 3,invc1 +inv14 .btequ 4,invc1 +inv15 .btequ 5,invc1 +inv16 .btequ 6,invc1 +;-------------------------------------------------------------------- +; three phase output buffer Register 0 adr:030ah +;-------------------------------------------------------------------- +idb0 .equ 030ah +du0 .btequ 0,idb0 +dub0 .btequ 1,idb0 +dv0 .btequ 2,idb0 +dvb0 .btequ 3,idb0 +dw0 .btequ 4,idb0 +dwb0 .btequ 5,idb0 +;-------------------------------------------------------------------- +; three phase output buffer Register 1 adr:030bh +;-------------------------------------------------------------------- +idb1 .equ 030bh +du1 .btequ 0,idb1 +dub1 .btequ 1,idb1 +dv1 .btequ 2,idb1 +dvb1 .btequ 3,idb1 +dw1 .btequ 4,idb1 +dwb1 .btequ 5,idb1 +;-------------------------------------------------------------------- +; dead time timer adr:030ch +;-------------------------------------------------------------------- +dtt .equ 030ch +;-------------------------------------------------------------------- +; timer b2 Interrupt occurrence +; frequency set counter adr:030dh +;-------------------------------------------------------------------- +ictb2 .equ 030dh +;-------------------------------------------------------------------- +; timer b3 Register adr:0311h-0310h +;-------------------------------------------------------------------- +tb3 .equ 0310h +;-------------------------------------------------------------------- +; timer b4 Register adr:0313h-0312h +;-------------------------------------------------------------------- +tb4 .equ 0312h +;-------------------------------------------------------------------- +; timer b5 Register adr:0315h-0314h +;-------------------------------------------------------------------- +tb5 .equ 0314h +;-------------------------------------------------------------------- +; timer b3 mode Register adr:031bh +;-------------------------------------------------------------------- +tb3mr .equ 031bh +tmod0_tb3mr .btequ 0,tb3mr +tmod1_tb3mr .btequ 1,tb3mr +mr0_tb3mr .btequ 2,tb3mr +mr1_tb3mr .btequ 3,tb3mr +mr2_tb3mr .btequ 4,tb3mr +mr3_tb3mr .btequ 5,tb3mr +tck0_tb3mr .btequ 6,tb3mr +tck1_tb3mr .btequ 7,tb3mr +;-------------------------------------------------------------------- +; timer b4 mode Register adr:031ch +;-------------------------------------------------------------------- +tb4mr .equ 031ch +tmod0_tb4mr .btequ 0,tb4mr +tmod1_tb4mr .btequ 1,tb4mr +mr0_tb4mr .btequ 2,tb4mr +mr1_tb4mr .btequ 3,tb4mr +mr2_tb4mr .btequ 4,tb4mr +mr3_tb4mr .btequ 5,tb4mr +tck0_tb4mr .btequ 6,tb4mr +tck1_tb4mr .btequ 7,tb4mr +;-------------------------------------------------------------------- +; timer b5 mode Register adr:031dh +;-------------------------------------------------------------------- +tb5mr .equ 031dh +tmod0_tb5mr .btequ 0,tb5mr +tmod1_tb5mr .btequ 1,tb5mr +mr0_tb5mr .btequ 2,tb5mr +mr1_tb5mr .btequ 3,tb5mr +mr2_tb5mr .btequ 4,tb5mr +mr3_tb5mr .btequ 5,tb5mr +tck0_tb5mr .btequ 6,tb5mr +tck1_tb5mr .btequ 7,tb5mr +;-------------------------------------------------------------------- +; Interrupt cause select Register adr:031fh +;-------------------------------------------------------------------- +ifsr .equ 031fh +ifsr0 .btequ 0,ifsr +ifsr1 .btequ 1,ifsr +ifsr2 .btequ 2,ifsr +ifsr3 .btequ 3,ifsr +ifsr4 .btequ 4,ifsr +ifsr5 .btequ 5,ifsr +ifsr6 .btequ 6,ifsr +ifsr7 .btequ 7,ifsr +;-------------------------------------------------------------------- +; +; +; uart3 +; +; +;-------------------------------------------------------------------- +; uart3 special mode Register 4 adr:0324h +;-------------------------------------------------------------------- +u3smr4 .equ 0324h +stareq_u3smr4 .btequ 0,u3smr4 +rstareq_u3smr4 .btequ 1,u3smr4 +stpreq_u3smr4 .btequ 2,u3smr4 +stspsel_u3smr4 .btequ 3,u3smr4 +ackd_u3smr4 .btequ 4,u3smr4 +ackc_u3smr4 .btequ 5,u3smr4 +sclhi_u3smr4 .btequ 6,u3smr4 +swc9_u3smr4 .btequ 7,u3smr4 +;-------------------------------------------------------------------- +; uart3 special mode Register 3 adr:0325h +;-------------------------------------------------------------------- +u3smr3 .equ 0325h +sse_u3smr3 .btequ 0,u3smr3 +ckph_u3smr3 .btequ 1,u3smr3 +dinc_u3smr3 .btequ 2,u3smr3 +nodc_u3smr3 .btequ 3,u3smr3 +err_u3smr3 .btequ 4,u3smr3 +dl0_u3smr3 .btequ 5,u3smr3 +dl1_u3smr3 .btequ 6,u3smr3 +dl2_u3smr3 .btequ 7,u3smr3 +;-------------------------------------------------------------------- +; uart3 special mode Register 2 adr:0326h +;-------------------------------------------------------------------- +u3smr2 .equ 0326h +iicm2_u3smr2 .btequ 0,u3smr2 +csc_u3smr2 .btequ 1,u3smr2 +swc_u3smr2 .btequ 2,u3smr2 +als_u3smr2 .btequ 3,u3smr2 +stc_u3smr2 .btequ 4,u3smr2 +swc2_u3smr2 .btequ 5,u3smr2 +sdhi_u3smr2 .btequ 6,u3smr2 +su1him_u3smr2 .btequ 7,u3smr2 +;-------------------------------------------------------------------- +; uart3 special mode Register adr:0327h +;-------------------------------------------------------------------- +u3smr .equ 0327h +iicm_u3smr .btequ 0,u3smr +abc_u3smr .btequ 1,u3smr +bbs_u3smr .btequ 2,u3smr +lsyn_u3smr .btequ 3,u3smr +abscs_u3smr .btequ 4,u3smr +acse_u3smr .btequ 5,u3smr +sss_u3smr .btequ 6,u3smr +sclkdiv_u3smr .btequ 7,u3smr +;-------------------------------------------------------------------- +; uart3 transmit receive mode Register adr:0328h +;-------------------------------------------------------------------- +u3mr .equ 0328h +smd0_u3mr .btequ 0,u3mr +smd1_u3mr .btequ 1,u3mr +smd2_u3mr .btequ 2,u3mr +ckdir_u3mr .btequ 3,u3mr +stps_u3mr .btequ 4,u3mr +pry_u3mr .btequ 5,u3mr +prye_u3mr .btequ 6,u3mr +iopol_u3mr .btequ 7,u3mr +;-------------------------------------------------------------------- +; uart3 bit rate generator adr:0329h +;-------------------------------------------------------------------- +u3brg .equ 0329h +;-------------------------------------------------------------------- +; uart3 transmit buffer Register adr:032bh-032ah +;-------------------------------------------------------------------- +u3tb .equ 032ah +u3tbl .equ u3tb +u3tbh .equ u3tb+1 +;-------------------------------------------------------------------- +; uart3 transmit receive Control Register 0 adr:032ch +;-------------------------------------------------------------------- +u3c0 .equ 032ch +clk0_u3c0 .btequ 0,u3c0 +clk1_u3c0 .btequ 1,u3c0 +crs_u3c0 .btequ 2,u3c0 +txept_u3c0 .btequ 3,u3c0 +crd_u3c0 .btequ 4,u3c0 +nch_u3c0 .btequ 5,u3c0 +ckpol_u3c0 .btequ 6,u3c0 +uform_u3c0 .btequ 7,u3c0 +;-------------------------------------------------------------------- +; uart3 transmit receive Control Register 1 adr:032dh +;-------------------------------------------------------------------- +u3c1 .equ 032dh +te_u3c1 .btequ 0,u3c1 +ti_u3c1 .btequ 1,u3c1 +re_u3c1 .btequ 2,u3c1 +ri_u3c1 .btequ 3,u3c1 +u3irs_u3c1 .btequ 4,u3c1 +u3rrm_u3c1 .btequ 5,u3c1 +u3lch_u3c1 .btequ 6,u3c1 +sclkstpb_u3c1 .btequ 7,u3c1 +u3ere_u3c1 .btequ 7,u3c1 +;-------------------------------------------------------------------- +; uart3 receive buffer Register adr:032fh-032eh +;-------------------------------------------------------------------- +u3rb .equ 032eh +u3rbl .equ u3rb +u3rbh .equ u3rb+1 +abt_u3rb .btequ 3,u3rbh +oer_u3rb .btequ 4,u3rbh +fer_u3rb .btequ 5,u3rbh +per_u3rb .btequ 6,u3rbh +sum_u3rb .btequ 7,u3rbh +;-------------------------------------------------------------------- +; +; +; uart2 +; +; +;-------------------------------------------------------------------- +; uart2 special mode Register 4 adr:0334h +;-------------------------------------------------------------------- +u2smr4 .equ 0334h +stareq_u2smr4 .btequ 0,u2smr4 +rstareq_u2smr4 .btequ 1,u2smr4 +stpreq_u2smr4 .btequ 2,u2smr4 +stspsel_u2smr4 .btequ 3,u2smr4 +ackd_u2smr4 .btequ 4,u2smr4 +ackc_u2smr4 .btequ 5,u2smr4 +sclhi_u2smr4 .btequ 6,u2smr4 +swc9_u2smr4 .btequ 7,u2smr4 +;-------------------------------------------------------------------- +; uart2 special mode Register 3 adr:0335h +;-------------------------------------------------------------------- +u2smr3 .equ 0335h +sse_u2smr3 .btequ 0,u2smr3 +ckph_u2smr3 .btequ 1,u2smr3 +dinc_u2smr3 .btequ 2,u2smr3 +nodc_u2smr3 .btequ 3,u2smr3 +err_u2smr3 .btequ 4,u2smr3 +dl0_u2smr3 .btequ 5,u2smr3 +dl1_u2smr3 .btequ 6,u2smr3 +dl2_u2smr3 .btequ 7,u2smr3 +;-------------------------------------------------------------------- +; uart2 special mode Register 2 adr:0336h +;-------------------------------------------------------------------- +u2smr2 .equ 0336h +iicm2_u2smr2 .btequ 0,u2smr2 +csc_u2smr2 .btequ 1,u2smr2 +swc_u2smr2 .btequ 2,u2smr2 +als_u2smr2 .btequ 3,u2smr2 +stc_u2smr2 .btequ 4,u2smr2 +swc2_u2smr2 .btequ 5,u2smr2 +sdhi_u2smr2 .btequ 6,u2smr2 +su1him_u2smr2 .btequ 7,u2smr2 +;-------------------------------------------------------------------- +; uart2 special mode Register adr:0337h +;-------------------------------------------------------------------- +u2smr .equ 0337h +iicm_u2smr .btequ 0,u2smr +abc_u2smr .btequ 1,u2smr +bbs_u2smr .btequ 2,u2smr +lsyn_u2smr .btequ 3,u2smr +abscs_u2smr .btequ 4,u2smr +acse_u2smr .btequ 5,u2smr +sss_u2smr .btequ 6,u2smr +sclkdiv_u2smr .btequ 7,u2smr +;-------------------------------------------------------------------- +; uart2 transmit receive mode Register adr:0338h +;-------------------------------------------------------------------- +u2mr .equ 0338h +smd0_u2mr .btequ 0,u2mr +smd1_u2mr .btequ 1,u2mr +smd2_u2mr .btequ 2,u2mr +ckdir_u2mr .btequ 3,u2mr +stps_u2mr .btequ 4,u2mr +pry_u2mr .btequ 5,u2mr +prye_u2mr .btequ 6,u2mr +iopol_u2mr .btequ 7,u2mr +;-------------------------------------------------------------------- +; uart2 bit rate generator adr:0339h +;-------------------------------------------------------------------- +u2brg .equ 0339h +;-------------------------------------------------------------------- +; uart2 transmit buffer Register adr:033bh-033ah +;-------------------------------------------------------------------- +u2tb .equ 033ah +u2tbl .equ u2tb +u2tbh .equ u2tb+1 +;-------------------------------------------------------------------- +; uart2 transmit receive Control Register 0 adr:033ch +;-------------------------------------------------------------------- +u2c0 .equ 033ch +clk0_u2c0 .btequ 0,u2c0 +clk1_u2c0 .btequ 1,u2c0 +crs_u2c0 .btequ 2,u2c0 +txept_u2c0 .btequ 3,u2c0 +crd_u2c0 .btequ 4,u2c0 +nch_u2c0 .btequ 5,u2c0 +ckpol_u2c0 .btequ 6,u2c0 +uform_u2c0 .btequ 7,u2c0 +;-------------------------------------------------------------------- +; uart2 transmit receive Control Register 1 adr:033dh +;-------------------------------------------------------------------- +u2c1 .equ 033dh +te_u2c1 .btequ 0,u2c1 +ti_u2c1 .btequ 1,u2c1 +re_u2c1 .btequ 2,u2c1 +ri_u2c1 .btequ 3,u2c1 +u2irs_u2c1 .btequ 4,u2c1 +u2rrm_u2c1 .btequ 5,u2c1 +u2lch_u2c1 .btequ 6,u2c1 +sclkstpb_u2c1 .btequ 7,u2c1 +u2ere_u2c1 .btequ 7,u2c1 +;-------------------------------------------------------------------- +; uart2 receive buffer Register adr:033fh-033eh +;-------------------------------------------------------------------- +u2rb .equ 033eh +u2rbl .equ u2rb +u2rbh .equ u2rb+1 +abt_u2rb .btequ 3,u2rbh +oer_u2rb .btequ 4,u2rbh +fer_u2rb .btequ 5,u2rbh +per_u2rb .btequ 6,u2rbh +sum_u2rb .btequ 7,u2rbh +;-------------------------------------------------------------------- +; +; +; timer +; +; +;-------------------------------------------------------------------- +; count start flag adr:0340h +;------------------------------------------------------------------- +tabsr .equ 0340h +ta0s .btequ 0,tabsr +ta1s .btequ 1,tabsr +ta2s .btequ 2,tabsr +ta3s .btequ 3,tabsr +ta4s .btequ 4,tabsr +tb0s .btequ 5,tabsr +tb1s .btequ 6,tabsr +tb2s .btequ 7,tabsr +;-------------------------------------------------------------------- +; clock prescaler reset flag adr:0341h +;-------------------------------------------------------------------- +cpsrf .equ 0341h +cpsr .btequ 7,cpsrf +;-------------------------------------------------------------------- +; one shot start flag adr:0342h +;-------------------------------------------------------------------- +onsf .equ 0342h +ta0os .btequ 0,onsf +ta1os .btequ 1,onsf +ta2os .btequ 2,onsf +ta3os .btequ 3,onsf +ta4os .btequ 4,onsf +tazie .btequ 5,onsf +ta0tgl .btequ 6,onsf +ta0tgh .btequ 7,onsf +;-------------------------------------------------------------------- +; trigger select Register adr:0343h +;-------------------------------------------------------------------- +trgsr .equ 0343h +ta1tgl .btequ 0,trgsr +ta1tgh .btequ 1,trgsr +ta2tgl .btequ 2,trgsr +ta2tgh .btequ 3,trgsr +ta3tgl .btequ 4,trgsr +ta3tgh .btequ 5,trgsr +ta4tgl .btequ 6,trgsr +ta4tgh .btequ 7,trgsr +;-------------------------------------------------------------------- +; up down flag adr:0344h +;-------------------------------------------------------------------- +udf .equ 0344h +ta0ud .btequ 0,udf +ta1ud .btequ 1,udf +ta2ud .btequ 2,udf +ta3ud .btequ 3,udf +ta4ud .btequ 4,udf +ta2p .btequ 5,udf +ta3p .btequ 6,udf +ta4p .btequ 7,udf +;-------------------------------------------------------------------- +; timer a0 adr:0347h-0346h +;-------------------------------------------------------------------- +ta0 .equ 0346h +;-------------------------------------------------------------------- +; timer a1 adr:0349h-0348h +;-------------------------------------------------------------------- +ta1 .equ 0348h +;-------------------------------------------------------------------- +; timer a2 adr:034bh-034ah +;-------------------------------------------------------------------- +ta2 .equ 034ah +;-------------------------------------------------------------------- +; timer a3 adr:034dh-034ch +;-------------------------------------------------------------------- +ta3 .equ 034ch +;-------------------------------------------------------------------- +; timer a4 adr:034fh-034eh +;-------------------------------------------------------------------- +ta4 .equ 034eh +;-------------------------------------------------------------------- +; timer b0 adr:0351h-0350h +;-------------------------------------------------------------------- +tb0 .equ 0350h +;-------------------------------------------------------------------- +; timer b1 adr:0353h-0352h +;-------------------------------------------------------------------- +tb1 .equ 0352h +;-------------------------------------------------------------------- +; timer b2 adr:0355h-0354h +;-------------------------------------------------------------------- +tb2 .equ 0354h +;-------------------------------------------------------------------- +; timer a0 mode Register adr:0356h +;-------------------------------------------------------------------- +ta0mr .equ 0356h +tmod0_ta0mr .btequ 0,ta0mr +tmod1_ta0mr .btequ 1,ta0mr +mr1_ta0mr .btequ 3,ta0mr +mr2_ta0mr .btequ 4,ta0mr +mr3_ta0mr .btequ 5,ta0mr +tck0_ta0mr .btequ 6,ta0mr +tck1_ta0mr .btequ 7,ta0mr +;-------------------------------------------------------------------- +; timer a1 mode Register adr:0357h +;-------------------------------------------------------------------- +ta1mr .equ 0357h +tmod0_ta1mr .btequ 0,ta1mr +tmod1_ta1mr .btequ 1,ta1mr +mr1_ta1mr .btequ 3,ta1mr +mr2_ta1mr .btequ 4,ta1mr +mr3_ta1mr .btequ 5,ta1mr +tck0_ta1mr .btequ 6,ta1mr +tck1_ta1mr .btequ 7,ta1mr +;-------------------------------------------------------------------- +; timer a2 mode Register adr:0358h +;-------------------------------------------------------------------- +ta2mr .equ 0358h +tmod0_ta2mr .btequ 0,ta2mr +tmod1_ta2mr .btequ 1,ta2mr +mr1_ta2mr .btequ 3,ta2mr +mr2_ta2mr .btequ 4,ta2mr +mr3_ta2mr .btequ 5,ta2mr +tck0_ta2mr .btequ 6,ta2mr +tck1_ta2mr .btequ 7,ta2mr +;-------------------------------------------------------------------- +; timer a3 mode Register adr:0359h +;-------------------------------------------------------------------- +ta3mr .equ 0359h +tmod0_ta3mr .btequ 0,ta3mr +tmod1_ta3mr .btequ 1,ta3mr +mr1_ta3mr .btequ 3,ta3mr +mr2_ta3mr .btequ 4,ta3mr +mr3_ta3mr .btequ 5,ta3mr +tck0_ta3mr .btequ 6,ta3mr +tck1_ta3mr .btequ 7,ta3mr +;-------------------------------------------------------------------- +; timer a4 mode Register adr:035ah +;-------------------------------------------------------------------- +ta4mr .equ 035ah +tmod0_ta4mr .btequ 0,ta4mr +tmod1_ta4mr .btequ 1,ta4mr +mr1_ta4mr .btequ 3,ta4mr +mr2_ta4mr .btequ 4,ta4mr +mr3_ta4mr .btequ 5,ta4mr +tck0_ta4mr .btequ 6,ta4mr +tck1_ta4mr .btequ 7,ta4mr +;-------------------------------------------------------------------- +; timer b0 mode Register adr:035bh +;-------------------------------------------------------------------- +tb0mr .equ 035bh +tmod0_tb0mr .btequ 0,tb0mr +tmod1_tb0mr .btequ 1,tb0mr +mr0_tb0mr .btequ 2,tb0mr +mr1_tb0mr .btequ 3,tb0mr +mr2_tb0mr .btequ 4,tb0mr +mr3_tb0mr .btequ 5,tb0mr +tck0_tb0mr .btequ 6,tb0mr +tck1_tb0mr .btequ 7,tb0mr +;-------------------------------------------------------------------- +; timer b1 mode Register adr:035ch +;-------------------------------------------------------------------- +tb1mr .equ 035ch +tmod0_tb1mr .btequ 0,tb1mr +tmod1_tb1mr .btequ 1,tb1mr +mr0_tb1mr .btequ 2,tb1mr +mr1_tb1mr .btequ 3,tb1mr +mr2_tb1mr .btequ 4,tb1mr +mr3_tb1mr .btequ 5,tb1mr +tck0_tb1mr .btequ 6,tb1mr +tck1_tb1mr .btequ 7,tb1mr +;-------------------------------------------------------------------- +; timer b2 mode Register adr:035dh +;-------------------------------------------------------------------- +tb2mr .equ 035dh +tmod0_tb2mr .btequ 0,tb2mr +tmod1_tb2mr .btequ 1,tb2mr +mr0_tb2mr .btequ 2,tb2mr +mr1_tb2mr .btequ 3,tb2mr +mr2_tb2mr .btequ 4,tb2mr +mr3_tb2mr .btequ 5,tb2mr +tck0_tb2mr .btequ 6,tb2mr +tck1_tb2mr .btequ 7,tb2mr +;-------------------------------------------------------------------- +; timer b2 special mode Register adr:035eh +;-------------------------------------------------------------------- +tb2sc .equ 035eh +pwcon_tb2sc .btequ 0,tb2sc +;-------------------------------------------------------------------- +; timer count source prescaler Register adr:035fh +;-------------------------------------------------------------------- +tcspr .equ 035fh +cnt0_tcspr .btequ 0,tcspr +cnt1_tcspr .btequ 1,tcspr +cnt2_tcspr .btequ 2,tcspr +cnt3_tcspr .btequ 3,tcspr +cst_tcspr .btequ 7,tcspr +;-------------------------------------------------------------------- +; +; +; uart0 +; +; +;-------------------------------------------------------------------- +; uart0 special mode Register 4 adr:0364h +;-------------------------------------------------------------------- +u0smr4 .equ 0364h +stareq_u0smr4 .btequ 0,u0smr4 +rstareq_u0smr4 .btequ 1,u0smr4 +stpreq_u0smr4 .btequ 2,u0smr4 +stspsel_u0smr4 .btequ 3,u0smr4 +ackd_u0smr4 .btequ 4,u0smr4 +ackc_u0smr4 .btequ 5,u0smr4 +sclhi_u0smr4 .btequ 6,u0smr4 +swc9_u0smr4 .btequ 7,u0smr4 +;-------------------------------------------------------------------- +; uart0 special mode Register 3 adr:0365h +;-------------------------------------------------------------------- +u0smr3 .equ 0365h +sse_u0smr3 .btequ 0,u0smr3 +ckph_u0smr3 .btequ 1,u0smr3 +dinc_u0smr3 .btequ 2,u0smr3 +nodc_u0smr3 .btequ 3,u0smr3 +err_u0smr3 .btequ 4,u0smr3 +dl0_u0smr3 .btequ 5,u0smr3 +dl1_u0smr3 .btequ 6,u0smr3 +dl2_u0smr3 .btequ 7,u0smr3 +;-------------------------------------------------------------------- +; uart0 special mode Register 2 adr:0366h +;-------------------------------------------------------------------- +u0smr2 .equ 0366h +iicm2_u0smr2 .btequ 0,u0smr2 +csc_u0smr2 .btequ 1,u0smr2 +swc_u0smr2 .btequ 2,u0smr2 +als_u0smr2 .btequ 3,u0smr2 +stc_u0smr2 .btequ 4,u0smr2 +swc2_u0smr2 .btequ 5,u0smr2 +sdhi_u0smr2 .btequ 6,u0smr2 +su1him_u0smr2 .btequ 7,u0smr2 +;-------------------------------------------------------------------- +; uart0 special mode Register adr:0367h +;-------------------------------------------------------------------- +u0smr .equ 0367h +iicm_u0smr .btequ 0,u0smr +abc_u0smr .btequ 1,u0smr +bbs_u0smr .btequ 2,u0smr +lsyn_u0smr .btequ 3,u0smr +abscs_u0smr .btequ 4,u0smr +acse_u0smr .btequ 5,u0smr +sss_u0smr .btequ 6,u0smr +sclkdiv_u0smr .btequ 7,u0smr +;-------------------------------------------------------------------- +; uart0 transmit receive mode Register adr:0368h +;-------------------------------------------------------------------- +u0mr .equ 0368h +smd0_u0mr .btequ 0,u0mr +smd1_u0mr .btequ 1,u0mr +smd2_u0mr .btequ 2,u0mr +ckdir_u0mr .btequ 3,u0mr +stps_u0mr .btequ 4,u0mr +pry_u0mr .btequ 5,u0mr +prye_u0mr .btequ 6,u0mr +iopol_u0mr .btequ 7,u0mr +;-------------------------------------------------------------------- +; uart0 bit rate generator adr:0369h +;-------------------------------------------------------------------- +u0brg .equ 0369h +;-------------------------------------------------------------------- +; uart0 transmit buffer Register adr:036bh-036ah +;-------------------------------------------------------------------- +u0tb .equ 036ah +u0tbl .equ u0tb +u0tbh .equ u0tb+1 +;-------------------------------------------------------------------- +; uart0 transmit receive Control Register 0 adr:036ch +;-------------------------------------------------------------------- +u0c0 .equ 036ch +clk0_u0c0 .btequ 0,u0c0 +clk1_u0c0 .btequ 1,u0c0 +crs_u0c0 .btequ 2,u0c0 +txept_u0c0 .btequ 3,u0c0 +crd_u0c0 .btequ 4,u0c0 +nch_u0c0 .btequ 5,u0c0 +ckpol_u0c0 .btequ 6,u0c0 +uform_u0c0 .btequ 7,u0c0 +;-------------------------------------------------------------------- +; uart0 transmit receive Control Register 1 adr:036dh +;-------------------------------------------------------------------- +u0c1 .equ 036dh +te_u0c1 .btequ 0,u0c1 +ti_u0c1 .btequ 1,u0c1 +re_u0c1 .btequ 2,u0c1 +ri_u0c1 .btequ 3,u0c1 +u0irs_u0c1 .btequ 4,u0c1 +u0rrm_u0c1 .btequ 5,u0c1 +u0lch_u0c1 .btequ 6,u0c1 +sclkstpb_u0c1 .btequ 7,u0c1 +u0ere_u0c1 .btequ 7,u0c1 +;-------------------------------------------------------------------- +; uart0 receive buffer Register adr:036fh-036eh +;-------------------------------------------------------------------- +u0rb .equ 036eh +u0rbl .equ u0rb +u0rbh .equ u0rb+1 +abt_u0rb .btequ 3,u0rbh +oer_u0rb .btequ 4,u0rbh +fer_u0rb .btequ 5,u0rbh +per_u0rb .btequ 6,u0rbh +sum_u0rb .btequ 7,u0rbh +;-------------------------------------------------------------------- +; +; +; dma +; +; +;-------------------------------------------------------------------- +; dma0 request cause select Register adr:0378h +;-------------------------------------------------------------------- +dm0sl .equ 0378h +dsel0_dm0sl .btequ 0,dm0sl +dsel1_dm0sl .btequ 1,dm0sl +dsel2_dm0sl .btequ 2,dm0sl +dsel3_dm0sl .btequ 3,dm0sl +dsel4_dm0sl .btequ 4,dm0sl +dsr_dm0sl .btequ 5,dm0sl +drq_dm0sl .btequ 7,dm0sl +;-------------------------------------------------------------------- +; dma1 request cause select Register adr:0379h +;-------------------------------------------------------------------- +dm1sl .equ 0379h +dsel0_dm1sl .btequ 0,dm1sl +dsel1_dm1sl .btequ 1,dm1sl +dsel2_dm1sl .btequ 2,dm1sl +dsel3_dm1sl .btequ 3,dm1sl +dsel4_dm1sl .btequ 4,dm1sl +dsr_dm1sl .btequ 5,dm1sl +drq_dm1sl .btequ 7,dm1sl +;-------------------------------------------------------------------- +; dma2 request cause select Register adr:037ah +;-------------------------------------------------------------------- +dm2sl .equ 037ah +dsel0_dm2sl .btequ 0,dm2sl +dsel1_dm2sl .btequ 1,dm2sl +dsel2_dm2sl .btequ 2,dm2sl +dsel3_dm2sl .btequ 3,dm2sl +dsel4_dm2sl .btequ 4,dm2sl +dsr_dm2sl .btequ 5,dm2sl +drq_dm2sl .btequ 7,dm2sl +;-------------------------------------------------------------------- +; dma3 request cause select Register adr:037bh +;-------------------------------------------------------------------- +dm3sl .equ 037bh +dsel0_dm3sl .btequ 0,dm3sl +dsel1_dm3sl .btequ 1,dm3sl +dsel2_dm3sl .btequ 2,dm3sl +dsel3_dm3sl .btequ 3,dm3sl +dsel4_dm3sl .btequ 4,dm3sl +dsr_dm3sl .btequ 5,dm3sl +drq_dm3sl .btequ 7,dm3sl +;-------------------------------------------------------------------- +; +; +; crc +; +; +;-------------------------------------------------------------------- +; crc data Register adr:037dh-037ch +;-------------------------------------------------------------------- +crcd .equ 037ch +crcdl .equ crcd +crcdh .equ crcd+1 +;-------------------------------------------------------------------- +; crc input Register adr:037eh +;-------------------------------------------------------------------- +crcin .equ 037eh +;-------------------------------------------------------------------- +; +; +; a/d0 +; +; +;-------------------------------------------------------------------- +; a/d0 Register 0 adr:0381h-0380h +;-------------------------------------------------------------------- +ad00 .equ 0380h +ad00l .equ ad00 +ad00h .equ ad00+1 +;-------------------------------------------------------------------- +; a/d0 Register 1 adr:0383h-0382h +;-------------------------------------------------------------------- +ad01 .equ 0382h +ad01l .equ ad01 +ad01h .equ ad01+1 +;-------------------------------------------------------------------- +; a/d0 Register 2 adr:0385h-0384h +;-------------------------------------------------------------------- +ad02 .equ 0384h +ad02l .equ ad02 +ad02h .equ ad02+1 +;-------------------------------------------------------------------- +; a/d0 Register 3 adr:0387h-0386h +;-------------------------------------------------------------------- +ad03 .equ 0386h +ad03l .equ ad03 +ad03h .equ ad03+1 +;-------------------------------------------------------------------- +; a/d0 Register 4 adr:0389h-0388h +;-------------------------------------------------------------------- +ad04 .equ 0388h +ad04l .equ ad04 +ad04h .equ ad04+1 +;-------------------------------------------------------------------- +; a/d0 Register 5 adr:038bh-038ah +;-------------------------------------------------------------------- +ad05 .equ 038ah +ad05l .equ ad05 +ad05h .equ ad05+1 +;-------------------------------------------------------------------- +; a/d0 Register 6 adr:038dh-038ch +;-------------------------------------------------------------------- +ad06 .equ 038ch +ad06l .equ ad06 +ad06h .equ ad06+1 +;-------------------------------------------------------------------- +; a/d0 Register 7 adr:038fh-038eh +;-------------------------------------------------------------------- +ad07 .equ 038eh +ad07l .equ ad07 +ad07h .equ ad07+1 +;-------------------------------------------------------------------- +; a/d0 Control Register 2 adr:0394h +;-------------------------------------------------------------------- +ad0con2 .equ 0394h +smp_ad0con2 .btequ 0,ad0con2 +aps0_ad0con2 .btequ 1,ad0con2 +aps1_ad0con2 .btequ 2,ad0con2 +trg0_ad0con2 .btequ 5,ad0con2 +;-------------------------------------------------------------------- +; a/d0 Control Register 3 adr:0395h +;-------------------------------------------------------------------- +ad0con3 .equ 0395h +dus_ad0con3 .btequ 0,ad0con3 +mss_ad0con3 .btequ 1,ad0con3 +cks2_ad0con3 .btequ 2,ad0con3 +msf0_ad0con3 .btequ 3,ad0con3 +msf1_ad0con3 .btequ 4,ad0con3 +;-------------------------------------------------------------------- +; a/d0 Control Register 0 adr:0396h +;-------------------------------------------------------------------- +ad0con0 .equ 0396h +ch0_ad0con0 .btequ 0,ad0con0 +ch1_ad0con0 .btequ 1,ad0con0 +ch2_ad0con0 .btequ 2,ad0con0 +md0_ad0con0 .btequ 3,ad0con0 +md1_ad0con0 .btequ 4,ad0con0 +trg_ad0con0 .btequ 5,ad0con0 +adst_ad0con0 .btequ 6,ad0con0 +cks0_ad0con0 .btequ 7,ad0con0 +;-------------------------------------------------------------------- +; a/d0 Control Register 1 adr:0397h +;-------------------------------------------------------------------- +ad0con1 .equ 0397h +scan0_ad0con1 .btequ 0,ad0con1 +scan1_ad0con1 .btequ 1,ad0con1 +md2_ad0con1 .btequ 2,ad0con1 +bits_ad0con1 .btequ 3,ad0con1 +cks1_ad0con1 .btequ 4,ad0con1 +vcut_ad0con1 .btequ 5,ad0con1 +opa0_ad0con1 .btequ 6,ad0con1 +opa1_ad0con1 .btequ 7,ad0con1 +;-------------------------------------------------------------------- +; +; +; d/a +; +; +;-------------------------------------------------------------------- +; d/a Register 0 adr:0398h +;-------------------------------------------------------------------- +da0 .equ 0398h +;-------------------------------------------------------------------- +; d/a Register 1 adr:039ah +;-------------------------------------------------------------------- +da1 .equ 039ah +;-------------------------------------------------------------------- +; d/a Control Register adr:039ch +;-------------------------------------------------------------------- +dacon .equ 039ch +da0e .btequ 0,dacon +da1e .btequ 1,dacon +;-------------------------------------------------------------------- +; +; +; port output function Register +; +; +;-------------------------------------------------------------------- +;-------------------------------------------------------------------- +; port output function select Register d1 adr:03a7h +;-------------------------------------------------------------------- +psd1 .equ 03a7h +psd1_0 .btequ 0,psd1 +psd1_1 .btequ 1,psd1 +psd1_6 .btequ 6,psd1 +;-------------------------------------------------------------------- +; port output function select Register c3 adr:03adh +;-------------------------------------------------------------------- +psc3 .equ 03adh +psc3_6 .btequ 6,psc3 +;-------------------------------------------------------------------- +; port output function select Register c adr:03afh +;-------------------------------------------------------------------- +psc .equ 03afh +psc_0 .btequ 0,psc +psc_1 .btequ 1,psc +psc_2 .btequ 2,psc +psc_3 .btequ 3,psc +psc_4 .btequ 4,psc +psc_6 .btequ 6,psc +psc_7 .btequ 7,psc +;-------------------------------------------------------------------- +; port output function select Register a0 adr:03b0h +;-------------------------------------------------------------------- +ps0 .equ 03b0h +ps0_0 .btequ 0,ps0 +ps0_1 .btequ 1,ps0 +ps0_2 .btequ 2,ps0 +ps0_3 .btequ 3,ps0 +ps0_4 .btequ 4,ps0 +ps0_5 .btequ 5,ps0 +ps0_6 .btequ 6,ps0 +ps0_7 .btequ 7,ps0 +;-------------------------------------------------------------------- +; port output function select Register a1 adr:03b1h +;-------------------------------------------------------------------- +ps1 .equ 03b1h +ps1_0 .btequ 0,ps1 +ps1_1 .btequ 1,ps1 +ps1_2 .btequ 2,ps1 +ps1_3 .btequ 3,ps1 +ps1_4 .btequ 4,ps1 +ps1_5 .btequ 5,ps1 +ps1_6 .btequ 6,ps1 +ps1_7 .btequ 7,ps1 +;-------------------------------------------------------------------- +; port output function select Register b0 adr:03b2h +;-------------------------------------------------------------------- +psl0 .equ 03b2h +psl0_2 .btequ 2,psl0 +psl0_4 .btequ 4,psl0 +psl0_6 .btequ 6,psl0 +;-------------------------------------------------------------------- +; port output function select Register b1 adr:03b3h +;-------------------------------------------------------------------- +psl1 .equ 03b3h +psl1_0 .btequ 0,psl1 +psl1_1 .btequ 1,psl1 +psl1_2 .btequ 2,psl1 +psl1_3 .btequ 3,psl1 +psl1_4 .btequ 4,psl1 +psl1_5 .btequ 5,psl1 +psl1_6 .btequ 6,psl1 +psl1_7 .btequ 7,psl1 +;-------------------------------------------------------------------- +; port output function select Register a2 adr:03b4h +;-------------------------------------------------------------------- +ps2 .equ 03b4h +ps2_0 .btequ 0,ps2 +ps2_1 .btequ 1,ps2 +ps2_2 .btequ 2,ps2 +;-------------------------------------------------------------------- +; port output function select Register a3 adr:03b5h +;-------------------------------------------------------------------- +ps3 .equ 03b5h +ps3_0 .btequ 0,ps3 +ps3_1 .btequ 1,ps3 +ps3_2 .btequ 2,ps3 +ps3_3 .btequ 3,ps3 +ps3_4 .btequ 4,ps3 +ps3_5 .btequ 5,ps3 +ps3_6 .btequ 6,ps3 +ps3_7 .btequ 7,ps3 +;-------------------------------------------------------------------- +; port output function select Register b2 adr:03b6h +;-------------------------------------------------------------------- +psl2 .equ 03b6h +psl2_0 .btequ 0,psl2 +psl2_1 .btequ 1,psl2 +psl2_2 .btequ 2,psl2 +;-------------------------------------------------------------------- +; port output function select Register b3 adr:03b7h +;-------------------------------------------------------------------- +psl3 .equ 03b7h +psl3_1 .btequ 1,psl3 +psl3_2 .btequ 2,psl3 +psl3_3 .btequ 3,psl3 +psl3_4 .btequ 4,psl3 +psl3_5 .btequ 5,psl3 +psl3_6 .btequ 6,psl3 +psl3_7 .btequ 7,psl3 +;-------------------------------------------------------------------- +; +; +; port group +; +; +;-------------------------------------------------------------------- +; port p6 Register adr:03c0h +;-------------------------------------------------------------------- +p6 .equ 03c0h +p6_0 .btequ 0,p6 +p6_1 .btequ 1,p6 +p6_2 .btequ 2,p6 +p6_3 .btequ 3,p6 +p6_4 .btequ 4,p6 +p6_5 .btequ 5,p6 +p6_6 .btequ 6,p6 +p6_7 .btequ 7,p6 +;-------------------------------------------------------------------- +; port p7 Register adr:03c1h +;-------------------------------------------------------------------- +p7 .equ 03c1h +p7_0 .btequ 0,p7 +p7_1 .btequ 1,p7 +p7_2 .btequ 2,p7 +p7_3 .btequ 3,p7 +p7_4 .btequ 4,p7 +p7_5 .btequ 5,p7 +p7_6 .btequ 6,p7 +p7_7 .btequ 7,p7 +;-------------------------------------------------------------------- +; port p6 direction Register adr:03c2h +;-------------------------------------------------------------------- +pd6 .equ 03c2h +pd6_0 .btequ 0,pd6 +pd6_1 .btequ 1,pd6 +pd6_2 .btequ 2,pd6 +pd6_3 .btequ 3,pd6 +pd6_4 .btequ 4,pd6 +pd6_5 .btequ 5,pd6 +pd6_6 .btequ 6,pd6 +pd6_7 .btequ 7,pd6 +;-------------------------------------------------------------------- +; port p7 direction Register adr:03c3h +;-------------------------------------------------------------------- +pd7 .equ 03c3h +pd7_0 .btequ 0,pd7 +pd7_1 .btequ 1,pd7 +pd7_2 .btequ 2,pd7 +pd7_3 .btequ 3,pd7 +pd7_4 .btequ 4,pd7 +pd7_5 .btequ 5,pd7 +pd7_6 .btequ 6,pd7 +pd7_7 .btequ 7,pd7 +;-------------------------------------------------------------------- +; port p8 Register adr:03c4h +;-------------------------------------------------------------------- +p8 .equ 03c4h +p8_0 .btequ 0,p8 +p8_1 .btequ 1,p8 +p8_2 .btequ 2,p8 +p8_3 .btequ 3,p8 +p8_4 .btequ 4,p8 +p8_5 .btequ 5,p8 +p8_6 .btequ 6,p8 +p8_7 .btequ 7,p8 +;-------------------------------------------------------------------- +; port p9 Register adr:03c5h +;-------------------------------------------------------------------- +p9 .equ 03c5h +p9_0 .btequ 0,p9 +p9_1 .btequ 1,p9 +p9_2 .btequ 2,p9 +p9_3 .btequ 3,p9 +p9_4 .btequ 4,p9 +p9_5 .btequ 5,p9 +p9_6 .btequ 6,p9 +p9_7 .btequ 7,p9 +;-------------------------------------------------------------------- +; port p8 direction Register adr:03c6h +;-------------------------------------------------------------------- +pd8 .equ 03c6h +pd8_0 .btequ 0,pd8 +pd8_1 .btequ 1,pd8 +pd8_2 .btequ 2,pd8 +pd8_3 .btequ 3,pd8 +pd8_4 .btequ 4,pd8 +pd8_6 .btequ 6,pd8 +pd8_7 .btequ 7,pd8 +;-------------------------------------------------------------------- +; port p9 direction Register adr:03c7h +;-------------------------------------------------------------------- +pd9 .equ 03c7h +pd9_0 .btequ 0,pd9 +pd9_1 .btequ 1,pd9 +pd9_2 .btequ 2,pd9 +pd9_3 .btequ 3,pd9 +pd9_4 .btequ 4,pd9 +pd9_5 .btequ 5,pd9 +pd9_6 .btequ 6,pd9 +pd9_7 .btequ 7,pd9 +;-------------------------------------------------------------------- +; port p10 Register adr:03c8h +;-------------------------------------------------------------------- +p10 .equ 03c8h +p10_0 .btequ 0,p10 +p10_1 .btequ 1,p10 +p10_2 .btequ 2,p10 +p10_3 .btequ 3,p10 +p10_4 .btequ 4,p10 +p10_5 .btequ 5,p10 +p10_6 .btequ 6,p10 +p10_7 .btequ 7,p10 +;-------------------------------------------------------------------- +; port p10 direction Register adr:03cah +;-------------------------------------------------------------------- +pd10 .equ 03cah +pd10_0 .btequ 0,pd10 +pd10_1 .btequ 1,pd10 +pd10_2 .btequ 2,pd10 +pd10_3 .btequ 3,pd10 +pd10_4 .btequ 4,pd10 +pd10_5 .btequ 5,pd10 +pd10_6 .btequ 6,pd10 +pd10_7 .btequ 7,pd10 +;-------------------------------------------------------------------- +; pull-up Control Register3 adr:03dbh +;-------------------------------------------------------------------- +pur3 .equ 03dbh +pu30 .btequ 0,pur3 +pu31 .btequ 1,pur3 +pu32 .btequ 2,pur3 +pu33 .btequ 3,pur3 +pu34 .btequ 4,pur3 +pu35 .btequ 5,pur3 +pu36 .btequ 6,pur3 +pu37 .btequ 7,pur3 +;-------------------------------------------------------------------- +; pull-up Control Register4 adr:03dch +;-------------------------------------------------------------------- +pur4 .equ 03dch +pu40 .btequ 0,pur4 +pu41 .btequ 1,pur4 +pu42 .btequ 2,pur4 +pu43 .btequ 3,pur4 +;-------------------------------------------------------------------- +; port p0 Register adr:03e0h +;-------------------------------------------------------------------- +p0 .equ 03e0h +p0_0 .btequ 0,p0 +p0_1 .btequ 1,p0 +p0_2 .btequ 2,p0 +p0_3 .btequ 3,p0 +p0_4 .btequ 4,p0 +p0_5 .btequ 5,p0 +p0_6 .btequ 6,p0 +p0_7 .btequ 7,p0 +;-------------------------------------------------------------------- +; port p1 Register adr:03e1h +;-------------------------------------------------------------------- +p1 .equ 03e1h +p1_0 .btequ 0,p1 +p1_1 .btequ 1,p1 +p1_2 .btequ 2,p1 +p1_3 .btequ 3,p1 +p1_4 .btequ 4,p1 +p1_5 .btequ 5,p1 +p1_6 .btequ 6,p1 +p1_7 .btequ 7,p1 +;-------------------------------------------------------------------- +; port p0 direction Register adr:03e2h +;-------------------------------------------------------------------- +pd0 .equ 03e2h +pd0_0 .btequ 0,pd0 +pd0_1 .btequ 1,pd0 +pd0_2 .btequ 2,pd0 +pd0_3 .btequ 3,pd0 +pd0_4 .btequ 4,pd0 +pd0_5 .btequ 5,pd0 +pd0_6 .btequ 6,pd0 +pd0_7 .btequ 7,pd0 +;-------------------------------------------------------------------- +; port p1 direction Register adr:03e3h +;-------------------------------------------------------------------- +pd1 .equ 03e3h +pd1_0 .btequ 0,pd1 +pd1_1 .btequ 1,pd1 +pd1_2 .btequ 2,pd1 +pd1_3 .btequ 3,pd1 +pd1_4 .btequ 4,pd1 +pd1_5 .btequ 5,pd1 +pd1_6 .btequ 6,pd1 +pd1_7 .btequ 7,pd1 +;-------------------------------------------------------------------- +; port p2 Register adr:03e4h +;-------------------------------------------------------------------- +p2 .equ 03e4h +p2_0 .btequ 0,p2 +p2_1 .btequ 1,p2 +p2_2 .btequ 2,p2 +p2_3 .btequ 3,p2 +p2_4 .btequ 4,p2 +p2_5 .btequ 5,p2 +p2_6 .btequ 6,p2 +p2_7 .btequ 7,p2 +;-------------------------------------------------------------------- +; port p3 Register adr:03e5h +;-------------------------------------------------------------------- +p3 .equ 03e5h +p3_0 .btequ 0,p3 +p3_1 .btequ 1,p3 +p3_2 .btequ 2,p3 +p3_3 .btequ 3,p3 +p3_4 .btequ 4,p3 +p3_5 .btequ 5,p3 +p3_6 .btequ 6,p3 +p3_7 .btequ 7,p3 +;-------------------------------------------------------------------- +; port p2 direction Register adr:03e6h +;-------------------------------------------------------------------- +pd2 .equ 03e6h +pd2_0 .btequ 0,pd2 +pd2_1 .btequ 1,pd2 +pd2_2 .btequ 2,pd2 +pd2_3 .btequ 3,pd2 +pd2_4 .btequ 4,pd2 +pd2_5 .btequ 5,pd2 +pd2_6 .btequ 6,pd2 +pd2_7 .btequ 7,pd2 +;-------------------------------------------------------------------- +; port p3 direction Register adr:03e7h +;-------------------------------------------------------------------- +pd3 .equ 03e7h +pd3_0 .btequ 0,pd3 +pd3_1 .btequ 1,pd3 +pd3_2 .btequ 2,pd3 +pd3_3 .btequ 3,pd3 +pd3_4 .btequ 4,pd3 +pd3_5 .btequ 5,pd3 +pd3_6 .btequ 6,pd3 +pd3_7 .btequ 7,pd3 +;-------------------------------------------------------------------- +; port p4 Register adr:03e8h +;-------------------------------------------------------------------- +p4 .equ 03e8h +p4_0 .btequ 0,p4 +p4_1 .btequ 1,p4 +p4_2 .btequ 2,p4 +p4_3 .btequ 3,p4 +p4_4 .btequ 4,p4 +p4_5 .btequ 5,p4 +p4_6 .btequ 6,p4 +p4_7 .btequ 7,p4 +;-------------------------------------------------------------------- +; port p5 Register adr:03e9h +;-------------------------------------------------------------------- +p5 .equ 03e9h +p5_0 .btequ 0,p5 +p5_1 .btequ 1,p5 +p5_2 .btequ 2,p5 +p5_3 .btequ 3,p5 +p5_4 .btequ 4,p5 +p5_5 .btequ 5,p5 +p5_6 .btequ 6,p5 +p5_7 .btequ 7,p5 +;-------------------------------------------------------------------- +; port p4 direction Register adr:03eah +;-------------------------------------------------------------------- +pd4 .equ 03eah +pd4_0 .btequ 0,pd4 +pd4_1 .btequ 1,pd4 +pd4_2 .btequ 2,pd4 +pd4_3 .btequ 3,pd4 +pd4_4 .btequ 4,pd4 +pd4_5 .btequ 5,pd4 +pd4_6 .btequ 6,pd4 +pd4_7 .btequ 7,pd4 +;-------------------------------------------------------------------- +; port p5 direction Register adr:03ebh +;-------------------------------------------------------------------- +pd5 .equ 03ebh +pd5_0 .btequ 0,pd5 +pd5_1 .btequ 1,pd5 +pd5_2 .btequ 2,pd5 +pd5_3 .btequ 3,pd5 +pd5_4 .btequ 4,pd5 +pd5_5 .btequ 5,pd5 +pd5_6 .btequ 6,pd5 +pd5_7 .btequ 7,pd5 +;-------------------------------------------------------------------- +; pull-up Control Register 0 adr:03f0h +;-------------------------------------------------------------------- +pur0 .equ 03f0h +pu00 .btequ 0,pur0 +pu01 .btequ 1,pur0 +pu02 .btequ 2,pur0 +pu03 .btequ 3,pur0 +pu04 .btequ 4,pur0 +pu05 .btequ 5,pur0 +pu06 .btequ 6,pur0 +pu07 .btequ 7,pur0 +;-------------------------------------------------------------------- +; pull-up Control Register 1 adr:03f1h +;-------------------------------------------------------------------- +pur1 .equ 03f1h +pu10 .btequ 0,pur1 +pu11 .btequ 1,pur1 +pu12 .btequ 2,pur1 +pu13 .btequ 3,pur1 +;-------------------------------------------------------------------- +; port Control Register adr:03ffh +;-------------------------------------------------------------------- +pcr .equ 03ffh +pcr0 .btequ 0,pcr + diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/stackdef.h b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/stackdef.h new file mode 100644 index 00000000..6177e0a2 --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/stackdef.h @@ -0,0 +1,40 @@ +/***********************************************************************/ +/* */ +/* FILE :stackdef.h */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :define the size of stack. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ + +/********************************************************************** + * startup for M16C/M32C + * Copyright (C) 2004 (2010) Renesas Electronics Corporation. + * and Renesas Solutions Corporation. All rights reserved. * + * stackdef.h : stack size difinition + * + * Function: define ustack size and istack size + * + * $Date: 2005/11/01 04:35:51 $ + * $Revision: 1.5 $ + *********************************************************************/ +////////////////////////////////////////////////////// +// define the size of stack +// When you change the size of stack, +// modify these lines. +// specify stacksize using -D option. +// +#ifndef __STACKSIZE__ +#pragma STACKSIZE 0x300 +#else +#pragma STACKSIZE __STACKSIZE__ +#endif +#ifndef __ISTACKSIZE__ +#pragma ISTACKSIZE 0x300 +#else +#pragma ISTACKSIZE __ISTACKSIZE__ +#endif +extern _UINT _stack_top,_istack_top; + diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/typedefine.h b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/typedefine.h new file mode 100644 index 00000000..88cd7af8 --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/typedefine.h @@ -0,0 +1,34 @@ +/***********************************************************************/ +/* */ +/* FILE :typedefine.h */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :define scalar types. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ + +/***************************************************** + * Startup for M32C/9X + * Copyright (C) 2004 (2010) Renesas Electronics Corporation. + * and Renesas Solutions Corporation. All rights reserved. + * + * typedef for startup + * + * $Date: 2005/11/01 04:35:51 $ + * $Revision: 1.4 $ + ****************************************************/ +#ifndef __TYPEDEF__ +typedef signed char _SBYTE; +typedef unsigned char _UBYTE; +typedef signed short _SWORD; +typedef unsigned short _UWORD; +typedef signed int _SINT; +typedef unsigned int _UINT; +typedef signed long _SDWORD; +typedef unsigned long _UDWORD; +typedef signed long long _SQDWORD; +typedef unsigned long long _UQDWORD; +#endif +#define __TYPEDEF__ diff --git a/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/vector.h b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/vector.h new file mode 100644 index 00000000..8ec3e526 --- /dev/null +++ b/ports/m32c/hew_tests/hew_tst_sem1/hew_tst_sem1/vector.h @@ -0,0 +1,32 @@ +/***********************************************************************/ +/* */ +/* FILE :vector.h */ +/* DATE :Thu, Feb 27, 2014 */ +/* DESCRIPTION :define the top address of the interrupt vectors. */ +/* CPU GROUP :80 */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.18). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/***********************************************************************/ + +/********************************************************************* + * STARTUP for M32C/9X + * Copyright (C) 2004 (2010) Renesas Electronics Corporation. + * and Renesas Solutions Corporation. All rights reserved. * + * + * vector.h : define address for vector + * + * Function:define variable vector's address + * define fixed vector's address + * + * $Date: 2005/11/01 04:35:51 $ + * $Revision: 1.4 $ + ********************************************************************/ +//////////////////////////////////////////// +// declare sfr register using in "resetprg.c" + + +#define Fvectaddr 0xffffdc +#ifndef VECTOR_ADR +#define VECTOR_ADR 0x0fffd00 +#endif diff --git a/ports/m32c/hew_tests/led.pnl b/ports/m32c/hew_tests/led.pnl new file mode 100644 index 00000000..ae11ce86 --- /dev/null +++ b/ports/m32c/hew_tests/led.pnl @@ -0,0 +1,12 @@ +GOF01 30 90 220 230 11 1 5 03e0h 0 1 0 0 ff ffffff +GOF01 80 90 190 220 11 1 5 03e0h 0 1 0 0 ff ffffff +GOF01 30 90 170 180 11 1 5 03e0h 0 1 0 0 ff ffffff +GOF01 30 40 140 170 11 1 5 03e0h 0 1 0 0 ff ffffff +GOF01 80 90 140 170 11 1 5 03e0h 0 1 0 0 ff ffffff +GOF01 50 60 150 170 11 1 5 03e0h 0 1 0 0 ff ffffff +GOF01 30 90 120 130 11 1 5 03e0h 0 1 0 0 ff ffffff +GOF01 30 40 100 120 11 1 5 03e0h 0 1 0 0 ff ffffff +GOF01 80 90 100 120 11 1 5 03e0h 0 1 0 0 ff ffffff +GOF01 40 80 90 100 11 1 5 03E0h 0 1 0 0 ff ffffff +GOF01 10 200 240 280 10 1 5 03E0h 0 1 0 0 1 26 Click stop to view results 0 +GOF01 20 110 50 80 10 1 5 03E0h 0 1 0 0 1 8 Finished 0 diff --git a/ports/m32c/stdint.h b/ports/m32c/stdint.h new file mode 100644 index 00000000..875146c6 --- /dev/null +++ b/ports/m32c/stdint.h @@ -0,0 +1,14 @@ +#ifndef _STDINT +#define _STDINT + + +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed short int int16_t; +typedef unsigned short int uint16_t; +typedef signed long int int32_t; +typedef unsigned long int uint32_t; + + + +#endif /* _STDINT */ diff --git a/ports/m32c/tests-main.c b/ports/m32c/tests-main.c new file mode 100644 index 00000000..ce207d9a --- /dev/null +++ b/ports/m32c/tests-main.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2010, Kelvin Lawson. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. No personal names or organizations' names associated with the + * Atomthreads project may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include "atom.h" +#include "atomport-private.h" +#include "atomtests.h" +#include "atomtimer.h" + + +/* Constants */ + +/* + * Idle thread stack size + * + * This needs to be large enough to handle any interrupt handlers + * and callbacks called by interrupt handlers (e.g. user-created + * timer callbacks) as well as the saving of all context when + * switching away from this thread. + * + * In this case, the idle stack is allocated on the BSS via the + * idle_thread_stack[] byte array. + */ +#define IDLE_STACK_SIZE_BYTES 164 + + +/* + * Main thread stack size + * + * Note that this is not a required OS kernel thread - you will replace + * this with your own application thread. + * + * In this case the Main thread is responsible for calling out to the + * test routines. Once a test routine has finished, the test status is + * printed out on the UART and the thread remains running in a loop + * flashing a LED. + * + * The Main thread stack generally needs to be larger than the idle + * thread stack, as not only does it need to store interrupt handler + * stack saves and context switch saves, but the application main thread + * will generally be carrying out more nested function calls and require + * stack for application code local variables etc. + * + * With all OS tests implemented to date on the AVR, the Main thread + * stack has not exceeded 201 bytes. To allow all tests to run we set + * a minimum main thread stack size of 204 bytes. This may increase in + * future as the codebase changes but for the time being is enough to + * cope with all of the automated tests. + */ +#define MAIN_STACK_SIZE_BYTES 300 + + +/* + * Startup code stack + * + * Some stack space is required at initial startup for running the main() + * routine. This stack space is only temporarily required at first bootup + * and is no longer required as soon as the OS is started. By default + * GCC sets this to the top of RAM (RAMEND) and it grows down from there. + * Because we only need this temporarily, though, it would be wasteful to + * set aside a region at the top of RAM which is not used during runtime. + * + * What we do here is to reuse part of the idle thread's stack during + * initial startup. As soon as we enter the main() routine we move the + * stack pointer to half-way down the idle thread's stack. This is used + * temporarily while calls are made to atomOSInit(), atomThreadCreate() + * and atomOSStart(). Once the OS is started this stack area is no + * longer required, and can be used for its original purpose (for the + * idle thread's stack). + * + * This does mean, however, that we cannot monitor the stack usage of the + * idle thread. Stack usage is monitored by prefilling the stack with a + * known value, and we are obliterating some of that prefilled area by + * using it as our startup stack, so we cannot use the stack-checking API + * to get a true picture of idle thread stack usage. If you wish to + * monitor idle thread stack usage for your applications then you are + * free to use a different region for the startup stack (e.g. set aside + * an area permanently, or place it somewhere you know you can reuse + * later in the application). For the time being, this method gives us a + * simple way of reducing the memory consumption without having to add + * any special AVR-specific considerations to the automated test + * applications. + * + * This optimisation was required to allow some of the larger automated + * test modules to run on devices with 1KB of RAM. You should avoid doing + * this if you can afford to set aside 64 bytes or so, or if you are + * writing your own applications in which you have further control over + * where data is located. + */ + + +/* Local data */ + +/* Application threads' TCBs */ +static ATOM_TCB main_tcb; + +/* Main thread's stack area */ +static uint8_t main_thread_stack[MAIN_STACK_SIZE_BYTES]; + +/* Idle thread's stack area */ +static uint8_t idle_thread_stack[IDLE_STACK_SIZE_BYTES]; + + +/* Forward declarations */ +static void main_thread_func (uint32_t data); + + +/** + * \b main + * + * Program entry point. + * + * Sets up the AVR hardware resources (system tick timer interrupt) necessary + * for the OS to be started. Creates an application thread and starts the OS. + */ + +int main ( void ) +{ + int8_t status; + + init_timerb2(); + init_pin_P0_0(); + /** + * Initialise the OS before creating our threads. + * + * Note that we cannot enable stack-checking on the idle thread on + * this platform because we are already using part of the idle + * thread's stack now as our startup stack. Prefilling for stack + * checking would overwrite our current stack. + * + * If you are not reusing the idle thread's stack during startup then + * you are free to enable stack-checking here. + */ + status = atomOSInit(&idle_thread_stack[0], IDLE_STACK_SIZE_BYTES, FALSE); + if (status == ATOM_OK) + { + + /* Create an application thread */ + status = atomThreadCreate(&main_tcb, + TEST_THREAD_PRIO, main_thread_func, 0, + &main_thread_stack[0], + MAIN_STACK_SIZE_BYTES, + TRUE); + if (status == ATOM_OK) + { + /** + * First application thread successfully created. It is + * now possible to start the OS. Execution will not return + * from atomOSStart(), which will restore the context of + * our application thread and start executing it. + * + * Note that interrupts are still disabled at this point. + * They will be enabled as we restore and execute our first + * thread in archFirstThreadRestore(). + */ + atomOSStart(); + } + } + + while (1) + ; + + /* There was an error starting the OS if we reach here */ + return (0); +} + + +/** + * \b main_thread_func + * + * Entry point for main application thread. + * + * This is the first thread that will be executed when the OS is started. + * + * @param[in] data Unused (optional thread entry parameter) + * + * @return None + */ +static void main_thread_func (uint32_t data) +{ + uint32_t test_status; + int sleep_ticks; + + + + /* Put a message out on the UART */ + printf("Go\n"); + + /* Start test. All tests use the same start API. */ + test_status = test_start(); + + /* Check main thread stack usage (if enabled) */ +#ifdef ATOM_STACK_CHECKING + if (test_status == 0) + { + uint32_t used_bytes, free_bytes; + + /* Check idle thread stack usage */ + if (atomThreadStackCheck (&main_tcb, &used_bytes, &free_bytes) == ATOM_OK) + { + /* Check the thread did not use up to the end of stack */ + if (free_bytes == 0) + { + printf("Main stack overflow\n"); + test_status++; + } + + /* Log the stack usage */ +#ifdef TESTS_LOG_STACK_USAGE + printf("MainUse:%d\n", used_bytes); +#endif + } + + } +#endif + + /* Log final status */ + if (test_status == 0) + { + printf("Pass\n"); + } + else + { + printf("Fail(%d)\n", test_status); + } + + /* Flash LED once per second if passed, very quickly if failed */ + sleep_ticks = (test_status == 0) ? SYSTEM_TICKS_PER_SEC : (SYSTEM_TICKS_PER_SEC/8); + + /* Test finished, flash slowly for pass, fast for fail */ + while (1) + { + /* Put code here to toggle led. Platform specific */ + /* For simulator just use a breakpoint */ + toggle_pin_P0_0(); + + /* Sleep then toggle LED again */ + atomTimerDelay (sleep_ticks); + } + +}