Tweak landing page layout

Author: kmurray

index.md

@@ -6,14 +6,9 @@ The Verilog to Routing (VTR) project provides open-source CAD tools for FPGA arc
 
 <figure style="float:right">
     <img src='/img/vpr_placement.png' alt='VPR Placement' width="350px" />
-    <figcaption>VPR Placement</figcaption>
+    <figcaption>VPR: Placement</figcaption>
 </figure>
 
-<!--<div style="font-size:80%; text-align:center;">-->
-<!--<img src="/img/vpr_placement.png" alt="alternate text" width="350px" style="float:right" />-->
-<!--<p>VPR Placement</p>-->
-<!--</div>-->
-
 Open source CAD tools enable the investigation of new FPGA architectures and CAD algorithms, which are not possible with closed-source tools.
 
 The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. It then perfoms:
@@ -32,10 +27,11 @@ VTR can also produce the information required for bitstream generation to target
 
 VTR is flexible and can taget a wide range of hypothetical, commercial-like and commercial FPGA architectures, and includes benchmark designs suitable for evaluating FPGA architectures.
 
-For more information see the [documentation](https://docs.verilogtorouting.org).
 
+For more information see the [documentation](https://docs.verilogtorouting.org).
 
-<figure style="float:none">
-    <img src="/img/vpr_routing_utilization.png" width="600px" alt="Routing Utilization"/>
-    <figcaption>Routing Utilization</figcaption>
+<figure style="float:right">
+    <img src="/img/vpr_routing_utilization.png" width="400px" alt="Routing Utilization"/>
+    <figcaption>VPR: Routing Utilization</figcaption>
 </figure>
+