diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index aed84079f59..88c982993c8 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -850,7 +850,7 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe * ``cost_variance``: Estimates the initial temperature using the variance of cost after a set of trial swaps. The initial temperature is set to a value proportional to the variance. * ``equilibrium``: Estimates the initial temperature by trying to predict the equilibrium temperature for the initial placement (i.e. the temperature that would result in no change in cost). - **Default** ``cost_variance`` + **Default** ``equilibrium`` .. option:: --init_t diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index f986866ed05..bce97205a8d 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -2323,7 +2323,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio "\tequilibrium: Estimates the initial temperature by trying to " "predict the equilibrium temperature for the initial placement " "(i.e. the temperature that would result in no change in cost).") - .default_value("cost_variance") + .default_value("equilibrium") .show_in(argparse::ShowIn::HELP_ONLY); place_grp.add_argument(args.PlaceInitT, "--init_t") diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt index 1c07cad2e4f..00fafca74c1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.91 vpr 62.53 MiB -1 -1 0.10 16916 1 0.05 -1 -1 32024 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 6 1 13 14 2 8 9 4 4 16 clb auto 23.8 MiB 0.01 22 27 6 15 6 62.5 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.8829e-05 2.8382e-05 0.000261465 0.000217889 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00235757 0.00212728 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00170712 0.00164334 - k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.93 vpr 62.57 MiB -1 -1 0.14 17260 1 0.06 -1 -1 31980 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64076 3 -1 23 23 2 3 5 4 4 16 clb auto 23.8 MiB 0.01 3 12 2 3 7 62.6 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.0445e-05 5.1078e-05 0.000540631 0.00048682 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00313926 0.00293123 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00237872 0.0022794 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.47 vpr 67.04 MiB -1 -1 0.08 27956 1 0.03 -1 -1 35908 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68648 6 1 13 14 2 8 9 4 4 16 clb auto 28.4 MiB 0.00 23 18 450 161 197 92 67.0 MiB 0.00 0.00 1.02737 1.02737 -3.59667 -1.02737 0.545 0.01 2.2386e-05 1.7505e-05 0.00141611 0.00109159 -1 -1 -1 -1 20 11 11 107788 107788 10441.3 652.579 0.01 0.00277003 0.00227007 742 1670 -1 13 3 10 10 137 80 1.2939 0.545 -4.03651 -1.2939 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00106682 0.000989623 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.51 vpr 66.91 MiB -1 -1 0.09 28592 1 0.04 -1 -1 35576 -1 -1 2 3 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68520 3 -1 23 23 2 3 5 4 4 16 clb auto 28.3 MiB 0.01 5 3 12 4 2 6 66.9 MiB 0.00 0.00 0.620233 0.620297 -7.93119 -0.620297 0.545 0.01 6.0765e-05 5.1182e-05 0.000423486 0.000375079 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00215853 0.00198452 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00156675 0.00148493 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt index ace8a8d93f0..7acc2cb6e43 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.12 vpr 61.70 MiB -1 -1 0.11 16536 1 0.08 -1 -1 31596 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63184 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.7 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.8582e-05 2.7966e-05 0.000277936 0.000219445 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.02 0.00248443 0.00222718 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00178059 0.00171145 - k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.12 vpr 61.63 MiB -1 -1 0.15 16580 1 0.06 -1 -1 31648 -1 -1 1 2 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63112 2 -1 16 16 1 2 3 3 3 9 -1 auto 23.2 MiB 0.01 3 6 4 0 2 61.6 MiB 0.00 0.00 0.545 -3.815 -0.545 0.545 0.00 4.1349e-05 3.4027e-05 0.000423997 0.000380122 -1 -1 -1 -1 2 1 1 53894 53894 1178.84 130.982 0.00 0.00258339 0.00244324 283 309 -1 1 1 1 1 8 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00225406 0.00217221 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.56 vpr 66.72 MiB -1 -1 0.09 27956 1 0.04 -1 -1 35668 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68324 6 1 13 14 2 8 9 4 4 16 clb auto 28.1 MiB 0.00 23 18 450 161 197 92 66.7 MiB 0.00 0.00 1.02737 1.02737 -3.59667 -1.02737 0.545 0.01 2.2666e-05 1.781e-05 0.00197092 0.00153227 -1 -1 -1 -1 20 11 11 107788 107788 10441.3 652.579 0.01 0.00365711 0.00291454 742 1670 -1 13 3 10 10 137 80 1.2939 0.545 -4.03651 -1.2939 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00105744 0.000982198 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.59 vpr 66.92 MiB -1 -1 0.10 28208 1 0.04 -1 -1 35676 -1 -1 1 2 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68524 2 -1 16 16 1 2 3 3 3 9 -1 auto 28.4 MiB 0.01 3 3 6 4 0 2 66.9 MiB 0.00 0.00 0.603526 0.603526 -4.0491 -0.603526 0.603526 0.00 3.8014e-05 3.1187e-05 0.000340609 0.000305195 -1 -1 -1 -1 2 1 1 53894 53894 1178.84 130.982 0.00 0.00168803 0.00155817 283 309 -1 1 1 1 1 8 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00165916 0.00159042 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt index 8ad73fd83e5..9c26d09c041 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.08 vpr 61.77 MiB -1 -1 0.12 16500 1 0.10 -1 -1 31836 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63252 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.8 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.6498e-05 2.6643e-05 0.000260655 0.000218319 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00250948 0.00220504 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00176399 0.00169239 - k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.09 vpr 61.68 MiB -1 -1 0.15 16776 1 0.07 -1 -1 31648 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63160 3 -1 23 23 2 3 5 4 4 16 clb auto 23.2 MiB 0.01 3 12 2 3 7 61.7 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.5504e-05 5.6164e-05 0.000543565 0.00049453 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00311117 0.00290556 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.01 0.00 -1 -1 0.00 0.00221081 0.00210995 - k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 5 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 20 1 3 3 79 69 1.6 1.6 -1.8 -1.6 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.53 vpr 66.91 MiB -1 -1 0.11 27956 1 0.04 -1 -1 35928 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68520 6 1 13 14 2 8 9 4 4 16 clb auto 28.4 MiB 0.00 23 18 450 161 197 92 66.9 MiB 0.00 0.00 1.02737 1.02737 -3.59667 -1.02737 0.545 0.01 3.1465e-05 2.5612e-05 0.00200812 0.00158328 -1 -1 -1 -1 20 11 11 107788 107788 10441.3 652.579 0.01 0.00347702 0.00285088 742 1670 -1 13 3 10 10 137 80 1.2939 0.545 -4.03651 -1.2939 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00103911 0.000961979 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.52 vpr 66.79 MiB -1 -1 0.09 28480 1 0.04 -1 -1 35808 -1 -1 2 3 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68396 3 -1 23 23 2 3 5 4 4 16 clb auto 28.3 MiB 0.01 5 3 12 4 2 6 66.8 MiB 0.00 0.00 0.620233 0.620297 -7.93119 -0.620297 0.545 0.01 5.1837e-05 4.2663e-05 0.000437978 0.000389997 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00219175 0.00200554 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00153127 0.00144677 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.45 vpr 66.97 MiB -1 -1 0.07 27204 1 0.02 -1 -1 33400 -1 -1 1 3 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68580 3 1 5 6 1 4 5 3 3 9 -1 auto 28.5 MiB 0.00 9 9 12 4 4 4 67.0 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 2.3976e-05 1.7421e-05 0.000132931 0.000104907 -1 -1 -1 -1 20 10 1 53894 53894 4880.82 542.314 0.01 0.000978534 0.000890702 379 725 -1 22 1 3 3 78 68 1.8363 1.8363 -2.38094 -1.8363 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000827119 0.000789711 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt index 248d5d735f9..05498b4918c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.08 vpr 61.64 MiB -1 -1 0.11 16584 1 0.10 -1 -1 31848 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63124 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.6 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 4.0075e-05 2.932e-05 0.00026592 0.0002219 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00240468 0.00215628 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00168822 0.00161939 - k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.11 vpr 61.76 MiB -1 -1 0.14 16908 1 0.09 -1 -1 31852 -1 -1 1 2 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63240 2 -1 16 16 1 2 3 3 3 9 -1 auto 23.3 MiB 0.01 3 6 4 0 2 61.8 MiB 0.01 0.00 0.545 -3.815 -0.545 0.545 0.01 6.1203e-05 5.2668e-05 0.000507564 0.000460754 -1 -1 -1 -1 2 1 1 53894 53894 1178.84 130.982 0.01 0.00295561 0.00280974 283 309 -1 1 1 1 1 8 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00212103 0.00204508 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.59 vpr 67.04 MiB -1 -1 0.07 28356 1 0.04 -1 -1 36052 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68652 6 1 13 14 2 8 9 4 4 16 clb auto 28.6 MiB 0.00 23 18 450 161 197 92 67.0 MiB 0.00 0.00 1.02737 1.02737 -3.59667 -1.02737 0.545 0.01 3.1952e-05 2.6009e-05 0.00191807 0.00153692 -1 -1 -1 -1 20 11 11 107788 107788 10441.3 652.579 0.01 0.00341384 0.00283497 742 1670 -1 13 3 10 10 137 80 1.2939 0.545 -4.03651 -1.2939 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00107823 0.000999355 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.61 vpr 66.92 MiB -1 -1 0.09 27844 1 0.04 -1 -1 35936 -1 -1 1 2 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68524 2 -1 16 16 1 2 3 3 3 9 -1 auto 28.4 MiB 0.01 3 3 6 4 0 2 66.9 MiB 0.00 0.00 0.603526 0.603526 -4.0491 -0.603526 0.603526 0.00 5.2862e-05 4.5626e-05 0.000412617 0.000370502 -1 -1 -1 -1 2 1 1 53894 53894 1178.84 130.982 0.00 0.00177645 0.00165086 283 309 -1 1 1 1 1 8 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00128885 0.00122116 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt index 621ef7d1d4d..97ecec9f80f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.38 vpr 66.39 MiB 0.01 7296 -1 -1 1 0.04 -1 -1 36064 -1 -1 2 6 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 67988 6 1 13 14 2 8 9 4 4 16 clb auto 28.0 MiB 0.00 24 21 27 11 10 6 66.4 MiB 0.00 0.00 1.02737 1.02737 -3.61973 -1.02737 0.545 0.01 2.9114e-05 2.2771e-05 0.000206441 0.000172217 -1 -1 -1 -1 20 19 1 107788 107788 10441.3 652.579 0.01 0.00123969 0.00112119 742 1670 -1 21 1 6 6 145 97 1.40641 0.545 -4.37126 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.000907177 0.000858671 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.40 vpr 66.52 MiB 0.01 7296 -1 -1 1 0.04 -1 -1 35968 -1 -1 2 3 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 68120 3 1 25 26 2 8 6 4 4 16 clb auto 28.0 MiB 0.01 21 20 15 4 1 10 66.5 MiB 0.00 0.00 0.620233 0.620042 -8.9502 -0.620042 0.557849 0.01 6.3215e-05 5.2267e-05 0.000510931 0.000449792 -1 -1 -1 -1 20 22 1 107788 107788 10441.3 652.579 0.01 0.0022994 0.00210594 742 1670 -1 27 6 18 18 703 470 0.865467 0.557849 -9.14332 -0.865467 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00192643 0.00174498 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.37 vpr 66.52 MiB 0.01 7424 -1 -1 1 0.01 -1 -1 33512 -1 -1 2 6 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 68116 6 2 10 12 2 8 10 4 4 16 clb auto 28.0 MiB 0.00 24 18 30 15 9 6 66.5 MiB 0.00 0.00 0.620297 0.620297 -2.13801 -0.620297 nan 0.01 2.5488e-05 1.7348e-05 0.000155788 0.000118516 -1 -1 -1 -1 20 23 1 107788 107788 10441.3 652.579 0.01 0.00108355 0.00096926 742 1670 -1 18 12 28 28 332 190 0.716884 nan -2.52312 -0.716884 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00183306 0.00161237 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.40 vpr 66.61 MiB 0.01 7552 -1 -1 1 0.03 -1 -1 35812 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68204 6 1 13 14 2 8 9 4 4 16 clb auto 28.3 MiB 0.00 24 18 441 146 185 110 66.6 MiB 0.00 0.00 1.02737 1.02737 -3.59667 -1.02737 0.545 0.01 3.0654e-05 2.4859e-05 0.00173436 0.00139254 -1 -1 -1 -1 20 10 3 107788 107788 10441.3 652.579 0.01 0.00297659 0.00250769 742 1670 -1 15 3 9 9 118 69 1.27357 0.545 -3.99586 -1.27357 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.000994824 0.00092077 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.42 vpr 67.05 MiB 0.01 7552 -1 -1 1 0.04 -1 -1 35972 -1 -1 2 3 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68660 3 1 25 26 2 8 6 4 4 16 clb auto 28.4 MiB 0.01 21 20 15 4 1 10 67.1 MiB 0.00 0.00 0.620233 0.620042 -8.9502 -0.620042 0.557849 0.01 6.7453e-05 5.6664e-05 0.000541631 0.000478532 -1 -1 -1 -1 20 22 1 107788 107788 10441.3 652.579 0.01 0.00237007 0.00216852 742 1670 -1 27 6 18 18 703 470 0.865467 0.557849 -9.14332 -0.865467 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00203863 0.00185383 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.38 vpr 66.67 MiB 0.01 7424 -1 -1 1 0.01 -1 -1 33884 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68268 6 2 10 12 2 8 10 4 4 16 clb auto 28.3 MiB 0.00 24 18 460 144 221 95 66.7 MiB 0.00 0.00 0.620297 0.620297 -2.13801 -0.620297 nan 0.01 3.3435e-05 2.5618e-05 0.00111147 0.000826764 -1 -1 -1 -1 20 7 8 107788 107788 10441.3 652.579 0.01 0.0023734 0.00192454 742 1670 -1 13 3 12 12 158 98 0.738225 nan -2.20594 -0.738225 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.000987786 0.000920326 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt index 48c6371a849..4344ca0783b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.49 vpr 66.52 MiB 0.01 7296 -1 -1 1 0.04 -1 -1 35852 -1 -1 2 6 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 68120 6 1 13 14 2 8 9 4 4 16 clb auto 27.9 MiB 0.00 24 21 27 11 10 6 66.5 MiB 0.00 0.00 1.02737 1.02737 -3.61973 -1.02737 0.545 0.01 2.8263e-05 2.1906e-05 0.000189484 0.000157453 -1 -1 -1 -1 20 19 1 107788 107788 10441.3 652.579 0.01 0.00118418 0.00106937 742 1670 -1 21 1 6 6 145 97 1.40641 0.545 -4.37126 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.000902365 0.000854523 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.52 vpr 66.39 MiB 0.01 7296 -1 -1 1 0.04 -1 -1 35748 -1 -1 2 3 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 67984 3 1 23 24 2 8 6 4 4 16 clb auto 27.9 MiB 0.01 21 20 15 4 1 10 66.4 MiB 0.00 0.00 0.620233 0.620042 -8.4052 -0.620042 0.557849 0.01 8.8844e-05 7.7475e-05 0.00048395 0.000429767 -1 -1 -1 -1 20 22 1 107788 107788 10441.3 652.579 0.01 0.00214369 0.00195479 742 1670 -1 27 6 18 18 703 470 0.865467 0.557849 -8.59832 -0.865467 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00196944 0.0017614 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.44 vpr 66.40 MiB 0.01 7424 -1 -1 1 0.02 -1 -1 33996 -1 -1 2 6 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 67992 6 2 10 12 2 8 10 4 4 16 clb auto 27.9 MiB 0.00 24 18 30 15 9 6 66.4 MiB 0.00 0.00 0.620297 0.620297 -2.13801 -0.620297 nan 0.01 3.497e-05 2.4151e-05 0.000197165 0.000155309 -1 -1 -1 -1 20 23 1 107788 107788 10441.3 652.579 0.01 0.00110982 0.000988097 742 1670 -1 18 12 28 28 332 190 0.716884 nan -2.52312 -0.716884 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00121768 0.00106744 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.50 vpr 66.91 MiB 0.01 7424 -1 -1 1 0.04 -1 -1 35700 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68520 6 1 13 14 2 8 9 4 4 16 clb auto 28.4 MiB 0.00 24 18 441 146 185 110 66.9 MiB 0.00 0.00 1.02737 1.02737 -3.59667 -1.02737 0.545 0.01 2.3602e-05 1.8383e-05 0.00140866 0.00109275 -1 -1 -1 -1 20 10 3 107788 107788 10441.3 652.579 0.01 0.00249426 0.00207487 742 1670 -1 15 3 9 9 118 69 1.27357 0.545 -3.99586 -1.27357 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.000935824 0.000866064 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.53 vpr 66.44 MiB 0.01 7424 -1 -1 1 0.04 -1 -1 35616 -1 -1 2 3 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68036 3 1 23 24 2 8 6 4 4 16 clb auto 28.0 MiB 0.01 21 20 15 4 1 10 66.4 MiB 0.00 0.00 0.620233 0.620042 -8.4052 -0.620042 0.557849 0.01 5.4937e-05 4.5209e-05 0.00044414 0.000392342 -1 -1 -1 -1 20 22 1 107788 107788 10441.3 652.579 0.01 0.0021993 0.00200197 742 1670 -1 27 6 18 18 703 470 0.865467 0.557849 -8.59832 -0.865467 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00199383 0.00180419 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.45 vpr 67.04 MiB 0.01 7552 -1 -1 1 0.02 -1 -1 33864 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68648 6 2 10 12 2 8 10 4 4 16 clb auto 28.4 MiB 0.00 24 18 460 144 221 95 67.0 MiB 0.00 0.00 0.620297 0.620297 -2.13801 -0.620297 nan 0.01 1.862e-05 1.4156e-05 0.000983892 0.000726732 -1 -1 -1 -1 20 7 8 107788 107788 10441.3 652.579 0.01 0.00217529 0.00178026 742 1670 -1 13 3 12 12 158 98 0.738225 nan -2.20594 -0.738225 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00103206 0.000964792 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt index 796fc4871ce..5055fc18ff9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.41 vpr 66.52 MiB 0.01 7296 -1 -1 1 0.04 -1 -1 35704 -1 -1 2 6 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 68120 6 1 13 14 2 8 9 4 4 16 clb auto 28.0 MiB 0.00 24 21 27 11 10 6 66.5 MiB 0.00 0.00 1.02737 1.02737 -3.61973 -1.02737 0.545 0.01 2.8434e-05 2.2319e-05 0.000198583 0.000165404 -1 -1 -1 -1 20 19 1 107788 107788 10441.3 652.579 0.01 0.00126113 0.00114159 742 1670 -1 21 1 6 6 145 97 1.40641 0.545 -4.37126 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.000970526 0.00092005 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.46 vpr 66.32 MiB 0.01 7424 -1 -1 1 0.04 -1 -1 35876 -1 -1 2 3 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 67912 3 1 25 26 2 8 6 4 4 16 clb auto 27.8 MiB 0.01 21 20 15 4 1 10 66.3 MiB 0.00 0.00 0.620233 0.620042 -8.9502 -0.620042 0.557849 0.01 5.7769e-05 4.7816e-05 0.000480065 0.000426911 -1 -1 -1 -1 20 22 1 107788 107788 10441.3 652.579 0.01 0.00238452 0.00220324 742 1670 -1 27 6 18 18 703 470 0.865467 0.557849 -9.14332 -0.865467 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00206677 0.00187244 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.40 vpr 66.39 MiB 0.01 7296 -1 -1 1 0.02 -1 -1 34168 -1 -1 2 6 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 67984 6 2 10 12 2 8 10 4 4 16 clb auto 27.9 MiB 0.00 24 19 30 13 12 5 66.4 MiB 0.00 0.00 0.620297 0.620297 -2.13865 -0.620297 nan 0.01 3.6106e-05 2.6709e-05 0.000174194 0.000134938 -1 -1 -1 -1 20 23 1 107788 107788 10441.3 652.579 0.01 0.00111026 0.000991721 742 1670 -1 18 1 6 6 115 72 0.734392 nan -2.46704 -0.734392 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00096282 0.000913042 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.42 vpr 66.92 MiB 0.01 7424 -1 -1 1 0.04 -1 -1 35320 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68524 6 1 13 14 2 8 9 4 4 16 clb auto 28.4 MiB 0.00 24 18 441 146 185 110 66.9 MiB 0.00 0.00 1.02737 1.02737 -3.59667 -1.02737 0.545 0.01 2.298e-05 1.7823e-05 0.00130623 0.00100078 -1 -1 -1 -1 20 10 3 107788 107788 10441.3 652.579 0.01 0.00245466 0.00203616 742 1670 -1 15 3 9 9 118 69 1.27357 0.545 -3.99586 -1.27357 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00104981 0.00097519 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.48 vpr 66.92 MiB 0.02 7552 -1 -1 1 0.04 -1 -1 35748 -1 -1 2 3 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68528 3 1 25 26 2 8 6 4 4 16 clb auto 28.5 MiB 0.01 21 20 15 4 1 10 66.9 MiB 0.00 0.00 0.620233 0.620042 -8.9502 -0.620042 0.557849 0.01 7.1245e-05 6.0207e-05 0.000494845 0.000439424 -1 -1 -1 -1 20 22 1 107788 107788 10441.3 652.579 0.01 0.00224384 0.00205977 742 1670 -1 27 6 18 18 703 470 0.865467 0.557849 -9.14332 -0.865467 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00202736 0.00183257 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.41 vpr 66.71 MiB 0.01 7424 -1 -1 1 0.02 -1 -1 34248 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68308 6 2 10 12 2 8 10 4 4 16 clb auto 28.3 MiB 0.00 24 18 550 188 245 117 66.7 MiB 0.00 0.00 0.620297 0.619978 -2.13737 -0.619978 nan 0.01 2.1475e-05 1.4712e-05 0.00126359 0.000917777 -1 -1 -1 -1 20 17 8 107788 107788 10441.3 652.579 0.01 0.00273368 0.00223559 742 1670 -1 13 1 6 6 101 64 0.718652 nan -2.2024 -0.718652 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.000867199 0.000810286 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt index aef79a495f7..c8fe592ee48 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.50 vpr 66.65 MiB 0.01 7424 -1 -1 1 0.04 -1 -1 35448 -1 -1 2 6 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 68248 6 1 13 14 2 8 9 4 4 16 clb auto 28.2 MiB 0.00 24 21 27 11 10 6 66.6 MiB 0.00 0.00 1.02737 1.02737 -3.61973 -1.02737 0.545 0.01 2.8893e-05 2.2498e-05 0.000200095 0.00016596 -1 -1 -1 -1 20 19 1 107788 107788 10441.3 652.579 0.01 0.00125978 0.00113884 742 1670 -1 21 1 6 6 145 97 1.40641 0.545 -4.37126 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.000929969 0.000878886 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.54 vpr 66.52 MiB 0.01 7296 -1 -1 1 0.04 -1 -1 35612 -1 -1 2 3 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 68120 3 1 23 24 2 8 6 4 4 16 clb auto 28.0 MiB 0.01 21 20 15 4 1 10 66.5 MiB 0.00 0.00 0.620233 0.620042 -8.4052 -0.620042 0.557849 0.01 5.5939e-05 4.6079e-05 0.000448932 0.000395427 -1 -1 -1 -1 20 22 1 107788 107788 10441.3 652.579 0.01 0.00217818 0.00198289 742 1670 -1 27 6 18 18 703 470 0.865467 0.557849 -8.59832 -0.865467 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00187997 0.00169545 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.45 vpr 66.39 MiB 0.01 7424 -1 -1 1 0.02 -1 -1 33884 -1 -1 2 6 0 0 success v8.0.0-13264-g193f5fbab release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-07-03T23:08:02 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 67988 6 2 10 12 2 8 10 4 4 16 clb auto 27.9 MiB 0.00 24 18 30 15 9 6 66.4 MiB 0.00 0.00 0.620297 0.620297 -2.13801 -0.620297 nan 0.01 3.6643e-05 2.5329e-05 0.000173718 0.00013245 -1 -1 -1 -1 20 23 1 107788 107788 10441.3 652.579 0.01 0.00123821 0.00111443 742 1670 -1 18 12 28 28 332 190 0.716884 nan -2.52312 -0.716884 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00125868 0.00110108 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.52 vpr 66.92 MiB 0.01 7552 -1 -1 1 0.04 -1 -1 35700 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68524 6 1 13 14 2 8 9 4 4 16 clb auto 28.4 MiB 0.01 24 18 441 146 185 110 66.9 MiB 0.00 0.00 1.02737 1.02737 -3.59667 -1.02737 0.545 0.01 2.3118e-05 1.7918e-05 0.00131651 0.00101519 -1 -1 -1 -1 20 10 3 107788 107788 10441.3 652.579 0.01 0.00264603 0.00223029 742 1670 -1 15 3 9 9 118 69 1.27357 0.545 -3.99586 -1.27357 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00112117 0.0010336 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.56 vpr 66.66 MiB 0.01 7424 -1 -1 1 0.04 -1 -1 35616 -1 -1 2 3 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68264 3 1 23 24 2 8 6 4 4 16 clb auto 28.2 MiB 0.01 21 20 15 4 1 10 66.7 MiB 0.00 0.00 0.620233 0.620042 -8.4052 -0.620042 0.557849 0.01 7.0386e-05 5.9713e-05 0.00048477 0.000430154 -1 -1 -1 -1 20 22 1 107788 107788 10441.3 652.579 0.01 0.00224273 0.00205048 742 1670 -1 27 6 18 18 703 470 0.865467 0.557849 -8.59832 -0.865467 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00200723 0.00180129 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.46 vpr 67.04 MiB 0.01 7552 -1 -1 1 0.02 -1 -1 33752 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock 68648 6 2 10 12 2 8 10 4 4 16 clb auto 28.4 MiB 0.00 24 18 460 144 221 95 67.0 MiB 0.00 0.00 0.620297 0.620297 -2.13801 -0.620297 nan 0.01 2.9293e-05 2.3973e-05 0.00106141 0.000789786 -1 -1 -1 -1 20 7 8 107788 107788 10441.3 652.579 0.01 0.00232512 0.00190475 742 1670 -1 13 3 12 12 158 98 0.738225 nan -2.20594 -0.738225 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.000914394 0.000847158 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index c7eda167c1b..6b358140782 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.28 vpr 65.06 MiB -1 -1 0.32 25124 5 0.13 -1 -1 33204 -1 -1 12 10 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66624 10 2 181 183 1 36 24 6 6 36 clb auto 25.8 MiB 0.03 207.924 173 738 313 392 33 65.1 MiB 0.00 0.00 -1 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 12 200 16 646728 646728 19965.4 554.594 0.06 0.0284287 0.0242229 1696 3924 -1 183 13 182 396 7354 2264 2.26643 2.26643 -96.8734 -2.26643 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.00943562 0.0084916 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.25 vpr 66.82 MiB -1 -1 0.33 33580 4 0.13 -1 -1 37244 -1 -1 12 10 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 68420 10 2 181 183 1 36 24 6 6 36 clb auto 27.8 MiB 0.03 207.924 162 3594 1770 1611 213 66.8 MiB 0.01 0.00 -1 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 22 146 15 646728 646728 36341.4 1009.48 0.15 0.0801358 0.0657565 1904 6228 -1 133 9 127 270 4884 1441 2.16995 2.16995 -88.7521 -2.16995 0 0 46159.1 1282.20 0.00 0.01 0.01 -1 -1 0.00 0.00855432 0.00764578 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index 9b0595b4178..885e5882a2f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.18 vpr 65.12 MiB -1 -1 0.07 20056 1 0.02 -1 -1 30184 -1 -1 3 9 0 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66680 9 8 75 70 1 34 20 5 5 25 clb auto 26.3 MiB 0.43 114.248 93 155 44 110 1 65.1 MiB 0.00 0.00 2.48207 2.48207 -27.1572 -2.48207 2.48207 0.01 9.0945e-05 8.1701e-05 0.00141539 0.00134109 -1 -1 -1 -1 38 165 21 151211 75605.7 48493.3 1939.73 0.07 0.0223168 0.0187671 2100 8065 -1 131 11 138 150 6413 3401 2.45975 2.45975 -31.742 -2.45975 0 0 61632.8 2465.31 0.00 0.01 0.01 -1 -1 0.00 0.00481316 0.00444816 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.90 vpr 66.45 MiB -1 -1 0.07 20448 1 0.03 -1 -1 30248 -1 -1 7 19 0 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 68040 19 18 308 249 1 134 44 6 6 36 clb auto 26.7 MiB 3.90 555.076 430 2046 441 1590 15 66.4 MiB 0.02 0.00 4.92757 4.85986 -99.4383 -4.85986 4.85986 0.02 0.000306401 0.000281136 0.0111256 0.0103951 -1 -1 -1 -1 58 821 30 403230 176413 123560. 3432.22 0.20 0.0844156 0.0738626 4154 22415 -1 616 12 418 679 23261 9368 4.85226 4.85226 -102.344 -4.85226 0 0 154963. 4304.53 0.00 0.02 0.02 -1 -1 0.00 0.0155369 0.0145429 53 83 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.22 vpr 67.04 MiB -1 -1 0.07 28260 1 0.02 -1 -1 33988 -1 -1 3 9 0 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 68644 9 8 75 70 1 34 20 5 5 25 clb auto 28.0 MiB 0.55 114.248 86 1748 649 1077 22 67.0 MiB 0.01 0.00 2.48207 2.48207 -26.2408 -2.48207 2.48207 0.02 0.000106774 9.2103e-05 0.00781851 0.00678833 -1 -1 -1 -1 22 233 24 151211 75605.7 31301.6 1252.07 0.08 0.0286007 0.023998 1836 4950 -1 162 13 109 143 4206 2350 2.74859 2.74859 -34.0527 -2.74859 0 0 38887.3 1555.49 0.00 0.01 0.00 -1 -1 0.00 0.00497565 0.00446327 13 18 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.86 vpr 67.69 MiB -1 -1 0.08 28644 1 0.03 -1 -1 34336 -1 -1 7 19 0 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 69312 19 18 308 249 1 134 44 6 6 36 clb auto 28.1 MiB 5.67 555.076 431 7744 3814 3889 41 67.7 MiB 0.08 0.00 4.92757 4.85986 -99.5625 -4.85986 4.85986 0.03 0.000347635 0.000298635 0.0407126 0.0351402 -1 -1 -1 -1 46 892 24 403230 176413 100559. 2793.30 0.36 0.152757 0.129116 3874 18143 -1 727 23 773 1424 46266 18920 6.41328 6.41328 -126.273 -6.41328 0 0 127342. 3537.27 0.00 0.03 0.02 -1 -1 0.00 0.0230107 0.0204902 53 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt index 08bf25ffc28..234512db02e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.34 vpr 58.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 60284 1 4 28 32 2 10 9 4 4 16 clb auto 19.9 MiB 0.00 22 21 27 10 10 7 58.9 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.225e-05 3.6679e-05 0.000383164 0.000352606 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0064028 0.0053995 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00329728 0.00303366 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.31 vpr 58.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 60232 1 4 28 32 2 10 9 4 4 16 clb auto 19.9 MiB 0.00 22 21 27 10 10 7 58.8 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.1789e-05 3.6149e-05 0.000353848 0.000324333 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.005404 0.00455662 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00183826 0.00171243 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.32 vpr 58.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 59900 1 4 28 32 2 10 9 4 4 16 clb auto 19.9 MiB 0.00 22 21 27 10 10 7 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 9.288e-05 8.371e-05 0.00056272 0.000518581 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00656619 0.00552777 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00214154 0.0019592 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.24 vpr 60.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62116 1 4 28 32 2 10 9 4 4 16 clb auto 22.1 MiB 0.00 22 21 774 371 276 127 60.7 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.7321e-05 3.993e-05 0.00449915 0.00382008 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.0106069 0.00872526 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00169671 0.00154408 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.24 vpr 61.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62496 1 4 28 32 2 10 9 4 4 16 clb auto 22.3 MiB 0.00 22 21 774 371 276 127 61.0 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 5.5515e-05 4.7432e-05 0.00516991 0.0044429 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.0115274 0.00951085 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00167376 0.00152137 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.24 vpr 60.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62372 1 4 28 32 2 10 9 4 4 16 clb auto 22.3 MiB 0.00 22 21 774 371 276 127 60.9 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.8008e-05 4.0427e-05 0.0044909 0.00380767 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.010696 0.00880945 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00173292 0.00158056 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cluster_seed_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cluster_seed_type/config/golden_results.txt index 454f9bd007a..42e55d55571 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cluster_seed_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cluster_seed_type/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml diffeq2.v common_--cluster_seed_type_blend 6.77 vpr 69.92 MiB -1 -1 0.15 23224 4 0.10 -1 -1 33452 -1 -1 22 66 0 5 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 71600 66 96 778 595 1 467 189 16 16 256 mult_36 auto 30.5 MiB 0.20 6722.15 3867 38129 11944 25485 700 69.9 MiB 0.22 0.00 13.5168 11.9676 -733.358 -11.9676 11.9676 0.23 0.0012293 0.00115121 0.0930215 0.0871131 -1 -1 -1 -1 52 9459 33 1.21132e+07 3.16567e+06 870783. 3401.49 4.48 0.60084 0.555495 28652 182587 -1 7774 23 2572 4950 928544 268929 12.8496 12.8496 -845.825 -12.8496 0 0 1.14646e+06 4478.35 0.04 0.22 0.12 -1 -1 0.04 0.0731266 0.0686105 - EArch.xml diffeq2.v common_--cluster_seed_type_timing 4.53 vpr 69.87 MiB -1 -1 0.18 22840 4 0.10 -1 -1 33480 -1 -1 22 66 0 5 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 71548 66 96 778 595 1 467 189 16 16 256 mult_36 auto 30.5 MiB 0.20 6551.83 4027 38129 10931 26725 473 69.9 MiB 0.21 0.00 12.92 11.821 -734.537 -11.821 11.821 0.23 0.00123074 0.00115353 0.0941779 0.0882754 -1 -1 -1 -1 48 9214 32 1.21132e+07 3.16567e+06 817991. 3195.28 2.20 0.415994 0.38641 27888 167588 -1 7975 24 3322 6799 1271301 350530 13.154 13.154 -849.543 -13.154 0 0 1.04918e+06 4098.38 0.03 0.27 0.11 -1 -1 0.03 0.0770635 0.0722456 - EArch.xml diffeq2.v common_--cluster_seed_type_max_inputs 6.48 vpr 69.53 MiB -1 -1 0.15 23224 4 0.10 -1 -1 33468 -1 -1 22 66 0 5 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 71200 66 96 778 595 1 464 189 16 16 256 mult_36 auto 30.5 MiB 0.28 6680.33 3919 28373 7766 20329 278 69.5 MiB 0.17 0.00 13.2078 12.0281 -738.098 -12.0281 12.0281 0.22 0.00119784 0.00112182 0.0700888 0.0657397 -1 -1 -1 -1 52 9970 30 1.21132e+07 3.16567e+06 870783. 3401.49 4.12 0.400208 0.370566 28652 182587 -1 8007 20 3357 6704 1372477 375679 13.0635 13.0635 -835.635 -13.0635 0 0 1.14646e+06 4478.35 0.03 0.28 0.12 -1 -1 0.03 0.0740148 0.069885 - EArch.xml diffeq2.v common_--cluster_seed_type_max_pins 4.53 vpr 69.88 MiB -1 -1 0.18 23220 4 0.10 -1 -1 33480 -1 -1 22 66 0 5 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 71552 66 96 778 595 1 464 189 16 16 256 mult_36 auto 30.5 MiB 0.25 6732.23 3928 31083 8255 22537 291 69.9 MiB 0.18 0.00 13.2056 12.003 -736.457 -12.003 12.003 0.23 0.00125624 0.00117918 0.0763028 0.0715574 -1 -1 -1 -1 52 9019 35 1.21132e+07 3.16567e+06 870783. 3401.49 2.22 0.419364 0.388088 28652 182587 -1 7954 20 2686 5259 1001802 293202 13.0605 13.0605 -838.315 -13.0605 0 0 1.14646e+06 4478.35 0.03 0.22 0.12 -1 -1 0.03 0.0684734 0.0643813 - EArch.xml diffeq2.v common_--cluster_seed_type_max_input_pins 7.25 vpr 69.50 MiB -1 -1 0.27 22844 4 0.10 -1 -1 33480 -1 -1 22 66 0 5 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 71172 66 96 778 595 1 464 189 16 16 256 mult_36 auto 30.5 MiB 0.25 6715.25 4044 39213 11992 26834 387 69.5 MiB 0.23 0.00 13.2056 11.9418 -735.124 -11.9418 11.9418 0.30 0.00121378 0.00114118 0.0989951 0.0928669 -1 -1 -1 -1 46 9773 46 1.21132e+07 3.16567e+06 786648. 3072.85 4.57 0.583819 0.539454 27632 162627 -1 8402 24 3019 5739 1097344 305871 13.0928 13.0928 -842.77 -13.0928 0 0 1.01260e+06 3955.47 0.03 0.25 0.12 -1 -1 0.03 0.0798643 0.0747466 - EArch.xml diffeq2.v common_--cluster_seed_type_blend2 9.21 vpr 69.85 MiB -1 -1 0.16 23224 4 0.10 -1 -1 33452 -1 -1 22 66 0 5 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 71528 66 96 778 595 1 467 189 16 16 256 mult_36 auto 30.5 MiB 0.20 7184.04 3659 42465 13171 27963 1331 69.9 MiB 0.23 0.00 13.8986 12.0512 -733.846 -12.0512 12.0512 0.23 0.00119862 0.00112417 0.101825 0.0951952 -1 -1 -1 -1 52 9559 31 1.21132e+07 3.16567e+06 870783. 3401.49 6.80 0.696256 0.642968 28652 182587 -1 7581 22 4048 8402 1397354 423053 13.1979 13.1979 -846.537 -13.1979 0 0 1.14646e+06 4478.35 0.03 0.28 0.12 -1 -1 0.03 0.0730323 0.0685525 + EArch.xml diffeq2.v common_--cluster_seed_type_blend 8.07 vpr 71.94 MiB -1 -1 0.20 31548 4 0.10 -1 -1 37540 -1 -1 22 66 0 5 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 73664 66 96 778 595 1 467 189 16 16 256 mult_36 auto 32.7 MiB 0.28 6722.15 3855 63603 30270 32720 613 71.9 MiB 0.54 0.01 13.5168 11.8115 -731.759 -11.8115 11.8115 0.34 0.0015838 0.00142881 0.189035 0.169355 -1 -1 -1 -1 54 8913 24 1.21132e+07 3.16567e+06 903890. 3530.82 5.05 0.762472 0.688551 28908 188420 -1 7917 21 3895 8403 1514469 426032 13.1113 13.1113 -856.802 -13.1113 0 0 1.17254e+06 4580.24 0.05 0.35 0.18 -1 -1 0.05 0.0837341 0.0771874 + EArch.xml diffeq2.v common_--cluster_seed_type_timing 9.87 vpr 71.59 MiB -1 -1 0.16 31552 4 0.15 -1 -1 37264 -1 -1 22 66 0 5 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 73304 66 96 778 595 1 467 189 16 16 256 mult_36 auto 32.5 MiB 0.27 6551.83 3904 63603 31409 31601 593 71.6 MiB 0.61 0.01 12.92 12.0365 -737.339 -12.0365 12.0365 0.37 0.00162625 0.00147101 0.215151 0.193092 -1 -1 -1 -1 50 10262 48 1.21132e+07 3.16567e+06 843554. 3295.13 6.63 0.938708 0.849562 28144 172338 -1 8195 33 4664 9420 1629662 473055 13.4994 13.4994 -864.126 -13.4994 0 0 1.08719e+06 4246.82 0.05 0.41 0.16 -1 -1 0.05 0.114475 0.10514 + EArch.xml diffeq2.v common_--cluster_seed_type_max_inputs 8.85 vpr 71.66 MiB -1 -1 0.20 31548 4 0.10 -1 -1 37400 -1 -1 22 66 0 5 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 73380 66 96 778 595 1 464 189 16 16 256 mult_36 auto 32.4 MiB 0.39 6680.33 3675 61977 28764 32440 773 71.7 MiB 0.51 0.01 13.2078 12.0862 -739.95 -12.0862 12.0862 0.33 0.00166237 0.00151104 0.188912 0.169672 -1 -1 -1 -1 52 9408 28 1.21132e+07 3.16567e+06 870783. 3401.49 5.76 0.645028 0.586431 28652 182587 -1 7769 20 2996 5953 1014691 299790 12.9839 12.9839 -840.047 -12.9839 0 0 1.14646e+06 4478.35 0.07 0.27 0.22 -1 -1 0.07 0.0854521 0.07925 + EArch.xml diffeq2.v common_--cluster_seed_type_max_pins 7.43 vpr 71.88 MiB -1 -1 0.17 31680 4 0.10 -1 -1 37652 -1 -1 22 66 0 5 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 73600 66 96 778 595 1 464 189 16 16 256 mult_36 auto 32.7 MiB 0.34 6732.23 4026 59809 29376 29931 502 71.9 MiB 0.54 0.01 13.2056 11.7679 -727.861 -11.7679 11.7679 0.33 0.00150878 0.0013486 0.195454 0.175407 -1 -1 -1 -1 52 9475 24 1.21132e+07 3.16567e+06 870783. 3401.49 4.40 0.626474 0.568593 28652 182587 -1 7894 20 2631 5265 944725 272999 12.7564 12.7564 -822.429 -12.7564 0 0 1.14646e+06 4478.35 0.07 0.29 0.18 -1 -1 0.07 0.0966458 0.0896055 + EArch.xml diffeq2.v common_--cluster_seed_type_max_input_pins 14.87 vpr 71.53 MiB -1 -1 0.18 31296 4 0.10 -1 -1 37396 -1 -1 22 66 0 5 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 73248 66 96 778 595 1 464 189 16 16 256 mult_36 auto 32.5 MiB 0.36 6715.25 3787 72817 33489 37980 1348 71.5 MiB 0.58 0.01 13.2056 11.9984 -739.722 -11.9984 11.9984 0.33 0.00151917 0.00136213 0.218433 0.195989 -1 -1 -1 -1 60 9604 40 1.21132e+07 3.16567e+06 1.01260e+06 3955.47 11.81 0.980752 0.888523 29928 206364 -1 7473 20 2992 5911 984789 307180 12.937 12.937 -830.995 -12.937 0 0 1.26536e+06 4942.82 0.05 0.25 0.20 -1 -1 0.05 0.0806253 0.0745171 + EArch.xml diffeq2.v common_--cluster_seed_type_blend2 11.86 vpr 71.72 MiB -1 -1 0.20 31420 4 0.10 -1 -1 37652 -1 -1 22 66 0 5 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 73440 66 96 778 595 1 467 189 16 16 256 mult_36 auto 32.6 MiB 0.27 7184.04 3802 65771 33716 31433 622 71.7 MiB 0.59 0.01 13.8986 11.8837 -729.396 -11.8837 11.8837 0.32 0.00160062 0.00144479 0.201891 0.181485 -1 -1 -1 -1 48 9779 43 1.21132e+07 3.16567e+06 817991. 3195.28 8.86 0.859511 0.778772 27888 167588 -1 8156 24 3768 7670 1371126 380977 13.4414 13.4414 -868.472 -13.4414 0 0 1.04918e+06 4098.38 0.05 0.34 0.15 -1 -1 0.05 0.0927116 0.0854742 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 12766b5c0da..a678e253ad3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.29 vpr 59.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 60868 3 1 5 6 1 4 5 3 3 9 -1 auto 20.6 MiB 0.00 9 9 12 4 4 4 59.4 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 1.1872e-05 8.14e-06 9.3179e-05 7.2143e-05 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.00 0.00107468 0.000996752 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000979352 0.00095045 - k6_frac_N10_40nm.xml conn_order.eblif common 0.29 vpr 58.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 59988 2 1 4 5 1 3 4 3 3 9 -1 auto 20.3 MiB 0.00 6 6 9 4 1 4 58.6 MiB 0.00 0.00 0.69084 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0482e-05 7.006e-06 9.1439e-05 7.0793e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00103924 0.000964643 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000967028 0.000939224 + k6_frac_N10_40nm.xml test_eblif.eblif common 0.23 vpr 61.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 63088 3 1 5 6 1 4 5 3 3 9 -1 auto 23.0 MiB 0.00 9 9 12 4 4 4 61.6 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 1.4164e-05 1.0423e-05 0.00010296 8.0468e-05 -1 -1 -1 -1 20 6 1 53894 53894 4880.82 542.314 0.01 0.000950855 0.000862354 379 725 -1 10 1 3 3 47 36 0.9134 0.9134 -1.45893 -0.9134 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00123469 0.00118718 + k6_frac_N10_40nm.xml conn_order.eblif common 0.25 vpr 61.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62572 2 1 4 5 1 3 4 3 3 9 -1 auto 22.7 MiB 0.00 6 6 9 4 1 4 61.1 MiB 0.00 0.00 0.69084 0.69084 -1.21731 -0.69084 0.69084 0.00 1.3727e-05 1.012e-05 0.00010105 7.9612e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00124763 0.00116641 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00117184 0.00113089 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index 134ec2cb50f..965f1e7dd78 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -x_gaussian_y_uniform.xml stereovision3.v common 1.32 vpr 65.39 MiB -1 -1 0.32 25132 5 0.12 -1 -1 33204 -1 -1 7 10 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66964 10 2 181 183 1 38 19 6 6 36 clb auto 26.0 MiB 0.04 178.808 145 69 21 42 6 65.4 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000234286 0.000211966 0.00250655 0.00240675 -1 -1 -1 -1 6 140 7 646728 377258 -1 -1 0.08 0.0325224 0.0283608 1804 2280 -1 124 5 95 134 3976 1698 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00786313 0.00742222 -x_uniform_y_gaussian.xml stereovision3.v common 1.26 vpr 65.77 MiB -1 -1 0.33 25132 5 0.11 -1 -1 33204 -1 -1 7 10 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67352 10 2 181 183 1 38 19 6 6 36 clb auto 26.4 MiB 0.04 178.808 152 69 24 42 3 65.8 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.00028744 0.000264403 0.00250191 0.00239908 -1 -1 -1 -1 6 134 7 646728 377258 -1 -1 0.08 0.0314553 0.0273397 1804 2280 -1 111 5 77 103 2632 1092 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00784097 0.00740591 -x_gaussian_y_gaussian.xml stereovision3.v common 1.28 vpr 65.75 MiB -1 -1 0.33 25136 5 0.11 -1 -1 33204 -1 -1 7 10 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67332 10 2 181 183 1 38 19 6 6 36 clb auto 26.4 MiB 0.04 178.808 148 69 20 46 3 65.8 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000587128 0.000538921 0.00348281 0.00330861 -1 -1 -1 -1 6 139 6 646728 377258 -1 -1 0.07 0.0311427 0.0273954 1804 2280 -1 118 4 100 132 3670 1619 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00757621 0.00719682 -x_delta_y_uniform.xml stereovision3.v common 1.34 vpr 65.38 MiB -1 -1 0.32 25132 5 0.12 -1 -1 33204 -1 -1 7 10 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66952 10 2 181 183 1 38 19 6 6 36 clb auto 26.4 MiB 0.04 178.808 149 69 19 45 5 65.4 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000236336 0.000213455 0.00241412 0.00231334 -1 -1 -1 -1 10 134 7 646728 377258 -1 -1 0.12 0.0501894 0.0430041 1804 2280 -1 125 4 80 110 3202 1364 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00753184 0.0071548 -x_delta_y_delta.xml stereovision3.v common 1.28 vpr 65.21 MiB -1 -1 0.35 25120 5 0.12 -1 -1 33204 -1 -1 7 10 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66780 10 2 181 183 1 38 19 6 6 36 clb auto 26.2 MiB 0.04 178.808 167 69 20 41 8 65.2 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000232171 0.000209235 0.00240626 0.00230646 -1 -1 -1 -1 24 115 12 646728 377258 -1 -1 0.05 0.0303293 0.0264238 1804 2280 -1 114 12 103 166 4404 1699 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0103933 0.00949905 -x_uniform_y_delta.xml stereovision3.v common 1.32 vpr 65.38 MiB -1 -1 0.32 25132 5 0.11 -1 -1 33204 -1 -1 7 10 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66952 10 2 181 183 1 38 19 6 6 36 clb auto 26.4 MiB 0.04 178.808 131 444 104 303 37 65.4 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000269758 0.000247455 0.00590962 0.00548344 -1 -1 -1 -1 10 120 31 646728 377258 -1 -1 0.15 0.0643122 0.0551131 1804 2280 -1 114 6 104 150 4407 1931 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00818361 0.00769125 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + x_gaussian_y_uniform.xml stereovision3.v common 1.20 vpr 67.74 MiB -1 -1 0.37 33460 4 0.12 -1 -1 37112 -1 -1 7 10 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 69364 10 2 181 183 1 38 19 6 6 36 clb auto 28.6 MiB 0.05 178.808 123 1644 664 873 107 67.7 MiB 0.03 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000251263 0.000211797 0.0197183 0.0167823 -1 -1 -1 -1 6 143 10 646728 377258 -1 -1 0.08 0.051002 0.0432445 1804 2280 -1 93 4 76 106 2693 1173 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00772498 0.00724416 + x_uniform_y_gaussian.xml stereovision3.v common 1.23 vpr 67.49 MiB -1 -1 0.41 33588 4 0.14 -1 -1 36728 -1 -1 7 10 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 69108 10 2 181 183 1 38 19 6 6 36 clb auto 28.3 MiB 0.05 178.808 124 1794 630 1036 128 67.5 MiB 0.03 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000249709 0.000210207 0.0209578 0.017909 -1 -1 -1 -1 6 110 6 646728 377258 -1 -1 0.08 0.051096 0.0434329 1804 2280 -1 88 5 83 119 3158 1307 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00806464 0.00751446 + x_gaussian_y_gaussian.xml stereovision3.v common 1.16 vpr 67.81 MiB -1 -1 0.34 33200 4 0.14 -1 -1 36640 -1 -1 7 10 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 69436 10 2 181 183 1 38 19 6 6 36 clb auto 28.5 MiB 0.05 178.808 125 1344 442 806 96 67.8 MiB 0.02 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.00026918 0.000227728 0.0157306 0.0133988 -1 -1 -1 -1 8 83 4 646728 377258 -1 -1 0.07 0.0505648 0.0427727 1804 2280 -1 82 3 60 82 1907 777 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00752222 0.00711388 + x_delta_y_uniform.xml stereovision3.v common 1.24 vpr 67.99 MiB -1 -1 0.34 33204 4 0.12 -1 -1 37112 -1 -1 7 10 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 69620 10 2 181 183 1 38 19 6 6 36 clb auto 28.8 MiB 0.05 178.808 132 1319 399 813 107 68.0 MiB 0.02 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000263544 0.000215835 0.0157473 0.0134718 -1 -1 -1 -1 24 84 10 646728 377258 -1 -1 0.17 0.107513 0.0891598 1804 2280 -1 84 12 97 159 3720 1640 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0109449 0.00984768 + x_delta_y_delta.xml stereovision3.v common 1.19 vpr 67.74 MiB -1 -1 0.35 33712 4 0.12 -1 -1 36984 -1 -1 7 10 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 69364 10 2 181 183 1 38 19 6 6 36 clb auto 28.6 MiB 0.05 178.808 131 769 177 528 64 67.7 MiB 0.02 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000388114 0.000346561 0.010153 0.00881381 -1 -1 -1 -1 38 87 3 646728 377258 -1 -1 0.12 0.0685264 0.0574961 1804 2280 -1 88 3 63 83 2004 812 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00758195 0.00716201 + x_uniform_y_delta.xml stereovision3.v common 1.17 vpr 67.86 MiB -1 -1 0.36 33328 4 0.12 -1 -1 36860 -1 -1 7 10 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 69492 10 2 181 183 1 38 19 6 6 36 clb auto 28.6 MiB 0.05 178.808 129 1819 664 1036 119 67.9 MiB 0.03 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000248577 0.000208967 0.0207732 0.0177042 -1 -1 -1 -1 10 99 5 646728 377258 -1 -1 0.06 0.0506743 0.0431496 1804 2280 -1 91 4 73 98 2443 1017 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00744863 0.00698579 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 29d894b0ca9..4ad2988e22b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack -k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--route_chan_width_30_-check_incremental_sta_consistency 1.3166 0.595 0.781297 -1 -1 0.57 0.757256 -1 1.3166 -1 1.16524 -1 1.77873 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.6593 -1 -1 0.268 3.18526 -1 1.16523 -1 3.40324 -1 -1.46764 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 + arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack + k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.49146 0.595 0.839813 -1 -1 0.57 0.814813 -1 1.49146 -1 1.07141 -1 1.81465 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71781 -1 -1 0.268 3.24281 -1 1.34009 -1 3.30941 -1 -1.43172 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--route_chan_width_30_-check_incremental_sta_consistency 1.66139 0.595 0.781297 -1 -1 0.57 0.757256 -1 1.66139 -1 1.07053 -1 1.38001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.6593 -1 -1 0.268 3.18526 -1 1.51002 -1 3.30853 -1 -1.86636 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.49146 0.595 0.839813 -1 -1 0.57 0.814813 -1 1.49146 -1 1.07141 -1 2.00533 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71781 -1 -1 0.268 3.24281 -1 1.34009 -1 3.30941 -1 -1.24105 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.49146 0.595 0.839813 -1 -1 0.57 0.814813 -1 1.49146 -1 1.07141 -1 2.00533 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71781 -1 -1 0.268 3.24281 -1 1.34009 -1 3.30941 -1 -1.24105 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.49146 0.595 0.839813 -1 -1 0.57 0.814813 -1 1.49146 -1 1.07141 -1 2.00533 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71781 -1 -1 0.268 3.24281 -1 1.34009 -1 3.30941 -1 -1.24105 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.49146 0.595 0.839813 -1 -1 0.57 0.814813 -1 1.49146 -1 1.07141 -1 2.00533 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71781 -1 -1 0.268 3.24281 -1 1.34009 -1 3.30941 -1 -1.24105 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index 54c772b000b..38b29afe9bb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -slicem.xml carry_chain.blif common 0.55 vpr 59.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 60608 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 20.0 MiB 0.14 70 70 15 4 10 1 59.2 MiB 0.00 0.00 0.552322 0.523836 -5.19346 -0.523836 0.523836 0.00 6.9502e-05 6.1709e-05 0.000560427 0.0005174 -1 -1 -1 -1 27 337 26 133321 74067 -1 -1 0.10 0.0143519 0.0119083 1284 5874 -1 249 10 84 84 16544 9291 1.47622 1.47622 -16.7882 -1.47622 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00281556 0.00255387 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + slicem.xml carry_chain.blif common 0.67 vpr 60.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62188 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 21.8 MiB 0.16 70 70 15 2 12 1 60.7 MiB 0.00 0.00 0.552322 0.552322 -5.50609 -0.552322 0.552322 0.00 0.000112039 9.9204e-05 0.000742235 0.000676248 -1 -1 -1 -1 25 275 11 133321 74067 -1 -1 0.23 0.0385246 0.031254 1252 5405 -1 288 16 109 109 22836 14717 2.12661 2.12661 -18.6286 -2.12661 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.00653421 0.00576531 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index 52df0b4226a..790fe5b19fb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.34 vpr 63.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65444 5 3 11 14 2 9 10 4 4 16 clb auto 25.3 MiB 0.00 22 21 30 5 21 4 63.9 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.00 2.0625e-05 1.5838e-05 0.000141061 0.000113781 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.0012242 0.00112081 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00105153 0.000982952 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.34 vpr 63.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65444 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 22 30 6 14 10 63.9 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.00 1.9257e-05 1.5084e-05 0.000141356 0.000116257 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.0014464 0.00133261 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00111831 0.00105174 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.34 vpr 63.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65440 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 22 3 63.9 MiB 0.00 0.00 0.646297 0.646297 -2.19033 -0.646297 0.571 0.00 2.2623e-05 1.7066e-05 0.000152724 0.000121465 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00130932 0.00118172 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00112377 0.00104262 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.34 vpr 63.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65440 5 3 11 14 2 9 10 4 4 16 clb auto 25.3 MiB 0.00 22 21 30 5 21 4 63.9 MiB 0.00 0.00 1.64604 1.6463 -5.31965 -1.6463 0.571 0.00 2.4017e-05 1.7634e-05 0.000164857 0.00012819 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00134436 0.00120613 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00119811 0.00111008 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.33 vpr 63.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65432 5 3 11 14 2 9 10 4 4 16 clb auto 25.3 MiB 0.00 22 22 30 8 14 8 63.9 MiB 0.00 0.00 1.44967 1.44967 -2.9103 -1.44967 0.571 0.00 2.871e-05 1.8826e-05 0.000174794 0.000136637 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00160721 0.00138992 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00121904 0.00112635 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.32 vpr 63.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65056 5 3 11 14 2 9 10 4 4 16 clb auto 25.3 MiB 0.00 22 21 30 5 23 2 63.5 MiB 0.00 0.00 0.146298 0.146298 0 0 0.571 0.00 2.2333e-05 1.7497e-05 0.000149983 0.000123092 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.01 0.00126465 0.00116132 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00112161 0.00103998 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.28 vpr 66.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 67784 5 3 11 14 2 9 10 4 4 16 clb auto 27.9 MiB 0.00 22 20 370 90 177 103 66.2 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.01 2.8444e-05 2.3163e-05 0.00122602 0.000998536 -1 -1 -1 -1 8 15 3 107788 107788 4794.78 299.674 0.01 0.00225959 0.00193154 564 862 -1 24 3 14 14 524 362 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.000956254 0.000881282 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.28 vpr 66.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 67908 5 3 11 14 2 9 10 4 4 16 clb auto 27.9 MiB 0.00 22 20 430 104 172 154 66.3 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.01 2.0103e-05 1.5797e-05 0.000985303 0.000773073 -1 -1 -1 -1 8 11 3 107788 107788 4794.78 299.674 0.01 0.00233131 0.00202398 564 862 -1 20 5 13 13 309 150 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00110213 0.00101662 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.28 vpr 66.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 67824 5 3 11 14 2 9 10 4 4 16 clb auto 27.8 MiB 0.00 22 20 410 113 223 74 66.2 MiB 0.00 0.00 0.646297 0.645978 -2.18937 -0.645978 0.571 0.01 3.1841e-05 2.5339e-05 0.00146272 0.00113068 -1 -1 -1 -1 8 17 8 107788 107788 4794.78 299.674 0.01 0.00280569 0.00228172 564 862 -1 12 8 25 25 377 165 0.592131 0.571 -2.01022 -0.592131 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00134358 0.00120679 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.28 vpr 66.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 68036 5 3 11 14 2 9 10 4 4 16 clb auto 27.9 MiB 0.00 22 20 390 106 205 79 66.4 MiB 0.00 0.00 1.64604 1.64598 -5.31933 -1.64598 0.571 0.01 2.5235e-05 1.8864e-05 0.00121347 0.000871784 -1 -1 -1 -1 8 23 7 107788 107788 4794.78 299.674 0.01 0.00245402 0.00194121 564 862 -1 9 4 11 11 190 81 1.57153 0.571 -4.89933 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00101278 0.000905517 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.29 vpr 66.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 67908 5 3 11 14 2 9 10 4 4 16 clb auto 27.8 MiB 0.00 22 22 30 10 12 8 66.3 MiB 0.00 0.00 1.44967 1.44903 -2.90973 -1.44903 0.571 0.01 4.0089e-05 2.851e-05 0.000237466 0.000182412 -1 -1 -1 -1 8 24 5 107788 107788 4794.78 299.674 0.01 0.00184265 0.00161855 564 862 -1 19 5 18 18 404 200 1.37578 0.571 -2.70755 -1.37578 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00164644 0.00148011 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.28 vpr 66.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 67780 5 3 11 14 2 9 10 4 4 16 clb auto 27.8 MiB 0.00 22 20 370 95 153 122 66.2 MiB 0.00 0.00 0.146298 0.145978 0 0 0.571 0.01 3.1296e-05 2.585e-05 0.00133849 0.00107786 -1 -1 -1 -1 8 11 2 107788 107788 4794.78 299.674 0.01 0.00244223 0.00208521 564 862 -1 17 5 13 13 264 119 0.0706414 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00118209 0.00105613 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index e1d79bdb10a..2736bab4b45 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.36 vpr 65.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67388 5 3 11 14 2 9 10 4 4 16 clb auto 27.2 MiB 0.01 24 21 30 9 19 2 65.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5473e-05 1.7301e-05 0.000167912 0.000130475 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00135898 0.0012276 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00110677 0.00105058 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.39 vpr 65.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67116 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 24 21 30 9 19 2 65.5 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5616e-05 1.7166e-05 0.00017674 0.000137487 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00134039 0.00122011 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00105168 0.00100326 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.37 vpr 65.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67388 5 3 11 14 2 9 10 4 4 16 clb auto 27.2 MiB 0.00 24 21 30 9 19 2 65.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5579e-05 1.7539e-05 0.000171263 0.000133079 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00134321 0.00122373 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00119818 0.00113735 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist_--flat_routing_on 0.87 vpr 70.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 72612 5 3 11 14 2 9 10 4 4 16 clb auto 31.5 MiB 0.01 24 21 30 9 19 2 70.9 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.637e-05 1.8011e-05 0.000182605 0.000143806 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.28 0.00141607 0.00126727 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.13 0.00 0.00 0.13 0.00 0.00117866 0.00111949 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated_--flat_routing_on 0.92 vpr 71.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 73192 5 3 11 14 2 9 10 4 4 16 clb auto 31.7 MiB 0.01 24 21 30 9 19 2 71.5 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5186e-05 1.7057e-05 0.000179994 0.000141571 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.27 0.00171603 0.00156239 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.13 0.00 0.00 0.12 0.00 0.00102213 0.000956952 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed_--flat_routing_on 0.94 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 73188 5 3 11 14 2 9 10 4 4 16 clb auto 31.7 MiB 0.01 24 21 30 9 19 2 71.5 MiB 0.01 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 7.3708e-05 5.4573e-05 0.000412328 0.000301427 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.37 0.00180836 0.00155551 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.13 0.00 0.00 0.13 0.00 0.00105531 0.00099317 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.33 vpr 67.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 69592 5 3 11 14 2 9 10 4 4 16 clb auto 29.6 MiB 0.00 24 20 470 157 233 80 68.0 MiB 0.00 0.00 0.713166 0.620297 -3.41517 -0.620297 0.545 0.01 3.2808e-05 2.6212e-05 0.00175644 0.00136172 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00278199 0.00229402 750 1675 -1 26 3 10 10 347 239 0.869227 0.545 -4.0122 -0.869227 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00104282 0.000958535 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.33 vpr 68.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 69848 5 3 11 14 2 9 10 4 4 16 clb auto 29.8 MiB 0.00 24 20 470 157 233 80 68.2 MiB 0.01 0.00 0.713166 0.620297 -3.41517 -0.620297 0.545 0.01 4.8178e-05 3.7477e-05 0.00194215 0.00145639 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.002929 0.002353 750 1675 -1 26 3 10 10 347 239 0.869227 0.545 -4.0122 -0.869227 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00101005 0.000927011 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.36 vpr 68.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 69644 5 3 11 14 2 9 10 4 4 16 clb auto 29.7 MiB 0.01 24 20 470 157 233 80 68.0 MiB 0.01 0.00 0.713166 0.620297 -3.41517 -0.620297 0.545 0.01 3.3761e-05 2.6832e-05 0.00187696 0.00145854 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00311327 0.00259666 750 1675 -1 26 3 10 10 347 239 0.869227 0.545 -4.0122 -0.869227 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00109409 0.00100261 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist_--flat_routing_on 0.85 vpr 73.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 75476 5 3 11 14 2 9 10 4 4 16 clb auto 34.1 MiB 0.01 24 20 470 157 233 80 73.7 MiB 0.01 0.00 0.713166 0.620297 -3.41517 -0.620297 0.545 0.01 2.4647e-05 1.8997e-05 0.00147348 0.00109713 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.29 0.00253124 0.00204256 858 2299 78 26 3 14 18 543 310 0.826797 0.545 -4.0122 -0.826797 0 0 18030.6 1126.91 0.00 0.14 0.00 0.00 0.13 0.00 0.00108912 0.000973002 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated_--flat_routing_on 0.83 vpr 73.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 75400 5 3 11 14 2 9 10 4 4 16 clb auto 34.2 MiB 0.01 24 20 470 157 233 80 73.6 MiB 0.01 0.00 0.713166 0.620297 -3.41517 -0.620297 0.545 0.01 3.3159e-05 2.6445e-05 0.0018292 0.00140916 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.29 0.00301154 0.00246893 858 2299 78 26 3 14 18 543 310 0.826797 0.545 -4.0122 -0.826797 0 0 18030.6 1126.91 0.00 0.14 0.00 0.00 0.13 0.00 0.000985226 0.000893761 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed_--flat_routing_on 0.85 vpr 73.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 75524 5 3 11 14 2 9 10 4 4 16 clb auto 34.3 MiB 0.01 24 20 470 157 233 80 73.8 MiB 0.01 0.00 0.713166 0.620297 -3.41517 -0.620297 0.545 0.01 3.3928e-05 2.7101e-05 0.00185424 0.00143199 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.28 0.00293834 0.00240114 858 2299 78 26 3 14 18 543 310 0.826797 0.545 -4.0122 -0.826797 0 0 18030.6 1126.91 0.00 0.14 0.00 0.00 0.13 0.00 0.00132602 0.00123387 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt index 628a4ecac06..d5c98287203 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.04 vpr 65.09 MiB 0.01 6528 -1 -1 1 0.02 -1 -1 30164 -1 -1 3 9 0 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66656 9 8 71 66 1 36 20 5 5 25 clb auto 25.9 MiB 0.37 137 104 641 217 414 10 65.1 MiB 0.01 0.00 2.52843 2.52843 -27.6091 -2.52843 2.52843 0.01 8.67e-05 7.787e-05 0.00373235 0.00344665 -1 -1 -1 -1 34 184 17 151211 75605.7 45067.1 1802.68 0.06 0.0209391 0.0180819 2028 7167 -1 163 8 113 147 4448 2390 2.44943 2.44943 -32.3965 -2.44943 0 0 54748.7 2189.95 0.00 0.01 0.01 -1 -1 0.00 0.00417463 0.00389661 14 17 16 6 0 0 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 3.98 vpr 66.44 MiB 0.02 6528 -1 -1 1 0.03 -1 -1 30340 -1 -1 8 19 0 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 68036 19 18 299 240 1 146 45 6 6 36 clb auto 26.7 MiB 2.84 653.57 493 2365 478 1860 27 66.4 MiB 0.02 0.00 4.89372 4.89372 -99.4605 -4.89372 4.89372 0.02 0.000301071 0.000276751 0.0118892 0.0110929 -1 -1 -1 -1 50 1014 29 403230 201615 107229. 2978.57 0.37 0.122549 0.106175 3946 19047 -1 750 24 791 1256 41360 17092 5.0429 5.0429 -109.858 -5.0429 0 0 134937. 3748.26 0.00 0.03 0.01 -1 -1 0.00 0.0206879 0.0188446 62 82 85 13 0 0 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.06 vpr 67.00 MiB 0.01 7552 -1 -1 1 0.02 -1 -1 33928 -1 -1 3 9 0 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 68604 9 8 71 66 1 36 20 5 5 25 clb auto 28.0 MiB 0.47 137 100 1856 839 997 20 67.0 MiB 0.01 0.00 2.52843 2.52843 -26.7717 -2.52843 2.52843 0.02 0.000102478 8.8259e-05 0.00788003 0.00684874 -1 -1 -1 -1 24 258 34 151211 75605.7 33517.4 1340.70 0.10 0.036601 0.0305551 1884 5578 -1 194 11 173 231 7378 4279 3.39217 3.39217 -39.4697 -3.39217 0 0 43252.0 1730.08 0.00 0.01 0.00 -1 -1 0.00 0.00458775 0.00413452 14 17 16 6 0 0 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.99 vpr 68.20 MiB 0.01 7552 -1 -1 1 0.02 -1 -1 34176 -1 -1 8 19 0 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 69836 19 18 299 240 1 146 45 6 6 36 clb auto 28.7 MiB 3.99 653.57 491 6525 2977 3491 57 68.2 MiB 0.07 0.00 4.89372 4.85986 -98.8397 -4.85986 4.85986 0.03 0.000345351 0.00029696 0.0318326 0.0276591 -1 -1 -1 -1 50 1287 45 403230 201615 107229. 2978.57 0.29 0.122312 0.103793 3946 19047 -1 873 21 912 1418 48737 19829 7.20414 7.20414 -142.6 -7.20414 0 0 134937. 3748.26 0.00 0.03 0.02 -1 -1 0.00 0.0214774 0.019203 62 82 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt index a9a6f39c560..c8981260b97 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.30 vpr 58.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 60284 1 4 28 32 2 10 9 4 4 16 clb auto 19.9 MiB 0.00 22 21 27 10 10 7 58.9 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.1304e-05 3.5664e-05 0.000367598 0.000338494 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00515273 0.00432828 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0018417 0.00171607 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.32 vpr 58.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 60280 1 4 28 32 2 10 9 4 4 16 clb auto 20.2 MiB 0.00 22 21 27 10 10 7 58.9 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.1405e-05 3.587e-05 0.000363116 0.000333222 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00506304 0.00425289 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0018187 0.00169123 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.33 vpr 58.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 60276 1 4 28 32 2 10 9 4 4 16 clb auto 20.2 MiB 0.01 22 21 27 10 10 7 58.9 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.1903e-05 3.6273e-05 0.000408105 0.000374276 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0059491 0.00500988 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00179922 0.00167653 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.26 vpr 60.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 62112 1 4 28 32 2 10 9 4 4 16 clb auto 22.0 MiB 0.01 22 21 774 371 276 127 60.7 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 5.5221e-05 4.7071e-05 0.00494045 0.00420065 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.011551 0.00958918 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00169254 0.00153428 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.27 vpr 60.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 62360 1 4 28 32 2 10 9 4 4 16 clb auto 22.3 MiB 0.01 22 21 774 371 276 127 60.9 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.8998e-05 4.1407e-05 0.00452353 0.00383971 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.0112105 0.00927806 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00170963 0.00155396 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.27 vpr 60.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 62112 1 4 28 32 2 10 9 4 4 16 clb auto 22.0 MiB 0.00 22 21 774 371 276 127 60.7 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.7264e-05 3.9741e-05 0.00594611 0.00508072 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.0124357 0.0102841 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00164458 0.00149153 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt index 36b0f63444e..5bea68ef034 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.29 vpr 59.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 60880 3 1 5 6 1 4 5 3 3 9 -1 auto 20.6 MiB 0.00 9 9 12 4 4 4 59.5 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 2.0899e-05 1.5818e-05 0.000131482 0.00010482 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.00 0.00115479 0.001067 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00093356 0.000903442 - k6_frac_N10_40nm.xml conn_order.eblif common 0.30 vpr 59.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 60880 2 1 4 5 1 3 4 3 3 9 -1 auto 21.0 MiB 0.00 6 6 9 4 1 4 59.5 MiB 0.00 0.00 0.69084 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0604e-05 7.044e-06 8.51e-05 6.5445e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00104016 0.000969486 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000950734 0.000923374 + k6_frac_N10_40nm.xml test_eblif.eblif common 0.23 vpr 61.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 62744 3 1 5 6 1 4 5 3 3 9 -1 auto 22.7 MiB 0.00 9 9 12 4 4 4 61.3 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 1.6264e-05 1.1218e-05 0.000134339 0.000103828 -1 -1 -1 -1 20 6 1 53894 53894 4880.82 542.314 0.00 0.000989468 0.000899121 379 725 -1 10 1 3 3 47 36 0.9134 0.9134 -1.45893 -0.9134 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000765108 0.000731602 + k6_frac_N10_40nm.xml conn_order.eblif common 0.22 vpr 60.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 62448 2 1 4 5 1 3 4 3 3 9 -1 auto 22.7 MiB 0.00 6 6 9 4 1 4 61.0 MiB 0.00 0.00 0.69084 0.69084 -1.21731 -0.69084 0.69084 0.00 1.279e-05 9.217e-06 0.000101604 7.9707e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.000961308 0.000880504 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000756954 0.00071939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt index 3f79787318c..1825347bd38 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -x_gaussian_y_uniform.xml stereovision3.v common 1.26 vpr 65.97 MiB 0.05 9984 -1 -1 4 0.13 -1 -1 32752 -1 -1 13 11 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67552 11 30 262 292 2 107 54 7 7 49 clb auto 26.8 MiB 0.10 616.875 417 1584 294 1246 44 66.0 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000416353 0.000367529 0.00994982 0.00908129 -1 -1 -1 -1 10 316 4 1.07788e+06 700622 -1 -1 0.14 0.0562948 0.0492348 2680 3516 -1 303 3 166 264 10866 5200 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0124277 0.0118459 -x_uniform_y_gaussian.xml stereovision3.v common 1.22 vpr 66.48 MiB 0.05 9984 -1 -1 4 0.13 -1 -1 32936 -1 -1 13 11 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 68076 11 30 262 292 2 107 54 7 7 49 clb auto 27.2 MiB 0.08 616.875 414 1788 351 1376 61 66.5 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.01 0.000512963 0.000464617 0.0138881 0.0126547 -1 -1 -1 -1 14 314 2 1.07788e+06 700622 -1 -1 0.10 0.0754498 0.0659735 2680 3516 -1 310 2 155 239 10358 5279 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0120642 0.0115746 -x_gaussian_y_gaussian.xml stereovision3.v common 1.13 vpr 66.14 MiB 0.05 9984 -1 -1 4 0.13 -1 -1 32752 -1 -1 13 11 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67728 11 30 262 292 2 107 54 7 7 49 clb auto 27.1 MiB 0.07 616.875 425 1278 215 1008 55 66.1 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000409433 0.000362671 0.00834634 0.00762868 -1 -1 -1 -1 14 315 4 1.07788e+06 700622 -1 -1 0.09 0.0557333 0.0486885 2680 3516 -1 315 2 153 237 10496 5358 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0113954 0.0109264 -x_delta_y_uniform.xml stereovision3.v common 1.25 vpr 66.16 MiB 0.05 9984 -1 -1 4 0.13 -1 -1 33116 -1 -1 13 11 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67744 11 30 262 292 2 107 54 7 7 49 clb auto 27.2 MiB 0.07 616.875 439 3216 631 2470 115 66.2 MiB 0.03 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000408615 0.000360289 0.0159685 0.0142654 -1 -1 -1 -1 38 324 9 1.07788e+06 700622 -1 -1 0.16 0.0971159 0.0832784 2680 3516 -1 326 2 157 241 10391 4993 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0115714 0.0110971 -x_delta_y_delta.xml stereovision3.v common 1.40 vpr 65.97 MiB 0.04 9984 -1 -1 4 0.13 -1 -1 33116 -1 -1 13 11 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67556 11 30 262 292 2 107 54 7 7 49 clb auto 26.6 MiB 0.08 616.875 458 2706 504 2104 98 66.0 MiB 0.03 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000427931 0.000379909 0.0157036 0.0141546 -1 -1 -1 -1 58 334 10 1.07788e+06 700622 -1 -1 0.26 0.128803 0.109871 2680 3516 -1 328 14 252 425 19869 9742 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0192015 0.0172867 -x_uniform_y_delta.xml stereovision3.v common 1.45 vpr 66.07 MiB 0.05 9984 -1 -1 4 0.13 -1 -1 32748 -1 -1 13 11 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67656 11 30 262 292 2 107 54 7 7 49 clb auto 26.8 MiB 0.07 616.875 435 2400 433 1894 73 66.1 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000404334 0.000354952 0.0128106 0.0115127 -1 -1 -1 -1 34 331 14 1.07788e+06 700622 -1 -1 0.32 0.174611 0.147668 2680 3516 -1 328 16 196 323 13259 6216 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0201871 0.0182425 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + x_gaussian_y_uniform.xml stereovision3.v common 1.32 vpr 68.53 MiB 0.06 11136 -1 -1 4 0.14 -1 -1 37180 -1 -1 13 11 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 70176 11 30 260 290 2 106 54 7 7 49 clb auto 28.9 MiB 0.11 601.862 410 8316 3706 4382 228 68.5 MiB 0.08 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.01 0.000453162 0.000372708 0.0452504 0.0374881 -1 -1 -1 -1 18 294 2 1.07788e+06 700622 -1 -1 0.24 0.139096 0.115666 2680 3516 -1 294 14 205 364 17937 8896 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0198162 0.0175965 + x_uniform_y_gaussian.xml stereovision3.v common 1.27 vpr 68.66 MiB 0.05 11008 -1 -1 4 0.14 -1 -1 36796 -1 -1 13 11 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 70304 11 30 260 290 2 106 54 7 7 49 clb auto 29.1 MiB 0.08 601.862 427 6582 2493 3884 205 68.7 MiB 0.06 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.01 0.000468459 0.000381502 0.0344443 0.02854 -1 -1 -1 -1 10 333 4 1.07788e+06 700622 -1 -1 0.24 0.0998599 0.0841849 2680 3516 -1 318 3 173 276 13040 6410 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0126719 0.0119522 + x_gaussian_y_gaussian.xml stereovision3.v common 1.11 vpr 68.01 MiB 0.04 11008 -1 -1 4 0.13 -1 -1 37308 -1 -1 13 11 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 69640 11 30 260 290 2 106 54 7 7 49 clb auto 28.9 MiB 0.08 601.862 391 7602 3159 4236 207 68.0 MiB 0.08 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.01 0.000437966 0.000357194 0.0428972 0.0354838 -1 -1 -1 -1 14 274 3 1.07788e+06 700622 -1 -1 0.10 0.0946463 0.079051 2680 3516 -1 274 2 150 240 9508 4674 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0118934 0.0113057 + x_delta_y_uniform.xml stereovision3.v common 1.35 vpr 68.61 MiB 0.05 11136 -1 -1 4 0.14 -1 -1 36864 -1 -1 13 11 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 70256 11 30 260 290 2 106 54 7 7 49 clb auto 29.1 MiB 0.08 601.862 454 8928 3901 4795 232 68.6 MiB 0.08 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.00 0.000460902 0.000377205 0.0438501 0.0360874 -1 -1 -1 -1 54 353 10 1.07788e+06 700622 -1 -1 0.33 0.201292 0.167895 2680 3516 -1 356 3 161 252 11536 5889 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0123856 0.0116841 + x_delta_y_delta.xml stereovision3.v common 1.26 vpr 68.18 MiB 0.04 11008 -1 -1 4 0.14 -1 -1 36800 -1 -1 13 11 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 69816 11 30 260 290 2 106 54 7 7 49 clb auto 29.2 MiB 0.09 601.862 448 10764 5492 4983 289 68.2 MiB 0.10 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.00 0.000470829 0.000387225 0.0516894 0.0422739 -1 -1 -1 -1 58 342 16 1.07788e+06 700622 -1 -1 0.21 0.15083 0.1246 2680 3516 -1 335 16 275 552 23457 10563 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.04 0.00 -1 -1 0.00 0.0265677 0.0236852 + x_uniform_y_delta.xml stereovision3.v common 1.35 vpr 68.61 MiB 0.04 11008 -1 -1 4 0.14 -1 -1 37048 -1 -1 13 11 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 70256 11 30 260 290 2 106 54 7 7 49 clb auto 28.9 MiB 0.09 601.862 432 9642 4649 4734 259 68.6 MiB 0.09 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.00 0.000460469 0.00037582 0.0485559 0.0398589 -1 -1 -1 -1 44 311 16 1.07788e+06 700622 -1 -1 0.29 0.193743 0.1599 2680 3516 -1 309 2 154 244 10287 5014 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0133517 0.012591 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt index c253a5c19af..4fa9995ac82 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -slicem.xml carry_chain.blif common 0.56 vpr 58.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-13087-gc7fa1e4cc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T11:11:46 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 59840 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 19.6 MiB 0.14 70 70 15 4 10 1 58.4 MiB 0.00 0.00 0.552322 0.523836 -5.19346 -0.523836 0.523836 0.00 6.9066e-05 6.1567e-05 0.000565679 0.000523075 -1 -1 -1 -1 27 337 26 133321 74067 -1 -1 0.11 0.0166712 0.0129996 1284 5874 -1 249 10 84 84 16544 9291 1.47622 1.47622 -16.7882 -1.47622 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00284048 0.00258062 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + slicem.xml carry_chain.blif common 0.67 vpr 60.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 62184 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 21.9 MiB 0.20 70 70 15 2 12 1 60.7 MiB 0.00 0.00 0.552322 0.552322 -5.50609 -0.552322 0.552322 0.00 8.294e-05 7.1293e-05 0.000626458 0.000571365 -1 -1 -1 -1 25 275 11 133321 74067 -1 -1 0.22 0.0367556 0.0298663 1252 5405 -1 288 16 109 109 22836 14717 2.12661 2.12661 -18.6286 -2.12661 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00384983 0.00335128 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt index 168c2f4d2af..c424228e785 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.34 vpr 64.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65832 5 3 11 14 2 9 10 4 4 16 clb auto 25.9 MiB 0.00 22 21 30 5 21 4 64.3 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.01 2.0768e-05 1.6001e-05 0.000147568 0.000119565 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00129398 0.00118616 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00112596 0.00105625 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.34 vpr 64.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66208 5 3 11 14 2 9 10 4 4 16 clb auto 26.0 MiB 0.00 22 22 30 6 14 10 64.7 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.00 1.9256e-05 1.5057e-05 0.000132205 0.000107658 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00131935 0.00120535 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00110585 0.00104019 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.36 vpr 64.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65728 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 22 3 64.2 MiB 0.00 0.00 0.646297 0.646297 -2.19033 -0.646297 0.571 0.01 2.2141e-05 1.6465e-05 0.000148081 0.000116843 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00135332 0.00122428 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00119514 0.00111047 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.33 vpr 63.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65196 5 3 11 14 2 9 10 4 4 16 clb auto 25.4 MiB 0.00 22 21 30 5 21 4 63.7 MiB 0.00 0.00 1.64604 1.6463 -5.31965 -1.6463 0.571 0.01 2.4032e-05 1.7566e-05 0.000155129 0.000120471 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00131049 0.00117637 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00117652 0.00109158 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.35 vpr 64.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65824 5 3 11 14 2 9 10 4 4 16 clb auto 26.1 MiB 0.00 22 22 30 8 14 8 64.3 MiB 0.00 0.00 1.44967 1.44967 -2.9103 -1.44967 0.571 0.00 2.827e-05 1.8504e-05 0.000168534 0.00013083 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00162991 0.00141589 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0012413 0.00114824 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.33 vpr 64.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 65824 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 23 2 64.3 MiB 0.00 0.00 0.146298 0.146298 0 0 0.571 0.00 2.2475e-05 1.7643e-05 0.000159849 0.000132984 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.01 0.00131473 0.00120754 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00117588 0.00109128 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.30 vpr 66.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 67656 5 3 11 14 2 9 10 4 4 16 clb auto 27.7 MiB 0.00 22 20 370 90 177 103 66.1 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.01 2.9443e-05 2.3962e-05 0.0012498 0.00101955 -1 -1 -1 -1 8 15 3 107788 107788 4794.78 299.674 0.01 0.00228835 0.00195386 564 862 -1 24 3 14 14 524 362 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.000912704 0.000837767 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.27 vpr 66.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 68036 5 3 11 14 2 9 10 4 4 16 clb auto 27.8 MiB 0.00 22 20 430 104 172 154 66.4 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.01 1.9614e-05 1.5415e-05 0.0010293 0.000819149 -1 -1 -1 -1 8 11 3 107788 107788 4794.78 299.674 0.01 0.00205952 0.00175874 564 862 -1 20 5 13 13 309 150 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.000952502 0.000872239 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.28 vpr 66.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 67912 5 3 11 14 2 9 10 4 4 16 clb auto 27.9 MiB 0.01 22 20 410 113 223 74 66.3 MiB 0.00 0.00 0.646297 0.645978 -2.18937 -0.645978 0.571 0.01 3.0873e-05 2.4578e-05 0.00151287 0.0011723 -1 -1 -1 -1 8 17 8 107788 107788 4794.78 299.674 0.01 0.00299477 0.00247792 564 862 -1 12 8 25 25 377 165 0.592131 0.571 -2.01022 -0.592131 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00119501 0.00106059 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.28 vpr 66.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 68036 5 3 11 14 2 9 10 4 4 16 clb auto 28.1 MiB 0.00 22 20 390 106 205 79 66.4 MiB 0.00 0.00 1.64604 1.64598 -5.31933 -1.64598 0.571 0.01 2.9203e-05 2.1796e-05 0.00119597 0.000863886 -1 -1 -1 -1 8 23 7 107788 107788 4794.78 299.674 0.01 0.00259145 0.00208601 564 862 -1 9 4 11 11 190 81 1.57153 0.571 -4.89933 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00102744 0.000926089 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.27 vpr 66.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 67784 5 3 11 14 2 9 10 4 4 16 clb auto 27.8 MiB 0.00 22 22 30 10 12 8 66.2 MiB 0.00 0.00 1.44967 1.44903 -2.90973 -1.44903 0.571 0.01 4.8819e-05 3.7e-05 0.000215878 0.000169501 -1 -1 -1 -1 8 24 5 107788 107788 4794.78 299.674 0.01 0.00143114 0.00122243 564 862 -1 19 5 18 18 404 200 1.37578 0.571 -2.70755 -1.37578 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00113405 0.00101135 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.27 vpr 66.13 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 67720 5 3 11 14 2 9 10 4 4 16 clb auto 27.7 MiB 0.00 22 20 370 95 153 122 66.1 MiB 0.00 0.00 0.146298 0.145978 0 0 0.571 0.01 3.0867e-05 2.5256e-05 0.00131289 0.00106875 -1 -1 -1 -1 8 11 2 107788 107788 4794.78 299.674 0.01 0.00229577 0.00196649 564 862 -1 17 5 13 13 264 119 0.0706414 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00109453 0.000995331 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt index 61814cf74f8..1a4fcfa6b1d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.17 vpr 65.36 MiB 0.01 6528 -1 -1 1 0.02 -1 -1 29876 -1 -1 3 9 0 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66924 9 8 75 70 1 34 20 5 5 25 clb auto 26.0 MiB 0.41 123 90 695 231 450 14 65.4 MiB 0.01 0.00 2.48207 2.48207 -27.8628 -2.48207 2.48207 0.01 9.0537e-05 8.1627e-05 0.00403872 0.00373682 -1 -1 -1 -1 52 159 13 151211 75605.7 63348.9 2533.96 0.14 0.0360473 0.0303989 2316 10503 -1 119 9 62 71 2459 1186 2.40307 2.40307 -29.7272 -2.40307 0 0 82390.3 3295.61 0.00 0.01 0.01 -1 -1 0.00 0.00434551 0.00403881 13 18 19 7 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.46 vpr 65.27 MiB 0.01 6144 -1 -1 1 0.02 -1 -1 29588 -1 -1 2 11 0 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66836 11 10 108 97 1 49 23 4 4 16 clb auto 25.9 MiB 1.75 144.497 130 311 99 187 25 65.3 MiB 0.01 0.00 3.45122 3.45122 -42.5364 -3.45122 3.45122 0.01 0.000120707 0.000109599 0.00237886 0.00224793 -1 -1 -1 -1 34 209 16 50403.8 50403.8 21558.4 1347.40 0.12 0.0470495 0.0393656 1020 3049 -1 148 11 130 155 3770 2306 3.45122 3.45122 -44.6246 -3.45122 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00595518 0.00551105 15 27 29 8 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 4.04 vpr 65.17 MiB 0.02 6144 -1 -1 1 0.02 -1 -1 29992 -1 -1 7 13 0 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66736 13 12 149 129 1 68 32 6 6 36 clb auto 25.9 MiB 3.17 259.837 198 732 206 512 14 65.2 MiB 0.01 0.00 3.50789 3.50789 -53.1047 -3.50789 3.50789 0.02 0.000162226 0.000148185 0.00405536 0.00381363 -1 -1 -1 -1 38 445 20 403230 176413 85314.8 2369.86 0.24 0.0657256 0.0559277 3698 15565 -1 339 18 284 421 12893 5702 3.4668 3.4668 -57.03 -3.4668 0 0 107229. 2978.57 0.00 0.01 0.01 -1 -1 0.00 0.00967729 0.00881943 25 38 42 9 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.42 vpr 66.01 MiB 0.01 6144 -1 -1 1 0.02 -1 -1 30232 -1 -1 7 15 0 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67596 15 14 196 165 1 92 36 6 6 36 clb auto 26.3 MiB 1.52 403.804 302 744 207 512 25 66.0 MiB 0.01 0.00 3.89713 3.62628 -64.2673 -3.62628 3.62628 0.03 0.000287924 0.000234951 0.00592667 0.0055105 -1 -1 -1 -1 36 795 23 403230 176413 82124.2 2281.23 0.18 0.0594614 0.0513596 3630 14583 -1 647 22 712 1054 40040 16870 4.12851 4.12851 -83.5066 -4.12851 0 0 100559. 2793.30 0.00 0.02 0.01 -1 -1 0.00 0.0133279 0.0120671 37 51 57 11 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 4.76 vpr 65.06 MiB 0.01 6528 -1 -1 1 0.03 -1 -1 29732 -1 -1 5 17 0 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 66624 17 16 251 206 1 120 38 5 5 25 clb auto 25.6 MiB 3.86 489.194 407 2180 523 1636 21 65.1 MiB 0.02 0.00 3.91442 3.88071 -74.6211 -3.88071 3.88071 0.01 0.000251566 0.000231279 0.0113711 0.0105923 -1 -1 -1 -1 50 648 31 151211 126010 61632.8 2465.31 0.15 0.0727381 0.0632279 2268 9834 -1 512 21 605 964 28691 13093 4.81019 4.81019 -90.2864 -4.81019 0 0 77226.2 3089.05 0.00 0.03 0.01 -1 -1 0.00 0.0172179 0.0156983 45 66 75 13 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.96 vpr 66.03 MiB 0.01 6528 -1 -1 1 0.03 -1 -1 30364 -1 -1 7 19 0 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67616 19 18 308 249 1 134 44 6 6 36 clb auto 26.7 MiB 4.02 593.868 481 1661 359 1294 8 66.0 MiB 0.02 0.00 4.92231 4.8546 -99.813 -4.8546 4.8546 0.02 0.000299333 0.000274645 0.00947807 0.00888201 -1 -1 -1 -1 68 830 22 403230 176413 143382. 3982.83 0.20 0.0780388 0.0683344 4366 25715 -1 733 16 557 928 35415 13097 4.72078 4.72078 -100.987 -4.72078 0 0 176130. 4892.50 0.00 0.03 0.02 -1 -1 0.00 0.0183418 0.0169946 53 83 93 14 0 0 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.18 vpr 66.92 MiB 0.01 7552 -1 -1 1 0.02 -1 -1 33508 -1 -1 3 9 0 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 68528 9 8 75 70 1 34 20 5 5 25 clb auto 27.9 MiB 0.52 123 90 2477 1148 1302 27 66.9 MiB 0.02 0.00 2.48207 2.48207 -28.1156 -2.48207 2.48207 0.02 0.00017509 0.00015144 0.0119101 0.0103534 -1 -1 -1 -1 34 189 14 151211 75605.7 45067.1 1802.68 0.14 0.0511387 0.0425617 2028 7167 -1 146 11 105 133 3695 2011 2.64007 2.64007 -33.2822 -2.64007 0 0 54748.7 2189.95 0.00 0.01 0.01 -1 -1 0.00 0.00502557 0.00455757 13 18 19 7 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 3.06 vpr 67.09 MiB 0.01 7552 -1 -1 1 0.02 -1 -1 33980 -1 -1 2 11 0 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 68696 11 10 108 97 1 49 23 4 4 16 clb auto 27.9 MiB 2.50 144.497 127 1911 800 873 238 67.1 MiB 0.02 0.00 3.45122 3.45122 -42.5068 -3.45122 3.45122 0.01 0.000144339 0.000125024 0.0100987 0.00883193 -1 -1 -1 -1 34 239 30 50403.8 50403.8 21558.4 1347.40 0.08 0.0460273 0.038796 1020 3049 -1 152 10 140 181 4372 2642 3.68822 3.68822 -46.7576 -3.68822 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00618826 0.00564489 15 27 29 8 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 5.08 vpr 67.44 MiB 0.01 7552 -1 -1 1 0.02 -1 -1 33828 -1 -1 7 13 0 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 69056 13 12 149 129 1 68 32 6 6 36 clb auto 28.0 MiB 4.20 259.837 197 3032 1105 1866 61 67.4 MiB 0.03 0.00 3.50789 3.50789 -52.7999 -3.50789 3.50789 0.03 0.000196508 0.000170297 0.0134802 0.0117856 -1 -1 -1 -1 52 392 44 403230 176413 110337. 3064.92 0.31 0.101779 0.0850851 4014 20275 -1 276 19 253 363 12206 5278 3.49758 3.49758 -52.8425 -3.49758 0 0 143382. 3982.83 0.00 0.01 0.02 -1 -1 0.00 0.0106156 0.0094697 25 38 42 9 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.95 vpr 67.93 MiB 0.01 7552 -1 -1 1 0.02 -1 -1 33628 -1 -1 7 15 0 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 69560 15 14 196 165 1 92 36 6 6 36 clb auto 28.5 MiB 2.00 403.804 274 3753 1426 2249 78 67.9 MiB 0.04 0.00 3.89713 3.62628 -63.9965 -3.62628 3.62628 0.03 0.000241508 0.000208616 0.0181966 0.0159188 -1 -1 -1 -1 56 442 17 403230 176413 117789. 3271.93 0.34 0.108077 0.0909094 4086 21443 -1 365 18 406 563 16464 6899 3.5903 3.5903 -62.6621 -3.5903 0 0 149557. 4154.36 0.00 0.02 0.02 -1 -1 0.00 0.0131535 0.0117499 37 51 57 11 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 5.82 vpr 68.04 MiB 0.01 7552 -1 -1 1 0.02 -1 -1 33904 -1 -1 5 17 0 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 69668 17 16 251 206 1 120 38 5 5 25 clb auto 28.5 MiB 4.99 489.194 407 7661 3749 3866 46 68.0 MiB 0.08 0.00 3.91442 3.88071 -74.7949 -3.88071 3.88071 0.02 0.000295654 0.00025444 0.0402952 0.0348047 -1 -1 -1 -1 50 686 48 151211 126010 61632.8 2465.31 0.18 0.1223 0.103767 2268 9834 -1 552 25 695 1245 39419 17834 4.6289 4.6289 -93.861 -4.6289 0 0 77226.2 3089.05 0.00 0.03 0.01 -1 -1 0.00 0.0205563 0.0182316 45 66 75 13 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.24 vpr 68.47 MiB 0.01 7552 -1 -1 1 0.02 -1 -1 33768 -1 -1 7 19 0 -1 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 70112 19 18 308 249 1 134 44 6 6 36 clb auto 28.9 MiB 5.69 593.868 431 7359 3370 3953 36 68.5 MiB 0.14 0.00 4.92231 4.8546 -99.5986 -4.8546 4.8546 0.05 0.000726408 0.000636467 0.0695133 0.0609147 -1 -1 -1 -1 46 899 26 403230 176413 100559. 2793.30 0.71 0.289292 0.248411 3874 18143 -1 726 15 584 939 34653 14534 4.86806 4.86806 -109.554 -4.86806 0 0 127342. 3537.27 0.00 0.03 0.02 -1 -1 0.00 0.0184771 0.0168376 53 83 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt index 58d4e516112..d52bd9470ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.36 vpr 66.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67776 5 3 11 14 2 9 10 4 4 16 clb auto 27.5 MiB 0.00 24 21 30 9 19 2 66.2 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 3.1543e-05 1.749e-05 0.000181879 0.000137264 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0013403 0.00121192 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00104912 0.000992256 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.36 vpr 66.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67764 5 3 11 14 2 9 10 4 4 16 clb auto 27.5 MiB 0.01 24 21 30 9 19 2 66.2 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5838e-05 1.7605e-05 0.000193938 0.000153476 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00137781 0.00125449 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00106496 0.00101428 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.37 vpr 66.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 67776 5 3 11 14 2 9 10 4 4 16 clb auto 27.9 MiB 0.01 24 21 30 9 19 2 66.2 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5555e-05 1.7373e-05 0.000169231 0.000132264 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00137206 0.00123656 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00103853 0.000987893 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.36 vpr 67.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 69336 5 3 11 14 2 9 10 4 4 16 clb auto 29.2 MiB 0.01 24 20 470 157 233 80 67.7 MiB 0.00 0.00 0.713166 0.620297 -3.41517 -0.620297 0.545 0.01 3.4032e-05 2.7099e-05 0.0018333 0.0014152 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00286806 0.00236185 750 1675 -1 26 3 10 10 347 239 0.869227 0.545 -4.0122 -0.869227 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00108133 0.00100256 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.36 vpr 67.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 69336 5 3 11 14 2 9 10 4 4 16 clb auto 29.3 MiB 0.01 24 20 470 157 233 80 67.7 MiB 0.00 0.00 0.713166 0.620297 -3.41517 -0.620297 0.545 0.01 2.7147e-05 2.0763e-05 0.00147983 0.00110808 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00257385 0.00210637 750 1675 -1 26 3 10 10 347 239 0.869227 0.545 -4.0122 -0.869227 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00107764 0.000986855 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.36 vpr 67.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin 69404 5 3 11 14 2 9 10 4 4 16 clb auto 29.2 MiB 0.01 24 20 470 157 233 80 67.8 MiB 0.00 0.00 0.713166 0.620297 -3.41517 -0.620297 0.545 0.01 3.4021e-05 2.7118e-05 0.00158936 0.00120768 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00263803 0.00216378 750 1675 -1 26 3 10 10 347 239 0.869227 0.545 -4.0122 -0.869227 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00110614 0.00101242