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| 1 | +/* |
| 2 | + * Copyright (c) 2025 Microchip Technology Inc. |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +#ifndef INCLUDE_DT_BINDINGS_PIC32C_COMMON_MCHP_PINCTRL_PINMUX_PIC32C_H_ |
| 8 | +#define INCLUDE_DT_BINDINGS_PIC32C_COMMON_MCHP_PINCTRL_PINMUX_PIC32C_H_ |
| 9 | + |
| 10 | +/** |
| 11 | + * @name Microchip PIC32C port. |
| 12 | + * Derived from SAM D/E5x PINCTRL |
| 13 | + */ |
| 14 | + |
| 15 | +/** PORT */ |
| 16 | +#define MCHP_PINMUX_PORT_a 0U |
| 17 | +#define MCHP_PINMUX_PORT_b 1U |
| 18 | +#define MCHP_PINMUX_PORT_c 2U |
| 19 | +#define MCHP_PINMUX_PORT_d 3U |
| 20 | +#define MCHP_PINMUX_PORT_e 4U |
| 21 | +#define MCHP_PINMUX_PORT_f 5U |
| 22 | +#define MCHP_PINMUX_PORT_g 6U |
| 23 | +#define MCHP_PINMUX_PORT_h 7U |
| 24 | +#define MCHP_PINMUX_PORT_i 8U |
| 25 | +#define MCHP_PINMUX_PORT_j 9U |
| 26 | +#define MCHP_PINMUX_PORT_k 10U |
| 27 | +#define MCHP_PINMUX_PORT_l 11U |
| 28 | +#define MCHP_PINMUX_PORT_m 12U |
| 29 | +#define MCHP_PINMUX_PORT_n 13U |
| 30 | +#define MCHP_PINMUX_PORT_o 14U |
| 31 | +#define MCHP_PINMUX_PORT_p 15U |
| 32 | + |
| 33 | +/** GPIO */ |
| 34 | +#define MCHP_PINMUX_PERIPH_gpio 0U |
| 35 | +/** Peripherals */ |
| 36 | +#define MCHP_PINMUX_PERIPH_a 0U |
| 37 | +#define MCHP_PINMUX_PERIPH_b 1U |
| 38 | +#define MCHP_PINMUX_PERIPH_c 2U |
| 39 | +#define MCHP_PINMUX_PERIPH_d 3U |
| 40 | +#define MCHP_PINMUX_PERIPH_e 4U |
| 41 | +#define MCHP_PINMUX_PERIPH_f 5U |
| 42 | +#define MCHP_PINMUX_PERIPH_g 6U |
| 43 | +#define MCHP_PINMUX_PERIPH_h 7U |
| 44 | +#define MCHP_PINMUX_PERIPH_i 8U |
| 45 | +#define MCHP_PINMUX_PERIPH_j 9U |
| 46 | +#define MCHP_PINMUX_PERIPH_k 10U |
| 47 | +#define MCHP_PINMUX_PERIPH_l 11U |
| 48 | +#define MCHP_PINMUX_PERIPH_m 12U |
| 49 | +#define MCHP_PINMUX_PERIPH_n 13U |
| 50 | +/** Extra */ |
| 51 | +#define MCHP_PINMUX_PERIPH_x 0U |
| 52 | +/** System */ |
| 53 | +#define MCHP_PINMUX_PERIPH_s 0U |
| 54 | +/** LPM */ |
| 55 | +#define MCHP_PINMUX_PERIPH_lpm 0U |
| 56 | +/** Wake-up pin sources */ |
| 57 | +#define MCHP_PINMUX_PERIPH_wkup0 0U |
| 58 | +#define MCHP_PINMUX_PERIPH_wkup1 1U |
| 59 | +#define MCHP_PINMUX_PERIPH_wkup2 2U |
| 60 | +#define MCHP_PINMUX_PERIPH_wkup3 3U |
| 61 | +#define MCHP_PINMUX_PERIPH_wkup4 4U |
| 62 | +#define MCHP_PINMUX_PERIPH_wkup5 5U |
| 63 | +#define MCHP_PINMUX_PERIPH_wkup6 6U |
| 64 | +#define MCHP_PINMUX_PERIPH_wkup7 7U |
| 65 | +#define MCHP_PINMUX_PERIPH_wkup8 8U |
| 66 | +#define MCHP_PINMUX_PERIPH_wkup9 9U |
| 67 | +#define MCHP_PINMUX_PERIPH_wkup10 10U |
| 68 | +#define MCHP_PINMUX_PERIPH_wkup11 11U |
| 69 | +#define MCHP_PINMUX_PERIPH_wkup12 12U |
| 70 | +#define MCHP_PINMUX_PERIPH_wkup13 13U |
| 71 | +#define MCHP_PINMUX_PERIPH_wkup14 14U |
| 72 | +#define MCHP_PINMUX_PERIPH_wkup15 15U |
| 73 | + |
| 74 | +/** Selects pin to be used as GPIO */ |
| 75 | +#define MCHP_PINMUX_FUNC_gpio 0U |
| 76 | +/** Selects pin to be used as by some peripheral */ |
| 77 | +#define MCHP_PINMUX_FUNC_periph 1U |
| 78 | +/** Selects pin to be used as extra function */ |
| 79 | +#define MCHP_PINMUX_FUNC_extra 2U |
| 80 | +/** Selects pin to be used as system function */ |
| 81 | +#define MCHP_PINMUX_FUNC_system 3U |
| 82 | +/** Selects and configure pin to be used in Low Power Mode */ |
| 83 | +#define MCHP_PINMUX_FUNC_lpm 4U |
| 84 | +/** Selects and configure wake-up pin sources Low Power Mode */ |
| 85 | +#define MCHP_PINMUX_FUNC_wakeup 5U |
| 86 | + |
| 87 | +/** Pinmux bit field position. */ |
| 88 | +#define MCHP_PINCTRL_PINMUX_POS (16U) |
| 89 | +/** Pinmux bit field mask. */ |
| 90 | +#define MCHP_PINCTRL_PINMUX_MASK (0xFFFF) |
| 91 | + |
| 92 | +/** Port field mask. */ |
| 93 | +#define MCHP_PINMUX_PORT_MSK (0xFU) |
| 94 | +/** Port field position. */ |
| 95 | +#define MCHP_PINMUX_PORT_POS (0U) |
| 96 | +/** Pin field mask. */ |
| 97 | +#define MCHP_PINMUX_PIN_MSK (0x1FU) |
| 98 | +/** Pin field position. */ |
| 99 | +#define MCHP_PINMUX_PIN_POS (MCHP_PINMUX_PORT_POS + 4U) |
| 100 | +/** Function field mask. */ |
| 101 | +#define MCHP_PINMUX_FUNC_MSK (0x7U) |
| 102 | +/** Function field position. */ |
| 103 | +#define MCHP_PINMUX_FUNC_POS (MCHP_PINMUX_PIN_POS + 5U) |
| 104 | +/** Peripheral field mask. */ |
| 105 | +#define MCHP_PINMUX_PERIPH_MSK (0xFU) |
| 106 | +/** Peripheral field position. */ |
| 107 | +#define MCHP_PINMUX_PERIPH_POS (MCHP_PINMUX_FUNC_POS + 3U) |
| 108 | + |
| 109 | +/* |
| 110 | + * MCHP pinmux bit field. |
| 111 | + * |
| 112 | + * Fields: |
| 113 | + * |
| 114 | + * - 0..3: port |
| 115 | + * - 4..8: pin_num |
| 116 | + * - 9..11: func |
| 117 | + * - 12..15: pin_mux |
| 118 | + * |
| 119 | + * port Port ('A'..'P') |
| 120 | + * pin Pin (0..31) |
| 121 | + * func Function (GPIO, Peripheral, System, Extra, LPM - 0..4) |
| 122 | + * pin_mux Peripheral based on the Function selected (0..15) |
| 123 | + */ |
| 124 | +#define MCHP_PINMUX(port, pin_num, pin_mux, func) \ |
| 125 | + ((((MCHP_PINMUX_PORT_##port) & MCHP_PINMUX_PORT_MSK) \ |
| 126 | + << MCHP_PINMUX_PORT_POS) | \ |
| 127 | + (((pin_num) & MCHP_PINMUX_PIN_MSK) << MCHP_PINMUX_PIN_POS) | \ |
| 128 | + (((MCHP_PINMUX_FUNC_##func) & MCHP_PINMUX_FUNC_MSK) \ |
| 129 | + << MCHP_PINMUX_FUNC_POS) | \ |
| 130 | + (((MCHP_PINMUX_PERIPH_##pin_mux) & MCHP_PINMUX_PERIPH_MSK) \ |
| 131 | + << MCHP_PINMUX_PERIPH_POS)) |
| 132 | + |
| 133 | +/* |
| 134 | + * Obtain Pinmux value from pinctrl_soc_pin_t configuration. |
| 135 | + * |
| 136 | + * pincfg pinctrl_soc_pin_t bit field value. |
| 137 | + */ |
| 138 | +#define MCHP_PINMUX_PIN_GET(pincfg) \ |
| 139 | + ((pincfg >> MCHP_PINMUX_PIN_POS) & MCHP_PINMUX_PIN_MSK) |
| 140 | +#define MCHP_PINMUX_PORT_GET(pincfg) \ |
| 141 | + ((pincfg >> MCHP_PINMUX_PORT_POS) & MCHP_PINMUX_PORT_MSK) |
| 142 | +#define MCHP_PINMUX_FUNC_GET(pincfg) \ |
| 143 | + ((pincfg >> MCHP_PINMUX_FUNC_POS) & MCHP_PINMUX_FUNC_MSK) |
| 144 | +#define MCHP_PINMUX_PERIPH_GET(pincfg) \ |
| 145 | + ((pincfg >> MCHP_PINMUX_PERIPH_POS) & MCHP_PINMUX_PERIPH_MSK) |
| 146 | + |
| 147 | +#endif /* INCLUDE_DT_BINDINGS_PIC32C_PIC32CM_GC_SG_COMMON_MCHP_PINCTRL_PINMUX_PIC32C_H_ */ |
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