diff --git a/README.md b/README.md
index afe614dd..24bdda97 100644
--- a/README.md
+++ b/README.md
@@ -16,9 +16,14 @@ The HAL directory structure detailed below.
 │
 ├── include
 │   └── dt-bindings
+|       ├── pic32c
+|       |  └── pic32cm_gc_sg - dt-binding header files for PIC32CM GC family devices
 │       ├── sam
-│       │   └── sam_d5x_e5x — dt-binding header files for the SAM_D5X_E5X family devices
-│
+|       |   └── sam_d5x_e5x — dt-binding header files for the SAM_D5X_E5X family devices
+|       ├── pic32c
+|       |  ├── pic32cm_gc_sg - dt-binding header files for PIC32CM GC family devices
+│       └── pinctrl
+│           └── PIC32CX PINCTRL C header files
 ├── mec
 │   ├── Legacy MEC150x/2x C chip and peripheral header files
 │
@@ -32,17 +37,16 @@ The HAL directory structure detailed below.
 ├── mpfs
 │   ├── PolarFire board and HAL files
 │
-├── packs
-│   ├── CMakeLists.txt
-│   ├── pic32c
-│   │   ├── CMakeLists.txt
-│   │   ├── pic32cm_jh — DFP header files for PIC32CM JH family devices
-│   │   ├── pic32cx_sg — DFP header files for PIC32CX SG family devices
-│   │   ├── pic32cz_ca — DFP header files for PIC32CZ CA family devices
-│   │
-│   └── sam
-│       ├── CMakeLists.txt
-│       ├── sam_d5x_e5x — DFP header files for SAM_D5X_E5X family devices
+├── pic32c
+│   ├── CMakeLists.txt
+│   ├── pic32cm_gc_sg — DFP header files for PIC32CM_GC and PIC32CM_SG family devices
+|   ├── pic32cm_jh — DFP header files for PIC32CM JH family devices
+│   ├── pic32cz_sg — DFP header files for PIC32CX SG family devices
+│   ├── pic32cz_ca — DFP header files for PIC32CZ CA family devices
+│
+├── sam
+│   ├── CMakeLists.txt
+│   ├── sam_d5x_e5x — DFP header files for SAM_D5X_E5X family devices
 │
 ├── README.md
 │
diff --git a/include/dt-bindings/pic32c/pic32cm_gc_sg/common/mchp_pinctrl_pinmux_pic32c.h b/include/dt-bindings/pic32c/pic32cm_gc_sg/common/mchp_pinctrl_pinmux_pic32c.h
new file mode 100644
index 00000000..aff5e519
--- /dev/null
+++ b/include/dt-bindings/pic32c/pic32cm_gc_sg/common/mchp_pinctrl_pinmux_pic32c.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef INCLUDE_DT_BINDINGS_PIC32C_COMMON_MCHP_PINCTRL_PINMUX_PIC32C_H_
+#define INCLUDE_DT_BINDINGS_PIC32C_COMMON_MCHP_PINCTRL_PINMUX_PIC32C_H_
+
+/**
+ * @name Microchip PIC32C port. 
+ * Derived from SAM D/E5x PINCTRL
+ */
+
+/** PORT */
+#define MCHP_PINMUX_PORT_a 0U
+#define MCHP_PINMUX_PORT_b 1U
+#define MCHP_PINMUX_PORT_c 2U
+#define MCHP_PINMUX_PORT_d 3U
+#define MCHP_PINMUX_PORT_e 4U
+#define MCHP_PINMUX_PORT_f 5U
+#define MCHP_PINMUX_PORT_g 6U
+#define MCHP_PINMUX_PORT_h 7U
+#define MCHP_PINMUX_PORT_i 8U
+#define MCHP_PINMUX_PORT_j 9U
+#define MCHP_PINMUX_PORT_k 10U
+#define MCHP_PINMUX_PORT_l 11U
+#define MCHP_PINMUX_PORT_m 12U
+#define MCHP_PINMUX_PORT_n 13U
+#define MCHP_PINMUX_PORT_o 14U
+#define MCHP_PINMUX_PORT_p 15U
+
+/** GPIO */
+#define MCHP_PINMUX_PERIPH_gpio 0U
+/** Peripherals */
+#define MCHP_PINMUX_PERIPH_a 0U
+#define MCHP_PINMUX_PERIPH_b 1U
+#define MCHP_PINMUX_PERIPH_c 2U
+#define MCHP_PINMUX_PERIPH_d 3U
+#define MCHP_PINMUX_PERIPH_e 4U
+#define MCHP_PINMUX_PERIPH_f 5U
+#define MCHP_PINMUX_PERIPH_g 6U
+#define MCHP_PINMUX_PERIPH_h 7U
+#define MCHP_PINMUX_PERIPH_i 8U
+#define MCHP_PINMUX_PERIPH_j 9U
+#define MCHP_PINMUX_PERIPH_k 10U
+#define MCHP_PINMUX_PERIPH_l 11U
+#define MCHP_PINMUX_PERIPH_m 12U
+#define MCHP_PINMUX_PERIPH_n 13U
+/** Extra */
+#define MCHP_PINMUX_PERIPH_x 0U
+/** System */
+#define MCHP_PINMUX_PERIPH_s 0U
+/** LPM */
+#define MCHP_PINMUX_PERIPH_lpm 0U
+/** Wake-up pin sources */
+#define MCHP_PINMUX_PERIPH_wkup0 0U
+#define MCHP_PINMUX_PERIPH_wkup1 1U
+#define MCHP_PINMUX_PERIPH_wkup2 2U
+#define MCHP_PINMUX_PERIPH_wkup3 3U
+#define MCHP_PINMUX_PERIPH_wkup4 4U
+#define MCHP_PINMUX_PERIPH_wkup5 5U
+#define MCHP_PINMUX_PERIPH_wkup6 6U
+#define MCHP_PINMUX_PERIPH_wkup7 7U
+#define MCHP_PINMUX_PERIPH_wkup8 8U
+#define MCHP_PINMUX_PERIPH_wkup9 9U
+#define MCHP_PINMUX_PERIPH_wkup10 10U
+#define MCHP_PINMUX_PERIPH_wkup11 11U
+#define MCHP_PINMUX_PERIPH_wkup12 12U
+#define MCHP_PINMUX_PERIPH_wkup13 13U
+#define MCHP_PINMUX_PERIPH_wkup14 14U
+#define MCHP_PINMUX_PERIPH_wkup15 15U
+
+/** Selects pin to be used as GPIO */
+#define MCHP_PINMUX_FUNC_gpio 0U
+/** Selects pin to be used as by some peripheral */
+#define MCHP_PINMUX_FUNC_periph 1U
+/** Selects pin to be used as extra function */
+#define MCHP_PINMUX_FUNC_extra 2U
+/** Selects pin to be used as system function */
+#define MCHP_PINMUX_FUNC_system 3U
+/** Selects and configure pin to be used in Low Power Mode */
+#define MCHP_PINMUX_FUNC_lpm 4U
+/** Selects and configure wake-up pin sources Low Power Mode */
+#define MCHP_PINMUX_FUNC_wakeup 5U
+
+/** Pinmux bit field position. */
+#define MCHP_PINCTRL_PINMUX_POS (16U)
+/** Pinmux bit field mask. */
+#define MCHP_PINCTRL_PINMUX_MASK (0xFFFF)
+
+/** Port field mask. */
+#define MCHP_PINMUX_PORT_MSK (0xFU)
+/** Port field position. */
+#define MCHP_PINMUX_PORT_POS (0U)
+/** Pin field mask. */
+#define MCHP_PINMUX_PIN_MSK (0x1FU)
+/** Pin field position. */
+#define MCHP_PINMUX_PIN_POS (MCHP_PINMUX_PORT_POS + 4U)
+/** Function field mask. */
+#define MCHP_PINMUX_FUNC_MSK (0x7U)
+/** Function field position. */
+#define MCHP_PINMUX_FUNC_POS (MCHP_PINMUX_PIN_POS + 5U)
+/** Peripheral field mask. */
+#define MCHP_PINMUX_PERIPH_MSK (0xFU)
+/** Peripheral field position. */
+#define MCHP_PINMUX_PERIPH_POS (MCHP_PINMUX_FUNC_POS + 3U)
+
+/*
+ * MCHP pinmux bit field.
+ *
+ * Fields:
+ *
+ * -   0..3: port
+ * -   4..8: pin_num
+ * -  9..11: func
+ * - 12..15: pin_mux
+ *
+ * port    Port ('A'..'P')
+ * pin     Pin  (0..31)
+ * func    Function (GPIO, Peripheral, System, Extra, LPM - 0..4)
+ * pin_mux Peripheral based on the Function selected (0..15)
+ */
+#define MCHP_PINMUX(port, pin_num, pin_mux, func)                              \
+  ((((MCHP_PINMUX_PORT_##port) & MCHP_PINMUX_PORT_MSK)                         \
+    << MCHP_PINMUX_PORT_POS) |                                                 \
+   (((pin_num) & MCHP_PINMUX_PIN_MSK) << MCHP_PINMUX_PIN_POS) |                \
+   (((MCHP_PINMUX_FUNC_##func) & MCHP_PINMUX_FUNC_MSK)                         \
+    << MCHP_PINMUX_FUNC_POS) |                                                 \
+   (((MCHP_PINMUX_PERIPH_##pin_mux) & MCHP_PINMUX_PERIPH_MSK)                  \
+    << MCHP_PINMUX_PERIPH_POS))
+
+/*
+ * Obtain Pinmux value from pinctrl_soc_pin_t configuration.
+ *
+ * pincfg pinctrl_soc_pin_t bit field value.
+ */
+#define MCHP_PINMUX_PIN_GET(pincfg)                                            \
+  ((pincfg >> MCHP_PINMUX_PIN_POS) & MCHP_PINMUX_PIN_MSK)
+#define MCHP_PINMUX_PORT_GET(pincfg)                                           \
+  ((pincfg >> MCHP_PINMUX_PORT_POS) & MCHP_PINMUX_PORT_MSK)
+#define MCHP_PINMUX_FUNC_GET(pincfg)                                           \
+  ((pincfg >> MCHP_PINMUX_FUNC_POS) & MCHP_PINMUX_FUNC_MSK)
+#define MCHP_PINMUX_PERIPH_GET(pincfg)                                         \
+  ((pincfg >> MCHP_PINMUX_PERIPH_POS) & MCHP_PINMUX_PERIPH_MSK)
+
+#endif /* INCLUDE_DT_BINDINGS_PIC32C_PIC32CM_GC_SG_COMMON_MCHP_PINCTRL_PINMUX_PIC32C_H_ */
diff --git a/include/dt-bindings/pic32c/pic32cm_gc_sg/pic32cm_gc00/pic32cm5112gc00048-pinctrl.h b/include/dt-bindings/pic32c/pic32cm_gc_sg/pic32cm_gc00/pic32cm5112gc00048-pinctrl.h
new file mode 100644
index 00000000..5e26e517
--- /dev/null
+++ b/include/dt-bindings/pic32c/pic32cm_gc_sg/pic32cm_gc00/pic32cm5112gc00048-pinctrl.h
@@ -0,0 +1,785 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Autogenerated file
+ */
+
+#ifndef MICROCHIP_PIC32CM5112GC00048_PINCTRL_H_
+#define MICROCHIP_PIC32CM5112GC00048_PINCTRL_H_
+
+#include <dt-bindings/pic32c/common/mchp_pinctrl_pinmux_pic32c.h>
+
+/* pa0_gpio */
+#define PA0_GPIO MCHP_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 MCHP_PINMUX(a, 0, a, periph)
+
+/* pa0adc_test_pad_adc_res_test3 */
+#define PA0ADC_TEST_PAD_ADC_RES_TEST3 MCHP_PINMUX(a, 0, adc_test_pad, periph)
+
+/* pa0d_sercom3_pad1 */
+#define PA0D_SERCOM3_PAD1 MCHP_PINMUX(a, 0, d, periph)
+
+/* pa0f_tcc5_wo1 */
+#define PA0F_TCC5_WO1 MCHP_PINMUX(a, 0, f, periph)
+
+/* pa0h_can1_rx */
+#define PA0H_CAN1_RX MCHP_PINMUX(a, 0, h, periph)
+
+/* pa0i_ccl0_in6 */
+#define PA0I_CCL0_IN6 MCHP_PINMUX(a, 0, i, periph)
+
+/* pa0p_ptc_ptcxy4 */
+#define PA0P_PTC_PTCXY4 MCHP_PINMUX(a, 0, p, periph)
+
+/* pa0p_ptc_drv4 */
+#define PA0P_PTC_DRV4 MCHP_PINMUX(a, 0, p, periph)
+
+/* pa0pdmi_test_pdm_pdmi3 */
+#define PA0PDMI_TEST_PDM_PDMI3 MCHP_PINMUX(a, 0, pdmi_test, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO MCHP_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 MCHP_PINMUX(a, 1, a, periph)
+
+/* pa1adc_test_pad_adc_res_test4 */
+#define PA1ADC_TEST_PAD_ADC_RES_TEST4 MCHP_PINMUX(a, 1, adc_test_pad, periph)
+
+/* pa1b_ac_cmp0 */
+#define PA1B_AC_CMP0 MCHP_PINMUX(a, 1, b, periph)
+
+/* pa1d_sercom3_pad2 */
+#define PA1D_SERCOM3_PAD2 MCHP_PINMUX(a, 1, d, periph)
+
+/* pa1f_tcc6_wo0 */
+#define PA1F_TCC6_WO0 MCHP_PINMUX(a, 1, f, periph)
+
+/* pa1h_can1_tx */
+#define PA1H_CAN1_TX MCHP_PINMUX(a, 1, h, periph)
+
+/* pa1i_ccl0_in7 */
+#define PA1I_CCL0_IN7 MCHP_PINMUX(a, 1, i, periph)
+
+/* pa1p_ptc_ptcxy5 */
+#define PA1P_PTC_PTCXY5 MCHP_PINMUX(a, 1, p, periph)
+
+/* pa1p_ptc_drv5 */
+#define PA1P_PTC_DRV5 MCHP_PINMUX(a, 1, p, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO MCHP_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 MCHP_PINMUX(a, 2, a, periph)
+
+/* pa2adc_test_pad_adc_res_test5 */
+#define PA2ADC_TEST_PAD_ADC_RES_TEST5 MCHP_PINMUX(a, 2, adc_test_pad, periph)
+
+/* pa2b_ac_cmp1 */
+#define PA2B_AC_CMP1 MCHP_PINMUX(a, 2, b, periph)
+
+/* pa2d_sercom3_pad3 */
+#define PA2D_SERCOM3_PAD3 MCHP_PINMUX(a, 2, d, periph)
+
+/* pa2f_tcc6_wo1 */
+#define PA2F_TCC6_WO1 MCHP_PINMUX(a, 2, f, periph)
+
+/* pa2i_ccl0_out2 */
+#define PA2I_CCL0_OUT2 MCHP_PINMUX(a, 2, i, periph)
+
+/* pa2p_ptc_ptcxy6 */
+#define PA2P_PTC_PTCXY6 MCHP_PINMUX(a, 2, p, periph)
+
+/* pa2p_ptc_drv6 */
+#define PA2P_PTC_DRV6 MCHP_PINMUX(a, 2, p, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO MCHP_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 MCHP_PINMUX(a, 3, a, periph)
+
+/* pa3adc_test_pad_adc_res_test6 */
+#define PA3ADC_TEST_PAD_ADC_RES_TEST6 MCHP_PINMUX(a, 3, adc_test_pad, periph)
+
+/* pa3b_adc_adc0_ain0 */
+#define PA3B_ADC_ADC0_AIN0 MCHP_PINMUX(a, 3, b, periph)
+
+/* pa3d_sercom4_pad0 */
+#define PA3D_SERCOM4_PAD0 MCHP_PINMUX(a, 3, d, periph)
+
+/* pa3p_ptc_ptcxy7 */
+#define PA3P_PTC_PTCXY7 MCHP_PINMUX(a, 3, p, periph)
+
+/* pa3p_ptc_drv7 */
+#define PA3P_PTC_DRV7 MCHP_PINMUX(a, 3, p, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO MCHP_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 MCHP_PINMUX(a, 4, a, periph)
+
+/* pa4adc_test_pad_adc_res_test7 */
+#define PA4ADC_TEST_PAD_ADC_RES_TEST7 MCHP_PINMUX(a, 4, adc_test_pad, periph)
+
+/* pa4b_adc_adc0_ain1 */
+#define PA4B_ADC_ADC0_AIN1 MCHP_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc_adc0_ann0 */
+#define PA4B_ADC_ADC0_ANN0 MCHP_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom4_pad1 */
+#define PA4D_SERCOM4_PAD1 MCHP_PINMUX(a, 4, d, periph)
+
+/* pa4p_ptc_ptcxy8 */
+#define PA4P_PTC_PTCXY8 MCHP_PINMUX(a, 4, p, periph)
+
+/* pa4p_ptc_drv8 */
+#define PA4P_PTC_DRV8 MCHP_PINMUX(a, 4, p, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO MCHP_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 MCHP_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc_adc0_ain2 */
+#define PA5B_ADC_ADC0_AIN2 MCHP_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom4_pad2 */
+#define PA5D_SERCOM4_PAD2 MCHP_PINMUX(a, 5, d, periph)
+
+/* pa5i_ccl1_out2 */
+#define PA5I_CCL1_OUT2 MCHP_PINMUX(a, 5, i, periph)
+
+/* pa5p_ptc_ptcxy9 */
+#define PA5P_PTC_PTCXY9 MCHP_PINMUX(a, 5, p, periph)
+
+/* pa5p_ptc_drv9 */
+#define PA5P_PTC_DRV9 MCHP_PINMUX(a, 5, p, periph)
+
+/* pa5valio_testval_valio3 */
+#define PA5VALIO_TESTVAL_VALIO3 MCHP_PINMUX(a, 5, valio, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO MCHP_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 MCHP_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc_adc0_ain3 */
+#define PA6B_ADC_ADC0_AIN3 MCHP_PINMUX(a, 6, b, periph)
+
+/* pa6b_adc_adc0_ann2 */
+#define PA6B_ADC_ADC0_ANN2 MCHP_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom4_pad3 */
+#define PA6D_SERCOM4_PAD3 MCHP_PINMUX(a, 6, d, periph)
+
+/* pa6i_ccl1_in7 */
+#define PA6I_CCL1_IN7 MCHP_PINMUX(a, 6, i, periph)
+
+/* pa6p_ptc_ptcxy10 */
+#define PA6P_PTC_PTCXY10 MCHP_PINMUX(a, 6, p, periph)
+
+/* pa6p_ptc_drv10 */
+#define PA6P_PTC_DRV10 MCHP_PINMUX(a, 6, p, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO MCHP_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 MCHP_PINMUX(a, 7, a, periph)
+
+/* pa7b_ac_ain0 */
+#define PA7B_AC_AIN0 MCHP_PINMUX(a, 7, b, periph)
+
+/* pa7b_adc_adc0_ain4 */
+#define PA7B_ADC_ADC0_AIN4 MCHP_PINMUX(a, 7, b, periph)
+
+/* pa7p_ptc_ptcxy11 */
+#define PA7P_PTC_PTCXY11 MCHP_PINMUX(a, 7, p, periph)
+
+/* pa7p_ptc_drv11 */
+#define PA7P_PTC_DRV11 MCHP_PINMUX(a, 7, p, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO MCHP_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_extint8 */
+#define PA8A_EIC_EXTINT8 MCHP_PINMUX(a, 8, a, periph)
+
+/* pa8b_ac_ain1 */
+#define PA8B_AC_AIN1 MCHP_PINMUX(a, 8, b, periph)
+
+/* pa8b_adc_adc0_ain5 */
+#define PA8B_ADC_ADC0_AIN5 MCHP_PINMUX(a, 8, b, periph)
+
+/* pa8b_adc_adc0_ann4 */
+#define PA8B_ADC_ADC0_ANN4 MCHP_PINMUX(a, 8, b, periph)
+
+/* pa8p_ptc_ptcxy12 */
+#define PA8P_PTC_PTCXY12 MCHP_PINMUX(a, 8, p, periph)
+
+/* pa8p_ptc_drv12 */
+#define PA8P_PTC_DRV12 MCHP_PINMUX(a, 8, p, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO MCHP_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 MCHP_PINMUX(a, 9, a, periph)
+
+/* pa9b_adc_adc0_ain6 */
+#define PA9B_ADC_ADC0_AIN6 MCHP_PINMUX(a, 9, b, periph)
+
+/* pa9i_ccl1_in6 */
+#define PA9I_CCL1_IN6 MCHP_PINMUX(a, 9, i, periph)
+
+/* pa9p_ptc_ptcxy13 */
+#define PA9P_PTC_PTCXY13 MCHP_PINMUX(a, 9, p, periph)
+
+/* pa9p_ptc_drv13 */
+#define PA9P_PTC_DRV13 MCHP_PINMUX(a, 9, p, periph)
+
+/* pa9volt_ref_adc_vrefh */
+#define PA9VOLT_REF_ADC_VREFH MCHP_PINMUX(a, 9, volt_ref, periph)
+
+/* pb0_gpio */
+#define PB0_GPIO MCHP_PINMUX(b, 0, gpio, gpio)
+
+/* pb0a_eic_extint0 */
+#define PB0A_EIC_EXTINT0 MCHP_PINMUX(b, 0, a, periph)
+
+/* pb0b_ac_ain2 */
+#define PB0B_AC_AIN2 MCHP_PINMUX(b, 0, b, periph)
+
+/* pb0b_adc_adc0_ain7 */
+#define PB0B_ADC_ADC0_AIN7 MCHP_PINMUX(b, 0, b, periph)
+
+/* pb0i_ccl1_out3 */
+#define PB0I_CCL1_OUT3 MCHP_PINMUX(b, 0, i, periph)
+
+/* pb0p_ptc_ptcxy14 */
+#define PB0P_PTC_PTCXY14 MCHP_PINMUX(b, 0, p, periph)
+
+/* pb0p_ptc_drv14 */
+#define PB0P_PTC_DRV14 MCHP_PINMUX(b, 0, p, periph)
+
+/* pb1_gpio */
+#define PB1_GPIO MCHP_PINMUX(b, 1, gpio, gpio)
+
+/* pb1a_eic_extint1 */
+#define PB1A_EIC_EXTINT1 MCHP_PINMUX(b, 1, a, periph)
+
+/* pb2_gpio */
+#define PB2_GPIO MCHP_PINMUX(b, 2, gpio, gpio)
+
+/* pb2a_eic_extint2 */
+#define PB2A_EIC_EXTINT2 MCHP_PINMUX(b, 2, a, periph)
+
+/* pb3_gpio */
+#define PB3_GPIO MCHP_PINMUX(b, 3, gpio, gpio)
+
+/* pb3a_eic_extint3 */
+#define PB3A_EIC_EXTINT3 MCHP_PINMUX(b, 3, a, periph)
+
+/* pb3adc_test_pad_adc_res_test8 */
+#define PB3ADC_TEST_PAD_ADC_RES_TEST8 MCHP_PINMUX(b, 3, adc_test_pad, periph)
+
+/* pb3b_ac_ain3 */
+#define PB3B_AC_AIN3 MCHP_PINMUX(b, 3, b, periph)
+
+/* pb3b_adc_adc0_ain8 */
+#define PB3B_ADC_ADC0_AIN8 MCHP_PINMUX(b, 3, b, periph)
+
+/* pb3d_sercom5_pad0 */
+#define PB3D_SERCOM5_PAD0 MCHP_PINMUX(b, 3, d, periph)
+
+/* pb3i_ccl1_in10 */
+#define PB3I_CCL1_IN10 MCHP_PINMUX(b, 3, i, periph)
+
+/* pb3p_ptc_ptcxy15 */
+#define PB3P_PTC_PTCXY15 MCHP_PINMUX(b, 3, p, periph)
+
+/* pb3p_ptc_drv15 */
+#define PB3P_PTC_DRV15 MCHP_PINMUX(b, 3, p, periph)
+
+/* pb3pdmo_lv_test_pdm_pdmo0 */
+#define PB3PDMO_LV_TEST_PDM_PDMO0 MCHP_PINMUX(b, 3, pdmo_lv_test, periph)
+
+/* pb3pdmo_mv_test_pdm_pdmo0_mv */
+#define PB3PDMO_MV_TEST_PDM_PDMO0_MV MCHP_PINMUX(b, 3, pdmo_mv_test, periph)
+
+/* pb4_gpio */
+#define PB4_GPIO MCHP_PINMUX(b, 4, gpio, gpio)
+
+/* pb4a_eic_extint4 */
+#define PB4A_EIC_EXTINT4 MCHP_PINMUX(b, 4, a, periph)
+
+/* pb4adc_test_pad_adc_res_test9 */
+#define PB4ADC_TEST_PAD_ADC_RES_TEST9 MCHP_PINMUX(b, 4, adc_test_pad, periph)
+
+/* pb4b_adc_adc0_ain9 */
+#define PB4B_ADC_ADC0_AIN9 MCHP_PINMUX(b, 4, b, periph)
+
+/* pb4d_sercom5_pad1 */
+#define PB4D_SERCOM5_PAD1 MCHP_PINMUX(b, 4, d, periph)
+
+/* pb4i_ccl1_in9 */
+#define PB4I_CCL1_IN9 MCHP_PINMUX(b, 4, i, periph)
+
+/* pb4p_ptc_ptcxy16 */
+#define PB4P_PTC_PTCXY16 MCHP_PINMUX(b, 4, p, periph)
+
+/* pb4p_ptc_drv16 */
+#define PB4P_PTC_DRV16 MCHP_PINMUX(b, 4, p, periph)
+
+/* pb4pdmo_lv_test_pdm_pdmo1 */
+#define PB4PDMO_LV_TEST_PDM_PDMO1 MCHP_PINMUX(b, 4, pdmo_lv_test, periph)
+
+/* pb4pdmo_mv_test_pdm_pdmo1_mv */
+#define PB4PDMO_MV_TEST_PDM_PDMO1_MV MCHP_PINMUX(b, 4, pdmo_mv_test, periph)
+
+/* pb5_gpio */
+#define PB5_GPIO MCHP_PINMUX(b, 5, gpio, gpio)
+
+/* pb5a_eic_extint5 */
+#define PB5A_EIC_EXTINT5 MCHP_PINMUX(b, 5, a, periph)
+
+/* pb5adc_test_pad_adc_res_test10 */
+#define PB5ADC_TEST_PAD_ADC_RES_TEST10 MCHP_PINMUX(b, 5, adc_test_pad, periph)
+
+/* pb5b_adc_adc0_ain10 */
+#define PB5B_ADC_ADC0_AIN10 MCHP_PINMUX(b, 5, b, periph)
+
+/* pb5d_sercom5_pad2 */
+#define PB5D_SERCOM5_PAD2 MCHP_PINMUX(b, 5, d, periph)
+
+/* pb5i_ccl0_in9 */
+#define PB5I_CCL0_IN9 MCHP_PINMUX(b, 5, i, periph)
+
+/* pb5p_ptc_ptcxy17 */
+#define PB5P_PTC_PTCXY17 MCHP_PINMUX(b, 5, p, periph)
+
+/* pb5p_ptc_drv17 */
+#define PB5P_PTC_DRV17 MCHP_PINMUX(b, 5, p, periph)
+
+/* pb5pdmo_lv_test_pdm_pdmo2 */
+#define PB5PDMO_LV_TEST_PDM_PDMO2 MCHP_PINMUX(b, 5, pdmo_lv_test, periph)
+
+/* pb5pdmo_mv_test_pdm_pdmo2_mv */
+#define PB5PDMO_MV_TEST_PDM_PDMO2_MV MCHP_PINMUX(b, 5, pdmo_mv_test, periph)
+
+/* pb6_gpio */
+#define PB6_GPIO MCHP_PINMUX(b, 6, gpio, gpio)
+
+/* pb6a_eic_extint6 */
+#define PB6A_EIC_EXTINT6 MCHP_PINMUX(b, 6, a, periph)
+
+/* pb6adc_test_pad_adc_res_test11 */
+#define PB6ADC_TEST_PAD_ADC_RES_TEST11 MCHP_PINMUX(b, 6, adc_test_pad, periph)
+
+/* pb6b_adc_adc0_ain11 */
+#define PB6B_ADC_ADC0_AIN11 MCHP_PINMUX(b, 6, b, periph)
+
+/* pb6d_sercom5_pad3 */
+#define PB6D_SERCOM5_PAD3 MCHP_PINMUX(b, 6, d, periph)
+
+/* pb6i_ccl0_in10 */
+#define PB6I_CCL0_IN10 MCHP_PINMUX(b, 6, i, periph)
+
+/* pb6k_gclk_io0 */
+#define PB6K_GCLK_IO0 MCHP_PINMUX(b, 6, k, periph)
+
+/* pb6p_ptc_ptcxy18 */
+#define PB6P_PTC_PTCXY18 MCHP_PINMUX(b, 6, p, periph)
+
+/* pb6p_ptc_drv18 */
+#define PB6P_PTC_DRV18 MCHP_PINMUX(b, 6, p, periph)
+
+/* pb6pdmo_lv_test_pdm_pdmo3 */
+#define PB6PDMO_LV_TEST_PDM_PDMO3 MCHP_PINMUX(b, 6, pdmo_lv_test, periph)
+
+/* pb6pdmo_mv_test_pdm_pdmo3_mv */
+#define PB6PDMO_MV_TEST_PDM_PDMO3_MV MCHP_PINMUX(b, 6, pdmo_mv_test, periph)
+
+/* pc0_gpio */
+#define PC0_GPIO MCHP_PINMUX(c, 0, gpio, gpio)
+
+/* pc0a_eic_extint0 */
+#define PC0A_EIC_EXTINT0 MCHP_PINMUX(c, 0, a, periph)
+
+/* pc0d_sercom0_pad0 */
+#define PC0D_SERCOM0_PAD0 MCHP_PINMUX(c, 0, d, periph)
+
+/* pc0f_tcc0_wo0 */
+#define PC0F_TCC0_WO0 MCHP_PINMUX(c, 0, f, periph)
+
+/* pc0i_ccl0_out3 */
+#define PC0I_CCL0_OUT3 MCHP_PINMUX(c, 0, i, periph)
+
+/* pc0k_gclk_io1 */
+#define PC0K_GCLK_IO1 MCHP_PINMUX(c, 0, k, periph)
+
+/* pc0p_ptc_ptcxy19 */
+#define PC0P_PTC_PTCXY19 MCHP_PINMUX(c, 0, p, periph)
+
+/* pc0p_ptc_drv19 */
+#define PC0P_PTC_DRV19 MCHP_PINMUX(c, 0, p, periph)
+
+/* pc0pdmo_lv_test_pdm_pdmo4 */
+#define PC0PDMO_LV_TEST_PDM_PDMO4 MCHP_PINMUX(c, 0, pdmo_lv_test, periph)
+
+/* pc0pdmo_mv_test_pdm_pdmo4_mv */
+#define PC0PDMO_MV_TEST_PDM_PDMO4_MV MCHP_PINMUX(c, 0, pdmo_mv_test, periph)
+
+/* pc1_gpio */
+#define PC1_GPIO MCHP_PINMUX(c, 1, gpio, gpio)
+
+/* pc1a_eic_extint1 */
+#define PC1A_EIC_EXTINT1 MCHP_PINMUX(c, 1, a, periph)
+
+/* pc1d_sercom0_pad1 */
+#define PC1D_SERCOM0_PAD1 MCHP_PINMUX(c, 1, d, periph)
+
+/* pc1f_tcc0_wo1 */
+#define PC1F_TCC0_WO1 MCHP_PINMUX(c, 1, f, periph)
+
+/* pc1h_can0_rx */
+#define PC1H_CAN0_RX MCHP_PINMUX(c, 1, h, periph)
+
+/* pc1i_ccl0_in0 */
+#define PC1I_CCL0_IN0 MCHP_PINMUX(c, 1, i, periph)
+
+/* pc1k_gclk_io2 */
+#define PC1K_GCLK_IO2 MCHP_PINMUX(c, 1, k, periph)
+
+/* pc1p_ptc_ptcxy20 */
+#define PC1P_PTC_PTCXY20 MCHP_PINMUX(c, 1, p, periph)
+
+/* pc1p_ptc_drv20 */
+#define PC1P_PTC_DRV20 MCHP_PINMUX(c, 1, p, periph)
+
+/* pc1pdmo_lv_test_pdm_pdmo5 */
+#define PC1PDMO_LV_TEST_PDM_PDMO5 MCHP_PINMUX(c, 1, pdmo_lv_test, periph)
+
+/* pc1pdmo_mv_test_pdm_pdmo5_mv */
+#define PC1PDMO_MV_TEST_PDM_PDMO5_MV MCHP_PINMUX(c, 1, pdmo_mv_test, periph)
+
+/* pc1valio_testval_valio4 */
+#define PC1VALIO_TESTVAL_VALIO4 MCHP_PINMUX(c, 1, valio, periph)
+
+/* pc2_gpio */
+#define PC2_GPIO MCHP_PINMUX(c, 2, gpio, gpio)
+
+/* pc2a_eic_extint2 */
+#define PC2A_EIC_EXTINT2 MCHP_PINMUX(c, 2, a, periph)
+
+/* pc2d_sercom0_pad2 */
+#define PC2D_SERCOM0_PAD2 MCHP_PINMUX(c, 2, d, periph)
+
+/* pc2f_tcc1_wo0 */
+#define PC2F_TCC1_WO0 MCHP_PINMUX(c, 2, f, periph)
+
+/* pc2h_can0_tx */
+#define PC2H_CAN0_TX MCHP_PINMUX(c, 2, h, periph)
+
+/* pc2i_ccl0_in1 */
+#define PC2I_CCL0_IN1 MCHP_PINMUX(c, 2, i, periph)
+
+/* pc2k_gclk_io3 */
+#define PC2K_GCLK_IO3 MCHP_PINMUX(c, 2, k, periph)
+
+/* pc2p_ptc_ptcxy21 */
+#define PC2P_PTC_PTCXY21 MCHP_PINMUX(c, 2, p, periph)
+
+/* pc2p_ptc_drv21 */
+#define PC2P_PTC_DRV21 MCHP_PINMUX(c, 2, p, periph)
+
+/* pc2pdmo_lv_test_pdm_pdmo6 */
+#define PC2PDMO_LV_TEST_PDM_PDMO6 MCHP_PINMUX(c, 2, pdmo_lv_test, periph)
+
+/* pc2pdmo_mv_test_pdm_pdmo6_mv */
+#define PC2PDMO_MV_TEST_PDM_PDMO6_MV MCHP_PINMUX(c, 2, pdmo_mv_test, periph)
+
+/* pc2valio_testval_valio5 */
+#define PC2VALIO_TESTVAL_VALIO5 MCHP_PINMUX(c, 2, valio, periph)
+
+/* pc3_gpio */
+#define PC3_GPIO MCHP_PINMUX(c, 3, gpio, gpio)
+
+/* pc3a_eic_extint3 */
+#define PC3A_EIC_EXTINT3 MCHP_PINMUX(c, 3, a, periph)
+
+/* pc3d_sercom0_pad3 */
+#define PC3D_SERCOM0_PAD3 MCHP_PINMUX(c, 3, d, periph)
+
+/* pc3f_tcc1_wo1 */
+#define PC3F_TCC1_WO1 MCHP_PINMUX(c, 3, f, periph)
+
+/* pc3i_ccl0_out0 */
+#define PC3I_CCL0_OUT0 MCHP_PINMUX(c, 3, i, periph)
+
+/* pc3k_gclk_io4 */
+#define PC3K_GCLK_IO4 MCHP_PINMUX(c, 3, k, periph)
+
+/* pc3p_ptc_eci0 */
+#define PC3P_PTC_ECI0 MCHP_PINMUX(c, 3, p, periph)
+
+/* pc3pdmo_lv_test_pdm_pdmo7 */
+#define PC3PDMO_LV_TEST_PDM_PDMO7 MCHP_PINMUX(c, 3, pdmo_lv_test, periph)
+
+/* pc3pdmo_mv_test_pdm_pdmo7_mv */
+#define PC3PDMO_MV_TEST_PDM_PDMO7_MV MCHP_PINMUX(c, 3, pdmo_mv_test, periph)
+
+/* pc4_gpio */
+#define PC4_GPIO MCHP_PINMUX(c, 4, gpio, gpio)
+
+/* pc4a_eic_extint4 */
+#define PC4A_EIC_EXTINT4 MCHP_PINMUX(c, 4, a, periph)
+
+/* pc4d_sercom2_pad0 */
+#define PC4D_SERCOM2_PAD0 MCHP_PINMUX(c, 4, d, periph)
+
+/* pc4f_tcc2_wo0 */
+#define PC4F_TCC2_WO0 MCHP_PINMUX(c, 4, f, periph)
+
+/* pc4i_ccl1_in0 */
+#define PC4I_CCL1_IN0 MCHP_PINMUX(c, 4, i, periph)
+
+/* pc4k_gclk_io5 */
+#define PC4K_GCLK_IO5 MCHP_PINMUX(c, 4, k, periph)
+
+/* pc4p_ptc_eci1 */
+#define PC4P_PTC_ECI1 MCHP_PINMUX(c, 4, p, periph)
+
+/* pc4valio_testval_valio2 */
+#define PC4VALIO_TESTVAL_VALIO2 MCHP_PINMUX(c, 4, valio, periph)
+
+/* pc5_gpio */
+#define PC5_GPIO MCHP_PINMUX(c, 5, gpio, gpio)
+
+/* pc5a_eic_extint5 */
+#define PC5A_EIC_EXTINT5 MCHP_PINMUX(c, 5, a, periph)
+
+/* pc5d_sercom1_pad3 */
+#define PC5D_SERCOM1_PAD3 MCHP_PINMUX(c, 5, d, periph)
+
+/* pc5dsu_msa_dsu_msa */
+#define PC5DSU_MSA_DSU_MSA MCHP_PINMUX(c, 5, dsu_msa, periph)
+
+/* pc5f_tcc2_wo1 */
+#define PC5F_TCC2_WO1 MCHP_PINMUX(c, 5, f, periph)
+
+/* pc5h_can1_rx */
+#define PC5H_CAN1_RX MCHP_PINMUX(c, 5, h, periph)
+
+/* pc5i_ccl1_in1 */
+#define PC5I_CCL1_IN1 MCHP_PINMUX(c, 5, i, periph)
+
+/* pc5k_gclk_io1 */
+#define PC5K_GCLK_IO1 MCHP_PINMUX(c, 5, k, periph)
+
+/* pc6_gpio */
+#define PC6_GPIO MCHP_PINMUX(c, 6, gpio, gpio)
+
+/* pc6a_eic_extint6 */
+#define PC6A_EIC_EXTINT6 MCHP_PINMUX(c, 6, a, periph)
+
+/* pc6d_sercom1_pad2 */
+#define PC6D_SERCOM1_PAD2 MCHP_PINMUX(c, 6, d, periph)
+
+/* pc6dsu_swccstat_dsu_swccstat */
+#define PC6DSU_SWCCSTAT_DSU_SWCCSTAT MCHP_PINMUX(c, 6, dsu_swccstat, periph)
+
+/* pc6h_can1_tx */
+#define PC6H_CAN1_TX MCHP_PINMUX(c, 6, h, periph)
+
+/* pc6i_ccl1_out0 */
+#define PC6I_CCL1_OUT0 MCHP_PINMUX(c, 6, i, periph)
+
+/* pc8_gpio */
+#define PC8_GPIO MCHP_PINMUX(c, 8, gpio, gpio)
+
+/* pc8dsu_test_gclk_gclk_tst_gclk */
+#define PC8DSU_TEST_GCLK_GCLK_TST_GCLK MCHP_PINMUX(c, 8, dsu_test_gclk, periph)
+
+/* pd0_gpio */
+#define PD0_GPIO MCHP_PINMUX(d, 0, gpio, gpio)
+
+/* pd0a_eic_nmi */
+#define PD0A_EIC_NMI MCHP_PINMUX(d, 0, a, periph)
+
+/* pd0d_sercom1_pad1 */
+#define PD0D_SERCOM1_PAD1 MCHP_PINMUX(d, 0, d, periph)
+
+/* pd0f_tcc3_wo0 */
+#define PD0F_TCC3_WO0 MCHP_PINMUX(d, 0, f, periph)
+
+/* pd0i_ccl0_in3 */
+#define PD0I_CCL0_IN3 MCHP_PINMUX(d, 0, i, periph)
+
+/* pd0valio_testval_valio0 */
+#define PD0VALIO_TESTVAL_VALIO0 MCHP_PINMUX(d, 0, valio, periph)
+
+/* pd1_gpio */
+#define PD1_GPIO MCHP_PINMUX(d, 1, gpio, gpio)
+
+/* pd1a_eic_extint1 */
+#define PD1A_EIC_EXTINT1 MCHP_PINMUX(d, 1, a, periph)
+
+/* pd1d_sercom1_pad0 */
+#define PD1D_SERCOM1_PAD0 MCHP_PINMUX(d, 1, d, periph)
+
+/* pd1f_tcc3_wo1 */
+#define PD1F_TCC3_WO1 MCHP_PINMUX(d, 1, f, periph)
+
+/* pd1h_usb_sof */
+#define PD1H_USB_SOF MCHP_PINMUX(d, 1, h, periph)
+
+/* pd1i_ccl0_in4 */
+#define PD1I_CCL0_IN4 MCHP_PINMUX(d, 1, i, periph)
+
+/* pd1valio_testval_valio1 */
+#define PD1VALIO_TESTVAL_VALIO1 MCHP_PINMUX(d, 1, valio, periph)
+
+/* pd2_gpio */
+#define PD2_GPIO MCHP_PINMUX(d, 2, gpio, gpio)
+
+/* pd2h_usb_usbdm */
+#define PD2H_USB_USBDM MCHP_PINMUX(d, 2, h, periph)
+
+/* pd3_gpio */
+#define PD3_GPIO MCHP_PINMUX(d, 3, gpio, gpio)
+
+/* pd3h_usb_usbdp */
+#define PD3H_USB_USBDP MCHP_PINMUX(d, 3, h, periph)
+
+/* pd4_gpio */
+#define PD4_GPIO MCHP_PINMUX(d, 4, gpio, gpio)
+
+/* pd4a_eic_extint2 */
+#define PD4A_EIC_EXTINT2 MCHP_PINMUX(d, 4, a, periph)
+
+/* pd4k_gclk_io1 */
+#define PD4K_GCLK_IO1 MCHP_PINMUX(d, 4, k, periph)
+
+/* pd5_gpio */
+#define PD5_GPIO MCHP_PINMUX(d, 5, gpio, gpio)
+
+/* pd5a_eic_extint3 */
+#define PD5A_EIC_EXTINT3 MCHP_PINMUX(d, 5, a, periph)
+
+/* pd5k_gclk_io0 */
+#define PD5K_GCLK_IO0 MCHP_PINMUX(d, 5, k, periph)
+
+/* pd6_gpio */
+#define PD6_GPIO MCHP_PINMUX(d, 6, gpio, gpio)
+
+/* pd6d_sercom2_pad1 */
+#define PD6D_SERCOM2_PAD1 MCHP_PINMUX(d, 6, d, periph)
+
+/* pd6h_can0_rx */
+#define PD6H_CAN0_RX MCHP_PINMUX(d, 6, h, periph)
+
+/* pd6i_ccl1_in3 */
+#define PD6I_CCL1_IN3 MCHP_PINMUX(d, 6, i, periph)
+
+/* pd6p_ptc_ptcxy0 */
+#define PD6P_PTC_PTCXY0 MCHP_PINMUX(d, 6, p, periph)
+
+/* pd6p_ptc_drv0 */
+#define PD6P_PTC_DRV0 MCHP_PINMUX(d, 6, p, periph)
+
+/* pd7_gpio */
+#define PD7_GPIO MCHP_PINMUX(d, 7, gpio, gpio)
+
+/* pd7a_eic_extint4 */
+#define PD7A_EIC_EXTINT4 MCHP_PINMUX(d, 7, a, periph)
+
+/* pd7adc_test_pad_adc_res_test2 */
+#define PD7ADC_TEST_PAD_ADC_RES_TEST2 MCHP_PINMUX(d, 7, adc_test_pad, periph)
+
+/* pd7d_sercom2_pad2 */
+#define PD7D_SERCOM2_PAD2 MCHP_PINMUX(d, 7, d, periph)
+
+/* pd7f_tcc4_wo0 */
+#define PD7F_TCC4_WO0 MCHP_PINMUX(d, 7, f, periph)
+
+/* pd7i_ccl1_in4 */
+#define PD7I_CCL1_IN4 MCHP_PINMUX(d, 7, i, periph)
+
+/* pd7p_ptc_ptcxy1 */
+#define PD7P_PTC_PTCXY1 MCHP_PINMUX(d, 7, p, periph)
+
+/* pd7p_ptc_drv1 */
+#define PD7P_PTC_DRV1 MCHP_PINMUX(d, 7, p, periph)
+
+/* pd7pdmi_test_pdm_pdmi0 */
+#define PD7PDMI_TEST_PDM_PDMI0 MCHP_PINMUX(d, 7, pdmi_test, periph)
+
+/* pd8_gpio */
+#define PD8_GPIO MCHP_PINMUX(d, 8, gpio, gpio)
+
+/* pd8a_eic_extint5 */
+#define PD8A_EIC_EXTINT5 MCHP_PINMUX(d, 8, a, periph)
+
+/* pd8adc_test_pad_adc_res_test0 */
+#define PD8ADC_TEST_PAD_ADC_RES_TEST0 MCHP_PINMUX(d, 8, adc_test_pad, periph)
+
+/* pd8d_sercom2_pad3 */
+#define PD8D_SERCOM2_PAD3 MCHP_PINMUX(d, 8, d, periph)
+
+/* pd8f_tcc4_wo1 */
+#define PD8F_TCC4_WO1 MCHP_PINMUX(d, 8, f, periph)
+
+/* pd8h_can0_tx */
+#define PD8H_CAN0_TX MCHP_PINMUX(d, 8, h, periph)
+
+/* pd8i_ccl0_out1 */
+#define PD8I_CCL0_OUT1 MCHP_PINMUX(d, 8, i, periph)
+
+/* pd8p_ptc_ptcxy2 */
+#define PD8P_PTC_PTCXY2 MCHP_PINMUX(d, 8, p, periph)
+
+/* pd8p_ptc_drv2 */
+#define PD8P_PTC_DRV2 MCHP_PINMUX(d, 8, p, periph)
+
+/* pd8pdmi_test_pdm_pdmi1 */
+#define PD8PDMI_TEST_PDM_PDMI1 MCHP_PINMUX(d, 8, pdmi_test, periph)
+
+/* pd9_gpio */
+#define PD9_GPIO MCHP_PINMUX(d, 9, gpio, gpio)
+
+/* pd9a_eic_extint6 */
+#define PD9A_EIC_EXTINT6 MCHP_PINMUX(d, 9, a, periph)
+
+/* pd9adc_test_pad_adc_res_test1 */
+#define PD9ADC_TEST_PAD_ADC_RES_TEST1 MCHP_PINMUX(d, 9, adc_test_pad, periph)
+
+/* pd9d_sercom3_pad0 */
+#define PD9D_SERCOM3_PAD0 MCHP_PINMUX(d, 9, d, periph)
+
+/* pd9f_tcc5_wo0 */
+#define PD9F_TCC5_WO0 MCHP_PINMUX(d, 9, f, periph)
+
+/* pd9i_ccl1_out1 */
+#define PD9I_CCL1_OUT1 MCHP_PINMUX(d, 9, i, periph)
+
+/* pd9p_ptc_ptcxy3 */
+#define PD9P_PTC_PTCXY3 MCHP_PINMUX(d, 9, p, periph)
+
+/* pd9p_ptc_drv3 */
+#define PD9P_PTC_DRV3 MCHP_PINMUX(d, 9, p, periph)
+
+/* pd9pdmi_test_pdm_pdmi2 */
+#define PD9PDMI_TEST_PDM_PDMI2 MCHP_PINMUX(d, 9, pdmi_test, periph)
+
+#endif /* MICROCHIP_PIC32CM5112GC00048_PINCTRL_H_ */
diff --git a/include/dt-bindings/pic32c/pic32cm_gc_sg/pic32cm_gc00/pic32cm5112gc00064-pinctrl.h b/include/dt-bindings/pic32c/pic32cm_gc_sg/pic32cm_gc00/pic32cm5112gc00064-pinctrl.h
new file mode 100644
index 00000000..d2b02822
--- /dev/null
+++ b/include/dt-bindings/pic32c/pic32cm_gc_sg/pic32cm_gc00/pic32cm5112gc00064-pinctrl.h
@@ -0,0 +1,1028 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Autogenerated file
+ */
+
+#ifndef MICROCHIP_PIC32CM5112GC00064_PINCTRL_H_
+#define MICROCHIP_PIC32CM5112GC00064_PINCTRL_H_
+
+#include <dt-bindings/pic32c/common/mchp_pinctrl_pinmux_pic32c.h>
+
+/* pa0_gpio */
+#define PA0_GPIO MCHP_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 MCHP_PINMUX(a, 0, a, periph)
+
+/* pa0adc_test_pad_adc_res_test3 */
+#define PA0ADC_TEST_PAD_ADC_RES_TEST3 MCHP_PINMUX(a, 0, adc_test_pad, periph)
+
+/* pa0d_sercom3_pad1 */
+#define PA0D_SERCOM3_PAD1 MCHP_PINMUX(a, 0, d, periph)
+
+/* pa0f_tcc5_wo1 */
+#define PA0F_TCC5_WO1 MCHP_PINMUX(a, 0, f, periph)
+
+/* pa0h_can1_rx */
+#define PA0H_CAN1_RX MCHP_PINMUX(a, 0, h, periph)
+
+/* pa0i_ccl0_in6 */
+#define PA0I_CCL0_IN6 MCHP_PINMUX(a, 0, i, periph)
+
+/* pa0p_ptc_ptcxy4 */
+#define PA0P_PTC_PTCXY4 MCHP_PINMUX(a, 0, p, periph)
+
+/* pa0p_ptc_drv4 */
+#define PA0P_PTC_DRV4 MCHP_PINMUX(a, 0, p, periph)
+
+/* pa0pdmi_test_pdm_pdmi3 */
+#define PA0PDMI_TEST_PDM_PDMI3 MCHP_PINMUX(a, 0, pdmi_test, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO MCHP_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 MCHP_PINMUX(a, 1, a, periph)
+
+/* pa1adc_test_pad_adc_res_test4 */
+#define PA1ADC_TEST_PAD_ADC_RES_TEST4 MCHP_PINMUX(a, 1, adc_test_pad, periph)
+
+/* pa1b_ac_cmp0 */
+#define PA1B_AC_CMP0 MCHP_PINMUX(a, 1, b, periph)
+
+/* pa1d_sercom3_pad2 */
+#define PA1D_SERCOM3_PAD2 MCHP_PINMUX(a, 1, d, periph)
+
+/* pa1f_tcc6_wo0 */
+#define PA1F_TCC6_WO0 MCHP_PINMUX(a, 1, f, periph)
+
+/* pa1h_can1_tx */
+#define PA1H_CAN1_TX MCHP_PINMUX(a, 1, h, periph)
+
+/* pa1i_ccl0_in7 */
+#define PA1I_CCL0_IN7 MCHP_PINMUX(a, 1, i, periph)
+
+/* pa1p_ptc_ptcxy5 */
+#define PA1P_PTC_PTCXY5 MCHP_PINMUX(a, 1, p, periph)
+
+/* pa1p_ptc_drv5 */
+#define PA1P_PTC_DRV5 MCHP_PINMUX(a, 1, p, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO MCHP_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 MCHP_PINMUX(a, 2, a, periph)
+
+/* pa2adc_test_pad_adc_res_test5 */
+#define PA2ADC_TEST_PAD_ADC_RES_TEST5 MCHP_PINMUX(a, 2, adc_test_pad, periph)
+
+/* pa2b_ac_cmp1 */
+#define PA2B_AC_CMP1 MCHP_PINMUX(a, 2, b, periph)
+
+/* pa2d_sercom3_pad3 */
+#define PA2D_SERCOM3_PAD3 MCHP_PINMUX(a, 2, d, periph)
+
+/* pa2f_tcc6_wo1 */
+#define PA2F_TCC6_WO1 MCHP_PINMUX(a, 2, f, periph)
+
+/* pa2i_ccl0_out2 */
+#define PA2I_CCL0_OUT2 MCHP_PINMUX(a, 2, i, periph)
+
+/* pa2p_ptc_ptcxy6 */
+#define PA2P_PTC_PTCXY6 MCHP_PINMUX(a, 2, p, periph)
+
+/* pa2p_ptc_drv6 */
+#define PA2P_PTC_DRV6 MCHP_PINMUX(a, 2, p, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO MCHP_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 MCHP_PINMUX(a, 3, a, periph)
+
+/* pa3adc_test_pad_adc_res_test6 */
+#define PA3ADC_TEST_PAD_ADC_RES_TEST6 MCHP_PINMUX(a, 3, adc_test_pad, periph)
+
+/* pa3b_adc_adc0_ain0 */
+#define PA3B_ADC_ADC0_AIN0 MCHP_PINMUX(a, 3, b, periph)
+
+/* pa3d_sercom4_pad0 */
+#define PA3D_SERCOM4_PAD0 MCHP_PINMUX(a, 3, d, periph)
+
+/* pa3p_ptc_ptcxy7 */
+#define PA3P_PTC_PTCXY7 MCHP_PINMUX(a, 3, p, periph)
+
+/* pa3p_ptc_drv7 */
+#define PA3P_PTC_DRV7 MCHP_PINMUX(a, 3, p, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO MCHP_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 MCHP_PINMUX(a, 4, a, periph)
+
+/* pa4adc_test_pad_adc_res_test7 */
+#define PA4ADC_TEST_PAD_ADC_RES_TEST7 MCHP_PINMUX(a, 4, adc_test_pad, periph)
+
+/* pa4b_adc_adc0_ain1 */
+#define PA4B_ADC_ADC0_AIN1 MCHP_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc_adc0_ann0 */
+#define PA4B_ADC_ADC0_ANN0 MCHP_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom4_pad1 */
+#define PA4D_SERCOM4_PAD1 MCHP_PINMUX(a, 4, d, periph)
+
+/* pa4p_ptc_ptcxy8 */
+#define PA4P_PTC_PTCXY8 MCHP_PINMUX(a, 4, p, periph)
+
+/* pa4p_ptc_drv8 */
+#define PA4P_PTC_DRV8 MCHP_PINMUX(a, 4, p, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO MCHP_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 MCHP_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc_adc0_ain2 */
+#define PA5B_ADC_ADC0_AIN2 MCHP_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom4_pad2 */
+#define PA5D_SERCOM4_PAD2 MCHP_PINMUX(a, 5, d, periph)
+
+/* pa5i_ccl1_out2 */
+#define PA5I_CCL1_OUT2 MCHP_PINMUX(a, 5, i, periph)
+
+/* pa5p_ptc_ptcxy9 */
+#define PA5P_PTC_PTCXY9 MCHP_PINMUX(a, 5, p, periph)
+
+/* pa5p_ptc_drv9 */
+#define PA5P_PTC_DRV9 MCHP_PINMUX(a, 5, p, periph)
+
+/* pa5valio_testval_valio3 */
+#define PA5VALIO_TESTVAL_VALIO3 MCHP_PINMUX(a, 5, valio, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO MCHP_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 MCHP_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc_adc0_ain3 */
+#define PA6B_ADC_ADC0_AIN3 MCHP_PINMUX(a, 6, b, periph)
+
+/* pa6b_adc_adc0_ann2 */
+#define PA6B_ADC_ADC0_ANN2 MCHP_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom4_pad3 */
+#define PA6D_SERCOM4_PAD3 MCHP_PINMUX(a, 6, d, periph)
+
+/* pa6i_ccl1_in7 */
+#define PA6I_CCL1_IN7 MCHP_PINMUX(a, 6, i, periph)
+
+/* pa6p_ptc_ptcxy10 */
+#define PA6P_PTC_PTCXY10 MCHP_PINMUX(a, 6, p, periph)
+
+/* pa6p_ptc_drv10 */
+#define PA6P_PTC_DRV10 MCHP_PINMUX(a, 6, p, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO MCHP_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 MCHP_PINMUX(a, 7, a, periph)
+
+/* pa7b_ac_ain0 */
+#define PA7B_AC_AIN0 MCHP_PINMUX(a, 7, b, periph)
+
+/* pa7b_adc_adc0_ain4 */
+#define PA7B_ADC_ADC0_AIN4 MCHP_PINMUX(a, 7, b, periph)
+
+/* pa7p_ptc_ptcxy11 */
+#define PA7P_PTC_PTCXY11 MCHP_PINMUX(a, 7, p, periph)
+
+/* pa7p_ptc_drv11 */
+#define PA7P_PTC_DRV11 MCHP_PINMUX(a, 7, p, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO MCHP_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_extint8 */
+#define PA8A_EIC_EXTINT8 MCHP_PINMUX(a, 8, a, periph)
+
+/* pa8b_ac_ain1 */
+#define PA8B_AC_AIN1 MCHP_PINMUX(a, 8, b, periph)
+
+/* pa8b_adc_adc0_ain5 */
+#define PA8B_ADC_ADC0_AIN5 MCHP_PINMUX(a, 8, b, periph)
+
+/* pa8b_adc_adc0_ann4 */
+#define PA8B_ADC_ADC0_ANN4 MCHP_PINMUX(a, 8, b, periph)
+
+/* pa8p_ptc_ptcxy12 */
+#define PA8P_PTC_PTCXY12 MCHP_PINMUX(a, 8, p, periph)
+
+/* pa8p_ptc_drv12 */
+#define PA8P_PTC_DRV12 MCHP_PINMUX(a, 8, p, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO MCHP_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 MCHP_PINMUX(a, 9, a, periph)
+
+/* pa9b_adc_adc0_ain6 */
+#define PA9B_ADC_ADC0_AIN6 MCHP_PINMUX(a, 9, b, periph)
+
+/* pa9i_ccl1_in6 */
+#define PA9I_CCL1_IN6 MCHP_PINMUX(a, 9, i, periph)
+
+/* pa9p_ptc_ptcxy13 */
+#define PA9P_PTC_PTCXY13 MCHP_PINMUX(a, 9, p, periph)
+
+/* pa9p_ptc_drv13 */
+#define PA9P_PTC_DRV13 MCHP_PINMUX(a, 9, p, periph)
+
+/* pa9volt_ref_adc_vrefh */
+#define PA9VOLT_REF_ADC_VREFH MCHP_PINMUX(a, 9, volt_ref, periph)
+
+/* pa10_gpio */
+#define PA10_GPIO MCHP_PINMUX(a, 10, gpio, gpio)
+
+/* pa10a_eic_extint10 */
+#define PA10A_EIC_EXTINT10 MCHP_PINMUX(a, 10, a, periph)
+
+/* pa10f_tcc4_wo0 */
+#define PA10F_TCC4_WO0 MCHP_PINMUX(a, 10, f, periph)
+
+/* pa10h_can0_rx */
+#define PA10H_CAN0_RX MCHP_PINMUX(a, 10, h, periph)
+
+/* pa10i_ccl0_in8 */
+#define PA10I_CCL0_IN8 MCHP_PINMUX(a, 10, i, periph)
+
+/* pa10p_ptc_ptcxy22 */
+#define PA10P_PTC_PTCXY22 MCHP_PINMUX(a, 10, p, periph)
+
+/* pa10p_ptc_drv22 */
+#define PA10P_PTC_DRV22 MCHP_PINMUX(a, 10, p, periph)
+
+/* pa11_gpio */
+#define PA11_GPIO MCHP_PINMUX(a, 11, gpio, gpio)
+
+/* pa11a_eic_extint11 */
+#define PA11A_EIC_EXTINT11 MCHP_PINMUX(a, 11, a, periph)
+
+/* pa11f_tcc4_wo1 */
+#define PA11F_TCC4_WO1 MCHP_PINMUX(a, 11, f, periph)
+
+/* pa11h_can0_tx */
+#define PA11H_CAN0_TX MCHP_PINMUX(a, 11, h, periph)
+
+/* pa11i_ccl1_in8 */
+#define PA11I_CCL1_IN8 MCHP_PINMUX(a, 11, i, periph)
+
+/* pa11p_ptc_ptcxy23 */
+#define PA11P_PTC_PTCXY23 MCHP_PINMUX(a, 11, p, periph)
+
+/* pa11p_ptc_drv23 */
+#define PA11P_PTC_DRV23 MCHP_PINMUX(a, 11, p, periph)
+
+/* pa12_gpio */
+#define PA12_GPIO MCHP_PINMUX(a, 12, gpio, gpio)
+
+/* pa12a_eic_extint12 */
+#define PA12A_EIC_EXTINT12 MCHP_PINMUX(a, 12, a, periph)
+
+/* pa12i_ccl1_in8 */
+#define PA12I_CCL1_IN8 MCHP_PINMUX(a, 12, i, periph)
+
+/* pa12p_ptc_ptcxy24 */
+#define PA12P_PTC_PTCXY24 MCHP_PINMUX(a, 12, p, periph)
+
+/* pa12p_ptc_drv24 */
+#define PA12P_PTC_DRV24 MCHP_PINMUX(a, 12, p, periph)
+
+/* pa13_gpio */
+#define PA13_GPIO MCHP_PINMUX(a, 13, gpio, gpio)
+
+/* pa13a_eic_extint13 */
+#define PA13A_EIC_EXTINT13 MCHP_PINMUX(a, 13, a, periph)
+
+/* pa13b_ac_cmp0 */
+#define PA13B_AC_CMP0 MCHP_PINMUX(a, 13, b, periph)
+
+/* pa13p_ptc_ptcxy25 */
+#define PA13P_PTC_PTCXY25 MCHP_PINMUX(a, 13, p, periph)
+
+/* pa13p_ptc_drv25 */
+#define PA13P_PTC_DRV25 MCHP_PINMUX(a, 13, p, periph)
+
+/* pb0_gpio */
+#define PB0_GPIO MCHP_PINMUX(b, 0, gpio, gpio)
+
+/* pb0a_eic_extint0 */
+#define PB0A_EIC_EXTINT0 MCHP_PINMUX(b, 0, a, periph)
+
+/* pb0b_ac_ain2 */
+#define PB0B_AC_AIN2 MCHP_PINMUX(b, 0, b, periph)
+
+/* pb0b_adc_adc0_ain7 */
+#define PB0B_ADC_ADC0_AIN7 MCHP_PINMUX(b, 0, b, periph)
+
+/* pb0i_ccl1_out3 */
+#define PB0I_CCL1_OUT3 MCHP_PINMUX(b, 0, i, periph)
+
+/* pb0p_ptc_ptcxy14 */
+#define PB0P_PTC_PTCXY14 MCHP_PINMUX(b, 0, p, periph)
+
+/* pb0p_ptc_drv14 */
+#define PB0P_PTC_DRV14 MCHP_PINMUX(b, 0, p, periph)
+
+/* pb1_gpio */
+#define PB1_GPIO MCHP_PINMUX(b, 1, gpio, gpio)
+
+/* pb1a_eic_extint1 */
+#define PB1A_EIC_EXTINT1 MCHP_PINMUX(b, 1, a, periph)
+
+/* pb2_gpio */
+#define PB2_GPIO MCHP_PINMUX(b, 2, gpio, gpio)
+
+/* pb2a_eic_extint2 */
+#define PB2A_EIC_EXTINT2 MCHP_PINMUX(b, 2, a, periph)
+
+/* pb3_gpio */
+#define PB3_GPIO MCHP_PINMUX(b, 3, gpio, gpio)
+
+/* pb3a_eic_extint3 */
+#define PB3A_EIC_EXTINT3 MCHP_PINMUX(b, 3, a, periph)
+
+/* pb3adc_test_pad_adc_res_test8 */
+#define PB3ADC_TEST_PAD_ADC_RES_TEST8 MCHP_PINMUX(b, 3, adc_test_pad, periph)
+
+/* pb3b_ac_ain3 */
+#define PB3B_AC_AIN3 MCHP_PINMUX(b, 3, b, periph)
+
+/* pb3b_adc_adc0_ain8 */
+#define PB3B_ADC_ADC0_AIN8 MCHP_PINMUX(b, 3, b, periph)
+
+/* pb3d_sercom5_pad0 */
+#define PB3D_SERCOM5_PAD0 MCHP_PINMUX(b, 3, d, periph)
+
+/* pb3i_ccl1_in10 */
+#define PB3I_CCL1_IN10 MCHP_PINMUX(b, 3, i, periph)
+
+/* pb3p_ptc_ptcxy15 */
+#define PB3P_PTC_PTCXY15 MCHP_PINMUX(b, 3, p, periph)
+
+/* pb3p_ptc_drv15 */
+#define PB3P_PTC_DRV15 MCHP_PINMUX(b, 3, p, periph)
+
+/* pb3pdmo_lv_test_pdm_pdmo0 */
+#define PB3PDMO_LV_TEST_PDM_PDMO0 MCHP_PINMUX(b, 3, pdmo_lv_test, periph)
+
+/* pb3pdmo_mv_test_pdm_pdmo0_mv */
+#define PB3PDMO_MV_TEST_PDM_PDMO0_MV MCHP_PINMUX(b, 3, pdmo_mv_test, periph)
+
+/* pb4_gpio */
+#define PB4_GPIO MCHP_PINMUX(b, 4, gpio, gpio)
+
+/* pb4a_eic_extint4 */
+#define PB4A_EIC_EXTINT4 MCHP_PINMUX(b, 4, a, periph)
+
+/* pb4adc_test_pad_adc_res_test9 */
+#define PB4ADC_TEST_PAD_ADC_RES_TEST9 MCHP_PINMUX(b, 4, adc_test_pad, periph)
+
+/* pb4b_adc_adc0_ain9 */
+#define PB4B_ADC_ADC0_AIN9 MCHP_PINMUX(b, 4, b, periph)
+
+/* pb4d_sercom5_pad1 */
+#define PB4D_SERCOM5_PAD1 MCHP_PINMUX(b, 4, d, periph)
+
+/* pb4i_ccl1_in9 */
+#define PB4I_CCL1_IN9 MCHP_PINMUX(b, 4, i, periph)
+
+/* pb4p_ptc_ptcxy16 */
+#define PB4P_PTC_PTCXY16 MCHP_PINMUX(b, 4, p, periph)
+
+/* pb4p_ptc_drv16 */
+#define PB4P_PTC_DRV16 MCHP_PINMUX(b, 4, p, periph)
+
+/* pb4pdmo_lv_test_pdm_pdmo1 */
+#define PB4PDMO_LV_TEST_PDM_PDMO1 MCHP_PINMUX(b, 4, pdmo_lv_test, periph)
+
+/* pb4pdmo_mv_test_pdm_pdmo1_mv */
+#define PB4PDMO_MV_TEST_PDM_PDMO1_MV MCHP_PINMUX(b, 4, pdmo_mv_test, periph)
+
+/* pb5_gpio */
+#define PB5_GPIO MCHP_PINMUX(b, 5, gpio, gpio)
+
+/* pb5a_eic_extint5 */
+#define PB5A_EIC_EXTINT5 MCHP_PINMUX(b, 5, a, periph)
+
+/* pb5adc_test_pad_adc_res_test10 */
+#define PB5ADC_TEST_PAD_ADC_RES_TEST10 MCHP_PINMUX(b, 5, adc_test_pad, periph)
+
+/* pb5b_adc_adc0_ain10 */
+#define PB5B_ADC_ADC0_AIN10 MCHP_PINMUX(b, 5, b, periph)
+
+/* pb5d_sercom5_pad2 */
+#define PB5D_SERCOM5_PAD2 MCHP_PINMUX(b, 5, d, periph)
+
+/* pb5i_ccl0_in9 */
+#define PB5I_CCL0_IN9 MCHP_PINMUX(b, 5, i, periph)
+
+/* pb5p_ptc_ptcxy17 */
+#define PB5P_PTC_PTCXY17 MCHP_PINMUX(b, 5, p, periph)
+
+/* pb5p_ptc_drv17 */
+#define PB5P_PTC_DRV17 MCHP_PINMUX(b, 5, p, periph)
+
+/* pb5pdmo_lv_test_pdm_pdmo2 */
+#define PB5PDMO_LV_TEST_PDM_PDMO2 MCHP_PINMUX(b, 5, pdmo_lv_test, periph)
+
+/* pb5pdmo_mv_test_pdm_pdmo2_mv */
+#define PB5PDMO_MV_TEST_PDM_PDMO2_MV MCHP_PINMUX(b, 5, pdmo_mv_test, periph)
+
+/* pb6_gpio */
+#define PB6_GPIO MCHP_PINMUX(b, 6, gpio, gpio)
+
+/* pb6a_eic_extint6 */
+#define PB6A_EIC_EXTINT6 MCHP_PINMUX(b, 6, a, periph)
+
+/* pb6adc_test_pad_adc_res_test11 */
+#define PB6ADC_TEST_PAD_ADC_RES_TEST11 MCHP_PINMUX(b, 6, adc_test_pad, periph)
+
+/* pb6b_adc_adc0_ain11 */
+#define PB6B_ADC_ADC0_AIN11 MCHP_PINMUX(b, 6, b, periph)
+
+/* pb6d_sercom5_pad3 */
+#define PB6D_SERCOM5_PAD3 MCHP_PINMUX(b, 6, d, periph)
+
+/* pb6i_ccl0_in10 */
+#define PB6I_CCL0_IN10 MCHP_PINMUX(b, 6, i, periph)
+
+/* pb6k_gclk_io0 */
+#define PB6K_GCLK_IO0 MCHP_PINMUX(b, 6, k, periph)
+
+/* pb6p_ptc_ptcxy18 */
+#define PB6P_PTC_PTCXY18 MCHP_PINMUX(b, 6, p, periph)
+
+/* pb6p_ptc_drv18 */
+#define PB6P_PTC_DRV18 MCHP_PINMUX(b, 6, p, periph)
+
+/* pb6pdmo_lv_test_pdm_pdmo3 */
+#define PB6PDMO_LV_TEST_PDM_PDMO3 MCHP_PINMUX(b, 6, pdmo_lv_test, periph)
+
+/* pb6pdmo_mv_test_pdm_pdmo3_mv */
+#define PB6PDMO_MV_TEST_PDM_PDMO3_MV MCHP_PINMUX(b, 6, pdmo_mv_test, periph)
+
+/* pb7_gpio */
+#define PB7_GPIO MCHP_PINMUX(b, 7, gpio, gpio)
+
+/* pb7a_eic_extint8 */
+#define PB7A_EIC_EXTINT8 MCHP_PINMUX(b, 7, a, periph)
+
+/* pb7b_ac_cmp1 */
+#define PB7B_AC_CMP1 MCHP_PINMUX(b, 7, b, periph)
+
+/* pb7i_ccl1_in11 */
+#define PB7I_CCL1_IN11 MCHP_PINMUX(b, 7, i, periph)
+
+/* pb7p_ptc_ptcxy26 */
+#define PB7P_PTC_PTCXY26 MCHP_PINMUX(b, 7, p, periph)
+
+/* pb7p_ptc_drv26 */
+#define PB7P_PTC_DRV26 MCHP_PINMUX(b, 7, p, periph)
+
+/* pb8_gpio */
+#define PB8_GPIO MCHP_PINMUX(b, 8, gpio, gpio)
+
+/* pb8a_eic_extint9 */
+#define PB8A_EIC_EXTINT9 MCHP_PINMUX(b, 8, a, periph)
+
+/* pb8f_tcc2_wo1 */
+#define PB8F_TCC2_WO1 MCHP_PINMUX(b, 8, f, periph)
+
+/* pb8i_ccl1_in11 */
+#define PB8I_CCL1_IN11 MCHP_PINMUX(b, 8, i, periph)
+
+/* pb8p_ptc_ptcxy27 */
+#define PB8P_PTC_PTCXY27 MCHP_PINMUX(b, 8, p, periph)
+
+/* pb8p_ptc_drv27 */
+#define PB8P_PTC_DRV27 MCHP_PINMUX(b, 8, p, periph)
+
+/* pb9_gpio */
+#define PB9_GPIO MCHP_PINMUX(b, 9, gpio, gpio)
+
+/* pb9a_eic_extint10 */
+#define PB9A_EIC_EXTINT10 MCHP_PINMUX(b, 9, a, periph)
+
+/* pb9f_tcc2_wo0 */
+#define PB9F_TCC2_WO0 MCHP_PINMUX(b, 9, f, periph)
+
+/* pb9k_gclk_io7 */
+#define PB9K_GCLK_IO7 MCHP_PINMUX(b, 9, k, periph)
+
+/* pb9p_ptc_ptcxy28 */
+#define PB9P_PTC_PTCXY28 MCHP_PINMUX(b, 9, p, periph)
+
+/* pb9p_ptc_drv28 */
+#define PB9P_PTC_DRV28 MCHP_PINMUX(b, 9, p, periph)
+
+/* pb10_gpio */
+#define PB10_GPIO MCHP_PINMUX(b, 10, gpio, gpio)
+
+/* pb10a_eic_extint11 */
+#define PB10A_EIC_EXTINT11 MCHP_PINMUX(b, 10, a, periph)
+
+/* pb10i_ccl0_in11 */
+#define PB10I_CCL0_IN11 MCHP_PINMUX(b, 10, i, periph)
+
+/* pb10k_gclk_io6 */
+#define PB10K_GCLK_IO6 MCHP_PINMUX(b, 10, k, periph)
+
+/* pb10p_ptc_ptcxy29 */
+#define PB10P_PTC_PTCXY29 MCHP_PINMUX(b, 10, p, periph)
+
+/* pb10p_ptc_drv29 */
+#define PB10P_PTC_DRV29 MCHP_PINMUX(b, 10, p, periph)
+
+/* pc0_gpio */
+#define PC0_GPIO MCHP_PINMUX(c, 0, gpio, gpio)
+
+/* pc0a_eic_extint0 */
+#define PC0A_EIC_EXTINT0 MCHP_PINMUX(c, 0, a, periph)
+
+/* pc0d_sercom0_pad0 */
+#define PC0D_SERCOM0_PAD0 MCHP_PINMUX(c, 0, d, periph)
+
+/* pc0f_tcc0_wo0 */
+#define PC0F_TCC0_WO0 MCHP_PINMUX(c, 0, f, periph)
+
+/* pc0i_ccl0_out3 */
+#define PC0I_CCL0_OUT3 MCHP_PINMUX(c, 0, i, periph)
+
+/* pc0k_gclk_io1 */
+#define PC0K_GCLK_IO1 MCHP_PINMUX(c, 0, k, periph)
+
+/* pc0p_ptc_ptcxy19 */
+#define PC0P_PTC_PTCXY19 MCHP_PINMUX(c, 0, p, periph)
+
+/* pc0p_ptc_drv19 */
+#define PC0P_PTC_DRV19 MCHP_PINMUX(c, 0, p, periph)
+
+/* pc0pdmo_lv_test_pdm_pdmo4 */
+#define PC0PDMO_LV_TEST_PDM_PDMO4 MCHP_PINMUX(c, 0, pdmo_lv_test, periph)
+
+/* pc0pdmo_mv_test_pdm_pdmo4_mv */
+#define PC0PDMO_MV_TEST_PDM_PDMO4_MV MCHP_PINMUX(c, 0, pdmo_mv_test, periph)
+
+/* pc1_gpio */
+#define PC1_GPIO MCHP_PINMUX(c, 1, gpio, gpio)
+
+/* pc1a_eic_extint1 */
+#define PC1A_EIC_EXTINT1 MCHP_PINMUX(c, 1, a, periph)
+
+/* pc1d_sercom0_pad1 */
+#define PC1D_SERCOM0_PAD1 MCHP_PINMUX(c, 1, d, periph)
+
+/* pc1f_tcc0_wo1 */
+#define PC1F_TCC0_WO1 MCHP_PINMUX(c, 1, f, periph)
+
+/* pc1h_can0_rx */
+#define PC1H_CAN0_RX MCHP_PINMUX(c, 1, h, periph)
+
+/* pc1i_ccl0_in0 */
+#define PC1I_CCL0_IN0 MCHP_PINMUX(c, 1, i, periph)
+
+/* pc1k_gclk_io2 */
+#define PC1K_GCLK_IO2 MCHP_PINMUX(c, 1, k, periph)
+
+/* pc1p_ptc_ptcxy20 */
+#define PC1P_PTC_PTCXY20 MCHP_PINMUX(c, 1, p, periph)
+
+/* pc1p_ptc_drv20 */
+#define PC1P_PTC_DRV20 MCHP_PINMUX(c, 1, p, periph)
+
+/* pc1pdmo_lv_test_pdm_pdmo5 */
+#define PC1PDMO_LV_TEST_PDM_PDMO5 MCHP_PINMUX(c, 1, pdmo_lv_test, periph)
+
+/* pc1pdmo_mv_test_pdm_pdmo5_mv */
+#define PC1PDMO_MV_TEST_PDM_PDMO5_MV MCHP_PINMUX(c, 1, pdmo_mv_test, periph)
+
+/* pc1valio_testval_valio4 */
+#define PC1VALIO_TESTVAL_VALIO4 MCHP_PINMUX(c, 1, valio, periph)
+
+/* pc2_gpio */
+#define PC2_GPIO MCHP_PINMUX(c, 2, gpio, gpio)
+
+/* pc2a_eic_extint2 */
+#define PC2A_EIC_EXTINT2 MCHP_PINMUX(c, 2, a, periph)
+
+/* pc2d_sercom0_pad2 */
+#define PC2D_SERCOM0_PAD2 MCHP_PINMUX(c, 2, d, periph)
+
+/* pc2f_tcc1_wo0 */
+#define PC2F_TCC1_WO0 MCHP_PINMUX(c, 2, f, periph)
+
+/* pc2h_can0_tx */
+#define PC2H_CAN0_TX MCHP_PINMUX(c, 2, h, periph)
+
+/* pc2i_ccl0_in1 */
+#define PC2I_CCL0_IN1 MCHP_PINMUX(c, 2, i, periph)
+
+/* pc2k_gclk_io3 */
+#define PC2K_GCLK_IO3 MCHP_PINMUX(c, 2, k, periph)
+
+/* pc2p_ptc_ptcxy21 */
+#define PC2P_PTC_PTCXY21 MCHP_PINMUX(c, 2, p, periph)
+
+/* pc2p_ptc_drv21 */
+#define PC2P_PTC_DRV21 MCHP_PINMUX(c, 2, p, periph)
+
+/* pc2pdmo_lv_test_pdm_pdmo6 */
+#define PC2PDMO_LV_TEST_PDM_PDMO6 MCHP_PINMUX(c, 2, pdmo_lv_test, periph)
+
+/* pc2pdmo_mv_test_pdm_pdmo6_mv */
+#define PC2PDMO_MV_TEST_PDM_PDMO6_MV MCHP_PINMUX(c, 2, pdmo_mv_test, periph)
+
+/* pc2valio_testval_valio5 */
+#define PC2VALIO_TESTVAL_VALIO5 MCHP_PINMUX(c, 2, valio, periph)
+
+/* pc3_gpio */
+#define PC3_GPIO MCHP_PINMUX(c, 3, gpio, gpio)
+
+/* pc3a_eic_extint3 */
+#define PC3A_EIC_EXTINT3 MCHP_PINMUX(c, 3, a, periph)
+
+/* pc3d_sercom0_pad3 */
+#define PC3D_SERCOM0_PAD3 MCHP_PINMUX(c, 3, d, periph)
+
+/* pc3f_tcc1_wo1 */
+#define PC3F_TCC1_WO1 MCHP_PINMUX(c, 3, f, periph)
+
+/* pc3i_ccl0_out0 */
+#define PC3I_CCL0_OUT0 MCHP_PINMUX(c, 3, i, periph)
+
+/* pc3k_gclk_io4 */
+#define PC3K_GCLK_IO4 MCHP_PINMUX(c, 3, k, periph)
+
+/* pc3p_ptc_eci0 */
+#define PC3P_PTC_ECI0 MCHP_PINMUX(c, 3, p, periph)
+
+/* pc3pdmo_lv_test_pdm_pdmo7 */
+#define PC3PDMO_LV_TEST_PDM_PDMO7 MCHP_PINMUX(c, 3, pdmo_lv_test, periph)
+
+/* pc3pdmo_mv_test_pdm_pdmo7_mv */
+#define PC3PDMO_MV_TEST_PDM_PDMO7_MV MCHP_PINMUX(c, 3, pdmo_mv_test, periph)
+
+/* pc4_gpio */
+#define PC4_GPIO MCHP_PINMUX(c, 4, gpio, gpio)
+
+/* pc4a_eic_extint4 */
+#define PC4A_EIC_EXTINT4 MCHP_PINMUX(c, 4, a, periph)
+
+/* pc4d_sercom2_pad0 */
+#define PC4D_SERCOM2_PAD0 MCHP_PINMUX(c, 4, d, periph)
+
+/* pc4f_tcc2_wo0 */
+#define PC4F_TCC2_WO0 MCHP_PINMUX(c, 4, f, periph)
+
+/* pc4i_ccl1_in0 */
+#define PC4I_CCL1_IN0 MCHP_PINMUX(c, 4, i, periph)
+
+/* pc4k_gclk_io5 */
+#define PC4K_GCLK_IO5 MCHP_PINMUX(c, 4, k, periph)
+
+/* pc4p_ptc_eci1 */
+#define PC4P_PTC_ECI1 MCHP_PINMUX(c, 4, p, periph)
+
+/* pc4valio_testval_valio2 */
+#define PC4VALIO_TESTVAL_VALIO2 MCHP_PINMUX(c, 4, valio, periph)
+
+/* pc5_gpio */
+#define PC5_GPIO MCHP_PINMUX(c, 5, gpio, gpio)
+
+/* pc5a_eic_extint5 */
+#define PC5A_EIC_EXTINT5 MCHP_PINMUX(c, 5, a, periph)
+
+/* pc5d_sercom1_pad3 */
+#define PC5D_SERCOM1_PAD3 MCHP_PINMUX(c, 5, d, periph)
+
+/* pc5dsu_msa_dsu_msa */
+#define PC5DSU_MSA_DSU_MSA MCHP_PINMUX(c, 5, dsu_msa, periph)
+
+/* pc5f_tcc2_wo1 */
+#define PC5F_TCC2_WO1 MCHP_PINMUX(c, 5, f, periph)
+
+/* pc5h_can1_rx */
+#define PC5H_CAN1_RX MCHP_PINMUX(c, 5, h, periph)
+
+/* pc5i_ccl1_in1 */
+#define PC5I_CCL1_IN1 MCHP_PINMUX(c, 5, i, periph)
+
+/* pc5k_gclk_io1 */
+#define PC5K_GCLK_IO1 MCHP_PINMUX(c, 5, k, periph)
+
+/* pc6_gpio */
+#define PC6_GPIO MCHP_PINMUX(c, 6, gpio, gpio)
+
+/* pc6a_eic_extint6 */
+#define PC6A_EIC_EXTINT6 MCHP_PINMUX(c, 6, a, periph)
+
+/* pc6d_sercom1_pad2 */
+#define PC6D_SERCOM1_PAD2 MCHP_PINMUX(c, 6, d, periph)
+
+/* pc6dsu_swccstat_dsu_swccstat */
+#define PC6DSU_SWCCSTAT_DSU_SWCCSTAT MCHP_PINMUX(c, 6, dsu_swccstat, periph)
+
+/* pc6h_can1_tx */
+#define PC6H_CAN1_TX MCHP_PINMUX(c, 6, h, periph)
+
+/* pc6i_ccl1_out0 */
+#define PC6I_CCL1_OUT0 MCHP_PINMUX(c, 6, i, periph)
+
+/* pc8_gpio */
+#define PC8_GPIO MCHP_PINMUX(c, 8, gpio, gpio)
+
+/* pc8dsu_test_gclk_gclk_tst_gclk */
+#define PC8DSU_TEST_GCLK_GCLK_TST_GCLK MCHP_PINMUX(c, 8, dsu_test_gclk, periph)
+
+/* pc9_gpio */
+#define PC9_GPIO MCHP_PINMUX(c, 9, gpio, gpio)
+
+/* pc9a_eic_extint9 */
+#define PC9A_EIC_EXTINT9 MCHP_PINMUX(c, 9, a, periph)
+
+/* pc9f_tcc1_wo0 */
+#define PC9F_TCC1_WO0 MCHP_PINMUX(c, 9, f, periph)
+
+/* pc9i_ccl0_in2 */
+#define PC9I_CCL0_IN2 MCHP_PINMUX(c, 9, i, periph)
+
+/* pc9k_gclk_io0 */
+#define PC9K_GCLK_IO0 MCHP_PINMUX(c, 9, k, periph)
+
+/* pc9p_ptc_ptcxy30 */
+#define PC9P_PTC_PTCXY30 MCHP_PINMUX(c, 9, p, periph)
+
+/* pc9p_ptc_drv30 */
+#define PC9P_PTC_DRV30 MCHP_PINMUX(c, 9, p, periph)
+
+/* pc10_gpio */
+#define PC10_GPIO MCHP_PINMUX(c, 10, gpio, gpio)
+
+/* pc10a_eic_extint10 */
+#define PC10A_EIC_EXTINT10 MCHP_PINMUX(c, 10, a, periph)
+
+/* pc10f_tcc1_wo1 */
+#define PC10F_TCC1_WO1 MCHP_PINMUX(c, 10, f, periph)
+
+/* pc10i_ccl1_in2 */
+#define PC10I_CCL1_IN2 MCHP_PINMUX(c, 10, i, periph)
+
+/* pc10k_gclk_io1 */
+#define PC10K_GCLK_IO1 MCHP_PINMUX(c, 10, k, periph)
+
+/* pc10p_ptc_ptcxy31 */
+#define PC10P_PTC_PTCXY31 MCHP_PINMUX(c, 10, p, periph)
+
+/* pc10p_ptc_drv31 */
+#define PC10P_PTC_DRV31 MCHP_PINMUX(c, 10, p, periph)
+
+/* pd0_gpio */
+#define PD0_GPIO MCHP_PINMUX(d, 0, gpio, gpio)
+
+/* pd0a_eic_nmi */
+#define PD0A_EIC_NMI MCHP_PINMUX(d, 0, a, periph)
+
+/* pd0d_sercom1_pad1 */
+#define PD0D_SERCOM1_PAD1 MCHP_PINMUX(d, 0, d, periph)
+
+/* pd0f_tcc3_wo0 */
+#define PD0F_TCC3_WO0 MCHP_PINMUX(d, 0, f, periph)
+
+/* pd0i_ccl0_in3 */
+#define PD0I_CCL0_IN3 MCHP_PINMUX(d, 0, i, periph)
+
+/* pd0valio_testval_valio0 */
+#define PD0VALIO_TESTVAL_VALIO0 MCHP_PINMUX(d, 0, valio, periph)
+
+/* pd1_gpio */
+#define PD1_GPIO MCHP_PINMUX(d, 1, gpio, gpio)
+
+/* pd1a_eic_extint1 */
+#define PD1A_EIC_EXTINT1 MCHP_PINMUX(d, 1, a, periph)
+
+/* pd1d_sercom1_pad0 */
+#define PD1D_SERCOM1_PAD0 MCHP_PINMUX(d, 1, d, periph)
+
+/* pd1f_tcc3_wo1 */
+#define PD1F_TCC3_WO1 MCHP_PINMUX(d, 1, f, periph)
+
+/* pd1h_usb_sof */
+#define PD1H_USB_SOF MCHP_PINMUX(d, 1, h, periph)
+
+/* pd1i_ccl0_in4 */
+#define PD1I_CCL0_IN4 MCHP_PINMUX(d, 1, i, periph)
+
+/* pd1valio_testval_valio1 */
+#define PD1VALIO_TESTVAL_VALIO1 MCHP_PINMUX(d, 1, valio, periph)
+
+/* pd2_gpio */
+#define PD2_GPIO MCHP_PINMUX(d, 2, gpio, gpio)
+
+/* pd2h_usb_usbdm */
+#define PD2H_USB_USBDM MCHP_PINMUX(d, 2, h, periph)
+
+/* pd3_gpio */
+#define PD3_GPIO MCHP_PINMUX(d, 3, gpio, gpio)
+
+/* pd3h_usb_usbdp */
+#define PD3H_USB_USBDP MCHP_PINMUX(d, 3, h, periph)
+
+/* pd4_gpio */
+#define PD4_GPIO MCHP_PINMUX(d, 4, gpio, gpio)
+
+/* pd4a_eic_extint2 */
+#define PD4A_EIC_EXTINT2 MCHP_PINMUX(d, 4, a, periph)
+
+/* pd4k_gclk_io1 */
+#define PD4K_GCLK_IO1 MCHP_PINMUX(d, 4, k, periph)
+
+/* pd5_gpio */
+#define PD5_GPIO MCHP_PINMUX(d, 5, gpio, gpio)
+
+/* pd5a_eic_extint3 */
+#define PD5A_EIC_EXTINT3 MCHP_PINMUX(d, 5, a, periph)
+
+/* pd5k_gclk_io0 */
+#define PD5K_GCLK_IO0 MCHP_PINMUX(d, 5, k, periph)
+
+/* pd6_gpio */
+#define PD6_GPIO MCHP_PINMUX(d, 6, gpio, gpio)
+
+/* pd6d_sercom2_pad1 */
+#define PD6D_SERCOM2_PAD1 MCHP_PINMUX(d, 6, d, periph)
+
+/* pd6h_can0_rx */
+#define PD6H_CAN0_RX MCHP_PINMUX(d, 6, h, periph)
+
+/* pd6i_ccl1_in3 */
+#define PD6I_CCL1_IN3 MCHP_PINMUX(d, 6, i, periph)
+
+/* pd6p_ptc_ptcxy0 */
+#define PD6P_PTC_PTCXY0 MCHP_PINMUX(d, 6, p, periph)
+
+/* pd6p_ptc_drv0 */
+#define PD6P_PTC_DRV0 MCHP_PINMUX(d, 6, p, periph)
+
+/* pd7_gpio */
+#define PD7_GPIO MCHP_PINMUX(d, 7, gpio, gpio)
+
+/* pd7a_eic_extint4 */
+#define PD7A_EIC_EXTINT4 MCHP_PINMUX(d, 7, a, periph)
+
+/* pd7adc_test_pad_adc_res_test2 */
+#define PD7ADC_TEST_PAD_ADC_RES_TEST2 MCHP_PINMUX(d, 7, adc_test_pad, periph)
+
+/* pd7d_sercom2_pad2 */
+#define PD7D_SERCOM2_PAD2 MCHP_PINMUX(d, 7, d, periph)
+
+/* pd7f_tcc4_wo0 */
+#define PD7F_TCC4_WO0 MCHP_PINMUX(d, 7, f, periph)
+
+/* pd7i_ccl1_in4 */
+#define PD7I_CCL1_IN4 MCHP_PINMUX(d, 7, i, periph)
+
+/* pd7p_ptc_ptcxy1 */
+#define PD7P_PTC_PTCXY1 MCHP_PINMUX(d, 7, p, periph)
+
+/* pd7p_ptc_drv1 */
+#define PD7P_PTC_DRV1 MCHP_PINMUX(d, 7, p, periph)
+
+/* pd7pdmi_test_pdm_pdmi0 */
+#define PD7PDMI_TEST_PDM_PDMI0 MCHP_PINMUX(d, 7, pdmi_test, periph)
+
+/* pd8_gpio */
+#define PD8_GPIO MCHP_PINMUX(d, 8, gpio, gpio)
+
+/* pd8a_eic_extint5 */
+#define PD8A_EIC_EXTINT5 MCHP_PINMUX(d, 8, a, periph)
+
+/* pd8adc_test_pad_adc_res_test0 */
+#define PD8ADC_TEST_PAD_ADC_RES_TEST0 MCHP_PINMUX(d, 8, adc_test_pad, periph)
+
+/* pd8d_sercom2_pad3 */
+#define PD8D_SERCOM2_PAD3 MCHP_PINMUX(d, 8, d, periph)
+
+/* pd8f_tcc4_wo1 */
+#define PD8F_TCC4_WO1 MCHP_PINMUX(d, 8, f, periph)
+
+/* pd8h_can0_tx */
+#define PD8H_CAN0_TX MCHP_PINMUX(d, 8, h, periph)
+
+/* pd8i_ccl0_out1 */
+#define PD8I_CCL0_OUT1 MCHP_PINMUX(d, 8, i, periph)
+
+/* pd8p_ptc_ptcxy2 */
+#define PD8P_PTC_PTCXY2 MCHP_PINMUX(d, 8, p, periph)
+
+/* pd8p_ptc_drv2 */
+#define PD8P_PTC_DRV2 MCHP_PINMUX(d, 8, p, periph)
+
+/* pd8pdmi_test_pdm_pdmi1 */
+#define PD8PDMI_TEST_PDM_PDMI1 MCHP_PINMUX(d, 8, pdmi_test, periph)
+
+/* pd9_gpio */
+#define PD9_GPIO MCHP_PINMUX(d, 9, gpio, gpio)
+
+/* pd9a_eic_extint6 */
+#define PD9A_EIC_EXTINT6 MCHP_PINMUX(d, 9, a, periph)
+
+/* pd9adc_test_pad_adc_res_test1 */
+#define PD9ADC_TEST_PAD_ADC_RES_TEST1 MCHP_PINMUX(d, 9, adc_test_pad, periph)
+
+/* pd9d_sercom3_pad0 */
+#define PD9D_SERCOM3_PAD0 MCHP_PINMUX(d, 9, d, periph)
+
+/* pd9f_tcc5_wo0 */
+#define PD9F_TCC5_WO0 MCHP_PINMUX(d, 9, f, periph)
+
+/* pd9i_ccl1_out1 */
+#define PD9I_CCL1_OUT1 MCHP_PINMUX(d, 9, i, periph)
+
+/* pd9p_ptc_ptcxy3 */
+#define PD9P_PTC_PTCXY3 MCHP_PINMUX(d, 9, p, periph)
+
+/* pd9p_ptc_drv3 */
+#define PD9P_PTC_DRV3 MCHP_PINMUX(d, 9, p, periph)
+
+/* pd9pdmi_test_pdm_pdmi2 */
+#define PD9PDMI_TEST_PDM_PDMI2 MCHP_PINMUX(d, 9, pdmi_test, periph)
+
+/* pd10_gpio */
+#define PD10_GPIO MCHP_PINMUX(d, 10, gpio, gpio)
+
+/* pd10a_eic_extint8 */
+#define PD10A_EIC_EXTINT8 MCHP_PINMUX(d, 10, a, periph)
+
+/* pd10d_sercom1_pad2 */
+#define PD10D_SERCOM1_PAD2 MCHP_PINMUX(d, 10, d, periph)
+
+/* pd10f_tcc5_wo0 */
+#define PD10F_TCC5_WO0 MCHP_PINMUX(d, 10, f, periph)
+
+/* pd10i_ccl0_in5 */
+#define PD10I_CCL0_IN5 MCHP_PINMUX(d, 10, i, periph)
+
+/* pd11_gpio */
+#define PD11_GPIO MCHP_PINMUX(d, 11, gpio, gpio)
+
+/* pd11a_eic_extint9 */
+#define PD11A_EIC_EXTINT9 MCHP_PINMUX(d, 11, a, periph)
+
+/* pd11d_sercom1_pad3 */
+#define PD11D_SERCOM1_PAD3 MCHP_PINMUX(d, 11, d, periph)
+
+/* pd11f_tcc5_wo1 */
+#define PD11F_TCC5_WO1 MCHP_PINMUX(d, 11, f, periph)
+
+/* pd11i_ccl1_in5 */
+#define PD11I_CCL1_IN5 MCHP_PINMUX(d, 11, i, periph)
+
+/* pd12_gpio */
+#define PD12_GPIO MCHP_PINMUX(d, 12, gpio, gpio)
+
+/* pd12a_eic_extint10 */
+#define PD12A_EIC_EXTINT10 MCHP_PINMUX(d, 12, a, periph)
+
+/* pd12f_tcc6_wo0 */
+#define PD12F_TCC6_WO0 MCHP_PINMUX(d, 12, f, periph)
+
+/* pd12h_can1_rx */
+#define PD12H_CAN1_RX MCHP_PINMUX(d, 12, h, periph)
+
+/* pd12i_ccl1_in5 */
+#define PD12I_CCL1_IN5 MCHP_PINMUX(d, 12, i, periph)
+
+/* pd13_gpio */
+#define PD13_GPIO MCHP_PINMUX(d, 13, gpio, gpio)
+
+/* pd13a_eic_extint11 */
+#define PD13A_EIC_EXTINT11 MCHP_PINMUX(d, 13, a, periph)
+
+/* pd13f_tcc6_wo1 */
+#define PD13F_TCC6_WO1 MCHP_PINMUX(d, 13, f, periph)
+
+/* pd13h_can1_tx */
+#define PD13H_CAN1_TX MCHP_PINMUX(d, 13, h, periph)
+
+#endif /* MICROCHIP_PIC32CM5112GC00064_PINCTRL_H_ */
diff --git a/include/dt-bindings/pic32c/pic32cm_gc_sg/pic32cm_gc00/pic32cm5112gc00100-pinctrl.h b/include/dt-bindings/pic32c/pic32cm_gc_sg/pic32cm_gc00/pic32cm5112gc00100-pinctrl.h
new file mode 100644
index 00000000..f812f013
--- /dev/null
+++ b/include/dt-bindings/pic32c/pic32cm_gc_sg/pic32cm_gc00/pic32cm5112gc00100-pinctrl.h
@@ -0,0 +1,1415 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Autogenerated file
+ */
+
+#ifndef MICROCHIP_PIC32CM5112GC00100_PINCTRL_H_
+#define MICROCHIP_PIC32CM5112GC00100_PINCTRL_H_
+
+#include <dt-bindings/pic32c/pic32cm_gc_sg/common/mchp_pinctrl_pinmux_pic32c.h>
+
+/* pa0_gpio */
+#define PA0_GPIO MCHP_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 MCHP_PINMUX(a, 0, a, periph)
+
+/* pa0adc_test_pad_adc_res_test3 */
+#define PA0ADC_TEST_PAD_ADC_RES_TEST3 MCHP_PINMUX(a, 0, adc_test_pad, periph)
+
+/* pa0d_sercom3_pad1 */
+#define PA0D_SERCOM3_PAD1 MCHP_PINMUX(a, 0, d, periph)
+
+/* pa0f_tcc5_wo1 */
+#define PA0F_TCC5_WO1 MCHP_PINMUX(a, 0, f, periph)
+
+/* pa0h_can1_rx */
+#define PA0H_CAN1_RX MCHP_PINMUX(a, 0, h, periph)
+
+/* pa0i_ccl0_in6 */
+#define PA0I_CCL0_IN6 MCHP_PINMUX(a, 0, i, periph)
+
+/* pa0p_ptc_ptcxy4 */
+#define PA0P_PTC_PTCXY4 MCHP_PINMUX(a, 0, p, periph)
+
+/* pa0p_ptc_drv4 */
+#define PA0P_PTC_DRV4 MCHP_PINMUX(a, 0, p, periph)
+
+/* pa0pdmi_test_pdm_pdmi3 */
+#define PA0PDMI_TEST_PDM_PDMI3 MCHP_PINMUX(a, 0, pdmi_test, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO MCHP_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 MCHP_PINMUX(a, 1, a, periph)
+
+/* pa1adc_test_pad_adc_res_test4 */
+#define PA1ADC_TEST_PAD_ADC_RES_TEST4 MCHP_PINMUX(a, 1, adc_test_pad, periph)
+
+/* pa1b_ac_cmp0 */
+#define PA1B_AC_CMP0 MCHP_PINMUX(a, 1, b, periph)
+
+/* pa1d_sercom3_pad2 */
+#define PA1D_SERCOM3_PAD2 MCHP_PINMUX(a, 1, d, periph)
+
+/* pa1f_tcc6_wo0 */
+#define PA1F_TCC6_WO0 MCHP_PINMUX(a, 1, f, periph)
+
+/* pa1h_can1_tx */
+#define PA1H_CAN1_TX MCHP_PINMUX(a, 1, h, periph)
+
+/* pa1i_ccl0_in7 */
+#define PA1I_CCL0_IN7 MCHP_PINMUX(a, 1, i, periph)
+
+/* pa1p_ptc_ptcxy5 */
+#define PA1P_PTC_PTCXY5 MCHP_PINMUX(a, 1, p, periph)
+
+/* pa1p_ptc_drv5 */
+#define PA1P_PTC_DRV5 MCHP_PINMUX(a, 1, p, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO MCHP_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 MCHP_PINMUX(a, 2, a, periph)
+
+/* pa2adc_test_pad_adc_res_test5 */
+#define PA2ADC_TEST_PAD_ADC_RES_TEST5 MCHP_PINMUX(a, 2, adc_test_pad, periph)
+
+/* pa2b_ac_cmp1 */
+#define PA2B_AC_CMP1 MCHP_PINMUX(a, 2, b, periph)
+
+/* pa2d_sercom3_pad3 */
+#define PA2D_SERCOM3_PAD3 MCHP_PINMUX(a, 2, d, periph)
+
+/* pa2f_tcc6_wo1 */
+#define PA2F_TCC6_WO1 MCHP_PINMUX(a, 2, f, periph)
+
+/* pa2i_ccl0_out2 */
+#define PA2I_CCL0_OUT2 MCHP_PINMUX(a, 2, i, periph)
+
+/* pa2p_ptc_ptcxy6 */
+#define PA2P_PTC_PTCXY6 MCHP_PINMUX(a, 2, p, periph)
+
+/* pa2p_ptc_drv6 */
+#define PA2P_PTC_DRV6 MCHP_PINMUX(a, 2, p, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO MCHP_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 MCHP_PINMUX(a, 3, a, periph)
+
+/* pa3adc_test_pad_adc_res_test6 */
+#define PA3ADC_TEST_PAD_ADC_RES_TEST6 MCHP_PINMUX(a, 3, adc_test_pad, periph)
+
+/* pa3b_adc_adc0_ain0 */
+#define PA3B_ADC_ADC0_AIN0 MCHP_PINMUX(a, 3, b, periph)
+
+/* pa3d_sercom4_pad0 */
+#define PA3D_SERCOM4_PAD0 MCHP_PINMUX(a, 3, d, periph)
+
+/* pa3p_ptc_ptcxy7 */
+#define PA3P_PTC_PTCXY7 MCHP_PINMUX(a, 3, p, periph)
+
+/* pa3p_ptc_drv7 */
+#define PA3P_PTC_DRV7 MCHP_PINMUX(a, 3, p, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO MCHP_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 MCHP_PINMUX(a, 4, a, periph)
+
+/* pa4adc_test_pad_adc_res_test7 */
+#define PA4ADC_TEST_PAD_ADC_RES_TEST7 MCHP_PINMUX(a, 4, adc_test_pad, periph)
+
+/* pa4b_adc_adc0_ain1 */
+#define PA4B_ADC_ADC0_AIN1 MCHP_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc_adc0_ann0 */
+#define PA4B_ADC_ADC0_ANN0 MCHP_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom4_pad1 */
+#define PA4D_SERCOM4_PAD1 MCHP_PINMUX(a, 4, d, periph)
+
+/* pa4p_ptc_ptcxy8 */
+#define PA4P_PTC_PTCXY8 MCHP_PINMUX(a, 4, p, periph)
+
+/* pa4p_ptc_drv8 */
+#define PA4P_PTC_DRV8 MCHP_PINMUX(a, 4, p, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO MCHP_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 MCHP_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc_adc0_ain2 */
+#define PA5B_ADC_ADC0_AIN2 MCHP_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom4_pad2 */
+#define PA5D_SERCOM4_PAD2 MCHP_PINMUX(a, 5, d, periph)
+
+/* pa5i_ccl1_out2 */
+#define PA5I_CCL1_OUT2 MCHP_PINMUX(a, 5, i, periph)
+
+/* pa5p_ptc_ptcxy9 */
+#define PA5P_PTC_PTCXY9 MCHP_PINMUX(a, 5, p, periph)
+
+/* pa5p_ptc_drv9 */
+#define PA5P_PTC_DRV9 MCHP_PINMUX(a, 5, p, periph)
+
+/* pa5valio_testval_valio3 */
+#define PA5VALIO_TESTVAL_VALIO3 MCHP_PINMUX(a, 5, valio, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO MCHP_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 MCHP_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc_adc0_ain3 */
+#define PA6B_ADC_ADC0_AIN3 MCHP_PINMUX(a, 6, b, periph)
+
+/* pa6b_adc_adc0_ann2 */
+#define PA6B_ADC_ADC0_ANN2 MCHP_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom4_pad3 */
+#define PA6D_SERCOM4_PAD3 MCHP_PINMUX(a, 6, d, periph)
+
+/* pa6i_ccl1_in7 */
+#define PA6I_CCL1_IN7 MCHP_PINMUX(a, 6, i, periph)
+
+/* pa6p_ptc_ptcxy10 */
+#define PA6P_PTC_PTCXY10 MCHP_PINMUX(a, 6, p, periph)
+
+/* pa6p_ptc_drv10 */
+#define PA6P_PTC_DRV10 MCHP_PINMUX(a, 6, p, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO MCHP_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 MCHP_PINMUX(a, 7, a, periph)
+
+/* pa7b_ac_ain0 */
+#define PA7B_AC_AIN0 MCHP_PINMUX(a, 7, b, periph)
+
+/* pa7b_adc_adc0_ain4 */
+#define PA7B_ADC_ADC0_AIN4 MCHP_PINMUX(a, 7, b, periph)
+
+/* pa7p_ptc_ptcxy11 */
+#define PA7P_PTC_PTCXY11 MCHP_PINMUX(a, 7, p, periph)
+
+/* pa7p_ptc_drv11 */
+#define PA7P_PTC_DRV11 MCHP_PINMUX(a, 7, p, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO MCHP_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_extint8 */
+#define PA8A_EIC_EXTINT8 MCHP_PINMUX(a, 8, a, periph)
+
+/* pa8b_ac_ain1 */
+#define PA8B_AC_AIN1 MCHP_PINMUX(a, 8, b, periph)
+
+/* pa8b_adc_adc0_ain5 */
+#define PA8B_ADC_ADC0_AIN5 MCHP_PINMUX(a, 8, b, periph)
+
+/* pa8b_adc_adc0_ann4 */
+#define PA8B_ADC_ADC0_ANN4 MCHP_PINMUX(a, 8, b, periph)
+
+/* pa8p_ptc_ptcxy12 */
+#define PA8P_PTC_PTCXY12 MCHP_PINMUX(a, 8, p, periph)
+
+/* pa8p_ptc_drv12 */
+#define PA8P_PTC_DRV12 MCHP_PINMUX(a, 8, p, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO MCHP_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 MCHP_PINMUX(a, 9, a, periph)
+
+/* pa9b_adc_adc0_ain6 */
+#define PA9B_ADC_ADC0_AIN6 MCHP_PINMUX(a, 9, b, periph)
+
+/* pa9i_ccl1_in6 */
+#define PA9I_CCL1_IN6 MCHP_PINMUX(a, 9, i, periph)
+
+/* pa9p_ptc_ptcxy13 */
+#define PA9P_PTC_PTCXY13 MCHP_PINMUX(a, 9, p, periph)
+
+/* pa9p_ptc_drv13 */
+#define PA9P_PTC_DRV13 MCHP_PINMUX(a, 9, p, periph)
+
+/* pa9volt_ref_adc_vrefh */
+#define PA9VOLT_REF_ADC_VREFH MCHP_PINMUX(a, 9, volt_ref, periph)
+
+/* pa10_gpio */
+#define PA10_GPIO MCHP_PINMUX(a, 10, gpio, gpio)
+
+/* pa10a_eic_extint10 */
+#define PA10A_EIC_EXTINT10 MCHP_PINMUX(a, 10, a, periph)
+
+/* pa10f_tcc4_wo0 */
+#define PA10F_TCC4_WO0 MCHP_PINMUX(a, 10, f, periph)
+
+/* pa10h_can0_rx */
+#define PA10H_CAN0_RX MCHP_PINMUX(a, 10, h, periph)
+
+/* pa10i_ccl0_in8 */
+#define PA10I_CCL0_IN8 MCHP_PINMUX(a, 10, i, periph)
+
+/* pa10p_ptc_ptcxy22 */
+#define PA10P_PTC_PTCXY22 MCHP_PINMUX(a, 10, p, periph)
+
+/* pa10p_ptc_drv22 */
+#define PA10P_PTC_DRV22 MCHP_PINMUX(a, 10, p, periph)
+
+/* pa11_gpio */
+#define PA11_GPIO MCHP_PINMUX(a, 11, gpio, gpio)
+
+/* pa11a_eic_extint11 */
+#define PA11A_EIC_EXTINT11 MCHP_PINMUX(a, 11, a, periph)
+
+/* pa11f_tcc4_wo1 */
+#define PA11F_TCC4_WO1 MCHP_PINMUX(a, 11, f, periph)
+
+/* pa11h_can0_tx */
+#define PA11H_CAN0_TX MCHP_PINMUX(a, 11, h, periph)
+
+/* pa11i_ccl1_in8 */
+#define PA11I_CCL1_IN8 MCHP_PINMUX(a, 11, i, periph)
+
+/* pa11p_ptc_ptcxy23 */
+#define PA11P_PTC_PTCXY23 MCHP_PINMUX(a, 11, p, periph)
+
+/* pa11p_ptc_drv23 */
+#define PA11P_PTC_DRV23 MCHP_PINMUX(a, 11, p, periph)
+
+/* pa12_gpio */
+#define PA12_GPIO MCHP_PINMUX(a, 12, gpio, gpio)
+
+/* pa12a_eic_extint12 */
+#define PA12A_EIC_EXTINT12 MCHP_PINMUX(a, 12, a, periph)
+
+/* pa12i_ccl1_in8 */
+#define PA12I_CCL1_IN8 MCHP_PINMUX(a, 12, i, periph)
+
+/* pa12p_ptc_ptcxy24 */
+#define PA12P_PTC_PTCXY24 MCHP_PINMUX(a, 12, p, periph)
+
+/* pa12p_ptc_drv24 */
+#define PA12P_PTC_DRV24 MCHP_PINMUX(a, 12, p, periph)
+
+/* pa13_gpio */
+#define PA13_GPIO MCHP_PINMUX(a, 13, gpio, gpio)
+
+/* pa13a_eic_extint13 */
+#define PA13A_EIC_EXTINT13 MCHP_PINMUX(a, 13, a, periph)
+
+/* pa13b_ac_cmp0 */
+#define PA13B_AC_CMP0 MCHP_PINMUX(a, 13, b, periph)
+
+/* pa13p_ptc_ptcxy25 */
+#define PA13P_PTC_PTCXY25 MCHP_PINMUX(a, 13, p, periph)
+
+/* pa13p_ptc_drv25 */
+#define PA13P_PTC_DRV25 MCHP_PINMUX(a, 13, p, periph)
+
+/* pa14_gpio */
+#define PA14_GPIO MCHP_PINMUX(a, 14, gpio, gpio)
+
+/* pa14a_eic_extint14 */
+#define PA14A_EIC_EXTINT14 MCHP_PINMUX(a, 14, a, periph)
+
+/* pa14d_sercom4_pad3 */
+#define PA14D_SERCOM4_PAD3 MCHP_PINMUX(a, 14, d, periph)
+
+/* pa14i_ccl0_in6 */
+#define PA14I_CCL0_IN6 MCHP_PINMUX(a, 14, i, periph)
+
+/* pa14p_ptc_ptcxy32 */
+#define PA14P_PTC_PTCXY32 MCHP_PINMUX(a, 14, p, periph)
+
+/* pa14p_ptc_drv32 */
+#define PA14P_PTC_DRV32 MCHP_PINMUX(a, 14, p, periph)
+
+/* pa15_gpio */
+#define PA15_GPIO MCHP_PINMUX(a, 15, gpio, gpio)
+
+/* pa15a_eic_extint15 */
+#define PA15A_EIC_EXTINT15 MCHP_PINMUX(a, 15, a, periph)
+
+/* pa15d_sercom5_pad3 */
+#define PA15D_SERCOM5_PAD3 MCHP_PINMUX(a, 15, d, periph)
+
+/* pa15i_ccl0_in7 */
+#define PA15I_CCL0_IN7 MCHP_PINMUX(a, 15, i, periph)
+
+/* pa15p_ptc_ptcxy33 */
+#define PA15P_PTC_PTCXY33 MCHP_PINMUX(a, 15, p, periph)
+
+/* pa15p_ptc_drv33 */
+#define PA15P_PTC_DRV33 MCHP_PINMUX(a, 15, p, periph)
+
+/* pa16_gpio */
+#define PA16_GPIO MCHP_PINMUX(a, 16, gpio, gpio)
+
+/* pa16a_eic_extint0 */
+#define PA16A_EIC_EXTINT0 MCHP_PINMUX(a, 16, a, periph)
+
+/* pa16d_sercom5_pad0 */
+#define PA16D_SERCOM5_PAD0 MCHP_PINMUX(a, 16, d, periph)
+
+/* pa16i_ccl1_in6 */
+#define PA16I_CCL1_IN6 MCHP_PINMUX(a, 16, i, periph)
+
+/* pa16p_ptc_ptcxy34 */
+#define PA16P_PTC_PTCXY34 MCHP_PINMUX(a, 16, p, periph)
+
+/* pa16p_ptc_drv34 */
+#define PA16P_PTC_DRV34 MCHP_PINMUX(a, 16, p, periph)
+
+/* pa17_gpio */
+#define PA17_GPIO MCHP_PINMUX(a, 17, gpio, gpio)
+
+/* pa17a_eic_extint1 */
+#define PA17A_EIC_EXTINT1 MCHP_PINMUX(a, 17, a, periph)
+
+/* pa17d_sercom5_pad1 */
+#define PA17D_SERCOM5_PAD1 MCHP_PINMUX(a, 17, d, periph)
+
+/* pa17i_ccl1_in7 */
+#define PA17I_CCL1_IN7 MCHP_PINMUX(a, 17, i, periph)
+
+/* pa17p_ptc_ptcxy35 */
+#define PA17P_PTC_PTCXY35 MCHP_PINMUX(a, 17, p, periph)
+
+/* pa17p_ptc_drv35 */
+#define PA17P_PTC_DRV35 MCHP_PINMUX(a, 17, p, periph)
+
+/* pa18_gpio */
+#define PA18_GPIO MCHP_PINMUX(a, 18, gpio, gpio)
+
+/* pa18a_eic_extint2 */
+#define PA18A_EIC_EXTINT2 MCHP_PINMUX(a, 18, a, periph)
+
+/* pa18d_sercom5_pad2 */
+#define PA18D_SERCOM5_PAD2 MCHP_PINMUX(a, 18, d, periph)
+
+/* pa18i_ccl0_in8 */
+#define PA18I_CCL0_IN8 MCHP_PINMUX(a, 18, i, periph)
+
+/* pa19_gpio */
+#define PA19_GPIO MCHP_PINMUX(a, 19, gpio, gpio)
+
+/* pa19a_eic_extint3 */
+#define PA19A_EIC_EXTINT3 MCHP_PINMUX(a, 19, a, periph)
+
+/* pa19f_tcc0_wo0 */
+#define PA19F_TCC0_WO0 MCHP_PINMUX(a, 19, f, periph)
+
+/* pa19i_ccl0_out2 */
+#define PA19I_CCL0_OUT2 MCHP_PINMUX(a, 19, i, periph)
+
+/* pa20_gpio */
+#define PA20_GPIO MCHP_PINMUX(a, 20, gpio, gpio)
+
+/* pa20a_eic_extint4 */
+#define PA20A_EIC_EXTINT4 MCHP_PINMUX(a, 20, a, periph)
+
+/* pa20f_tcc0_wo1 */
+#define PA20F_TCC0_WO1 MCHP_PINMUX(a, 20, f, periph)
+
+/* pa20i_ccl1_out2 */
+#define PA20I_CCL1_OUT2 MCHP_PINMUX(a, 20, i, periph)
+
+/* pb0_gpio */
+#define PB0_GPIO MCHP_PINMUX(b, 0, gpio, gpio)
+
+/* pb0a_eic_extint0 */
+#define PB0A_EIC_EXTINT0 MCHP_PINMUX(b, 0, a, periph)
+
+/* pb0b_ac_ain2 */
+#define PB0B_AC_AIN2 MCHP_PINMUX(b, 0, b, periph)
+
+/* pb0b_adc_adc0_ain7 */
+#define PB0B_ADC_ADC0_AIN7 MCHP_PINMUX(b, 0, b, periph)
+
+/* pb0i_ccl1_out3 */
+#define PB0I_CCL1_OUT3 MCHP_PINMUX(b, 0, i, periph)
+
+/* pb0p_ptc_ptcxy14 */
+#define PB0P_PTC_PTCXY14 MCHP_PINMUX(b, 0, p, periph)
+
+/* pb0p_ptc_drv14 */
+#define PB0P_PTC_DRV14 MCHP_PINMUX(b, 0, p, periph)
+
+/* pb1_gpio */
+#define PB1_GPIO MCHP_PINMUX(b, 1, gpio, gpio)
+
+/* pb1a_eic_extint1 */
+#define PB1A_EIC_EXTINT1 MCHP_PINMUX(b, 1, a, periph)
+
+/* pb2_gpio */
+#define PB2_GPIO MCHP_PINMUX(b, 2, gpio, gpio)
+
+/* pb2a_eic_extint2 */
+#define PB2A_EIC_EXTINT2 MCHP_PINMUX(b, 2, a, periph)
+
+/* pb3_gpio */
+#define PB3_GPIO MCHP_PINMUX(b, 3, gpio, gpio)
+
+/* pb3a_eic_extint3 */
+#define PB3A_EIC_EXTINT3 MCHP_PINMUX(b, 3, a, periph)
+
+/* pb3adc_test_pad_adc_res_test8 */
+#define PB3ADC_TEST_PAD_ADC_RES_TEST8 MCHP_PINMUX(b, 3, adc_test_pad, periph)
+
+/* pb3b_ac_ain3 */
+#define PB3B_AC_AIN3 MCHP_PINMUX(b, 3, b, periph)
+
+/* pb3b_adc_adc0_ain8 */
+#define PB3B_ADC_ADC0_AIN8 MCHP_PINMUX(b, 3, b, periph)
+
+/* pb3d_sercom5_pad0 */
+#define PB3D_SERCOM5_PAD0 MCHP_PINMUX(b, 3, d, periph)
+
+/* pb3i_ccl1_in10 */
+#define PB3I_CCL1_IN10 MCHP_PINMUX(b, 3, i, periph)
+
+/* pb3p_ptc_ptcxy15 */
+#define PB3P_PTC_PTCXY15 MCHP_PINMUX(b, 3, p, periph)
+
+/* pb3p_ptc_drv15 */
+#define PB3P_PTC_DRV15 MCHP_PINMUX(b, 3, p, periph)
+
+/* pb3pdmo_lv_test_pdm_pdmo0 */
+#define PB3PDMO_LV_TEST_PDM_PDMO0 MCHP_PINMUX(b, 3, pdmo_lv_test, periph)
+
+/* pb3pdmo_mv_test_pdm_pdmo0_mv */
+#define PB3PDMO_MV_TEST_PDM_PDMO0_MV MCHP_PINMUX(b, 3, pdmo_mv_test, periph)
+
+/* pb4_gpio */
+#define PB4_GPIO MCHP_PINMUX(b, 4, gpio, gpio)
+
+/* pb4a_eic_extint4 */
+#define PB4A_EIC_EXTINT4 MCHP_PINMUX(b, 4, a, periph)
+
+/* pb4adc_test_pad_adc_res_test9 */
+#define PB4ADC_TEST_PAD_ADC_RES_TEST9 MCHP_PINMUX(b, 4, adc_test_pad, periph)
+
+/* pb4b_adc_adc0_ain9 */
+#define PB4B_ADC_ADC0_AIN9 MCHP_PINMUX(b, 4, b, periph)
+
+/* pb4d_sercom5_pad1 */
+#define PB4D_SERCOM5_PAD1 MCHP_PINMUX(b, 4, d, periph)
+
+/* pb4i_ccl1_in9 */
+#define PB4I_CCL1_IN9 MCHP_PINMUX(b, 4, i, periph)
+
+/* pb4p_ptc_ptcxy16 */
+#define PB4P_PTC_PTCXY16 MCHP_PINMUX(b, 4, p, periph)
+
+/* pb4p_ptc_drv16 */
+#define PB4P_PTC_DRV16 MCHP_PINMUX(b, 4, p, periph)
+
+/* pb4pdmo_lv_test_pdm_pdmo1 */
+#define PB4PDMO_LV_TEST_PDM_PDMO1 MCHP_PINMUX(b, 4, pdmo_lv_test, periph)
+
+/* pb4pdmo_mv_test_pdm_pdmo1_mv */
+#define PB4PDMO_MV_TEST_PDM_PDMO1_MV MCHP_PINMUX(b, 4, pdmo_mv_test, periph)
+
+/* pb5_gpio */
+#define PB5_GPIO MCHP_PINMUX(b, 5, gpio, gpio)
+
+/* pb5a_eic_extint5 */
+#define PB5A_EIC_EXTINT5 MCHP_PINMUX(b, 5, a, periph)
+
+/* pb5adc_test_pad_adc_res_test10 */
+#define PB5ADC_TEST_PAD_ADC_RES_TEST10 MCHP_PINMUX(b, 5, adc_test_pad, periph)
+
+/* pb5b_adc_adc0_ain10 */
+#define PB5B_ADC_ADC0_AIN10 MCHP_PINMUX(b, 5, b, periph)
+
+/* pb5d_sercom5_pad2 */
+#define PB5D_SERCOM5_PAD2 MCHP_PINMUX(b, 5, d, periph)
+
+/* pb5i_ccl0_in9 */
+#define PB5I_CCL0_IN9 MCHP_PINMUX(b, 5, i, periph)
+
+/* pb5p_ptc_ptcxy17 */
+#define PB5P_PTC_PTCXY17 MCHP_PINMUX(b, 5, p, periph)
+
+/* pb5p_ptc_drv17 */
+#define PB5P_PTC_DRV17 MCHP_PINMUX(b, 5, p, periph)
+
+/* pb5pdmo_lv_test_pdm_pdmo2 */
+#define PB5PDMO_LV_TEST_PDM_PDMO2 MCHP_PINMUX(b, 5, pdmo_lv_test, periph)
+
+/* pb5pdmo_mv_test_pdm_pdmo2_mv */
+#define PB5PDMO_MV_TEST_PDM_PDMO2_MV MCHP_PINMUX(b, 5, pdmo_mv_test, periph)
+
+/* pb6_gpio */
+#define PB6_GPIO MCHP_PINMUX(b, 6, gpio, gpio)
+
+/* pb6a_eic_extint6 */
+#define PB6A_EIC_EXTINT6 MCHP_PINMUX(b, 6, a, periph)
+
+/* pb6adc_test_pad_adc_res_test11 */
+#define PB6ADC_TEST_PAD_ADC_RES_TEST11 MCHP_PINMUX(b, 6, adc_test_pad, periph)
+
+/* pb6b_adc_adc0_ain11 */
+#define PB6B_ADC_ADC0_AIN11 MCHP_PINMUX(b, 6, b, periph)
+
+/* pb6d_sercom5_pad3 */
+#define PB6D_SERCOM5_PAD3 MCHP_PINMUX(b, 6, d, periph)
+
+/* pb6i_ccl0_in10 */
+#define PB6I_CCL0_IN10 MCHP_PINMUX(b, 6, i, periph)
+
+/* pb6k_gclk_io0 */
+#define PB6K_GCLK_IO0 MCHP_PINMUX(b, 6, k, periph)
+
+/* pb6p_ptc_ptcxy18 */
+#define PB6P_PTC_PTCXY18 MCHP_PINMUX(b, 6, p, periph)
+
+/* pb6p_ptc_drv18 */
+#define PB6P_PTC_DRV18 MCHP_PINMUX(b, 6, p, periph)
+
+/* pb6pdmo_lv_test_pdm_pdmo3 */
+#define PB6PDMO_LV_TEST_PDM_PDMO3 MCHP_PINMUX(b, 6, pdmo_lv_test, periph)
+
+/* pb6pdmo_mv_test_pdm_pdmo3_mv */
+#define PB6PDMO_MV_TEST_PDM_PDMO3_MV MCHP_PINMUX(b, 6, pdmo_mv_test, periph)
+
+/* pb7_gpio */
+#define PB7_GPIO MCHP_PINMUX(b, 7, gpio, gpio)
+
+/* pb7a_eic_extint8 */
+#define PB7A_EIC_EXTINT8 MCHP_PINMUX(b, 7, a, periph)
+
+/* pb7b_ac_cmp1 */
+#define PB7B_AC_CMP1 MCHP_PINMUX(b, 7, b, periph)
+
+/* pb7i_ccl1_in11 */
+#define PB7I_CCL1_IN11 MCHP_PINMUX(b, 7, i, periph)
+
+/* pb7p_ptc_ptcxy26 */
+#define PB7P_PTC_PTCXY26 MCHP_PINMUX(b, 7, p, periph)
+
+/* pb7p_ptc_drv26 */
+#define PB7P_PTC_DRV26 MCHP_PINMUX(b, 7, p, periph)
+
+/* pb8_gpio */
+#define PB8_GPIO MCHP_PINMUX(b, 8, gpio, gpio)
+
+/* pb8a_eic_extint9 */
+#define PB8A_EIC_EXTINT9 MCHP_PINMUX(b, 8, a, periph)
+
+/* pb8f_tcc2_wo1 */
+#define PB8F_TCC2_WO1 MCHP_PINMUX(b, 8, f, periph)
+
+/* pb8i_ccl1_in11 */
+#define PB8I_CCL1_IN11 MCHP_PINMUX(b, 8, i, periph)
+
+/* pb8p_ptc_ptcxy27 */
+#define PB8P_PTC_PTCXY27 MCHP_PINMUX(b, 8, p, periph)
+
+/* pb8p_ptc_drv27 */
+#define PB8P_PTC_DRV27 MCHP_PINMUX(b, 8, p, periph)
+
+/* pb9_gpio */
+#define PB9_GPIO MCHP_PINMUX(b, 9, gpio, gpio)
+
+/* pb9a_eic_extint10 */
+#define PB9A_EIC_EXTINT10 MCHP_PINMUX(b, 9, a, periph)
+
+/* pb9f_tcc2_wo0 */
+#define PB9F_TCC2_WO0 MCHP_PINMUX(b, 9, f, periph)
+
+/* pb9k_gclk_io7 */
+#define PB9K_GCLK_IO7 MCHP_PINMUX(b, 9, k, periph)
+
+/* pb9p_ptc_ptcxy28 */
+#define PB9P_PTC_PTCXY28 MCHP_PINMUX(b, 9, p, periph)
+
+/* pb9p_ptc_drv28 */
+#define PB9P_PTC_DRV28 MCHP_PINMUX(b, 9, p, periph)
+
+/* pb10_gpio */
+#define PB10_GPIO MCHP_PINMUX(b, 10, gpio, gpio)
+
+/* pb10a_eic_extint11 */
+#define PB10A_EIC_EXTINT11 MCHP_PINMUX(b, 10, a, periph)
+
+/* pb10i_ccl0_in11 */
+#define PB10I_CCL0_IN11 MCHP_PINMUX(b, 10, i, periph)
+
+/* pb10k_gclk_io6 */
+#define PB10K_GCLK_IO6 MCHP_PINMUX(b, 10, k, periph)
+
+/* pb10p_ptc_ptcxy29 */
+#define PB10P_PTC_PTCXY29 MCHP_PINMUX(b, 10, p, periph)
+
+/* pb10p_ptc_drv29 */
+#define PB10P_PTC_DRV29 MCHP_PINMUX(b, 10, p, periph)
+
+/* pb11_gpio */
+#define PB11_GPIO MCHP_PINMUX(b, 11, gpio, gpio)
+
+/* pb11a_eic_extint12 */
+#define PB11A_EIC_EXTINT12 MCHP_PINMUX(b, 11, a, periph)
+
+/* pb11f_tcc0_wo0 */
+#define PB11F_TCC0_WO0 MCHP_PINMUX(b, 11, f, periph)
+
+/* pb11i_ccl1_in9 */
+#define PB11I_CCL1_IN9 MCHP_PINMUX(b, 11, i, periph)
+
+/* pb12_gpio */
+#define PB12_GPIO MCHP_PINMUX(b, 12, gpio, gpio)
+
+/* pb12a_eic_extint2 */
+#define PB12A_EIC_EXTINT2 MCHP_PINMUX(b, 12, a, periph)
+
+/* pb12f_tcc0_wo1 */
+#define PB12F_TCC0_WO1 MCHP_PINMUX(b, 12, f, periph)
+
+/* pb12i_ccl0_in9 */
+#define PB12I_CCL0_IN9 MCHP_PINMUX(b, 12, i, periph)
+
+/* pb13_gpio */
+#define PB13_GPIO MCHP_PINMUX(b, 13, gpio, gpio)
+
+/* pb13a_eic_extint14 */
+#define PB13A_EIC_EXTINT14 MCHP_PINMUX(b, 13, a, periph)
+
+/* pb13f_tcc3_wo0 */
+#define PB13F_TCC3_WO0 MCHP_PINMUX(b, 13, f, periph)
+
+/* pb13i_ccl1_in10 */
+#define PB13I_CCL1_IN10 MCHP_PINMUX(b, 13, i, periph)
+
+/* pb14_gpio */
+#define PB14_GPIO MCHP_PINMUX(b, 14, gpio, gpio)
+
+/* pb14a_eic_extint15 */
+#define PB14A_EIC_EXTINT15 MCHP_PINMUX(b, 14, a, periph)
+
+/* pb14f_tcc3_wo1 */
+#define PB14F_TCC3_WO1 MCHP_PINMUX(b, 14, f, periph)
+
+/* pb14i_ccl0_in10 */
+#define PB14I_CCL0_IN10 MCHP_PINMUX(b, 14, i, periph)
+
+/* pb15_gpio */
+#define PB15_GPIO MCHP_PINMUX(b, 15, gpio, gpio)
+
+/* pb15a_eic_extint0 */
+#define PB15A_EIC_EXTINT0 MCHP_PINMUX(b, 15, a, periph)
+
+/* pb15d_sercom0_pad0 */
+#define PB15D_SERCOM0_PAD0 MCHP_PINMUX(b, 15, d, periph)
+
+/* pb15i_ccl0_in11 */
+#define PB15I_CCL0_IN11 MCHP_PINMUX(b, 15, i, periph)
+
+/* pb15k_gclk_io0 */
+#define PB15K_GCLK_IO0 MCHP_PINMUX(b, 15, k, periph)
+
+/* pb16_gpio */
+#define PB16_GPIO MCHP_PINMUX(b, 16, gpio, gpio)
+
+/* pb16a_eic_extint1 */
+#define PB16A_EIC_EXTINT1 MCHP_PINMUX(b, 16, a, periph)
+
+/* pb16d_sercom0_pad1 */
+#define PB16D_SERCOM0_PAD1 MCHP_PINMUX(b, 16, d, periph)
+
+/* pb16i_ccl0_out3 */
+#define PB16I_CCL0_OUT3 MCHP_PINMUX(b, 16, i, periph)
+
+/* pb16k_gclk_io6 */
+#define PB16K_GCLK_IO6 MCHP_PINMUX(b, 16, k, periph)
+
+/* pb17_gpio */
+#define PB17_GPIO MCHP_PINMUX(b, 17, gpio, gpio)
+
+/* pb17a_eic_extint2 */
+#define PB17A_EIC_EXTINT2 MCHP_PINMUX(b, 17, a, periph)
+
+/* pb17d_sercom0_pad2 */
+#define PB17D_SERCOM0_PAD2 MCHP_PINMUX(b, 17, d, periph)
+
+/* pb17i_ccl1_out3 */
+#define PB17I_CCL1_OUT3 MCHP_PINMUX(b, 17, i, periph)
+
+/* pc0_gpio */
+#define PC0_GPIO MCHP_PINMUX(c, 0, gpio, gpio)
+
+/* pc0a_eic_extint0 */
+#define PC0A_EIC_EXTINT0 MCHP_PINMUX(c, 0, a, periph)
+
+/* pc0d_sercom0_pad0 */
+#define PC0D_SERCOM0_PAD0 MCHP_PINMUX(c, 0, d, periph)
+
+/* pc0f_tcc0_wo0 */
+#define PC0F_TCC0_WO0 MCHP_PINMUX(c, 0, f, periph)
+
+/* pc0i_ccl0_out3 */
+#define PC0I_CCL0_OUT3 MCHP_PINMUX(c, 0, i, periph)
+
+/* pc0k_gclk_io1 */
+#define PC0K_GCLK_IO1 MCHP_PINMUX(c, 0, k, periph)
+
+/* pc0p_ptc_ptcxy19 */
+#define PC0P_PTC_PTCXY19 MCHP_PINMUX(c, 0, p, periph)
+
+/* pc0p_ptc_drv19 */
+#define PC0P_PTC_DRV19 MCHP_PINMUX(c, 0, p, periph)
+
+/* pc0pdmo_lv_test_pdm_pdmo4 */
+#define PC0PDMO_LV_TEST_PDM_PDMO4 MCHP_PINMUX(c, 0, pdmo_lv_test, periph)
+
+/* pc0pdmo_mv_test_pdm_pdmo4_mv */
+#define PC0PDMO_MV_TEST_PDM_PDMO4_MV MCHP_PINMUX(c, 0, pdmo_mv_test, periph)
+
+/* pc1_gpio */
+#define PC1_GPIO MCHP_PINMUX(c, 1, gpio, gpio)
+
+/* pc1a_eic_extint1 */
+#define PC1A_EIC_EXTINT1 MCHP_PINMUX(c, 1, a, periph)
+
+/* pc1d_sercom0_pad1 */
+#define PC1D_SERCOM0_PAD1 MCHP_PINMUX(c, 1, d, periph)
+
+/* pc1f_tcc0_wo1 */
+#define PC1F_TCC0_WO1 MCHP_PINMUX(c, 1, f, periph)
+
+/* pc1h_can0_rx */
+#define PC1H_CAN0_RX MCHP_PINMUX(c, 1, h, periph)
+
+/* pc1i_ccl0_in0 */
+#define PC1I_CCL0_IN0 MCHP_PINMUX(c, 1, i, periph)
+
+/* pc1k_gclk_io2 */
+#define PC1K_GCLK_IO2 MCHP_PINMUX(c, 1, k, periph)
+
+/* pc1p_ptc_ptcxy20 */
+#define PC1P_PTC_PTCXY20 MCHP_PINMUX(c, 1, p, periph)
+
+/* pc1p_ptc_drv20 */
+#define PC1P_PTC_DRV20 MCHP_PINMUX(c, 1, p, periph)
+
+/* pc1pdmo_lv_test_pdm_pdmo5 */
+#define PC1PDMO_LV_TEST_PDM_PDMO5 MCHP_PINMUX(c, 1, pdmo_lv_test, periph)
+
+/* pc1pdmo_mv_test_pdm_pdmo5_mv */
+#define PC1PDMO_MV_TEST_PDM_PDMO5_MV MCHP_PINMUX(c, 1, pdmo_mv_test, periph)
+
+/* pc1valio_testval_valio4 */
+#define PC1VALIO_TESTVAL_VALIO4 MCHP_PINMUX(c, 1, valio, periph)
+
+/* pc2_gpio */
+#define PC2_GPIO MCHP_PINMUX(c, 2, gpio, gpio)
+
+/* pc2a_eic_extint2 */
+#define PC2A_EIC_EXTINT2 MCHP_PINMUX(c, 2, a, periph)
+
+/* pc2d_sercom0_pad2 */
+#define PC2D_SERCOM0_PAD2 MCHP_PINMUX(c, 2, d, periph)
+
+/* pc2f_tcc1_wo0 */
+#define PC2F_TCC1_WO0 MCHP_PINMUX(c, 2, f, periph)
+
+/* pc2h_can0_tx */
+#define PC2H_CAN0_TX MCHP_PINMUX(c, 2, h, periph)
+
+/* pc2i_ccl0_in1 */
+#define PC2I_CCL0_IN1 MCHP_PINMUX(c, 2, i, periph)
+
+/* pc2k_gclk_io3 */
+#define PC2K_GCLK_IO3 MCHP_PINMUX(c, 2, k, periph)
+
+/* pc2p_ptc_ptcxy21 */
+#define PC2P_PTC_PTCXY21 MCHP_PINMUX(c, 2, p, periph)
+
+/* pc2p_ptc_drv21 */
+#define PC2P_PTC_DRV21 MCHP_PINMUX(c, 2, p, periph)
+
+/* pc2pdmo_lv_test_pdm_pdmo6 */
+#define PC2PDMO_LV_TEST_PDM_PDMO6 MCHP_PINMUX(c, 2, pdmo_lv_test, periph)
+
+/* pc2pdmo_mv_test_pdm_pdmo6_mv */
+#define PC2PDMO_MV_TEST_PDM_PDMO6_MV MCHP_PINMUX(c, 2, pdmo_mv_test, periph)
+
+/* pc2valio_testval_valio5 */
+#define PC2VALIO_TESTVAL_VALIO5 MCHP_PINMUX(c, 2, valio, periph)
+
+/* pc3_gpio */
+#define PC3_GPIO MCHP_PINMUX(c, 3, gpio, gpio)
+
+/* pc3a_eic_extint3 */
+#define PC3A_EIC_EXTINT3 MCHP_PINMUX(c, 3, a, periph)
+
+/* pc3d_sercom0_pad3 */
+#define PC3D_SERCOM0_PAD3 MCHP_PINMUX(c, 3, d, periph)
+
+/* pc3f_tcc1_wo1 */
+#define PC3F_TCC1_WO1 MCHP_PINMUX(c, 3, f, periph)
+
+/* pc3i_ccl0_out0 */
+#define PC3I_CCL0_OUT0 MCHP_PINMUX(c, 3, i, periph)
+
+/* pc3k_gclk_io4 */
+#define PC3K_GCLK_IO4 MCHP_PINMUX(c, 3, k, periph)
+
+/* pc3p_ptc_eci0 */
+#define PC3P_PTC_ECI0 MCHP_PINMUX(c, 3, p, periph)
+
+/* pc3pdmo_lv_test_pdm_pdmo7 */
+#define PC3PDMO_LV_TEST_PDM_PDMO7 MCHP_PINMUX(c, 3, pdmo_lv_test, periph)
+
+/* pc3pdmo_mv_test_pdm_pdmo7_mv */
+#define PC3PDMO_MV_TEST_PDM_PDMO7_MV MCHP_PINMUX(c, 3, pdmo_mv_test, periph)
+
+/* pc4_gpio */
+#define PC4_GPIO MCHP_PINMUX(c, 4, gpio, gpio)
+
+/* pc4a_eic_extint4 */
+#define PC4A_EIC_EXTINT4 MCHP_PINMUX(c, 4, a, periph)
+
+/* pc4d_sercom2_pad0 */
+#define PC4D_SERCOM2_PAD0 MCHP_PINMUX(c, 4, d, periph)
+
+/* pc4f_tcc2_wo0 */
+#define PC4F_TCC2_WO0 MCHP_PINMUX(c, 4, f, periph)
+
+/* pc4i_ccl1_in0 */
+#define PC4I_CCL1_IN0 MCHP_PINMUX(c, 4, i, periph)
+
+/* pc4k_gclk_io5 */
+#define PC4K_GCLK_IO5 MCHP_PINMUX(c, 4, k, periph)
+
+/* pc4p_ptc_eci1 */
+#define PC4P_PTC_ECI1 MCHP_PINMUX(c, 4, p, periph)
+
+/* pc4valio_testval_valio2 */
+#define PC4VALIO_TESTVAL_VALIO2 MCHP_PINMUX(c, 4, valio, periph)
+
+/* pc5_gpio */
+#define PC5_GPIO MCHP_PINMUX(c, 5, gpio, gpio)
+
+/* pc5a_eic_extint5 */
+#define PC5A_EIC_EXTINT5 MCHP_PINMUX(c, 5, a, periph)
+
+/* pc5d_sercom1_pad3 */
+#define PC5D_SERCOM1_PAD3 MCHP_PINMUX(c, 5, d, periph)
+
+/* pc5dsu_msa_dsu_msa */
+#define PC5DSU_MSA_DSU_MSA MCHP_PINMUX(c, 5, dsu_msa, periph)
+
+/* pc5f_tcc2_wo1 */
+#define PC5F_TCC2_WO1 MCHP_PINMUX(c, 5, f, periph)
+
+/* pc5h_can1_rx */
+#define PC5H_CAN1_RX MCHP_PINMUX(c, 5, h, periph)
+
+/* pc5i_ccl1_in1 */
+#define PC5I_CCL1_IN1 MCHP_PINMUX(c, 5, i, periph)
+
+/* pc5k_gclk_io1 */
+#define PC5K_GCLK_IO1 MCHP_PINMUX(c, 5, k, periph)
+
+/* pc6_gpio */
+#define PC6_GPIO MCHP_PINMUX(c, 6, gpio, gpio)
+
+/* pc6a_eic_extint6 */
+#define PC6A_EIC_EXTINT6 MCHP_PINMUX(c, 6, a, periph)
+
+/* pc6d_sercom1_pad2 */
+#define PC6D_SERCOM1_PAD2 MCHP_PINMUX(c, 6, d, periph)
+
+/* pc6dsu_swccstat_dsu_swccstat */
+#define PC6DSU_SWCCSTAT_DSU_SWCCSTAT MCHP_PINMUX(c, 6, dsu_swccstat, periph)
+
+/* pc6h_can1_tx */
+#define PC6H_CAN1_TX MCHP_PINMUX(c, 6, h, periph)
+
+/* pc6i_ccl1_out0 */
+#define PC6I_CCL1_OUT0 MCHP_PINMUX(c, 6, i, periph)
+
+/* pc8_gpio */
+#define PC8_GPIO MCHP_PINMUX(c, 8, gpio, gpio)
+
+/* pc8dsu_test_gclk_gclk_tst_gclk */
+#define PC8DSU_TEST_GCLK_GCLK_TST_GCLK MCHP_PINMUX(c, 8, dsu_test_gclk, periph)
+
+/* pc9_gpio */
+#define PC9_GPIO MCHP_PINMUX(c, 9, gpio, gpio)
+
+/* pc9a_eic_extint9 */
+#define PC9A_EIC_EXTINT9 MCHP_PINMUX(c, 9, a, periph)
+
+/* pc9f_tcc1_wo0 */
+#define PC9F_TCC1_WO0 MCHP_PINMUX(c, 9, f, periph)
+
+/* pc9i_ccl0_in2 */
+#define PC9I_CCL0_IN2 MCHP_PINMUX(c, 9, i, periph)
+
+/* pc9k_gclk_io0 */
+#define PC9K_GCLK_IO0 MCHP_PINMUX(c, 9, k, periph)
+
+/* pc9p_ptc_ptcxy30 */
+#define PC9P_PTC_PTCXY30 MCHP_PINMUX(c, 9, p, periph)
+
+/* pc9p_ptc_drv30 */
+#define PC9P_PTC_DRV30 MCHP_PINMUX(c, 9, p, periph)
+
+/* pc10_gpio */
+#define PC10_GPIO MCHP_PINMUX(c, 10, gpio, gpio)
+
+/* pc10a_eic_extint10 */
+#define PC10A_EIC_EXTINT10 MCHP_PINMUX(c, 10, a, periph)
+
+/* pc10f_tcc1_wo1 */
+#define PC10F_TCC1_WO1 MCHP_PINMUX(c, 10, f, periph)
+
+/* pc10i_ccl1_in2 */
+#define PC10I_CCL1_IN2 MCHP_PINMUX(c, 10, i, periph)
+
+/* pc10k_gclk_io1 */
+#define PC10K_GCLK_IO1 MCHP_PINMUX(c, 10, k, periph)
+
+/* pc10p_ptc_ptcxy31 */
+#define PC10P_PTC_PTCXY31 MCHP_PINMUX(c, 10, p, periph)
+
+/* pc10p_ptc_drv31 */
+#define PC10P_PTC_DRV31 MCHP_PINMUX(c, 10, p, periph)
+
+/* pc11_gpio */
+#define PC11_GPIO MCHP_PINMUX(c, 11, gpio, gpio)
+
+/* pc11a_eic_extint11 */
+#define PC11A_EIC_EXTINT11 MCHP_PINMUX(c, 11, a, periph)
+
+/* pc11d_sercom0_pad3 */
+#define PC11D_SERCOM0_PAD3 MCHP_PINMUX(c, 11, d, periph)
+
+/* pc11i_ccl1_in0 */
+#define PC11I_CCL1_IN0 MCHP_PINMUX(c, 11, i, periph)
+
+/* pc12_gpio */
+#define PC12_GPIO MCHP_PINMUX(c, 12, gpio, gpio)
+
+/* pc12a_eic_extint12 */
+#define PC12A_EIC_EXTINT12 MCHP_PINMUX(c, 12, a, periph)
+
+/* pc12d_sercom1_pad3 */
+#define PC12D_SERCOM1_PAD3 MCHP_PINMUX(c, 12, d, periph)
+
+/* pc12i_ccl0_in0 */
+#define PC12I_CCL0_IN0 MCHP_PINMUX(c, 12, i, periph)
+
+/* pc13_gpio */
+#define PC13_GPIO MCHP_PINMUX(c, 13, gpio, gpio)
+
+/* pc13a_eic_extint13 */
+#define PC13A_EIC_EXTINT13 MCHP_PINMUX(c, 13, a, periph)
+
+/* pc13d_sercom1_pad2 */
+#define PC13D_SERCOM1_PAD2 MCHP_PINMUX(c, 13, d, periph)
+
+/* pc13i_ccl0_out0 */
+#define PC13I_CCL0_OUT0 MCHP_PINMUX(c, 13, i, periph)
+
+/* pc14_gpio */
+#define PC14_GPIO MCHP_PINMUX(c, 14, gpio, gpio)
+
+/* pc14a_eic_extint14 */
+#define PC14A_EIC_EXTINT14 MCHP_PINMUX(c, 14, a, periph)
+
+/* pc14d_sercom1_pad1 */
+#define PC14D_SERCOM1_PAD1 MCHP_PINMUX(c, 14, d, periph)
+
+/* pc14i_ccl0_in1 */
+#define PC14I_CCL0_IN1 MCHP_PINMUX(c, 14, i, periph)
+
+/* pc15_gpio */
+#define PC15_GPIO MCHP_PINMUX(c, 15, gpio, gpio)
+
+/* pc15a_eic_extint15 */
+#define PC15A_EIC_EXTINT15 MCHP_PINMUX(c, 15, a, periph)
+
+/* pc15d_sercom1_pad0 */
+#define PC15D_SERCOM1_PAD0 MCHP_PINMUX(c, 15, d, periph)
+
+/* pc15i_ccl0_in2 */
+#define PC15I_CCL0_IN2 MCHP_PINMUX(c, 15, i, periph)
+
+/* pc16_gpio */
+#define PC16_GPIO MCHP_PINMUX(c, 16, gpio, gpio)
+
+/* pc16a_eic_extint0 */
+#define PC16A_EIC_EXTINT0 MCHP_PINMUX(c, 16, a, periph)
+
+/* pc16d_sercom2_pad3 */
+#define PC16D_SERCOM2_PAD3 MCHP_PINMUX(c, 16, d, periph)
+
+/* pc16i_ccl1_in2 */
+#define PC16I_CCL1_IN2 MCHP_PINMUX(c, 16, i, periph)
+
+/* pc17_gpio */
+#define PC17_GPIO MCHP_PINMUX(c, 17, gpio, gpio)
+
+/* pc17a_eic_extint1 */
+#define PC17A_EIC_EXTINT1 MCHP_PINMUX(c, 17, a, periph)
+
+/* pc17d_sercom2_pad2 */
+#define PC17D_SERCOM2_PAD2 MCHP_PINMUX(c, 17, d, periph)
+
+/* pc17i_ccl1_in1 */
+#define PC17I_CCL1_IN1 MCHP_PINMUX(c, 17, i, periph)
+
+/* pc18_gpio */
+#define PC18_GPIO MCHP_PINMUX(c, 18, gpio, gpio)
+
+/* pc18a_eic_extint2 */
+#define PC18A_EIC_EXTINT2 MCHP_PINMUX(c, 18, a, periph)
+
+/* pc18d_sercom2_pad1 */
+#define PC18D_SERCOM2_PAD1 MCHP_PINMUX(c, 18, d, periph)
+
+/* pc19_gpio */
+#define PC19_GPIO MCHP_PINMUX(c, 19, gpio, gpio)
+
+/* pc19a_eic_extint3 */
+#define PC19A_EIC_EXTINT3 MCHP_PINMUX(c, 19, a, periph)
+
+/* pc19d_sercom2_pad0 */
+#define PC19D_SERCOM2_PAD0 MCHP_PINMUX(c, 19, d, periph)
+
+/* pc19i_ccl1_out0 */
+#define PC19I_CCL1_OUT0 MCHP_PINMUX(c, 19, i, periph)
+
+/* pd0_gpio */
+#define PD0_GPIO MCHP_PINMUX(d, 0, gpio, gpio)
+
+/* pd0a_eic_nmi */
+#define PD0A_EIC_NMI MCHP_PINMUX(d, 0, a, periph)
+
+/* pd0d_sercom1_pad1 */
+#define PD0D_SERCOM1_PAD1 MCHP_PINMUX(d, 0, d, periph)
+
+/* pd0f_tcc3_wo0 */
+#define PD0F_TCC3_WO0 MCHP_PINMUX(d, 0, f, periph)
+
+/* pd0i_ccl0_in3 */
+#define PD0I_CCL0_IN3 MCHP_PINMUX(d, 0, i, periph)
+
+/* pd0valio_testval_valio0 */
+#define PD0VALIO_TESTVAL_VALIO0 MCHP_PINMUX(d, 0, valio, periph)
+
+/* pd1_gpio */
+#define PD1_GPIO MCHP_PINMUX(d, 1, gpio, gpio)
+
+/* pd1a_eic_extint1 */
+#define PD1A_EIC_EXTINT1 MCHP_PINMUX(d, 1, a, periph)
+
+/* pd1d_sercom1_pad0 */
+#define PD1D_SERCOM1_PAD0 MCHP_PINMUX(d, 1, d, periph)
+
+/* pd1f_tcc3_wo1 */
+#define PD1F_TCC3_WO1 MCHP_PINMUX(d, 1, f, periph)
+
+/* pd1h_usb_sof */
+#define PD1H_USB_SOF MCHP_PINMUX(d, 1, h, periph)
+
+/* pd1i_ccl0_in4 */
+#define PD1I_CCL0_IN4 MCHP_PINMUX(d, 1, i, periph)
+
+/* pd1valio_testval_valio1 */
+#define PD1VALIO_TESTVAL_VALIO1 MCHP_PINMUX(d, 1, valio, periph)
+
+/* pd2_gpio */
+#define PD2_GPIO MCHP_PINMUX(d, 2, gpio, gpio)
+
+/* pd2h_usb_usbdm */
+#define PD2H_USB_USBDM MCHP_PINMUX(d, 2, h, periph)
+
+/* pd3_gpio */
+#define PD3_GPIO MCHP_PINMUX(d, 3, gpio, gpio)
+
+/* pd3h_usb_usbdp */
+#define PD3H_USB_USBDP MCHP_PINMUX(d, 3, h, periph)
+
+/* pd4_gpio */
+#define PD4_GPIO MCHP_PINMUX(d, 4, gpio, gpio)
+
+/* pd4a_eic_extint2 */
+#define PD4A_EIC_EXTINT2 MCHP_PINMUX(d, 4, a, periph)
+
+/* pd4k_gclk_io1 */
+#define PD4K_GCLK_IO1 MCHP_PINMUX(d, 4, k, periph)
+
+/* pd5_gpio */
+#define PD5_GPIO MCHP_PINMUX(d, 5, gpio, gpio)
+
+/* pd5a_eic_extint3 */
+#define PD5A_EIC_EXTINT3 MCHP_PINMUX(d, 5, a, periph)
+
+/* pd5k_gclk_io0 */
+#define PD5K_GCLK_IO0 MCHP_PINMUX(d, 5, k, periph)
+
+/* pd6_gpio */
+#define PD6_GPIO MCHP_PINMUX(d, 6, gpio, gpio)
+
+/* pd6d_sercom2_pad1 */
+#define PD6D_SERCOM2_PAD1 MCHP_PINMUX(d, 6, d, periph)
+
+/* pd6h_can0_rx */
+#define PD6H_CAN0_RX MCHP_PINMUX(d, 6, h, periph)
+
+/* pd6i_ccl1_in3 */
+#define PD6I_CCL1_IN3 MCHP_PINMUX(d, 6, i, periph)
+
+/* pd6p_ptc_ptcxy0 */
+#define PD6P_PTC_PTCXY0 MCHP_PINMUX(d, 6, p, periph)
+
+/* pd6p_ptc_drv0 */
+#define PD6P_PTC_DRV0 MCHP_PINMUX(d, 6, p, periph)
+
+/* pd7_gpio */
+#define PD7_GPIO MCHP_PINMUX(d, 7, gpio, gpio)
+
+/* pd7a_eic_extint4 */
+#define PD7A_EIC_EXTINT4 MCHP_PINMUX(d, 7, a, periph)
+
+/* pd7adc_test_pad_adc_res_test2 */
+#define PD7ADC_TEST_PAD_ADC_RES_TEST2 MCHP_PINMUX(d, 7, adc_test_pad, periph)
+
+/* pd7d_sercom2_pad2 */
+#define PD7D_SERCOM2_PAD2 MCHP_PINMUX(d, 7, d, periph)
+
+/* pd7f_tcc4_wo0 */
+#define PD7F_TCC4_WO0 MCHP_PINMUX(d, 7, f, periph)
+
+/* pd7i_ccl1_in4 */
+#define PD7I_CCL1_IN4 MCHP_PINMUX(d, 7, i, periph)
+
+/* pd7p_ptc_ptcxy1 */
+#define PD7P_PTC_PTCXY1 MCHP_PINMUX(d, 7, p, periph)
+
+/* pd7p_ptc_drv1 */
+#define PD7P_PTC_DRV1 MCHP_PINMUX(d, 7, p, periph)
+
+/* pd7pdmi_test_pdm_pdmi0 */
+#define PD7PDMI_TEST_PDM_PDMI0 MCHP_PINMUX(d, 7, pdmi_test, periph)
+
+/* pd8_gpio */
+#define PD8_GPIO MCHP_PINMUX(d, 8, gpio, gpio)
+
+/* pd8a_eic_extint5 */
+#define PD8A_EIC_EXTINT5 MCHP_PINMUX(d, 8, a, periph)
+
+/* pd8adc_test_pad_adc_res_test0 */
+#define PD8ADC_TEST_PAD_ADC_RES_TEST0 MCHP_PINMUX(d, 8, adc_test_pad, periph)
+
+/* pd8d_sercom2_pad3 */
+#define PD8D_SERCOM2_PAD3 MCHP_PINMUX(d, 8, d, periph)
+
+/* pd8f_tcc4_wo1 */
+#define PD8F_TCC4_WO1 MCHP_PINMUX(d, 8, f, periph)
+
+/* pd8h_can0_tx */
+#define PD8H_CAN0_TX MCHP_PINMUX(d, 8, h, periph)
+
+/* pd8i_ccl0_out1 */
+#define PD8I_CCL0_OUT1 MCHP_PINMUX(d, 8, i, periph)
+
+/* pd8p_ptc_ptcxy2 */
+#define PD8P_PTC_PTCXY2 MCHP_PINMUX(d, 8, p, periph)
+
+/* pd8p_ptc_drv2 */
+#define PD8P_PTC_DRV2 MCHP_PINMUX(d, 8, p, periph)
+
+/* pd8pdmi_test_pdm_pdmi1 */
+#define PD8PDMI_TEST_PDM_PDMI1 MCHP_PINMUX(d, 8, pdmi_test, periph)
+
+/* pd9_gpio */
+#define PD9_GPIO MCHP_PINMUX(d, 9, gpio, gpio)
+
+/* pd9a_eic_extint6 */
+#define PD9A_EIC_EXTINT6 MCHP_PINMUX(d, 9, a, periph)
+
+/* pd9adc_test_pad_adc_res_test1 */
+#define PD9ADC_TEST_PAD_ADC_RES_TEST1 MCHP_PINMUX(d, 9, adc_test_pad, periph)
+
+/* pd9d_sercom3_pad0 */
+#define PD9D_SERCOM3_PAD0 MCHP_PINMUX(d, 9, d, periph)
+
+/* pd9f_tcc5_wo0 */
+#define PD9F_TCC5_WO0 MCHP_PINMUX(d, 9, f, periph)
+
+/* pd9i_ccl1_out1 */
+#define PD9I_CCL1_OUT1 MCHP_PINMUX(d, 9, i, periph)
+
+/* pd9p_ptc_ptcxy3 */
+#define PD9P_PTC_PTCXY3 MCHP_PINMUX(d, 9, p, periph)
+
+/* pd9p_ptc_drv3 */
+#define PD9P_PTC_DRV3 MCHP_PINMUX(d, 9, p, periph)
+
+/* pd9pdmi_test_pdm_pdmi2 */
+#define PD9PDMI_TEST_PDM_PDMI2 MCHP_PINMUX(d, 9, pdmi_test, periph)
+
+/* pd10_gpio */
+#define PD10_GPIO MCHP_PINMUX(d, 10, gpio, gpio)
+
+/* pd10a_eic_extint8 */
+#define PD10A_EIC_EXTINT8 MCHP_PINMUX(d, 10, a, periph)
+
+/* pd10d_sercom1_pad2 */
+#define PD10D_SERCOM1_PAD2 MCHP_PINMUX(d, 10, d, periph)
+
+/* pd10f_tcc5_wo0 */
+#define PD10F_TCC5_WO0 MCHP_PINMUX(d, 10, f, periph)
+
+/* pd10i_ccl0_in5 */
+#define PD10I_CCL0_IN5 MCHP_PINMUX(d, 10, i, periph)
+
+/* pd11_gpio */
+#define PD11_GPIO MCHP_PINMUX(d, 11, gpio, gpio)
+
+/* pd11a_eic_extint9 */
+#define PD11A_EIC_EXTINT9 MCHP_PINMUX(d, 11, a, periph)
+
+/* pd11d_sercom1_pad3 */
+#define PD11D_SERCOM1_PAD3 MCHP_PINMUX(d, 11, d, periph)
+
+/* pd11f_tcc5_wo1 */
+#define PD11F_TCC5_WO1 MCHP_PINMUX(d, 11, f, periph)
+
+/* pd11i_ccl1_in5 */
+#define PD11I_CCL1_IN5 MCHP_PINMUX(d, 11, i, periph)
+
+/* pd12_gpio */
+#define PD12_GPIO MCHP_PINMUX(d, 12, gpio, gpio)
+
+/* pd12a_eic_extint10 */
+#define PD12A_EIC_EXTINT10 MCHP_PINMUX(d, 12, a, periph)
+
+/* pd12f_tcc6_wo0 */
+#define PD12F_TCC6_WO0 MCHP_PINMUX(d, 12, f, periph)
+
+/* pd12h_can1_rx */
+#define PD12H_CAN1_RX MCHP_PINMUX(d, 12, h, periph)
+
+/* pd12i_ccl1_in5 */
+#define PD12I_CCL1_IN5 MCHP_PINMUX(d, 12, i, periph)
+
+/* pd13_gpio */
+#define PD13_GPIO MCHP_PINMUX(d, 13, gpio, gpio)
+
+/* pd13a_eic_extint11 */
+#define PD13A_EIC_EXTINT11 MCHP_PINMUX(d, 13, a, periph)
+
+/* pd13f_tcc6_wo1 */
+#define PD13F_TCC6_WO1 MCHP_PINMUX(d, 13, f, periph)
+
+/* pd13h_can1_tx */
+#define PD13H_CAN1_TX MCHP_PINMUX(d, 13, h, periph)
+
+/* pd14_gpio */
+#define PD14_GPIO MCHP_PINMUX(d, 14, gpio, gpio)
+
+/* pd14a_eic_extint12 */
+#define PD14A_EIC_EXTINT12 MCHP_PINMUX(d, 14, a, periph)
+
+/* pd14d_sercom3_pad3 */
+#define PD14D_SERCOM3_PAD3 MCHP_PINMUX(d, 14, d, periph)
+
+/* pd14i_ccl0_out1 */
+#define PD14I_CCL0_OUT1 MCHP_PINMUX(d, 14, i, periph)
+
+/* pd15_gpio */
+#define PD15_GPIO MCHP_PINMUX(d, 15, gpio, gpio)
+
+/* pd15a_eic_extint13 */
+#define PD15A_EIC_EXTINT13 MCHP_PINMUX(d, 15, a, periph)
+
+/* pd15d_sercom3_pad1 */
+#define PD15D_SERCOM3_PAD1 MCHP_PINMUX(d, 15, d, periph)
+
+/* pd15i_ccl1_out1 */
+#define PD15I_CCL1_OUT1 MCHP_PINMUX(d, 15, i, periph)
+
+/* pd16_gpio */
+#define PD16_GPIO MCHP_PINMUX(d, 16, gpio, gpio)
+
+/* pd16a_eic_extint14 */
+#define PD16A_EIC_EXTINT14 MCHP_PINMUX(d, 16, a, periph)
+
+/* pd16d_sercom3_pad0 */
+#define PD16D_SERCOM3_PAD0 MCHP_PINMUX(d, 16, d, periph)
+
+/* pd16i_ccl1_in4 */
+#define PD16I_CCL1_IN4 MCHP_PINMUX(d, 16, i, periph)
+
+/* pd17_gpio */
+#define PD17_GPIO MCHP_PINMUX(d, 17, gpio, gpio)
+
+/* pd17a_eic_extint15 */
+#define PD17A_EIC_EXTINT15 MCHP_PINMUX(d, 17, a, periph)
+
+/* pd17d_sercom3_pad2 */
+#define PD17D_SERCOM3_PAD2 MCHP_PINMUX(d, 17, d, periph)
+
+/* pd17i_ccl0_in4 */
+#define PD17I_CCL0_IN4 MCHP_PINMUX(d, 17, i, periph)
+
+/* pd18_gpio */
+#define PD18_GPIO MCHP_PINMUX(d, 18, gpio, gpio)
+
+/* pd18a_eic_extint0 */
+#define PD18A_EIC_EXTINT0 MCHP_PINMUX(d, 18, a, periph)
+
+/* pd18d_sercom4_pad2 */
+#define PD18D_SERCOM4_PAD2 MCHP_PINMUX(d, 18, d, periph)
+
+/* pd18i_ccl0_in3 */
+#define PD18I_CCL0_IN3 MCHP_PINMUX(d, 18, i, periph)
+
+/* pd19_gpio */
+#define PD19_GPIO MCHP_PINMUX(d, 19, gpio, gpio)
+
+/* pd19a_eic_extint1 */
+#define PD19A_EIC_EXTINT1 MCHP_PINMUX(d, 19, a, periph)
+
+/* pd19d_sercom4_pad0 */
+#define PD19D_SERCOM4_PAD0 MCHP_PINMUX(d, 19, d, periph)
+
+/* pd19i_ccl0_in5 */
+#define PD19I_CCL0_IN5 MCHP_PINMUX(d, 19, i, periph)
+
+/* pd20_gpio */
+#define PD20_GPIO MCHP_PINMUX(d, 20, gpio, gpio)
+
+/* pd20a_eic_extint2 */
+#define PD20A_EIC_EXTINT2 MCHP_PINMUX(d, 20, a, periph)
+
+/* pd20d_sercom4_pad1 */
+#define PD20D_SERCOM4_PAD1 MCHP_PINMUX(d, 20, d, periph)
+
+/* pd20i_ccl1_in3 */
+#define PD20I_CCL1_IN3 MCHP_PINMUX(d, 20, i, periph)
+
+#endif /* MICROCHIP_PIC32CM5112GC00100_PINCTRL_H_ */
diff --git a/packs/pic32c/CMakeLists.txt b/packs/pic32c/CMakeLists.txt
index a063d79f..792716fd 100644
--- a/packs/pic32c/CMakeLists.txt
+++ b/packs/pic32c/CMakeLists.txt
@@ -6,3 +6,4 @@
 add_subdirectory_ifdef(CONFIG_SOC_FAMILY_MICROCHIP_PIC32CM_JH pic32cm_jh)
 add_subdirectory_ifdef(CONFIG_SOC_FAMILY_MICROCHIP_PIC32CX_SG pic32cx_sg)
 add_subdirectory_ifdef(CONFIG_SOC_FAMILY_MICROCHIP_PIC32CZ_CA pic32cz_ca)
+add_subdirectory_ifdef(CONFIG_SOC_FAMILY_MICROCHIP_PIC32CM_GC_SG pic32cm_gc_sg)
diff --git a/pic32c/pic32cm_gc_sg/CMakeLists.txt b/pic32c/pic32cm_gc_sg/CMakeLists.txt
new file mode 100644
index 00000000..2d67a11b
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_include_directories(${CONFIG_SOC_SERIES}/include)
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/atdf/PIC32CM5112GC00048.atdf b/pic32c/pic32cm_gc_sg/pic32cm_gc00/atdf/PIC32CM5112GC00048.atdf
new file mode 100644
index 00000000..42a91317
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/atdf/PIC32CM5112GC00048.atdf
@@ -0,0 +1,11100 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="4.5" public="true" xsi:noNamespaceSchemaLocation="https://schemas.microchip.com/com/microchip/atdf/4.5/atdf.xsd">
+  <!--
+ Copyright (c) 2024 Microchip Technology Inc.
+
+ SPDX-License-Identifier: Apache-2.0
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+-->
+  <!--
+CHPMKR VERSION: 2.17.0
+-->
+  <file timestamp="2024-11-05T16:47:51Z"/>
+  <variants xmlns:mhc="http://www.atmel.com/schemas/avr-tools-device-file/mhc">
+    <variant ordercode="PIC32CM5112GC00048-I/NA" mhc:ordercode="PIC32CM5112GC00048-I/NA" package="TQFP48" pinout="P48" speedmax="72000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00048-V/NA" mhc:ordercode="PIC32CM5112GC00048-V/NA" package="TQFP48" pinout="P48" speedmax="72000000" tempmin="-40" tempmax="105" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00048-E/NA" mhc:ordercode="PIC32CM5112GC00048-E/NA" package="TQFP48" pinout="P48" speedmax="72000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00048-I/NA" mhc:ordercode="PIC32CM5112GC00048-I/NA" package="VQFN48" pinout="P48_1" speedmax="72000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00048-V/NA" mhc:ordercode="PIC32CM5112GC00048-V/NA" package="VQFN48" pinout="P48_1" speedmax="72000000" tempmin="-40" tempmax="105" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00048-E/NA" mhc:ordercode="PIC32CM5112GC00048-E/NA" package="VQFN48" pinout="P48_1" speedmax="72000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="PIC32CM5112GC00048" architecture="CORTEX-M23" family="PIC32CM" series="PIC32CMGC00">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="BROMC_ROM" start="0x4000000" size="0x10000" type="rom" rw="R" exec="true"/>
+          <memory-segment name="FCR_BFM" start="0x8000000" size="0x4000" type="flash" rw="RW" exec="true"/>
+          <memory-segment name="FCR_CFM_BOOTCFG1A" start="0xA000000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_USEROTP" start="0xA001000" size="0x1000" type="user_signatures" rw="RW"/>
+          <memory-segment name="FCR_CFM_BOOTCFG1" start="0xA002000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_ROMCFG" start="0xA003000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_VSS0" start="0xA004000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_VSS1" start="0xA005000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_TEST" start="0xA006000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_CALOTP" start="0xA007000" size="0x1000" type="other" rw="R"/>
+          <memory-segment name="FCR_PFM" start="0xC000000" size="0x80000" type="flash" rw="RW" exec="true"/>
+          <memory-segment name="MCRAMC_RET" start="0x20000000" size="0x00020000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="APB0_BRIDGE" start="0x44000000" size="0x00034000" type="io" rw="RW"/>
+          <memory-segment name="APB1_BRIDGE" start="0x44800000" size="0x0003a000" type="io" rw="RW"/>
+          <memory-segment name="APB2_BRIDGE" start="0x45000000" size="0x00010000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xe0000000" size="0x00100000" type="io" rw="RW"/>
+        </address-space>
+      </address-spaces>
+      <parameters>
+        <param name="NUM_IRQ" value="141" caption="Number of interrupt request lines"/>
+        <param name="__BKPT_NUM" value="4" caption="Number of breakpoints comparators"/>
+        <param name="__CM23_REV" value="0x0000" caption="Cortex-M23 Core Revision"/>
+        <param name="__ETM_PRESENT" value="0" caption="No Embedded Trace Macro implemented"/>
+        <param name="__FPU_PRESENT" value="0" caption="No FPU"/>
+        <param name="__MPU_NS_REGIONS" value="8" caption="Number of Non-Secure Memory Protection Regions"/>
+        <param name="__MPU_PRESENT" value="1" caption="MPU implemented"/>
+        <param name="__MPU_REGIONS" value="8" caption="same as __MPU_S_REGIONS"/>
+        <param name="__MPU_S_REGIONS" value="8" caption="Number of Secure Memory Protection Regions"/>
+        <param name="__MTB_PRESENT" value="0" caption="No Macro Trace Buffer implemented"/>
+        <param name="__NVIC_PRIO_BITS" value="2" caption="Number of NVIC Priority Bits"/>
+        <param name="__SAUREGION_PRESENT" value="0" caption="Number of Security Attribute Unit Regions (No SAU)"/>
+        <param name="__SEC_ENABLED" value="0" caption="ARMv8-M security extensions (Trust Zone) enabled"/>
+        <param name="__SYST_NUM" value="2" caption="Number of SYSTICK, include secure and non-secure SYSTICK timers"/>
+        <param name="__VTOR_PRESENT" value="1" caption="Include Vector Table Offset Register"/>
+        <param name="__Vendor_SysTickConfig" value="0" caption="Standard SYSTICK used"/>
+        <param name="__WPT_NUM" value="2" caption="Number of watch point comparators"/>
+        <param name="POWER_DOMAIN" value="PD_CORE"/>
+        <param name="__ARCH_ARM" value="1"/>
+        <param name="__ARCH_ARM_CORTEX_M" value="1"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="03784" name2="cmp_ac_u2501_v2" version="2a0">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x4482A000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B" pad="PA07"/>
+              <signal group="AIN" index="1" function="B" pad="PA08"/>
+              <signal group="AIN" index="2" function="B" pad="PB00"/>
+              <signal group="AIN" index="3" function="B" pad="PB03"/>
+              <signal group="CMP" index="0" function="B" pad="PA01" ioset="1"/>
+              <signal group="CMP" index="1" function="B" pad="PA02" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="ATEST_IMPLEMENTED" value="1" caption="Defines if the ATEST register is implemented"/>
+              <param name="ATEST_SIZE" value="2" caption="Defines the number of effective bits in ATEST register"/>
+              <param name="DACVALUE_BIT" value="7" caption="Defines the number of bits in DACCTRLn.VALUE"/>
+              <param name="IO_INPUTS" value="4" caption="Defines the number of AC pair inputs connected to IO pins"/>
+              <param name="PAIRS" value="1" caption="Defines the number of AC pairs"/>
+              <param name="NUM_CMP" value="2" caption="Number of comparators"/>
+              <param name="LOAD_CALIB" value="0" caption="Defines if calibration is required"/>
+              <param name="GCLK_ID" value="34"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="21" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="40" caption="Instance index for AC"/>
+              <param name="MCLK_ID_APB" value="50" caption="Index for AC APB clock"/>
+              <param name="PAC_ID" value="40" caption="Index for AC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="03620" name2="adc_msh_ctrl_apb_v1" version="1b0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x44818000"/>
+            <signals>
+              <signal group="ADC0_AIN" index="0" function="B" pad="PA03"/>
+              <signal group="ADC0_AIN" index="1" function="B" pad="PA04"/>
+              <signal group="ADC0_AIN" index="2" function="B" pad="PA05"/>
+              <signal group="ADC0_AIN" index="3" function="B" pad="PA06"/>
+              <signal group="ADC0_AIN" index="4" function="B" pad="PA07"/>
+              <signal group="ADC0_AIN" index="5" function="B" pad="PA08"/>
+              <signal group="ADC0_AIN" index="6" function="B" pad="PA09"/>
+              <signal group="ADC0_AIN" index="7" function="B" pad="PB00"/>
+              <signal group="ADC0_AIN" index="8" function="B" pad="PB03"/>
+              <signal group="ADC0_AIN" index="9" function="B" pad="PB04"/>
+              <signal group="ADC0_AIN" index="10" function="B" pad="PB05"/>
+              <signal group="ADC0_AIN" index="11" function="B" pad="PB06"/>
+              <signal group="ADC0_ANN" index="0" function="B" pad="PA04"/>
+              <signal group="ADC0_ANN" index="2" function="B" pad="PA06"/>
+              <signal group="ADC0_ANN" index="4" function="B" pad="PA08"/>
+              <signal group="RES_TEST" index="0" function="ADC_TEST_PAD" pad="PD08"/>
+              <signal group="RES_TEST" index="1" function="ADC_TEST_PAD" pad="PD09"/>
+              <signal group="RES_TEST" index="2" function="ADC_TEST_PAD" pad="PD07"/>
+              <signal group="RES_TEST" index="3" function="ADC_TEST_PAD" pad="PA00"/>
+              <signal group="RES_TEST" index="4" function="ADC_TEST_PAD" pad="PA01"/>
+              <signal group="RES_TEST" index="5" function="ADC_TEST_PAD" pad="PA02"/>
+              <signal group="RES_TEST" index="6" function="ADC_TEST_PAD" pad="PA03"/>
+              <signal group="RES_TEST" index="7" function="ADC_TEST_PAD" pad="PA04"/>
+              <signal group="RES_TEST" index="8" function="ADC_TEST_PAD" pad="PB03"/>
+              <signal group="RES_TEST" index="9" function="ADC_TEST_PAD" pad="PB04"/>
+              <signal group="RES_TEST" index="10" function="ADC_TEST_PAD" pad="PB05"/>
+              <signal group="RES_TEST" index="11" function="ADC_TEST_PAD" pad="PB06"/>
+              <signal group="VREFH" function="VOLT_REF" pad="PA09"/>
+            </signals>
+            <parameters>
+              <param name="APB_FIFO_DEPTH" value="16" caption="--"/>
+              <param name="CHNSAR_NMBR1" value="16" caption="--"/>
+              <param name="CHNSAR_NMBR2" value="0" caption="--"/>
+              <param name="CHNSAR_NMBR3" value="0" caption="--"/>
+              <param name="CHNSAR_NMBR4" value="0" caption="--"/>
+              <param name="DCMP_NMBR" value="1" caption="--"/>
+              <param name="EARLY_INTR_PRESENT" value="1" caption="--"/>
+              <param name="FLTR_NMBR" value="1" caption="--"/>
+              <param name="OCP_ADDR_WIDTH" value="0" caption="--"/>
+              <param name="OCP_FIFO_DEPTH" value="0" caption="--"/>
+              <param name="OCP_PORT_PRESENT" value="0" caption="--"/>
+              <param name="SARCORE_NMBR" value="1" caption="--"/>
+              <param name="TRGS_NMBR" value="16" caption="--"/>
+              <param name="VREF_STARTUP_TIME" value="50" caption="--"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="DMAC_ID_PFFRDY" value="37"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="12" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="39" caption="Instance index for ADC"/>
+              <param name="MCLK_ID_APB" value="49" caption="Index for ADC APB clock"/>
+              <param name="PAC_ID" value="39" caption="Index for ADC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="AT" id="04932" name2="sec_anti_tamper_v1" version="1a0">
+          <instance name="AT">
+            <register-group name="AT" name-in-module="AT" address-space="base" offset="0x4500C000"/>
+            <parameters>
+              <param name="AT_TMPR_OSC_NUM_INV" value="881" caption="Number of inverters in tamper oscillator"/>
+              <param name="AT_CTRLAPRIV_IMPLEMENTED" value="1" caption="Implement the CTRLA.PRIV bit and privilege access filtering to registers.0 = CTRLA.PRIV not implemented1 = CTRLA.PRIV implemented"/>
+              <param name="AT_WPCTRL_IMPLEMENTED" value="0" caption="Implement the WPCTRL register for write protection. 1 = Use WPCTRL register is preset . Used to control write protection enable/disable. 0 = No WPCTRL sfr, only used in legacy device with a PACUse at_wrprot to control write protection enable/disable"/>
+              <param name="AT_WPCTRL_KEY" value="0x412054" caption="WPCTRL 24-bit key value. See register description for usage.Set to a unique value for each macro. ASCII of &quot;A T&quot;"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="6" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="45" caption="Instance index for AT"/>
+              <param name="MCLK_ID_APB" value="56" caption="Index for AT APB clock"/>
+              <param name="PAC_ID" value="45" caption="Index for AT registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="BROMC" id="04402" name2="prm_boot_ahb_v2" version="2a0">
+          <instance name="BROMC">
+            <register-group name="BROMC" name-in-module="BROMC" address-space="base" offset="0x44804000"/>
+            <parameters>
+              <param name="BROMC_PADDR_MSB" value="12" caption="--"/>
+              <param name="BROMC_PDATA_MSB" value="31" caption="--"/>
+              <param name="BROMC_PSTRB_MSB" value="3" caption="--"/>
+              <param name="BROMC_PPROT_MSB" value="5" caption="--"/>
+              <param name="BROMC_ROM_ADDR_MSB" value="13" caption="--"/>
+              <param name="BROMC_ROM_DATA_MSB" value="31" caption="--"/>
+              <param name="BROMC_ROM_DATA_SIZE" value="16384" caption="--"/>
+              <param name="BROMC_ROM_PRMWS_DEFAULT" value="0" caption="--"/>
+              <param name="BROMC_ROM_KEN" value="0" caption="--"/>
+              <param name="BROMC_ROM_CRC_EN" value="1" caption="--"/>
+              <param name="BROMC_ROM_SPLIT" value="0x3400" caption="(8K for PK code)  (Note: This parameter may change once boot and PK code sizes are known)"/>
+              <param name="BROMC_BOOTCRC_MODE" value="2" caption="--"/>
+              <param name="BROMC_FUSES_DATA_MSB" value="127" caption="See Flash Control Chapter for Values"/>
+              <param name="BROMC_FUSES_RDY_MSB" value="14" caption="See Flash Control Chapter for Values"/>
+              <param name="BROMC_FUSES_UCFG_ROWID" value="14" caption="See Chapter 5 CCFG Fuse map for Values"/>
+              <param name="BROMC_FUSES_UCFG_START" value="0" caption="See Chapter 5 CCFG Fuse map for Values"/>
+              <param name="BROMC_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="BROMC_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="BROMC_WPCTRL_KEY" value="0x42524F" caption="--"/>
+              <param name="BROMC_NUM_COOLDN_CYCLES" value="2" caption="--"/>
+              <param name="BROMC_NUM_WARMUP_CYCLES" value="2" caption="--"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="2" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="23" caption="Instance index for BROMC"/>
+              <param name="MCLK_ID_AHB" value="32" caption="Index for BROMC AHB clock"/>
+              <param name="MCLK_ID_APB" value="33" caption="Index for BROMC APB clock"/>
+              <param name="PAC_ID" value="23" caption="Index for BROMC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="CAN" id="05010" name2="can_fd_apb_v1" version="1a0">
+          <instance name="CAN0">
+            <register-group name="CAN0" name-in-module="CAN" address-space="base" offset="0x4402E000"/>
+            <signals>
+              <signal group="RX" function="H" pad="PC01" ioset="1"/>
+              <signal group="RX" function="H" pad="PD06" ioset="2"/>
+              <signal group="TX" function="H" pad="PC02" ioset="1"/>
+              <signal group="TX" function="H" pad="PD08" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="ECC_ERR_IMPLEMENTED" value="0" caption="ECC error implemented?"/>
+              <param name="INTERNAL_TB_SOF" value="3" caption="0: No SOF and no internal Time base, 1: SOF and no internal Time"/>
+              <param name="MSG_RAM_ADDR" value="0x20" caption="8-bits MSB"/>
+              <param name="NUMBER_TS" value="1" caption="0: 4 Timestamp reg, 1: 8 timestamp reg, 2: 16 timestamp reg"/>
+              <param name="PRIV_IMPLEMENTED" value="1" caption="Privilege access is implemented? 0: CTRLA.PRIV bit not implemented, 1: CTRLA.PRIV bit implemented"/>
+              <param name="RXD_SYNC_METHOD" value="0" caption="RXD Synchronization Method"/>
+              <param name="SYNT_TIMESTAMP" value="0x00000" caption="CAN_SYNT_TIMESTAMP[19:16]: CREL.YEAR reset value (BCD-coded),CAN_SYNT_TIMESTAMP[15:8]: CREL.MON reset value (BCD-coded), CAN_SYNT_TIMESTAMP[7:0]: CREL.DAY reset value (BCD-coded)"/>
+              <param name="WPCTRL_IMPLEMENTED" value="0" caption="Write protection control register implemented?"/>
+              <param name="WPCTRL_KEY" value="0x43414E" caption="Write protection 24 bit key"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="23" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="17" caption="Instance index for CAN0"/>
+              <param name="MCLK_ID_AHB" value="23" caption="Index for CAN0 AHB clock"/>
+              <param name="PAC_ID" value="17" caption="Index for CAN0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="CAN1">
+            <register-group name="CAN1" name-in-module="CAN" address-space="base" offset="0x44030000"/>
+            <signals>
+              <signal group="RX" function="H" pad="PA00" ioset="2"/>
+              <signal group="RX" function="H" pad="PC05" ioset="1"/>
+              <signal group="TX" function="H" pad="PA01" ioset="2"/>
+              <signal group="TX" function="H" pad="PC06" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="ECC_ERR_IMPLEMENTED" value="0" caption="ECC error implemented?"/>
+              <param name="INTERNAL_TB_SOF" value="3" caption="0: No SOF and no internal Time base, 1: SOF and no internal Time"/>
+              <param name="MSG_RAM_ADDR" value="0x20" caption="8-bits MSB"/>
+              <param name="NUMBER_TS" value="1" caption="0: 4 Timestamp reg, 1: 8 timestamp reg, 2: 16 timestamp reg"/>
+              <param name="PRIV_IMPLEMENTED" value="1" caption="Privilege access is implemented? 0: CTRLA.PRIV bit not implemented, 1: CTRLA.PRIV bit implemented"/>
+              <param name="RXD_SYNC_METHOD" value="0" caption="RXD Synchronization Method"/>
+              <param name="SYNT_TIMESTAMP" value="0x00000" caption="CAN_SYNT_TIMESTAMP[19:16]: CREL.YEAR reset value (BCD-coded),CAN_SYNT_TIMESTAMP[15:8]: CREL.MON reset value (BCD-coded), CAN_SYNT_TIMESTAMP[7:0]: CREL.DAY reset value (BCD-coded)"/>
+              <param name="WPCTRL_IMPLEMENTED" value="0" caption="Write protection control register implemented?"/>
+              <param name="WPCTRL_KEY" value="0x43414E" caption="Write protection 24 bit key"/>
+              <param name="GCLK_ID" value="7"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="24" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="18" caption="Instance index for CAN1"/>
+              <param name="MCLK_ID_AHB" value="24" caption="Index for CAN1 AHB clock"/>
+              <param name="PAC_ID" value="18" caption="Index for CAN1 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="CCL" id="03628" name2="cla_ccl_u2225_v2" version="2b0">
+          <instance name="CCL0">
+            <register-group name="CCL0" name-in-module="CCL" address-space="base" offset="0x4482E000"/>
+            <signals>
+              <signal group="IN" index="0" function="I" pad="PC01" ioset="1"/>
+              <signal group="IN" index="1" function="I" pad="PC02" ioset="1"/>
+              <signal group="IN" index="3" function="I" pad="PD00" ioset="1"/>
+              <signal group="IN" index="4" function="I" pad="PD01" ioset="1"/>
+              <signal group="IN" index="6" function="I" pad="PA00" ioset="1"/>
+              <signal group="IN" index="7" function="I" pad="PA01" ioset="1"/>
+              <signal group="IN" index="9" function="I" pad="PB05" ioset="1"/>
+              <signal group="IN" index="10" function="I" pad="PB06" ioset="1"/>
+              <signal group="OUT" index="0" function="I" pad="PC03" ioset="1"/>
+              <signal group="OUT" index="1" function="I" pad="PD08" ioset="1"/>
+              <signal group="OUT" index="2" function="I" pad="PA02" ioset="1"/>
+              <signal group="OUT" index="3" function="I" pad="PC00" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="LUT_NUM" value="4" caption="Number of LUT in a CCL"/>
+              <param name="GCLK_ID" value="36"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="23" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="42" caption="Instance index for CCL0"/>
+              <param name="MCLK_ID_APB" value="52" caption="Index for CCL0 APB clock"/>
+              <param name="PAC_ID" value="42" caption="Index for CCL0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="CCL1">
+            <register-group name="CCL1" name-in-module="CCL" address-space="base" offset="0x44830000"/>
+            <signals>
+              <signal group="IN" index="0" function="I" pad="PC04" ioset="1"/>
+              <signal group="IN" index="1" function="I" pad="PC05" ioset="1"/>
+              <signal group="IN" index="3" function="I" pad="PD06" ioset="1"/>
+              <signal group="IN" index="4" function="I" pad="PD07" ioset="1"/>
+              <signal group="IN" index="6" function="I" pad="PA09" ioset="1"/>
+              <signal group="IN" index="7" function="I" pad="PA06" ioset="1"/>
+              <signal group="IN" index="9" function="I" pad="PB04" ioset="1"/>
+              <signal group="IN" index="10" function="I" pad="PB03" ioset="1"/>
+              <signal group="OUT" index="0" function="I" pad="PC06" ioset="1"/>
+              <signal group="OUT" index="1" function="I" pad="PD09" ioset="1"/>
+              <signal group="OUT" index="2" function="I" pad="PA05" ioset="1"/>
+              <signal group="OUT" index="3" function="I" pad="PB00" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="LUT_NUM" value="4" caption="Number of LUT in a CCL"/>
+              <param name="GCLK_ID" value="37"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="24" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="43" caption="Instance index for CCL1"/>
+              <param name="MCLK_ID_APB" value="53" caption="Index for CCL1 APB clock"/>
+              <param name="PAC_ID" value="43" caption="Index for CCL1 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="CoreDebug" id="SYSTEM_IP" version="1.0.0">
+          <instance name="CoreDebug">
+            <register-group name="CoreDebug" name-in-module="CoreDebug" address-space="base" offset="0xE000EDF0"/>
+          </instance>
+        </module>
+        <module name="DIB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="DIB">
+            <register-group name="DIB" name-in-module="DIB" address-space="base" offset="0xE000EFB0"/>
+          </instance>
+        </module>
+        <module name="DMAC" id="dma_u2223_v2" name2="dma_u2223_v2" version="2i0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x44802000"/>
+            <parameters>
+              <param name="CH_NUM" value="8" caption="--"/>
+              <param name="EVIN_NUM" value="4" caption="--"/>
+              <param name="EVOUT_NUM" value="4" caption="--"/>
+              <param name="LVL_NUM" value="4" caption="--"/>
+              <param name="QOSCTRL_D_RESETVALUE" value="2" caption="--"/>
+              <param name="QOSCTRL_F_RESETVALUE" value="2" caption="--"/>
+              <param name="QOSCTRL_WRB_RESETVALUE" value="2" caption="--"/>
+              <param name="SPLIT_IRQ_NUM" value="4" caption="--"/>
+              <param name="TRIG_NUM" value="43" caption="--"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="1" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="21" caption="Instance index for DMAC"/>
+              <param name="MCLK_ID_AHB" value="28" caption="Index for DMAC AHB clock"/>
+              <param name="MCLK_ID_APB" value="29" caption="Index for DMAC APB clock"/>
+              <param name="PAC_ID" value="21" caption="Index for DMAC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="04465" name2="icd_dsu_v1" version="1a0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x44000000"/>
+            <signals>
+              <signal group="MSA" function="DSU_MSA" pad="PC05"/>
+              <signal group="SWCCSTAT" function="DSU_SWCCSTAT" pad="PC06"/>
+            </signals>
+            <parameters>
+              <param name="DSU_BASE_ADDR_INTERNAL" value="0x44000000" caption="--"/>
+              <param name="DSU_CPU_NUM" value="0" caption="--"/>
+              <param name="DSU_TZ_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DSU_CORESIGHT_REVISION" value="0x0" caption="--"/>
+              <param name="DSU_CORESIGHT_ENTRY" value="0xE00FF001 0x0 0x0 0x0" caption="--"/>
+              <param name="DSU_ID_MASKID" value="0x00" caption="Microchip Device Mask ID which provides the value for bits [15:8] of the ID - Part Number."/>
+              <param name="DSU_ID_VER" value="0x0" caption="ID Version Code provides the Mask Revision value for the device. Use metal changeable cells to configure this value."/>
+              <param name="DSU_SD_KEY" value="0xFFABAFD0" caption="--"/>
+              <param name="DSU_DCFG_MASK" value="0xFF0FFF0F 0x10FC7F80 0xC0800203 0x0 0x0 0x0 0x0 0x0" caption="--"/>
+              <param name="DSU_DAL1_VAL" value="0x55" caption="--"/>
+              <param name="DSU_DAL2_VAL" value="0xAA" caption="--"/>
+              <param name="DSU_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DSU_CTRLB_IMPLEMENTED_MASK" value="0x00000000" caption="--"/>
+              <param name="DSU_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="DSU_WPCTRL_KEY" value="0x445355" caption="--"/>
+              <param name="DSU_PRVKEY_IMPLEMENTED" value="0" caption="key sourced by PUF, not DSU"/>
+              <param name="DSU_BRCTRL_KEY" value="0x445355" caption="--"/>
+              <param name="DSU_TDID_DIE" value="0x00" caption="--"/>
+              <param name="DSU_TDID_MASK" value="0x00" caption="--"/>
+              <param name="DSU_SWCCS_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DSU_TESTMODE_IMPLEMENTED_MASK" value="0x000007FF 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DSU_FUSES_DATA_MSB" value="127" caption="128-bit bus"/>
+              <param name="DSU_FUSES_RDY_MSB" value="14" caption="15 bit fuse ready bus"/>
+              <param name="DSU_FUSES_ID_DEVID_START" value="24" caption="DEVID field is DSUCFG0[31:24]"/>
+              <param name="DSU_FUSES_ID_DEVID_SIZE" value="8" caption="--"/>
+              <param name="DSU_FUSES_ID_DEVID_ROWID" value="8" caption="DEVID on RowID Index = 8"/>
+              <param name="DSU_FUSES_DCFG_START" value="0 32 64 96 0 32 64 96" caption="--"/>
+              <param name="DSU_FUSES_DCFG_SIZE" value="32 32 32 32 32 32 32 32" caption="--"/>
+              <param name="DSU_FUSES_DCFG_ROWID" value="8 8 8 8 9 9 9 9" caption="DSUCFG7-0 = FCCFG39-32"/>
+              <param name="DMAC_ID_DCC0" value="1"/>
+              <param name="DMAC_ID_DCC1" value="2"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="0" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="0" caption="Instance index for DSU"/>
+              <param name="MCLK_ID_AHB" value="0" caption="Index for DSU AHB clock"/>
+              <param name="PAC_ID" value="0" caption="Index for DSU registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DWT" id="SYSTEM_IP" version="1.0.0">
+          <instance name="DWT">
+            <register-group name="DWT" name-in-module="DWT" address-space="base" offset="0xE0001000"/>
+            <parameters>
+              <param name="__WPT_NUM" value="2" caption="Number of DWT watchpoint comparators"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="03706" name2="int_eic_u2804_v1" version="1b0">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x44020000"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PC00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PC01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PD01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PC02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PD04"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PC03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PD05"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PB04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PC04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PD07"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PB05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PC05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PD08"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PC06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PD09"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="NMI" function="A" pad="PD00"/>
+            </signals>
+            <parameters>
+              <param name="EXTINT_NUM" value="16" caption="--"/>
+              <param name="NUMBER_OF_CONFIG_REGS" value="2" caption="=(EIC_EXTINT_NUM +7) / 8"/>
+              <param name="NUMBER_OF_INTERRUPTS" value="16" caption="=(EIC_EXTINT_NUM)"/>
+              <param name="SECURE_IMPLEMENTED" value="1" caption="--"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="16" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="13" caption="Instance index for EIC"/>
+              <param name="MCLK_ID_APB" value="13" caption="Index for EIC APB clock"/>
+              <param name="PAC_ID" value="13" caption="Index for EIC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="03601" name2="ptg_evsys_u2504_v2" version="2b0">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x44806000"/>
+            <parameters>
+              <param name="ASYNCHRONOUS_CHANNELS" value="0xFFFFF000" caption="--"/>
+              <param name="CHANNELS" value="12" caption="--"/>
+              <param name="CHANNELS_BITS" value="4" caption="=LEN( BIN(EVSYS_CHANNELS-1)) - 2)derived parameter"/>
+              <param name="GENERATORS" value="90" caption="Should be 90"/>
+              <param name="GENERATORS_BITS" value="7" caption="=LEN( BIN(EVSYS_GENERATORS-1)) - 2)derived parameter"/>
+              <param name="SECURE_IMPLEMENTED" value="0" caption="--"/>
+              <param name="SPLIT_IRQ_NUM" value="12" caption="--"/>
+              <param name="SYNCH_NUM" value="12" caption="--"/>
+              <param name="SYNCH_NUM_BITS" value="4" caption="=LEN( BIN(EVSYS_SYNCH_NUM-1)) - 2)derived parameter"/>
+              <param name="USERS" value="62" caption="Should be 62"/>
+              <param name="USERS_BITS" value="6" caption="=LEN( BIN(EVSYS_USERS-1)) - 2)derived parameter"/>
+              <param name="USERS_GROUPS" value="2" caption="=(EVSYS_USERS+31) / 32derived parameter"/>
+              <param name="GCLK_ID_CH0" value="8"/>
+              <param name="GCLK_ID_CH1" value="9"/>
+              <param name="GCLK_ID_CH2" value="10"/>
+              <param name="GCLK_ID_CH3" value="11"/>
+              <param name="GCLK_ID_CH4" value="12"/>
+              <param name="GCLK_ID_CH5" value="13"/>
+              <param name="GCLK_ID_CH6" value="14"/>
+              <param name="GCLK_ID_CH7" value="15"/>
+              <param name="GCLK_ID_CH8" value="16"/>
+              <param name="GCLK_ID_CH9" value="17"/>
+              <param name="GCLK_ID_CH10" value="18"/>
+              <param name="GCLK_ID_CH11" value="19"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="3" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="25" caption="Instance index for EVSYS"/>
+              <param name="MCLK_ID_APB" value="35" caption="Index for EVSYS APB clock"/>
+              <param name="PAC_ID" value="25" caption="Index for EVSYS registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FCR" id="04972" name2="pfm_ctrlr_apb_v2" version="2a0">
+          <instance name="FCR">
+            <register-group name="FCR" name-in-module="FCR" address-space="base" offset="0x44002000"/>
+            <parameters>
+              <param name="FCR_AHB_PORTS_NB" value="1" caption="--"/>
+              <param name="FCR_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCR_INTFLAGSET_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCR_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="FCR_WPCTRL_KEY" value="0x464352" caption="--"/>
+              <param name="FCR_PDMO_MSB" value="7" caption="--"/>
+              <param name="FCR_PFM_ADDR_BASE" value="0x0C000000" caption="--"/>
+              <param name="FCR_BFM_ADDR_BASE" value="0x08000000" caption="--"/>
+              <param name="FCR_CFM_ADDR_BASE" value="0x0A000000" caption="--"/>
+              <param name="FCR_FCD_ADDR_BASE" value="0x0B000000" caption="--"/>
+              <param name="FCR_VSS_CFG0_BASE" value="0x0A004000" caption="--"/>
+              <param name="FCR_VSS_CFG1_BASE" value="0x0A005000" caption="--"/>
+              <param name="FCR_VSS_CFG2_BASE" value="0" caption="--"/>
+              <param name="FCR_VSS_CFG3_BASE" value="0" caption="--"/>
+              <param name="FCR_VSS_CFG4_BASE" value="0" caption="--"/>
+              <param name="FCR_VSS_CFG5_BASE" value="0" caption="--"/>
+              <param name="FCR_CRC_PRESENT" value="1" caption="--"/>
+              <param name="FCR_FLT_PRESENT" value="1" caption="--"/>
+              <param name="FCR_ECC_PRESENT" value="1" caption="--"/>
+              <param name="FCR_PCHE_PRESENT" value="1" caption="--"/>
+              <param name="FCR_PCHE_AHB_NUM" value="0" caption="--"/>
+              <param name="FCR_PCHE_NUM_LINES" value="4" caption="--"/>
+              <param name="FCR_PCHE_TAG_MASK" value="0xF9F8000F" caption="--"/>
+              <param name="FCR_FUSES_READY_CYCLES" value="2" caption="--"/>
+              <param name="FCR_FUSES_DATA_CYCLES" value="4" caption="--"/>
+              <param name="FUSES_RDY_MSB" value="14" caption="--"/>
+              <param name="FUSES_DATA_MSB" value="127" caption="--"/>
+              <param name="FCR_HDATA_SIZE" value="32" caption="--"/>
+              <param name="FCR_F1RR_ADDR" value="0x0A007000" caption="--"/>
+              <param name="FCR_F2RR_ADDR" value="0" caption="Not applicable for QSilver"/>
+              <param name="FCR_RR_NUM_READS" value="1" caption="--"/>
+              <param name="FCR_NUM_RR_SFR" value="1" caption="--"/>
+              <param name="FCR_FFF_ADDR" value="0x0A007040" caption="--"/>
+              <param name="FCR_NOT_FFF_VALUE" value="0xA5A5A5A5" caption="--"/>
+              <param name="FCR_OTPLOCK_ADDR" value="0x0A007060" caption="--"/>
+              <param name="FCR_CAL_ADDR" value="0x0A007080" caption="--"/>
+              <param name="FCR_CAL_NUM_READS" value="14" caption="--"/>
+              <param name="FCR_PBUCFG_ADDR" value="0x0A003400" caption="--"/>
+              <param name="FCR_PERIOD_MIN" value="75" caption="--"/>
+              <param name="FCR_PERIOD_NOM" value="116" caption="--"/>
+              <param name="FCR_TCALH_NS" value="10000" caption="--"/>
+              <param name="PFM_NUM_PANELS" value="1" caption="--"/>
+              <param name="PFM_PNL_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_SYS_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_ROW_ADDR_MSB" value="9" caption="--"/>
+              <param name="PFM_PAGE_ADDR_MSB" value="11" caption="--"/>
+              <param name="PFM_PNL_DATA_MSB" value="139" caption="--"/>
+              <param name="PFM_DATA_MSB" value="127" caption="--"/>
+              <param name="PFM_PNL_WDATA_MSB" value="34" caption="Parameter only in DOS Rev C, not in RTL"/>
+              <param name="PFM_NUM_RR" value="2" caption="--"/>
+              <param name="PFM_SRHT_PRESENT" value="0" caption="--"/>
+              <param name="BFM_PNL_ADDR_MSB" value="13" caption="--"/>
+              <param name="BFM_SYS_ADDR_MSB" value="13" caption="--"/>
+              <param name="CFM_PNL_ADDR_MSB" value="14" caption="--"/>
+              <param name="CFM_SYS_ADDR_MSB" value="14" caption="--"/>
+              <param name="NVR_NUM_PAGES" value="12" caption="--"/>
+              <param name="PFM_TDPDH_NS" value="5000" caption="--"/>
+              <param name="PFM_TDPDS_NS" value="100" caption="--"/>
+              <param name="PFM_TMS_NS" value="5000" caption="See Note 2"/>
+              <param name="PFM_TMH_NS" value="100" caption="See Note 2"/>
+              <param name="PFM_TRT_NS" value="500" caption="--"/>
+              <param name="PFM_TRHR_NS" value="1000" caption="--"/>
+              <param name="PFM_TONWAIT_NS" value="6000" caption="--"/>
+              <param name="PFM_TLKCFG_NS" value="1000" caption="--"/>
+              <param name="PFM_ACC_NS" value="25" caption="--"/>
+              <param name="PFM_ACC_HT_NS" value="30" caption="--"/>
+              <param name="PFM_ACC_RECALL_NS" value="70" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="1" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="1" caption="Instance index for FCR"/>
+              <param name="MCLK_ID_AHB" value="1" caption="Index for FCR AHB clock"/>
+              <param name="PAC_ID" value="1" caption="Index for FCR registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FCW" id="04971" name2="pfm_ctrlw_apb_v2" version="2a0">
+          <instance name="FCW">
+            <register-group name="FCW" name-in-module="FCW" address-space="base" offset="0x44004000"/>
+            <parameters>
+              <param name="FCW_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCW_INTFLAGSET_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCW_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="FCW_WPCTRL_KEY" value="0x464357" caption="--"/>
+              <param name="FCW_PFM_ADDR_BASE" value="0x0C000000" caption="--"/>
+              <param name="FCW_BFM_ADDR_BASE" value="0x08000000" caption="--"/>
+              <param name="FCW_CFM_ADDR_BASE" value="0x0A000000" caption="--"/>
+              <param name="FCW_VSS_CFG0_BASE" value="0x0A004000" caption="--"/>
+              <param name="FCW_VSS_CFG1_BASE" value="0x0A005000" caption="--"/>
+              <param name="FCW_VSS_CFG2_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_VSS_CFG3_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_VSS_CFG4_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_VSS_CFG5_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_PWP_REGIONS" value="4" caption="--"/>
+              <param name="FCW_PWP_MSB" value="6" caption="--"/>
+              <param name="FCW_TAMPER_PRESENT" value="1" caption="--"/>
+              <param name="FCW_TAMPER_ADDR" value="0x0A003200" caption="--"/>
+              <param name="FCW_TAMPER_DATA" value="0x00000000" caption="--"/>
+              <param name="FCW_SD_USE_CPCNT" value="1" caption="--"/>
+              <param name="FCW_NUM_DATA_SFR" value="4" caption="(PFM_DATA_MSB+1)/32"/>
+              <param name="FCW_TPAR_MSB" value="3" caption="(PFM_PNL_DATA_MSB - PFM_DATA_MSB)/4"/>
+              <param name="FCW_PERIOD_MIN" value="75" caption="--"/>
+              <param name="FCW_PERIOD_NOM" value="116" caption="--"/>
+              <param name="PFM_SIZE" value="6" caption="--"/>
+              <param name="PFM_NUM_PANELS" value="1" caption="--"/>
+              <param name="PFM_PNL_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_SYS_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_ROW_ADDR_MSB" value="9" caption="--"/>
+              <param name="PFM_PAGE_ADDR_MSB" value="11" caption="--"/>
+              <param name="PFM_PNL_DATA_MSB" value="139" caption="--"/>
+              <param name="PFM_DATA_MSB" value="127" caption="--"/>
+              <param name="PFM_NUM_RR" value="2" caption="--"/>
+              <param name="BFM_PNL_ADDR_MSB" value="13" caption="--"/>
+              <param name="BFM_SYS_ADDR_MSB" value="13" caption="--"/>
+              <param name="CFM_PNL_ADDR_MSB" value="14" caption="--"/>
+              <param name="CFM_SYS_ADDR_MSB" value="14" caption="--"/>
+              <param name="NVR_NUM_PAGES" value="12" caption="--"/>
+              <param name="PFM_TWS_NS" value="5" caption="value irrelevant, must be &gt;0"/>
+              <param name="PFM_TWH_NS" value="5" caption="value irrelevant, must be &gt;0"/>
+              <param name="PFM_TNVS_NS" value="4000" caption="See Note 2"/>
+              <param name="PFM_TPROG_NS" value="18000" caption="See Note 3"/>
+              <param name="PFM_TPREPROG_NS" value="3000" caption="See Note 3"/>
+              <param name="PFM_TADS_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TADH_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TPGS_NS" value="8000" caption="See Note 2"/>
+              <param name="PFM_TPREPGH_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TPREPGS_NS" value="1000" caption="See Note 2"/>
+              <param name="PFM_TPGH_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TRCV_PROG_NS" value="5000" caption="See Note 2"/>
+              <param name="PFM_TRCV_ERASE_NS" value="50000" caption="See Note 2"/>
+              <param name="PFM_TERASE_NS" value="18000000" caption="See Note 3"/>
+              <param name="PFM_TERASE_RETRY_NS" value="4500000" caption="See Note 3"/>
+              <param name="PFM_TSCE_NS" value="18000000" caption="See Note 3"/>
+              <param name="PFM_TRW_NS" value="100" caption="See Note 2"/>
+              <param name="PFM_TPUMPENS" value="1000" caption="See Note 2"/>
+              <param name="PFM_TPUMPENH" value="100" caption="See Note 2"/>
+              <param name="PFM_TPUMP_CYCLES" value="1029" caption="See Note 2"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="2" caption="H2PB Peripheral ID"/>
+              <param name="FLASH_SIZE" value="524288"/>
+              <param name="INSTANCE_ID" value="2" caption="Instance index for FCW"/>
+              <param name="MCLK_ID_AHB" value="2" caption="Index for FCW AHB clock"/>
+              <param name="PAC_ID" value="2" caption="Index for FCW registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FPB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="FPB">
+            <register-group name="FPB" name-in-module="FPB" address-space="base" offset="0xE0002000"/>
+            <parameters>
+              <param name="__BKPT_NUM" value="4" caption="Number of FPB breakpoint comparators"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FREQM" id="03707" name2="clk_freqm_u2257_v3" version="3a0">
+          <instance name="FREQM">
+            <register-group name="FREQM" name-in-module="FREQM" address-space="base" offset="0x4400C000"/>
+            <parameters>
+              <param name="MSRCLK_NB" value="2" caption="Number of measured clock sources"/>
+              <param name="GCLK_ID_MSR0" value="2"/>
+              <param name="GCLK_ID_MSR1" value="3"/>
+              <param name="GCLK_ID_REF" value="4"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="6" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="10" caption="Instance index for FREQM"/>
+              <param name="MCLK_ID_APB" value="10" caption="Index for FREQM APB clock"/>
+              <param name="PAC_ID" value="10" caption="Index for FREQM registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="fuses" name2="fuses" version="1a0">
+          <instance name="FUSES">
+            <register-group name="FUSES_ROMCFG" name-in-module="FUSES_ROMCFG" address-space="base" offset="0x0A003000"/>
+<register-group name="FUSES_BOOTCFG1" name-in-module="FUSES_BOOTCFG1" address-space="base" offset="0x0A002000"/>
+<register-group name="FUSES_BOOTCFG1A" name-in-module="FUSES_BOOTCFG1" address-space="base" offset="0x0A000000"/>
+            <register-group name="FUSES_CALOTP" name-in-module="FUSES_CALOTP" address-space="base" offset="0x0A007000"/>
+          </instance>
+        </module>
+        <module name="GCLK" id="03588" name2="clk_gclk_u2122_v1" version="1d0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x44008000"/>
+            <signals>
+              <signal group="IO" index="0" function="K" pad="PB06"/>
+              <signal group="IO" index="0" function="K" pad="PD05"/>
+              <signal group="IO" index="1" function="K" pad="PC00"/>
+              <signal group="IO" index="1" function="K" pad="PC05"/>
+              <signal group="IO" index="1" function="K" pad="PD04"/>
+              <signal group="IO" index="2" function="K" pad="PC01"/>
+              <signal group="IO" index="3" function="K" pad="PC02"/>
+              <signal group="IO" index="4" function="K" pad="PC03"/>
+              <signal group="IO" index="5" function="K" pad="PC04"/>
+              <signal group="TST_GCLK" function="DSU_TEST_GCLK" pad="PC08"/>
+            </signals>
+            <parameters>
+              <param name="GEN_NUM" value="12" caption="--"/>
+              <param name="IO_NUM" value="8" caption="derived, # of &quot;1&quot; in GCLK_GEN_IO_EXIST"/>
+              <param name="MUXED_NUM" value="39" caption="Number of GCLK channels"/>
+              <param name="SOURCE_NUM" value="11" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="4" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="8" caption="Instance index for GCLK"/>
+              <param name="MCLK_ID_APB" value="8" caption="Index for GCLK APB clock"/>
+              <param name="PAC_ID" value="8" caption="Index for GCLK registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="H2PB" id="04947" name2="bus_ahb2apb_v1" version="1a0">
+          <instance name="H2PB0">
+            <register-group name="H2PB0" name-in-module="H2PB" address-space="base" offset="0x44032000"/>
+            <parameters>
+              <param name="H2PB_MST_N" value="2" caption="--"/>
+              <param name="H2PB_MST_MAX" value="1" caption="derived parameter"/>
+              <param name="H2PB_SLV_N" value="32" caption="--"/>
+              <param name="H2PB_SLV_MAX" value="31" caption="derived parameter"/>
+              <param name="H2PB_PADDR_IDXB" value="5" caption="derived parameter"/>
+              <param name="H2PB_PADDR_LSB" value="13" caption="--"/>
+              <param name="H2PB_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="H2PB_PAGE_SIZE" value="8192" caption="derived parameter"/>
+              <param name="H2PB_OWN_SFR_SLOT" value="25" caption="--"/>
+              <param name="H2PB_PADDR_SIZE" value="18" caption="local parameter"/>
+              <param name="H2PB_PADDR_MSB" value="17" caption="derived local parameter"/>
+              <param name="H2PB_BASE_MSB" value="13" caption="derived parameter"/>
+              <param name="H2PB_USE_HSEL" value="1" caption="--"/>
+              <param name="H2PB_USE_DPATH_PIPER" value="0" caption="1=&quot;all pipelined&quot;0=&quot;address pipelined&quot;"/>
+              <param name="H2PB_USE_EARLY_PREAD" value="0" caption="--"/>
+              <param name="H2PB_CLK_DIV_EN" value="0" caption="1=&quot;n:1 clock&quot;0=&quot;1:1 clock&quot;"/>
+              <param name="H2PB_USE_PSTRB_FOR_READS" value="1" caption="--"/>
+              <param name="H2PB_WPCTRL_KEY" value="0x504230" caption="--"/>
+              <param name="H2PB_NONSEC_INIT_VAL" value="0x00000001" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="25" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="19" caption="Instance index for H2PB0"/>
+              <param name="MCLK_ID_AHB" value="25" caption="Index for H2PB0 AHB clock"/>
+              <param name="MCLK_ID_APB" value="26" caption="Index for H2PB0 APB clock"/>
+              <param name="PAC_ID" value="19" caption="Index for H2PB0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="H2PB1">
+            <register-group name="H2PB1" name-in-module="H2PB" address-space="base" offset="0x44838000"/>
+            <parameters>
+              <param name="H2PB_MST_N" value="2" caption="--"/>
+              <param name="H2PB_MST_MAX" value="1" caption="derived parameter"/>
+              <param name="H2PB_SLV_N" value="32" caption="--"/>
+              <param name="H2PB_SLV_MAX" value="31" caption="derived parameter"/>
+              <param name="H2PB_PADDR_IDXB" value="5" caption="derived parameter"/>
+              <param name="H2PB_PADDR_LSB" value="13" caption="--"/>
+              <param name="H2PB_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="H2PB_PAGE_SIZE" value="8192" caption="derived parameter"/>
+              <param name="H2PB_OWN_SFR_SLOT" value="28" caption="--"/>
+              <param name="H2PB_PADDR_SIZE" value="18" caption="local parameter"/>
+              <param name="H2PB_PADDR_MSB" value="17" caption="derived local parameter"/>
+              <param name="H2PB_BASE_MSB" value="13" caption="derived parameter"/>
+              <param name="H2PB_USE_HSEL" value="1" caption="--"/>
+              <param name="H2PB_USE_DPATH_PIPER" value="0" caption="1=&quot;all pipelined&quot;0=&quot;address pipelined&quot;"/>
+              <param name="H2PB_USE_EARLY_PREAD" value="0" caption="--"/>
+              <param name="H2PB_CLK_DIV_EN" value="0" caption="1=&quot;n:1 clock&quot;0=&quot;1:1 clock&quot;"/>
+              <param name="H2PB_USE_PSTRB_FOR_READS" value="1" caption="--"/>
+              <param name="H2PB_WPCTRL_KEY" value="0x504231" caption="--"/>
+              <param name="H2PB_NONSEC_INIT_VAL" value="0x00000000" caption="--"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="28" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="46" caption="Instance index for H2PB1"/>
+              <param name="MCLK_ID_AHB" value="57" caption="Index for H2PB1 AHB clock"/>
+              <param name="MCLK_ID_APB" value="58" caption="Index for H2PB1 APB clock"/>
+              <param name="PAC_ID" value="46" caption="Index for H2PB1 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="H2PB2">
+            <register-group name="H2PB2" name-in-module="H2PB" address-space="base" offset="0x4500E000"/>
+            <parameters>
+              <param name="H2PB_MST_N" value="1" caption="--"/>
+              <param name="H2PB_MST_MAX" value="0" caption="derived parameter"/>
+              <param name="H2PB_SLV_N" value="8" caption="--"/>
+              <param name="H2PB_SLV_MAX" value="7" caption="derived parameter"/>
+              <param name="H2PB_PADDR_IDXB" value="3" caption="derived parameter"/>
+              <param name="H2PB_PADDR_LSB" value="13" caption="--"/>
+              <param name="H2PB_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="H2PB_PAGE_SIZE" value="8192" caption="derived parameter"/>
+              <param name="H2PB_OWN_SFR_SLOT" value="7" caption="--"/>
+              <param name="H2PB_PADDR_SIZE" value="16" caption="local parameter"/>
+              <param name="H2PB_PADDR_MSB" value="15" caption="derived local parameter"/>
+              <param name="H2PB_BASE_MSB" value="15" caption="derived parameter"/>
+              <param name="H2PB_USE_HSEL" value="1" caption="--"/>
+              <param name="H2PB_USE_DPATH_PIPER" value="1" caption="1=&quot;all pipelined&quot;0=&quot;address pipelined&quot;"/>
+              <param name="H2PB_USE_EARLY_PREAD" value="0" caption="--"/>
+              <param name="H2PB_CLK_DIV_EN" value="1" caption="1=&quot;n:1 clock&quot;0=&quot;1:1 clock&quot;"/>
+              <param name="H2PB_USE_PSTRB_FOR_READS" value="1" caption="--"/>
+              <param name="H2PB_WPCTRL_KEY" value="0x504232" caption="--"/>
+              <param name="H2PB_NONSEC_INIT_VAL" value="0x00" caption="--"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="7" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="47" caption="Instance index for H2PB2"/>
+              <param name="MCLK_ID_AHB" value="59" caption="Index for H2PB2 AHB clock"/>
+              <param name="MCLK_ID_APB" value="60" caption="Index for H2PB2 APB clock"/>
+              <param name="PAC_ID" value="47" caption="Index for H2PB2 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIX2" id="bus_hmatrix2_v5" name2="bus_hmatrix2_v5" version="5f0">
+          <instance name="HMATRIX2">
+            <register-group name="HMATRIX2" name-in-module="HMATRIX2" address-space="base" offset="0x44010000"/>
+            <parameters>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="8" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="22" caption="Instance index for HMATRIX2"/>
+              <param name="MCLK_ID_AHB" value="30" caption="Index for HMATRIX2 AHB clock"/>
+              <param name="MCLK_ID_APB" value="31" caption="Index for HMATRIX2 APB clock"/>
+              <param name="PAC_ID" value="22" caption="Index for HMATRIX2 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ICB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="ICB">
+            <register-group name="ICB" name-in-module="ICB" address-space="base" offset="0xE000E000"/>
+          </instance>
+        </module>
+        <module name="MCLK" id="04158" name2="clk_mclk_v1" version="1a0">
+          <instance name="MCLK">
+            <register-group name="MCLK" name-in-module="MCLK" address-space="base" offset="0x4400A000"/>
+            <parameters>
+              <param name="MCLK_SYNC_EDGES" value="1" caption="--"/>
+              <param name="MCLK_DIV_CLK_NUM" value="3" caption="one for all other, one for H2PB2 domain, one for MBISTINTF"/>
+              <param name="MCLK_CKDIV_REGS_BITS" value="8" caption="--"/>
+              <param name="MCLK_CKDIV_RESET_VALUE" value="0x1 0x2 0x4 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1" caption="values must be binary divisor numberunused divisors must be 8'h1"/>
+              <param name="MCLK_CKDIV_WRLOCK" value="0x00000000" caption="--"/>
+              <param name="MCLK_CPU_CLK_DIVIDER" value="0" caption="--"/>
+              <param name="MCLK_CPU_CLK_IDLE" value="0" caption="--"/>
+              <param name="MCLK_CPU_CLK_OFFDLY" value="2" caption="--"/>
+              <param name="MCLK_CPU_CLK_ONDLY" value="0" caption="--"/>
+              <param name="MCLK_SYS_CLK_DIVIDER" value="0" caption="--"/>
+              <param name="MCLK_SYS_CLK_OFFDLY" value="2" caption="--"/>
+              <param name="MCLK_CLKMSK_NUM" value="65" caption="--"/>
+              <param name="MCLK_CKPER_IMPLEMENTED" value="0xFFFFFFFF 0xFFFFFFFF 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_RSTVAL" value="0xFFEEFFFF 0xFFFFFFFF 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_DIVIDER" value="0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0" caption="--"/>
+              <param name="MCLK_CKPER_REQEXISTS" value="0xD9FFFFFF 0xE1FFFFFF 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_MASTER" value="0x11800004 0x40400000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_WILLRISE" value="0x00080000 0x10000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="JTAG_IMPLEMENTED" value="1" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="5" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="9" caption="Instance index for MCLK"/>
+              <param name="MCLK_ID_APB" value="9" caption="Index for MCLK APB clock"/>
+              <param name="PAC_ID" value="9" caption="Index for MCLK registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MCRAMC" id="04921" name2="drm_mcramc_v5" version="5b0">
+          <instance name="MCRAMC">
+            <register-group name="MCRAMC" name-in-module="MCRAMC" address-space="base" offset="0x4402C000"/>
+            <parameters>
+              <param name="AHB_CLOCK_ENABLE" value="0" caption="--"/>
+              <param name="AHB_ECC" value="1" caption="--"/>
+              <param name="AHB_PORTS_NB" value="8" caption="--"/>
+              <param name="AHB_READ_PREBUFFERING" value="0" caption="--"/>
+              <param name="AHB_REQUEST_ISOLATION_REGISTER" value="0" caption="--"/>
+              <param name="ARBITRATION_TYPE" value="2" caption="Parameter should be &quot;ENUM_HOPSCOTCH&quot;Fix for text parameter in ConstellationCONST_DEV-1173"/>
+              <param name="BIT_STROBE_RAM" value="0" caption="parameter n/a if STORE_BYTE_STROBE=0"/>
+              <param name="CHANNELS_NB" value="2" caption="--"/>
+              <param name="ECC_SYNDROM_REGISTER" value="0" caption="--"/>
+              <param name="HADDR_READ_ISOLATION_REGISTER" value="0" caption="--"/>
+              <param name="HRDATA_ISOLATION_CONFIGURABLE" value="1" caption="--"/>
+              <param name="HRDATA_ISOLATION_DEFAULT" value="0" caption="default to 0 wait states"/>
+              <param name="MCRAMC_CLK_GATER" value="0" caption="--"/>
+              <param name="MCRAMC_PADDR_SIZE" value="13" caption="--"/>
+              <param name="MEMORY_AUTO_CORRECTION" value="1" caption="--"/>
+              <param name="MEMORY_ENABLE_POLARITY" value="0" caption="--"/>
+              <param name="MW_CLOCK_ENABLE" value="0" caption="--"/>
+              <param name="MW_DATA_SIZE" value="32" caption="--"/>
+              <param name="MW_PORT_SLICES_NB" value="0" caption="--"/>
+              <param name="M0_CLOCK_ENABLE" value="0" caption="--"/>
+              <param name="M0_DATA_SIZE" value="32" caption="--"/>
+              <param name="M0_HYBRID_READ_WRITE_ACCESS" value="0" caption="--"/>
+              <param name="M0_PORT_SLICES_NB" value="0" caption="--"/>
+              <param name="PRIVILEGED_BIT_CHECK" value="1" caption="--"/>
+              <param name="RAM_ADD_SIZE" value="14" caption="--"/>
+              <param name="RAM_AHB_ADDRESS_OFFSET" value="0" caption="--"/>
+              <param name="RAM_ERASE" value="0" caption="--"/>
+              <param name="STORE_BYTE_STROBE" value="0" caption="--"/>
+              <param name="ULTRA" value="1" caption="--"/>
+              <param name="WP_KEY" value="0x465852" caption="&quot;FXR&quot;"/>
+              <param name="WRITE_ENABLE_POLARITY" value="0" caption="--"/>
+              <param name="WRITE_ENABLE_USED" value="1" caption="--"/>
+              <param name="WRITE_MASK_POLARITY" value="0" caption="--"/>
+              <param name="WRITE_PROTECT_REGISTER" value="0" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="22" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="16" caption="Instance index for MCRAMC"/>
+              <param name="MCLK_ID_APB" value="21" caption="Index for MCRAMC APB clock"/>
+              <param name="MCLK_ID_AHB" value="22" caption="Index for MCRAMC AHB clock"/>
+              <param name="PAC_ID" value="16" caption="Index for MCRAMC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MPU" id="SYSTEM_IP" version="1.0.0">
+          <instance name="MPU">
+            <register-group name="MPU" name-in-module="MPU" address-space="base" offset="0xE000ED90"/>
+            <parameters>
+              <param name="__MPU_REGIONS" value="8" caption="Number of MPU regions"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVIC" id="SYSTEM_IP" version="1.0.0">
+          <instance name="NVIC">
+            <register-group name="NVIC" name-in-module="NVIC" address-space="base" offset="0xE000E100"/>
+            <parameters>
+              <param name="NUM_IRQ" value="141" caption="Number of interrupt request lines"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="OSC32KCTRL" id="03717" name2="osc_osc32kctrl_u2400_v2" version="2a0">
+          <instance name="OSC32KCTRL">
+            <register-group name="OSC32KCTRL" name-in-module="OSC32KCTRL" address-space="base" offset="0x45008000"/>
+            <signals>
+              <signal group="CLKIN32" index="32" function="XOSC32K_XIN32_AMODE" pad="PB01"/>
+              <signal group="XIN32" index="32" function="XOSC32K_XIN32" pad="PB01"/>
+              <signal group="XOUT32" index="32" function="XOSC32K_XOUT32" pad="PB02"/>
+            </signals>
+            <parameters>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="4" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="7" caption="Instance index for OSC32KCTRL"/>
+              <param name="MCLK_ID_APB" value="7" caption="Index for OSC32KCTRL APB clock"/>
+              <param name="PAC_ID" value="7" caption="Index for OSC32KCTRL registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="OSCCTRL" id="03718" name2="osc_oscctrl_u2401_v2" version="2b0">
+          <instance name="OSCCTRL">
+            <register-group name="OSCCTRL" name-in-module="OSCCTRL" address-space="base" offset="0x44006000"/>
+            <signals>
+              <signal group="CLKIN" function="XOSC_XIN_AMODE" pad="PD05"/>
+              <signal group="XIN" function="XOSC_XIN" pad="PD05"/>
+              <signal group="XOUT" function="XOSC_XOUT" pad="PD04"/>
+            </signals>
+            <parameters>
+              <param name="DFLL48M_ATEST_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DFLL48M_ATEST_SIZE" value="8" caption="--"/>
+              <param name="DFLL48M_IS_STARTUP_OSCILLATOR" value="1" caption="--"/>
+              <param name="DFLL48M_RC48MCAL0_PORVAL" value="0x00000000" caption="--"/>
+              <param name="DIV_8MHZ_NUM" value="2" caption="--"/>
+              <param name="FRACDIVS_NUM" value="0" caption="--"/>
+              <param name="FRACDIV_DIVIDER_RESET_VAL" value="0" caption="--"/>
+              <param name="FRACDIV_PLLSRC" value="0" caption="--"/>
+              <param name="PLLS_NUM" value="1" caption="--"/>
+              <param name="PLL0_OUTPUTS_NUM" value="5" caption="--"/>
+              <param name="PLL1_OUTPUTS_NUM" value="0" caption="--"/>
+              <param name="USBHS_NUM" value="1" caption="should be 0, but IP has bug"/>
+              <param name="XOSC_ATEST_IMPLEMENTED" value="1" caption="--"/>
+              <param name="XOSC_ATEST_SIZE" value="4" caption="--"/>
+              <param name="XOSC_CFD_CLK_SELECT_SIZE" value="4" caption="--"/>
+              <param name="XOSC_CFD_HAS_RETENTION" value="0" caption="--"/>
+              <param name="GCLK_ID_DFLL48M" value="0"/>
+              <param name="GCLK_ID_PLL" value="1"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="3" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="6" caption="Instance index for OSCCTRL"/>
+              <param name="MCLK_ID_APB" value="6" caption="Index for OSCCTRL APB clock"/>
+              <param name="PAC_ID" value="6" caption="Index for OSCCTRL registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PAC" id="04298" name2="sec_pac_apb_v1" version="1a0">
+          <instance name="PAC">
+            <register-group name="PAC" name-in-module="PAC" address-space="base" offset="0x44022000"/>
+            <parameters>
+              <param name="PAC_PER_WRPROT_MASK" value="0xFFFFFFFF 0x0003FFFF 0x00000000 0x00000000" caption="Peripheral implemented mask. If PAC_PER_WRPROT_MASK[x]=1 then the PAC implements an SFR bit in INTFLAG, STATUS, and LOCK with the location of &lt;REG&gt;(x/32)[x mod 32]"/>
+              <param name="PAC_STATUS_RESET_VALUE" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="WRP STATUS Reset Value for Peripherals. On reset STATUS(x/32)[x mod 32]=PAC_STATUS_RESET_VALUE[x]The reset value for each peripheral should always be 0. The parameter exists if there is an unforeseen circumstance requiring it to be 1. Test blocks are not one of them as they are protected by dsu_test_mode."/>
+              <param name="PAC_LOCK_RESET_VALUE" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="PAC_ERRORS_INBAND" value="1" caption="--"/>
+              <param name="PAC_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="PAC_INTFLAGSET_IMPLEMENTED" value="0" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="17" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="14" caption="Instance index for PAC"/>
+              <param name="MCLK_ID_APB" value="14" caption="Index for PAC APB clock"/>
+              <param name="PAC_ID" value="14" caption="Index for PAC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PDM" id="test_pdm_v1" name2="test_pdm_v1" version="1.0.0">
+          <instance name="PDM">
+            <signals>
+              <signal group="PDMDIS" function="TST_DIG" pad="PDMDIS"/>
+              <signal group="PDMI" index="0" function="PDMI_TEST" pad="PD07"/>
+              <signal group="PDMI" index="1" function="PDMI_TEST" pad="PD08"/>
+              <signal group="PDMI" index="2" function="PDMI_TEST" pad="PD09"/>
+              <signal group="PDMI" index="3" function="PDMI_TEST" pad="PA00"/>
+              <signal group="PDMO" index="0" function="PDMO_LV_TEST" pad="PB03"/>
+              <signal group="PDMO" index="1" function="PDMO_LV_TEST" pad="PB04"/>
+              <signal group="PDMO" index="2" function="PDMO_LV_TEST" pad="PB05"/>
+              <signal group="PDMO" index="3" function="PDMO_LV_TEST" pad="PB06"/>
+              <signal group="PDMO" index="4" function="PDMO_LV_TEST" pad="PC00"/>
+              <signal group="PDMO" index="5" function="PDMO_LV_TEST" pad="PC01"/>
+              <signal group="PDMO" index="6" function="PDMO_LV_TEST" pad="PC02"/>
+              <signal group="PDMO" index="7" function="PDMO_LV_TEST" pad="PC03"/>
+              <signal group="PDMO0_MV" function="PDMO_MV_TEST" pad="PB03"/>
+              <signal group="PDMO1_MV" function="PDMO_MV_TEST" pad="PB04"/>
+              <signal group="PDMO2_MV" function="PDMO_MV_TEST" pad="PB05"/>
+              <signal group="PDMO3_MV" function="PDMO_MV_TEST" pad="PB06"/>
+              <signal group="PDMO4_MV" function="PDMO_MV_TEST" pad="PC00"/>
+              <signal group="PDMO5_MV" function="PDMO_MV_TEST" pad="PC01"/>
+              <signal group="PDMO6_MV" function="PDMO_MV_TEST" pad="PC02"/>
+              <signal group="PDMO7_MV" function="PDMO_MV_TEST" pad="PC03"/>
+            </signals>
+          </instance>
+        </module>
+        <module name="PM" id="03926" name2="pwr_rpmu_pm_v1" version="1c0">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x45000000"/>
+            <parameters>
+              <param name="BACKUP_IMPLEMENTED" value="1" caption="--"/>
+              <param name="PD_NUM" value="1" caption="Number of Switchable Power Domains2 total domains (PD_CORE_SW and PD_CORE_BU)"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="0" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="3" caption="Instance index for PM"/>
+              <param name="MCLK_ID_APB" value="3" caption="Index for PM APB clock"/>
+              <param name="PAC_ID" value="3" caption="Index for PM registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PORT" id="03720" name2="gpio_port_u2210_v4" version="4a0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x44800000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="32" function="default" pad="PB00"/>
+              <signal group="P" index="33" function="default" pad="PB01"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="36" function="default" pad="PB04"/>
+              <signal group="P" index="37" function="default" pad="PB05"/>
+              <signal group="P" index="38" function="default" pad="PB06"/>
+              <signal group="P" index="64" function="default" pad="PC00"/>
+              <signal group="P" index="65" function="default" pad="PC01"/>
+              <signal group="P" index="66" function="default" pad="PC02"/>
+              <signal group="P" index="67" function="default" pad="PC03"/>
+              <signal group="P" index="68" function="default" pad="PC04"/>
+              <signal group="P" index="69" function="default" pad="PC05"/>
+              <signal group="P" index="70" function="default" pad="PC06"/>
+              <signal group="P" index="71" function="default" pad="PC07"/>
+              <signal group="P" index="72" function="default" pad="PC08"/>
+              <signal group="P" index="96" function="default" pad="PD00"/>
+              <signal group="P" index="97" function="default" pad="PD01"/>
+              <signal group="P" index="98" function="default" pad="PD02"/>
+              <signal group="P" index="99" function="default" pad="PD03"/>
+              <signal group="P" index="100" function="default" pad="PD04"/>
+              <signal group="P" index="101" function="default" pad="PD05"/>
+              <signal group="P" index="102" function="default" pad="PD06"/>
+              <signal group="P" index="103" function="default" pad="PD07"/>
+              <signal group="P" index="104" function="default" pad="PD08"/>
+              <signal group="P" index="105" function="default" pad="PD09"/>
+            </signals>
+            <parameters>
+              <param name="AHB_IMPLEMENTED" value="0" caption="No AHB bus"/>
+              <param name="BITS" value="117" caption="--"/>
+              <param name="DIR_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DIR_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="DIR RegistersImplemented"/>
+              <param name="DRVSTR" value="0" caption="No DRVSTR bits"/>
+              <param name="DRVSTR_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DRVSTR_IMPLEMENTED" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="PINCFG.DRVSTR0RegistersImplemented"/>
+              <param name="DRVSTR1_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DRVSTR1_IMPLEMENTED" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="PINCFG.DRVSTR1RegistersImplemented"/>
+              <param name="EVENT_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="Event RegistersImplemented"/>
+              <param name="EV_NUM" value="4" caption="--"/>
+              <param name="GROUPS" value="4" caption="--"/>
+              <param name="HADDR_MSB" value="31" caption="--"/>
+              <param name="INEN_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="INEN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.INENRegistersImplemented"/>
+              <param name="IOBUS_IMPLEMENTED" value="0" caption="No IOBUS"/>
+              <param name="MSB" value="116" caption="PORT_BITS-1"/>
+              <param name="NONSEC_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="NONSEC_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="NONSECRegistersImplemented"/>
+              <param name="ODRAIN" value="1" caption="--"/>
+              <param name="ODRAIN_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="ODRAIN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.ODRAINRegistersImplemented"/>
+              <param name="OUT_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="OUT_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="OUT RegistersImplemented"/>
+              <param name="PIN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="Port PinsImplemented"/>
+              <param name="PMUXBIT0_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x0000000C" caption="--"/>
+              <param name="PMUXBIT0_IMPLEMENTED" value="0x001FFFFF 0x0003FFF9 0x000FFE7F 0x001FFFC3" caption="Bit 0 of PMUX field"/>
+              <param name="PMUXBIT1_DEFAULT_VAL" value="0x00000000 0x00000000 0x000001E0 0x0000000C" caption="--"/>
+              <param name="PMUXBIT1_IMPLEMENTED" value="0x0007FFFF 0x000387F9 0x000FFE7F 0x001FFFF3" caption="Bit 1 of PMUX field"/>
+              <param name="PMUXBIT2_DEFAULT_VAL" value="0x00000000 0x00000000 0x000001E0 0x0000000C" caption="--"/>
+              <param name="PMUXBIT2_IMPLEMENTED" value="0x001BFFFF 0x00007FF9 0x0000067F 0x00003FC3" caption="Bit 2 of PMUX field"/>
+              <param name="PMUXBIT3_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="PMUXBIT3_IMPLEMENTED" value="0x001FFFFF 0x0003FFF9 0x000BFE7F 0x001FDFF3" caption="Bit 3 of PMUX field"/>
+              <param name="PMUXEN_DEFAULT_VAL" value="0x00000000 0x00000000 0x000001E0 0x00000000" caption="--"/>
+              <param name="PMUXEN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.PMUXEN bit"/>
+              <param name="PPP_IMPLEMENTED" value="0" caption="No IOBUS2"/>
+              <param name="PULLEN_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="PULLEN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.PULLENRegistersImplemented"/>
+              <param name="SECURE_IMPLEMENTED" value="1" caption="Mixed Secure Enabled"/>
+              <param name="SLEWLIM" value="2" caption="Number of SLEWLIM bit"/>
+              <param name="SLEWLIM_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="SLEWLIM_IMPLEMENTED" value="0x0007C07F 0x00038078 0x000FF87F 0x001FCFC3" caption="PINCFG.SLEWLIM0RegistersImplemented"/>
+              <param name="SLEWLIM1_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="SLEWLIM1_IMPLEMENTED" value="0x0007C07F 0x00038078 0x000FF87F 0x001FCFC3" caption="PINCFG.SLEWLIM1RegistersImplemented"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="0" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="20" caption="Instance index for PORT"/>
+              <param name="MCLK_ID_APB" value="27" caption="Index for PORT APB clock"/>
+              <param name="PAC_ID" value="20" caption="Index for PORT registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="04743" name2="afe_ptc_ctrl_apb_plrs_v1" version="1a0">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x4482C000"/>
+            <signals>
+              <signal group="PTCXY" index="0" function="P" pad="PD06"/>
+              <signal group="PTCXY" index="1" function="P" pad="PD07"/>
+              <signal group="PTCXY" index="2" function="P" pad="PD08"/>
+              <signal group="PTCXY" index="3" function="P" pad="PD09"/>
+              <signal group="PTCXY" index="4" function="P" pad="PA00"/>
+              <signal group="PTCXY" index="5" function="P" pad="PA01"/>
+              <signal group="PTCXY" index="6" function="P" pad="PA02"/>
+              <signal group="PTCXY" index="7" function="P" pad="PA03"/>
+              <signal group="PTCXY" index="8" function="P" pad="PA04"/>
+              <signal group="PTCXY" index="9" function="P" pad="PA05"/>
+              <signal group="PTCXY" index="10" function="P" pad="PA06"/>
+              <signal group="PTCXY" index="11" function="P" pad="PA07"/>
+              <signal group="PTCXY" index="12" function="P" pad="PA08"/>
+              <signal group="PTCXY" index="13" function="P" pad="PA09"/>
+              <signal group="PTCXY" index="14" function="P" pad="PB00"/>
+              <signal group="PTCXY" index="15" function="P" pad="PB03"/>
+              <signal group="PTCXY" index="16" function="P" pad="PB04"/>
+              <signal group="PTCXY" index="17" function="P" pad="PB05"/>
+              <signal group="PTCXY" index="18" function="P" pad="PB06"/>
+              <signal group="PTCXY" index="19" function="P" pad="PC00"/>
+              <signal group="PTCXY" index="20" function="P" pad="PC01"/>
+              <signal group="PTCXY" index="21" function="P" pad="PC02"/>
+              <signal group="DRV" index="0" function="P" pad="PD06"/>
+              <signal group="DRV" index="1" function="P" pad="PD07"/>
+              <signal group="DRV" index="2" function="P" pad="PD08"/>
+              <signal group="DRV" index="3" function="P" pad="PD09"/>
+              <signal group="DRV" index="4" function="P" pad="PA00"/>
+              <signal group="DRV" index="5" function="P" pad="PA01"/>
+              <signal group="DRV" index="6" function="P" pad="PA02"/>
+              <signal group="DRV" index="7" function="P" pad="PA03"/>
+              <signal group="DRV" index="8" function="P" pad="PA04"/>
+              <signal group="DRV" index="9" function="P" pad="PA05"/>
+              <signal group="DRV" index="10" function="P" pad="PA06"/>
+              <signal group="DRV" index="11" function="P" pad="PA07"/>
+              <signal group="DRV" index="12" function="P" pad="PA08"/>
+              <signal group="DRV" index="13" function="P" pad="PA09"/>
+              <signal group="DRV" index="14" function="P" pad="PB00"/>
+              <signal group="DRV" index="15" function="P" pad="PB03"/>
+              <signal group="DRV" index="16" function="P" pad="PB04"/>
+              <signal group="DRV" index="17" function="P" pad="PB05"/>
+              <signal group="DRV" index="18" function="P" pad="PB06"/>
+              <signal group="DRV" index="19" function="P" pad="PC00"/>
+              <signal group="DRV" index="20" function="P" pad="PC01"/>
+              <signal group="DRV" index="21" function="P" pad="PC02"/>
+              <signal group="ECI" index="0" function="P" pad="PC03"/>
+              <signal group="ECI" index="1" function="P" pad="PC04"/>
+            </signals>
+            <parameters>
+              <param name="PTC_PDATA_MSB" value="31" caption="APB Data Bus Size MSB"/>
+              <param name="PTC_PADDR_MSB" value="12" caption="APB Address Bus Size MSB"/>
+              <param name="PTC_PADDR_SIZE" value="13" caption="Number of bits of the paddr input busPossible Values = PTC_PADDR_MSB -1"/>
+              <param name="PTC_LINES_NUM" value="36" caption="Number of PTC lines desired (0 to 64)"/>
+              <param name="PTC_CAL_IMPLEMENTED" value="1" caption="Defines if the CALIB register is implemented (1 = implemented)"/>
+              <param name="PTC_CAL_SIZE" value="16" caption="Defines Bitfield size for CALIB register"/>
+              <param name="PTC_CAL_PORVAL" value="0x00000000" caption="Defines the CALIB register reset value after POR0x00000000 to 0xFFFFFFFF"/>
+              <param name="PTC_ATEST_IMPLEMENTED" value="1" caption="Defines if the ATEST register is implemented (1 = implemented)"/>
+              <param name="PTC_ATEST_SIZE" value="8" caption="Defines the number of effective bits in ATEST register"/>
+              <param name="PTC_WPCTRL_IMPLEMENTED" value="0" caption="Implement the WPCTRL register for write protection.0 = Use apb_ptc_wrprot to control write protection enable/disable1 = Use WPCTRL register to control write protection enable/disable."/>
+              <param name="PTC_PRIV_IMPLEMENTED" value="1" caption="Implement the PRIV register for privilege/non-privilege bus accesses.0 = Register not present1 = Register present"/>
+              <param name="PTC_WPCTRL_KEY" value="0x505443" caption="WPCTRL 24-bit key value. See register description for usage.Set to a unique value for each macro."/>
+              <param name="GCLK_ID" value="35"/>
+              <param name="DMAC_ID_EOC" value="38"/>
+              <param name="DMAC_ID_SEQ" value="39"/>
+              <param name="DMAC_ID_WCOMP" value="40"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="22" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="41" caption="Instance index for PTC"/>
+              <param name="MCLK_ID_APB" value="51" caption="Index for PTC APB clock"/>
+              <param name="PAC_ID" value="41" caption="Index for PTC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RSTC" id="03926" name2="pwr_rpmu_rstc_v1" version="1c0">
+          <instance name="RSTC">
+            <register-group name="RSTC" name-in-module="RSTC" address-space="base" offset="0x45004000"/>
+            <parameters>
+              <param name="BACKUP_IMPLEMENTED" value="1"/>
+              <param name="CM_DBGRESET_STRETCHED" value="3" caption="Reset stretcher size for Cortex CPU related to DBGRESET."/>
+              <param name="CM_HRESET_N_STRETCHED" value="3" caption="Reset stretcher size for Cortex CPU related to HRESETn."/>
+              <param name="CM_PORESET_STRETCHED" value="3" caption="Reset stretcher size for Cortex CPU related to PORESET."/>
+              <param name="HIB_IMPLEMENTED" value="1"/>
+              <param name="VBAT_IMPLEMENTED" value="0" caption="One if VBAT (Battery backup mode) is supported"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="2" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="5" caption="Instance index for RSTC"/>
+              <param name="MCLK_ID_APB" value="5" caption="Index for RSTC APB clock"/>
+              <param name="PAC_ID" value="5" caption="Index for RSTC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="03608" name2="tmr_rtc_u2250_v3" version="3b0">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x45006000"/>
+            <signals>
+              <signal group="IN" index="0" function="RTC_PAD_IE" pad="PA07"/>
+              <signal group="IN" index="1" function="RTC_PAD_IE" pad="PA08"/>
+              <signal group="IN" index="2" function="RTC_PAD_IE" pad="PA09"/>
+              <signal group="IN" index="3" function="RTC_PAD_IE" pad="PB00"/>
+              <signal group="OUT" index="0" function="_RTC_PAD_OE_N" pad="PB03"/>
+              <signal group="OUT" index="1" function="_RTC_PAD_OE_N" pad="PB04"/>
+              <signal group="OUT" index="2" function="_RTC_PAD_OE_N" pad="PB05"/>
+              <signal group="OUT" index="3" function="_RTC_PAD_OE_N" pad="PB06"/>
+            </signals>
+            <parameters>
+              <param name="NUM_OF_ALARMS" value="2" caption="--"/>
+              <param name="NUM_OF_BKREGS" value="0" caption="--"/>
+              <param name="NUM_OF_COMP16" value="4" caption="=2 * RTC_NUM_OF_ALARMS"/>
+              <param name="NUM_OF_TAMPERS" value="8" caption="--"/>
+              <param name="DMAC_ID_TIMESTAMP" value="3"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="3" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="12" caption="Instance index for RTC"/>
+              <param name="MCLK_ID_APB" value="12" caption="Index for RTC APB clock"/>
+              <param name="PAC_ID" value="12" caption="Index for RTC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SAU" id="SYSTEM_IP" version="1.0.0">
+          <instance name="SAU">
+            <register-group name="SAU" name-in-module="SAU" address-space="base" offset="0xE000EDD0"/>
+          </instance>
+        </module>
+        <module name="SCB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="SCB">
+            <register-group name="SCB" name-in-module="SCB" address-space="base" offset="0xE000ED00"/>
+          </instance>
+        </module>
+        <module name="SERCOM" id="03715" name2="com_sercom_u2201_v6" version="6c0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x44808000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PC00" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PC01" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PC02" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PC03" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="DMAC_ID_RX" value="4"/>
+              <param name="DMAC_ID_TX" value="5"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="4" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="26" caption="Instance index for SERCOM0"/>
+              <param name="MCLK_ID_APB" value="36" caption="Index for SERCOM0 APB clock"/>
+              <param name="PAC_ID" value="26" caption="Index for SERCOM0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x4480A000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PD01"/>
+              <signal group="PAD" index="1" function="D" pad="PD00"/>
+              <signal group="PAD" index="2" function="D" pad="PC06" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PC05" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="DMAC_ID_RX" value="6"/>
+              <param name="DMAC_ID_TX" value="7"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="5" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="27" caption="Instance index for SERCOM1"/>
+              <param name="MCLK_ID_APB" value="37" caption="Index for SERCOM1 APB clock"/>
+              <param name="PAC_ID" value="27" caption="Index for SERCOM1 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x4480C000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PC04" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PD06" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PD07" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PD08" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="DMAC_ID_RX" value="8"/>
+              <param name="DMAC_ID_TX" value="9"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="6" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="28" caption="Instance index for SERCOM2"/>
+              <param name="MCLK_ID_APB" value="38" caption="Index for SERCOM2 APB clock"/>
+              <param name="PAC_ID" value="28" caption="Index for SERCOM2 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x4480E000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PD09" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PA00" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PA01" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PA02" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="DMAC_ID_RX" value="10"/>
+              <param name="DMAC_ID_TX" value="11"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="7" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="29" caption="Instance index for SERCOM3"/>
+              <param name="MCLK_ID_APB" value="39" caption="Index for SERCOM3 APB clock"/>
+              <param name="PAC_ID" value="29" caption="Index for SERCOM3 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x44820000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA03" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PA04" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PA05" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PA06" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="0" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="0" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_CORE" value="28"/>
+              <param name="DMAC_ID_RX" value="24"/>
+              <param name="DMAC_ID_TX" value="25"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="16" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="34" caption="Instance index for SERCOM4"/>
+              <param name="MCLK_ID_APB" value="44" caption="Index for SERCOM4 APB clock"/>
+              <param name="PAC_ID" value="34" caption="Index for SERCOM4 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x44822000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PB03" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PB04" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PB05" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PB06" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="0" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="0" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_CORE" value="29"/>
+              <param name="DMAC_ID_RX" value="26"/>
+              <param name="DMAC_ID_TX" value="27"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="17" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="35" caption="Instance index for SERCOM5"/>
+              <param name="MCLK_ID_APB" value="45" caption="Index for SERCOM5 APB clock"/>
+              <param name="PAC_ID" value="35" caption="Index for SERCOM5 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SUPC" id="03926" name2="pwr_rpmu_supc_v1" version="1c0">
+          <instance name="SUPC">
+            <register-group name="SUPC" name-in-module="SUPC" address-space="base" offset="0x45002000"/>
+            <signals>
+              <signal group="RESETn" function="RES" pad="RESET_N"/>
+              <signal group="SMOR_DTEST" index="0" function="SUPC_VREF_TESTMODE" pad="PD08"/>
+              <signal group="SMOR_DTEST" index="1" function="SUPC_VREF_TESTMODE" pad="PD09"/>
+              <signal group="SMOR_DTEST" index="2" function="SUPC_VREF_TESTMODE" pad="PD07"/>
+              <signal group="SMOR_DTEST" index="3" function="SUPC_VREF_TESTMODE" pad="PA00"/>
+              <signal group="SMOR_DTEST" index="4" function="SUPC_VREF_TESTMODE" pad="PA01"/>
+              <signal group="SMOR_DTEST" index="5" function="SUPC_VREF_TESTMODE" pad="PA02"/>
+              <signal group="SMOR_DTEST" index="6" function="SUPC_VREF_TESTMODE" pad="PA03"/>
+              <signal group="SMOR_DTEST" index="7" function="SUPC_VREF_TESTMODE" pad="PA04"/>
+              <signal group="SMOR_DTEST" index="8" function="SUPC_VREF_TESTMODE" pad="PB03"/>
+              <signal group="SMOR_DTEST" index="9" function="SUPC_VREF_TESTMODE" pad="PB04"/>
+              <signal group="SMOR_DTEST" index="10" function="SUPC_VREF_TESTMODE" pad="PB05"/>
+              <signal group="SMOR_DTEST" index="11" function="SUPC_VREF_TESTMODE" pad="PB06"/>
+              <signal group="SMOR_DTEST" index="12" function="SUPC_VREF_TESTMODE" pad="PC00"/>
+              <signal group="SMOR_DTEST" index="13" function="SUPC_VREF_TESTMODE" pad="PA06"/>
+              <signal group="SMOR_DTEST" index="14" function="SUPC_VREF_TESTMODE" pad="PA07"/>
+              <signal group="SMOR_DTEST" index="15" function="SUPC_VREF_TESTMODE" pad="PC03"/>
+              <signal group="OUT" index="0" function="SUPC" pad="PB04"/>
+              <signal group="OUT" index="1" function="SUPC" pad="PB05"/>
+              <signal group="USERLDO" function="USER_LDO" pad="PD06"/>
+              <signal group="USERLDO_OUT" function="USER_LDO_OP_AMP" pad="USERLDO"/>
+            </signals>
+            <parameters>
+              <param name="ADDVREG_NUM" value="1" caption="Jira PWR109-210"/>
+              <param name="ADDVREG_PLL_NUM" value="0" caption="--"/>
+              <param name="ADDVREG_PLL_START_INDEX" value="1" caption="--"/>
+              <param name="BKOUT_NUM" value="2" caption="--"/>
+              <param name="BORVDDUSB_NUM" value="1" caption="(Jira PWR109-219)"/>
+              <param name="CHRG_PUMP_NUM" value="2" caption="--"/>
+              <param name="IOB_IMPLEMENTED" value="0" caption="--"/>
+              <param name="USER_LDO_IMPLEMENTED" value="1" caption="--"/>
+              <param name="VBAT_IMPLEMENTED" value="0" caption="--"/>
+              <param name="VREGSW_NUM" value="1" caption="--"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="1" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="4" caption="Instance index for SUPC"/>
+              <param name="MCLK_ID_APB" value="4" caption="Index for SUPC APB clock"/>
+              <param name="PAC_ID" value="4" caption="Index for SUPC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SysTick" id="SYSTEM_IP" version="1.0.0">
+          <instance name="SysTick">
+            <register-group name="SysTick" name-in-module="SysTick" address-space="base" offset="0xE000E010"/>
+            <parameters>
+              <param name="__SYST_NUM" value="2" caption="Number of implemented SysTick timers"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="03610" name2="tmr_tcc_u2213_v4" version="4d0">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x44810000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PC00" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PC01" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="1" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID_TCC01" value="25"/>
+              <param name="DMAC_ID_OVF" value="12"/>
+              <param name="DMAC_ID_MC0" value="13"/>
+              <param name="DMAC_ID_MC1" value="14"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="8" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="30" caption="Instance index for TCC0"/>
+              <param name="MCLK_ID_APB" value="40" caption="Index for TCC0 APB clock"/>
+              <param name="PAC_ID" value="30" caption="Index for TCC0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x44812000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PC02" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PC03" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="2" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID_TCC01" value="25"/>
+              <param name="DMAC_ID_OVF" value="15"/>
+              <param name="DMAC_ID_MC0" value="16"/>
+              <param name="DMAC_ID_MC1" value="17"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="9" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="31" caption="Instance index for TCC1"/>
+              <param name="MCLK_ID_APB" value="41" caption="Index for TCC1 APB clock"/>
+              <param name="PAC_ID" value="31" caption="Index for TCC1 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x44814000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PC04" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PC05" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DMAC_ID_MC0" value="19"/>
+              <param name="DMAC_ID_MC1" value="20"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="10" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="32" caption="Instance index for TCC2"/>
+              <param name="MCLK_ID_APB" value="42" caption="Index for TCC2 APB clock"/>
+              <param name="PAC_ID" value="32" caption="Index for TCC2 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC3">
+            <register-group name="TCC3" name-in-module="TCC" address-space="base" offset="0x44816000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PD00" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PD01" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DMAC_ID_MC0" value="22"/>
+              <param name="DMAC_ID_MC1" value="23"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="11" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="33" caption="Instance index for TCC3"/>
+              <param name="MCLK_ID_APB" value="43" caption="Index for TCC3 APB clock"/>
+              <param name="PAC_ID" value="33" caption="Index for TCC3 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC4">
+            <register-group name="TCC4" name-in-module="TCC" address-space="base" offset="0x44824000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PD07" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PD08" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="DMAC_ID_OVF" value="28"/>
+              <param name="DMAC_ID_MC0" value="29"/>
+              <param name="DMAC_ID_MC1" value="30"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="18" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="36" caption="Instance index for TCC4"/>
+              <param name="MCLK_ID_APB" value="46" caption="Index for TCC4 APB clock"/>
+              <param name="PAC_ID" value="36" caption="Index for TCC4 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC5">
+            <register-group name="TCC5" name-in-module="TCC" address-space="base" offset="0x44826000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PD09" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PA00" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="31"/>
+              <param name="DMAC_ID_OVF" value="31"/>
+              <param name="DMAC_ID_MC0" value="32"/>
+              <param name="DMAC_ID_MC1" value="33"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="19" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="37" caption="Instance index for TCC5"/>
+              <param name="MCLK_ID_APB" value="47" caption="Index for TCC5 APB clock"/>
+              <param name="PAC_ID" value="37" caption="Index for TCC5 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC6">
+            <register-group name="TCC6" name-in-module="TCC" address-space="base" offset="0x44828000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PA01" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PA02" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="32"/>
+              <param name="DMAC_ID_OVF" value="34"/>
+              <param name="DMAC_ID_MC0" value="35"/>
+              <param name="DMAC_ID_MC1" value="36"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="20" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="38" caption="Instance index for TCC6"/>
+              <param name="MCLK_ID_APB" value="48" caption="Index for TCC6 APB clock"/>
+              <param name="PAC_ID" value="38" caption="Index for TCC6 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TESTVAL" id="test_valio_mapper_v1" name2="test_valio_mapper_v1" version="1.0.0">
+          <instance name="TESTVAL">
+            <signals>
+              <signal group="VALIO" index="0" function="VALIO" pad="PD00"/>
+              <signal group="VALIO" index="1" function="VALIO" pad="PD01"/>
+              <signal group="VALIO" index="2" function="VALIO" pad="PC04"/>
+              <signal group="VALIO" index="3" function="VALIO" pad="PA05"/>
+              <signal group="VALIO" index="4" function="VALIO" pad="PC01"/>
+              <signal group="VALIO" index="5" function="VALIO" pad="PC02"/>
+            </signals>
+          </instance>
+        </module>
+        <module name="USB" id="03613" name2="usb_u2222_v1" version="1d0">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x44832000"/>
+            <signals>
+              <signal group="SOF" function="H" pad="PD01"/>
+              <signal group="USBDM" function="H" pad="PD02"/>
+              <signal group="USBDP" function="H" pad="PD03"/>
+            </signals>
+            <parameters>
+              <param name="AHB_2_USB_FIFO_DEPTH" value="4" caption="bytes number, should be at least 2, and 2^n (4,8,16 ...)"/>
+              <param name="AHB_2_USB_RD_DATA_BITS" value="8" caption="8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode"/>
+              <param name="AHB_2_USB_WR_DATA_BITS" value="32" caption="8, 16 or 32 : here, AHB transfer is made in word mode"/>
+              <param name="AHB_2_USB_WR_THRESHOLD" value="2" caption="as soon as there are N bytes-free inside the fifo, ahb read transfer is requested"/>
+              <param name="DATA_BUS_16_8" value="0" caption="UTMI/SIE data bus size : 0 -&gt; 8 bits, 1 -&gt; 16 bits"/>
+              <param name="EPNUM" value="8" caption="parameter for rtl : max of ENDPOINT and PIPE NUM"/>
+              <param name="EPT_NUM" value="8" caption="Number of USB end points"/>
+              <param name="INITIAL_CONTROL_QOS" value="3" caption="CONTROL QOS RESET value"/>
+              <param name="INITIAL_DATA_QOS" value="3" caption="DATA QOS RESET value"/>
+              <param name="MISSING_SOF_DET_IMPLEMENTED" value="1" caption="48 mHz xPLL feature implemented"/>
+              <param name="PIPE_NUM" value="8" caption="Number of USB pipes"/>
+              <param name="SYSTEM_CLOCK_IS_CKUSB" value="0" caption="Dual (1'b0) or Single (1'b1) clock system"/>
+              <param name="USB_2_AHB_FIFO_DEPTH" value="4" caption="bytes number, should be at least 2, and 2^n (4,8,16 ...)"/>
+              <param name="USB_2_AHB_RD_DATA_BITS" value="16" caption="8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode"/>
+              <param name="USB_2_AHB_RD_THRESHOLD" value="2" caption="as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested"/>
+              <param name="USB_2_AHB_WR_DATA_BITS" value="8" caption="8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode"/>
+              <param name="GCLK_ID" value="38"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="25" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="44" caption="Instance index for USB"/>
+              <param name="MCLK_ID_AHB" value="54" caption="Index for USB AHB clock"/>
+              <param name="MCLK_ID_APB" value="55" caption="Index for USB APB clock"/>
+              <param name="PAC_ID" value="44" caption="Index for USB registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="03611" name2="wdt_u2251_v2" version="2b0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x4400E000"/>
+            <parameters>
+              <param name="FUSES_UPDATE_SUPPORT" value="0" caption="WDT Fuse Update Support"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="7" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="11" caption="Instance index for WDT"/>
+              <param name="MCLK_ID_APB" value="11" caption="Index for WDT APB clock"/>
+              <param name="PAC_ID" value="11" caption="Index for WDT registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+      </peripherals>
+      <interrupts>
+        <interrupt name="Reset" index="-15" caption="Reset Vector, invoked on Power up and warm reset"/>
+        <interrupt name="NonMaskableInt" index="-14" caption="Non maskable Interrupt, cannot be stopped or preempted"/>
+        <interrupt name="HardFault" index="-13" caption="Hard Fault, all classes of Fault"/>
+        <interrupt name="SVCall" index="-5" caption="System Service Call via SVC instruction"/>
+        <interrupt name="PendSV" index="-2" caption="Pendable request for system service"/>
+        <interrupt name="SysTick" index="-1" caption="System Tick Timer"/>
+        <interrupt name="FCR" index="0" module-instance="FCR"/>
+        <interrupt name="FCW" index="1" module-instance="FCW"/>
+        <interrupt name="PM" index="2" module-instance="PM"/>
+        <interrupt name="SUPC" index="3" module-instance="SUPC"/>
+        <interrupt name="OSCCTRL_XOSCRDY" index="4" module-instance="OSCCTRL"/>
+        <interrupt name="OSCCTRL_DFLLRDY" index="5" module-instance="OSCCTRL"/>
+        <interrupt name="OSCCTRL_PLLLOCKR_0" index="6" module-instance="OSCCTRL"/>
+        <interrupt name="OSC32KCTRL_XOSC32KRDY" index="7" module-instance="OSC32KCTRL"/>
+        <interrupt name="OSC32KCTRL_XOSC32KFAIL" index="8" module-instance="OSC32KCTRL"/>
+        <interrupt name="MCLK" index="9" module-instance="MCLK"/>
+        <interrupt name="FREQM" index="10" module-instance="FREQM"/>
+        <interrupt name="WDT" index="11" module-instance="WDT"/>
+        <interrupt name="RTC_TAMPER" index="12" module-instance="RTC"/>
+        <interrupt name="RTC_OVF" index="13" module-instance="RTC"/>
+        <interrupt name="RTC_PER0" index="14" module-instance="RTC"/>
+        <interrupt name="RTC_CMP0" index="15" module-instance="RTC"/>
+        <interrupt name="EIC_EXTINT0" index="16" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT1" index="17" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT2" index="18" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT3" index="19" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT4" index="20" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT5" index="21" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT6" index="22" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT7" index="23" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT8" index="24" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT9" index="25" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT10" index="26" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT11" index="27" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT12" index="28" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT13" index="29" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT14" index="30" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT15" index="31" module-instance="EIC"/>
+        <interrupt name="EIC_NSCHK" index="32" module-instance="EIC"/>
+        <interrupt name="MCRAMC" index="34" module-instance="MCRAMC"/>
+        <interrupt name="CAN0_INT0" index="35" module-instance="CAN0"/>
+        <interrupt name="CAN0_INT1" index="36" module-instance="CAN0"/>
+        <interrupt name="CAN0_BERR" index="37" module-instance="CAN0"/>
+        <interrupt name="CAN1_INT0" index="38" module-instance="CAN1"/>
+        <interrupt name="CAN1_INT1" index="39" module-instance="CAN1"/>
+        <interrupt name="CAN1_BERR" index="40" module-instance="CAN1"/>
+        <interrupt name="PORT" index="41" module-instance="PORT"/>
+        <interrupt name="DMAC_TCMPL0" index="42" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL1" index="43" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL2" index="44" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL3" index="45" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL4" index="46" module-instance="DMAC"/>
+        <interrupt name="HMATRIX2" index="47" module-instance="HMATRIX2"/>
+        <interrupt name="EVSYS_EVD0" index="48" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD1" index="49" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD2" index="50" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD3" index="51" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD4" index="52" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD5" index="53" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD6" index="54" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD7" index="55" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD8" index="56" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD9" index="57" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD10" index="58" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD11" index="59" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_6" index="60" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_5" index="61" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_0" index="62" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_1" index="63" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_2" index="64" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_3" index="65" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_4" index="66" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_6" index="67" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_5" index="68" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_0" index="69" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_1" index="70" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_2" index="71" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_3" index="72" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_4" index="73" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_6" index="74" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_5" index="75" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_0" index="76" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_1" index="77" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_2" index="78" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_3" index="79" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_4" index="80" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_6" index="81" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_5" index="82" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_0" index="83" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_1" index="84" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_2" index="85" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_3" index="86" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_4" index="87" module-instance="SERCOM3"/>
+        <interrupt name="TCC0_DFS" index="88" module-instance="TCC0"/>
+        <interrupt name="TCC0_CNT" index="89" module-instance="TCC0"/>
+        <interrupt name="TCC0_MC0" index="90" module-instance="TCC0"/>
+        <interrupt name="TCC0_MC1" index="91" module-instance="TCC0"/>
+        <interrupt name="TCC1_DFS" index="92" module-instance="TCC1"/>
+        <interrupt name="TCC1_CNT" index="93" module-instance="TCC1"/>
+        <interrupt name="TCC1_MC0" index="94" module-instance="TCC1"/>
+        <interrupt name="TCC1_MC1" index="95" module-instance="TCC1"/>
+        <interrupt name="TCC2_DFS" index="96" module-instance="TCC2"/>
+        <interrupt name="TCC2_CNT" index="97" module-instance="TCC2"/>
+        <interrupt name="TCC2_MC0" index="98" module-instance="TCC2"/>
+        <interrupt name="TCC2_MC1" index="99" module-instance="TCC2"/>
+        <interrupt name="TCC3_DFS" index="100" module-instance="TCC3"/>
+        <interrupt name="TCC3_CNT" index="101" module-instance="TCC3"/>
+        <interrupt name="TCC3_MC0" index="102" module-instance="TCC3"/>
+        <interrupt name="TCC3_MC1" index="103" module-instance="TCC3"/>
+        <interrupt name="SERCOM4_6" index="104" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_5" index="105" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_0" index="106" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_1" index="107" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_2" index="108" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_3" index="109" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_4" index="110" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_6" index="111" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_5" index="112" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_0" index="113" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_1" index="114" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_2" index="115" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_3" index="116" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_4" index="117" module-instance="SERCOM5"/>
+        <interrupt name="TCC4_DFS" index="118" module-instance="TCC4"/>
+        <interrupt name="TCC4_CNT" index="119" module-instance="TCC4"/>
+        <interrupt name="TCC4_MC0" index="120" module-instance="TCC4"/>
+        <interrupt name="TCC4_MC1" index="121" module-instance="TCC4"/>
+        <interrupt name="TCC5_DFS" index="122" module-instance="TCC5"/>
+        <interrupt name="TCC5_CNT" index="123" module-instance="TCC5"/>
+        <interrupt name="TCC5_MC0" index="124" module-instance="TCC5"/>
+        <interrupt name="TCC5_MC1" index="125" module-instance="TCC5"/>
+        <interrupt name="TCC6_DFS" index="126" module-instance="TCC6"/>
+        <interrupt name="TCC6_CNT" index="127" module-instance="TCC6"/>
+        <interrupt name="TCC6_MC0" index="128" module-instance="TCC6"/>
+        <interrupt name="TCC6_MC1" index="129" module-instance="TCC6"/>
+        <interrupt name="ADC_REQ0" index="130" module-instance="ADC"/>
+        <interrupt name="ADC_REQ1" index="131" module-instance="ADC"/>
+        <interrupt name="AC" index="132" module-instance="AC"/>
+        <interrupt name="PTC" index="133" module-instance="PTC"/>
+        <interrupt name="USB_EORSMDNRSM" index="134" module-instance="USB"/>
+        <interrupt name="USB_SOFHSOF" index="135" module-instance="USB"/>
+        <interrupt name="USB_TRCPT00" index="136" module-instance="USB"/>
+        <interrupt name="USB_TRCPT10" index="137" module-instance="USB"/>
+        <interrupt name="AT" index="138" module-instance="AT"/>
+      </interrupts>
+      <events>
+        <generators>
+          <generator name="SUPC_LVDET" index="1" module-instance="SUPC"/>
+          <generator name="OSCCTRL_XOSCFAIL" index="2" module-instance="OSCCTRL"/>
+          <generator name="OSC32KCTRL_XOSC32KFAIL" index="3" module-instance="OSC32KCTRL"/>
+          <generator name="FREQM_DONE" index="4" module-instance="FREQM"/>
+          <generator name="FREQM_WINMON" index="5" module-instance="FREQM"/>
+          <generator name="RTC_PER0" index="6" module-instance="RTC"/>
+          <generator name="RTC_PER1" index="7" module-instance="RTC"/>
+          <generator name="RTC_PER2" index="8" module-instance="RTC"/>
+          <generator name="RTC_PER3" index="9" module-instance="RTC"/>
+          <generator name="RTC_PER4" index="10" module-instance="RTC"/>
+          <generator name="RTC_PER5" index="11" module-instance="RTC"/>
+          <generator name="RTC_PER6" index="12" module-instance="RTC"/>
+          <generator name="RTC_PER7" index="13" module-instance="RTC"/>
+          <generator name="RTC_CMP0" index="14" module-instance="RTC"/>
+          <generator name="RTC_CMP1" index="15" module-instance="RTC"/>
+          <generator name="RTC_CMP2" index="16" module-instance="RTC"/>
+          <generator name="RTC_CMP3" index="17" module-instance="RTC"/>
+          <generator name="RTC_TAMPER" index="18" module-instance="RTC"/>
+          <generator name="RTC_OVF" index="19" module-instance="RTC"/>
+          <generator name="RTC_PERD" index="20" module-instance="RTC"/>
+          <generator name="EIC_EXTINT0" index="21" module-instance="EIC"/>
+          <generator name="EIC_EXTINT1" index="22" module-instance="EIC"/>
+          <generator name="EIC_EXTINT2" index="23" module-instance="EIC"/>
+          <generator name="EIC_EXTINT3" index="24" module-instance="EIC"/>
+          <generator name="EIC_EXTINT4" index="25" module-instance="EIC"/>
+          <generator name="EIC_EXTINT5" index="26" module-instance="EIC"/>
+          <generator name="EIC_EXTINT6" index="27" module-instance="EIC"/>
+          <generator name="EIC_EXTINT7" index="28" module-instance="EIC"/>
+          <generator name="EIC_EXTINT8" index="29" module-instance="EIC"/>
+          <generator name="EIC_EXTINT9" index="30" module-instance="EIC"/>
+          <generator name="EIC_EXTINT10" index="31" module-instance="EIC"/>
+          <generator name="EIC_EXTINT11" index="32" module-instance="EIC"/>
+          <generator name="EIC_EXTINT12" index="33" module-instance="EIC"/>
+          <generator name="EIC_EXTINT13" index="34" module-instance="EIC"/>
+          <generator name="EIC_EXTINT14" index="35" module-instance="EIC"/>
+          <generator name="EIC_EXTINT15" index="36" module-instance="EIC"/>
+          <generator name="DMAC_CH0" index="37" module-instance="DMAC"/>
+          <generator name="DMAC_CH1" index="38" module-instance="DMAC"/>
+          <generator name="DMAC_CH2" index="39" module-instance="DMAC"/>
+          <generator name="DMAC_CH3" index="40" module-instance="DMAC"/>
+          <generator name="TCC0_OVF" index="41" module-instance="TCC0"/>
+          <generator name="TCC0_TRG" index="42" module-instance="TCC0"/>
+          <generator name="TCC0_CNT" index="43" module-instance="TCC0"/>
+          <generator name="TCC0_MC0" index="44" module-instance="TCC0"/>
+          <generator name="TCC0_MC1" index="45" module-instance="TCC0"/>
+          <generator name="TCC1_OVF" index="46" module-instance="TCC1"/>
+          <generator name="TCC1_TRG" index="47" module-instance="TCC1"/>
+          <generator name="TCC1_CNT" index="48" module-instance="TCC1"/>
+          <generator name="TCC1_MC0" index="49" module-instance="TCC1"/>
+          <generator name="TCC1_MC1" index="50" module-instance="TCC1"/>
+          <generator name="TCC2_OVF" index="51" module-instance="TCC2"/>
+          <generator name="TCC2_TRG" index="52" module-instance="TCC2"/>
+          <generator name="TCC2_CNT" index="53" module-instance="TCC2"/>
+          <generator name="TCC2_MC0" index="54" module-instance="TCC2"/>
+          <generator name="TCC2_MC1" index="55" module-instance="TCC2"/>
+          <generator name="TCC3_OVF" index="56" module-instance="TCC3"/>
+          <generator name="TCC3_TRG" index="57" module-instance="TCC3"/>
+          <generator name="TCC3_CNT" index="58" module-instance="TCC3"/>
+          <generator name="TCC3_MC0" index="59" module-instance="TCC3"/>
+          <generator name="TCC3_MC1" index="60" module-instance="TCC3"/>
+          <generator name="TCC4_OVF" index="61" module-instance="TCC4"/>
+          <generator name="TCC4_TRG" index="62" module-instance="TCC4"/>
+          <generator name="TCC4_CNT" index="63" module-instance="TCC4"/>
+          <generator name="TCC4_MC0" index="64" module-instance="TCC4"/>
+          <generator name="TCC4_MC1" index="65" module-instance="TCC4"/>
+          <generator name="TCC5_OVF" index="66" module-instance="TCC5"/>
+          <generator name="TCC5_TRG" index="67" module-instance="TCC5"/>
+          <generator name="TCC5_CNT" index="68" module-instance="TCC5"/>
+          <generator name="TCC5_MC0" index="69" module-instance="TCC5"/>
+          <generator name="TCC5_MC1" index="70" module-instance="TCC5"/>
+          <generator name="TCC6_OVF" index="71" module-instance="TCC6"/>
+          <generator name="TCC6_TRG" index="72" module-instance="TCC6"/>
+          <generator name="TCC6_CNT" index="73" module-instance="TCC6"/>
+          <generator name="TCC6_MC0" index="74" module-instance="TCC6"/>
+          <generator name="TCC6_MC1" index="75" module-instance="TCC6"/>
+          <generator name="ADC_CHRDY" index="76" module-instance="ADC"/>
+          <generator name="ADC_CMP" index="77" module-instance="ADC"/>
+          <generator name="AC_COMP0" index="78" module-instance="AC"/>
+          <generator name="AC_COMP1" index="79" module-instance="AC"/>
+          <generator name="AC_WIN0" index="80" module-instance="AC"/>
+          <generator name="PTC_EOC" index="81" module-instance="PTC"/>
+          <generator name="PTC_WCOMP" index="82" module-instance="PTC"/>
+          <generator name="CCL0_LUTOUT0" index="83" module-instance="CCL0"/>
+          <generator name="CCL0_LUTOUT1" index="84" module-instance="CCL0"/>
+          <generator name="CCL0_LUTOUT2" index="85" module-instance="CCL0"/>
+          <generator name="CCL0_LUTOUT3" index="86" module-instance="CCL0"/>
+          <generator name="CCL1_LUTOUT0" index="87" module-instance="CCL1"/>
+          <generator name="CCL1_LUTOUT1" index="88" module-instance="CCL1"/>
+          <generator name="CCL1_LUTOUT2" index="89" module-instance="CCL1"/>
+          <generator name="CCL1_LUTOUT3" index="90" module-instance="CCL1"/>
+        </generators>
+        <users>
+          <user name="FREQM_START" index="0" module-instance="FREQM"/>
+          <user name="RTC_TAMPER" index="1" module-instance="RTC"/>
+          <user name="PORT_EV0" index="2" module-instance="PORT"/>
+          <user name="PORT_EV1" index="3" module-instance="PORT"/>
+          <user name="PORT_EV2" index="4" module-instance="PORT"/>
+          <user name="PORT_EV3" index="5" module-instance="PORT"/>
+          <user name="DMAC_CH0" index="6" module-instance="DMAC"/>
+          <user name="DMAC_CH1" index="7" module-instance="DMAC"/>
+          <user name="DMAC_CH2" index="8" module-instance="DMAC"/>
+          <user name="DMAC_CH3" index="9" module-instance="DMAC"/>
+          <user name="TCC0_EV0" index="10" module-instance="TCC0"/>
+          <user name="TCC0_EV1" index="11" module-instance="TCC0"/>
+          <user name="TCC0_MC0" index="12" module-instance="TCC0"/>
+          <user name="TCC0_MC1" index="13" module-instance="TCC0"/>
+          <user name="TCC1_EV0" index="14" module-instance="TCC1"/>
+          <user name="TCC1_EV1" index="15" module-instance="TCC1"/>
+          <user name="TCC1_MC0" index="16" module-instance="TCC1"/>
+          <user name="TCC1_MC1" index="17" module-instance="TCC1"/>
+          <user name="TCC2_EV0" index="18" module-instance="TCC2"/>
+          <user name="TCC2_EV1" index="19" module-instance="TCC2"/>
+          <user name="TCC2_MC0" index="20" module-instance="TCC2"/>
+          <user name="TCC2_MC1" index="21" module-instance="TCC2"/>
+          <user name="TCC3_EV0" index="22" module-instance="TCC3"/>
+          <user name="TCC3_EV1" index="23" module-instance="TCC3"/>
+          <user name="TCC3_MC0" index="24" module-instance="TCC3"/>
+          <user name="TCC3_MC1" index="25" module-instance="TCC3"/>
+          <user name="TCC4_EV0" index="26" module-instance="TCC4"/>
+          <user name="TCC4_EV1" index="27" module-instance="TCC4"/>
+          <user name="TCC4_MC0" index="28" module-instance="TCC4"/>
+          <user name="TCC4_MC1" index="29" module-instance="TCC4"/>
+          <user name="TCC5_EV0" index="30" module-instance="TCC5"/>
+          <user name="TCC5_EV1" index="31" module-instance="TCC5"/>
+          <user name="TCC5_MC0" index="32" module-instance="TCC5"/>
+          <user name="TCC5_MC1" index="33" module-instance="TCC5"/>
+          <user name="TCC6_EV0" index="34" module-instance="TCC6"/>
+          <user name="TCC6_EV1" index="35" module-instance="TCC6"/>
+          <user name="TCC6_MC0" index="36" module-instance="TCC6"/>
+          <user name="TCC6_MC1" index="37" module-instance="TCC6"/>
+          <user name="ADC_TRIG0" index="38" module-instance="ADC"/>
+          <user name="ADC_TRIG1" index="39" module-instance="ADC"/>
+          <user name="ADC_TRIG2" index="40" module-instance="ADC"/>
+          <user name="ADC_TRIG3" index="41" module-instance="ADC"/>
+          <user name="ADC_TRIG4" index="42" module-instance="ADC"/>
+          <user name="ADC_TRIG5" index="43" module-instance="ADC"/>
+          <user name="ADC_TRIG6" index="44" module-instance="ADC"/>
+          <user name="ADC_TRIG7" index="45" module-instance="ADC"/>
+          <user name="ADC_TRIG8" index="46" module-instance="ADC"/>
+          <user name="ADC_TRIG9" index="47" module-instance="ADC"/>
+          <user name="ADC_TRIG10" index="48" module-instance="ADC"/>
+          <user name="AC_SOC0" index="49" module-instance="AC"/>
+          <user name="AC_SOC1" index="50" module-instance="AC"/>
+          <user name="PTC_DSEQR" index="51" module-instance="PTC"/>
+          <user name="PTC_STCONV" index="52" module-instance="PTC"/>
+          <user name="CCL0_LUTIN0" index="53" module-instance="CCL0"/>
+          <user name="CCL0_LUTIN1" index="54" module-instance="CCL0"/>
+          <user name="CCL0_LUTIN2" index="55" module-instance="CCL0"/>
+          <user name="CCL0_LUTIN3" index="56" module-instance="CCL0"/>
+          <user name="CCL1_LUTIN0" index="57" module-instance="CCL1"/>
+          <user name="CCL1_LUTIN1" index="58" module-instance="CCL1"/>
+          <user name="CCL1_LUTIN2" index="59" module-instance="CCL1"/>
+          <user name="CCL1_LUTIN3" index="60" module-instance="CCL1"/>
+          <user name="AT_TAMPSRC5" index="61" module-instance="AT"/>
+        </users>
+      </events>
+      <interfaces>
+        <interface name="JTAG" type="samjtag"/>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x0AC02053"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="03784" name2="cmp_ac_u2501_v2" version="2a0" caption="Analog Comparator Controller">
+      <register-group name="CHANNEL" size="0x10">
+        <register name="COMPCTRL" offset="0x0" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Pair n Comparator Control 0">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x8"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x30" values="COMPCTRL__INTSEL"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x7000" values="COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x10000"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0x20000" values="COMPCTRL__SPEED"/>
+          <bitfield name="HYST" caption="Hysteresis Level" mask="0x180000" values="COMPCTRL__HYST"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0xE00000" values="COMPCTRL__FLEN"/>
+          <bitfield name="OUT" caption="Output" mask="0x3000000" values="COMPCTRL__OUT"/>
+          <bitfield name="SUT" caption="Start-up Time" mask="0xFC000000"/>
+        </register>
+        <register name="DACCTRL" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Dac n Control">
+          <bitfield name="VALUE0" caption="DAC0 Output Value" mask="0x7F"/>
+          <bitfield name="SHEN0" caption="DAC0 Sample and Hold Enable Operating Mode" mask="0x8000"/>
+          <bitfield name="VALUE1" caption="DAC1 Output Value" mask="0x7F0000"/>
+          <bitfield name="SHEN1" caption="DAC1 Sample and Hold Enable Operating Mode" mask="0x80000000"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Window Monitor  n Control">
+          <bitfield name="WEN" caption="Window n Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL" caption="Window n Interrupt Selection" mask="0x6" values="WINCTRL__WINTSEL"/>
+        </register>
+      </register-group>
+      <register-group name="AC" caption="Analog Comparator Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Control C">
+          <bitfield name="WIDTH" caption="Sample and Hold Clock Pulse Width" mask="0x3FF"/>
+          <bitfield name="PER" caption="Sample and Hold Clock Period" mask="0x3FF000"/>
+          <bitfield name="PRESCALER" caption="Prescaling Factor" mask="0x7000000" values="CTRLC__PRESCALER"/>
+          <bitfield name="AIPMPEN" caption="Analog Input Charge Pump Enable" mask="0x8000000"/>
+          <bitfield name="CONFIG" caption="Configuration Extension" mask="0xF0000000"/>
+        </register>
+        <register name="EVCTRL" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="INVEI0" caption="Inverted Event Input Enable 0" mask="0x1000000"/>
+          <bitfield name="INVEI1" caption="Inverted Event Input Enable 1" mask="0x2000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x100"/>
+        </register>
+        <register name="STATUSA" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30000" values="STATUSA__WSTATE"/>
+        </register>
+        <register name="STATUSB" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="COMPCTRL0" caption="COMPCTRL 0 Synchronization Busy" mask="0x4"/>
+          <bitfield name="COMPCTRL1" caption="COMPCTRL 1 Synchronization Busy" mask="0x8"/>
+          <bitfield name="WINCTRL0" caption="WINCTRL 0 Synchronization Busy" mask="0x400"/>
+        </register>
+        <register-group name="CHANNEL" name-in-module="CHANNEL" offset="0x30" size="0x10" count="1"/>
+      </register-group>
+      <value-group name="COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="INT0" caption="Internal connection 0, device specific" value="4"/>
+        <value name="BANDGAP" caption="Bangap" value="5"/>
+        <value name="GND" caption="Ground" value="6"/>
+        <value name="INTDAC" caption="Internal DAC" value="7"/>
+      </value-group>
+      <value-group name="COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="INT0" caption="Internal connection 0, device specific" value="4"/>
+        <value name="INT1" caption="Internal connection 1, device specific" value="5"/>
+        <value name="INT2" caption="Internal connection 2, device specific" value="6"/>
+        <value name="INTDAC" caption="Internal DAC" value="7"/>
+      </value-group>
+      <value-group name="COMPCTRL__SPEED">
+        <value name="HIGH" caption="High speed, high power" value="0"/>
+        <value name="LOW" caption="Low speed, low power" value="1"/>
+      </value-group>
+      <value-group name="COMPCTRL__HYST">
+        <value name="HYST10" caption="10mV" value="0"/>
+        <value name="HYST20" caption="20mV" value="1"/>
+        <value name="HYST40" caption="40mV" value="2"/>
+        <value name="HYST60" caption="60mV" value="3"/>
+      </value-group>
+      <value-group name="COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="WINCTRL__WINTSEL">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="CTRLC__PRESCALER">
+        <value name="DIV1" caption="Sampling rate is GCLK_AC (No division)" value="0x0"/>
+        <value name="DIV2" caption="Sampling rate is GCLK_AC/2" value="0x1"/>
+        <value name="DIV4" caption="Sampling rate is GCLK_AC/4" value="0x2"/>
+        <value name="DIV8" caption="Sampling rate is GCLK_AC/8" value="0x3"/>
+        <value name="DIV16" caption="Sampling rate is GCLK_AC/16" value="0x4"/>
+        <value name="DIV32" caption="Sampling rate is GCLK_AC/32" value="0x5"/>
+        <value name="DIV64" caption="Sampling rate is GCLK_AC/64" value="0x6"/>
+        <value name="DIV128" caption="Sampling rate is GCLK_AC/128" value="0x7"/>
+      </value-group>
+      <value-group name="STATUSA__WSTATE">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="03620" name2="adc_msh_ctrl_apb_v1" version="1b0" caption="ADC Controller">
+      <register-group name="CONFIG" size="0x20">
+        <register name="CORCTRL" offset="0x0" rw="RW" size="4" initval="0x00000C00" caption="SARCORE Control">
+          <bitfield name="SAMC" caption="Sample Count" mask="0x3FF"/>
+          <bitfield name="SELRES" caption="Selects Resolution" mask="0xC00" values="CORCTRL__SELRES"/>
+          <bitfield name="EIS" caption="Early Interrupt Select" mask="0x7000"/>
+          <bitfield name="EIRQOVR" caption="Interrupt Type Select" mask="0x8000"/>
+          <bitfield name="STRGSRC" caption="SCAN trigger source selection" mask="0xF0000" values="CORCTRL__STRGSRC"/>
+          <bitfield name="STRGLVL" caption="Scan Trigger Level Sensitivity" mask="0x200000"/>
+          <bitfield name="SCNRTDS" caption="SCAN Re-trigger Disable" mask="0x400000"/>
+          <bitfield name="ADCDIV" caption="Division Ratio for SARCORE clock" mask="0x7F000000"/>
+        </register>
+        <register name="CHNCFG1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 1 (LVL/CMPEN)">
+          <bitfield name="CHNCMPEN" caption="Channel Comparator Enable" mask="0xFFFF"/>
+          <bitfield name="LVL" caption="Channel Level" mask="0xFFFF0000"/>
+        </register>
+        <register name="CHNCFG2" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 2(FRACT/CSS)">
+          <bitfield name="CSS" caption="Channel SCAN Select" mask="0xFFFF"/>
+          <bitfield name="FRACT" caption="Channel Fractional" mask="0xFFFF0000"/>
+        </register>
+        <register name="CHNCFG3" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration3 (SIGN/DIFF)">
+          <bitfield name="DIFF" caption="Differential Mode" mask="0xFFFF"/>
+          <bitfield name="SIGN" caption="SIGN setting" mask="0xFFFF0000"/>
+        </register>
+        <register name="CHNCFG4" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 4 (TRGSRC)">
+          <bitfield name="TRGSRC0" caption="Channel 0 Trigger Source" mask="0xF" values="CHNCFG4__TRGSRC0"/>
+          <bitfield name="TRGSRC1" caption="Channel 1 Trigger Source" mask="0xF0" values="CHNCFG4__TRGSRC1"/>
+          <bitfield name="TRGSRC2" caption="Channel 2 Trigger Source" mask="0xF00" values="CHNCFG4__TRGSRC2"/>
+          <bitfield name="TRGSRC3" caption="Channel 3 Trigger Source" mask="0xF000" values="CHNCFG4__TRGSRC3"/>
+          <bitfield name="TRGSRC4" caption="Channel 4 Trigger Source" mask="0xF0000" values="CHNCFG4__TRGSRC4"/>
+          <bitfield name="TRGSRC5" caption="Channel 5 Trigger Source" mask="0xF00000" values="CHNCFG4__TRGSRC5"/>
+          <bitfield name="TRGSRC6" caption="Channel 6 Trigger Source" mask="0xF000000" values="CHNCFG4__TRGSRC6"/>
+          <bitfield name="TRGSRC7" caption="Channel 7 Trigger Source" mask="0xF0000000" values="CHNCFG4__TRGSRC7"/>
+        </register>
+        <register name="CHNCFG5" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 5 (TRGSRC)">
+          <bitfield name="TRGSRC8" caption="Channel 8 Trigger Source" mask="0xF" values="CHNCFG5__TRGSRC8"/>
+          <bitfield name="TRGSRC9" caption="Channel 9 Trigger Source" mask="0xF0" values="CHNCFG5__TRGSRC9"/>
+          <bitfield name="TRGSRC10" caption="Channel 10 Trigger Source" mask="0xF00" values="CHNCFG5__TRGSRC10"/>
+          <bitfield name="TRGSRC11" caption="Channel 11 Trigger Source" mask="0xF000" values="CHNCFG5__TRGSRC11"/>
+          <bitfield name="TRGSRC12" caption="Channel 12 Trigger Source" mask="0xF0000" values="CHNCFG5__TRGSRC12"/>
+          <bitfield name="TRGSRC13" caption="Channel 13 Trigger Source" mask="0xF00000" values="CHNCFG5__TRGSRC13"/>
+          <bitfield name="TRGSRC14" caption="Channel 14 Trigger Source" mask="0xF000000" values="CHNCFG5__TRGSRC14"/>
+          <bitfield name="TRGSRC15" caption="Channel 15 Trigger Source" mask="0xF0000000" values="CHNCFG5__TRGSRC15"/>
+        </register>
+        <register name="CALCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="SARCORE Calibration Value">
+          <mode name="DEFAULT"/>
+          <mode name="FUSES_ADC_SARCORE_12BIT_V7A0"/>
+          <mode name="FUSES_ADC_SARCORE_12BIT_V7C0"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_cmbf" caption="Enable Common Mode Buffer" mask="0x1"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_dither" caption="Enable Dither" mask="0x4"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dis_faz" caption="Disable auto-zeroing" mask="0x8"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dis_saz" caption="Disable auto-zeroing" mask="0x10"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dis_laz" caption="Disable auto-zeroing" mask="0x20"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_rdac" caption="Disable Power Cycling" mask="0x40"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dbg_sel" caption="Debug Bus Select" mask="0x80"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="sel_del" caption="Scan Mode comp_out" mask="0x100"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="t1_dly" caption="Regen Latch Delay" mask="0x600"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="tclk_div" caption="Test Clock Divider" mask="0xF800"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="iadc_1" caption="Current Consumption 1" mask="0x300000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="iadc_2" caption="Current Consumption 2" mask="0xC00000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="icmp_1" caption="Bias Current Stage 1" mask="0x3000000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="icmp_2" caption="Bias Current Stage 2" mask="0xC000000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="icmbf" caption="Bias Current Common Mode Buffer" mask="0x30000000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_ext_bias" caption="Dsiable Internal Bias Circuit" mask="0x80000000"/>
+          <bitfield modes="DEFAULT" name="CALBITS" caption="Calibration Values" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="EVCTRL" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Event conversion input enable" mask="0x1"/>
+          <bitfield name="STARTINV" caption="Start Conversion Invert" mask="0x8"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="CMPEO" caption="Comparator Window Event Out" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group name="INT" size="0x10">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="CMPHIT" caption="Compare Hit Disable" mask="0x10"/>
+          <bitfield name="SOVFL" caption="Synchonizer Overflow Disable" mask="0x80"/>
+          <bitfield name="CHRDYC" caption="Core Current Channel Disable" mask="0x100"/>
+          <bitfield name="FLTRDY" caption="Filter Ready Disable" mask="0x200"/>
+          <bitfield name="CHNERRC" caption="Channel Overwrite Error Disable" mask="0x400"/>
+          <bitfield name="EOSRDY" caption="Endo of Scan Disable" mask="0x800"/>
+          <bitfield name="CHRDY" caption="Channel Ready Disable" mask="0xFFFF0000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="CMPHIT" caption="Compare Hit Enable" mask="0x10"/>
+          <bitfield name="SOVFL" caption="Synchronizer Overflow Enable" mask="0x80"/>
+          <bitfield name="CHRDYC" caption="Current Channel Ready Enable" mask="0x100"/>
+          <bitfield name="FLTRDY" caption="Filter Ready Enable" mask="0x200"/>
+          <bitfield name="CHNERRC" caption="Channel Overwrite Enable" mask="0x400"/>
+          <bitfield name="EOSRDY" caption="End of Scan Enable" mask="0x800"/>
+          <bitfield name="CHRDY" caption="Channel Ready Enable" mask="0xFFFF0000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flags">
+          <bitfield name="CMPINTID" caption="Compare Channel ID" mask="0xF"/>
+          <bitfield name="CMPHIT" caption="Compare Hit" mask="0x10"/>
+          <bitfield name="SOVFL" caption="Synchronizer Overflow" mask="0x80"/>
+          <bitfield name="CHRDYC" caption="Current Channel Ready" mask="0x100"/>
+          <bitfield name="FLTRDY" caption="Filter Ready" mask="0x200"/>
+          <bitfield name="CHNERRC" caption="Channel Overwrite Error" mask="0x400"/>
+          <bitfield name="EOSRDY" caption="End of Scan Ready" mask="0x800"/>
+          <bitfield name="CRDYID" caption="Channel Ready ID" mask="0xF000"/>
+          <bitfield name="CHRDY" caption="Channel Ready" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+      <register-group name="ADC" caption="ADC Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000080" caption="CONTROL A REGISTER">
+          <bitfield name="SWRST" caption="SOFTWARE RESET BIT" mask="0x1"/>
+          <bitfield name="ENABLE" caption="ENABLE BIT" mask="0x2"/>
+          <bitfield name="ANAEN" caption="Analog Enable" mask="0x4"/>
+          <bitfield name="AIPMPEN" caption="Charge Pump Enable" mask="0x10"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL B REGISTER">
+          <bitfield name="ADCHSEL" caption="Software Trigger Channel Select" mask="0xF"/>
+          <bitfield name="ADCORSEL" caption="Software Trigger Core Select" mask="0x30"/>
+          <bitfield name="RQCNVRT" caption="Request Channel Convert" mask="0x40"/>
+          <bitfield name="SAMP" caption="Channel Sample" mask="0x80"/>
+          <bitfield name="GSWTRG" caption="Global Software Trigger" mask="0x100"/>
+          <bitfield name="LSWTRG" caption="Level Global Trigger" mask="0x200"/>
+          <bitfield name="TRGSUSP" caption="Trigger Suspend" mask="0x400"/>
+          <bitfield name="STRGEN" caption="Synchronous Trigger Enable" mask="0x800"/>
+          <bitfield name="SWCNVEN" caption="Software Conversion Enable" mask="0x8000"/>
+        </register>
+        <register name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Control C Register">
+          <bitfield name="CNT" caption="Clock Divider for Synchronous Trigger" mask="0xFFFF"/>
+          <bitfield name="COREINTERLEAVED" caption="Number of Core to Interleave Triggers" mask="0x70000000"/>
+        </register>
+        <register name="CTRLD" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Control D Register">
+          <bitfield name="CTLCKDIV" caption="Control Clock Divider" mask="0x3F00"/>
+          <bitfield name="CHNEN0" caption="Core 0 Digital Channel Enable" mask="0x10000"/>
+          <bitfield name="ANLEN0" caption="Analog and Bias circuitry Enable for core 0" mask="0x100000"/>
+          <bitfield name="WKUPEXP" caption="Wakeup cycles" mask="0xF000000"/>
+          <bitfield name="VREFSEL" caption="Voltage Reference Select" mask="0x70000000" values="CTRLD__VREFSEL"/>
+        </register>
+        <register-group name="CONFIG" name-in-module="CONFIG" offset="0x020" size="0x20" count="1"/>
+        <register name="CMPCTRL" offset="0xB0" rw="RW" size="4" initval="0x00000000" caption="Comparator Control">
+          <bitfield name="ADCMPLO" caption="Low Limit of Digital Comparator" mask="0xFFF"/>
+          <bitfield name="CMPEN" caption="Comparator Enable" mask="0x1000"/>
+          <bitfield name="IELOLO" caption="Enable VAL &lt; CMPLO" mask="0x2000"/>
+          <bitfield name="IELOHI" caption="Enable VAL &gt;= CMPLO" mask="0x4000"/>
+          <bitfield name="IEBTWN" caption="Enable CMPLO &lt;= VAL &lt; CMPHI" mask="0x8000"/>
+          <bitfield name="ADCMPHI" caption="High Limit of Digital Comparator" mask="0xFFF0000"/>
+          <bitfield name="IEHILO" caption="Enable VAL &lt; CMPHI" mask="0x10000000"/>
+          <bitfield name="IEHIHI" caption="Enable VAL &gt;= CMPHI" mask="0x20000000"/>
+        </register>
+        <register name="FLTCTRL" offset="0xC0" rw="RW" size="4" initval="0x00000000" caption="Filter Control">
+          <bitfield name="OVRSAM" caption="Oversampling Ratio" mask="0x7" values="FLTCTRL__OVRSAM"/>
+          <bitfield name="FMODE" caption="Filter Mode" mask="0x8"/>
+          <bitfield name="DATA16EN" caption="16bit Averaging Mode" mask="0x10"/>
+          <bitfield name="FLTEN" caption="Filter Enable" mask="0x100"/>
+          <bitfield name="FLTCHNID" caption="Channel ID" mask="0x3C00"/>
+        </register>
+        <register name="CORCHDATAID" offset="0xD0" rw="RW" size="4" initval="0x00000000" caption="Channel Ready DATA ID">
+          <bitfield name="CHRDYID" caption="Channel Read ID" mask="0xF"/>
+          <bitfield name="CORDYID" caption="Core Read ID" mask="0x30"/>
+        </register>
+        <register name="CHRDYDAT" offset="0xD4" rw="RW" size="4" initval="0x00000000" caption="Channel Ready Data Register">
+          <bitfield name="CHRDYDAT" caption="Channel Output Data" mask="0xFFFF"/>
+          <bitfield name="LVL" caption="Level Setting" mask="0x1000000"/>
+          <bitfield name="DIFF" caption="Differential Setting" mask="0x2000000"/>
+          <bitfield name="SIGN" caption="Sign Setting" mask="0x4000000"/>
+          <bitfield name="FRACT" caption="Fractional Setting" mask="0x8000000"/>
+        </register>
+        <register name="PFFDATA" offset="0xD8" rw="R" size="4" initval="0x00000000" caption="APB FIFO Output Data">
+          <bitfield name="PFFDATA" caption="SARCORE Conversion data from the APB FIFO" mask="0xFFFF"/>
+          <bitfield name="PFFCHNID" caption="Channel ID from APB FIFO" mask="0xF0000"/>
+          <bitfield name="PFFCORID" caption="Core ID from APB FIFO" mask="0x300000"/>
+          <bitfield name="PFFSIGN" caption="Channel Sign from the APB FIFO" mask="0x400000"/>
+          <bitfield name="PFFFRACT" caption="Fractional Setting from APB FIFO" mask="0x800000"/>
+          <bitfield name="PFFCNT" caption="Current Data Entries in APB FIFO" mask="0xFF000000"/>
+        </register>
+        <register name="DMABASE" offset="0xDC" rw="RW" size="4" initval="0x00000000" caption="DMA Sample Base Address">
+          <bitfield name="DMABASE" caption="DMA Sample Value Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DMACTRL" offset="0xE0" rw="RW" size="4" initval="0x00000000" caption="DMA Control Register">
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="DMACR0" caption="DMA CORE0 Enable" mask="0x10"/>
+          <bitfield name="DMABL" caption="DMA System RAM Buffer Length" mask="0x700"/>
+        </register>
+        <register name="PFFCTRL" offset="0xE4" rw="RW" size="4" initval="0x00000000" caption="APB FIFO Control Register">
+          <bitfield name="PFFEN" caption="APB FIFO Enable" mask="0x2"/>
+          <bitfield name="PFFCR0" caption="APB CORE 0 FIFO Enable" mask="0x10"/>
+          <bitfield name="PFFRDYDM" caption="DMA APB FIFO Data Ready" mask="0x10000" values="PFFCTRL__PFFRDYDM"/>
+        </register>
+        <register name="SYNCBUSY" offset="0xE8" rw="R" size="4" initval="0x00000000" caption="CORE SYNC Busy Status Register">
+          <bitfield name="SWRST" caption="Software Reset Sync Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable bit Sync Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB sync busy" mask="0x4"/>
+        </register>
+        <register name="DMAINTENCLR" offset="0xF0" rw="RW" size="4" atomic-op="clear:DMAINTENCLR" initval="0x00000000" caption="DMA Interrupt Enable Clear">
+          <bitfield name="RAF" caption="Ram Buffer A Full" mask="0xF"/>
+          <bitfield name="RBF" caption="Ram Buffer B Full" mask="0xF0"/>
+          <bitfield name="SOVFL" caption="Synchonizer Overflow" mask="0x10000"/>
+        </register>
+        <register name="DMAINTSET" offset="0xF4" rw="RW" size="4" atomic-op="set:DMAINTSET" initval="0x00000000" caption="DMA Interrupt Enable Set">
+          <bitfield name="RAF" caption="Ram Buffer A Full" mask="0xF"/>
+          <bitfield name="RBF" caption="Ram Buffer B Full" mask="0xF0"/>
+          <bitfield name="SOVFL" caption="Synchonizer Overflow" mask="0x10000"/>
+        </register>
+        <register name="DMAINTFLAG" offset="0xF8" rw="RW" size="4" atomic-op="clear:DMAINTFLAG" initval="0x00000000" caption="DMA Interrupt Flag and Status">
+          <bitfield name="RAF" caption="Ram Buffer A Full" mask="0xF"/>
+          <bitfield name="RBF" caption="Ram Buffer B Full" mask="0xF0"/>
+          <bitfield name="EAF" caption="Ram Buffer A Overflow Error" mask="0xF00"/>
+          <bitfield name="EBF" caption="Ram Buffer B Overflow Error" mask="0xF000"/>
+          <bitfield name="SOVFL" caption="Synchronizer overflow" mask="0x10000"/>
+          <bitfield name="DMAERR" caption="DMA Bus Error" mask="0x20000"/>
+        </register>
+        <register name="CTLINTENSET" offset="0xFC" rw="RW" size="4" atomic-op="set:CTLINTENSET" initval="0x00000000" caption="CORE Controller Interrupt Enable Set">
+          <bitfield name="CRRDY0" caption="Core 0 Ready" mask="0x1"/>
+          <bitfield name="VREFUPD" caption="VREF update" mask="0x40"/>
+          <bitfield name="VREFRDY" caption="VREF Ready" mask="0x80"/>
+          <bitfield name="PFFUNF" caption="APB FIFO Underflow" mask="0x100"/>
+          <bitfield name="PFFOVF" caption="APB FIFO Overflow" mask="0x200"/>
+          <bitfield name="PFFRDY" caption="APB FIFO Ready" mask="0x400"/>
+          <bitfield name="PFFHFUL" caption="APB FIFO Half Full" mask="0x800"/>
+        </register>
+        <register name="CTLINTENCLR" offset="0x100" rw="RW" size="4" atomic-op="clear:CTLINTENCLR" initval="0x00000000" caption="CORE Controller Interrupt Enable Clear">
+          <bitfield name="CRRDY0" caption="Core Ready 0 Disable" mask="0x1"/>
+          <bitfield name="VREFUPD" caption="VREF Update" mask="0x40"/>
+          <bitfield name="VREFRDY" caption="VREF Ready" mask="0x80"/>
+          <bitfield name="PFFUNF" caption="APB FIFO underflow" mask="0x100"/>
+          <bitfield name="PFFOVF" caption="APB FIFO overflow" mask="0x200"/>
+          <bitfield name="PFFRDY" caption="APB FIFO Ready" mask="0x400"/>
+          <bitfield name="PFFHFUL" caption="APB FIFO Half Full" mask="0x800"/>
+        </register>
+        <register name="CTLINTFLAG" offset="0x104" rw="RW" size="4" atomic-op="clear:CTLINTFLAG" initval="0x00000000" caption="CORE Controller Interrupt Flags">
+          <bitfield name="CRRDY" caption="Core Ready" mask="0xF"/>
+          <bitfield name="VREFUPD" caption="VREF update" mask="0x40"/>
+          <bitfield name="VREFRDY" caption="VREF Ready" mask="0x80"/>
+          <bitfield name="PFFUNF" caption="APB FIFO underflow" mask="0x100"/>
+          <bitfield name="PFFOVF" caption="APB FIFO overflow" mask="0x200"/>
+          <bitfield name="PFFRDY" caption="APB FIFO Ready" mask="0x400"/>
+          <bitfield name="PFFHFUL" caption="APB FIFO Half Full" mask="0x800"/>
+        </register>
+        <register-group name="INT" name-in-module="INT" offset="0x120" size="0x10" count="1"/>
+        <register name="DBGCTRL" offset="0x168" rw="RW" size="4" initval="0x00000000" caption="Debug Control Register">
+          <bitfield name="DBGRUN" caption="Debug Running State" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="CORCTRL__SELRES">
+        <value name="6_BITS" caption="6 bits" value="0"/>
+        <value name="8_BITS" caption="8 bits" value="1"/>
+        <value name="10_BITS" caption="10 bits" value="2"/>
+        <value name="12_BITS" caption="12 bits (power-on default)" value="3"/>
+      </value-group>
+      <value-group name="CORCTRL__STRGSRC">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC0">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC1">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC2">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC3">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC4">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC5">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC6">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC7">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC8">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC9">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC10">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC11">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC12">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC13">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC14">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC15">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CTRLD__VREFSEL">
+        <value name="AVDD_AVSS" caption="AVDD and AVSS" value="0"/>
+        <value name="EXTERNAL_VREFH_AVSS" caption="External VREFH and AVSS" value="1"/>
+      </value-group>
+      <value-group name="FLTCTRL__OVRSAM">
+        <value name="4_SAMPLES" caption="(If FMODE is 0) 4 samples (shift sum 1 bit to right, output data is 13-bits) / (If FMODE is 1) 2 samples to be averaged" value="0"/>
+        <value name="16_SAMPLES" caption="(If FMODE is 0) 16 samples (shift sum 2 bits to right, output data is 14-bits) / (If FMODE is 1) 4 samples to be averaged" value="1"/>
+        <value name="64_SAMPLES" caption="(If FMODE is 0) 64 samples (shift sum 3 bits to right, output data is 15-bits) / (If FMODE is 1) 8 samples to be averaged" value="2"/>
+        <value name="256_SAMPLES" caption="(If FMODE is 0) 256 samples (shift sum 4 bits to right, output data is 16-bits) / (If FMODE is 1) 16 samples to be averaged" value="3"/>
+        <value name="2_SAMPLES" caption="(If FMODE is 0) 2 samples (shift sum 0 bits to right, output data is 12.1 format) / (If FMODE is 1) 32 samples to be averaged" value="4"/>
+        <value name="8_SAMPLES" caption="(If FMODE is 0) 8 samples (shift sum 1 bit to right, output data is 13.1 format) / (If FMODE is 1) 64 samples to be averaged" value="5"/>
+        <value name="32_SAMPLES" caption="(If FMODE is 0) 32 samples (shift sum 2 bits to right, output data is 14.1 format) / (If FMODE is 1) 128 samples to be averaged" value="6"/>
+        <value name="128_SAMPLES" caption="(If FMODE is 0) 128 samples (shift sum 3 bits to right, output data is 15.1 format) / (If FMODE is 1) 256 samples to be averaged" value="7"/>
+      </value-group>
+      <value-group name="PFFCTRL__PFFRDYDM">
+        <value name="CTLINTFLAG_PFFHFUL" caption="Selects CTLINTFLAG.PFFHFUL for the ADC DMA PFFRDY trigger signal to the DMAC" value="0"/>
+        <value name="CTLINTFLAG_PFFRDY" caption="Selects CTLINTFLAG.PFFRDY for the ADC DMA PFFRDY trigger signal to the DMAC" value="1"/>
+      </value-group>
+    </module>
+    <module name="AT" id="04932" name2="sec_anti_tamper_v1" version="1a0" caption="Anti-Tamper Controller (AT)">
+      <register-group name="AT" caption="Anti-Tamper Controller (AT)">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control Register A">
+          <bitfield name="SWRST" caption="Software Reset1 = Reset registers , Bus I/F and internal state0 = No effect" mask="0x1"/>
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+          <bitfield name="RUNSTDBY" caption="RUNSTDBY Enable Bit" mask="0x40"/>
+        </register>
+        <register name="TAMPER_KEY" offset="0x100" rw="RW" size="4" count="16" initval="0x00000000" caption="Tamper Key n Register">
+          <bitfield name="TAMPERKEY" caption="Tamper Key Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__LEVELA" offset="0x200" rw="R" size="4" initval="0x00000000" caption="Tamper levels 0 to 7.">
+          <bitfield name="LEVEL0" caption="Level 0." mask="0xF"/>
+          <bitfield name="LEVEL1" caption="Level 1." mask="0xF0"/>
+          <bitfield name="LEVEL2" caption="Level 2." mask="0xF00"/>
+          <bitfield name="LEVEL3" caption="Level 3." mask="0xF000"/>
+          <bitfield name="LEVEL4" caption="Level 4." mask="0xF0000"/>
+          <bitfield name="LEVEL5" caption="Level 5." mask="0xF00000"/>
+          <bitfield name="LEVEL6" caption="Level 6." mask="0xF000000"/>
+          <bitfield name="LEVEL7" caption="Level 7." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__LEVELB" offset="0x204" rw="R" size="4" initval="0x00000000" caption="Tamper levels 8 to 15.">
+          <bitfield name="LEVEL8" caption="Level 8." mask="0xF"/>
+          <bitfield name="LEVEL9" caption="Level 9." mask="0xF0"/>
+          <bitfield name="LEVEL10" caption="Level 10." mask="0xF00"/>
+          <bitfield name="LEVEL11" caption="Level 11." mask="0xF000"/>
+          <bitfield name="LEVEL12" caption="Level 12." mask="0xF0000"/>
+          <bitfield name="LEVEL13" caption="Level 13." mask="0xF00000"/>
+          <bitfield name="LEVEL14" caption="Level 14." mask="0xF000000"/>
+          <bitfield name="LEVEL15" caption="Level 15." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__LEVELC" offset="0x208" rw="R" size="4" initval="0x00000000" caption="Tamper levels 16 to 23.">
+          <bitfield name="LEVEL16" caption="Level 16." mask="0xF"/>
+          <bitfield name="LEVEL17" caption="Level 17." mask="0xF0"/>
+          <bitfield name="LEVEL18" caption="Level 18." mask="0xF00"/>
+          <bitfield name="LEVEL19" caption="Level 19." mask="0xF000"/>
+          <bitfield name="LEVEL20" caption="Level 20." mask="0xF0000"/>
+          <bitfield name="LEVEL21" caption="Level 21." mask="0xF00000"/>
+          <bitfield name="LEVEL22" caption="Level 22." mask="0xF000000"/>
+          <bitfield name="LEVEL23" caption="Level 23." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__LEVELD" offset="0x20C" rw="R" size="4" initval="0x00000000" caption="Tamper levels 24 to 31.">
+          <bitfield name="LEVEL24" caption="Level 24." mask="0xF"/>
+          <bitfield name="LEVEL25" caption="Level 25." mask="0xF0"/>
+          <bitfield name="LEVEL26" caption="Level 26." mask="0xF00"/>
+          <bitfield name="LEVEL27" caption="Level 27." mask="0xF000"/>
+          <bitfield name="LEVEL28" caption="Level 28." mask="0xF0000"/>
+          <bitfield name="LEVEL29" caption="Level 29." mask="0xF00000"/>
+          <bitfield name="LEVEL30" caption="Level 30." mask="0xF000000"/>
+          <bitfield name="LEVEL31" caption="Level 31." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__SETLEVEL" offset="0x210" rw="W" size="4" initval="0x00000000" caption="Set tamper level.">
+          <bitfield name="LEVEL" caption="Tamper level." mask="0x7"/>
+          <bitfield name="ID" caption="Tamper ID." mask="0x1F00"/>
+          <bitfield name="PROTKEY" caption="Protection key (0xA84C)." mask="0xFFFF0000"/>
+        </register>
+        <register name="anti_tamper__FILTERCFG" offset="0x214" rw="RW" size="4" initval="0x00000000" caption="Filter configuration (threshold, period).">
+          <bitfield name="THRESH" caption="Threshold." mask="0x7"/>
+          <bitfield name="PERIOD" caption="Period." mask="0x1F00"/>
+          <bitfield name="PROTKEY" caption="Protection key (0x92F5)." mask="0xFFFF0000"/>
+        </register>
+        <register name="anti_tamper__SOFTTAMP" offset="0x218" rw="RW" size="4" initval="0x00000000" caption="Software triggered tamper.">
+          <bitfield name="ACTIVE" caption="Tamper active." mask="0x1"/>
+          <bitfield name="ID" caption="Tamper ID." mask="0x1F00"/>
+          <bitfield name="PROTKEY" caption="Protection key (0x4BEE)." mask="0xFFFF0000"/>
+        </register>
+        <register name="anti_tamper__RAWSTAT" offset="0x21C" rw="R" size="4" initval="0x00000000" caption="Raw status.">
+          <bitfield name="RAWSTAT" caption="Raw status." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__STAT" offset="0x220" rw="RW" size="4" initval="0x00000001" caption="Status (write to clear).">
+          <bitfield name="STAT" caption="Status (write to clear)." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__TIMESTAMP" offset="0x224" rw="R" size="4" initval="0x00000000" caption="Timestamp for the last tamper.">
+          <bitfield name="TIMESTAMP" caption="Timestamp for the last tamper." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__FILTERCNT" offset="0x228" rw="R" size="4" initval="0x00000000" caption="Current value of filter counter.">
+          <bitfield name="FILTERCNT" caption="Current value of filter counter." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__SOFTINFO" offset="0x22C" rw="RW" size="4" initval="0x00000000" caption="Register for software purpose only.">
+          <bitfield name="SOFTINFO" caption="Register for software purpose only." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__TAMPERFLAG" offset="0x230" rw="RW" size="4" initval="0x00000000" caption="The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output.">
+          <bitfield name="TAMPERFLAG" caption="The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output." mask="0x1"/>
+        </register>
+        <register name="anti_tamper__SOFTRESET" offset="0x234" rw="R" size="4" atomic-op="set:anti_tamper__SOFTRESET" initval="0x00000000" caption="Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above.">
+          <bitfield name="SOFTRESET" caption="Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above." mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="0" caption="AT registers accessible in privileged and unprivileged modes." value="0"/>
+        <value name="1" caption="AT registers only accessible in privileged mode." value="1"/>
+      </value-group>
+    </module>
+    <module name="BROMC" id="04402" name2="prm_boot_ahb_v2" version="2a0" caption="ARM GF55LPx Boot ROM Controller Macro">
+      <register-group name="BROMC" caption="ARM GF55LPx Boot ROM Controller Macro">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000002" caption="Control A REGISTER">
+          <bitfield name="SWRST" caption="Software Reset bit" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable bit" mask="0x2" values="CTRLA__ENABLE"/>
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+          <bitfield name="PRMWS" caption="ROM Access Time Wait State" mask="0x700" values="CTRLA__PRMWS"/>
+        </register>
+        <register name="UCFG" offset="0x4" rw="R" size="4" initval="0x00000001" caption="User Configuration REGISTER">
+          <bitfield name="BCRCDIS" caption="Boot CRC Disable" mask="0x1" values="UCFG__BCRCDIS"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__ENABLE">
+        <value name="0" caption="Disable ROM read access and power down the ROM. The ROM PGEN input is driven high. The ROM will clamp outputs to 1 and disable all internal current sinks. Refer to the ROM compiler specification for details on powering down the ROM." value="0"/>
+        <value name="1" caption="Enable ROM read access, power up the ROM. The ROM PGEN input is driven low." value="1"/>
+      </value-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="0" caption="Macro register accessible in privileged and unprivileged modes" value="0"/>
+        <value name="1" caption="Macro registers only accessible in privileged mode" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__PRMWS">
+        <value name="0" caption="No wait states, single cycle access" value="0"/>
+        <value name="1" caption="Access time extended 2 clock cycles" value="1"/>
+        <value name="2" caption="Access time extended to 3 clock cycles" value="2"/>
+        <value name="7" caption="Access time extended to 8 clock cycles" value="7"/>
+      </value-group>
+      <value-group name="UCFG__BCRCDIS">
+        <value name="0" caption="Boot ROM content is CRC verified by the ROM controller, status is reported to the DSU. On CRC failure, the controller blocks access to the ROM controller." value="0"/>
+        <value name="1" caption="No CRC verification at Boot." value="1"/>
+      </value-group>
+    </module>
+    <module name="CAN" id="05010" name2="can_fd_apb_v1" version="1a0" caption="Control Area Network">
+      <register-group name="CAN" caption="Control Area Network">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="PRIV" caption="Priveged Access" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run during standby" mask="0x40"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B Register">
+          <bitfield name="OFFSET" caption="Message RAM Base Address Offset." mask="0xFF0000"/>
+        </register>
+        <register name="INTENCLR" offset="0x28" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear register">
+          <bitfield name="DBG" caption="Debug Message Interrupt Disable" mask="0x1"/>
+          <bitfield name="BERR" caption="Bus Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x2C" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set register">
+          <bitfield name="DBG" caption="Debug Message Interrupt Enable" mask="0x1"/>
+          <bitfield name="BERR" caption="Bus Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x30" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear register">
+          <bitfield name="DBG" caption="Debug Message Reception" mask="0x1"/>
+          <bitfield name="BERR" caption="AHB Bus Error Detection" mask="0x2"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x34" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="Interrupt Flag Software Set Register">
+          <bitfield name="DBG" caption="Debug Message Interrupt Flag Set" mask="0x1"/>
+          <bitfield name="BERR" caption="AHB Bus Error Detection Interrupt Flag Set" mask="0x2"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x5C" rw="R" size="4" initval="0x00000000" caption="SYNCBUSY Register">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+        </register>
+        <register name="CREL_MCAN" offset="0x100" rw="R" size="4" initval="0x33000000" caption="Core Release">
+          <bitfield name="DAY" caption="Timestamp day" mask="0xFF"/>
+          <bitfield name="MON" caption="Timestamp month" mask="0xFF00"/>
+          <bitfield name="YEAR" caption="Timestamp year" mask="0xF0000"/>
+          <bitfield name="SUBSTEP" caption="Sub-step of Core Release" mask="0xF00000"/>
+          <bitfield name="STEP" caption="Step of Core Release" mask="0xF000000"/>
+          <bitfield name="REL" caption="Core Release" mask="0xF0000000"/>
+        </register>
+        <register name="ENDN" offset="0x104" rw="R" size="4" initval="0x87654321" caption="Endian">
+          <bitfield name="ETV" caption="Endianness Test Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CUST" offset="0x108" rw="RW" size="4" initval="0x00000000" caption="Customer Register">
+          <bitfield name="CUST" caption="Customer Register" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DBTP" offset="0x10C" rw="RW" size="4" initval="0x00000A33" caption="Fast Bit Timing and Prescaler">
+          <bitfield name="DSJW" caption="Data (Re)Synchronization Jump Width" mask="0xF"/>
+          <bitfield name="DTSEG2" caption="Data time segment after sample point" mask="0xF0"/>
+          <bitfield name="DTSEG1" caption="Data time segment before sample point" mask="0x1F00"/>
+          <bitfield name="DBRP" caption="Data Baud Rate Prescaler" mask="0x1F0000"/>
+          <bitfield name="TDC" caption="Tranceiver Delay Compensation" mask="0x800000"/>
+        </register>
+        <register name="TEST" offset="0x110" rw="RW" size="4" initval="0x00000000" caption="Test">
+          <bitfield name="LBCK" caption="Loop Back Mode" mask="0x10"/>
+          <bitfield name="TX" caption="Control of Transmit Pin" mask="0x60" values="TEST__TX"/>
+          <bitfield name="RX" caption="Receive Pin" mask="0x80"/>
+        </register>
+        <register name="RWD" offset="0x114" rw="RW" size="4" initval="0x00000000" caption="RAM Watchdog">
+          <bitfield name="WDC" caption="Watchdog Configuration" mask="0xFF"/>
+          <bitfield name="WDV" caption="Watchdog Value" mask="0xFF00"/>
+        </register>
+        <register name="CCCR" offset="0x118" rw="RW" access="WSYNC" size="4" initval="0x00000001" caption="CC Control">
+          <bitfield name="INIT" caption="Initialization" mask="0x1"/>
+          <bitfield name="CCE" caption="Configuration Change Enable" mask="0x2"/>
+          <bitfield name="ASM" caption="ASM Restricted Operation Mode" mask="0x4"/>
+          <bitfield name="CSA" caption="Clock Stop Acknowledge" mask="0x8"/>
+          <bitfield name="CSR" caption="Clock Stop Request" mask="0x10"/>
+          <bitfield name="MON" caption="Bus Monitoring Mode" mask="0x20"/>
+          <bitfield name="DAR" caption="Disable Automatic Retransmission" mask="0x40"/>
+          <bitfield name="TEST" caption="Test Mode Enable" mask="0x80"/>
+          <bitfield name="FDOE" caption="FD Operation Enable" mask="0x100"/>
+          <bitfield name="BRSE" caption="Bit Rate Switch Enable" mask="0x200"/>
+          <bitfield name="UTSU" caption="Use Timestamping Unit" mask="0x400"/>
+          <bitfield name="WMM" caption="Wide Message Marker" mask="0x800"/>
+          <bitfield name="PXHD" caption="Protocol Exception Handling Disable" mask="0x1000"/>
+          <bitfield name="EFBI" caption="Edge Filtering during Bus Integration" mask="0x2000"/>
+          <bitfield name="TXP" caption="Transmit Pause" mask="0x4000"/>
+        </register>
+        <register name="NBTP" offset="0x11C" rw="RW" size="4" initval="0x06000A03" caption="Nominal Bit Timing and Prescaler">
+          <bitfield name="NTSEG2" caption="Nominal Time segment after sample point" mask="0x7F"/>
+          <bitfield name="NTSEG1" caption="Nominal Time segment before sample point" mask="0xFF00"/>
+          <bitfield name="NBRP" caption="Nominal Baud Rate Prescaler" mask="0x1FF0000"/>
+          <bitfield name="NSJW" caption="Nominal (Re)Synchronization Jump Width" mask="0xFE000000"/>
+        </register>
+        <register name="TSCC" offset="0x120" rw="RW" size="4" initval="0x00000000" caption="Timestamp Counter Configuration">
+          <bitfield name="TSS" caption="Timestamp Select" mask="0x3" values="TSCC__TSS"/>
+          <bitfield name="TCP" caption="Timestamp Counter Prescaler" mask="0xF0000"/>
+        </register>
+        <register name="TSCV" offset="0x124" rw="R" size="4" initval="0x00000000" caption="Timestamp Counter Value">
+          <bitfield name="TSC" caption="Timestamp Counter" mask="0xFFFF"/>
+        </register>
+        <register name="TOCC" offset="0x128" rw="RW" size="4" initval="0xFFFF0000" caption="Timeout Counter Configuration">
+          <bitfield name="ETOC" caption="Enable Timeout Counter" mask="0x1"/>
+          <bitfield name="TOS" caption="Timeout Select" mask="0x6" values="TOCC__TOS"/>
+          <bitfield name="TOP" caption="Timeout Period" mask="0xFFFF0000"/>
+        </register>
+        <register name="TOCV" offset="0x12C" rw="RW" size="4" initval="0x0000FFFF" caption="Timeout Counter Value">
+          <bitfield name="TOC" caption="Timeout Counter" mask="0xFFFF"/>
+        </register>
+        <register name="ECR" offset="0x140" rw="R" size="4" initval="0x00000000" caption="Error Counter">
+          <bitfield name="TEC" caption="Transmit Error Counter" mask="0xFF"/>
+          <bitfield name="REC" caption="Receive Error Counter" mask="0x7F00"/>
+          <bitfield name="RP" caption="Receive Error Passive" mask="0x8000"/>
+          <bitfield name="CEL" caption="CAN Error Logging" mask="0xFF0000"/>
+        </register>
+        <register name="PSR" offset="0x144" rw="R" size="4" initval="0x00000707" caption="Protocol Status">
+          <bitfield name="LEC" caption="Last Error Code" mask="0x7" values="PSR__LEC"/>
+          <bitfield name="ACT" caption="Activity" mask="0x18" values="PSR__ACT"/>
+          <bitfield name="EP" caption="Error Passive" mask="0x20"/>
+          <bitfield name="EW" caption="Warning Status" mask="0x40"/>
+          <bitfield name="BO" caption="Bus_Off Status" mask="0x80"/>
+          <bitfield name="DLEC" caption="Data Phase Last Error Code" mask="0x700" values="PSR__DLEC"/>
+          <bitfield name="RESI" caption="ESI flag of last received CAN FD Message" mask="0x800"/>
+          <bitfield name="RBRS" caption="BRS flag of last received CAN FD Message" mask="0x1000"/>
+          <bitfield name="RFDF" caption="Received a CAN FD Message" mask="0x2000"/>
+          <bitfield name="PXE" caption="Protocol Exception Event" mask="0x4000"/>
+          <bitfield name="TDCV" caption="Transmitter Delay Compensation Value" mask="0x7F0000"/>
+        </register>
+        <register name="TDCR" offset="0x148" rw="RW" size="4" initval="0x00000000" caption="Extended ID Filter Configuration">
+          <bitfield name="TDCF" caption="Transmitter Delay Compensation Filter Length" mask="0x7F"/>
+          <bitfield name="TDCO" caption="Transmitter Delay Compensation Offset" mask="0x7F00"/>
+        </register>
+        <register name="IR" offset="0x150" rw="RW" size="4" initval="0x00000000" caption="Interrupt">
+          <bitfield name="RF0N" caption="Rx FIFO 0 New Message" mask="0x1"/>
+          <bitfield name="RF0W" caption="Rx FIFO 0 Watermark Reached" mask="0x2"/>
+          <bitfield name="RF0F" caption="Rx FIFO 0 Full" mask="0x4"/>
+          <bitfield name="RF0L" caption="Rx FIFO 0 Message Lost" mask="0x8"/>
+          <bitfield name="RF1N" caption="Rx FIFO 1 New Message" mask="0x10"/>
+          <bitfield name="RF1W" caption="Rx FIFO 1 Watermark Reached" mask="0x20"/>
+          <bitfield name="RF1F" caption="Rx FIFO 1 FIFO Full" mask="0x40"/>
+          <bitfield name="RF1L" caption="Rx FIFO 1 Message Lost" mask="0x80"/>
+          <bitfield name="HPM" caption="High Priority Message" mask="0x100"/>
+          <bitfield name="TC" caption="Timestamp Completed" mask="0x200"/>
+          <bitfield name="TCF" caption="Transmission Cancellation Finished" mask="0x400"/>
+          <bitfield name="TFE" caption="Tx FIFO Empty" mask="0x800"/>
+          <bitfield name="TEFN" caption="Tx Event FIFO New Entry" mask="0x1000"/>
+          <bitfield name="TEFW" caption="Tx Event FIFO Watermark Reached" mask="0x2000"/>
+          <bitfield name="TEFF" caption="Tx Event FIFO Full" mask="0x4000"/>
+          <bitfield name="TEFL" caption="Tx Event FIFO Element Lost" mask="0x8000"/>
+          <bitfield name="TSW" caption="Timestamp Wraparound" mask="0x10000"/>
+          <bitfield name="MRAF" caption="Message RAM Access Failure" mask="0x20000"/>
+          <bitfield name="TOO" caption="Timeout Occurred" mask="0x40000"/>
+          <bitfield name="DRX" caption="Message stored to Dedicated Rx Buffer" mask="0x80000"/>
+          <bitfield name="ELO" caption="Error Logging Overflow" mask="0x400000"/>
+          <bitfield name="EP" caption="Error Passive" mask="0x800000"/>
+          <bitfield name="EW" caption="Warning Status" mask="0x1000000"/>
+          <bitfield name="BO" caption="Bus_Off Status" mask="0x2000000"/>
+          <bitfield name="WDI" caption="Watchdog Interrupt" mask="0x4000000"/>
+          <bitfield name="PEA" caption="Protocol Error in Arbitration Phase" mask="0x8000000"/>
+          <bitfield name="PED" caption="Protocol Error in Data Phase" mask="0x10000000"/>
+          <bitfield name="ARA" caption="Access to Reserved Address" mask="0x20000000"/>
+        </register>
+        <register name="IE" offset="0x154" rw="RW" size="4" initval="0x00000000" caption="Interrupt Enable">
+          <bitfield name="RF0NE" caption="Rx FIFO 0 New Message Interrupt Enable" mask="0x1"/>
+          <bitfield name="RF0WE" caption="Rx FIFO 0 Watermark Reached Interrupt Enable" mask="0x2"/>
+          <bitfield name="RF0FE" caption="Rx FIFO 0 Full Interrupt Enable" mask="0x4"/>
+          <bitfield name="RF0LE" caption="Rx FIFO 0 Message Lost Interrupt Enable" mask="0x8"/>
+          <bitfield name="RF1NE" caption="Rx FIFO 1 New Message Interrupt Enable" mask="0x10"/>
+          <bitfield name="RF1WE" caption="Rx FIFO 1 Watermark Reached Interrupt Enable" mask="0x20"/>
+          <bitfield name="RF1FE" caption="Rx FIFO 1 FIFO Full Interrupt Enable" mask="0x40"/>
+          <bitfield name="RF1LE" caption="Rx FIFO 1 Message Lost Interrupt Enable" mask="0x80"/>
+          <bitfield name="HPME" caption="High Priority Message Interrupt Enable" mask="0x100"/>
+          <bitfield name="TCE" caption="Timestamp Completed Interrupt Enable" mask="0x200"/>
+          <bitfield name="TCFE" caption="Transmission Cancellation Finished Interrupt Enable" mask="0x400"/>
+          <bitfield name="TFEE" caption="Tx FIFO Empty Interrupt Enable" mask="0x800"/>
+          <bitfield name="TEFNE" caption="Tx Event FIFO New Entry Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TEFWE" caption="Tx Event FIFO Watermark Reached Interrupt Enable" mask="0x2000"/>
+          <bitfield name="TEFFE" caption="Tx Event FIFO Full Interrupt Enable" mask="0x4000"/>
+          <bitfield name="TEFLE" caption="Tx Event FIFO Element Lost Interrupt Enable" mask="0x8000"/>
+          <bitfield name="TSWE" caption="Timestamp Wraparound Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MRAFE" caption="Message RAM Access Failure Interrupt Enable" mask="0x20000"/>
+          <bitfield name="TOOE" caption="Timeout Occurred Interrupt Enable" mask="0x40000"/>
+          <bitfield name="DRXE" caption="Message stored to Dedicated Rx Buffer Interrupt Enable" mask="0x80000"/>
+          <bitfield name="ELOE" caption="Error Logging Overflow Interrupt Enable" mask="0x400000"/>
+          <bitfield name="EPE" caption="Error Passive Interrupt Enable" mask="0x800000"/>
+          <bitfield name="EWE" caption="Warning Status Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="BOE" caption="Bus_Off Status Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="WDIE" caption="Watchdog Interrupt Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="PEAE" caption="Protocol Error in Arbitration Phase Enable" mask="0x8000000"/>
+          <bitfield name="PEDE" caption="Protocol Error in Data Phase Enable" mask="0x10000000"/>
+          <bitfield name="ARAE" caption="Access to Reserved Address Enable" mask="0x20000000"/>
+        </register>
+        <register name="ILS" offset="0x158" rw="RW" size="4" initval="0x00000000" caption="Interrupt Line Select">
+          <bitfield name="RF0NL" caption="Rx FIFO 0 New Message Interrupt Line" mask="0x1"/>
+          <bitfield name="RF0WL" caption="Rx FIFO 0 Watermark Reached Interrupt Line" mask="0x2"/>
+          <bitfield name="RF0FL" caption="Rx FIFO 0 Full Interrupt Line" mask="0x4"/>
+          <bitfield name="RF0LL" caption="Rx FIFO 0 Message Lost Interrupt Line" mask="0x8"/>
+          <bitfield name="RF1NL" caption="Rx FIFO 1 New Message Interrupt Line" mask="0x10"/>
+          <bitfield name="RF1WL" caption="Rx FIFO 1 Watermark Reached Interrupt Line" mask="0x20"/>
+          <bitfield name="RF1FL" caption="Rx FIFO 1 FIFO Full Interrupt Line" mask="0x40"/>
+          <bitfield name="RF1LL" caption="Rx FIFO 1 Message Lost Interrupt Line" mask="0x80"/>
+          <bitfield name="HPML" caption="High Priority Message Interrupt Line" mask="0x100"/>
+          <bitfield name="TCL" caption="Timestamp Completed Interrupt Line" mask="0x200"/>
+          <bitfield name="TCFL" caption="Transmission Cancellation Finished Interrupt Line" mask="0x400"/>
+          <bitfield name="TFEL" caption="Tx FIFO Empty Interrupt Line" mask="0x800"/>
+          <bitfield name="TEFNL" caption="Tx Event FIFO New Entry Interrupt Line" mask="0x1000"/>
+          <bitfield name="TEFWL" caption="Tx Event FIFO Watermark Reached Interrupt Line" mask="0x2000"/>
+          <bitfield name="TEFFL" caption="Tx Event FIFO Full Interrupt Line" mask="0x4000"/>
+          <bitfield name="TEFLL" caption="Tx Event FIFO Element Lost Interrupt Line" mask="0x8000"/>
+          <bitfield name="TSWL" caption="Timestamp Wraparound Interrupt Line" mask="0x10000"/>
+          <bitfield name="MRAFL" caption="Message RAM Access Failure Interrupt Line" mask="0x20000"/>
+          <bitfield name="TOOL" caption="Timeout Occurred Interrupt Line" mask="0x40000"/>
+          <bitfield name="DRXL" caption="Message stored to Dedicated Rx Buffer Interrupt Line" mask="0x80000"/>
+          <bitfield name="ELOL" caption="Error Logging Overflow Interrupt Line" mask="0x400000"/>
+          <bitfield name="EPL" caption="Error Passive Interrupt Line" mask="0x800000"/>
+          <bitfield name="EWL" caption="Warning Status Interrupt Line" mask="0x1000000"/>
+          <bitfield name="BOL" caption="Bus_Off Status Interrupt Line" mask="0x2000000"/>
+          <bitfield name="WDIL" caption="Watchdog Interrupt Interrupt Line" mask="0x4000000"/>
+          <bitfield name="PEAL" caption="Protocol Error in Arbitration Phase Line" mask="0x8000000"/>
+          <bitfield name="PEDL" caption="Protocol Error in Data Phase Line" mask="0x10000000"/>
+          <bitfield name="ARAL" caption="Access to Reserved Address Line" mask="0x20000000"/>
+        </register>
+        <register name="ILE" offset="0x15C" rw="RW" size="4" initval="0x00000000" caption="Interrupt Line Enable">
+          <bitfield name="EINT0" caption="Enable Interrupt Line 0" mask="0x1"/>
+          <bitfield name="EINT1" caption="Enable Interrupt Line 1" mask="0x2"/>
+        </register>
+        <register name="GFC" offset="0x180" rw="RW" size="4" initval="0x00000000" caption="Global Filter Configuration">
+          <bitfield name="RRFE" caption="Reject Remote Frames Extended" mask="0x1"/>
+          <bitfield name="RRFS" caption="Reject Remote Frames Standard" mask="0x2"/>
+          <bitfield name="ANFE" caption="Accept Non-matching Frames Extended" mask="0xC" values="GFC__ANFE"/>
+          <bitfield name="ANFS" caption="Accept Non-matching Frames Standard" mask="0x30" values="GFC__ANFS"/>
+        </register>
+        <register name="SIDFC" offset="0x184" rw="RW" size="4" initval="0x00000000" caption="Standard ID Filter Configuration">
+          <bitfield name="FLSSA" caption="Filter List Standard Start Address" mask="0xFFFC"/>
+          <bitfield name="LSS" caption="List Size Standard" mask="0xFF0000"/>
+        </register>
+        <register name="XIDFC" offset="0x188" rw="RW" size="4" initval="0x00000000" caption="Extended ID Filter Configuration">
+          <bitfield name="FLESA" caption="Filter List Extended Start Address" mask="0xFFFC"/>
+          <bitfield name="LSE" caption="List Size Extended" mask="0x7F0000"/>
+        </register>
+        <register name="XIDAM" offset="0x190" rw="RW" size="4" initval="0x1FFFFFFF" caption="Extended ID AND Mask">
+          <bitfield name="EIDM" caption="Extended ID Mask" mask="0x1FFFFFFF"/>
+        </register>
+        <register name="HPMS" offset="0x194" rw="R" size="4" initval="0x00000000" caption="High Priority Message Status">
+          <bitfield name="BIDX" caption="Buffer Index" mask="0x3F"/>
+          <bitfield name="MSI" caption="Message Storage Indicator" mask="0xC0" values="HPMS__MSI"/>
+          <bitfield name="FIDX" caption="Filter Index" mask="0x7F00"/>
+          <bitfield name="FLST" caption="Filter List" mask="0x8000"/>
+        </register>
+        <register name="NDAT1" offset="0x198" rw="RW" size="4" initval="0x00000000" caption="New Data 1">
+          <bitfield name="ND0" caption="New Data 0" mask="0x1"/>
+          <bitfield name="ND1" caption="New Data 1" mask="0x2"/>
+          <bitfield name="ND2" caption="New Data 2" mask="0x4"/>
+          <bitfield name="ND3" caption="New Data 3" mask="0x8"/>
+          <bitfield name="ND4" caption="New Data 4" mask="0x10"/>
+          <bitfield name="ND5" caption="New Data 5" mask="0x20"/>
+          <bitfield name="ND6" caption="New Data 6" mask="0x40"/>
+          <bitfield name="ND7" caption="New Data 7" mask="0x80"/>
+          <bitfield name="ND8" caption="New Data 8" mask="0x100"/>
+          <bitfield name="ND9" caption="New Data 9" mask="0x200"/>
+          <bitfield name="ND10" caption="New Data 10" mask="0x400"/>
+          <bitfield name="ND11" caption="New Data 11" mask="0x800"/>
+          <bitfield name="ND12" caption="New Data 12" mask="0x1000"/>
+          <bitfield name="ND13" caption="New Data 13" mask="0x2000"/>
+          <bitfield name="ND14" caption="New Data 14" mask="0x4000"/>
+          <bitfield name="ND15" caption="New Data 15" mask="0x8000"/>
+          <bitfield name="ND16" caption="New Data 16" mask="0x10000"/>
+          <bitfield name="ND17" caption="New Data 17" mask="0x20000"/>
+          <bitfield name="ND18" caption="New Data 18" mask="0x40000"/>
+          <bitfield name="ND19" caption="New Data 19" mask="0x80000"/>
+          <bitfield name="ND20" caption="New Data 20" mask="0x100000"/>
+          <bitfield name="ND21" caption="New Data 21" mask="0x200000"/>
+          <bitfield name="ND22" caption="New Data 22" mask="0x400000"/>
+          <bitfield name="ND23" caption="New Data 23" mask="0x800000"/>
+          <bitfield name="ND24" caption="New Data 24" mask="0x1000000"/>
+          <bitfield name="ND25" caption="New Data 25" mask="0x2000000"/>
+          <bitfield name="ND26" caption="New Data 26" mask="0x4000000"/>
+          <bitfield name="ND27" caption="New Data 27" mask="0x8000000"/>
+          <bitfield name="ND28" caption="New Data 28" mask="0x10000000"/>
+          <bitfield name="ND29" caption="New Data 29" mask="0x20000000"/>
+          <bitfield name="ND30" caption="New Data 30" mask="0x40000000"/>
+          <bitfield name="ND31" caption="New Data 31" mask="0x80000000"/>
+        </register>
+        <register name="NDAT2" offset="0x19C" rw="RW" size="4" initval="0x00000000" caption="New Data 2">
+          <bitfield name="ND32" caption="New Data 32" mask="0x1"/>
+          <bitfield name="ND33" caption="New Data 33" mask="0x2"/>
+          <bitfield name="ND34" caption="New Data 34" mask="0x4"/>
+          <bitfield name="ND35" caption="New Data 35" mask="0x8"/>
+          <bitfield name="ND36" caption="New Data 36" mask="0x10"/>
+          <bitfield name="ND37" caption="New Data 37" mask="0x20"/>
+          <bitfield name="ND38" caption="New Data 38" mask="0x40"/>
+          <bitfield name="ND39" caption="New Data 39" mask="0x80"/>
+          <bitfield name="ND40" caption="New Data 40" mask="0x100"/>
+          <bitfield name="ND41" caption="New Data 41" mask="0x200"/>
+          <bitfield name="ND42" caption="New Data 42" mask="0x400"/>
+          <bitfield name="ND43" caption="New Data 43" mask="0x800"/>
+          <bitfield name="ND44" caption="New Data 44" mask="0x1000"/>
+          <bitfield name="ND45" caption="New Data 45" mask="0x2000"/>
+          <bitfield name="ND46" caption="New Data 46" mask="0x4000"/>
+          <bitfield name="ND47" caption="New Data 47" mask="0x8000"/>
+          <bitfield name="ND48" caption="New Data 48" mask="0x10000"/>
+          <bitfield name="ND49" caption="New Data 49" mask="0x20000"/>
+          <bitfield name="ND50" caption="New Data 50" mask="0x40000"/>
+          <bitfield name="ND51" caption="New Data 51" mask="0x80000"/>
+          <bitfield name="ND52" caption="New Data 52" mask="0x100000"/>
+          <bitfield name="ND53" caption="New Data 53" mask="0x200000"/>
+          <bitfield name="ND54" caption="New Data 54" mask="0x400000"/>
+          <bitfield name="ND55" caption="New Data 55" mask="0x800000"/>
+          <bitfield name="ND56" caption="New Data 56" mask="0x1000000"/>
+          <bitfield name="ND57" caption="New Data 57" mask="0x2000000"/>
+          <bitfield name="ND58" caption="New Data 58" mask="0x4000000"/>
+          <bitfield name="ND59" caption="New Data 59" mask="0x8000000"/>
+          <bitfield name="ND60" caption="New Data 60" mask="0x10000000"/>
+          <bitfield name="ND61" caption="New Data 61" mask="0x20000000"/>
+          <bitfield name="ND62" caption="New Data 62" mask="0x40000000"/>
+          <bitfield name="ND63" caption="New Data 63" mask="0x80000000"/>
+        </register>
+        <register name="RXF0C" offset="0x1A0" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 0 Configuration">
+          <bitfield name="F0SA" caption="Rx FIFO 0 Start Address" mask="0xFFFC"/>
+          <bitfield name="F0S" caption="Rx FIFO 0 Size" mask="0x7F0000"/>
+          <bitfield name="F0WM" caption="Rx FIFO 0 Watermark" mask="0x7F000000"/>
+          <bitfield name="F0OM" caption="FIFO 0 Operation Mode" mask="0x80000000"/>
+        </register>
+        <register name="RXF0S" offset="0x1A4" rw="R" size="4" initval="0x00000000" caption="Rx FIFO 0 Status">
+          <bitfield name="F0FL" caption="Rx FIFO 0 Fill Level" mask="0x7F"/>
+          <bitfield name="F0GI" caption="Rx FIFO 0 Get Index" mask="0x3F00"/>
+          <bitfield name="F0PI" caption="Rx FIFO 0 Put Index" mask="0x3F0000"/>
+          <bitfield name="F0F" caption="Rx FIFO 0 Full" mask="0x1000000"/>
+          <bitfield name="RF0L" caption="Rx FIFO 0 Message Lost" mask="0x2000000"/>
+        </register>
+        <register name="RXF0A" offset="0x1A8" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 0 Acknowledge">
+          <bitfield name="F0AI" caption="Rx FIFO 0 Acknowledge Index" mask="0x3F"/>
+        </register>
+        <register name="RXBC" offset="0x1AC" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer Configuration">
+          <bitfield name="RBSA" caption="Rx Buffer Start Address" mask="0xFFFC"/>
+        </register>
+        <register name="RXF1C" offset="0x1B0" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 1 Configuration">
+          <bitfield name="F1SA" caption="Rx FIFO 1 Start Address" mask="0xFFFC"/>
+          <bitfield name="F1S" caption="Rx FIFO 1 Size" mask="0x7F0000"/>
+          <bitfield name="F1WM" caption="Rx FIFO 1 Watermark" mask="0x7F000000"/>
+          <bitfield name="F1OM" caption="FIFO 1 Operation Mode" mask="0x80000000"/>
+        </register>
+        <register name="RXF1S" offset="0x1B4" rw="R" size="4" initval="0x00000000" caption="Rx FIFO 1 Status">
+          <bitfield name="F1FL" caption="Rx FIFO 1 Fill Level" mask="0x7F"/>
+          <bitfield name="F1GI" caption="Rx FIFO 1 Get Index" mask="0x3F00"/>
+          <bitfield name="F1PI" caption="Rx FIFO 1 Put Index" mask="0x3F0000"/>
+          <bitfield name="F1F" caption="Rx FIFO 1 Full" mask="0x1000000"/>
+          <bitfield name="RF1L" caption="Rx FIFO 1 Message Lost" mask="0x2000000"/>
+          <bitfield name="DMS" caption="Debug Message Status" mask="0xC0000000" values="RXF1S__DMS"/>
+        </register>
+        <register name="RXF1A" offset="0x1B8" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 1 Acknowledge">
+          <bitfield name="F1AI" caption="Rx FIFO 1 Acknowledge Index" mask="0x3F"/>
+        </register>
+        <register name="RXESC" offset="0x1BC" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer / FIFO Element Size Configuration">
+          <bitfield name="F0DS" caption="Rx FIFO 0 Data Field Size" mask="0x7" values="RXESC__F0DS"/>
+          <bitfield name="F1DS" caption="Rx FIFO 1 Data Field Size" mask="0x70" values="RXESC__F1DS"/>
+          <bitfield name="RBDS" caption="Rx Buffer Data Field Size" mask="0x700" values="RXESC__RBDS"/>
+        </register>
+        <register name="TXBC" offset="0x1C0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Configuration">
+          <bitfield name="TBSA" caption="Tx Buffers Start Address" mask="0xFFFC"/>
+          <bitfield name="NDTB" caption="Number of Dedicated Transmit Buffers" mask="0x3F0000"/>
+          <bitfield name="TFQS" caption="Transmit FIFO/Queue Size" mask="0x3F000000"/>
+          <bitfield name="TFQM" caption="Tx FIFO/Queue Mode" mask="0x40000000"/>
+        </register>
+        <register name="TXFQS" offset="0x1C4" rw="R" size="4" initval="0x00000000" caption="Tx FIFO / Queue Status">
+          <bitfield name="TFFL" caption="Tx FIFO Free Level" mask="0x3F"/>
+          <bitfield name="TFGI" caption="Tx FIFO Get Index" mask="0x1F00"/>
+          <bitfield name="TFQPI" caption="Tx FIFO/Queue Put Index" mask="0x1F0000"/>
+          <bitfield name="TFQF" caption="Tx FIFO/Queue Full" mask="0x200000"/>
+        </register>
+        <register name="TXESC" offset="0x1C8" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Element Size Configuration">
+          <bitfield name="TBDS" caption="Tx Buffer Data Field Size" mask="0x7" values="TXESC__TBDS"/>
+        </register>
+        <register name="TXBRP" offset="0x1CC" rw="R" size="4" initval="0x00000000" caption="Tx Buffer Request Pending">
+          <bitfield name="TRP0" caption="Transmission Request Pending 0" mask="0x1"/>
+          <bitfield name="TRP1" caption="Transmission Request Pending 1" mask="0x2"/>
+          <bitfield name="TRP2" caption="Transmission Request Pending 2" mask="0x4"/>
+          <bitfield name="TRP3" caption="Transmission Request Pending 3" mask="0x8"/>
+          <bitfield name="TRP4" caption="Transmission Request Pending 4" mask="0x10"/>
+          <bitfield name="TRP5" caption="Transmission Request Pending 5" mask="0x20"/>
+          <bitfield name="TRP6" caption="Transmission Request Pending 6" mask="0x40"/>
+          <bitfield name="TRP7" caption="Transmission Request Pending 7" mask="0x80"/>
+          <bitfield name="TRP8" caption="Transmission Request Pending 8" mask="0x100"/>
+          <bitfield name="TRP9" caption="Transmission Request Pending 9" mask="0x200"/>
+          <bitfield name="TRP10" caption="Transmission Request Pending 10" mask="0x400"/>
+          <bitfield name="TRP11" caption="Transmission Request Pending 11" mask="0x800"/>
+          <bitfield name="TRP12" caption="Transmission Request Pending 12" mask="0x1000"/>
+          <bitfield name="TRP13" caption="Transmission Request Pending 13" mask="0x2000"/>
+          <bitfield name="TRP14" caption="Transmission Request Pending 14" mask="0x4000"/>
+          <bitfield name="TRP15" caption="Transmission Request Pending 15" mask="0x8000"/>
+          <bitfield name="TRP16" caption="Transmission Request Pending 16" mask="0x10000"/>
+          <bitfield name="TRP17" caption="Transmission Request Pending 17" mask="0x20000"/>
+          <bitfield name="TRP18" caption="Transmission Request Pending 18" mask="0x40000"/>
+          <bitfield name="TRP19" caption="Transmission Request Pending 19" mask="0x80000"/>
+          <bitfield name="TRP20" caption="Transmission Request Pending 20" mask="0x100000"/>
+          <bitfield name="TRP21" caption="Transmission Request Pending 21" mask="0x200000"/>
+          <bitfield name="TRP22" caption="Transmission Request Pending 22" mask="0x400000"/>
+          <bitfield name="TRP23" caption="Transmission Request Pending 23" mask="0x800000"/>
+          <bitfield name="TRP24" caption="Transmission Request Pending 24" mask="0x1000000"/>
+          <bitfield name="TRP25" caption="Transmission Request Pending 25" mask="0x2000000"/>
+          <bitfield name="TRP26" caption="Transmission Request Pending 26" mask="0x4000000"/>
+          <bitfield name="TRP27" caption="Transmission Request Pending 27" mask="0x8000000"/>
+          <bitfield name="TRP28" caption="Transmission Request Pending 28" mask="0x10000000"/>
+          <bitfield name="TRP29" caption="Transmission Request Pending 29" mask="0x20000000"/>
+          <bitfield name="TRP30" caption="Transmission Request Pending 30" mask="0x40000000"/>
+          <bitfield name="TRP31" caption="Transmission Request Pending 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBAR" offset="0x1D0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Add Request">
+          <bitfield name="AR0" caption="Add Request 0" mask="0x1"/>
+          <bitfield name="AR1" caption="Add Request 1" mask="0x2"/>
+          <bitfield name="AR2" caption="Add Request 2" mask="0x4"/>
+          <bitfield name="AR3" caption="Add Request 3" mask="0x8"/>
+          <bitfield name="AR4" caption="Add Request 4" mask="0x10"/>
+          <bitfield name="AR5" caption="Add Request 5" mask="0x20"/>
+          <bitfield name="AR6" caption="Add Request 6" mask="0x40"/>
+          <bitfield name="AR7" caption="Add Request 7" mask="0x80"/>
+          <bitfield name="AR8" caption="Add Request 8" mask="0x100"/>
+          <bitfield name="AR9" caption="Add Request 9" mask="0x200"/>
+          <bitfield name="AR10" caption="Add Request 10" mask="0x400"/>
+          <bitfield name="AR11" caption="Add Request 11" mask="0x800"/>
+          <bitfield name="AR12" caption="Add Request 12" mask="0x1000"/>
+          <bitfield name="AR13" caption="Add Request 13" mask="0x2000"/>
+          <bitfield name="AR14" caption="Add Request 14" mask="0x4000"/>
+          <bitfield name="AR15" caption="Add Request 15" mask="0x8000"/>
+          <bitfield name="AR16" caption="Add Request 16" mask="0x10000"/>
+          <bitfield name="AR17" caption="Add Request 17" mask="0x20000"/>
+          <bitfield name="AR18" caption="Add Request 18" mask="0x40000"/>
+          <bitfield name="AR19" caption="Add Request 19" mask="0x80000"/>
+          <bitfield name="AR20" caption="Add Request 20" mask="0x100000"/>
+          <bitfield name="AR21" caption="Add Request 21" mask="0x200000"/>
+          <bitfield name="AR22" caption="Add Request 22" mask="0x400000"/>
+          <bitfield name="AR23" caption="Add Request 23" mask="0x800000"/>
+          <bitfield name="AR24" caption="Add Request 24" mask="0x1000000"/>
+          <bitfield name="AR25" caption="Add Request 25" mask="0x2000000"/>
+          <bitfield name="AR26" caption="Add Request 26" mask="0x4000000"/>
+          <bitfield name="AR27" caption="Add Request 27" mask="0x8000000"/>
+          <bitfield name="AR28" caption="Add Request 28" mask="0x10000000"/>
+          <bitfield name="AR29" caption="Add Request 29" mask="0x20000000"/>
+          <bitfield name="AR30" caption="Add Request 30" mask="0x40000000"/>
+          <bitfield name="AR31" caption="Add Request 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBCR" offset="0x1D4" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Cancellation Request">
+          <bitfield name="CR0" caption="Cancellation Request 0" mask="0x1"/>
+          <bitfield name="CR1" caption="Cancellation Request 1" mask="0x2"/>
+          <bitfield name="CR2" caption="Cancellation Request 2" mask="0x4"/>
+          <bitfield name="CR3" caption="Cancellation Request 3" mask="0x8"/>
+          <bitfield name="CR4" caption="Cancellation Request 4" mask="0x10"/>
+          <bitfield name="CR5" caption="Cancellation Request 5" mask="0x20"/>
+          <bitfield name="CR6" caption="Cancellation Request 6" mask="0x40"/>
+          <bitfield name="CR7" caption="Cancellation Request 7" mask="0x80"/>
+          <bitfield name="CR8" caption="Cancellation Request 8" mask="0x100"/>
+          <bitfield name="CR9" caption="Cancellation Request 9" mask="0x200"/>
+          <bitfield name="CR10" caption="Cancellation Request 10" mask="0x400"/>
+          <bitfield name="CR11" caption="Cancellation Request 11" mask="0x800"/>
+          <bitfield name="CR12" caption="Cancellation Request 12" mask="0x1000"/>
+          <bitfield name="CR13" caption="Cancellation Request 13" mask="0x2000"/>
+          <bitfield name="CR14" caption="Cancellation Request 14" mask="0x4000"/>
+          <bitfield name="CR15" caption="Cancellation Request 15" mask="0x8000"/>
+          <bitfield name="CR16" caption="Cancellation Request 16" mask="0x10000"/>
+          <bitfield name="CR17" caption="Cancellation Request 17" mask="0x20000"/>
+          <bitfield name="CR18" caption="Cancellation Request 18" mask="0x40000"/>
+          <bitfield name="CR19" caption="Cancellation Request 19" mask="0x80000"/>
+          <bitfield name="CR20" caption="Cancellation Request 20" mask="0x100000"/>
+          <bitfield name="CR21" caption="Cancellation Request 21" mask="0x200000"/>
+          <bitfield name="CR22" caption="Cancellation Request 22" mask="0x400000"/>
+          <bitfield name="CR23" caption="Cancellation Request 23" mask="0x800000"/>
+          <bitfield name="CR24" caption="Cancellation Request 24" mask="0x1000000"/>
+          <bitfield name="CR25" caption="Cancellation Request 25" mask="0x2000000"/>
+          <bitfield name="CR26" caption="Cancellation Request 26" mask="0x4000000"/>
+          <bitfield name="CR27" caption="Cancellation Request 27" mask="0x8000000"/>
+          <bitfield name="CR28" caption="Cancellation Request 28" mask="0x10000000"/>
+          <bitfield name="CR29" caption="Cancellation Request 29" mask="0x20000000"/>
+          <bitfield name="CR30" caption="Cancellation Request 30" mask="0x40000000"/>
+          <bitfield name="CR31" caption="Cancellation Request 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBTO" offset="0x1D8" rw="R" size="4" initval="0x00000000" caption="Tx Buffer Transmission Occurred">
+          <bitfield name="TO0" caption="Transmission Occurred 0" mask="0x1"/>
+          <bitfield name="TO1" caption="Transmission Occurred 1" mask="0x2"/>
+          <bitfield name="TO2" caption="Transmission Occurred 2" mask="0x4"/>
+          <bitfield name="TO3" caption="Transmission Occurred 3" mask="0x8"/>
+          <bitfield name="TO4" caption="Transmission Occurred 4" mask="0x10"/>
+          <bitfield name="TO5" caption="Transmission Occurred 5" mask="0x20"/>
+          <bitfield name="TO6" caption="Transmission Occurred 6" mask="0x40"/>
+          <bitfield name="TO7" caption="Transmission Occurred 7" mask="0x80"/>
+          <bitfield name="TO8" caption="Transmission Occurred 8" mask="0x100"/>
+          <bitfield name="TO9" caption="Transmission Occurred 9" mask="0x200"/>
+          <bitfield name="TO10" caption="Transmission Occurred 10" mask="0x400"/>
+          <bitfield name="TO11" caption="Transmission Occurred 11" mask="0x800"/>
+          <bitfield name="TO12" caption="Transmission Occurred 12" mask="0x1000"/>
+          <bitfield name="TO13" caption="Transmission Occurred 13" mask="0x2000"/>
+          <bitfield name="TO14" caption="Transmission Occurred 14" mask="0x4000"/>
+          <bitfield name="TO15" caption="Transmission Occurred 15" mask="0x8000"/>
+          <bitfield name="TO16" caption="Transmission Occurred 16" mask="0x10000"/>
+          <bitfield name="TO17" caption="Transmission Occurred 17" mask="0x20000"/>
+          <bitfield name="TO18" caption="Transmission Occurred 18" mask="0x40000"/>
+          <bitfield name="TO19" caption="Transmission Occurred 19" mask="0x80000"/>
+          <bitfield name="TO20" caption="Transmission Occurred 20" mask="0x100000"/>
+          <bitfield name="TO21" caption="Transmission Occurred 21" mask="0x200000"/>
+          <bitfield name="TO22" caption="Transmission Occurred 22" mask="0x400000"/>
+          <bitfield name="TO23" caption="Transmission Occurred 23" mask="0x800000"/>
+          <bitfield name="TO24" caption="Transmission Occurred 24" mask="0x1000000"/>
+          <bitfield name="TO25" caption="Transmission Occurred 25" mask="0x2000000"/>
+          <bitfield name="TO26" caption="Transmission Occurred 26" mask="0x4000000"/>
+          <bitfield name="TO27" caption="Transmission Occurred 27" mask="0x8000000"/>
+          <bitfield name="TO28" caption="Transmission Occurred 28" mask="0x10000000"/>
+          <bitfield name="TO29" caption="Transmission Occurred 29" mask="0x20000000"/>
+          <bitfield name="TO30" caption="Transmission Occurred 30" mask="0x40000000"/>
+          <bitfield name="TO31" caption="Transmission Occurred 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBCF" offset="0x1DC" rw="R" size="4" initval="0x00000000" caption="Tx Buffer Cancellation Finished">
+          <bitfield name="CF0" caption="Tx Buffer Cancellation Finished 0" mask="0x1"/>
+          <bitfield name="CF1" caption="Tx Buffer Cancellation Finished 1" mask="0x2"/>
+          <bitfield name="CF2" caption="Tx Buffer Cancellation Finished 2" mask="0x4"/>
+          <bitfield name="CF3" caption="Tx Buffer Cancellation Finished 3" mask="0x8"/>
+          <bitfield name="CF4" caption="Tx Buffer Cancellation Finished 4" mask="0x10"/>
+          <bitfield name="CF5" caption="Tx Buffer Cancellation Finished 5" mask="0x20"/>
+          <bitfield name="CF6" caption="Tx Buffer Cancellation Finished 6" mask="0x40"/>
+          <bitfield name="CF7" caption="Tx Buffer Cancellation Finished 7" mask="0x80"/>
+          <bitfield name="CF8" caption="Tx Buffer Cancellation Finished 8" mask="0x100"/>
+          <bitfield name="CF9" caption="Tx Buffer Cancellation Finished 9" mask="0x200"/>
+          <bitfield name="CF10" caption="Tx Buffer Cancellation Finished 10" mask="0x400"/>
+          <bitfield name="CF11" caption="Tx Buffer Cancellation Finished 11" mask="0x800"/>
+          <bitfield name="CF12" caption="Tx Buffer Cancellation Finished 12" mask="0x1000"/>
+          <bitfield name="CF13" caption="Tx Buffer Cancellation Finished 13" mask="0x2000"/>
+          <bitfield name="CF14" caption="Tx Buffer Cancellation Finished 14" mask="0x4000"/>
+          <bitfield name="CF15" caption="Tx Buffer Cancellation Finished 15" mask="0x8000"/>
+          <bitfield name="CF16" caption="Tx Buffer Cancellation Finished 16" mask="0x10000"/>
+          <bitfield name="CF17" caption="Tx Buffer Cancellation Finished 17" mask="0x20000"/>
+          <bitfield name="CF18" caption="Tx Buffer Cancellation Finished 18" mask="0x40000"/>
+          <bitfield name="CF19" caption="Tx Buffer Cancellation Finished 19" mask="0x80000"/>
+          <bitfield name="CF20" caption="Tx Buffer Cancellation Finished 20" mask="0x100000"/>
+          <bitfield name="CF21" caption="Tx Buffer Cancellation Finished 21" mask="0x200000"/>
+          <bitfield name="CF22" caption="Tx Buffer Cancellation Finished 22" mask="0x400000"/>
+          <bitfield name="CF23" caption="Tx Buffer Cancellation Finished 23" mask="0x800000"/>
+          <bitfield name="CF24" caption="Tx Buffer Cancellation Finished 24" mask="0x1000000"/>
+          <bitfield name="CF25" caption="Tx Buffer Cancellation Finished 25" mask="0x2000000"/>
+          <bitfield name="CF26" caption="Tx Buffer Cancellation Finished 26" mask="0x4000000"/>
+          <bitfield name="CF27" caption="Tx Buffer Cancellation Finished 27" mask="0x8000000"/>
+          <bitfield name="CF28" caption="Tx Buffer Cancellation Finished 28" mask="0x10000000"/>
+          <bitfield name="CF29" caption="Tx Buffer Cancellation Finished 29" mask="0x20000000"/>
+          <bitfield name="CF30" caption="Tx Buffer Cancellation Finished 30" mask="0x40000000"/>
+          <bitfield name="CF31" caption="Tx Buffer Cancellation Finished 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBTIE" offset="0x1E0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Transmission Interrupt Enable">
+          <bitfield name="TIE0" caption="Transmission Interrupt Enable 0" mask="0x1"/>
+          <bitfield name="TIE1" caption="Transmission Interrupt Enable 1" mask="0x2"/>
+          <bitfield name="TIE2" caption="Transmission Interrupt Enable 2" mask="0x4"/>
+          <bitfield name="TIE3" caption="Transmission Interrupt Enable 3" mask="0x8"/>
+          <bitfield name="TIE4" caption="Transmission Interrupt Enable 4" mask="0x10"/>
+          <bitfield name="TIE5" caption="Transmission Interrupt Enable 5" mask="0x20"/>
+          <bitfield name="TIE6" caption="Transmission Interrupt Enable 6" mask="0x40"/>
+          <bitfield name="TIE7" caption="Transmission Interrupt Enable 7" mask="0x80"/>
+          <bitfield name="TIE8" caption="Transmission Interrupt Enable 8" mask="0x100"/>
+          <bitfield name="TIE9" caption="Transmission Interrupt Enable 9" mask="0x200"/>
+          <bitfield name="TIE10" caption="Transmission Interrupt Enable 10" mask="0x400"/>
+          <bitfield name="TIE11" caption="Transmission Interrupt Enable 11" mask="0x800"/>
+          <bitfield name="TIE12" caption="Transmission Interrupt Enable 12" mask="0x1000"/>
+          <bitfield name="TIE13" caption="Transmission Interrupt Enable 13" mask="0x2000"/>
+          <bitfield name="TIE14" caption="Transmission Interrupt Enable 14" mask="0x4000"/>
+          <bitfield name="TIE15" caption="Transmission Interrupt Enable 15" mask="0x8000"/>
+          <bitfield name="TIE16" caption="Transmission Interrupt Enable 16" mask="0x10000"/>
+          <bitfield name="TIE17" caption="Transmission Interrupt Enable 17" mask="0x20000"/>
+          <bitfield name="TIE18" caption="Transmission Interrupt Enable 18" mask="0x40000"/>
+          <bitfield name="TIE19" caption="Transmission Interrupt Enable 19" mask="0x80000"/>
+          <bitfield name="TIE20" caption="Transmission Interrupt Enable 20" mask="0x100000"/>
+          <bitfield name="TIE21" caption="Transmission Interrupt Enable 21" mask="0x200000"/>
+          <bitfield name="TIE22" caption="Transmission Interrupt Enable 22" mask="0x400000"/>
+          <bitfield name="TIE23" caption="Transmission Interrupt Enable 23" mask="0x800000"/>
+          <bitfield name="TIE24" caption="Transmission Interrupt Enable 24" mask="0x1000000"/>
+          <bitfield name="TIE25" caption="Transmission Interrupt Enable 25" mask="0x2000000"/>
+          <bitfield name="TIE26" caption="Transmission Interrupt Enable 26" mask="0x4000000"/>
+          <bitfield name="TIE27" caption="Transmission Interrupt Enable 27" mask="0x8000000"/>
+          <bitfield name="TIE28" caption="Transmission Interrupt Enable 28" mask="0x10000000"/>
+          <bitfield name="TIE29" caption="Transmission Interrupt Enable 29" mask="0x20000000"/>
+          <bitfield name="TIE30" caption="Transmission Interrupt Enable 30" mask="0x40000000"/>
+          <bitfield name="TIE31" caption="Transmission Interrupt Enable 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBCIE" offset="0x1E4" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Cancellation Finished Interrupt Enable">
+          <bitfield name="CFIE0" caption="Cancellation Finished Interrupt Enable 0" mask="0x1"/>
+          <bitfield name="CFIE1" caption="Cancellation Finished Interrupt Enable 1" mask="0x2"/>
+          <bitfield name="CFIE2" caption="Cancellation Finished Interrupt Enable 2" mask="0x4"/>
+          <bitfield name="CFIE3" caption="Cancellation Finished Interrupt Enable 3" mask="0x8"/>
+          <bitfield name="CFIE4" caption="Cancellation Finished Interrupt Enable 4" mask="0x10"/>
+          <bitfield name="CFIE5" caption="Cancellation Finished Interrupt Enable 5" mask="0x20"/>
+          <bitfield name="CFIE6" caption="Cancellation Finished Interrupt Enable 6" mask="0x40"/>
+          <bitfield name="CFIE7" caption="Cancellation Finished Interrupt Enable 7" mask="0x80"/>
+          <bitfield name="CFIE8" caption="Cancellation Finished Interrupt Enable 8" mask="0x100"/>
+          <bitfield name="CFIE9" caption="Cancellation Finished Interrupt Enable 9" mask="0x200"/>
+          <bitfield name="CFIE10" caption="Cancellation Finished Interrupt Enable 10" mask="0x400"/>
+          <bitfield name="CFIE11" caption="Cancellation Finished Interrupt Enable 11" mask="0x800"/>
+          <bitfield name="CFIE12" caption="Cancellation Finished Interrupt Enable 12" mask="0x1000"/>
+          <bitfield name="CFIE13" caption="Cancellation Finished Interrupt Enable 13" mask="0x2000"/>
+          <bitfield name="CFIE14" caption="Cancellation Finished Interrupt Enable 14" mask="0x4000"/>
+          <bitfield name="CFIE15" caption="Cancellation Finished Interrupt Enable 15" mask="0x8000"/>
+          <bitfield name="CFIE16" caption="Cancellation Finished Interrupt Enable 16" mask="0x10000"/>
+          <bitfield name="CFIE17" caption="Cancellation Finished Interrupt Enable 17" mask="0x20000"/>
+          <bitfield name="CFIE18" caption="Cancellation Finished Interrupt Enable 18" mask="0x40000"/>
+          <bitfield name="CFIE19" caption="Cancellation Finished Interrupt Enable 19" mask="0x80000"/>
+          <bitfield name="CFIE20" caption="Cancellation Finished Interrupt Enable 20" mask="0x100000"/>
+          <bitfield name="CFIE21" caption="Cancellation Finished Interrupt Enable 21" mask="0x200000"/>
+          <bitfield name="CFIE22" caption="Cancellation Finished Interrupt Enable 22" mask="0x400000"/>
+          <bitfield name="CFIE23" caption="Cancellation Finished Interrupt Enable 23" mask="0x800000"/>
+          <bitfield name="CFIE24" caption="Cancellation Finished Interrupt Enable 24" mask="0x1000000"/>
+          <bitfield name="CFIE25" caption="Cancellation Finished Interrupt Enable 25" mask="0x2000000"/>
+          <bitfield name="CFIE26" caption="Cancellation Finished Interrupt Enable 26" mask="0x4000000"/>
+          <bitfield name="CFIE27" caption="Cancellation Finished Interrupt Enable 27" mask="0x8000000"/>
+          <bitfield name="CFIE28" caption="Cancellation Finished Interrupt Enable 28" mask="0x10000000"/>
+          <bitfield name="CFIE29" caption="Cancellation Finished Interrupt Enable 29" mask="0x20000000"/>
+          <bitfield name="CFIE30" caption="Cancellation Finished Interrupt Enable 30" mask="0x40000000"/>
+          <bitfield name="CFIE31" caption="Cancellation Finished Interrupt Enable 31" mask="0x80000000"/>
+        </register>
+        <register name="TXEFC" offset="0x1F0" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Configuration">
+          <bitfield name="EFSA" caption="Event FIFO Start Address" mask="0xFFFC"/>
+          <bitfield name="EFS" caption="Event FIFO Size" mask="0x3F0000"/>
+          <bitfield name="EFWM" caption="Event FIFO Watermark" mask="0x3F000000"/>
+        </register>
+        <register name="TXEFS" offset="0x1F4" rw="R" size="4" initval="0x00000000" caption="Tx Event FIFO Status">
+          <bitfield name="EFFL" caption="Event FIFO Fill Level" mask="0x3F"/>
+          <bitfield name="EFGI" caption="Event FIFO Get Index" mask="0x1F00"/>
+          <bitfield name="EFPI" caption="Event FIFO Put Index" mask="0x1F0000"/>
+          <bitfield name="EFF" caption="Event FIFO Full" mask="0x1000000"/>
+          <bitfield name="TEFL" caption="Tx Event FIFO Element Lost" mask="0x2000000"/>
+        </register>
+        <register name="TXEFA" offset="0x1F8" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Acknowledge">
+          <bitfield name="EFAI" caption="Event FIFO Acknowledge Index" mask="0x1F"/>
+        </register>
+        <register name="CREL_TSU" offset="0x260" rw="R" size="4" initval="0x10000000" caption="TSU CREL">
+          <bitfield name="DAY" caption="Timestamp Day" mask="0xFF"/>
+          <bitfield name="MON" caption="Timestamp Month" mask="0xFF00"/>
+          <bitfield name="YEAR" caption="Timestamp Year" mask="0xF0000"/>
+          <bitfield name="SUBSTEP" caption="Sub-step of Core Release" mask="0xF00000"/>
+          <bitfield name="STEP" caption="Step of Core Release" mask="0xF000000"/>
+          <bitfield name="REL" caption="Core Release" mask="0xF0000000"/>
+        </register>
+        <register name="TSCFG" offset="0x264" rw="RW" size="4" initval="0x00000000" caption="Timestamp Configuration">
+          <bitfield name="TSUE" caption="Timestamp Unit Enable" mask="0x1"/>
+          <bitfield name="TBCS" caption="Timebase Counter Select" mask="0x2"/>
+          <bitfield name="SCP" caption="Select Capturing Position" mask="0x4"/>
+          <bitfield name="TBPRE" caption="Time Base Prescaler" mask="0xFF00"/>
+        </register>
+        <register name="TSS1" offset="0x268" rw="R" size="4" initval="0x00000000" caption="Timestamp Status 1">
+          <bitfield name="TSL" caption="Timestamp Lost" mask="0xFFFF"/>
+          <bitfield name="TSN" caption="Timestamp New" mask="0xFFFF0000"/>
+        </register>
+        <register name="TSS2" offset="0x26C" rw="R" size="4" initval="0x0000A000" caption="Timestamp Status 2">
+          <bitfield name="TSP" caption="Timestamp Pointer" mask="0xF"/>
+          <bitfield name="NTSG" caption="Number of Timestamps Generic" mask="0x3000"/>
+          <bitfield name="ITBG" caption="Internal Timebase and SOF select Generic" mask="0xC000"/>
+        </register>
+        <register name="TS0" offset="0x270" rw="R" size="4" initval="0x00000000" caption="Timestamp 0">
+          <bitfield name="TS" caption="Timestamp Word TS0" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS1" offset="0x274" rw="R" size="4" initval="0x00000000" caption="Timestamp 1">
+          <bitfield name="TS" caption="Timestamp Word TS1" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS2" offset="0x278" rw="R" size="4" initval="0x00000000" caption="Timestamp 2">
+          <bitfield name="TS" caption="Timestamp Word TS2" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS3" offset="0x27C" rw="R" size="4" initval="0x00000000" caption="Timestamp 3">
+          <bitfield name="TS" caption="Timestamp Word TS0" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS4" offset="0x280" rw="R" size="4" initval="0x00000000" caption="Timestamp 4">
+          <bitfield name="TS" caption="Timestamp Word TS4" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS5" offset="0x284" rw="R" size="4" initval="0x00000000" caption="Timestamp 5">
+          <bitfield name="TS" caption="Timestamp Word TS5" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS6" offset="0x288" rw="R" size="4" initval="0x00000000" caption="Timestamp 6">
+          <bitfield name="TS" caption="Timestamp Word TS6" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS7" offset="0x28C" rw="R" size="4" initval="0x00000000" caption="Timestamp 7">
+          <bitfield name="TS" caption="Timestamp Word TS7" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS8" offset="0x290" rw="R" size="4" initval="0x00000000" caption="Timestamp 8">
+          <bitfield name="TS" caption="Timestamp Word TS8" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS9" offset="0x294" rw="R" size="4" initval="0x00000000" caption="Timestamp 9">
+          <bitfield name="TS" caption="Timestamp Word TS9" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS10" offset="0x298" rw="R" size="4" initval="0x00000000" caption="Timestamp 10">
+          <bitfield name="TS" caption="Timestamp Word TS10" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS11" offset="0x29C" rw="R" size="4" initval="0x00000000" caption="Timestamp 11">
+          <bitfield name="TS" caption="Timestamp Word TS11" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS12" offset="0x2A0" rw="R" size="4" initval="0x00000000" caption="Timestamp 12">
+          <bitfield name="TS" caption="Timestamp Word TS12" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS13" offset="0x2A4" rw="R" size="4" initval="0x00000000" caption="Timestamp 13">
+          <bitfield name="TS" caption="Timestamp Word TS13" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS14" offset="0x2A8" rw="R" size="4" initval="0x00000000" caption="Timestamp 14">
+          <bitfield name="TS" caption="Timestamp Word TS14" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS15" offset="0x2AC" rw="R" size="4" initval="0x00000000" caption="Timestamp 15">
+          <bitfield name="TS" caption="Timestamp Word TS15" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="ATB" offset="0x2B0" rw="RW" size="4" atomic-op="clear:ATB" initval="0x00000000" caption="Actual Timebase">
+          <bitfield name="TB" caption="Timebase for timestamp generation" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_RXBE" caption="Control Area Network" aligned="4">
+        <register name="R0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer and FIFO Element 0">
+          <bitfield name="ID" caption="Identifier" mask="0x1FFFFFFF"/>
+          <bitfield name="RTR" caption="Remote Transmission Request" mask="0x20000000"/>
+          <bitfield name="XTD" caption="Extended Identifier" mask="0x40000000"/>
+          <bitfield name="ESI" caption="Error State Indicator" mask="0x80000000"/>
+        </register>
+        <register name="R1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer and FIFO Element 1">
+          <bitfield name="RXTS" caption="Rx Timestamp" mask="0xFFFF"/>
+          <bitfield name="DLC" caption="Data Length Code" mask="0xF0000"/>
+          <bitfield name="BRS" caption="Bit Rate Search" mask="0x100000"/>
+          <bitfield name="FDF" caption="FD Format" mask="0x200000"/>
+          <bitfield name="FIDX" caption="Filter Index" mask="0x7F000000"/>
+          <bitfield name="ANMF" caption="Accepted Non-matching Frame" mask="0x80000000"/>
+        </register>
+        <register name="R2" offset="0x8" rw="RW" size="4" count="16" initval="0x00000000" caption="Rx Buffer and FIFO Element Data">
+          <bitfield name="DB0" caption="Data Byte 0" mask="0xFF"/>
+          <bitfield name="DB1" caption="Data Byte 1" mask="0xFF00"/>
+          <bitfield name="DB2" caption="Data Byte 2" mask="0xFF0000"/>
+          <bitfield name="DB3" caption="Data Byte 3" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_SIDFE" caption="Control Area Network" aligned="4">
+        <register name="S0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Standard Message ID Filter Element">
+          <bitfield name="SFID2" caption="Standard Filter ID 2" mask="0x7FF"/>
+          <bitfield name="SFID1" caption="Standard Filter ID 1" mask="0x7FF0000"/>
+          <bitfield name="SFEC" caption="Standard Filter Element Configuration" mask="0x38000000" values="S0__SFEC"/>
+          <bitfield name="SFT" caption="Standard Filter Type" mask="0xC0000000" values="S0__SFT"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_TXBE" caption="Control Area Network" aligned="4">
+        <register name="T0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Element 0">
+          <bitfield name="ID" caption="Identifier" mask="0x1FFFFFFF"/>
+          <bitfield name="RTR" caption="Remote Transmission Request" mask="0x20000000"/>
+          <bitfield name="XTD" caption="Extended Identifier" mask="0x40000000"/>
+          <bitfield name="ESI" caption="Error State Indicator" mask="0x80000000"/>
+        </register>
+        <register name="T1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Element 1">
+          <bitfield name="MMH" caption="Message Marker Higher Byte" mask="0xFF00"/>
+          <bitfield name="DLC" caption="Identifier" mask="0xF0000"/>
+          <bitfield name="BRS" caption="Bit Rate Search" mask="0x100000"/>
+          <bitfield name="FDF" caption="FD Format" mask="0x200000"/>
+          <bitfield name="TSCE" caption="Time Stamp Capture Enable for TSU" mask="0x400000"/>
+          <bitfield name="EFC" caption="Event FIFO Control" mask="0x800000"/>
+          <bitfield name="MML" caption="Message Marker Lower Byte" mask="0xFF000000"/>
+        </register>
+        <register name="T2" offset="0x8" rw="RW" size="4" count="16" initval="0x00000000" caption="Tx Buffer Element Data">
+          <bitfield name="DB0" caption="Data Byte 0" mask="0xFF"/>
+          <bitfield name="DB1" caption="Data Byte 1" mask="0xFF00"/>
+          <bitfield name="DB2" caption="Data Byte 2" mask="0xFF0000"/>
+          <bitfield name="DB3" caption="Data Byte 3" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_TXEFE" caption="Control Area Network" aligned="4">
+        <register name="E0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Element 0">
+          <bitfield name="ID" caption="Identifier" mask="0x1FFFFFFF"/>
+          <bitfield name="RTR" caption="Remote Transmission Request" mask="0x20000000"/>
+          <bitfield name="XTD" caption="Extended Indentifier" mask="0x40000000"/>
+          <bitfield name="ESI" caption="Error State Indicator" mask="0x80000000"/>
+        </register>
+        <register name="E1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Element 1">
+          <bitfield name="TXTS" caption="Tx Timestamp" mask="0xFFFF"/>
+          <bitfield name="DLC" caption="Data Length Code" mask="0xF0000"/>
+          <bitfield name="BRS" caption="Bit Rate Search" mask="0x100000"/>
+          <bitfield name="FDF" caption="FD Format" mask="0x200000"/>
+          <bitfield name="ET" caption="Event Type" mask="0xC00000" values="E1__ET"/>
+          <bitfield name="MM" caption="Message Marker" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_XIDFE" caption="Control Area Network" aligned="4">
+        <register name="F0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Extended Message ID Filter Element 0">
+          <bitfield name="EFID1" caption="Extended Filter ID 1" mask="0x1FFFFFFF"/>
+          <bitfield name="EFEC" caption="Extended Filter Element Configuration" mask="0xE0000000" values="F0__EFEC"/>
+        </register>
+        <register name="F1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Extended Message ID Filter Element 1">
+          <bitfield name="EFID2" caption="Extended Filter ID 2" mask="0x1FFFFFFF"/>
+          <bitfield name="EFT" caption="Extended Filter Type" mask="0xC0000000" values="F1__EFT"/>
+        </register>
+      </register-group>
+      <value-group name="TEST__TX">
+        <value name="CORE" caption="TX controlled by CAN core" value="0"/>
+        <value name="SAMPLE" caption="TX monitoring sample point" value="1"/>
+        <value name="DOMINANT" caption="Dominant (0) level at pin CAN_TX" value="2"/>
+        <value name="RECESSIVE" caption="Recessive (1) level at pin CAN_TX" value="3"/>
+      </value-group>
+      <value-group name="TSCC__TSS">
+        <value name="ZERO" caption="Timestamp counter value always 0x0000" value="0"/>
+        <value name="INC" caption="Timestamp counter value incremented by TCP" value="1"/>
+        <value name="EXT" caption="External timestamp counter value used" value="2"/>
+      </value-group>
+      <value-group name="TOCC__TOS">
+        <value name="CONT" caption="Continuout operation" value="0"/>
+        <value name="TXEF" caption="Timeout controlled by TX Event FIFO" value="1"/>
+        <value name="RXF0" caption="Timeout controlled by Rx FIFO 0" value="2"/>
+        <value name="RXF1" caption="Timeout controlled by Rx FIFO 1" value="3"/>
+      </value-group>
+      <value-group name="PSR__LEC">
+        <value name="NONE" caption="No Error" value="0"/>
+        <value name="STUFF" caption="Stuff Error" value="1"/>
+        <value name="FORM" caption="Form Error" value="2"/>
+        <value name="ACK" caption="Ack Error" value="3"/>
+        <value name="BIT1" caption="Bit1 Error" value="4"/>
+        <value name="BIT0" caption="Bit0 Error" value="5"/>
+        <value name="CRC" caption="CRC Error" value="6"/>
+        <value name="NC" caption="No Change" value="7"/>
+      </value-group>
+      <value-group name="PSR__ACT">
+        <value name="SYNC" caption="Node is synchronizing on CAN communication" value="0"/>
+        <value name="IDLE" caption="Node is neither receiver nor transmitter" value="1"/>
+        <value name="RX" caption="Node is operating as receiver" value="2"/>
+        <value name="TX" caption="Node is operating as transmitter" value="3"/>
+      </value-group>
+      <value-group name="PSR__DLEC">
+        <value name="NONE" caption="No Error" value="0"/>
+        <value name="STUFF" caption="Stuff Error" value="1"/>
+        <value name="FORM" caption="Form Error" value="2"/>
+        <value name="ACK" caption="Ack Error" value="3"/>
+        <value name="BIT1" caption="Bit1 Error" value="4"/>
+        <value name="BIT0" caption="Bit0 Error" value="5"/>
+        <value name="CRC" caption="CRC Error" value="6"/>
+        <value name="NC" caption="No Change" value="7"/>
+      </value-group>
+      <value-group name="GFC__ANFE">
+        <value name="RXF0" caption="Accept in Rx FIFO 0" value="0"/>
+        <value name="RXF1" caption="Accept in Rx FIFO 1" value="1"/>
+        <value name="REJECT" caption="Reject" value="2"/>
+      </value-group>
+      <value-group name="GFC__ANFS">
+        <value name="RXF0" caption="Accept in Rx FIFO 0" value="0"/>
+        <value name="RXF1" caption="Accept in Rx FIFO 1" value="1"/>
+        <value name="REJECT" caption="Reject" value="2"/>
+      </value-group>
+      <value-group name="HPMS__MSI">
+        <value name="NONE" caption="No FIFO selected" value="0"/>
+        <value name="LOST" caption="FIFO message lost" value="1"/>
+        <value name="FIFO0" caption="Message stored in FIFO 0" value="2"/>
+        <value name="FIFO1" caption="Message stored in FIFO 1" value="3"/>
+      </value-group>
+      <value-group name="RXF1S__DMS">
+        <value name="IDLE" caption="Idle state" value="0"/>
+        <value name="DBGA" caption="Debug message A received" value="1"/>
+        <value name="DBGB" caption="Debug message A/B received" value="2"/>
+        <value name="DBGC" caption="Debug message A/B/C received, DMA request set" value="3"/>
+      </value-group>
+      <value-group name="RXESC__F0DS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="RXESC__F1DS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="RXESC__RBDS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="TXESC__TBDS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="S0__SFEC">
+        <value name="DISABLE" caption="Disable filter element" value="0"/>
+        <value name="STF0M" caption="Store in Rx FIFO 0 if filter match" value="1"/>
+        <value name="STF1M" caption="Store in Rx FIFO 1 if filter match" value="2"/>
+        <value name="REJECT" caption="Reject ID if filter match" value="3"/>
+        <value name="PRIORITY" caption="Set priority if filter match" value="4"/>
+        <value name="PRIF0M" caption="Set priority and store in FIFO 0 if filter match" value="5"/>
+        <value name="PRIF1M" caption="Set priority and store in FIFO 1 if filter match" value="6"/>
+        <value name="STRXBUF" caption="Store into Rx Buffer" value="7"/>
+      </value-group>
+      <value-group name="S0__SFT">
+        <value name="RANGE" caption="Range filter from SFID1 to SFID2" value="0"/>
+        <value name="DUAL" caption="Dual ID filter for SFID1 or SFID2" value="1"/>
+        <value name="CLASSIC" caption="Classic filter" value="2"/>
+      </value-group>
+      <value-group name="E1__ET">
+        <value name="TXE" caption="Tx event" value="1"/>
+        <value name="TXC" caption="Transmission in spite of cancellation" value="2"/>
+      </value-group>
+      <value-group name="F0__EFEC">
+        <value name="DISABLE" caption="Disable filter element" value="0"/>
+        <value name="STF0M" caption="Store in Rx FIFO 0 if filter match" value="1"/>
+        <value name="STF1M" caption="Store in Rx FIFO 1 if filter match" value="2"/>
+        <value name="REJECT" caption="Reject ID if filter match" value="3"/>
+        <value name="PRIORITY" caption="Set priority if filter match" value="4"/>
+        <value name="PRIF0M" caption="Set priority and store in FIFO 0 if filter match" value="5"/>
+        <value name="PRIF1M" caption="Set priority and store in FIFO 1 if filter match" value="6"/>
+        <value name="STRXBUF" caption="Store into Rx Buffer" value="7"/>
+      </value-group>
+      <value-group name="F1__EFT">
+        <value name="RANGEM" caption="Range filter from EFID1 to EFID2" value="0"/>
+        <value name="DUAL" caption="Dual ID filter for EFID1 or EFID2" value="1"/>
+        <value name="CLASSIC" caption="Classic filter" value="2"/>
+        <value name="RANGE" caption="Range filter from EFID1 to EFID2 with no XIDAM mask" value="3"/>
+      </value-group>
+    </module>
+    <module name="CCL" id="03628" name2="cla_ccl_u2225_v2" version="2b0" caption="Configurable Custom Logic">
+      <register-group name="CCL" caption="Configurable Custom Logic">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1" values="CTRL__SWRST"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2" values="CTRL__ENABLE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40" values="CTRL__RUNSTDBY"/>
+        </register>
+        <register name="SEQCTRL" offset="0x4" rw="RW" size="1" count="2" initval="0x00" caption="SEQ Control x">
+          <bitfield name="SEQSEL" caption="Sequential Selection" mask="0xF" values="SEQCTRL__SEQSEL"/>
+        </register>
+        <register name="LUTCTRL" offset="0x8" rw="RW" size="4" count="4" initval="0x00000000" caption="LUT Control x">
+          <bitfield name="ENABLE" caption="LUT Enable" mask="0x2" values="LUTCTRL__ENABLE"/>
+          <bitfield name="FILTSEL" caption="Filter Selection" mask="0x30" values="LUTCTRL__FILTSEL"/>
+          <bitfield name="EDGESEL" caption="Edge Selection" mask="0x80" values="LUTCTRL__EDGESEL"/>
+          <bitfield name="INSEL0" caption="Input Selection 0" mask="0xF00" values="LUTCTRL__INSEL0"/>
+          <bitfield name="INSEL1" caption="Input Selection 1" mask="0xF000" values="LUTCTRL__INSEL1"/>
+          <bitfield name="INSEL2" caption="Input Selection 2" mask="0xF0000" values="LUTCTRL__INSEL2"/>
+          <bitfield name="INVEI" caption="Inverted Event Input Enable" mask="0x100000" values="LUTCTRL__INVEI"/>
+          <bitfield name="LUTEI" caption="LUT Event Input Enable" mask="0x200000" values="LUTCTRL__LUTEI"/>
+          <bitfield name="LUTEO" caption="LUT Event Output Enable" mask="0x400000" values="LUTCTRL__LUTEO"/>
+          <bitfield name="TRUTH" caption="Truth Value" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <value-group name="CTRL__SWRST">
+        <value name="DISABLE" caption="The peripheral is not reset" value="0"/>
+        <value name="ENABLE" caption="The peripheral is reset" value="1"/>
+      </value-group>
+      <value-group name="CTRL__ENABLE">
+        <value name="DISABLE" caption="The peripheral is disabled" value="0"/>
+        <value name="ENABLE" caption="The peripheral is enabled" value="1"/>
+      </value-group>
+      <value-group name="CTRL__RUNSTDBY">
+        <value name="DISABLE" caption="Generic clock is not required in standby sleep mode" value="0"/>
+        <value name="ENABLE" caption="Generic clock is  required in standby sleep mode" value="1"/>
+      </value-group>
+      <value-group name="SEQCTRL__SEQSEL">
+        <value name="DISABLE" caption="Sequential logic is disabled" value="0"/>
+        <value name="DFF" caption="D flip flop" value="1"/>
+        <value name="JK" caption="JK flip flop" value="2"/>
+        <value name="LATCH" caption="D latch" value="3"/>
+        <value name="RS" caption="RS latch" value="4"/>
+      </value-group>
+      <value-group name="LUTCTRL__ENABLE">
+        <value name="DISABLE" caption="LUT block is disabled" value="0"/>
+        <value name="ENABLE" caption="LUT block is enabled" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__FILTSEL">
+        <value name="DISABLE" caption="Filter disabled" value="0"/>
+        <value name="SYNCH" caption="Synchronizer enabled" value="1"/>
+        <value name="FILTER" caption="Filter enabled" value="2"/>
+      </value-group>
+      <value-group name="LUTCTRL__EDGESEL">
+        <value name="DISABLE" caption="Edge detector is disabled" value="0"/>
+        <value name="ENABLE" caption="Edge detector is enabled" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__INSEL0">
+        <value name="MASK" caption="Masked input" value="0x0"/>
+        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
+        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
+        <value name="EVENT" caption="Event input source" value="0x3"/>
+        <value name="IO" caption="I/O pin input source" value="0x4"/>
+        <value name="PERSEL0" caption="Peripheral 0 input source" value="0x5"/>
+        <value name="PERSEL1" caption="Peripheral 1 input source" value="0x6"/>
+        <value name="PERSEL2" caption="Peripheral 2 input source" value="0x7"/>
+        <value name="PERSEL3" caption="Peripheral 3 input source" value="0x8"/>
+        <value name="PERSEL4" caption="Peripheral 4 input source" value="0x9"/>
+        <value name="PERSEL5" caption="Peripheral 5 input source" value="0xA"/>
+        <value name="ASYNCEVENT" caption="Asynchronous event input source. The EVENT input will bypass edge detection logic." value="0xB"/>
+      </value-group>
+      <value-group name="LUTCTRL__INSEL1">
+        <value name="MASK" caption="Masked input" value="0x0"/>
+        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
+        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
+        <value name="EVENT" caption="Event input source" value="0x3"/>
+        <value name="IO" caption="I/O pin input source" value="0x4"/>
+        <value name="PERSEL0" caption="Peripheral 0 input source" value="0x5"/>
+        <value name="PERSEL1" caption="Peripheral 1 input source" value="0x6"/>
+        <value name="PERSEL2" caption="Peripheral 2 input source" value="0x7"/>
+        <value name="PERSEL3" caption="Peripheral 3 input source" value="0x8"/>
+        <value name="PERSEL4" caption="Peripheral 4 input source" value="0x9"/>
+        <value name="PERSEL5" caption="Peripheral 5 input source" value="0xA"/>
+        <value name="ASYNCEVENT" caption="Asynchronous event input source. The EVENT input will bypass edge detection logic." value="0xB"/>
+      </value-group>
+      <value-group name="LUTCTRL__INSEL2">
+        <value name="MASK" caption="Masked input" value="0x0"/>
+        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
+        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
+        <value name="EVENT" caption="Event input source" value="0x3"/>
+        <value name="IO" caption="I/O pin input source" value="0x4"/>
+        <value name="PERSEL0" caption="Peripheral 0 input source" value="0x5"/>
+        <value name="PERSEL1" caption="Peripheral 1 input source" value="0x6"/>
+        <value name="PERSEL2" caption="Peripheral 2 input source" value="0x7"/>
+        <value name="PERSEL3" caption="Peripheral 3 input source" value="0x8"/>
+        <value name="PERSEL4" caption="Peripheral 4 input source" value="0x9"/>
+        <value name="PERSEL5" caption="Peripheral 5 input source" value="0xA"/>
+        <value name="ASYNCEVENT" caption="Asynchronous event input source. The EVENT input will bypass edge detection logic." value="0xB"/>
+      </value-group>
+      <value-group name="LUTCTRL__INVEI">
+        <value name="NORMAL" caption="Incoming event is not inverted" value="0"/>
+        <value name="INVERTED" caption="Incoming event is inverted" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__LUTEI">
+        <value name="DISABLE" caption="LUT incoming event is disabled" value="0"/>
+        <value name="ENABLE" caption="LUT incoming event is enabled" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__LUTEO">
+        <value name="DISABLE" caption="LUT event output is disabled" value="0"/>
+        <value name="ENABLE" caption="LUT event output is enabled" value="1"/>
+      </value-group>
+    </module>
+    <module name="CoreDebug" id="SYSTEM_IP" version="1.0.0" caption="Debug Control Block">
+      <register-group name="CoreDebug" caption="Debug Control Block">
+        <register name="DHCSR" offset="0x0" rw="RW" size="4" access-size="4" caption="Debug Halting Control and Status Register">
+          <bitfield name="C_DEBUGEN" caption="Enable Halting debug" mask="0x1"/>
+          <bitfield name="C_HALT" caption="Halt processor" mask="0x2"/>
+          <bitfield name="C_STEP" caption="Enable single step" mask="0x4"/>
+          <bitfield name="C_MASKINTS" caption="Mask PendSV, SysTick and external configurable interrupts" mask="0x8"/>
+          <bitfield name="S_SNAPSTALL" caption="Snap stall control" mask="0x20"/>
+          <bitfield name="S_REGRDY" caption="Register ready status" mask="0x10000"/>
+          <bitfield name="S_HALT" caption="Halted status" mask="0x20000"/>
+          <bitfield name="S_SLEEP" caption="Sleeping status" mask="0x40000"/>
+          <bitfield name="S_LOCKUP" caption="Lockup status" mask="0x80000"/>
+          <bitfield name="S_SDE" caption="Secure debug enabled" mask="0x100000"/>
+          <bitfield name="S_RETIRE_ST" caption="Retire sticky status" mask="0x1000000"/>
+          <bitfield name="S_RESET_ST" caption="Reset sticky status" mask="0x2000000"/>
+          <bitfield name="S_RESTART_ST" caption="Restart sticky status" mask="0x4000000"/>
+        </register>
+        <register name="DCRSR" offset="0x4" rw="W" size="4" access-size="4" caption="Debug Core Register Select Register">
+          <bitfield name="REGSEL" caption="Register selector" mask="0x7F"/>
+          <bitfield name="REGWnR" caption="Register write/not-read access" mask="0x10000"/>
+        </register>
+        <register name="DEMCR" offset="0xC" rw="RW" size="4" access-size="4" caption="Debug Exception and Monitor Control Register">
+          <bitfield name="VC_CORERESET" caption="Core reset Halting debug vector catch enable" mask="0x1"/>
+          <bitfield name="VC_MMERR" caption="MemManage exception Halting debug vector catch enable" mask="0x10"/>
+          <bitfield name="VC_NOCPERR" caption="UsageFault exception coprocessor access Halting debug vector catch enable" mask="0x20"/>
+          <bitfield name="VC_CHKERR" caption="UsageFault exception checking error Halting debug vector catch enable" mask="0x40"/>
+          <bitfield name="VC_STATERR" caption="UsageFault exception state information error Halting debug vector catch enable" mask="0x80"/>
+          <bitfield name="VC_BUSERR" caption="BusFault exception Halting debug vector catch enable" mask="0x100"/>
+          <bitfield name="VC_INTERR" caption="Excception entry and return faults Halting debug vector catch enable" mask="0x200"/>
+          <bitfield name="VC_HARDERR" caption="HardFault exception Halting debug vector catch enable" mask="0x400"/>
+          <bitfield name="VC_SFERR" caption="SecureFault exception Halting debug vector catch enable" mask="0x800"/>
+          <bitfield name="MON_EN" caption="DebugMonitor enable" mask="0x10000"/>
+          <bitfield name="MON_PEND" caption="DebugMonitor pending state" mask="0x20000"/>
+          <bitfield name="MON_STEP" caption="Enable DebugMonitor stepping" mask="0x40000"/>
+          <bitfield name="MON_REQ" caption="DebugMonitor semaphore bit" mask="0x80000"/>
+          <bitfield name="SDME" caption="Secure DebugMonitor enable" mask="0x100000"/>
+          <bitfield name="TRCENA" caption="Global DWT and ITM features enable" mask="0x1000000"/>
+        </register>
+        <register name="DSCSR" offset="0x18" rw="RW" size="4" access-size="4" caption="Debug Security Control and Status Register">
+          <bitfield name="SBRSELEN" caption="Secure Banked register select enable" mask="0x1"/>
+          <bitfield name="SBRSEL" caption="Secure Banked register select" mask="0x2"/>
+          <bitfield name="CDS" caption="Current domain Secure" mask="0x10000"/>
+          <bitfield name="CDSKEY" caption="CDS field write-enable key" mask="0x20000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="DIB" id="SYSTEM_IP" version="1.0.0" caption="Debug Identification Block">
+      <register-group name="DIB" caption="Debug Identification Block">
+        <register name="DLAR" offset="0x0" rw="W" size="4" access-size="4" caption="SCS Software Lock Access Register">
+          <bitfield name="KEY" caption="Lock access control" mask="0xFFFFFFFF" values="DLAR__KEY"/>
+        </register>
+        <register name="DLSR" offset="0x4" rw="R" size="4" access-size="4" caption="SCS Software Lock Status Register">
+          <bitfield name="SLI" caption="Software Lock implemented" mask="0x1"/>
+          <bitfield name="SLK" caption="Software Lock status" mask="0x2"/>
+          <bitfield name="nTT" caption="Not thirty-two bit" mask="0x4"/>
+        </register>
+        <register name="DAUTHSTATUS" offset="0x8" rw="R" size="4" access-size="4" caption="Debug Authentication Status Register">
+          <bitfield name="NSID" caption="" mask="0x3" values="DAUTHSTATUS__NSID"/>
+          <bitfield name="NSNID" caption="" mask="0xC" values="DAUTHSTATUS__NSNID"/>
+          <bitfield name="SID" caption="" mask="0x30" values="DAUTHSTATUS__SID"/>
+          <bitfield name="SNID" caption="" mask="0xC0" values="DAUTHSTATUS__SNID"/>
+        </register>
+        <register name="DDEVARCH" offset="0xC" rw="R" size="4" access-size="4" initval="0x47702A04" caption="SCS Device Architecture Register">
+          <bitfield name="ARCHPART" caption="Architecture Part" mask="0xFFF"/>
+          <bitfield name="ARCHVER" caption="Architecture Version" mask="0xF000"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF0000"/>
+          <bitfield name="PRESENT" caption="DEVARCH Present" mask="0x100000"/>
+          <bitfield name="ARCHITECT" caption="Architect" mask="0xFFE00000"/>
+        </register>
+        <register name="DDEVTYPE" offset="0x1C" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Device Type Register">
+          <bitfield name="MAJOR" caption="Major type" mask="0xF"/>
+          <bitfield name="SUB" caption="Sub-type" mask="0xF0"/>
+        </register>
+        <register name="DPIDR4" offset="0x20" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 4">
+          <bitfield name="DES_2" caption="JEP106 continuation code" mask="0xF"/>
+          <bitfield name="SIZE" caption="4KB count" mask="0xF0"/>
+        </register>
+        <register name="DPIDR5" offset="0x24" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Peripheral Identification Register 5"/>
+        <register name="DPIDR6" offset="0x28" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Peripheral Identification Register 6"/>
+        <register name="DPIDR7" offset="0x2C" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Peripheral Identification Register 7"/>
+        <register name="DPIDR0" offset="0x30" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 0">
+          <bitfield name="PART_0" caption="Part number bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="DPIDR1" offset="0x34" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 1">
+          <bitfield name="PART_1" caption="Part number bits[11:8]" mask="0xF"/>
+          <bitfield name="DES_0" caption="JEP106 identification code bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="DPIDR2" offset="0x38" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 2">
+          <bitfield name="DES_1" caption="JEP106 identification code bits[6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="JEDEC assignee value is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Component revision" mask="0xF0"/>
+        </register>
+        <register name="DPIDR3" offset="0x3C" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 3">
+          <bitfield name="CMOD" caption="Customer Modified" mask="0xF"/>
+          <bitfield name="REVAND" caption="RevAnd" mask="0xF0"/>
+        </register>
+        <register name="DCIDR0" offset="0x40" rw="R" size="4" access-size="4" initval="0x0000000D" caption="SCS Component Identification Register 0">
+          <bitfield name="PRMBL_0" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DCIDR1" offset="0x44" rw="R" size="4" access-size="4" initval="0x00000090" caption="SCS Component Identification Register 1">
+          <bitfield name="PRMBL_1" caption="CoreSight component identification preamble" mask="0xF"/>
+          <bitfield name="CLASS" caption="CoreSight component class" mask="0xF0"/>
+        </register>
+        <register name="DCIDR2" offset="0x48" rw="R" size="4" access-size="4" initval="0x00000005" caption="SCS Component Identification Register 2">
+          <bitfield name="PRMBL_2" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DCIDR3" offset="0x4C" rw="R" size="4" access-size="4" initval="0x000000B1" caption="SCS Component Identification Register 3">
+          <bitfield name="PRMBL_3" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="DLAR__KEY">
+        <value name="UNLOCK" caption="Unlock key value" value="0xC5ACCE55"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__NSID">
+        <value name="NO" caption="Non-secure invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Non-secure invasive debug allowed" value="3"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__NSNID">
+        <value name="NO" caption="Non-secure non-invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Non-secure non-invasive debug allowed" value="3"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__SID">
+        <value name="NOSEC" caption="Security Extension not implemented" value="0"/>
+        <value name="NO" caption="Secure invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Secure invasive debug allowed" value="3"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__SNID">
+        <value name="NOSEC" caption="Security Extension not implemented" value="0"/>
+        <value name="NO" caption="Secure non-invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Secure non-invasive debug allowed" value="3"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="dma_u2223_v2" name2="dma_u2223_v2" version="2i0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x2A" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0x7"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0x700"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0x70000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0x7000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0x7"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0x7"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Channel run in standby" mask="0x40"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+      <value-group name="CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (BEATSIZE+1) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (BEATSIZE+1) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (BEATSIZE+1) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (BEATSIZE+1) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (BEATSIZE+1) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (BEATSIZE+1) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (BEATSIZE+1) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (BEATSIZE+1) * 128" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="04465" name2="icd_dsu_v1" version="1a0" caption="Polaris Device Services Unit Macro DOS">
+      <register-group name="DSU" caption="Polaris Device Services Unit Macro DOS">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A REGISTER">
+          <bitfield name="PRIV" caption="Privileged Access Only for APB Interface" mask="0x4" values="CTRLA__PRIV"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B REGISTER">
+          <bitfield name="DCCDMALVL0" caption="DMA Trigger n Level" mask="0x1" values="CTRLB__DCCDMALVL"/>
+          <bitfield name="DCCDMALVL1" caption="DMA Trigger n Level" mask="0x2" values="CTRLB__DCCDMALVL"/>
+          <bitfield name="MISC" caption="Device Specific Configuration Register" mask="0xFFFFFF00"/>
+        </register>
+        <register name="CTRLC" offset="0x100" rw="RW" size="4" initval="0x00000000" caption="Control C REGISTER">
+          <bitfield name="DBGRW0" caption="CPUn Debug R/W" mask="0x1" values="CTRLC__DBGRW"/>
+        </register>
+        <register name="STATUSA" offset="0x104" rw="RW" size="4" atomic-op="clear:STATUSA" initval="0x00000000" caption="Status A REGISTER">
+          <bitfield name="DONE" caption="Done Status" mask="0x1" values="STATUSA__DONE"/>
+          <bitfield name="BERR" caption="Bus Error Status" mask="0x4" values="STATUSA__BERR"/>
+          <bitfield name="PERR" caption="Protection Error Status" mask="0x8" values="STATUSA__PERR"/>
+          <bitfield name="ROMCRC" caption="Boot ROM CRC Self-Check Status" mask="0xC0" values="STATUSA__ROMCRC"/>
+          <bitfield name="CRSTEXT0" caption="CPUx Reset Extension Status" mask="0x100" values="STATUSA__CRSTEXT"/>
+          <bitfield name="BREXT0" caption="BootRom 0 Phase Extension Status" mask="0x10000" values="STATUSA__BREXT"/>
+        </register>
+        <register name="STATUSB" offset="0x108" rw="R" size="4" initval="0x00000000" caption="Status B REGISTER">
+          <bitfield name="BCCD0" caption="Boot ROM Communication Channel 0 Dirty" mask="0x1" values="STATUSB__BCCD"/>
+          <bitfield name="BCCD1" caption="Boot ROM Communication Channel 1 Dirty" mask="0x2" values="STATUSB__BCCD"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4" values="STATUSB__DCCD"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8" values="STATUSB__DCCD"/>
+          <bitfield name="DBGPRES" caption="Debugger Present Status" mask="0x100" values="STATUSB__DBGPRES"/>
+          <bitfield name="HPS" caption="Hot-Plugging Status" mask="0x400" values="STATUSB__HPS"/>
+        </register>
+        <register name="BCC" offset="0x110" rw="RW" size="4" count="2" initval="0x00000000" caption="Boot ROM Channel n REGISTER">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x118" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n REGISTER">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x120" rw="RW" size="4" initval="0x00000053" caption="Device Identification Register">
+          <bitfield name="FV" caption="Fixed Value of 1" mask="0x1"/>
+          <bitfield name="MANID" caption="JEDEC Manufacture ID" mask="0xFFE"/>
+          <bitfield name="PNDID" caption="Part Number Device ID" mask="0xFF000"/>
+          <bitfield name="PNMID" caption="Part Number Mask ID" mask="0xFF00000"/>
+          <bitfield name="VER" caption="Version Code" mask="0xF0000000"/>
+        </register>
+        <register name="DAL" offset="0x124" rw="R" size="4" initval="0x00000000" caption="Debugger Access Level REGISTER">
+          <bitfield name="CPU0" caption="CPU 0 Debugger Access Level" mask="0x3" values="DAL__CPU0"/>
+          <bitfield name="CPU1" caption="CPU n Debugger Access Level" mask="0xC" values="DAL__CPU"/>
+          <bitfield name="CPU2" caption="CPU n Debugger Access Level" mask="0x30" values="DAL__CPU"/>
+          <bitfield name="CPU3" caption="CPU n Debugger Access Level" mask="0xC0" values="DAL__CPU"/>
+        </register>
+        <register name="ENTRY0" offset="0x1000" rw="R" size="4" initval="0x9C0FE002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY0__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY0__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY1" offset="0x1004" rw="R" size="4" initval="0xBBFFF002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY1__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY1__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY2" offset="0x1008" rw="R" size="4" initval="0xBBFFF002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY2__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY2__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY3" offset="0x100C" rw="R" size="4" initval="0xBBFFF002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY3__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY3__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY4" offset="0x1010" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 4 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY4__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY4__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY5" offset="0x1014" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 5 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY5__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY5__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY6" offset="0x1018" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 6 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY6__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY6__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY7" offset="0x101C" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 7 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY7__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY7__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Memory Type Register">
+          <bitfield name="SYSMEM" caption="CoreSight System Memory Present" mask="0x1" values="MEMTYPE__SYSMEM"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 4 Register">
+          <bitfield name="DES2" caption="CoreSight JEP106 Continuation Code" mask="0xF"/>
+          <bitfield name="SIZE" caption="CoreSight Size" mask="0xF0"/>
+        </register>
+        <register name="PID5" offset="0x1FD4" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 5 Register">
+          <bitfield name="RES0" caption="CoreSight Reserved Field" mask="0xFF"/>
+        </register>
+        <register name="PID6" offset="0x1FD8" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 6 Register">
+          <bitfield name="RES0" caption="CoreSight Reserved Field" mask="0xFF"/>
+        </register>
+        <register name="PID7" offset="0x1FDC" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 7 Register">
+          <bitfield name="RES0" caption="CoreSight Reserved Field" mask="0xFF"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="CoreSight Peripheral Identification 0 Register">
+          <bitfield name="PART0" caption="CoreSight Part Number Bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x0000009C" caption="CoreSight Peripheral Identification 1 Register">
+          <bitfield name="PART1" caption="CoreSight Part Number Bits[11:8]" mask="0xF"/>
+          <bitfield name="DES0" caption="CoreSight JEP106 Identification Code Bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x0000000A" caption="CoreSight Peripheral Identification 2 Register">
+          <bitfield name="DES1" caption="CoreSight JEP106 Identification Code Bits [6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="CoreSight JEDEC Assignment" mask="0x8"/>
+          <bitfield name="REVISION" caption="CoreSight Revision" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 3 Register">
+          <bitfield name="CMOD" caption="CoreSight Custom Modifier 0" mask="0xF"/>
+          <bitfield name="REVAND" caption="CoreSight REVAND" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="CoreSight Component Identification 0 Register">
+          <bitfield name="PRMBL0" caption="CoreSight Preamble 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="CoreSight Component Identification 1 Register">
+          <bitfield name="PRMBL1" caption="CoreSight Preamble 1" mask="0xF"/>
+          <bitfield name="CCLASS" caption="CoreSight Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="CoreSight Component Identification 2 Register">
+          <bitfield name="PRMBL2" caption="CoreSight Preamble 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="CoreSight Component Identification 3 Register">
+          <bitfield name="PRMBL3" caption="CoreSight Preamble 3" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="0" caption="Internal Address Space registers accessible in privileged and unprivileged modes. Test functions generate unprivileged requests." value="0"/>
+        <value name="1" caption="Internal Address Space registers only accessible in privileged mode. Test functions generate privileged requests." value="1"/>
+      </value-group>
+      <value-group name="CTRLB__DCCDMALVL">
+        <value name="EMPTY" caption="Trigger n rises when DCCn is read and falls when it is written" value="0"/>
+        <value name="FULL" caption="Trigger n rises when DCCn is written and falls when it is read" value="1"/>
+      </value-group>
+      <value-group name="CTRLC__DBGRW">
+        <value name="0" caption="Allow debugger accesses through CPUn to carry the debug attribute (i.e debugger reads are non-destructive)." value="0"/>
+        <value name="1" caption="Debugger accesses through CPUn do not carry the debug attribute (i.e debugger reads are destructive)." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__DONE">
+        <value name="0" caption="DSU is executing a command or idle." value="0"/>
+        <value name="1" caption="TCTRL.CMD command completed" value="1"/>
+      </value-group>
+      <value-group name="STATUSA__BERR">
+        <value name="0" caption="No bus error detected" value="0"/>
+        <value name="1" caption="Bus error incurred while performing the DSU command." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__PERR">
+        <value name="0" caption="No protection error detected" value="0"/>
+        <value name="1" caption="Invalid command written to TCTRL.CMD, partial write to the upper or lower bytes of TCTRL.CMD, or invalid key written to SAFEDOOR." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__ROMCRC">
+        <value name="0" caption="CRC is in progress" value="0"/>
+        <value name="1" caption="CRC completed but failed indicating possible issue with the ROM content. System held in lockup state." value="1"/>
+        <value name="2" caption="CRC completed and passed" value="2"/>
+        <value name="3" caption="CRC never executed because user disabled CRC check through fuse settings." value="3"/>
+      </value-group>
+      <value-group name="STATUSA__CRSTEXT">
+        <value name="0" caption="CPUx released from reset extension." value="0"/>
+        <value name="1" caption="CPUx held in reset extension. Set on Cold-Plugging detection." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__BREXT">
+        <value name="0" caption="Boot ROM Phase Extension released for CPUx." value="0"/>
+        <value name="1" caption="Boot ROM Phase Extension for CPUx. Set on Cold-Plugging detection." value="1"/>
+      </value-group>
+      <value-group name="STATUSB__BCCD">
+        <value name="0" caption="BCCDx.DATA register was read from." value="0"/>
+        <value name="1" caption="BCCDx.DATA register was written to." value="1"/>
+      </value-group>
+      <value-group name="STATUSB__DCCD">
+        <value name="0" caption="DCCDx.DATA register was read from." value="0"/>
+        <value name="1" caption="DCCDx.DATA register was written to." value="1"/>
+      </value-group>
+      <value-group name="STATUSB__DBGPRES">
+        <value name="0" caption="No debugger detected" value="0"/>
+        <value name="1" caption="Debugger probe detected" value="1"/>
+      </value-group>
+      <value-group name="STATUSB__HPS">
+        <value name="0" caption="Hot-Plugging inactive" value="0"/>
+        <value name="1" caption="Hot-Plugging active" value="1"/>
+      </value-group>
+      <value-group name="DAL__CPU0">
+        <value name="SECURED" caption="Debugger targeting CPU0 domain can only access the DSU external address space otherwise debugger access is disabled" value="0"/>
+        <value name="NS_DEBUG" caption="Debugger can access only non-secure regions" value="1"/>
+        <value name="FULL_DEBUG" caption="Debugger can access secure and non-secure regions" value="2"/>
+      </value-group>
+      <value-group name="DAL__CPU">
+        <value name="SECURED" caption="Debugger access is disabled" value="0"/>
+        <value name="NS_DEBUG" caption="Debugger can access only non-secure regions" value="1"/>
+        <value name="FULL_DEBUG" caption="Debugger has full access to debug CPUn" value="2"/>
+        <value name="UNIMPLEMENTED" caption="Unimplemented CPU" value="3"/>
+      </value-group>
+      <value-group name="ENTRY0__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY0__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY1__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY1__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY2__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY2__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY3__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY3__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY4__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY4__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY5__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY5__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY6__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY6__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY7__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY7__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="MEMTYPE__SYSMEM">
+        <value name="0" caption="System memory not present on bus. This is a dedicated debug bus." value="0"/>
+        <value name="1" caption="System memory is also present on this bus" value="1"/>
+      </value-group>
+    </module>
+    <module name="DWT" id="SYSTEM_IP" version="1.0.0" caption="Data Watchpoint and Trace">
+      <register-group name="COMPARATOR" size="0x10">
+        <register name="DWT_COMP" offset="0x0" rw="RW" size="4" access-size="4" caption="DWT Comparator Register n">
+          <bitfield name="VALUE" caption="Cycle/PC/data value or data address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DWT_FUNCTION" offset="0x8" rw="RW" size="4" access-size="4" caption="DWT Function Register x">
+          <bitfield name="MATCH" caption="Match type" mask="0xF"/>
+          <bitfield name="ACTION" caption="Action on match" mask="0x30"/>
+          <bitfield name="DATAVSIZE" caption="Data value size" mask="0xC00"/>
+          <bitfield name="MATCHED" caption="Comparator matched" mask="0x1000000"/>
+          <bitfield name="ID" caption="Identify capability" mask="0xF8000000"/>
+        </register>
+      </register-group>
+      <register-group name="DWT" caption="Data Watchpoint and Trace">
+        <register name="DWT_CTRL" offset="0x0" rw="RW" size="4" access-size="4" initval="0x0B000000" caption="DWT Control Register">
+          <bitfield name="CYCCNTENA" caption="CYCCNT enable" mask="0x1"/>
+          <bitfield name="POSTPRESET" caption="POSTCNT preset" mask="0x1E"/>
+          <bitfield name="POSTINIT" caption="POSTCNT initial" mask="0x1E0"/>
+          <bitfield name="CYCTAP" caption="Cycle count tap" mask="0x200"/>
+          <bitfield name="SYNCTAP" caption="Synchronization tap" mask="0xC00"/>
+          <bitfield name="PCSAMPLENA" caption="PC sample enable" mask="0x1000"/>
+          <bitfield name="EXCTRCENA" caption="Exception trace enable" mask="0x10000"/>
+          <bitfield name="CPIEVTENA" caption="CPI event enable" mask="0x20000"/>
+          <bitfield name="EXCEVTENA" caption="Exception event enable" mask="0x40000"/>
+          <bitfield name="SLEEPEVTENA" caption="Sleep event enable" mask="0x80000"/>
+          <bitfield name="LSUEVTENA" caption="LSU event enable" mask="0x100000"/>
+          <bitfield name="FOLDEVTENA" caption="Fold event enable" mask="0x200000"/>
+          <bitfield name="CYCEVTENA" caption="Cycle event enable" mask="0x400000"/>
+          <bitfield name="CYCDISS" caption="Cycle counter disabled secure" mask="0x800000"/>
+          <bitfield name="NOPRFCNT" caption="No profile counters" mask="0x1000000"/>
+          <bitfield name="NOCYCCNT" caption="No cycle count" mask="0x2000000"/>
+          <bitfield name="NOEXTTRIG" caption="No external triggers" mask="0x4000000"/>
+          <bitfield name="NOTRCPKT" caption="No trace packets" mask="0x8000000"/>
+          <bitfield name="NUMCOMP" caption="Number of comparators" mask="0xF0000000"/>
+        </register>
+        <register name="DWT_PCSR" offset="0x1C" rw="R" size="4" access-size="4" caption="DWT Program Counter Sample Register">
+          <bitfield name="EIASAMPLE" caption="Executed instruction address sample" mask="0xFFFFFFFF"/>
+        </register>
+        <register-group name="COMPARATOR" name-in-module="COMPARATOR" offset="0x020" size="0x10" count="2"/>
+        <register name="DWT_LAR" offset="0xFB0" rw="W" size="4" access-size="4" caption="DWT Software Lock Access Register">
+          <bitfield name="KEY" caption="Lock access control" mask="0xFFFFFFFF" values="DWT_LAR__KEY"/>
+        </register>
+        <register name="DWT_LSR" offset="0xFB4" rw="R" size="4" access-size="4" caption="DWT Software Lock Status Register">
+          <bitfield name="SLI" caption="Software Lock implemented" mask="0x1"/>
+          <bitfield name="SLK" caption="Software Lock status" mask="0x2"/>
+          <bitfield name="nTT" caption="Not thirty-two bit" mask="0x4"/>
+        </register>
+        <register name="DWT_DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" initval="0x47701A02" caption="DWT Device Architecture Register">
+          <bitfield name="ARCHPART" caption="Architecture Part" mask="0xFFF"/>
+          <bitfield name="ARCHVER" caption="Architecture Version" mask="0xF000"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF0000"/>
+          <bitfield name="PRESENT" caption="DEVARCH Present" mask="0x100000"/>
+          <bitfield name="ARCHITECT" caption="Architect" mask="0xFFE00000"/>
+        </register>
+        <register name="DWT_DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Device Type Register">
+          <bitfield name="MAJOR" caption="Major type" mask="0xF"/>
+          <bitfield name="SUB" caption="Sub-type" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR4" offset="0xFD0" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 4">
+          <bitfield name="DES_2" caption="JEP106 continuation code" mask="0xF"/>
+          <bitfield name="SIZE" caption="4KB count" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR5" offset="0xFD4" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Peripheral Identification Register 5"/>
+        <register name="DWT_PIDR6" offset="0xFD8" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Peripheral Identification Register 6"/>
+        <register name="DWT_PIDR7" offset="0xFDC" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Peripheral Identification Register 7"/>
+        <register name="DWT_PIDR0" offset="0xFE0" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 0">
+          <bitfield name="PART_0" caption="Part number bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="DWT_PIDR1" offset="0xFE4" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 1">
+          <bitfield name="PART_1" caption="Part number bits[11:8]" mask="0xF"/>
+          <bitfield name="DES_0" caption="JEP106 identification code bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR2" offset="0xFE8" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 2">
+          <bitfield name="DES_1" caption="JEP106 identification code bits[6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="JEDEC assignee value is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Component revision" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR3" offset="0xFEC" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 3">
+          <bitfield name="CMOD" caption="Customer Modified" mask="0xF"/>
+          <bitfield name="REVAND" caption="RevAnd" mask="0xF0"/>
+        </register>
+        <register name="DWT_CIDR0" offset="0xFF0" rw="R" size="4" access-size="4" initval="0x0000000D" caption="DWT Component Identification Register 0">
+          <bitfield name="PRMBL_0" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DWT_CIDR1" offset="0xFF4" rw="R" size="4" access-size="4" initval="0x00000090" caption="DWT Component Identification Register 1">
+          <bitfield name="PRMBL_1" caption="CoreSight component identification preamble" mask="0xF"/>
+          <bitfield name="CLASS" caption="CoreSight component class" mask="0xF0"/>
+        </register>
+        <register name="DWT_CIDR2" offset="0xFF8" rw="R" size="4" access-size="4" initval="0x00000005" caption="DWT Component Identification Register 2">
+          <bitfield name="PRMBL_2" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DWT_CIDR3" offset="0xFFC" rw="R" size="4" access-size="4" initval="0x000000B1" caption="DWT Component Identification Register 3">
+          <bitfield name="PRMBL_3" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="DWT_LAR__KEY">
+        <value name="UNLOCK" caption="Unlock key value" value="0xC5ACCE55"/>
+      </value-group>
+    </module>
+    <module name="EIC" id="03706" name2="int_eic_u2804_v1" version="1b0" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKSEL" caption="Clock Selection" mask="0x10" values="CTRLA__CKSEL"/>
+        </register>
+        <register name="NMICTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense Configuration" mask="0x7" values="NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+          <bitfield name="NMIASYNCH" caption="Asynchronous Edge Detection Mode" mask="0x10" values="NMICTRL__NMIASYNCH"/>
+        </register>
+        <register name="NMIFLAG" offset="0x2" rw="RW" size="2" atomic-op="clear:NMIFLAG" initval="0x0000" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x4" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy Status" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO" caption="External Interrupt Event Output Enable" mask="0xFFFF"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT" caption="External Interrupt Enable" mask="0xFFFF"/>
+          <bitfield name="NSCHK" caption="Non-secure Check Interrupt Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT" caption="External Interrupt Enable" mask="0xFFFF"/>
+          <bitfield name="NSCHK" caption="Non-secure Check Interrupt Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT" caption="External Interrupt" mask="0xFFFF"/>
+          <bitfield name="NSCHK" caption="Non-secure Check Interrupt" mask="0x80000000"/>
+        </register>
+        <register name="ASYNCH" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="External Interrupt Asynchronous Mode">
+          <bitfield name="ASYNCH" caption="Asynchronous Edge Detection Mode" mask="0xFFFF" values="ASYNCH__ASYNCH"/>
+        </register>
+        <register name="CONFIG" offset="0x1C" rw="RW" size="4" count="2" initval="0x00000000" caption="External Interrupt Sense Configuration">
+          <bitfield name="SENSE0" caption="Input Sense Configuration 0" mask="0x7" values="CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter Enable 0" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense Configuration 1" mask="0x70" values="CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter Enable 1" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense Configuration 2" mask="0x700" values="CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter Enable 2" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense Configuration 3" mask="0x7000" values="CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter Enable 3" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense Configuration 4" mask="0x70000" values="CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter Enable 4" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense Configuration 5" mask="0x700000" values="CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter Enable 5" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense Configuration 6" mask="0x7000000" values="CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter Enable 6" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense Configuration 7" mask="0x70000000" values="CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter Enable 7" mask="0x80000000"/>
+        </register>
+        <register name="DEBOUNCEN" offset="0x30" rw="RW" size="4" initval="0x00000000" caption="Debouncer Enable">
+          <bitfield name="DEBOUNCEN" caption="Debouncer Enable" mask="0xFFFF"/>
+        </register>
+        <register name="DPRESCALER" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Debouncer Prescaler">
+          <bitfield name="PRESCALER0" caption="Debouncer Prescaler" mask="0x7" values="DPRESCALER__PRESCALER"/>
+          <bitfield name="STATES0" caption="Debouncer number of states" mask="0x8" values="DPRESCALER__STATES"/>
+          <bitfield name="PRESCALER1" caption="Debouncer Prescaler" mask="0x70" values="DPRESCALER__PRESCALER"/>
+          <bitfield name="STATES1" caption="Debouncer number of states" mask="0x80" values="DPRESCALER__STATES"/>
+          <bitfield name="TICKON" caption="Pin Sampler frequency selection" mask="0x10000" values="DPRESCALER__TICKON"/>
+        </register>
+        <register name="PINSTATE" offset="0x38" rw="R" size="4" initval="0x00000000" caption="Pin State">
+          <bitfield name="PINSTATE" caption="Pin State" mask="0xFFFF"/>
+        </register>
+        <register name="NSCHK" offset="0x3C" rw="RW" size="4" initval="0x00000000" caption="Non-secure Interrupt Check Enable">
+          <bitfield name="EXTINT" caption="External Interrupt Nonsecure Check Enable" mask="0xFFFF"/>
+          <bitfield name="NMI" caption="Non-Maskable External Interrupt Nonsecure Check Enable" mask="0x80000000"/>
+        </register>
+        <register name="NONSEC" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Non-secure Interrupt">
+          <bitfield name="EXTINT" caption="External Interrupt Nonsecure Enable" mask="0xFFFF"/>
+          <bitfield name="NMI" caption="Non-Maskable Interrupt Nonsecure Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__CKSEL">
+        <value name="CLK_GCLK" caption="Clocked by GCLK" value="0"/>
+        <value name="CLK_ULP32K" caption="Clocked by ULP32K" value="1"/>
+      </value-group>
+      <value-group name="NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="NMICTRL__NMIASYNCH">
+        <value name="SYNC" caption="Edge detection is clock synchronously operated" value="0"/>
+        <value name="ASYNC" caption="Edge detection is clock asynchronously operated" value="1"/>
+      </value-group>
+      <value-group name="ASYNCH__ASYNCH">
+        <value name="SYNC" caption="EIC_EXTINTx edge detection is synchronously operated" value="0"/>
+        <value name="ASYNC" caption="EIC_EXTINTx edge detection is asynchronously operated" value="1"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="DPRESCALER__PRESCALER">
+        <value name="DIV2" caption="EIC clock divided by 2" value="0"/>
+        <value name="DIV4" caption="EIC clock divided by 4" value="1"/>
+        <value name="DIV8" caption="EIC clock divided by 8" value="2"/>
+        <value name="DIV16" caption="EIC clock divided by 16" value="3"/>
+        <value name="DIV32" caption="EIC clock divided by 32" value="4"/>
+        <value name="DIV64" caption="EIC clock divided by 64" value="5"/>
+        <value name="DIV128" caption="EIC clock divided by 128" value="6"/>
+        <value name="DIV256" caption="EIC clock divided by 256" value="7"/>
+      </value-group>
+      <value-group name="DPRESCALER__STATES">
+        <value name="LFREQ3" caption="3 low frequency samples" value="0"/>
+        <value name="LFREQ7" caption="7 low frequency samples" value="1"/>
+      </value-group>
+      <value-group name="DPRESCALER__TICKON">
+        <value name="CLK_GCLK_EIC" caption="Bounce sampler is using GCLK_EIC" value="0"/>
+        <value name="CLK_LFREQ" caption="Bounce sampler is using Low Frequency Clock" value="1"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="03601" name2="ptg_evsys_u2504_v2" version="2b0" caption="Event System Interface">
+      <register-group name="CHANNEL" size="0x8">
+        <register name="CHANNEL" offset="0x0" rw="RW" size="4" initval="0x00008000" caption="Channel n Control">
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x300" values="CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC00" values="CHANNEL__EDGSEL"/>
+          <bitfield name="RUNSTDBY" caption="Run in standby" mask="0x4000"/>
+          <bitfield name="ONDEMAND" caption="Generic Clock On Demand" mask="0x8000"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel n Interrupt Enable Clear">
+          <bitfield name="OVR" caption="Channel Overrun Interrupt Disable" mask="0x1"/>
+          <bitfield name="EVD" caption="Channel Event Detected Interrupt Disable" mask="0x2"/>
+        </register>
+        <register name="CHINTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel n Interrupt Enable Set">
+          <bitfield name="OVR" caption="Channel Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EVD" caption="Channel Event Detected Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel n Interrupt Flag Status and Clear">
+          <bitfield name="OVR" caption="Channel Overrun" mask="0x1"/>
+          <bitfield name="EVD" caption="Channel Event Detected" mask="0x2"/>
+        </register>
+        <register name="CHSTATUS" offset="0x7" rw="R" size="1" initval="0x01" caption="Channel n Status">
+          <bitfield name="RDYUSR" caption="Ready User" mask="0x1"/>
+          <bitfield name="BUSYCH" caption="Busy Channel" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRLA" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="SWEVT" offset="0x4" rw="W" size="4" initval="0x00000000" caption="Software Event">
+          <bitfield name="CHANNEL0" caption="Channel 0 Software Selection" mask="0x1"/>
+          <bitfield name="CHANNEL1" caption="Channel 1 Software Selection" mask="0x2"/>
+          <bitfield name="CHANNEL2" caption="Channel 2 Software Selection" mask="0x4"/>
+          <bitfield name="CHANNEL3" caption="Channel 3 Software Selection" mask="0x8"/>
+          <bitfield name="CHANNEL4" caption="Channel 4 Software Selection" mask="0x10"/>
+          <bitfield name="CHANNEL5" caption="Channel 5 Software Selection" mask="0x20"/>
+          <bitfield name="CHANNEL6" caption="Channel 6 Software Selection" mask="0x40"/>
+          <bitfield name="CHANNEL7" caption="Channel 7 Software Selection" mask="0x80"/>
+          <bitfield name="CHANNEL8" caption="Channel 8 Software Selection" mask="0x100"/>
+          <bitfield name="CHANNEL9" caption="Channel 9 Software Selection" mask="0x200"/>
+          <bitfield name="CHANNEL10" caption="Channel 10 Software Selection" mask="0x400"/>
+          <bitfield name="CHANNEL11" caption="Channel 11 Software Selection" mask="0x800"/>
+        </register>
+        <register name="PRICTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Priority Control">
+          <bitfield name="PRI" caption="Channel Priority Number" mask="0xF"/>
+          <bitfield name="RREN" caption="Round-Robin Scheduling Enable" mask="0x80"/>
+        </register>
+        <register name="INTPEND" offset="0x10" rw="RW" size="2" initval="0x4000" caption="Channel Pending Interrupt">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="OVR" caption="Channel Overrun" mask="0x100"/>
+          <bitfield name="EVD" caption="Channel Event Detected" mask="0x200"/>
+          <bitfield name="READY" caption="Ready" mask="0x4000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x14" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x18" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="READYUSR" offset="0x1C" rw="R" size="4" initval="0x00000FFF" caption="Ready Users">
+          <bitfield name="READYUSR0" caption="Ready User for Channel 0" mask="0x1"/>
+          <bitfield name="READYUSR1" caption="Ready User for Channel 1" mask="0x2"/>
+          <bitfield name="READYUSR2" caption="Ready User for Channel 2" mask="0x4"/>
+          <bitfield name="READYUSR3" caption="Ready User for Channel 3" mask="0x8"/>
+          <bitfield name="READYUSR4" caption="Ready User for Channel 4" mask="0x10"/>
+          <bitfield name="READYUSR5" caption="Ready User for Channel 5" mask="0x20"/>
+          <bitfield name="READYUSR6" caption="Ready User for Channel 6" mask="0x40"/>
+          <bitfield name="READYUSR7" caption="Ready User for Channel 7" mask="0x80"/>
+          <bitfield name="READYUSR8" caption="Ready User for Channel 8" mask="0x100"/>
+          <bitfield name="READYUSR9" caption="Ready User for Channel 9" mask="0x200"/>
+          <bitfield name="READYUSR10" caption="Ready User for Channel 10" mask="0x400"/>
+          <bitfield name="READYUSR11" caption="Ready User for Channel 11" mask="0x800"/>
+        </register>
+        <register-group name="CHANNEL" name-in-module="CHANNEL" offset="0x020" size="0x8" count="12"/>
+        <register name="USER" offset="0x120" rw="RW" size="1" count="62" initval="0x00" caption="User Multiplexer n">
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0xF"/>
+        </register>
+      </register-group>
+      <value-group name="CHANNEL__PATH">
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="0x0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="0x1"/>
+      </value-group>
+      <value-group name="CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+    </module>
+    <module name="FCR" id="04972" name2="pfm_ctrlr_apb_v2" version="2a0" caption="Polaris Flash Read Controller">
+      <register-group name="FCR" caption="Polaris Flash Read Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00008000" caption="CTRL A REGISTER">
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+          <bitfield name="FWS" caption="Flash Access Time Defined in terms of AHB Clock Wait States" mask="0xF00" values="CTRLA__FWS"/>
+          <bitfield name="ADRWS" caption="Address Wait State Enable" mask="0x4000" values="CTRLA__ADRWS"/>
+          <bitfield name="AUTOWS" caption="Automatic Wait State Enable." mask="0x8000" values="CTRLA__AUTOWS"/>
+          <bitfield name="RDBUFWS" caption="Read Buffer Wait StatesPer AHB port control of deterministic or zero wait state read buffer access." mask="0x10000" values="CTRLA__RDBUFWS"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CTRL B REGISTER">
+          <bitfield name="PRM" caption="Set NVM Power Reduction Mode" mask="0x1" values="CTRLB__PRM"/>
+          <bitfield name="CHEINV" caption="Cache InvalidateCache invalidation takes 1 clock cycle, but may be delayed by an active read." mask="0x80" values="CTRLB__CHEINV"/>
+          <bitfield name="SLP" caption="NVM Power Reduction Mode selection during System Standby Sleep" mask="0x300" values="CTRLB__SLP"/>
+          <bitfield name="CHEDIS" caption="Cache Disable" mask="0x10000" values="CTRLB__CHEDIS"/>
+          <bitfield name="PREFDIS" caption="Prefetch Disable" mask="0x20000" values="CTRLB__PREFDIS"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Clear Enable" mask="0x1" values="INTENCLR__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Clear Enable" mask="0x100" values="INTENCLR__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Clear Enable" mask="0x200" values="INTENCLR__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Clear Enable" mask="0x10000" values="INTENCLR__FLTCAP"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable SET REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Set Enable" mask="0x1" values="INTENSET__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Set Enable" mask="0x100" values="INTENSET__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Set Enable" mask="0x200" values="INTENSET__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Set Enable" mask="0x10000" values="INTENSET__FLTCAP"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Flag" mask="0x1" values="INTFLAG__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Flag" mask="0x100" values="INTFLAG__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Flag" mask="0x200" values="INTFLAG__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Flag" mask="0x10000" values="INTFLAG__FLTCAP"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="Interrupt Flag Set REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Flag" mask="0x1" values="INTFLAGSET__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Flag" mask="0x100" values="INTFLAGSET__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Flag" mask="0x200" values="INTFLAGSET__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Flag" mask="0x10000" values="INTFLAGSET__FLTCAP"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="R" size="4" initval="0xE0000000" caption="Status REGISTER">
+          <bitfield name="PRM" caption="NVM Power Reduction Mode Status" mask="0x1" values="STATUS__PRM"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Debug Control CTRL REGISTER">
+          <bitfield name="CRCRUN" caption="CRC Debug Run Enable" mask="0x1" values="DBGCTRL__CRCRUN"/>
+          <bitfield name="DBGECC" caption="Debug ECC ModeECC errors from debugger reads are:" mask="0x6" values="DBGCTRL__DBGECC"/>
+        </register>
+        <register name="ECCCTRL" offset="0x20" rw="RW" size="4" initval="0x00000040" caption="ECC Control REGISTER">
+          <bitfield name="ECCCTL" caption="NVM ECC Mode Control - restricts one or more NVMOPs" mask="0x30" values="ECCCTRL__ECCCTL"/>
+          <bitfield name="ECCUNLCK" caption="NVM ECC Mode Control Unlock" mask="0x40" values="ECCCTRL__ECCUNLCK"/>
+          <bitfield name="SECCNT" caption="Flash SEC Count" mask="0xFF00"/>
+        </register>
+        <register name="CRCCTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="CRC Control REGISTER">
+          <bitfield name="CRCRST" caption="CRC Reset" mask="0x1" values="CRCCTRL__CRCRST"/>
+          <bitfield name="CRCEN" caption="Start CRC Calculation" mask="0x2" values="CRCCTRL__CRCEN"/>
+          <bitfield name="RUNSTDBY" caption="CRC Run in Standby" mask="0x20" values="CRCCTRL__RUNSTDBY"/>
+        </register>
+        <register name="CRCMODE" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="CRC MODE REGISTER">
+          <bitfield name="PLEN32" caption="Polynomial Length Select" mask="0x1000" values="CRCMODE__PLEN32"/>
+          <bitfield name="AUTOR" caption="CRC Auto Repeat" mask="0x2000" values="CRCMODE__AUTOR"/>
+          <bitfield name="ROUT" caption="CRC Reflected Output" mask="0x4000" values="CRCMODE__ROUT"/>
+          <bitfield name="RIN" caption="CRC Reflected Input" mask="0x8000" values="CRCMODE__RIN"/>
+          <bitfield name="PERIOD" caption="Read Period in PerCLK counts" mask="0xFFF0000"/>
+        </register>
+        <register name="CRCPAUSE" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="CRC Pause REGISTER">
+          <bitfield name="PAUSE" caption="CRC Pause" mask="0x1" values="CRCPAUSE__PAUSE"/>
+        </register>
+        <register name="CRCMADR" offset="0x30" rw="RW" size="4" initval="0x00000000" caption="CRC Message Address REGISTER">
+          <bitfield name="CRCMADR" caption="Message Start Address in Flash" mask="0xFFFFFFF"/>
+        </register>
+        <register name="CRCMLEN" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="CRC Message Length REGISTER">
+          <bitfield name="CRCMLEN" caption="Message Length in Bytes" mask="0xFFFFF"/>
+        </register>
+        <register name="CRCIV" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="CRC Initial Value REGISTER">
+          <bitfield name="CRCIV" caption="CRC Initial Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCACC" offset="0x3C" rw="R" size="4" initval="0x00000000" caption="CRC Accumulator REGISTER">
+          <bitfield name="CRCACC" caption="CRC Accumulator Result" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCPOLY" offset="0x40" rw="RW" size="4" initval="0x00000001" caption="CRC Polynomial REGISTER">
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Coefficients for LFSR" mask="0xFFFFFFFF" values="CRCPOLY__CRCPOLY"/>
+        </register>
+        <register name="CRCFXOR" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="CRC Final XOR REGISTER">
+          <bitfield name="CRCFXOR" caption="CRC Final XOR" mask="0xFFFFFFFF" values="CRCFXOR__CRCFXOR"/>
+        </register>
+        <register name="CRCSUM" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="CRC CheckSUM REGISTER">
+          <bitfield name="CRCSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FFLTCTRL" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Control REGISTER">
+          <bitfield name="FLTRST" caption="Fault Reset" mask="0x1" values="FFLTCTRL__FLTRST"/>
+          <bitfield name="FLTEN" caption="ECC Fault Enable bit" mask="0x2" values="FFLTCTRL__FLTEN"/>
+        </register>
+        <register name="FFLTMODE" offset="0x50" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Mode REGISTER">
+          <bitfield name="CTLFLT" caption="ECC/Parity Control Fault bits" mask="0x700" values="FFLTMODE__CTLFLT"/>
+          <bitfield name="FLTMD" caption="Fault Mode Control" mask="0x7000" values="FFLTMODE__FLTMD"/>
+        </register>
+        <register name="FFLTPTR" offset="0x54" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Pointer REGISTER">
+          <bitfield name="FLTPTR1" caption="Fault 1 Injection Pointer" mask="0xFF"/>
+          <bitfield name="FLTPTR2" caption="Fault 2 Injection Pointer" mask="0xFF0000"/>
+        </register>
+        <register name="FFLTADR" offset="0x58" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Address REGISTER">
+          <bitfield name="FLTADR" caption="Fault Injection Address" mask="0xFFFFFFF"/>
+        </register>
+        <register name="FFLTCAP" offset="0x5C" rw="R" size="4" initval="0x00000000" caption="Flash ECC Fault Capture Address REGISTER">
+          <bitfield name="FLTADR" caption="Fault Capture Address" mask="0xFFFFFFF"/>
+        </register>
+        <register name="FFLTPAR" offset="0x60" rw="R" size="4" initval="0x00000000" caption="Flash ECC Fault Parity REGISTER">
+          <bitfield name="SECIN" caption="The Single Error Parity bits from Flash" mask="0xFF"/>
+          <bitfield name="DEDIN" caption="The Overall Parity from Flash" mask="0x8000"/>
+          <bitfield name="SECOUT" caption="The Calculated Single Error Parity bits" mask="0xFF0000"/>
+          <bitfield name="DEDOUT" caption="The Calculated Overall Parity used in Double Error Detection" mask="0x80000000"/>
+        </register>
+        <register name="FFLTSYN" offset="0x64" rw="R" size="4" initval="0x00000000" caption="Flash ECC Fault Syndrome REGISTER">
+          <bitfield name="SECSYN" caption="Single Error Correction Syndrome" mask="0xFF"/>
+          <bitfield name="DEDSYN" caption="DED Syndrome" mask="0x8000" values="FFLTSYN__DEDSYN"/>
+          <bitfield name="DSERR" caption="Double Error Detected &amp; Single Error Corrected" mask="0x30000" values="FFLTSYN__DSERR"/>
+          <bitfield name="CERR" caption="ECC Control bit Error" mask="0x40000" values="FFLTSYN__CERR"/>
+          <bitfield name="CTLSTAT" caption="Parity vs ECC Control Status" mask="0x7000000" values="FFLTSYN__CTLSTAT"/>
+          <bitfield name="PERR" caption="Per Word (n=3:0) Parity Error Status" mask="0xF0000000" values="FFLTSYN__PERR"/>
+        </register>
+        <register name="CRP" offset="0x68" rw="RW" size="4" initval="0x00C20000" caption="CFM Page Read Protection REGISTER (CFM8)">
+          <bitfield name="BC1ARP" caption="Panel 1 Read Protect BootCfg1A" mask="0x1" values="CRP__BC1ARP"/>
+          <bitfield name="UO1RP" caption="Panel 1 Read Protect UserOTP1" mask="0x2" values="CRP__UO1RP"/>
+          <bitfield name="BC1RP" caption="Panel 1 Read Protect BootCfg1" mask="0x4" values="CRP__BC1RP"/>
+          <bitfield name="RCRP" caption="Panel 1 Read Protect ROMCfg" mask="0x8" values="CRP__RCRP"/>
+          <bitfield name="VSSRP0" caption="Panel 1 Read Protect VSSn" mask="0x10" values="CRP__VSSRP"/>
+          <bitfield name="VSSRP1" caption="Panel 1 Read Protect VSSn" mask="0x20" values="CRP__VSSRP"/>
+          <bitfield name="TRP" caption="Panel 1 Read Protect Test" mask="0x40" values="CRP__TRP"/>
+          <bitfield name="CORP" caption="Panel 1 Read Protect CalOTP" mask="0x80" values="CRP__CORP"/>
+          <bitfield name="BC1ARPLOCK" caption="Panel 1 Lock Read Protection BootCfg1A" mask="0x10000" values="CRP__BC1ARPLOCK"/>
+          <bitfield name="UO1RPLOCK" caption="Panel 1 Lock Read Protection UserOTP1" mask="0x20000" values="CRP__UO1RPLOCK"/>
+          <bitfield name="BC1RPLOCK" caption="Panel 1 Lock Read Protection BootCfg1" mask="0x40000" values="CRP__BC1RPLOCK"/>
+          <bitfield name="RCRPLOCK" caption="Panel 1 Lock Read Protection ROMCfg" mask="0x80000" values="CRP__RCRPLOCK"/>
+          <bitfield name="VSSRPLOCK0" caption="Panel 1 Lock Read Protection VSSn" mask="0x100000" values="CRP__VSSRPLOCK"/>
+          <bitfield name="VSSRPLOCK1" caption="Panel 1 Lock Read Protection VSSn" mask="0x200000" values="CRP__VSSRPLOCK"/>
+          <bitfield name="TRPLOCK" caption="Panel 1 Lock Read Protection Test" mask="0x400000" values="CRP__TRPLOCK"/>
+          <bitfield name="CORPLOCK" caption="Panel 1 Lock Read Protection CalOTP" mask="0x800000" values="CRP__CORPLOCK"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="DISABLE" caption="Macro register accessible in privileged and unprivileged accesses." value="0"/>
+        <value name="ENABLE" caption="Macro registers only accessible in privileged accesses" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__FWS">
+        <value name="0" caption="Zero Wait States" value="0"/>
+        <value name="1" caption="One Wait State" value="1"/>
+        <value name="14" caption="Fourteen Wait States" value="14"/>
+        <value name="15" caption="Fifteen Wait States" value="15"/>
+      </value-group>
+      <value-group name="CTRLA__ADRWS">
+        <value name="ZERO" caption="Add 0 Address Wait States - allowing for higher performance at lower clock frequencies" value="0"/>
+        <value name="ONE" caption="Add 1 Address Wait State - allowing for higher clock frequencies" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__AUTOWS">
+        <value name="DISABLE" caption="Use FWS: Total flash wait states are ADRWS + FWS" value="0"/>
+        <value name="ENABLE" caption="Use Automatic wait states: Total flash wait states are ADRWS + Taws" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__RDBUFWS">
+        <value name="ZEROWS" caption="0 Wait States" value="0"/>
+        <value name="DETERMINISTIC" caption="ADRWS + FWS wait state for hits to AHB read buffer" value="1"/>
+      </value-group>
+      <value-group name="CTRLB__PRM">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="TOGGLE" caption="Toggle the Flash Power Mode" value="1"/>
+      </value-group>
+      <value-group name="CTRLB__CHEINV">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="INV" caption="Invalidate Cache" value="1"/>
+      </value-group>
+      <value-group name="CTRLB__SLP">
+        <value name="MANUAL" caption="Maintain state of STATUS.PRM on entry to Standby" value="0"/>
+        <value name="RSVD01" caption="RSVD" value="1"/>
+        <value name="AUTOFAST" caption="Enter Flash Hibernate on entry to Standby w/ wakeup to Auto Standby" value="2"/>
+        <value name="AUTOSLOW" caption="Enter Flash Hibernate on entry to Standby w/ wakeup on first access" value="3"/>
+      </value-group>
+      <value-group name="CTRLB__CHEDIS">
+        <value name="ENABLE" caption="Cache Enabled; Accesses to flash use AUTOWS/FSW selection." value="0"/>
+        <value name="DISABLE" caption="Cache Disabled; Interface uses RDBUFWS selection." value="1"/>
+      </value-group>
+      <value-group name="CTRLB__PREFDIS">
+        <value name="ENABLE" caption="Predictive Prefetch Enabled" value="0"/>
+        <value name="DISABLE" caption="Predictive Prefetch Disabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__SERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__CRCDONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__CRCERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__FLTCAP">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__SERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CRCDONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CRCERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__FLTCAP">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__SERR">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="SECCNT Count reached" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__CRCDONE">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="Calculation Done" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__CRCERR">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="CRCACC Is Not Equal to the XOR of CRCSUM and CRCFXOR" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__FLTCAP">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="An ECC Fault Capture, related to FLTMD[], occurred" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__SERR">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="SECCNT Count reached" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__CRCDONE">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__CRCERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__FLTCAP">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="STATUS__PRM">
+        <value name="0" caption="Flash is Ready (for read or NVMOP)" value="0"/>
+        <value name="1" caption="Flash is Powered Down and wakes on first access (read or NVMOP)" value="1"/>
+      </value-group>
+      <value-group name="DBGCTRL__CRCRUN">
+        <value name="HALT" caption="CRC Logic Halts in Debug Mode" value="0"/>
+        <value name="RUN" caption="CRC Logic Runs in Debug Mode." value="1"/>
+      </value-group>
+      <value-group name="DBGCTRL__DBGECC">
+        <value name="NOERR" caption="Corrected per ECCCTRL; No Bus ERR; INTFLAG, SEC counter, and FLT logic are not updated." value="0"/>
+        <value name="DISABLE" caption="Not corrected; No Bus Error; INTFLAG, SEC counter, and FLT logic are not updated." value="1"/>
+        <value name="ENABLE" caption="Corrected per ECCCTRL; Bus Error, INTFLAG, SEC counter, and FLT logic operates as setup." value="2"/>
+        <value name="RSVD11" caption="Don't use but same as 01 (DISABLE)" value="3"/>
+      </value-group>
+      <value-group name="ECCCTRL__ECCCTL">
+        <value name="STRICT" caption="ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)" value="0"/>
+        <value name="DYNAMIC" caption="Dynamic Writes with Dynamic Reads" value="1"/>
+        <value name="ECC" caption="ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)" value="2"/>
+        <value name="DISABLE" caption="Dynamic Writes with No Error Check Reads" value="3"/>
+      </value-group>
+      <value-group name="ECCCTRL__ECCUNLCK">
+        <value name="LOCKED" caption="ECCUNLCK and ECCCTL[1:0] cannot be written" value="0"/>
+        <value name="UNLOCKED" caption="ECCUNLCK and ECCCTL[1:0] can be written" value="1"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCRST">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="RESET" caption="Resets all CRC SFR bits." value="1"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCEN">
+        <value name="DISABLE" caption="Stops CRC calculation." value="0"/>
+        <value name="ENABLE" caption="CRC Calculation Enabled (w/ start on write to 1)." value="1"/>
+      </value-group>
+      <value-group name="CRCCTRL__RUNSTDBY">
+        <value name="HALT" caption="CRC Halts in Standby" value="0"/>
+        <value name="RUN" caption="CRC Runs in Standby but only if STATUS.PRM=0 (i.e. Flash is in Auto Standby)" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__PLEN32">
+        <value name="SIXTEEN" caption="Polynomial is 16-bits" value="0"/>
+        <value name="THIRTYTWO" caption="Polynomial is 32-bits" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__AUTOR">
+        <value name="DISABLE" caption="Perform CRC calculation once then set DONE and if needed, CRCERR." value="0"/>
+        <value name="ENABLE" caption="Continually Repeat CRC calculation; stop on error, set CRCDONE and CRCERR" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__ROUT">
+        <value name="DISABLE" caption="The CRCACC is Not Reflected" value="0"/>
+        <value name="ENABLE" caption="The CRCACC is Reflected (before the Final XOR)" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__RIN">
+        <value name="DISABLE" caption="The LFSR CRC is calculated Most Significant Bit first (Not Reflected)" value="0"/>
+        <value name="ENABLE" caption="The LFSR CRC is calculated Least Significant Bit first (Reflected)" value="1"/>
+      </value-group>
+      <value-group name="CRCPAUSE__PAUSE">
+        <value name="DISABLE" caption="CRC Reads Flash as Required" value="0"/>
+        <value name="ENABLE" caption="Pause CRC Reads of Flash" value="1"/>
+      </value-group>
+      <value-group name="CRCPOLY__CRCPOLY">
+        <value name="0" caption="Disable the XOR input to the shift register at the associated bit position" value="0"/>
+        <value name="1" caption="Enable the XOR input to the shift register at the associated bit position" value="1"/>
+      </value-group>
+      <value-group name="CRCFXOR__CRCFXOR">
+        <value name="0" caption="Disable the Final XOR at the associated bit position" value="0"/>
+        <value name="1" caption="Enable the Final XOR at the associated bit position" value="1"/>
+      </value-group>
+      <value-group name="FFLTCTRL__FLTRST">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="RESET" caption="Resets all FLT SFR bits." value="1"/>
+      </value-group>
+      <value-group name="FFLTCTRL__FLTEN">
+        <value name="DISABLE" caption="ECC Fault Injection Disabled" value="0"/>
+        <value name="ENABLE" caption="ECC Fault Injection Enabled (module performs operation selected by FFLTMODE.FLTMD)" value="1"/>
+      </value-group>
+      <value-group name="FFLTMODE__CTLFLT">
+        <value name="0" caption="No Fault Injected" value="0"/>
+        <value name="1" caption="Inject a Fault on to the associated ECC/Parity Control bits (CTL[n])" value="1"/>
+      </value-group>
+      <value-group name="FFLTMODE__FLTMD">
+        <value name="DISABLE" caption="Fault Injection Disabled" value="0"/>
+        <value name="CAPT" caption="Fault Capture Mode Enabled - Captures the address (in FLTADR) and Syndrome in (FLTSYN)" value="2"/>
+        <value name="SINGLEREAD" caption="Single Fault Injection (at bit selected by FLT1PTR) for Reads" value="4"/>
+        <value name="DOUBLEREAD" caption="Double Fault Injection for Reads" value="5"/>
+        <value name="SINGLEWRITE" caption="Single Fault Injection (at bit selected by FLT1PTR) for Writes" value="6"/>
+        <value name="DOUBLEWRITE" caption="Double Fault Injection for Writes" value="7"/>
+      </value-group>
+      <value-group name="FFLTSYN__DEDSYN">
+        <value name="0" caption="Calculated Overall Parity Concurs with Read Overall Parity" value="0"/>
+        <value name="1" caption="Calculated Overall Parity Differs from Read Overall Parity" value="1"/>
+      </value-group>
+      <value-group name="FFLTSYN__DSERR">
+        <value name="NONE" caption="No Errors" value="0"/>
+        <value name="SINGLE" caption="Single Error Corrected" value="1"/>
+        <value name="DOUBLE_10" caption="Double Error Detected" value="2"/>
+        <value name="DOUBLE_11" caption="Double Error Detected" value="3"/>
+      </value-group>
+      <value-group name="FFLTSYN__CERR">
+        <value name="NONE" caption="No Control bit Error (ECCSTAT either 111 or 000)" value="0"/>
+        <value name="SINGLE" caption="Single Control Bit Error" value="1"/>
+      </value-group>
+      <value-group name="FFLTSYN__CTLSTAT">
+        <value name="USEDECC_0" caption="Calculation used ECC (i.e. programming used quad write)" value="0"/>
+        <value name="USEDECC_1" caption="Calculation used ECC (i.e. programming used quad write)" value="1"/>
+        <value name="USEDECC_10" caption="Calculation used ECC (i.e. programming used quad write)" value="2"/>
+        <value name="USEDPARITY_11" caption="Calculation used Parity (i.e. programming used single write)" value="3"/>
+        <value name="USEDECC_100" caption="Calculation used ECC (i.e. programming used quad write)" value="4"/>
+        <value name="USEDPARITY_101" caption="Calculation used Parity (i.e. programming used single write)" value="5"/>
+        <value name="USEDPARITY_110" caption="Calculation used Parity (i.e. programming used single write)" value="6"/>
+        <value name="USEDPARITY_111" caption="Calculation used Parity (i.e. programming used single write)" value="7"/>
+      </value-group>
+      <value-group name="FFLTSYN__PERR">
+        <value name="NONE" caption="No Parity Error on Word n" value="0"/>
+        <value name="ERROR" caption="Parity Error on Word n" value="1"/>
+      </value-group>
+      <value-group name="CRP__BC1ARP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__UO1RP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+      </value-group>
+      <value-group name="CRP__BC1RP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__RCRP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__VSSRP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__TRP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__CORP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__BC1ARPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__UO1RPLOCK">
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__BC1RPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__RCRPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__VSSRPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__TRPLOCK">
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__CORPLOCK">
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+    </module>
+    <module name="FCW" id="04971" name2="pfm_ctrlw_apb_v2" version="2a0" caption="Polaris Flash Write Controller">
+      <register-group name="FCW" caption="Polaris Flash Write Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A REGISTER">
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+        </register>
+        <register name="CTRLOP" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control Operation REGISTER">
+          <bitfield name="NVMOP" caption="NVM Operation" mask="0xF" values="CTRLOP__NVMOP"/>
+          <bitfield name="PREPG" caption="NVM Pre-Program Configuration Bit" mask="0x80" values="CTRLOP__PREPG"/>
+        </register>
+        <register name="MUTEX" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="MUTEX REGISTER">
+          <bitfield name="LOCK" caption="Flash Write Controller (FCW) Lock by Owner" mask="0x1" values="MUTEX__LOCK"/>
+          <bitfield name="OWNER" caption="Flash Write Controller (FCW) Owner ID" mask="0x6" values="MUTEX__OWNER"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Interrupt Enable" mask="0x1" values="INTENCLR__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Interrupt Enable" mask="0x2" values="INTENCLR__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Interrupt Enable" mask="0x4" values="INTENCLR__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Interrupt Enable" mask="0x8" values="INTENCLR__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Interrupt Enable" mask="0x10" values="INTENCLR__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Interrupt Enable" mask="0x20" values="INTENCLR__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Interrupt Enable" mask="0x40" values="INTENCLR__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Interrupt Enable" mask="0x100" values="INTENCLR__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Interrupt Enable" mask="0x1000" values="INTENCLR__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Interrupt Enable" mask="0x2000" values="INTENCLR__WRERR"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Interrupt Set Enable" mask="0x1" values="INTENSET__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Interrupt Set Enable" mask="0x2" values="INTENSET__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Interrupt Set Enable" mask="0x4" values="INTENSET__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Interrupt Set Enable" mask="0x8" values="INTENSET__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Interrupt Enable" mask="0x10" values="INTENSET__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Interrupt Enable" mask="0x20" values="INTENSET__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Interrupt Enable" mask="0x40" values="INTENSET__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Interrupt Enable" mask="0x100" values="INTENSET__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Interrupt Enable" mask="0x1000" values="INTENSET__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Interrupt Enable" mask="0x2000" values="INTENSET__WRERR"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Flag Bit" mask="0x1" values="INTFLAG__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Flag Bit" mask="0x2" values="INTFLAG__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Flag Bit" mask="0x4" values="INTFLAG__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Flag Bit" mask="0x8" values="INTFLAG__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Flag Bit" mask="0x10" values="INTFLAG__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Flag Bit" mask="0x20" values="INTFLAG__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Flag Bit" mask="0x40" values="INTFLAG__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Flag Bit" mask="0x100" values="INTFLAG__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Flag Bit" mask="0x1000" values="INTFLAG__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Flag Bit" mask="0x2000" values="INTFLAG__WRERR"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="Interrupt Flag Set REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Set Flag Bit" mask="0x1" values="INTFLAGSET__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Set Flag Bit" mask="0x2" values="INTFLAGSET__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Set Flag Bit" mask="0x4" values="INTFLAGSET__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Set Flag Bit" mask="0x8" values="INTFLAGSET__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Set Flag Bit" mask="0x10" values="INTFLAGSET__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Set Flag Bit" mask="0x20" values="INTFLAGSET__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Set Flag Bit" mask="0x40" values="INTFLAGSET__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Set Flag Bit" mask="0x100" values="INTFLAGSET__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Set Flag Bit" mask="0x1000" values="INTFLAGSET__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Set Flag Bit" mask="0x2000" values="INTFLAGSET__WRERR"/>
+        </register>
+        <register name="STATUS" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="Status REGISTER">
+          <bitfield name="BUSY" caption="NVM Busy Status" mask="0x1" values="STATUS__BUSY"/>
+          <bitfield name="HTDRDY" caption="High Temp Detect Ready Status" mask="0x100" values="STATUS__HTDRDY"/>
+        </register>
+        <register name="KEY" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Feature Unlock Key REGISTER">
+          <bitfield name="FEATURE" caption="Feature Select" mask="0xFF" values="KEY__FEATURE"/>
+          <bitfield name="CODE" caption="Unlock Code" mask="0xFFFFFF00"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Flash Destination Address REGISTER">
+          <bitfield name="ADDR" caption="Flash Address used by NVMOP" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="System Source Address REGISTER">
+          <bitfield name="SRCADDR" caption="Source Data (Word) Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DATA" offset="0x2C" rw="RW" size="4" count="4" initval="0x00000000" caption="Flash Write Data n REGISTER">
+          <bitfield name="DATA" caption="Flash Write Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="SWAP" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="NVM Panel Swap REGISTER">
+          <bitfield name="BFSWAP" caption="BFM Swap Status/Control Bit" mask="0x1" values="SWAP__BFSWAP"/>
+          <bitfield name="BFSLOCK" caption="BFM Swap Lock Bit" mask="0x2" values="SWAP__BFSLOCK"/>
+          <bitfield name="PFSWAP" caption="PFM Swap Status/Control Bit" mask="0x100" values="SWAP__PFSWAP"/>
+          <bitfield name="PFSLOCK" caption="PFM Swap Lock Bit" mask="0x200" values="SWAP__PFSLOCK"/>
+        </register>
+        <register name="PWP" offset="0x50" rw="RW" size="4" count="4" initval="0x00000000" caption="PFM Write Protect Region n REGISTER">
+          <bitfield name="PWPSIZE" caption="PWP Size in 4KB pages" mask="0x7F"/>
+          <bitfield name="PWPMIR" caption="Mirror PWP bit" mask="0x2000" values="PWP__PWPMIR"/>
+          <bitfield name="PWPLOCK" caption="PWP Lock Bit" mask="0x4000" values="PWP__PWPLOCK"/>
+          <bitfield name="PWPEN" caption="PWP Enable Bit" mask="0x8000" values="PWP__PWPEN"/>
+          <bitfield name="PWPBASE" caption="PWP Base Address - 4KB Page Aligned" mask="0x7F0000"/>
+        </register>
+        <register name="LBWP" offset="0x70" rw="RW" size="4" initval="0x00000003" caption="Lower BFM Write Protect REGISTER">
+          <bitfield name="LBWP" caption="Lower Boot Pages Write Protect Bits" mask="0x3" values="LBWP__LBWP"/>
+          <bitfield name="LBWPLOCK" caption="LBWP Lock Bit" mask="0x80000000" values="LBWP__LBWPLOCK"/>
+        </register>
+        <register name="UBWP" offset="0x74" rw="RW" size="4" initval="0x00000003" caption="Upper BFM Write Protect REGISTER">
+          <bitfield name="UBWP" caption="Upper Boot Pages Write Protect Bits" mask="0x3" values="UBWP__UBWP"/>
+          <bitfield name="UBWPLOCK" caption="UBWP Lock Bit" mask="0x80000000" values="UBWP__UBWPLOCK"/>
+        </register>
+        <register name="UOWP" offset="0x78" rw="RW" size="4" initval="0x0000000F" caption="User OTP Write protection REGISTER">
+          <bitfield name="UO1WPR" caption="User OTP Page 1 Write Protect Row Bit" mask="0xF" values="UOWP__UO1WPR"/>
+          <bitfield name="UO1WPRLOCK" caption="User OTP Page 1 WP Row Lock Bit" mask="0xF0000" values="UOWP__UO1WPRLOCK"/>
+        </register>
+        <register name="CWP" offset="0x7C" rw="RW" size="4" initval="0x08C008FD" caption="CFM Page Write Protect REGISTER">
+          <bitfield name="BC1AWP" caption="Panel 1 Write Protect BootCfg1A" mask="0x1" values="CWP__BC1AWP"/>
+          <bitfield name="BC1WP" caption="Panel 1 Write Protect BootCfg1" mask="0x4" values="CWP__BC1WP"/>
+          <bitfield name="RCWP" caption="Panel 1 Write Protect ROMCfg" mask="0x8" values="CWP__RCWP"/>
+          <bitfield name="VSSWP0" caption="Panel 1 Write Protect VSSn" mask="0x10" values="CWP__VSSWP"/>
+          <bitfield name="VSSWP1" caption="Panel 1 Write Protect VSSn" mask="0x20" values="CWP__VSSWP"/>
+          <bitfield name="TWP" caption="Panel 1 Write Protect Test" mask="0x40" values="CWP__TWP"/>
+          <bitfield name="COWP" caption="Panel 1 Write Protect CalOTP" mask="0x80" values="CWP__COWP"/>
+          <bitfield name="BC1AWPLOCK" caption="Panel 1 Lock Write Protection BootCfg1A" mask="0x10000" values="CWP__BC1AWPLOCK"/>
+          <bitfield name="BC1WPLOCK" caption="Panel 1 Lock Write Protection BootCfg1" mask="0x40000" values="CWP__BC1WPLOCK"/>
+          <bitfield name="RCWPLOCK" caption="Panel 1 Lock Write Protection ROMCfg" mask="0x80000" values="CWP__RCWPLOCK"/>
+          <bitfield name="VSSWPLOCK0" caption="Panel 1 Lock Write Protection VSSn" mask="0x100000" values="CWP__VSSWPLOCK"/>
+          <bitfield name="VSSWPLOCK1" caption="Panel 1 Lock Write Protection VSSn" mask="0x200000" values="CWP__VSSWPLOCK"/>
+          <bitfield name="TWPLOCK" caption="Panel 1 Lock Write Protection Test" mask="0x400000" values="CWP__TWPLOCK"/>
+          <bitfield name="COWPLOCK" caption="Panel 1 Lock Write Protection CalOTP" mask="0x800000" values="CWP__COWPLOCK"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="DISABLE" caption="Macro register accessible in privileged and unprivileged accesses." value="0"/>
+        <value name="ENABLE" caption="Macro registers only accessible in privileged accesses" value="1"/>
+      </value-group>
+      <value-group name="CTRLOP__NVMOP">
+        <value name="NOP" caption="No Operation" value="0"/>
+        <value name="SINGLEWRITE" caption="Single (Word) Program Operation: Programs word selected by ADDR" value="1"/>
+        <value name="QUADWRITE" caption="Quad (Word) Program Operation: Programs flash word selected by ADDR" value="2"/>
+        <value name="ROWWRITE" caption="Row Write Operation: Programs row selected by ADDR" value="3"/>
+        <value name="PAGEERASE" caption="Page Erase Operation: Erases page selected by ADDR" value="4"/>
+        <value name="LPFMERASE" caption="Lower PFM Erase Operation: (RSVD NVMOP for Single Panel Devices)" value="5"/>
+        <value name="UPFMERASE" caption="Upper PFM Erase Operation: (RSVD NVMOP for Single Panel Devices)" value="6"/>
+        <value name="PFMERASE" caption="PFM Erase Operation: Upper &amp;amp; Lower PFM Erase" value="7"/>
+        <value name="CE" caption="Chip Erase Operation: Erases PFM+SRF, BFM, CFM (except for CalOTP, Test, VSS pages if HSM is Present, UserOTP, &amp;amp; ROMCFG)." value="14"/>
+      </value-group>
+      <value-group name="CTRLOP__PREPG">
+        <value name="DISABLE" caption="Program Operations exclude Pre-Program step" value="0"/>
+        <value name="ENABLE" caption="Program Operations include Pre-Program step" value="1"/>
+      </value-group>
+      <value-group name="MUTEX__LOCK">
+        <value name="UNLOCK" caption="FCW is not locked" value="0"/>
+        <value name="LOCK" caption="FCW is locked by owner" value="1"/>
+      </value-group>
+      <value-group name="MUTEX__OWNER">
+        <value name="NONE" caption="No Owner - always 0 if LOCK=0" value="0"/>
+        <value name="SYSTEM" caption="The System owns the FCW" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__DONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__KEYERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__CFGERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__FIFOERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__BUSERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__WPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__OPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__HTDPGM">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__RSTERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__WRERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__DONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__KEYERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CFGERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__FIFOERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__BUSERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__WPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__OPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__HTDPGM">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__RSTERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__WRERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__DONE">
+        <value name="0" caption="NVMOP Not Done" value="0"/>
+        <value name="1" caption="NVMOP Done" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__KEYERR">
+        <value name="0" caption="No Key Error" value="0"/>
+        <value name="1" caption="Key Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__CFGERR">
+        <value name="0" caption="No CFG Error" value="0"/>
+        <value name="1" caption="CFC Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__FIFOERR">
+        <value name="0" caption="No FIFO Error" value="0"/>
+        <value name="1" caption="FIFO Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__BUSERR">
+        <value name="0" caption="No Bus Error" value="0"/>
+        <value name="1" caption="Bus Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__WPERR">
+        <value name="0" caption="No Write Protection Error" value="0"/>
+        <value name="1" caption="Write Protection Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__OPERR">
+        <value name="0" caption="No NVMOP Error" value="0"/>
+        <value name="1" caption="Selected Operation is Disabled Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__HTDPGM">
+        <value name="0" caption="High Temp NOT Detected" value="0"/>
+        <value name="1" caption="High Temp Detected (possible data corruption, verify operation)" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__RSTERR">
+        <value name="0" caption="No Reset and Voltage level OK during write/erase" value="0"/>
+        <value name="1" caption="A reset or Low Voltage Detected (possible data corruption, verify data)" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__WRERR">
+        <value name="0" caption="The Write/Erase sequence completed normally" value="0"/>
+        <value name="1" caption="The Write/Erase sequence did not complete successfully" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__DONE">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__KEYERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__CFGERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__FIFOERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__BUSERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__WPERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__OPERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__HTDPGM">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__RSTERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__WRERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="STATUS__BUSY">
+        <value name="IDLE" caption="NVM Not Busy" value="0"/>
+        <value name="BUSY" caption="NVM Busy - All SFR bits are not writable" value="1"/>
+      </value-group>
+      <value-group name="STATUS__HTDRDY">
+        <value name="NOTREADY" caption="HTD Not Ready" value="0"/>
+        <value name="READY" caption="HTD Ready" value="1"/>
+      </value-group>
+      <value-group name="KEY__FEATURE">
+        <value name="LOCKALL" caption="No selection, invalid selection, or invalid Key - Locks all SFR protected by KEY register" value="0"/>
+        <value name="WRKEY" caption="WRKEY Value: Unlock SFR bits associated with Write/Erase" value="1"/>
+        <value name="SWAPKEY" caption="SWAPKEY Value: Unlock SFR bits associated with Panel Swapping" value="2"/>
+        <value name="CFGKEY" caption="CFGKEY Value: Unlock SFR bits associated with general Flash configuration" value="4"/>
+      </value-group>
+      <value-group name="SWAP__BFSWAP">
+        <value name="UNSWAP" caption="Upper and Lower BFM Regions are NOT Swapped" value="0"/>
+        <value name="SWAP" caption="Upper and Lower BFM Regions are Swapped" value="1"/>
+      </value-group>
+      <value-group name="SWAP__BFSLOCK">
+        <value name="UNLOCKED" caption="BFSLOCK and BFSWAP can be written" value="0"/>
+        <value name="LOCKED" caption="BFSLOCK and BFSWAP cannot be written" value="1"/>
+      </value-group>
+      <value-group name="SWAP__PFSWAP">
+        <value name="UNSWAP" caption="Upper and Lower PFM Regions are NOT Swapped" value="0"/>
+        <value name="SWAP" caption="Upper and Lower PFM Regions are Swapped" value="1"/>
+      </value-group>
+      <value-group name="SWAP__PFSLOCK">
+        <value name="UNLOCKED" caption="PFSLOCK and PFSWAP can be written" value="0"/>
+        <value name="LOCKED" caption="PFSLOCK and PFSWAP cannot be written" value="1"/>
+      </value-group>
+      <value-group name="PWP__PWPMIR">
+        <value name="UNMIRROR" caption="PWP settings are NOT Mirrored" value="0"/>
+        <value name="MIRROR" caption="PWP settings are Mirrored" value="1"/>
+      </value-group>
+      <value-group name="PWP__PWPLOCK">
+        <value name="UNLOCKED" caption="This register is Not Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="This register is Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="PWP__PWPEN">
+        <value name="DISABLE" caption="PWP is Not Enabled for the defined region" value="0"/>
+        <value name="ENABLE" caption="PWP is Enabled for the defined region" value="1"/>
+      </value-group>
+      <value-group name="LBWP__LBWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Lower Boot Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Lower Boot Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="LBWP__LBWPLOCK">
+        <value name="UNLOCKED" caption="This register is NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="This register is Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="UBWP__UBWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Upper Boot Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Upper Boot Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="UBWP__UBWPLOCK">
+        <value name="UNLOCKED" caption="This register is NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="This register is Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="UOWP__UO1WPR">
+        <value name="DISABLE" caption="Write Protection for User OTP Page 1 Row &quot;n&quot; is Disabled" value="0"/>
+        <value name="ENABLE" caption="Write Protection for User OTP Page 1 Row &quot;n&quot; is Enabled" value="1"/>
+      </value-group>
+      <value-group name="UOWP__UO1WPRLOCK">
+        <value name="UNLOCKED" caption="UO1WPR[n] &amp;amp; UO1WPRLOCK[n] bits are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="UO1WPR[n] &amp;amp; UO1WPRLOCK[n] bits are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1AWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1WP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__RCWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__VSSWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__TWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enable" value="1"/>
+      </value-group>
+      <value-group name="CWP__COWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1AWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1WPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__RCWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__VSSWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__TWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__COWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+    </module>
+    <module name="FPB" id="SYSTEM_IP" version="1.0.0" caption="Flash Patch and Breakpoint">
+      <register-group name="FPB" caption="Flash Patch and Breakpoint">
+        <register name="FP_CTRL" offset="0x0" rw="RW" size="4" access-size="4" caption="Flash Patch Control Register">
+          <bitfield name="ENABLE" caption="Flash Patch global enable" mask="0x1"/>
+          <bitfield name="KEY" caption="FP_CTRL write-enable key" mask="0x2"/>
+          <bitfield name="NUM_CODE" caption="Number of implemented code comparators bits [3:0]" mask="0xF0"/>
+          <bitfield name="NUM_LIT" caption="Number of literal comparators" mask="0xF00"/>
+          <bitfield name="NUM_CODE_1" caption="Number of implemented code comparators bits [6:4]" mask="0x7000"/>
+          <bitfield name="REV" caption="Revision" mask="0xF0000000"/>
+        </register>
+        <register name="FP_REMAP" offset="0x4" rw="R" size="4" access-size="4" caption="Flash Patch Remap Register">
+          <bitfield name="REMAP" caption="Remap address" mask="0x1FFFFFE0"/>
+          <bitfield name="RMPSPT" caption="Remap supported" mask="0x20000000"/>
+        </register>
+        <register name="FP_COMP" offset="0x8" rw="RW" size="4" access-size="4" count="4" caption="Flash Patch Comparator Register n">
+          <mode name="BREAKPOINT"/>
+          <mode name="DEFAULT"/>
+          <bitfield name="BE" caption="Breakpoint enable" mask="0x1"/>
+          <bitfield modes="DEFAULT" name="FPADDR" caption="Flash Patch address" mask="0x1FFFFFFC"/>
+          <bitfield modes="DEFAULT" name="FE" caption="Flash Patch enable" mask="0x80000000"/>
+          <bitfield modes="BREAKPOINT" name="BPADDR" caption="Breakpoint address" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="FP_LAR" offset="0xFB0" rw="W" size="4" access-size="4" caption="FPB Software Lock Access Register">
+          <bitfield name="KEY" caption="Lock access control" mask="0xFFFFFFFF" values="FP_LAR__KEY"/>
+        </register>
+        <register name="FP_LSR" offset="0xFB4" rw="R" size="4" access-size="4" caption="FPB Software Lock Status Register">
+          <bitfield name="SLI" caption="Software Lock implemented" mask="0x1"/>
+          <bitfield name="SLK" caption="Software Lock status" mask="0x2"/>
+          <bitfield name="nTT" caption="Not thirty-two bit" mask="0x4"/>
+        </register>
+        <register name="FP_DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" initval="0x47701A03" caption="FPB Device Architecture Register">
+          <bitfield name="ARCHPART" caption="Architecture Part" mask="0xFFF"/>
+          <bitfield name="ARCHVER" caption="Architecture Version" mask="0xF000"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF0000"/>
+          <bitfield name="PRESENT" caption="DEVARCH Present" mask="0x100000"/>
+          <bitfield name="ARCHITECT" caption="Architect" mask="0xFFE00000"/>
+        </register>
+        <register name="FP_DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" initval="0x00000000" caption="FPB Device Type Register">
+          <bitfield name="MAJOR" caption="Major type" mask="0xF"/>
+          <bitfield name="SUB" caption="Sub-type" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR4" offset="0xFD0" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 4">
+          <bitfield name="DES_2" caption="JEP106 continuation code" mask="0xF"/>
+          <bitfield name="SIZE" caption="4KB count" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR5" offset="0xFD4" rw="R" size="4" access-size="4" initval="0x00000000" caption="FP Peripheral Identification Register 5"/>
+        <register name="FP_PIDR6" offset="0xFD8" rw="R" size="4" access-size="4" initval="0x00000000" caption="FP Peripheral Identification Register 6"/>
+        <register name="FP_PIDR7" offset="0xFDC" rw="R" size="4" access-size="4" initval="0x00000000" caption="FP Peripheral Identification Register 7"/>
+        <register name="FP_PIDR0" offset="0xFE0" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 0">
+          <bitfield name="PART_0" caption="Part number bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="FP_PIDR1" offset="0xFE4" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 1">
+          <bitfield name="PART_1" caption="Part number bits[11:8]" mask="0xF"/>
+          <bitfield name="DES_0" caption="JEP106 identification code bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR2" offset="0xFE8" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 2">
+          <bitfield name="DES_1" caption="JEP106 identification code bits[6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="JEDEC assignee value is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Component revision" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR3" offset="0xFEC" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 3">
+          <bitfield name="CMOD" caption="Customer Modified" mask="0xF"/>
+          <bitfield name="REVAND" caption="RevAnd" mask="0xF0"/>
+        </register>
+        <register name="FP_CIDR0" offset="0xFF0" rw="R" size="4" access-size="4" initval="0x0000000D" caption="FP Component Identification Register 0">
+          <bitfield name="PRMBL_0" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="FP_CIDR1" offset="0xFF4" rw="R" size="4" access-size="4" initval="0x00000090" caption="FP Component Identification Register 1">
+          <bitfield name="PRMBL_1" caption="CoreSight component identification preamble" mask="0xF"/>
+          <bitfield name="CLASS" caption="CoreSight component class" mask="0xF0"/>
+        </register>
+        <register name="FP_CIDR2" offset="0xFF8" rw="R" size="4" access-size="4" initval="0x00000005" caption="FP Component Identification Register 2">
+          <bitfield name="PRMBL_2" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="FP_CIDR3" offset="0xFFC" rw="R" size="4" access-size="4" initval="0x000000B1" caption="FP Component Identification Register 3">
+          <bitfield name="PRMBL_3" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="FP_LAR__KEY">
+        <value name="UNLOCK" caption="Unlock key value" value="0xC5ACCE55"/>
+      </value-group>
+    </module>
+    <module name="FREQM" id="03707" name2="clk_freqm_u2257_v3" version="3a0" caption="Frequency Meter">
+      <register-group name="FREQM" caption="Frequency Meter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x80" caption="Control A Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run In Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B Register">
+          <bitfield name="START" caption="Start Measurement" mask="0x1"/>
+        </register>
+        <register name="CFGA" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Config A Register">
+          <bitfield name="REFNUM" caption="Number of Reference Clock Cycles" mask="0xFF"/>
+          <bitfield name="MSRSEL" caption="Measurement Clock Selection" mask="0x700" values="CFGA__MSRSEL"/>
+          <bitfield name="DIVREF" caption="Divide Reference Clock" mask="0x8000" values="CFGA__DIVREF"/>
+        </register>
+        <register name="CTRLC" offset="0x4" rw="RW" size="1" initval="0x00" caption="Control C Register">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="CTRLC__WINMODE"/>
+        </register>
+        <register name="EVCTRL" offset="0x6" rw="RW" size="1" initval="0x00" caption="Event Control Register">
+          <bitfield name="STARTEI" caption="Start Measurement Event Input Enable" mask="0x1"/>
+          <bitfield name="STARTINV" caption="Start Measurement Event Invert Enable" mask="0x2"/>
+          <bitfield name="DONEEO" caption="Measurement Done Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear Register">
+          <bitfield name="DONE" caption="Measurement Done Interrupt Disable" mask="0x1"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Disable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set Register">
+          <bitfield name="DONE" caption="Measurement Done Interrupt Enable" mask="0x1"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0xA" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Register">
+          <bitfield name="DONE" caption="Measurement Done" mask="0x1"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0xB" rw="RW" size="1" initval="0x00" caption="Status Register">
+          <bitfield name="BUSY" caption="FREQM Status" mask="0x1"/>
+          <bitfield name="OVF" caption="Sticky Count Value Overflow" mask="0x2"/>
+        </register>
+        <register name="SYNCBUSY" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="VALUE" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Count Value Register">
+          <bitfield name="VALUE" caption="Measurement Value" mask="0xFFFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="CFGA__MSRSEL">
+        <value name="GCLK" caption="GCLK Input Clock" value="0x0"/>
+        <value name="CPU" caption="CPU Input Clock" value="0x1"/>
+      </value-group>
+      <value-group name="CFGA__DIVREF">
+        <value name="DIV1" caption="The reference clock is divided by 1" value="0x0"/>
+        <value name="DIV8" caption="The reference clock is divided by 8" value="0x1"/>
+      </value-group>
+      <value-group name="CTRLC__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="VALUE &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="VALUE &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="WINLT &lt; VALUE &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="!(WINLT &lt; VALUE &lt; WINUT)" value="0x4"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="fuses" name2="fuses" version="1a0" caption="Defines FUSES module data">
+      <register-group name="FUSES_ROMCFG" caption="Defines FUSES module data">
+        <register name="DAL" offset="0x0" rw="RW" size="4" caption="DEVICE ACCESS LEVEL Register">
+          <bitfield name="DAL_CPU" caption="CPU Device Access Level" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FRCFGBROM" offset="0x400" rw="RW" size="4" caption="PRE-BOOT bromc user Options Register">
+          <bitfield name="BCRCDIS" caption="Boot ROM CRC Disable" mask="0x1"/>
+        </register>
+        <register name="FRCFGMBIST" offset="0x408" rw="RW" size="4" caption="PRE-BOOT MBIST user Options Register">
+          <bitfield name="MOBH" caption="MBIST On Boot Enable for HIBERNATE Only Retaining Memory Groups" mask="0xC" values="FRCFGMBIST__MOBH"/>
+          <bitfield name="MOBB" caption="MBIST On Boot Enable for BACKUP/HIBERNATE Retaining Memory Groups" mask="0x30" values="FRCFGMBIST__MOBB"/>
+</register>
+            <register name="KEYVAL_INTCHK0" offset="0x420" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK1" offset="0x424" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK2" offset="0x428" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK3" offset="0x42C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK4" offset="0x430" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK5" offset="0x434" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK6" offset="0x438" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK7" offset="0x43C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL0" offset="0x440" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL1" offset="0x444" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL2" offset="0x448" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL3" offset="0x44C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL4" offset="0x450" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL5" offset="0x454" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL6" offset="0x458" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL7" offset="0x45C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR0" offset="0x460" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR1" offset="0x464" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR2" offset="0x468" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR3" offset="0x46C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR4" offset="0x470" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR5" offset="0x474" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR6" offset="0x478" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR7" offset="0x47C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S0" offset="0x480" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S1" offset="0x484" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S2" offset="0x488" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S3" offset="0x48C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S4" offset="0x490" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S5" offset="0x494" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S6" offset="0x498" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S7" offset="0x49C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR0" offset="0x4A0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR1" offset="0x4A4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR2" offset="0x4A8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR3" offset="0x4AC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR4" offset="0x4B0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR5" offset="0x4B4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR6" offset="0x4B8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR7" offset="0x4BC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS0" offset="0x4C0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS1" offset="0x4C4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS2" offset="0x4C8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS3" offset="0x4CC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS4" offset="0x4D0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS5" offset="0x4D4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS6" offset="0x4D8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS7" offset="0x4DC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG0" offset="0x4E0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG1" offset="0x4E4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG2" offset="0x4E8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG3" offset="0x4EC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG4" offset="0x4F0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG5" offset="0x4F4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG6" offset="0x4F8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG7" offset="0x4FC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_0" offset="0x500" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_1" offset="0x504" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_2" offset="0x508" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_3" offset="0x50C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_4" offset="0x510" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_5" offset="0x514" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_6" offset="0x518" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_7" offset="0x51C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_0" offset="0x520" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_1" offset="0x524" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_2" offset="0x528" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_3" offset="0x52C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_4" offset="0x530" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_5" offset="0x534" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_6" offset="0x538" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_7" offset="0x53C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL0" offset="0x540" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL1" offset="0x544" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL2" offset="0x548" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL3" offset="0x54C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL4" offset="0x550" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL5" offset="0x554" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL6" offset="0x558" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL7" offset="0x55C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="PUF_AC" offset="0xC00" rw="RW" size="4" count="249" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="PUF_AC" caption="" mask="0xFFFFFFFF"/>
+            </register>
+        </register-group>
+        <register-group name="FUSES_BOOTCFG1" caption="Defines FUSES module data">
+            <register name="DEVSIGN" offset="0xC" rw="RW" size="4" initval="0xFFFFFFFF" caption="DEVSIGN">
+            <bitfield name="SEQ" caption="Sequence number" mask="0x0000FFFF"/>
+            <bitfield name="SEQBAR" caption="Sequence number BAR" mask="0xFFFF0000"/>
+            </register>
+            <register name="BOOT_FLAG" offset="0x800" rw="RW" size="4" initval="0xFFFFFFF9" caption="BOOT CODE FLAGS REGISTER">
+            <bitfield name="PUFRETRY" caption="PUF Retry" mask="0x2"/>
+            <bitfield name="PUFSTARTUP" caption="PUF Start Up Mode" mask="0x4"/>
+            <bitfield name="DICEDIS" caption="Device Identifier Composition Engine Disable" mask="0x8"/>
+            <bitfield name="BOOTMODE" caption="Boot Mode" mask="0x10"/>
+            <bitfield name="RAM_INIT_ENB" caption="RAM ECC Enable" mask="0x40"/>
+            <bitfield name="PUFSCORE" caption="PUF Score Value" mask="0x700" values="BOOT_FLAG__PUFSCORE"/>
+            </register>
+            <register name="DICE_CDI_INDEX" offset="0x810" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="DICE_CDI_INDEX" caption="" mask="0x7F"/>
+            </register>
+            <register name="DICE_FW_HASH_INDEX" offset="0x814" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="DICE_FW_HASH_INDEX" caption="" mask="0x7F"/>
+            </register>
+            <register name="BOOT_GPIOSEL" offset="0x818" rw="RW" size="4" initval="0xFFFFFFFF" caption="BOOT EXTERNAL NOTIFICATION IO PIN REGISTER">
+            <bitfield name="GPIOPINSEL" caption="Selects IO Port Pin for Boot External Notification Signal" mask="0x1F"/>
+            <bitfield name="GPIOPORTSEL" caption="Selects IO Port for Boot External Notification Signal" mask="0x1E0"/>
+            <bitfield name="FLTPOL" caption="Selects IO Port for Boot External Notification Signal" mask="0x200"/>
+            <bitfield name="FLTODRAIN" caption="Open Drain Control for Boot External Notification Signal" mask="0x800"/>
+            <bitfield name="FLTSLEWLIM" caption="Selects Driver Slew Rate Selection for Boot External Notification Signal" mask="0x3000"/>
+            </register>
+            <register name="H2PB0_NONSECCLRA" offset="0x81C" rw="RW" size="4" initval="0xFFFFFFFE" caption="Non-Security Clear Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="H2PB0_NONSECSETA" offset="0x820" rw="RW" size="4" initval="0x00000001" caption="Non-Security SET Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="PAC_WRCTRL_H2PB0" offset="0x830" rw="RW" size="4" initval="0x00000013" caption="Write Control Register">
+            <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+            <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="PAC_WRCTRL_H2PB0__KEY"/>
+            </register>
+            <register name="H2PB1_NONSECCLRA" offset="0x834" rw="RW" size="4" initval="0xFFFFFFFF" caption="Non-Security Clear Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="H2PB1_NONSECSETA" offset="0x838" rw="RW" size="4" initval="0x00000000" caption="Non-Security SET Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="PAC_WRCTRL_H2PB1" offset="0x848" rw="RW" size="4" initval="0x0000002E" caption="Write Control Register">
+            <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+            <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="PAC_WRCTRL_H2PB1__KEY"/>
+            </register>
+            <register name="H2PB2_NONSECCLRA" offset="0x84C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Non-Security Clear Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="H2PB2_NONSECSETA" offset="0x850" rw="RW" size="4" initval="0x00000000" caption="Non-Security SET Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="PAC_WRCTRL_H2PB2" offset="0x860" rw="RW" size="4" initval="0x0000002F" caption="Write Control Register">
+            <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+            <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="PAC_WRCTRL_H2PB2__KEY"/>
+            </register>
+            <register name="IDAU_RCTRL_BFM" offset="0x864" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control BFM Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control BFM Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control BFM Command" mask="0xFF000000" values="IDAU_RCTRL_BFM_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control BFM Command" mask="0xFF000000" values="IDAU_RCTRL_BFM_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_RCTRL_PFMANS" offset="0x868" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control PFMANS Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control PFMAN Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control PFMAN Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANS_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control PFMAN Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANS_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_RCTRL_PFMANSC" offset="0x86C" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control PFMANSC Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control PFMANSC Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control PFMANSC Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANSC_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control PFMANSC Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANSC_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_RCTRL_DRM" offset="0x870" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control DRM Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control DRM Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control DRM Command" mask="0xFF000000" values="IDAU_RCTRL_DRM_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control DRM Command" mask="0xFF000000" values="IDAU_RCTRL_DRM_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_CTRL_EN" offset="0x874" rw="RW" size="4" initval="0xA5010000" caption="Control">
+            <bitfield name="CMD" caption="IDAU Enable Command Register" mask="0xFFFF0000" values="IDAU_CTRL_EN__CMD"/>
+            </register>
+            <register name="IDAU_CTRL_WLCK" offset="0x878" rw="RW" size="4" initval="0xFFFFFFFF" caption="Control">
+            <bitfield name="CMD" caption="IDAU Write Lock Command Register" mask="0xFFFF0000" values="IDAU_CTRL_WLCK__CMD"/>
+            </register>
+            <register name="FCW_CWP" offset="0x87C" rw="RW" size="4" initval="0x00000000" caption="CFM Page Write Protect REGISTER">
+            <bitfield name="BC1AWP" caption="Panel 1 Write Protect BootCfg1A" mask="0x1" values="FCW_CWP__BC1AWP"/>
+            <bitfield name="BC1WP" caption="Panel 1 Write Protect BootCfg1" mask="0x4" values="FCW_CWP__BC1WP"/>
+            <bitfield name="RCWP" caption="Panel 1 Write Protect ROMCfg" mask="0x8" values="FCW_CWP__RCWP"/>
+            <bitfield name="VSSWP0" caption="Panel 1 Write Protect VSSn" mask="0x10" values="FCW_CWP__VSSWP"/>
+            <bitfield name="VSSWP1" caption="Panel 1 Write Protect VSSn" mask="0x20" values="FCW_CWP__VSSWP"/>
+            <bitfield name="BC1AWPLOCK" caption="Panel 1 Lock Write Protection BootCfg1A" mask="0x10000" values="FCW_CWP__BC1AWPLOCK"/>
+            <bitfield name="BC1WPLOCK" caption="Panel 1 Lock Write Protection BootCfg1" mask="0x40000" values="FCW_CWP__BC1WPLOCK"/>
+            <bitfield name="RCWPLOCK" caption="Panel 1 Lock Write Protection ROMCfg" mask="0x80000" values="FCW_CWP__RCWPLOCK"/>
+            <bitfield name="VSSWPLOCK0" caption="Panel 1 Lock Write Protection VSSn" mask="0x100000" values="FCW_CWP__VSSWPLOCK"/>
+            <bitfield name="VSSWPLOCK1" caption="Panel 1 Lock Write Protection VSSn" mask="0x200000" values="FCW_CWP__VSSWPLOCK"/>
+            </register>
+            <register name="FCR_CRP" offset="0x880" rw="RW" size="4" initval="0x00000000" caption="CFM Page Read Protection Register">
+            <bitfield name="BC1ARP" caption="Panel 1 Read Protect BootCfg1A" mask="0x1" values="FCR_CRP__BC1ARP"/>
+            <bitfield name="BC1RP" caption="Panel 1 Read Protect BootCfg1" mask="0x4" values="FCR_CRP__BC1RP"/>
+            <bitfield name="RCRP" caption="Panel 1 Read Protect ROMCfg" mask="0x8" values="FCR_CRP__RCRP"/>
+            <bitfield name="VSSRP0" caption="Panel 1 Read Protect VSSn" mask="0x10" values="FCR_CRP__VSSRP"/>
+            <bitfield name="VSSRP1" caption="Panel 1 Read Protect VSSn" mask="0x20" values="FCR_CRP__VSSRP"/>
+            <bitfield name="BC1ARPLOCK" caption="Panel 1 Lock Read Protection BootCfg1A" mask="0x10000" values="FCR_CRP__BC1ARPLOCK"/>
+            <bitfield name="BC1RPLOCK" caption="Panel 1 Lock Read Protection BootCfg1" mask="0x40000" values="FCR_CRP__BC1RPLOCK"/>
+            <bitfield name="RCRPLOCK" caption="Panel 1 Lock Read Protection ROMCfg" mask="0x80000" values="FCR_CRP__RCRPLOCK"/>
+            <bitfield name="VSSRPLOCK0" caption="Panel 1 Lock Read Protection VSSn" mask="0x100000" values="FCR_CRP__VSSRPLOCK"/>
+            <bitfield name="VSSRPLOCK1" caption="Panel 1 Lock Read Protection VSSn" mask="0x200000" values="FCR_CRP__VSSRPLOCK"/>
+            </register>
+            <register name="FCR_ECCCTRL" offset="0x884" rw="RW" size="4" initval="0x00000070" caption="ECC Control REGISTER">
+            <bitfield name="ECCCTL" caption="NVM ECC Mode Control - restricts one or more NVMOPs" mask="0x30" values="FCR_ECCCTRL__ECCCTL"/>
+            <bitfield name="ECCUNLCK" caption="NVM ECC Mode Control Unlock" mask="0x40" values="FCR_ECCCTRL__ECCUNLCK"/>
+            <bitfield name="SECCNT" caption="Flash SEC Count" mask="0xFF00"/>
+            </register>
+            <register name="SUPC_BRCFGUSMOR_BOR" offset="0x888" rw="RW" size="4" initval="0x00000000" caption="Boot Rom Configurable SMOR User CFG BOR register">
+            <bitfield name="HYST_BOR_VDDIO" caption="Refer to pwr_smor_[nn]_v2 DOS document for details." mask="0x1" values="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDIO"/>
+            <bitfield name="BOR_TRIP_VDDIO" caption="Nominal BOR Trip, Refer to pwr_smor_[nn]_v2 DOS document for details." mask="0x6" values="SUPC_BRCFGUSMOR_BOR__BOR_TRIP_VDDIO"/>
+            <bitfield name="HYST_BOR_VDDREG" caption="Refer to pwr_smor_[nn]_v2 DOS document for details." mask="0x400" values="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDREG"/>
+            </register>
+            <register name="SUPC_BRCFGUDSSMOR" offset="0x890" rw="RW" size="4" initval="0x00000000" caption="Boot Rom Configurable DSSMOR User CFG register">
+            <bitfield name="BOR_HYST" caption="Refer to pwr_smor_ds_[nn]_v2 DOS document for details." mask="0x1" values="SUPC_BRCFGUDSSMOR__BOR_HYST"/>
+            <bitfield name="BOR_TRIP" caption="Nominal BOR Trip, Refer to pwr_smor_ds_[nn]_v2 DOS document for details." mask="0x6" values="SUPC_BRCFGUDSSMOR__BOR_TRIP"/>
+            </register>
+            <register name="SUPC_BRCFGUCP0" offset="0x894" rw="RW" size="4" initval="0x00000001" caption="Boot Rom Configurable CHARGE PUMP User CFG register">
+            <bitfield name="CP" caption="Refer to vreg_chrg_pump_v4 DOS document for details." mask="0xF" values="SUPC_BRCFGUCP0__CP"/>
+            </register>
+            <register name="WDT_SETUP" offset="0x898" rw="RW" size="4" initval="0x00000000" caption="">
+            <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+            <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+            <bitfield name="RUNSTDBY" caption="Run During Standby" mask="0x40"/>
+            <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+            <bitfield name="PER" caption="Time-Out Period" mask="0xF00" values="WDT_SETUP__PER"/>
+            <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF000" values="WDT_SETUP__WINDOW"/>
+            <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF0000" values="WDT_SETUP__EWOFFSET"/>        </register>
+      </register-group>
+      <register-group name="FUSES_CALOTP" caption="Defines FUSES module data">
+        <register name="F1RR" offset="0x0" rw="R" size="4" caption="PANEL 0 REDUNDANCY RECORD 1-0 Register">
+          <bitfield name="RR0ADDR" caption="Redundancy Replaced Page Address" mask="0x7F"/>
+          <bitfield name="RR0DIS" caption="Redundancy Record 0 enabled" mask="0x8000" values="F1RR__RR0DIS"/>
+          <bitfield name="RR1ADDR" caption="Redundancy Replaced Page Address" mask="0x7F0000"/>
+          <bitfield name="RR1DIS" caption="Redundancy Record 1 enabled" mask="0x80000000" values="F1RR__RR1DIS"/>
+        </register>
+        <register name="FCCFG0" offset="0x80" rw="R" size="4" caption="Calibration Configuration 0 Register">
+          <bitfield name="CFG_SMOR0" caption="SMOR configuration bits" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG1" offset="0x84" rw="R" size="4" caption="Calibration Configuration 1 Register">
+          <bitfield name="CFG_SMOR1" caption="SMOR configuration bits" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG8" offset="0xA0" rw="R" size="4" caption="Calibration Configuration 8 Register">
+          <bitfield name="CFG_DS_SMOR_REF" caption="DSSMOR configuration bits" mask="0xFFFF"/>
+          <bitfield name="CFG_DS_SMOR_CLK" caption="DSSMOR configuration bits" mask="0xFFFF0000"/>
+        </register>
+        <register name="FCCFG16" offset="0xC0" rw="R" size="4" caption="Calibration Configuration 16 Register">
+          <bitfield name="CFG_DFLL48M" caption="Comparator configuration bits" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG17" offset="0xC4" rw="R" size="4" caption="Calibration Configuration 17 Register">
+          <bitfield name="CFG_XTAL_HF" caption="Crystal Oscillator calibration configuration bits" mask="0xFFFF"/>
+        </register>
+        <register name="FCCFG24" offset="0xE0" rw="R" size="4" caption="Calibration Configuration 24 Register">
+          <bitfield name="CFG_CALVREGSW0" caption="99 ma VREG Calibration configuration bits" mask="0xFFFF"/>
+        </register>
+        <register name="FCCFG27" offset="0xEC" rw="R" size="4" caption="Calibration Configuration 27 Register">
+          <bitfield name="CFG_CALVREGRAM" caption="50 ma VREG Calibration configuration bits" mask="0xFFFF0000"/>
+        </register>
+        <register name="FCCFG28" offset="0xF0" rw="R" size="4" caption="Calibration Configuration 28 Register">
+          <bitfield name="CALCP" caption="Charge Pump Calibration  configuration bits for all charge pumps" mask="0xF"/>
+          <bitfield name="CALSUPC" caption="RPMU / SUPC configuration bits" mask="0xFF00"/>
+        </register>
+        <register name="FCCFG29" offset="0xF4" rw="R" size="4" caption="Calibration Configuration 29 Register">
+          <bitfield name="CALUSERLDO" caption="User LDO Calibration  configuration bits" mask="0xFF"/>
+        </register>
+        <register name="FCCFG32" offset="0x100" rw="R" size="4" caption="DSU Device Configuration 0 Register (DEVID)">
+          <bitfield name="PFM_SZ" caption="Program Flash Memory (PFM) Size on Device" mask="0xF" values="FCCFG32__PFM_SZ"/>
+          <bitfield name="DRM_SZ" caption="Data Ram Memory (DRM) Size on Device" mask="0xFF00" values="FCCFG32__DRM_SZ"/>
+          <bitfield name="FPACKAGE" caption="Number of Pins present on the Package" mask="0xF0000" values="FCCFG32__FPACKAGE"/>
+          <bitfield name="DEVSEL" caption="Device Variant Configuration" mask="0xFF000000"/>
+        </register>
+        <register name="FCCFG33" offset="0x104" rw="R" size="4" caption="DSU Device Configuration 1 Register">
+          <bitfield name="ME_HSM" caption="Module enables for Variant configuration" mask="0x80" values="FCCFG33__ME_HSM"/>
+          <bitfield name="ME_TCC0" caption="Module enables for Variant configuration" mask="0x100" values="FCCFG33__ME_TCC0"/>
+          <bitfield name="ME_TCC1" caption="Module enables for Variant configuration" mask="0x200" values="FCCFG33__ME_TCC1"/>
+          <bitfield name="ME_TCC2" caption="Module enables for Variant configuration" mask="0x400" values="FCCFG33__ME_TCC2"/>
+          <bitfield name="ME_TCC3" caption="Module enables for Variant configuration" mask="0x800" values="FCCFG33__ME_TCC3"/>
+          <bitfield name="ME_TCC4" caption="Module enables for Variant configuration" mask="0x1000" values="FCCFG33__ME_TCC4"/>
+          <bitfield name="ME_TCC5" caption="Module enables for Variant configuration" mask="0x2000" values="FCCFG33__ME_TCC5"/>
+          <bitfield name="ME_TCC6" caption="Module enables for Variant configuration" mask="0x4000" values="FCCFG33__ME_TCC6"/>
+          <bitfield name="ME_SERCOM0" caption="Module enables for Variant configuration" mask="0x40000" values="FCCFG33__ME_SERCOM0"/>
+          <bitfield name="ME_SERCOM1" caption="Module enables for Variant configuration" mask="0x80000" values="FCCFG33__ME_SERCOM1"/>
+          <bitfield name="ME_SERCOM2" caption="Module enables for Variant configuration" mask="0x100000" values="FCCFG33__ME_SERCOM2"/>
+          <bitfield name="ME_SERCOM3" caption="Module enables for Variant configuration" mask="0x200000" values="FCCFG33__ME_SERCOM3"/>
+          <bitfield name="ME_SERCOM4" caption="Module enables for Variant configuration" mask="0x400000" values="FCCFG33__ME_SERCOM4"/>
+          <bitfield name="ME_SERCOM5" caption="Module enables for Variant configuration" mask="0x800000" values="FCCFG33__ME_SERCOM5"/>
+          <bitfield name="ME_PTC" caption="Module enables for Variant configuration" mask="0x10000000" values="FCCFG33__ME_PTC"/>
+        </register>
+        <register name="FCCFG34" offset="0x108" rw="R" size="4" caption="DSU Device Configuration 2 Register">
+          <bitfield name="ME_CAN0" caption="Module enables for Variant configuration" mask="0x1" values="FCCFG34__ME_CAN0"/>
+          <bitfield name="ME_CAN1" caption="Module enables for Variant configuration" mask="0x2" values="FCCFG34__ME_CAN1"/>
+          <bitfield name="ME_USBFS" caption="Module enables for Variant configuration" mask="0x200" values="FCCFG34__ME_USBFS"/>
+          <bitfield name="ME_DPA" caption="Module enables for Variant configuration" mask="0x800000" values="FCCFG34__ME_DPA"/>
+          <bitfield name="ME_TRAM" caption="Module enables for Variant configuration" mask="0x40000000" values="FCCFG34__ME_TRAM"/>
+          <bitfield name="ME_PUF" caption="Module enables for Variant configuration" mask="0x80000000" values="FCCFG34__ME_PUF"/>
+        </register>
+        <register name="FCCFG49" offset="0x144" rw="R" size="4" caption="Calibration Configuration 49 Register">
+          <bitfield name="RAMC_EMAW" caption="Write Time Extra Margin Adjust" mask="0x3" values="FCCFG49__RAMC_EMAW"/>
+          <bitfield name="RAMC_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x1C" values="FCCFG49__RAMC_EMA"/>
+          <bitfield name="RAMAB_EMAW" caption="Write Time Extra Margin Adjust" mask="0xC0"/>
+          <bitfield name="RAMAB_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x700"/>
+          <bitfield name="TRAM_EMAW" caption="Write Time Extra Margin Adjust" mask="0x3000"/>
+          <bitfield name="TRAM_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x1C000"/>
+          <bitfield name="TRAM_EMAS" caption="Sense Amp Extra Margin Adjust" mask="0x20000" values="FCCFG49__TRAM_EMAS"/>
+          <bitfield name="BROM_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x700000"/>
+          <bitfield name="PUF_EMAW" caption="Write Time Extra Margin Adjust" mask="0x3000000"/>
+          <bitfield name="PUF_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x1C000000"/>
+          <bitfield name="PUF_EMAS" caption="Sense Amp Extra Margin Adjust" mask="0x20000000" values="FCCFG49__PUF_EMAS"/>
+        </register>
+        <register name="FCCFG56" offset="0x160" rw="R" size="4" caption="Calibration Configuration 56 Register">
+          <bitfield name="BRINGOSC" caption="SUPC Ring-osc depth" mask="0x3" values="FCCFG56__BRINGOSC"/>
+          <bitfield name="DIS_BOR12_RAMON" caption="Disable BOR12 (VREGRAM comparator) when RAM are turned ON when leaving sleep mode" mask="0x10"/>
+          <bitfield name="DIS_BOR12_VSCALING" caption="Disable BOR12 (VREGRAM comparator) when down voltage scaling is on going from 1.2v to 0.8v to workaround VREG undershoot issue" mask="0x20"/>
+          <bitfield name="VLP2FPST" caption="Vreg Low Power to Full Power Stabilization Time" mask="0x30000" values="FCCFG56__VLP2FPST"/>
+          <bitfield name="VLPMST" caption="Vreg LP Mode Stabilization Time" mask="0xC0000" values="FCCFG56__VLPMST"/>
+          <bitfield name="VTONST" caption="Vreg Turned On Stabilization Time" mask="0x300000" values="FCCFG56__VTONST"/>
+          <bitfield name="VPDDST" caption="Vreg Pull Down Disable Stabilization Time" mask="0xC00000" values="FCCFG56__VPDDST"/>
+          <bitfield name="VDVSST" caption="Vreg Down Voltage Scaling Stabilization Time" mask="0x3000000" values="FCCFG56__VDVSST"/>
+        </register>
+        <register name="FCCFG57" offset="0x164" rw="R" size="4" caption="Calibration Configuration 57 Register">
+          <bitfield name="DLYVAL" caption="Delay Value" mask="0x7F"/>
+          <bitfield name="IGNACK" caption="Ignore Acknowledge" mask="0x80" values="FCCFG57__IGNACK"/>
+        </register>
+        <register name="FCCFG58" offset="0x168" rw="R" size="4" caption="Calibration Configuration 58 Register">
+          <bitfield name="BRINGOSC" caption="Backup Ring Oscillator Size Depth" mask="0x3" values="FCCFG58__BRINGOSC"/>
+        </register>
+        <register name="FCCFG59" offset="0x16C" rw="R" size="4" caption="Calibration Configuration 59 Register">
+          <bitfield name="IDAU_EN" caption="IDAU Enabled" mask="0x1" values="FCCFG59__IDAU_EN"/>
+        </register>
+        <register name="FCCFG60" offset="0x170" rw="R" size="4" caption="Calibration Configuration 60 Register">
+          <bitfield name="PUFRAMDNTIME" caption="PUF RAM Power Down Delay Time" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG61" offset="0x174" rw="R" size="4" caption="Calibration Configuration 61 Register">
+          <bitfield name="PUFRAMUPTIME" caption="PUF RAM Power Up Delay Time" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG64" offset="0x180" rw="R" size="4" caption="Calibration Configuration 64 Register">
+          <bitfield name="PTC_CALIB_PTC_IBIAS_TRIM" caption="PTC IBIAS TRIM" mask="0x7"/>
+          <bitfield name="PTC_CALIB_PTAT_EN" caption="Enable PTAT current" mask="0x8"/>
+          <bitfield name="PTC_CALIB_EXT_IBIAS_EN" caption="Enable External Bias" mask="0x10"/>
+        </register>
+        <register name="FCCFG65" offset="0x184" rw="R" size="4" caption="Calibration Configuration 65 Register">
+          <bitfield name="EN_CMBF" caption="Enable Common Mode Power Cycling" mask="0x1"/>
+          <bitfield name="EN_DITHER" caption="Enable Dithering" mask="0x4"/>
+          <bitfield name="DIS_FAZ" caption="First Auto Zeroing" mask="0x8"/>
+          <bitfield name="DIS_SAZ" caption="Second Auto Zeroing" mask="0x10"/>
+          <bitfield name="DIS_LAZ" caption="Current Auto Zeroing" mask="0x20"/>
+          <bitfield name="EN_RDAC" caption="RDAC Duty Cycle" mask="0x40"/>
+          <bitfield name="DBG_SEL" caption="Enable Test Output" mask="0x80"/>
+          <bitfield name="SEL_DEL" caption="Select Value to comp_out" mask="0x100"/>
+          <bitfield name="T1_DELAY" caption="Programmable delay, selects the delay between regen and latch" mask="0x600"/>
+          <bitfield name="TCLK_DIV" caption="Programmable divider for adc_clk_div. The division ratio is 256, 128, 64,32, and 16 going from MSB to LSB." mask="0xF800"/>
+          <bitfield name="IADC_1" caption="Controls the current consumption for of the whole ADC" mask="0x300000"/>
+          <bitfield name="IADC_2" caption="Controls the current consumption for of the whole ADC." mask="0xC00000"/>
+          <bitfield name="ICMP_1" caption="Controls the bias current for 1 stage of the comparator. This will control the resolution needed by comparator. More current means less time but at expense of gain." mask="0x3000000"/>
+          <bitfield name="ICMP_2" caption="Controls the bias current for 2 stage of the comparator. This will control the resolution needed by comparator. More current means less time but at expense of gain." mask="0xC000000"/>
+          <bitfield name="ICMBF" caption="Controls the bias current for Common mode buffer amplifier (CMBF)" mask="0x30000000"/>
+          <bitfield name="EN_ATEST" caption="Enable analog test signals" mask="0x40000000"/>
+          <bitfield name="EN_EXT_BIAS" caption="Internal switched capacitor bias current allows to make the bias current proportional to conversion frequency." mask="0x80000000"/>
+        </register>
+        <register name="FCCFG66" offset="0x188" rw="R" size="4" caption="Calibration Configuration 66 Register">
+          <bitfield name="AC_CONFIG" caption="Comparator 0 Calibration Configuration bits.'" mask="0xF"/>
+        </register>
+        <register name="FCCFG68" offset="0x190" rw="R" size="4" caption="Calibration Configuration 68 Register">
+          <bitfield name="TRANSP" caption="USB PAD P Driver Configuration bits.'" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB PAD N Driver Configuration bits.'" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB PAD Rise/Fall Configuration bits.'" mask="0x7000"/>
+        </register>
+      </register-group>
+      <value-group name="FRCFGMBIST__MOBH">
+        <value name="ENABLED_ANY" caption="MOB runs after any non-BACKUP/HIBERNATE exit reset" value="1"/>
+        <value name="ENABLED_POR" caption="MOB runs only after a POR" value="2"/>
+        <value name="DISABLED" caption="MOB Disabled" value="3"/>
+</value-group>
+        <value-group name="BOOT_FLAG__PUFSCORE">
+            <value name="0" caption="0" value="0"/>
+            <value name="1" caption="1" value="1"/>
+            <value name="2" caption="2" value="2"/>
+            <value name="3" caption="3" value="3"/>
+            <value name="4" caption="4" value="4"/>
+            <value name="5" caption="5" value="5"/>
+            <value name="6" caption="6" value="6"/>
+            <value name="7" caption="7" value="7"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB0__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB1__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB2__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_EN__CMD">
+            <value name="ENABLE" caption="Module Enable" value="0xA501"/>
+            <value name="DISABLE" caption="Module Disable" value="0xA502"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_WLCK__CMD">
+            <value name="WLCK" caption="Write Lock" value="0xA503"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCCTL">
+            <value name="STRICT" caption="ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)" value="0"/>
+            <value name="DYNAMIC" caption="Dynamic Writes with Dynamic Reads" value="1"/>
+            <value name="ECC" caption="ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)" value="2"/>
+            <value name="DISABLE" caption="Dynamic Writes with No Error Check Reads" value="3"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCUNLCK">
+            <value name="LOCKED" caption="ECCUNLCK and ECCCTL[1:0] cannot be written" value="0"/>
+            <value name="UNLOCKED" caption="ECCUNLCK and ECCCTL[1:0] can be written" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDIO">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__BOR_TRIP_VDDIO">
+            <value name="0" caption="1.68V (default)" value="0"/>
+            <value name="1" caption="2.2V" value="1"/>
+            <value name="2" caption="2.64V" value="2"/>
+            <value name="3" caption="2.93V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDREG">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_HYST">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_TRIP">
+            <value name="0" caption="1.61V (default)" value="0"/>
+            <value name="1" caption="2.12V" value="1"/>
+            <value name="2" caption="2.55V" value="2"/>
+            <value name="3" caption="2.8V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUCP0__CP">
+            <value name="0" caption="Clock gating trip optimized for low output threshold voltage (3.01V)" value="0"/>
+            <value name="1" caption="Clock gating trip optimized for high output threshold voltage (3.2V) (default)" value="1"/>
+        </value-group>
+        <value-group name="WDT_SETUP__PER">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__WINDOW">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__EWOFFSET">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>      </value-group>
+      <value-group name="FRCFGMBIST__MOBB">
+        <value name="ENABLED_ANY" caption="MOB runs after any non-BACKUP/HIBERNATE exit reset" value="1"/>
+        <value name="ENABLED_POR" caption="MOB runs only after a POR" value="2"/>
+        <value name="DISABLED" caption="MOB Disabled" value="3"/>
+</value-group>
+        <value-group name="BOOT_FLAG__PUFSCORE">
+            <value name="0" caption="0" value="0"/>
+            <value name="1" caption="1" value="1"/>
+            <value name="2" caption="2" value="2"/>
+            <value name="3" caption="3" value="3"/>
+            <value name="4" caption="4" value="4"/>
+            <value name="5" caption="5" value="5"/>
+            <value name="6" caption="6" value="6"/>
+            <value name="7" caption="7" value="7"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB0__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB1__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB2__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_EN__CMD">
+            <value name="ENABLE" caption="Module Enable" value="0xA501"/>
+            <value name="DISABLE" caption="Module Disable" value="0xA502"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_WLCK__CMD">
+            <value name="WLCK" caption="Write Lock" value="0xA503"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCCTL">
+            <value name="STRICT" caption="ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)" value="0"/>
+            <value name="DYNAMIC" caption="Dynamic Writes with Dynamic Reads" value="1"/>
+            <value name="ECC" caption="ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)" value="2"/>
+            <value name="DISABLE" caption="Dynamic Writes with No Error Check Reads" value="3"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCUNLCK">
+            <value name="LOCKED" caption="ECCUNLCK and ECCCTL[1:0] cannot be written" value="0"/>
+            <value name="UNLOCKED" caption="ECCUNLCK and ECCCTL[1:0] can be written" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDIO">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__BOR_TRIP_VDDIO">
+            <value name="0" caption="1.68V (default)" value="0"/>
+            <value name="1" caption="2.2V" value="1"/>
+            <value name="2" caption="2.64V" value="2"/>
+            <value name="3" caption="2.93V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDREG">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_HYST">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_TRIP">
+            <value name="0" caption="1.61V (default)" value="0"/>
+            <value name="1" caption="2.12V" value="1"/>
+            <value name="2" caption="2.55V" value="2"/>
+            <value name="3" caption="2.8V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUCP0__CP">
+            <value name="0" caption="Clock gating trip optimized for low output threshold voltage (3.01V)" value="0"/>
+            <value name="1" caption="Clock gating trip optimized for high output threshold voltage (3.2V) (default)" value="1"/>
+        </value-group>
+        <value-group name="WDT_SETUP__PER">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__WINDOW">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__EWOFFSET">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>      </value-group>
+      <value-group name="F1RR__RR0DIS">
+        <value name="0" caption="FCR maps the redundant page 0 into the address defined by RR0ADDR" value="0"/>
+        <value name="1" caption="Redundant page 0 mapping is Disabled" value="1"/>
+      </value-group>
+      <value-group name="F1RR__RR1DIS">
+        <value name="0" caption="FCR maps the redundant page 1 into the address defined by RR1ADDR" value="0"/>
+        <value name="1" caption="Redundant page 1 mapping is Disabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG32__PFM_SZ">
+        <value name="6" caption="512KB" value="6"/>
+      </value-group>
+      <value-group name="FCCFG32__DRM_SZ">
+        <value name="0" caption="Rsvd" value="0"/>
+        <value name="1" caption="128KB" value="1"/>
+      </value-group>
+      <value-group name="FCCFG32__FPACKAGE">
+        <value name="5" caption="48 pins" value="5"/>
+        <value name="6" caption="64 pins" value="6"/>
+        <value name="7" caption="Rsvd" value="7"/>
+        <value name="8" caption="100 pins" value="8"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_HSM">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC0">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC1">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC2">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC3">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC4">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC5">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC6">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM0">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM1">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM2">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM3">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM4">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM5">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_PTC">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_CAN0">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_CAN1">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_USBFS">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_DPA">
+        <value name="0" caption="DPA is Disabled" value="0"/>
+        <value name="1" caption="DPA functions in HSM is Operational" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_TRAM">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_PUF">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG49__RAMC_EMAW">
+        <value name="0" caption="Slowest Access" value="0"/>
+        <value name="1" caption="" value="1"/>
+        <value name="2" caption="" value="2"/>
+        <value name="3" caption="Fastest Access; Default (reset)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG49__RAMC_EMA">
+        <value name="0" caption="" value="0"/>
+        <value name="1" caption="" value="1"/>
+        <value name="2" caption="Slowest Access" value="2"/>
+        <value name="3" caption="" value="3"/>
+        <value name="4" caption="" value="4"/>
+        <value name="5" caption="Fastest Access" value="5"/>
+        <value name="6" caption="" value="6"/>
+        <value name="7" caption="Default (reset)" value="7"/>
+      </value-group>
+      <value-group name="FCCFG49__TRAM_EMAS">
+        <value name="0" caption="Sense Amp Pulse Not Extended" value="0"/>
+        <value name="1" caption="Sense Amp Pulse Extended; Default (reset)" value="1"/>
+      </value-group>
+      <value-group name="FCCFG49__PUF_EMAS">
+        <value name="0" caption="Sense Amp Pulse Not Extended" value="0"/>
+        <value name="1" caption="Sense Amp Pulse Extended; Default (reset)" value="1"/>
+      </value-group>
+      <value-group name="FCCFG56__BRINGOSC">
+        <value name="0" caption="Ring oscillator depth is default (DLY0)" value="0"/>
+        <value name="1" caption="Ring oscillator depth is default + 1 ORDLY15 (DLY1)" value="1"/>
+        <value name="2" caption="Ring oscillator depth is default + 2 ORDLY15 (DLY2)" value="2"/>
+        <value name="3" caption="Ring oscillator depth is default + 3 ORDLY15 (DLY3)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VLP2FPST">
+        <value name="0" caption="5us -32 clock cycles based on 6Mhz clock (5US)" value="0"/>
+        <value name="1" caption="10us -64 clock cycles based on 6Mhz clock (10US)" value="1"/>
+        <value name="2" caption="21us -128 clock cycles based on 6Mhz clock (21US)" value="2"/>
+        <value name="3" caption="1.3us -8 clock cycles based on 6Mhz clock (1US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VLPMST">
+        <value name="0" caption="1.3us -8 clock cycles based on 6Mhz clock (1US)" value="0"/>
+        <value name="1" caption="2.6us -16 clock cycles based on 6Mhz clock (2US)" value="1"/>
+        <value name="2" caption="5us -32 clock cycles based on 6Mhz clock (5US)" value="2"/>
+        <value name="3" caption="0.166us -1 clock cycles based on 6Mhz clock (0US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VTONST">
+        <value name="0" caption="31us -192 clock cycles based on 6Mhz clock (31US)" value="0"/>
+        <value name="1" caption="42us -256 clock cycles based on 6Mhz clock (42US)" value="1"/>
+        <value name="2" caption="84us -512 clock cycles based on 6Mhz clock (84US)" value="2"/>
+        <value name="3" caption="10.6us -64 clock cycles based on 6Mhz clock (10US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VPDDST">
+        <value name="0" caption="21us -128 clock cycles based on 6Mhz clock (21US)" value="0"/>
+        <value name="1" caption="42us -256 clock cycles based on 6Mhz clock (42US)" value="1"/>
+        <value name="2" caption="84us -512 clock cycles based on 6Mhz clock (84US)" value="2"/>
+        <value name="3" caption="10.6us -64 clock cycles based on 6Mhz clock (10US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VDVSST">
+        <value name="0" caption="32us -192 clock cycles based on 6Mhz clock (32US)" value="0"/>
+        <value name="1" caption="42us -256 clock cycles based on 6Mhz clock (42US)" value="1"/>
+        <value name="2" caption="84us -512 clock cycles based on 6Mhz clock (84US)" value="2"/>
+        <value name="3" caption="10us -64 clock cycles based on 6Mhz clock (10US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG57__IGNACK">
+        <value name="0" caption="Power Switch acknowledge signal is taken into account when entering/exiting retention mode. According to the DLYVAL field, a supplementary delay is also added (from 0 to 127 digital ring oscillator period)" value="0"/>
+        <value name="1" caption="Power Switch acknowledge signal is ignored when entering/exiting retention mode, and is replaced by a overflow counter signal clocked on internal digital ring oscillator. The overflow counter is programmable by using the DLYVAL field" value="1"/>
+      </value-group>
+      <value-group name="FCCFG58__BRINGOSC">
+        <value name="0" caption="Ring Oscillator depth is default (DLY0)" value="0"/>
+        <value name="1" caption="Ring Oscillator depth is default + 1 ORDLY15 (DLY1)" value="1"/>
+        <value name="2" caption="Ring Oscillator depth is default + 2 ORDLU15 (DLY2)" value="2"/>
+        <value name="3" caption="Ring Oscillator depth is default + 3 ORDLY15 (DLY3)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG59__IDAU_EN">
+        <value name="0" caption="GC device. All IDAU regions exempt. The boot code will initialize the IDAU, H2PB and PAC as described in Section 2.9.2" value="0"/>
+        <value name="1" caption="IDAU regions enabled. The boot code will initialize the IDAU, H2PB and PAC to the values set by customer and referred to in USERCFG as described in Section 2.9.3" value="1"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="03588" name2="clk_gclk_u2122_v1" version="1d0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x4" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy bit" mask="0x1"/>
+          <bitfield name="GENCTRL0" caption="Generic Clock Generator Control 0 Synchronization Busy bit" mask="0x4"/>
+          <bitfield name="GENCTRL1" caption="Generic Clock Generator Control 1 Synchronization Busy bit" mask="0x8"/>
+          <bitfield name="GENCTRL2" caption="Generic Clock Generator Control 2 Synchronization Busy bit" mask="0x10"/>
+          <bitfield name="GENCTRL3" caption="Generic Clock Generator Control 3 Synchronization Busy bit" mask="0x20"/>
+          <bitfield name="GENCTRL4" caption="Generic Clock Generator Control 4 Synchronization Busy bit" mask="0x40"/>
+          <bitfield name="GENCTRL5" caption="Generic Clock Generator Control 5 Synchronization Busy bit" mask="0x80"/>
+          <bitfield name="GENCTRL6" caption="Generic Clock Generator Control 6 Synchronization Busy bit" mask="0x100"/>
+          <bitfield name="GENCTRL7" caption="Generic Clock Generator Control 7 Synchronization Busy bit" mask="0x200"/>
+          <bitfield name="GENCTRL8" caption="Generic Clock Generator Control 8 Synchronization Busy bit" mask="0x400"/>
+          <bitfield name="GENCTRL9" caption="Generic Clock Generator Control 9 Synchronization Busy bit" mask="0x800"/>
+          <bitfield name="GENCTRL10" caption="Generic Clock Generator Control 10 Synchronization Busy bit" mask="0x1000"/>
+          <bitfield name="GENCTRL11" caption="Generic Clock Generator Control 11 Synchronization Busy bit" mask="0x2000"/>
+        </register>
+        <register name="GENCTRL" offset="0x20" rw="RW" access="WSYNC" size="4" count="12" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="SRC" caption="Source Select" mask="0xF" values="GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x100"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x200"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x400"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x800"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x1000" values="GENCTRL__DIVSEL"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x2000"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF0000"/>
+        </register>
+        <register name="PCHCTRL" offset="0x80" rw="RW" size="4" count="39" initval="0x00000000" caption="Peripheral Clock Control">
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF" values="PCHCTRL__GEN"/>
+          <bitfield name="CHEN" caption="Channel Enable" mask="0x40"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+      </register-group>
+      <value-group name="GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0x00"/>
+        <value name="GCLK_IN" caption="Generator input pad (GCLK_IO)" value="0x01"/>
+        <value name="GCLK_GEN1" caption="Generic clock generator 1 output" value="0x02"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="0x03"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="0x04"/>
+        <value name="DFLL48M" caption="DFLL oscillator output" value="0x05"/>
+        <value name="PLL0_CLKOUT1" caption="PLL 0 port CLKOUT1" value="0x06"/>
+        <value name="PLL0_CLKOUT2" caption="PLL 0 port CLKOUT2" value="0x07"/>
+        <value name="PLL0_CLKOUT3" caption="PLL 0 port CLKOUT3" value="0x08"/>
+        <value name="PLL0_CLKOUT4" caption="PLL 0 port CLKOUT4" value="0x09"/>
+        <value name="PLL0_CLKOUT5" caption="PLL 0 port CLKOUT5" value="0x0A"/>
+      </value-group>
+      <value-group name="GENCTRL__DIVSEL">
+        <value name="DIV1" caption="Divide input directly by divider factor" value="0"/>
+        <value name="DIV2" caption="Divide input by 2^(divider factor+ 1)" value="1"/>
+      </value-group>
+      <value-group name="PCHCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+        <value name="GCLK8" caption="Generic clock generator 8" value="0x8"/>
+        <value name="GCLK9" caption="Generic clock generator 9" value="0x9"/>
+        <value name="GCLK10" caption="Generic clock generator 10" value="0xA"/>
+        <value name="GCLK11" caption="Generic clock generator 11" value="0xB"/>
+      </value-group>
+    </module>
+    <module name="H2PB" id="04947" name2="bus_ahb2apb_v1" version="1a0" caption="AHB To APB Bridge">
+      <register-group name="H2PB" caption="AHB To APB Bridge">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="H2PB CONTROL Register">
+          <bitfield name="PRIV" caption="PRIV privileged access protection bit" mask="0x4"/>
+          <bitfield name="SECEN" caption="SECEN security enable bit" mask="0x8"/>
+        </register>
+        <register name="NONSECCLRA" offset="0x8" rw="RW" size="4" atomic-op="clear:NONSECCLRA" initval="0x00000000" caption="Non-Security Clear Register A">
+          <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+          <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+          <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+          <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+          <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+          <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+          <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+          <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+          <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+          <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+          <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+          <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+          <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+          <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+          <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+          <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+          <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+          <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+          <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+          <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+          <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+          <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+          <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+          <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+          <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+          <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+          <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+          <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+          <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+          <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+          <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+          <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+        </register>
+        <register name="NONSECSETA" offset="0xC" rw="RW" size="4" atomic-op="set:NONSECSETA" initval="0x00000000" caption="Non-Security SET Register A">
+          <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+          <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+          <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+          <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+          <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+          <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+          <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+          <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+          <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+          <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+          <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+          <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+          <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+          <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+          <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+          <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+          <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+          <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+          <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+          <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+          <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+          <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+          <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+          <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+          <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+          <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+          <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+          <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+          <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+          <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+          <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+          <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="HMATRIX2" id="bus_hmatrix2_v5" name2="bus_hmatrix2_v5" version="5f0" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+          <bitfield name="M0PR" caption="Master 0 Priority" mask="0x3"/>
+          <bitfield name="LQOSEN0" caption="Latency Quality Of Service Enable for Master 0" mask="0x4"/>
+          <bitfield name="M1PR" caption="Master 1 Priority" mask="0x30"/>
+          <bitfield name="LQOSEN1" caption="Latency Quality Of Service Enable for Master 1" mask="0x40"/>
+          <bitfield name="M2PR" caption="Master 2 Priority" mask="0x300"/>
+          <bitfield name="LQOSEN2" caption="Latency Quality Of Service Enable for Master 2" mask="0x400"/>
+          <bitfield name="M3PR" caption="Master 3 Priority" mask="0x3000"/>
+          <bitfield name="LQOSEN3" caption="Latency Quality Of Service Enable for Master 3" mask="0x4000"/>
+          <bitfield name="M4PR" caption="Master 4 Priority" mask="0x30000"/>
+          <bitfield name="LQOSEN4" caption="Latency Quality Of Service Enable for Master 4" mask="0x40000"/>
+          <bitfield name="M5PR" caption="Master 5 Priority" mask="0x300000"/>
+          <bitfield name="LQOSEN5" caption="Latency Quality Of Service Enable for Master 5" mask="0x400000"/>
+        </register>
+      </register-group>
+      <register-group name="HMATRIX2" caption="HSB Matrix">
+        <register name="MCFG" offset="0x0" rw="RW" size="4" access-size="4" count="6" initval="0x00000002" caption="Master Configuration">
+          <bitfield name="ULBT" caption="Undefined Length Burst Type" mask="0x7" values="MCFG__ULBT"/>
+        </register>
+        <register name="SCFG" offset="0x40" rw="RW" size="4" access-size="4" count="9" initval="0x00000010" caption="Slave Configuration">
+          <bitfield name="SLOT_CYCLE" caption="Maximum Number of Allowed Cycles for a Burst" mask="0x1FF"/>
+          <bitfield name="DEFMSTR_TYPE" caption="Default Master Type" mask="0x30000" values="SCFG__DEFMSTR_TYPE"/>
+          <bitfield name="FIXED_DEFMSTR" caption="Fixed Index of Default Master" mask="0x3C0000"/>
+        </register>
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" size="0x8" count="9"/>
+        <register name="MRCR" offset="0x100" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Master Remap Control">
+          <bitfield name="RCB0" caption="Remap Command Bit for Master 0" mask="0x1" values="MRCR__RCB"/>
+          <bitfield name="RCB1" caption="Remap Command Bit for Master 1" mask="0x2" values="MRCR__RCB"/>
+          <bitfield name="RCB2" caption="Remap Command Bit for Master 2" mask="0x4" values="MRCR__RCB"/>
+          <bitfield name="RCB3" caption="Remap Command Bit for Master 3" mask="0x8" values="MRCR__RCB"/>
+          <bitfield name="RCB4" caption="Remap Command Bit for Master 4" mask="0x10" values="MRCR__RCB"/>
+          <bitfield name="RCB5" caption="Remap Command Bit for Master 5" mask="0x20" values="MRCR__RCB"/>
+        </register>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="9" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEIER" offset="0x150" rw="W" size="4" access-size="4" atomic-op="set:MEIMR" caption="Master Error Interrupt Enable">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MEIDR" offset="0x154" rw="W" size="4" access-size="4" atomic-op="clear:MEIMR" caption="Master Error Interrupt Disable">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MEIMR" offset="0x158" rw="R" size="4" access-size="4" caption="Master Error Interrupt Mask">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MESR" offset="0x15C" rw="R" size="4" access-size="4" atomic-op="clear:MESR" caption="Master Error Status">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MEAR" offset="0x160" rw="R" size="4" access-size="4" count="6" caption="Master Error Address"/>
+      </register-group>
+      <value-group name="MCFG__ULBT">
+        <value name="INFINITE" caption="Infinite Length" value="0"/>
+        <value name="SINGLE" caption="Single Access" value="1"/>
+        <value name="FOUR_BEAT" caption="Four Beat Burst" value="2"/>
+        <value name="EIGHT_BEAT" caption="Eight Beat Burst" value="3"/>
+        <value name="SIXTEEN_BEAT" caption="Sixteen Beat Burst" value="4"/>
+      </value-group>
+      <value-group name="SCFG__DEFMSTR_TYPE">
+        <value name="NO_DEFAULT" caption="No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst." value="0"/>
+        <value name="LAST_DEFAULT" caption="Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave." value="1"/>
+        <value name="FIXED_DEFAULT" caption="Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave." value="2"/>
+      </value-group>
+      <value-group name="MRCR__RCB">
+        <value name="DIS" caption="Disable remapped address decoding for master" value="0"/>
+        <value name="ENA" caption="Enable remapped address decoding for master" value="1"/>
+      </value-group>
+    </module>
+    <module name="ICB" id="SYSTEM_IP" version="1.0.0" caption="Implementation Control Block">
+      <register-group name="ICB" caption="Implementation Control Block">
+        <register name="ICTR" offset="0x4" rw="R" size="4" access-size="4" caption="Interrupt Controller Type Register">
+          <bitfield name="INTLINESNUM" caption="Interrupt line set number" mask="0xF"/>
+        </register>
+        <register name="ACTLR" offset="0x8" rw="RW" size="4" access-size="4" caption="Auxiliary Control Register"/>
+      </register-group>
+    </module>
+    <module name="MCLK" id="04158" name2="clk_mclk_v1" version="1a0" caption="Polaris Main Clock Controller">
+      <register-group name="MCLK" caption="Polaris Main Clock Controller">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear Register">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable Clear" mask="0x1" values="INTENCLR__CKRDY"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set Register">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable Set" mask="0x1" values="INTENSET__CKRDY"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="W" size="4" atomic-op="clear:INTFLAG" initval="0x00000001" caption="Interrupt Flag Status Register">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Flag" mask="0x1"/>
+        </register>
+        <register name="CLKDIV" offset="0xC" rw="RW" size="4" count="3" initval="0x00000000" caption="Clock Divider Control n Register">
+          <bitfield name="DIV" caption="Clock Domain n Division Factor" mask="0xFF" values="CLKDIV__DIV"/>
+        </register>
+        <register name="CLKMSK" offset="0x3C" rw="RW" size="4" count="9" initval="0x00000000" caption="Peripheral Clock Enable Mask n Register">
+          <bitfield name="MASK0" caption="Peripheral Clock Enable Mask" mask="0x1" values="CLKMSK__MASK"/>
+          <bitfield name="MASK1" caption="Peripheral Clock Enable Mask" mask="0x2" values="CLKMSK__MASK"/>
+          <bitfield name="MASK2" caption="Peripheral Clock Enable Mask" mask="0x4" values="CLKMSK__MASK"/>
+          <bitfield name="MASK3" caption="Peripheral Clock Enable Mask" mask="0x8" values="CLKMSK__MASK"/>
+          <bitfield name="MASK4" caption="Peripheral Clock Enable Mask" mask="0x10" values="CLKMSK__MASK"/>
+          <bitfield name="MASK5" caption="Peripheral Clock Enable Mask" mask="0x20" values="CLKMSK__MASK"/>
+          <bitfield name="MASK6" caption="Peripheral Clock Enable Mask" mask="0x40" values="CLKMSK__MASK"/>
+          <bitfield name="MASK7" caption="Peripheral Clock Enable Mask" mask="0x80" values="CLKMSK__MASK"/>
+          <bitfield name="MASK8" caption="Peripheral Clock Enable Mask" mask="0x100" values="CLKMSK__MASK"/>
+          <bitfield name="MASK9" caption="Peripheral Clock Enable Mask" mask="0x200" values="CLKMSK__MASK"/>
+          <bitfield name="MASK10" caption="Peripheral Clock Enable Mask" mask="0x400" values="CLKMSK__MASK"/>
+          <bitfield name="MASK11" caption="Peripheral Clock Enable Mask" mask="0x800" values="CLKMSK__MASK"/>
+          <bitfield name="MASK12" caption="Peripheral Clock Enable Mask" mask="0x1000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK13" caption="Peripheral Clock Enable Mask" mask="0x2000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK14" caption="Peripheral Clock Enable Mask" mask="0x4000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK15" caption="Peripheral Clock Enable Mask" mask="0x8000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK16" caption="Peripheral Clock Enable Mask" mask="0x10000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK17" caption="Peripheral Clock Enable Mask" mask="0x20000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK18" caption="Peripheral Clock Enable Mask" mask="0x40000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK19" caption="Peripheral Clock Enable Mask" mask="0x80000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK20" caption="Peripheral Clock Enable Mask" mask="0x100000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK21" caption="Peripheral Clock Enable Mask" mask="0x200000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK22" caption="Peripheral Clock Enable Mask" mask="0x400000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK23" caption="Peripheral Clock Enable Mask" mask="0x800000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK24" caption="Peripheral Clock Enable Mask" mask="0x1000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK25" caption="Peripheral Clock Enable Mask" mask="0x2000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK26" caption="Peripheral Clock Enable Mask" mask="0x4000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK27" caption="Peripheral Clock Enable Mask" mask="0x8000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK28" caption="Peripheral Clock Enable Mask" mask="0x10000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK29" caption="Peripheral Clock Enable Mask" mask="0x20000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK30" caption="Peripheral Clock Enable Mask" mask="0x40000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK31" caption="Peripheral Clock Enable Mask" mask="0x80000000" values="CLKMSK__MASK"/>
+        </register>
+      </register-group>
+      <value-group name="INTENCLR__CKRDY">
+        <value name="0" caption="The Clock Ready interrupt is disabled" value="0"/>
+        <value name="1" caption="The Clock Ready interrupt is enabled." value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CKRDY">
+        <value name="0" caption="The Clock Ready interrupt is disabled." value="0"/>
+        <value name="1" caption="The Clock Ready interrupt is enabled." value="1"/>
+      </value-group>
+      <value-group name="CLKDIV__DIV">
+        <value name="DIV1" caption="Divide by 1" value="1"/>
+        <value name="DIV2" caption="Divide by 2" value="2"/>
+        <value name="DIV4" caption="Divide by 4" value="4"/>
+        <value name="DIV8" caption="Divide by 8" value="8"/>
+        <value name="DIV16" caption="Divide by 16" value="16"/>
+        <value name="DIV32" caption="Divide by 32" value="32"/>
+        <value name="DIV64" caption="Divide by 64" value="64"/>
+        <value name="DIV128" caption="Divide by 128" value="128"/>
+      </value-group>
+      <value-group name="CLKMSK__MASK">
+        <value name="0" caption="Peripheral clock mclk_clk_periph[n*32+x] stopped" value="0"/>
+        <value name="1" caption="Peripheral clock mclk_clk_periph[n*32+x] enabled" value="1"/>
+      </value-group>
+    </module>
+    <module name="MCRAMC" id="04921" name2="drm_mcramc_v5" version="5b0" caption="Multi-Channel RAM Controller">
+      <register-group name="MCRAMC" caption="Multi-Channel RAM Controller">
+        <register name="MCRAMC_CTRLA" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000002" caption="Control Enable A Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1" values="MCRAMC_CTRLA__SWRST"/>
+          <bitfield name="ENABLE" caption="ECC Decoder Enable" mask="0x2" values="MCRAMC_CTRLA__ENABLE"/>
+          <bitfield name="PRIV" caption="Priviledged Access Enable" mask="0x4"/>
+          <bitfield name="WS" caption="Wait State Enable" mask="0x100"/>
+        </register>
+        <register name="MCRAMC_INTENCLR" offset="0x8" rw="RW" size="4" access-size="4" atomic-op="clear:MCRAMC_INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear Register">
+          <bitfield name="SERREN" caption="Single Bit Error Interrupt Enable, Clear" mask="0x1"/>
+          <bitfield name="DERREN" caption="Double Bit Error Interrupt Enable, Clear" mask="0x2"/>
+        </register>
+        <register name="MCRAMC_INTENSET" offset="0xC" rw="RW" size="4" access-size="4" atomic-op="set:MCRAMC_INTENSET" initval="0x00000000" caption="Interrupt Enable Set Register">
+          <bitfield name="SERREN" caption="Single Bit Error Interrupt Enable, Set" mask="0x1"/>
+          <bitfield name="DERREN" caption="Double Bit Error Interrupt Enable, Set" mask="0x2"/>
+        </register>
+        <register name="MCRAMC_INTSTA" offset="0x10" rw="RW" size="4" access-size="4" atomic-op="clear:MCRAMC_INTSTA" initval="0x00000000" caption="Interrupt Status Register">
+          <bitfield name="SERR" caption="Single Bit Error" mask="0x1"/>
+          <bitfield name="DERR" caption="Double Bit Error" mask="0x2"/>
+        </register>
+        <register name="MCRAMC_FLTCTRL" offset="0x14" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Fault Injection Control Register">
+          <bitfield name="FLTEN" caption="Fault Injection Enabled" mask="0x2" values="MCRAMC_FLTCTRL__FLTEN"/>
+          <bitfield name="FLTMD" caption="Fault Injection Mode" mask="0x3000"/>
+        </register>
+        <register name="MCRAMC_FLTPTR" offset="0x18" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Fault Injection Pointer Register">
+          <bitfield name="FLT1PTR" caption="Single Fault Injection Bit Pointer" mask="0xFF"/>
+          <bitfield name="FLT2PTR" caption="Double Fault Injection Bit Pointer" mask="0xFF0000"/>
+        </register>
+        <register name="MCRAMC_FLTADR" offset="0x1C" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Fault Injection Address Register">
+          <bitfield name="FLTADR" caption="Fault Address Offset" mask="0xFFFFFF"/>
+        </register>
+        <register name="MCRAMC_ERRCADR" offset="0x20" rw="R" size="4" access-size="4" initval="0x00000000" caption="Error Capture Address Register">
+          <bitfield name="ERCADR" caption="ECC SECDED Error Capture Address" mask="0xFFFFFF"/>
+        </register>
+        <register name="MCRAMC_ERRCPAR" offset="0x24" rw="R" size="4" access-size="4" initval="0x00000000" caption="Error Capture Parity Register">
+          <bitfield name="ERCPAR" caption="ECC SECDED Error Capture Parity" mask="0xFF"/>
+        </register>
+        <register name="MCRAMC_ERRCSYN" offset="0x28" rw="R" size="4" access-size="4" initval="0x00000000" caption="Error Capture Syndrome Register">
+          <bitfield name="ERCSYN" caption="ECC SECDED Error Capture Syndrome" mask="0xFF" values="MCRAMC_ERRCSYN__ERCSYN"/>
+          <bitfield name="ERR1" caption="ECC Single Bit Error" mask="0x4000"/>
+          <bitfield name="ERR2" caption="ECC Double Bit Error" mask="0x8000" values="MCRAMC_ERRCSYN__ERR2"/>
+        </register>
+        <register name="MCRAMC_VERSION" offset="0xFC" rw="R" size="4" access-size="4" initval="0x00000510" caption="Version Register">
+          <bitfield name="VERSION" caption="MCRAMC Version" mask="0xFFF"/>
+          <bitfield name="MFN" caption="Metal Fix Number" mask="0x70000"/>
+        </register>
+      </register-group>
+      <value-group name="MCRAMC_CTRLA__SWRST">
+        <value name="0" caption="No effect." value="0"/>
+        <value name="1" caption="Reset the MCRAMC. A software-triggered hardware reset of the MCRAMC user interface is performed." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_CTRLA__ENABLE">
+        <value name="0" caption="ECC decoding is disabled." value="0"/>
+        <value name="1" caption="ECC decoding is enabled." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_FLTCTRL__FLTEN">
+        <value name="0" caption="Disables fault injection." value="0"/>
+        <value name="1" caption="Enables fault injection at FLTADR address offset as selected by FLTMD and FLTxPTR." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_ERRCSYN__ERCSYN">
+        <value name="0" caption="Not a Single bit error." value="0"/>
+        <value name="1" caption="Single bit error." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_ERRCSYN__ERR2">
+        <value name="0" caption="Not a Double bit error." value="0"/>
+        <value name="1" caption="Double bit error." value="1"/>
+      </value-group>
+    </module>
+    <module name="MPU" id="SYSTEM_IP" version="1.0.0" caption="Memory Protection Unit">
+      <register-group name="MPU" caption="Memory Protection Unit">
+        <register name="MPU_TYPE" offset="0x0" rw="R" size="4" access-size="4" caption="MPU Type Register">
+          <bitfield name="SEPARATE" caption="Separate instructions and data address regions" mask="0x1"/>
+          <bitfield name="DREGION" caption="Number of MPU data regions" mask="0xFF00"/>
+        </register>
+        <register name="MPU_CTRL" offset="0x4" rw="RW" size="4" access-size="4" caption="MPU Control Register">
+          <bitfield name="ENABLE" caption="MPU enable" mask="0x1"/>
+          <bitfield name="HFNMIENA" caption="HardFault, NMI enable" mask="0x2"/>
+          <bitfield name="PRIVDEFENA" caption="Privileged default enable" mask="0x4"/>
+        </register>
+        <register name="MPU_RNR" offset="0x8" rw="RW" size="4" access-size="4" caption="MPU Region Number Register">
+          <bitfield name="REGION" caption="Selected region number" mask="0xFF"/>
+        </register>
+        <register name="MPU_RBAR" offset="0xC" rw="RW" size="4" access-size="4" caption="MPU Region Base Address Register">
+          <bitfield name="XN" caption="Execute Never" mask="0x1"/>
+          <bitfield name="AP" caption="Access permissions" mask="0x6" values="MPU_RBAR__AP"/>
+          <bitfield name="SH" caption="Shareability" mask="0x18" values="MPU_RBAR__SH"/>
+          <bitfield name="BASE" caption="Base address" mask="0xFFFFFFE0"/>
+        </register>
+        <register name="MPU_RLAR" offset="0x10" rw="RW" size="4" access-size="4" caption="MPU Region Limit Address Register">
+          <bitfield name="EN" caption="Region enable" mask="0x1"/>
+          <bitfield name="AttrInd" caption="Attribute Index" mask="0xE"/>
+          <bitfield name="LIMIT" caption="Limit address" mask="0xFFFFFFE0"/>
+        </register>
+        <register name="MPU_MAIR0" offset="0x30" rw="RW" size="4" access-size="4" caption="MPU Memory Attribute Indirection Register 0">
+          <bitfield name="Attr0" caption="Attribute of MPU region 0" mask="0xFF"/>
+          <bitfield name="Attr1" caption="Attribute of MPU region 1" mask="0xFF00"/>
+          <bitfield name="Attr2" caption="Attribute of MPU region 2" mask="0xFF0000"/>
+          <bitfield name="Attr3" caption="Attribute of MPU region 3" mask="0xFF000000"/>
+        </register>
+        <register name="MPU_MAIR1" offset="0x34" rw="RW" size="4" access-size="4" caption="MPU Memory Attribute Indirection Register 1">
+          <bitfield name="Attr4" caption="Attribute of MPU region 4" mask="0xFF"/>
+          <bitfield name="Attr5" caption="Attribute of MPU region 5" mask="0xFF00"/>
+          <bitfield name="Attr6" caption="Attribute of MPU region 6" mask="0xFF0000"/>
+          <bitfield name="Attr7" caption="Attribute of MPU region 7" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <value-group name="MPU_RBAR__AP">
+        <value name="RWPRIV" caption="Read/write by privileged code only" value="0"/>
+        <value name="RWANY" caption="Read/write by any privilege level" value="1"/>
+        <value name="RPRIV" caption="Read-only by privileged code only" value="2"/>
+        <value name="RANY" caption="Read-only by any privilege level" value="3"/>
+      </value-group>
+      <value-group name="MPU_RBAR__SH">
+        <value name="NO" caption="Non-shareable" value="0"/>
+        <value name="OUTER" caption="Outer shareable" value="2"/>
+        <value name="INNER" caption="Inner shareable" value="3"/>
+      </value-group>
+    </module>
+    <module name="NVIC" id="SYSTEM_IP" version="1.0.0" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register name="NVIC_ISER" offset="0x0" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Set Enable Register n">
+          <bitfield name="SETENA" caption="Set enable" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ICER" offset="0x80" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Clear Enable Register n">
+          <bitfield name="CLRENA" caption="Clear enable" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ISPR" offset="0x100" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Set Pending Register n">
+          <bitfield name="SETPEND" caption="Set pending" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ICPR" offset="0x180" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Clear Pending Register n">
+          <bitfield name="CLRPEND" caption="Clear pending" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_IABR" offset="0x200" rw="R" size="4" access-size="4" count="5" caption="Interrupt Active Bit Register n">
+          <bitfield name="ACTIVE" caption="Active state" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ITNS" offset="0x280" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Target Non-secure Register n">
+          <bitfield name="ITNS" caption="Interrupt Targets Non-secure" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_IPR" offset="0x300" rw="RW" size="4" access-size="4" count="36" caption="Interrupt Priority Register n">
+          <bitfield name="PRI_N0" caption="Priority of interrupt number 4n+0" mask="0xFF"/>
+          <bitfield name="PRI_N1" caption="Priority of interrupt number 4n+1" mask="0xFF00"/>
+          <bitfield name="PRI_N2" caption="Priority of interrupt number 4n+2" mask="0xFF0000"/>
+          <bitfield name="PRI_N3" caption="Priority of interrupt number 4n+3" mask="0xFF000000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="OSC32KCTRL" id="03717" name2="osc_osc32kctrl_u2400_v2" version="2a0" caption="32kHz Oscillators Control">
+      <register-group name="OSC32KCTRL" caption="32kHz Oscillators Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector" mask="0x4"/>
+          <bitfield name="XOSC32KSW" caption="XOSC32K Clock switch" mask="0x8"/>
+        </register>
+        <register name="CLKSELCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Clock Selection Control">
+          <bitfield name="RTCSEL" caption="RTC Clock Selection" mask="0x3" values="CLKSELCTRL__RTCSEL"/>
+          <bitfield name="HSMSEL" caption="HSM Clock Selection" mask="0x30" values="CLKSELCTRL__HSMSEL"/>
+        </register>
+        <register name="CFDCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Clock Failure Detector Control">
+          <bitfield name="CFDEN" caption="Clock Failure Detector Enable" mask="0x1"/>
+          <bitfield name="SWBACK" caption="Clock Switch Back" mask="0x2"/>
+          <bitfield name="CFDPRESC" caption="Clock Failure Detector Prescaler" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="CFDEO" caption="Clock Failure Detector Event Output Enable" mask="0x1"/>
+        </register>
+        <register name="XOSC32K" offset="0x1C" rw="RW" size="4" initval="0x00200080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="ONDEMAND" caption="On Demand Mode" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Startup Mode" mask="0xF00" values="XOSC32K__STARTUP"/>
+          <bitfield name="ENSL" caption="Enable Servo Loop" mask="0x10000"/>
+          <bitfield name="BOOST" caption="Gain Boost" mask="0x20000"/>
+          <bitfield name="CGM" caption="Control Gain Mode" mask="0x3C0000" values="XOSC32K__CGM"/>
+          <bitfield name="CTRLX" caption="Extended Control" mask="0xF000000"/>
+        </register>
+      </register-group>
+      <value-group name="CLKSELCTRL__RTCSEL">
+        <value name="ULP32K" caption="32.768kHz from 32kHz internal ULP oscillator" value="0x0"/>
+        <value name="ULP1K" caption="1.024kHz from 32kHz internal ULP oscillator" value="0x1"/>
+        <value name="XOSC32K" caption="32.768kHz from 32.768kHz external crystal oscillator" value="0x2"/>
+        <value name="XOSC1K" caption="1.024kHz from 32.768kHz internal oscillator" value="0x3"/>
+      </value-group>
+      <value-group name="CLKSELCTRL__HSMSEL">
+        <value name="ULP32K" caption="32.768kHz from 32kHz internal ULP oscillator" value="0x0"/>
+        <value name="XOSC32K" caption="32.768kHz from 32.768kHz external crystal oscillator" value="0x2"/>
+      </value-group>
+      <value-group name="XOSC32K__STARTUP">
+        <value name="1CYCLE" caption="1 ULP clock cycle" value="0x0"/>
+        <value name="16CYCLES" caption="16 ULP clock cycles" value="0x1"/>
+        <value name="32CYCLES" caption="32 ULP clock cycles" value="0x2"/>
+        <value name="2048CYCLES" caption="2048 ULP clock cycles" value="0x3"/>
+        <value name="4096CYCLES" caption="4096 ULP clock cycles" value="0x4"/>
+        <value name="8192CYCLES" caption="8192 ULP clock cycles" value="0x5"/>
+        <value name="16384CYCLES" caption="16384 ULP clock cycles" value="0x6"/>
+        <value name="32768CYCLES" caption="32768 ULP clock cycles" value="0x7"/>
+        <value name="65536CYCLES" caption="65536 ULP clock cycles" value="0x8"/>
+        <value name="131072CYCLES" caption="131072 ULP clock cycles" value="0x9"/>
+        <value name="262144CYCLES" caption="262144 ULP clock cycles" value="0xA"/>
+      </value-group>
+      <value-group name="XOSC32K__CGM">
+        <value name="CGM0" caption="The lower Control Gain Mode value" value="0x0"/>
+        <value name="CGM1" caption="A higher Control Gain Mode value than CGM0" value="0x1"/>
+        <value name="CGM2" caption="A higher Control Gain Mode value than CGM1" value="0x2"/>
+        <value name="CGM3" caption="A higher Control Gain Mode value than CGM2" value="0x3"/>
+        <value name="CGM4" caption="A higher Control Gain Mode value than CGM3" value="0x4"/>
+        <value name="CGM5" caption="A higher Control Gain Mode value than CGM4" value="0x5"/>
+        <value name="CGM6" caption="A higher Control Gain Mode value than CGM5" value="0x6"/>
+        <value name="CGM7" caption="A higher Control Gain Mode value than CGM6" value="0x7"/>
+        <value name="CGM8" caption="A higher Control Gain Mode value than CGM7" value="0x8"/>
+        <value name="CGM9" caption="A higher Control Gain Mode value than CGM8" value="0x9"/>
+        <value name="CGM10" caption="A higher Control Gain Mode value than CGM9" value="0xA"/>
+        <value name="CGM11" caption="A higher Control Gain Mode value than CGM10" value="0xB"/>
+        <value name="CGM12" caption="A higher Control Gain Mode value than CGM11" value="0xC"/>
+        <value name="CGM13" caption="A higher Control Gain Mode value than CGM12" value="0xD"/>
+        <value name="CGM14" caption="A higher Control Gain Mode value than CGM13" value="0xE"/>
+        <value name="CGM15" caption="The highest Control Gain Mode value" value="0xF"/>
+      </value-group>
+    </module>
+    <module name="OSCCTRL" id="03718" name2="osc_oscctrl_u2401_v2" version="2b0" caption="Oscillators Control">
+      <register-group name="OSCCTRL" caption="Oscillators Control">
+        <register name="EVCTRL" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="CFDEO" caption="Clock Failure Detector Event Output Enable" mask="0x1"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure Interrupt Enable" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure Interrupt Enable" mask="0x4"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock Interrupt Enable" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow Interrupt Enable" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure Interrupt Enable" mask="0x2000"/>
+          <bitfield name="PLL0LOCKR" caption="PLL 0 Lock Rise Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="PLL0LOCKF" caption="PLL 0 Lock Fall Interrupt Enable" mask="0x2000000"/>
+        </register>
+        <register name="INTENSET" offset="0x8" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure Interrupt Enable" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure Interrupt Enable" mask="0x4"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock Interrupt Enable" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow Interrupt Enable" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure Interrupt Enable" mask="0x2000"/>
+          <bitfield name="PLL0LOCKR" caption="PLL 0 Lock Rise Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="PLL0LOCKF" caption="PLL 0 Lock Fall Interrupt Enable" mask="0x2000000"/>
+        </register>
+        <register name="INTFLAG" offset="0xC" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure" mask="0x4"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure" mask="0x2000"/>
+          <bitfield name="PLL0LOCKR" caption="PLL 0 Lock Rise" mask="0x1000000"/>
+          <bitfield name="PLL0LOCKF" caption="PLL 0 Lock Fall" mask="0x2000000"/>
+        </register>
+        <register name="STATUS" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure" mask="0x4"/>
+          <bitfield name="XOSCCKSW" caption="XOSC Clock Switch" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure" mask="0x2000"/>
+          <bitfield name="PLL0LOCK" caption="PLL 0 Lock" mask="0x1000000"/>
+        </register>
+        <register name="XOSCCTRLA" offset="0x14" rw="RW" size="4" initval="0x00000D00" caption="External Multipurpose Crystal Oscillator Control A">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="AGC" caption="Auto Gain Control Loop Enable" mask="0x4"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x8"/>
+          <bitfield name="CFDEN" caption="Clock Failure Detector Enable" mask="0x10"/>
+          <bitfield name="SWBEN" caption="Xosc Clock Switch Back Enable" mask="0x20"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF00" values="XOSCCTRLA__STARTUP"/>
+          <bitfield name="CFDPRESC" caption="Clock Failure Detector Prescaler" mask="0xF0000" values="XOSCCTRLA__CFDPRESC"/>
+          <bitfield name="USBHSDIV" caption="USBHS Referrence Clock Division" mask="0x3000000" values="XOSCCTRLA__USBHSDIV"/>
+          <bitfield name="WRTLOCK" caption="Write Lock for CTRLA register" mask="0x80000000"/>
+        </register>
+        <register name="XOSCCTRLB" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="External Multipurpose Crystal Oscillator Control B">
+          <bitfield name="USRCFG" caption="User Configuration Control Bits" mask="0xFF"/>
+          <bitfield name="WRTLOCK" caption="Write Lock for CTRLB register" mask="0x80000000"/>
+        </register>
+        <register name="DFLLCTRLA" offset="0x2C" rw="RW" size="4" initval="0x00000082" caption="DFLL48M Control A">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x4"/>
+          <bitfield name="LOWFREQ" caption="Low Frequency Mode" mask="0x8"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="DFLLCTRLB" offset="0x30" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="DFLL48M Control B">
+          <bitfield name="LOOPEN" caption="Operating Mode Selection" mask="0x1"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x2"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x4"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x8"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x10"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x20"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x80"/>
+        </register>
+        <register name="DFLLTUNE" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="DFLL48M Tune">
+          <bitfield name="TUNE" caption="Tune Value" mask="0x7F"/>
+        </register>
+        <register name="DFLLDIFF" offset="0x38" rw="R" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Diff">
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF"/>
+        </register>
+        <register name="DFLLMUL" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="STEP" caption="Tune Maximum Step" mask="0x7F0000"/>
+        </register>
+        <register name="PLL0CTRL" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="PLL Control">
+          <bitfield name="ENABLE" caption="PLL Enable" mask="0x2"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x4"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="REFSEL" caption="Reference selection" mask="0x700" values="PLL0CTRL__REFSEL"/>
+          <bitfield name="BWSEL" caption="Bandwidth selection" mask="0x3800" values="PLL0CTRL__BWSEL"/>
+        </register>
+        <register name="PLL0FBDIV" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="PLL Feed-Back Divider">
+          <bitfield name="FBDIV" caption="PLL Feed-Back Divider Factor" mask="0x3FF"/>
+        </register>
+        <register name="PLL0REFDIV" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="PLL reference divider">
+          <bitfield name="REFDIV" caption="PLL reference division factor" mask="0x3F"/>
+        </register>
+        <register name="PLL0POSTDIVA" offset="0x4C" rw="RW" size="4" initval="0x20202020" caption="PLL output clock divider A">
+          <bitfield name="POSTDIV0" caption="PLL output 0 clock division factor" mask="0x3F"/>
+          <bitfield name="OUTEN0" caption="PLL output 0 enable" mask="0x80"/>
+          <bitfield name="POSTDIV1" caption="PLL output 0 clock division factor" mask="0x3F00"/>
+          <bitfield name="OUTEN1" caption="PLL output 0 enable" mask="0x8000"/>
+          <bitfield name="POSTDIV2" caption="PLL output 0 clock division factor" mask="0x3F0000"/>
+          <bitfield name="OUTEN2" caption="PLL output 0 enable" mask="0x800000"/>
+          <bitfield name="POSTDIV3" caption="PLL output 0 clock division factor" mask="0x3F000000"/>
+          <bitfield name="OUTEN3" caption="PLL output 0 enable" mask="0x80000000"/>
+        </register>
+        <register name="PLL0POSTDIVB" offset="0x50" rw="RW" size="4" initval="0x00000020" caption="PLL output clock divider B">
+          <bitfield name="POSTDIV4" caption="PLL output 4 clock division factor" mask="0x3F"/>
+          <bitfield name="OUTEN4" caption="PLL output 4 enable" mask="0x80"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x78" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="DFLLENABLE" caption="DFLL48M ENABLE Synchronization Busy" mask="0x2"/>
+          <bitfield name="DFLLCTRLB" caption="DFLLCTRLB Synchronization Busy" mask="0x4"/>
+          <bitfield name="DFLLTUNE" caption="DFLLTUNE Synchronization Busy" mask="0x8"/>
+          <bitfield name="DFLLDIFF" caption="DFLLDIFF Synchronization Busy" mask="0x10"/>
+          <bitfield name="DFLLMUL" caption="DFLLMUL Synchronization Busy" mask="0x20"/>
+          <bitfield name="FRACDIV0" caption="FRACDIV0 Synchronization Busy" mask="0x40"/>
+          <bitfield name="FRACDIV1" caption="FRACDIV1 Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="XOSCCAL" offset="0x80" rw="RW" size="4" initval="0x00000000" caption="XOSC Calibration Register">
+          <mode name="DEFAULT"/>
+          <mode name="FUSES_OSC_XTAL_HF_AGC_V2"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="FTRANS" caption="Fine Transconductance programmability for Oscillator" mask="0x3"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="KICKEREN" caption="Kicker enable" mask="0x4"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="ENVAMP" caption="envelope amplitude at osci" mask="0x8"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="HYST" caption="loop hysteresis control" mask="0x10"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="CMSEL" caption="clock buffer common mode selection" mask="0x20"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="FLIPPOL" caption="flip output clock polarity" mask="0x40"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="REDGAIN" caption="reduce gain control timer" mask="0x100"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="REDOSC" caption="reduce oscillation debug counter" mask="0x200"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="SPARES" caption="Spare bits" mask="0xFC00"/>
+          <bitfield modes="DEFAULT" name="CAL" caption="XOSC Calibration" mask="0xFFFF"/>
+        </register>
+        <register name="RC48MCAL0" offset="0x88" rw="RW" size="4" initval="0x00000000" caption="RC48M Calibration 0">
+          <mode name="DEFAULT"/>
+          <mode name="FUSES_OSC_RC48MHZ_V1"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="temp_trim_mv" caption="Temp trim value" mask="0x3F"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="proc_trim_mv" caption="Proc trim value" mask="0x3FC0"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="iosc_boost" caption="IOSC boost" mask="0x10000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="out_buf_sel" caption="Output buffer select" mask="0x20000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="ldo_vout_boost" caption="LDO VOUT boost" mask="0x40000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="cmp_8m_lp" caption="Comparator 8MHz low-power" mask="0x80000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="cmp_pwr_ctrl" caption="Comparator power control" mask="0x700000"/>
+          <bitfield modes="DEFAULT" name="CAL" caption="RC48M Calibration" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="XOSCCTRLA__STARTUP">
+        <value name="CYCLE1" caption="31 us" value="0"/>
+        <value name="CYCLE2" caption="61 us" value="1"/>
+        <value name="CYCLE4" caption="122 us" value="2"/>
+        <value name="CYCLE8" caption="244 us" value="3"/>
+        <value name="CYCLE16" caption="488 us" value="4"/>
+        <value name="CYCLE32" caption="977 us" value="5"/>
+        <value name="CYCLE64" caption="1953 us" value="6"/>
+        <value name="CYCLE128" caption="3906 us" value="7"/>
+        <value name="CYCLE256" caption="7813 us" value="8"/>
+        <value name="CYCLE512" caption="15625 us" value="9"/>
+        <value name="CYCLE1024" caption="31250 us" value="10"/>
+        <value name="CYCLE2048" caption="62500 us" value="11"/>
+        <value name="CYCLE4096" caption="125000 us" value="12"/>
+        <value name="CYCLE8192" caption="250000 us" value="13"/>
+        <value name="CYCLE16384" caption="500000 us" value="14"/>
+        <value name="CYCLE32768" caption="1000000 us" value="15"/>
+      </value-group>
+      <value-group name="XOSCCTRLA__CFDPRESC">
+        <value name="DIV1" caption="48 MHz" value="0"/>
+        <value name="DIV2" caption="24 MHz" value="1"/>
+        <value name="DIV4" caption="12 MHz" value="2"/>
+        <value name="DIV8" caption="6 MHz" value="3"/>
+        <value name="DIV16" caption="3 MHz" value="4"/>
+        <value name="DIV32" caption="1.5 MHz" value="5"/>
+        <value name="DIV64" caption="0.75 MHz" value="6"/>
+        <value name="DIV128" caption="0.375 MHz" value="7"/>
+        <value name="DIV256" caption="187.5 KHz" value="8"/>
+        <value name="DIV512" caption="93.75 KHz" value="9"/>
+        <value name="DIV1024" caption="46.875 KHz" value="10"/>
+        <value name="DIV2048" caption="23.437 KHz" value="11"/>
+        <value name="DIV4096" caption="11.718 KHz" value="12"/>
+        <value name="DIV8192" caption="5.85 KHz" value="13"/>
+        <value name="DIV16384" caption="2.92 KHz" value="14"/>
+        <value name="DIV32768" caption="1.46 KHz" value="15"/>
+      </value-group>
+      <value-group name="XOSCCTRLA__USBHSDIV">
+        <value name="DIS" caption="USBHS PLL reference XOSC clock is disabled" value="0"/>
+        <value name="DIV1" caption="USBHS PLL reference XOSC clock is divided by 1" value="1"/>
+        <value name="DIV2" caption="USBHS PLL reference XOSC clock is divided by 2" value="2"/>
+        <value name="DIV4" caption="USBHS PLL reference XOSC clock is divided by 4" value="3"/>
+      </value-group>
+      <value-group name="PLL0CTRL__REFSEL">
+        <value name="GCLK" caption="Dedicated GCLK clock reference" value="0x0"/>
+        <value name="XOSC" caption="XOSC clock reference" value="0x1"/>
+        <value name="DFLL48M" caption="DFLL48M clock reference" value="0x2"/>
+      </value-group>
+      <value-group name="PLL0CTRL__BWSEL">
+        <value name="BWSEL0" caption="TBD" value="0x0"/>
+        <value name="BWSEL1" caption="TBD" value="0x1"/>
+        <value name="BWSEL2" caption="TBD" value="0x2"/>
+        <value name="BWSEL3" caption="TBD" value="0x3"/>
+        <value name="BWSEL4" caption="TBD" value="0x4"/>
+        <value name="BWSEL5" caption="TBD" value="0x5"/>
+        <value name="BWSEL6" caption="TBD" value="0x6"/>
+        <value name="BWSEL7" caption="TBD" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PAC" id="04298" name2="sec_pac_apb_v1" version="1a0" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A Register">
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+        </register>
+        <register name="WRCTRL" offset="0x4" rw="W" size="4" initval="0x00000000" caption="Write Control Register">
+          <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+          <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="WRCTRL__KEY"/>
+        </register>
+        <register name="STATUS" offset="0x40" rw="R" size="4" count="4" initval="0x00000000" caption="Peripheral Status n Register">
+          <bitfield name="PERID0" caption="PERID Write Protection Status" mask="0x1" values="STATUS__PERID"/>
+          <bitfield name="PERID1" caption="PERID Write Protection Status" mask="0x2" values="STATUS__PERID"/>
+          <bitfield name="PERID2" caption="PERID Write Protection Status" mask="0x4" values="STATUS__PERID"/>
+          <bitfield name="PERID3" caption="PERID Write Protection Status" mask="0x8" values="STATUS__PERID"/>
+          <bitfield name="PERID4" caption="PERID Write Protection Status" mask="0x10" values="STATUS__PERID"/>
+          <bitfield name="PERID5" caption="PERID Write Protection Status" mask="0x20" values="STATUS__PERID"/>
+          <bitfield name="PERID6" caption="PERID Write Protection Status" mask="0x40" values="STATUS__PERID"/>
+          <bitfield name="PERID7" caption="PERID Write Protection Status" mask="0x80" values="STATUS__PERID"/>
+          <bitfield name="PERID8" caption="PERID Write Protection Status" mask="0x100" values="STATUS__PERID"/>
+          <bitfield name="PERID9" caption="PERID Write Protection Status" mask="0x200" values="STATUS__PERID"/>
+          <bitfield name="PERID10" caption="PERID Write Protection Status" mask="0x400" values="STATUS__PERID"/>
+          <bitfield name="PERID11" caption="PERID Write Protection Status" mask="0x800" values="STATUS__PERID"/>
+          <bitfield name="PERID12" caption="PERID Write Protection Status" mask="0x1000" values="STATUS__PERID"/>
+          <bitfield name="PERID13" caption="PERID Write Protection Status" mask="0x2000" values="STATUS__PERID"/>
+          <bitfield name="PERID14" caption="PERID Write Protection Status" mask="0x4000" values="STATUS__PERID"/>
+          <bitfield name="PERID15" caption="PERID Write Protection Status" mask="0x8000" values="STATUS__PERID"/>
+          <bitfield name="PERID16" caption="PERID Write Protection Status" mask="0x10000" values="STATUS__PERID"/>
+          <bitfield name="PERID17" caption="PERID Write Protection Status" mask="0x20000" values="STATUS__PERID"/>
+          <bitfield name="PERID18" caption="PERID Write Protection Status" mask="0x40000" values="STATUS__PERID"/>
+          <bitfield name="PERID19" caption="PERID Write Protection Status" mask="0x80000" values="STATUS__PERID"/>
+          <bitfield name="PERID20" caption="PERID Write Protection Status" mask="0x100000" values="STATUS__PERID"/>
+          <bitfield name="PERID21" caption="PERID Write Protection Status" mask="0x200000" values="STATUS__PERID"/>
+          <bitfield name="PERID22" caption="PERID Write Protection Status" mask="0x400000" values="STATUS__PERID"/>
+          <bitfield name="PERID23" caption="PERID Write Protection Status" mask="0x800000" values="STATUS__PERID"/>
+          <bitfield name="PERID24" caption="PERID Write Protection Status" mask="0x1000000" values="STATUS__PERID"/>
+          <bitfield name="PERID25" caption="PERID Write Protection Status" mask="0x2000000" values="STATUS__PERID"/>
+          <bitfield name="PERID26" caption="PERID Write Protection Status" mask="0x4000000" values="STATUS__PERID"/>
+          <bitfield name="PERID27" caption="PERID Write Protection Status" mask="0x8000000" values="STATUS__PERID"/>
+          <bitfield name="PERID28" caption="PERID Write Protection Status" mask="0x10000000" values="STATUS__PERID"/>
+          <bitfield name="PERID29" caption="PERID Write Protection Status" mask="0x20000000" values="STATUS__PERID"/>
+          <bitfield name="PERID30" caption="PERID Write Protection Status" mask="0x40000000" values="STATUS__PERID"/>
+          <bitfield name="PERID31" caption="PERID Write Protection Status" mask="0x80000000" values="STATUS__PERID"/>
+        </register>
+        <register name="LOCK" offset="0x50" rw="R" size="4" count="4" initval="0x00000000" caption="Peripheral Lock n Register">
+          <bitfield name="PERID0" caption="PERID Write Protection Lock Status" mask="0x1" values="LOCK__PERID"/>
+          <bitfield name="PERID1" caption="PERID Write Protection Lock Status" mask="0x2" values="LOCK__PERID"/>
+          <bitfield name="PERID2" caption="PERID Write Protection Lock Status" mask="0x4" values="LOCK__PERID"/>
+          <bitfield name="PERID3" caption="PERID Write Protection Lock Status" mask="0x8" values="LOCK__PERID"/>
+          <bitfield name="PERID4" caption="PERID Write Protection Lock Status" mask="0x10" values="LOCK__PERID"/>
+          <bitfield name="PERID5" caption="PERID Write Protection Lock Status" mask="0x20" values="LOCK__PERID"/>
+          <bitfield name="PERID6" caption="PERID Write Protection Lock Status" mask="0x40" values="LOCK__PERID"/>
+          <bitfield name="PERID7" caption="PERID Write Protection Lock Status" mask="0x80" values="LOCK__PERID"/>
+          <bitfield name="PERID8" caption="PERID Write Protection Lock Status" mask="0x100" values="LOCK__PERID"/>
+          <bitfield name="PERID9" caption="PERID Write Protection Lock Status" mask="0x200" values="LOCK__PERID"/>
+          <bitfield name="PERID10" caption="PERID Write Protection Lock Status" mask="0x400" values="LOCK__PERID"/>
+          <bitfield name="PERID11" caption="PERID Write Protection Lock Status" mask="0x800" values="LOCK__PERID"/>
+          <bitfield name="PERID12" caption="PERID Write Protection Lock Status" mask="0x1000" values="LOCK__PERID"/>
+          <bitfield name="PERID13" caption="PERID Write Protection Lock Status" mask="0x2000" values="LOCK__PERID"/>
+          <bitfield name="PERID14" caption="PERID Write Protection Lock Status" mask="0x4000" values="LOCK__PERID"/>
+          <bitfield name="PERID15" caption="PERID Write Protection Lock Status" mask="0x8000" values="LOCK__PERID"/>
+          <bitfield name="PERID16" caption="PERID Write Protection Lock Status" mask="0x10000" values="LOCK__PERID"/>
+          <bitfield name="PERID17" caption="PERID Write Protection Lock Status" mask="0x20000" values="LOCK__PERID"/>
+          <bitfield name="PERID18" caption="PERID Write Protection Lock Status" mask="0x40000" values="LOCK__PERID"/>
+          <bitfield name="PERID19" caption="PERID Write Protection Lock Status" mask="0x80000" values="LOCK__PERID"/>
+          <bitfield name="PERID20" caption="PERID Write Protection Lock Status" mask="0x100000" values="LOCK__PERID"/>
+          <bitfield name="PERID21" caption="PERID Write Protection Lock Status" mask="0x200000" values="LOCK__PERID"/>
+          <bitfield name="PERID22" caption="PERID Write Protection Lock Status" mask="0x400000" values="LOCK__PERID"/>
+          <bitfield name="PERID23" caption="PERID Write Protection Lock Status" mask="0x800000" values="LOCK__PERID"/>
+          <bitfield name="PERID24" caption="PERID Write Protection Lock Status" mask="0x1000000" values="LOCK__PERID"/>
+          <bitfield name="PERID25" caption="PERID Write Protection Lock Status" mask="0x2000000" values="LOCK__PERID"/>
+          <bitfield name="PERID26" caption="PERID Write Protection Lock Status" mask="0x4000000" values="LOCK__PERID"/>
+          <bitfield name="PERID27" caption="PERID Write Protection Lock Status" mask="0x8000000" values="LOCK__PERID"/>
+          <bitfield name="PERID28" caption="PERID Write Protection Lock Status" mask="0x10000000" values="LOCK__PERID"/>
+          <bitfield name="PERID29" caption="PERID Write Protection Lock Status" mask="0x20000000" values="LOCK__PERID"/>
+          <bitfield name="PERID30" caption="PERID Write Protection Lock Status" mask="0x40000000" values="LOCK__PERID"/>
+          <bitfield name="PERID31" caption="PERID Write Protection Lock Status" mask="0x80000000" values="LOCK__PERID"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="DISABLE" caption="Macro register accessible in privileged and unprivileged accesses." value="0"/>
+        <value name="ENABLE" caption="Macro registers only accessible in privileged accesses" value="1"/>
+      </value-group>
+      <value-group name="WRCTRL__KEY">
+        <value name="OFF" caption="OFF - No Action" value="0"/>
+        <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+        <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+        <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+      </value-group>
+      <value-group name="STATUS__PERID">
+        <value name="0" caption="Write Protection disabled" value="0"/>
+        <value name="1" caption="Write Protection enabled" value="1"/>
+      </value-group>
+      <value-group name="LOCK__PERID">
+        <value name="0" caption="Write Protection Unlocked" value="0"/>
+        <value name="1" caption="Write Protection Locked" value="1"/>
+      </value-group>
+    </module>
+    <module name="PDM" id="test_pdm_v1" name2="test_pdm_v1" version="1.0.0" caption=""/>
+    <module name="PM" id="03926" name2="pwr_rpmu_pm_v1" version="1c0" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="IORET" caption="I/O Retention" mask="0x4" values="CTRLA__IORET"/>
+        </register>
+        <register name="SLEEPCFG" offset="0x1" rw="RW" size="1" initval="0x02" caption="Sleep Configuration">
+          <bitfield name="SLEEPMODE" caption="Sleep Mode" mask="0x7" values="SLEEPCFG__SLEEPMODE"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="SLEEPRDY" caption="Backup Sleep Mode Entry Ready Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="SLEEPRDY" caption="Backup Sleep Mode Entry Ready Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="SLEEPRDY" caption="Backup Sleep Mode Entry Ready" mask="0x1"/>
+        </register>
+        <register name="STDBYCFG" offset="0x8" rw="RW" size="1" initval="0x04" caption="Standby Configuration">
+          <bitfield name="RAMCFG" caption="Ram Configuration" mask="0x1" values="STDBYCFG__RAMCFG"/>
+          <bitfield name="LPRAM" caption="Low Power RAM Enable" mask="0x4"/>
+        </register>
+        <register name="HIBCFG" offset="0x9" rw="RW" size="1" initval="0x04" caption="Hibernate Configuration">
+          <bitfield name="RAMCFG" caption="Ram Configuration" mask="0x1" values="HIBCFG__RAMCFG"/>
+          <bitfield name="LPRAM" caption="Low Power RAM Enable" mask="0x4"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__IORET">
+        <value name="NOIORET" caption="When  the  device  exits  the  HIBERNATE or BACKUP  mode,  the  I/O  line  configuration are released." value="0x0"/>
+        <value name="IORET" caption="When  the  device  exits  the  HIBERNATE or BACKUP  mode,  the  I/O  line  configuration are stretched." value="0x1"/>
+      </value-group>
+      <value-group name="SLEEPCFG__SLEEPMODE">
+        <value name="IDLE" caption="CPU, AHB and APB clocks are OFF" value="2"/>
+        <value name="STANDBY" caption="All Clocks are OFF" value="4"/>
+        <value name="HIBERNATE" caption="Backup domain is ON as well as some PDRAMs" value="5"/>
+        <value name="BACKUP" caption="Only Backup domain is powered ON" value="6"/>
+        <value name="OFF" caption="All power domains are powered OFF" value="7"/>
+      </value-group>
+      <value-group name="STDBYCFG__RAMCFG">
+        <value name="RET" caption="All the RAMs are retained" value="0"/>
+        <value name="OFF" caption="Only the first 32K bytes are retained" value="1"/>
+      </value-group>
+      <value-group name="HIBCFG__RAMCFG">
+        <value name="RET" caption="All the RAMs are retained" value="0x0"/>
+        <value name="OFF" caption="Only the first 32K bytes are retained" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="03720" name2="gpio_port_u2210_v4" version="4a0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="PORT Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="PORT Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="PORT Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="PORT Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="PORT Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="ODRAIN" caption="Open Drain Output" mask="0x80000"/>
+          <bitfield name="SLEWLIM" caption="Output Driver Slew Rate Selection" mask="0x300000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="EVCTRL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="Event Input Control">
+          <bitfield name="PID0" caption="PORT Event Pin Identifier 0" mask="0x1F"/>
+          <bitfield name="EVACT0" caption="PORT Event Action 0" mask="0x60" values="EVCTRL__EVACT0"/>
+          <bitfield name="PORTEI0" caption="PORT Event Input Enable 0" mask="0x80"/>
+          <bitfield name="PID1" caption="PORT Event Pin Identifier 1" mask="0x1F00"/>
+          <bitfield name="EVACT1" caption="PORT Event Action 1" mask="0x6000"/>
+          <bitfield name="PORTEI1" caption="PORT Event Input Enable 1" mask="0x8000"/>
+          <bitfield name="PID2" caption="PORT Event Pin Identifier 2" mask="0x1F0000"/>
+          <bitfield name="EVACT2" caption="PORT Event Action 2" mask="0x600000"/>
+          <bitfield name="PORTEI2" caption="PORT Event Input Enable 2" mask="0x800000"/>
+          <bitfield name="PID3" caption="PORT Event Pin Identifier 3" mask="0x1F000000"/>
+          <bitfield name="EVACT3" caption="PORT Event Action 3" mask="0x60000000"/>
+          <bitfield name="PORTEI3" caption="PORT Event Input Enable 3" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing for Even-Numbered Pin" mask="0xF" values="PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing for Odd-Numbered Pin" mask="0xF0" values="PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="ODRAIN" caption="Open Drain Output" mask="0x8"/>
+          <bitfield name="SLEWLIM" caption="Output Driver Slew Rate Selection" mask="0x30" values="PINCFG__SLEWLIM"/>
+        </register>
+        <register name="INTENCLR" offset="0x60" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="NSCHK" caption="Non-Secure Check Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x64" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="NSCHK" caption="Non-Secure Check Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x68" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="NSCHK" caption="Non-Secure Check" mask="0x1"/>
+        </register>
+        <register name="NONSEC" offset="0x6C" rw="RW" size="4" initval="0x00000000" caption="Security Attribution">
+          <bitfield name="NONSEC" caption="Port Security Attribution" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NSCHK" offset="0x70" rw="RW" size="4" initval="0x00000000" caption="Security Attribution Check">
+          <bitfield name="NSCHK" caption="Port Security Attribution Check" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" size="0x80" count="4"/>
+      </register-group>
+      <value-group name="EVCTRL__EVACT0">
+        <value name="OUT" caption="Event output to pin" value="0x0"/>
+        <value name="SET" caption="Set output register of pin on event" value="0x1"/>
+        <value name="CLR" caption="Clear output register of pin on event" value="0x2"/>
+        <value name="TGL" caption="Toggle output register of pin on event" value="0x3"/>
+      </value-group>
+      <value-group name="PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0"/>
+        <value name="B" caption="Peripheral function B selected" value="1"/>
+        <value name="D" caption="Peripheral function D selected" value="3"/>
+        <value name="F" caption="Peripheral function F selected" value="5"/>
+        <value name="H" caption="Peripheral function H selected" value="7"/>
+        <value name="I" caption="Peripheral function I selected" value="8"/>
+        <value name="K" caption="Peripheral function K selected" value="10"/>
+        <value name="P" caption="Peripheral function P selected" value="15"/>
+      </value-group>
+      <value-group name="PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0"/>
+        <value name="B" caption="Peripheral function B selected" value="1"/>
+        <value name="D" caption="Peripheral function D selected" value="3"/>
+        <value name="F" caption="Peripheral function F selected" value="5"/>
+        <value name="H" caption="Peripheral function H selected" value="7"/>
+        <value name="I" caption="Peripheral function I selected" value="8"/>
+        <value name="K" caption="Peripheral function K selected" value="10"/>
+        <value name="P" caption="Peripheral function P selected" value="15"/>
+      </value-group>
+      <value-group name="PINCFG__SLEWLIM">
+        <value name="FAST" caption="Slew rate control disabled (fast rise/fall time operation)" value="0x0"/>
+        <value name="SLOW4" caption="Slew rate control enabled (4x slower)" value="0x1"/>
+        <value name="SLOW8" caption="Slew rate control enabled (8x slower)" value="0x2"/>
+        <value name="SLOW12" caption="Slew rate control enabled (12x slower)" value="0x3"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="04743" name2="afe_ptc_ctrl_apb_plrs_v1" version="1a0" caption="Polaris Peripheral Touch Controller">
+      <register-group name="PTC" caption="Polaris Peripheral Touch Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="CONTROL ENABLE REGISTER">
+          <bitfield name="SWRST" caption="Software Reset for this macro." mask="0x1" values="CTRLA__SWRST"/>
+          <bitfield name="ENABLE" caption="PTC -- Enable" mask="0x2" values="CTRLA__ENABLE"/>
+          <bitfield name="PRIV" caption="Privileged Access Only -- provides filtering of privilege/non-privilege bus accesses to SFR registers" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run In Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="EVENT CONTROL REGISTER">
+          <bitfield name="STCONVEI" caption="Start Conversion Event Input Enable" mask="0x1"/>
+          <bitfield name="DSEQREI" caption="DMA Sequencing Restart Event Input Enable" mask="0x2"/>
+          <bitfield name="STCONVINV" caption="Start Conversion Event Invert Enable" mask="0x4"/>
+          <bitfield name="DSEQRINV" caption="DMA Sequencing Restart Event Invert Enable" mask="0x8"/>
+          <bitfield name="EOCEO" caption="End of Conversion Event Output Enable" mask="0x10"/>
+          <bitfield name="WCOMPEO" caption="Window Comparator Event Output Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="DEBUG CONTROL Register">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="CTRLB" offset="0xC" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL B Register">
+          <bitfield name="CTSM" caption="Capacitive Touch Sensing Mode" mask="0x7"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x10"/>
+          <bitfield name="SDS" caption="Sampling Delay Selection." mask="0xF00"/>
+          <bitfield name="ASDV" caption="Automatic Sampling Delay Variation." mask="0x1000"/>
+          <bitfield name="CCDS" caption="Channel Change Delay Selection" mask="0x6000"/>
+          <bitfield name="RSEL" caption="Resistor Selection" mask="0x700000"/>
+        </register>
+        <register name="CTRLC" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL C Register">
+          <bitfield name="CCF" caption="Compensation Capacitor Fine Value" mask="0x1F"/>
+          <bitfield name="CCC" caption="Compensation Capacitor Coarse Value" mask="0x1F00"/>
+          <bitfield name="CI" caption="Integration Capacitor Value" mask="0x1F0000"/>
+          <bitfield name="CSD" caption="Charge Share Delay Value" mask="0xFF000000"/>
+        </register>
+        <register name="CTRLD" offset="0x14" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL D Register">
+          <bitfield name="DAN" caption="Digital Accumulation Number" mask="0x7"/>
+          <bitfield name="AAN" caption="Analog Accumulation Number" mask="0xF00"/>
+          <bitfield name="WINCM" caption="Window Comparator Mode" mask="0x70000"/>
+          <bitfield name="WINSS" caption="Window Single Sample" mask="0x80000"/>
+          <bitfield name="EXTCIEN" caption="External Integration Capacitor Enable" mask="0x300000"/>
+          <bitfield name="POLICC" caption="Polarity of Internal Compensation Capacitor" mask="0x800000"/>
+          <bitfield name="DSEN" caption="DSEN Driven Shield Enable." mask="0x1000000"/>
+          <bitfield name="DSEQSTOP" caption="Stop DMA Sequence" mask="0x80000000"/>
+        </register>
+        <register name="CTRLE" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="CONTROL E REGISTER">
+          <bitfield name="AIPMPEN" caption="Analog Input Charge Pump Enable" mask="0x10"/>
+          <bitfield name="PRSC" caption="This field defines the PTC clock relative to the peripheral clock according to the table below." mask="0x700"/>
+          <bitfield name="WKUPEXP" caption="Wake-Up Exponent" mask="0xF000"/>
+        </register>
+        <register name="SWTRIG" offset="0x1C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Software Trigger Register">
+          <bitfield name="STCONV" caption="Start Conversion" mask="0x1"/>
+        </register>
+        <register name="WINLT" offset="0x20" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Window Comparator Low Threshold Register">
+          <bitfield name="WCLT" caption="Window Comparator Low Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINHT" offset="0x24" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Window Comparator High Threshold Register">
+          <bitfield name="WCHT" caption="Window Comparator High Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="PINEN1" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="PTC Line Enable 1 Register">
+          <bitfield name="PINEN" caption="PTC-Line 31-0 Enable" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PINEN2" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="PTC Line Enable 2 Register">
+          <bitfield name="PINEN" caption="PTC-Line 63-32 Enable" mask="0xF"/>
+        </register>
+        <register name="XSEL1" offset="0x30" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="X Line Selection 1 Register">
+          <bitfield name="XSEL" caption="X-Line Selection [31:0]" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="XSEL2" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="X Line Selection 2 Register">
+          <bitfield name="XSEL" caption="X-Line Selection [63:32]" mask="0xF"/>
+        </register>
+        <register name="YSEL1" offset="0x38" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Y Line Selection 1 Register">
+          <bitfield name="YSEL" caption="Y-Line Selection [31:0]" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="YSEL2" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Y Line Selection 2 Register">
+          <bitfield name="YSEL" caption="Y-Line Selection [63:32]" mask="0xF"/>
+        </register>
+        <register name="POLCTRL1" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Polarity Control 1 Register">
+          <bitfield name="POLARITY" caption="Choose X/Y lines Polarity [31:0]" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="POLCTRL2" offset="0x44" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Polarity Control 2 Register">
+          <bitfield name="POLARITY" caption="Choose X/Y lines Polarity [63:32]" mask="0xF"/>
+        </register>
+        <register name="INTENCLR" offset="0x48" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="INTERRUPT ENABLE CLEAR Register">
+          <bitfield name="EOC" caption="End of Conversion Enable Clear." mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Enable Clear." mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Enable Clear." mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x4C" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="INTERRUPT ENABLE SET Register">
+          <bitfield name="EOC" caption="End of Conversion Enable Set." mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Enable Set." mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Enable Set." mask="0x80"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x50" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="INTERRUPT FLAG SET Register">
+          <bitfield name="EOC" caption="End of Conversion Enable Set." mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Enable Set." mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Enable Set." mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x54" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="INTERRUPT FLAG STATUS and CLEAR Register">
+          <bitfield name="EOC" caption="End of Conversion Flag" mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Flag" mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Flag" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x58" rw="R" size="4" initval="0x00000000" caption="STATUS Register">
+          <bitfield name="PTCBUSY" caption="PTC Busy Status" mask="0x1"/>
+          <bitfield name="DAD" caption="Digital Accumulation Done" mask="0x80"/>
+          <bitfield name="WCC" caption="Window Comparator Counter" mask="0x7F00"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x5C" rw="R" size="4" initval="0x00000000" caption="Synchronization Register">
+          <bitfield name="SWRST" caption="SWRST Synchronization Busy --- Synchronizing Busy bit for swrst" mask="0x1"/>
+          <bitfield name="ENABLE" caption="ENABLE Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Control B Synchronization Busy" mask="0x4"/>
+          <bitfield name="CTRLC" caption="Control C Synchronization Busy" mask="0x8"/>
+          <bitfield name="CTRLD" caption="Control D Synchronization Busy" mask="0x10"/>
+          <bitfield name="SWTRIG" caption="Software Trigger Synchronization Busy" mask="0x20"/>
+          <bitfield name="WINLT" caption="Window Comparator Low Threshold Synchronization Busy" mask="0x40"/>
+          <bitfield name="WINHT" caption="Window Comparator High Threshold Synchronization Busy" mask="0x80"/>
+          <bitfield name="XSEL1" caption="X-lines Selection 1 Synchronization Busy" mask="0x100"/>
+          <bitfield name="XSEL2" caption="X-lines Selection 2 Synchronization Busy" mask="0x200"/>
+          <bitfield name="YSEL1" caption="Y-lines Selection 1 Synchronization Busy" mask="0x400"/>
+          <bitfield name="YSEL2" caption="Y-lines Selection 2 Synchronization Busy" mask="0x800"/>
+          <bitfield name="POLCTRL1" caption="Polarity Control 1 Synchronization Busy" mask="0x1000"/>
+          <bitfield name="POLCTRL2" caption="Polarity Control 2 Synchronization Busy" mask="0x2000"/>
+        </register>
+        <register name="DSEQCTRL" offset="0x60" rw="RW" size="4" initval="0x00000000" caption="DMA SEQUENCE CTRL Register">
+          <bitfield name="CTRLD" caption="Control D." mask="0x1"/>
+          <bitfield name="WINLT" caption="Window Comparator Low Threshold" mask="0x2"/>
+          <bitfield name="WINHT" caption="Window Comparator High Threshold" mask="0x4"/>
+          <bitfield name="XSEL" caption="X-line n Selection lower/upper half word" mask="0x78"/>
+          <bitfield name="YSEL" caption="Y-line n Selection lower/uper half word" mask="0x780"/>
+          <bitfield name="POL" caption="Polarity n lower/upper half word" mask="0x7800"/>
+          <bitfield name="CC" caption="Compensation Capacitor" mask="0x8000"/>
+          <bitfield name="CI" caption="Integration Capacitor" mask="0x10000"/>
+          <bitfield name="CSD" caption="Charge Share Delay" mask="0x20000"/>
+          <bitfield name="AUTOSTART" caption="PTC Auto-Start Conversion." mask="0x80000000"/>
+        </register>
+        <register name="DSEQSTAT" offset="0x64" rw="R" size="4" initval="0x00000000" caption="DMA SEQUENCE STATUS - Register">
+          <bitfield name="CTRLD" caption="Control D." mask="0x1"/>
+          <bitfield name="WINLT" caption="Window Comparator Low Threshold" mask="0x2"/>
+          <bitfield name="WINHT" caption="Window Comparator High Threshold" mask="0x4"/>
+          <bitfield name="XSEL" caption="X-line n  Selection lower/upper half word" mask="0x78"/>
+          <bitfield name="YSEL" caption="Y-line n Selection lower/upper half word" mask="0x780"/>
+          <bitfield name="POL" caption="Polarity n lower/upper half word" mask="0x7800"/>
+          <bitfield name="CC" caption="Compensation Capacitor" mask="0x8000"/>
+          <bitfield name="CI" caption="Integration Capacitor" mask="0x10000"/>
+          <bitfield name="CSD" caption="Charge Share Delay" mask="0x20000"/>
+          <bitfield name="BUSY" caption="Sequencing Busy" mask="0x80000000"/>
+        </register>
+        <register name="DSEQDATA" offset="0x68" rw="W" size="4" initval="0x00000000" caption="DMA SEQUENCE DATA - Register">
+          <bitfield name="DATA" caption="DMA Sequential Data." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="RESULT" offset="0x6C" rw="R" size="4" initval="0x00000000" caption="Register">
+          <bitfield name="RES" caption="Result Conversion Value." mask="0xFFF"/>
+          <bitfield name="ACCRES" caption="Accumulated Result Conversion Value." mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__SWRST">
+        <value name="0" caption="There is no reset operation ongoing" value="0"/>
+        <value name="1" caption="The reset operation is ongoing" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__ENABLE">
+        <value name="0" caption="Disable module. System clock is only requested for bus transactions. GCLK is never requested." value="0"/>
+        <value name="1" caption="Enable module by allowing both the generic clock and system clock requests based on the incoming clock requests from the SIB." value="1"/>
+      </value-group>
+    </module>
+    <module name="RSTC" id="03926" name2="pwr_rpmu_rstc_v1" version="1c0" caption="Reset Controller">
+      <register-group name="RSTC" caption="Reset Controller">
+        <register name="RCAUSE" offset="0x0" rw="R" size="2" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="PORCORE" caption="Brown Out CORE Detector Reset" mask="0x2"/>
+          <bitfield name="BORVDDREG" caption="Brown Out VDDREG Detector Reset" mask="0x4"/>
+          <bitfield name="BORVDDA" caption="Brown Out VDDA Detector Reset" mask="0x8"/>
+          <bitfield name="BORVDDIO" caption="Brown Out VDDIO Detector Reset" mask="0x10"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x20"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x40"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x80"/>
+          <bitfield name="BACKUP" caption="Backup Reset" mask="0x100"/>
+          <bitfield name="LOCKUP" caption="Lockup Reset" mask="0x200"/>
+        </register>
+        <register name="BKUPEXIT" offset="0x2" rw="R" size="1" initval="0x00" caption="Backup Exit Source. Implemented only if RSTC_BACKUP_IMPLEMENTED=1">
+          <bitfield name="RTC" caption="Real Timer Counter Interrupt" mask="0x2"/>
+          <bitfield name="HIB0" caption="Hibernate" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Debug Control">
+          <bitfield name="LCKUPDIS" caption="Lockup Disable" mask="0x1"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="RTC" id="03608" name2="tmr_rtc_u2250_v3" version="3b0" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <mode name="MODE2" qualifier="RTC.MODE2.CTRLA.MODE" value="2" caption="Clock/Calendar with Alarm"/>
+        <register modes="MODE2" name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="MODE2_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register modes="MODE2" name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="MODE2_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group name="RTC" caption="Real-Time Counter">
+        <mode name="MODE0" qualifier="RTC.MODE0.CTRLA.MODE" value="0" caption="32-bit Counter with Single 32-bit Compare"/>
+        <mode name="MODE1" qualifier="RTC.MODE1.CTRLA.MODE" value="1" caption="16-bit Counter with Two 16-bit Compares"/>
+        <mode name="MODE2" qualifier="RTC.MODE2.CTRLA.MODE" value="2" caption="Clock/Calendar with Alarm"/>
+        <register modes="MODE0" name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="MODE0_CTRLA__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="MODE0_CTRLA__PRESCALER"/>
+          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
+          <bitfield name="COUNTSYNC" caption="Count Read Synchronization Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="MODE1_CTRLA__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="MODE1_CTRLA__PRESCALER"/>
+          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
+          <bitfield name="COUNTSYNC" caption="Count Read Synchronization Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="MODE2_CTRLA__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="MODE2_CTRLA__PRESCALER"/>
+          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
+          <bitfield name="CLOCKSYNC" caption="Clock Read Synchronization Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE0 Control B">
+          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
+          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
+          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
+          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
+          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
+          <bitfield name="DEBF" caption="Debounce Frequency" mask="0x700" values="MODE0_CTRLB__DEBF"/>
+          <bitfield name="ACTF" caption="Active Layer Frequency" mask="0x7000" values="MODE0_CTRLB__ACTF"/>
+          <bitfield name="SEPTO" caption="Separate Tamper Outputs" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE1 Control B">
+          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
+          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
+          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
+          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
+          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
+          <bitfield name="DEBF" caption="Debounce Frequency" mask="0x700" values="MODE1_CTRLB__DEBF"/>
+          <bitfield name="ACTF" caption="Active Layer Frequency" mask="0x7000" values="MODE1_CTRLB__ACTF"/>
+          <bitfield name="SEPTO" caption="Separate Tamper Outputs" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE2 Control B">
+          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
+          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
+          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
+          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
+          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
+          <bitfield name="DEBF" caption="Debounce Frequency" mask="0x700" values="MODE2_CTRLB__DEBF"/>
+          <bitfield name="ACTF" caption="Active Layer Frequency" mask="0x7000" values="MODE2_CTRLB__ACTF"/>
+          <bitfield name="SEPTO" caption="Separate Tamper Outputs" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
+          <bitfield name="PERDEO" caption="Periodic Interval Daily Event Output Enable" mask="0x1000000"/>
+        </register>
+        <register modes="MODE1" name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="CMPEO2" caption="Compare 2 Event Output Enable" mask="0x400"/>
+          <bitfield name="CMPEO3" caption="Compare 3 Event Output Enable" mask="0x800"/>
+          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
+          <bitfield name="PERDEO" caption="Periodic Interval Daily Event Output Enable" mask="0x1000000"/>
+        </register>
+        <register modes="MODE2" name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="ALARMEO1" caption="Alarm 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
+          <bitfield name="PERDEO" caption="Periodic Interval Daily Event Output Enable" mask="0x1000000"/>
+        </register>
+        <register modes="MODE0" name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="CMP2" caption="Compare 2 Interrupt Enable" mask="0x400"/>
+          <bitfield name="CMP3" caption="Compare 3 Interrupt Enable" mask="0x800"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="ALARM1" caption="Alarm 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="CMP2" caption="Compare 2 Interrupt Enable" mask="0x400"/>
+          <bitfield name="CMP3" caption="Compare 3 Interrupt Enable" mask="0x800"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="PER0" caption="Periodic Interval 0 Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Enable" mask="0x80"/>
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="ALARM1" caption="Alarm 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x200"/>
+          <bitfield name="CMP2" caption="Compare 2" mask="0x400"/>
+          <bitfield name="CMP3" caption="Compare 3" mask="0x800"/>
+          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x100"/>
+          <bitfield name="ALARM1" caption="Alarm 1" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
+        </register>
+        <register name="DBGCTRL" offset="0xE" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register modes="MODE0" name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE0 Synchronization Busy Status">
+          <bitfield name="SWRST" caption="Software Reset Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
+          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
+          <bitfield name="COUNT" caption="COUNT Register Busy" mask="0x8"/>
+          <bitfield name="COMP0" caption="COMP 0 Register Busy" mask="0x20"/>
+          <bitfield name="COMP1" caption="COMP 1 Register Busy" mask="0x40"/>
+          <bitfield name="COUNTSYNC" caption="Count Synchronization Enable Bit Busy" mask="0x8000"/>
+          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
+          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
+          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
+          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
+        </register>
+        <register modes="MODE1" name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE1 Synchronization Busy Status">
+          <bitfield name="SWRST" caption="Software Reset Bit Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
+          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
+          <bitfield name="COUNT" caption="COUNT Register Busy" mask="0x8"/>
+          <bitfield name="PER" caption="PER Register Busy" mask="0x10"/>
+          <bitfield name="COMP0" caption="COMP 0 Register Busy" mask="0x20"/>
+          <bitfield name="COMP1" caption="COMP 1 Register Busy" mask="0x40"/>
+          <bitfield name="COMP2" caption="COMP 2 Register Busy" mask="0x80"/>
+          <bitfield name="COMP3" caption="COMP 3 Register Busy" mask="0x100"/>
+          <bitfield name="COUNTSYNC" caption="Count Synchronization Enable Bit Busy" mask="0x8000"/>
+          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
+          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
+          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
+          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
+        </register>
+        <register modes="MODE2" name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE2 Synchronization Busy Status">
+          <bitfield name="SWRST" caption="Software Reset Bit Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
+          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
+          <bitfield name="CLOCK" caption="CLOCK Register Busy" mask="0x8"/>
+          <bitfield name="ALARM0" caption="ALARM 0 Register Busy" mask="0x20"/>
+          <bitfield name="ALARM1" caption="ALARM 1 Register Busy" mask="0x40"/>
+          <bitfield name="MASK0" caption="MASK 0 Register Busy" mask="0x800"/>
+          <bitfield name="MASK1" caption="MASK 1 Register Busy" mask="0x1000"/>
+          <bitfield name="CLOCKSYNC" caption="Clock Synchronization Enable Bit Busy" mask="0x8000"/>
+          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
+          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
+          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
+          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
+        </register>
+        <register name="FREQCORR" offset="0x14" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register modes="MODE0" name="COUNT" offset="0x18" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="MODE1" name="COUNT" offset="0x18" rw="RW" access="RSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register modes="MODE2" name="CLOCK" offset="0x18" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register modes="MODE1" name="PER" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register modes="MODE0" name="COMP" offset="0x20" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="MODE1" name="COMP" offset="0x20" rw="RW" access="WSYNC" size="2" count="4" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+        <register-group modes="MODE2" name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x20" size="0x8" count="2"/>
+        <register name="GP" offset="0x40" rw="RW" access="WSYNC" size="4" count="4" initval="0x00000000" caption="General Purpose">
+          <bitfield name="GP" caption="General Purpose" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TAMPCTRL" offset="0x60" rw="RW" size="4" initval="0x00000000" caption="Tamper Control">
+          <bitfield name="IN0ACT" caption="Tamper Input 0 Action" mask="0x3" values="TAMPCTRL__IN0ACT"/>
+          <bitfield name="IN1ACT" caption="Tamper Input 1 Action" mask="0xC" values="TAMPCTRL__IN1ACT"/>
+          <bitfield name="IN2ACT" caption="Tamper Input 2 Action" mask="0x30" values="TAMPCTRL__IN2ACT"/>
+          <bitfield name="IN3ACT" caption="Tamper Input 3 Action" mask="0xC0" values="TAMPCTRL__IN3ACT"/>
+          <bitfield name="IN4ACT" caption="Tamper Input 4 Action" mask="0x300" values="TAMPCTRL__IN4ACT"/>
+          <bitfield name="IN5ACT" caption="Tamper Input 5 Action" mask="0xC00" values="TAMPCTRL__IN5ACT"/>
+          <bitfield name="IN6ACT" caption="Tamper Input 6 Action" mask="0x3000" values="TAMPCTRL__IN6ACT"/>
+          <bitfield name="IN7ACT" caption="Tamper Input 7 Action" mask="0xC000" values="TAMPCTRL__IN7ACT"/>
+          <bitfield name="TAMLVL0" caption="Tamper Level Select 0" mask="0x10000"/>
+          <bitfield name="TAMLVL1" caption="Tamper Level Select 1" mask="0x20000"/>
+          <bitfield name="TAMLVL2" caption="Tamper Level Select 2" mask="0x40000"/>
+          <bitfield name="TAMLVL3" caption="Tamper Level Select 3" mask="0x80000"/>
+          <bitfield name="TAMLVL4" caption="Tamper Level Select 4" mask="0x100000"/>
+          <bitfield name="TAMLVL5" caption="Tamper Level Select 5" mask="0x200000"/>
+          <bitfield name="TAMLVL6" caption="Tamper Level Select 6" mask="0x400000"/>
+          <bitfield name="TAMLVL7" caption="Tamper Level Select 7" mask="0x800000"/>
+          <bitfield name="DEBNC0" caption="Debouncer Enable 0" mask="0x1000000"/>
+          <bitfield name="DEBNC1" caption="Debouncer Enable 1" mask="0x2000000"/>
+          <bitfield name="DEBNC2" caption="Debouncer Enable 2" mask="0x4000000"/>
+          <bitfield name="DEBNC3" caption="Debouncer Enable 3" mask="0x8000000"/>
+          <bitfield name="DEBNC4" caption="Debouncer Enable 4" mask="0x10000000"/>
+          <bitfield name="DEBNC5" caption="Debouncer Enable 5" mask="0x20000000"/>
+          <bitfield name="DEBNC6" caption="Debouncer Enable 6" mask="0x40000000"/>
+          <bitfield name="DEBNC7" caption="Debouncer Enable 7" mask="0x80000000"/>
+        </register>
+        <register modes="MODE0" name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" ocd-rw="" size="4" initval="0x00000000" caption="MODE0 Timestamp">
+          <bitfield name="COUNT" caption="Count Timestamp Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="MODE1" name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" ocd-rw="" size="4" initval="0x00000000" caption="MODE1 Timestamp">
+          <bitfield name="COUNT" caption="Count Timestamp Value" mask="0xFFFF"/>
+        </register>
+        <register modes="MODE2" name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" ocd-rw="" size="4" initval="0x00000000" caption="MODE2 Timestamp">
+          <bitfield name="SECOND" caption="Second Timestamp Value" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute Timestamp Value" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour Timestamp Value" mask="0x1F000"/>
+          <bitfield name="DAY" caption="Day Timestamp Value" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month Timestamp Value" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year Timestamp Value" mask="0xFC000000"/>
+        </register>
+        <register name="TAMPID" offset="0x68" rw="RW" size="4" atomic-op="clear:TAMPID" initval="0x00000000" caption="Tamper ID">
+          <bitfield name="TAMPID0" caption="Tamper Input 0 Detected" mask="0x1"/>
+          <bitfield name="TAMPID1" caption="Tamper Input 1 Detected" mask="0x2"/>
+          <bitfield name="TAMPID2" caption="Tamper Input 2 Detected" mask="0x4"/>
+          <bitfield name="TAMPID3" caption="Tamper Input 3 Detected" mask="0x8"/>
+          <bitfield name="TAMPID4" caption="Tamper Input 4 Detected" mask="0x10"/>
+          <bitfield name="TAMPID5" caption="Tamper Input 5 Detected" mask="0x20"/>
+          <bitfield name="TAMPID6" caption="Tamper Input 6 Detected" mask="0x40"/>
+          <bitfield name="TAMPID7" caption="Tamper Input 7 Detected" mask="0x80"/>
+          <bitfield name="TAMPEVT" caption="Tamper Event Detected" mask="0x80000000"/>
+        </register>
+        <register name="TAMPCTRLB" offset="0x6C" rw="RW" size="4" initval="0x00000000" caption="Tamper Control B">
+          <bitfield name="ALSI0" caption="Active Layer Select Internal 0" mask="0x1"/>
+          <bitfield name="ALSI1" caption="Active Layer Select Internal 1" mask="0x2"/>
+          <bitfield name="ALSI2" caption="Active Layer Select Internal 2" mask="0x4"/>
+          <bitfield name="ALSI3" caption="Active Layer Select Internal 3" mask="0x8"/>
+          <bitfield name="ALSI4" caption="Active Layer Select Internal 4" mask="0x10"/>
+          <bitfield name="ALSI5" caption="Active Layer Select Internal 5" mask="0x20"/>
+          <bitfield name="ALSI6" caption="Active Layer Select Internal 6" mask="0x40"/>
+          <bitfield name="ALSI7" caption="Active Layer Select Internal 7" mask="0x80"/>
+        </register>
+      </register-group>
+      <value-group name="MODE2_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="MODE2_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+      <value-group name="MODE0_CTRLA__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="MODE0_CTRLA__PRESCALER">
+        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x1"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x2"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x3"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x4"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x5"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x6"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x7"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x8"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x9"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
+      </value-group>
+      <value-group name="MODE1_CTRLA__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="2"/>
+      </value-group>
+      <value-group name="MODE1_CTRLA__PRESCALER">
+        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0"/>
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="1"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="2"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="3"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="4"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="5"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="6"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="7"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="8"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="9"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
+      </value-group>
+      <value-group name="MODE2_CTRLA__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="2"/>
+      </value-group>
+      <value-group name="MODE2_CTRLA__PRESCALER">
+        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x1"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x2"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x3"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x4"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x5"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x6"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x7"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x8"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x9"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
+      </value-group>
+      <value-group name="MODE0_CTRLB__DEBF">
+        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE0_CTRLB__ACTF">
+        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE1_CTRLB__DEBF">
+        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE1_CTRLB__ACTF">
+        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE2_CTRLB__DEBF">
+        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE2_CTRLB__ACTF">
+        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN0ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN1ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN2ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN3ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN4ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN4 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN5ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN5 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN6ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN6 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN7ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN7 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+    </module>
+    <module name="SAU" id="SYSTEM_IP" version="1.0.0" caption="Security Attribution Unit">
+      <register-group name="SAU" caption="Security Attribution Unit">
+        <register name="SAU_CTRL" offset="0x0" rw="RW" size="4" access-size="4" caption="SAU Control Register">
+          <bitfield name="ENABLE" caption="SAU enable" mask="0x1"/>
+          <bitfield name="ALLNS" caption="All Non-secure" mask="0x2"/>
+        </register>
+        <register name="SAU_TYPE" offset="0x4" rw="R" size="4" access-size="4" caption="SAU Type Register">
+          <bitfield name="SREGION" caption="Number of SAU regions" mask="0xFF"/>
+        </register>
+        <register name="SAU_RNR" offset="0x8" rw="RW" size="4" access-size="4" caption="SAU Region Number Register">
+          <bitfield name="REGION" caption="Selected SAU region number" mask="0xFF"/>
+        </register>
+        <register name="SAU_RBAR" offset="0xC" rw="RW" size="4" access-size="4" caption="SAU Region Base Address Register">
+          <bitfield name="BADDR" caption="Base address" mask="0xFFFFFFE0"/>
+        </register>
+        <register name="SAU_RLAR" offset="0x10" rw="RW" size="4" access-size="4" caption="SAU Region Limit Address Register">
+          <bitfield name="ENABLE" caption="SAU region enable" mask="0x1"/>
+          <bitfield name="NSC" caption="Non-secure callable region" mask="0x2"/>
+          <bitfield name="LADDR" caption="Limit address" mask="0xFFFFFFE0"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="SCB" id="SYSTEM_IP" version="1.0.0" caption="System Control Block">
+      <register-group name="SCB" caption="System Control Block">
+        <register name="CPUID" offset="0x0" rw="R" size="4" access-size="4" caption="CPUID base register">
+          <bitfield name="Revision" caption="Revision number" mask="0xF"/>
+          <bitfield name="PartNo" caption="Part number, 0xD20=Cortex-M23" mask="0xFFF0"/>
+          <bitfield name="Architecture" caption="Architecture version, 0xC=ARMv8-M Base Line, 0xF=ARMv8-M Main Line" mask="0xF0000"/>
+          <bitfield name="Variant" caption="Variant number" mask="0xF00000"/>
+          <bitfield name="Implementer" caption="Implementer code, ARM=0x41" mask="0xFF000000"/>
+        </register>
+        <register name="ICSR" offset="0x4" rw="RW" size="4" access-size="4" caption="Interrupt Control and State Register">
+          <bitfield name="VECTACTIVE" caption="Vector active" mask="0x1FF"/>
+          <bitfield name="RETTOBASE" caption="Return to base" mask="0x800"/>
+          <bitfield name="VECTPENDING" caption="Vector pending" mask="0x1FF000"/>
+          <bitfield name="ISRPENDING" caption="Interrupt pending" mask="0x400000"/>
+          <bitfield name="ISRPREEMPT" caption="Interrupt preempt" mask="0x800000"/>
+          <bitfield name="PENDSTCLR" caption="Pend SysTick clear" mask="0x2000000" values="ICSR__PENDSTCLR"/>
+          <bitfield name="PENDSTSET" caption="Pend SysTick set" mask="0x4000000" values="ICSR__PENDSTSET"/>
+          <bitfield name="PENDSVCLR" caption="Pend PendSV clear" mask="0x8000000" values="ICSR__PENDSVCLR"/>
+          <bitfield name="PENDSVSET" caption="Pend PendSV set" mask="0x10000000" values="ICSR__PENDSVSET"/>
+          <bitfield name="PENDNMICLR" caption="Pend NMI clear" mask="0x40000000"/>
+          <bitfield name="PENDNMISET" caption="Pend NMI set" mask="0x80000000" values="ICSR__PENDNMISET"/>
+        </register>
+        <register name="VTOR" offset="0x8" rw="RW" size="4" access-size="4" caption="Vector Table Offset Register">
+          <bitfield name="TBLOFF" caption="Vector table base offset" mask="0xFFFFFF80"/>
+        </register>
+        <register name="AIRCR" offset="0xC" rw="RW" size="4" access-size="4" caption="Application Interrupt and Reset Control Register">
+          <bitfield name="VECTCLRACTIVE" caption="Debug: Clear Active State" mask="0x2" values="AIRCR__VECTCLRACTIVE"/>
+          <bitfield name="SYSRESETREQ" caption="System Reset Request" mask="0x4" values="AIRCR__SYSRESETREQ"/>
+          <bitfield name="SYSRESETREQS" caption="System Reset Request Secure only" mask="0x8" values="AIRCR__SYSRESETREQS"/>
+          <bitfield name="BFHFNMINS" caption="BusFault, HardFault and NMI Non-secure enable" mask="0x2000" values="AIRCR__BFHFNMINS"/>
+          <bitfield name="PRIS" caption="Prioritize Secure Exceptions" mask="0x4000" values="AIRCR__PRIS"/>
+          <bitfield name="ENDIANNESS" caption="Data Endianness, 0=little, 1=big" mask="0x8000" values="AIRCR__ENDIANNESS"/>
+          <bitfield name="VECTKEY" caption="Register Key (0x05FA)" mask="0xFFFF0000"/>
+        </register>
+        <register name="SCR" offset="0x10" rw="RW" size="4" access-size="4" caption="System Control Register">
+          <bitfield name="SLEEPONEXIT" caption="Sleep on exit" mask="0x2" values="SCR__SLEEPONEXIT"/>
+          <bitfield name="SLEEPDEEP" caption="Sleep deep" mask="0x4" values="SCR__SLEEPDEEP"/>
+          <bitfield name="SLEEPDEEPS" caption="Sleep deep secure" mask="0x8"/>
+          <bitfield name="SEVONPEND" caption="Send Event on Pending bit" mask="0x10" values="SCR__SEVONPEND"/>
+        </register>
+        <register name="CCR" offset="0x14" rw="RW" size="4" access-size="4" caption="Configuration and Control Register">
+          <bitfield name="USERSETMPEND" caption="User set main pending" mask="0x2"/>
+          <bitfield name="UNALIGN_TRP" caption="Unaligned trap" mask="0x8" values="CCR__UNALIGN_TRP"/>
+          <bitfield name="DIV_0_TRP" caption="Divide by zero trap" mask="0x10"/>
+          <bitfield name="BFHFNMIGN" caption="BusFault in HardFault or NMI ignore" mask="0x100"/>
+          <bitfield name="STKOFHFNMIGN" caption="Stack overflow in HardFault and NMI ignore" mask="0x400"/>
+          <bitfield name="DC" caption="Data cache enable" mask="0x10000"/>
+          <bitfield name="IC" caption="Instruction cache enable" mask="0x20000"/>
+          <bitfield name="BP" caption="Branch prediction enable" mask="0x40000"/>
+        </register>
+        <register name="SHPR2" offset="0x1C" rw="RW" size="4" access-size="4" caption="System Handler Priority Register 2">
+          <bitfield name="PRI_11" caption="Priority of system handler 11, SVCall" mask="0xFF000000"/>
+        </register>
+        <register name="SHPR3" offset="0x20" rw="RW" size="4" access-size="4" caption="System Handler Priority Register 3">
+          <bitfield name="PRI_12" caption="Priority of system handler 12, DebugMonitor" mask="0xFF"/>
+          <bitfield name="PRI_14" caption="Priority of system handler 14, PendSV" mask="0xFF0000"/>
+          <bitfield name="PRI_15" caption="Priority of system handler 15, SysTick" mask="0xFF000000"/>
+        </register>
+        <register name="SHCSR" offset="0x24" rw="RW" size="4" access-size="4" caption="System Handler Control and State Register">
+          <bitfield name="HARDFAULTACT" caption="HardFault exception active state" mask="0x4"/>
+          <bitfield name="NMIACT" caption="NMI exception active state" mask="0x20"/>
+          <bitfield name="SVCALLACT" caption="SVCall exception active state" mask="0x80"/>
+          <bitfield name="PENDSVACT" caption="PendSV exception active state" mask="0x400"/>
+          <bitfield name="SYSTICKACT" caption="SysTick exception active state" mask="0x800"/>
+          <bitfield name="SVCALLPENDED" caption="SVCall exception pended state" mask="0x8000"/>
+          <bitfield name="HARDFAULTPENDED" caption="HardFault exception pended state" mask="0x200000"/>
+        </register>
+        <register name="DFSR" offset="0x30" rw="RW" size="4" access-size="4" caption="Debug Fault Status Register">
+          <bitfield name="HALTED" caption="Halt or step event" mask="0x1"/>
+          <bitfield name="BKPT" caption="Breakpoint event" mask="0x2"/>
+          <bitfield name="DWTTRAP" caption="Watchpoint event" mask="0x4"/>
+          <bitfield name="VCATCH" caption="Vector Catch event" mask="0x8"/>
+          <bitfield name="EXTERNAL" caption="External event" mask="0x10"/>
+        </register>
+        <register name="AFSR" offset="0x3C" rw="RW" size="4" access-size="4" caption="Auxiliary Fault Status Register"/>
+        <register name="CLIDR" offset="0x78" rw="R" size="4" access-size="4" caption="Cache Level ID Register">
+          <bitfield name="Ctype1" caption="Cache type at level 1" mask="0x7" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype2" caption="Cache type at level 2" mask="0x38" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype3" caption="Cache type at level 3" mask="0x1C0" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype4" caption="Cache type at level 4" mask="0xE00" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype5" caption="Cache type at level 5" mask="0x7000" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype6" caption="Cache type at level 6" mask="0x38000" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype7" caption="Cache type at level 7" mask="0x1C0000" values="CLIDR__Ctype"/>
+          <bitfield name="LoUIS" caption="Level of Unification Inner Shareable" mask="0xE00000"/>
+          <bitfield name="LoC" caption="Level of Coherence" mask="0x7000000"/>
+          <bitfield name="LoUU" caption="Level of Unification Uniprocessor" mask="0x38000000"/>
+          <bitfield name="ICB" caption="Inner cache boundary" mask="0xC0000000" values="CLIDR__ICB"/>
+        </register>
+        <register name="CTR" offset="0x7C" rw="R" size="4" access-size="4" caption="Cache Type Register">
+          <bitfield name="IminLine" caption="Instruction cache minimum line length" mask="0xF"/>
+          <bitfield name="DminLine" caption="Data cache minimum line length" mask="0xF0000"/>
+          <bitfield name="ERG" caption="Exclusives Reservation Granule" mask="0xF00000"/>
+          <bitfield name="CWG" caption="Cache Write-back Granule" mask="0xF000000"/>
+          <bitfield name="Format" caption="Cache Type Register format" mask="0xE0000000" values="CTR__Format"/>
+        </register>
+        <register name="CCSIDR" offset="0x80" rw="R" size="4" access-size="4" caption="Current Cache Size ID register">
+          <bitfield name="LineSize" caption="log2(number of words per line) - 2" mask="0x7"/>
+          <bitfield name="Associativity" caption="Associativity - 1" mask="0x1FF8"/>
+          <bitfield name="NumSets" caption="Number of sets - 1" mask="0xFFFE000"/>
+          <bitfield name="WA" caption="Write-Allocate" mask="0x10000000"/>
+          <bitfield name="RA" caption="Read-Allocate" mask="0x20000000"/>
+          <bitfield name="WB" caption="Write-Back" mask="0x40000000"/>
+          <bitfield name="WT" caption="Write-Through" mask="0x80000000"/>
+        </register>
+        <register name="CSSELR" offset="0x84" rw="RW" size="4" access-size="4" caption="Cache Size Selection Register">
+          <bitfield name="InD" caption="Instruction not Data" mask="0x1"/>
+          <bitfield name="Level" caption="Cache level - 1" mask="0xE"/>
+        </register>
+      </register-group>
+      <value-group name="ICSR__PENDSTCLR">
+        <value name="VALUE_0" caption="No effect" value="0"/>
+        <value name="VALUE_1" caption="Removes the pending state from the SysTick exception" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDSTSET">
+        <value name="VALUE_0" caption="Write: no effect; read: SysTick exception is not pending" value="0"/>
+        <value name="VALUE_1" caption="Write: changes SysTick exception state to pending; read: SysTick exception is pending" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDSVCLR">
+        <value name="VALUE_0" caption="No effect" value="0"/>
+        <value name="VALUE_1" caption="Removes the pending state from the PendSV exception" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDSVSET">
+        <value name="VALUE_0" caption="Write: no effect; read: PendSV exception is not pending" value="0"/>
+        <value name="VALUE_1" caption="Write: changes PendSV exception state to pending; read: PendSV exception is pending" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDNMISET">
+        <value name="VALUE_0" caption="Write: no effect; read: NMI exception is not pending" value="0"/>
+        <value name="VALUE_1" caption="Write: changes NMI exception state to pending; read: NMI exception is pending" value="1"/>
+      </value-group>
+      <value-group name="AIRCR__VECTCLRACTIVE">
+        <value name="NO" caption="Do not clear active state" value="0x0"/>
+        <value name="YES" caption="Clear active state" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__SYSRESETREQ">
+        <value name="NO" caption="Do not request a system reset" value="0"/>
+        <value name="YES" caption="Request a system reset" value="1"/>
+      </value-group>
+      <value-group name="AIRCR__SYSRESETREQS">
+        <value name="BOTH" caption="SYSRESETREQ functionality is available to both Security states" value="0x0"/>
+        <value name="SECURE" caption="SYSRESETREQ functionality is only available to Secure state" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__BFHFNMINS">
+        <value name="SECURE" caption="BusFault, HardFault, and NMI are Secure" value="0x0"/>
+        <value name="NON_SECURE" caption="BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__PRIS">
+        <value name="SAME" caption="Priority ranges of Secure and Non-secure exceptions are identical" value="0x0"/>
+        <value name="NS_DEPRIO" caption="Non-secure exceptions are de-prioritized" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__ENDIANNESS">
+        <value name="LITTLE" caption="Little-endian" value="0"/>
+        <value name="BIG" caption="Big-endian" value="1"/>
+      </value-group>
+      <value-group name="SCR__SLEEPONEXIT">
+        <value name="VALUE_0" caption="O not sleep when returning to Thread mode" value="0"/>
+        <value name="VALUE_1" caption="Enter sleep, or deep sleep, on return from an ISR" value="1"/>
+      </value-group>
+      <value-group name="SCR__SLEEPDEEP">
+        <value name="VALUE_0" caption="Sleep" value="0"/>
+        <value name="VALUE_1" caption="Deep sleep" value="1"/>
+      </value-group>
+      <value-group name="SCR__SEVONPEND">
+        <value name="VALUE_0" caption="Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded" value="0"/>
+        <value name="VALUE_1" caption="Enabled events and all interrupts, including disabled interrupts, can wakeup the processor" value="1"/>
+      </value-group>
+      <value-group name="CCR__UNALIGN_TRP">
+        <value name="VALUE_0" caption="Do not trap unaligned halfword and word accesses" value="0"/>
+        <value name="VALUE_1" caption="Trap unaligned halfword and word accesses" value="1"/>
+      </value-group>
+      <value-group name="CLIDR__Ctype">
+        <value name="NO" caption="No cache" value="0"/>
+        <value name="IC" caption="Instruction cache only" value="1"/>
+        <value name="DC" caption="Data cache only" value="2"/>
+        <value name="SEPARATE" caption="Separate instruction and data caches" value="3"/>
+        <value name="UNIFIED" caption="Unified cache" value="4"/>
+      </value-group>
+      <value-group name="CLIDR__ICB">
+        <value name="NO" caption="Not disclosed in this mechanism" value="0"/>
+        <value name="L1" caption="L1 cache is the highest inner level" value="1"/>
+        <value name="L2" caption="L2 cache is the highest inner level" value="2"/>
+        <value name="L3" caption="L3 cache is the highest inner level" value="3"/>
+      </value-group>
+      <value-group name="CTR__Format">
+        <value name="NO" caption="No cache type information provided" value="0"/>
+        <value name="YES" caption="Cache type information is provided" value="4"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="03715" name2="com_sercom_u2201_v6" version="6c0" caption="Serial Communication Interface">
+      <register-group name="SERCOM" caption="Serial Communication Interface">
+        <mode name="I2CM" qualifier="SERCOM.I2CM_CTRLA.MODE" value="5" caption="I2C Master Mode"/>
+        <mode name="I2CS" qualifier="SERCOM.I2CS_CTRLA.MODE" value="4" caption="I2C Slave Mode"/>
+        <mode name="SPI" qualifier="SERCOM.SPI_CTRLA.MODE" mask="6" value="2" caption="SPI Mode"/>
+        <mode name="USART" qualifier="SERCOM.USART_CTRLA.MODE" mask="6" value="0" caption="USART Mode"/>
+        <register modes="I2CM" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="FILTSEL" caption="Input Filter Selection" mask="0x300" values="I2CM_CTRLA__FILTSEL"/>
+          <bitfield name="SLEWRATE" caption="Slew Rate Selection" mask="0xC00" values="I2CM_CTRLA__SLEWRATE"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SMBUSEN" caption="SMBUS Input Buffer Enable" mask="0x20000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000" values="I2CM_CTRLA__SDAHOLD"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000" values="I2CM_CTRLA__SPEED"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000" values="I2CM_CTRLA__INACTOUT"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register modes="I2CS" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="FILTSEL" caption="Input Filter Selection" mask="0x300"/>
+          <bitfield name="SLEWRATE" caption="Slew Rate Selection" mask="0xC00" values="I2CS_CTRLA__SLEWRATE"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SMBUSEN" caption="SMBUS Input Buffer Enable" mask="0x20000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000" values="I2CS_CTRLA__SDAHOLD"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000" values="I2CS_CTRLA__SPEED"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register modes="SPI" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000" values="SPI_CTRLA__DOPO"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000" values="SPI_CTRLA__DIPO"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000" values="SPI_CTRLA__FORM"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000" values="SPI_CTRLA__CPHA"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000" values="SPI_CTRLA__CPOL"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000" values="SPI_CTRLA__DORD"/>
+        </register>
+        <register modes="USART" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="TXINV" caption="Transmit Data Invert" mask="0x200" values="USART_CTRLA__TXINV"/>
+          <bitfield name="RXINV" caption="Receive Data Invert" mask="0x400" values="USART_CTRLA__RXINV"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000" values="USART_CTRLA__SAMPR"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000" values="USART_CTRLA__TXPO"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000" values="USART_CTRLA__RXPO"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000" values="USART_CTRLA__FORM"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000" values="USART_CTRLA__CMODE"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000" values="USART_CTRLA__DORD"/>
+        </register>
+        <register modes="I2CM" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="I2CM_CTRLB__FIFOCLR"/>
+        </register>
+        <register modes="I2CS" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000" values="I2CS_CTRLB__AMODE"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="I2CS_CTRLB__FIFOCLR"/>
+        </register>
+        <register modes="SPI" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7" values="SPI_CTRLB__CHSIZE"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200" values="SPI_CTRLB__SSDE"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000" values="SPI_CTRLB__MSSEN"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000" values="SPI_CTRLB__AMODE"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="SPI_CTRLB__FIFOCLR"/>
+        </register>
+        <register modes="USART" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7" values="USART_CTRLB__CHSIZE"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40" values="USART_CTRLB__SBMODE"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400" values="USART_CTRLB__ENC"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000" values="USART_CTRLB__PMODE"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="USART_CTRLB__FIFOCLR"/>
+          <bitfield name="LINCMD" caption="LIN Command" mask="0x3000000" values="USART_CTRLB__LINCMD"/>
+        </register>
+        <register modes="I2CM" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="I2CM Control C">
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="I2CM_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="I2CM_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="I2CS" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="I2CS Control C">
+          <bitfield name="SDASETUP" caption="SDA Setup Time" mask="0xF"/>
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="I2CS_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="I2CS_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="SPI" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="SPI Control C">
+          <bitfield name="ICSPACE" caption="Inter-Character Spacing" mask="0x3F"/>
+          <bitfield name="FSES" caption="Frame Synch Edge Select" mask="0x100"/>
+          <bitfield name="FSLEN" caption="Frame Synch Length" mask="0x200" values="SPI_CTRLC__FSLEN"/>
+          <bitfield name="FSPOL" caption="Frame Synch Polarity" mask="0x400" values="SPI_CTRLC__FSPOL"/>
+          <bitfield name="IGNTUR" caption="Ignore Transmit Underrun" mask="0x800"/>
+          <bitfield name="FRMEN" caption="Frame mode enable" mask="0x10000"/>
+          <bitfield name="FMODE" caption="Frame mode" mask="0x20000" values="SPI_CTRLC__FMODE"/>
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="SPI_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="SPI_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="USART" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="USART Control C">
+          <bitfield name="GTIME" caption="Guard Time" mask="0x7"/>
+          <bitfield name="BRKLEN" caption="LIN Master Break Length" mask="0x300" values="USART_CTRLC__BRKLEN"/>
+          <bitfield name="HDRDLY" caption="LIN Master Header Delay" mask="0xC00" values="USART_CTRLC__HDRDLY"/>
+          <bitfield name="INACK" caption="Inhibit Not Acknowledge" mask="0x10000"/>
+          <bitfield name="DSNACK" caption="Disable Successive NACK" mask="0x20000"/>
+          <bitfield name="MAXITER" caption="Maximum Iterations" mask="0x700000"/>
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x3000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="USART_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="USART_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="I2CM" name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register modes="SPI" name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register modes="USART" name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT" qualifier="SERCOM.USART.CTRLA.FORM" value="0" caption="Default"/>
+          <mode name="FRAC" qualifier="SERCOM.USART.CTRLA.FORM" value="4" caption="Fractional Baud mode"/>
+          <mode name="FRACFP" qualifier="SERCOM.USART.CTRLA.FORM" value="5" caption="Fractional Baud with Parity mode"/>
+          <mode name="USARTFP" qualifier="SERCOM.USART.CTRLA.FORM" value="1" caption="USART Frame with Parity mode"/>
+          <bitfield modes="FRAC FRACFP" name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+          <bitfield modes="FRAC FRACFP" name="FP" caption="Fractional Part" mask="0xE000"/>
+          <bitfield modes="DEFAULT USARTFP" name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+        </register>
+        <register modes="USART" name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register modes="I2CM" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Disable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="I2CS" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Disable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="SPI" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="USART" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Enable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="I2CS" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Enable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="SPI" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="USART" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="I2CS" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="SPI" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="USART" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="STATUS" offset="0x1A" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register modes="I2CS" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+          <bitfield name="LENERR" caption="Transaction Length Error" mask="0x800"/>
+        </register>
+        <register modes="SPI" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="TUR" caption="Frame Transmit Underrun" mask="0x8"/>
+          <bitfield name="LENERR" caption="Transaction Length Error" mask="0x800"/>
+        </register>
+        <register modes="USART" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+          <bitfield name="TXE" caption="Transmitter Empty" mask="0x40"/>
+          <bitfield name="ITER" caption="Maximum Number of Repetitions Reached" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+          <bitfield name="LENGTH" caption="Length Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="I2CS" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+          <bitfield name="LENGTH" caption="Length Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="SPI" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+          <bitfield name="LENGTH" caption="LENGTH Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="USART" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+          <bitfield name="RXERRCNT" caption="RXERRCNT Synchronization Busy" mask="0x8"/>
+          <bitfield name="LENGTH" caption="LENGTH Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="USART" name="RXERRCNT" offset="0x20" rw="R" access="RSYNC" size="1" initval="0x00" caption="USART Receive Error Count"/>
+        <register modes="I2CS" name="LENGTH" offset="0x22" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="I2CS Length">
+          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
+          <bitfield name="LENEN" caption="Data Length Enable" mask="0x100"/>
+        </register>
+        <register modes="SPI" name="LENGTH" offset="0x22" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="SPI Length">
+          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
+          <bitfield name="LENEN" caption="Data Length Enable" mask="0x100"/>
+        </register>
+        <register modes="USART" name="LENGTH" offset="0x22" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="USART Length">
+          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
+          <bitfield name="LENEN" caption="Data Length Enable" mask="0x300" values="USART_LENGTH__LENEN"/>
+        </register>
+        <register modes="I2CM" name="ADDR" offset="0x24" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register modes="I2CS" name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register modes="SPI" name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register modes="I2CM" name="DATA" offset="0x28" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="I2CS" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="SPI" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="USART" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="I2CM" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+        <register modes="SPI" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+        <register modes="USART" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+        <register modes="I2CM" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="I2CM FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="I2CS" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="I2CS FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="SPI" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="SPI FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="USART" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="USART FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="I2CM" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="I2CM FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+        <register modes="I2CS" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="I2CS FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+        <register modes="SPI" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="SPI FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+        <register modes="USART" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="USART FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+      </register-group>
+      <value-group name="I2CM_CTRLA__MODE">
+        <value name="I2C_MASTER" caption="I2C host mode operation" value="5"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__FILTSEL">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="50NS" caption="Minimum 50ns filter" value="0x2"/>
+        <value name="10NS" caption="Minimum 10ns filter" value="0x3"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__SLEWRATE">
+        <value name="SMM" caption="Standard mode" value="0x0"/>
+        <value name="FM" caption="Fast mode" value="0x1"/>
+        <value name="FMP" caption="Fast mode plus" value="0x2"/>
+        <value name="HS" caption="High-speed mode" value="0x3"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__SDAHOLD">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="75NS" caption="50ns - 100ns hold time" value="0x1"/>
+        <value name="450NS" caption="300ns - 600ns hold time" value="0x2"/>
+        <value name="600NS" caption="400ns - 800ns hold time" value="0x3"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__SPEED">
+        <value name="SM" caption="Standard-Mode (SM) and Fast-Mode (FM)" value="0x0"/>
+        <value name="FMP" caption="Fast-Mode Plus (FM+)" value="0x1"/>
+        <value name="HS" caption="High-Speed Mode" value="0x2"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__INACTOUT">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="55US" caption="5-6 SCL cycle time-out" value="0x1"/>
+        <value name="105US" caption="10-11 SCL cycle time-out" value="0x2"/>
+        <value name="205US" caption="20-21-6 SCL cycle time-out" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__MODE">
+        <value name="I2C_SLAVE" caption="I2C client mode operation" value="0x4"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__SLEWRATE">
+        <value name="SM" caption="Standard mode" value="0x0"/>
+        <value name="FM" caption="Fast mode" value="0x1"/>
+        <value name="FMP" caption="Fast mode plus" value="0x2"/>
+        <value name="HS" caption="High-speed mode" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__SDAHOLD">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="75NS" caption="50ns - 100ns hold time" value="0x1"/>
+        <value name="450NS" caption="300ns - 600ns hold time" value="0x2"/>
+        <value name="600NS" caption="400ns - 800ns hold time" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__SPEED">
+        <value name="SM" caption="Standard-Mode (SM) and Fast-Mode (FM)" value="0x0"/>
+        <value name="FMP" caption="Fast-Mode Plus (FM+)" value="0x1"/>
+        <value name="HS" caption="High-Speed Mode" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__MODE">
+        <value name="SLAVE" caption="SPI slave operation" value="0x2"/>
+        <value name="MASTER" caption="SPI master operation" value="0x3"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__DOPO">
+        <value name="PAD0" caption="DO on PAD[0], SCK on PAD[1] and SS on PAD[2]" value="0x0"/>
+        <value name="PAD3" caption="DO on PAD[3], SCK on PAD[1] and SS on PAD[2]" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__DIPO">
+        <value name="PAD0" caption="SERCOM PAD0 is used as data input" value="0x0"/>
+        <value name="PAD1" caption="SERCOM PAD1 is used as data input" value="0x1"/>
+        <value name="PAD2" caption="SERCOM PAD2 is used as data input" value="0x2"/>
+        <value name="PAD3" caption="SERCOM PAD3 is used as data input" value="0x3"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__FORM">
+        <value name="SPI" caption="SPI frame" value="0x0"/>
+        <value name="ADDR" caption="SPI frame with address" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__CPHA">
+        <value name="LEADING_EDGE" caption="The data is sampled on a leading SCK edge and changed on a trailing SCK edge" value="0x0"/>
+        <value name="TRAILING_EDGE" caption="The data is sampled on a trailing SCK edge and changed on a leading SCK edge" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__CPOL">
+        <value name="LOW" caption="SCK is low when idle" value="0x0"/>
+        <value name="HIGH" caption="SCK is high when idle" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__DORD">
+        <value name="MSB" caption="MSB is transmitted first" value="0x0"/>
+        <value name="LSB" caption="LSB is transmitted first" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__MODE">
+        <value name="EXTCLK" caption="USART with external clock" value="0x0"/>
+        <value name="INTCLK" caption="Usart with internal clock" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__TXINV">
+        <value name="DISABLE" caption="TxD is not inverted" value="0x0"/>
+        <value name="INV" caption="TxD is inverted" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__RXINV">
+        <value name="DISABLE" caption="RxD is not inverted" value="0x0"/>
+        <value name="INV" caption="RxD is inverted" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__SAMPR">
+        <value name="ARITHM16X" caption="16x oversampling using arithmetic baud rate generation" value="0x0"/>
+        <value name="FRAC16X" caption="16x oversampling using fractional baud rate generation" value="0x1"/>
+        <value name="ARITHM8X" caption="8x oversampling using arithmetic baud rate generation" value="0x2"/>
+        <value name="FRAC8X" caption="8x oversampling using fractional baud rate generation" value="0x3"/>
+        <value name="ARITHM3X" caption="3x oversampling using arithmetic baud rate generation" value="0x4"/>
+      </value-group>
+      <value-group name="USART_CTRLA__TXPO">
+        <value name="PAD0" caption="PAD[0] = TxD; PAD[1] = XCK" value="0x0"/>
+        <value name="PAD2" caption="PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS" value="0x2"/>
+        <value name="PAD3" caption="PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLA__RXPO">
+        <value name="PAD0" caption="SERCOM PAD0 is used for data reception" value="0x0"/>
+        <value name="PAD1" caption="SERCOM PAD1 is used for data reception" value="0x1"/>
+        <value name="PAD2" caption="SERCOM PAD2 is used for data reception" value="0x2"/>
+        <value name="PAD3" caption="SERCOM PAD3 is used for data reception" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLA__FORM">
+        <value name="USART" caption="USART frame" value="0x0"/>
+        <value name="USARTP" caption="USART frame with parity" value="0x1"/>
+        <value name="LINBRKGEN" caption="LIN Master Break and Synck generation" value="0x2"/>
+        <value name="LINBRKDET" caption="LIN Slave break detection and auto-baud" value="0x4"/>
+        <value name="BRKDET" caption="Break detection and auto-baud with parity" value="0x5"/>
+      </value-group>
+      <value-group name="USART_CTRLA__CMODE">
+        <value name="ASYNC" caption="Asynchronous communication." value="0x0"/>
+        <value name="SYNC" caption="Synchronous communication." value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__DORD">
+        <value name="MSB" caption="MSB is transmitted first." value="0x0"/>
+        <value name="LSB" caption="LSB is transmitted first." value="0x1"/>
+      </value-group>
+      <value-group name="I2CM_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLB__AMODE">
+        <value name="MASK" caption="The slave responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK" value="0x0"/>
+        <value name="2ADDRS" caption="The slave responds to the two unique addresses in ADDR and ADDRMASK" value="0x1"/>
+        <value name="RANGE" caption="The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit" value="0x2"/>
+      </value-group>
+      <value-group name="I2CS_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__CHSIZE">
+        <value name="8BITS" caption="8-bits character" value="0x0"/>
+        <value name="9BITS" caption="9-bits character" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__SSDE">
+        <value name="DISABLE" caption="SS low detector is disabled" value="0x0"/>
+        <value name="ENABLE" caption="SS low detector is enabled" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__MSSEN">
+        <value name="DISABLE" caption="Hardware SS control is disabled" value="0x0"/>
+        <value name="ENABLE" caption="Hardware SS control is enabled" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__AMODE">
+        <value name="MASK" caption="ADDRMASK is used as a mask to the AADR register" value="0x0"/>
+        <value name="2ADDRS" caption="The slave responds to the two unique addresses in ADDR and ADDRMASK" value="0x1"/>
+        <value name="RANGE" caption="The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLB__CHSIZE">
+        <value name="8BITS" caption="8-bits character" value="0x0"/>
+        <value name="9BITS" caption="9-bits character" value="0x1"/>
+        <value name="5BITS" caption="5-bits character" value="0x5"/>
+        <value name="6BITS" caption="6-bits character" value="0x6"/>
+        <value name="7BITS" caption="7-bits character" value="0x7"/>
+      </value-group>
+      <value-group name="USART_CTRLB__SBMODE">
+        <value name="ONE" caption="One stop bit" value="0x0"/>
+        <value name="TWO" caption="Two stop bits" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLB__ENC">
+        <value name="DISABLE" caption="Data is not encoded" value="0x0"/>
+        <value name="IRDA" caption="Data is IrDA encoded" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLB__PMODE">
+        <value name="EVEN" caption="Even parity" value="0x0"/>
+        <value name="ODD" caption="Odd parity" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLB__LINCMD">
+        <value name="NONE" caption="Normal USART transmission" value="0x0"/>
+        <value name="SOFTWARE_CONTROL_TRANSMIT_CMD" caption="Break field is transmitted when DATA is written" value="0x1"/>
+        <value name="AUTO_TRANSMIT_CMD" caption="Break, synch and identifier are automaticcaly transmitted when DATA is written with the identifier" value="0x2"/>
+      </value-group>
+      <value-group name="I2CM_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="I2CM_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x2"/>
+      </value-group>
+      <value-group name="I2CS_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="I2CS_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__FSLEN">
+        <value name="STROBE" caption="One SCK pulse" value="0x0"/>
+        <value name="LEVEL" caption="One frame duration" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__FSPOL">
+        <value name="HIGH" caption="VCC-level valid polarity" value="0x0"/>
+        <value name="LOW" caption="GND-level valid polarity" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__FMODE">
+        <value name="MASTER" caption="Frame Master" value="0x0"/>
+        <value name="SLAVE" caption="Frame Slave" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated as long as the FIFO is empty" value="0x2"/>
+      </value-group>
+      <value-group name="USART_CTRLC__BRKLEN">
+        <value name="13BITS" caption="Break field transmission is 13 bit times" value="0x0"/>
+        <value name="17BITS" caption="Break field transmission is 17 bit times" value="0x1"/>
+        <value name="21BITS" caption="Break field transmission is 21 bit times" value="0x2"/>
+        <value name="26BITS" caption="Break field transmission is 26 bit times" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLC__HDRDLY">
+        <value name="1BIT" caption="Delay between break and sync transmission is 1-bit time" value="0x0"/>
+        <value name="4BITS" caption="Delay between break and sync transmission is 4-bit time" value="0x1"/>
+        <value name="8BITS" caption="Delay between break and sync transmission is 8-bit time" value="0x2"/>
+        <value name="14BITS" caption="Delay between break and sync transmission is 14-bit time" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="USART_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated when the FIFO is empty" value="0x2"/>
+      </value-group>
+      <value-group name="USART_LENGTH__LENEN">
+        <value name="DISABLE" caption="Length counter is disabled" value="0x0"/>
+        <value name="TX" caption="Length counter is enabled for transmit" value="0x1"/>
+        <value name="RX" caption="Length counter is enabled for receive" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="SUPC" id="03926" name2="pwr_rpmu_supc_v1" version="1c0" caption="Supply Controller">
+      <register-group name="SUPC" caption="Supply Controller">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="LVDET" caption="Low Voltage Detector Interrupt Enable" mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO Regulator Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Interrupt Enable" mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Interrupt Enable" mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="LVDET" caption="Low Voltage Detector Interrupt Enable" mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO Regulator Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Interrupt Enable" mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Interrupt Enable" mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="LVDET" caption="Low Voltage Detector Interrupt. Set to one if VDDIO crosses the treshold voltage in the good direction according to LVD.DIR." mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Interrupt. Set to one if LVD is ready to operate." mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO Regulator Ready Interrupt. Set to one if ULDO is ready meaning that output voltage is correct." mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Interrupt. Is set to one if overheat condition is detected." mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Interrupt. Set to one if VDDUSB issue is detected." mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct." mask="0x100"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Flag status">
+          <bitfield name="LVDET" caption="Low Voltage Detector Status." mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Status" mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO regulator Status. It corresponds to vreg_ready_mv signal from ULDO." mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Status. It corresponds to vreg_overheat_event_mv signal from ULDO." mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Status. One if VDDUSB is OK. It corresponds to bor_vddusb_n_mv signal of SMOR." mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator." mask="0x100"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Synchronisation Busy">
+          <bitfield name="BOR" caption="BOR Synchronization Busy" mask="0x1"/>
+        </register>
+        <register name="BOR" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="BOR Control">
+          <bitfield name="DCBORPSEL" caption="Duty Cycle BOR Prescaler Select" mask="0x70" values="BOR__DCBORPSEL"/>
+          <bitfield name="BORFILT" caption="BOR filtering" mask="0x300" values="BOR__BORFILT"/>
+        </register>
+        <register name="LVD" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="LVD Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="DIR" caption="Direction" mask="0x4" values="LVD__DIR"/>
+          <bitfield name="OEVEN" caption="Output Event Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x10"/>
+          <bitfield name="LEVEL" caption="Threshold Level. See &quot;pwr_smor_[nn]_v1 DOS&quot; - level section to get details." mask="0xF0000"/>
+        </register>
+        <register name="VREGCTRL" offset="0x1C" rw="RW" size="4" initval="0x00000004" caption="VREG Control">
+          <bitfield name="VREGOUT" caption="VREG Output Control in RUN mode only. Enable by production fuse by CALSUPC.VREGOUTEN" mask="0x3" values="VREGCTRL__VREGOUT"/>
+          <bitfield name="OFFSTDBY" caption="Off in Standby Control for VREGSW[N-1]. Useful for Riverside only." mask="0x4" values="VREGCTRL__OFFSTDBY"/>
+          <bitfield name="LVSTDBY" caption="Low Voltage Standby Enable" mask="0x10" values="VREGCTRL__LVSTDBY"/>
+          <bitfield name="LVHIB" caption="Low Voltage Hibernate Enable" mask="0x20" values="VREGCTRL__LVHIB"/>
+          <bitfield name="CPEN" caption="Charge Pump Enable and Auto-enable." mask="0x300"/>
+          <bitfield name="ULDOEN" caption="User LDO Voltage Regulator Enable" mask="0x1000"/>
+          <bitfield name="ULDOSTDBY" caption="User LDO Voltage Regulator Configuration" mask="0x2000" values="VREGCTRL__ULDOSTDBY"/>
+          <bitfield name="ULDOLEVEL" caption="User LDO Voltage Level Selection" mask="0xC000" values="VREGCTRL__ULDOLEVEL"/>
+          <bitfield name="AVREGEN" caption="Additional Voltage Regulator Enable" mask="0x10000"/>
+          <bitfield name="AVREGSTDBY" caption="Additional Voltage Regulator Configuration" mask="0x1000000" values="VREGCTRL__AVREGSTDBY"/>
+          <bitfield name="SRAM_VLD" caption="SRAM VALID Status Bit" mask="0x40000000"/>
+          <bitfield name="BKUP_VLD" caption="Backup Domain Valid Status Bit" mask="0x80000000"/>
+        </register>
+        <register name="VREFCTRL" offset="0x20" rw="RW" size="4" initval="0x00000002" caption="VREF Control">
+          <bitfield name="LPSTDBY" caption="Bandgap and Regulators Low Power Standby Enable" mask="0x1" values="VREFCTRL__LPSTDBY"/>
+          <bitfield name="LPHIB" caption="Bandgap and Regulators Low Power Hibernate Enable" mask="0x2" values="VREFCTRL__LPHIB"/>
+          <bitfield name="TSEN" caption="Temperature Sensor Output Enable" mask="0x10"/>
+        </register>
+        <register name="BKOUT" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="Backup Output Control">
+          <bitfield name="EN0" caption="Enable Output" mask="0x1"/>
+          <bitfield name="EN1" caption="Enable Output" mask="0x4"/>
+          <bitfield name="CLR0" caption="Clear Output" mask="0x100"/>
+          <bitfield name="CLR1" caption="Clear Output" mask="0x400"/>
+          <bitfield name="SET0" caption="Set Output" mask="0x10000"/>
+          <bitfield name="SET1" caption="Set Output" mask="0x40000"/>
+          <bitfield name="TGLOM0" caption="Toggle Output Mode" mask="0x3000000" values="BKOUT__TGLOM"/>
+          <bitfield name="TGLOM1" caption="Toggle Output Mode" mask="0xC000000" values="BKOUT__TGLOM"/>
+        </register>
+        <register name="BKIN" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Backup Input Control">
+          <bitfield name="BKIN" caption="Backup Input Value" mask="0x3"/>
+        </register>
+      </register-group>
+      <value-group name="BOR__DCBORPSEL">
+        <value name="NODIV" caption="Not Divided" value="0x0"/>
+        <value name="DIV2" caption="Divide clock by 2" value="0x1"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x2"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x3"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x4"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x5"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x6"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x7"/>
+      </value-group>
+      <value-group name="BOR__BORFILT">
+        <value name="NOFILT" caption="No digital filtering" value="0x0"/>
+        <value name="FILT32US" caption="32us filtering" value="0x1"/>
+        <value name="FILT125US" caption="125us filtering" value="0x2"/>
+        <value name="FILT250US" caption="250us filtering" value="0x3"/>
+      </value-group>
+      <value-group name="LVD__DIR">
+        <value name="rising" caption="Rising detection" value="0x0"/>
+        <value name="falling" caption="Falling detection" value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__VREGOUT">
+        <value name="1p2v" caption="In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.2v." value="0x0"/>
+        <value name="1p0v" caption="In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.0v." value="0x1"/>
+        <value name="0p8v" caption="In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 0.8v." value="0x2"/>
+      </value-group>
+      <value-group name="VREGCTRL__OFFSTDBY">
+        <value name="OFF" caption="In standby mode, VREGSW1,2,3 are OFF" value="0x0"/>
+        <value name="ON" caption="In standby mode, VREGSW1,2,3 are ON" value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__LVSTDBY">
+        <value name="1p2v" caption="In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 1.2v." value="0x0"/>
+        <value name="0p8v" caption="In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 0.8v." value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__LVHIB">
+        <value name="1p2v" caption="In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 1.2v." value="0x0"/>
+        <value name="0p8v" caption="In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 0.8v" value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__ULDOSTDBY">
+        <value name="OFFINSTDBY" caption="Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well." value="0x0"/>
+        <value name="ONINSTDBY" caption="Regulator is ON in Standby mode. is OFF from Hibernate mode. It is OFF in backup mode as well." value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__ULDOLEVEL">
+        <value name="1p2v" caption="Vout = 1.2v" value="0x0"/>
+        <value name="1p5v" caption="Vout = 1.5v" value="0x1"/>
+        <value name="1p8v" caption="Vout = 1.8v" value="0x2"/>
+        <value name="2p5v" caption="Vout = 2.5v" value="0x3"/>
+      </value-group>
+      <value-group name="VREGCTRL__AVREGSTDBY">
+        <value name="OFFINSTDBY" caption="Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well." value="0x0"/>
+        <value name="ONINSTDBY" caption="Regulator is ON in Standby mode if AVREGEN bit is set. is OFF from Hibernate mode. It is OFF in backup mode as well." value="0x1"/>
+      </value-group>
+      <value-group name="VREFCTRL__LPSTDBY">
+        <value name="FullPower" caption="In standby mode, bandgap and enabled regulator(s) are set to nominal power mode." value="0x0"/>
+        <value name="LowPower" caption="In standby mode, bandgap and enabled regulator(s) are set to low power mode." value="0x1"/>
+      </value-group>
+      <value-group name="VREFCTRL__LPHIB">
+        <value name="FullPower" caption="In hibernate mode, bandgap is set to nominal power mode. As a consequence, enabled regulator(s) are set to nominal power mode." value="0x0"/>
+        <value name="LowPower" caption="In hibernate mode, bandgap is set to low power mode. As a consequence, enabled regulator(s) are set to low power mode." value="0x1"/>
+      </value-group>
+      <value-group name="BKOUT__TGLOM">
+        <value name="DISABLE" caption="The output does not toggle." value="0x0"/>
+        <value name="RTCTGL" caption="The output toggles on RTC event." value="0x1"/>
+        <value name="BKUPTGL" caption="The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software." value="0x2"/>
+      </value-group>
+    </module>
+    <module name="SysTick" id="SYSTEM_IP" version="1.0.0" caption="SysTick Timer">
+      <register-group name="SysTick" caption="SysTick Timer">
+        <register name="SYST_CSR" offset="0x0" rw="RW" size="4" access-size="4" caption="SysTick Control and Status Register">
+          <bitfield name="ENABLE" caption="SysTick enable" mask="0x1"/>
+          <bitfield name="TICKINT" caption="Tick interrupt" mask="0x2"/>
+          <bitfield name="CLKSOURCE" caption="Clock source" mask="0x4"/>
+          <bitfield name="COUNTFLAG" caption="Count flag" mask="0x10000"/>
+        </register>
+        <register name="SYST_RVR" offset="0x4" rw="RW" size="4" access-size="4" caption="SysTick Reload Value Register">
+          <bitfield name="RELOAD" caption="Counter reload value" mask="0x1000000"/>
+        </register>
+        <register name="SYST_CVR" offset="0x8" rw="RW" size="4" access-size="4" caption="SysTick Current Value Register">
+          <bitfield name="CURRENT" caption="Current counter value" mask="0x1000000"/>
+        </register>
+        <register name="SYST_CALIB" offset="0xC" rw="R" size="4" access-size="4" caption="SysTick Calibration Value Register">
+          <bitfield name="TENMS" caption="Ten milliseconds" mask="0xFFFFFF"/>
+          <bitfield name="SKEW" caption="Skew" mask="0x40000000"/>
+          <bitfield name="NOREF" caption="No reference" mask="0x80000000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="TCC" id="03610" name2="tmr_tcc_u2213_v4" version="4d0" caption="Timer Counter for Control Applications">
+      <register-group name="TCC" caption="Timer Counter for Control Applications">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="MSYNC" caption="Master Synchronization (only for TCC Slave Instance)" mask="0x8000"/>
+          <bitfield name="FCYCLE" caption="Full Cycle" mask="0x10000"/>
+          <bitfield name="DMAOS" caption="DMA One-shot Trigger Mode" mask="0x800000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="RWSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period Busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKPRESC" caption="Fault A Blanking Prescaler" mask="0x8000"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKPRESC" caption="Fault B Blanking Prescaler" mask="0x8000"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="UFS" caption="Non-Recoverable Update Fault Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="UFS" caption="Non-Recoverable Update Fault Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="UFS" caption="Non-Recoverable Update Fault" mask="0x400"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" access="RWSYNC" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="UFS" caption="Non-recoverable Update Fault State" mask="0x4"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBUFV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="PERBUFV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBUFV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBUFV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH6" name="COUNT" caption="Counter Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="COUNT" caption="Counter Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="COUNT" caption="Counter Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x70" values="WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0x0000FFFF" caption="Period">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHER" caption="Dithering Cycle Number" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHER" caption="Dithering Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHER" caption="Dithering Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="PER" caption="Period Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="PER" caption="Period Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="PER" caption="Period Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="PER" caption="Period Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHER" caption="Dithering Cycle Number" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHER" caption="Dithering Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHER" caption="Dithering Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="CC" caption="Channel Compare/Capture Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="CC" caption="Channel Compare/Capture Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="CC" caption="Channel Compare/Capture Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="CC" caption="Channel Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+        <register name="PERBUF" offset="0x6C" rw="RW" access="WSYNC" size="4" initval="0x0000FFFF" caption="Period Buffer">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="PERBUF" caption="Period Buffer Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="PERBUF" caption="Period Buffer Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="PERBUF" caption="Period Buffer Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="PERBUF" caption="Period Buffer Value" mask="0xFFFF"/>
+        </register>
+        <register name="CCBUF" offset="0x70" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHERBUF" caption="Channel Compare/Capture Buffer Value" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="CCBUF" caption="Dithering Buffer Cycle Number" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update or double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+        <value name="DMAOS" caption="One-shot DMA trigger" value="5"/>
+      </value-group>
+      <value-group name="CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update or double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+        <value name="DMAOS" caption="One-shot DMA trigger" value="5"/>
+      </value-group>
+      <value-group name="FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__BLANK">
+        <value name="START" caption="Blanking applied from start of the ramp" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+        <value name="CAPTMARK" caption="Capture with ramp index as MSB value" value="7"/>
+      </value-group>
+      <value-group name="FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__BLANK">
+        <value name="START" caption="Blanking applied from start of the ramp" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+        <value name="CAPTMARK" caption="Capture with ramp index as MSB value" value="7"/>
+      </value-group>
+      <value-group name="EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="STAMP" caption="Stamp capture" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DPWM" caption="Dual compare PWM" value="3"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+        <value name="RAMP2C" caption="Critical RAMP2 operation" value="3"/>
+        <value name="RAMP2CS" caption="Critical Swapped RAMP2 operation" value="4"/>
+      </value-group>
+    </module>
+    <module name="TESTVAL" id="test_valio_mapper_v1" name2="test_valio_mapper_v1" version="1.0.0" caption=""/>
+    <module name="USB" id="03613" name2="usb_u2222_v1" version="1d0" caption="Full-Speed Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <register modes="DEVICE" name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="DEVICE" name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register modes="DEVICE" name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register modes="DEVICE" name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register modes="HOST" name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="HOST" name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register modes="HOST" name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register modes="HOST" name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register modes="HOST" name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register modes="HOST" name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <register modes="DEVICE" name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register modes="DEVICE" name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register modes="DEVICE" name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register modes="HOST" name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register modes="HOST" name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register modes="HOST" name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register modes="HOST" name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register modes="HOST" name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group name="USB" caption="Full-Speed Universal Serial Bus">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x0F" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC"/>
+        </register>
+        <register modes="DEVICE" name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register modes="HOST" name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="HOST_CTRLB__SPDCONF"/>
+          <bitfield name="AUTORESUME" caption="Auto Resume Enable" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register modes="DEVICE" name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register modes="HOST" name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register modes="DEVICE" name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register modes="HOST" name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register modes="HOST" name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register modes="DEVICE" name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register modes="HOST" name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register modes="DEVICE" name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register modes="HOST" name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register modes="DEVICE" name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register modes="HOST" name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register modes="DEVICE" name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group modes="DEVICE" name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" size="0x20" count="8"/>
+        <register-group modes="HOST" name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" size="0x20" count="8"/>
+      </register-group>
+      <register-group name="USB_DESCRIPTOR" caption="Full-Speed Universal Serial Bus">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register-group modes="DEVICE" name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" size="0x10" count="2"/>
+        <register-group modes="HOST" name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" size="0x10" count="2"/>
+      </register-group>
+      <value-group name="CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="LS" caption="Low-speed mode" value="0x1"/>
+        <value name="HS" caption="High-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="03611" name2="wdt_u2251_v2" version="2b0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run During Standby" mask="0x40"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="WEN" caption="Window Enable Synchronization Busy" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run During Standby Synchronization Busy" mask="0x8"/>
+          <bitfield name="ALWAYSON" caption="Always-On Synchronization Busy" mask="0x10"/>
+          <bitfield name="CLEAR" caption="Clear Synchronization Busy" mask="0x20"/>
+        </register>
+        <register name="CLEAR" offset="0xC" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="CONFIG__PER">
+        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="CONFIG__WINDOW">
+        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="EWCTRL__EWOFFSET">
+        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  </modules>
+  <pinouts>
+    <pinout name="P48" caption="P48">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PA04"/>
+      <pin position="6" pad="VDDIO"/>
+      <pin position="7" pad="VSSIO2"/>
+      <pin position="8" pad="PA05"/>
+      <pin position="9" pad="PA06"/>
+      <pin position="10" pad="PA07"/>
+      <pin position="11" pad="PA08"/>
+      <pin position="12" pad="PA09"/>
+      <pin position="13" pad="PB00"/>
+      <pin position="14" pad="AVDD"/>
+      <pin position="15" pad="AVSS"/>
+      <pin position="16" pad="PB01"/>
+      <pin position="17" pad="PB02"/>
+      <pin position="18" pad="VDDIO"/>
+      <pin position="19" pad="VSSIO4"/>
+      <pin position="20" pad="VDDREG"/>
+      <pin position="21" pad="PB03"/>
+      <pin position="22" pad="PB04"/>
+      <pin position="23" pad="PB05"/>
+      <pin position="24" pad="PB06"/>
+      <pin position="25" pad="PC00"/>
+      <pin position="26" pad="PC01"/>
+      <pin position="27" pad="PC02"/>
+      <pin position="28" pad="PC03"/>
+      <pin position="29" pad="PC04"/>
+      <pin position="30" pad="RESET_N"/>
+      <pin position="31" pad="VDDIO"/>
+      <pin position="32" pad="VSSIO7"/>
+      <pin position="33" pad="PC05"/>
+      <pin position="34" pad="PC06"/>
+      <pin position="35" pad="PC07"/>
+      <pin position="36" pad="PC08"/>
+      <pin position="37" pad="PD00"/>
+      <pin position="38" pad="PD01"/>
+      <pin position="39" pad="PD02"/>
+      <pin position="40" pad="PD03"/>
+      <pin position="41" pad="VSSIO"/>
+      <pin position="42" pad="VDDF"/>
+      <pin position="43" pad="USERLDO"/>
+      <pin position="44" pad="PD07"/>
+      <pin position="45" pad="PD04"/>
+      <pin position="46" pad="PD05"/>
+      <pin position="47" pad="PD08"/>
+      <pin position="48" pad="PD09"/>
+    </pinout>
+    <pinout name="P48_1" caption="P48_1">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PA04"/>
+      <pin position="6" pad="VDDIO"/>
+      <pin position="7" pad="VSSIO2"/>
+      <pin position="8" pad="PA05"/>
+      <pin position="9" pad="PA06"/>
+      <pin position="10" pad="PA07"/>
+      <pin position="11" pad="PA08"/>
+      <pin position="12" pad="PA09"/>
+      <pin position="13" pad="PB00"/>
+      <pin position="14" pad="AVDD"/>
+      <pin position="15" pad="AVSS"/>
+      <pin position="16" pad="PB01"/>
+      <pin position="17" pad="PB02"/>
+      <pin position="18" pad="VDDIO"/>
+      <pin position="19" pad="VSSIO4"/>
+      <pin position="20" pad="VDDREG"/>
+      <pin position="21" pad="PB03"/>
+      <pin position="22" pad="PB04"/>
+      <pin position="23" pad="PB05"/>
+      <pin position="24" pad="PB06"/>
+      <pin position="25" pad="PC00"/>
+      <pin position="26" pad="PC01"/>
+      <pin position="27" pad="PC02"/>
+      <pin position="28" pad="PC03"/>
+      <pin position="29" pad="PC04"/>
+      <pin position="30" pad="RESET_N"/>
+      <pin position="31" pad="VDDIO"/>
+      <pin position="32" pad="VSSIO7"/>
+      <pin position="33" pad="PC05"/>
+      <pin position="34" pad="PC06"/>
+      <pin position="35" pad="PC07"/>
+      <pin position="36" pad="PC08"/>
+      <pin position="37" pad="PD00"/>
+      <pin position="38" pad="PD01"/>
+      <pin position="39" pad="PD02"/>
+      <pin position="40" pad="PD03"/>
+      <pin position="41" pad="VSSIO"/>
+      <pin position="42" pad="VDDF"/>
+      <pin position="43" pad="USERLDO"/>
+      <pin position="44" pad="PD07"/>
+      <pin position="45" pad="PD04"/>
+      <pin position="46" pad="PD05"/>
+      <pin position="47" pad="PD08"/>
+      <pin position="48" pad="PD09"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/atdf/PIC32CM5112GC00064.atdf b/pic32c/pic32cm_gc_sg/pic32cm_gc00/atdf/PIC32CM5112GC00064.atdf
new file mode 100644
index 00000000..0f08905b
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/atdf/PIC32CM5112GC00064.atdf
@@ -0,0 +1,11217 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="4.5" public="true" xsi:noNamespaceSchemaLocation="https://schemas.microchip.com/com/microchip/atdf/4.5/atdf.xsd">
+  <!--
+ Copyright (c) 2024 Microchip Technology Inc.
+
+ SPDX-License-Identifier: Apache-2.0
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+-->
+  <!--
+CHPMKR VERSION: 2.17.0
+-->
+  <file timestamp="2024-11-05T16:47:48Z"/>
+  <variants xmlns:mhc="http://www.atmel.com/schemas/avr-tools-device-file/mhc">
+    <variant ordercode="PIC32CM5112GC00064-I/NA" mhc:ordercode="PIC32CM5112GC00064-I/NA" package="TQFP64" pinout="P64" speedmax="72000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00064-V/NA" mhc:ordercode="PIC32CM5112GC00064-V/NA" package="TQFP64" pinout="P64" speedmax="72000000" tempmin="-40" tempmax="105" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00064-E/NA" mhc:ordercode="PIC32CM5112GC00064-E/NA" package="TQFP64" pinout="P64" speedmax="72000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00064-I/NA" mhc:ordercode="PIC32CM5112GC00064-I/NA" package="VQFN64" pinout="P64_1" speedmax="72000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00064-V/NA" mhc:ordercode="PIC32CM5112GC00064-V/NA" package="VQFN64" pinout="P64_1" speedmax="72000000" tempmin="-40" tempmax="105" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00064-E/NA" mhc:ordercode="PIC32CM5112GC00064-E/NA" package="VQFN64" pinout="P64_1" speedmax="72000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="PIC32CM5112GC00064" architecture="CORTEX-M23" family="PIC32CM" series="PIC32CMGC00">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="BROMC_ROM" start="0x4000000" size="0x10000" type="rom" rw="R" exec="true"/>
+          <memory-segment name="FCR_BFM" start="0x8000000" size="0x4000" type="flash" rw="RW" exec="true"/>
+          <memory-segment name="FCR_CFM_BOOTCFG1A" start="0xA000000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_USEROTP" start="0xA001000" size="0x1000" type="user_signatures" rw="RW"/>
+          <memory-segment name="FCR_CFM_BOOTCFG1" start="0xA002000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_ROMCFG" start="0xA003000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_VSS0" start="0xA004000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_VSS1" start="0xA005000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_TEST" start="0xA006000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_CALOTP" start="0xA007000" size="0x1000" type="other" rw="R"/>
+          <memory-segment name="FCR_PFM" start="0xC000000" size="0x80000" type="flash" rw="RW" exec="true"/>
+          <memory-segment name="MCRAMC_RET" start="0x20000000" size="0x00020000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="APB0_BRIDGE" start="0x44000000" size="0x00034000" type="io" rw="RW"/>
+          <memory-segment name="APB1_BRIDGE" start="0x44800000" size="0x0003a000" type="io" rw="RW"/>
+          <memory-segment name="APB2_BRIDGE" start="0x45000000" size="0x00010000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xe0000000" size="0x00100000" type="io" rw="RW"/>
+        </address-space>
+      </address-spaces>
+      <parameters>
+        <param name="NUM_IRQ" value="141" caption="Number of interrupt request lines"/>
+        <param name="__BKPT_NUM" value="4" caption="Number of breakpoints comparators"/>
+        <param name="__CM23_REV" value="0x0000" caption="Cortex-M23 Core Revision"/>
+        <param name="__ETM_PRESENT" value="0" caption="No Embedded Trace Macro implemented"/>
+        <param name="__FPU_PRESENT" value="0" caption="No FPU"/>
+        <param name="__MPU_NS_REGIONS" value="8" caption="Number of Non-Secure Memory Protection Regions"/>
+        <param name="__MPU_PRESENT" value="1" caption="MPU implemented"/>
+        <param name="__MPU_REGIONS" value="8" caption="same as __MPU_S_REGIONS"/>
+        <param name="__MPU_S_REGIONS" value="8" caption="Number of Secure Memory Protection Regions"/>
+        <param name="__MTB_PRESENT" value="0" caption="No Macro Trace Buffer implemented"/>
+        <param name="__NVIC_PRIO_BITS" value="2" caption="Number of NVIC Priority Bits"/>
+        <param name="__SAUREGION_PRESENT" value="0" caption="Number of Security Attribute Unit Regions (No SAU)"/>
+        <param name="__SEC_ENABLED" value="0" caption="ARMv8-M security extensions (Trust Zone) enabled"/>
+        <param name="__SYST_NUM" value="2" caption="Number of SYSTICK, include secure and non-secure SYSTICK timers"/>
+        <param name="__VTOR_PRESENT" value="1" caption="Include Vector Table Offset Register"/>
+        <param name="__Vendor_SysTickConfig" value="0" caption="Standard SYSTICK used"/>
+        <param name="__WPT_NUM" value="2" caption="Number of watch point comparators"/>
+        <param name="POWER_DOMAIN" value="PD_CORE"/>
+        <param name="__ARCH_ARM" value="1"/>
+        <param name="__ARCH_ARM_CORTEX_M" value="1"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="03784" name2="cmp_ac_u2501_v2" version="2a0">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x4482A000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B" pad="PA07"/>
+              <signal group="AIN" index="1" function="B" pad="PA08"/>
+              <signal group="AIN" index="2" function="B" pad="PB00"/>
+              <signal group="AIN" index="3" function="B" pad="PB03"/>
+              <signal group="CMP" index="0" function="B" pad="PA01" ioset="1"/>
+              <signal group="CMP" index="0" function="B" pad="PA13" ioset="2"/>
+              <signal group="CMP" index="1" function="B" pad="PA02" ioset="1"/>
+              <signal group="CMP" index="1" function="B" pad="PB07" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="ATEST_IMPLEMENTED" value="1" caption="Defines if the ATEST register is implemented"/>
+              <param name="ATEST_SIZE" value="2" caption="Defines the number of effective bits in ATEST register"/>
+              <param name="DACVALUE_BIT" value="7" caption="Defines the number of bits in DACCTRLn.VALUE"/>
+              <param name="IO_INPUTS" value="4" caption="Defines the number of AC pair inputs connected to IO pins"/>
+              <param name="PAIRS" value="1" caption="Defines the number of AC pairs"/>
+              <param name="NUM_CMP" value="2" caption="Number of comparators"/>
+              <param name="LOAD_CALIB" value="0" caption="Defines if calibration is required"/>
+              <param name="GCLK_ID" value="34"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="21" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="40" caption="Instance index for AC"/>
+              <param name="MCLK_ID_APB" value="50" caption="Index for AC APB clock"/>
+              <param name="PAC_ID" value="40" caption="Index for AC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="03620" name2="adc_msh_ctrl_apb_v1" version="1b0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x44818000"/>
+            <signals>
+              <signal group="ADC0_AIN" index="0" function="B" pad="PA03"/>
+              <signal group="ADC0_AIN" index="1" function="B" pad="PA04"/>
+              <signal group="ADC0_AIN" index="2" function="B" pad="PA05"/>
+              <signal group="ADC0_AIN" index="3" function="B" pad="PA06"/>
+              <signal group="ADC0_AIN" index="4" function="B" pad="PA07"/>
+              <signal group="ADC0_AIN" index="5" function="B" pad="PA08"/>
+              <signal group="ADC0_AIN" index="6" function="B" pad="PA09"/>
+              <signal group="ADC0_AIN" index="7" function="B" pad="PB00"/>
+              <signal group="ADC0_AIN" index="8" function="B" pad="PB03"/>
+              <signal group="ADC0_AIN" index="9" function="B" pad="PB04"/>
+              <signal group="ADC0_AIN" index="10" function="B" pad="PB05"/>
+              <signal group="ADC0_AIN" index="11" function="B" pad="PB06"/>
+              <signal group="ADC0_ANN" index="0" function="B" pad="PA04"/>
+              <signal group="ADC0_ANN" index="2" function="B" pad="PA06"/>
+              <signal group="ADC0_ANN" index="4" function="B" pad="PA08"/>
+              <signal group="RES_TEST" index="0" function="ADC_TEST_PAD" pad="PD08"/>
+              <signal group="RES_TEST" index="1" function="ADC_TEST_PAD" pad="PD09"/>
+              <signal group="RES_TEST" index="2" function="ADC_TEST_PAD" pad="PD07"/>
+              <signal group="RES_TEST" index="3" function="ADC_TEST_PAD" pad="PA00"/>
+              <signal group="RES_TEST" index="4" function="ADC_TEST_PAD" pad="PA01"/>
+              <signal group="RES_TEST" index="5" function="ADC_TEST_PAD" pad="PA02"/>
+              <signal group="RES_TEST" index="6" function="ADC_TEST_PAD" pad="PA03"/>
+              <signal group="RES_TEST" index="7" function="ADC_TEST_PAD" pad="PA04"/>
+              <signal group="RES_TEST" index="8" function="ADC_TEST_PAD" pad="PB03"/>
+              <signal group="RES_TEST" index="9" function="ADC_TEST_PAD" pad="PB04"/>
+              <signal group="RES_TEST" index="10" function="ADC_TEST_PAD" pad="PB05"/>
+              <signal group="RES_TEST" index="11" function="ADC_TEST_PAD" pad="PB06"/>
+              <signal group="VREFH" function="VOLT_REF" pad="PA09"/>
+            </signals>
+            <parameters>
+              <param name="APB_FIFO_DEPTH" value="16" caption="--"/>
+              <param name="CHNSAR_NMBR1" value="16" caption="--"/>
+              <param name="CHNSAR_NMBR2" value="0" caption="--"/>
+              <param name="CHNSAR_NMBR3" value="0" caption="--"/>
+              <param name="CHNSAR_NMBR4" value="0" caption="--"/>
+              <param name="DCMP_NMBR" value="1" caption="--"/>
+              <param name="EARLY_INTR_PRESENT" value="1" caption="--"/>
+              <param name="FLTR_NMBR" value="1" caption="--"/>
+              <param name="OCP_ADDR_WIDTH" value="0" caption="--"/>
+              <param name="OCP_FIFO_DEPTH" value="0" caption="--"/>
+              <param name="OCP_PORT_PRESENT" value="0" caption="--"/>
+              <param name="SARCORE_NMBR" value="1" caption="--"/>
+              <param name="TRGS_NMBR" value="16" caption="--"/>
+              <param name="VREF_STARTUP_TIME" value="50" caption="--"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="DMAC_ID_PFFRDY" value="37"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="12" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="39" caption="Instance index for ADC"/>
+              <param name="MCLK_ID_APB" value="49" caption="Index for ADC APB clock"/>
+              <param name="PAC_ID" value="39" caption="Index for ADC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="AT" id="04932" name2="sec_anti_tamper_v1" version="1a0">
+          <instance name="AT">
+            <register-group name="AT" name-in-module="AT" address-space="base" offset="0x4500C000"/>
+            <parameters>
+              <param name="AT_TMPR_OSC_NUM_INV" value="881" caption="Number of inverters in tamper oscillator"/>
+              <param name="AT_CTRLAPRIV_IMPLEMENTED" value="1" caption="Implement the CTRLA.PRIV bit and privilege access filtering to registers.0 = CTRLA.PRIV not implemented1 = CTRLA.PRIV implemented"/>
+              <param name="AT_WPCTRL_IMPLEMENTED" value="0" caption="Implement the WPCTRL register for write protection. 1 = Use WPCTRL register is preset . Used to control write protection enable/disable. 0 = No WPCTRL sfr, only used in legacy device with a PACUse at_wrprot to control write protection enable/disable"/>
+              <param name="AT_WPCTRL_KEY" value="0x412054" caption="WPCTRL 24-bit key value. See register description for usage.Set to a unique value for each macro. ASCII of &quot;A T&quot;"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="6" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="45" caption="Instance index for AT"/>
+              <param name="MCLK_ID_APB" value="56" caption="Index for AT APB clock"/>
+              <param name="PAC_ID" value="45" caption="Index for AT registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="BROMC" id="04402" name2="prm_boot_ahb_v2" version="2a0">
+          <instance name="BROMC">
+            <register-group name="BROMC" name-in-module="BROMC" address-space="base" offset="0x44804000"/>
+            <parameters>
+              <param name="BROMC_PADDR_MSB" value="12" caption="--"/>
+              <param name="BROMC_PDATA_MSB" value="31" caption="--"/>
+              <param name="BROMC_PSTRB_MSB" value="3" caption="--"/>
+              <param name="BROMC_PPROT_MSB" value="5" caption="--"/>
+              <param name="BROMC_ROM_ADDR_MSB" value="13" caption="--"/>
+              <param name="BROMC_ROM_DATA_MSB" value="31" caption="--"/>
+              <param name="BROMC_ROM_DATA_SIZE" value="16384" caption="--"/>
+              <param name="BROMC_ROM_PRMWS_DEFAULT" value="0" caption="--"/>
+              <param name="BROMC_ROM_KEN" value="0" caption="--"/>
+              <param name="BROMC_ROM_CRC_EN" value="1" caption="--"/>
+              <param name="BROMC_ROM_SPLIT" value="0x3400" caption="(8K for PK code)  (Note: This parameter may change once boot and PK code sizes are known)"/>
+              <param name="BROMC_BOOTCRC_MODE" value="2" caption="--"/>
+              <param name="BROMC_FUSES_DATA_MSB" value="127" caption="See Flash Control Chapter for Values"/>
+              <param name="BROMC_FUSES_RDY_MSB" value="14" caption="See Flash Control Chapter for Values"/>
+              <param name="BROMC_FUSES_UCFG_ROWID" value="14" caption="See Chapter 5 CCFG Fuse map for Values"/>
+              <param name="BROMC_FUSES_UCFG_START" value="0" caption="See Chapter 5 CCFG Fuse map for Values"/>
+              <param name="BROMC_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="BROMC_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="BROMC_WPCTRL_KEY" value="0x42524F" caption="--"/>
+              <param name="BROMC_NUM_COOLDN_CYCLES" value="2" caption="--"/>
+              <param name="BROMC_NUM_WARMUP_CYCLES" value="2" caption="--"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="2" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="23" caption="Instance index for BROMC"/>
+              <param name="MCLK_ID_AHB" value="32" caption="Index for BROMC AHB clock"/>
+              <param name="MCLK_ID_APB" value="33" caption="Index for BROMC APB clock"/>
+              <param name="PAC_ID" value="23" caption="Index for BROMC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="CAN" id="05010" name2="can_fd_apb_v1" version="1a0">
+          <instance name="CAN0">
+            <register-group name="CAN0" name-in-module="CAN" address-space="base" offset="0x4402E000"/>
+            <signals>
+              <signal group="RX" function="H" pad="PA10" ioset="3"/>
+              <signal group="RX" function="H" pad="PC01" ioset="1"/>
+              <signal group="RX" function="H" pad="PD06" ioset="2"/>
+              <signal group="TX" function="H" pad="PA11" ioset="3"/>
+              <signal group="TX" function="H" pad="PC02" ioset="1"/>
+              <signal group="TX" function="H" pad="PD08" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="ECC_ERR_IMPLEMENTED" value="0" caption="ECC error implemented?"/>
+              <param name="INTERNAL_TB_SOF" value="3" caption="0: No SOF and no internal Time base, 1: SOF and no internal Time"/>
+              <param name="MSG_RAM_ADDR" value="0x20" caption="8-bits MSB"/>
+              <param name="NUMBER_TS" value="1" caption="0: 4 Timestamp reg, 1: 8 timestamp reg, 2: 16 timestamp reg"/>
+              <param name="PRIV_IMPLEMENTED" value="1" caption="Privilege access is implemented? 0: CTRLA.PRIV bit not implemented, 1: CTRLA.PRIV bit implemented"/>
+              <param name="RXD_SYNC_METHOD" value="0" caption="RXD Synchronization Method"/>
+              <param name="SYNT_TIMESTAMP" value="0x00000" caption="CAN_SYNT_TIMESTAMP[19:16]: CREL.YEAR reset value (BCD-coded),CAN_SYNT_TIMESTAMP[15:8]: CREL.MON reset value (BCD-coded), CAN_SYNT_TIMESTAMP[7:0]: CREL.DAY reset value (BCD-coded)"/>
+              <param name="WPCTRL_IMPLEMENTED" value="0" caption="Write protection control register implemented?"/>
+              <param name="WPCTRL_KEY" value="0x43414E" caption="Write protection 24 bit key"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="23" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="17" caption="Instance index for CAN0"/>
+              <param name="MCLK_ID_AHB" value="23" caption="Index for CAN0 AHB clock"/>
+              <param name="PAC_ID" value="17" caption="Index for CAN0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="CAN1">
+            <register-group name="CAN1" name-in-module="CAN" address-space="base" offset="0x44030000"/>
+            <signals>
+              <signal group="RX" function="H" pad="PA00" ioset="2"/>
+              <signal group="RX" function="H" pad="PC05" ioset="1"/>
+              <signal group="RX" function="H" pad="PD12" ioset="3"/>
+              <signal group="TX" function="H" pad="PA01" ioset="2"/>
+              <signal group="TX" function="H" pad="PC06" ioset="1"/>
+              <signal group="TX" function="H" pad="PD13" ioset="3"/>
+            </signals>
+            <parameters>
+              <param name="ECC_ERR_IMPLEMENTED" value="0" caption="ECC error implemented?"/>
+              <param name="INTERNAL_TB_SOF" value="3" caption="0: No SOF and no internal Time base, 1: SOF and no internal Time"/>
+              <param name="MSG_RAM_ADDR" value="0x20" caption="8-bits MSB"/>
+              <param name="NUMBER_TS" value="1" caption="0: 4 Timestamp reg, 1: 8 timestamp reg, 2: 16 timestamp reg"/>
+              <param name="PRIV_IMPLEMENTED" value="1" caption="Privilege access is implemented? 0: CTRLA.PRIV bit not implemented, 1: CTRLA.PRIV bit implemented"/>
+              <param name="RXD_SYNC_METHOD" value="0" caption="RXD Synchronization Method"/>
+              <param name="SYNT_TIMESTAMP" value="0x00000" caption="CAN_SYNT_TIMESTAMP[19:16]: CREL.YEAR reset value (BCD-coded),CAN_SYNT_TIMESTAMP[15:8]: CREL.MON reset value (BCD-coded), CAN_SYNT_TIMESTAMP[7:0]: CREL.DAY reset value (BCD-coded)"/>
+              <param name="WPCTRL_IMPLEMENTED" value="0" caption="Write protection control register implemented?"/>
+              <param name="WPCTRL_KEY" value="0x43414E" caption="Write protection 24 bit key"/>
+              <param name="GCLK_ID" value="7"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="24" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="18" caption="Instance index for CAN1"/>
+              <param name="MCLK_ID_AHB" value="24" caption="Index for CAN1 AHB clock"/>
+              <param name="PAC_ID" value="18" caption="Index for CAN1 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="CCL" id="03628" name2="cla_ccl_u2225_v2" version="2b0">
+          <instance name="CCL0">
+            <register-group name="CCL0" name-in-module="CCL" address-space="base" offset="0x4482E000"/>
+            <signals>
+              <signal group="IN" index="0" function="I" pad="PC01" ioset="1"/>
+              <signal group="IN" index="1" function="I" pad="PC02" ioset="1"/>
+              <signal group="IN" index="2" function="I" pad="PC09" ioset="1"/>
+              <signal group="IN" index="3" function="I" pad="PD00" ioset="1"/>
+              <signal group="IN" index="4" function="I" pad="PD01" ioset="1"/>
+              <signal group="IN" index="5" function="I" pad="PD10" ioset="1"/>
+              <signal group="IN" index="6" function="I" pad="PA00" ioset="1"/>
+              <signal group="IN" index="7" function="I" pad="PA01" ioset="1"/>
+              <signal group="IN" index="8" function="I" pad="PA10" ioset="1"/>
+              <signal group="IN" index="9" function="I" pad="PB05" ioset="1"/>
+              <signal group="IN" index="10" function="I" pad="PB06" ioset="1"/>
+              <signal group="IN" index="11" function="I" pad="PB10" ioset="1"/>
+              <signal group="OUT" index="0" function="I" pad="PC03" ioset="1"/>
+              <signal group="OUT" index="1" function="I" pad="PD08" ioset="1"/>
+              <signal group="OUT" index="2" function="I" pad="PA02" ioset="1"/>
+              <signal group="OUT" index="3" function="I" pad="PC00" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="LUT_NUM" value="4" caption="Number of LUT in a CCL"/>
+              <param name="GCLK_ID" value="36"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="23" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="42" caption="Instance index for CCL0"/>
+              <param name="MCLK_ID_APB" value="52" caption="Index for CCL0 APB clock"/>
+              <param name="PAC_ID" value="42" caption="Index for CCL0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="CCL1">
+            <register-group name="CCL1" name-in-module="CCL" address-space="base" offset="0x44830000"/>
+            <signals>
+              <signal group="IN" index="0" function="I" pad="PC04" ioset="1"/>
+              <signal group="IN" index="1" function="I" pad="PC05" ioset="1"/>
+              <signal group="IN" index="2" function="I" pad="PC10" ioset="1"/>
+              <signal group="IN" index="3" function="I" pad="PD06" ioset="1"/>
+              <signal group="IN" index="4" function="I" pad="PD07" ioset="1"/>
+              <signal group="IN" index="5" function="I" pad="PD11" ioset="1"/>
+              <signal group="IN" index="5" function="I" pad="PD12" ioset="2"/>
+              <signal group="IN" index="6" function="I" pad="PA09" ioset="1"/>
+              <signal group="IN" index="7" function="I" pad="PA06" ioset="1"/>
+              <signal group="IN" index="8" function="I" pad="PA11" ioset="1"/>
+              <signal group="IN" index="8" function="I" pad="PA12" ioset="2"/>
+              <signal group="IN" index="9" function="I" pad="PB04" ioset="1"/>
+              <signal group="IN" index="10" function="I" pad="PB03" ioset="1"/>
+              <signal group="IN" index="11" function="I" pad="PB07" ioset="2"/>
+              <signal group="IN" index="11" function="I" pad="PB08" ioset="1"/>
+              <signal group="OUT" index="0" function="I" pad="PC06" ioset="1"/>
+              <signal group="OUT" index="1" function="I" pad="PD09" ioset="1"/>
+              <signal group="OUT" index="2" function="I" pad="PA05" ioset="1"/>
+              <signal group="OUT" index="3" function="I" pad="PB00" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="LUT_NUM" value="4" caption="Number of LUT in a CCL"/>
+              <param name="GCLK_ID" value="37"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="24" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="43" caption="Instance index for CCL1"/>
+              <param name="MCLK_ID_APB" value="53" caption="Index for CCL1 APB clock"/>
+              <param name="PAC_ID" value="43" caption="Index for CCL1 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="CoreDebug" id="SYSTEM_IP" version="1.0.0">
+          <instance name="CoreDebug">
+            <register-group name="CoreDebug" name-in-module="CoreDebug" address-space="base" offset="0xE000EDF0"/>
+          </instance>
+        </module>
+        <module name="DIB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="DIB">
+            <register-group name="DIB" name-in-module="DIB" address-space="base" offset="0xE000EFB0"/>
+          </instance>
+        </module>
+        <module name="DMAC" id="dma_u2223_v2" name2="dma_u2223_v2" version="2i0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x44802000"/>
+            <parameters>
+              <param name="CH_NUM" value="8" caption="--"/>
+              <param name="EVIN_NUM" value="4" caption="--"/>
+              <param name="EVOUT_NUM" value="4" caption="--"/>
+              <param name="LVL_NUM" value="4" caption="--"/>
+              <param name="QOSCTRL_D_RESETVALUE" value="2" caption="--"/>
+              <param name="QOSCTRL_F_RESETVALUE" value="2" caption="--"/>
+              <param name="QOSCTRL_WRB_RESETVALUE" value="2" caption="--"/>
+              <param name="SPLIT_IRQ_NUM" value="4" caption="--"/>
+              <param name="TRIG_NUM" value="43" caption="--"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="1" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="21" caption="Instance index for DMAC"/>
+              <param name="MCLK_ID_AHB" value="28" caption="Index for DMAC AHB clock"/>
+              <param name="MCLK_ID_APB" value="29" caption="Index for DMAC APB clock"/>
+              <param name="PAC_ID" value="21" caption="Index for DMAC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="04465" name2="icd_dsu_v1" version="1a0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x44000000"/>
+            <signals>
+              <signal group="MSA" function="DSU_MSA" pad="PC05"/>
+              <signal group="SWCCSTAT" function="DSU_SWCCSTAT" pad="PC06"/>
+            </signals>
+            <parameters>
+              <param name="DSU_BASE_ADDR_INTERNAL" value="0x44000000" caption="--"/>
+              <param name="DSU_CPU_NUM" value="0" caption="--"/>
+              <param name="DSU_TZ_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DSU_CORESIGHT_REVISION" value="0x0" caption="--"/>
+              <param name="DSU_CORESIGHT_ENTRY" value="0xE00FF001 0x0 0x0 0x0" caption="--"/>
+              <param name="DSU_ID_MASKID" value="0x00" caption="Microchip Device Mask ID which provides the value for bits [15:8] of the ID - Part Number."/>
+              <param name="DSU_ID_VER" value="0x0" caption="ID Version Code provides the Mask Revision value for the device. Use metal changeable cells to configure this value."/>
+              <param name="DSU_SD_KEY" value="0xFFABAFD0" caption="--"/>
+              <param name="DSU_DCFG_MASK" value="0xFF0FFF0F 0x10FC7F80 0xC0800203 0x0 0x0 0x0 0x0 0x0" caption="--"/>
+              <param name="DSU_DAL1_VAL" value="0x55" caption="--"/>
+              <param name="DSU_DAL2_VAL" value="0xAA" caption="--"/>
+              <param name="DSU_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DSU_CTRLB_IMPLEMENTED_MASK" value="0x00000000" caption="--"/>
+              <param name="DSU_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="DSU_WPCTRL_KEY" value="0x445355" caption="--"/>
+              <param name="DSU_PRVKEY_IMPLEMENTED" value="0" caption="key sourced by PUF, not DSU"/>
+              <param name="DSU_BRCTRL_KEY" value="0x445355" caption="--"/>
+              <param name="DSU_TDID_DIE" value="0x00" caption="--"/>
+              <param name="DSU_TDID_MASK" value="0x00" caption="--"/>
+              <param name="DSU_SWCCS_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DSU_TESTMODE_IMPLEMENTED_MASK" value="0x000007FF 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DSU_FUSES_DATA_MSB" value="127" caption="128-bit bus"/>
+              <param name="DSU_FUSES_RDY_MSB" value="14" caption="15 bit fuse ready bus"/>
+              <param name="DSU_FUSES_ID_DEVID_START" value="24" caption="DEVID field is DSUCFG0[31:24]"/>
+              <param name="DSU_FUSES_ID_DEVID_SIZE" value="8" caption="--"/>
+              <param name="DSU_FUSES_ID_DEVID_ROWID" value="8" caption="DEVID on RowID Index = 8"/>
+              <param name="DSU_FUSES_DCFG_START" value="0 32 64 96 0 32 64 96" caption="--"/>
+              <param name="DSU_FUSES_DCFG_SIZE" value="32 32 32 32 32 32 32 32" caption="--"/>
+              <param name="DSU_FUSES_DCFG_ROWID" value="8 8 8 8 9 9 9 9" caption="DSUCFG7-0 = FCCFG39-32"/>
+              <param name="DMAC_ID_DCC0" value="1"/>
+              <param name="DMAC_ID_DCC1" value="2"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="0" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="0" caption="Instance index for DSU"/>
+              <param name="MCLK_ID_AHB" value="0" caption="Index for DSU AHB clock"/>
+              <param name="PAC_ID" value="0" caption="Index for DSU registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DWT" id="SYSTEM_IP" version="1.0.0">
+          <instance name="DWT">
+            <register-group name="DWT" name-in-module="DWT" address-space="base" offset="0xE0001000"/>
+            <parameters>
+              <param name="__WPT_NUM" value="2" caption="Number of DWT watchpoint comparators"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="03706" name2="int_eic_u2804_v1" version="1b0">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x44020000"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PC00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PC01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PD01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PC02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PD04"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PC03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PD05"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PB04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PC04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PD07"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PB05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PC05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PD08"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PC06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PD09"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA08"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB07"/>
+              <signal group="EXTINT" index="8" function="A" pad="PD10"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PC09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PD11"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PC10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PD12"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PB10"/>
+              <signal group="EXTINT" index="11" function="A" pad="PD13"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="NMI" function="A" pad="PD00"/>
+            </signals>
+            <parameters>
+              <param name="EXTINT_NUM" value="16" caption="--"/>
+              <param name="NUMBER_OF_CONFIG_REGS" value="2" caption="=(EIC_EXTINT_NUM +7) / 8"/>
+              <param name="NUMBER_OF_INTERRUPTS" value="16" caption="=(EIC_EXTINT_NUM)"/>
+              <param name="SECURE_IMPLEMENTED" value="1" caption="--"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="16" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="13" caption="Instance index for EIC"/>
+              <param name="MCLK_ID_APB" value="13" caption="Index for EIC APB clock"/>
+              <param name="PAC_ID" value="13" caption="Index for EIC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="03601" name2="ptg_evsys_u2504_v2" version="2b0">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x44806000"/>
+            <parameters>
+              <param name="ASYNCHRONOUS_CHANNELS" value="0xFFFFF000" caption="--"/>
+              <param name="CHANNELS" value="12" caption="--"/>
+              <param name="CHANNELS_BITS" value="4" caption="=LEN( BIN(EVSYS_CHANNELS-1)) - 2)derived parameter"/>
+              <param name="GENERATORS" value="90" caption="Should be 90"/>
+              <param name="GENERATORS_BITS" value="7" caption="=LEN( BIN(EVSYS_GENERATORS-1)) - 2)derived parameter"/>
+              <param name="SECURE_IMPLEMENTED" value="0" caption="--"/>
+              <param name="SPLIT_IRQ_NUM" value="12" caption="--"/>
+              <param name="SYNCH_NUM" value="12" caption="--"/>
+              <param name="SYNCH_NUM_BITS" value="4" caption="=LEN( BIN(EVSYS_SYNCH_NUM-1)) - 2)derived parameter"/>
+              <param name="USERS" value="62" caption="Should be 62"/>
+              <param name="USERS_BITS" value="6" caption="=LEN( BIN(EVSYS_USERS-1)) - 2)derived parameter"/>
+              <param name="USERS_GROUPS" value="2" caption="=(EVSYS_USERS+31) / 32derived parameter"/>
+              <param name="GCLK_ID_CH0" value="8"/>
+              <param name="GCLK_ID_CH1" value="9"/>
+              <param name="GCLK_ID_CH2" value="10"/>
+              <param name="GCLK_ID_CH3" value="11"/>
+              <param name="GCLK_ID_CH4" value="12"/>
+              <param name="GCLK_ID_CH5" value="13"/>
+              <param name="GCLK_ID_CH6" value="14"/>
+              <param name="GCLK_ID_CH7" value="15"/>
+              <param name="GCLK_ID_CH8" value="16"/>
+              <param name="GCLK_ID_CH9" value="17"/>
+              <param name="GCLK_ID_CH10" value="18"/>
+              <param name="GCLK_ID_CH11" value="19"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="3" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="25" caption="Instance index for EVSYS"/>
+              <param name="MCLK_ID_APB" value="35" caption="Index for EVSYS APB clock"/>
+              <param name="PAC_ID" value="25" caption="Index for EVSYS registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FCR" id="04972" name2="pfm_ctrlr_apb_v2" version="2a0">
+          <instance name="FCR">
+            <register-group name="FCR" name-in-module="FCR" address-space="base" offset="0x44002000"/>
+            <parameters>
+              <param name="FCR_AHB_PORTS_NB" value="1" caption="--"/>
+              <param name="FCR_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCR_INTFLAGSET_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCR_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="FCR_WPCTRL_KEY" value="0x464352" caption="--"/>
+              <param name="FCR_PDMO_MSB" value="7" caption="--"/>
+              <param name="FCR_PFM_ADDR_BASE" value="0x0C000000" caption="--"/>
+              <param name="FCR_BFM_ADDR_BASE" value="0x08000000" caption="--"/>
+              <param name="FCR_CFM_ADDR_BASE" value="0x0A000000" caption="--"/>
+              <param name="FCR_FCD_ADDR_BASE" value="0x0B000000" caption="--"/>
+              <param name="FCR_VSS_CFG0_BASE" value="0x0A004000" caption="--"/>
+              <param name="FCR_VSS_CFG1_BASE" value="0x0A005000" caption="--"/>
+              <param name="FCR_VSS_CFG2_BASE" value="0" caption="--"/>
+              <param name="FCR_VSS_CFG3_BASE" value="0" caption="--"/>
+              <param name="FCR_VSS_CFG4_BASE" value="0" caption="--"/>
+              <param name="FCR_VSS_CFG5_BASE" value="0" caption="--"/>
+              <param name="FCR_CRC_PRESENT" value="1" caption="--"/>
+              <param name="FCR_FLT_PRESENT" value="1" caption="--"/>
+              <param name="FCR_ECC_PRESENT" value="1" caption="--"/>
+              <param name="FCR_PCHE_PRESENT" value="1" caption="--"/>
+              <param name="FCR_PCHE_AHB_NUM" value="0" caption="--"/>
+              <param name="FCR_PCHE_NUM_LINES" value="4" caption="--"/>
+              <param name="FCR_PCHE_TAG_MASK" value="0xF9F8000F" caption="--"/>
+              <param name="FCR_FUSES_READY_CYCLES" value="2" caption="--"/>
+              <param name="FCR_FUSES_DATA_CYCLES" value="4" caption="--"/>
+              <param name="FUSES_RDY_MSB" value="14" caption="--"/>
+              <param name="FUSES_DATA_MSB" value="127" caption="--"/>
+              <param name="FCR_HDATA_SIZE" value="32" caption="--"/>
+              <param name="FCR_F1RR_ADDR" value="0x0A007000" caption="--"/>
+              <param name="FCR_F2RR_ADDR" value="0" caption="Not applicable for QSilver"/>
+              <param name="FCR_RR_NUM_READS" value="1" caption="--"/>
+              <param name="FCR_NUM_RR_SFR" value="1" caption="--"/>
+              <param name="FCR_FFF_ADDR" value="0x0A007040" caption="--"/>
+              <param name="FCR_NOT_FFF_VALUE" value="0xA5A5A5A5" caption="--"/>
+              <param name="FCR_OTPLOCK_ADDR" value="0x0A007060" caption="--"/>
+              <param name="FCR_CAL_ADDR" value="0x0A007080" caption="--"/>
+              <param name="FCR_CAL_NUM_READS" value="14" caption="--"/>
+              <param name="FCR_PBUCFG_ADDR" value="0x0A003400" caption="--"/>
+              <param name="FCR_PERIOD_MIN" value="75" caption="--"/>
+              <param name="FCR_PERIOD_NOM" value="116" caption="--"/>
+              <param name="FCR_TCALH_NS" value="10000" caption="--"/>
+              <param name="PFM_NUM_PANELS" value="1" caption="--"/>
+              <param name="PFM_PNL_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_SYS_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_ROW_ADDR_MSB" value="9" caption="--"/>
+              <param name="PFM_PAGE_ADDR_MSB" value="11" caption="--"/>
+              <param name="PFM_PNL_DATA_MSB" value="139" caption="--"/>
+              <param name="PFM_DATA_MSB" value="127" caption="--"/>
+              <param name="PFM_PNL_WDATA_MSB" value="34" caption="Parameter only in DOS Rev C, not in RTL"/>
+              <param name="PFM_NUM_RR" value="2" caption="--"/>
+              <param name="PFM_SRHT_PRESENT" value="0" caption="--"/>
+              <param name="BFM_PNL_ADDR_MSB" value="13" caption="--"/>
+              <param name="BFM_SYS_ADDR_MSB" value="13" caption="--"/>
+              <param name="CFM_PNL_ADDR_MSB" value="14" caption="--"/>
+              <param name="CFM_SYS_ADDR_MSB" value="14" caption="--"/>
+              <param name="NVR_NUM_PAGES" value="12" caption="--"/>
+              <param name="PFM_TDPDH_NS" value="5000" caption="--"/>
+              <param name="PFM_TDPDS_NS" value="100" caption="--"/>
+              <param name="PFM_TMS_NS" value="5000" caption="See Note 2"/>
+              <param name="PFM_TMH_NS" value="100" caption="See Note 2"/>
+              <param name="PFM_TRT_NS" value="500" caption="--"/>
+              <param name="PFM_TRHR_NS" value="1000" caption="--"/>
+              <param name="PFM_TONWAIT_NS" value="6000" caption="--"/>
+              <param name="PFM_TLKCFG_NS" value="1000" caption="--"/>
+              <param name="PFM_ACC_NS" value="25" caption="--"/>
+              <param name="PFM_ACC_HT_NS" value="30" caption="--"/>
+              <param name="PFM_ACC_RECALL_NS" value="70" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="1" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="1" caption="Instance index for FCR"/>
+              <param name="MCLK_ID_AHB" value="1" caption="Index for FCR AHB clock"/>
+              <param name="PAC_ID" value="1" caption="Index for FCR registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FCW" id="04971" name2="pfm_ctrlw_apb_v2" version="2a0">
+          <instance name="FCW">
+            <register-group name="FCW" name-in-module="FCW" address-space="base" offset="0x44004000"/>
+            <parameters>
+              <param name="FCW_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCW_INTFLAGSET_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCW_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="FCW_WPCTRL_KEY" value="0x464357" caption="--"/>
+              <param name="FCW_PFM_ADDR_BASE" value="0x0C000000" caption="--"/>
+              <param name="FCW_BFM_ADDR_BASE" value="0x08000000" caption="--"/>
+              <param name="FCW_CFM_ADDR_BASE" value="0x0A000000" caption="--"/>
+              <param name="FCW_VSS_CFG0_BASE" value="0x0A004000" caption="--"/>
+              <param name="FCW_VSS_CFG1_BASE" value="0x0A005000" caption="--"/>
+              <param name="FCW_VSS_CFG2_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_VSS_CFG3_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_VSS_CFG4_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_VSS_CFG5_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_PWP_REGIONS" value="4" caption="--"/>
+              <param name="FCW_PWP_MSB" value="6" caption="--"/>
+              <param name="FCW_TAMPER_PRESENT" value="1" caption="--"/>
+              <param name="FCW_TAMPER_ADDR" value="0x0A003200" caption="--"/>
+              <param name="FCW_TAMPER_DATA" value="0x00000000" caption="--"/>
+              <param name="FCW_SD_USE_CPCNT" value="1" caption="--"/>
+              <param name="FCW_NUM_DATA_SFR" value="4" caption="(PFM_DATA_MSB+1)/32"/>
+              <param name="FCW_TPAR_MSB" value="3" caption="(PFM_PNL_DATA_MSB - PFM_DATA_MSB)/4"/>
+              <param name="FCW_PERIOD_MIN" value="75" caption="--"/>
+              <param name="FCW_PERIOD_NOM" value="116" caption="--"/>
+              <param name="PFM_SIZE" value="6" caption="--"/>
+              <param name="PFM_NUM_PANELS" value="1" caption="--"/>
+              <param name="PFM_PNL_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_SYS_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_ROW_ADDR_MSB" value="9" caption="--"/>
+              <param name="PFM_PAGE_ADDR_MSB" value="11" caption="--"/>
+              <param name="PFM_PNL_DATA_MSB" value="139" caption="--"/>
+              <param name="PFM_DATA_MSB" value="127" caption="--"/>
+              <param name="PFM_NUM_RR" value="2" caption="--"/>
+              <param name="BFM_PNL_ADDR_MSB" value="13" caption="--"/>
+              <param name="BFM_SYS_ADDR_MSB" value="13" caption="--"/>
+              <param name="CFM_PNL_ADDR_MSB" value="14" caption="--"/>
+              <param name="CFM_SYS_ADDR_MSB" value="14" caption="--"/>
+              <param name="NVR_NUM_PAGES" value="12" caption="--"/>
+              <param name="PFM_TWS_NS" value="5" caption="value irrelevant, must be &gt;0"/>
+              <param name="PFM_TWH_NS" value="5" caption="value irrelevant, must be &gt;0"/>
+              <param name="PFM_TNVS_NS" value="4000" caption="See Note 2"/>
+              <param name="PFM_TPROG_NS" value="18000" caption="See Note 3"/>
+              <param name="PFM_TPREPROG_NS" value="3000" caption="See Note 3"/>
+              <param name="PFM_TADS_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TADH_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TPGS_NS" value="8000" caption="See Note 2"/>
+              <param name="PFM_TPREPGH_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TPREPGS_NS" value="1000" caption="See Note 2"/>
+              <param name="PFM_TPGH_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TRCV_PROG_NS" value="5000" caption="See Note 2"/>
+              <param name="PFM_TRCV_ERASE_NS" value="50000" caption="See Note 2"/>
+              <param name="PFM_TERASE_NS" value="18000000" caption="See Note 3"/>
+              <param name="PFM_TERASE_RETRY_NS" value="4500000" caption="See Note 3"/>
+              <param name="PFM_TSCE_NS" value="18000000" caption="See Note 3"/>
+              <param name="PFM_TRW_NS" value="100" caption="See Note 2"/>
+              <param name="PFM_TPUMPENS" value="1000" caption="See Note 2"/>
+              <param name="PFM_TPUMPENH" value="100" caption="See Note 2"/>
+              <param name="PFM_TPUMP_CYCLES" value="1029" caption="See Note 2"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="2" caption="H2PB Peripheral ID"/>
+              <param name="FLASH_SIZE" value="524288"/>
+              <param name="INSTANCE_ID" value="2" caption="Instance index for FCW"/>
+              <param name="MCLK_ID_AHB" value="2" caption="Index for FCW AHB clock"/>
+              <param name="PAC_ID" value="2" caption="Index for FCW registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FPB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="FPB">
+            <register-group name="FPB" name-in-module="FPB" address-space="base" offset="0xE0002000"/>
+            <parameters>
+              <param name="__BKPT_NUM" value="4" caption="Number of FPB breakpoint comparators"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FREQM" id="03707" name2="clk_freqm_u2257_v3" version="3a0">
+          <instance name="FREQM">
+            <register-group name="FREQM" name-in-module="FREQM" address-space="base" offset="0x4400C000"/>
+            <parameters>
+              <param name="MSRCLK_NB" value="2" caption="Number of measured clock sources"/>
+              <param name="GCLK_ID_MSR0" value="2"/>
+              <param name="GCLK_ID_MSR1" value="3"/>
+              <param name="GCLK_ID_REF" value="4"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="6" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="10" caption="Instance index for FREQM"/>
+              <param name="MCLK_ID_APB" value="10" caption="Index for FREQM APB clock"/>
+              <param name="PAC_ID" value="10" caption="Index for FREQM registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="fuses" name2="fuses" version="1a0">
+          <instance name="FUSES">
+            <register-group name="FUSES_ROMCFG" name-in-module="FUSES_ROMCFG" address-space="base" offset="0x0A003000"/>
+<register-group name="FUSES_BOOTCFG1" name-in-module="FUSES_BOOTCFG1" address-space="base" offset="0x0A002000"/>
+<register-group name="FUSES_BOOTCFG1A" name-in-module="FUSES_BOOTCFG1" address-space="base" offset="0x0A000000"/>
+            <register-group name="FUSES_CALOTP" name-in-module="FUSES_CALOTP" address-space="base" offset="0x0A007000"/>
+          </instance>
+        </module>
+        <module name="GCLK" id="03588" name2="clk_gclk_u2122_v1" version="1d0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x44008000"/>
+            <signals>
+              <signal group="IO" index="0" function="K" pad="PB06"/>
+              <signal group="IO" index="0" function="K" pad="PC09"/>
+              <signal group="IO" index="0" function="K" pad="PD05"/>
+              <signal group="IO" index="1" function="K" pad="PC00"/>
+              <signal group="IO" index="1" function="K" pad="PC10"/>
+              <signal group="IO" index="1" function="K" pad="PC05"/>
+              <signal group="IO" index="1" function="K" pad="PD04"/>
+              <signal group="IO" index="2" function="K" pad="PC01"/>
+              <signal group="IO" index="3" function="K" pad="PC02"/>
+              <signal group="IO" index="4" function="K" pad="PC03"/>
+              <signal group="IO" index="5" function="K" pad="PC04"/>
+              <signal group="IO" index="6" function="K" pad="PB10"/>
+              <signal group="IO" index="7" function="K" pad="PB09"/>
+              <signal group="TST_GCLK" function="DSU_TEST_GCLK" pad="PC08"/>
+            </signals>
+            <parameters>
+              <param name="GEN_NUM" value="12" caption="--"/>
+              <param name="IO_NUM" value="8" caption="derived, # of &quot;1&quot; in GCLK_GEN_IO_EXIST"/>
+              <param name="MUXED_NUM" value="39" caption="Number of GCLK channels"/>
+              <param name="SOURCE_NUM" value="11" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="4" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="8" caption="Instance index for GCLK"/>
+              <param name="MCLK_ID_APB" value="8" caption="Index for GCLK APB clock"/>
+              <param name="PAC_ID" value="8" caption="Index for GCLK registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="H2PB" id="04947" name2="bus_ahb2apb_v1" version="1a0">
+          <instance name="H2PB0">
+            <register-group name="H2PB0" name-in-module="H2PB" address-space="base" offset="0x44032000"/>
+            <parameters>
+              <param name="H2PB_MST_N" value="2" caption="--"/>
+              <param name="H2PB_MST_MAX" value="1" caption="derived parameter"/>
+              <param name="H2PB_SLV_N" value="32" caption="--"/>
+              <param name="H2PB_SLV_MAX" value="31" caption="derived parameter"/>
+              <param name="H2PB_PADDR_IDXB" value="5" caption="derived parameter"/>
+              <param name="H2PB_PADDR_LSB" value="13" caption="--"/>
+              <param name="H2PB_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="H2PB_PAGE_SIZE" value="8192" caption="derived parameter"/>
+              <param name="H2PB_OWN_SFR_SLOT" value="25" caption="--"/>
+              <param name="H2PB_PADDR_SIZE" value="18" caption="local parameter"/>
+              <param name="H2PB_PADDR_MSB" value="17" caption="derived local parameter"/>
+              <param name="H2PB_BASE_MSB" value="13" caption="derived parameter"/>
+              <param name="H2PB_USE_HSEL" value="1" caption="--"/>
+              <param name="H2PB_USE_DPATH_PIPER" value="0" caption="1=&quot;all pipelined&quot;0=&quot;address pipelined&quot;"/>
+              <param name="H2PB_USE_EARLY_PREAD" value="0" caption="--"/>
+              <param name="H2PB_CLK_DIV_EN" value="0" caption="1=&quot;n:1 clock&quot;0=&quot;1:1 clock&quot;"/>
+              <param name="H2PB_USE_PSTRB_FOR_READS" value="1" caption="--"/>
+              <param name="H2PB_WPCTRL_KEY" value="0x504230" caption="--"/>
+              <param name="H2PB_NONSEC_INIT_VAL" value="0x00000001" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="25" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="19" caption="Instance index for H2PB0"/>
+              <param name="MCLK_ID_AHB" value="25" caption="Index for H2PB0 AHB clock"/>
+              <param name="MCLK_ID_APB" value="26" caption="Index for H2PB0 APB clock"/>
+              <param name="PAC_ID" value="19" caption="Index for H2PB0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="H2PB1">
+            <register-group name="H2PB1" name-in-module="H2PB" address-space="base" offset="0x44838000"/>
+            <parameters>
+              <param name="H2PB_MST_N" value="2" caption="--"/>
+              <param name="H2PB_MST_MAX" value="1" caption="derived parameter"/>
+              <param name="H2PB_SLV_N" value="32" caption="--"/>
+              <param name="H2PB_SLV_MAX" value="31" caption="derived parameter"/>
+              <param name="H2PB_PADDR_IDXB" value="5" caption="derived parameter"/>
+              <param name="H2PB_PADDR_LSB" value="13" caption="--"/>
+              <param name="H2PB_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="H2PB_PAGE_SIZE" value="8192" caption="derived parameter"/>
+              <param name="H2PB_OWN_SFR_SLOT" value="28" caption="--"/>
+              <param name="H2PB_PADDR_SIZE" value="18" caption="local parameter"/>
+              <param name="H2PB_PADDR_MSB" value="17" caption="derived local parameter"/>
+              <param name="H2PB_BASE_MSB" value="13" caption="derived parameter"/>
+              <param name="H2PB_USE_HSEL" value="1" caption="--"/>
+              <param name="H2PB_USE_DPATH_PIPER" value="0" caption="1=&quot;all pipelined&quot;0=&quot;address pipelined&quot;"/>
+              <param name="H2PB_USE_EARLY_PREAD" value="0" caption="--"/>
+              <param name="H2PB_CLK_DIV_EN" value="0" caption="1=&quot;n:1 clock&quot;0=&quot;1:1 clock&quot;"/>
+              <param name="H2PB_USE_PSTRB_FOR_READS" value="1" caption="--"/>
+              <param name="H2PB_WPCTRL_KEY" value="0x504231" caption="--"/>
+              <param name="H2PB_NONSEC_INIT_VAL" value="0x00000000" caption="--"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="28" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="46" caption="Instance index for H2PB1"/>
+              <param name="MCLK_ID_AHB" value="57" caption="Index for H2PB1 AHB clock"/>
+              <param name="MCLK_ID_APB" value="58" caption="Index for H2PB1 APB clock"/>
+              <param name="PAC_ID" value="46" caption="Index for H2PB1 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="H2PB2">
+            <register-group name="H2PB2" name-in-module="H2PB" address-space="base" offset="0x4500E000"/>
+            <parameters>
+              <param name="H2PB_MST_N" value="1" caption="--"/>
+              <param name="H2PB_MST_MAX" value="0" caption="derived parameter"/>
+              <param name="H2PB_SLV_N" value="8" caption="--"/>
+              <param name="H2PB_SLV_MAX" value="7" caption="derived parameter"/>
+              <param name="H2PB_PADDR_IDXB" value="3" caption="derived parameter"/>
+              <param name="H2PB_PADDR_LSB" value="13" caption="--"/>
+              <param name="H2PB_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="H2PB_PAGE_SIZE" value="8192" caption="derived parameter"/>
+              <param name="H2PB_OWN_SFR_SLOT" value="7" caption="--"/>
+              <param name="H2PB_PADDR_SIZE" value="16" caption="local parameter"/>
+              <param name="H2PB_PADDR_MSB" value="15" caption="derived local parameter"/>
+              <param name="H2PB_BASE_MSB" value="15" caption="derived parameter"/>
+              <param name="H2PB_USE_HSEL" value="1" caption="--"/>
+              <param name="H2PB_USE_DPATH_PIPER" value="1" caption="1=&quot;all pipelined&quot;0=&quot;address pipelined&quot;"/>
+              <param name="H2PB_USE_EARLY_PREAD" value="0" caption="--"/>
+              <param name="H2PB_CLK_DIV_EN" value="1" caption="1=&quot;n:1 clock&quot;0=&quot;1:1 clock&quot;"/>
+              <param name="H2PB_USE_PSTRB_FOR_READS" value="1" caption="--"/>
+              <param name="H2PB_WPCTRL_KEY" value="0x504232" caption="--"/>
+              <param name="H2PB_NONSEC_INIT_VAL" value="0x00" caption="--"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="7" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="47" caption="Instance index for H2PB2"/>
+              <param name="MCLK_ID_AHB" value="59" caption="Index for H2PB2 AHB clock"/>
+              <param name="MCLK_ID_APB" value="60" caption="Index for H2PB2 APB clock"/>
+              <param name="PAC_ID" value="47" caption="Index for H2PB2 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIX2" id="bus_hmatrix2_v5" name2="bus_hmatrix2_v5" version="5f0">
+          <instance name="HMATRIX2">
+            <register-group name="HMATRIX2" name-in-module="HMATRIX2" address-space="base" offset="0x44010000"/>
+            <parameters>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="8" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="22" caption="Instance index for HMATRIX2"/>
+              <param name="MCLK_ID_AHB" value="30" caption="Index for HMATRIX2 AHB clock"/>
+              <param name="MCLK_ID_APB" value="31" caption="Index for HMATRIX2 APB clock"/>
+              <param name="PAC_ID" value="22" caption="Index for HMATRIX2 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ICB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="ICB">
+            <register-group name="ICB" name-in-module="ICB" address-space="base" offset="0xE000E000"/>
+          </instance>
+        </module>
+        <module name="MCLK" id="04158" name2="clk_mclk_v1" version="1a0">
+          <instance name="MCLK">
+            <register-group name="MCLK" name-in-module="MCLK" address-space="base" offset="0x4400A000"/>
+            <parameters>
+              <param name="MCLK_SYNC_EDGES" value="1" caption="--"/>
+              <param name="MCLK_DIV_CLK_NUM" value="3" caption="one for all other, one for H2PB2 domain, one for MBISTINTF"/>
+              <param name="MCLK_CKDIV_REGS_BITS" value="8" caption="--"/>
+              <param name="MCLK_CKDIV_RESET_VALUE" value="0x1 0x2 0x4 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1" caption="values must be binary divisor numberunused divisors must be 8'h1"/>
+              <param name="MCLK_CKDIV_WRLOCK" value="0x00000000" caption="--"/>
+              <param name="MCLK_CPU_CLK_DIVIDER" value="0" caption="--"/>
+              <param name="MCLK_CPU_CLK_IDLE" value="0" caption="--"/>
+              <param name="MCLK_CPU_CLK_OFFDLY" value="2" caption="--"/>
+              <param name="MCLK_CPU_CLK_ONDLY" value="0" caption="--"/>
+              <param name="MCLK_SYS_CLK_DIVIDER" value="0" caption="--"/>
+              <param name="MCLK_SYS_CLK_OFFDLY" value="2" caption="--"/>
+              <param name="MCLK_CLKMSK_NUM" value="65" caption="--"/>
+              <param name="MCLK_CKPER_IMPLEMENTED" value="0xFFFFFFFF 0xFFFFFFFF 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_RSTVAL" value="0xFFEEFFFF 0xFFFFFFFF 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_DIVIDER" value="0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0" caption="--"/>
+              <param name="MCLK_CKPER_REQEXISTS" value="0xD9FFFFFF 0xE1FFFFFF 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_MASTER" value="0x11800004 0x40400000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_WILLRISE" value="0x00080000 0x10000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="JTAG_IMPLEMENTED" value="1" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="5" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="9" caption="Instance index for MCLK"/>
+              <param name="MCLK_ID_APB" value="9" caption="Index for MCLK APB clock"/>
+              <param name="PAC_ID" value="9" caption="Index for MCLK registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MCRAMC" id="04921" name2="drm_mcramc_v5" version="5b0">
+          <instance name="MCRAMC">
+            <register-group name="MCRAMC" name-in-module="MCRAMC" address-space="base" offset="0x4402C000"/>
+            <parameters>
+              <param name="AHB_CLOCK_ENABLE" value="0" caption="--"/>
+              <param name="AHB_ECC" value="1" caption="--"/>
+              <param name="AHB_PORTS_NB" value="8" caption="--"/>
+              <param name="AHB_READ_PREBUFFERING" value="0" caption="--"/>
+              <param name="AHB_REQUEST_ISOLATION_REGISTER" value="0" caption="--"/>
+              <param name="ARBITRATION_TYPE" value="2" caption="Parameter should be &quot;ENUM_HOPSCOTCH&quot;Fix for text parameter in ConstellationCONST_DEV-1173"/>
+              <param name="BIT_STROBE_RAM" value="0" caption="parameter n/a if STORE_BYTE_STROBE=0"/>
+              <param name="CHANNELS_NB" value="2" caption="--"/>
+              <param name="ECC_SYNDROM_REGISTER" value="0" caption="--"/>
+              <param name="HADDR_READ_ISOLATION_REGISTER" value="0" caption="--"/>
+              <param name="HRDATA_ISOLATION_CONFIGURABLE" value="1" caption="--"/>
+              <param name="HRDATA_ISOLATION_DEFAULT" value="0" caption="default to 0 wait states"/>
+              <param name="MCRAMC_CLK_GATER" value="0" caption="--"/>
+              <param name="MCRAMC_PADDR_SIZE" value="13" caption="--"/>
+              <param name="MEMORY_AUTO_CORRECTION" value="1" caption="--"/>
+              <param name="MEMORY_ENABLE_POLARITY" value="0" caption="--"/>
+              <param name="MW_CLOCK_ENABLE" value="0" caption="--"/>
+              <param name="MW_DATA_SIZE" value="32" caption="--"/>
+              <param name="MW_PORT_SLICES_NB" value="0" caption="--"/>
+              <param name="M0_CLOCK_ENABLE" value="0" caption="--"/>
+              <param name="M0_DATA_SIZE" value="32" caption="--"/>
+              <param name="M0_HYBRID_READ_WRITE_ACCESS" value="0" caption="--"/>
+              <param name="M0_PORT_SLICES_NB" value="0" caption="--"/>
+              <param name="PRIVILEGED_BIT_CHECK" value="1" caption="--"/>
+              <param name="RAM_ADD_SIZE" value="14" caption="--"/>
+              <param name="RAM_AHB_ADDRESS_OFFSET" value="0" caption="--"/>
+              <param name="RAM_ERASE" value="0" caption="--"/>
+              <param name="STORE_BYTE_STROBE" value="0" caption="--"/>
+              <param name="ULTRA" value="1" caption="--"/>
+              <param name="WP_KEY" value="0x465852" caption="&quot;FXR&quot;"/>
+              <param name="WRITE_ENABLE_POLARITY" value="0" caption="--"/>
+              <param name="WRITE_ENABLE_USED" value="1" caption="--"/>
+              <param name="WRITE_MASK_POLARITY" value="0" caption="--"/>
+              <param name="WRITE_PROTECT_REGISTER" value="0" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="22" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="16" caption="Instance index for MCRAMC"/>
+              <param name="MCLK_ID_APB" value="21" caption="Index for MCRAMC APB clock"/>
+              <param name="MCLK_ID_AHB" value="22" caption="Index for MCRAMC AHB clock"/>
+              <param name="PAC_ID" value="16" caption="Index for MCRAMC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MPU" id="SYSTEM_IP" version="1.0.0">
+          <instance name="MPU">
+            <register-group name="MPU" name-in-module="MPU" address-space="base" offset="0xE000ED90"/>
+            <parameters>
+              <param name="__MPU_REGIONS" value="8" caption="Number of MPU regions"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVIC" id="SYSTEM_IP" version="1.0.0">
+          <instance name="NVIC">
+            <register-group name="NVIC" name-in-module="NVIC" address-space="base" offset="0xE000E100"/>
+            <parameters>
+              <param name="NUM_IRQ" value="141" caption="Number of interrupt request lines"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="OSC32KCTRL" id="03717" name2="osc_osc32kctrl_u2400_v2" version="2a0">
+          <instance name="OSC32KCTRL">
+            <register-group name="OSC32KCTRL" name-in-module="OSC32KCTRL" address-space="base" offset="0x45008000"/>
+            <signals>
+              <signal group="CLKIN32" index="32" function="XOSC32K_XIN32_AMODE" pad="PB01"/>
+              <signal group="XIN32" index="32" function="XOSC32K_XIN32" pad="PB01"/>
+              <signal group="XOUT32" index="32" function="XOSC32K_XOUT32" pad="PB02"/>
+            </signals>
+            <parameters>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="4" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="7" caption="Instance index for OSC32KCTRL"/>
+              <param name="MCLK_ID_APB" value="7" caption="Index for OSC32KCTRL APB clock"/>
+              <param name="PAC_ID" value="7" caption="Index for OSC32KCTRL registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="OSCCTRL" id="03718" name2="osc_oscctrl_u2401_v2" version="2b0">
+          <instance name="OSCCTRL">
+            <register-group name="OSCCTRL" name-in-module="OSCCTRL" address-space="base" offset="0x44006000"/>
+            <signals>
+              <signal group="CLKIN" function="XOSC_XIN_AMODE" pad="PD05"/>
+              <signal group="XIN" function="XOSC_XIN" pad="PD05"/>
+              <signal group="XOUT" function="XOSC_XOUT" pad="PD04"/>
+            </signals>
+            <parameters>
+              <param name="DFLL48M_ATEST_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DFLL48M_ATEST_SIZE" value="8" caption="--"/>
+              <param name="DFLL48M_IS_STARTUP_OSCILLATOR" value="1" caption="--"/>
+              <param name="DFLL48M_RC48MCAL0_PORVAL" value="0x00000000" caption="--"/>
+              <param name="DIV_8MHZ_NUM" value="2" caption="--"/>
+              <param name="FRACDIVS_NUM" value="0" caption="--"/>
+              <param name="FRACDIV_DIVIDER_RESET_VAL" value="0" caption="--"/>
+              <param name="FRACDIV_PLLSRC" value="0" caption="--"/>
+              <param name="PLLS_NUM" value="1" caption="--"/>
+              <param name="PLL0_OUTPUTS_NUM" value="5" caption="--"/>
+              <param name="PLL1_OUTPUTS_NUM" value="0" caption="--"/>
+              <param name="USBHS_NUM" value="1" caption="should be 0, but IP has bug"/>
+              <param name="XOSC_ATEST_IMPLEMENTED" value="1" caption="--"/>
+              <param name="XOSC_ATEST_SIZE" value="4" caption="--"/>
+              <param name="XOSC_CFD_CLK_SELECT_SIZE" value="4" caption="--"/>
+              <param name="XOSC_CFD_HAS_RETENTION" value="0" caption="--"/>
+              <param name="GCLK_ID_DFLL48M" value="0"/>
+              <param name="GCLK_ID_PLL" value="1"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="3" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="6" caption="Instance index for OSCCTRL"/>
+              <param name="MCLK_ID_APB" value="6" caption="Index for OSCCTRL APB clock"/>
+              <param name="PAC_ID" value="6" caption="Index for OSCCTRL registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PAC" id="04298" name2="sec_pac_apb_v1" version="1a0">
+          <instance name="PAC">
+            <register-group name="PAC" name-in-module="PAC" address-space="base" offset="0x44022000"/>
+            <parameters>
+              <param name="PAC_PER_WRPROT_MASK" value="0xFFFFFFFF 0x0003FFFF 0x00000000 0x00000000" caption="Peripheral implemented mask. If PAC_PER_WRPROT_MASK[x]=1 then the PAC implements an SFR bit in INTFLAG, STATUS, and LOCK with the location of &lt;REG&gt;(x/32)[x mod 32]"/>
+              <param name="PAC_STATUS_RESET_VALUE" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="WRP STATUS Reset Value for Peripherals. On reset STATUS(x/32)[x mod 32]=PAC_STATUS_RESET_VALUE[x]The reset value for each peripheral should always be 0. The parameter exists if there is an unforeseen circumstance requiring it to be 1. Test blocks are not one of them as they are protected by dsu_test_mode."/>
+              <param name="PAC_LOCK_RESET_VALUE" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="PAC_ERRORS_INBAND" value="1" caption="--"/>
+              <param name="PAC_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="PAC_INTFLAGSET_IMPLEMENTED" value="0" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="17" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="14" caption="Instance index for PAC"/>
+              <param name="MCLK_ID_APB" value="14" caption="Index for PAC APB clock"/>
+              <param name="PAC_ID" value="14" caption="Index for PAC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PDM" id="test_pdm_v1" name2="test_pdm_v1" version="1.0.0">
+          <instance name="PDM">
+            <signals>
+              <signal group="PDMDIS" function="TST_DIG" pad="PDMDIS"/>
+              <signal group="PDMI" index="0" function="PDMI_TEST" pad="PD07"/>
+              <signal group="PDMI" index="1" function="PDMI_TEST" pad="PD08"/>
+              <signal group="PDMI" index="2" function="PDMI_TEST" pad="PD09"/>
+              <signal group="PDMI" index="3" function="PDMI_TEST" pad="PA00"/>
+              <signal group="PDMO" index="0" function="PDMO_LV_TEST" pad="PB03"/>
+              <signal group="PDMO" index="1" function="PDMO_LV_TEST" pad="PB04"/>
+              <signal group="PDMO" index="2" function="PDMO_LV_TEST" pad="PB05"/>
+              <signal group="PDMO" index="3" function="PDMO_LV_TEST" pad="PB06"/>
+              <signal group="PDMO" index="4" function="PDMO_LV_TEST" pad="PC00"/>
+              <signal group="PDMO" index="5" function="PDMO_LV_TEST" pad="PC01"/>
+              <signal group="PDMO" index="6" function="PDMO_LV_TEST" pad="PC02"/>
+              <signal group="PDMO" index="7" function="PDMO_LV_TEST" pad="PC03"/>
+              <signal group="PDMO0_MV" function="PDMO_MV_TEST" pad="PB03"/>
+              <signal group="PDMO1_MV" function="PDMO_MV_TEST" pad="PB04"/>
+              <signal group="PDMO2_MV" function="PDMO_MV_TEST" pad="PB05"/>
+              <signal group="PDMO3_MV" function="PDMO_MV_TEST" pad="PB06"/>
+              <signal group="PDMO4_MV" function="PDMO_MV_TEST" pad="PC00"/>
+              <signal group="PDMO5_MV" function="PDMO_MV_TEST" pad="PC01"/>
+              <signal group="PDMO6_MV" function="PDMO_MV_TEST" pad="PC02"/>
+              <signal group="PDMO7_MV" function="PDMO_MV_TEST" pad="PC03"/>
+            </signals>
+          </instance>
+        </module>
+        <module name="PM" id="03926" name2="pwr_rpmu_pm_v1" version="1c0">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x45000000"/>
+            <parameters>
+              <param name="BACKUP_IMPLEMENTED" value="1" caption="--"/>
+              <param name="PD_NUM" value="1" caption="Number of Switchable Power Domains2 total domains (PD_CORE_SW and PD_CORE_BU)"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="0" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="3" caption="Instance index for PM"/>
+              <param name="MCLK_ID_APB" value="3" caption="Index for PM APB clock"/>
+              <param name="PAC_ID" value="3" caption="Index for PM registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PORT" id="03720" name2="gpio_port_u2210_v4" version="4a0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x44800000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="32" function="default" pad="PB00"/>
+              <signal group="P" index="33" function="default" pad="PB01"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="36" function="default" pad="PB04"/>
+              <signal group="P" index="37" function="default" pad="PB05"/>
+              <signal group="P" index="38" function="default" pad="PB06"/>
+              <signal group="P" index="39" function="default" pad="PB07"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+              <signal group="P" index="42" function="default" pad="PB10"/>
+              <signal group="P" index="64" function="default" pad="PC00"/>
+              <signal group="P" index="65" function="default" pad="PC01"/>
+              <signal group="P" index="66" function="default" pad="PC02"/>
+              <signal group="P" index="67" function="default" pad="PC03"/>
+              <signal group="P" index="68" function="default" pad="PC04"/>
+              <signal group="P" index="69" function="default" pad="PC05"/>
+              <signal group="P" index="70" function="default" pad="PC06"/>
+              <signal group="P" index="71" function="default" pad="PC07"/>
+              <signal group="P" index="72" function="default" pad="PC08"/>
+              <signal group="P" index="73" function="default" pad="PC09"/>
+              <signal group="P" index="74" function="default" pad="PC10"/>
+              <signal group="P" index="96" function="default" pad="PD00"/>
+              <signal group="P" index="97" function="default" pad="PD01"/>
+              <signal group="P" index="98" function="default" pad="PD02"/>
+              <signal group="P" index="99" function="default" pad="PD03"/>
+              <signal group="P" index="100" function="default" pad="PD04"/>
+              <signal group="P" index="101" function="default" pad="PD05"/>
+              <signal group="P" index="102" function="default" pad="PD06"/>
+              <signal group="P" index="103" function="default" pad="PD07"/>
+              <signal group="P" index="104" function="default" pad="PD08"/>
+              <signal group="P" index="105" function="default" pad="PD09"/>
+              <signal group="P" index="106" function="default" pad="PD10"/>
+              <signal group="P" index="107" function="default" pad="PD11"/>
+              <signal group="P" index="108" function="default" pad="PD12"/>
+              <signal group="P" index="109" function="default" pad="PD13"/>
+            </signals>
+            <parameters>
+              <param name="AHB_IMPLEMENTED" value="0" caption="No AHB bus"/>
+              <param name="BITS" value="117" caption="--"/>
+              <param name="DIR_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DIR_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="DIR RegistersImplemented"/>
+              <param name="DRVSTR" value="0" caption="No DRVSTR bits"/>
+              <param name="DRVSTR_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DRVSTR_IMPLEMENTED" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="PINCFG.DRVSTR0RegistersImplemented"/>
+              <param name="DRVSTR1_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DRVSTR1_IMPLEMENTED" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="PINCFG.DRVSTR1RegistersImplemented"/>
+              <param name="EVENT_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="Event RegistersImplemented"/>
+              <param name="EV_NUM" value="4" caption="--"/>
+              <param name="GROUPS" value="4" caption="--"/>
+              <param name="HADDR_MSB" value="31" caption="--"/>
+              <param name="INEN_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="INEN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.INENRegistersImplemented"/>
+              <param name="IOBUS_IMPLEMENTED" value="0" caption="No IOBUS"/>
+              <param name="MSB" value="116" caption="PORT_BITS-1"/>
+              <param name="NONSEC_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="NONSEC_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="NONSECRegistersImplemented"/>
+              <param name="ODRAIN" value="1" caption="--"/>
+              <param name="ODRAIN_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="ODRAIN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.ODRAINRegistersImplemented"/>
+              <param name="OUT_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="OUT_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="OUT RegistersImplemented"/>
+              <param name="PIN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="Port PinsImplemented"/>
+              <param name="PMUXBIT0_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x0000000C" caption="--"/>
+              <param name="PMUXBIT0_IMPLEMENTED" value="0x001FFFFF 0x0003FFF9 0x000FFE7F 0x001FFFC3" caption="Bit 0 of PMUX field"/>
+              <param name="PMUXBIT1_DEFAULT_VAL" value="0x00000000 0x00000000 0x000001E0 0x0000000C" caption="--"/>
+              <param name="PMUXBIT1_IMPLEMENTED" value="0x0007FFFF 0x000387F9 0x000FFE7F 0x001FFFF3" caption="Bit 1 of PMUX field"/>
+              <param name="PMUXBIT2_DEFAULT_VAL" value="0x00000000 0x00000000 0x000001E0 0x0000000C" caption="--"/>
+              <param name="PMUXBIT2_IMPLEMENTED" value="0x001BFFFF 0x00007FF9 0x0000067F 0x00003FC3" caption="Bit 2 of PMUX field"/>
+              <param name="PMUXBIT3_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="PMUXBIT3_IMPLEMENTED" value="0x001FFFFF 0x0003FFF9 0x000BFE7F 0x001FDFF3" caption="Bit 3 of PMUX field"/>
+              <param name="PMUXEN_DEFAULT_VAL" value="0x00000000 0x00000000 0x000001E0 0x00000000" caption="--"/>
+              <param name="PMUXEN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.PMUXEN bit"/>
+              <param name="PPP_IMPLEMENTED" value="0" caption="No IOBUS2"/>
+              <param name="PULLEN_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="PULLEN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.PULLENRegistersImplemented"/>
+              <param name="SECURE_IMPLEMENTED" value="1" caption="Mixed Secure Enabled"/>
+              <param name="SLEWLIM" value="2" caption="Number of SLEWLIM bit"/>
+              <param name="SLEWLIM_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="SLEWLIM_IMPLEMENTED" value="0x0007C07F 0x00038078 0x000FF87F 0x001FCFC3" caption="PINCFG.SLEWLIM0RegistersImplemented"/>
+              <param name="SLEWLIM1_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="SLEWLIM1_IMPLEMENTED" value="0x0007C07F 0x00038078 0x000FF87F 0x001FCFC3" caption="PINCFG.SLEWLIM1RegistersImplemented"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="0" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="20" caption="Instance index for PORT"/>
+              <param name="MCLK_ID_APB" value="27" caption="Index for PORT APB clock"/>
+              <param name="PAC_ID" value="20" caption="Index for PORT registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="04743" name2="afe_ptc_ctrl_apb_plrs_v1" version="1a0">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x4482C000"/>
+            <signals>
+              <signal group="PTCXY" index="0" function="P" pad="PD06"/>
+              <signal group="PTCXY" index="1" function="P" pad="PD07"/>
+              <signal group="PTCXY" index="2" function="P" pad="PD08"/>
+              <signal group="PTCXY" index="3" function="P" pad="PD09"/>
+              <signal group="PTCXY" index="4" function="P" pad="PA00"/>
+              <signal group="PTCXY" index="5" function="P" pad="PA01"/>
+              <signal group="PTCXY" index="6" function="P" pad="PA02"/>
+              <signal group="PTCXY" index="7" function="P" pad="PA03"/>
+              <signal group="PTCXY" index="8" function="P" pad="PA04"/>
+              <signal group="PTCXY" index="9" function="P" pad="PA05"/>
+              <signal group="PTCXY" index="10" function="P" pad="PA06"/>
+              <signal group="PTCXY" index="11" function="P" pad="PA07"/>
+              <signal group="PTCXY" index="12" function="P" pad="PA08"/>
+              <signal group="PTCXY" index="13" function="P" pad="PA09"/>
+              <signal group="PTCXY" index="14" function="P" pad="PB00"/>
+              <signal group="PTCXY" index="15" function="P" pad="PB03"/>
+              <signal group="PTCXY" index="16" function="P" pad="PB04"/>
+              <signal group="PTCXY" index="17" function="P" pad="PB05"/>
+              <signal group="PTCXY" index="18" function="P" pad="PB06"/>
+              <signal group="PTCXY" index="19" function="P" pad="PC00"/>
+              <signal group="PTCXY" index="20" function="P" pad="PC01"/>
+              <signal group="PTCXY" index="21" function="P" pad="PC02"/>
+              <signal group="PTCXY" index="22" function="P" pad="PA10"/>
+              <signal group="PTCXY" index="23" function="P" pad="PA11"/>
+              <signal group="PTCXY" index="24" function="P" pad="PA12"/>
+              <signal group="PTCXY" index="25" function="P" pad="PA13"/>
+              <signal group="PTCXY" index="26" function="P" pad="PB07"/>
+              <signal group="PTCXY" index="27" function="P" pad="PB08"/>
+              <signal group="PTCXY" index="28" function="P" pad="PB09"/>
+              <signal group="PTCXY" index="29" function="P" pad="PB10"/>
+              <signal group="PTCXY" index="30" function="P" pad="PC09"/>
+              <signal group="PTCXY" index="31" function="P" pad="PC10"/>
+              <signal group="DRV" index="0" function="P" pad="PD06"/>
+              <signal group="DRV" index="1" function="P" pad="PD07"/>
+              <signal group="DRV" index="2" function="P" pad="PD08"/>
+              <signal group="DRV" index="3" function="P" pad="PD09"/>
+              <signal group="DRV" index="4" function="P" pad="PA00"/>
+              <signal group="DRV" index="5" function="P" pad="PA01"/>
+              <signal group="DRV" index="6" function="P" pad="PA02"/>
+              <signal group="DRV" index="7" function="P" pad="PA03"/>
+              <signal group="DRV" index="8" function="P" pad="PA04"/>
+              <signal group="DRV" index="9" function="P" pad="PA05"/>
+              <signal group="DRV" index="10" function="P" pad="PA06"/>
+              <signal group="DRV" index="11" function="P" pad="PA07"/>
+              <signal group="DRV" index="12" function="P" pad="PA08"/>
+              <signal group="DRV" index="13" function="P" pad="PA09"/>
+              <signal group="DRV" index="14" function="P" pad="PB00"/>
+              <signal group="DRV" index="15" function="P" pad="PB03"/>
+              <signal group="DRV" index="16" function="P" pad="PB04"/>
+              <signal group="DRV" index="17" function="P" pad="PB05"/>
+              <signal group="DRV" index="18" function="P" pad="PB06"/>
+              <signal group="DRV" index="19" function="P" pad="PC00"/>
+              <signal group="DRV" index="20" function="P" pad="PC01"/>
+              <signal group="DRV" index="21" function="P" pad="PC02"/>
+              <signal group="DRV" index="22" function="P" pad="PA10"/>
+              <signal group="DRV" index="23" function="P" pad="PA11"/>
+              <signal group="DRV" index="24" function="P" pad="PA12"/>
+              <signal group="DRV" index="25" function="P" pad="PA13"/>
+              <signal group="DRV" index="26" function="P" pad="PB07"/>
+              <signal group="DRV" index="27" function="P" pad="PB08"/>
+              <signal group="DRV" index="28" function="P" pad="PB09"/>
+              <signal group="DRV" index="29" function="P" pad="PB10"/>
+              <signal group="DRV" index="30" function="P" pad="PC09"/>
+              <signal group="DRV" index="31" function="P" pad="PC10"/>
+              <signal group="ECI" index="0" function="P" pad="PC03"/>
+              <signal group="ECI" index="1" function="P" pad="PC04"/>
+            </signals>
+            <parameters>
+              <param name="PTC_PDATA_MSB" value="31" caption="APB Data Bus Size MSB"/>
+              <param name="PTC_PADDR_MSB" value="12" caption="APB Address Bus Size MSB"/>
+              <param name="PTC_PADDR_SIZE" value="13" caption="Number of bits of the paddr input busPossible Values = PTC_PADDR_MSB -1"/>
+              <param name="PTC_LINES_NUM" value="36" caption="Number of PTC lines desired (0 to 64)"/>
+              <param name="PTC_CAL_IMPLEMENTED" value="1" caption="Defines if the CALIB register is implemented (1 = implemented)"/>
+              <param name="PTC_CAL_SIZE" value="16" caption="Defines Bitfield size for CALIB register"/>
+              <param name="PTC_CAL_PORVAL" value="0x00000000" caption="Defines the CALIB register reset value after POR0x00000000 to 0xFFFFFFFF"/>
+              <param name="PTC_ATEST_IMPLEMENTED" value="1" caption="Defines if the ATEST register is implemented (1 = implemented)"/>
+              <param name="PTC_ATEST_SIZE" value="8" caption="Defines the number of effective bits in ATEST register"/>
+              <param name="PTC_WPCTRL_IMPLEMENTED" value="0" caption="Implement the WPCTRL register for write protection.0 = Use apb_ptc_wrprot to control write protection enable/disable1 = Use WPCTRL register to control write protection enable/disable."/>
+              <param name="PTC_PRIV_IMPLEMENTED" value="1" caption="Implement the PRIV register for privilege/non-privilege bus accesses.0 = Register not present1 = Register present"/>
+              <param name="PTC_WPCTRL_KEY" value="0x505443" caption="WPCTRL 24-bit key value. See register description for usage.Set to a unique value for each macro."/>
+              <param name="GCLK_ID" value="35"/>
+              <param name="DMAC_ID_EOC" value="38"/>
+              <param name="DMAC_ID_SEQ" value="39"/>
+              <param name="DMAC_ID_WCOMP" value="40"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="22" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="41" caption="Instance index for PTC"/>
+              <param name="MCLK_ID_APB" value="51" caption="Index for PTC APB clock"/>
+              <param name="PAC_ID" value="41" caption="Index for PTC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RSTC" id="03926" name2="pwr_rpmu_rstc_v1" version="1c0">
+          <instance name="RSTC">
+            <register-group name="RSTC" name-in-module="RSTC" address-space="base" offset="0x45004000"/>
+            <parameters>
+              <param name="BACKUP_IMPLEMENTED" value="1"/>
+              <param name="CM_DBGRESET_STRETCHED" value="3" caption="Reset stretcher size for Cortex CPU related to DBGRESET."/>
+              <param name="CM_HRESET_N_STRETCHED" value="3" caption="Reset stretcher size for Cortex CPU related to HRESETn."/>
+              <param name="CM_PORESET_STRETCHED" value="3" caption="Reset stretcher size for Cortex CPU related to PORESET."/>
+              <param name="HIB_IMPLEMENTED" value="1"/>
+              <param name="VBAT_IMPLEMENTED" value="0" caption="One if VBAT (Battery backup mode) is supported"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="2" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="5" caption="Instance index for RSTC"/>
+              <param name="MCLK_ID_APB" value="5" caption="Index for RSTC APB clock"/>
+              <param name="PAC_ID" value="5" caption="Index for RSTC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="03608" name2="tmr_rtc_u2250_v3" version="3b0">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x45006000"/>
+            <signals>
+              <signal group="IN" index="0" function="RTC_PAD_IE" pad="PA07"/>
+              <signal group="IN" index="1" function="RTC_PAD_IE" pad="PA08"/>
+              <signal group="IN" index="2" function="RTC_PAD_IE" pad="PA09"/>
+              <signal group="IN" index="3" function="RTC_PAD_IE" pad="PB00"/>
+              <signal group="IN" index="4" function="RTC_PAD_IE" pad="PB07"/>
+              <signal group="IN" index="5" function="RTC_PAD_IE" pad="PB08"/>
+              <signal group="OUT" index="0" function="_RTC_PAD_OE_N" pad="PB03"/>
+              <signal group="OUT" index="1" function="_RTC_PAD_OE_N" pad="PB04"/>
+              <signal group="OUT" index="2" function="_RTC_PAD_OE_N" pad="PB05"/>
+              <signal group="OUT" index="3" function="_RTC_PAD_OE_N" pad="PB06"/>
+              <signal group="OUT" index="4" function="_RTC_PAD_OE_N" pad="PB09"/>
+              <signal group="OUT" index="5" function="_RTC_PAD_OE_N" pad="PB10"/>
+            </signals>
+            <parameters>
+              <param name="NUM_OF_ALARMS" value="2" caption="--"/>
+              <param name="NUM_OF_BKREGS" value="0" caption="--"/>
+              <param name="NUM_OF_COMP16" value="4" caption="=2 * RTC_NUM_OF_ALARMS"/>
+              <param name="NUM_OF_TAMPERS" value="8" caption="--"/>
+              <param name="DMAC_ID_TIMESTAMP" value="3"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="3" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="12" caption="Instance index for RTC"/>
+              <param name="MCLK_ID_APB" value="12" caption="Index for RTC APB clock"/>
+              <param name="PAC_ID" value="12" caption="Index for RTC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SAU" id="SYSTEM_IP" version="1.0.0">
+          <instance name="SAU">
+            <register-group name="SAU" name-in-module="SAU" address-space="base" offset="0xE000EDD0"/>
+          </instance>
+        </module>
+        <module name="SCB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="SCB">
+            <register-group name="SCB" name-in-module="SCB" address-space="base" offset="0xE000ED00"/>
+          </instance>
+        </module>
+        <module name="SERCOM" id="03715" name2="com_sercom_u2201_v6" version="6c0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x44808000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PC00" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PC01" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PC02" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PC03" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="DMAC_ID_RX" value="4"/>
+              <param name="DMAC_ID_TX" value="5"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="4" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="26" caption="Instance index for SERCOM0"/>
+              <param name="MCLK_ID_APB" value="36" caption="Index for SERCOM0 APB clock"/>
+              <param name="PAC_ID" value="26" caption="Index for SERCOM0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x4480A000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PD01"/>
+              <signal group="PAD" index="1" function="D" pad="PD00"/>
+              <signal group="PAD" index="2" function="D" pad="PC06" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PD10" ioset="2"/>
+              <signal group="PAD" index="3" function="D" pad="PC05" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PD11" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="DMAC_ID_RX" value="6"/>
+              <param name="DMAC_ID_TX" value="7"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="5" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="27" caption="Instance index for SERCOM1"/>
+              <param name="MCLK_ID_APB" value="37" caption="Index for SERCOM1 APB clock"/>
+              <param name="PAC_ID" value="27" caption="Index for SERCOM1 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x4480C000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PC04" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PD06" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PD07" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PD08" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="DMAC_ID_RX" value="8"/>
+              <param name="DMAC_ID_TX" value="9"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="6" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="28" caption="Instance index for SERCOM2"/>
+              <param name="MCLK_ID_APB" value="38" caption="Index for SERCOM2 APB clock"/>
+              <param name="PAC_ID" value="28" caption="Index for SERCOM2 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x4480E000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PD09" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PA00" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PA01" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PA02" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="DMAC_ID_RX" value="10"/>
+              <param name="DMAC_ID_TX" value="11"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="7" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="29" caption="Instance index for SERCOM3"/>
+              <param name="MCLK_ID_APB" value="39" caption="Index for SERCOM3 APB clock"/>
+              <param name="PAC_ID" value="29" caption="Index for SERCOM3 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x44820000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA03" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PA04" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PA05" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PA06" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="0" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="0" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_CORE" value="28"/>
+              <param name="DMAC_ID_RX" value="24"/>
+              <param name="DMAC_ID_TX" value="25"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="16" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="34" caption="Instance index for SERCOM4"/>
+              <param name="MCLK_ID_APB" value="44" caption="Index for SERCOM4 APB clock"/>
+              <param name="PAC_ID" value="34" caption="Index for SERCOM4 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x44822000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PB03" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PB04" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PB05" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PB06" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="0" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="0" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_CORE" value="29"/>
+              <param name="DMAC_ID_RX" value="26"/>
+              <param name="DMAC_ID_TX" value="27"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="17" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="35" caption="Instance index for SERCOM5"/>
+              <param name="MCLK_ID_APB" value="45" caption="Index for SERCOM5 APB clock"/>
+              <param name="PAC_ID" value="35" caption="Index for SERCOM5 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SUPC" id="03926" name2="pwr_rpmu_supc_v1" version="1c0">
+          <instance name="SUPC">
+            <register-group name="SUPC" name-in-module="SUPC" address-space="base" offset="0x45002000"/>
+            <signals>
+              <signal group="RESETn" function="RES" pad="RESET_N"/>
+              <signal group="SMOR_DTEST" index="0" function="SUPC_VREF_TESTMODE" pad="PD08"/>
+              <signal group="SMOR_DTEST" index="1" function="SUPC_VREF_TESTMODE" pad="PD09"/>
+              <signal group="SMOR_DTEST" index="2" function="SUPC_VREF_TESTMODE" pad="PD07"/>
+              <signal group="SMOR_DTEST" index="3" function="SUPC_VREF_TESTMODE" pad="PA00"/>
+              <signal group="SMOR_DTEST" index="4" function="SUPC_VREF_TESTMODE" pad="PA01"/>
+              <signal group="SMOR_DTEST" index="5" function="SUPC_VREF_TESTMODE" pad="PA02"/>
+              <signal group="SMOR_DTEST" index="6" function="SUPC_VREF_TESTMODE" pad="PA03"/>
+              <signal group="SMOR_DTEST" index="7" function="SUPC_VREF_TESTMODE" pad="PA04"/>
+              <signal group="SMOR_DTEST" index="8" function="SUPC_VREF_TESTMODE" pad="PB03"/>
+              <signal group="SMOR_DTEST" index="9" function="SUPC_VREF_TESTMODE" pad="PB04"/>
+              <signal group="SMOR_DTEST" index="10" function="SUPC_VREF_TESTMODE" pad="PB05"/>
+              <signal group="SMOR_DTEST" index="11" function="SUPC_VREF_TESTMODE" pad="PB06"/>
+              <signal group="SMOR_DTEST" index="12" function="SUPC_VREF_TESTMODE" pad="PC00"/>
+              <signal group="SMOR_DTEST" index="13" function="SUPC_VREF_TESTMODE" pad="PA06"/>
+              <signal group="SMOR_DTEST" index="14" function="SUPC_VREF_TESTMODE" pad="PA07"/>
+              <signal group="SMOR_DTEST" index="15" function="SUPC_VREF_TESTMODE" pad="PC03"/>
+              <signal group="OUT" index="0" function="SUPC" pad="PB04"/>
+              <signal group="OUT" index="1" function="SUPC" pad="PB05"/>
+              <signal group="USERLDO" function="USER_LDO" pad="PD06"/>
+              <signal group="USERLDO_OUT" function="USER_LDO_OP_AMP" pad="USERLDO"/>
+            </signals>
+            <parameters>
+              <param name="ADDVREG_NUM" value="1" caption="Jira PWR109-210"/>
+              <param name="ADDVREG_PLL_NUM" value="0" caption="--"/>
+              <param name="ADDVREG_PLL_START_INDEX" value="1" caption="--"/>
+              <param name="BKOUT_NUM" value="2" caption="--"/>
+              <param name="BORVDDUSB_NUM" value="1" caption="(Jira PWR109-219)"/>
+              <param name="CHRG_PUMP_NUM" value="2" caption="--"/>
+              <param name="IOB_IMPLEMENTED" value="0" caption="--"/>
+              <param name="USER_LDO_IMPLEMENTED" value="1" caption="--"/>
+              <param name="VBAT_IMPLEMENTED" value="0" caption="--"/>
+              <param name="VREGSW_NUM" value="1" caption="--"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="1" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="4" caption="Instance index for SUPC"/>
+              <param name="MCLK_ID_APB" value="4" caption="Index for SUPC APB clock"/>
+              <param name="PAC_ID" value="4" caption="Index for SUPC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SysTick" id="SYSTEM_IP" version="1.0.0">
+          <instance name="SysTick">
+            <register-group name="SysTick" name-in-module="SysTick" address-space="base" offset="0xE000E010"/>
+            <parameters>
+              <param name="__SYST_NUM" value="2" caption="Number of implemented SysTick timers"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="03610" name2="tmr_tcc_u2213_v4" version="4d0">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x44810000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PC00" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PC01" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="1" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID_TCC01" value="25"/>
+              <param name="DMAC_ID_OVF" value="12"/>
+              <param name="DMAC_ID_MC0" value="13"/>
+              <param name="DMAC_ID_MC1" value="14"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="8" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="30" caption="Instance index for TCC0"/>
+              <param name="MCLK_ID_APB" value="40" caption="Index for TCC0 APB clock"/>
+              <param name="PAC_ID" value="30" caption="Index for TCC0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x44812000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PC02" ioset="1"/>
+              <signal group="WO" index="0" function="F" pad="PC09" ioset="2"/>
+              <signal group="WO" index="1" function="F" pad="PC03" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PC10" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="2" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID_TCC01" value="25"/>
+              <param name="DMAC_ID_OVF" value="15"/>
+              <param name="DMAC_ID_MC0" value="16"/>
+              <param name="DMAC_ID_MC1" value="17"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="9" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="31" caption="Instance index for TCC1"/>
+              <param name="MCLK_ID_APB" value="41" caption="Index for TCC1 APB clock"/>
+              <param name="PAC_ID" value="31" caption="Index for TCC1 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x44814000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PB09" ioset="2"/>
+              <signal group="WO" index="0" function="F" pad="PC04" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PB08" ioset="2"/>
+              <signal group="WO" index="1" function="F" pad="PC05" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DMAC_ID_MC0" value="19"/>
+              <param name="DMAC_ID_MC1" value="20"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="10" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="32" caption="Instance index for TCC2"/>
+              <param name="MCLK_ID_APB" value="42" caption="Index for TCC2 APB clock"/>
+              <param name="PAC_ID" value="32" caption="Index for TCC2 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC3">
+            <register-group name="TCC3" name-in-module="TCC" address-space="base" offset="0x44816000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PD00" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PD01" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DMAC_ID_MC0" value="22"/>
+              <param name="DMAC_ID_MC1" value="23"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="11" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="33" caption="Instance index for TCC3"/>
+              <param name="MCLK_ID_APB" value="43" caption="Index for TCC3 APB clock"/>
+              <param name="PAC_ID" value="33" caption="Index for TCC3 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC4">
+            <register-group name="TCC4" name-in-module="TCC" address-space="base" offset="0x44824000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PA10" ioset="2"/>
+              <signal group="WO" index="0" function="F" pad="PD07" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PA11" ioset="2"/>
+              <signal group="WO" index="1" function="F" pad="PD08" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="DMAC_ID_OVF" value="28"/>
+              <param name="DMAC_ID_MC0" value="29"/>
+              <param name="DMAC_ID_MC1" value="30"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="18" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="36" caption="Instance index for TCC4"/>
+              <param name="MCLK_ID_APB" value="46" caption="Index for TCC4 APB clock"/>
+              <param name="PAC_ID" value="36" caption="Index for TCC4 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC5">
+            <register-group name="TCC5" name-in-module="TCC" address-space="base" offset="0x44826000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PD10" ioset="2"/>
+              <signal group="WO" index="0" function="F" pad="PD09" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PA00" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PD11" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="31"/>
+              <param name="DMAC_ID_OVF" value="31"/>
+              <param name="DMAC_ID_MC0" value="32"/>
+              <param name="DMAC_ID_MC1" value="33"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="19" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="37" caption="Instance index for TCC5"/>
+              <param name="MCLK_ID_APB" value="47" caption="Index for TCC5 APB clock"/>
+              <param name="PAC_ID" value="37" caption="Index for TCC5 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC6">
+            <register-group name="TCC6" name-in-module="TCC" address-space="base" offset="0x44828000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PA01" ioset="1"/>
+              <signal group="WO" index="0" function="F" pad="PD12" ioset="2"/>
+              <signal group="WO" index="1" function="F" pad="PA02" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PD13" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="32"/>
+              <param name="DMAC_ID_OVF" value="34"/>
+              <param name="DMAC_ID_MC0" value="35"/>
+              <param name="DMAC_ID_MC1" value="36"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="20" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="38" caption="Instance index for TCC6"/>
+              <param name="MCLK_ID_APB" value="48" caption="Index for TCC6 APB clock"/>
+              <param name="PAC_ID" value="38" caption="Index for TCC6 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TESTVAL" id="test_valio_mapper_v1" name2="test_valio_mapper_v1" version="1.0.0">
+          <instance name="TESTVAL">
+            <signals>
+              <signal group="VALIO" index="0" function="VALIO" pad="PD00"/>
+              <signal group="VALIO" index="1" function="VALIO" pad="PD01"/>
+              <signal group="VALIO" index="2" function="VALIO" pad="PC04"/>
+              <signal group="VALIO" index="3" function="VALIO" pad="PA05"/>
+              <signal group="VALIO" index="4" function="VALIO" pad="PC01"/>
+              <signal group="VALIO" index="5" function="VALIO" pad="PC02"/>
+            </signals>
+          </instance>
+        </module>
+        <module name="USB" id="03613" name2="usb_u2222_v1" version="1d0">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x44832000"/>
+            <signals>
+              <signal group="SOF" function="H" pad="PD01"/>
+              <signal group="USBDM" function="H" pad="PD02"/>
+              <signal group="USBDP" function="H" pad="PD03"/>
+            </signals>
+            <parameters>
+              <param name="AHB_2_USB_FIFO_DEPTH" value="4" caption="bytes number, should be at least 2, and 2^n (4,8,16 ...)"/>
+              <param name="AHB_2_USB_RD_DATA_BITS" value="8" caption="8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode"/>
+              <param name="AHB_2_USB_WR_DATA_BITS" value="32" caption="8, 16 or 32 : here, AHB transfer is made in word mode"/>
+              <param name="AHB_2_USB_WR_THRESHOLD" value="2" caption="as soon as there are N bytes-free inside the fifo, ahb read transfer is requested"/>
+              <param name="DATA_BUS_16_8" value="0" caption="UTMI/SIE data bus size : 0 -&gt; 8 bits, 1 -&gt; 16 bits"/>
+              <param name="EPNUM" value="8" caption="parameter for rtl : max of ENDPOINT and PIPE NUM"/>
+              <param name="EPT_NUM" value="8" caption="Number of USB end points"/>
+              <param name="INITIAL_CONTROL_QOS" value="3" caption="CONTROL QOS RESET value"/>
+              <param name="INITIAL_DATA_QOS" value="3" caption="DATA QOS RESET value"/>
+              <param name="MISSING_SOF_DET_IMPLEMENTED" value="1" caption="48 mHz xPLL feature implemented"/>
+              <param name="PIPE_NUM" value="8" caption="Number of USB pipes"/>
+              <param name="SYSTEM_CLOCK_IS_CKUSB" value="0" caption="Dual (1'b0) or Single (1'b1) clock system"/>
+              <param name="USB_2_AHB_FIFO_DEPTH" value="4" caption="bytes number, should be at least 2, and 2^n (4,8,16 ...)"/>
+              <param name="USB_2_AHB_RD_DATA_BITS" value="16" caption="8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode"/>
+              <param name="USB_2_AHB_RD_THRESHOLD" value="2" caption="as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested"/>
+              <param name="USB_2_AHB_WR_DATA_BITS" value="8" caption="8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode"/>
+              <param name="GCLK_ID" value="38"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="25" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="44" caption="Instance index for USB"/>
+              <param name="MCLK_ID_AHB" value="54" caption="Index for USB AHB clock"/>
+              <param name="MCLK_ID_APB" value="55" caption="Index for USB APB clock"/>
+              <param name="PAC_ID" value="44" caption="Index for USB registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="03611" name2="wdt_u2251_v2" version="2b0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x4400E000"/>
+            <parameters>
+              <param name="FUSES_UPDATE_SUPPORT" value="0" caption="WDT Fuse Update Support"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="7" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="11" caption="Instance index for WDT"/>
+              <param name="MCLK_ID_APB" value="11" caption="Index for WDT APB clock"/>
+              <param name="PAC_ID" value="11" caption="Index for WDT registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+      </peripherals>
+      <interrupts>
+        <interrupt name="Reset" index="-15" caption="Reset Vector, invoked on Power up and warm reset"/>
+        <interrupt name="NonMaskableInt" index="-14" caption="Non maskable Interrupt, cannot be stopped or preempted"/>
+        <interrupt name="HardFault" index="-13" caption="Hard Fault, all classes of Fault"/>
+        <interrupt name="SVCall" index="-5" caption="System Service Call via SVC instruction"/>
+        <interrupt name="PendSV" index="-2" caption="Pendable request for system service"/>
+        <interrupt name="SysTick" index="-1" caption="System Tick Timer"/>
+        <interrupt name="FCR" index="0" module-instance="FCR"/>
+        <interrupt name="FCW" index="1" module-instance="FCW"/>
+        <interrupt name="PM" index="2" module-instance="PM"/>
+        <interrupt name="SUPC" index="3" module-instance="SUPC"/>
+        <interrupt name="OSCCTRL_XOSCRDY" index="4" module-instance="OSCCTRL"/>
+        <interrupt name="OSCCTRL_DFLLRDY" index="5" module-instance="OSCCTRL"/>
+        <interrupt name="OSCCTRL_PLLLOCKR_0" index="6" module-instance="OSCCTRL"/>
+        <interrupt name="OSC32KCTRL_XOSC32KRDY" index="7" module-instance="OSC32KCTRL"/>
+        <interrupt name="OSC32KCTRL_XOSC32KFAIL" index="8" module-instance="OSC32KCTRL"/>
+        <interrupt name="MCLK" index="9" module-instance="MCLK"/>
+        <interrupt name="FREQM" index="10" module-instance="FREQM"/>
+        <interrupt name="WDT" index="11" module-instance="WDT"/>
+        <interrupt name="RTC_TAMPER" index="12" module-instance="RTC"/>
+        <interrupt name="RTC_OVF" index="13" module-instance="RTC"/>
+        <interrupt name="RTC_PER0" index="14" module-instance="RTC"/>
+        <interrupt name="RTC_CMP0" index="15" module-instance="RTC"/>
+        <interrupt name="EIC_EXTINT0" index="16" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT1" index="17" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT2" index="18" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT3" index="19" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT4" index="20" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT5" index="21" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT6" index="22" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT7" index="23" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT8" index="24" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT9" index="25" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT10" index="26" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT11" index="27" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT12" index="28" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT13" index="29" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT14" index="30" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT15" index="31" module-instance="EIC"/>
+        <interrupt name="EIC_NSCHK" index="32" module-instance="EIC"/>
+        <interrupt name="MCRAMC" index="34" module-instance="MCRAMC"/>
+        <interrupt name="CAN0_INT0" index="35" module-instance="CAN0"/>
+        <interrupt name="CAN0_INT1" index="36" module-instance="CAN0"/>
+        <interrupt name="CAN0_BERR" index="37" module-instance="CAN0"/>
+        <interrupt name="CAN1_INT0" index="38" module-instance="CAN1"/>
+        <interrupt name="CAN1_INT1" index="39" module-instance="CAN1"/>
+        <interrupt name="CAN1_BERR" index="40" module-instance="CAN1"/>
+        <interrupt name="PORT" index="41" module-instance="PORT"/>
+        <interrupt name="DMAC_TCMPL0" index="42" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL1" index="43" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL2" index="44" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL3" index="45" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL4" index="46" module-instance="DMAC"/>
+        <interrupt name="HMATRIX2" index="47" module-instance="HMATRIX2"/>
+        <interrupt name="EVSYS_EVD0" index="48" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD1" index="49" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD2" index="50" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD3" index="51" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD4" index="52" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD5" index="53" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD6" index="54" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD7" index="55" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD8" index="56" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD9" index="57" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD10" index="58" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD11" index="59" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_6" index="60" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_5" index="61" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_0" index="62" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_1" index="63" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_2" index="64" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_3" index="65" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_4" index="66" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_6" index="67" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_5" index="68" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_0" index="69" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_1" index="70" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_2" index="71" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_3" index="72" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_4" index="73" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_6" index="74" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_5" index="75" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_0" index="76" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_1" index="77" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_2" index="78" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_3" index="79" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_4" index="80" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_6" index="81" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_5" index="82" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_0" index="83" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_1" index="84" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_2" index="85" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_3" index="86" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_4" index="87" module-instance="SERCOM3"/>
+        <interrupt name="TCC0_DFS" index="88" module-instance="TCC0"/>
+        <interrupt name="TCC0_CNT" index="89" module-instance="TCC0"/>
+        <interrupt name="TCC0_MC0" index="90" module-instance="TCC0"/>
+        <interrupt name="TCC0_MC1" index="91" module-instance="TCC0"/>
+        <interrupt name="TCC1_DFS" index="92" module-instance="TCC1"/>
+        <interrupt name="TCC1_CNT" index="93" module-instance="TCC1"/>
+        <interrupt name="TCC1_MC0" index="94" module-instance="TCC1"/>
+        <interrupt name="TCC1_MC1" index="95" module-instance="TCC1"/>
+        <interrupt name="TCC2_DFS" index="96" module-instance="TCC2"/>
+        <interrupt name="TCC2_CNT" index="97" module-instance="TCC2"/>
+        <interrupt name="TCC2_MC0" index="98" module-instance="TCC2"/>
+        <interrupt name="TCC2_MC1" index="99" module-instance="TCC2"/>
+        <interrupt name="TCC3_DFS" index="100" module-instance="TCC3"/>
+        <interrupt name="TCC3_CNT" index="101" module-instance="TCC3"/>
+        <interrupt name="TCC3_MC0" index="102" module-instance="TCC3"/>
+        <interrupt name="TCC3_MC1" index="103" module-instance="TCC3"/>
+        <interrupt name="SERCOM4_6" index="104" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_5" index="105" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_0" index="106" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_1" index="107" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_2" index="108" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_3" index="109" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_4" index="110" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_6" index="111" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_5" index="112" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_0" index="113" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_1" index="114" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_2" index="115" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_3" index="116" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_4" index="117" module-instance="SERCOM5"/>
+        <interrupt name="TCC4_DFS" index="118" module-instance="TCC4"/>
+        <interrupt name="TCC4_CNT" index="119" module-instance="TCC4"/>
+        <interrupt name="TCC4_MC0" index="120" module-instance="TCC4"/>
+        <interrupt name="TCC4_MC1" index="121" module-instance="TCC4"/>
+        <interrupt name="TCC5_DFS" index="122" module-instance="TCC5"/>
+        <interrupt name="TCC5_CNT" index="123" module-instance="TCC5"/>
+        <interrupt name="TCC5_MC0" index="124" module-instance="TCC5"/>
+        <interrupt name="TCC5_MC1" index="125" module-instance="TCC5"/>
+        <interrupt name="TCC6_DFS" index="126" module-instance="TCC6"/>
+        <interrupt name="TCC6_CNT" index="127" module-instance="TCC6"/>
+        <interrupt name="TCC6_MC0" index="128" module-instance="TCC6"/>
+        <interrupt name="TCC6_MC1" index="129" module-instance="TCC6"/>
+        <interrupt name="ADC_REQ0" index="130" module-instance="ADC"/>
+        <interrupt name="ADC_REQ1" index="131" module-instance="ADC"/>
+        <interrupt name="AC" index="132" module-instance="AC"/>
+        <interrupt name="PTC" index="133" module-instance="PTC"/>
+        <interrupt name="USB_EORSMDNRSM" index="134" module-instance="USB"/>
+        <interrupt name="USB_SOFHSOF" index="135" module-instance="USB"/>
+        <interrupt name="USB_TRCPT00" index="136" module-instance="USB"/>
+        <interrupt name="USB_TRCPT10" index="137" module-instance="USB"/>
+        <interrupt name="AT" index="138" module-instance="AT"/>
+      </interrupts>
+      <events>
+        <generators>
+          <generator name="SUPC_LVDET" index="1" module-instance="SUPC"/>
+          <generator name="OSCCTRL_XOSCFAIL" index="2" module-instance="OSCCTRL"/>
+          <generator name="OSC32KCTRL_XOSC32KFAIL" index="3" module-instance="OSC32KCTRL"/>
+          <generator name="FREQM_DONE" index="4" module-instance="FREQM"/>
+          <generator name="FREQM_WINMON" index="5" module-instance="FREQM"/>
+          <generator name="RTC_PER0" index="6" module-instance="RTC"/>
+          <generator name="RTC_PER1" index="7" module-instance="RTC"/>
+          <generator name="RTC_PER2" index="8" module-instance="RTC"/>
+          <generator name="RTC_PER3" index="9" module-instance="RTC"/>
+          <generator name="RTC_PER4" index="10" module-instance="RTC"/>
+          <generator name="RTC_PER5" index="11" module-instance="RTC"/>
+          <generator name="RTC_PER6" index="12" module-instance="RTC"/>
+          <generator name="RTC_PER7" index="13" module-instance="RTC"/>
+          <generator name="RTC_CMP0" index="14" module-instance="RTC"/>
+          <generator name="RTC_CMP1" index="15" module-instance="RTC"/>
+          <generator name="RTC_CMP2" index="16" module-instance="RTC"/>
+          <generator name="RTC_CMP3" index="17" module-instance="RTC"/>
+          <generator name="RTC_TAMPER" index="18" module-instance="RTC"/>
+          <generator name="RTC_OVF" index="19" module-instance="RTC"/>
+          <generator name="RTC_PERD" index="20" module-instance="RTC"/>
+          <generator name="EIC_EXTINT0" index="21" module-instance="EIC"/>
+          <generator name="EIC_EXTINT1" index="22" module-instance="EIC"/>
+          <generator name="EIC_EXTINT2" index="23" module-instance="EIC"/>
+          <generator name="EIC_EXTINT3" index="24" module-instance="EIC"/>
+          <generator name="EIC_EXTINT4" index="25" module-instance="EIC"/>
+          <generator name="EIC_EXTINT5" index="26" module-instance="EIC"/>
+          <generator name="EIC_EXTINT6" index="27" module-instance="EIC"/>
+          <generator name="EIC_EXTINT7" index="28" module-instance="EIC"/>
+          <generator name="EIC_EXTINT8" index="29" module-instance="EIC"/>
+          <generator name="EIC_EXTINT9" index="30" module-instance="EIC"/>
+          <generator name="EIC_EXTINT10" index="31" module-instance="EIC"/>
+          <generator name="EIC_EXTINT11" index="32" module-instance="EIC"/>
+          <generator name="EIC_EXTINT12" index="33" module-instance="EIC"/>
+          <generator name="EIC_EXTINT13" index="34" module-instance="EIC"/>
+          <generator name="EIC_EXTINT14" index="35" module-instance="EIC"/>
+          <generator name="EIC_EXTINT15" index="36" module-instance="EIC"/>
+          <generator name="DMAC_CH0" index="37" module-instance="DMAC"/>
+          <generator name="DMAC_CH1" index="38" module-instance="DMAC"/>
+          <generator name="DMAC_CH2" index="39" module-instance="DMAC"/>
+          <generator name="DMAC_CH3" index="40" module-instance="DMAC"/>
+          <generator name="TCC0_OVF" index="41" module-instance="TCC0"/>
+          <generator name="TCC0_TRG" index="42" module-instance="TCC0"/>
+          <generator name="TCC0_CNT" index="43" module-instance="TCC0"/>
+          <generator name="TCC0_MC0" index="44" module-instance="TCC0"/>
+          <generator name="TCC0_MC1" index="45" module-instance="TCC0"/>
+          <generator name="TCC1_OVF" index="46" module-instance="TCC1"/>
+          <generator name="TCC1_TRG" index="47" module-instance="TCC1"/>
+          <generator name="TCC1_CNT" index="48" module-instance="TCC1"/>
+          <generator name="TCC1_MC0" index="49" module-instance="TCC1"/>
+          <generator name="TCC1_MC1" index="50" module-instance="TCC1"/>
+          <generator name="TCC2_OVF" index="51" module-instance="TCC2"/>
+          <generator name="TCC2_TRG" index="52" module-instance="TCC2"/>
+          <generator name="TCC2_CNT" index="53" module-instance="TCC2"/>
+          <generator name="TCC2_MC0" index="54" module-instance="TCC2"/>
+          <generator name="TCC2_MC1" index="55" module-instance="TCC2"/>
+          <generator name="TCC3_OVF" index="56" module-instance="TCC3"/>
+          <generator name="TCC3_TRG" index="57" module-instance="TCC3"/>
+          <generator name="TCC3_CNT" index="58" module-instance="TCC3"/>
+          <generator name="TCC3_MC0" index="59" module-instance="TCC3"/>
+          <generator name="TCC3_MC1" index="60" module-instance="TCC3"/>
+          <generator name="TCC4_OVF" index="61" module-instance="TCC4"/>
+          <generator name="TCC4_TRG" index="62" module-instance="TCC4"/>
+          <generator name="TCC4_CNT" index="63" module-instance="TCC4"/>
+          <generator name="TCC4_MC0" index="64" module-instance="TCC4"/>
+          <generator name="TCC4_MC1" index="65" module-instance="TCC4"/>
+          <generator name="TCC5_OVF" index="66" module-instance="TCC5"/>
+          <generator name="TCC5_TRG" index="67" module-instance="TCC5"/>
+          <generator name="TCC5_CNT" index="68" module-instance="TCC5"/>
+          <generator name="TCC5_MC0" index="69" module-instance="TCC5"/>
+          <generator name="TCC5_MC1" index="70" module-instance="TCC5"/>
+          <generator name="TCC6_OVF" index="71" module-instance="TCC6"/>
+          <generator name="TCC6_TRG" index="72" module-instance="TCC6"/>
+          <generator name="TCC6_CNT" index="73" module-instance="TCC6"/>
+          <generator name="TCC6_MC0" index="74" module-instance="TCC6"/>
+          <generator name="TCC6_MC1" index="75" module-instance="TCC6"/>
+          <generator name="ADC_CHRDY" index="76" module-instance="ADC"/>
+          <generator name="ADC_CMP" index="77" module-instance="ADC"/>
+          <generator name="AC_COMP0" index="78" module-instance="AC"/>
+          <generator name="AC_COMP1" index="79" module-instance="AC"/>
+          <generator name="AC_WIN0" index="80" module-instance="AC"/>
+          <generator name="PTC_EOC" index="81" module-instance="PTC"/>
+          <generator name="PTC_WCOMP" index="82" module-instance="PTC"/>
+          <generator name="CCL0_LUTOUT0" index="83" module-instance="CCL0"/>
+          <generator name="CCL0_LUTOUT1" index="84" module-instance="CCL0"/>
+          <generator name="CCL0_LUTOUT2" index="85" module-instance="CCL0"/>
+          <generator name="CCL0_LUTOUT3" index="86" module-instance="CCL0"/>
+          <generator name="CCL1_LUTOUT0" index="87" module-instance="CCL1"/>
+          <generator name="CCL1_LUTOUT1" index="88" module-instance="CCL1"/>
+          <generator name="CCL1_LUTOUT2" index="89" module-instance="CCL1"/>
+          <generator name="CCL1_LUTOUT3" index="90" module-instance="CCL1"/>
+        </generators>
+        <users>
+          <user name="FREQM_START" index="0" module-instance="FREQM"/>
+          <user name="RTC_TAMPER" index="1" module-instance="RTC"/>
+          <user name="PORT_EV0" index="2" module-instance="PORT"/>
+          <user name="PORT_EV1" index="3" module-instance="PORT"/>
+          <user name="PORT_EV2" index="4" module-instance="PORT"/>
+          <user name="PORT_EV3" index="5" module-instance="PORT"/>
+          <user name="DMAC_CH0" index="6" module-instance="DMAC"/>
+          <user name="DMAC_CH1" index="7" module-instance="DMAC"/>
+          <user name="DMAC_CH2" index="8" module-instance="DMAC"/>
+          <user name="DMAC_CH3" index="9" module-instance="DMAC"/>
+          <user name="TCC0_EV0" index="10" module-instance="TCC0"/>
+          <user name="TCC0_EV1" index="11" module-instance="TCC0"/>
+          <user name="TCC0_MC0" index="12" module-instance="TCC0"/>
+          <user name="TCC0_MC1" index="13" module-instance="TCC0"/>
+          <user name="TCC1_EV0" index="14" module-instance="TCC1"/>
+          <user name="TCC1_EV1" index="15" module-instance="TCC1"/>
+          <user name="TCC1_MC0" index="16" module-instance="TCC1"/>
+          <user name="TCC1_MC1" index="17" module-instance="TCC1"/>
+          <user name="TCC2_EV0" index="18" module-instance="TCC2"/>
+          <user name="TCC2_EV1" index="19" module-instance="TCC2"/>
+          <user name="TCC2_MC0" index="20" module-instance="TCC2"/>
+          <user name="TCC2_MC1" index="21" module-instance="TCC2"/>
+          <user name="TCC3_EV0" index="22" module-instance="TCC3"/>
+          <user name="TCC3_EV1" index="23" module-instance="TCC3"/>
+          <user name="TCC3_MC0" index="24" module-instance="TCC3"/>
+          <user name="TCC3_MC1" index="25" module-instance="TCC3"/>
+          <user name="TCC4_EV0" index="26" module-instance="TCC4"/>
+          <user name="TCC4_EV1" index="27" module-instance="TCC4"/>
+          <user name="TCC4_MC0" index="28" module-instance="TCC4"/>
+          <user name="TCC4_MC1" index="29" module-instance="TCC4"/>
+          <user name="TCC5_EV0" index="30" module-instance="TCC5"/>
+          <user name="TCC5_EV1" index="31" module-instance="TCC5"/>
+          <user name="TCC5_MC0" index="32" module-instance="TCC5"/>
+          <user name="TCC5_MC1" index="33" module-instance="TCC5"/>
+          <user name="TCC6_EV0" index="34" module-instance="TCC6"/>
+          <user name="TCC6_EV1" index="35" module-instance="TCC6"/>
+          <user name="TCC6_MC0" index="36" module-instance="TCC6"/>
+          <user name="TCC6_MC1" index="37" module-instance="TCC6"/>
+          <user name="ADC_TRIG0" index="38" module-instance="ADC"/>
+          <user name="ADC_TRIG1" index="39" module-instance="ADC"/>
+          <user name="ADC_TRIG2" index="40" module-instance="ADC"/>
+          <user name="ADC_TRIG3" index="41" module-instance="ADC"/>
+          <user name="ADC_TRIG4" index="42" module-instance="ADC"/>
+          <user name="ADC_TRIG5" index="43" module-instance="ADC"/>
+          <user name="ADC_TRIG6" index="44" module-instance="ADC"/>
+          <user name="ADC_TRIG7" index="45" module-instance="ADC"/>
+          <user name="ADC_TRIG8" index="46" module-instance="ADC"/>
+          <user name="ADC_TRIG9" index="47" module-instance="ADC"/>
+          <user name="ADC_TRIG10" index="48" module-instance="ADC"/>
+          <user name="AC_SOC0" index="49" module-instance="AC"/>
+          <user name="AC_SOC1" index="50" module-instance="AC"/>
+          <user name="PTC_DSEQR" index="51" module-instance="PTC"/>
+          <user name="PTC_STCONV" index="52" module-instance="PTC"/>
+          <user name="CCL0_LUTIN0" index="53" module-instance="CCL0"/>
+          <user name="CCL0_LUTIN1" index="54" module-instance="CCL0"/>
+          <user name="CCL0_LUTIN2" index="55" module-instance="CCL0"/>
+          <user name="CCL0_LUTIN3" index="56" module-instance="CCL0"/>
+          <user name="CCL1_LUTIN0" index="57" module-instance="CCL1"/>
+          <user name="CCL1_LUTIN1" index="58" module-instance="CCL1"/>
+          <user name="CCL1_LUTIN2" index="59" module-instance="CCL1"/>
+          <user name="CCL1_LUTIN3" index="60" module-instance="CCL1"/>
+          <user name="AT_TAMPSRC5" index="61" module-instance="AT"/>
+        </users>
+      </events>
+      <interfaces>
+        <interface name="JTAG" type="samjtag"/>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x0AC01053"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="03784" name2="cmp_ac_u2501_v2" version="2a0" caption="Analog Comparator Controller">
+      <register-group name="CHANNEL" size="0x10">
+        <register name="COMPCTRL" offset="0x0" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Pair n Comparator Control 0">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x8"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x30" values="COMPCTRL__INTSEL"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x7000" values="COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x10000"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0x20000" values="COMPCTRL__SPEED"/>
+          <bitfield name="HYST" caption="Hysteresis Level" mask="0x180000" values="COMPCTRL__HYST"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0xE00000" values="COMPCTRL__FLEN"/>
+          <bitfield name="OUT" caption="Output" mask="0x3000000" values="COMPCTRL__OUT"/>
+          <bitfield name="SUT" caption="Start-up Time" mask="0xFC000000"/>
+        </register>
+        <register name="DACCTRL" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Dac n Control">
+          <bitfield name="VALUE0" caption="DAC0 Output Value" mask="0x7F"/>
+          <bitfield name="SHEN0" caption="DAC0 Sample and Hold Enable Operating Mode" mask="0x8000"/>
+          <bitfield name="VALUE1" caption="DAC1 Output Value" mask="0x7F0000"/>
+          <bitfield name="SHEN1" caption="DAC1 Sample and Hold Enable Operating Mode" mask="0x80000000"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Window Monitor  n Control">
+          <bitfield name="WEN" caption="Window n Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL" caption="Window n Interrupt Selection" mask="0x6" values="WINCTRL__WINTSEL"/>
+        </register>
+      </register-group>
+      <register-group name="AC" caption="Analog Comparator Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Control C">
+          <bitfield name="WIDTH" caption="Sample and Hold Clock Pulse Width" mask="0x3FF"/>
+          <bitfield name="PER" caption="Sample and Hold Clock Period" mask="0x3FF000"/>
+          <bitfield name="PRESCALER" caption="Prescaling Factor" mask="0x7000000" values="CTRLC__PRESCALER"/>
+          <bitfield name="AIPMPEN" caption="Analog Input Charge Pump Enable" mask="0x8000000"/>
+          <bitfield name="CONFIG" caption="Configuration Extension" mask="0xF0000000"/>
+        </register>
+        <register name="EVCTRL" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="INVEI0" caption="Inverted Event Input Enable 0" mask="0x1000000"/>
+          <bitfield name="INVEI1" caption="Inverted Event Input Enable 1" mask="0x2000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x100"/>
+        </register>
+        <register name="STATUSA" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30000" values="STATUSA__WSTATE"/>
+        </register>
+        <register name="STATUSB" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="COMPCTRL0" caption="COMPCTRL 0 Synchronization Busy" mask="0x4"/>
+          <bitfield name="COMPCTRL1" caption="COMPCTRL 1 Synchronization Busy" mask="0x8"/>
+          <bitfield name="WINCTRL0" caption="WINCTRL 0 Synchronization Busy" mask="0x400"/>
+        </register>
+        <register-group name="CHANNEL" name-in-module="CHANNEL" offset="0x30" size="0x10" count="1"/>
+      </register-group>
+      <value-group name="COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="INT0" caption="Internal connection 0, device specific" value="4"/>
+        <value name="BANDGAP" caption="Bangap" value="5"/>
+        <value name="GND" caption="Ground" value="6"/>
+        <value name="INTDAC" caption="Internal DAC" value="7"/>
+      </value-group>
+      <value-group name="COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="INT0" caption="Internal connection 0, device specific" value="4"/>
+        <value name="INT1" caption="Internal connection 1, device specific" value="5"/>
+        <value name="INT2" caption="Internal connection 2, device specific" value="6"/>
+        <value name="INTDAC" caption="Internal DAC" value="7"/>
+      </value-group>
+      <value-group name="COMPCTRL__SPEED">
+        <value name="HIGH" caption="High speed, high power" value="0"/>
+        <value name="LOW" caption="Low speed, low power" value="1"/>
+      </value-group>
+      <value-group name="COMPCTRL__HYST">
+        <value name="HYST10" caption="10mV" value="0"/>
+        <value name="HYST20" caption="20mV" value="1"/>
+        <value name="HYST40" caption="40mV" value="2"/>
+        <value name="HYST60" caption="60mV" value="3"/>
+      </value-group>
+      <value-group name="COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="WINCTRL__WINTSEL">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="CTRLC__PRESCALER">
+        <value name="DIV1" caption="Sampling rate is GCLK_AC (No division)" value="0x0"/>
+        <value name="DIV2" caption="Sampling rate is GCLK_AC/2" value="0x1"/>
+        <value name="DIV4" caption="Sampling rate is GCLK_AC/4" value="0x2"/>
+        <value name="DIV8" caption="Sampling rate is GCLK_AC/8" value="0x3"/>
+        <value name="DIV16" caption="Sampling rate is GCLK_AC/16" value="0x4"/>
+        <value name="DIV32" caption="Sampling rate is GCLK_AC/32" value="0x5"/>
+        <value name="DIV64" caption="Sampling rate is GCLK_AC/64" value="0x6"/>
+        <value name="DIV128" caption="Sampling rate is GCLK_AC/128" value="0x7"/>
+      </value-group>
+      <value-group name="STATUSA__WSTATE">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="03620" name2="adc_msh_ctrl_apb_v1" version="1b0" caption="ADC Controller">
+      <register-group name="CONFIG" size="0x20">
+        <register name="CORCTRL" offset="0x0" rw="RW" size="4" initval="0x00000C00" caption="SARCORE Control">
+          <bitfield name="SAMC" caption="Sample Count" mask="0x3FF"/>
+          <bitfield name="SELRES" caption="Selects Resolution" mask="0xC00" values="CORCTRL__SELRES"/>
+          <bitfield name="EIS" caption="Early Interrupt Select" mask="0x7000"/>
+          <bitfield name="EIRQOVR" caption="Interrupt Type Select" mask="0x8000"/>
+          <bitfield name="STRGSRC" caption="SCAN trigger source selection" mask="0xF0000" values="CORCTRL__STRGSRC"/>
+          <bitfield name="STRGLVL" caption="Scan Trigger Level Sensitivity" mask="0x200000"/>
+          <bitfield name="SCNRTDS" caption="SCAN Re-trigger Disable" mask="0x400000"/>
+          <bitfield name="ADCDIV" caption="Division Ratio for SARCORE clock" mask="0x7F000000"/>
+        </register>
+        <register name="CHNCFG1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 1 (LVL/CMPEN)">
+          <bitfield name="CHNCMPEN" caption="Channel Comparator Enable" mask="0xFFFF"/>
+          <bitfield name="LVL" caption="Channel Level" mask="0xFFFF0000"/>
+        </register>
+        <register name="CHNCFG2" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 2(FRACT/CSS)">
+          <bitfield name="CSS" caption="Channel SCAN Select" mask="0xFFFF"/>
+          <bitfield name="FRACT" caption="Channel Fractional" mask="0xFFFF0000"/>
+        </register>
+        <register name="CHNCFG3" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration3 (SIGN/DIFF)">
+          <bitfield name="DIFF" caption="Differential Mode" mask="0xFFFF"/>
+          <bitfield name="SIGN" caption="SIGN setting" mask="0xFFFF0000"/>
+        </register>
+        <register name="CHNCFG4" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 4 (TRGSRC)">
+          <bitfield name="TRGSRC0" caption="Channel 0 Trigger Source" mask="0xF" values="CHNCFG4__TRGSRC0"/>
+          <bitfield name="TRGSRC1" caption="Channel 1 Trigger Source" mask="0xF0" values="CHNCFG4__TRGSRC1"/>
+          <bitfield name="TRGSRC2" caption="Channel 2 Trigger Source" mask="0xF00" values="CHNCFG4__TRGSRC2"/>
+          <bitfield name="TRGSRC3" caption="Channel 3 Trigger Source" mask="0xF000" values="CHNCFG4__TRGSRC3"/>
+          <bitfield name="TRGSRC4" caption="Channel 4 Trigger Source" mask="0xF0000" values="CHNCFG4__TRGSRC4"/>
+          <bitfield name="TRGSRC5" caption="Channel 5 Trigger Source" mask="0xF00000" values="CHNCFG4__TRGSRC5"/>
+          <bitfield name="TRGSRC6" caption="Channel 6 Trigger Source" mask="0xF000000" values="CHNCFG4__TRGSRC6"/>
+          <bitfield name="TRGSRC7" caption="Channel 7 Trigger Source" mask="0xF0000000" values="CHNCFG4__TRGSRC7"/>
+        </register>
+        <register name="CHNCFG5" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 5 (TRGSRC)">
+          <bitfield name="TRGSRC8" caption="Channel 8 Trigger Source" mask="0xF" values="CHNCFG5__TRGSRC8"/>
+          <bitfield name="TRGSRC9" caption="Channel 9 Trigger Source" mask="0xF0" values="CHNCFG5__TRGSRC9"/>
+          <bitfield name="TRGSRC10" caption="Channel 10 Trigger Source" mask="0xF00" values="CHNCFG5__TRGSRC10"/>
+          <bitfield name="TRGSRC11" caption="Channel 11 Trigger Source" mask="0xF000" values="CHNCFG5__TRGSRC11"/>
+          <bitfield name="TRGSRC12" caption="Channel 12 Trigger Source" mask="0xF0000" values="CHNCFG5__TRGSRC12"/>
+          <bitfield name="TRGSRC13" caption="Channel 13 Trigger Source" mask="0xF00000" values="CHNCFG5__TRGSRC13"/>
+          <bitfield name="TRGSRC14" caption="Channel 14 Trigger Source" mask="0xF000000" values="CHNCFG5__TRGSRC14"/>
+          <bitfield name="TRGSRC15" caption="Channel 15 Trigger Source" mask="0xF0000000" values="CHNCFG5__TRGSRC15"/>
+        </register>
+        <register name="CALCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="SARCORE Calibration Value">
+          <mode name="DEFAULT"/>
+          <mode name="FUSES_ADC_SARCORE_12BIT_V7A0"/>
+          <mode name="FUSES_ADC_SARCORE_12BIT_V7C0"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_cmbf" caption="Enable Common Mode Buffer" mask="0x1"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_dither" caption="Enable Dither" mask="0x4"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dis_faz" caption="Disable auto-zeroing" mask="0x8"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dis_saz" caption="Disable auto-zeroing" mask="0x10"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dis_laz" caption="Disable auto-zeroing" mask="0x20"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_rdac" caption="Disable Power Cycling" mask="0x40"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dbg_sel" caption="Debug Bus Select" mask="0x80"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="sel_del" caption="Scan Mode comp_out" mask="0x100"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="t1_dly" caption="Regen Latch Delay" mask="0x600"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="tclk_div" caption="Test Clock Divider" mask="0xF800"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="iadc_1" caption="Current Consumption 1" mask="0x300000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="iadc_2" caption="Current Consumption 2" mask="0xC00000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="icmp_1" caption="Bias Current Stage 1" mask="0x3000000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="icmp_2" caption="Bias Current Stage 2" mask="0xC000000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="icmbf" caption="Bias Current Common Mode Buffer" mask="0x30000000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_ext_bias" caption="Dsiable Internal Bias Circuit" mask="0x80000000"/>
+          <bitfield modes="DEFAULT" name="CALBITS" caption="Calibration Values" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="EVCTRL" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Event conversion input enable" mask="0x1"/>
+          <bitfield name="STARTINV" caption="Start Conversion Invert" mask="0x8"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="CMPEO" caption="Comparator Window Event Out" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group name="INT" size="0x10">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="CMPHIT" caption="Compare Hit Disable" mask="0x10"/>
+          <bitfield name="SOVFL" caption="Synchonizer Overflow Disable" mask="0x80"/>
+          <bitfield name="CHRDYC" caption="Core Current Channel Disable" mask="0x100"/>
+          <bitfield name="FLTRDY" caption="Filter Ready Disable" mask="0x200"/>
+          <bitfield name="CHNERRC" caption="Channel Overwrite Error Disable" mask="0x400"/>
+          <bitfield name="EOSRDY" caption="Endo of Scan Disable" mask="0x800"/>
+          <bitfield name="CHRDY" caption="Channel Ready Disable" mask="0xFFFF0000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="CMPHIT" caption="Compare Hit Enable" mask="0x10"/>
+          <bitfield name="SOVFL" caption="Synchronizer Overflow Enable" mask="0x80"/>
+          <bitfield name="CHRDYC" caption="Current Channel Ready Enable" mask="0x100"/>
+          <bitfield name="FLTRDY" caption="Filter Ready Enable" mask="0x200"/>
+          <bitfield name="CHNERRC" caption="Channel Overwrite Enable" mask="0x400"/>
+          <bitfield name="EOSRDY" caption="End of Scan Enable" mask="0x800"/>
+          <bitfield name="CHRDY" caption="Channel Ready Enable" mask="0xFFFF0000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flags">
+          <bitfield name="CMPINTID" caption="Compare Channel ID" mask="0xF"/>
+          <bitfield name="CMPHIT" caption="Compare Hit" mask="0x10"/>
+          <bitfield name="SOVFL" caption="Synchronizer Overflow" mask="0x80"/>
+          <bitfield name="CHRDYC" caption="Current Channel Ready" mask="0x100"/>
+          <bitfield name="FLTRDY" caption="Filter Ready" mask="0x200"/>
+          <bitfield name="CHNERRC" caption="Channel Overwrite Error" mask="0x400"/>
+          <bitfield name="EOSRDY" caption="End of Scan Ready" mask="0x800"/>
+          <bitfield name="CRDYID" caption="Channel Ready ID" mask="0xF000"/>
+          <bitfield name="CHRDY" caption="Channel Ready" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+      <register-group name="ADC" caption="ADC Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000080" caption="CONTROL A REGISTER">
+          <bitfield name="SWRST" caption="SOFTWARE RESET BIT" mask="0x1"/>
+          <bitfield name="ENABLE" caption="ENABLE BIT" mask="0x2"/>
+          <bitfield name="ANAEN" caption="Analog Enable" mask="0x4"/>
+          <bitfield name="AIPMPEN" caption="Charge Pump Enable" mask="0x10"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL B REGISTER">
+          <bitfield name="ADCHSEL" caption="Software Trigger Channel Select" mask="0xF"/>
+          <bitfield name="ADCORSEL" caption="Software Trigger Core Select" mask="0x30"/>
+          <bitfield name="RQCNVRT" caption="Request Channel Convert" mask="0x40"/>
+          <bitfield name="SAMP" caption="Channel Sample" mask="0x80"/>
+          <bitfield name="GSWTRG" caption="Global Software Trigger" mask="0x100"/>
+          <bitfield name="LSWTRG" caption="Level Global Trigger" mask="0x200"/>
+          <bitfield name="TRGSUSP" caption="Trigger Suspend" mask="0x400"/>
+          <bitfield name="STRGEN" caption="Synchronous Trigger Enable" mask="0x800"/>
+          <bitfield name="SWCNVEN" caption="Software Conversion Enable" mask="0x8000"/>
+        </register>
+        <register name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Control C Register">
+          <bitfield name="CNT" caption="Clock Divider for Synchronous Trigger" mask="0xFFFF"/>
+          <bitfield name="COREINTERLEAVED" caption="Number of Core to Interleave Triggers" mask="0x70000000"/>
+        </register>
+        <register name="CTRLD" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Control D Register">
+          <bitfield name="CTLCKDIV" caption="Control Clock Divider" mask="0x3F00"/>
+          <bitfield name="CHNEN0" caption="Core 0 Digital Channel Enable" mask="0x10000"/>
+          <bitfield name="ANLEN0" caption="Analog and Bias circuitry Enable for core 0" mask="0x100000"/>
+          <bitfield name="WKUPEXP" caption="Wakeup cycles" mask="0xF000000"/>
+          <bitfield name="VREFSEL" caption="Voltage Reference Select" mask="0x70000000" values="CTRLD__VREFSEL"/>
+        </register>
+        <register-group name="CONFIG" name-in-module="CONFIG" offset="0x020" size="0x20" count="1"/>
+        <register name="CMPCTRL" offset="0xB0" rw="RW" size="4" initval="0x00000000" caption="Comparator Control">
+          <bitfield name="ADCMPLO" caption="Low Limit of Digital Comparator" mask="0xFFF"/>
+          <bitfield name="CMPEN" caption="Comparator Enable" mask="0x1000"/>
+          <bitfield name="IELOLO" caption="Enable VAL &lt; CMPLO" mask="0x2000"/>
+          <bitfield name="IELOHI" caption="Enable VAL &gt;= CMPLO" mask="0x4000"/>
+          <bitfield name="IEBTWN" caption="Enable CMPLO &lt;= VAL &lt; CMPHI" mask="0x8000"/>
+          <bitfield name="ADCMPHI" caption="High Limit of Digital Comparator" mask="0xFFF0000"/>
+          <bitfield name="IEHILO" caption="Enable VAL &lt; CMPHI" mask="0x10000000"/>
+          <bitfield name="IEHIHI" caption="Enable VAL &gt;= CMPHI" mask="0x20000000"/>
+        </register>
+        <register name="FLTCTRL" offset="0xC0" rw="RW" size="4" initval="0x00000000" caption="Filter Control">
+          <bitfield name="OVRSAM" caption="Oversampling Ratio" mask="0x7" values="FLTCTRL__OVRSAM"/>
+          <bitfield name="FMODE" caption="Filter Mode" mask="0x8"/>
+          <bitfield name="DATA16EN" caption="16bit Averaging Mode" mask="0x10"/>
+          <bitfield name="FLTEN" caption="Filter Enable" mask="0x100"/>
+          <bitfield name="FLTCHNID" caption="Channel ID" mask="0x3C00"/>
+        </register>
+        <register name="CORCHDATAID" offset="0xD0" rw="RW" size="4" initval="0x00000000" caption="Channel Ready DATA ID">
+          <bitfield name="CHRDYID" caption="Channel Read ID" mask="0xF"/>
+          <bitfield name="CORDYID" caption="Core Read ID" mask="0x30"/>
+        </register>
+        <register name="CHRDYDAT" offset="0xD4" rw="RW" size="4" initval="0x00000000" caption="Channel Ready Data Register">
+          <bitfield name="CHRDYDAT" caption="Channel Output Data" mask="0xFFFF"/>
+          <bitfield name="LVL" caption="Level Setting" mask="0x1000000"/>
+          <bitfield name="DIFF" caption="Differential Setting" mask="0x2000000"/>
+          <bitfield name="SIGN" caption="Sign Setting" mask="0x4000000"/>
+          <bitfield name="FRACT" caption="Fractional Setting" mask="0x8000000"/>
+        </register>
+        <register name="PFFDATA" offset="0xD8" rw="R" size="4" initval="0x00000000" caption="APB FIFO Output Data">
+          <bitfield name="PFFDATA" caption="SARCORE Conversion data from the APB FIFO" mask="0xFFFF"/>
+          <bitfield name="PFFCHNID" caption="Channel ID from APB FIFO" mask="0xF0000"/>
+          <bitfield name="PFFCORID" caption="Core ID from APB FIFO" mask="0x300000"/>
+          <bitfield name="PFFSIGN" caption="Channel Sign from the APB FIFO" mask="0x400000"/>
+          <bitfield name="PFFFRACT" caption="Fractional Setting from APB FIFO" mask="0x800000"/>
+          <bitfield name="PFFCNT" caption="Current Data Entries in APB FIFO" mask="0xFF000000"/>
+        </register>
+        <register name="DMABASE" offset="0xDC" rw="RW" size="4" initval="0x00000000" caption="DMA Sample Base Address">
+          <bitfield name="DMABASE" caption="DMA Sample Value Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DMACTRL" offset="0xE0" rw="RW" size="4" initval="0x00000000" caption="DMA Control Register">
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="DMACR0" caption="DMA CORE0 Enable" mask="0x10"/>
+          <bitfield name="DMABL" caption="DMA System RAM Buffer Length" mask="0x700"/>
+        </register>
+        <register name="PFFCTRL" offset="0xE4" rw="RW" size="4" initval="0x00000000" caption="APB FIFO Control Register">
+          <bitfield name="PFFEN" caption="APB FIFO Enable" mask="0x2"/>
+          <bitfield name="PFFCR0" caption="APB CORE 0 FIFO Enable" mask="0x10"/>
+          <bitfield name="PFFRDYDM" caption="DMA APB FIFO Data Ready" mask="0x10000" values="PFFCTRL__PFFRDYDM"/>
+        </register>
+        <register name="SYNCBUSY" offset="0xE8" rw="R" size="4" initval="0x00000000" caption="CORE SYNC Busy Status Register">
+          <bitfield name="SWRST" caption="Software Reset Sync Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable bit Sync Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB sync busy" mask="0x4"/>
+        </register>
+        <register name="DMAINTENCLR" offset="0xF0" rw="RW" size="4" atomic-op="clear:DMAINTENCLR" initval="0x00000000" caption="DMA Interrupt Enable Clear">
+          <bitfield name="RAF" caption="Ram Buffer A Full" mask="0xF"/>
+          <bitfield name="RBF" caption="Ram Buffer B Full" mask="0xF0"/>
+          <bitfield name="SOVFL" caption="Synchonizer Overflow" mask="0x10000"/>
+        </register>
+        <register name="DMAINTSET" offset="0xF4" rw="RW" size="4" atomic-op="set:DMAINTSET" initval="0x00000000" caption="DMA Interrupt Enable Set">
+          <bitfield name="RAF" caption="Ram Buffer A Full" mask="0xF"/>
+          <bitfield name="RBF" caption="Ram Buffer B Full" mask="0xF0"/>
+          <bitfield name="SOVFL" caption="Synchonizer Overflow" mask="0x10000"/>
+        </register>
+        <register name="DMAINTFLAG" offset="0xF8" rw="RW" size="4" atomic-op="clear:DMAINTFLAG" initval="0x00000000" caption="DMA Interrupt Flag and Status">
+          <bitfield name="RAF" caption="Ram Buffer A Full" mask="0xF"/>
+          <bitfield name="RBF" caption="Ram Buffer B Full" mask="0xF0"/>
+          <bitfield name="EAF" caption="Ram Buffer A Overflow Error" mask="0xF00"/>
+          <bitfield name="EBF" caption="Ram Buffer B Overflow Error" mask="0xF000"/>
+          <bitfield name="SOVFL" caption="Synchronizer overflow" mask="0x10000"/>
+          <bitfield name="DMAERR" caption="DMA Bus Error" mask="0x20000"/>
+        </register>
+        <register name="CTLINTENSET" offset="0xFC" rw="RW" size="4" atomic-op="set:CTLINTENSET" initval="0x00000000" caption="CORE Controller Interrupt Enable Set">
+          <bitfield name="CRRDY0" caption="Core 0 Ready" mask="0x1"/>
+          <bitfield name="VREFUPD" caption="VREF update" mask="0x40"/>
+          <bitfield name="VREFRDY" caption="VREF Ready" mask="0x80"/>
+          <bitfield name="PFFUNF" caption="APB FIFO Underflow" mask="0x100"/>
+          <bitfield name="PFFOVF" caption="APB FIFO Overflow" mask="0x200"/>
+          <bitfield name="PFFRDY" caption="APB FIFO Ready" mask="0x400"/>
+          <bitfield name="PFFHFUL" caption="APB FIFO Half Full" mask="0x800"/>
+        </register>
+        <register name="CTLINTENCLR" offset="0x100" rw="RW" size="4" atomic-op="clear:CTLINTENCLR" initval="0x00000000" caption="CORE Controller Interrupt Enable Clear">
+          <bitfield name="CRRDY0" caption="Core Ready 0 Disable" mask="0x1"/>
+          <bitfield name="VREFUPD" caption="VREF Update" mask="0x40"/>
+          <bitfield name="VREFRDY" caption="VREF Ready" mask="0x80"/>
+          <bitfield name="PFFUNF" caption="APB FIFO underflow" mask="0x100"/>
+          <bitfield name="PFFOVF" caption="APB FIFO overflow" mask="0x200"/>
+          <bitfield name="PFFRDY" caption="APB FIFO Ready" mask="0x400"/>
+          <bitfield name="PFFHFUL" caption="APB FIFO Half Full" mask="0x800"/>
+        </register>
+        <register name="CTLINTFLAG" offset="0x104" rw="RW" size="4" atomic-op="clear:CTLINTFLAG" initval="0x00000000" caption="CORE Controller Interrupt Flags">
+          <bitfield name="CRRDY" caption="Core Ready" mask="0xF"/>
+          <bitfield name="VREFUPD" caption="VREF update" mask="0x40"/>
+          <bitfield name="VREFRDY" caption="VREF Ready" mask="0x80"/>
+          <bitfield name="PFFUNF" caption="APB FIFO underflow" mask="0x100"/>
+          <bitfield name="PFFOVF" caption="APB FIFO overflow" mask="0x200"/>
+          <bitfield name="PFFRDY" caption="APB FIFO Ready" mask="0x400"/>
+          <bitfield name="PFFHFUL" caption="APB FIFO Half Full" mask="0x800"/>
+        </register>
+        <register-group name="INT" name-in-module="INT" offset="0x120" size="0x10" count="1"/>
+        <register name="DBGCTRL" offset="0x168" rw="RW" size="4" initval="0x00000000" caption="Debug Control Register">
+          <bitfield name="DBGRUN" caption="Debug Running State" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="CORCTRL__SELRES">
+        <value name="6_BITS" caption="6 bits" value="0"/>
+        <value name="8_BITS" caption="8 bits" value="1"/>
+        <value name="10_BITS" caption="10 bits" value="2"/>
+        <value name="12_BITS" caption="12 bits (power-on default)" value="3"/>
+      </value-group>
+      <value-group name="CORCTRL__STRGSRC">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC0">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC1">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC2">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC3">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC4">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC5">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC6">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC7">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC8">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC9">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC10">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC11">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC12">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC13">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC14">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC15">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CTRLD__VREFSEL">
+        <value name="AVDD_AVSS" caption="AVDD and AVSS" value="0"/>
+        <value name="EXTERNAL_VREFH_AVSS" caption="External VREFH and AVSS" value="1"/>
+      </value-group>
+      <value-group name="FLTCTRL__OVRSAM">
+        <value name="4_SAMPLES" caption="(If FMODE is 0) 4 samples (shift sum 1 bit to right, output data is 13-bits) / (If FMODE is 1) 2 samples to be averaged" value="0"/>
+        <value name="16_SAMPLES" caption="(If FMODE is 0) 16 samples (shift sum 2 bits to right, output data is 14-bits) / (If FMODE is 1) 4 samples to be averaged" value="1"/>
+        <value name="64_SAMPLES" caption="(If FMODE is 0) 64 samples (shift sum 3 bits to right, output data is 15-bits) / (If FMODE is 1) 8 samples to be averaged" value="2"/>
+        <value name="256_SAMPLES" caption="(If FMODE is 0) 256 samples (shift sum 4 bits to right, output data is 16-bits) / (If FMODE is 1) 16 samples to be averaged" value="3"/>
+        <value name="2_SAMPLES" caption="(If FMODE is 0) 2 samples (shift sum 0 bits to right, output data is 12.1 format) / (If FMODE is 1) 32 samples to be averaged" value="4"/>
+        <value name="8_SAMPLES" caption="(If FMODE is 0) 8 samples (shift sum 1 bit to right, output data is 13.1 format) / (If FMODE is 1) 64 samples to be averaged" value="5"/>
+        <value name="32_SAMPLES" caption="(If FMODE is 0) 32 samples (shift sum 2 bits to right, output data is 14.1 format) / (If FMODE is 1) 128 samples to be averaged" value="6"/>
+        <value name="128_SAMPLES" caption="(If FMODE is 0) 128 samples (shift sum 3 bits to right, output data is 15.1 format) / (If FMODE is 1) 256 samples to be averaged" value="7"/>
+      </value-group>
+      <value-group name="PFFCTRL__PFFRDYDM">
+        <value name="CTLINTFLAG_PFFHFUL" caption="Selects CTLINTFLAG.PFFHFUL for the ADC DMA PFFRDY trigger signal to the DMAC" value="0"/>
+        <value name="CTLINTFLAG_PFFRDY" caption="Selects CTLINTFLAG.PFFRDY for the ADC DMA PFFRDY trigger signal to the DMAC" value="1"/>
+      </value-group>
+    </module>
+    <module name="AT" id="04932" name2="sec_anti_tamper_v1" version="1a0" caption="Anti-Tamper Controller (AT)">
+      <register-group name="AT" caption="Anti-Tamper Controller (AT)">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control Register A">
+          <bitfield name="SWRST" caption="Software Reset1 = Reset registers , Bus I/F and internal state0 = No effect" mask="0x1"/>
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+          <bitfield name="RUNSTDBY" caption="RUNSTDBY Enable Bit" mask="0x40"/>
+        </register>
+        <register name="TAMPER_KEY" offset="0x100" rw="RW" size="4" count="16" initval="0x00000000" caption="Tamper Key n Register">
+          <bitfield name="TAMPERKEY" caption="Tamper Key Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__LEVELA" offset="0x200" rw="R" size="4" initval="0x00000000" caption="Tamper levels 0 to 7.">
+          <bitfield name="LEVEL0" caption="Level 0." mask="0xF"/>
+          <bitfield name="LEVEL1" caption="Level 1." mask="0xF0"/>
+          <bitfield name="LEVEL2" caption="Level 2." mask="0xF00"/>
+          <bitfield name="LEVEL3" caption="Level 3." mask="0xF000"/>
+          <bitfield name="LEVEL4" caption="Level 4." mask="0xF0000"/>
+          <bitfield name="LEVEL5" caption="Level 5." mask="0xF00000"/>
+          <bitfield name="LEVEL6" caption="Level 6." mask="0xF000000"/>
+          <bitfield name="LEVEL7" caption="Level 7." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__LEVELB" offset="0x204" rw="R" size="4" initval="0x00000000" caption="Tamper levels 8 to 15.">
+          <bitfield name="LEVEL8" caption="Level 8." mask="0xF"/>
+          <bitfield name="LEVEL9" caption="Level 9." mask="0xF0"/>
+          <bitfield name="LEVEL10" caption="Level 10." mask="0xF00"/>
+          <bitfield name="LEVEL11" caption="Level 11." mask="0xF000"/>
+          <bitfield name="LEVEL12" caption="Level 12." mask="0xF0000"/>
+          <bitfield name="LEVEL13" caption="Level 13." mask="0xF00000"/>
+          <bitfield name="LEVEL14" caption="Level 14." mask="0xF000000"/>
+          <bitfield name="LEVEL15" caption="Level 15." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__LEVELC" offset="0x208" rw="R" size="4" initval="0x00000000" caption="Tamper levels 16 to 23.">
+          <bitfield name="LEVEL16" caption="Level 16." mask="0xF"/>
+          <bitfield name="LEVEL17" caption="Level 17." mask="0xF0"/>
+          <bitfield name="LEVEL18" caption="Level 18." mask="0xF00"/>
+          <bitfield name="LEVEL19" caption="Level 19." mask="0xF000"/>
+          <bitfield name="LEVEL20" caption="Level 20." mask="0xF0000"/>
+          <bitfield name="LEVEL21" caption="Level 21." mask="0xF00000"/>
+          <bitfield name="LEVEL22" caption="Level 22." mask="0xF000000"/>
+          <bitfield name="LEVEL23" caption="Level 23." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__LEVELD" offset="0x20C" rw="R" size="4" initval="0x00000000" caption="Tamper levels 24 to 31.">
+          <bitfield name="LEVEL24" caption="Level 24." mask="0xF"/>
+          <bitfield name="LEVEL25" caption="Level 25." mask="0xF0"/>
+          <bitfield name="LEVEL26" caption="Level 26." mask="0xF00"/>
+          <bitfield name="LEVEL27" caption="Level 27." mask="0xF000"/>
+          <bitfield name="LEVEL28" caption="Level 28." mask="0xF0000"/>
+          <bitfield name="LEVEL29" caption="Level 29." mask="0xF00000"/>
+          <bitfield name="LEVEL30" caption="Level 30." mask="0xF000000"/>
+          <bitfield name="LEVEL31" caption="Level 31." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__SETLEVEL" offset="0x210" rw="W" size="4" initval="0x00000000" caption="Set tamper level.">
+          <bitfield name="LEVEL" caption="Tamper level." mask="0x7"/>
+          <bitfield name="ID" caption="Tamper ID." mask="0x1F00"/>
+          <bitfield name="PROTKEY" caption="Protection key (0xA84C)." mask="0xFFFF0000"/>
+        </register>
+        <register name="anti_tamper__FILTERCFG" offset="0x214" rw="RW" size="4" initval="0x00000000" caption="Filter configuration (threshold, period).">
+          <bitfield name="THRESH" caption="Threshold." mask="0x7"/>
+          <bitfield name="PERIOD" caption="Period." mask="0x1F00"/>
+          <bitfield name="PROTKEY" caption="Protection key (0x92F5)." mask="0xFFFF0000"/>
+        </register>
+        <register name="anti_tamper__SOFTTAMP" offset="0x218" rw="RW" size="4" initval="0x00000000" caption="Software triggered tamper.">
+          <bitfield name="ACTIVE" caption="Tamper active." mask="0x1"/>
+          <bitfield name="ID" caption="Tamper ID." mask="0x1F00"/>
+          <bitfield name="PROTKEY" caption="Protection key (0x4BEE)." mask="0xFFFF0000"/>
+        </register>
+        <register name="anti_tamper__RAWSTAT" offset="0x21C" rw="R" size="4" initval="0x00000000" caption="Raw status.">
+          <bitfield name="RAWSTAT" caption="Raw status." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__STAT" offset="0x220" rw="RW" size="4" initval="0x00000001" caption="Status (write to clear).">
+          <bitfield name="STAT" caption="Status (write to clear)." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__TIMESTAMP" offset="0x224" rw="R" size="4" initval="0x00000000" caption="Timestamp for the last tamper.">
+          <bitfield name="TIMESTAMP" caption="Timestamp for the last tamper." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__FILTERCNT" offset="0x228" rw="R" size="4" initval="0x00000000" caption="Current value of filter counter.">
+          <bitfield name="FILTERCNT" caption="Current value of filter counter." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__SOFTINFO" offset="0x22C" rw="RW" size="4" initval="0x00000000" caption="Register for software purpose only.">
+          <bitfield name="SOFTINFO" caption="Register for software purpose only." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__TAMPERFLAG" offset="0x230" rw="RW" size="4" initval="0x00000000" caption="The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output.">
+          <bitfield name="TAMPERFLAG" caption="The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output." mask="0x1"/>
+        </register>
+        <register name="anti_tamper__SOFTRESET" offset="0x234" rw="R" size="4" atomic-op="set:anti_tamper__SOFTRESET" initval="0x00000000" caption="Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above.">
+          <bitfield name="SOFTRESET" caption="Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above." mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="0" caption="AT registers accessible in privileged and unprivileged modes." value="0"/>
+        <value name="1" caption="AT registers only accessible in privileged mode." value="1"/>
+      </value-group>
+    </module>
+    <module name="BROMC" id="04402" name2="prm_boot_ahb_v2" version="2a0" caption="ARM GF55LPx Boot ROM Controller Macro">
+      <register-group name="BROMC" caption="ARM GF55LPx Boot ROM Controller Macro">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000002" caption="Control A REGISTER">
+          <bitfield name="SWRST" caption="Software Reset bit" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable bit" mask="0x2" values="CTRLA__ENABLE"/>
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+          <bitfield name="PRMWS" caption="ROM Access Time Wait State" mask="0x700" values="CTRLA__PRMWS"/>
+        </register>
+        <register name="UCFG" offset="0x4" rw="R" size="4" initval="0x00000001" caption="User Configuration REGISTER">
+          <bitfield name="BCRCDIS" caption="Boot CRC Disable" mask="0x1" values="UCFG__BCRCDIS"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__ENABLE">
+        <value name="0" caption="Disable ROM read access and power down the ROM. The ROM PGEN input is driven high. The ROM will clamp outputs to 1 and disable all internal current sinks. Refer to the ROM compiler specification for details on powering down the ROM." value="0"/>
+        <value name="1" caption="Enable ROM read access, power up the ROM. The ROM PGEN input is driven low." value="1"/>
+      </value-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="0" caption="Macro register accessible in privileged and unprivileged modes" value="0"/>
+        <value name="1" caption="Macro registers only accessible in privileged mode" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__PRMWS">
+        <value name="0" caption="No wait states, single cycle access" value="0"/>
+        <value name="1" caption="Access time extended 2 clock cycles" value="1"/>
+        <value name="2" caption="Access time extended to 3 clock cycles" value="2"/>
+        <value name="7" caption="Access time extended to 8 clock cycles" value="7"/>
+      </value-group>
+      <value-group name="UCFG__BCRCDIS">
+        <value name="0" caption="Boot ROM content is CRC verified by the ROM controller, status is reported to the DSU. On CRC failure, the controller blocks access to the ROM controller." value="0"/>
+        <value name="1" caption="No CRC verification at Boot." value="1"/>
+      </value-group>
+    </module>
+    <module name="CAN" id="05010" name2="can_fd_apb_v1" version="1a0" caption="Control Area Network">
+      <register-group name="CAN" caption="Control Area Network">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="PRIV" caption="Priveged Access" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run during standby" mask="0x40"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B Register">
+          <bitfield name="OFFSET" caption="Message RAM Base Address Offset." mask="0xFF0000"/>
+        </register>
+        <register name="INTENCLR" offset="0x28" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear register">
+          <bitfield name="DBG" caption="Debug Message Interrupt Disable" mask="0x1"/>
+          <bitfield name="BERR" caption="Bus Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x2C" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set register">
+          <bitfield name="DBG" caption="Debug Message Interrupt Enable" mask="0x1"/>
+          <bitfield name="BERR" caption="Bus Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x30" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear register">
+          <bitfield name="DBG" caption="Debug Message Reception" mask="0x1"/>
+          <bitfield name="BERR" caption="AHB Bus Error Detection" mask="0x2"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x34" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="Interrupt Flag Software Set Register">
+          <bitfield name="DBG" caption="Debug Message Interrupt Flag Set" mask="0x1"/>
+          <bitfield name="BERR" caption="AHB Bus Error Detection Interrupt Flag Set" mask="0x2"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x5C" rw="R" size="4" initval="0x00000000" caption="SYNCBUSY Register">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+        </register>
+        <register name="CREL_MCAN" offset="0x100" rw="R" size="4" initval="0x33000000" caption="Core Release">
+          <bitfield name="DAY" caption="Timestamp day" mask="0xFF"/>
+          <bitfield name="MON" caption="Timestamp month" mask="0xFF00"/>
+          <bitfield name="YEAR" caption="Timestamp year" mask="0xF0000"/>
+          <bitfield name="SUBSTEP" caption="Sub-step of Core Release" mask="0xF00000"/>
+          <bitfield name="STEP" caption="Step of Core Release" mask="0xF000000"/>
+          <bitfield name="REL" caption="Core Release" mask="0xF0000000"/>
+        </register>
+        <register name="ENDN" offset="0x104" rw="R" size="4" initval="0x87654321" caption="Endian">
+          <bitfield name="ETV" caption="Endianness Test Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CUST" offset="0x108" rw="RW" size="4" initval="0x00000000" caption="Customer Register">
+          <bitfield name="CUST" caption="Customer Register" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DBTP" offset="0x10C" rw="RW" size="4" initval="0x00000A33" caption="Fast Bit Timing and Prescaler">
+          <bitfield name="DSJW" caption="Data (Re)Synchronization Jump Width" mask="0xF"/>
+          <bitfield name="DTSEG2" caption="Data time segment after sample point" mask="0xF0"/>
+          <bitfield name="DTSEG1" caption="Data time segment before sample point" mask="0x1F00"/>
+          <bitfield name="DBRP" caption="Data Baud Rate Prescaler" mask="0x1F0000"/>
+          <bitfield name="TDC" caption="Tranceiver Delay Compensation" mask="0x800000"/>
+        </register>
+        <register name="TEST" offset="0x110" rw="RW" size="4" initval="0x00000000" caption="Test">
+          <bitfield name="LBCK" caption="Loop Back Mode" mask="0x10"/>
+          <bitfield name="TX" caption="Control of Transmit Pin" mask="0x60" values="TEST__TX"/>
+          <bitfield name="RX" caption="Receive Pin" mask="0x80"/>
+        </register>
+        <register name="RWD" offset="0x114" rw="RW" size="4" initval="0x00000000" caption="RAM Watchdog">
+          <bitfield name="WDC" caption="Watchdog Configuration" mask="0xFF"/>
+          <bitfield name="WDV" caption="Watchdog Value" mask="0xFF00"/>
+        </register>
+        <register name="CCCR" offset="0x118" rw="RW" access="WSYNC" size="4" initval="0x00000001" caption="CC Control">
+          <bitfield name="INIT" caption="Initialization" mask="0x1"/>
+          <bitfield name="CCE" caption="Configuration Change Enable" mask="0x2"/>
+          <bitfield name="ASM" caption="ASM Restricted Operation Mode" mask="0x4"/>
+          <bitfield name="CSA" caption="Clock Stop Acknowledge" mask="0x8"/>
+          <bitfield name="CSR" caption="Clock Stop Request" mask="0x10"/>
+          <bitfield name="MON" caption="Bus Monitoring Mode" mask="0x20"/>
+          <bitfield name="DAR" caption="Disable Automatic Retransmission" mask="0x40"/>
+          <bitfield name="TEST" caption="Test Mode Enable" mask="0x80"/>
+          <bitfield name="FDOE" caption="FD Operation Enable" mask="0x100"/>
+          <bitfield name="BRSE" caption="Bit Rate Switch Enable" mask="0x200"/>
+          <bitfield name="UTSU" caption="Use Timestamping Unit" mask="0x400"/>
+          <bitfield name="WMM" caption="Wide Message Marker" mask="0x800"/>
+          <bitfield name="PXHD" caption="Protocol Exception Handling Disable" mask="0x1000"/>
+          <bitfield name="EFBI" caption="Edge Filtering during Bus Integration" mask="0x2000"/>
+          <bitfield name="TXP" caption="Transmit Pause" mask="0x4000"/>
+        </register>
+        <register name="NBTP" offset="0x11C" rw="RW" size="4" initval="0x06000A03" caption="Nominal Bit Timing and Prescaler">
+          <bitfield name="NTSEG2" caption="Nominal Time segment after sample point" mask="0x7F"/>
+          <bitfield name="NTSEG1" caption="Nominal Time segment before sample point" mask="0xFF00"/>
+          <bitfield name="NBRP" caption="Nominal Baud Rate Prescaler" mask="0x1FF0000"/>
+          <bitfield name="NSJW" caption="Nominal (Re)Synchronization Jump Width" mask="0xFE000000"/>
+        </register>
+        <register name="TSCC" offset="0x120" rw="RW" size="4" initval="0x00000000" caption="Timestamp Counter Configuration">
+          <bitfield name="TSS" caption="Timestamp Select" mask="0x3" values="TSCC__TSS"/>
+          <bitfield name="TCP" caption="Timestamp Counter Prescaler" mask="0xF0000"/>
+        </register>
+        <register name="TSCV" offset="0x124" rw="R" size="4" initval="0x00000000" caption="Timestamp Counter Value">
+          <bitfield name="TSC" caption="Timestamp Counter" mask="0xFFFF"/>
+        </register>
+        <register name="TOCC" offset="0x128" rw="RW" size="4" initval="0xFFFF0000" caption="Timeout Counter Configuration">
+          <bitfield name="ETOC" caption="Enable Timeout Counter" mask="0x1"/>
+          <bitfield name="TOS" caption="Timeout Select" mask="0x6" values="TOCC__TOS"/>
+          <bitfield name="TOP" caption="Timeout Period" mask="0xFFFF0000"/>
+        </register>
+        <register name="TOCV" offset="0x12C" rw="RW" size="4" initval="0x0000FFFF" caption="Timeout Counter Value">
+          <bitfield name="TOC" caption="Timeout Counter" mask="0xFFFF"/>
+        </register>
+        <register name="ECR" offset="0x140" rw="R" size="4" initval="0x00000000" caption="Error Counter">
+          <bitfield name="TEC" caption="Transmit Error Counter" mask="0xFF"/>
+          <bitfield name="REC" caption="Receive Error Counter" mask="0x7F00"/>
+          <bitfield name="RP" caption="Receive Error Passive" mask="0x8000"/>
+          <bitfield name="CEL" caption="CAN Error Logging" mask="0xFF0000"/>
+        </register>
+        <register name="PSR" offset="0x144" rw="R" size="4" initval="0x00000707" caption="Protocol Status">
+          <bitfield name="LEC" caption="Last Error Code" mask="0x7" values="PSR__LEC"/>
+          <bitfield name="ACT" caption="Activity" mask="0x18" values="PSR__ACT"/>
+          <bitfield name="EP" caption="Error Passive" mask="0x20"/>
+          <bitfield name="EW" caption="Warning Status" mask="0x40"/>
+          <bitfield name="BO" caption="Bus_Off Status" mask="0x80"/>
+          <bitfield name="DLEC" caption="Data Phase Last Error Code" mask="0x700" values="PSR__DLEC"/>
+          <bitfield name="RESI" caption="ESI flag of last received CAN FD Message" mask="0x800"/>
+          <bitfield name="RBRS" caption="BRS flag of last received CAN FD Message" mask="0x1000"/>
+          <bitfield name="RFDF" caption="Received a CAN FD Message" mask="0x2000"/>
+          <bitfield name="PXE" caption="Protocol Exception Event" mask="0x4000"/>
+          <bitfield name="TDCV" caption="Transmitter Delay Compensation Value" mask="0x7F0000"/>
+        </register>
+        <register name="TDCR" offset="0x148" rw="RW" size="4" initval="0x00000000" caption="Extended ID Filter Configuration">
+          <bitfield name="TDCF" caption="Transmitter Delay Compensation Filter Length" mask="0x7F"/>
+          <bitfield name="TDCO" caption="Transmitter Delay Compensation Offset" mask="0x7F00"/>
+        </register>
+        <register name="IR" offset="0x150" rw="RW" size="4" initval="0x00000000" caption="Interrupt">
+          <bitfield name="RF0N" caption="Rx FIFO 0 New Message" mask="0x1"/>
+          <bitfield name="RF0W" caption="Rx FIFO 0 Watermark Reached" mask="0x2"/>
+          <bitfield name="RF0F" caption="Rx FIFO 0 Full" mask="0x4"/>
+          <bitfield name="RF0L" caption="Rx FIFO 0 Message Lost" mask="0x8"/>
+          <bitfield name="RF1N" caption="Rx FIFO 1 New Message" mask="0x10"/>
+          <bitfield name="RF1W" caption="Rx FIFO 1 Watermark Reached" mask="0x20"/>
+          <bitfield name="RF1F" caption="Rx FIFO 1 FIFO Full" mask="0x40"/>
+          <bitfield name="RF1L" caption="Rx FIFO 1 Message Lost" mask="0x80"/>
+          <bitfield name="HPM" caption="High Priority Message" mask="0x100"/>
+          <bitfield name="TC" caption="Timestamp Completed" mask="0x200"/>
+          <bitfield name="TCF" caption="Transmission Cancellation Finished" mask="0x400"/>
+          <bitfield name="TFE" caption="Tx FIFO Empty" mask="0x800"/>
+          <bitfield name="TEFN" caption="Tx Event FIFO New Entry" mask="0x1000"/>
+          <bitfield name="TEFW" caption="Tx Event FIFO Watermark Reached" mask="0x2000"/>
+          <bitfield name="TEFF" caption="Tx Event FIFO Full" mask="0x4000"/>
+          <bitfield name="TEFL" caption="Tx Event FIFO Element Lost" mask="0x8000"/>
+          <bitfield name="TSW" caption="Timestamp Wraparound" mask="0x10000"/>
+          <bitfield name="MRAF" caption="Message RAM Access Failure" mask="0x20000"/>
+          <bitfield name="TOO" caption="Timeout Occurred" mask="0x40000"/>
+          <bitfield name="DRX" caption="Message stored to Dedicated Rx Buffer" mask="0x80000"/>
+          <bitfield name="ELO" caption="Error Logging Overflow" mask="0x400000"/>
+          <bitfield name="EP" caption="Error Passive" mask="0x800000"/>
+          <bitfield name="EW" caption="Warning Status" mask="0x1000000"/>
+          <bitfield name="BO" caption="Bus_Off Status" mask="0x2000000"/>
+          <bitfield name="WDI" caption="Watchdog Interrupt" mask="0x4000000"/>
+          <bitfield name="PEA" caption="Protocol Error in Arbitration Phase" mask="0x8000000"/>
+          <bitfield name="PED" caption="Protocol Error in Data Phase" mask="0x10000000"/>
+          <bitfield name="ARA" caption="Access to Reserved Address" mask="0x20000000"/>
+        </register>
+        <register name="IE" offset="0x154" rw="RW" size="4" initval="0x00000000" caption="Interrupt Enable">
+          <bitfield name="RF0NE" caption="Rx FIFO 0 New Message Interrupt Enable" mask="0x1"/>
+          <bitfield name="RF0WE" caption="Rx FIFO 0 Watermark Reached Interrupt Enable" mask="0x2"/>
+          <bitfield name="RF0FE" caption="Rx FIFO 0 Full Interrupt Enable" mask="0x4"/>
+          <bitfield name="RF0LE" caption="Rx FIFO 0 Message Lost Interrupt Enable" mask="0x8"/>
+          <bitfield name="RF1NE" caption="Rx FIFO 1 New Message Interrupt Enable" mask="0x10"/>
+          <bitfield name="RF1WE" caption="Rx FIFO 1 Watermark Reached Interrupt Enable" mask="0x20"/>
+          <bitfield name="RF1FE" caption="Rx FIFO 1 FIFO Full Interrupt Enable" mask="0x40"/>
+          <bitfield name="RF1LE" caption="Rx FIFO 1 Message Lost Interrupt Enable" mask="0x80"/>
+          <bitfield name="HPME" caption="High Priority Message Interrupt Enable" mask="0x100"/>
+          <bitfield name="TCE" caption="Timestamp Completed Interrupt Enable" mask="0x200"/>
+          <bitfield name="TCFE" caption="Transmission Cancellation Finished Interrupt Enable" mask="0x400"/>
+          <bitfield name="TFEE" caption="Tx FIFO Empty Interrupt Enable" mask="0x800"/>
+          <bitfield name="TEFNE" caption="Tx Event FIFO New Entry Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TEFWE" caption="Tx Event FIFO Watermark Reached Interrupt Enable" mask="0x2000"/>
+          <bitfield name="TEFFE" caption="Tx Event FIFO Full Interrupt Enable" mask="0x4000"/>
+          <bitfield name="TEFLE" caption="Tx Event FIFO Element Lost Interrupt Enable" mask="0x8000"/>
+          <bitfield name="TSWE" caption="Timestamp Wraparound Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MRAFE" caption="Message RAM Access Failure Interrupt Enable" mask="0x20000"/>
+          <bitfield name="TOOE" caption="Timeout Occurred Interrupt Enable" mask="0x40000"/>
+          <bitfield name="DRXE" caption="Message stored to Dedicated Rx Buffer Interrupt Enable" mask="0x80000"/>
+          <bitfield name="ELOE" caption="Error Logging Overflow Interrupt Enable" mask="0x400000"/>
+          <bitfield name="EPE" caption="Error Passive Interrupt Enable" mask="0x800000"/>
+          <bitfield name="EWE" caption="Warning Status Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="BOE" caption="Bus_Off Status Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="WDIE" caption="Watchdog Interrupt Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="PEAE" caption="Protocol Error in Arbitration Phase Enable" mask="0x8000000"/>
+          <bitfield name="PEDE" caption="Protocol Error in Data Phase Enable" mask="0x10000000"/>
+          <bitfield name="ARAE" caption="Access to Reserved Address Enable" mask="0x20000000"/>
+        </register>
+        <register name="ILS" offset="0x158" rw="RW" size="4" initval="0x00000000" caption="Interrupt Line Select">
+          <bitfield name="RF0NL" caption="Rx FIFO 0 New Message Interrupt Line" mask="0x1"/>
+          <bitfield name="RF0WL" caption="Rx FIFO 0 Watermark Reached Interrupt Line" mask="0x2"/>
+          <bitfield name="RF0FL" caption="Rx FIFO 0 Full Interrupt Line" mask="0x4"/>
+          <bitfield name="RF0LL" caption="Rx FIFO 0 Message Lost Interrupt Line" mask="0x8"/>
+          <bitfield name="RF1NL" caption="Rx FIFO 1 New Message Interrupt Line" mask="0x10"/>
+          <bitfield name="RF1WL" caption="Rx FIFO 1 Watermark Reached Interrupt Line" mask="0x20"/>
+          <bitfield name="RF1FL" caption="Rx FIFO 1 FIFO Full Interrupt Line" mask="0x40"/>
+          <bitfield name="RF1LL" caption="Rx FIFO 1 Message Lost Interrupt Line" mask="0x80"/>
+          <bitfield name="HPML" caption="High Priority Message Interrupt Line" mask="0x100"/>
+          <bitfield name="TCL" caption="Timestamp Completed Interrupt Line" mask="0x200"/>
+          <bitfield name="TCFL" caption="Transmission Cancellation Finished Interrupt Line" mask="0x400"/>
+          <bitfield name="TFEL" caption="Tx FIFO Empty Interrupt Line" mask="0x800"/>
+          <bitfield name="TEFNL" caption="Tx Event FIFO New Entry Interrupt Line" mask="0x1000"/>
+          <bitfield name="TEFWL" caption="Tx Event FIFO Watermark Reached Interrupt Line" mask="0x2000"/>
+          <bitfield name="TEFFL" caption="Tx Event FIFO Full Interrupt Line" mask="0x4000"/>
+          <bitfield name="TEFLL" caption="Tx Event FIFO Element Lost Interrupt Line" mask="0x8000"/>
+          <bitfield name="TSWL" caption="Timestamp Wraparound Interrupt Line" mask="0x10000"/>
+          <bitfield name="MRAFL" caption="Message RAM Access Failure Interrupt Line" mask="0x20000"/>
+          <bitfield name="TOOL" caption="Timeout Occurred Interrupt Line" mask="0x40000"/>
+          <bitfield name="DRXL" caption="Message stored to Dedicated Rx Buffer Interrupt Line" mask="0x80000"/>
+          <bitfield name="ELOL" caption="Error Logging Overflow Interrupt Line" mask="0x400000"/>
+          <bitfield name="EPL" caption="Error Passive Interrupt Line" mask="0x800000"/>
+          <bitfield name="EWL" caption="Warning Status Interrupt Line" mask="0x1000000"/>
+          <bitfield name="BOL" caption="Bus_Off Status Interrupt Line" mask="0x2000000"/>
+          <bitfield name="WDIL" caption="Watchdog Interrupt Interrupt Line" mask="0x4000000"/>
+          <bitfield name="PEAL" caption="Protocol Error in Arbitration Phase Line" mask="0x8000000"/>
+          <bitfield name="PEDL" caption="Protocol Error in Data Phase Line" mask="0x10000000"/>
+          <bitfield name="ARAL" caption="Access to Reserved Address Line" mask="0x20000000"/>
+        </register>
+        <register name="ILE" offset="0x15C" rw="RW" size="4" initval="0x00000000" caption="Interrupt Line Enable">
+          <bitfield name="EINT0" caption="Enable Interrupt Line 0" mask="0x1"/>
+          <bitfield name="EINT1" caption="Enable Interrupt Line 1" mask="0x2"/>
+        </register>
+        <register name="GFC" offset="0x180" rw="RW" size="4" initval="0x00000000" caption="Global Filter Configuration">
+          <bitfield name="RRFE" caption="Reject Remote Frames Extended" mask="0x1"/>
+          <bitfield name="RRFS" caption="Reject Remote Frames Standard" mask="0x2"/>
+          <bitfield name="ANFE" caption="Accept Non-matching Frames Extended" mask="0xC" values="GFC__ANFE"/>
+          <bitfield name="ANFS" caption="Accept Non-matching Frames Standard" mask="0x30" values="GFC__ANFS"/>
+        </register>
+        <register name="SIDFC" offset="0x184" rw="RW" size="4" initval="0x00000000" caption="Standard ID Filter Configuration">
+          <bitfield name="FLSSA" caption="Filter List Standard Start Address" mask="0xFFFC"/>
+          <bitfield name="LSS" caption="List Size Standard" mask="0xFF0000"/>
+        </register>
+        <register name="XIDFC" offset="0x188" rw="RW" size="4" initval="0x00000000" caption="Extended ID Filter Configuration">
+          <bitfield name="FLESA" caption="Filter List Extended Start Address" mask="0xFFFC"/>
+          <bitfield name="LSE" caption="List Size Extended" mask="0x7F0000"/>
+        </register>
+        <register name="XIDAM" offset="0x190" rw="RW" size="4" initval="0x1FFFFFFF" caption="Extended ID AND Mask">
+          <bitfield name="EIDM" caption="Extended ID Mask" mask="0x1FFFFFFF"/>
+        </register>
+        <register name="HPMS" offset="0x194" rw="R" size="4" initval="0x00000000" caption="High Priority Message Status">
+          <bitfield name="BIDX" caption="Buffer Index" mask="0x3F"/>
+          <bitfield name="MSI" caption="Message Storage Indicator" mask="0xC0" values="HPMS__MSI"/>
+          <bitfield name="FIDX" caption="Filter Index" mask="0x7F00"/>
+          <bitfield name="FLST" caption="Filter List" mask="0x8000"/>
+        </register>
+        <register name="NDAT1" offset="0x198" rw="RW" size="4" initval="0x00000000" caption="New Data 1">
+          <bitfield name="ND0" caption="New Data 0" mask="0x1"/>
+          <bitfield name="ND1" caption="New Data 1" mask="0x2"/>
+          <bitfield name="ND2" caption="New Data 2" mask="0x4"/>
+          <bitfield name="ND3" caption="New Data 3" mask="0x8"/>
+          <bitfield name="ND4" caption="New Data 4" mask="0x10"/>
+          <bitfield name="ND5" caption="New Data 5" mask="0x20"/>
+          <bitfield name="ND6" caption="New Data 6" mask="0x40"/>
+          <bitfield name="ND7" caption="New Data 7" mask="0x80"/>
+          <bitfield name="ND8" caption="New Data 8" mask="0x100"/>
+          <bitfield name="ND9" caption="New Data 9" mask="0x200"/>
+          <bitfield name="ND10" caption="New Data 10" mask="0x400"/>
+          <bitfield name="ND11" caption="New Data 11" mask="0x800"/>
+          <bitfield name="ND12" caption="New Data 12" mask="0x1000"/>
+          <bitfield name="ND13" caption="New Data 13" mask="0x2000"/>
+          <bitfield name="ND14" caption="New Data 14" mask="0x4000"/>
+          <bitfield name="ND15" caption="New Data 15" mask="0x8000"/>
+          <bitfield name="ND16" caption="New Data 16" mask="0x10000"/>
+          <bitfield name="ND17" caption="New Data 17" mask="0x20000"/>
+          <bitfield name="ND18" caption="New Data 18" mask="0x40000"/>
+          <bitfield name="ND19" caption="New Data 19" mask="0x80000"/>
+          <bitfield name="ND20" caption="New Data 20" mask="0x100000"/>
+          <bitfield name="ND21" caption="New Data 21" mask="0x200000"/>
+          <bitfield name="ND22" caption="New Data 22" mask="0x400000"/>
+          <bitfield name="ND23" caption="New Data 23" mask="0x800000"/>
+          <bitfield name="ND24" caption="New Data 24" mask="0x1000000"/>
+          <bitfield name="ND25" caption="New Data 25" mask="0x2000000"/>
+          <bitfield name="ND26" caption="New Data 26" mask="0x4000000"/>
+          <bitfield name="ND27" caption="New Data 27" mask="0x8000000"/>
+          <bitfield name="ND28" caption="New Data 28" mask="0x10000000"/>
+          <bitfield name="ND29" caption="New Data 29" mask="0x20000000"/>
+          <bitfield name="ND30" caption="New Data 30" mask="0x40000000"/>
+          <bitfield name="ND31" caption="New Data 31" mask="0x80000000"/>
+        </register>
+        <register name="NDAT2" offset="0x19C" rw="RW" size="4" initval="0x00000000" caption="New Data 2">
+          <bitfield name="ND32" caption="New Data 32" mask="0x1"/>
+          <bitfield name="ND33" caption="New Data 33" mask="0x2"/>
+          <bitfield name="ND34" caption="New Data 34" mask="0x4"/>
+          <bitfield name="ND35" caption="New Data 35" mask="0x8"/>
+          <bitfield name="ND36" caption="New Data 36" mask="0x10"/>
+          <bitfield name="ND37" caption="New Data 37" mask="0x20"/>
+          <bitfield name="ND38" caption="New Data 38" mask="0x40"/>
+          <bitfield name="ND39" caption="New Data 39" mask="0x80"/>
+          <bitfield name="ND40" caption="New Data 40" mask="0x100"/>
+          <bitfield name="ND41" caption="New Data 41" mask="0x200"/>
+          <bitfield name="ND42" caption="New Data 42" mask="0x400"/>
+          <bitfield name="ND43" caption="New Data 43" mask="0x800"/>
+          <bitfield name="ND44" caption="New Data 44" mask="0x1000"/>
+          <bitfield name="ND45" caption="New Data 45" mask="0x2000"/>
+          <bitfield name="ND46" caption="New Data 46" mask="0x4000"/>
+          <bitfield name="ND47" caption="New Data 47" mask="0x8000"/>
+          <bitfield name="ND48" caption="New Data 48" mask="0x10000"/>
+          <bitfield name="ND49" caption="New Data 49" mask="0x20000"/>
+          <bitfield name="ND50" caption="New Data 50" mask="0x40000"/>
+          <bitfield name="ND51" caption="New Data 51" mask="0x80000"/>
+          <bitfield name="ND52" caption="New Data 52" mask="0x100000"/>
+          <bitfield name="ND53" caption="New Data 53" mask="0x200000"/>
+          <bitfield name="ND54" caption="New Data 54" mask="0x400000"/>
+          <bitfield name="ND55" caption="New Data 55" mask="0x800000"/>
+          <bitfield name="ND56" caption="New Data 56" mask="0x1000000"/>
+          <bitfield name="ND57" caption="New Data 57" mask="0x2000000"/>
+          <bitfield name="ND58" caption="New Data 58" mask="0x4000000"/>
+          <bitfield name="ND59" caption="New Data 59" mask="0x8000000"/>
+          <bitfield name="ND60" caption="New Data 60" mask="0x10000000"/>
+          <bitfield name="ND61" caption="New Data 61" mask="0x20000000"/>
+          <bitfield name="ND62" caption="New Data 62" mask="0x40000000"/>
+          <bitfield name="ND63" caption="New Data 63" mask="0x80000000"/>
+        </register>
+        <register name="RXF0C" offset="0x1A0" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 0 Configuration">
+          <bitfield name="F0SA" caption="Rx FIFO 0 Start Address" mask="0xFFFC"/>
+          <bitfield name="F0S" caption="Rx FIFO 0 Size" mask="0x7F0000"/>
+          <bitfield name="F0WM" caption="Rx FIFO 0 Watermark" mask="0x7F000000"/>
+          <bitfield name="F0OM" caption="FIFO 0 Operation Mode" mask="0x80000000"/>
+        </register>
+        <register name="RXF0S" offset="0x1A4" rw="R" size="4" initval="0x00000000" caption="Rx FIFO 0 Status">
+          <bitfield name="F0FL" caption="Rx FIFO 0 Fill Level" mask="0x7F"/>
+          <bitfield name="F0GI" caption="Rx FIFO 0 Get Index" mask="0x3F00"/>
+          <bitfield name="F0PI" caption="Rx FIFO 0 Put Index" mask="0x3F0000"/>
+          <bitfield name="F0F" caption="Rx FIFO 0 Full" mask="0x1000000"/>
+          <bitfield name="RF0L" caption="Rx FIFO 0 Message Lost" mask="0x2000000"/>
+        </register>
+        <register name="RXF0A" offset="0x1A8" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 0 Acknowledge">
+          <bitfield name="F0AI" caption="Rx FIFO 0 Acknowledge Index" mask="0x3F"/>
+        </register>
+        <register name="RXBC" offset="0x1AC" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer Configuration">
+          <bitfield name="RBSA" caption="Rx Buffer Start Address" mask="0xFFFC"/>
+        </register>
+        <register name="RXF1C" offset="0x1B0" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 1 Configuration">
+          <bitfield name="F1SA" caption="Rx FIFO 1 Start Address" mask="0xFFFC"/>
+          <bitfield name="F1S" caption="Rx FIFO 1 Size" mask="0x7F0000"/>
+          <bitfield name="F1WM" caption="Rx FIFO 1 Watermark" mask="0x7F000000"/>
+          <bitfield name="F1OM" caption="FIFO 1 Operation Mode" mask="0x80000000"/>
+        </register>
+        <register name="RXF1S" offset="0x1B4" rw="R" size="4" initval="0x00000000" caption="Rx FIFO 1 Status">
+          <bitfield name="F1FL" caption="Rx FIFO 1 Fill Level" mask="0x7F"/>
+          <bitfield name="F1GI" caption="Rx FIFO 1 Get Index" mask="0x3F00"/>
+          <bitfield name="F1PI" caption="Rx FIFO 1 Put Index" mask="0x3F0000"/>
+          <bitfield name="F1F" caption="Rx FIFO 1 Full" mask="0x1000000"/>
+          <bitfield name="RF1L" caption="Rx FIFO 1 Message Lost" mask="0x2000000"/>
+          <bitfield name="DMS" caption="Debug Message Status" mask="0xC0000000" values="RXF1S__DMS"/>
+        </register>
+        <register name="RXF1A" offset="0x1B8" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 1 Acknowledge">
+          <bitfield name="F1AI" caption="Rx FIFO 1 Acknowledge Index" mask="0x3F"/>
+        </register>
+        <register name="RXESC" offset="0x1BC" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer / FIFO Element Size Configuration">
+          <bitfield name="F0DS" caption="Rx FIFO 0 Data Field Size" mask="0x7" values="RXESC__F0DS"/>
+          <bitfield name="F1DS" caption="Rx FIFO 1 Data Field Size" mask="0x70" values="RXESC__F1DS"/>
+          <bitfield name="RBDS" caption="Rx Buffer Data Field Size" mask="0x700" values="RXESC__RBDS"/>
+        </register>
+        <register name="TXBC" offset="0x1C0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Configuration">
+          <bitfield name="TBSA" caption="Tx Buffers Start Address" mask="0xFFFC"/>
+          <bitfield name="NDTB" caption="Number of Dedicated Transmit Buffers" mask="0x3F0000"/>
+          <bitfield name="TFQS" caption="Transmit FIFO/Queue Size" mask="0x3F000000"/>
+          <bitfield name="TFQM" caption="Tx FIFO/Queue Mode" mask="0x40000000"/>
+        </register>
+        <register name="TXFQS" offset="0x1C4" rw="R" size="4" initval="0x00000000" caption="Tx FIFO / Queue Status">
+          <bitfield name="TFFL" caption="Tx FIFO Free Level" mask="0x3F"/>
+          <bitfield name="TFGI" caption="Tx FIFO Get Index" mask="0x1F00"/>
+          <bitfield name="TFQPI" caption="Tx FIFO/Queue Put Index" mask="0x1F0000"/>
+          <bitfield name="TFQF" caption="Tx FIFO/Queue Full" mask="0x200000"/>
+        </register>
+        <register name="TXESC" offset="0x1C8" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Element Size Configuration">
+          <bitfield name="TBDS" caption="Tx Buffer Data Field Size" mask="0x7" values="TXESC__TBDS"/>
+        </register>
+        <register name="TXBRP" offset="0x1CC" rw="R" size="4" initval="0x00000000" caption="Tx Buffer Request Pending">
+          <bitfield name="TRP0" caption="Transmission Request Pending 0" mask="0x1"/>
+          <bitfield name="TRP1" caption="Transmission Request Pending 1" mask="0x2"/>
+          <bitfield name="TRP2" caption="Transmission Request Pending 2" mask="0x4"/>
+          <bitfield name="TRP3" caption="Transmission Request Pending 3" mask="0x8"/>
+          <bitfield name="TRP4" caption="Transmission Request Pending 4" mask="0x10"/>
+          <bitfield name="TRP5" caption="Transmission Request Pending 5" mask="0x20"/>
+          <bitfield name="TRP6" caption="Transmission Request Pending 6" mask="0x40"/>
+          <bitfield name="TRP7" caption="Transmission Request Pending 7" mask="0x80"/>
+          <bitfield name="TRP8" caption="Transmission Request Pending 8" mask="0x100"/>
+          <bitfield name="TRP9" caption="Transmission Request Pending 9" mask="0x200"/>
+          <bitfield name="TRP10" caption="Transmission Request Pending 10" mask="0x400"/>
+          <bitfield name="TRP11" caption="Transmission Request Pending 11" mask="0x800"/>
+          <bitfield name="TRP12" caption="Transmission Request Pending 12" mask="0x1000"/>
+          <bitfield name="TRP13" caption="Transmission Request Pending 13" mask="0x2000"/>
+          <bitfield name="TRP14" caption="Transmission Request Pending 14" mask="0x4000"/>
+          <bitfield name="TRP15" caption="Transmission Request Pending 15" mask="0x8000"/>
+          <bitfield name="TRP16" caption="Transmission Request Pending 16" mask="0x10000"/>
+          <bitfield name="TRP17" caption="Transmission Request Pending 17" mask="0x20000"/>
+          <bitfield name="TRP18" caption="Transmission Request Pending 18" mask="0x40000"/>
+          <bitfield name="TRP19" caption="Transmission Request Pending 19" mask="0x80000"/>
+          <bitfield name="TRP20" caption="Transmission Request Pending 20" mask="0x100000"/>
+          <bitfield name="TRP21" caption="Transmission Request Pending 21" mask="0x200000"/>
+          <bitfield name="TRP22" caption="Transmission Request Pending 22" mask="0x400000"/>
+          <bitfield name="TRP23" caption="Transmission Request Pending 23" mask="0x800000"/>
+          <bitfield name="TRP24" caption="Transmission Request Pending 24" mask="0x1000000"/>
+          <bitfield name="TRP25" caption="Transmission Request Pending 25" mask="0x2000000"/>
+          <bitfield name="TRP26" caption="Transmission Request Pending 26" mask="0x4000000"/>
+          <bitfield name="TRP27" caption="Transmission Request Pending 27" mask="0x8000000"/>
+          <bitfield name="TRP28" caption="Transmission Request Pending 28" mask="0x10000000"/>
+          <bitfield name="TRP29" caption="Transmission Request Pending 29" mask="0x20000000"/>
+          <bitfield name="TRP30" caption="Transmission Request Pending 30" mask="0x40000000"/>
+          <bitfield name="TRP31" caption="Transmission Request Pending 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBAR" offset="0x1D0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Add Request">
+          <bitfield name="AR0" caption="Add Request 0" mask="0x1"/>
+          <bitfield name="AR1" caption="Add Request 1" mask="0x2"/>
+          <bitfield name="AR2" caption="Add Request 2" mask="0x4"/>
+          <bitfield name="AR3" caption="Add Request 3" mask="0x8"/>
+          <bitfield name="AR4" caption="Add Request 4" mask="0x10"/>
+          <bitfield name="AR5" caption="Add Request 5" mask="0x20"/>
+          <bitfield name="AR6" caption="Add Request 6" mask="0x40"/>
+          <bitfield name="AR7" caption="Add Request 7" mask="0x80"/>
+          <bitfield name="AR8" caption="Add Request 8" mask="0x100"/>
+          <bitfield name="AR9" caption="Add Request 9" mask="0x200"/>
+          <bitfield name="AR10" caption="Add Request 10" mask="0x400"/>
+          <bitfield name="AR11" caption="Add Request 11" mask="0x800"/>
+          <bitfield name="AR12" caption="Add Request 12" mask="0x1000"/>
+          <bitfield name="AR13" caption="Add Request 13" mask="0x2000"/>
+          <bitfield name="AR14" caption="Add Request 14" mask="0x4000"/>
+          <bitfield name="AR15" caption="Add Request 15" mask="0x8000"/>
+          <bitfield name="AR16" caption="Add Request 16" mask="0x10000"/>
+          <bitfield name="AR17" caption="Add Request 17" mask="0x20000"/>
+          <bitfield name="AR18" caption="Add Request 18" mask="0x40000"/>
+          <bitfield name="AR19" caption="Add Request 19" mask="0x80000"/>
+          <bitfield name="AR20" caption="Add Request 20" mask="0x100000"/>
+          <bitfield name="AR21" caption="Add Request 21" mask="0x200000"/>
+          <bitfield name="AR22" caption="Add Request 22" mask="0x400000"/>
+          <bitfield name="AR23" caption="Add Request 23" mask="0x800000"/>
+          <bitfield name="AR24" caption="Add Request 24" mask="0x1000000"/>
+          <bitfield name="AR25" caption="Add Request 25" mask="0x2000000"/>
+          <bitfield name="AR26" caption="Add Request 26" mask="0x4000000"/>
+          <bitfield name="AR27" caption="Add Request 27" mask="0x8000000"/>
+          <bitfield name="AR28" caption="Add Request 28" mask="0x10000000"/>
+          <bitfield name="AR29" caption="Add Request 29" mask="0x20000000"/>
+          <bitfield name="AR30" caption="Add Request 30" mask="0x40000000"/>
+          <bitfield name="AR31" caption="Add Request 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBCR" offset="0x1D4" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Cancellation Request">
+          <bitfield name="CR0" caption="Cancellation Request 0" mask="0x1"/>
+          <bitfield name="CR1" caption="Cancellation Request 1" mask="0x2"/>
+          <bitfield name="CR2" caption="Cancellation Request 2" mask="0x4"/>
+          <bitfield name="CR3" caption="Cancellation Request 3" mask="0x8"/>
+          <bitfield name="CR4" caption="Cancellation Request 4" mask="0x10"/>
+          <bitfield name="CR5" caption="Cancellation Request 5" mask="0x20"/>
+          <bitfield name="CR6" caption="Cancellation Request 6" mask="0x40"/>
+          <bitfield name="CR7" caption="Cancellation Request 7" mask="0x80"/>
+          <bitfield name="CR8" caption="Cancellation Request 8" mask="0x100"/>
+          <bitfield name="CR9" caption="Cancellation Request 9" mask="0x200"/>
+          <bitfield name="CR10" caption="Cancellation Request 10" mask="0x400"/>
+          <bitfield name="CR11" caption="Cancellation Request 11" mask="0x800"/>
+          <bitfield name="CR12" caption="Cancellation Request 12" mask="0x1000"/>
+          <bitfield name="CR13" caption="Cancellation Request 13" mask="0x2000"/>
+          <bitfield name="CR14" caption="Cancellation Request 14" mask="0x4000"/>
+          <bitfield name="CR15" caption="Cancellation Request 15" mask="0x8000"/>
+          <bitfield name="CR16" caption="Cancellation Request 16" mask="0x10000"/>
+          <bitfield name="CR17" caption="Cancellation Request 17" mask="0x20000"/>
+          <bitfield name="CR18" caption="Cancellation Request 18" mask="0x40000"/>
+          <bitfield name="CR19" caption="Cancellation Request 19" mask="0x80000"/>
+          <bitfield name="CR20" caption="Cancellation Request 20" mask="0x100000"/>
+          <bitfield name="CR21" caption="Cancellation Request 21" mask="0x200000"/>
+          <bitfield name="CR22" caption="Cancellation Request 22" mask="0x400000"/>
+          <bitfield name="CR23" caption="Cancellation Request 23" mask="0x800000"/>
+          <bitfield name="CR24" caption="Cancellation Request 24" mask="0x1000000"/>
+          <bitfield name="CR25" caption="Cancellation Request 25" mask="0x2000000"/>
+          <bitfield name="CR26" caption="Cancellation Request 26" mask="0x4000000"/>
+          <bitfield name="CR27" caption="Cancellation Request 27" mask="0x8000000"/>
+          <bitfield name="CR28" caption="Cancellation Request 28" mask="0x10000000"/>
+          <bitfield name="CR29" caption="Cancellation Request 29" mask="0x20000000"/>
+          <bitfield name="CR30" caption="Cancellation Request 30" mask="0x40000000"/>
+          <bitfield name="CR31" caption="Cancellation Request 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBTO" offset="0x1D8" rw="R" size="4" initval="0x00000000" caption="Tx Buffer Transmission Occurred">
+          <bitfield name="TO0" caption="Transmission Occurred 0" mask="0x1"/>
+          <bitfield name="TO1" caption="Transmission Occurred 1" mask="0x2"/>
+          <bitfield name="TO2" caption="Transmission Occurred 2" mask="0x4"/>
+          <bitfield name="TO3" caption="Transmission Occurred 3" mask="0x8"/>
+          <bitfield name="TO4" caption="Transmission Occurred 4" mask="0x10"/>
+          <bitfield name="TO5" caption="Transmission Occurred 5" mask="0x20"/>
+          <bitfield name="TO6" caption="Transmission Occurred 6" mask="0x40"/>
+          <bitfield name="TO7" caption="Transmission Occurred 7" mask="0x80"/>
+          <bitfield name="TO8" caption="Transmission Occurred 8" mask="0x100"/>
+          <bitfield name="TO9" caption="Transmission Occurred 9" mask="0x200"/>
+          <bitfield name="TO10" caption="Transmission Occurred 10" mask="0x400"/>
+          <bitfield name="TO11" caption="Transmission Occurred 11" mask="0x800"/>
+          <bitfield name="TO12" caption="Transmission Occurred 12" mask="0x1000"/>
+          <bitfield name="TO13" caption="Transmission Occurred 13" mask="0x2000"/>
+          <bitfield name="TO14" caption="Transmission Occurred 14" mask="0x4000"/>
+          <bitfield name="TO15" caption="Transmission Occurred 15" mask="0x8000"/>
+          <bitfield name="TO16" caption="Transmission Occurred 16" mask="0x10000"/>
+          <bitfield name="TO17" caption="Transmission Occurred 17" mask="0x20000"/>
+          <bitfield name="TO18" caption="Transmission Occurred 18" mask="0x40000"/>
+          <bitfield name="TO19" caption="Transmission Occurred 19" mask="0x80000"/>
+          <bitfield name="TO20" caption="Transmission Occurred 20" mask="0x100000"/>
+          <bitfield name="TO21" caption="Transmission Occurred 21" mask="0x200000"/>
+          <bitfield name="TO22" caption="Transmission Occurred 22" mask="0x400000"/>
+          <bitfield name="TO23" caption="Transmission Occurred 23" mask="0x800000"/>
+          <bitfield name="TO24" caption="Transmission Occurred 24" mask="0x1000000"/>
+          <bitfield name="TO25" caption="Transmission Occurred 25" mask="0x2000000"/>
+          <bitfield name="TO26" caption="Transmission Occurred 26" mask="0x4000000"/>
+          <bitfield name="TO27" caption="Transmission Occurred 27" mask="0x8000000"/>
+          <bitfield name="TO28" caption="Transmission Occurred 28" mask="0x10000000"/>
+          <bitfield name="TO29" caption="Transmission Occurred 29" mask="0x20000000"/>
+          <bitfield name="TO30" caption="Transmission Occurred 30" mask="0x40000000"/>
+          <bitfield name="TO31" caption="Transmission Occurred 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBCF" offset="0x1DC" rw="R" size="4" initval="0x00000000" caption="Tx Buffer Cancellation Finished">
+          <bitfield name="CF0" caption="Tx Buffer Cancellation Finished 0" mask="0x1"/>
+          <bitfield name="CF1" caption="Tx Buffer Cancellation Finished 1" mask="0x2"/>
+          <bitfield name="CF2" caption="Tx Buffer Cancellation Finished 2" mask="0x4"/>
+          <bitfield name="CF3" caption="Tx Buffer Cancellation Finished 3" mask="0x8"/>
+          <bitfield name="CF4" caption="Tx Buffer Cancellation Finished 4" mask="0x10"/>
+          <bitfield name="CF5" caption="Tx Buffer Cancellation Finished 5" mask="0x20"/>
+          <bitfield name="CF6" caption="Tx Buffer Cancellation Finished 6" mask="0x40"/>
+          <bitfield name="CF7" caption="Tx Buffer Cancellation Finished 7" mask="0x80"/>
+          <bitfield name="CF8" caption="Tx Buffer Cancellation Finished 8" mask="0x100"/>
+          <bitfield name="CF9" caption="Tx Buffer Cancellation Finished 9" mask="0x200"/>
+          <bitfield name="CF10" caption="Tx Buffer Cancellation Finished 10" mask="0x400"/>
+          <bitfield name="CF11" caption="Tx Buffer Cancellation Finished 11" mask="0x800"/>
+          <bitfield name="CF12" caption="Tx Buffer Cancellation Finished 12" mask="0x1000"/>
+          <bitfield name="CF13" caption="Tx Buffer Cancellation Finished 13" mask="0x2000"/>
+          <bitfield name="CF14" caption="Tx Buffer Cancellation Finished 14" mask="0x4000"/>
+          <bitfield name="CF15" caption="Tx Buffer Cancellation Finished 15" mask="0x8000"/>
+          <bitfield name="CF16" caption="Tx Buffer Cancellation Finished 16" mask="0x10000"/>
+          <bitfield name="CF17" caption="Tx Buffer Cancellation Finished 17" mask="0x20000"/>
+          <bitfield name="CF18" caption="Tx Buffer Cancellation Finished 18" mask="0x40000"/>
+          <bitfield name="CF19" caption="Tx Buffer Cancellation Finished 19" mask="0x80000"/>
+          <bitfield name="CF20" caption="Tx Buffer Cancellation Finished 20" mask="0x100000"/>
+          <bitfield name="CF21" caption="Tx Buffer Cancellation Finished 21" mask="0x200000"/>
+          <bitfield name="CF22" caption="Tx Buffer Cancellation Finished 22" mask="0x400000"/>
+          <bitfield name="CF23" caption="Tx Buffer Cancellation Finished 23" mask="0x800000"/>
+          <bitfield name="CF24" caption="Tx Buffer Cancellation Finished 24" mask="0x1000000"/>
+          <bitfield name="CF25" caption="Tx Buffer Cancellation Finished 25" mask="0x2000000"/>
+          <bitfield name="CF26" caption="Tx Buffer Cancellation Finished 26" mask="0x4000000"/>
+          <bitfield name="CF27" caption="Tx Buffer Cancellation Finished 27" mask="0x8000000"/>
+          <bitfield name="CF28" caption="Tx Buffer Cancellation Finished 28" mask="0x10000000"/>
+          <bitfield name="CF29" caption="Tx Buffer Cancellation Finished 29" mask="0x20000000"/>
+          <bitfield name="CF30" caption="Tx Buffer Cancellation Finished 30" mask="0x40000000"/>
+          <bitfield name="CF31" caption="Tx Buffer Cancellation Finished 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBTIE" offset="0x1E0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Transmission Interrupt Enable">
+          <bitfield name="TIE0" caption="Transmission Interrupt Enable 0" mask="0x1"/>
+          <bitfield name="TIE1" caption="Transmission Interrupt Enable 1" mask="0x2"/>
+          <bitfield name="TIE2" caption="Transmission Interrupt Enable 2" mask="0x4"/>
+          <bitfield name="TIE3" caption="Transmission Interrupt Enable 3" mask="0x8"/>
+          <bitfield name="TIE4" caption="Transmission Interrupt Enable 4" mask="0x10"/>
+          <bitfield name="TIE5" caption="Transmission Interrupt Enable 5" mask="0x20"/>
+          <bitfield name="TIE6" caption="Transmission Interrupt Enable 6" mask="0x40"/>
+          <bitfield name="TIE7" caption="Transmission Interrupt Enable 7" mask="0x80"/>
+          <bitfield name="TIE8" caption="Transmission Interrupt Enable 8" mask="0x100"/>
+          <bitfield name="TIE9" caption="Transmission Interrupt Enable 9" mask="0x200"/>
+          <bitfield name="TIE10" caption="Transmission Interrupt Enable 10" mask="0x400"/>
+          <bitfield name="TIE11" caption="Transmission Interrupt Enable 11" mask="0x800"/>
+          <bitfield name="TIE12" caption="Transmission Interrupt Enable 12" mask="0x1000"/>
+          <bitfield name="TIE13" caption="Transmission Interrupt Enable 13" mask="0x2000"/>
+          <bitfield name="TIE14" caption="Transmission Interrupt Enable 14" mask="0x4000"/>
+          <bitfield name="TIE15" caption="Transmission Interrupt Enable 15" mask="0x8000"/>
+          <bitfield name="TIE16" caption="Transmission Interrupt Enable 16" mask="0x10000"/>
+          <bitfield name="TIE17" caption="Transmission Interrupt Enable 17" mask="0x20000"/>
+          <bitfield name="TIE18" caption="Transmission Interrupt Enable 18" mask="0x40000"/>
+          <bitfield name="TIE19" caption="Transmission Interrupt Enable 19" mask="0x80000"/>
+          <bitfield name="TIE20" caption="Transmission Interrupt Enable 20" mask="0x100000"/>
+          <bitfield name="TIE21" caption="Transmission Interrupt Enable 21" mask="0x200000"/>
+          <bitfield name="TIE22" caption="Transmission Interrupt Enable 22" mask="0x400000"/>
+          <bitfield name="TIE23" caption="Transmission Interrupt Enable 23" mask="0x800000"/>
+          <bitfield name="TIE24" caption="Transmission Interrupt Enable 24" mask="0x1000000"/>
+          <bitfield name="TIE25" caption="Transmission Interrupt Enable 25" mask="0x2000000"/>
+          <bitfield name="TIE26" caption="Transmission Interrupt Enable 26" mask="0x4000000"/>
+          <bitfield name="TIE27" caption="Transmission Interrupt Enable 27" mask="0x8000000"/>
+          <bitfield name="TIE28" caption="Transmission Interrupt Enable 28" mask="0x10000000"/>
+          <bitfield name="TIE29" caption="Transmission Interrupt Enable 29" mask="0x20000000"/>
+          <bitfield name="TIE30" caption="Transmission Interrupt Enable 30" mask="0x40000000"/>
+          <bitfield name="TIE31" caption="Transmission Interrupt Enable 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBCIE" offset="0x1E4" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Cancellation Finished Interrupt Enable">
+          <bitfield name="CFIE0" caption="Cancellation Finished Interrupt Enable 0" mask="0x1"/>
+          <bitfield name="CFIE1" caption="Cancellation Finished Interrupt Enable 1" mask="0x2"/>
+          <bitfield name="CFIE2" caption="Cancellation Finished Interrupt Enable 2" mask="0x4"/>
+          <bitfield name="CFIE3" caption="Cancellation Finished Interrupt Enable 3" mask="0x8"/>
+          <bitfield name="CFIE4" caption="Cancellation Finished Interrupt Enable 4" mask="0x10"/>
+          <bitfield name="CFIE5" caption="Cancellation Finished Interrupt Enable 5" mask="0x20"/>
+          <bitfield name="CFIE6" caption="Cancellation Finished Interrupt Enable 6" mask="0x40"/>
+          <bitfield name="CFIE7" caption="Cancellation Finished Interrupt Enable 7" mask="0x80"/>
+          <bitfield name="CFIE8" caption="Cancellation Finished Interrupt Enable 8" mask="0x100"/>
+          <bitfield name="CFIE9" caption="Cancellation Finished Interrupt Enable 9" mask="0x200"/>
+          <bitfield name="CFIE10" caption="Cancellation Finished Interrupt Enable 10" mask="0x400"/>
+          <bitfield name="CFIE11" caption="Cancellation Finished Interrupt Enable 11" mask="0x800"/>
+          <bitfield name="CFIE12" caption="Cancellation Finished Interrupt Enable 12" mask="0x1000"/>
+          <bitfield name="CFIE13" caption="Cancellation Finished Interrupt Enable 13" mask="0x2000"/>
+          <bitfield name="CFIE14" caption="Cancellation Finished Interrupt Enable 14" mask="0x4000"/>
+          <bitfield name="CFIE15" caption="Cancellation Finished Interrupt Enable 15" mask="0x8000"/>
+          <bitfield name="CFIE16" caption="Cancellation Finished Interrupt Enable 16" mask="0x10000"/>
+          <bitfield name="CFIE17" caption="Cancellation Finished Interrupt Enable 17" mask="0x20000"/>
+          <bitfield name="CFIE18" caption="Cancellation Finished Interrupt Enable 18" mask="0x40000"/>
+          <bitfield name="CFIE19" caption="Cancellation Finished Interrupt Enable 19" mask="0x80000"/>
+          <bitfield name="CFIE20" caption="Cancellation Finished Interrupt Enable 20" mask="0x100000"/>
+          <bitfield name="CFIE21" caption="Cancellation Finished Interrupt Enable 21" mask="0x200000"/>
+          <bitfield name="CFIE22" caption="Cancellation Finished Interrupt Enable 22" mask="0x400000"/>
+          <bitfield name="CFIE23" caption="Cancellation Finished Interrupt Enable 23" mask="0x800000"/>
+          <bitfield name="CFIE24" caption="Cancellation Finished Interrupt Enable 24" mask="0x1000000"/>
+          <bitfield name="CFIE25" caption="Cancellation Finished Interrupt Enable 25" mask="0x2000000"/>
+          <bitfield name="CFIE26" caption="Cancellation Finished Interrupt Enable 26" mask="0x4000000"/>
+          <bitfield name="CFIE27" caption="Cancellation Finished Interrupt Enable 27" mask="0x8000000"/>
+          <bitfield name="CFIE28" caption="Cancellation Finished Interrupt Enable 28" mask="0x10000000"/>
+          <bitfield name="CFIE29" caption="Cancellation Finished Interrupt Enable 29" mask="0x20000000"/>
+          <bitfield name="CFIE30" caption="Cancellation Finished Interrupt Enable 30" mask="0x40000000"/>
+          <bitfield name="CFIE31" caption="Cancellation Finished Interrupt Enable 31" mask="0x80000000"/>
+        </register>
+        <register name="TXEFC" offset="0x1F0" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Configuration">
+          <bitfield name="EFSA" caption="Event FIFO Start Address" mask="0xFFFC"/>
+          <bitfield name="EFS" caption="Event FIFO Size" mask="0x3F0000"/>
+          <bitfield name="EFWM" caption="Event FIFO Watermark" mask="0x3F000000"/>
+        </register>
+        <register name="TXEFS" offset="0x1F4" rw="R" size="4" initval="0x00000000" caption="Tx Event FIFO Status">
+          <bitfield name="EFFL" caption="Event FIFO Fill Level" mask="0x3F"/>
+          <bitfield name="EFGI" caption="Event FIFO Get Index" mask="0x1F00"/>
+          <bitfield name="EFPI" caption="Event FIFO Put Index" mask="0x1F0000"/>
+          <bitfield name="EFF" caption="Event FIFO Full" mask="0x1000000"/>
+          <bitfield name="TEFL" caption="Tx Event FIFO Element Lost" mask="0x2000000"/>
+        </register>
+        <register name="TXEFA" offset="0x1F8" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Acknowledge">
+          <bitfield name="EFAI" caption="Event FIFO Acknowledge Index" mask="0x1F"/>
+        </register>
+        <register name="CREL_TSU" offset="0x260" rw="R" size="4" initval="0x10000000" caption="TSU CREL">
+          <bitfield name="DAY" caption="Timestamp Day" mask="0xFF"/>
+          <bitfield name="MON" caption="Timestamp Month" mask="0xFF00"/>
+          <bitfield name="YEAR" caption="Timestamp Year" mask="0xF0000"/>
+          <bitfield name="SUBSTEP" caption="Sub-step of Core Release" mask="0xF00000"/>
+          <bitfield name="STEP" caption="Step of Core Release" mask="0xF000000"/>
+          <bitfield name="REL" caption="Core Release" mask="0xF0000000"/>
+        </register>
+        <register name="TSCFG" offset="0x264" rw="RW" size="4" initval="0x00000000" caption="Timestamp Configuration">
+          <bitfield name="TSUE" caption="Timestamp Unit Enable" mask="0x1"/>
+          <bitfield name="TBCS" caption="Timebase Counter Select" mask="0x2"/>
+          <bitfield name="SCP" caption="Select Capturing Position" mask="0x4"/>
+          <bitfield name="TBPRE" caption="Time Base Prescaler" mask="0xFF00"/>
+        </register>
+        <register name="TSS1" offset="0x268" rw="R" size="4" initval="0x00000000" caption="Timestamp Status 1">
+          <bitfield name="TSL" caption="Timestamp Lost" mask="0xFFFF"/>
+          <bitfield name="TSN" caption="Timestamp New" mask="0xFFFF0000"/>
+        </register>
+        <register name="TSS2" offset="0x26C" rw="R" size="4" initval="0x0000A000" caption="Timestamp Status 2">
+          <bitfield name="TSP" caption="Timestamp Pointer" mask="0xF"/>
+          <bitfield name="NTSG" caption="Number of Timestamps Generic" mask="0x3000"/>
+          <bitfield name="ITBG" caption="Internal Timebase and SOF select Generic" mask="0xC000"/>
+        </register>
+        <register name="TS0" offset="0x270" rw="R" size="4" initval="0x00000000" caption="Timestamp 0">
+          <bitfield name="TS" caption="Timestamp Word TS0" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS1" offset="0x274" rw="R" size="4" initval="0x00000000" caption="Timestamp 1">
+          <bitfield name="TS" caption="Timestamp Word TS1" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS2" offset="0x278" rw="R" size="4" initval="0x00000000" caption="Timestamp 2">
+          <bitfield name="TS" caption="Timestamp Word TS2" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS3" offset="0x27C" rw="R" size="4" initval="0x00000000" caption="Timestamp 3">
+          <bitfield name="TS" caption="Timestamp Word TS0" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS4" offset="0x280" rw="R" size="4" initval="0x00000000" caption="Timestamp 4">
+          <bitfield name="TS" caption="Timestamp Word TS4" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS5" offset="0x284" rw="R" size="4" initval="0x00000000" caption="Timestamp 5">
+          <bitfield name="TS" caption="Timestamp Word TS5" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS6" offset="0x288" rw="R" size="4" initval="0x00000000" caption="Timestamp 6">
+          <bitfield name="TS" caption="Timestamp Word TS6" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS7" offset="0x28C" rw="R" size="4" initval="0x00000000" caption="Timestamp 7">
+          <bitfield name="TS" caption="Timestamp Word TS7" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS8" offset="0x290" rw="R" size="4" initval="0x00000000" caption="Timestamp 8">
+          <bitfield name="TS" caption="Timestamp Word TS8" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS9" offset="0x294" rw="R" size="4" initval="0x00000000" caption="Timestamp 9">
+          <bitfield name="TS" caption="Timestamp Word TS9" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS10" offset="0x298" rw="R" size="4" initval="0x00000000" caption="Timestamp 10">
+          <bitfield name="TS" caption="Timestamp Word TS10" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS11" offset="0x29C" rw="R" size="4" initval="0x00000000" caption="Timestamp 11">
+          <bitfield name="TS" caption="Timestamp Word TS11" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS12" offset="0x2A0" rw="R" size="4" initval="0x00000000" caption="Timestamp 12">
+          <bitfield name="TS" caption="Timestamp Word TS12" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS13" offset="0x2A4" rw="R" size="4" initval="0x00000000" caption="Timestamp 13">
+          <bitfield name="TS" caption="Timestamp Word TS13" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS14" offset="0x2A8" rw="R" size="4" initval="0x00000000" caption="Timestamp 14">
+          <bitfield name="TS" caption="Timestamp Word TS14" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS15" offset="0x2AC" rw="R" size="4" initval="0x00000000" caption="Timestamp 15">
+          <bitfield name="TS" caption="Timestamp Word TS15" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="ATB" offset="0x2B0" rw="RW" size="4" atomic-op="clear:ATB" initval="0x00000000" caption="Actual Timebase">
+          <bitfield name="TB" caption="Timebase for timestamp generation" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_RXBE" caption="Control Area Network" aligned="4">
+        <register name="R0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer and FIFO Element 0">
+          <bitfield name="ID" caption="Identifier" mask="0x1FFFFFFF"/>
+          <bitfield name="RTR" caption="Remote Transmission Request" mask="0x20000000"/>
+          <bitfield name="XTD" caption="Extended Identifier" mask="0x40000000"/>
+          <bitfield name="ESI" caption="Error State Indicator" mask="0x80000000"/>
+        </register>
+        <register name="R1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer and FIFO Element 1">
+          <bitfield name="RXTS" caption="Rx Timestamp" mask="0xFFFF"/>
+          <bitfield name="DLC" caption="Data Length Code" mask="0xF0000"/>
+          <bitfield name="BRS" caption="Bit Rate Search" mask="0x100000"/>
+          <bitfield name="FDF" caption="FD Format" mask="0x200000"/>
+          <bitfield name="FIDX" caption="Filter Index" mask="0x7F000000"/>
+          <bitfield name="ANMF" caption="Accepted Non-matching Frame" mask="0x80000000"/>
+        </register>
+        <register name="R2" offset="0x8" rw="RW" size="4" count="16" initval="0x00000000" caption="Rx Buffer and FIFO Element Data">
+          <bitfield name="DB0" caption="Data Byte 0" mask="0xFF"/>
+          <bitfield name="DB1" caption="Data Byte 1" mask="0xFF00"/>
+          <bitfield name="DB2" caption="Data Byte 2" mask="0xFF0000"/>
+          <bitfield name="DB3" caption="Data Byte 3" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_SIDFE" caption="Control Area Network" aligned="4">
+        <register name="S0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Standard Message ID Filter Element">
+          <bitfield name="SFID2" caption="Standard Filter ID 2" mask="0x7FF"/>
+          <bitfield name="SFID1" caption="Standard Filter ID 1" mask="0x7FF0000"/>
+          <bitfield name="SFEC" caption="Standard Filter Element Configuration" mask="0x38000000" values="S0__SFEC"/>
+          <bitfield name="SFT" caption="Standard Filter Type" mask="0xC0000000" values="S0__SFT"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_TXBE" caption="Control Area Network" aligned="4">
+        <register name="T0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Element 0">
+          <bitfield name="ID" caption="Identifier" mask="0x1FFFFFFF"/>
+          <bitfield name="RTR" caption="Remote Transmission Request" mask="0x20000000"/>
+          <bitfield name="XTD" caption="Extended Identifier" mask="0x40000000"/>
+          <bitfield name="ESI" caption="Error State Indicator" mask="0x80000000"/>
+        </register>
+        <register name="T1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Element 1">
+          <bitfield name="MMH" caption="Message Marker Higher Byte" mask="0xFF00"/>
+          <bitfield name="DLC" caption="Identifier" mask="0xF0000"/>
+          <bitfield name="BRS" caption="Bit Rate Search" mask="0x100000"/>
+          <bitfield name="FDF" caption="FD Format" mask="0x200000"/>
+          <bitfield name="TSCE" caption="Time Stamp Capture Enable for TSU" mask="0x400000"/>
+          <bitfield name="EFC" caption="Event FIFO Control" mask="0x800000"/>
+          <bitfield name="MML" caption="Message Marker Lower Byte" mask="0xFF000000"/>
+        </register>
+        <register name="T2" offset="0x8" rw="RW" size="4" count="16" initval="0x00000000" caption="Tx Buffer Element Data">
+          <bitfield name="DB0" caption="Data Byte 0" mask="0xFF"/>
+          <bitfield name="DB1" caption="Data Byte 1" mask="0xFF00"/>
+          <bitfield name="DB2" caption="Data Byte 2" mask="0xFF0000"/>
+          <bitfield name="DB3" caption="Data Byte 3" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_TXEFE" caption="Control Area Network" aligned="4">
+        <register name="E0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Element 0">
+          <bitfield name="ID" caption="Identifier" mask="0x1FFFFFFF"/>
+          <bitfield name="RTR" caption="Remote Transmission Request" mask="0x20000000"/>
+          <bitfield name="XTD" caption="Extended Indentifier" mask="0x40000000"/>
+          <bitfield name="ESI" caption="Error State Indicator" mask="0x80000000"/>
+        </register>
+        <register name="E1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Element 1">
+          <bitfield name="TXTS" caption="Tx Timestamp" mask="0xFFFF"/>
+          <bitfield name="DLC" caption="Data Length Code" mask="0xF0000"/>
+          <bitfield name="BRS" caption="Bit Rate Search" mask="0x100000"/>
+          <bitfield name="FDF" caption="FD Format" mask="0x200000"/>
+          <bitfield name="ET" caption="Event Type" mask="0xC00000" values="E1__ET"/>
+          <bitfield name="MM" caption="Message Marker" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_XIDFE" caption="Control Area Network" aligned="4">
+        <register name="F0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Extended Message ID Filter Element 0">
+          <bitfield name="EFID1" caption="Extended Filter ID 1" mask="0x1FFFFFFF"/>
+          <bitfield name="EFEC" caption="Extended Filter Element Configuration" mask="0xE0000000" values="F0__EFEC"/>
+        </register>
+        <register name="F1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Extended Message ID Filter Element 1">
+          <bitfield name="EFID2" caption="Extended Filter ID 2" mask="0x1FFFFFFF"/>
+          <bitfield name="EFT" caption="Extended Filter Type" mask="0xC0000000" values="F1__EFT"/>
+        </register>
+      </register-group>
+      <value-group name="TEST__TX">
+        <value name="CORE" caption="TX controlled by CAN core" value="0"/>
+        <value name="SAMPLE" caption="TX monitoring sample point" value="1"/>
+        <value name="DOMINANT" caption="Dominant (0) level at pin CAN_TX" value="2"/>
+        <value name="RECESSIVE" caption="Recessive (1) level at pin CAN_TX" value="3"/>
+      </value-group>
+      <value-group name="TSCC__TSS">
+        <value name="ZERO" caption="Timestamp counter value always 0x0000" value="0"/>
+        <value name="INC" caption="Timestamp counter value incremented by TCP" value="1"/>
+        <value name="EXT" caption="External timestamp counter value used" value="2"/>
+      </value-group>
+      <value-group name="TOCC__TOS">
+        <value name="CONT" caption="Continuout operation" value="0"/>
+        <value name="TXEF" caption="Timeout controlled by TX Event FIFO" value="1"/>
+        <value name="RXF0" caption="Timeout controlled by Rx FIFO 0" value="2"/>
+        <value name="RXF1" caption="Timeout controlled by Rx FIFO 1" value="3"/>
+      </value-group>
+      <value-group name="PSR__LEC">
+        <value name="NONE" caption="No Error" value="0"/>
+        <value name="STUFF" caption="Stuff Error" value="1"/>
+        <value name="FORM" caption="Form Error" value="2"/>
+        <value name="ACK" caption="Ack Error" value="3"/>
+        <value name="BIT1" caption="Bit1 Error" value="4"/>
+        <value name="BIT0" caption="Bit0 Error" value="5"/>
+        <value name="CRC" caption="CRC Error" value="6"/>
+        <value name="NC" caption="No Change" value="7"/>
+      </value-group>
+      <value-group name="PSR__ACT">
+        <value name="SYNC" caption="Node is synchronizing on CAN communication" value="0"/>
+        <value name="IDLE" caption="Node is neither receiver nor transmitter" value="1"/>
+        <value name="RX" caption="Node is operating as receiver" value="2"/>
+        <value name="TX" caption="Node is operating as transmitter" value="3"/>
+      </value-group>
+      <value-group name="PSR__DLEC">
+        <value name="NONE" caption="No Error" value="0"/>
+        <value name="STUFF" caption="Stuff Error" value="1"/>
+        <value name="FORM" caption="Form Error" value="2"/>
+        <value name="ACK" caption="Ack Error" value="3"/>
+        <value name="BIT1" caption="Bit1 Error" value="4"/>
+        <value name="BIT0" caption="Bit0 Error" value="5"/>
+        <value name="CRC" caption="CRC Error" value="6"/>
+        <value name="NC" caption="No Change" value="7"/>
+      </value-group>
+      <value-group name="GFC__ANFE">
+        <value name="RXF0" caption="Accept in Rx FIFO 0" value="0"/>
+        <value name="RXF1" caption="Accept in Rx FIFO 1" value="1"/>
+        <value name="REJECT" caption="Reject" value="2"/>
+      </value-group>
+      <value-group name="GFC__ANFS">
+        <value name="RXF0" caption="Accept in Rx FIFO 0" value="0"/>
+        <value name="RXF1" caption="Accept in Rx FIFO 1" value="1"/>
+        <value name="REJECT" caption="Reject" value="2"/>
+      </value-group>
+      <value-group name="HPMS__MSI">
+        <value name="NONE" caption="No FIFO selected" value="0"/>
+        <value name="LOST" caption="FIFO message lost" value="1"/>
+        <value name="FIFO0" caption="Message stored in FIFO 0" value="2"/>
+        <value name="FIFO1" caption="Message stored in FIFO 1" value="3"/>
+      </value-group>
+      <value-group name="RXF1S__DMS">
+        <value name="IDLE" caption="Idle state" value="0"/>
+        <value name="DBGA" caption="Debug message A received" value="1"/>
+        <value name="DBGB" caption="Debug message A/B received" value="2"/>
+        <value name="DBGC" caption="Debug message A/B/C received, DMA request set" value="3"/>
+      </value-group>
+      <value-group name="RXESC__F0DS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="RXESC__F1DS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="RXESC__RBDS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="TXESC__TBDS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="S0__SFEC">
+        <value name="DISABLE" caption="Disable filter element" value="0"/>
+        <value name="STF0M" caption="Store in Rx FIFO 0 if filter match" value="1"/>
+        <value name="STF1M" caption="Store in Rx FIFO 1 if filter match" value="2"/>
+        <value name="REJECT" caption="Reject ID if filter match" value="3"/>
+        <value name="PRIORITY" caption="Set priority if filter match" value="4"/>
+        <value name="PRIF0M" caption="Set priority and store in FIFO 0 if filter match" value="5"/>
+        <value name="PRIF1M" caption="Set priority and store in FIFO 1 if filter match" value="6"/>
+        <value name="STRXBUF" caption="Store into Rx Buffer" value="7"/>
+      </value-group>
+      <value-group name="S0__SFT">
+        <value name="RANGE" caption="Range filter from SFID1 to SFID2" value="0"/>
+        <value name="DUAL" caption="Dual ID filter for SFID1 or SFID2" value="1"/>
+        <value name="CLASSIC" caption="Classic filter" value="2"/>
+      </value-group>
+      <value-group name="E1__ET">
+        <value name="TXE" caption="Tx event" value="1"/>
+        <value name="TXC" caption="Transmission in spite of cancellation" value="2"/>
+      </value-group>
+      <value-group name="F0__EFEC">
+        <value name="DISABLE" caption="Disable filter element" value="0"/>
+        <value name="STF0M" caption="Store in Rx FIFO 0 if filter match" value="1"/>
+        <value name="STF1M" caption="Store in Rx FIFO 1 if filter match" value="2"/>
+        <value name="REJECT" caption="Reject ID if filter match" value="3"/>
+        <value name="PRIORITY" caption="Set priority if filter match" value="4"/>
+        <value name="PRIF0M" caption="Set priority and store in FIFO 0 if filter match" value="5"/>
+        <value name="PRIF1M" caption="Set priority and store in FIFO 1 if filter match" value="6"/>
+        <value name="STRXBUF" caption="Store into Rx Buffer" value="7"/>
+      </value-group>
+      <value-group name="F1__EFT">
+        <value name="RANGEM" caption="Range filter from EFID1 to EFID2" value="0"/>
+        <value name="DUAL" caption="Dual ID filter for EFID1 or EFID2" value="1"/>
+        <value name="CLASSIC" caption="Classic filter" value="2"/>
+        <value name="RANGE" caption="Range filter from EFID1 to EFID2 with no XIDAM mask" value="3"/>
+      </value-group>
+    </module>
+    <module name="CCL" id="03628" name2="cla_ccl_u2225_v2" version="2b0" caption="Configurable Custom Logic">
+      <register-group name="CCL" caption="Configurable Custom Logic">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1" values="CTRL__SWRST"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2" values="CTRL__ENABLE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40" values="CTRL__RUNSTDBY"/>
+        </register>
+        <register name="SEQCTRL" offset="0x4" rw="RW" size="1" count="2" initval="0x00" caption="SEQ Control x">
+          <bitfield name="SEQSEL" caption="Sequential Selection" mask="0xF" values="SEQCTRL__SEQSEL"/>
+        </register>
+        <register name="LUTCTRL" offset="0x8" rw="RW" size="4" count="4" initval="0x00000000" caption="LUT Control x">
+          <bitfield name="ENABLE" caption="LUT Enable" mask="0x2" values="LUTCTRL__ENABLE"/>
+          <bitfield name="FILTSEL" caption="Filter Selection" mask="0x30" values="LUTCTRL__FILTSEL"/>
+          <bitfield name="EDGESEL" caption="Edge Selection" mask="0x80" values="LUTCTRL__EDGESEL"/>
+          <bitfield name="INSEL0" caption="Input Selection 0" mask="0xF00" values="LUTCTRL__INSEL0"/>
+          <bitfield name="INSEL1" caption="Input Selection 1" mask="0xF000" values="LUTCTRL__INSEL1"/>
+          <bitfield name="INSEL2" caption="Input Selection 2" mask="0xF0000" values="LUTCTRL__INSEL2"/>
+          <bitfield name="INVEI" caption="Inverted Event Input Enable" mask="0x100000" values="LUTCTRL__INVEI"/>
+          <bitfield name="LUTEI" caption="LUT Event Input Enable" mask="0x200000" values="LUTCTRL__LUTEI"/>
+          <bitfield name="LUTEO" caption="LUT Event Output Enable" mask="0x400000" values="LUTCTRL__LUTEO"/>
+          <bitfield name="TRUTH" caption="Truth Value" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <value-group name="CTRL__SWRST">
+        <value name="DISABLE" caption="The peripheral is not reset" value="0"/>
+        <value name="ENABLE" caption="The peripheral is reset" value="1"/>
+      </value-group>
+      <value-group name="CTRL__ENABLE">
+        <value name="DISABLE" caption="The peripheral is disabled" value="0"/>
+        <value name="ENABLE" caption="The peripheral is enabled" value="1"/>
+      </value-group>
+      <value-group name="CTRL__RUNSTDBY">
+        <value name="DISABLE" caption="Generic clock is not required in standby sleep mode" value="0"/>
+        <value name="ENABLE" caption="Generic clock is  required in standby sleep mode" value="1"/>
+      </value-group>
+      <value-group name="SEQCTRL__SEQSEL">
+        <value name="DISABLE" caption="Sequential logic is disabled" value="0"/>
+        <value name="DFF" caption="D flip flop" value="1"/>
+        <value name="JK" caption="JK flip flop" value="2"/>
+        <value name="LATCH" caption="D latch" value="3"/>
+        <value name="RS" caption="RS latch" value="4"/>
+      </value-group>
+      <value-group name="LUTCTRL__ENABLE">
+        <value name="DISABLE" caption="LUT block is disabled" value="0"/>
+        <value name="ENABLE" caption="LUT block is enabled" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__FILTSEL">
+        <value name="DISABLE" caption="Filter disabled" value="0"/>
+        <value name="SYNCH" caption="Synchronizer enabled" value="1"/>
+        <value name="FILTER" caption="Filter enabled" value="2"/>
+      </value-group>
+      <value-group name="LUTCTRL__EDGESEL">
+        <value name="DISABLE" caption="Edge detector is disabled" value="0"/>
+        <value name="ENABLE" caption="Edge detector is enabled" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__INSEL0">
+        <value name="MASK" caption="Masked input" value="0x0"/>
+        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
+        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
+        <value name="EVENT" caption="Event input source" value="0x3"/>
+        <value name="IO" caption="I/O pin input source" value="0x4"/>
+        <value name="PERSEL0" caption="Peripheral 0 input source" value="0x5"/>
+        <value name="PERSEL1" caption="Peripheral 1 input source" value="0x6"/>
+        <value name="PERSEL2" caption="Peripheral 2 input source" value="0x7"/>
+        <value name="PERSEL3" caption="Peripheral 3 input source" value="0x8"/>
+        <value name="PERSEL4" caption="Peripheral 4 input source" value="0x9"/>
+        <value name="PERSEL5" caption="Peripheral 5 input source" value="0xA"/>
+        <value name="ASYNCEVENT" caption="Asynchronous event input source. The EVENT input will bypass edge detection logic." value="0xB"/>
+      </value-group>
+      <value-group name="LUTCTRL__INSEL1">
+        <value name="MASK" caption="Masked input" value="0x0"/>
+        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
+        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
+        <value name="EVENT" caption="Event input source" value="0x3"/>
+        <value name="IO" caption="I/O pin input source" value="0x4"/>
+        <value name="PERSEL0" caption="Peripheral 0 input source" value="0x5"/>
+        <value name="PERSEL1" caption="Peripheral 1 input source" value="0x6"/>
+        <value name="PERSEL2" caption="Peripheral 2 input source" value="0x7"/>
+        <value name="PERSEL3" caption="Peripheral 3 input source" value="0x8"/>
+        <value name="PERSEL4" caption="Peripheral 4 input source" value="0x9"/>
+        <value name="PERSEL5" caption="Peripheral 5 input source" value="0xA"/>
+        <value name="ASYNCEVENT" caption="Asynchronous event input source. The EVENT input will bypass edge detection logic." value="0xB"/>
+      </value-group>
+      <value-group name="LUTCTRL__INSEL2">
+        <value name="MASK" caption="Masked input" value="0x0"/>
+        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
+        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
+        <value name="EVENT" caption="Event input source" value="0x3"/>
+        <value name="IO" caption="I/O pin input source" value="0x4"/>
+        <value name="PERSEL0" caption="Peripheral 0 input source" value="0x5"/>
+        <value name="PERSEL1" caption="Peripheral 1 input source" value="0x6"/>
+        <value name="PERSEL2" caption="Peripheral 2 input source" value="0x7"/>
+        <value name="PERSEL3" caption="Peripheral 3 input source" value="0x8"/>
+        <value name="PERSEL4" caption="Peripheral 4 input source" value="0x9"/>
+        <value name="PERSEL5" caption="Peripheral 5 input source" value="0xA"/>
+        <value name="ASYNCEVENT" caption="Asynchronous event input source. The EVENT input will bypass edge detection logic." value="0xB"/>
+      </value-group>
+      <value-group name="LUTCTRL__INVEI">
+        <value name="NORMAL" caption="Incoming event is not inverted" value="0"/>
+        <value name="INVERTED" caption="Incoming event is inverted" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__LUTEI">
+        <value name="DISABLE" caption="LUT incoming event is disabled" value="0"/>
+        <value name="ENABLE" caption="LUT incoming event is enabled" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__LUTEO">
+        <value name="DISABLE" caption="LUT event output is disabled" value="0"/>
+        <value name="ENABLE" caption="LUT event output is enabled" value="1"/>
+      </value-group>
+    </module>
+    <module name="CoreDebug" id="SYSTEM_IP" version="1.0.0" caption="Debug Control Block">
+      <register-group name="CoreDebug" caption="Debug Control Block">
+        <register name="DHCSR" offset="0x0" rw="RW" size="4" access-size="4" caption="Debug Halting Control and Status Register">
+          <bitfield name="C_DEBUGEN" caption="Enable Halting debug" mask="0x1"/>
+          <bitfield name="C_HALT" caption="Halt processor" mask="0x2"/>
+          <bitfield name="C_STEP" caption="Enable single step" mask="0x4"/>
+          <bitfield name="C_MASKINTS" caption="Mask PendSV, SysTick and external configurable interrupts" mask="0x8"/>
+          <bitfield name="S_SNAPSTALL" caption="Snap stall control" mask="0x20"/>
+          <bitfield name="S_REGRDY" caption="Register ready status" mask="0x10000"/>
+          <bitfield name="S_HALT" caption="Halted status" mask="0x20000"/>
+          <bitfield name="S_SLEEP" caption="Sleeping status" mask="0x40000"/>
+          <bitfield name="S_LOCKUP" caption="Lockup status" mask="0x80000"/>
+          <bitfield name="S_SDE" caption="Secure debug enabled" mask="0x100000"/>
+          <bitfield name="S_RETIRE_ST" caption="Retire sticky status" mask="0x1000000"/>
+          <bitfield name="S_RESET_ST" caption="Reset sticky status" mask="0x2000000"/>
+          <bitfield name="S_RESTART_ST" caption="Restart sticky status" mask="0x4000000"/>
+        </register>
+        <register name="DCRSR" offset="0x4" rw="W" size="4" access-size="4" caption="Debug Core Register Select Register">
+          <bitfield name="REGSEL" caption="Register selector" mask="0x7F"/>
+          <bitfield name="REGWnR" caption="Register write/not-read access" mask="0x10000"/>
+        </register>
+        <register name="DEMCR" offset="0xC" rw="RW" size="4" access-size="4" caption="Debug Exception and Monitor Control Register">
+          <bitfield name="VC_CORERESET" caption="Core reset Halting debug vector catch enable" mask="0x1"/>
+          <bitfield name="VC_MMERR" caption="MemManage exception Halting debug vector catch enable" mask="0x10"/>
+          <bitfield name="VC_NOCPERR" caption="UsageFault exception coprocessor access Halting debug vector catch enable" mask="0x20"/>
+          <bitfield name="VC_CHKERR" caption="UsageFault exception checking error Halting debug vector catch enable" mask="0x40"/>
+          <bitfield name="VC_STATERR" caption="UsageFault exception state information error Halting debug vector catch enable" mask="0x80"/>
+          <bitfield name="VC_BUSERR" caption="BusFault exception Halting debug vector catch enable" mask="0x100"/>
+          <bitfield name="VC_INTERR" caption="Excception entry and return faults Halting debug vector catch enable" mask="0x200"/>
+          <bitfield name="VC_HARDERR" caption="HardFault exception Halting debug vector catch enable" mask="0x400"/>
+          <bitfield name="VC_SFERR" caption="SecureFault exception Halting debug vector catch enable" mask="0x800"/>
+          <bitfield name="MON_EN" caption="DebugMonitor enable" mask="0x10000"/>
+          <bitfield name="MON_PEND" caption="DebugMonitor pending state" mask="0x20000"/>
+          <bitfield name="MON_STEP" caption="Enable DebugMonitor stepping" mask="0x40000"/>
+          <bitfield name="MON_REQ" caption="DebugMonitor semaphore bit" mask="0x80000"/>
+          <bitfield name="SDME" caption="Secure DebugMonitor enable" mask="0x100000"/>
+          <bitfield name="TRCENA" caption="Global DWT and ITM features enable" mask="0x1000000"/>
+        </register>
+        <register name="DSCSR" offset="0x18" rw="RW" size="4" access-size="4" caption="Debug Security Control and Status Register">
+          <bitfield name="SBRSELEN" caption="Secure Banked register select enable" mask="0x1"/>
+          <bitfield name="SBRSEL" caption="Secure Banked register select" mask="0x2"/>
+          <bitfield name="CDS" caption="Current domain Secure" mask="0x10000"/>
+          <bitfield name="CDSKEY" caption="CDS field write-enable key" mask="0x20000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="DIB" id="SYSTEM_IP" version="1.0.0" caption="Debug Identification Block">
+      <register-group name="DIB" caption="Debug Identification Block">
+        <register name="DLAR" offset="0x0" rw="W" size="4" access-size="4" caption="SCS Software Lock Access Register">
+          <bitfield name="KEY" caption="Lock access control" mask="0xFFFFFFFF" values="DLAR__KEY"/>
+        </register>
+        <register name="DLSR" offset="0x4" rw="R" size="4" access-size="4" caption="SCS Software Lock Status Register">
+          <bitfield name="SLI" caption="Software Lock implemented" mask="0x1"/>
+          <bitfield name="SLK" caption="Software Lock status" mask="0x2"/>
+          <bitfield name="nTT" caption="Not thirty-two bit" mask="0x4"/>
+        </register>
+        <register name="DAUTHSTATUS" offset="0x8" rw="R" size="4" access-size="4" caption="Debug Authentication Status Register">
+          <bitfield name="NSID" caption="" mask="0x3" values="DAUTHSTATUS__NSID"/>
+          <bitfield name="NSNID" caption="" mask="0xC" values="DAUTHSTATUS__NSNID"/>
+          <bitfield name="SID" caption="" mask="0x30" values="DAUTHSTATUS__SID"/>
+          <bitfield name="SNID" caption="" mask="0xC0" values="DAUTHSTATUS__SNID"/>
+        </register>
+        <register name="DDEVARCH" offset="0xC" rw="R" size="4" access-size="4" initval="0x47702A04" caption="SCS Device Architecture Register">
+          <bitfield name="ARCHPART" caption="Architecture Part" mask="0xFFF"/>
+          <bitfield name="ARCHVER" caption="Architecture Version" mask="0xF000"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF0000"/>
+          <bitfield name="PRESENT" caption="DEVARCH Present" mask="0x100000"/>
+          <bitfield name="ARCHITECT" caption="Architect" mask="0xFFE00000"/>
+        </register>
+        <register name="DDEVTYPE" offset="0x1C" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Device Type Register">
+          <bitfield name="MAJOR" caption="Major type" mask="0xF"/>
+          <bitfield name="SUB" caption="Sub-type" mask="0xF0"/>
+        </register>
+        <register name="DPIDR4" offset="0x20" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 4">
+          <bitfield name="DES_2" caption="JEP106 continuation code" mask="0xF"/>
+          <bitfield name="SIZE" caption="4KB count" mask="0xF0"/>
+        </register>
+        <register name="DPIDR5" offset="0x24" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Peripheral Identification Register 5"/>
+        <register name="DPIDR6" offset="0x28" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Peripheral Identification Register 6"/>
+        <register name="DPIDR7" offset="0x2C" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Peripheral Identification Register 7"/>
+        <register name="DPIDR0" offset="0x30" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 0">
+          <bitfield name="PART_0" caption="Part number bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="DPIDR1" offset="0x34" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 1">
+          <bitfield name="PART_1" caption="Part number bits[11:8]" mask="0xF"/>
+          <bitfield name="DES_0" caption="JEP106 identification code bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="DPIDR2" offset="0x38" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 2">
+          <bitfield name="DES_1" caption="JEP106 identification code bits[6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="JEDEC assignee value is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Component revision" mask="0xF0"/>
+        </register>
+        <register name="DPIDR3" offset="0x3C" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 3">
+          <bitfield name="CMOD" caption="Customer Modified" mask="0xF"/>
+          <bitfield name="REVAND" caption="RevAnd" mask="0xF0"/>
+        </register>
+        <register name="DCIDR0" offset="0x40" rw="R" size="4" access-size="4" initval="0x0000000D" caption="SCS Component Identification Register 0">
+          <bitfield name="PRMBL_0" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DCIDR1" offset="0x44" rw="R" size="4" access-size="4" initval="0x00000090" caption="SCS Component Identification Register 1">
+          <bitfield name="PRMBL_1" caption="CoreSight component identification preamble" mask="0xF"/>
+          <bitfield name="CLASS" caption="CoreSight component class" mask="0xF0"/>
+        </register>
+        <register name="DCIDR2" offset="0x48" rw="R" size="4" access-size="4" initval="0x00000005" caption="SCS Component Identification Register 2">
+          <bitfield name="PRMBL_2" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DCIDR3" offset="0x4C" rw="R" size="4" access-size="4" initval="0x000000B1" caption="SCS Component Identification Register 3">
+          <bitfield name="PRMBL_3" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="DLAR__KEY">
+        <value name="UNLOCK" caption="Unlock key value" value="0xC5ACCE55"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__NSID">
+        <value name="NO" caption="Non-secure invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Non-secure invasive debug allowed" value="3"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__NSNID">
+        <value name="NO" caption="Non-secure non-invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Non-secure non-invasive debug allowed" value="3"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__SID">
+        <value name="NOSEC" caption="Security Extension not implemented" value="0"/>
+        <value name="NO" caption="Secure invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Secure invasive debug allowed" value="3"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__SNID">
+        <value name="NOSEC" caption="Security Extension not implemented" value="0"/>
+        <value name="NO" caption="Secure non-invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Secure non-invasive debug allowed" value="3"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="dma_u2223_v2" name2="dma_u2223_v2" version="2i0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x2A" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0x7"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0x700"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0x70000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0x7000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0x7"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0x7"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Channel run in standby" mask="0x40"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+      <value-group name="CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (BEATSIZE+1) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (BEATSIZE+1) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (BEATSIZE+1) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (BEATSIZE+1) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (BEATSIZE+1) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (BEATSIZE+1) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (BEATSIZE+1) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (BEATSIZE+1) * 128" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="04465" name2="icd_dsu_v1" version="1a0" caption="Polaris Device Services Unit Macro DOS">
+      <register-group name="DSU" caption="Polaris Device Services Unit Macro DOS">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A REGISTER">
+          <bitfield name="PRIV" caption="Privileged Access Only for APB Interface" mask="0x4" values="CTRLA__PRIV"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B REGISTER">
+          <bitfield name="DCCDMALVL0" caption="DMA Trigger n Level" mask="0x1" values="CTRLB__DCCDMALVL"/>
+          <bitfield name="DCCDMALVL1" caption="DMA Trigger n Level" mask="0x2" values="CTRLB__DCCDMALVL"/>
+          <bitfield name="MISC" caption="Device Specific Configuration Register" mask="0xFFFFFF00"/>
+        </register>
+        <register name="CTRLC" offset="0x100" rw="RW" size="4" initval="0x00000000" caption="Control C REGISTER">
+          <bitfield name="DBGRW0" caption="CPUn Debug R/W" mask="0x1" values="CTRLC__DBGRW"/>
+        </register>
+        <register name="STATUSA" offset="0x104" rw="RW" size="4" atomic-op="clear:STATUSA" initval="0x00000000" caption="Status A REGISTER">
+          <bitfield name="DONE" caption="Done Status" mask="0x1" values="STATUSA__DONE"/>
+          <bitfield name="BERR" caption="Bus Error Status" mask="0x4" values="STATUSA__BERR"/>
+          <bitfield name="PERR" caption="Protection Error Status" mask="0x8" values="STATUSA__PERR"/>
+          <bitfield name="ROMCRC" caption="Boot ROM CRC Self-Check Status" mask="0xC0" values="STATUSA__ROMCRC"/>
+          <bitfield name="CRSTEXT0" caption="CPUx Reset Extension Status" mask="0x100" values="STATUSA__CRSTEXT"/>
+          <bitfield name="BREXT0" caption="BootRom 0 Phase Extension Status" mask="0x10000" values="STATUSA__BREXT"/>
+        </register>
+        <register name="STATUSB" offset="0x108" rw="R" size="4" initval="0x00000000" caption="Status B REGISTER">
+          <bitfield name="BCCD0" caption="Boot ROM Communication Channel 0 Dirty" mask="0x1" values="STATUSB__BCCD"/>
+          <bitfield name="BCCD1" caption="Boot ROM Communication Channel 1 Dirty" mask="0x2" values="STATUSB__BCCD"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4" values="STATUSB__DCCD"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8" values="STATUSB__DCCD"/>
+          <bitfield name="DBGPRES" caption="Debugger Present Status" mask="0x100" values="STATUSB__DBGPRES"/>
+          <bitfield name="HPS" caption="Hot-Plugging Status" mask="0x400" values="STATUSB__HPS"/>
+        </register>
+        <register name="BCC" offset="0x110" rw="RW" size="4" count="2" initval="0x00000000" caption="Boot ROM Channel n REGISTER">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x118" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n REGISTER">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x120" rw="RW" size="4" initval="0x00000053" caption="Device Identification Register">
+          <bitfield name="FV" caption="Fixed Value of 1" mask="0x1"/>
+          <bitfield name="MANID" caption="JEDEC Manufacture ID" mask="0xFFE"/>
+          <bitfield name="PNDID" caption="Part Number Device ID" mask="0xFF000"/>
+          <bitfield name="PNMID" caption="Part Number Mask ID" mask="0xFF00000"/>
+          <bitfield name="VER" caption="Version Code" mask="0xF0000000"/>
+        </register>
+        <register name="DAL" offset="0x124" rw="R" size="4" initval="0x00000000" caption="Debugger Access Level REGISTER">
+          <bitfield name="CPU0" caption="CPU 0 Debugger Access Level" mask="0x3" values="DAL__CPU0"/>
+          <bitfield name="CPU1" caption="CPU n Debugger Access Level" mask="0xC" values="DAL__CPU"/>
+          <bitfield name="CPU2" caption="CPU n Debugger Access Level" mask="0x30" values="DAL__CPU"/>
+          <bitfield name="CPU3" caption="CPU n Debugger Access Level" mask="0xC0" values="DAL__CPU"/>
+        </register>
+        <register name="ENTRY0" offset="0x1000" rw="R" size="4" initval="0x9C0FE002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY0__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY0__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY1" offset="0x1004" rw="R" size="4" initval="0xBBFFF002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY1__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY1__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY2" offset="0x1008" rw="R" size="4" initval="0xBBFFF002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY2__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY2__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY3" offset="0x100C" rw="R" size="4" initval="0xBBFFF002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY3__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY3__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY4" offset="0x1010" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 4 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY4__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY4__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY5" offset="0x1014" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 5 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY5__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY5__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY6" offset="0x1018" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 6 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY6__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY6__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY7" offset="0x101C" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 7 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY7__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY7__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Memory Type Register">
+          <bitfield name="SYSMEM" caption="CoreSight System Memory Present" mask="0x1" values="MEMTYPE__SYSMEM"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 4 Register">
+          <bitfield name="DES2" caption="CoreSight JEP106 Continuation Code" mask="0xF"/>
+          <bitfield name="SIZE" caption="CoreSight Size" mask="0xF0"/>
+        </register>
+        <register name="PID5" offset="0x1FD4" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 5 Register">
+          <bitfield name="RES0" caption="CoreSight Reserved Field" mask="0xFF"/>
+        </register>
+        <register name="PID6" offset="0x1FD8" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 6 Register">
+          <bitfield name="RES0" caption="CoreSight Reserved Field" mask="0xFF"/>
+        </register>
+        <register name="PID7" offset="0x1FDC" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 7 Register">
+          <bitfield name="RES0" caption="CoreSight Reserved Field" mask="0xFF"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="CoreSight Peripheral Identification 0 Register">
+          <bitfield name="PART0" caption="CoreSight Part Number Bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x0000009C" caption="CoreSight Peripheral Identification 1 Register">
+          <bitfield name="PART1" caption="CoreSight Part Number Bits[11:8]" mask="0xF"/>
+          <bitfield name="DES0" caption="CoreSight JEP106 Identification Code Bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x0000000A" caption="CoreSight Peripheral Identification 2 Register">
+          <bitfield name="DES1" caption="CoreSight JEP106 Identification Code Bits [6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="CoreSight JEDEC Assignment" mask="0x8"/>
+          <bitfield name="REVISION" caption="CoreSight Revision" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 3 Register">
+          <bitfield name="CMOD" caption="CoreSight Custom Modifier 0" mask="0xF"/>
+          <bitfield name="REVAND" caption="CoreSight REVAND" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="CoreSight Component Identification 0 Register">
+          <bitfield name="PRMBL0" caption="CoreSight Preamble 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="CoreSight Component Identification 1 Register">
+          <bitfield name="PRMBL1" caption="CoreSight Preamble 1" mask="0xF"/>
+          <bitfield name="CCLASS" caption="CoreSight Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="CoreSight Component Identification 2 Register">
+          <bitfield name="PRMBL2" caption="CoreSight Preamble 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="CoreSight Component Identification 3 Register">
+          <bitfield name="PRMBL3" caption="CoreSight Preamble 3" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="0" caption="Internal Address Space registers accessible in privileged and unprivileged modes. Test functions generate unprivileged requests." value="0"/>
+        <value name="1" caption="Internal Address Space registers only accessible in privileged mode. Test functions generate privileged requests." value="1"/>
+      </value-group>
+      <value-group name="CTRLB__DCCDMALVL">
+        <value name="EMPTY" caption="Trigger n rises when DCCn is read and falls when it is written" value="0"/>
+        <value name="FULL" caption="Trigger n rises when DCCn is written and falls when it is read" value="1"/>
+      </value-group>
+      <value-group name="CTRLC__DBGRW">
+        <value name="0" caption="Allow debugger accesses through CPUn to carry the debug attribute (i.e debugger reads are non-destructive)." value="0"/>
+        <value name="1" caption="Debugger accesses through CPUn do not carry the debug attribute (i.e debugger reads are destructive)." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__DONE">
+        <value name="0" caption="DSU is executing a command or idle." value="0"/>
+        <value name="1" caption="TCTRL.CMD command completed" value="1"/>
+      </value-group>
+      <value-group name="STATUSA__BERR">
+        <value name="0" caption="No bus error detected" value="0"/>
+        <value name="1" caption="Bus error incurred while performing the DSU command." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__PERR">
+        <value name="0" caption="No protection error detected" value="0"/>
+        <value name="1" caption="Invalid command written to TCTRL.CMD, partial write to the upper or lower bytes of TCTRL.CMD, or invalid key written to SAFEDOOR." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__ROMCRC">
+        <value name="0" caption="CRC is in progress" value="0"/>
+        <value name="1" caption="CRC completed but failed indicating possible issue with the ROM content. System held in lockup state." value="1"/>
+        <value name="2" caption="CRC completed and passed" value="2"/>
+        <value name="3" caption="CRC never executed because user disabled CRC check through fuse settings." value="3"/>
+      </value-group>
+      <value-group name="STATUSA__CRSTEXT">
+        <value name="0" caption="CPUx released from reset extension." value="0"/>
+        <value name="1" caption="CPUx held in reset extension. Set on Cold-Plugging detection." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__BREXT">
+        <value name="0" caption="Boot ROM Phase Extension released for CPUx." value="0"/>
+        <value name="1" caption="Boot ROM Phase Extension for CPUx. Set on Cold-Plugging detection." value="1"/>
+      </value-group>
+      <value-group name="STATUSB__BCCD">
+        <value name="0" caption="BCCDx.DATA register was read from." value="0"/>
+        <value name="1" caption="BCCDx.DATA register was written to." value="1"/>
+      </value-group>
+      <value-group name="STATUSB__DCCD">
+        <value name="0" caption="DCCDx.DATA register was read from." value="0"/>
+        <value name="1" caption="DCCDx.DATA register was written to." value="1"/>
+      </value-group>
+      <value-group name="STATUSB__DBGPRES">
+        <value name="0" caption="No debugger detected" value="0"/>
+        <value name="1" caption="Debugger probe detected" value="1"/>
+      </value-group>
+      <value-group name="STATUSB__HPS">
+        <value name="0" caption="Hot-Plugging inactive" value="0"/>
+        <value name="1" caption="Hot-Plugging active" value="1"/>
+      </value-group>
+      <value-group name="DAL__CPU0">
+        <value name="SECURED" caption="Debugger targeting CPU0 domain can only access the DSU external address space otherwise debugger access is disabled" value="0"/>
+        <value name="NS_DEBUG" caption="Debugger can access only non-secure regions" value="1"/>
+        <value name="FULL_DEBUG" caption="Debugger can access secure and non-secure regions" value="2"/>
+      </value-group>
+      <value-group name="DAL__CPU">
+        <value name="SECURED" caption="Debugger access is disabled" value="0"/>
+        <value name="NS_DEBUG" caption="Debugger can access only non-secure regions" value="1"/>
+        <value name="FULL_DEBUG" caption="Debugger has full access to debug CPUn" value="2"/>
+        <value name="UNIMPLEMENTED" caption="Unimplemented CPU" value="3"/>
+      </value-group>
+      <value-group name="ENTRY0__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY0__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY1__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY1__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY2__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY2__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY3__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY3__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY4__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY4__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY5__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY5__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY6__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY6__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY7__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY7__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="MEMTYPE__SYSMEM">
+        <value name="0" caption="System memory not present on bus. This is a dedicated debug bus." value="0"/>
+        <value name="1" caption="System memory is also present on this bus" value="1"/>
+      </value-group>
+    </module>
+    <module name="DWT" id="SYSTEM_IP" version="1.0.0" caption="Data Watchpoint and Trace">
+      <register-group name="COMPARATOR" size="0x10">
+        <register name="DWT_COMP" offset="0x0" rw="RW" size="4" access-size="4" caption="DWT Comparator Register n">
+          <bitfield name="VALUE" caption="Cycle/PC/data value or data address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DWT_FUNCTION" offset="0x8" rw="RW" size="4" access-size="4" caption="DWT Function Register x">
+          <bitfield name="MATCH" caption="Match type" mask="0xF"/>
+          <bitfield name="ACTION" caption="Action on match" mask="0x30"/>
+          <bitfield name="DATAVSIZE" caption="Data value size" mask="0xC00"/>
+          <bitfield name="MATCHED" caption="Comparator matched" mask="0x1000000"/>
+          <bitfield name="ID" caption="Identify capability" mask="0xF8000000"/>
+        </register>
+      </register-group>
+      <register-group name="DWT" caption="Data Watchpoint and Trace">
+        <register name="DWT_CTRL" offset="0x0" rw="RW" size="4" access-size="4" initval="0x0B000000" caption="DWT Control Register">
+          <bitfield name="CYCCNTENA" caption="CYCCNT enable" mask="0x1"/>
+          <bitfield name="POSTPRESET" caption="POSTCNT preset" mask="0x1E"/>
+          <bitfield name="POSTINIT" caption="POSTCNT initial" mask="0x1E0"/>
+          <bitfield name="CYCTAP" caption="Cycle count tap" mask="0x200"/>
+          <bitfield name="SYNCTAP" caption="Synchronization tap" mask="0xC00"/>
+          <bitfield name="PCSAMPLENA" caption="PC sample enable" mask="0x1000"/>
+          <bitfield name="EXCTRCENA" caption="Exception trace enable" mask="0x10000"/>
+          <bitfield name="CPIEVTENA" caption="CPI event enable" mask="0x20000"/>
+          <bitfield name="EXCEVTENA" caption="Exception event enable" mask="0x40000"/>
+          <bitfield name="SLEEPEVTENA" caption="Sleep event enable" mask="0x80000"/>
+          <bitfield name="LSUEVTENA" caption="LSU event enable" mask="0x100000"/>
+          <bitfield name="FOLDEVTENA" caption="Fold event enable" mask="0x200000"/>
+          <bitfield name="CYCEVTENA" caption="Cycle event enable" mask="0x400000"/>
+          <bitfield name="CYCDISS" caption="Cycle counter disabled secure" mask="0x800000"/>
+          <bitfield name="NOPRFCNT" caption="No profile counters" mask="0x1000000"/>
+          <bitfield name="NOCYCCNT" caption="No cycle count" mask="0x2000000"/>
+          <bitfield name="NOEXTTRIG" caption="No external triggers" mask="0x4000000"/>
+          <bitfield name="NOTRCPKT" caption="No trace packets" mask="0x8000000"/>
+          <bitfield name="NUMCOMP" caption="Number of comparators" mask="0xF0000000"/>
+        </register>
+        <register name="DWT_PCSR" offset="0x1C" rw="R" size="4" access-size="4" caption="DWT Program Counter Sample Register">
+          <bitfield name="EIASAMPLE" caption="Executed instruction address sample" mask="0xFFFFFFFF"/>
+        </register>
+        <register-group name="COMPARATOR" name-in-module="COMPARATOR" offset="0x020" size="0x10" count="2"/>
+        <register name="DWT_LAR" offset="0xFB0" rw="W" size="4" access-size="4" caption="DWT Software Lock Access Register">
+          <bitfield name="KEY" caption="Lock access control" mask="0xFFFFFFFF" values="DWT_LAR__KEY"/>
+        </register>
+        <register name="DWT_LSR" offset="0xFB4" rw="R" size="4" access-size="4" caption="DWT Software Lock Status Register">
+          <bitfield name="SLI" caption="Software Lock implemented" mask="0x1"/>
+          <bitfield name="SLK" caption="Software Lock status" mask="0x2"/>
+          <bitfield name="nTT" caption="Not thirty-two bit" mask="0x4"/>
+        </register>
+        <register name="DWT_DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" initval="0x47701A02" caption="DWT Device Architecture Register">
+          <bitfield name="ARCHPART" caption="Architecture Part" mask="0xFFF"/>
+          <bitfield name="ARCHVER" caption="Architecture Version" mask="0xF000"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF0000"/>
+          <bitfield name="PRESENT" caption="DEVARCH Present" mask="0x100000"/>
+          <bitfield name="ARCHITECT" caption="Architect" mask="0xFFE00000"/>
+        </register>
+        <register name="DWT_DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Device Type Register">
+          <bitfield name="MAJOR" caption="Major type" mask="0xF"/>
+          <bitfield name="SUB" caption="Sub-type" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR4" offset="0xFD0" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 4">
+          <bitfield name="DES_2" caption="JEP106 continuation code" mask="0xF"/>
+          <bitfield name="SIZE" caption="4KB count" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR5" offset="0xFD4" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Peripheral Identification Register 5"/>
+        <register name="DWT_PIDR6" offset="0xFD8" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Peripheral Identification Register 6"/>
+        <register name="DWT_PIDR7" offset="0xFDC" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Peripheral Identification Register 7"/>
+        <register name="DWT_PIDR0" offset="0xFE0" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 0">
+          <bitfield name="PART_0" caption="Part number bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="DWT_PIDR1" offset="0xFE4" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 1">
+          <bitfield name="PART_1" caption="Part number bits[11:8]" mask="0xF"/>
+          <bitfield name="DES_0" caption="JEP106 identification code bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR2" offset="0xFE8" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 2">
+          <bitfield name="DES_1" caption="JEP106 identification code bits[6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="JEDEC assignee value is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Component revision" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR3" offset="0xFEC" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 3">
+          <bitfield name="CMOD" caption="Customer Modified" mask="0xF"/>
+          <bitfield name="REVAND" caption="RevAnd" mask="0xF0"/>
+        </register>
+        <register name="DWT_CIDR0" offset="0xFF0" rw="R" size="4" access-size="4" initval="0x0000000D" caption="DWT Component Identification Register 0">
+          <bitfield name="PRMBL_0" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DWT_CIDR1" offset="0xFF4" rw="R" size="4" access-size="4" initval="0x00000090" caption="DWT Component Identification Register 1">
+          <bitfield name="PRMBL_1" caption="CoreSight component identification preamble" mask="0xF"/>
+          <bitfield name="CLASS" caption="CoreSight component class" mask="0xF0"/>
+        </register>
+        <register name="DWT_CIDR2" offset="0xFF8" rw="R" size="4" access-size="4" initval="0x00000005" caption="DWT Component Identification Register 2">
+          <bitfield name="PRMBL_2" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DWT_CIDR3" offset="0xFFC" rw="R" size="4" access-size="4" initval="0x000000B1" caption="DWT Component Identification Register 3">
+          <bitfield name="PRMBL_3" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="DWT_LAR__KEY">
+        <value name="UNLOCK" caption="Unlock key value" value="0xC5ACCE55"/>
+      </value-group>
+    </module>
+    <module name="EIC" id="03706" name2="int_eic_u2804_v1" version="1b0" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKSEL" caption="Clock Selection" mask="0x10" values="CTRLA__CKSEL"/>
+        </register>
+        <register name="NMICTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense Configuration" mask="0x7" values="NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+          <bitfield name="NMIASYNCH" caption="Asynchronous Edge Detection Mode" mask="0x10" values="NMICTRL__NMIASYNCH"/>
+        </register>
+        <register name="NMIFLAG" offset="0x2" rw="RW" size="2" atomic-op="clear:NMIFLAG" initval="0x0000" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x4" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy Status" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO" caption="External Interrupt Event Output Enable" mask="0xFFFF"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT" caption="External Interrupt Enable" mask="0xFFFF"/>
+          <bitfield name="NSCHK" caption="Non-secure Check Interrupt Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT" caption="External Interrupt Enable" mask="0xFFFF"/>
+          <bitfield name="NSCHK" caption="Non-secure Check Interrupt Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT" caption="External Interrupt" mask="0xFFFF"/>
+          <bitfield name="NSCHK" caption="Non-secure Check Interrupt" mask="0x80000000"/>
+        </register>
+        <register name="ASYNCH" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="External Interrupt Asynchronous Mode">
+          <bitfield name="ASYNCH" caption="Asynchronous Edge Detection Mode" mask="0xFFFF" values="ASYNCH__ASYNCH"/>
+        </register>
+        <register name="CONFIG" offset="0x1C" rw="RW" size="4" count="2" initval="0x00000000" caption="External Interrupt Sense Configuration">
+          <bitfield name="SENSE0" caption="Input Sense Configuration 0" mask="0x7" values="CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter Enable 0" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense Configuration 1" mask="0x70" values="CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter Enable 1" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense Configuration 2" mask="0x700" values="CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter Enable 2" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense Configuration 3" mask="0x7000" values="CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter Enable 3" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense Configuration 4" mask="0x70000" values="CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter Enable 4" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense Configuration 5" mask="0x700000" values="CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter Enable 5" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense Configuration 6" mask="0x7000000" values="CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter Enable 6" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense Configuration 7" mask="0x70000000" values="CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter Enable 7" mask="0x80000000"/>
+        </register>
+        <register name="DEBOUNCEN" offset="0x30" rw="RW" size="4" initval="0x00000000" caption="Debouncer Enable">
+          <bitfield name="DEBOUNCEN" caption="Debouncer Enable" mask="0xFFFF"/>
+        </register>
+        <register name="DPRESCALER" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Debouncer Prescaler">
+          <bitfield name="PRESCALER0" caption="Debouncer Prescaler" mask="0x7" values="DPRESCALER__PRESCALER"/>
+          <bitfield name="STATES0" caption="Debouncer number of states" mask="0x8" values="DPRESCALER__STATES"/>
+          <bitfield name="PRESCALER1" caption="Debouncer Prescaler" mask="0x70" values="DPRESCALER__PRESCALER"/>
+          <bitfield name="STATES1" caption="Debouncer number of states" mask="0x80" values="DPRESCALER__STATES"/>
+          <bitfield name="TICKON" caption="Pin Sampler frequency selection" mask="0x10000" values="DPRESCALER__TICKON"/>
+        </register>
+        <register name="PINSTATE" offset="0x38" rw="R" size="4" initval="0x00000000" caption="Pin State">
+          <bitfield name="PINSTATE" caption="Pin State" mask="0xFFFF"/>
+        </register>
+        <register name="NSCHK" offset="0x3C" rw="RW" size="4" initval="0x00000000" caption="Non-secure Interrupt Check Enable">
+          <bitfield name="EXTINT" caption="External Interrupt Nonsecure Check Enable" mask="0xFFFF"/>
+          <bitfield name="NMI" caption="Non-Maskable External Interrupt Nonsecure Check Enable" mask="0x80000000"/>
+        </register>
+        <register name="NONSEC" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Non-secure Interrupt">
+          <bitfield name="EXTINT" caption="External Interrupt Nonsecure Enable" mask="0xFFFF"/>
+          <bitfield name="NMI" caption="Non-Maskable Interrupt Nonsecure Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__CKSEL">
+        <value name="CLK_GCLK" caption="Clocked by GCLK" value="0"/>
+        <value name="CLK_ULP32K" caption="Clocked by ULP32K" value="1"/>
+      </value-group>
+      <value-group name="NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="NMICTRL__NMIASYNCH">
+        <value name="SYNC" caption="Edge detection is clock synchronously operated" value="0"/>
+        <value name="ASYNC" caption="Edge detection is clock asynchronously operated" value="1"/>
+      </value-group>
+      <value-group name="ASYNCH__ASYNCH">
+        <value name="SYNC" caption="EIC_EXTINTx edge detection is synchronously operated" value="0"/>
+        <value name="ASYNC" caption="EIC_EXTINTx edge detection is asynchronously operated" value="1"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="DPRESCALER__PRESCALER">
+        <value name="DIV2" caption="EIC clock divided by 2" value="0"/>
+        <value name="DIV4" caption="EIC clock divided by 4" value="1"/>
+        <value name="DIV8" caption="EIC clock divided by 8" value="2"/>
+        <value name="DIV16" caption="EIC clock divided by 16" value="3"/>
+        <value name="DIV32" caption="EIC clock divided by 32" value="4"/>
+        <value name="DIV64" caption="EIC clock divided by 64" value="5"/>
+        <value name="DIV128" caption="EIC clock divided by 128" value="6"/>
+        <value name="DIV256" caption="EIC clock divided by 256" value="7"/>
+      </value-group>
+      <value-group name="DPRESCALER__STATES">
+        <value name="LFREQ3" caption="3 low frequency samples" value="0"/>
+        <value name="LFREQ7" caption="7 low frequency samples" value="1"/>
+      </value-group>
+      <value-group name="DPRESCALER__TICKON">
+        <value name="CLK_GCLK_EIC" caption="Bounce sampler is using GCLK_EIC" value="0"/>
+        <value name="CLK_LFREQ" caption="Bounce sampler is using Low Frequency Clock" value="1"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="03601" name2="ptg_evsys_u2504_v2" version="2b0" caption="Event System Interface">
+      <register-group name="CHANNEL" size="0x8">
+        <register name="CHANNEL" offset="0x0" rw="RW" size="4" initval="0x00008000" caption="Channel n Control">
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x300" values="CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC00" values="CHANNEL__EDGSEL"/>
+          <bitfield name="RUNSTDBY" caption="Run in standby" mask="0x4000"/>
+          <bitfield name="ONDEMAND" caption="Generic Clock On Demand" mask="0x8000"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel n Interrupt Enable Clear">
+          <bitfield name="OVR" caption="Channel Overrun Interrupt Disable" mask="0x1"/>
+          <bitfield name="EVD" caption="Channel Event Detected Interrupt Disable" mask="0x2"/>
+        </register>
+        <register name="CHINTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel n Interrupt Enable Set">
+          <bitfield name="OVR" caption="Channel Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EVD" caption="Channel Event Detected Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel n Interrupt Flag Status and Clear">
+          <bitfield name="OVR" caption="Channel Overrun" mask="0x1"/>
+          <bitfield name="EVD" caption="Channel Event Detected" mask="0x2"/>
+        </register>
+        <register name="CHSTATUS" offset="0x7" rw="R" size="1" initval="0x01" caption="Channel n Status">
+          <bitfield name="RDYUSR" caption="Ready User" mask="0x1"/>
+          <bitfield name="BUSYCH" caption="Busy Channel" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRLA" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="SWEVT" offset="0x4" rw="W" size="4" initval="0x00000000" caption="Software Event">
+          <bitfield name="CHANNEL0" caption="Channel 0 Software Selection" mask="0x1"/>
+          <bitfield name="CHANNEL1" caption="Channel 1 Software Selection" mask="0x2"/>
+          <bitfield name="CHANNEL2" caption="Channel 2 Software Selection" mask="0x4"/>
+          <bitfield name="CHANNEL3" caption="Channel 3 Software Selection" mask="0x8"/>
+          <bitfield name="CHANNEL4" caption="Channel 4 Software Selection" mask="0x10"/>
+          <bitfield name="CHANNEL5" caption="Channel 5 Software Selection" mask="0x20"/>
+          <bitfield name="CHANNEL6" caption="Channel 6 Software Selection" mask="0x40"/>
+          <bitfield name="CHANNEL7" caption="Channel 7 Software Selection" mask="0x80"/>
+          <bitfield name="CHANNEL8" caption="Channel 8 Software Selection" mask="0x100"/>
+          <bitfield name="CHANNEL9" caption="Channel 9 Software Selection" mask="0x200"/>
+          <bitfield name="CHANNEL10" caption="Channel 10 Software Selection" mask="0x400"/>
+          <bitfield name="CHANNEL11" caption="Channel 11 Software Selection" mask="0x800"/>
+        </register>
+        <register name="PRICTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Priority Control">
+          <bitfield name="PRI" caption="Channel Priority Number" mask="0xF"/>
+          <bitfield name="RREN" caption="Round-Robin Scheduling Enable" mask="0x80"/>
+        </register>
+        <register name="INTPEND" offset="0x10" rw="RW" size="2" initval="0x4000" caption="Channel Pending Interrupt">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="OVR" caption="Channel Overrun" mask="0x100"/>
+          <bitfield name="EVD" caption="Channel Event Detected" mask="0x200"/>
+          <bitfield name="READY" caption="Ready" mask="0x4000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x14" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x18" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="READYUSR" offset="0x1C" rw="R" size="4" initval="0x00000FFF" caption="Ready Users">
+          <bitfield name="READYUSR0" caption="Ready User for Channel 0" mask="0x1"/>
+          <bitfield name="READYUSR1" caption="Ready User for Channel 1" mask="0x2"/>
+          <bitfield name="READYUSR2" caption="Ready User for Channel 2" mask="0x4"/>
+          <bitfield name="READYUSR3" caption="Ready User for Channel 3" mask="0x8"/>
+          <bitfield name="READYUSR4" caption="Ready User for Channel 4" mask="0x10"/>
+          <bitfield name="READYUSR5" caption="Ready User for Channel 5" mask="0x20"/>
+          <bitfield name="READYUSR6" caption="Ready User for Channel 6" mask="0x40"/>
+          <bitfield name="READYUSR7" caption="Ready User for Channel 7" mask="0x80"/>
+          <bitfield name="READYUSR8" caption="Ready User for Channel 8" mask="0x100"/>
+          <bitfield name="READYUSR9" caption="Ready User for Channel 9" mask="0x200"/>
+          <bitfield name="READYUSR10" caption="Ready User for Channel 10" mask="0x400"/>
+          <bitfield name="READYUSR11" caption="Ready User for Channel 11" mask="0x800"/>
+        </register>
+        <register-group name="CHANNEL" name-in-module="CHANNEL" offset="0x020" size="0x8" count="12"/>
+        <register name="USER" offset="0x120" rw="RW" size="1" count="62" initval="0x00" caption="User Multiplexer n">
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0xF"/>
+        </register>
+      </register-group>
+      <value-group name="CHANNEL__PATH">
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="0x0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="0x1"/>
+      </value-group>
+      <value-group name="CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+    </module>
+    <module name="FCR" id="04972" name2="pfm_ctrlr_apb_v2" version="2a0" caption="Polaris Flash Read Controller">
+      <register-group name="FCR" caption="Polaris Flash Read Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00008000" caption="CTRL A REGISTER">
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+          <bitfield name="FWS" caption="Flash Access Time Defined in terms of AHB Clock Wait States" mask="0xF00" values="CTRLA__FWS"/>
+          <bitfield name="ADRWS" caption="Address Wait State Enable" mask="0x4000" values="CTRLA__ADRWS"/>
+          <bitfield name="AUTOWS" caption="Automatic Wait State Enable." mask="0x8000" values="CTRLA__AUTOWS"/>
+          <bitfield name="RDBUFWS" caption="Read Buffer Wait StatesPer AHB port control of deterministic or zero wait state read buffer access." mask="0x10000" values="CTRLA__RDBUFWS"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CTRL B REGISTER">
+          <bitfield name="PRM" caption="Set NVM Power Reduction Mode" mask="0x1" values="CTRLB__PRM"/>
+          <bitfield name="CHEINV" caption="Cache InvalidateCache invalidation takes 1 clock cycle, but may be delayed by an active read." mask="0x80" values="CTRLB__CHEINV"/>
+          <bitfield name="SLP" caption="NVM Power Reduction Mode selection during System Standby Sleep" mask="0x300" values="CTRLB__SLP"/>
+          <bitfield name="CHEDIS" caption="Cache Disable" mask="0x10000" values="CTRLB__CHEDIS"/>
+          <bitfield name="PREFDIS" caption="Prefetch Disable" mask="0x20000" values="CTRLB__PREFDIS"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Clear Enable" mask="0x1" values="INTENCLR__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Clear Enable" mask="0x100" values="INTENCLR__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Clear Enable" mask="0x200" values="INTENCLR__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Clear Enable" mask="0x10000" values="INTENCLR__FLTCAP"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable SET REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Set Enable" mask="0x1" values="INTENSET__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Set Enable" mask="0x100" values="INTENSET__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Set Enable" mask="0x200" values="INTENSET__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Set Enable" mask="0x10000" values="INTENSET__FLTCAP"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Flag" mask="0x1" values="INTFLAG__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Flag" mask="0x100" values="INTFLAG__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Flag" mask="0x200" values="INTFLAG__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Flag" mask="0x10000" values="INTFLAG__FLTCAP"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="Interrupt Flag Set REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Flag" mask="0x1" values="INTFLAGSET__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Flag" mask="0x100" values="INTFLAGSET__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Flag" mask="0x200" values="INTFLAGSET__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Flag" mask="0x10000" values="INTFLAGSET__FLTCAP"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="R" size="4" initval="0xE0000000" caption="Status REGISTER">
+          <bitfield name="PRM" caption="NVM Power Reduction Mode Status" mask="0x1" values="STATUS__PRM"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Debug Control CTRL REGISTER">
+          <bitfield name="CRCRUN" caption="CRC Debug Run Enable" mask="0x1" values="DBGCTRL__CRCRUN"/>
+          <bitfield name="DBGECC" caption="Debug ECC ModeECC errors from debugger reads are:" mask="0x6" values="DBGCTRL__DBGECC"/>
+        </register>
+        <register name="ECCCTRL" offset="0x20" rw="RW" size="4" initval="0x00000040" caption="ECC Control REGISTER">
+          <bitfield name="ECCCTL" caption="NVM ECC Mode Control - restricts one or more NVMOPs" mask="0x30" values="ECCCTRL__ECCCTL"/>
+          <bitfield name="ECCUNLCK" caption="NVM ECC Mode Control Unlock" mask="0x40" values="ECCCTRL__ECCUNLCK"/>
+          <bitfield name="SECCNT" caption="Flash SEC Count" mask="0xFF00"/>
+        </register>
+        <register name="CRCCTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="CRC Control REGISTER">
+          <bitfield name="CRCRST" caption="CRC Reset" mask="0x1" values="CRCCTRL__CRCRST"/>
+          <bitfield name="CRCEN" caption="Start CRC Calculation" mask="0x2" values="CRCCTRL__CRCEN"/>
+          <bitfield name="RUNSTDBY" caption="CRC Run in Standby" mask="0x20" values="CRCCTRL__RUNSTDBY"/>
+        </register>
+        <register name="CRCMODE" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="CRC MODE REGISTER">
+          <bitfield name="PLEN32" caption="Polynomial Length Select" mask="0x1000" values="CRCMODE__PLEN32"/>
+          <bitfield name="AUTOR" caption="CRC Auto Repeat" mask="0x2000" values="CRCMODE__AUTOR"/>
+          <bitfield name="ROUT" caption="CRC Reflected Output" mask="0x4000" values="CRCMODE__ROUT"/>
+          <bitfield name="RIN" caption="CRC Reflected Input" mask="0x8000" values="CRCMODE__RIN"/>
+          <bitfield name="PERIOD" caption="Read Period in PerCLK counts" mask="0xFFF0000"/>
+        </register>
+        <register name="CRCPAUSE" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="CRC Pause REGISTER">
+          <bitfield name="PAUSE" caption="CRC Pause" mask="0x1" values="CRCPAUSE__PAUSE"/>
+        </register>
+        <register name="CRCMADR" offset="0x30" rw="RW" size="4" initval="0x00000000" caption="CRC Message Address REGISTER">
+          <bitfield name="CRCMADR" caption="Message Start Address in Flash" mask="0xFFFFFFF"/>
+        </register>
+        <register name="CRCMLEN" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="CRC Message Length REGISTER">
+          <bitfield name="CRCMLEN" caption="Message Length in Bytes" mask="0xFFFFF"/>
+        </register>
+        <register name="CRCIV" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="CRC Initial Value REGISTER">
+          <bitfield name="CRCIV" caption="CRC Initial Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCACC" offset="0x3C" rw="R" size="4" initval="0x00000000" caption="CRC Accumulator REGISTER">
+          <bitfield name="CRCACC" caption="CRC Accumulator Result" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCPOLY" offset="0x40" rw="RW" size="4" initval="0x00000001" caption="CRC Polynomial REGISTER">
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Coefficients for LFSR" mask="0xFFFFFFFF" values="CRCPOLY__CRCPOLY"/>
+        </register>
+        <register name="CRCFXOR" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="CRC Final XOR REGISTER">
+          <bitfield name="CRCFXOR" caption="CRC Final XOR" mask="0xFFFFFFFF" values="CRCFXOR__CRCFXOR"/>
+        </register>
+        <register name="CRCSUM" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="CRC CheckSUM REGISTER">
+          <bitfield name="CRCSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FFLTCTRL" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Control REGISTER">
+          <bitfield name="FLTRST" caption="Fault Reset" mask="0x1" values="FFLTCTRL__FLTRST"/>
+          <bitfield name="FLTEN" caption="ECC Fault Enable bit" mask="0x2" values="FFLTCTRL__FLTEN"/>
+        </register>
+        <register name="FFLTMODE" offset="0x50" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Mode REGISTER">
+          <bitfield name="CTLFLT" caption="ECC/Parity Control Fault bits" mask="0x700" values="FFLTMODE__CTLFLT"/>
+          <bitfield name="FLTMD" caption="Fault Mode Control" mask="0x7000" values="FFLTMODE__FLTMD"/>
+        </register>
+        <register name="FFLTPTR" offset="0x54" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Pointer REGISTER">
+          <bitfield name="FLTPTR1" caption="Fault 1 Injection Pointer" mask="0xFF"/>
+          <bitfield name="FLTPTR2" caption="Fault 2 Injection Pointer" mask="0xFF0000"/>
+        </register>
+        <register name="FFLTADR" offset="0x58" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Address REGISTER">
+          <bitfield name="FLTADR" caption="Fault Injection Address" mask="0xFFFFFFF"/>
+        </register>
+        <register name="FFLTCAP" offset="0x5C" rw="R" size="4" initval="0x00000000" caption="Flash ECC Fault Capture Address REGISTER">
+          <bitfield name="FLTADR" caption="Fault Capture Address" mask="0xFFFFFFF"/>
+        </register>
+        <register name="FFLTPAR" offset="0x60" rw="R" size="4" initval="0x00000000" caption="Flash ECC Fault Parity REGISTER">
+          <bitfield name="SECIN" caption="The Single Error Parity bits from Flash" mask="0xFF"/>
+          <bitfield name="DEDIN" caption="The Overall Parity from Flash" mask="0x8000"/>
+          <bitfield name="SECOUT" caption="The Calculated Single Error Parity bits" mask="0xFF0000"/>
+          <bitfield name="DEDOUT" caption="The Calculated Overall Parity used in Double Error Detection" mask="0x80000000"/>
+        </register>
+        <register name="FFLTSYN" offset="0x64" rw="R" size="4" initval="0x00000000" caption="Flash ECC Fault Syndrome REGISTER">
+          <bitfield name="SECSYN" caption="Single Error Correction Syndrome" mask="0xFF"/>
+          <bitfield name="DEDSYN" caption="DED Syndrome" mask="0x8000" values="FFLTSYN__DEDSYN"/>
+          <bitfield name="DSERR" caption="Double Error Detected &amp; Single Error Corrected" mask="0x30000" values="FFLTSYN__DSERR"/>
+          <bitfield name="CERR" caption="ECC Control bit Error" mask="0x40000" values="FFLTSYN__CERR"/>
+          <bitfield name="CTLSTAT" caption="Parity vs ECC Control Status" mask="0x7000000" values="FFLTSYN__CTLSTAT"/>
+          <bitfield name="PERR" caption="Per Word (n=3:0) Parity Error Status" mask="0xF0000000" values="FFLTSYN__PERR"/>
+        </register>
+        <register name="CRP" offset="0x68" rw="RW" size="4" initval="0x00C20000" caption="CFM Page Read Protection REGISTER (CFM8)">
+          <bitfield name="BC1ARP" caption="Panel 1 Read Protect BootCfg1A" mask="0x1" values="CRP__BC1ARP"/>
+          <bitfield name="UO1RP" caption="Panel 1 Read Protect UserOTP1" mask="0x2" values="CRP__UO1RP"/>
+          <bitfield name="BC1RP" caption="Panel 1 Read Protect BootCfg1" mask="0x4" values="CRP__BC1RP"/>
+          <bitfield name="RCRP" caption="Panel 1 Read Protect ROMCfg" mask="0x8" values="CRP__RCRP"/>
+          <bitfield name="VSSRP0" caption="Panel 1 Read Protect VSSn" mask="0x10" values="CRP__VSSRP"/>
+          <bitfield name="VSSRP1" caption="Panel 1 Read Protect VSSn" mask="0x20" values="CRP__VSSRP"/>
+          <bitfield name="TRP" caption="Panel 1 Read Protect Test" mask="0x40" values="CRP__TRP"/>
+          <bitfield name="CORP" caption="Panel 1 Read Protect CalOTP" mask="0x80" values="CRP__CORP"/>
+          <bitfield name="BC1ARPLOCK" caption="Panel 1 Lock Read Protection BootCfg1A" mask="0x10000" values="CRP__BC1ARPLOCK"/>
+          <bitfield name="UO1RPLOCK" caption="Panel 1 Lock Read Protection UserOTP1" mask="0x20000" values="CRP__UO1RPLOCK"/>
+          <bitfield name="BC1RPLOCK" caption="Panel 1 Lock Read Protection BootCfg1" mask="0x40000" values="CRP__BC1RPLOCK"/>
+          <bitfield name="RCRPLOCK" caption="Panel 1 Lock Read Protection ROMCfg" mask="0x80000" values="CRP__RCRPLOCK"/>
+          <bitfield name="VSSRPLOCK0" caption="Panel 1 Lock Read Protection VSSn" mask="0x100000" values="CRP__VSSRPLOCK"/>
+          <bitfield name="VSSRPLOCK1" caption="Panel 1 Lock Read Protection VSSn" mask="0x200000" values="CRP__VSSRPLOCK"/>
+          <bitfield name="TRPLOCK" caption="Panel 1 Lock Read Protection Test" mask="0x400000" values="CRP__TRPLOCK"/>
+          <bitfield name="CORPLOCK" caption="Panel 1 Lock Read Protection CalOTP" mask="0x800000" values="CRP__CORPLOCK"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="DISABLE" caption="Macro register accessible in privileged and unprivileged accesses." value="0"/>
+        <value name="ENABLE" caption="Macro registers only accessible in privileged accesses" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__FWS">
+        <value name="0" caption="Zero Wait States" value="0"/>
+        <value name="1" caption="One Wait State" value="1"/>
+        <value name="14" caption="Fourteen Wait States" value="14"/>
+        <value name="15" caption="Fifteen Wait States" value="15"/>
+      </value-group>
+      <value-group name="CTRLA__ADRWS">
+        <value name="ZERO" caption="Add 0 Address Wait States - allowing for higher performance at lower clock frequencies" value="0"/>
+        <value name="ONE" caption="Add 1 Address Wait State - allowing for higher clock frequencies" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__AUTOWS">
+        <value name="DISABLE" caption="Use FWS: Total flash wait states are ADRWS + FWS" value="0"/>
+        <value name="ENABLE" caption="Use Automatic wait states: Total flash wait states are ADRWS + Taws" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__RDBUFWS">
+        <value name="ZEROWS" caption="0 Wait States" value="0"/>
+        <value name="DETERMINISTIC" caption="ADRWS + FWS wait state for hits to AHB read buffer" value="1"/>
+      </value-group>
+      <value-group name="CTRLB__PRM">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="TOGGLE" caption="Toggle the Flash Power Mode" value="1"/>
+      </value-group>
+      <value-group name="CTRLB__CHEINV">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="INV" caption="Invalidate Cache" value="1"/>
+      </value-group>
+      <value-group name="CTRLB__SLP">
+        <value name="MANUAL" caption="Maintain state of STATUS.PRM on entry to Standby" value="0"/>
+        <value name="RSVD01" caption="RSVD" value="1"/>
+        <value name="AUTOFAST" caption="Enter Flash Hibernate on entry to Standby w/ wakeup to Auto Standby" value="2"/>
+        <value name="AUTOSLOW" caption="Enter Flash Hibernate on entry to Standby w/ wakeup on first access" value="3"/>
+      </value-group>
+      <value-group name="CTRLB__CHEDIS">
+        <value name="ENABLE" caption="Cache Enabled; Accesses to flash use AUTOWS/FSW selection." value="0"/>
+        <value name="DISABLE" caption="Cache Disabled; Interface uses RDBUFWS selection." value="1"/>
+      </value-group>
+      <value-group name="CTRLB__PREFDIS">
+        <value name="ENABLE" caption="Predictive Prefetch Enabled" value="0"/>
+        <value name="DISABLE" caption="Predictive Prefetch Disabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__SERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__CRCDONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__CRCERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__FLTCAP">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__SERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CRCDONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CRCERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__FLTCAP">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__SERR">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="SECCNT Count reached" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__CRCDONE">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="Calculation Done" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__CRCERR">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="CRCACC Is Not Equal to the XOR of CRCSUM and CRCFXOR" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__FLTCAP">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="An ECC Fault Capture, related to FLTMD[], occurred" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__SERR">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="SECCNT Count reached" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__CRCDONE">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__CRCERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__FLTCAP">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="STATUS__PRM">
+        <value name="0" caption="Flash is Ready (for read or NVMOP)" value="0"/>
+        <value name="1" caption="Flash is Powered Down and wakes on first access (read or NVMOP)" value="1"/>
+      </value-group>
+      <value-group name="DBGCTRL__CRCRUN">
+        <value name="HALT" caption="CRC Logic Halts in Debug Mode" value="0"/>
+        <value name="RUN" caption="CRC Logic Runs in Debug Mode." value="1"/>
+      </value-group>
+      <value-group name="DBGCTRL__DBGECC">
+        <value name="NOERR" caption="Corrected per ECCCTRL; No Bus ERR; INTFLAG, SEC counter, and FLT logic are not updated." value="0"/>
+        <value name="DISABLE" caption="Not corrected; No Bus Error; INTFLAG, SEC counter, and FLT logic are not updated." value="1"/>
+        <value name="ENABLE" caption="Corrected per ECCCTRL; Bus Error, INTFLAG, SEC counter, and FLT logic operates as setup." value="2"/>
+        <value name="RSVD11" caption="Don't use but same as 01 (DISABLE)" value="3"/>
+      </value-group>
+      <value-group name="ECCCTRL__ECCCTL">
+        <value name="STRICT" caption="ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)" value="0"/>
+        <value name="DYNAMIC" caption="Dynamic Writes with Dynamic Reads" value="1"/>
+        <value name="ECC" caption="ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)" value="2"/>
+        <value name="DISABLE" caption="Dynamic Writes with No Error Check Reads" value="3"/>
+      </value-group>
+      <value-group name="ECCCTRL__ECCUNLCK">
+        <value name="LOCKED" caption="ECCUNLCK and ECCCTL[1:0] cannot be written" value="0"/>
+        <value name="UNLOCKED" caption="ECCUNLCK and ECCCTL[1:0] can be written" value="1"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCRST">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="RESET" caption="Resets all CRC SFR bits." value="1"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCEN">
+        <value name="DISABLE" caption="Stops CRC calculation." value="0"/>
+        <value name="ENABLE" caption="CRC Calculation Enabled (w/ start on write to 1)." value="1"/>
+      </value-group>
+      <value-group name="CRCCTRL__RUNSTDBY">
+        <value name="HALT" caption="CRC Halts in Standby" value="0"/>
+        <value name="RUN" caption="CRC Runs in Standby but only if STATUS.PRM=0 (i.e. Flash is in Auto Standby)" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__PLEN32">
+        <value name="SIXTEEN" caption="Polynomial is 16-bits" value="0"/>
+        <value name="THIRTYTWO" caption="Polynomial is 32-bits" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__AUTOR">
+        <value name="DISABLE" caption="Perform CRC calculation once then set DONE and if needed, CRCERR." value="0"/>
+        <value name="ENABLE" caption="Continually Repeat CRC calculation; stop on error, set CRCDONE and CRCERR" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__ROUT">
+        <value name="DISABLE" caption="The CRCACC is Not Reflected" value="0"/>
+        <value name="ENABLE" caption="The CRCACC is Reflected (before the Final XOR)" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__RIN">
+        <value name="DISABLE" caption="The LFSR CRC is calculated Most Significant Bit first (Not Reflected)" value="0"/>
+        <value name="ENABLE" caption="The LFSR CRC is calculated Least Significant Bit first (Reflected)" value="1"/>
+      </value-group>
+      <value-group name="CRCPAUSE__PAUSE">
+        <value name="DISABLE" caption="CRC Reads Flash as Required" value="0"/>
+        <value name="ENABLE" caption="Pause CRC Reads of Flash" value="1"/>
+      </value-group>
+      <value-group name="CRCPOLY__CRCPOLY">
+        <value name="0" caption="Disable the XOR input to the shift register at the associated bit position" value="0"/>
+        <value name="1" caption="Enable the XOR input to the shift register at the associated bit position" value="1"/>
+      </value-group>
+      <value-group name="CRCFXOR__CRCFXOR">
+        <value name="0" caption="Disable the Final XOR at the associated bit position" value="0"/>
+        <value name="1" caption="Enable the Final XOR at the associated bit position" value="1"/>
+      </value-group>
+      <value-group name="FFLTCTRL__FLTRST">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="RESET" caption="Resets all FLT SFR bits." value="1"/>
+      </value-group>
+      <value-group name="FFLTCTRL__FLTEN">
+        <value name="DISABLE" caption="ECC Fault Injection Disabled" value="0"/>
+        <value name="ENABLE" caption="ECC Fault Injection Enabled (module performs operation selected by FFLTMODE.FLTMD)" value="1"/>
+      </value-group>
+      <value-group name="FFLTMODE__CTLFLT">
+        <value name="0" caption="No Fault Injected" value="0"/>
+        <value name="1" caption="Inject a Fault on to the associated ECC/Parity Control bits (CTL[n])" value="1"/>
+      </value-group>
+      <value-group name="FFLTMODE__FLTMD">
+        <value name="DISABLE" caption="Fault Injection Disabled" value="0"/>
+        <value name="CAPT" caption="Fault Capture Mode Enabled - Captures the address (in FLTADR) and Syndrome in (FLTSYN)" value="2"/>
+        <value name="SINGLEREAD" caption="Single Fault Injection (at bit selected by FLT1PTR) for Reads" value="4"/>
+        <value name="DOUBLEREAD" caption="Double Fault Injection for Reads" value="5"/>
+        <value name="SINGLEWRITE" caption="Single Fault Injection (at bit selected by FLT1PTR) for Writes" value="6"/>
+        <value name="DOUBLEWRITE" caption="Double Fault Injection for Writes" value="7"/>
+      </value-group>
+      <value-group name="FFLTSYN__DEDSYN">
+        <value name="0" caption="Calculated Overall Parity Concurs with Read Overall Parity" value="0"/>
+        <value name="1" caption="Calculated Overall Parity Differs from Read Overall Parity" value="1"/>
+      </value-group>
+      <value-group name="FFLTSYN__DSERR">
+        <value name="NONE" caption="No Errors" value="0"/>
+        <value name="SINGLE" caption="Single Error Corrected" value="1"/>
+        <value name="DOUBLE_10" caption="Double Error Detected" value="2"/>
+        <value name="DOUBLE_11" caption="Double Error Detected" value="3"/>
+      </value-group>
+      <value-group name="FFLTSYN__CERR">
+        <value name="NONE" caption="No Control bit Error (ECCSTAT either 111 or 000)" value="0"/>
+        <value name="SINGLE" caption="Single Control Bit Error" value="1"/>
+      </value-group>
+      <value-group name="FFLTSYN__CTLSTAT">
+        <value name="USEDECC_0" caption="Calculation used ECC (i.e. programming used quad write)" value="0"/>
+        <value name="USEDECC_1" caption="Calculation used ECC (i.e. programming used quad write)" value="1"/>
+        <value name="USEDECC_10" caption="Calculation used ECC (i.e. programming used quad write)" value="2"/>
+        <value name="USEDPARITY_11" caption="Calculation used Parity (i.e. programming used single write)" value="3"/>
+        <value name="USEDECC_100" caption="Calculation used ECC (i.e. programming used quad write)" value="4"/>
+        <value name="USEDPARITY_101" caption="Calculation used Parity (i.e. programming used single write)" value="5"/>
+        <value name="USEDPARITY_110" caption="Calculation used Parity (i.e. programming used single write)" value="6"/>
+        <value name="USEDPARITY_111" caption="Calculation used Parity (i.e. programming used single write)" value="7"/>
+      </value-group>
+      <value-group name="FFLTSYN__PERR">
+        <value name="NONE" caption="No Parity Error on Word n" value="0"/>
+        <value name="ERROR" caption="Parity Error on Word n" value="1"/>
+      </value-group>
+      <value-group name="CRP__BC1ARP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__UO1RP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+      </value-group>
+      <value-group name="CRP__BC1RP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__RCRP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__VSSRP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__TRP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__CORP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__BC1ARPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__UO1RPLOCK">
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__BC1RPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__RCRPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__VSSRPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__TRPLOCK">
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__CORPLOCK">
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+    </module>
+    <module name="FCW" id="04971" name2="pfm_ctrlw_apb_v2" version="2a0" caption="Polaris Flash Write Controller">
+      <register-group name="FCW" caption="Polaris Flash Write Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A REGISTER">
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+        </register>
+        <register name="CTRLOP" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control Operation REGISTER">
+          <bitfield name="NVMOP" caption="NVM Operation" mask="0xF" values="CTRLOP__NVMOP"/>
+          <bitfield name="PREPG" caption="NVM Pre-Program Configuration Bit" mask="0x80" values="CTRLOP__PREPG"/>
+        </register>
+        <register name="MUTEX" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="MUTEX REGISTER">
+          <bitfield name="LOCK" caption="Flash Write Controller (FCW) Lock by Owner" mask="0x1" values="MUTEX__LOCK"/>
+          <bitfield name="OWNER" caption="Flash Write Controller (FCW) Owner ID" mask="0x6" values="MUTEX__OWNER"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Interrupt Enable" mask="0x1" values="INTENCLR__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Interrupt Enable" mask="0x2" values="INTENCLR__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Interrupt Enable" mask="0x4" values="INTENCLR__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Interrupt Enable" mask="0x8" values="INTENCLR__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Interrupt Enable" mask="0x10" values="INTENCLR__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Interrupt Enable" mask="0x20" values="INTENCLR__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Interrupt Enable" mask="0x40" values="INTENCLR__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Interrupt Enable" mask="0x100" values="INTENCLR__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Interrupt Enable" mask="0x1000" values="INTENCLR__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Interrupt Enable" mask="0x2000" values="INTENCLR__WRERR"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Interrupt Set Enable" mask="0x1" values="INTENSET__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Interrupt Set Enable" mask="0x2" values="INTENSET__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Interrupt Set Enable" mask="0x4" values="INTENSET__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Interrupt Set Enable" mask="0x8" values="INTENSET__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Interrupt Enable" mask="0x10" values="INTENSET__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Interrupt Enable" mask="0x20" values="INTENSET__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Interrupt Enable" mask="0x40" values="INTENSET__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Interrupt Enable" mask="0x100" values="INTENSET__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Interrupt Enable" mask="0x1000" values="INTENSET__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Interrupt Enable" mask="0x2000" values="INTENSET__WRERR"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Flag Bit" mask="0x1" values="INTFLAG__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Flag Bit" mask="0x2" values="INTFLAG__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Flag Bit" mask="0x4" values="INTFLAG__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Flag Bit" mask="0x8" values="INTFLAG__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Flag Bit" mask="0x10" values="INTFLAG__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Flag Bit" mask="0x20" values="INTFLAG__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Flag Bit" mask="0x40" values="INTFLAG__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Flag Bit" mask="0x100" values="INTFLAG__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Flag Bit" mask="0x1000" values="INTFLAG__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Flag Bit" mask="0x2000" values="INTFLAG__WRERR"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="Interrupt Flag Set REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Set Flag Bit" mask="0x1" values="INTFLAGSET__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Set Flag Bit" mask="0x2" values="INTFLAGSET__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Set Flag Bit" mask="0x4" values="INTFLAGSET__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Set Flag Bit" mask="0x8" values="INTFLAGSET__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Set Flag Bit" mask="0x10" values="INTFLAGSET__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Set Flag Bit" mask="0x20" values="INTFLAGSET__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Set Flag Bit" mask="0x40" values="INTFLAGSET__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Set Flag Bit" mask="0x100" values="INTFLAGSET__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Set Flag Bit" mask="0x1000" values="INTFLAGSET__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Set Flag Bit" mask="0x2000" values="INTFLAGSET__WRERR"/>
+        </register>
+        <register name="STATUS" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="Status REGISTER">
+          <bitfield name="BUSY" caption="NVM Busy Status" mask="0x1" values="STATUS__BUSY"/>
+          <bitfield name="HTDRDY" caption="High Temp Detect Ready Status" mask="0x100" values="STATUS__HTDRDY"/>
+        </register>
+        <register name="KEY" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Feature Unlock Key REGISTER">
+          <bitfield name="FEATURE" caption="Feature Select" mask="0xFF" values="KEY__FEATURE"/>
+          <bitfield name="CODE" caption="Unlock Code" mask="0xFFFFFF00"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Flash Destination Address REGISTER">
+          <bitfield name="ADDR" caption="Flash Address used by NVMOP" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="System Source Address REGISTER">
+          <bitfield name="SRCADDR" caption="Source Data (Word) Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DATA" offset="0x2C" rw="RW" size="4" count="4" initval="0x00000000" caption="Flash Write Data n REGISTER">
+          <bitfield name="DATA" caption="Flash Write Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="SWAP" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="NVM Panel Swap REGISTER">
+          <bitfield name="BFSWAP" caption="BFM Swap Status/Control Bit" mask="0x1" values="SWAP__BFSWAP"/>
+          <bitfield name="BFSLOCK" caption="BFM Swap Lock Bit" mask="0x2" values="SWAP__BFSLOCK"/>
+          <bitfield name="PFSWAP" caption="PFM Swap Status/Control Bit" mask="0x100" values="SWAP__PFSWAP"/>
+          <bitfield name="PFSLOCK" caption="PFM Swap Lock Bit" mask="0x200" values="SWAP__PFSLOCK"/>
+        </register>
+        <register name="PWP" offset="0x50" rw="RW" size="4" count="4" initval="0x00000000" caption="PFM Write Protect Region n REGISTER">
+          <bitfield name="PWPSIZE" caption="PWP Size in 4KB pages" mask="0x7F"/>
+          <bitfield name="PWPMIR" caption="Mirror PWP bit" mask="0x2000" values="PWP__PWPMIR"/>
+          <bitfield name="PWPLOCK" caption="PWP Lock Bit" mask="0x4000" values="PWP__PWPLOCK"/>
+          <bitfield name="PWPEN" caption="PWP Enable Bit" mask="0x8000" values="PWP__PWPEN"/>
+          <bitfield name="PWPBASE" caption="PWP Base Address - 4KB Page Aligned" mask="0x7F0000"/>
+        </register>
+        <register name="LBWP" offset="0x70" rw="RW" size="4" initval="0x00000003" caption="Lower BFM Write Protect REGISTER">
+          <bitfield name="LBWP" caption="Lower Boot Pages Write Protect Bits" mask="0x3" values="LBWP__LBWP"/>
+          <bitfield name="LBWPLOCK" caption="LBWP Lock Bit" mask="0x80000000" values="LBWP__LBWPLOCK"/>
+        </register>
+        <register name="UBWP" offset="0x74" rw="RW" size="4" initval="0x00000003" caption="Upper BFM Write Protect REGISTER">
+          <bitfield name="UBWP" caption="Upper Boot Pages Write Protect Bits" mask="0x3" values="UBWP__UBWP"/>
+          <bitfield name="UBWPLOCK" caption="UBWP Lock Bit" mask="0x80000000" values="UBWP__UBWPLOCK"/>
+        </register>
+        <register name="UOWP" offset="0x78" rw="RW" size="4" initval="0x0000000F" caption="User OTP Write protection REGISTER">
+          <bitfield name="UO1WPR" caption="User OTP Page 1 Write Protect Row Bit" mask="0xF" values="UOWP__UO1WPR"/>
+          <bitfield name="UO1WPRLOCK" caption="User OTP Page 1 WP Row Lock Bit" mask="0xF0000" values="UOWP__UO1WPRLOCK"/>
+        </register>
+        <register name="CWP" offset="0x7C" rw="RW" size="4" initval="0x08C008FD" caption="CFM Page Write Protect REGISTER">
+          <bitfield name="BC1AWP" caption="Panel 1 Write Protect BootCfg1A" mask="0x1" values="CWP__BC1AWP"/>
+          <bitfield name="BC1WP" caption="Panel 1 Write Protect BootCfg1" mask="0x4" values="CWP__BC1WP"/>
+          <bitfield name="RCWP" caption="Panel 1 Write Protect ROMCfg" mask="0x8" values="CWP__RCWP"/>
+          <bitfield name="VSSWP0" caption="Panel 1 Write Protect VSSn" mask="0x10" values="CWP__VSSWP"/>
+          <bitfield name="VSSWP1" caption="Panel 1 Write Protect VSSn" mask="0x20" values="CWP__VSSWP"/>
+          <bitfield name="TWP" caption="Panel 1 Write Protect Test" mask="0x40" values="CWP__TWP"/>
+          <bitfield name="COWP" caption="Panel 1 Write Protect CalOTP" mask="0x80" values="CWP__COWP"/>
+          <bitfield name="BC1AWPLOCK" caption="Panel 1 Lock Write Protection BootCfg1A" mask="0x10000" values="CWP__BC1AWPLOCK"/>
+          <bitfield name="BC1WPLOCK" caption="Panel 1 Lock Write Protection BootCfg1" mask="0x40000" values="CWP__BC1WPLOCK"/>
+          <bitfield name="RCWPLOCK" caption="Panel 1 Lock Write Protection ROMCfg" mask="0x80000" values="CWP__RCWPLOCK"/>
+          <bitfield name="VSSWPLOCK0" caption="Panel 1 Lock Write Protection VSSn" mask="0x100000" values="CWP__VSSWPLOCK"/>
+          <bitfield name="VSSWPLOCK1" caption="Panel 1 Lock Write Protection VSSn" mask="0x200000" values="CWP__VSSWPLOCK"/>
+          <bitfield name="TWPLOCK" caption="Panel 1 Lock Write Protection Test" mask="0x400000" values="CWP__TWPLOCK"/>
+          <bitfield name="COWPLOCK" caption="Panel 1 Lock Write Protection CalOTP" mask="0x800000" values="CWP__COWPLOCK"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="DISABLE" caption="Macro register accessible in privileged and unprivileged accesses." value="0"/>
+        <value name="ENABLE" caption="Macro registers only accessible in privileged accesses" value="1"/>
+      </value-group>
+      <value-group name="CTRLOP__NVMOP">
+        <value name="NOP" caption="No Operation" value="0"/>
+        <value name="SINGLEWRITE" caption="Single (Word) Program Operation: Programs word selected by ADDR" value="1"/>
+        <value name="QUADWRITE" caption="Quad (Word) Program Operation: Programs flash word selected by ADDR" value="2"/>
+        <value name="ROWWRITE" caption="Row Write Operation: Programs row selected by ADDR" value="3"/>
+        <value name="PAGEERASE" caption="Page Erase Operation: Erases page selected by ADDR" value="4"/>
+        <value name="LPFMERASE" caption="Lower PFM Erase Operation: (RSVD NVMOP for Single Panel Devices)" value="5"/>
+        <value name="UPFMERASE" caption="Upper PFM Erase Operation: (RSVD NVMOP for Single Panel Devices)" value="6"/>
+        <value name="PFMERASE" caption="PFM Erase Operation: Upper &amp;amp; Lower PFM Erase" value="7"/>
+        <value name="CE" caption="Chip Erase Operation: Erases PFM+SRF, BFM, CFM (except for CalOTP, Test, VSS pages if HSM is Present, UserOTP, &amp;amp; ROMCFG)." value="14"/>
+      </value-group>
+      <value-group name="CTRLOP__PREPG">
+        <value name="DISABLE" caption="Program Operations exclude Pre-Program step" value="0"/>
+        <value name="ENABLE" caption="Program Operations include Pre-Program step" value="1"/>
+      </value-group>
+      <value-group name="MUTEX__LOCK">
+        <value name="UNLOCK" caption="FCW is not locked" value="0"/>
+        <value name="LOCK" caption="FCW is locked by owner" value="1"/>
+      </value-group>
+      <value-group name="MUTEX__OWNER">
+        <value name="NONE" caption="No Owner - always 0 if LOCK=0" value="0"/>
+        <value name="SYSTEM" caption="The System owns the FCW" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__DONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__KEYERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__CFGERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__FIFOERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__BUSERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__WPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__OPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__HTDPGM">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__RSTERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__WRERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__DONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__KEYERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CFGERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__FIFOERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__BUSERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__WPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__OPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__HTDPGM">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__RSTERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__WRERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__DONE">
+        <value name="0" caption="NVMOP Not Done" value="0"/>
+        <value name="1" caption="NVMOP Done" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__KEYERR">
+        <value name="0" caption="No Key Error" value="0"/>
+        <value name="1" caption="Key Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__CFGERR">
+        <value name="0" caption="No CFG Error" value="0"/>
+        <value name="1" caption="CFC Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__FIFOERR">
+        <value name="0" caption="No FIFO Error" value="0"/>
+        <value name="1" caption="FIFO Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__BUSERR">
+        <value name="0" caption="No Bus Error" value="0"/>
+        <value name="1" caption="Bus Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__WPERR">
+        <value name="0" caption="No Write Protection Error" value="0"/>
+        <value name="1" caption="Write Protection Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__OPERR">
+        <value name="0" caption="No NVMOP Error" value="0"/>
+        <value name="1" caption="Selected Operation is Disabled Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__HTDPGM">
+        <value name="0" caption="High Temp NOT Detected" value="0"/>
+        <value name="1" caption="High Temp Detected (possible data corruption, verify operation)" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__RSTERR">
+        <value name="0" caption="No Reset and Voltage level OK during write/erase" value="0"/>
+        <value name="1" caption="A reset or Low Voltage Detected (possible data corruption, verify data)" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__WRERR">
+        <value name="0" caption="The Write/Erase sequence completed normally" value="0"/>
+        <value name="1" caption="The Write/Erase sequence did not complete successfully" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__DONE">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__KEYERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__CFGERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__FIFOERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__BUSERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__WPERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__OPERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__HTDPGM">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__RSTERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__WRERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="STATUS__BUSY">
+        <value name="IDLE" caption="NVM Not Busy" value="0"/>
+        <value name="BUSY" caption="NVM Busy - All SFR bits are not writable" value="1"/>
+      </value-group>
+      <value-group name="STATUS__HTDRDY">
+        <value name="NOTREADY" caption="HTD Not Ready" value="0"/>
+        <value name="READY" caption="HTD Ready" value="1"/>
+      </value-group>
+      <value-group name="KEY__FEATURE">
+        <value name="LOCKALL" caption="No selection, invalid selection, or invalid Key - Locks all SFR protected by KEY register" value="0"/>
+        <value name="WRKEY" caption="WRKEY Value: Unlock SFR bits associated with Write/Erase" value="1"/>
+        <value name="SWAPKEY" caption="SWAPKEY Value: Unlock SFR bits associated with Panel Swapping" value="2"/>
+        <value name="CFGKEY" caption="CFGKEY Value: Unlock SFR bits associated with general Flash configuration" value="4"/>
+      </value-group>
+      <value-group name="SWAP__BFSWAP">
+        <value name="UNSWAP" caption="Upper and Lower BFM Regions are NOT Swapped" value="0"/>
+        <value name="SWAP" caption="Upper and Lower BFM Regions are Swapped" value="1"/>
+      </value-group>
+      <value-group name="SWAP__BFSLOCK">
+        <value name="UNLOCKED" caption="BFSLOCK and BFSWAP can be written" value="0"/>
+        <value name="LOCKED" caption="BFSLOCK and BFSWAP cannot be written" value="1"/>
+      </value-group>
+      <value-group name="SWAP__PFSWAP">
+        <value name="UNSWAP" caption="Upper and Lower PFM Regions are NOT Swapped" value="0"/>
+        <value name="SWAP" caption="Upper and Lower PFM Regions are Swapped" value="1"/>
+      </value-group>
+      <value-group name="SWAP__PFSLOCK">
+        <value name="UNLOCKED" caption="PFSLOCK and PFSWAP can be written" value="0"/>
+        <value name="LOCKED" caption="PFSLOCK and PFSWAP cannot be written" value="1"/>
+      </value-group>
+      <value-group name="PWP__PWPMIR">
+        <value name="UNMIRROR" caption="PWP settings are NOT Mirrored" value="0"/>
+        <value name="MIRROR" caption="PWP settings are Mirrored" value="1"/>
+      </value-group>
+      <value-group name="PWP__PWPLOCK">
+        <value name="UNLOCKED" caption="This register is Not Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="This register is Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="PWP__PWPEN">
+        <value name="DISABLE" caption="PWP is Not Enabled for the defined region" value="0"/>
+        <value name="ENABLE" caption="PWP is Enabled for the defined region" value="1"/>
+      </value-group>
+      <value-group name="LBWP__LBWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Lower Boot Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Lower Boot Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="LBWP__LBWPLOCK">
+        <value name="UNLOCKED" caption="This register is NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="This register is Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="UBWP__UBWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Upper Boot Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Upper Boot Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="UBWP__UBWPLOCK">
+        <value name="UNLOCKED" caption="This register is NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="This register is Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="UOWP__UO1WPR">
+        <value name="DISABLE" caption="Write Protection for User OTP Page 1 Row &quot;n&quot; is Disabled" value="0"/>
+        <value name="ENABLE" caption="Write Protection for User OTP Page 1 Row &quot;n&quot; is Enabled" value="1"/>
+      </value-group>
+      <value-group name="UOWP__UO1WPRLOCK">
+        <value name="UNLOCKED" caption="UO1WPR[n] &amp;amp; UO1WPRLOCK[n] bits are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="UO1WPR[n] &amp;amp; UO1WPRLOCK[n] bits are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1AWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1WP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__RCWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__VSSWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__TWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enable" value="1"/>
+      </value-group>
+      <value-group name="CWP__COWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1AWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1WPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__RCWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__VSSWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__TWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__COWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+    </module>
+    <module name="FPB" id="SYSTEM_IP" version="1.0.0" caption="Flash Patch and Breakpoint">
+      <register-group name="FPB" caption="Flash Patch and Breakpoint">
+        <register name="FP_CTRL" offset="0x0" rw="RW" size="4" access-size="4" caption="Flash Patch Control Register">
+          <bitfield name="ENABLE" caption="Flash Patch global enable" mask="0x1"/>
+          <bitfield name="KEY" caption="FP_CTRL write-enable key" mask="0x2"/>
+          <bitfield name="NUM_CODE" caption="Number of implemented code comparators bits [3:0]" mask="0xF0"/>
+          <bitfield name="NUM_LIT" caption="Number of literal comparators" mask="0xF00"/>
+          <bitfield name="NUM_CODE_1" caption="Number of implemented code comparators bits [6:4]" mask="0x7000"/>
+          <bitfield name="REV" caption="Revision" mask="0xF0000000"/>
+        </register>
+        <register name="FP_REMAP" offset="0x4" rw="R" size="4" access-size="4" caption="Flash Patch Remap Register">
+          <bitfield name="REMAP" caption="Remap address" mask="0x1FFFFFE0"/>
+          <bitfield name="RMPSPT" caption="Remap supported" mask="0x20000000"/>
+        </register>
+        <register name="FP_COMP" offset="0x8" rw="RW" size="4" access-size="4" count="4" caption="Flash Patch Comparator Register n">
+          <mode name="BREAKPOINT"/>
+          <mode name="DEFAULT"/>
+          <bitfield name="BE" caption="Breakpoint enable" mask="0x1"/>
+          <bitfield modes="DEFAULT" name="FPADDR" caption="Flash Patch address" mask="0x1FFFFFFC"/>
+          <bitfield modes="DEFAULT" name="FE" caption="Flash Patch enable" mask="0x80000000"/>
+          <bitfield modes="BREAKPOINT" name="BPADDR" caption="Breakpoint address" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="FP_LAR" offset="0xFB0" rw="W" size="4" access-size="4" caption="FPB Software Lock Access Register">
+          <bitfield name="KEY" caption="Lock access control" mask="0xFFFFFFFF" values="FP_LAR__KEY"/>
+        </register>
+        <register name="FP_LSR" offset="0xFB4" rw="R" size="4" access-size="4" caption="FPB Software Lock Status Register">
+          <bitfield name="SLI" caption="Software Lock implemented" mask="0x1"/>
+          <bitfield name="SLK" caption="Software Lock status" mask="0x2"/>
+          <bitfield name="nTT" caption="Not thirty-two bit" mask="0x4"/>
+        </register>
+        <register name="FP_DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" initval="0x47701A03" caption="FPB Device Architecture Register">
+          <bitfield name="ARCHPART" caption="Architecture Part" mask="0xFFF"/>
+          <bitfield name="ARCHVER" caption="Architecture Version" mask="0xF000"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF0000"/>
+          <bitfield name="PRESENT" caption="DEVARCH Present" mask="0x100000"/>
+          <bitfield name="ARCHITECT" caption="Architect" mask="0xFFE00000"/>
+        </register>
+        <register name="FP_DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" initval="0x00000000" caption="FPB Device Type Register">
+          <bitfield name="MAJOR" caption="Major type" mask="0xF"/>
+          <bitfield name="SUB" caption="Sub-type" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR4" offset="0xFD0" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 4">
+          <bitfield name="DES_2" caption="JEP106 continuation code" mask="0xF"/>
+          <bitfield name="SIZE" caption="4KB count" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR5" offset="0xFD4" rw="R" size="4" access-size="4" initval="0x00000000" caption="FP Peripheral Identification Register 5"/>
+        <register name="FP_PIDR6" offset="0xFD8" rw="R" size="4" access-size="4" initval="0x00000000" caption="FP Peripheral Identification Register 6"/>
+        <register name="FP_PIDR7" offset="0xFDC" rw="R" size="4" access-size="4" initval="0x00000000" caption="FP Peripheral Identification Register 7"/>
+        <register name="FP_PIDR0" offset="0xFE0" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 0">
+          <bitfield name="PART_0" caption="Part number bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="FP_PIDR1" offset="0xFE4" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 1">
+          <bitfield name="PART_1" caption="Part number bits[11:8]" mask="0xF"/>
+          <bitfield name="DES_0" caption="JEP106 identification code bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR2" offset="0xFE8" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 2">
+          <bitfield name="DES_1" caption="JEP106 identification code bits[6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="JEDEC assignee value is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Component revision" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR3" offset="0xFEC" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 3">
+          <bitfield name="CMOD" caption="Customer Modified" mask="0xF"/>
+          <bitfield name="REVAND" caption="RevAnd" mask="0xF0"/>
+        </register>
+        <register name="FP_CIDR0" offset="0xFF0" rw="R" size="4" access-size="4" initval="0x0000000D" caption="FP Component Identification Register 0">
+          <bitfield name="PRMBL_0" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="FP_CIDR1" offset="0xFF4" rw="R" size="4" access-size="4" initval="0x00000090" caption="FP Component Identification Register 1">
+          <bitfield name="PRMBL_1" caption="CoreSight component identification preamble" mask="0xF"/>
+          <bitfield name="CLASS" caption="CoreSight component class" mask="0xF0"/>
+        </register>
+        <register name="FP_CIDR2" offset="0xFF8" rw="R" size="4" access-size="4" initval="0x00000005" caption="FP Component Identification Register 2">
+          <bitfield name="PRMBL_2" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="FP_CIDR3" offset="0xFFC" rw="R" size="4" access-size="4" initval="0x000000B1" caption="FP Component Identification Register 3">
+          <bitfield name="PRMBL_3" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="FP_LAR__KEY">
+        <value name="UNLOCK" caption="Unlock key value" value="0xC5ACCE55"/>
+      </value-group>
+    </module>
+    <module name="FREQM" id="03707" name2="clk_freqm_u2257_v3" version="3a0" caption="Frequency Meter">
+      <register-group name="FREQM" caption="Frequency Meter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x80" caption="Control A Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run In Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B Register">
+          <bitfield name="START" caption="Start Measurement" mask="0x1"/>
+        </register>
+        <register name="CFGA" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Config A Register">
+          <bitfield name="REFNUM" caption="Number of Reference Clock Cycles" mask="0xFF"/>
+          <bitfield name="MSRSEL" caption="Measurement Clock Selection" mask="0x700" values="CFGA__MSRSEL"/>
+          <bitfield name="DIVREF" caption="Divide Reference Clock" mask="0x8000" values="CFGA__DIVREF"/>
+        </register>
+        <register name="CTRLC" offset="0x4" rw="RW" size="1" initval="0x00" caption="Control C Register">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="CTRLC__WINMODE"/>
+        </register>
+        <register name="EVCTRL" offset="0x6" rw="RW" size="1" initval="0x00" caption="Event Control Register">
+          <bitfield name="STARTEI" caption="Start Measurement Event Input Enable" mask="0x1"/>
+          <bitfield name="STARTINV" caption="Start Measurement Event Invert Enable" mask="0x2"/>
+          <bitfield name="DONEEO" caption="Measurement Done Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear Register">
+          <bitfield name="DONE" caption="Measurement Done Interrupt Disable" mask="0x1"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Disable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set Register">
+          <bitfield name="DONE" caption="Measurement Done Interrupt Enable" mask="0x1"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0xA" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Register">
+          <bitfield name="DONE" caption="Measurement Done" mask="0x1"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0xB" rw="RW" size="1" initval="0x00" caption="Status Register">
+          <bitfield name="BUSY" caption="FREQM Status" mask="0x1"/>
+          <bitfield name="OVF" caption="Sticky Count Value Overflow" mask="0x2"/>
+        </register>
+        <register name="SYNCBUSY" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="VALUE" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Count Value Register">
+          <bitfield name="VALUE" caption="Measurement Value" mask="0xFFFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="CFGA__MSRSEL">
+        <value name="GCLK" caption="GCLK Input Clock" value="0x0"/>
+        <value name="CPU" caption="CPU Input Clock" value="0x1"/>
+      </value-group>
+      <value-group name="CFGA__DIVREF">
+        <value name="DIV1" caption="The reference clock is divided by 1" value="0x0"/>
+        <value name="DIV8" caption="The reference clock is divided by 8" value="0x1"/>
+      </value-group>
+      <value-group name="CTRLC__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="VALUE &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="VALUE &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="WINLT &lt; VALUE &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="!(WINLT &lt; VALUE &lt; WINUT)" value="0x4"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="fuses" name2="fuses" version="1a0" caption="Defines FUSES module data">
+      <register-group name="FUSES_ROMCFG" caption="Defines FUSES module data">
+        <register name="DAL" offset="0x0" rw="RW" size="4" caption="DEVICE ACCESS LEVEL Register">
+          <bitfield name="DAL_CPU" caption="CPU Device Access Level" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FRCFGBROM" offset="0x400" rw="RW" size="4" caption="PRE-BOOT bromc user Options Register">
+          <bitfield name="BCRCDIS" caption="Boot ROM CRC Disable" mask="0x1"/>
+        </register>
+        <register name="FRCFGMBIST" offset="0x408" rw="RW" size="4" caption="PRE-BOOT MBIST user Options Register">
+          <bitfield name="MOBH" caption="MBIST On Boot Enable for HIBERNATE Only Retaining Memory Groups" mask="0xC" values="FRCFGMBIST__MOBH"/>
+          <bitfield name="MOBB" caption="MBIST On Boot Enable for BACKUP/HIBERNATE Retaining Memory Groups" mask="0x30" values="FRCFGMBIST__MOBB"/>
+</register>
+            <register name="KEYVAL_INTCHK0" offset="0x420" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK1" offset="0x424" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK2" offset="0x428" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK3" offset="0x42C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK4" offset="0x430" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK5" offset="0x434" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK6" offset="0x438" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK7" offset="0x43C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL0" offset="0x440" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL1" offset="0x444" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL2" offset="0x448" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL3" offset="0x44C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL4" offset="0x450" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL5" offset="0x454" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL6" offset="0x458" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL7" offset="0x45C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR0" offset="0x460" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR1" offset="0x464" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR2" offset="0x468" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR3" offset="0x46C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR4" offset="0x470" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR5" offset="0x474" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR6" offset="0x478" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR7" offset="0x47C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S0" offset="0x480" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S1" offset="0x484" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S2" offset="0x488" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S3" offset="0x48C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S4" offset="0x490" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S5" offset="0x494" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S6" offset="0x498" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S7" offset="0x49C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR0" offset="0x4A0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR1" offset="0x4A4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR2" offset="0x4A8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR3" offset="0x4AC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR4" offset="0x4B0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR5" offset="0x4B4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR6" offset="0x4B8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR7" offset="0x4BC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS0" offset="0x4C0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS1" offset="0x4C4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS2" offset="0x4C8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS3" offset="0x4CC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS4" offset="0x4D0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS5" offset="0x4D4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS6" offset="0x4D8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS7" offset="0x4DC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG0" offset="0x4E0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG1" offset="0x4E4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG2" offset="0x4E8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG3" offset="0x4EC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG4" offset="0x4F0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG5" offset="0x4F4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG6" offset="0x4F8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG7" offset="0x4FC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_0" offset="0x500" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_1" offset="0x504" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_2" offset="0x508" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_3" offset="0x50C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_4" offset="0x510" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_5" offset="0x514" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_6" offset="0x518" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_7" offset="0x51C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_0" offset="0x520" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_1" offset="0x524" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_2" offset="0x528" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_3" offset="0x52C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_4" offset="0x530" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_5" offset="0x534" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_6" offset="0x538" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_7" offset="0x53C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL0" offset="0x540" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL1" offset="0x544" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL2" offset="0x548" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL3" offset="0x54C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL4" offset="0x550" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL5" offset="0x554" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL6" offset="0x558" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL7" offset="0x55C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="PUF_AC" offset="0xC00" rw="RW" size="4" count="249" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="PUF_AC" caption="" mask="0xFFFFFFFF"/>
+            </register>
+        </register-group>
+        <register-group name="FUSES_BOOTCFG1" caption="Defines FUSES module data">
+            <register name="DEVSIGN" offset="0xC" rw="RW" size="4" initval="0xFFFFFFFF" caption="DEVSIGN">
+            <bitfield name="SEQ" caption="Sequence number" mask="0x0000FFFF"/>
+            <bitfield name="SEQBAR" caption="Sequence number BAR" mask="0xFFFF0000"/>
+            </register>
+            <register name="BOOT_FLAG" offset="0x800" rw="RW" size="4" initval="0xFFFFFFF9" caption="BOOT CODE FLAGS REGISTER">
+            <bitfield name="PUFRETRY" caption="PUF Retry" mask="0x2"/>
+            <bitfield name="PUFSTARTUP" caption="PUF Start Up Mode" mask="0x4"/>
+            <bitfield name="DICEDIS" caption="Device Identifier Composition Engine Disable" mask="0x8"/>
+            <bitfield name="BOOTMODE" caption="Boot Mode" mask="0x10"/>
+            <bitfield name="RAM_INIT_ENB" caption="RAM ECC Enable" mask="0x40"/>
+            <bitfield name="PUFSCORE" caption="PUF Score Value" mask="0x700" values="BOOT_FLAG__PUFSCORE"/>
+            </register>
+            <register name="DICE_CDI_INDEX" offset="0x810" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="DICE_CDI_INDEX" caption="" mask="0x7F"/>
+            </register>
+            <register name="DICE_FW_HASH_INDEX" offset="0x814" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="DICE_FW_HASH_INDEX" caption="" mask="0x7F"/>
+            </register>
+            <register name="BOOT_GPIOSEL" offset="0x818" rw="RW" size="4" initval="0xFFFFFFFF" caption="BOOT EXTERNAL NOTIFICATION IO PIN REGISTER">
+            <bitfield name="GPIOPINSEL" caption="Selects IO Port Pin for Boot External Notification Signal" mask="0x1F"/>
+            <bitfield name="GPIOPORTSEL" caption="Selects IO Port for Boot External Notification Signal" mask="0x1E0"/>
+            <bitfield name="FLTPOL" caption="Selects IO Port for Boot External Notification Signal" mask="0x200"/>
+            <bitfield name="FLTODRAIN" caption="Open Drain Control for Boot External Notification Signal" mask="0x800"/>
+            <bitfield name="FLTSLEWLIM" caption="Selects Driver Slew Rate Selection for Boot External Notification Signal" mask="0x3000"/>
+            </register>
+            <register name="H2PB0_NONSECCLRA" offset="0x81C" rw="RW" size="4" initval="0xFFFFFFFE" caption="Non-Security Clear Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="H2PB0_NONSECSETA" offset="0x820" rw="RW" size="4" initval="0x00000001" caption="Non-Security SET Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="PAC_WRCTRL_H2PB0" offset="0x830" rw="RW" size="4" initval="0x00000013" caption="Write Control Register">
+            <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+            <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="PAC_WRCTRL_H2PB0__KEY"/>
+            </register>
+            <register name="H2PB1_NONSECCLRA" offset="0x834" rw="RW" size="4" initval="0xFFFFFFFF" caption="Non-Security Clear Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="H2PB1_NONSECSETA" offset="0x838" rw="RW" size="4" initval="0x00000000" caption="Non-Security SET Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="PAC_WRCTRL_H2PB1" offset="0x848" rw="RW" size="4" initval="0x0000002E" caption="Write Control Register">
+            <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+            <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="PAC_WRCTRL_H2PB1__KEY"/>
+            </register>
+            <register name="H2PB2_NONSECCLRA" offset="0x84C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Non-Security Clear Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="H2PB2_NONSECSETA" offset="0x850" rw="RW" size="4" initval="0x00000000" caption="Non-Security SET Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="PAC_WRCTRL_H2PB2" offset="0x860" rw="RW" size="4" initval="0x0000002F" caption="Write Control Register">
+            <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+            <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="PAC_WRCTRL_H2PB2__KEY"/>
+            </register>
+            <register name="IDAU_RCTRL_BFM" offset="0x864" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control BFM Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control BFM Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control BFM Command" mask="0xFF000000" values="IDAU_RCTRL_BFM_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control BFM Command" mask="0xFF000000" values="IDAU_RCTRL_BFM_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_RCTRL_PFMANS" offset="0x868" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control PFMANS Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control PFMAN Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control PFMAN Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANS_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control PFMAN Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANS_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_RCTRL_PFMANSC" offset="0x86C" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control PFMANSC Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control PFMANSC Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control PFMANSC Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANSC_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control PFMANSC Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANSC_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_RCTRL_DRM" offset="0x870" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control DRM Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control DRM Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control DRM Command" mask="0xFF000000" values="IDAU_RCTRL_DRM_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control DRM Command" mask="0xFF000000" values="IDAU_RCTRL_DRM_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_CTRL_EN" offset="0x874" rw="RW" size="4" initval="0xA5010000" caption="Control">
+            <bitfield name="CMD" caption="IDAU Enable Command Register" mask="0xFFFF0000" values="IDAU_CTRL_EN__CMD"/>
+            </register>
+            <register name="IDAU_CTRL_WLCK" offset="0x878" rw="RW" size="4" initval="0xFFFFFFFF" caption="Control">
+            <bitfield name="CMD" caption="IDAU Write Lock Command Register" mask="0xFFFF0000" values="IDAU_CTRL_WLCK__CMD"/>
+            </register>
+            <register name="FCW_CWP" offset="0x87C" rw="RW" size="4" initval="0x00000000" caption="CFM Page Write Protect REGISTER">
+            <bitfield name="BC1AWP" caption="Panel 1 Write Protect BootCfg1A" mask="0x1" values="FCW_CWP__BC1AWP"/>
+            <bitfield name="BC1WP" caption="Panel 1 Write Protect BootCfg1" mask="0x4" values="FCW_CWP__BC1WP"/>
+            <bitfield name="RCWP" caption="Panel 1 Write Protect ROMCfg" mask="0x8" values="FCW_CWP__RCWP"/>
+            <bitfield name="VSSWP0" caption="Panel 1 Write Protect VSSn" mask="0x10" values="FCW_CWP__VSSWP"/>
+            <bitfield name="VSSWP1" caption="Panel 1 Write Protect VSSn" mask="0x20" values="FCW_CWP__VSSWP"/>
+            <bitfield name="BC1AWPLOCK" caption="Panel 1 Lock Write Protection BootCfg1A" mask="0x10000" values="FCW_CWP__BC1AWPLOCK"/>
+            <bitfield name="BC1WPLOCK" caption="Panel 1 Lock Write Protection BootCfg1" mask="0x40000" values="FCW_CWP__BC1WPLOCK"/>
+            <bitfield name="RCWPLOCK" caption="Panel 1 Lock Write Protection ROMCfg" mask="0x80000" values="FCW_CWP__RCWPLOCK"/>
+            <bitfield name="VSSWPLOCK0" caption="Panel 1 Lock Write Protection VSSn" mask="0x100000" values="FCW_CWP__VSSWPLOCK"/>
+            <bitfield name="VSSWPLOCK1" caption="Panel 1 Lock Write Protection VSSn" mask="0x200000" values="FCW_CWP__VSSWPLOCK"/>
+            </register>
+            <register name="FCR_CRP" offset="0x880" rw="RW" size="4" initval="0x00000000" caption="CFM Page Read Protection Register">
+            <bitfield name="BC1ARP" caption="Panel 1 Read Protect BootCfg1A" mask="0x1" values="FCR_CRP__BC1ARP"/>
+            <bitfield name="BC1RP" caption="Panel 1 Read Protect BootCfg1" mask="0x4" values="FCR_CRP__BC1RP"/>
+            <bitfield name="RCRP" caption="Panel 1 Read Protect ROMCfg" mask="0x8" values="FCR_CRP__RCRP"/>
+            <bitfield name="VSSRP0" caption="Panel 1 Read Protect VSSn" mask="0x10" values="FCR_CRP__VSSRP"/>
+            <bitfield name="VSSRP1" caption="Panel 1 Read Protect VSSn" mask="0x20" values="FCR_CRP__VSSRP"/>
+            <bitfield name="BC1ARPLOCK" caption="Panel 1 Lock Read Protection BootCfg1A" mask="0x10000" values="FCR_CRP__BC1ARPLOCK"/>
+            <bitfield name="BC1RPLOCK" caption="Panel 1 Lock Read Protection BootCfg1" mask="0x40000" values="FCR_CRP__BC1RPLOCK"/>
+            <bitfield name="RCRPLOCK" caption="Panel 1 Lock Read Protection ROMCfg" mask="0x80000" values="FCR_CRP__RCRPLOCK"/>
+            <bitfield name="VSSRPLOCK0" caption="Panel 1 Lock Read Protection VSSn" mask="0x100000" values="FCR_CRP__VSSRPLOCK"/>
+            <bitfield name="VSSRPLOCK1" caption="Panel 1 Lock Read Protection VSSn" mask="0x200000" values="FCR_CRP__VSSRPLOCK"/>
+            </register>
+            <register name="FCR_ECCCTRL" offset="0x884" rw="RW" size="4" initval="0x00000070" caption="ECC Control REGISTER">
+            <bitfield name="ECCCTL" caption="NVM ECC Mode Control - restricts one or more NVMOPs" mask="0x30" values="FCR_ECCCTRL__ECCCTL"/>
+            <bitfield name="ECCUNLCK" caption="NVM ECC Mode Control Unlock" mask="0x40" values="FCR_ECCCTRL__ECCUNLCK"/>
+            <bitfield name="SECCNT" caption="Flash SEC Count" mask="0xFF00"/>
+            </register>
+            <register name="SUPC_BRCFGUSMOR_BOR" offset="0x888" rw="RW" size="4" initval="0x00000000" caption="Boot Rom Configurable SMOR User CFG BOR register">
+            <bitfield name="HYST_BOR_VDDIO" caption="Refer to pwr_smor_[nn]_v2 DOS document for details." mask="0x1" values="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDIO"/>
+            <bitfield name="BOR_TRIP_VDDIO" caption="Nominal BOR Trip, Refer to pwr_smor_[nn]_v2 DOS document for details." mask="0x6" values="SUPC_BRCFGUSMOR_BOR__BOR_TRIP_VDDIO"/>
+            <bitfield name="HYST_BOR_VDDREG" caption="Refer to pwr_smor_[nn]_v2 DOS document for details." mask="0x400" values="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDREG"/>
+            </register>
+            <register name="SUPC_BRCFGUDSSMOR" offset="0x890" rw="RW" size="4" initval="0x00000000" caption="Boot Rom Configurable DSSMOR User CFG register">
+            <bitfield name="BOR_HYST" caption="Refer to pwr_smor_ds_[nn]_v2 DOS document for details." mask="0x1" values="SUPC_BRCFGUDSSMOR__BOR_HYST"/>
+            <bitfield name="BOR_TRIP" caption="Nominal BOR Trip, Refer to pwr_smor_ds_[nn]_v2 DOS document for details." mask="0x6" values="SUPC_BRCFGUDSSMOR__BOR_TRIP"/>
+            </register>
+            <register name="SUPC_BRCFGUCP0" offset="0x894" rw="RW" size="4" initval="0x00000001" caption="Boot Rom Configurable CHARGE PUMP User CFG register">
+            <bitfield name="CP" caption="Refer to vreg_chrg_pump_v4 DOS document for details." mask="0xF" values="SUPC_BRCFGUCP0__CP"/>
+            </register>
+            <register name="WDT_SETUP" offset="0x898" rw="RW" size="4" initval="0x00000000" caption="">
+            <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+            <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+            <bitfield name="RUNSTDBY" caption="Run During Standby" mask="0x40"/>
+            <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+            <bitfield name="PER" caption="Time-Out Period" mask="0xF00" values="WDT_SETUP__PER"/>
+            <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF000" values="WDT_SETUP__WINDOW"/>
+            <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF0000" values="WDT_SETUP__EWOFFSET"/>        </register>
+      </register-group>
+      <register-group name="FUSES_CALOTP" caption="Defines FUSES module data">
+        <register name="F1RR" offset="0x0" rw="R" size="4" caption="PANEL 0 REDUNDANCY RECORD 1-0 Register">
+          <bitfield name="RR0ADDR" caption="Redundancy Replaced Page Address" mask="0x7F"/>
+          <bitfield name="RR0DIS" caption="Redundancy Record 0 enabled" mask="0x8000" values="F1RR__RR0DIS"/>
+          <bitfield name="RR1ADDR" caption="Redundancy Replaced Page Address" mask="0x7F0000"/>
+          <bitfield name="RR1DIS" caption="Redundancy Record 1 enabled" mask="0x80000000" values="F1RR__RR1DIS"/>
+        </register>
+        <register name="FCCFG0" offset="0x80" rw="R" size="4" caption="Calibration Configuration 0 Register">
+          <bitfield name="CFG_SMOR0" caption="SMOR configuration bits" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG1" offset="0x84" rw="R" size="4" caption="Calibration Configuration 1 Register">
+          <bitfield name="CFG_SMOR1" caption="SMOR configuration bits" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG8" offset="0xA0" rw="R" size="4" caption="Calibration Configuration 8 Register">
+          <bitfield name="CFG_DS_SMOR_REF" caption="DSSMOR configuration bits" mask="0xFFFF"/>
+          <bitfield name="CFG_DS_SMOR_CLK" caption="DSSMOR configuration bits" mask="0xFFFF0000"/>
+        </register>
+        <register name="FCCFG16" offset="0xC0" rw="R" size="4" caption="Calibration Configuration 16 Register">
+          <bitfield name="CFG_DFLL48M" caption="Comparator configuration bits" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG17" offset="0xC4" rw="R" size="4" caption="Calibration Configuration 17 Register">
+          <bitfield name="CFG_XTAL_HF" caption="Crystal Oscillator calibration configuration bits" mask="0xFFFF"/>
+        </register>
+        <register name="FCCFG24" offset="0xE0" rw="R" size="4" caption="Calibration Configuration 24 Register">
+          <bitfield name="CFG_CALVREGSW0" caption="99 ma VREG Calibration configuration bits" mask="0xFFFF"/>
+        </register>
+        <register name="FCCFG27" offset="0xEC" rw="R" size="4" caption="Calibration Configuration 27 Register">
+          <bitfield name="CFG_CALVREGRAM" caption="50 ma VREG Calibration configuration bits" mask="0xFFFF0000"/>
+        </register>
+        <register name="FCCFG28" offset="0xF0" rw="R" size="4" caption="Calibration Configuration 28 Register">
+          <bitfield name="CALCP" caption="Charge Pump Calibration  configuration bits for all charge pumps" mask="0xF"/>
+          <bitfield name="CALSUPC" caption="RPMU / SUPC configuration bits" mask="0xFF00"/>
+        </register>
+        <register name="FCCFG29" offset="0xF4" rw="R" size="4" caption="Calibration Configuration 29 Register">
+          <bitfield name="CALUSERLDO" caption="User LDO Calibration  configuration bits" mask="0xFF"/>
+        </register>
+        <register name="FCCFG32" offset="0x100" rw="R" size="4" caption="DSU Device Configuration 0 Register (DEVID)">
+          <bitfield name="PFM_SZ" caption="Program Flash Memory (PFM) Size on Device" mask="0xF" values="FCCFG32__PFM_SZ"/>
+          <bitfield name="DRM_SZ" caption="Data Ram Memory (DRM) Size on Device" mask="0xFF00" values="FCCFG32__DRM_SZ"/>
+          <bitfield name="FPACKAGE" caption="Number of Pins present on the Package" mask="0xF0000" values="FCCFG32__FPACKAGE"/>
+          <bitfield name="DEVSEL" caption="Device Variant Configuration" mask="0xFF000000"/>
+        </register>
+        <register name="FCCFG33" offset="0x104" rw="R" size="4" caption="DSU Device Configuration 1 Register">
+          <bitfield name="ME_HSM" caption="Module enables for Variant configuration" mask="0x80" values="FCCFG33__ME_HSM"/>
+          <bitfield name="ME_TCC0" caption="Module enables for Variant configuration" mask="0x100" values="FCCFG33__ME_TCC0"/>
+          <bitfield name="ME_TCC1" caption="Module enables for Variant configuration" mask="0x200" values="FCCFG33__ME_TCC1"/>
+          <bitfield name="ME_TCC2" caption="Module enables for Variant configuration" mask="0x400" values="FCCFG33__ME_TCC2"/>
+          <bitfield name="ME_TCC3" caption="Module enables for Variant configuration" mask="0x800" values="FCCFG33__ME_TCC3"/>
+          <bitfield name="ME_TCC4" caption="Module enables for Variant configuration" mask="0x1000" values="FCCFG33__ME_TCC4"/>
+          <bitfield name="ME_TCC5" caption="Module enables for Variant configuration" mask="0x2000" values="FCCFG33__ME_TCC5"/>
+          <bitfield name="ME_TCC6" caption="Module enables for Variant configuration" mask="0x4000" values="FCCFG33__ME_TCC6"/>
+          <bitfield name="ME_SERCOM0" caption="Module enables for Variant configuration" mask="0x40000" values="FCCFG33__ME_SERCOM0"/>
+          <bitfield name="ME_SERCOM1" caption="Module enables for Variant configuration" mask="0x80000" values="FCCFG33__ME_SERCOM1"/>
+          <bitfield name="ME_SERCOM2" caption="Module enables for Variant configuration" mask="0x100000" values="FCCFG33__ME_SERCOM2"/>
+          <bitfield name="ME_SERCOM3" caption="Module enables for Variant configuration" mask="0x200000" values="FCCFG33__ME_SERCOM3"/>
+          <bitfield name="ME_SERCOM4" caption="Module enables for Variant configuration" mask="0x400000" values="FCCFG33__ME_SERCOM4"/>
+          <bitfield name="ME_SERCOM5" caption="Module enables for Variant configuration" mask="0x800000" values="FCCFG33__ME_SERCOM5"/>
+          <bitfield name="ME_PTC" caption="Module enables for Variant configuration" mask="0x10000000" values="FCCFG33__ME_PTC"/>
+        </register>
+        <register name="FCCFG34" offset="0x108" rw="R" size="4" caption="DSU Device Configuration 2 Register">
+          <bitfield name="ME_CAN0" caption="Module enables for Variant configuration" mask="0x1" values="FCCFG34__ME_CAN0"/>
+          <bitfield name="ME_CAN1" caption="Module enables for Variant configuration" mask="0x2" values="FCCFG34__ME_CAN1"/>
+          <bitfield name="ME_USBFS" caption="Module enables for Variant configuration" mask="0x200" values="FCCFG34__ME_USBFS"/>
+          <bitfield name="ME_DPA" caption="Module enables for Variant configuration" mask="0x800000" values="FCCFG34__ME_DPA"/>
+          <bitfield name="ME_TRAM" caption="Module enables for Variant configuration" mask="0x40000000" values="FCCFG34__ME_TRAM"/>
+          <bitfield name="ME_PUF" caption="Module enables for Variant configuration" mask="0x80000000" values="FCCFG34__ME_PUF"/>
+        </register>
+        <register name="FCCFG49" offset="0x144" rw="R" size="4" caption="Calibration Configuration 49 Register">
+          <bitfield name="RAMC_EMAW" caption="Write Time Extra Margin Adjust" mask="0x3" values="FCCFG49__RAMC_EMAW"/>
+          <bitfield name="RAMC_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x1C" values="FCCFG49__RAMC_EMA"/>
+          <bitfield name="RAMAB_EMAW" caption="Write Time Extra Margin Adjust" mask="0xC0"/>
+          <bitfield name="RAMAB_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x700"/>
+          <bitfield name="TRAM_EMAW" caption="Write Time Extra Margin Adjust" mask="0x3000"/>
+          <bitfield name="TRAM_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x1C000"/>
+          <bitfield name="TRAM_EMAS" caption="Sense Amp Extra Margin Adjust" mask="0x20000" values="FCCFG49__TRAM_EMAS"/>
+          <bitfield name="BROM_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x700000"/>
+          <bitfield name="PUF_EMAW" caption="Write Time Extra Margin Adjust" mask="0x3000000"/>
+          <bitfield name="PUF_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x1C000000"/>
+          <bitfield name="PUF_EMAS" caption="Sense Amp Extra Margin Adjust" mask="0x20000000" values="FCCFG49__PUF_EMAS"/>
+        </register>
+        <register name="FCCFG56" offset="0x160" rw="R" size="4" caption="Calibration Configuration 56 Register">
+          <bitfield name="BRINGOSC" caption="SUPC Ring-osc depth" mask="0x3" values="FCCFG56__BRINGOSC"/>
+          <bitfield name="DIS_BOR12_RAMON" caption="Disable BOR12 (VREGRAM comparator) when RAM are turned ON when leaving sleep mode" mask="0x10"/>
+          <bitfield name="DIS_BOR12_VSCALING" caption="Disable BOR12 (VREGRAM comparator) when down voltage scaling is on going from 1.2v to 0.8v to workaround VREG undershoot issue" mask="0x20"/>
+          <bitfield name="VLP2FPST" caption="Vreg Low Power to Full Power Stabilization Time" mask="0x30000" values="FCCFG56__VLP2FPST"/>
+          <bitfield name="VLPMST" caption="Vreg LP Mode Stabilization Time" mask="0xC0000" values="FCCFG56__VLPMST"/>
+          <bitfield name="VTONST" caption="Vreg Turned On Stabilization Time" mask="0x300000" values="FCCFG56__VTONST"/>
+          <bitfield name="VPDDST" caption="Vreg Pull Down Disable Stabilization Time" mask="0xC00000" values="FCCFG56__VPDDST"/>
+          <bitfield name="VDVSST" caption="Vreg Down Voltage Scaling Stabilization Time" mask="0x3000000" values="FCCFG56__VDVSST"/>
+        </register>
+        <register name="FCCFG57" offset="0x164" rw="R" size="4" caption="Calibration Configuration 57 Register">
+          <bitfield name="DLYVAL" caption="Delay Value" mask="0x7F"/>
+          <bitfield name="IGNACK" caption="Ignore Acknowledge" mask="0x80" values="FCCFG57__IGNACK"/>
+        </register>
+        <register name="FCCFG58" offset="0x168" rw="R" size="4" caption="Calibration Configuration 58 Register">
+          <bitfield name="BRINGOSC" caption="Backup Ring Oscillator Size Depth" mask="0x3" values="FCCFG58__BRINGOSC"/>
+        </register>
+        <register name="FCCFG59" offset="0x16C" rw="R" size="4" caption="Calibration Configuration 59 Register">
+          <bitfield name="IDAU_EN" caption="IDAU Enabled" mask="0x1" values="FCCFG59__IDAU_EN"/>
+        </register>
+        <register name="FCCFG60" offset="0x170" rw="R" size="4" caption="Calibration Configuration 60 Register">
+          <bitfield name="PUFRAMDNTIME" caption="PUF RAM Power Down Delay Time" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG61" offset="0x174" rw="R" size="4" caption="Calibration Configuration 61 Register">
+          <bitfield name="PUFRAMUPTIME" caption="PUF RAM Power Up Delay Time" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG64" offset="0x180" rw="R" size="4" caption="Calibration Configuration 64 Register">
+          <bitfield name="PTC_CALIB_PTC_IBIAS_TRIM" caption="PTC IBIAS TRIM" mask="0x7"/>
+          <bitfield name="PTC_CALIB_PTAT_EN" caption="Enable PTAT current" mask="0x8"/>
+          <bitfield name="PTC_CALIB_EXT_IBIAS_EN" caption="Enable External Bias" mask="0x10"/>
+        </register>
+        <register name="FCCFG65" offset="0x184" rw="R" size="4" caption="Calibration Configuration 65 Register">
+          <bitfield name="EN_CMBF" caption="Enable Common Mode Power Cycling" mask="0x1"/>
+          <bitfield name="EN_DITHER" caption="Enable Dithering" mask="0x4"/>
+          <bitfield name="DIS_FAZ" caption="First Auto Zeroing" mask="0x8"/>
+          <bitfield name="DIS_SAZ" caption="Second Auto Zeroing" mask="0x10"/>
+          <bitfield name="DIS_LAZ" caption="Current Auto Zeroing" mask="0x20"/>
+          <bitfield name="EN_RDAC" caption="RDAC Duty Cycle" mask="0x40"/>
+          <bitfield name="DBG_SEL" caption="Enable Test Output" mask="0x80"/>
+          <bitfield name="SEL_DEL" caption="Select Value to comp_out" mask="0x100"/>
+          <bitfield name="T1_DELAY" caption="Programmable delay, selects the delay between regen and latch" mask="0x600"/>
+          <bitfield name="TCLK_DIV" caption="Programmable divider for adc_clk_div. The division ratio is 256, 128, 64,32, and 16 going from MSB to LSB." mask="0xF800"/>
+          <bitfield name="IADC_1" caption="Controls the current consumption for of the whole ADC" mask="0x300000"/>
+          <bitfield name="IADC_2" caption="Controls the current consumption for of the whole ADC." mask="0xC00000"/>
+          <bitfield name="ICMP_1" caption="Controls the bias current for 1 stage of the comparator. This will control the resolution needed by comparator. More current means less time but at expense of gain." mask="0x3000000"/>
+          <bitfield name="ICMP_2" caption="Controls the bias current for 2 stage of the comparator. This will control the resolution needed by comparator. More current means less time but at expense of gain." mask="0xC000000"/>
+          <bitfield name="ICMBF" caption="Controls the bias current for Common mode buffer amplifier (CMBF)" mask="0x30000000"/>
+          <bitfield name="EN_ATEST" caption="Enable analog test signals" mask="0x40000000"/>
+          <bitfield name="EN_EXT_BIAS" caption="Internal switched capacitor bias current allows to make the bias current proportional to conversion frequency." mask="0x80000000"/>
+        </register>
+        <register name="FCCFG66" offset="0x188" rw="R" size="4" caption="Calibration Configuration 66 Register">
+          <bitfield name="AC_CONFIG" caption="Comparator 0 Calibration Configuration bits.'" mask="0xF"/>
+        </register>
+        <register name="FCCFG68" offset="0x190" rw="R" size="4" caption="Calibration Configuration 68 Register">
+          <bitfield name="TRANSP" caption="USB PAD P Driver Configuration bits.'" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB PAD N Driver Configuration bits.'" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB PAD Rise/Fall Configuration bits.'" mask="0x7000"/>
+        </register>
+      </register-group>
+      <value-group name="FRCFGMBIST__MOBH">
+        <value name="ENABLED_ANY" caption="MOB runs after any non-BACKUP/HIBERNATE exit reset" value="1"/>
+        <value name="ENABLED_POR" caption="MOB runs only after a POR" value="2"/>
+        <value name="DISABLED" caption="MOB Disabled" value="3"/>
+</value-group>
+        <value-group name="BOOT_FLAG__PUFSCORE">
+            <value name="0" caption="0" value="0"/>
+            <value name="1" caption="1" value="1"/>
+            <value name="2" caption="2" value="2"/>
+            <value name="3" caption="3" value="3"/>
+            <value name="4" caption="4" value="4"/>
+            <value name="5" caption="5" value="5"/>
+            <value name="6" caption="6" value="6"/>
+            <value name="7" caption="7" value="7"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB0__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB1__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB2__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_EN__CMD">
+            <value name="ENABLE" caption="Module Enable" value="0xA501"/>
+            <value name="DISABLE" caption="Module Disable" value="0xA502"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_WLCK__CMD">
+            <value name="WLCK" caption="Write Lock" value="0xA503"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCCTL">
+            <value name="STRICT" caption="ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)" value="0"/>
+            <value name="DYNAMIC" caption="Dynamic Writes with Dynamic Reads" value="1"/>
+            <value name="ECC" caption="ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)" value="2"/>
+            <value name="DISABLE" caption="Dynamic Writes with No Error Check Reads" value="3"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCUNLCK">
+            <value name="LOCKED" caption="ECCUNLCK and ECCCTL[1:0] cannot be written" value="0"/>
+            <value name="UNLOCKED" caption="ECCUNLCK and ECCCTL[1:0] can be written" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDIO">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__BOR_TRIP_VDDIO">
+            <value name="0" caption="1.68V (default)" value="0"/>
+            <value name="1" caption="2.2V" value="1"/>
+            <value name="2" caption="2.64V" value="2"/>
+            <value name="3" caption="2.93V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDREG">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_HYST">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_TRIP">
+            <value name="0" caption="1.61V (default)" value="0"/>
+            <value name="1" caption="2.12V" value="1"/>
+            <value name="2" caption="2.55V" value="2"/>
+            <value name="3" caption="2.8V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUCP0__CP">
+            <value name="0" caption="Clock gating trip optimized for low output threshold voltage (3.01V)" value="0"/>
+            <value name="1" caption="Clock gating trip optimized for high output threshold voltage (3.2V) (default)" value="1"/>
+        </value-group>
+        <value-group name="WDT_SETUP__PER">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__WINDOW">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__EWOFFSET">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>      </value-group>
+      <value-group name="FRCFGMBIST__MOBB">
+        <value name="ENABLED_ANY" caption="MOB runs after any non-BACKUP/HIBERNATE exit reset" value="1"/>
+        <value name="ENABLED_POR" caption="MOB runs only after a POR" value="2"/>
+        <value name="DISABLED" caption="MOB Disabled" value="3"/>
+</value-group>
+        <value-group name="BOOT_FLAG__PUFSCORE">
+            <value name="0" caption="0" value="0"/>
+            <value name="1" caption="1" value="1"/>
+            <value name="2" caption="2" value="2"/>
+            <value name="3" caption="3" value="3"/>
+            <value name="4" caption="4" value="4"/>
+            <value name="5" caption="5" value="5"/>
+            <value name="6" caption="6" value="6"/>
+            <value name="7" caption="7" value="7"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB0__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB1__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB2__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_EN__CMD">
+            <value name="ENABLE" caption="Module Enable" value="0xA501"/>
+            <value name="DISABLE" caption="Module Disable" value="0xA502"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_WLCK__CMD">
+            <value name="WLCK" caption="Write Lock" value="0xA503"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCCTL">
+            <value name="STRICT" caption="ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)" value="0"/>
+            <value name="DYNAMIC" caption="Dynamic Writes with Dynamic Reads" value="1"/>
+            <value name="ECC" caption="ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)" value="2"/>
+            <value name="DISABLE" caption="Dynamic Writes with No Error Check Reads" value="3"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCUNLCK">
+            <value name="LOCKED" caption="ECCUNLCK and ECCCTL[1:0] cannot be written" value="0"/>
+            <value name="UNLOCKED" caption="ECCUNLCK and ECCCTL[1:0] can be written" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDIO">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__BOR_TRIP_VDDIO">
+            <value name="0" caption="1.68V (default)" value="0"/>
+            <value name="1" caption="2.2V" value="1"/>
+            <value name="2" caption="2.64V" value="2"/>
+            <value name="3" caption="2.93V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDREG">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_HYST">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_TRIP">
+            <value name="0" caption="1.61V (default)" value="0"/>
+            <value name="1" caption="2.12V" value="1"/>
+            <value name="2" caption="2.55V" value="2"/>
+            <value name="3" caption="2.8V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUCP0__CP">
+            <value name="0" caption="Clock gating trip optimized for low output threshold voltage (3.01V)" value="0"/>
+            <value name="1" caption="Clock gating trip optimized for high output threshold voltage (3.2V) (default)" value="1"/>
+        </value-group>
+        <value-group name="WDT_SETUP__PER">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__WINDOW">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__EWOFFSET">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>      </value-group>
+      <value-group name="F1RR__RR0DIS">
+        <value name="0" caption="FCR maps the redundant page 0 into the address defined by RR0ADDR" value="0"/>
+        <value name="1" caption="Redundant page 0 mapping is Disabled" value="1"/>
+      </value-group>
+      <value-group name="F1RR__RR1DIS">
+        <value name="0" caption="FCR maps the redundant page 1 into the address defined by RR1ADDR" value="0"/>
+        <value name="1" caption="Redundant page 1 mapping is Disabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG32__PFM_SZ">
+        <value name="6" caption="512KB" value="6"/>
+      </value-group>
+      <value-group name="FCCFG32__DRM_SZ">
+        <value name="0" caption="Rsvd" value="0"/>
+        <value name="1" caption="128KB" value="1"/>
+      </value-group>
+      <value-group name="FCCFG32__FPACKAGE">
+        <value name="5" caption="48 pins" value="5"/>
+        <value name="6" caption="64 pins" value="6"/>
+        <value name="7" caption="Rsvd" value="7"/>
+        <value name="8" caption="100 pins" value="8"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_HSM">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC0">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC1">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC2">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC3">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC4">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC5">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC6">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM0">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM1">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM2">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM3">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM4">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM5">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_PTC">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_CAN0">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_CAN1">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_USBFS">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_DPA">
+        <value name="0" caption="DPA is Disabled" value="0"/>
+        <value name="1" caption="DPA functions in HSM is Operational" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_TRAM">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_PUF">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG49__RAMC_EMAW">
+        <value name="0" caption="Slowest Access" value="0"/>
+        <value name="1" caption="" value="1"/>
+        <value name="2" caption="" value="2"/>
+        <value name="3" caption="Fastest Access; Default (reset)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG49__RAMC_EMA">
+        <value name="0" caption="" value="0"/>
+        <value name="1" caption="" value="1"/>
+        <value name="2" caption="Slowest Access" value="2"/>
+        <value name="3" caption="" value="3"/>
+        <value name="4" caption="" value="4"/>
+        <value name="5" caption="Fastest Access" value="5"/>
+        <value name="6" caption="" value="6"/>
+        <value name="7" caption="Default (reset)" value="7"/>
+      </value-group>
+      <value-group name="FCCFG49__TRAM_EMAS">
+        <value name="0" caption="Sense Amp Pulse Not Extended" value="0"/>
+        <value name="1" caption="Sense Amp Pulse Extended; Default (reset)" value="1"/>
+      </value-group>
+      <value-group name="FCCFG49__PUF_EMAS">
+        <value name="0" caption="Sense Amp Pulse Not Extended" value="0"/>
+        <value name="1" caption="Sense Amp Pulse Extended; Default (reset)" value="1"/>
+      </value-group>
+      <value-group name="FCCFG56__BRINGOSC">
+        <value name="0" caption="Ring oscillator depth is default (DLY0)" value="0"/>
+        <value name="1" caption="Ring oscillator depth is default + 1 ORDLY15 (DLY1)" value="1"/>
+        <value name="2" caption="Ring oscillator depth is default + 2 ORDLY15 (DLY2)" value="2"/>
+        <value name="3" caption="Ring oscillator depth is default + 3 ORDLY15 (DLY3)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VLP2FPST">
+        <value name="0" caption="5us -32 clock cycles based on 6Mhz clock (5US)" value="0"/>
+        <value name="1" caption="10us -64 clock cycles based on 6Mhz clock (10US)" value="1"/>
+        <value name="2" caption="21us -128 clock cycles based on 6Mhz clock (21US)" value="2"/>
+        <value name="3" caption="1.3us -8 clock cycles based on 6Mhz clock (1US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VLPMST">
+        <value name="0" caption="1.3us -8 clock cycles based on 6Mhz clock (1US)" value="0"/>
+        <value name="1" caption="2.6us -16 clock cycles based on 6Mhz clock (2US)" value="1"/>
+        <value name="2" caption="5us -32 clock cycles based on 6Mhz clock (5US)" value="2"/>
+        <value name="3" caption="0.166us -1 clock cycles based on 6Mhz clock (0US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VTONST">
+        <value name="0" caption="31us -192 clock cycles based on 6Mhz clock (31US)" value="0"/>
+        <value name="1" caption="42us -256 clock cycles based on 6Mhz clock (42US)" value="1"/>
+        <value name="2" caption="84us -512 clock cycles based on 6Mhz clock (84US)" value="2"/>
+        <value name="3" caption="10.6us -64 clock cycles based on 6Mhz clock (10US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VPDDST">
+        <value name="0" caption="21us -128 clock cycles based on 6Mhz clock (21US)" value="0"/>
+        <value name="1" caption="42us -256 clock cycles based on 6Mhz clock (42US)" value="1"/>
+        <value name="2" caption="84us -512 clock cycles based on 6Mhz clock (84US)" value="2"/>
+        <value name="3" caption="10.6us -64 clock cycles based on 6Mhz clock (10US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VDVSST">
+        <value name="0" caption="32us -192 clock cycles based on 6Mhz clock (32US)" value="0"/>
+        <value name="1" caption="42us -256 clock cycles based on 6Mhz clock (42US)" value="1"/>
+        <value name="2" caption="84us -512 clock cycles based on 6Mhz clock (84US)" value="2"/>
+        <value name="3" caption="10us -64 clock cycles based on 6Mhz clock (10US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG57__IGNACK">
+        <value name="0" caption="Power Switch acknowledge signal is taken into account when entering/exiting retention mode. According to the DLYVAL field, a supplementary delay is also added (from 0 to 127 digital ring oscillator period)" value="0"/>
+        <value name="1" caption="Power Switch acknowledge signal is ignored when entering/exiting retention mode, and is replaced by a overflow counter signal clocked on internal digital ring oscillator. The overflow counter is programmable by using the DLYVAL field" value="1"/>
+      </value-group>
+      <value-group name="FCCFG58__BRINGOSC">
+        <value name="0" caption="Ring Oscillator depth is default (DLY0)" value="0"/>
+        <value name="1" caption="Ring Oscillator depth is default + 1 ORDLY15 (DLY1)" value="1"/>
+        <value name="2" caption="Ring Oscillator depth is default + 2 ORDLU15 (DLY2)" value="2"/>
+        <value name="3" caption="Ring Oscillator depth is default + 3 ORDLY15 (DLY3)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG59__IDAU_EN">
+        <value name="0" caption="GC device. All IDAU regions exempt. The boot code will initialize the IDAU, H2PB and PAC as described in Section 2.9.2" value="0"/>
+        <value name="1" caption="IDAU regions enabled. The boot code will initialize the IDAU, H2PB and PAC to the values set by customer and referred to in USERCFG as described in Section 2.9.3" value="1"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="03588" name2="clk_gclk_u2122_v1" version="1d0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x4" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy bit" mask="0x1"/>
+          <bitfield name="GENCTRL0" caption="Generic Clock Generator Control 0 Synchronization Busy bit" mask="0x4"/>
+          <bitfield name="GENCTRL1" caption="Generic Clock Generator Control 1 Synchronization Busy bit" mask="0x8"/>
+          <bitfield name="GENCTRL2" caption="Generic Clock Generator Control 2 Synchronization Busy bit" mask="0x10"/>
+          <bitfield name="GENCTRL3" caption="Generic Clock Generator Control 3 Synchronization Busy bit" mask="0x20"/>
+          <bitfield name="GENCTRL4" caption="Generic Clock Generator Control 4 Synchronization Busy bit" mask="0x40"/>
+          <bitfield name="GENCTRL5" caption="Generic Clock Generator Control 5 Synchronization Busy bit" mask="0x80"/>
+          <bitfield name="GENCTRL6" caption="Generic Clock Generator Control 6 Synchronization Busy bit" mask="0x100"/>
+          <bitfield name="GENCTRL7" caption="Generic Clock Generator Control 7 Synchronization Busy bit" mask="0x200"/>
+          <bitfield name="GENCTRL8" caption="Generic Clock Generator Control 8 Synchronization Busy bit" mask="0x400"/>
+          <bitfield name="GENCTRL9" caption="Generic Clock Generator Control 9 Synchronization Busy bit" mask="0x800"/>
+          <bitfield name="GENCTRL10" caption="Generic Clock Generator Control 10 Synchronization Busy bit" mask="0x1000"/>
+          <bitfield name="GENCTRL11" caption="Generic Clock Generator Control 11 Synchronization Busy bit" mask="0x2000"/>
+        </register>
+        <register name="GENCTRL" offset="0x20" rw="RW" access="WSYNC" size="4" count="12" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="SRC" caption="Source Select" mask="0xF" values="GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x100"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x200"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x400"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x800"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x1000" values="GENCTRL__DIVSEL"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x2000"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF0000"/>
+        </register>
+        <register name="PCHCTRL" offset="0x80" rw="RW" size="4" count="39" initval="0x00000000" caption="Peripheral Clock Control">
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF" values="PCHCTRL__GEN"/>
+          <bitfield name="CHEN" caption="Channel Enable" mask="0x40"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+      </register-group>
+      <value-group name="GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0x00"/>
+        <value name="GCLK_IN" caption="Generator input pad (GCLK_IO)" value="0x01"/>
+        <value name="GCLK_GEN1" caption="Generic clock generator 1 output" value="0x02"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="0x03"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="0x04"/>
+        <value name="DFLL48M" caption="DFLL oscillator output" value="0x05"/>
+        <value name="PLL0_CLKOUT1" caption="PLL 0 port CLKOUT1" value="0x06"/>
+        <value name="PLL0_CLKOUT2" caption="PLL 0 port CLKOUT2" value="0x07"/>
+        <value name="PLL0_CLKOUT3" caption="PLL 0 port CLKOUT3" value="0x08"/>
+        <value name="PLL0_CLKOUT4" caption="PLL 0 port CLKOUT4" value="0x09"/>
+        <value name="PLL0_CLKOUT5" caption="PLL 0 port CLKOUT5" value="0x0A"/>
+      </value-group>
+      <value-group name="GENCTRL__DIVSEL">
+        <value name="DIV1" caption="Divide input directly by divider factor" value="0"/>
+        <value name="DIV2" caption="Divide input by 2^(divider factor+ 1)" value="1"/>
+      </value-group>
+      <value-group name="PCHCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+        <value name="GCLK8" caption="Generic clock generator 8" value="0x8"/>
+        <value name="GCLK9" caption="Generic clock generator 9" value="0x9"/>
+        <value name="GCLK10" caption="Generic clock generator 10" value="0xA"/>
+        <value name="GCLK11" caption="Generic clock generator 11" value="0xB"/>
+      </value-group>
+    </module>
+    <module name="H2PB" id="04947" name2="bus_ahb2apb_v1" version="1a0" caption="AHB To APB Bridge">
+      <register-group name="H2PB" caption="AHB To APB Bridge">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="H2PB CONTROL Register">
+          <bitfield name="PRIV" caption="PRIV privileged access protection bit" mask="0x4"/>
+          <bitfield name="SECEN" caption="SECEN security enable bit" mask="0x8"/>
+        </register>
+        <register name="NONSECCLRA" offset="0x8" rw="RW" size="4" atomic-op="clear:NONSECCLRA" initval="0x00000000" caption="Non-Security Clear Register A">
+          <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+          <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+          <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+          <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+          <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+          <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+          <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+          <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+          <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+          <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+          <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+          <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+          <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+          <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+          <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+          <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+          <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+          <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+          <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+          <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+          <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+          <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+          <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+          <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+          <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+          <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+          <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+          <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+          <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+          <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+          <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+          <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+        </register>
+        <register name="NONSECSETA" offset="0xC" rw="RW" size="4" atomic-op="set:NONSECSETA" initval="0x00000000" caption="Non-Security SET Register A">
+          <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+          <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+          <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+          <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+          <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+          <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+          <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+          <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+          <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+          <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+          <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+          <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+          <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+          <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+          <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+          <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+          <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+          <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+          <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+          <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+          <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+          <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+          <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+          <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+          <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+          <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+          <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+          <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+          <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+          <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+          <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+          <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="HMATRIX2" id="bus_hmatrix2_v5" name2="bus_hmatrix2_v5" version="5f0" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+          <bitfield name="M0PR" caption="Master 0 Priority" mask="0x3"/>
+          <bitfield name="LQOSEN0" caption="Latency Quality Of Service Enable for Master 0" mask="0x4"/>
+          <bitfield name="M1PR" caption="Master 1 Priority" mask="0x30"/>
+          <bitfield name="LQOSEN1" caption="Latency Quality Of Service Enable for Master 1" mask="0x40"/>
+          <bitfield name="M2PR" caption="Master 2 Priority" mask="0x300"/>
+          <bitfield name="LQOSEN2" caption="Latency Quality Of Service Enable for Master 2" mask="0x400"/>
+          <bitfield name="M3PR" caption="Master 3 Priority" mask="0x3000"/>
+          <bitfield name="LQOSEN3" caption="Latency Quality Of Service Enable for Master 3" mask="0x4000"/>
+          <bitfield name="M4PR" caption="Master 4 Priority" mask="0x30000"/>
+          <bitfield name="LQOSEN4" caption="Latency Quality Of Service Enable for Master 4" mask="0x40000"/>
+          <bitfield name="M5PR" caption="Master 5 Priority" mask="0x300000"/>
+          <bitfield name="LQOSEN5" caption="Latency Quality Of Service Enable for Master 5" mask="0x400000"/>
+        </register>
+      </register-group>
+      <register-group name="HMATRIX2" caption="HSB Matrix">
+        <register name="MCFG" offset="0x0" rw="RW" size="4" access-size="4" count="6" initval="0x00000002" caption="Master Configuration">
+          <bitfield name="ULBT" caption="Undefined Length Burst Type" mask="0x7" values="MCFG__ULBT"/>
+        </register>
+        <register name="SCFG" offset="0x40" rw="RW" size="4" access-size="4" count="9" initval="0x00000010" caption="Slave Configuration">
+          <bitfield name="SLOT_CYCLE" caption="Maximum Number of Allowed Cycles for a Burst" mask="0x1FF"/>
+          <bitfield name="DEFMSTR_TYPE" caption="Default Master Type" mask="0x30000" values="SCFG__DEFMSTR_TYPE"/>
+          <bitfield name="FIXED_DEFMSTR" caption="Fixed Index of Default Master" mask="0x3C0000"/>
+        </register>
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" size="0x8" count="9"/>
+        <register name="MRCR" offset="0x100" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Master Remap Control">
+          <bitfield name="RCB0" caption="Remap Command Bit for Master 0" mask="0x1" values="MRCR__RCB"/>
+          <bitfield name="RCB1" caption="Remap Command Bit for Master 1" mask="0x2" values="MRCR__RCB"/>
+          <bitfield name="RCB2" caption="Remap Command Bit for Master 2" mask="0x4" values="MRCR__RCB"/>
+          <bitfield name="RCB3" caption="Remap Command Bit for Master 3" mask="0x8" values="MRCR__RCB"/>
+          <bitfield name="RCB4" caption="Remap Command Bit for Master 4" mask="0x10" values="MRCR__RCB"/>
+          <bitfield name="RCB5" caption="Remap Command Bit for Master 5" mask="0x20" values="MRCR__RCB"/>
+        </register>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="9" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEIER" offset="0x150" rw="W" size="4" access-size="4" atomic-op="set:MEIMR" caption="Master Error Interrupt Enable">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MEIDR" offset="0x154" rw="W" size="4" access-size="4" atomic-op="clear:MEIMR" caption="Master Error Interrupt Disable">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MEIMR" offset="0x158" rw="R" size="4" access-size="4" caption="Master Error Interrupt Mask">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MESR" offset="0x15C" rw="R" size="4" access-size="4" atomic-op="clear:MESR" caption="Master Error Status">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MEAR" offset="0x160" rw="R" size="4" access-size="4" count="6" caption="Master Error Address"/>
+      </register-group>
+      <value-group name="MCFG__ULBT">
+        <value name="INFINITE" caption="Infinite Length" value="0"/>
+        <value name="SINGLE" caption="Single Access" value="1"/>
+        <value name="FOUR_BEAT" caption="Four Beat Burst" value="2"/>
+        <value name="EIGHT_BEAT" caption="Eight Beat Burst" value="3"/>
+        <value name="SIXTEEN_BEAT" caption="Sixteen Beat Burst" value="4"/>
+      </value-group>
+      <value-group name="SCFG__DEFMSTR_TYPE">
+        <value name="NO_DEFAULT" caption="No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst." value="0"/>
+        <value name="LAST_DEFAULT" caption="Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave." value="1"/>
+        <value name="FIXED_DEFAULT" caption="Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave." value="2"/>
+      </value-group>
+      <value-group name="MRCR__RCB">
+        <value name="DIS" caption="Disable remapped address decoding for master" value="0"/>
+        <value name="ENA" caption="Enable remapped address decoding for master" value="1"/>
+      </value-group>
+    </module>
+    <module name="ICB" id="SYSTEM_IP" version="1.0.0" caption="Implementation Control Block">
+      <register-group name="ICB" caption="Implementation Control Block">
+        <register name="ICTR" offset="0x4" rw="R" size="4" access-size="4" caption="Interrupt Controller Type Register">
+          <bitfield name="INTLINESNUM" caption="Interrupt line set number" mask="0xF"/>
+        </register>
+        <register name="ACTLR" offset="0x8" rw="RW" size="4" access-size="4" caption="Auxiliary Control Register"/>
+      </register-group>
+    </module>
+    <module name="MCLK" id="04158" name2="clk_mclk_v1" version="1a0" caption="Polaris Main Clock Controller">
+      <register-group name="MCLK" caption="Polaris Main Clock Controller">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear Register">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable Clear" mask="0x1" values="INTENCLR__CKRDY"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set Register">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable Set" mask="0x1" values="INTENSET__CKRDY"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="W" size="4" atomic-op="clear:INTFLAG" initval="0x00000001" caption="Interrupt Flag Status Register">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Flag" mask="0x1"/>
+        </register>
+        <register name="CLKDIV" offset="0xC" rw="RW" size="4" count="3" initval="0x00000000" caption="Clock Divider Control n Register">
+          <bitfield name="DIV" caption="Clock Domain n Division Factor" mask="0xFF" values="CLKDIV__DIV"/>
+        </register>
+        <register name="CLKMSK" offset="0x3C" rw="RW" size="4" count="9" initval="0x00000000" caption="Peripheral Clock Enable Mask n Register">
+          <bitfield name="MASK0" caption="Peripheral Clock Enable Mask" mask="0x1" values="CLKMSK__MASK"/>
+          <bitfield name="MASK1" caption="Peripheral Clock Enable Mask" mask="0x2" values="CLKMSK__MASK"/>
+          <bitfield name="MASK2" caption="Peripheral Clock Enable Mask" mask="0x4" values="CLKMSK__MASK"/>
+          <bitfield name="MASK3" caption="Peripheral Clock Enable Mask" mask="0x8" values="CLKMSK__MASK"/>
+          <bitfield name="MASK4" caption="Peripheral Clock Enable Mask" mask="0x10" values="CLKMSK__MASK"/>
+          <bitfield name="MASK5" caption="Peripheral Clock Enable Mask" mask="0x20" values="CLKMSK__MASK"/>
+          <bitfield name="MASK6" caption="Peripheral Clock Enable Mask" mask="0x40" values="CLKMSK__MASK"/>
+          <bitfield name="MASK7" caption="Peripheral Clock Enable Mask" mask="0x80" values="CLKMSK__MASK"/>
+          <bitfield name="MASK8" caption="Peripheral Clock Enable Mask" mask="0x100" values="CLKMSK__MASK"/>
+          <bitfield name="MASK9" caption="Peripheral Clock Enable Mask" mask="0x200" values="CLKMSK__MASK"/>
+          <bitfield name="MASK10" caption="Peripheral Clock Enable Mask" mask="0x400" values="CLKMSK__MASK"/>
+          <bitfield name="MASK11" caption="Peripheral Clock Enable Mask" mask="0x800" values="CLKMSK__MASK"/>
+          <bitfield name="MASK12" caption="Peripheral Clock Enable Mask" mask="0x1000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK13" caption="Peripheral Clock Enable Mask" mask="0x2000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK14" caption="Peripheral Clock Enable Mask" mask="0x4000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK15" caption="Peripheral Clock Enable Mask" mask="0x8000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK16" caption="Peripheral Clock Enable Mask" mask="0x10000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK17" caption="Peripheral Clock Enable Mask" mask="0x20000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK18" caption="Peripheral Clock Enable Mask" mask="0x40000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK19" caption="Peripheral Clock Enable Mask" mask="0x80000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK20" caption="Peripheral Clock Enable Mask" mask="0x100000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK21" caption="Peripheral Clock Enable Mask" mask="0x200000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK22" caption="Peripheral Clock Enable Mask" mask="0x400000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK23" caption="Peripheral Clock Enable Mask" mask="0x800000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK24" caption="Peripheral Clock Enable Mask" mask="0x1000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK25" caption="Peripheral Clock Enable Mask" mask="0x2000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK26" caption="Peripheral Clock Enable Mask" mask="0x4000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK27" caption="Peripheral Clock Enable Mask" mask="0x8000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK28" caption="Peripheral Clock Enable Mask" mask="0x10000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK29" caption="Peripheral Clock Enable Mask" mask="0x20000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK30" caption="Peripheral Clock Enable Mask" mask="0x40000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK31" caption="Peripheral Clock Enable Mask" mask="0x80000000" values="CLKMSK__MASK"/>
+        </register>
+      </register-group>
+      <value-group name="INTENCLR__CKRDY">
+        <value name="0" caption="The Clock Ready interrupt is disabled" value="0"/>
+        <value name="1" caption="The Clock Ready interrupt is enabled." value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CKRDY">
+        <value name="0" caption="The Clock Ready interrupt is disabled." value="0"/>
+        <value name="1" caption="The Clock Ready interrupt is enabled." value="1"/>
+      </value-group>
+      <value-group name="CLKDIV__DIV">
+        <value name="DIV1" caption="Divide by 1" value="1"/>
+        <value name="DIV2" caption="Divide by 2" value="2"/>
+        <value name="DIV4" caption="Divide by 4" value="4"/>
+        <value name="DIV8" caption="Divide by 8" value="8"/>
+        <value name="DIV16" caption="Divide by 16" value="16"/>
+        <value name="DIV32" caption="Divide by 32" value="32"/>
+        <value name="DIV64" caption="Divide by 64" value="64"/>
+        <value name="DIV128" caption="Divide by 128" value="128"/>
+      </value-group>
+      <value-group name="CLKMSK__MASK">
+        <value name="0" caption="Peripheral clock mclk_clk_periph[n*32+x] stopped" value="0"/>
+        <value name="1" caption="Peripheral clock mclk_clk_periph[n*32+x] enabled" value="1"/>
+      </value-group>
+    </module>
+    <module name="MCRAMC" id="04921" name2="drm_mcramc_v5" version="5b0" caption="Multi-Channel RAM Controller">
+      <register-group name="MCRAMC" caption="Multi-Channel RAM Controller">
+        <register name="MCRAMC_CTRLA" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000002" caption="Control Enable A Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1" values="MCRAMC_CTRLA__SWRST"/>
+          <bitfield name="ENABLE" caption="ECC Decoder Enable" mask="0x2" values="MCRAMC_CTRLA__ENABLE"/>
+          <bitfield name="PRIV" caption="Priviledged Access Enable" mask="0x4"/>
+          <bitfield name="WS" caption="Wait State Enable" mask="0x100"/>
+        </register>
+        <register name="MCRAMC_INTENCLR" offset="0x8" rw="RW" size="4" access-size="4" atomic-op="clear:MCRAMC_INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear Register">
+          <bitfield name="SERREN" caption="Single Bit Error Interrupt Enable, Clear" mask="0x1"/>
+          <bitfield name="DERREN" caption="Double Bit Error Interrupt Enable, Clear" mask="0x2"/>
+        </register>
+        <register name="MCRAMC_INTENSET" offset="0xC" rw="RW" size="4" access-size="4" atomic-op="set:MCRAMC_INTENSET" initval="0x00000000" caption="Interrupt Enable Set Register">
+          <bitfield name="SERREN" caption="Single Bit Error Interrupt Enable, Set" mask="0x1"/>
+          <bitfield name="DERREN" caption="Double Bit Error Interrupt Enable, Set" mask="0x2"/>
+        </register>
+        <register name="MCRAMC_INTSTA" offset="0x10" rw="RW" size="4" access-size="4" atomic-op="clear:MCRAMC_INTSTA" initval="0x00000000" caption="Interrupt Status Register">
+          <bitfield name="SERR" caption="Single Bit Error" mask="0x1"/>
+          <bitfield name="DERR" caption="Double Bit Error" mask="0x2"/>
+        </register>
+        <register name="MCRAMC_FLTCTRL" offset="0x14" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Fault Injection Control Register">
+          <bitfield name="FLTEN" caption="Fault Injection Enabled" mask="0x2" values="MCRAMC_FLTCTRL__FLTEN"/>
+          <bitfield name="FLTMD" caption="Fault Injection Mode" mask="0x3000"/>
+        </register>
+        <register name="MCRAMC_FLTPTR" offset="0x18" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Fault Injection Pointer Register">
+          <bitfield name="FLT1PTR" caption="Single Fault Injection Bit Pointer" mask="0xFF"/>
+          <bitfield name="FLT2PTR" caption="Double Fault Injection Bit Pointer" mask="0xFF0000"/>
+        </register>
+        <register name="MCRAMC_FLTADR" offset="0x1C" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Fault Injection Address Register">
+          <bitfield name="FLTADR" caption="Fault Address Offset" mask="0xFFFFFF"/>
+        </register>
+        <register name="MCRAMC_ERRCADR" offset="0x20" rw="R" size="4" access-size="4" initval="0x00000000" caption="Error Capture Address Register">
+          <bitfield name="ERCADR" caption="ECC SECDED Error Capture Address" mask="0xFFFFFF"/>
+        </register>
+        <register name="MCRAMC_ERRCPAR" offset="0x24" rw="R" size="4" access-size="4" initval="0x00000000" caption="Error Capture Parity Register">
+          <bitfield name="ERCPAR" caption="ECC SECDED Error Capture Parity" mask="0xFF"/>
+        </register>
+        <register name="MCRAMC_ERRCSYN" offset="0x28" rw="R" size="4" access-size="4" initval="0x00000000" caption="Error Capture Syndrome Register">
+          <bitfield name="ERCSYN" caption="ECC SECDED Error Capture Syndrome" mask="0xFF" values="MCRAMC_ERRCSYN__ERCSYN"/>
+          <bitfield name="ERR1" caption="ECC Single Bit Error" mask="0x4000"/>
+          <bitfield name="ERR2" caption="ECC Double Bit Error" mask="0x8000" values="MCRAMC_ERRCSYN__ERR2"/>
+        </register>
+        <register name="MCRAMC_VERSION" offset="0xFC" rw="R" size="4" access-size="4" initval="0x00000510" caption="Version Register">
+          <bitfield name="VERSION" caption="MCRAMC Version" mask="0xFFF"/>
+          <bitfield name="MFN" caption="Metal Fix Number" mask="0x70000"/>
+        </register>
+      </register-group>
+      <value-group name="MCRAMC_CTRLA__SWRST">
+        <value name="0" caption="No effect." value="0"/>
+        <value name="1" caption="Reset the MCRAMC. A software-triggered hardware reset of the MCRAMC user interface is performed." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_CTRLA__ENABLE">
+        <value name="0" caption="ECC decoding is disabled." value="0"/>
+        <value name="1" caption="ECC decoding is enabled." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_FLTCTRL__FLTEN">
+        <value name="0" caption="Disables fault injection." value="0"/>
+        <value name="1" caption="Enables fault injection at FLTADR address offset as selected by FLTMD and FLTxPTR." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_ERRCSYN__ERCSYN">
+        <value name="0" caption="Not a Single bit error." value="0"/>
+        <value name="1" caption="Single bit error." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_ERRCSYN__ERR2">
+        <value name="0" caption="Not a Double bit error." value="0"/>
+        <value name="1" caption="Double bit error." value="1"/>
+      </value-group>
+    </module>
+    <module name="MPU" id="SYSTEM_IP" version="1.0.0" caption="Memory Protection Unit">
+      <register-group name="MPU" caption="Memory Protection Unit">
+        <register name="MPU_TYPE" offset="0x0" rw="R" size="4" access-size="4" caption="MPU Type Register">
+          <bitfield name="SEPARATE" caption="Separate instructions and data address regions" mask="0x1"/>
+          <bitfield name="DREGION" caption="Number of MPU data regions" mask="0xFF00"/>
+        </register>
+        <register name="MPU_CTRL" offset="0x4" rw="RW" size="4" access-size="4" caption="MPU Control Register">
+          <bitfield name="ENABLE" caption="MPU enable" mask="0x1"/>
+          <bitfield name="HFNMIENA" caption="HardFault, NMI enable" mask="0x2"/>
+          <bitfield name="PRIVDEFENA" caption="Privileged default enable" mask="0x4"/>
+        </register>
+        <register name="MPU_RNR" offset="0x8" rw="RW" size="4" access-size="4" caption="MPU Region Number Register">
+          <bitfield name="REGION" caption="Selected region number" mask="0xFF"/>
+        </register>
+        <register name="MPU_RBAR" offset="0xC" rw="RW" size="4" access-size="4" caption="MPU Region Base Address Register">
+          <bitfield name="XN" caption="Execute Never" mask="0x1"/>
+          <bitfield name="AP" caption="Access permissions" mask="0x6" values="MPU_RBAR__AP"/>
+          <bitfield name="SH" caption="Shareability" mask="0x18" values="MPU_RBAR__SH"/>
+          <bitfield name="BASE" caption="Base address" mask="0xFFFFFFE0"/>
+        </register>
+        <register name="MPU_RLAR" offset="0x10" rw="RW" size="4" access-size="4" caption="MPU Region Limit Address Register">
+          <bitfield name="EN" caption="Region enable" mask="0x1"/>
+          <bitfield name="AttrInd" caption="Attribute Index" mask="0xE"/>
+          <bitfield name="LIMIT" caption="Limit address" mask="0xFFFFFFE0"/>
+        </register>
+        <register name="MPU_MAIR0" offset="0x30" rw="RW" size="4" access-size="4" caption="MPU Memory Attribute Indirection Register 0">
+          <bitfield name="Attr0" caption="Attribute of MPU region 0" mask="0xFF"/>
+          <bitfield name="Attr1" caption="Attribute of MPU region 1" mask="0xFF00"/>
+          <bitfield name="Attr2" caption="Attribute of MPU region 2" mask="0xFF0000"/>
+          <bitfield name="Attr3" caption="Attribute of MPU region 3" mask="0xFF000000"/>
+        </register>
+        <register name="MPU_MAIR1" offset="0x34" rw="RW" size="4" access-size="4" caption="MPU Memory Attribute Indirection Register 1">
+          <bitfield name="Attr4" caption="Attribute of MPU region 4" mask="0xFF"/>
+          <bitfield name="Attr5" caption="Attribute of MPU region 5" mask="0xFF00"/>
+          <bitfield name="Attr6" caption="Attribute of MPU region 6" mask="0xFF0000"/>
+          <bitfield name="Attr7" caption="Attribute of MPU region 7" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <value-group name="MPU_RBAR__AP">
+        <value name="RWPRIV" caption="Read/write by privileged code only" value="0"/>
+        <value name="RWANY" caption="Read/write by any privilege level" value="1"/>
+        <value name="RPRIV" caption="Read-only by privileged code only" value="2"/>
+        <value name="RANY" caption="Read-only by any privilege level" value="3"/>
+      </value-group>
+      <value-group name="MPU_RBAR__SH">
+        <value name="NO" caption="Non-shareable" value="0"/>
+        <value name="OUTER" caption="Outer shareable" value="2"/>
+        <value name="INNER" caption="Inner shareable" value="3"/>
+      </value-group>
+    </module>
+    <module name="NVIC" id="SYSTEM_IP" version="1.0.0" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register name="NVIC_ISER" offset="0x0" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Set Enable Register n">
+          <bitfield name="SETENA" caption="Set enable" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ICER" offset="0x80" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Clear Enable Register n">
+          <bitfield name="CLRENA" caption="Clear enable" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ISPR" offset="0x100" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Set Pending Register n">
+          <bitfield name="SETPEND" caption="Set pending" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ICPR" offset="0x180" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Clear Pending Register n">
+          <bitfield name="CLRPEND" caption="Clear pending" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_IABR" offset="0x200" rw="R" size="4" access-size="4" count="5" caption="Interrupt Active Bit Register n">
+          <bitfield name="ACTIVE" caption="Active state" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ITNS" offset="0x280" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Target Non-secure Register n">
+          <bitfield name="ITNS" caption="Interrupt Targets Non-secure" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_IPR" offset="0x300" rw="RW" size="4" access-size="4" count="36" caption="Interrupt Priority Register n">
+          <bitfield name="PRI_N0" caption="Priority of interrupt number 4n+0" mask="0xFF"/>
+          <bitfield name="PRI_N1" caption="Priority of interrupt number 4n+1" mask="0xFF00"/>
+          <bitfield name="PRI_N2" caption="Priority of interrupt number 4n+2" mask="0xFF0000"/>
+          <bitfield name="PRI_N3" caption="Priority of interrupt number 4n+3" mask="0xFF000000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="OSC32KCTRL" id="03717" name2="osc_osc32kctrl_u2400_v2" version="2a0" caption="32kHz Oscillators Control">
+      <register-group name="OSC32KCTRL" caption="32kHz Oscillators Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector" mask="0x4"/>
+          <bitfield name="XOSC32KSW" caption="XOSC32K Clock switch" mask="0x8"/>
+        </register>
+        <register name="CLKSELCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Clock Selection Control">
+          <bitfield name="RTCSEL" caption="RTC Clock Selection" mask="0x3" values="CLKSELCTRL__RTCSEL"/>
+          <bitfield name="HSMSEL" caption="HSM Clock Selection" mask="0x30" values="CLKSELCTRL__HSMSEL"/>
+        </register>
+        <register name="CFDCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Clock Failure Detector Control">
+          <bitfield name="CFDEN" caption="Clock Failure Detector Enable" mask="0x1"/>
+          <bitfield name="SWBACK" caption="Clock Switch Back" mask="0x2"/>
+          <bitfield name="CFDPRESC" caption="Clock Failure Detector Prescaler" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="CFDEO" caption="Clock Failure Detector Event Output Enable" mask="0x1"/>
+        </register>
+        <register name="XOSC32K" offset="0x1C" rw="RW" size="4" initval="0x00200080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="ONDEMAND" caption="On Demand Mode" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Startup Mode" mask="0xF00" values="XOSC32K__STARTUP"/>
+          <bitfield name="ENSL" caption="Enable Servo Loop" mask="0x10000"/>
+          <bitfield name="BOOST" caption="Gain Boost" mask="0x20000"/>
+          <bitfield name="CGM" caption="Control Gain Mode" mask="0x3C0000" values="XOSC32K__CGM"/>
+          <bitfield name="CTRLX" caption="Extended Control" mask="0xF000000"/>
+        </register>
+      </register-group>
+      <value-group name="CLKSELCTRL__RTCSEL">
+        <value name="ULP32K" caption="32.768kHz from 32kHz internal ULP oscillator" value="0x0"/>
+        <value name="ULP1K" caption="1.024kHz from 32kHz internal ULP oscillator" value="0x1"/>
+        <value name="XOSC32K" caption="32.768kHz from 32.768kHz external crystal oscillator" value="0x2"/>
+        <value name="XOSC1K" caption="1.024kHz from 32.768kHz internal oscillator" value="0x3"/>
+      </value-group>
+      <value-group name="CLKSELCTRL__HSMSEL">
+        <value name="ULP32K" caption="32.768kHz from 32kHz internal ULP oscillator" value="0x0"/>
+        <value name="XOSC32K" caption="32.768kHz from 32.768kHz external crystal oscillator" value="0x2"/>
+      </value-group>
+      <value-group name="XOSC32K__STARTUP">
+        <value name="1CYCLE" caption="1 ULP clock cycle" value="0x0"/>
+        <value name="16CYCLES" caption="16 ULP clock cycles" value="0x1"/>
+        <value name="32CYCLES" caption="32 ULP clock cycles" value="0x2"/>
+        <value name="2048CYCLES" caption="2048 ULP clock cycles" value="0x3"/>
+        <value name="4096CYCLES" caption="4096 ULP clock cycles" value="0x4"/>
+        <value name="8192CYCLES" caption="8192 ULP clock cycles" value="0x5"/>
+        <value name="16384CYCLES" caption="16384 ULP clock cycles" value="0x6"/>
+        <value name="32768CYCLES" caption="32768 ULP clock cycles" value="0x7"/>
+        <value name="65536CYCLES" caption="65536 ULP clock cycles" value="0x8"/>
+        <value name="131072CYCLES" caption="131072 ULP clock cycles" value="0x9"/>
+        <value name="262144CYCLES" caption="262144 ULP clock cycles" value="0xA"/>
+      </value-group>
+      <value-group name="XOSC32K__CGM">
+        <value name="CGM0" caption="The lower Control Gain Mode value" value="0x0"/>
+        <value name="CGM1" caption="A higher Control Gain Mode value than CGM0" value="0x1"/>
+        <value name="CGM2" caption="A higher Control Gain Mode value than CGM1" value="0x2"/>
+        <value name="CGM3" caption="A higher Control Gain Mode value than CGM2" value="0x3"/>
+        <value name="CGM4" caption="A higher Control Gain Mode value than CGM3" value="0x4"/>
+        <value name="CGM5" caption="A higher Control Gain Mode value than CGM4" value="0x5"/>
+        <value name="CGM6" caption="A higher Control Gain Mode value than CGM5" value="0x6"/>
+        <value name="CGM7" caption="A higher Control Gain Mode value than CGM6" value="0x7"/>
+        <value name="CGM8" caption="A higher Control Gain Mode value than CGM7" value="0x8"/>
+        <value name="CGM9" caption="A higher Control Gain Mode value than CGM8" value="0x9"/>
+        <value name="CGM10" caption="A higher Control Gain Mode value than CGM9" value="0xA"/>
+        <value name="CGM11" caption="A higher Control Gain Mode value than CGM10" value="0xB"/>
+        <value name="CGM12" caption="A higher Control Gain Mode value than CGM11" value="0xC"/>
+        <value name="CGM13" caption="A higher Control Gain Mode value than CGM12" value="0xD"/>
+        <value name="CGM14" caption="A higher Control Gain Mode value than CGM13" value="0xE"/>
+        <value name="CGM15" caption="The highest Control Gain Mode value" value="0xF"/>
+      </value-group>
+    </module>
+    <module name="OSCCTRL" id="03718" name2="osc_oscctrl_u2401_v2" version="2b0" caption="Oscillators Control">
+      <register-group name="OSCCTRL" caption="Oscillators Control">
+        <register name="EVCTRL" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="CFDEO" caption="Clock Failure Detector Event Output Enable" mask="0x1"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure Interrupt Enable" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure Interrupt Enable" mask="0x4"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock Interrupt Enable" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow Interrupt Enable" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure Interrupt Enable" mask="0x2000"/>
+          <bitfield name="PLL0LOCKR" caption="PLL 0 Lock Rise Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="PLL0LOCKF" caption="PLL 0 Lock Fall Interrupt Enable" mask="0x2000000"/>
+        </register>
+        <register name="INTENSET" offset="0x8" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure Interrupt Enable" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure Interrupt Enable" mask="0x4"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock Interrupt Enable" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow Interrupt Enable" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure Interrupt Enable" mask="0x2000"/>
+          <bitfield name="PLL0LOCKR" caption="PLL 0 Lock Rise Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="PLL0LOCKF" caption="PLL 0 Lock Fall Interrupt Enable" mask="0x2000000"/>
+        </register>
+        <register name="INTFLAG" offset="0xC" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure" mask="0x4"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure" mask="0x2000"/>
+          <bitfield name="PLL0LOCKR" caption="PLL 0 Lock Rise" mask="0x1000000"/>
+          <bitfield name="PLL0LOCKF" caption="PLL 0 Lock Fall" mask="0x2000000"/>
+        </register>
+        <register name="STATUS" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure" mask="0x4"/>
+          <bitfield name="XOSCCKSW" caption="XOSC Clock Switch" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure" mask="0x2000"/>
+          <bitfield name="PLL0LOCK" caption="PLL 0 Lock" mask="0x1000000"/>
+        </register>
+        <register name="XOSCCTRLA" offset="0x14" rw="RW" size="4" initval="0x00000D00" caption="External Multipurpose Crystal Oscillator Control A">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="AGC" caption="Auto Gain Control Loop Enable" mask="0x4"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x8"/>
+          <bitfield name="CFDEN" caption="Clock Failure Detector Enable" mask="0x10"/>
+          <bitfield name="SWBEN" caption="Xosc Clock Switch Back Enable" mask="0x20"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF00" values="XOSCCTRLA__STARTUP"/>
+          <bitfield name="CFDPRESC" caption="Clock Failure Detector Prescaler" mask="0xF0000" values="XOSCCTRLA__CFDPRESC"/>
+          <bitfield name="USBHSDIV" caption="USBHS Referrence Clock Division" mask="0x3000000" values="XOSCCTRLA__USBHSDIV"/>
+          <bitfield name="WRTLOCK" caption="Write Lock for CTRLA register" mask="0x80000000"/>
+        </register>
+        <register name="XOSCCTRLB" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="External Multipurpose Crystal Oscillator Control B">
+          <bitfield name="USRCFG" caption="User Configuration Control Bits" mask="0xFF"/>
+          <bitfield name="WRTLOCK" caption="Write Lock for CTRLB register" mask="0x80000000"/>
+        </register>
+        <register name="DFLLCTRLA" offset="0x2C" rw="RW" size="4" initval="0x00000082" caption="DFLL48M Control A">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x4"/>
+          <bitfield name="LOWFREQ" caption="Low Frequency Mode" mask="0x8"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="DFLLCTRLB" offset="0x30" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="DFLL48M Control B">
+          <bitfield name="LOOPEN" caption="Operating Mode Selection" mask="0x1"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x2"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x4"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x8"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x10"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x20"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x80"/>
+        </register>
+        <register name="DFLLTUNE" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="DFLL48M Tune">
+          <bitfield name="TUNE" caption="Tune Value" mask="0x7F"/>
+        </register>
+        <register name="DFLLDIFF" offset="0x38" rw="R" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Diff">
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF"/>
+        </register>
+        <register name="DFLLMUL" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="STEP" caption="Tune Maximum Step" mask="0x7F0000"/>
+        </register>
+        <register name="PLL0CTRL" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="PLL Control">
+          <bitfield name="ENABLE" caption="PLL Enable" mask="0x2"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x4"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="REFSEL" caption="Reference selection" mask="0x700" values="PLL0CTRL__REFSEL"/>
+          <bitfield name="BWSEL" caption="Bandwidth selection" mask="0x3800" values="PLL0CTRL__BWSEL"/>
+        </register>
+        <register name="PLL0FBDIV" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="PLL Feed-Back Divider">
+          <bitfield name="FBDIV" caption="PLL Feed-Back Divider Factor" mask="0x3FF"/>
+        </register>
+        <register name="PLL0REFDIV" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="PLL reference divider">
+          <bitfield name="REFDIV" caption="PLL reference division factor" mask="0x3F"/>
+        </register>
+        <register name="PLL0POSTDIVA" offset="0x4C" rw="RW" size="4" initval="0x20202020" caption="PLL output clock divider A">
+          <bitfield name="POSTDIV0" caption="PLL output 0 clock division factor" mask="0x3F"/>
+          <bitfield name="OUTEN0" caption="PLL output 0 enable" mask="0x80"/>
+          <bitfield name="POSTDIV1" caption="PLL output 0 clock division factor" mask="0x3F00"/>
+          <bitfield name="OUTEN1" caption="PLL output 0 enable" mask="0x8000"/>
+          <bitfield name="POSTDIV2" caption="PLL output 0 clock division factor" mask="0x3F0000"/>
+          <bitfield name="OUTEN2" caption="PLL output 0 enable" mask="0x800000"/>
+          <bitfield name="POSTDIV3" caption="PLL output 0 clock division factor" mask="0x3F000000"/>
+          <bitfield name="OUTEN3" caption="PLL output 0 enable" mask="0x80000000"/>
+        </register>
+        <register name="PLL0POSTDIVB" offset="0x50" rw="RW" size="4" initval="0x00000020" caption="PLL output clock divider B">
+          <bitfield name="POSTDIV4" caption="PLL output 4 clock division factor" mask="0x3F"/>
+          <bitfield name="OUTEN4" caption="PLL output 4 enable" mask="0x80"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x78" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="DFLLENABLE" caption="DFLL48M ENABLE Synchronization Busy" mask="0x2"/>
+          <bitfield name="DFLLCTRLB" caption="DFLLCTRLB Synchronization Busy" mask="0x4"/>
+          <bitfield name="DFLLTUNE" caption="DFLLTUNE Synchronization Busy" mask="0x8"/>
+          <bitfield name="DFLLDIFF" caption="DFLLDIFF Synchronization Busy" mask="0x10"/>
+          <bitfield name="DFLLMUL" caption="DFLLMUL Synchronization Busy" mask="0x20"/>
+          <bitfield name="FRACDIV0" caption="FRACDIV0 Synchronization Busy" mask="0x40"/>
+          <bitfield name="FRACDIV1" caption="FRACDIV1 Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="XOSCCAL" offset="0x80" rw="RW" size="4" initval="0x00000000" caption="XOSC Calibration Register">
+          <mode name="DEFAULT"/>
+          <mode name="FUSES_OSC_XTAL_HF_AGC_V2"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="FTRANS" caption="Fine Transconductance programmability for Oscillator" mask="0x3"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="KICKEREN" caption="Kicker enable" mask="0x4"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="ENVAMP" caption="envelope amplitude at osci" mask="0x8"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="HYST" caption="loop hysteresis control" mask="0x10"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="CMSEL" caption="clock buffer common mode selection" mask="0x20"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="FLIPPOL" caption="flip output clock polarity" mask="0x40"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="REDGAIN" caption="reduce gain control timer" mask="0x100"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="REDOSC" caption="reduce oscillation debug counter" mask="0x200"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="SPARES" caption="Spare bits" mask="0xFC00"/>
+          <bitfield modes="DEFAULT" name="CAL" caption="XOSC Calibration" mask="0xFFFF"/>
+        </register>
+        <register name="RC48MCAL0" offset="0x88" rw="RW" size="4" initval="0x00000000" caption="RC48M Calibration 0">
+          <mode name="DEFAULT"/>
+          <mode name="FUSES_OSC_RC48MHZ_V1"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="temp_trim_mv" caption="Temp trim value" mask="0x3F"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="proc_trim_mv" caption="Proc trim value" mask="0x3FC0"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="iosc_boost" caption="IOSC boost" mask="0x10000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="out_buf_sel" caption="Output buffer select" mask="0x20000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="ldo_vout_boost" caption="LDO VOUT boost" mask="0x40000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="cmp_8m_lp" caption="Comparator 8MHz low-power" mask="0x80000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="cmp_pwr_ctrl" caption="Comparator power control" mask="0x700000"/>
+          <bitfield modes="DEFAULT" name="CAL" caption="RC48M Calibration" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="XOSCCTRLA__STARTUP">
+        <value name="CYCLE1" caption="31 us" value="0"/>
+        <value name="CYCLE2" caption="61 us" value="1"/>
+        <value name="CYCLE4" caption="122 us" value="2"/>
+        <value name="CYCLE8" caption="244 us" value="3"/>
+        <value name="CYCLE16" caption="488 us" value="4"/>
+        <value name="CYCLE32" caption="977 us" value="5"/>
+        <value name="CYCLE64" caption="1953 us" value="6"/>
+        <value name="CYCLE128" caption="3906 us" value="7"/>
+        <value name="CYCLE256" caption="7813 us" value="8"/>
+        <value name="CYCLE512" caption="15625 us" value="9"/>
+        <value name="CYCLE1024" caption="31250 us" value="10"/>
+        <value name="CYCLE2048" caption="62500 us" value="11"/>
+        <value name="CYCLE4096" caption="125000 us" value="12"/>
+        <value name="CYCLE8192" caption="250000 us" value="13"/>
+        <value name="CYCLE16384" caption="500000 us" value="14"/>
+        <value name="CYCLE32768" caption="1000000 us" value="15"/>
+      </value-group>
+      <value-group name="XOSCCTRLA__CFDPRESC">
+        <value name="DIV1" caption="48 MHz" value="0"/>
+        <value name="DIV2" caption="24 MHz" value="1"/>
+        <value name="DIV4" caption="12 MHz" value="2"/>
+        <value name="DIV8" caption="6 MHz" value="3"/>
+        <value name="DIV16" caption="3 MHz" value="4"/>
+        <value name="DIV32" caption="1.5 MHz" value="5"/>
+        <value name="DIV64" caption="0.75 MHz" value="6"/>
+        <value name="DIV128" caption="0.375 MHz" value="7"/>
+        <value name="DIV256" caption="187.5 KHz" value="8"/>
+        <value name="DIV512" caption="93.75 KHz" value="9"/>
+        <value name="DIV1024" caption="46.875 KHz" value="10"/>
+        <value name="DIV2048" caption="23.437 KHz" value="11"/>
+        <value name="DIV4096" caption="11.718 KHz" value="12"/>
+        <value name="DIV8192" caption="5.85 KHz" value="13"/>
+        <value name="DIV16384" caption="2.92 KHz" value="14"/>
+        <value name="DIV32768" caption="1.46 KHz" value="15"/>
+      </value-group>
+      <value-group name="XOSCCTRLA__USBHSDIV">
+        <value name="DIS" caption="USBHS PLL reference XOSC clock is disabled" value="0"/>
+        <value name="DIV1" caption="USBHS PLL reference XOSC clock is divided by 1" value="1"/>
+        <value name="DIV2" caption="USBHS PLL reference XOSC clock is divided by 2" value="2"/>
+        <value name="DIV4" caption="USBHS PLL reference XOSC clock is divided by 4" value="3"/>
+      </value-group>
+      <value-group name="PLL0CTRL__REFSEL">
+        <value name="GCLK" caption="Dedicated GCLK clock reference" value="0x0"/>
+        <value name="XOSC" caption="XOSC clock reference" value="0x1"/>
+        <value name="DFLL48M" caption="DFLL48M clock reference" value="0x2"/>
+      </value-group>
+      <value-group name="PLL0CTRL__BWSEL">
+        <value name="BWSEL0" caption="TBD" value="0x0"/>
+        <value name="BWSEL1" caption="TBD" value="0x1"/>
+        <value name="BWSEL2" caption="TBD" value="0x2"/>
+        <value name="BWSEL3" caption="TBD" value="0x3"/>
+        <value name="BWSEL4" caption="TBD" value="0x4"/>
+        <value name="BWSEL5" caption="TBD" value="0x5"/>
+        <value name="BWSEL6" caption="TBD" value="0x6"/>
+        <value name="BWSEL7" caption="TBD" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PAC" id="04298" name2="sec_pac_apb_v1" version="1a0" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A Register">
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+        </register>
+        <register name="WRCTRL" offset="0x4" rw="W" size="4" initval="0x00000000" caption="Write Control Register">
+          <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+          <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="WRCTRL__KEY"/>
+        </register>
+        <register name="STATUS" offset="0x40" rw="R" size="4" count="4" initval="0x00000000" caption="Peripheral Status n Register">
+          <bitfield name="PERID0" caption="PERID Write Protection Status" mask="0x1" values="STATUS__PERID"/>
+          <bitfield name="PERID1" caption="PERID Write Protection Status" mask="0x2" values="STATUS__PERID"/>
+          <bitfield name="PERID2" caption="PERID Write Protection Status" mask="0x4" values="STATUS__PERID"/>
+          <bitfield name="PERID3" caption="PERID Write Protection Status" mask="0x8" values="STATUS__PERID"/>
+          <bitfield name="PERID4" caption="PERID Write Protection Status" mask="0x10" values="STATUS__PERID"/>
+          <bitfield name="PERID5" caption="PERID Write Protection Status" mask="0x20" values="STATUS__PERID"/>
+          <bitfield name="PERID6" caption="PERID Write Protection Status" mask="0x40" values="STATUS__PERID"/>
+          <bitfield name="PERID7" caption="PERID Write Protection Status" mask="0x80" values="STATUS__PERID"/>
+          <bitfield name="PERID8" caption="PERID Write Protection Status" mask="0x100" values="STATUS__PERID"/>
+          <bitfield name="PERID9" caption="PERID Write Protection Status" mask="0x200" values="STATUS__PERID"/>
+          <bitfield name="PERID10" caption="PERID Write Protection Status" mask="0x400" values="STATUS__PERID"/>
+          <bitfield name="PERID11" caption="PERID Write Protection Status" mask="0x800" values="STATUS__PERID"/>
+          <bitfield name="PERID12" caption="PERID Write Protection Status" mask="0x1000" values="STATUS__PERID"/>
+          <bitfield name="PERID13" caption="PERID Write Protection Status" mask="0x2000" values="STATUS__PERID"/>
+          <bitfield name="PERID14" caption="PERID Write Protection Status" mask="0x4000" values="STATUS__PERID"/>
+          <bitfield name="PERID15" caption="PERID Write Protection Status" mask="0x8000" values="STATUS__PERID"/>
+          <bitfield name="PERID16" caption="PERID Write Protection Status" mask="0x10000" values="STATUS__PERID"/>
+          <bitfield name="PERID17" caption="PERID Write Protection Status" mask="0x20000" values="STATUS__PERID"/>
+          <bitfield name="PERID18" caption="PERID Write Protection Status" mask="0x40000" values="STATUS__PERID"/>
+          <bitfield name="PERID19" caption="PERID Write Protection Status" mask="0x80000" values="STATUS__PERID"/>
+          <bitfield name="PERID20" caption="PERID Write Protection Status" mask="0x100000" values="STATUS__PERID"/>
+          <bitfield name="PERID21" caption="PERID Write Protection Status" mask="0x200000" values="STATUS__PERID"/>
+          <bitfield name="PERID22" caption="PERID Write Protection Status" mask="0x400000" values="STATUS__PERID"/>
+          <bitfield name="PERID23" caption="PERID Write Protection Status" mask="0x800000" values="STATUS__PERID"/>
+          <bitfield name="PERID24" caption="PERID Write Protection Status" mask="0x1000000" values="STATUS__PERID"/>
+          <bitfield name="PERID25" caption="PERID Write Protection Status" mask="0x2000000" values="STATUS__PERID"/>
+          <bitfield name="PERID26" caption="PERID Write Protection Status" mask="0x4000000" values="STATUS__PERID"/>
+          <bitfield name="PERID27" caption="PERID Write Protection Status" mask="0x8000000" values="STATUS__PERID"/>
+          <bitfield name="PERID28" caption="PERID Write Protection Status" mask="0x10000000" values="STATUS__PERID"/>
+          <bitfield name="PERID29" caption="PERID Write Protection Status" mask="0x20000000" values="STATUS__PERID"/>
+          <bitfield name="PERID30" caption="PERID Write Protection Status" mask="0x40000000" values="STATUS__PERID"/>
+          <bitfield name="PERID31" caption="PERID Write Protection Status" mask="0x80000000" values="STATUS__PERID"/>
+        </register>
+        <register name="LOCK" offset="0x50" rw="R" size="4" count="4" initval="0x00000000" caption="Peripheral Lock n Register">
+          <bitfield name="PERID0" caption="PERID Write Protection Lock Status" mask="0x1" values="LOCK__PERID"/>
+          <bitfield name="PERID1" caption="PERID Write Protection Lock Status" mask="0x2" values="LOCK__PERID"/>
+          <bitfield name="PERID2" caption="PERID Write Protection Lock Status" mask="0x4" values="LOCK__PERID"/>
+          <bitfield name="PERID3" caption="PERID Write Protection Lock Status" mask="0x8" values="LOCK__PERID"/>
+          <bitfield name="PERID4" caption="PERID Write Protection Lock Status" mask="0x10" values="LOCK__PERID"/>
+          <bitfield name="PERID5" caption="PERID Write Protection Lock Status" mask="0x20" values="LOCK__PERID"/>
+          <bitfield name="PERID6" caption="PERID Write Protection Lock Status" mask="0x40" values="LOCK__PERID"/>
+          <bitfield name="PERID7" caption="PERID Write Protection Lock Status" mask="0x80" values="LOCK__PERID"/>
+          <bitfield name="PERID8" caption="PERID Write Protection Lock Status" mask="0x100" values="LOCK__PERID"/>
+          <bitfield name="PERID9" caption="PERID Write Protection Lock Status" mask="0x200" values="LOCK__PERID"/>
+          <bitfield name="PERID10" caption="PERID Write Protection Lock Status" mask="0x400" values="LOCK__PERID"/>
+          <bitfield name="PERID11" caption="PERID Write Protection Lock Status" mask="0x800" values="LOCK__PERID"/>
+          <bitfield name="PERID12" caption="PERID Write Protection Lock Status" mask="0x1000" values="LOCK__PERID"/>
+          <bitfield name="PERID13" caption="PERID Write Protection Lock Status" mask="0x2000" values="LOCK__PERID"/>
+          <bitfield name="PERID14" caption="PERID Write Protection Lock Status" mask="0x4000" values="LOCK__PERID"/>
+          <bitfield name="PERID15" caption="PERID Write Protection Lock Status" mask="0x8000" values="LOCK__PERID"/>
+          <bitfield name="PERID16" caption="PERID Write Protection Lock Status" mask="0x10000" values="LOCK__PERID"/>
+          <bitfield name="PERID17" caption="PERID Write Protection Lock Status" mask="0x20000" values="LOCK__PERID"/>
+          <bitfield name="PERID18" caption="PERID Write Protection Lock Status" mask="0x40000" values="LOCK__PERID"/>
+          <bitfield name="PERID19" caption="PERID Write Protection Lock Status" mask="0x80000" values="LOCK__PERID"/>
+          <bitfield name="PERID20" caption="PERID Write Protection Lock Status" mask="0x100000" values="LOCK__PERID"/>
+          <bitfield name="PERID21" caption="PERID Write Protection Lock Status" mask="0x200000" values="LOCK__PERID"/>
+          <bitfield name="PERID22" caption="PERID Write Protection Lock Status" mask="0x400000" values="LOCK__PERID"/>
+          <bitfield name="PERID23" caption="PERID Write Protection Lock Status" mask="0x800000" values="LOCK__PERID"/>
+          <bitfield name="PERID24" caption="PERID Write Protection Lock Status" mask="0x1000000" values="LOCK__PERID"/>
+          <bitfield name="PERID25" caption="PERID Write Protection Lock Status" mask="0x2000000" values="LOCK__PERID"/>
+          <bitfield name="PERID26" caption="PERID Write Protection Lock Status" mask="0x4000000" values="LOCK__PERID"/>
+          <bitfield name="PERID27" caption="PERID Write Protection Lock Status" mask="0x8000000" values="LOCK__PERID"/>
+          <bitfield name="PERID28" caption="PERID Write Protection Lock Status" mask="0x10000000" values="LOCK__PERID"/>
+          <bitfield name="PERID29" caption="PERID Write Protection Lock Status" mask="0x20000000" values="LOCK__PERID"/>
+          <bitfield name="PERID30" caption="PERID Write Protection Lock Status" mask="0x40000000" values="LOCK__PERID"/>
+          <bitfield name="PERID31" caption="PERID Write Protection Lock Status" mask="0x80000000" values="LOCK__PERID"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="DISABLE" caption="Macro register accessible in privileged and unprivileged accesses." value="0"/>
+        <value name="ENABLE" caption="Macro registers only accessible in privileged accesses" value="1"/>
+      </value-group>
+      <value-group name="WRCTRL__KEY">
+        <value name="OFF" caption="OFF - No Action" value="0"/>
+        <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+        <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+        <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+      </value-group>
+      <value-group name="STATUS__PERID">
+        <value name="0" caption="Write Protection disabled" value="0"/>
+        <value name="1" caption="Write Protection enabled" value="1"/>
+      </value-group>
+      <value-group name="LOCK__PERID">
+        <value name="0" caption="Write Protection Unlocked" value="0"/>
+        <value name="1" caption="Write Protection Locked" value="1"/>
+      </value-group>
+    </module>
+    <module name="PDM" id="test_pdm_v1" name2="test_pdm_v1" version="1.0.0" caption=""/>
+    <module name="PM" id="03926" name2="pwr_rpmu_pm_v1" version="1c0" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="IORET" caption="I/O Retention" mask="0x4" values="CTRLA__IORET"/>
+        </register>
+        <register name="SLEEPCFG" offset="0x1" rw="RW" size="1" initval="0x02" caption="Sleep Configuration">
+          <bitfield name="SLEEPMODE" caption="Sleep Mode" mask="0x7" values="SLEEPCFG__SLEEPMODE"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="SLEEPRDY" caption="Backup Sleep Mode Entry Ready Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="SLEEPRDY" caption="Backup Sleep Mode Entry Ready Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="SLEEPRDY" caption="Backup Sleep Mode Entry Ready" mask="0x1"/>
+        </register>
+        <register name="STDBYCFG" offset="0x8" rw="RW" size="1" initval="0x04" caption="Standby Configuration">
+          <bitfield name="RAMCFG" caption="Ram Configuration" mask="0x1" values="STDBYCFG__RAMCFG"/>
+          <bitfield name="LPRAM" caption="Low Power RAM Enable" mask="0x4"/>
+        </register>
+        <register name="HIBCFG" offset="0x9" rw="RW" size="1" initval="0x04" caption="Hibernate Configuration">
+          <bitfield name="RAMCFG" caption="Ram Configuration" mask="0x1" values="HIBCFG__RAMCFG"/>
+          <bitfield name="LPRAM" caption="Low Power RAM Enable" mask="0x4"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__IORET">
+        <value name="NOIORET" caption="When  the  device  exits  the  HIBERNATE or BACKUP  mode,  the  I/O  line  configuration are released." value="0x0"/>
+        <value name="IORET" caption="When  the  device  exits  the  HIBERNATE or BACKUP  mode,  the  I/O  line  configuration are stretched." value="0x1"/>
+      </value-group>
+      <value-group name="SLEEPCFG__SLEEPMODE">
+        <value name="IDLE" caption="CPU, AHB and APB clocks are OFF" value="2"/>
+        <value name="STANDBY" caption="All Clocks are OFF" value="4"/>
+        <value name="HIBERNATE" caption="Backup domain is ON as well as some PDRAMs" value="5"/>
+        <value name="BACKUP" caption="Only Backup domain is powered ON" value="6"/>
+        <value name="OFF" caption="All power domains are powered OFF" value="7"/>
+      </value-group>
+      <value-group name="STDBYCFG__RAMCFG">
+        <value name="RET" caption="All the RAMs are retained" value="0"/>
+        <value name="OFF" caption="Only the first 32K bytes are retained" value="1"/>
+      </value-group>
+      <value-group name="HIBCFG__RAMCFG">
+        <value name="RET" caption="All the RAMs are retained" value="0x0"/>
+        <value name="OFF" caption="Only the first 32K bytes are retained" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="03720" name2="gpio_port_u2210_v4" version="4a0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="PORT Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="PORT Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="PORT Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="PORT Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="PORT Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="ODRAIN" caption="Open Drain Output" mask="0x80000"/>
+          <bitfield name="SLEWLIM" caption="Output Driver Slew Rate Selection" mask="0x300000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="EVCTRL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="Event Input Control">
+          <bitfield name="PID0" caption="PORT Event Pin Identifier 0" mask="0x1F"/>
+          <bitfield name="EVACT0" caption="PORT Event Action 0" mask="0x60" values="EVCTRL__EVACT0"/>
+          <bitfield name="PORTEI0" caption="PORT Event Input Enable 0" mask="0x80"/>
+          <bitfield name="PID1" caption="PORT Event Pin Identifier 1" mask="0x1F00"/>
+          <bitfield name="EVACT1" caption="PORT Event Action 1" mask="0x6000"/>
+          <bitfield name="PORTEI1" caption="PORT Event Input Enable 1" mask="0x8000"/>
+          <bitfield name="PID2" caption="PORT Event Pin Identifier 2" mask="0x1F0000"/>
+          <bitfield name="EVACT2" caption="PORT Event Action 2" mask="0x600000"/>
+          <bitfield name="PORTEI2" caption="PORT Event Input Enable 2" mask="0x800000"/>
+          <bitfield name="PID3" caption="PORT Event Pin Identifier 3" mask="0x1F000000"/>
+          <bitfield name="EVACT3" caption="PORT Event Action 3" mask="0x60000000"/>
+          <bitfield name="PORTEI3" caption="PORT Event Input Enable 3" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing for Even-Numbered Pin" mask="0xF" values="PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing for Odd-Numbered Pin" mask="0xF0" values="PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="ODRAIN" caption="Open Drain Output" mask="0x8"/>
+          <bitfield name="SLEWLIM" caption="Output Driver Slew Rate Selection" mask="0x30" values="PINCFG__SLEWLIM"/>
+        </register>
+        <register name="INTENCLR" offset="0x60" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="NSCHK" caption="Non-Secure Check Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x64" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="NSCHK" caption="Non-Secure Check Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x68" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="NSCHK" caption="Non-Secure Check" mask="0x1"/>
+        </register>
+        <register name="NONSEC" offset="0x6C" rw="RW" size="4" initval="0x00000000" caption="Security Attribution">
+          <bitfield name="NONSEC" caption="Port Security Attribution" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NSCHK" offset="0x70" rw="RW" size="4" initval="0x00000000" caption="Security Attribution Check">
+          <bitfield name="NSCHK" caption="Port Security Attribution Check" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" size="0x80" count="4"/>
+      </register-group>
+      <value-group name="EVCTRL__EVACT0">
+        <value name="OUT" caption="Event output to pin" value="0x0"/>
+        <value name="SET" caption="Set output register of pin on event" value="0x1"/>
+        <value name="CLR" caption="Clear output register of pin on event" value="0x2"/>
+        <value name="TGL" caption="Toggle output register of pin on event" value="0x3"/>
+      </value-group>
+      <value-group name="PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0"/>
+        <value name="B" caption="Peripheral function B selected" value="1"/>
+        <value name="D" caption="Peripheral function D selected" value="3"/>
+        <value name="F" caption="Peripheral function F selected" value="5"/>
+        <value name="H" caption="Peripheral function H selected" value="7"/>
+        <value name="I" caption="Peripheral function I selected" value="8"/>
+        <value name="K" caption="Peripheral function K selected" value="10"/>
+        <value name="P" caption="Peripheral function P selected" value="15"/>
+      </value-group>
+      <value-group name="PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0"/>
+        <value name="B" caption="Peripheral function B selected" value="1"/>
+        <value name="D" caption="Peripheral function D selected" value="3"/>
+        <value name="F" caption="Peripheral function F selected" value="5"/>
+        <value name="H" caption="Peripheral function H selected" value="7"/>
+        <value name="I" caption="Peripheral function I selected" value="8"/>
+        <value name="K" caption="Peripheral function K selected" value="10"/>
+        <value name="P" caption="Peripheral function P selected" value="15"/>
+      </value-group>
+      <value-group name="PINCFG__SLEWLIM">
+        <value name="FAST" caption="Slew rate control disabled (fast rise/fall time operation)" value="0x0"/>
+        <value name="SLOW4" caption="Slew rate control enabled (4x slower)" value="0x1"/>
+        <value name="SLOW8" caption="Slew rate control enabled (8x slower)" value="0x2"/>
+        <value name="SLOW12" caption="Slew rate control enabled (12x slower)" value="0x3"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="04743" name2="afe_ptc_ctrl_apb_plrs_v1" version="1a0" caption="Polaris Peripheral Touch Controller">
+      <register-group name="PTC" caption="Polaris Peripheral Touch Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="CONTROL ENABLE REGISTER">
+          <bitfield name="SWRST" caption="Software Reset for this macro." mask="0x1" values="CTRLA__SWRST"/>
+          <bitfield name="ENABLE" caption="PTC -- Enable" mask="0x2" values="CTRLA__ENABLE"/>
+          <bitfield name="PRIV" caption="Privileged Access Only -- provides filtering of privilege/non-privilege bus accesses to SFR registers" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run In Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="EVENT CONTROL REGISTER">
+          <bitfield name="STCONVEI" caption="Start Conversion Event Input Enable" mask="0x1"/>
+          <bitfield name="DSEQREI" caption="DMA Sequencing Restart Event Input Enable" mask="0x2"/>
+          <bitfield name="STCONVINV" caption="Start Conversion Event Invert Enable" mask="0x4"/>
+          <bitfield name="DSEQRINV" caption="DMA Sequencing Restart Event Invert Enable" mask="0x8"/>
+          <bitfield name="EOCEO" caption="End of Conversion Event Output Enable" mask="0x10"/>
+          <bitfield name="WCOMPEO" caption="Window Comparator Event Output Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="DEBUG CONTROL Register">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="CTRLB" offset="0xC" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL B Register">
+          <bitfield name="CTSM" caption="Capacitive Touch Sensing Mode" mask="0x7"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x10"/>
+          <bitfield name="SDS" caption="Sampling Delay Selection." mask="0xF00"/>
+          <bitfield name="ASDV" caption="Automatic Sampling Delay Variation." mask="0x1000"/>
+          <bitfield name="CCDS" caption="Channel Change Delay Selection" mask="0x6000"/>
+          <bitfield name="RSEL" caption="Resistor Selection" mask="0x700000"/>
+        </register>
+        <register name="CTRLC" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL C Register">
+          <bitfield name="CCF" caption="Compensation Capacitor Fine Value" mask="0x1F"/>
+          <bitfield name="CCC" caption="Compensation Capacitor Coarse Value" mask="0x1F00"/>
+          <bitfield name="CI" caption="Integration Capacitor Value" mask="0x1F0000"/>
+          <bitfield name="CSD" caption="Charge Share Delay Value" mask="0xFF000000"/>
+        </register>
+        <register name="CTRLD" offset="0x14" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL D Register">
+          <bitfield name="DAN" caption="Digital Accumulation Number" mask="0x7"/>
+          <bitfield name="AAN" caption="Analog Accumulation Number" mask="0xF00"/>
+          <bitfield name="WINCM" caption="Window Comparator Mode" mask="0x70000"/>
+          <bitfield name="WINSS" caption="Window Single Sample" mask="0x80000"/>
+          <bitfield name="EXTCIEN" caption="External Integration Capacitor Enable" mask="0x300000"/>
+          <bitfield name="POLICC" caption="Polarity of Internal Compensation Capacitor" mask="0x800000"/>
+          <bitfield name="DSEN" caption="DSEN Driven Shield Enable." mask="0x1000000"/>
+          <bitfield name="DSEQSTOP" caption="Stop DMA Sequence" mask="0x80000000"/>
+        </register>
+        <register name="CTRLE" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="CONTROL E REGISTER">
+          <bitfield name="AIPMPEN" caption="Analog Input Charge Pump Enable" mask="0x10"/>
+          <bitfield name="PRSC" caption="This field defines the PTC clock relative to the peripheral clock according to the table below." mask="0x700"/>
+          <bitfield name="WKUPEXP" caption="Wake-Up Exponent" mask="0xF000"/>
+        </register>
+        <register name="SWTRIG" offset="0x1C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Software Trigger Register">
+          <bitfield name="STCONV" caption="Start Conversion" mask="0x1"/>
+        </register>
+        <register name="WINLT" offset="0x20" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Window Comparator Low Threshold Register">
+          <bitfield name="WCLT" caption="Window Comparator Low Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINHT" offset="0x24" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Window Comparator High Threshold Register">
+          <bitfield name="WCHT" caption="Window Comparator High Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="PINEN1" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="PTC Line Enable 1 Register">
+          <bitfield name="PINEN" caption="PTC-Line 31-0 Enable" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PINEN2" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="PTC Line Enable 2 Register">
+          <bitfield name="PINEN" caption="PTC-Line 63-32 Enable" mask="0xF"/>
+        </register>
+        <register name="XSEL1" offset="0x30" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="X Line Selection 1 Register">
+          <bitfield name="XSEL" caption="X-Line Selection [31:0]" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="XSEL2" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="X Line Selection 2 Register">
+          <bitfield name="XSEL" caption="X-Line Selection [63:32]" mask="0xF"/>
+        </register>
+        <register name="YSEL1" offset="0x38" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Y Line Selection 1 Register">
+          <bitfield name="YSEL" caption="Y-Line Selection [31:0]" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="YSEL2" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Y Line Selection 2 Register">
+          <bitfield name="YSEL" caption="Y-Line Selection [63:32]" mask="0xF"/>
+        </register>
+        <register name="POLCTRL1" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Polarity Control 1 Register">
+          <bitfield name="POLARITY" caption="Choose X/Y lines Polarity [31:0]" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="POLCTRL2" offset="0x44" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Polarity Control 2 Register">
+          <bitfield name="POLARITY" caption="Choose X/Y lines Polarity [63:32]" mask="0xF"/>
+        </register>
+        <register name="INTENCLR" offset="0x48" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="INTERRUPT ENABLE CLEAR Register">
+          <bitfield name="EOC" caption="End of Conversion Enable Clear." mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Enable Clear." mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Enable Clear." mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x4C" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="INTERRUPT ENABLE SET Register">
+          <bitfield name="EOC" caption="End of Conversion Enable Set." mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Enable Set." mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Enable Set." mask="0x80"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x50" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="INTERRUPT FLAG SET Register">
+          <bitfield name="EOC" caption="End of Conversion Enable Set." mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Enable Set." mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Enable Set." mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x54" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="INTERRUPT FLAG STATUS and CLEAR Register">
+          <bitfield name="EOC" caption="End of Conversion Flag" mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Flag" mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Flag" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x58" rw="R" size="4" initval="0x00000000" caption="STATUS Register">
+          <bitfield name="PTCBUSY" caption="PTC Busy Status" mask="0x1"/>
+          <bitfield name="DAD" caption="Digital Accumulation Done" mask="0x80"/>
+          <bitfield name="WCC" caption="Window Comparator Counter" mask="0x7F00"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x5C" rw="R" size="4" initval="0x00000000" caption="Synchronization Register">
+          <bitfield name="SWRST" caption="SWRST Synchronization Busy --- Synchronizing Busy bit for swrst" mask="0x1"/>
+          <bitfield name="ENABLE" caption="ENABLE Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Control B Synchronization Busy" mask="0x4"/>
+          <bitfield name="CTRLC" caption="Control C Synchronization Busy" mask="0x8"/>
+          <bitfield name="CTRLD" caption="Control D Synchronization Busy" mask="0x10"/>
+          <bitfield name="SWTRIG" caption="Software Trigger Synchronization Busy" mask="0x20"/>
+          <bitfield name="WINLT" caption="Window Comparator Low Threshold Synchronization Busy" mask="0x40"/>
+          <bitfield name="WINHT" caption="Window Comparator High Threshold Synchronization Busy" mask="0x80"/>
+          <bitfield name="XSEL1" caption="X-lines Selection 1 Synchronization Busy" mask="0x100"/>
+          <bitfield name="XSEL2" caption="X-lines Selection 2 Synchronization Busy" mask="0x200"/>
+          <bitfield name="YSEL1" caption="Y-lines Selection 1 Synchronization Busy" mask="0x400"/>
+          <bitfield name="YSEL2" caption="Y-lines Selection 2 Synchronization Busy" mask="0x800"/>
+          <bitfield name="POLCTRL1" caption="Polarity Control 1 Synchronization Busy" mask="0x1000"/>
+          <bitfield name="POLCTRL2" caption="Polarity Control 2 Synchronization Busy" mask="0x2000"/>
+        </register>
+        <register name="DSEQCTRL" offset="0x60" rw="RW" size="4" initval="0x00000000" caption="DMA SEQUENCE CTRL Register">
+          <bitfield name="CTRLD" caption="Control D." mask="0x1"/>
+          <bitfield name="WINLT" caption="Window Comparator Low Threshold" mask="0x2"/>
+          <bitfield name="WINHT" caption="Window Comparator High Threshold" mask="0x4"/>
+          <bitfield name="XSEL" caption="X-line n Selection lower/upper half word" mask="0x78"/>
+          <bitfield name="YSEL" caption="Y-line n Selection lower/uper half word" mask="0x780"/>
+          <bitfield name="POL" caption="Polarity n lower/upper half word" mask="0x7800"/>
+          <bitfield name="CC" caption="Compensation Capacitor" mask="0x8000"/>
+          <bitfield name="CI" caption="Integration Capacitor" mask="0x10000"/>
+          <bitfield name="CSD" caption="Charge Share Delay" mask="0x20000"/>
+          <bitfield name="AUTOSTART" caption="PTC Auto-Start Conversion." mask="0x80000000"/>
+        </register>
+        <register name="DSEQSTAT" offset="0x64" rw="R" size="4" initval="0x00000000" caption="DMA SEQUENCE STATUS - Register">
+          <bitfield name="CTRLD" caption="Control D." mask="0x1"/>
+          <bitfield name="WINLT" caption="Window Comparator Low Threshold" mask="0x2"/>
+          <bitfield name="WINHT" caption="Window Comparator High Threshold" mask="0x4"/>
+          <bitfield name="XSEL" caption="X-line n  Selection lower/upper half word" mask="0x78"/>
+          <bitfield name="YSEL" caption="Y-line n Selection lower/upper half word" mask="0x780"/>
+          <bitfield name="POL" caption="Polarity n lower/upper half word" mask="0x7800"/>
+          <bitfield name="CC" caption="Compensation Capacitor" mask="0x8000"/>
+          <bitfield name="CI" caption="Integration Capacitor" mask="0x10000"/>
+          <bitfield name="CSD" caption="Charge Share Delay" mask="0x20000"/>
+          <bitfield name="BUSY" caption="Sequencing Busy" mask="0x80000000"/>
+        </register>
+        <register name="DSEQDATA" offset="0x68" rw="W" size="4" initval="0x00000000" caption="DMA SEQUENCE DATA - Register">
+          <bitfield name="DATA" caption="DMA Sequential Data." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="RESULT" offset="0x6C" rw="R" size="4" initval="0x00000000" caption="Register">
+          <bitfield name="RES" caption="Result Conversion Value." mask="0xFFF"/>
+          <bitfield name="ACCRES" caption="Accumulated Result Conversion Value." mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__SWRST">
+        <value name="0" caption="There is no reset operation ongoing" value="0"/>
+        <value name="1" caption="The reset operation is ongoing" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__ENABLE">
+        <value name="0" caption="Disable module. System clock is only requested for bus transactions. GCLK is never requested." value="0"/>
+        <value name="1" caption="Enable module by allowing both the generic clock and system clock requests based on the incoming clock requests from the SIB." value="1"/>
+      </value-group>
+    </module>
+    <module name="RSTC" id="03926" name2="pwr_rpmu_rstc_v1" version="1c0" caption="Reset Controller">
+      <register-group name="RSTC" caption="Reset Controller">
+        <register name="RCAUSE" offset="0x0" rw="R" size="2" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="PORCORE" caption="Brown Out CORE Detector Reset" mask="0x2"/>
+          <bitfield name="BORVDDREG" caption="Brown Out VDDREG Detector Reset" mask="0x4"/>
+          <bitfield name="BORVDDA" caption="Brown Out VDDA Detector Reset" mask="0x8"/>
+          <bitfield name="BORVDDIO" caption="Brown Out VDDIO Detector Reset" mask="0x10"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x20"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x40"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x80"/>
+          <bitfield name="BACKUP" caption="Backup Reset" mask="0x100"/>
+          <bitfield name="LOCKUP" caption="Lockup Reset" mask="0x200"/>
+        </register>
+        <register name="BKUPEXIT" offset="0x2" rw="R" size="1" initval="0x00" caption="Backup Exit Source. Implemented only if RSTC_BACKUP_IMPLEMENTED=1">
+          <bitfield name="RTC" caption="Real Timer Counter Interrupt" mask="0x2"/>
+          <bitfield name="HIB0" caption="Hibernate" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Debug Control">
+          <bitfield name="LCKUPDIS" caption="Lockup Disable" mask="0x1"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="RTC" id="03608" name2="tmr_rtc_u2250_v3" version="3b0" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <mode name="MODE2" qualifier="RTC.MODE2.CTRLA.MODE" value="2" caption="Clock/Calendar with Alarm"/>
+        <register modes="MODE2" name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="MODE2_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register modes="MODE2" name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="MODE2_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group name="RTC" caption="Real-Time Counter">
+        <mode name="MODE0" qualifier="RTC.MODE0.CTRLA.MODE" value="0" caption="32-bit Counter with Single 32-bit Compare"/>
+        <mode name="MODE1" qualifier="RTC.MODE1.CTRLA.MODE" value="1" caption="16-bit Counter with Two 16-bit Compares"/>
+        <mode name="MODE2" qualifier="RTC.MODE2.CTRLA.MODE" value="2" caption="Clock/Calendar with Alarm"/>
+        <register modes="MODE0" name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="MODE0_CTRLA__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="MODE0_CTRLA__PRESCALER"/>
+          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
+          <bitfield name="COUNTSYNC" caption="Count Read Synchronization Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="MODE1_CTRLA__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="MODE1_CTRLA__PRESCALER"/>
+          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
+          <bitfield name="COUNTSYNC" caption="Count Read Synchronization Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="MODE2_CTRLA__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="MODE2_CTRLA__PRESCALER"/>
+          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
+          <bitfield name="CLOCKSYNC" caption="Clock Read Synchronization Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE0 Control B">
+          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
+          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
+          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
+          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
+          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
+          <bitfield name="DEBF" caption="Debounce Frequency" mask="0x700" values="MODE0_CTRLB__DEBF"/>
+          <bitfield name="ACTF" caption="Active Layer Frequency" mask="0x7000" values="MODE0_CTRLB__ACTF"/>
+          <bitfield name="SEPTO" caption="Separate Tamper Outputs" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE1 Control B">
+          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
+          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
+          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
+          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
+          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
+          <bitfield name="DEBF" caption="Debounce Frequency" mask="0x700" values="MODE1_CTRLB__DEBF"/>
+          <bitfield name="ACTF" caption="Active Layer Frequency" mask="0x7000" values="MODE1_CTRLB__ACTF"/>
+          <bitfield name="SEPTO" caption="Separate Tamper Outputs" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE2 Control B">
+          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
+          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
+          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
+          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
+          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
+          <bitfield name="DEBF" caption="Debounce Frequency" mask="0x700" values="MODE2_CTRLB__DEBF"/>
+          <bitfield name="ACTF" caption="Active Layer Frequency" mask="0x7000" values="MODE2_CTRLB__ACTF"/>
+          <bitfield name="SEPTO" caption="Separate Tamper Outputs" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
+          <bitfield name="PERDEO" caption="Periodic Interval Daily Event Output Enable" mask="0x1000000"/>
+        </register>
+        <register modes="MODE1" name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="CMPEO2" caption="Compare 2 Event Output Enable" mask="0x400"/>
+          <bitfield name="CMPEO3" caption="Compare 3 Event Output Enable" mask="0x800"/>
+          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
+          <bitfield name="PERDEO" caption="Periodic Interval Daily Event Output Enable" mask="0x1000000"/>
+        </register>
+        <register modes="MODE2" name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="ALARMEO1" caption="Alarm 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
+          <bitfield name="PERDEO" caption="Periodic Interval Daily Event Output Enable" mask="0x1000000"/>
+        </register>
+        <register modes="MODE0" name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="CMP2" caption="Compare 2 Interrupt Enable" mask="0x400"/>
+          <bitfield name="CMP3" caption="Compare 3 Interrupt Enable" mask="0x800"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="ALARM1" caption="Alarm 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="CMP2" caption="Compare 2 Interrupt Enable" mask="0x400"/>
+          <bitfield name="CMP3" caption="Compare 3 Interrupt Enable" mask="0x800"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="PER0" caption="Periodic Interval 0 Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Enable" mask="0x80"/>
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="ALARM1" caption="Alarm 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x200"/>
+          <bitfield name="CMP2" caption="Compare 2" mask="0x400"/>
+          <bitfield name="CMP3" caption="Compare 3" mask="0x800"/>
+          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x100"/>
+          <bitfield name="ALARM1" caption="Alarm 1" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
+        </register>
+        <register name="DBGCTRL" offset="0xE" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register modes="MODE0" name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE0 Synchronization Busy Status">
+          <bitfield name="SWRST" caption="Software Reset Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
+          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
+          <bitfield name="COUNT" caption="COUNT Register Busy" mask="0x8"/>
+          <bitfield name="COMP0" caption="COMP 0 Register Busy" mask="0x20"/>
+          <bitfield name="COMP1" caption="COMP 1 Register Busy" mask="0x40"/>
+          <bitfield name="COUNTSYNC" caption="Count Synchronization Enable Bit Busy" mask="0x8000"/>
+          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
+          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
+          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
+          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
+        </register>
+        <register modes="MODE1" name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE1 Synchronization Busy Status">
+          <bitfield name="SWRST" caption="Software Reset Bit Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
+          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
+          <bitfield name="COUNT" caption="COUNT Register Busy" mask="0x8"/>
+          <bitfield name="PER" caption="PER Register Busy" mask="0x10"/>
+          <bitfield name="COMP0" caption="COMP 0 Register Busy" mask="0x20"/>
+          <bitfield name="COMP1" caption="COMP 1 Register Busy" mask="0x40"/>
+          <bitfield name="COMP2" caption="COMP 2 Register Busy" mask="0x80"/>
+          <bitfield name="COMP3" caption="COMP 3 Register Busy" mask="0x100"/>
+          <bitfield name="COUNTSYNC" caption="Count Synchronization Enable Bit Busy" mask="0x8000"/>
+          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
+          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
+          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
+          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
+        </register>
+        <register modes="MODE2" name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE2 Synchronization Busy Status">
+          <bitfield name="SWRST" caption="Software Reset Bit Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
+          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
+          <bitfield name="CLOCK" caption="CLOCK Register Busy" mask="0x8"/>
+          <bitfield name="ALARM0" caption="ALARM 0 Register Busy" mask="0x20"/>
+          <bitfield name="ALARM1" caption="ALARM 1 Register Busy" mask="0x40"/>
+          <bitfield name="MASK0" caption="MASK 0 Register Busy" mask="0x800"/>
+          <bitfield name="MASK1" caption="MASK 1 Register Busy" mask="0x1000"/>
+          <bitfield name="CLOCKSYNC" caption="Clock Synchronization Enable Bit Busy" mask="0x8000"/>
+          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
+          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
+          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
+          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
+        </register>
+        <register name="FREQCORR" offset="0x14" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register modes="MODE0" name="COUNT" offset="0x18" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="MODE1" name="COUNT" offset="0x18" rw="RW" access="RSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register modes="MODE2" name="CLOCK" offset="0x18" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register modes="MODE1" name="PER" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register modes="MODE0" name="COMP" offset="0x20" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="MODE1" name="COMP" offset="0x20" rw="RW" access="WSYNC" size="2" count="4" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+        <register-group modes="MODE2" name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x20" size="0x8" count="2"/>
+        <register name="GP" offset="0x40" rw="RW" access="WSYNC" size="4" count="4" initval="0x00000000" caption="General Purpose">
+          <bitfield name="GP" caption="General Purpose" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TAMPCTRL" offset="0x60" rw="RW" size="4" initval="0x00000000" caption="Tamper Control">
+          <bitfield name="IN0ACT" caption="Tamper Input 0 Action" mask="0x3" values="TAMPCTRL__IN0ACT"/>
+          <bitfield name="IN1ACT" caption="Tamper Input 1 Action" mask="0xC" values="TAMPCTRL__IN1ACT"/>
+          <bitfield name="IN2ACT" caption="Tamper Input 2 Action" mask="0x30" values="TAMPCTRL__IN2ACT"/>
+          <bitfield name="IN3ACT" caption="Tamper Input 3 Action" mask="0xC0" values="TAMPCTRL__IN3ACT"/>
+          <bitfield name="IN4ACT" caption="Tamper Input 4 Action" mask="0x300" values="TAMPCTRL__IN4ACT"/>
+          <bitfield name="IN5ACT" caption="Tamper Input 5 Action" mask="0xC00" values="TAMPCTRL__IN5ACT"/>
+          <bitfield name="IN6ACT" caption="Tamper Input 6 Action" mask="0x3000" values="TAMPCTRL__IN6ACT"/>
+          <bitfield name="IN7ACT" caption="Tamper Input 7 Action" mask="0xC000" values="TAMPCTRL__IN7ACT"/>
+          <bitfield name="TAMLVL0" caption="Tamper Level Select 0" mask="0x10000"/>
+          <bitfield name="TAMLVL1" caption="Tamper Level Select 1" mask="0x20000"/>
+          <bitfield name="TAMLVL2" caption="Tamper Level Select 2" mask="0x40000"/>
+          <bitfield name="TAMLVL3" caption="Tamper Level Select 3" mask="0x80000"/>
+          <bitfield name="TAMLVL4" caption="Tamper Level Select 4" mask="0x100000"/>
+          <bitfield name="TAMLVL5" caption="Tamper Level Select 5" mask="0x200000"/>
+          <bitfield name="TAMLVL6" caption="Tamper Level Select 6" mask="0x400000"/>
+          <bitfield name="TAMLVL7" caption="Tamper Level Select 7" mask="0x800000"/>
+          <bitfield name="DEBNC0" caption="Debouncer Enable 0" mask="0x1000000"/>
+          <bitfield name="DEBNC1" caption="Debouncer Enable 1" mask="0x2000000"/>
+          <bitfield name="DEBNC2" caption="Debouncer Enable 2" mask="0x4000000"/>
+          <bitfield name="DEBNC3" caption="Debouncer Enable 3" mask="0x8000000"/>
+          <bitfield name="DEBNC4" caption="Debouncer Enable 4" mask="0x10000000"/>
+          <bitfield name="DEBNC5" caption="Debouncer Enable 5" mask="0x20000000"/>
+          <bitfield name="DEBNC6" caption="Debouncer Enable 6" mask="0x40000000"/>
+          <bitfield name="DEBNC7" caption="Debouncer Enable 7" mask="0x80000000"/>
+        </register>
+        <register modes="MODE0" name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" ocd-rw="" size="4" initval="0x00000000" caption="MODE0 Timestamp">
+          <bitfield name="COUNT" caption="Count Timestamp Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="MODE1" name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" ocd-rw="" size="4" initval="0x00000000" caption="MODE1 Timestamp">
+          <bitfield name="COUNT" caption="Count Timestamp Value" mask="0xFFFF"/>
+        </register>
+        <register modes="MODE2" name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" ocd-rw="" size="4" initval="0x00000000" caption="MODE2 Timestamp">
+          <bitfield name="SECOND" caption="Second Timestamp Value" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute Timestamp Value" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour Timestamp Value" mask="0x1F000"/>
+          <bitfield name="DAY" caption="Day Timestamp Value" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month Timestamp Value" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year Timestamp Value" mask="0xFC000000"/>
+        </register>
+        <register name="TAMPID" offset="0x68" rw="RW" size="4" atomic-op="clear:TAMPID" initval="0x00000000" caption="Tamper ID">
+          <bitfield name="TAMPID0" caption="Tamper Input 0 Detected" mask="0x1"/>
+          <bitfield name="TAMPID1" caption="Tamper Input 1 Detected" mask="0x2"/>
+          <bitfield name="TAMPID2" caption="Tamper Input 2 Detected" mask="0x4"/>
+          <bitfield name="TAMPID3" caption="Tamper Input 3 Detected" mask="0x8"/>
+          <bitfield name="TAMPID4" caption="Tamper Input 4 Detected" mask="0x10"/>
+          <bitfield name="TAMPID5" caption="Tamper Input 5 Detected" mask="0x20"/>
+          <bitfield name="TAMPID6" caption="Tamper Input 6 Detected" mask="0x40"/>
+          <bitfield name="TAMPID7" caption="Tamper Input 7 Detected" mask="0x80"/>
+          <bitfield name="TAMPEVT" caption="Tamper Event Detected" mask="0x80000000"/>
+        </register>
+        <register name="TAMPCTRLB" offset="0x6C" rw="RW" size="4" initval="0x00000000" caption="Tamper Control B">
+          <bitfield name="ALSI0" caption="Active Layer Select Internal 0" mask="0x1"/>
+          <bitfield name="ALSI1" caption="Active Layer Select Internal 1" mask="0x2"/>
+          <bitfield name="ALSI2" caption="Active Layer Select Internal 2" mask="0x4"/>
+          <bitfield name="ALSI3" caption="Active Layer Select Internal 3" mask="0x8"/>
+          <bitfield name="ALSI4" caption="Active Layer Select Internal 4" mask="0x10"/>
+          <bitfield name="ALSI5" caption="Active Layer Select Internal 5" mask="0x20"/>
+          <bitfield name="ALSI6" caption="Active Layer Select Internal 6" mask="0x40"/>
+          <bitfield name="ALSI7" caption="Active Layer Select Internal 7" mask="0x80"/>
+        </register>
+      </register-group>
+      <value-group name="MODE2_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="MODE2_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+      <value-group name="MODE0_CTRLA__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="MODE0_CTRLA__PRESCALER">
+        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x1"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x2"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x3"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x4"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x5"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x6"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x7"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x8"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x9"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
+      </value-group>
+      <value-group name="MODE1_CTRLA__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="2"/>
+      </value-group>
+      <value-group name="MODE1_CTRLA__PRESCALER">
+        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0"/>
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="1"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="2"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="3"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="4"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="5"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="6"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="7"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="8"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="9"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
+      </value-group>
+      <value-group name="MODE2_CTRLA__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="2"/>
+      </value-group>
+      <value-group name="MODE2_CTRLA__PRESCALER">
+        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x1"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x2"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x3"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x4"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x5"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x6"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x7"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x8"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x9"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
+      </value-group>
+      <value-group name="MODE0_CTRLB__DEBF">
+        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE0_CTRLB__ACTF">
+        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE1_CTRLB__DEBF">
+        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE1_CTRLB__ACTF">
+        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE2_CTRLB__DEBF">
+        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE2_CTRLB__ACTF">
+        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN0ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN1ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN2ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN3ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN4ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN4 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN5ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN5 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN6ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN6 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN7ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN7 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+    </module>
+    <module name="SAU" id="SYSTEM_IP" version="1.0.0" caption="Security Attribution Unit">
+      <register-group name="SAU" caption="Security Attribution Unit">
+        <register name="SAU_CTRL" offset="0x0" rw="RW" size="4" access-size="4" caption="SAU Control Register">
+          <bitfield name="ENABLE" caption="SAU enable" mask="0x1"/>
+          <bitfield name="ALLNS" caption="All Non-secure" mask="0x2"/>
+        </register>
+        <register name="SAU_TYPE" offset="0x4" rw="R" size="4" access-size="4" caption="SAU Type Register">
+          <bitfield name="SREGION" caption="Number of SAU regions" mask="0xFF"/>
+        </register>
+        <register name="SAU_RNR" offset="0x8" rw="RW" size="4" access-size="4" caption="SAU Region Number Register">
+          <bitfield name="REGION" caption="Selected SAU region number" mask="0xFF"/>
+        </register>
+        <register name="SAU_RBAR" offset="0xC" rw="RW" size="4" access-size="4" caption="SAU Region Base Address Register">
+          <bitfield name="BADDR" caption="Base address" mask="0xFFFFFFE0"/>
+        </register>
+        <register name="SAU_RLAR" offset="0x10" rw="RW" size="4" access-size="4" caption="SAU Region Limit Address Register">
+          <bitfield name="ENABLE" caption="SAU region enable" mask="0x1"/>
+          <bitfield name="NSC" caption="Non-secure callable region" mask="0x2"/>
+          <bitfield name="LADDR" caption="Limit address" mask="0xFFFFFFE0"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="SCB" id="SYSTEM_IP" version="1.0.0" caption="System Control Block">
+      <register-group name="SCB" caption="System Control Block">
+        <register name="CPUID" offset="0x0" rw="R" size="4" access-size="4" caption="CPUID base register">
+          <bitfield name="Revision" caption="Revision number" mask="0xF"/>
+          <bitfield name="PartNo" caption="Part number, 0xD20=Cortex-M23" mask="0xFFF0"/>
+          <bitfield name="Architecture" caption="Architecture version, 0xC=ARMv8-M Base Line, 0xF=ARMv8-M Main Line" mask="0xF0000"/>
+          <bitfield name="Variant" caption="Variant number" mask="0xF00000"/>
+          <bitfield name="Implementer" caption="Implementer code, ARM=0x41" mask="0xFF000000"/>
+        </register>
+        <register name="ICSR" offset="0x4" rw="RW" size="4" access-size="4" caption="Interrupt Control and State Register">
+          <bitfield name="VECTACTIVE" caption="Vector active" mask="0x1FF"/>
+          <bitfield name="RETTOBASE" caption="Return to base" mask="0x800"/>
+          <bitfield name="VECTPENDING" caption="Vector pending" mask="0x1FF000"/>
+          <bitfield name="ISRPENDING" caption="Interrupt pending" mask="0x400000"/>
+          <bitfield name="ISRPREEMPT" caption="Interrupt preempt" mask="0x800000"/>
+          <bitfield name="PENDSTCLR" caption="Pend SysTick clear" mask="0x2000000" values="ICSR__PENDSTCLR"/>
+          <bitfield name="PENDSTSET" caption="Pend SysTick set" mask="0x4000000" values="ICSR__PENDSTSET"/>
+          <bitfield name="PENDSVCLR" caption="Pend PendSV clear" mask="0x8000000" values="ICSR__PENDSVCLR"/>
+          <bitfield name="PENDSVSET" caption="Pend PendSV set" mask="0x10000000" values="ICSR__PENDSVSET"/>
+          <bitfield name="PENDNMICLR" caption="Pend NMI clear" mask="0x40000000"/>
+          <bitfield name="PENDNMISET" caption="Pend NMI set" mask="0x80000000" values="ICSR__PENDNMISET"/>
+        </register>
+        <register name="VTOR" offset="0x8" rw="RW" size="4" access-size="4" caption="Vector Table Offset Register">
+          <bitfield name="TBLOFF" caption="Vector table base offset" mask="0xFFFFFF80"/>
+        </register>
+        <register name="AIRCR" offset="0xC" rw="RW" size="4" access-size="4" caption="Application Interrupt and Reset Control Register">
+          <bitfield name="VECTCLRACTIVE" caption="Debug: Clear Active State" mask="0x2" values="AIRCR__VECTCLRACTIVE"/>
+          <bitfield name="SYSRESETREQ" caption="System Reset Request" mask="0x4" values="AIRCR__SYSRESETREQ"/>
+          <bitfield name="SYSRESETREQS" caption="System Reset Request Secure only" mask="0x8" values="AIRCR__SYSRESETREQS"/>
+          <bitfield name="BFHFNMINS" caption="BusFault, HardFault and NMI Non-secure enable" mask="0x2000" values="AIRCR__BFHFNMINS"/>
+          <bitfield name="PRIS" caption="Prioritize Secure Exceptions" mask="0x4000" values="AIRCR__PRIS"/>
+          <bitfield name="ENDIANNESS" caption="Data Endianness, 0=little, 1=big" mask="0x8000" values="AIRCR__ENDIANNESS"/>
+          <bitfield name="VECTKEY" caption="Register Key (0x05FA)" mask="0xFFFF0000"/>
+        </register>
+        <register name="SCR" offset="0x10" rw="RW" size="4" access-size="4" caption="System Control Register">
+          <bitfield name="SLEEPONEXIT" caption="Sleep on exit" mask="0x2" values="SCR__SLEEPONEXIT"/>
+          <bitfield name="SLEEPDEEP" caption="Sleep deep" mask="0x4" values="SCR__SLEEPDEEP"/>
+          <bitfield name="SLEEPDEEPS" caption="Sleep deep secure" mask="0x8"/>
+          <bitfield name="SEVONPEND" caption="Send Event on Pending bit" mask="0x10" values="SCR__SEVONPEND"/>
+        </register>
+        <register name="CCR" offset="0x14" rw="RW" size="4" access-size="4" caption="Configuration and Control Register">
+          <bitfield name="USERSETMPEND" caption="User set main pending" mask="0x2"/>
+          <bitfield name="UNALIGN_TRP" caption="Unaligned trap" mask="0x8" values="CCR__UNALIGN_TRP"/>
+          <bitfield name="DIV_0_TRP" caption="Divide by zero trap" mask="0x10"/>
+          <bitfield name="BFHFNMIGN" caption="BusFault in HardFault or NMI ignore" mask="0x100"/>
+          <bitfield name="STKOFHFNMIGN" caption="Stack overflow in HardFault and NMI ignore" mask="0x400"/>
+          <bitfield name="DC" caption="Data cache enable" mask="0x10000"/>
+          <bitfield name="IC" caption="Instruction cache enable" mask="0x20000"/>
+          <bitfield name="BP" caption="Branch prediction enable" mask="0x40000"/>
+        </register>
+        <register name="SHPR2" offset="0x1C" rw="RW" size="4" access-size="4" caption="System Handler Priority Register 2">
+          <bitfield name="PRI_11" caption="Priority of system handler 11, SVCall" mask="0xFF000000"/>
+        </register>
+        <register name="SHPR3" offset="0x20" rw="RW" size="4" access-size="4" caption="System Handler Priority Register 3">
+          <bitfield name="PRI_12" caption="Priority of system handler 12, DebugMonitor" mask="0xFF"/>
+          <bitfield name="PRI_14" caption="Priority of system handler 14, PendSV" mask="0xFF0000"/>
+          <bitfield name="PRI_15" caption="Priority of system handler 15, SysTick" mask="0xFF000000"/>
+        </register>
+        <register name="SHCSR" offset="0x24" rw="RW" size="4" access-size="4" caption="System Handler Control and State Register">
+          <bitfield name="HARDFAULTACT" caption="HardFault exception active state" mask="0x4"/>
+          <bitfield name="NMIACT" caption="NMI exception active state" mask="0x20"/>
+          <bitfield name="SVCALLACT" caption="SVCall exception active state" mask="0x80"/>
+          <bitfield name="PENDSVACT" caption="PendSV exception active state" mask="0x400"/>
+          <bitfield name="SYSTICKACT" caption="SysTick exception active state" mask="0x800"/>
+          <bitfield name="SVCALLPENDED" caption="SVCall exception pended state" mask="0x8000"/>
+          <bitfield name="HARDFAULTPENDED" caption="HardFault exception pended state" mask="0x200000"/>
+        </register>
+        <register name="DFSR" offset="0x30" rw="RW" size="4" access-size="4" caption="Debug Fault Status Register">
+          <bitfield name="HALTED" caption="Halt or step event" mask="0x1"/>
+          <bitfield name="BKPT" caption="Breakpoint event" mask="0x2"/>
+          <bitfield name="DWTTRAP" caption="Watchpoint event" mask="0x4"/>
+          <bitfield name="VCATCH" caption="Vector Catch event" mask="0x8"/>
+          <bitfield name="EXTERNAL" caption="External event" mask="0x10"/>
+        </register>
+        <register name="AFSR" offset="0x3C" rw="RW" size="4" access-size="4" caption="Auxiliary Fault Status Register"/>
+        <register name="CLIDR" offset="0x78" rw="R" size="4" access-size="4" caption="Cache Level ID Register">
+          <bitfield name="Ctype1" caption="Cache type at level 1" mask="0x7" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype2" caption="Cache type at level 2" mask="0x38" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype3" caption="Cache type at level 3" mask="0x1C0" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype4" caption="Cache type at level 4" mask="0xE00" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype5" caption="Cache type at level 5" mask="0x7000" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype6" caption="Cache type at level 6" mask="0x38000" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype7" caption="Cache type at level 7" mask="0x1C0000" values="CLIDR__Ctype"/>
+          <bitfield name="LoUIS" caption="Level of Unification Inner Shareable" mask="0xE00000"/>
+          <bitfield name="LoC" caption="Level of Coherence" mask="0x7000000"/>
+          <bitfield name="LoUU" caption="Level of Unification Uniprocessor" mask="0x38000000"/>
+          <bitfield name="ICB" caption="Inner cache boundary" mask="0xC0000000" values="CLIDR__ICB"/>
+        </register>
+        <register name="CTR" offset="0x7C" rw="R" size="4" access-size="4" caption="Cache Type Register">
+          <bitfield name="IminLine" caption="Instruction cache minimum line length" mask="0xF"/>
+          <bitfield name="DminLine" caption="Data cache minimum line length" mask="0xF0000"/>
+          <bitfield name="ERG" caption="Exclusives Reservation Granule" mask="0xF00000"/>
+          <bitfield name="CWG" caption="Cache Write-back Granule" mask="0xF000000"/>
+          <bitfield name="Format" caption="Cache Type Register format" mask="0xE0000000" values="CTR__Format"/>
+        </register>
+        <register name="CCSIDR" offset="0x80" rw="R" size="4" access-size="4" caption="Current Cache Size ID register">
+          <bitfield name="LineSize" caption="log2(number of words per line) - 2" mask="0x7"/>
+          <bitfield name="Associativity" caption="Associativity - 1" mask="0x1FF8"/>
+          <bitfield name="NumSets" caption="Number of sets - 1" mask="0xFFFE000"/>
+          <bitfield name="WA" caption="Write-Allocate" mask="0x10000000"/>
+          <bitfield name="RA" caption="Read-Allocate" mask="0x20000000"/>
+          <bitfield name="WB" caption="Write-Back" mask="0x40000000"/>
+          <bitfield name="WT" caption="Write-Through" mask="0x80000000"/>
+        </register>
+        <register name="CSSELR" offset="0x84" rw="RW" size="4" access-size="4" caption="Cache Size Selection Register">
+          <bitfield name="InD" caption="Instruction not Data" mask="0x1"/>
+          <bitfield name="Level" caption="Cache level - 1" mask="0xE"/>
+        </register>
+      </register-group>
+      <value-group name="ICSR__PENDSTCLR">
+        <value name="VALUE_0" caption="No effect" value="0"/>
+        <value name="VALUE_1" caption="Removes the pending state from the SysTick exception" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDSTSET">
+        <value name="VALUE_0" caption="Write: no effect; read: SysTick exception is not pending" value="0"/>
+        <value name="VALUE_1" caption="Write: changes SysTick exception state to pending; read: SysTick exception is pending" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDSVCLR">
+        <value name="VALUE_0" caption="No effect" value="0"/>
+        <value name="VALUE_1" caption="Removes the pending state from the PendSV exception" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDSVSET">
+        <value name="VALUE_0" caption="Write: no effect; read: PendSV exception is not pending" value="0"/>
+        <value name="VALUE_1" caption="Write: changes PendSV exception state to pending; read: PendSV exception is pending" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDNMISET">
+        <value name="VALUE_0" caption="Write: no effect; read: NMI exception is not pending" value="0"/>
+        <value name="VALUE_1" caption="Write: changes NMI exception state to pending; read: NMI exception is pending" value="1"/>
+      </value-group>
+      <value-group name="AIRCR__VECTCLRACTIVE">
+        <value name="NO" caption="Do not clear active state" value="0x0"/>
+        <value name="YES" caption="Clear active state" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__SYSRESETREQ">
+        <value name="NO" caption="Do not request a system reset" value="0"/>
+        <value name="YES" caption="Request a system reset" value="1"/>
+      </value-group>
+      <value-group name="AIRCR__SYSRESETREQS">
+        <value name="BOTH" caption="SYSRESETREQ functionality is available to both Security states" value="0x0"/>
+        <value name="SECURE" caption="SYSRESETREQ functionality is only available to Secure state" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__BFHFNMINS">
+        <value name="SECURE" caption="BusFault, HardFault, and NMI are Secure" value="0x0"/>
+        <value name="NON_SECURE" caption="BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__PRIS">
+        <value name="SAME" caption="Priority ranges of Secure and Non-secure exceptions are identical" value="0x0"/>
+        <value name="NS_DEPRIO" caption="Non-secure exceptions are de-prioritized" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__ENDIANNESS">
+        <value name="LITTLE" caption="Little-endian" value="0"/>
+        <value name="BIG" caption="Big-endian" value="1"/>
+      </value-group>
+      <value-group name="SCR__SLEEPONEXIT">
+        <value name="VALUE_0" caption="O not sleep when returning to Thread mode" value="0"/>
+        <value name="VALUE_1" caption="Enter sleep, or deep sleep, on return from an ISR" value="1"/>
+      </value-group>
+      <value-group name="SCR__SLEEPDEEP">
+        <value name="VALUE_0" caption="Sleep" value="0"/>
+        <value name="VALUE_1" caption="Deep sleep" value="1"/>
+      </value-group>
+      <value-group name="SCR__SEVONPEND">
+        <value name="VALUE_0" caption="Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded" value="0"/>
+        <value name="VALUE_1" caption="Enabled events and all interrupts, including disabled interrupts, can wakeup the processor" value="1"/>
+      </value-group>
+      <value-group name="CCR__UNALIGN_TRP">
+        <value name="VALUE_0" caption="Do not trap unaligned halfword and word accesses" value="0"/>
+        <value name="VALUE_1" caption="Trap unaligned halfword and word accesses" value="1"/>
+      </value-group>
+      <value-group name="CLIDR__Ctype">
+        <value name="NO" caption="No cache" value="0"/>
+        <value name="IC" caption="Instruction cache only" value="1"/>
+        <value name="DC" caption="Data cache only" value="2"/>
+        <value name="SEPARATE" caption="Separate instruction and data caches" value="3"/>
+        <value name="UNIFIED" caption="Unified cache" value="4"/>
+      </value-group>
+      <value-group name="CLIDR__ICB">
+        <value name="NO" caption="Not disclosed in this mechanism" value="0"/>
+        <value name="L1" caption="L1 cache is the highest inner level" value="1"/>
+        <value name="L2" caption="L2 cache is the highest inner level" value="2"/>
+        <value name="L3" caption="L3 cache is the highest inner level" value="3"/>
+      </value-group>
+      <value-group name="CTR__Format">
+        <value name="NO" caption="No cache type information provided" value="0"/>
+        <value name="YES" caption="Cache type information is provided" value="4"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="03715" name2="com_sercom_u2201_v6" version="6c0" caption="Serial Communication Interface">
+      <register-group name="SERCOM" caption="Serial Communication Interface">
+        <mode name="I2CM" qualifier="SERCOM.I2CM_CTRLA.MODE" value="5" caption="I2C Master Mode"/>
+        <mode name="I2CS" qualifier="SERCOM.I2CS_CTRLA.MODE" value="4" caption="I2C Slave Mode"/>
+        <mode name="SPI" qualifier="SERCOM.SPI_CTRLA.MODE" mask="6" value="2" caption="SPI Mode"/>
+        <mode name="USART" qualifier="SERCOM.USART_CTRLA.MODE" mask="6" value="0" caption="USART Mode"/>
+        <register modes="I2CM" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="FILTSEL" caption="Input Filter Selection" mask="0x300" values="I2CM_CTRLA__FILTSEL"/>
+          <bitfield name="SLEWRATE" caption="Slew Rate Selection" mask="0xC00" values="I2CM_CTRLA__SLEWRATE"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SMBUSEN" caption="SMBUS Input Buffer Enable" mask="0x20000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000" values="I2CM_CTRLA__SDAHOLD"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000" values="I2CM_CTRLA__SPEED"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000" values="I2CM_CTRLA__INACTOUT"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register modes="I2CS" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="FILTSEL" caption="Input Filter Selection" mask="0x300"/>
+          <bitfield name="SLEWRATE" caption="Slew Rate Selection" mask="0xC00" values="I2CS_CTRLA__SLEWRATE"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SMBUSEN" caption="SMBUS Input Buffer Enable" mask="0x20000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000" values="I2CS_CTRLA__SDAHOLD"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000" values="I2CS_CTRLA__SPEED"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register modes="SPI" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000" values="SPI_CTRLA__DOPO"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000" values="SPI_CTRLA__DIPO"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000" values="SPI_CTRLA__FORM"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000" values="SPI_CTRLA__CPHA"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000" values="SPI_CTRLA__CPOL"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000" values="SPI_CTRLA__DORD"/>
+        </register>
+        <register modes="USART" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="TXINV" caption="Transmit Data Invert" mask="0x200" values="USART_CTRLA__TXINV"/>
+          <bitfield name="RXINV" caption="Receive Data Invert" mask="0x400" values="USART_CTRLA__RXINV"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000" values="USART_CTRLA__SAMPR"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000" values="USART_CTRLA__TXPO"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000" values="USART_CTRLA__RXPO"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000" values="USART_CTRLA__FORM"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000" values="USART_CTRLA__CMODE"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000" values="USART_CTRLA__DORD"/>
+        </register>
+        <register modes="I2CM" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="I2CM_CTRLB__FIFOCLR"/>
+        </register>
+        <register modes="I2CS" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000" values="I2CS_CTRLB__AMODE"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="I2CS_CTRLB__FIFOCLR"/>
+        </register>
+        <register modes="SPI" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7" values="SPI_CTRLB__CHSIZE"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200" values="SPI_CTRLB__SSDE"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000" values="SPI_CTRLB__MSSEN"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000" values="SPI_CTRLB__AMODE"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="SPI_CTRLB__FIFOCLR"/>
+        </register>
+        <register modes="USART" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7" values="USART_CTRLB__CHSIZE"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40" values="USART_CTRLB__SBMODE"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400" values="USART_CTRLB__ENC"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000" values="USART_CTRLB__PMODE"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="USART_CTRLB__FIFOCLR"/>
+          <bitfield name="LINCMD" caption="LIN Command" mask="0x3000000" values="USART_CTRLB__LINCMD"/>
+        </register>
+        <register modes="I2CM" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="I2CM Control C">
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="I2CM_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="I2CM_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="I2CS" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="I2CS Control C">
+          <bitfield name="SDASETUP" caption="SDA Setup Time" mask="0xF"/>
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="I2CS_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="I2CS_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="SPI" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="SPI Control C">
+          <bitfield name="ICSPACE" caption="Inter-Character Spacing" mask="0x3F"/>
+          <bitfield name="FSES" caption="Frame Synch Edge Select" mask="0x100"/>
+          <bitfield name="FSLEN" caption="Frame Synch Length" mask="0x200" values="SPI_CTRLC__FSLEN"/>
+          <bitfield name="FSPOL" caption="Frame Synch Polarity" mask="0x400" values="SPI_CTRLC__FSPOL"/>
+          <bitfield name="IGNTUR" caption="Ignore Transmit Underrun" mask="0x800"/>
+          <bitfield name="FRMEN" caption="Frame mode enable" mask="0x10000"/>
+          <bitfield name="FMODE" caption="Frame mode" mask="0x20000" values="SPI_CTRLC__FMODE"/>
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="SPI_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="SPI_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="USART" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="USART Control C">
+          <bitfield name="GTIME" caption="Guard Time" mask="0x7"/>
+          <bitfield name="BRKLEN" caption="LIN Master Break Length" mask="0x300" values="USART_CTRLC__BRKLEN"/>
+          <bitfield name="HDRDLY" caption="LIN Master Header Delay" mask="0xC00" values="USART_CTRLC__HDRDLY"/>
+          <bitfield name="INACK" caption="Inhibit Not Acknowledge" mask="0x10000"/>
+          <bitfield name="DSNACK" caption="Disable Successive NACK" mask="0x20000"/>
+          <bitfield name="MAXITER" caption="Maximum Iterations" mask="0x700000"/>
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x3000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="USART_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="USART_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="I2CM" name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register modes="SPI" name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register modes="USART" name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT" qualifier="SERCOM.USART.CTRLA.FORM" value="0" caption="Default"/>
+          <mode name="FRAC" qualifier="SERCOM.USART.CTRLA.FORM" value="4" caption="Fractional Baud mode"/>
+          <mode name="FRACFP" qualifier="SERCOM.USART.CTRLA.FORM" value="5" caption="Fractional Baud with Parity mode"/>
+          <mode name="USARTFP" qualifier="SERCOM.USART.CTRLA.FORM" value="1" caption="USART Frame with Parity mode"/>
+          <bitfield modes="FRAC FRACFP" name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+          <bitfield modes="FRAC FRACFP" name="FP" caption="Fractional Part" mask="0xE000"/>
+          <bitfield modes="DEFAULT USARTFP" name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+        </register>
+        <register modes="USART" name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register modes="I2CM" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Disable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="I2CS" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Disable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="SPI" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="USART" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Enable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="I2CS" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Enable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="SPI" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="USART" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="I2CS" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="SPI" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="USART" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="STATUS" offset="0x1A" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register modes="I2CS" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+          <bitfield name="LENERR" caption="Transaction Length Error" mask="0x800"/>
+        </register>
+        <register modes="SPI" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="TUR" caption="Frame Transmit Underrun" mask="0x8"/>
+          <bitfield name="LENERR" caption="Transaction Length Error" mask="0x800"/>
+        </register>
+        <register modes="USART" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+          <bitfield name="TXE" caption="Transmitter Empty" mask="0x40"/>
+          <bitfield name="ITER" caption="Maximum Number of Repetitions Reached" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+          <bitfield name="LENGTH" caption="Length Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="I2CS" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+          <bitfield name="LENGTH" caption="Length Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="SPI" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+          <bitfield name="LENGTH" caption="LENGTH Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="USART" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+          <bitfield name="RXERRCNT" caption="RXERRCNT Synchronization Busy" mask="0x8"/>
+          <bitfield name="LENGTH" caption="LENGTH Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="USART" name="RXERRCNT" offset="0x20" rw="R" access="RSYNC" size="1" initval="0x00" caption="USART Receive Error Count"/>
+        <register modes="I2CS" name="LENGTH" offset="0x22" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="I2CS Length">
+          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
+          <bitfield name="LENEN" caption="Data Length Enable" mask="0x100"/>
+        </register>
+        <register modes="SPI" name="LENGTH" offset="0x22" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="SPI Length">
+          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
+          <bitfield name="LENEN" caption="Data Length Enable" mask="0x100"/>
+        </register>
+        <register modes="USART" name="LENGTH" offset="0x22" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="USART Length">
+          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
+          <bitfield name="LENEN" caption="Data Length Enable" mask="0x300" values="USART_LENGTH__LENEN"/>
+        </register>
+        <register modes="I2CM" name="ADDR" offset="0x24" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register modes="I2CS" name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register modes="SPI" name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register modes="I2CM" name="DATA" offset="0x28" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="I2CS" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="SPI" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="USART" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="I2CM" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+        <register modes="SPI" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+        <register modes="USART" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+        <register modes="I2CM" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="I2CM FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="I2CS" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="I2CS FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="SPI" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="SPI FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="USART" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="USART FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="I2CM" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="I2CM FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+        <register modes="I2CS" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="I2CS FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+        <register modes="SPI" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="SPI FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+        <register modes="USART" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="USART FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+      </register-group>
+      <value-group name="I2CM_CTRLA__MODE">
+        <value name="I2C_MASTER" caption="I2C host mode operation" value="5"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__FILTSEL">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="50NS" caption="Minimum 50ns filter" value="0x2"/>
+        <value name="10NS" caption="Minimum 10ns filter" value="0x3"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__SLEWRATE">
+        <value name="SMM" caption="Standard mode" value="0x0"/>
+        <value name="FM" caption="Fast mode" value="0x1"/>
+        <value name="FMP" caption="Fast mode plus" value="0x2"/>
+        <value name="HS" caption="High-speed mode" value="0x3"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__SDAHOLD">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="75NS" caption="50ns - 100ns hold time" value="0x1"/>
+        <value name="450NS" caption="300ns - 600ns hold time" value="0x2"/>
+        <value name="600NS" caption="400ns - 800ns hold time" value="0x3"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__SPEED">
+        <value name="SM" caption="Standard-Mode (SM) and Fast-Mode (FM)" value="0x0"/>
+        <value name="FMP" caption="Fast-Mode Plus (FM+)" value="0x1"/>
+        <value name="HS" caption="High-Speed Mode" value="0x2"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__INACTOUT">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="55US" caption="5-6 SCL cycle time-out" value="0x1"/>
+        <value name="105US" caption="10-11 SCL cycle time-out" value="0x2"/>
+        <value name="205US" caption="20-21-6 SCL cycle time-out" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__MODE">
+        <value name="I2C_SLAVE" caption="I2C client mode operation" value="0x4"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__SLEWRATE">
+        <value name="SM" caption="Standard mode" value="0x0"/>
+        <value name="FM" caption="Fast mode" value="0x1"/>
+        <value name="FMP" caption="Fast mode plus" value="0x2"/>
+        <value name="HS" caption="High-speed mode" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__SDAHOLD">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="75NS" caption="50ns - 100ns hold time" value="0x1"/>
+        <value name="450NS" caption="300ns - 600ns hold time" value="0x2"/>
+        <value name="600NS" caption="400ns - 800ns hold time" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__SPEED">
+        <value name="SM" caption="Standard-Mode (SM) and Fast-Mode (FM)" value="0x0"/>
+        <value name="FMP" caption="Fast-Mode Plus (FM+)" value="0x1"/>
+        <value name="HS" caption="High-Speed Mode" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__MODE">
+        <value name="SLAVE" caption="SPI slave operation" value="0x2"/>
+        <value name="MASTER" caption="SPI master operation" value="0x3"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__DOPO">
+        <value name="PAD0" caption="DO on PAD[0], SCK on PAD[1] and SS on PAD[2]" value="0x0"/>
+        <value name="PAD3" caption="DO on PAD[3], SCK on PAD[1] and SS on PAD[2]" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__DIPO">
+        <value name="PAD0" caption="SERCOM PAD0 is used as data input" value="0x0"/>
+        <value name="PAD1" caption="SERCOM PAD1 is used as data input" value="0x1"/>
+        <value name="PAD2" caption="SERCOM PAD2 is used as data input" value="0x2"/>
+        <value name="PAD3" caption="SERCOM PAD3 is used as data input" value="0x3"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__FORM">
+        <value name="SPI" caption="SPI frame" value="0x0"/>
+        <value name="ADDR" caption="SPI frame with address" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__CPHA">
+        <value name="LEADING_EDGE" caption="The data is sampled on a leading SCK edge and changed on a trailing SCK edge" value="0x0"/>
+        <value name="TRAILING_EDGE" caption="The data is sampled on a trailing SCK edge and changed on a leading SCK edge" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__CPOL">
+        <value name="LOW" caption="SCK is low when idle" value="0x0"/>
+        <value name="HIGH" caption="SCK is high when idle" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__DORD">
+        <value name="MSB" caption="MSB is transmitted first" value="0x0"/>
+        <value name="LSB" caption="LSB is transmitted first" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__MODE">
+        <value name="EXTCLK" caption="USART with external clock" value="0x0"/>
+        <value name="INTCLK" caption="Usart with internal clock" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__TXINV">
+        <value name="DISABLE" caption="TxD is not inverted" value="0x0"/>
+        <value name="INV" caption="TxD is inverted" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__RXINV">
+        <value name="DISABLE" caption="RxD is not inverted" value="0x0"/>
+        <value name="INV" caption="RxD is inverted" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__SAMPR">
+        <value name="ARITHM16X" caption="16x oversampling using arithmetic baud rate generation" value="0x0"/>
+        <value name="FRAC16X" caption="16x oversampling using fractional baud rate generation" value="0x1"/>
+        <value name="ARITHM8X" caption="8x oversampling using arithmetic baud rate generation" value="0x2"/>
+        <value name="FRAC8X" caption="8x oversampling using fractional baud rate generation" value="0x3"/>
+        <value name="ARITHM3X" caption="3x oversampling using arithmetic baud rate generation" value="0x4"/>
+      </value-group>
+      <value-group name="USART_CTRLA__TXPO">
+        <value name="PAD0" caption="PAD[0] = TxD; PAD[1] = XCK" value="0x0"/>
+        <value name="PAD2" caption="PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS" value="0x2"/>
+        <value name="PAD3" caption="PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLA__RXPO">
+        <value name="PAD0" caption="SERCOM PAD0 is used for data reception" value="0x0"/>
+        <value name="PAD1" caption="SERCOM PAD1 is used for data reception" value="0x1"/>
+        <value name="PAD2" caption="SERCOM PAD2 is used for data reception" value="0x2"/>
+        <value name="PAD3" caption="SERCOM PAD3 is used for data reception" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLA__FORM">
+        <value name="USART" caption="USART frame" value="0x0"/>
+        <value name="USARTP" caption="USART frame with parity" value="0x1"/>
+        <value name="LINBRKGEN" caption="LIN Master Break and Synck generation" value="0x2"/>
+        <value name="LINBRKDET" caption="LIN Slave break detection and auto-baud" value="0x4"/>
+        <value name="BRKDET" caption="Break detection and auto-baud with parity" value="0x5"/>
+      </value-group>
+      <value-group name="USART_CTRLA__CMODE">
+        <value name="ASYNC" caption="Asynchronous communication." value="0x0"/>
+        <value name="SYNC" caption="Synchronous communication." value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__DORD">
+        <value name="MSB" caption="MSB is transmitted first." value="0x0"/>
+        <value name="LSB" caption="LSB is transmitted first." value="0x1"/>
+      </value-group>
+      <value-group name="I2CM_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLB__AMODE">
+        <value name="MASK" caption="The slave responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK" value="0x0"/>
+        <value name="2ADDRS" caption="The slave responds to the two unique addresses in ADDR and ADDRMASK" value="0x1"/>
+        <value name="RANGE" caption="The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit" value="0x2"/>
+      </value-group>
+      <value-group name="I2CS_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__CHSIZE">
+        <value name="8BITS" caption="8-bits character" value="0x0"/>
+        <value name="9BITS" caption="9-bits character" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__SSDE">
+        <value name="DISABLE" caption="SS low detector is disabled" value="0x0"/>
+        <value name="ENABLE" caption="SS low detector is enabled" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__MSSEN">
+        <value name="DISABLE" caption="Hardware SS control is disabled" value="0x0"/>
+        <value name="ENABLE" caption="Hardware SS control is enabled" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__AMODE">
+        <value name="MASK" caption="ADDRMASK is used as a mask to the AADR register" value="0x0"/>
+        <value name="2ADDRS" caption="The slave responds to the two unique addresses in ADDR and ADDRMASK" value="0x1"/>
+        <value name="RANGE" caption="The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLB__CHSIZE">
+        <value name="8BITS" caption="8-bits character" value="0x0"/>
+        <value name="9BITS" caption="9-bits character" value="0x1"/>
+        <value name="5BITS" caption="5-bits character" value="0x5"/>
+        <value name="6BITS" caption="6-bits character" value="0x6"/>
+        <value name="7BITS" caption="7-bits character" value="0x7"/>
+      </value-group>
+      <value-group name="USART_CTRLB__SBMODE">
+        <value name="ONE" caption="One stop bit" value="0x0"/>
+        <value name="TWO" caption="Two stop bits" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLB__ENC">
+        <value name="DISABLE" caption="Data is not encoded" value="0x0"/>
+        <value name="IRDA" caption="Data is IrDA encoded" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLB__PMODE">
+        <value name="EVEN" caption="Even parity" value="0x0"/>
+        <value name="ODD" caption="Odd parity" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLB__LINCMD">
+        <value name="NONE" caption="Normal USART transmission" value="0x0"/>
+        <value name="SOFTWARE_CONTROL_TRANSMIT_CMD" caption="Break field is transmitted when DATA is written" value="0x1"/>
+        <value name="AUTO_TRANSMIT_CMD" caption="Break, synch and identifier are automaticcaly transmitted when DATA is written with the identifier" value="0x2"/>
+      </value-group>
+      <value-group name="I2CM_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="I2CM_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x2"/>
+      </value-group>
+      <value-group name="I2CS_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="I2CS_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__FSLEN">
+        <value name="STROBE" caption="One SCK pulse" value="0x0"/>
+        <value name="LEVEL" caption="One frame duration" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__FSPOL">
+        <value name="HIGH" caption="VCC-level valid polarity" value="0x0"/>
+        <value name="LOW" caption="GND-level valid polarity" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__FMODE">
+        <value name="MASTER" caption="Frame Master" value="0x0"/>
+        <value name="SLAVE" caption="Frame Slave" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated as long as the FIFO is empty" value="0x2"/>
+      </value-group>
+      <value-group name="USART_CTRLC__BRKLEN">
+        <value name="13BITS" caption="Break field transmission is 13 bit times" value="0x0"/>
+        <value name="17BITS" caption="Break field transmission is 17 bit times" value="0x1"/>
+        <value name="21BITS" caption="Break field transmission is 21 bit times" value="0x2"/>
+        <value name="26BITS" caption="Break field transmission is 26 bit times" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLC__HDRDLY">
+        <value name="1BIT" caption="Delay between break and sync transmission is 1-bit time" value="0x0"/>
+        <value name="4BITS" caption="Delay between break and sync transmission is 4-bit time" value="0x1"/>
+        <value name="8BITS" caption="Delay between break and sync transmission is 8-bit time" value="0x2"/>
+        <value name="14BITS" caption="Delay between break and sync transmission is 14-bit time" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="USART_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated when the FIFO is empty" value="0x2"/>
+      </value-group>
+      <value-group name="USART_LENGTH__LENEN">
+        <value name="DISABLE" caption="Length counter is disabled" value="0x0"/>
+        <value name="TX" caption="Length counter is enabled for transmit" value="0x1"/>
+        <value name="RX" caption="Length counter is enabled for receive" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="SUPC" id="03926" name2="pwr_rpmu_supc_v1" version="1c0" caption="Supply Controller">
+      <register-group name="SUPC" caption="Supply Controller">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="LVDET" caption="Low Voltage Detector Interrupt Enable" mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO Regulator Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Interrupt Enable" mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Interrupt Enable" mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="LVDET" caption="Low Voltage Detector Interrupt Enable" mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO Regulator Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Interrupt Enable" mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Interrupt Enable" mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="LVDET" caption="Low Voltage Detector Interrupt. Set to one if VDDIO crosses the treshold voltage in the good direction according to LVD.DIR." mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Interrupt. Set to one if LVD is ready to operate." mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO Regulator Ready Interrupt. Set to one if ULDO is ready meaning that output voltage is correct." mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Interrupt. Is set to one if overheat condition is detected." mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Interrupt. Set to one if VDDUSB issue is detected." mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct." mask="0x100"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Flag status">
+          <bitfield name="LVDET" caption="Low Voltage Detector Status." mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Status" mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO regulator Status. It corresponds to vreg_ready_mv signal from ULDO." mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Status. It corresponds to vreg_overheat_event_mv signal from ULDO." mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Status. One if VDDUSB is OK. It corresponds to bor_vddusb_n_mv signal of SMOR." mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator." mask="0x100"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Synchronisation Busy">
+          <bitfield name="BOR" caption="BOR Synchronization Busy" mask="0x1"/>
+        </register>
+        <register name="BOR" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="BOR Control">
+          <bitfield name="DCBORPSEL" caption="Duty Cycle BOR Prescaler Select" mask="0x70" values="BOR__DCBORPSEL"/>
+          <bitfield name="BORFILT" caption="BOR filtering" mask="0x300" values="BOR__BORFILT"/>
+        </register>
+        <register name="LVD" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="LVD Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="DIR" caption="Direction" mask="0x4" values="LVD__DIR"/>
+          <bitfield name="OEVEN" caption="Output Event Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x10"/>
+          <bitfield name="LEVEL" caption="Threshold Level. See &quot;pwr_smor_[nn]_v1 DOS&quot; - level section to get details." mask="0xF0000"/>
+        </register>
+        <register name="VREGCTRL" offset="0x1C" rw="RW" size="4" initval="0x00000004" caption="VREG Control">
+          <bitfield name="VREGOUT" caption="VREG Output Control in RUN mode only. Enable by production fuse by CALSUPC.VREGOUTEN" mask="0x3" values="VREGCTRL__VREGOUT"/>
+          <bitfield name="OFFSTDBY" caption="Off in Standby Control for VREGSW[N-1]. Useful for Riverside only." mask="0x4" values="VREGCTRL__OFFSTDBY"/>
+          <bitfield name="LVSTDBY" caption="Low Voltage Standby Enable" mask="0x10" values="VREGCTRL__LVSTDBY"/>
+          <bitfield name="LVHIB" caption="Low Voltage Hibernate Enable" mask="0x20" values="VREGCTRL__LVHIB"/>
+          <bitfield name="CPEN" caption="Charge Pump Enable and Auto-enable." mask="0x300"/>
+          <bitfield name="ULDOEN" caption="User LDO Voltage Regulator Enable" mask="0x1000"/>
+          <bitfield name="ULDOSTDBY" caption="User LDO Voltage Regulator Configuration" mask="0x2000" values="VREGCTRL__ULDOSTDBY"/>
+          <bitfield name="ULDOLEVEL" caption="User LDO Voltage Level Selection" mask="0xC000" values="VREGCTRL__ULDOLEVEL"/>
+          <bitfield name="AVREGEN" caption="Additional Voltage Regulator Enable" mask="0x10000"/>
+          <bitfield name="AVREGSTDBY" caption="Additional Voltage Regulator Configuration" mask="0x1000000" values="VREGCTRL__AVREGSTDBY"/>
+          <bitfield name="SRAM_VLD" caption="SRAM VALID Status Bit" mask="0x40000000"/>
+          <bitfield name="BKUP_VLD" caption="Backup Domain Valid Status Bit" mask="0x80000000"/>
+        </register>
+        <register name="VREFCTRL" offset="0x20" rw="RW" size="4" initval="0x00000002" caption="VREF Control">
+          <bitfield name="LPSTDBY" caption="Bandgap and Regulators Low Power Standby Enable" mask="0x1" values="VREFCTRL__LPSTDBY"/>
+          <bitfield name="LPHIB" caption="Bandgap and Regulators Low Power Hibernate Enable" mask="0x2" values="VREFCTRL__LPHIB"/>
+          <bitfield name="TSEN" caption="Temperature Sensor Output Enable" mask="0x10"/>
+        </register>
+        <register name="BKOUT" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="Backup Output Control">
+          <bitfield name="EN0" caption="Enable Output" mask="0x1"/>
+          <bitfield name="EN1" caption="Enable Output" mask="0x4"/>
+          <bitfield name="CLR0" caption="Clear Output" mask="0x100"/>
+          <bitfield name="CLR1" caption="Clear Output" mask="0x400"/>
+          <bitfield name="SET0" caption="Set Output" mask="0x10000"/>
+          <bitfield name="SET1" caption="Set Output" mask="0x40000"/>
+          <bitfield name="TGLOM0" caption="Toggle Output Mode" mask="0x3000000" values="BKOUT__TGLOM"/>
+          <bitfield name="TGLOM1" caption="Toggle Output Mode" mask="0xC000000" values="BKOUT__TGLOM"/>
+        </register>
+        <register name="BKIN" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Backup Input Control">
+          <bitfield name="BKIN" caption="Backup Input Value" mask="0x3"/>
+        </register>
+      </register-group>
+      <value-group name="BOR__DCBORPSEL">
+        <value name="NODIV" caption="Not Divided" value="0x0"/>
+        <value name="DIV2" caption="Divide clock by 2" value="0x1"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x2"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x3"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x4"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x5"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x6"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x7"/>
+      </value-group>
+      <value-group name="BOR__BORFILT">
+        <value name="NOFILT" caption="No digital filtering" value="0x0"/>
+        <value name="FILT32US" caption="32us filtering" value="0x1"/>
+        <value name="FILT125US" caption="125us filtering" value="0x2"/>
+        <value name="FILT250US" caption="250us filtering" value="0x3"/>
+      </value-group>
+      <value-group name="LVD__DIR">
+        <value name="rising" caption="Rising detection" value="0x0"/>
+        <value name="falling" caption="Falling detection" value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__VREGOUT">
+        <value name="1p2v" caption="In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.2v." value="0x0"/>
+        <value name="1p0v" caption="In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.0v." value="0x1"/>
+        <value name="0p8v" caption="In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 0.8v." value="0x2"/>
+      </value-group>
+      <value-group name="VREGCTRL__OFFSTDBY">
+        <value name="OFF" caption="In standby mode, VREGSW1,2,3 are OFF" value="0x0"/>
+        <value name="ON" caption="In standby mode, VREGSW1,2,3 are ON" value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__LVSTDBY">
+        <value name="1p2v" caption="In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 1.2v." value="0x0"/>
+        <value name="0p8v" caption="In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 0.8v." value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__LVHIB">
+        <value name="1p2v" caption="In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 1.2v." value="0x0"/>
+        <value name="0p8v" caption="In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 0.8v" value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__ULDOSTDBY">
+        <value name="OFFINSTDBY" caption="Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well." value="0x0"/>
+        <value name="ONINSTDBY" caption="Regulator is ON in Standby mode. is OFF from Hibernate mode. It is OFF in backup mode as well." value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__ULDOLEVEL">
+        <value name="1p2v" caption="Vout = 1.2v" value="0x0"/>
+        <value name="1p5v" caption="Vout = 1.5v" value="0x1"/>
+        <value name="1p8v" caption="Vout = 1.8v" value="0x2"/>
+        <value name="2p5v" caption="Vout = 2.5v" value="0x3"/>
+      </value-group>
+      <value-group name="VREGCTRL__AVREGSTDBY">
+        <value name="OFFINSTDBY" caption="Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well." value="0x0"/>
+        <value name="ONINSTDBY" caption="Regulator is ON in Standby mode if AVREGEN bit is set. is OFF from Hibernate mode. It is OFF in backup mode as well." value="0x1"/>
+      </value-group>
+      <value-group name="VREFCTRL__LPSTDBY">
+        <value name="FullPower" caption="In standby mode, bandgap and enabled regulator(s) are set to nominal power mode." value="0x0"/>
+        <value name="LowPower" caption="In standby mode, bandgap and enabled regulator(s) are set to low power mode." value="0x1"/>
+      </value-group>
+      <value-group name="VREFCTRL__LPHIB">
+        <value name="FullPower" caption="In hibernate mode, bandgap is set to nominal power mode. As a consequence, enabled regulator(s) are set to nominal power mode." value="0x0"/>
+        <value name="LowPower" caption="In hibernate mode, bandgap is set to low power mode. As a consequence, enabled regulator(s) are set to low power mode." value="0x1"/>
+      </value-group>
+      <value-group name="BKOUT__TGLOM">
+        <value name="DISABLE" caption="The output does not toggle." value="0x0"/>
+        <value name="RTCTGL" caption="The output toggles on RTC event." value="0x1"/>
+        <value name="BKUPTGL" caption="The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software." value="0x2"/>
+      </value-group>
+    </module>
+    <module name="SysTick" id="SYSTEM_IP" version="1.0.0" caption="SysTick Timer">
+      <register-group name="SysTick" caption="SysTick Timer">
+        <register name="SYST_CSR" offset="0x0" rw="RW" size="4" access-size="4" caption="SysTick Control and Status Register">
+          <bitfield name="ENABLE" caption="SysTick enable" mask="0x1"/>
+          <bitfield name="TICKINT" caption="Tick interrupt" mask="0x2"/>
+          <bitfield name="CLKSOURCE" caption="Clock source" mask="0x4"/>
+          <bitfield name="COUNTFLAG" caption="Count flag" mask="0x10000"/>
+        </register>
+        <register name="SYST_RVR" offset="0x4" rw="RW" size="4" access-size="4" caption="SysTick Reload Value Register">
+          <bitfield name="RELOAD" caption="Counter reload value" mask="0x1000000"/>
+        </register>
+        <register name="SYST_CVR" offset="0x8" rw="RW" size="4" access-size="4" caption="SysTick Current Value Register">
+          <bitfield name="CURRENT" caption="Current counter value" mask="0x1000000"/>
+        </register>
+        <register name="SYST_CALIB" offset="0xC" rw="R" size="4" access-size="4" caption="SysTick Calibration Value Register">
+          <bitfield name="TENMS" caption="Ten milliseconds" mask="0xFFFFFF"/>
+          <bitfield name="SKEW" caption="Skew" mask="0x40000000"/>
+          <bitfield name="NOREF" caption="No reference" mask="0x80000000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="TCC" id="03610" name2="tmr_tcc_u2213_v4" version="4d0" caption="Timer Counter for Control Applications">
+      <register-group name="TCC" caption="Timer Counter for Control Applications">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="MSYNC" caption="Master Synchronization (only for TCC Slave Instance)" mask="0x8000"/>
+          <bitfield name="FCYCLE" caption="Full Cycle" mask="0x10000"/>
+          <bitfield name="DMAOS" caption="DMA One-shot Trigger Mode" mask="0x800000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="RWSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period Busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKPRESC" caption="Fault A Blanking Prescaler" mask="0x8000"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKPRESC" caption="Fault B Blanking Prescaler" mask="0x8000"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="UFS" caption="Non-Recoverable Update Fault Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="UFS" caption="Non-Recoverable Update Fault Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="UFS" caption="Non-Recoverable Update Fault" mask="0x400"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" access="RWSYNC" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="UFS" caption="Non-recoverable Update Fault State" mask="0x4"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBUFV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="PERBUFV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBUFV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBUFV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH6" name="COUNT" caption="Counter Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="COUNT" caption="Counter Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="COUNT" caption="Counter Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x70" values="WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0x0000FFFF" caption="Period">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHER" caption="Dithering Cycle Number" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHER" caption="Dithering Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHER" caption="Dithering Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="PER" caption="Period Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="PER" caption="Period Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="PER" caption="Period Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="PER" caption="Period Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHER" caption="Dithering Cycle Number" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHER" caption="Dithering Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHER" caption="Dithering Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="CC" caption="Channel Compare/Capture Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="CC" caption="Channel Compare/Capture Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="CC" caption="Channel Compare/Capture Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="CC" caption="Channel Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+        <register name="PERBUF" offset="0x6C" rw="RW" access="WSYNC" size="4" initval="0x0000FFFF" caption="Period Buffer">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="PERBUF" caption="Period Buffer Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="PERBUF" caption="Period Buffer Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="PERBUF" caption="Period Buffer Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="PERBUF" caption="Period Buffer Value" mask="0xFFFF"/>
+        </register>
+        <register name="CCBUF" offset="0x70" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHERBUF" caption="Channel Compare/Capture Buffer Value" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="CCBUF" caption="Dithering Buffer Cycle Number" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update or double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+        <value name="DMAOS" caption="One-shot DMA trigger" value="5"/>
+      </value-group>
+      <value-group name="CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update or double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+        <value name="DMAOS" caption="One-shot DMA trigger" value="5"/>
+      </value-group>
+      <value-group name="FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__BLANK">
+        <value name="START" caption="Blanking applied from start of the ramp" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+        <value name="CAPTMARK" caption="Capture with ramp index as MSB value" value="7"/>
+      </value-group>
+      <value-group name="FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__BLANK">
+        <value name="START" caption="Blanking applied from start of the ramp" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+        <value name="CAPTMARK" caption="Capture with ramp index as MSB value" value="7"/>
+      </value-group>
+      <value-group name="EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="STAMP" caption="Stamp capture" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DPWM" caption="Dual compare PWM" value="3"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+        <value name="RAMP2C" caption="Critical RAMP2 operation" value="3"/>
+        <value name="RAMP2CS" caption="Critical Swapped RAMP2 operation" value="4"/>
+      </value-group>
+    </module>
+    <module name="TESTVAL" id="test_valio_mapper_v1" name2="test_valio_mapper_v1" version="1.0.0" caption=""/>
+    <module name="USB" id="03613" name2="usb_u2222_v1" version="1d0" caption="Full-Speed Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <register modes="DEVICE" name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="DEVICE" name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register modes="DEVICE" name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register modes="DEVICE" name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register modes="HOST" name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="HOST" name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register modes="HOST" name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register modes="HOST" name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register modes="HOST" name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register modes="HOST" name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <register modes="DEVICE" name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register modes="DEVICE" name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register modes="DEVICE" name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register modes="HOST" name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register modes="HOST" name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register modes="HOST" name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register modes="HOST" name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register modes="HOST" name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group name="USB" caption="Full-Speed Universal Serial Bus">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x0F" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC"/>
+        </register>
+        <register modes="DEVICE" name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register modes="HOST" name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="HOST_CTRLB__SPDCONF"/>
+          <bitfield name="AUTORESUME" caption="Auto Resume Enable" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register modes="DEVICE" name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register modes="HOST" name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register modes="DEVICE" name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register modes="HOST" name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register modes="HOST" name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register modes="DEVICE" name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register modes="HOST" name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register modes="DEVICE" name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register modes="HOST" name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register modes="DEVICE" name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register modes="HOST" name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register modes="DEVICE" name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group modes="DEVICE" name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" size="0x20" count="8"/>
+        <register-group modes="HOST" name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" size="0x20" count="8"/>
+      </register-group>
+      <register-group name="USB_DESCRIPTOR" caption="Full-Speed Universal Serial Bus">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register-group modes="DEVICE" name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" size="0x10" count="2"/>
+        <register-group modes="HOST" name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" size="0x10" count="2"/>
+      </register-group>
+      <value-group name="CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="LS" caption="Low-speed mode" value="0x1"/>
+        <value name="HS" caption="High-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="03611" name2="wdt_u2251_v2" version="2b0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run During Standby" mask="0x40"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="WEN" caption="Window Enable Synchronization Busy" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run During Standby Synchronization Busy" mask="0x8"/>
+          <bitfield name="ALWAYSON" caption="Always-On Synchronization Busy" mask="0x10"/>
+          <bitfield name="CLEAR" caption="Clear Synchronization Busy" mask="0x20"/>
+        </register>
+        <register name="CLEAR" offset="0xC" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="CONFIG__PER">
+        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="CONFIG__WINDOW">
+        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="EWCTRL__EWOFFSET">
+        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  </modules>
+  <pinouts>
+    <pinout name="P64" caption="P64">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA10"/>
+      <pin position="5" pad="PA11"/>
+      <pin position="6" pad="PA12"/>
+      <pin position="7" pad="PA03"/>
+      <pin position="8" pad="PA04"/>
+      <pin position="9" pad="VDDIO"/>
+      <pin position="10" pad="VSSIO2"/>
+      <pin position="11" pad="PA05"/>
+      <pin position="12" pad="PA06"/>
+      <pin position="13" pad="PA13"/>
+      <pin position="14" pad="PA07"/>
+      <pin position="15" pad="PA08"/>
+      <pin position="16" pad="PA09"/>
+      <pin position="17" pad="PB00"/>
+      <pin position="18" pad="PB07"/>
+      <pin position="19" pad="AVDD"/>
+      <pin position="20" pad="AVSS"/>
+      <pin position="21" pad="PB01"/>
+      <pin position="22" pad="PB02"/>
+      <pin position="23" pad="VDDIO"/>
+      <pin position="24" pad="VSSIO4"/>
+      <pin position="25" pad="VDDREG"/>
+      <pin position="26" pad="PB03"/>
+      <pin position="27" pad="PB04"/>
+      <pin position="28" pad="PB05"/>
+      <pin position="29" pad="PB08"/>
+      <pin position="30" pad="PB09"/>
+      <pin position="31" pad="PB06"/>
+      <pin position="32" pad="PB10"/>
+      <pin position="33" pad="PC00"/>
+      <pin position="34" pad="PC01"/>
+      <pin position="35" pad="VDDIO"/>
+      <pin position="36" pad="VSSIO6"/>
+      <pin position="37" pad="PC02"/>
+      <pin position="38" pad="PC03"/>
+      <pin position="39" pad="PC09"/>
+      <pin position="40" pad="PC04"/>
+      <pin position="41" pad="PC10"/>
+      <pin position="42" pad="RESET_N"/>
+      <pin position="43" pad="VDDIO"/>
+      <pin position="44" pad="VSSIO7"/>
+      <pin position="45" pad="PC05"/>
+      <pin position="46" pad="PC06"/>
+      <pin position="47" pad="PC07"/>
+      <pin position="48" pad="PC08"/>
+      <pin position="49" pad="PD00"/>
+      <pin position="50" pad="PD10"/>
+      <pin position="51" pad="PD11"/>
+      <pin position="52" pad="PD01"/>
+      <pin position="53" pad="PD02"/>
+      <pin position="54" pad="PD03"/>
+      <pin position="55" pad="PD12"/>
+      <pin position="56" pad="PD13"/>
+      <pin position="57" pad="VSSIO"/>
+      <pin position="58" pad="VDDF"/>
+      <pin position="59" pad="USERLDO"/>
+      <pin position="60" pad="PD07"/>
+      <pin position="61" pad="PD04"/>
+      <pin position="62" pad="PD05"/>
+      <pin position="63" pad="PD08"/>
+      <pin position="64" pad="PD09"/>
+    </pinout>
+    <pinout name="P64_1" caption="P64_1">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA10"/>
+      <pin position="5" pad="PA11"/>
+      <pin position="6" pad="PA12"/>
+      <pin position="7" pad="PA03"/>
+      <pin position="8" pad="PA04"/>
+      <pin position="9" pad="VDDIO"/>
+      <pin position="10" pad="VSSIO2"/>
+      <pin position="11" pad="PA05"/>
+      <pin position="12" pad="PA06"/>
+      <pin position="13" pad="PA13"/>
+      <pin position="14" pad="PA07"/>
+      <pin position="15" pad="PA08"/>
+      <pin position="16" pad="PA09"/>
+      <pin position="17" pad="PB00"/>
+      <pin position="18" pad="PB07"/>
+      <pin position="19" pad="AVDD"/>
+      <pin position="20" pad="AVSS"/>
+      <pin position="21" pad="PB01"/>
+      <pin position="22" pad="PB02"/>
+      <pin position="23" pad="VDDIO"/>
+      <pin position="24" pad="VSSIO4"/>
+      <pin position="25" pad="VDDREG"/>
+      <pin position="26" pad="PB03"/>
+      <pin position="27" pad="PB04"/>
+      <pin position="28" pad="PB05"/>
+      <pin position="29" pad="PB08"/>
+      <pin position="30" pad="PB09"/>
+      <pin position="31" pad="PB06"/>
+      <pin position="32" pad="PB10"/>
+      <pin position="33" pad="PC00"/>
+      <pin position="34" pad="PC01"/>
+      <pin position="35" pad="VDDIO"/>
+      <pin position="36" pad="VSSIO6"/>
+      <pin position="37" pad="PC02"/>
+      <pin position="38" pad="PC03"/>
+      <pin position="39" pad="PC09"/>
+      <pin position="40" pad="PC04"/>
+      <pin position="41" pad="PC10"/>
+      <pin position="42" pad="RESET_N"/>
+      <pin position="43" pad="VDDIO"/>
+      <pin position="44" pad="VSSIO7"/>
+      <pin position="45" pad="PC05"/>
+      <pin position="46" pad="PC06"/>
+      <pin position="47" pad="PC07"/>
+      <pin position="48" pad="PC08"/>
+      <pin position="49" pad="PD00"/>
+      <pin position="50" pad="PD10"/>
+      <pin position="51" pad="PD11"/>
+      <pin position="52" pad="PD01"/>
+      <pin position="53" pad="PD02"/>
+      <pin position="54" pad="PD03"/>
+      <pin position="55" pad="PD12"/>
+      <pin position="56" pad="PD13"/>
+      <pin position="57" pad="VSSIO"/>
+      <pin position="58" pad="VDDF"/>
+      <pin position="59" pad="USERLDO"/>
+      <pin position="60" pad="PD07"/>
+      <pin position="61" pad="PD04"/>
+      <pin position="62" pad="PD05"/>
+      <pin position="63" pad="PD08"/>
+      <pin position="64" pad="PD09"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/atdf/PIC32CM5112GC00100.atdf b/pic32c/pic32cm_gc_sg/pic32cm_gc00/atdf/PIC32CM5112GC00100.atdf
new file mode 100644
index 00000000..c14413e2
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/atdf/PIC32CM5112GC00100.atdf
@@ -0,0 +1,11317 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="4.5" public="true" xsi:noNamespaceSchemaLocation="https://schemas.microchip.com/com/microchip/atdf/4.5/atdf.xsd">
+  <!--
+ Copyright (c) 2024 Microchip Technology Inc.
+
+ SPDX-License-Identifier: Apache-2.0
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+-->
+  <!--
+CHPMKR VERSION: 2.17.0
+-->
+  <file timestamp="2024-11-05T16:47:43Z"/>
+  <variants xmlns:mhc="http://www.atmel.com/schemas/avr-tools-device-file/mhc">
+    <variant ordercode="PIC32CM5112GC00100-I/NA" mhc:ordercode="PIC32CM5112GC00100-I/NA" package="TQFP100" pinout="P100" speedmax="72000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00100-V/NA" mhc:ordercode="PIC32CM5112GC00100-V/NA" package="TQFP100" pinout="P100" speedmax="72000000" tempmin="-40" tempmax="105" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="PIC32CM5112GC00100-E/NA" mhc:ordercode="PIC32CM5112GC00100-E/NA" package="TQFP100" pinout="P100" speedmax="72000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="PIC32CM5112GC00100" architecture="CORTEX-M23" family="PIC32CM" series="PIC32CMGC00">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="BROMC_ROM" start="0x4000000" size="0x10000" type="rom" rw="R" exec="true"/>
+          <memory-segment name="FCR_BFM" start="0x8000000" size="0x4000" type="flash" rw="RW" exec="true"/>
+          <memory-segment name="FCR_CFM_BOOTCFG1A" start="0xA000000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_USEROTP" start="0xA001000" size="0x1000" type="user_signatures" rw="RW"/>
+          <memory-segment name="FCR_CFM_BOOTCFG1" start="0xA002000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_ROMCFG" start="0xA003000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_VSS0" start="0xA004000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_VSS1" start="0xA005000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_TEST" start="0xA006000" size="0x1000" type="flash" rw="RW"/>
+          <memory-segment name="FCR_CFM_CALOTP" start="0xA007000" size="0x1000" type="other" rw="R"/>
+          <memory-segment name="FCR_PFM" start="0xC000000" size="0x80000" type="flash" rw="RW" exec="true"/>
+          <memory-segment name="MCRAMC_RET" start="0x20000000" size="0x00020000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="APB0_BRIDGE" start="0x44000000" size="0x00034000" type="io" rw="RW"/>
+          <memory-segment name="APB1_BRIDGE" start="0x44800000" size="0x0003a000" type="io" rw="RW"/>
+          <memory-segment name="APB2_BRIDGE" start="0x45000000" size="0x00010000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xe0000000" size="0x00100000" type="io" rw="RW"/>
+        </address-space>
+      </address-spaces>
+      <parameters>
+        <param name="NUM_IRQ" value="141" caption="Number of interrupt request lines"/>
+        <param name="__BKPT_NUM" value="4" caption="Number of breakpoints comparators"/>
+        <param name="__CM23_REV" value="0x0000" caption="Cortex-M23 Core Revision"/>
+        <param name="__ETM_PRESENT" value="0" caption="No Embedded Trace Macro implemented"/>
+        <param name="__FPU_PRESENT" value="0" caption="No FPU"/>
+        <param name="__MPU_NS_REGIONS" value="8" caption="Number of Non-Secure Memory Protection Regions"/>
+        <param name="__MPU_PRESENT" value="1" caption="MPU implemented"/>
+        <param name="__MPU_REGIONS" value="8" caption="same as __MPU_S_REGIONS"/>
+        <param name="__MPU_S_REGIONS" value="8" caption="Number of Secure Memory Protection Regions"/>
+        <param name="__MTB_PRESENT" value="0" caption="No Macro Trace Buffer implemented"/>
+        <param name="__NVIC_PRIO_BITS" value="2" caption="Number of NVIC Priority Bits"/>
+        <param name="__SAUREGION_PRESENT" value="0" caption="Number of Security Attribute Unit Regions (No SAU)"/>
+        <param name="__SEC_ENABLED" value="0" caption="ARMv8-M security extensions (Trust Zone) enabled"/>
+        <param name="__SYST_NUM" value="2" caption="Number of SYSTICK, include secure and non-secure SYSTICK timers"/>
+        <param name="__VTOR_PRESENT" value="1" caption="Include Vector Table Offset Register"/>
+        <param name="__Vendor_SysTickConfig" value="0" caption="Standard SYSTICK used"/>
+        <param name="__WPT_NUM" value="2" caption="Number of watch point comparators"/>
+        <param name="POWER_DOMAIN" value="PD_CORE"/>
+        <param name="__ARCH_ARM" value="1"/>
+        <param name="__ARCH_ARM_CORTEX_M" value="1"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="03784" name2="cmp_ac_u2501_v2" version="2a0">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x4482A000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B" pad="PA07"/>
+              <signal group="AIN" index="1" function="B" pad="PA08"/>
+              <signal group="AIN" index="2" function="B" pad="PB00"/>
+              <signal group="AIN" index="3" function="B" pad="PB03"/>
+              <signal group="CMP" index="0" function="B" pad="PA01" ioset="1"/>
+              <signal group="CMP" index="0" function="B" pad="PA13" ioset="2"/>
+              <signal group="CMP" index="1" function="B" pad="PA02" ioset="1"/>
+              <signal group="CMP" index="1" function="B" pad="PB07" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="ATEST_IMPLEMENTED" value="1" caption="Defines if the ATEST register is implemented"/>
+              <param name="ATEST_SIZE" value="2" caption="Defines the number of effective bits in ATEST register"/>
+              <param name="DACVALUE_BIT" value="7" caption="Defines the number of bits in DACCTRLn.VALUE"/>
+              <param name="IO_INPUTS" value="4" caption="Defines the number of AC pair inputs connected to IO pins"/>
+              <param name="PAIRS" value="1" caption="Defines the number of AC pairs"/>
+              <param name="NUM_CMP" value="2" caption="Number of comparators"/>
+              <param name="LOAD_CALIB" value="0" caption="Defines if calibration is required"/>
+              <param name="GCLK_ID" value="34"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="21" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="40" caption="Instance index for AC"/>
+              <param name="MCLK_ID_APB" value="50" caption="Index for AC APB clock"/>
+              <param name="PAC_ID" value="40" caption="Index for AC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="03620" name2="adc_msh_ctrl_apb_v1" version="1b0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x44818000"/>
+            <signals>
+              <signal group="ADC0_AIN" index="0" function="B" pad="PA03"/>
+              <signal group="ADC0_AIN" index="1" function="B" pad="PA04"/>
+              <signal group="ADC0_AIN" index="2" function="B" pad="PA05"/>
+              <signal group="ADC0_AIN" index="3" function="B" pad="PA06"/>
+              <signal group="ADC0_AIN" index="4" function="B" pad="PA07"/>
+              <signal group="ADC0_AIN" index="5" function="B" pad="PA08"/>
+              <signal group="ADC0_AIN" index="6" function="B" pad="PA09"/>
+              <signal group="ADC0_AIN" index="7" function="B" pad="PB00"/>
+              <signal group="ADC0_AIN" index="8" function="B" pad="PB03"/>
+              <signal group="ADC0_AIN" index="9" function="B" pad="PB04"/>
+              <signal group="ADC0_AIN" index="10" function="B" pad="PB05"/>
+              <signal group="ADC0_AIN" index="11" function="B" pad="PB06"/>
+              <signal group="ADC0_ANN" index="0" function="B" pad="PA04"/>
+              <signal group="ADC0_ANN" index="2" function="B" pad="PA06"/>
+              <signal group="ADC0_ANN" index="4" function="B" pad="PA08"/>
+              <signal group="RES_TEST" index="0" function="ADC_TEST_PAD" pad="PD08"/>
+              <signal group="RES_TEST" index="1" function="ADC_TEST_PAD" pad="PD09"/>
+              <signal group="RES_TEST" index="2" function="ADC_TEST_PAD" pad="PD07"/>
+              <signal group="RES_TEST" index="3" function="ADC_TEST_PAD" pad="PA00"/>
+              <signal group="RES_TEST" index="4" function="ADC_TEST_PAD" pad="PA01"/>
+              <signal group="RES_TEST" index="5" function="ADC_TEST_PAD" pad="PA02"/>
+              <signal group="RES_TEST" index="6" function="ADC_TEST_PAD" pad="PA03"/>
+              <signal group="RES_TEST" index="7" function="ADC_TEST_PAD" pad="PA04"/>
+              <signal group="RES_TEST" index="8" function="ADC_TEST_PAD" pad="PB03"/>
+              <signal group="RES_TEST" index="9" function="ADC_TEST_PAD" pad="PB04"/>
+              <signal group="RES_TEST" index="10" function="ADC_TEST_PAD" pad="PB05"/>
+              <signal group="RES_TEST" index="11" function="ADC_TEST_PAD" pad="PB06"/>
+              <signal group="VREFH" function="VOLT_REF" pad="PA09"/>
+            </signals>
+            <parameters>
+              <param name="APB_FIFO_DEPTH" value="16" caption="--"/>
+              <param name="CHNSAR_NMBR1" value="16" caption="--"/>
+              <param name="CHNSAR_NMBR2" value="0" caption="--"/>
+              <param name="CHNSAR_NMBR3" value="0" caption="--"/>
+              <param name="CHNSAR_NMBR4" value="0" caption="--"/>
+              <param name="DCMP_NMBR" value="1" caption="--"/>
+              <param name="EARLY_INTR_PRESENT" value="1" caption="--"/>
+              <param name="FLTR_NMBR" value="1" caption="--"/>
+              <param name="OCP_ADDR_WIDTH" value="0" caption="--"/>
+              <param name="OCP_FIFO_DEPTH" value="0" caption="--"/>
+              <param name="OCP_PORT_PRESENT" value="0" caption="--"/>
+              <param name="SARCORE_NMBR" value="1" caption="--"/>
+              <param name="TRGS_NMBR" value="16" caption="--"/>
+              <param name="VREF_STARTUP_TIME" value="50" caption="--"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="DMAC_ID_PFFRDY" value="37"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="12" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="39" caption="Instance index for ADC"/>
+              <param name="MCLK_ID_APB" value="49" caption="Index for ADC APB clock"/>
+              <param name="PAC_ID" value="39" caption="Index for ADC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="AT" id="04932" name2="sec_anti_tamper_v1" version="1a0">
+          <instance name="AT">
+            <register-group name="AT" name-in-module="AT" address-space="base" offset="0x4500C000"/>
+            <parameters>
+              <param name="AT_TMPR_OSC_NUM_INV" value="881" caption="Number of inverters in tamper oscillator"/>
+              <param name="AT_CTRLAPRIV_IMPLEMENTED" value="1" caption="Implement the CTRLA.PRIV bit and privilege access filtering to registers.0 = CTRLA.PRIV not implemented1 = CTRLA.PRIV implemented"/>
+              <param name="AT_WPCTRL_IMPLEMENTED" value="0" caption="Implement the WPCTRL register for write protection. 1 = Use WPCTRL register is preset . Used to control write protection enable/disable. 0 = No WPCTRL sfr, only used in legacy device with a PACUse at_wrprot to control write protection enable/disable"/>
+              <param name="AT_WPCTRL_KEY" value="0x412054" caption="WPCTRL 24-bit key value. See register description for usage.Set to a unique value for each macro. ASCII of &quot;A T&quot;"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="6" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="45" caption="Instance index for AT"/>
+              <param name="MCLK_ID_APB" value="56" caption="Index for AT APB clock"/>
+              <param name="PAC_ID" value="45" caption="Index for AT registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="BROMC" id="04402" name2="prm_boot_ahb_v2" version="2a0">
+          <instance name="BROMC">
+            <register-group name="BROMC" name-in-module="BROMC" address-space="base" offset="0x44804000"/>
+            <parameters>
+              <param name="BROMC_PADDR_MSB" value="12" caption="--"/>
+              <param name="BROMC_PDATA_MSB" value="31" caption="--"/>
+              <param name="BROMC_PSTRB_MSB" value="3" caption="--"/>
+              <param name="BROMC_PPROT_MSB" value="5" caption="--"/>
+              <param name="BROMC_ROM_ADDR_MSB" value="13" caption="--"/>
+              <param name="BROMC_ROM_DATA_MSB" value="31" caption="--"/>
+              <param name="BROMC_ROM_DATA_SIZE" value="16384" caption="--"/>
+              <param name="BROMC_ROM_PRMWS_DEFAULT" value="0" caption="--"/>
+              <param name="BROMC_ROM_KEN" value="0" caption="--"/>
+              <param name="BROMC_ROM_CRC_EN" value="1" caption="--"/>
+              <param name="BROMC_ROM_SPLIT" value="0x3400" caption="(8K for PK code)  (Note: This parameter may change once boot and PK code sizes are known)"/>
+              <param name="BROMC_BOOTCRC_MODE" value="2" caption="--"/>
+              <param name="BROMC_FUSES_DATA_MSB" value="127" caption="See Flash Control Chapter for Values"/>
+              <param name="BROMC_FUSES_RDY_MSB" value="14" caption="See Flash Control Chapter for Values"/>
+              <param name="BROMC_FUSES_UCFG_ROWID" value="14" caption="See Chapter 5 CCFG Fuse map for Values"/>
+              <param name="BROMC_FUSES_UCFG_START" value="0" caption="See Chapter 5 CCFG Fuse map for Values"/>
+              <param name="BROMC_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="BROMC_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="BROMC_WPCTRL_KEY" value="0x42524F" caption="--"/>
+              <param name="BROMC_NUM_COOLDN_CYCLES" value="2" caption="--"/>
+              <param name="BROMC_NUM_WARMUP_CYCLES" value="2" caption="--"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="2" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="23" caption="Instance index for BROMC"/>
+              <param name="MCLK_ID_AHB" value="32" caption="Index for BROMC AHB clock"/>
+              <param name="MCLK_ID_APB" value="33" caption="Index for BROMC APB clock"/>
+              <param name="PAC_ID" value="23" caption="Index for BROMC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="CAN" id="05010" name2="can_fd_apb_v1" version="1a0">
+          <instance name="CAN0">
+            <register-group name="CAN0" name-in-module="CAN" address-space="base" offset="0x4402E000"/>
+            <signals>
+              <signal group="RX" function="H" pad="PA10" ioset="3"/>
+              <signal group="RX" function="H" pad="PC01" ioset="1"/>
+              <signal group="RX" function="H" pad="PD06" ioset="2"/>
+              <signal group="TX" function="H" pad="PA11" ioset="3"/>
+              <signal group="TX" function="H" pad="PC02" ioset="1"/>
+              <signal group="TX" function="H" pad="PD08" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="ECC_ERR_IMPLEMENTED" value="0" caption="ECC error implemented?"/>
+              <param name="INTERNAL_TB_SOF" value="3" caption="0: No SOF and no internal Time base, 1: SOF and no internal Time"/>
+              <param name="MSG_RAM_ADDR" value="0x20" caption="8-bits MSB"/>
+              <param name="NUMBER_TS" value="1" caption="0: 4 Timestamp reg, 1: 8 timestamp reg, 2: 16 timestamp reg"/>
+              <param name="PRIV_IMPLEMENTED" value="1" caption="Privilege access is implemented? 0: CTRLA.PRIV bit not implemented, 1: CTRLA.PRIV bit implemented"/>
+              <param name="RXD_SYNC_METHOD" value="0" caption="RXD Synchronization Method"/>
+              <param name="SYNT_TIMESTAMP" value="0x00000" caption="CAN_SYNT_TIMESTAMP[19:16]: CREL.YEAR reset value (BCD-coded),CAN_SYNT_TIMESTAMP[15:8]: CREL.MON reset value (BCD-coded), CAN_SYNT_TIMESTAMP[7:0]: CREL.DAY reset value (BCD-coded)"/>
+              <param name="WPCTRL_IMPLEMENTED" value="0" caption="Write protection control register implemented?"/>
+              <param name="WPCTRL_KEY" value="0x43414E" caption="Write protection 24 bit key"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="23" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="17" caption="Instance index for CAN0"/>
+              <param name="MCLK_ID_AHB" value="23" caption="Index for CAN0 AHB clock"/>
+              <param name="PAC_ID" value="17" caption="Index for CAN0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="CAN1">
+            <register-group name="CAN1" name-in-module="CAN" address-space="base" offset="0x44030000"/>
+            <signals>
+              <signal group="RX" function="H" pad="PA00" ioset="2"/>
+              <signal group="RX" function="H" pad="PC05" ioset="1"/>
+              <signal group="RX" function="H" pad="PD12" ioset="3"/>
+              <signal group="TX" function="H" pad="PA01" ioset="2"/>
+              <signal group="TX" function="H" pad="PC06" ioset="1"/>
+              <signal group="TX" function="H" pad="PD13" ioset="3"/>
+            </signals>
+            <parameters>
+              <param name="ECC_ERR_IMPLEMENTED" value="0" caption="ECC error implemented?"/>
+              <param name="INTERNAL_TB_SOF" value="3" caption="0: No SOF and no internal Time base, 1: SOF and no internal Time"/>
+              <param name="MSG_RAM_ADDR" value="0x20" caption="8-bits MSB"/>
+              <param name="NUMBER_TS" value="1" caption="0: 4 Timestamp reg, 1: 8 timestamp reg, 2: 16 timestamp reg"/>
+              <param name="PRIV_IMPLEMENTED" value="1" caption="Privilege access is implemented? 0: CTRLA.PRIV bit not implemented, 1: CTRLA.PRIV bit implemented"/>
+              <param name="RXD_SYNC_METHOD" value="0" caption="RXD Synchronization Method"/>
+              <param name="SYNT_TIMESTAMP" value="0x00000" caption="CAN_SYNT_TIMESTAMP[19:16]: CREL.YEAR reset value (BCD-coded),CAN_SYNT_TIMESTAMP[15:8]: CREL.MON reset value (BCD-coded), CAN_SYNT_TIMESTAMP[7:0]: CREL.DAY reset value (BCD-coded)"/>
+              <param name="WPCTRL_IMPLEMENTED" value="0" caption="Write protection control register implemented?"/>
+              <param name="WPCTRL_KEY" value="0x43414E" caption="Write protection 24 bit key"/>
+              <param name="GCLK_ID" value="7"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="24" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="18" caption="Instance index for CAN1"/>
+              <param name="MCLK_ID_AHB" value="24" caption="Index for CAN1 AHB clock"/>
+              <param name="PAC_ID" value="18" caption="Index for CAN1 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="CCL" id="03628" name2="cla_ccl_u2225_v2" version="2b0">
+          <instance name="CCL0">
+            <register-group name="CCL0" name-in-module="CCL" address-space="base" offset="0x4482E000"/>
+            <signals>
+              <signal group="IN" index="0" function="I" pad="PC12" ioset="2"/>
+              <signal group="IN" index="0" function="I" pad="PC01" ioset="1"/>
+              <signal group="IN" index="1" function="I" pad="PC02" ioset="1"/>
+              <signal group="IN" index="1" function="I" pad="PC14" ioset="2"/>
+              <signal group="IN" index="2" function="I" pad="PC15" ioset="2"/>
+              <signal group="IN" index="2" function="I" pad="PC09" ioset="1"/>
+              <signal group="IN" index="3" function="I" pad="PD00" ioset="1"/>
+              <signal group="IN" index="3" function="I" pad="PD18" ioset="2"/>
+              <signal group="IN" index="4" function="I" pad="PD01" ioset="1"/>
+              <signal group="IN" index="4" function="I" pad="PD17" ioset="2"/>
+              <signal group="IN" index="5" function="I" pad="PD10" ioset="1"/>
+              <signal group="IN" index="5" function="I" pad="PD19" ioset="2"/>
+              <signal group="IN" index="6" function="I" pad="PA00" ioset="1"/>
+              <signal group="IN" index="6" function="I" pad="PA14" ioset="2"/>
+              <signal group="IN" index="7" function="I" pad="PA01" ioset="1"/>
+              <signal group="IN" index="7" function="I" pad="PA15" ioset="2"/>
+              <signal group="IN" index="8" function="I" pad="PA10" ioset="1"/>
+              <signal group="IN" index="8" function="I" pad="PA18" ioset="2"/>
+              <signal group="IN" index="9" function="I" pad="PB12" ioset="2"/>
+              <signal group="IN" index="9" function="I" pad="PB05" ioset="1"/>
+              <signal group="IN" index="10" function="I" pad="PB14" ioset="2"/>
+              <signal group="IN" index="10" function="I" pad="PB06" ioset="1"/>
+              <signal group="IN" index="11" function="I" pad="PB15" ioset="2"/>
+              <signal group="IN" index="11" function="I" pad="PB10" ioset="1"/>
+              <signal group="OUT" index="0" function="I" pad="PC13" ioset="2"/>
+              <signal group="OUT" index="0" function="I" pad="PC03" ioset="1"/>
+              <signal group="OUT" index="1" function="I" pad="PD14" ioset="2"/>
+              <signal group="OUT" index="1" function="I" pad="PD08" ioset="1"/>
+              <signal group="OUT" index="2" function="I" pad="PA02" ioset="1"/>
+              <signal group="OUT" index="2" function="I" pad="PA19" ioset="2"/>
+              <signal group="OUT" index="3" function="I" pad="PB16" ioset="2"/>
+              <signal group="OUT" index="3" function="I" pad="PC00" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="LUT_NUM" value="4" caption="Number of LUT in a CCL"/>
+              <param name="GCLK_ID" value="36"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="23" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="42" caption="Instance index for CCL0"/>
+              <param name="MCLK_ID_APB" value="52" caption="Index for CCL0 APB clock"/>
+              <param name="PAC_ID" value="42" caption="Index for CCL0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="CCL1">
+            <register-group name="CCL1" name-in-module="CCL" address-space="base" offset="0x44830000"/>
+            <signals>
+              <signal group="IN" index="0" function="I" pad="PC11" ioset="2"/>
+              <signal group="IN" index="0" function="I" pad="PC04" ioset="1"/>
+              <signal group="IN" index="1" function="I" pad="PC17" ioset="2"/>
+              <signal group="IN" index="1" function="I" pad="PC05" ioset="1"/>
+              <signal group="IN" index="2" function="I" pad="PC16" ioset="2"/>
+              <signal group="IN" index="2" function="I" pad="PC10" ioset="1"/>
+              <signal group="IN" index="3" function="I" pad="PD06" ioset="1"/>
+              <signal group="IN" index="3" function="I" pad="PD20" ioset="2"/>
+              <signal group="IN" index="4" function="I" pad="PD16" ioset="2"/>
+              <signal group="IN" index="4" function="I" pad="PD07" ioset="1"/>
+              <signal group="IN" index="5" function="I" pad="PD11" ioset="1"/>
+              <signal group="IN" index="5" function="I" pad="PD12" ioset="2"/>
+              <signal group="IN" index="6" function="I" pad="PA16" ioset="2"/>
+              <signal group="IN" index="6" function="I" pad="PA09" ioset="1"/>
+              <signal group="IN" index="7" function="I" pad="PA17" ioset="2"/>
+              <signal group="IN" index="7" function="I" pad="PA06" ioset="1"/>
+              <signal group="IN" index="8" function="I" pad="PA11" ioset="1"/>
+              <signal group="IN" index="8" function="I" pad="PA12" ioset="2"/>
+              <signal group="IN" index="9" function="I" pad="PB11" ioset="2"/>
+              <signal group="IN" index="9" function="I" pad="PB04" ioset="1"/>
+              <signal group="IN" index="10" function="I" pad="PB13" ioset="2"/>
+              <signal group="IN" index="10" function="I" pad="PB03" ioset="1"/>
+              <signal group="IN" index="11" function="I" pad="PB07" ioset="2"/>
+              <signal group="IN" index="11" function="I" pad="PB08" ioset="1"/>
+              <signal group="OUT" index="0" function="I" pad="PC19" ioset="2"/>
+              <signal group="OUT" index="0" function="I" pad="PC06" ioset="1"/>
+              <signal group="OUT" index="1" function="I" pad="PD15" ioset="2"/>
+              <signal group="OUT" index="1" function="I" pad="PD09" ioset="1"/>
+              <signal group="OUT" index="2" function="I" pad="PA05" ioset="1"/>
+              <signal group="OUT" index="2" function="I" pad="PA20" ioset="2"/>
+              <signal group="OUT" index="3" function="I" pad="PB00" ioset="1"/>
+              <signal group="OUT" index="3" function="I" pad="PB17" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="LUT_NUM" value="4" caption="Number of LUT in a CCL"/>
+              <param name="GCLK_ID" value="37"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="24" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="43" caption="Instance index for CCL1"/>
+              <param name="MCLK_ID_APB" value="53" caption="Index for CCL1 APB clock"/>
+              <param name="PAC_ID" value="43" caption="Index for CCL1 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="CoreDebug" id="SYSTEM_IP" version="1.0.0">
+          <instance name="CoreDebug">
+            <register-group name="CoreDebug" name-in-module="CoreDebug" address-space="base" offset="0xE000EDF0"/>
+          </instance>
+        </module>
+        <module name="DIB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="DIB">
+            <register-group name="DIB" name-in-module="DIB" address-space="base" offset="0xE000EFB0"/>
+          </instance>
+        </module>
+        <module name="DMAC" id="dma_u2223_v2" name2="dma_u2223_v2" version="2i0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x44802000"/>
+            <parameters>
+              <param name="CH_NUM" value="8" caption="--"/>
+              <param name="EVIN_NUM" value="4" caption="--"/>
+              <param name="EVOUT_NUM" value="4" caption="--"/>
+              <param name="LVL_NUM" value="4" caption="--"/>
+              <param name="QOSCTRL_D_RESETVALUE" value="2" caption="--"/>
+              <param name="QOSCTRL_F_RESETVALUE" value="2" caption="--"/>
+              <param name="QOSCTRL_WRB_RESETVALUE" value="2" caption="--"/>
+              <param name="SPLIT_IRQ_NUM" value="4" caption="--"/>
+              <param name="TRIG_NUM" value="43" caption="--"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="1" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="21" caption="Instance index for DMAC"/>
+              <param name="MCLK_ID_AHB" value="28" caption="Index for DMAC AHB clock"/>
+              <param name="MCLK_ID_APB" value="29" caption="Index for DMAC APB clock"/>
+              <param name="PAC_ID" value="21" caption="Index for DMAC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="04465" name2="icd_dsu_v1" version="1a0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x44000000"/>
+            <signals>
+              <signal group="MSA" function="DSU_MSA" pad="PC05"/>
+              <signal group="SWCCSTAT" function="DSU_SWCCSTAT" pad="PC06"/>
+            </signals>
+            <parameters>
+              <param name="DSU_BASE_ADDR_INTERNAL" value="0x44000000" caption="--"/>
+              <param name="DSU_CPU_NUM" value="0" caption="--"/>
+              <param name="DSU_TZ_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DSU_CORESIGHT_REVISION" value="0x0" caption="--"/>
+              <param name="DSU_CORESIGHT_ENTRY" value="0xE00FF001 0x0 0x0 0x0" caption="--"/>
+              <param name="DSU_ID_MASKID" value="0x00" caption="Microchip Device Mask ID which provides the value for bits [15:8] of the ID - Part Number."/>
+              <param name="DSU_ID_VER" value="0x0" caption="ID Version Code provides the Mask Revision value for the device. Use metal changeable cells to configure this value."/>
+              <param name="DSU_SD_KEY" value="0xFFABAFD0" caption="--"/>
+              <param name="DSU_DCFG_MASK" value="0xFF0FFF0F 0x10FC7F80 0xC0800203 0x0 0x0 0x0 0x0 0x0" caption="--"/>
+              <param name="DSU_DAL1_VAL" value="0x55" caption="--"/>
+              <param name="DSU_DAL2_VAL" value="0xAA" caption="--"/>
+              <param name="DSU_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DSU_CTRLB_IMPLEMENTED_MASK" value="0x00000000" caption="--"/>
+              <param name="DSU_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="DSU_WPCTRL_KEY" value="0x445355" caption="--"/>
+              <param name="DSU_PRVKEY_IMPLEMENTED" value="0" caption="key sourced by PUF, not DSU"/>
+              <param name="DSU_BRCTRL_KEY" value="0x445355" caption="--"/>
+              <param name="DSU_TDID_DIE" value="0x00" caption="--"/>
+              <param name="DSU_TDID_MASK" value="0x00" caption="--"/>
+              <param name="DSU_SWCCS_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DSU_TESTMODE_IMPLEMENTED_MASK" value="0x000007FF 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DSU_FUSES_DATA_MSB" value="127" caption="128-bit bus"/>
+              <param name="DSU_FUSES_RDY_MSB" value="14" caption="15 bit fuse ready bus"/>
+              <param name="DSU_FUSES_ID_DEVID_START" value="24" caption="DEVID field is DSUCFG0[31:24]"/>
+              <param name="DSU_FUSES_ID_DEVID_SIZE" value="8" caption="--"/>
+              <param name="DSU_FUSES_ID_DEVID_ROWID" value="8" caption="DEVID on RowID Index = 8"/>
+              <param name="DSU_FUSES_DCFG_START" value="0 32 64 96 0 32 64 96" caption="--"/>
+              <param name="DSU_FUSES_DCFG_SIZE" value="32 32 32 32 32 32 32 32" caption="--"/>
+              <param name="DSU_FUSES_DCFG_ROWID" value="8 8 8 8 9 9 9 9" caption="DSUCFG7-0 = FCCFG39-32"/>
+              <param name="DMAC_ID_DCC0" value="1"/>
+              <param name="DMAC_ID_DCC1" value="2"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="0" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="0" caption="Instance index for DSU"/>
+              <param name="MCLK_ID_AHB" value="0" caption="Index for DSU AHB clock"/>
+              <param name="PAC_ID" value="0" caption="Index for DSU registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DWT" id="SYSTEM_IP" version="1.0.0">
+          <instance name="DWT">
+            <register-group name="DWT" name-in-module="DWT" address-space="base" offset="0xE0001000"/>
+            <parameters>
+              <param name="__WPT_NUM" value="2" caption="Number of DWT watchpoint comparators"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="03706" name2="int_eic_u2804_v1" version="1b0">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x44020000"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB15"/>
+              <signal group="EXTINT" index="0" function="A" pad="PC00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PC16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PD18"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB16"/>
+              <signal group="EXTINT" index="1" function="A" pad="PC01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PC17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PD01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PD19"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB12"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB17"/>
+              <signal group="EXTINT" index="2" function="A" pad="PC02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PC18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PD04"/>
+              <signal group="EXTINT" index="2" function="A" pad="PD20"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PC03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PC19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PD05"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="4" function="A" pad="PB04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PC04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PD07"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PB05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PC05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PD08"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PC06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PD09"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA08"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB07"/>
+              <signal group="EXTINT" index="8" function="A" pad="PD10"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PC09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PD11"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PC10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PD12"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PB10"/>
+              <signal group="EXTINT" index="11" function="A" pad="PC11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PD13"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PB11"/>
+              <signal group="EXTINT" index="12" function="A" pad="PC12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PD14"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PC13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PD15"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="14" function="A" pad="PB13"/>
+              <signal group="EXTINT" index="14" function="A" pad="PC14"/>
+              <signal group="EXTINT" index="14" function="A" pad="PD16"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PB14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PC15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PD17"/>
+              <signal group="NMI" function="A" pad="PD00"/>
+            </signals>
+            <parameters>
+              <param name="EXTINT_NUM" value="16" caption="--"/>
+              <param name="NUMBER_OF_CONFIG_REGS" value="2" caption="=(EIC_EXTINT_NUM +7) / 8"/>
+              <param name="NUMBER_OF_INTERRUPTS" value="16" caption="=(EIC_EXTINT_NUM)"/>
+              <param name="SECURE_IMPLEMENTED" value="1" caption="--"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="16" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="13" caption="Instance index for EIC"/>
+              <param name="MCLK_ID_APB" value="13" caption="Index for EIC APB clock"/>
+              <param name="PAC_ID" value="13" caption="Index for EIC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="03601" name2="ptg_evsys_u2504_v2" version="2b0">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x44806000"/>
+            <parameters>
+              <param name="ASYNCHRONOUS_CHANNELS" value="0xFFFFF000" caption="--"/>
+              <param name="CHANNELS" value="12" caption="--"/>
+              <param name="CHANNELS_BITS" value="4" caption="=LEN( BIN(EVSYS_CHANNELS-1)) - 2)derived parameter"/>
+              <param name="GENERATORS" value="90" caption="Should be 90"/>
+              <param name="GENERATORS_BITS" value="7" caption="=LEN( BIN(EVSYS_GENERATORS-1)) - 2)derived parameter"/>
+              <param name="SECURE_IMPLEMENTED" value="0" caption="--"/>
+              <param name="SPLIT_IRQ_NUM" value="12" caption="--"/>
+              <param name="SYNCH_NUM" value="12" caption="--"/>
+              <param name="SYNCH_NUM_BITS" value="4" caption="=LEN( BIN(EVSYS_SYNCH_NUM-1)) - 2)derived parameter"/>
+              <param name="USERS" value="62" caption="Should be 62"/>
+              <param name="USERS_BITS" value="6" caption="=LEN( BIN(EVSYS_USERS-1)) - 2)derived parameter"/>
+              <param name="USERS_GROUPS" value="2" caption="=(EVSYS_USERS+31) / 32derived parameter"/>
+              <param name="GCLK_ID_CH0" value="8"/>
+              <param name="GCLK_ID_CH1" value="9"/>
+              <param name="GCLK_ID_CH2" value="10"/>
+              <param name="GCLK_ID_CH3" value="11"/>
+              <param name="GCLK_ID_CH4" value="12"/>
+              <param name="GCLK_ID_CH5" value="13"/>
+              <param name="GCLK_ID_CH6" value="14"/>
+              <param name="GCLK_ID_CH7" value="15"/>
+              <param name="GCLK_ID_CH8" value="16"/>
+              <param name="GCLK_ID_CH9" value="17"/>
+              <param name="GCLK_ID_CH10" value="18"/>
+              <param name="GCLK_ID_CH11" value="19"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="3" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="25" caption="Instance index for EVSYS"/>
+              <param name="MCLK_ID_APB" value="35" caption="Index for EVSYS APB clock"/>
+              <param name="PAC_ID" value="25" caption="Index for EVSYS registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FCR" id="04972" name2="pfm_ctrlr_apb_v2" version="2a0">
+          <instance name="FCR">
+            <register-group name="FCR" name-in-module="FCR" address-space="base" offset="0x44002000"/>
+            <parameters>
+              <param name="FCR_AHB_PORTS_NB" value="1" caption="--"/>
+              <param name="FCR_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCR_INTFLAGSET_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCR_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="FCR_WPCTRL_KEY" value="0x464352" caption="--"/>
+              <param name="FCR_PDMO_MSB" value="7" caption="--"/>
+              <param name="FCR_PFM_ADDR_BASE" value="0x0C000000" caption="--"/>
+              <param name="FCR_BFM_ADDR_BASE" value="0x08000000" caption="--"/>
+              <param name="FCR_CFM_ADDR_BASE" value="0x0A000000" caption="--"/>
+              <param name="FCR_FCD_ADDR_BASE" value="0x0B000000" caption="--"/>
+              <param name="FCR_VSS_CFG0_BASE" value="0x0A004000" caption="--"/>
+              <param name="FCR_VSS_CFG1_BASE" value="0x0A005000" caption="--"/>
+              <param name="FCR_VSS_CFG2_BASE" value="0" caption="--"/>
+              <param name="FCR_VSS_CFG3_BASE" value="0" caption="--"/>
+              <param name="FCR_VSS_CFG4_BASE" value="0" caption="--"/>
+              <param name="FCR_VSS_CFG5_BASE" value="0" caption="--"/>
+              <param name="FCR_CRC_PRESENT" value="1" caption="--"/>
+              <param name="FCR_FLT_PRESENT" value="1" caption="--"/>
+              <param name="FCR_ECC_PRESENT" value="1" caption="--"/>
+              <param name="FCR_PCHE_PRESENT" value="1" caption="--"/>
+              <param name="FCR_PCHE_AHB_NUM" value="0" caption="--"/>
+              <param name="FCR_PCHE_NUM_LINES" value="4" caption="--"/>
+              <param name="FCR_PCHE_TAG_MASK" value="0xF9F8000F" caption="--"/>
+              <param name="FCR_FUSES_READY_CYCLES" value="2" caption="--"/>
+              <param name="FCR_FUSES_DATA_CYCLES" value="4" caption="--"/>
+              <param name="FUSES_RDY_MSB" value="14" caption="--"/>
+              <param name="FUSES_DATA_MSB" value="127" caption="--"/>
+              <param name="FCR_HDATA_SIZE" value="32" caption="--"/>
+              <param name="FCR_F1RR_ADDR" value="0x0A007000" caption="--"/>
+              <param name="FCR_F2RR_ADDR" value="0" caption="Not applicable for QSilver"/>
+              <param name="FCR_RR_NUM_READS" value="1" caption="--"/>
+              <param name="FCR_NUM_RR_SFR" value="1" caption="--"/>
+              <param name="FCR_FFF_ADDR" value="0x0A007040" caption="--"/>
+              <param name="FCR_NOT_FFF_VALUE" value="0xA5A5A5A5" caption="--"/>
+              <param name="FCR_OTPLOCK_ADDR" value="0x0A007060" caption="--"/>
+              <param name="FCR_CAL_ADDR" value="0x0A007080" caption="--"/>
+              <param name="FCR_CAL_NUM_READS" value="14" caption="--"/>
+              <param name="FCR_PBUCFG_ADDR" value="0x0A003400" caption="--"/>
+              <param name="FCR_PERIOD_MIN" value="75" caption="--"/>
+              <param name="FCR_PERIOD_NOM" value="116" caption="--"/>
+              <param name="FCR_TCALH_NS" value="10000" caption="--"/>
+              <param name="PFM_NUM_PANELS" value="1" caption="--"/>
+              <param name="PFM_PNL_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_SYS_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_ROW_ADDR_MSB" value="9" caption="--"/>
+              <param name="PFM_PAGE_ADDR_MSB" value="11" caption="--"/>
+              <param name="PFM_PNL_DATA_MSB" value="139" caption="--"/>
+              <param name="PFM_DATA_MSB" value="127" caption="--"/>
+              <param name="PFM_PNL_WDATA_MSB" value="34" caption="Parameter only in DOS Rev C, not in RTL"/>
+              <param name="PFM_NUM_RR" value="2" caption="--"/>
+              <param name="PFM_SRHT_PRESENT" value="0" caption="--"/>
+              <param name="BFM_PNL_ADDR_MSB" value="13" caption="--"/>
+              <param name="BFM_SYS_ADDR_MSB" value="13" caption="--"/>
+              <param name="CFM_PNL_ADDR_MSB" value="14" caption="--"/>
+              <param name="CFM_SYS_ADDR_MSB" value="14" caption="--"/>
+              <param name="NVR_NUM_PAGES" value="12" caption="--"/>
+              <param name="PFM_TDPDH_NS" value="5000" caption="--"/>
+              <param name="PFM_TDPDS_NS" value="100" caption="--"/>
+              <param name="PFM_TMS_NS" value="5000" caption="See Note 2"/>
+              <param name="PFM_TMH_NS" value="100" caption="See Note 2"/>
+              <param name="PFM_TRT_NS" value="500" caption="--"/>
+              <param name="PFM_TRHR_NS" value="1000" caption="--"/>
+              <param name="PFM_TONWAIT_NS" value="6000" caption="--"/>
+              <param name="PFM_TLKCFG_NS" value="1000" caption="--"/>
+              <param name="PFM_ACC_NS" value="25" caption="--"/>
+              <param name="PFM_ACC_HT_NS" value="30" caption="--"/>
+              <param name="PFM_ACC_RECALL_NS" value="70" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="1" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="1" caption="Instance index for FCR"/>
+              <param name="MCLK_ID_AHB" value="1" caption="Index for FCR AHB clock"/>
+              <param name="PAC_ID" value="1" caption="Index for FCR registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FCW" id="04971" name2="pfm_ctrlw_apb_v2" version="2a0">
+          <instance name="FCW">
+            <register-group name="FCW" name-in-module="FCW" address-space="base" offset="0x44004000"/>
+            <parameters>
+              <param name="FCW_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCW_INTFLAGSET_IMPLEMENTED" value="1" caption="--"/>
+              <param name="FCW_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="FCW_WPCTRL_KEY" value="0x464357" caption="--"/>
+              <param name="FCW_PFM_ADDR_BASE" value="0x0C000000" caption="--"/>
+              <param name="FCW_BFM_ADDR_BASE" value="0x08000000" caption="--"/>
+              <param name="FCW_CFM_ADDR_BASE" value="0x0A000000" caption="--"/>
+              <param name="FCW_VSS_CFG0_BASE" value="0x0A004000" caption="--"/>
+              <param name="FCW_VSS_CFG1_BASE" value="0x0A005000" caption="--"/>
+              <param name="FCW_VSS_CFG2_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_VSS_CFG3_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_VSS_CFG4_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_VSS_CFG5_BASE" value="0" caption="Not applicable for QS"/>
+              <param name="FCW_PWP_REGIONS" value="4" caption="--"/>
+              <param name="FCW_PWP_MSB" value="6" caption="--"/>
+              <param name="FCW_TAMPER_PRESENT" value="1" caption="--"/>
+              <param name="FCW_TAMPER_ADDR" value="0x0A003200" caption="--"/>
+              <param name="FCW_TAMPER_DATA" value="0x00000000" caption="--"/>
+              <param name="FCW_SD_USE_CPCNT" value="1" caption="--"/>
+              <param name="FCW_NUM_DATA_SFR" value="4" caption="(PFM_DATA_MSB+1)/32"/>
+              <param name="FCW_TPAR_MSB" value="3" caption="(PFM_PNL_DATA_MSB - PFM_DATA_MSB)/4"/>
+              <param name="FCW_PERIOD_MIN" value="75" caption="--"/>
+              <param name="FCW_PERIOD_NOM" value="116" caption="--"/>
+              <param name="PFM_SIZE" value="6" caption="--"/>
+              <param name="PFM_NUM_PANELS" value="1" caption="--"/>
+              <param name="PFM_PNL_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_SYS_ADDR_MSB" value="18" caption="--"/>
+              <param name="PFM_ROW_ADDR_MSB" value="9" caption="--"/>
+              <param name="PFM_PAGE_ADDR_MSB" value="11" caption="--"/>
+              <param name="PFM_PNL_DATA_MSB" value="139" caption="--"/>
+              <param name="PFM_DATA_MSB" value="127" caption="--"/>
+              <param name="PFM_NUM_RR" value="2" caption="--"/>
+              <param name="BFM_PNL_ADDR_MSB" value="13" caption="--"/>
+              <param name="BFM_SYS_ADDR_MSB" value="13" caption="--"/>
+              <param name="CFM_PNL_ADDR_MSB" value="14" caption="--"/>
+              <param name="CFM_SYS_ADDR_MSB" value="14" caption="--"/>
+              <param name="NVR_NUM_PAGES" value="12" caption="--"/>
+              <param name="PFM_TWS_NS" value="5" caption="value irrelevant, must be &gt;0"/>
+              <param name="PFM_TWH_NS" value="5" caption="value irrelevant, must be &gt;0"/>
+              <param name="PFM_TNVS_NS" value="4000" caption="See Note 2"/>
+              <param name="PFM_TPROG_NS" value="18000" caption="See Note 3"/>
+              <param name="PFM_TPREPROG_NS" value="3000" caption="See Note 3"/>
+              <param name="PFM_TADS_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TADH_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TPGS_NS" value="8000" caption="See Note 2"/>
+              <param name="PFM_TPREPGH_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TPREPGS_NS" value="1000" caption="See Note 2"/>
+              <param name="PFM_TPGH_NS" value="15" caption="See Note 2"/>
+              <param name="PFM_TRCV_PROG_NS" value="5000" caption="See Note 2"/>
+              <param name="PFM_TRCV_ERASE_NS" value="50000" caption="See Note 2"/>
+              <param name="PFM_TERASE_NS" value="18000000" caption="See Note 3"/>
+              <param name="PFM_TERASE_RETRY_NS" value="4500000" caption="See Note 3"/>
+              <param name="PFM_TSCE_NS" value="18000000" caption="See Note 3"/>
+              <param name="PFM_TRW_NS" value="100" caption="See Note 2"/>
+              <param name="PFM_TPUMPENS" value="1000" caption="See Note 2"/>
+              <param name="PFM_TPUMPENH" value="100" caption="See Note 2"/>
+              <param name="PFM_TPUMP_CYCLES" value="1029" caption="See Note 2"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="2" caption="H2PB Peripheral ID"/>
+              <param name="FLASH_SIZE" value="524288"/>
+              <param name="INSTANCE_ID" value="2" caption="Instance index for FCW"/>
+              <param name="MCLK_ID_AHB" value="2" caption="Index for FCW AHB clock"/>
+              <param name="PAC_ID" value="2" caption="Index for FCW registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FPB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="FPB">
+            <register-group name="FPB" name-in-module="FPB" address-space="base" offset="0xE0002000"/>
+            <parameters>
+              <param name="__BKPT_NUM" value="4" caption="Number of FPB breakpoint comparators"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FREQM" id="03707" name2="clk_freqm_u2257_v3" version="3a0">
+          <instance name="FREQM">
+            <register-group name="FREQM" name-in-module="FREQM" address-space="base" offset="0x4400C000"/>
+            <parameters>
+              <param name="MSRCLK_NB" value="2" caption="Number of measured clock sources"/>
+              <param name="GCLK_ID_MSR0" value="2"/>
+              <param name="GCLK_ID_MSR1" value="3"/>
+              <param name="GCLK_ID_REF" value="4"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="6" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="10" caption="Instance index for FREQM"/>
+              <param name="MCLK_ID_APB" value="10" caption="Index for FREQM APB clock"/>
+              <param name="PAC_ID" value="10" caption="Index for FREQM registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="fuses" name2="fuses" version="1a0">
+          <instance name="FUSES">
+            <register-group name="FUSES_ROMCFG" name-in-module="FUSES_ROMCFG" address-space="base" offset="0x0A003000"/>
+<register-group name="FUSES_BOOTCFG1" name-in-module="FUSES_BOOTCFG1" address-space="base" offset="0x0A002000"/>
+<register-group name="FUSES_BOOTCFG1A" name-in-module="FUSES_BOOTCFG1" address-space="base" offset="0x0A000000"/>
+            <register-group name="FUSES_CALOTP" name-in-module="FUSES_CALOTP" address-space="base" offset="0x0A007000"/>
+          </instance>
+        </module>
+        <module name="GCLK" id="03588" name2="clk_gclk_u2122_v1" version="1d0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x44008000"/>
+            <signals>
+              <signal group="IO" index="0" function="K" pad="PB06"/>
+              <signal group="IO" index="0" function="K" pad="PB15"/>
+              <signal group="IO" index="0" function="K" pad="PC09"/>
+              <signal group="IO" index="0" function="K" pad="PD05"/>
+              <signal group="IO" index="1" function="K" pad="PC00"/>
+              <signal group="IO" index="1" function="K" pad="PC10"/>
+              <signal group="IO" index="1" function="K" pad="PC05"/>
+              <signal group="IO" index="1" function="K" pad="PD04"/>
+              <signal group="IO" index="2" function="K" pad="PC01"/>
+              <signal group="IO" index="3" function="K" pad="PC02"/>
+              <signal group="IO" index="4" function="K" pad="PC03"/>
+              <signal group="IO" index="5" function="K" pad="PC04"/>
+              <signal group="IO" index="6" function="K" pad="PB16"/>
+              <signal group="IO" index="6" function="K" pad="PB10"/>
+              <signal group="IO" index="7" function="K" pad="PB09"/>
+              <signal group="TST_GCLK" function="DSU_TEST_GCLK" pad="PC08"/>
+            </signals>
+            <parameters>
+              <param name="GEN_NUM" value="12" caption="--"/>
+              <param name="IO_NUM" value="8" caption="derived, # of &quot;1&quot; in GCLK_GEN_IO_EXIST"/>
+              <param name="MUXED_NUM" value="39" caption="Number of GCLK channels"/>
+              <param name="SOURCE_NUM" value="11" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="4" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="8" caption="Instance index for GCLK"/>
+              <param name="MCLK_ID_APB" value="8" caption="Index for GCLK APB clock"/>
+              <param name="PAC_ID" value="8" caption="Index for GCLK registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="H2PB" id="04947" name2="bus_ahb2apb_v1" version="1a0">
+          <instance name="H2PB0">
+            <register-group name="H2PB0" name-in-module="H2PB" address-space="base" offset="0x44032000"/>
+            <parameters>
+              <param name="H2PB_MST_N" value="2" caption="--"/>
+              <param name="H2PB_MST_MAX" value="1" caption="derived parameter"/>
+              <param name="H2PB_SLV_N" value="32" caption="--"/>
+              <param name="H2PB_SLV_MAX" value="31" caption="derived parameter"/>
+              <param name="H2PB_PADDR_IDXB" value="5" caption="derived parameter"/>
+              <param name="H2PB_PADDR_LSB" value="13" caption="--"/>
+              <param name="H2PB_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="H2PB_PAGE_SIZE" value="8192" caption="derived parameter"/>
+              <param name="H2PB_OWN_SFR_SLOT" value="25" caption="--"/>
+              <param name="H2PB_PADDR_SIZE" value="18" caption="local parameter"/>
+              <param name="H2PB_PADDR_MSB" value="17" caption="derived local parameter"/>
+              <param name="H2PB_BASE_MSB" value="13" caption="derived parameter"/>
+              <param name="H2PB_USE_HSEL" value="1" caption="--"/>
+              <param name="H2PB_USE_DPATH_PIPER" value="0" caption="1=&quot;all pipelined&quot;0=&quot;address pipelined&quot;"/>
+              <param name="H2PB_USE_EARLY_PREAD" value="0" caption="--"/>
+              <param name="H2PB_CLK_DIV_EN" value="0" caption="1=&quot;n:1 clock&quot;0=&quot;1:1 clock&quot;"/>
+              <param name="H2PB_USE_PSTRB_FOR_READS" value="1" caption="--"/>
+              <param name="H2PB_WPCTRL_KEY" value="0x504230" caption="--"/>
+              <param name="H2PB_NONSEC_INIT_VAL" value="0x00000001" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="25" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="19" caption="Instance index for H2PB0"/>
+              <param name="MCLK_ID_AHB" value="25" caption="Index for H2PB0 AHB clock"/>
+              <param name="MCLK_ID_APB" value="26" caption="Index for H2PB0 APB clock"/>
+              <param name="PAC_ID" value="19" caption="Index for H2PB0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="H2PB1">
+            <register-group name="H2PB1" name-in-module="H2PB" address-space="base" offset="0x44838000"/>
+            <parameters>
+              <param name="H2PB_MST_N" value="2" caption="--"/>
+              <param name="H2PB_MST_MAX" value="1" caption="derived parameter"/>
+              <param name="H2PB_SLV_N" value="32" caption="--"/>
+              <param name="H2PB_SLV_MAX" value="31" caption="derived parameter"/>
+              <param name="H2PB_PADDR_IDXB" value="5" caption="derived parameter"/>
+              <param name="H2PB_PADDR_LSB" value="13" caption="--"/>
+              <param name="H2PB_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="H2PB_PAGE_SIZE" value="8192" caption="derived parameter"/>
+              <param name="H2PB_OWN_SFR_SLOT" value="28" caption="--"/>
+              <param name="H2PB_PADDR_SIZE" value="18" caption="local parameter"/>
+              <param name="H2PB_PADDR_MSB" value="17" caption="derived local parameter"/>
+              <param name="H2PB_BASE_MSB" value="13" caption="derived parameter"/>
+              <param name="H2PB_USE_HSEL" value="1" caption="--"/>
+              <param name="H2PB_USE_DPATH_PIPER" value="0" caption="1=&quot;all pipelined&quot;0=&quot;address pipelined&quot;"/>
+              <param name="H2PB_USE_EARLY_PREAD" value="0" caption="--"/>
+              <param name="H2PB_CLK_DIV_EN" value="0" caption="1=&quot;n:1 clock&quot;0=&quot;1:1 clock&quot;"/>
+              <param name="H2PB_USE_PSTRB_FOR_READS" value="1" caption="--"/>
+              <param name="H2PB_WPCTRL_KEY" value="0x504231" caption="--"/>
+              <param name="H2PB_NONSEC_INIT_VAL" value="0x00000000" caption="--"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="28" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="46" caption="Instance index for H2PB1"/>
+              <param name="MCLK_ID_AHB" value="57" caption="Index for H2PB1 AHB clock"/>
+              <param name="MCLK_ID_APB" value="58" caption="Index for H2PB1 APB clock"/>
+              <param name="PAC_ID" value="46" caption="Index for H2PB1 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="H2PB2">
+            <register-group name="H2PB2" name-in-module="H2PB" address-space="base" offset="0x4500E000"/>
+            <parameters>
+              <param name="H2PB_MST_N" value="1" caption="--"/>
+              <param name="H2PB_MST_MAX" value="0" caption="derived parameter"/>
+              <param name="H2PB_SLV_N" value="8" caption="--"/>
+              <param name="H2PB_SLV_MAX" value="7" caption="derived parameter"/>
+              <param name="H2PB_PADDR_IDXB" value="3" caption="derived parameter"/>
+              <param name="H2PB_PADDR_LSB" value="13" caption="--"/>
+              <param name="H2PB_WPCTRL_IMPLEMENTED" value="0" caption="--"/>
+              <param name="H2PB_PAGE_SIZE" value="8192" caption="derived parameter"/>
+              <param name="H2PB_OWN_SFR_SLOT" value="7" caption="--"/>
+              <param name="H2PB_PADDR_SIZE" value="16" caption="local parameter"/>
+              <param name="H2PB_PADDR_MSB" value="15" caption="derived local parameter"/>
+              <param name="H2PB_BASE_MSB" value="15" caption="derived parameter"/>
+              <param name="H2PB_USE_HSEL" value="1" caption="--"/>
+              <param name="H2PB_USE_DPATH_PIPER" value="1" caption="1=&quot;all pipelined&quot;0=&quot;address pipelined&quot;"/>
+              <param name="H2PB_USE_EARLY_PREAD" value="0" caption="--"/>
+              <param name="H2PB_CLK_DIV_EN" value="1" caption="1=&quot;n:1 clock&quot;0=&quot;1:1 clock&quot;"/>
+              <param name="H2PB_USE_PSTRB_FOR_READS" value="1" caption="--"/>
+              <param name="H2PB_WPCTRL_KEY" value="0x504232" caption="--"/>
+              <param name="H2PB_NONSEC_INIT_VAL" value="0x00" caption="--"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="7" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="47" caption="Instance index for H2PB2"/>
+              <param name="MCLK_ID_AHB" value="59" caption="Index for H2PB2 AHB clock"/>
+              <param name="MCLK_ID_APB" value="60" caption="Index for H2PB2 APB clock"/>
+              <param name="PAC_ID" value="47" caption="Index for H2PB2 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIX2" id="bus_hmatrix2_v5" name2="bus_hmatrix2_v5" version="5f0">
+          <instance name="HMATRIX2">
+            <register-group name="HMATRIX2" name-in-module="HMATRIX2" address-space="base" offset="0x44010000"/>
+            <parameters>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="8" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="22" caption="Instance index for HMATRIX2"/>
+              <param name="MCLK_ID_AHB" value="30" caption="Index for HMATRIX2 AHB clock"/>
+              <param name="MCLK_ID_APB" value="31" caption="Index for HMATRIX2 APB clock"/>
+              <param name="PAC_ID" value="22" caption="Index for HMATRIX2 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ICB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="ICB">
+            <register-group name="ICB" name-in-module="ICB" address-space="base" offset="0xE000E000"/>
+          </instance>
+        </module>
+        <module name="MCLK" id="04158" name2="clk_mclk_v1" version="1a0">
+          <instance name="MCLK">
+            <register-group name="MCLK" name-in-module="MCLK" address-space="base" offset="0x4400A000"/>
+            <parameters>
+              <param name="MCLK_SYNC_EDGES" value="1" caption="--"/>
+              <param name="MCLK_DIV_CLK_NUM" value="3" caption="one for all other, one for H2PB2 domain, one for MBISTINTF"/>
+              <param name="MCLK_CKDIV_REGS_BITS" value="8" caption="--"/>
+              <param name="MCLK_CKDIV_RESET_VALUE" value="0x1 0x2 0x4 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1" caption="values must be binary divisor numberunused divisors must be 8'h1"/>
+              <param name="MCLK_CKDIV_WRLOCK" value="0x00000000" caption="--"/>
+              <param name="MCLK_CPU_CLK_DIVIDER" value="0" caption="--"/>
+              <param name="MCLK_CPU_CLK_IDLE" value="0" caption="--"/>
+              <param name="MCLK_CPU_CLK_OFFDLY" value="2" caption="--"/>
+              <param name="MCLK_CPU_CLK_ONDLY" value="0" caption="--"/>
+              <param name="MCLK_SYS_CLK_DIVIDER" value="0" caption="--"/>
+              <param name="MCLK_SYS_CLK_OFFDLY" value="2" caption="--"/>
+              <param name="MCLK_CLKMSK_NUM" value="65" caption="--"/>
+              <param name="MCLK_CKPER_IMPLEMENTED" value="0xFFFFFFFF 0xFFFFFFFF 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_RSTVAL" value="0xFFEEFFFF 0xFFFFFFFF 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_DIVIDER" value="0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0" caption="--"/>
+              <param name="MCLK_CKPER_REQEXISTS" value="0xD9FFFFFF 0xE1FFFFFF 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_MASTER" value="0x11800004 0x40400000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="MCLK_CKPER_WILLRISE" value="0x00080000 0x10000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="JTAG_IMPLEMENTED" value="1" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="5" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="9" caption="Instance index for MCLK"/>
+              <param name="MCLK_ID_APB" value="9" caption="Index for MCLK APB clock"/>
+              <param name="PAC_ID" value="9" caption="Index for MCLK registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MCRAMC" id="04921" name2="drm_mcramc_v5" version="5b0">
+          <instance name="MCRAMC">
+            <register-group name="MCRAMC" name-in-module="MCRAMC" address-space="base" offset="0x4402C000"/>
+            <parameters>
+              <param name="AHB_CLOCK_ENABLE" value="0" caption="--"/>
+              <param name="AHB_ECC" value="1" caption="--"/>
+              <param name="AHB_PORTS_NB" value="8" caption="--"/>
+              <param name="AHB_READ_PREBUFFERING" value="0" caption="--"/>
+              <param name="AHB_REQUEST_ISOLATION_REGISTER" value="0" caption="--"/>
+              <param name="ARBITRATION_TYPE" value="2" caption="Parameter should be &quot;ENUM_HOPSCOTCH&quot;Fix for text parameter in ConstellationCONST_DEV-1173"/>
+              <param name="BIT_STROBE_RAM" value="0" caption="parameter n/a if STORE_BYTE_STROBE=0"/>
+              <param name="CHANNELS_NB" value="2" caption="--"/>
+              <param name="ECC_SYNDROM_REGISTER" value="0" caption="--"/>
+              <param name="HADDR_READ_ISOLATION_REGISTER" value="0" caption="--"/>
+              <param name="HRDATA_ISOLATION_CONFIGURABLE" value="1" caption="--"/>
+              <param name="HRDATA_ISOLATION_DEFAULT" value="0" caption="default to 0 wait states"/>
+              <param name="MCRAMC_CLK_GATER" value="0" caption="--"/>
+              <param name="MCRAMC_PADDR_SIZE" value="13" caption="--"/>
+              <param name="MEMORY_AUTO_CORRECTION" value="1" caption="--"/>
+              <param name="MEMORY_ENABLE_POLARITY" value="0" caption="--"/>
+              <param name="MW_CLOCK_ENABLE" value="0" caption="--"/>
+              <param name="MW_DATA_SIZE" value="32" caption="--"/>
+              <param name="MW_PORT_SLICES_NB" value="0" caption="--"/>
+              <param name="M0_CLOCK_ENABLE" value="0" caption="--"/>
+              <param name="M0_DATA_SIZE" value="32" caption="--"/>
+              <param name="M0_HYBRID_READ_WRITE_ACCESS" value="0" caption="--"/>
+              <param name="M0_PORT_SLICES_NB" value="0" caption="--"/>
+              <param name="PRIVILEGED_BIT_CHECK" value="1" caption="--"/>
+              <param name="RAM_ADD_SIZE" value="14" caption="--"/>
+              <param name="RAM_AHB_ADDRESS_OFFSET" value="0" caption="--"/>
+              <param name="RAM_ERASE" value="0" caption="--"/>
+              <param name="STORE_BYTE_STROBE" value="0" caption="--"/>
+              <param name="ULTRA" value="1" caption="--"/>
+              <param name="WP_KEY" value="0x465852" caption="&quot;FXR&quot;"/>
+              <param name="WRITE_ENABLE_POLARITY" value="0" caption="--"/>
+              <param name="WRITE_ENABLE_USED" value="1" caption="--"/>
+              <param name="WRITE_MASK_POLARITY" value="0" caption="--"/>
+              <param name="WRITE_PROTECT_REGISTER" value="0" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="22" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="16" caption="Instance index for MCRAMC"/>
+              <param name="MCLK_ID_APB" value="21" caption="Index for MCRAMC APB clock"/>
+              <param name="MCLK_ID_AHB" value="22" caption="Index for MCRAMC AHB clock"/>
+              <param name="PAC_ID" value="16" caption="Index for MCRAMC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MPU" id="SYSTEM_IP" version="1.0.0">
+          <instance name="MPU">
+            <register-group name="MPU" name-in-module="MPU" address-space="base" offset="0xE000ED90"/>
+            <parameters>
+              <param name="__MPU_REGIONS" value="8" caption="Number of MPU regions"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVIC" id="SYSTEM_IP" version="1.0.0">
+          <instance name="NVIC">
+            <register-group name="NVIC" name-in-module="NVIC" address-space="base" offset="0xE000E100"/>
+            <parameters>
+              <param name="NUM_IRQ" value="141" caption="Number of interrupt request lines"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="OSC32KCTRL" id="03717" name2="osc_osc32kctrl_u2400_v2" version="2a0">
+          <instance name="OSC32KCTRL">
+            <register-group name="OSC32KCTRL" name-in-module="OSC32KCTRL" address-space="base" offset="0x45008000"/>
+            <signals>
+              <signal group="CLKIN32" index="32" function="XOSC32K_XIN32_AMODE" pad="PB01"/>
+              <signal group="XIN32" index="32" function="XOSC32K_XIN32" pad="PB01"/>
+              <signal group="XOUT32" index="32" function="XOSC32K_XOUT32" pad="PB02"/>
+            </signals>
+            <parameters>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="4" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="7" caption="Instance index for OSC32KCTRL"/>
+              <param name="MCLK_ID_APB" value="7" caption="Index for OSC32KCTRL APB clock"/>
+              <param name="PAC_ID" value="7" caption="Index for OSC32KCTRL registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="OSCCTRL" id="03718" name2="osc_oscctrl_u2401_v2" version="2b0">
+          <instance name="OSCCTRL">
+            <register-group name="OSCCTRL" name-in-module="OSCCTRL" address-space="base" offset="0x44006000"/>
+            <signals>
+              <signal group="CLKIN" function="XOSC_XIN_AMODE" pad="PD05"/>
+              <signal group="XIN" function="XOSC_XIN" pad="PD05"/>
+              <signal group="XOUT" function="XOSC_XOUT" pad="PD04"/>
+            </signals>
+            <parameters>
+              <param name="DFLL48M_ATEST_IMPLEMENTED" value="1" caption="--"/>
+              <param name="DFLL48M_ATEST_SIZE" value="8" caption="--"/>
+              <param name="DFLL48M_IS_STARTUP_OSCILLATOR" value="1" caption="--"/>
+              <param name="DFLL48M_RC48MCAL0_PORVAL" value="0x00000000" caption="--"/>
+              <param name="DIV_8MHZ_NUM" value="2" caption="--"/>
+              <param name="FRACDIVS_NUM" value="0" caption="--"/>
+              <param name="FRACDIV_DIVIDER_RESET_VAL" value="0" caption="--"/>
+              <param name="FRACDIV_PLLSRC" value="0" caption="--"/>
+              <param name="PLLS_NUM" value="1" caption="--"/>
+              <param name="PLL0_OUTPUTS_NUM" value="5" caption="--"/>
+              <param name="PLL1_OUTPUTS_NUM" value="0" caption="--"/>
+              <param name="USBHS_NUM" value="1" caption="should be 0, but IP has bug"/>
+              <param name="XOSC_ATEST_IMPLEMENTED" value="1" caption="--"/>
+              <param name="XOSC_ATEST_SIZE" value="4" caption="--"/>
+              <param name="XOSC_CFD_CLK_SELECT_SIZE" value="4" caption="--"/>
+              <param name="XOSC_CFD_HAS_RETENTION" value="0" caption="--"/>
+              <param name="GCLK_ID_DFLL48M" value="0"/>
+              <param name="GCLK_ID_PLL" value="1"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="3" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="6" caption="Instance index for OSCCTRL"/>
+              <param name="MCLK_ID_APB" value="6" caption="Index for OSCCTRL APB clock"/>
+              <param name="PAC_ID" value="6" caption="Index for OSCCTRL registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PAC" id="04298" name2="sec_pac_apb_v1" version="1a0">
+          <instance name="PAC">
+            <register-group name="PAC" name-in-module="PAC" address-space="base" offset="0x44022000"/>
+            <parameters>
+              <param name="PAC_PER_WRPROT_MASK" value="0xFFFFFFFF 0x0003FFFF 0x00000000 0x00000000" caption="Peripheral implemented mask. If PAC_PER_WRPROT_MASK[x]=1 then the PAC implements an SFR bit in INTFLAG, STATUS, and LOCK with the location of &lt;REG&gt;(x/32)[x mod 32]"/>
+              <param name="PAC_STATUS_RESET_VALUE" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="WRP STATUS Reset Value for Peripherals. On reset STATUS(x/32)[x mod 32]=PAC_STATUS_RESET_VALUE[x]The reset value for each peripheral should always be 0. The parameter exists if there is an unforeseen circumstance requiring it to be 1. Test blocks are not one of them as they are protected by dsu_test_mode."/>
+              <param name="PAC_LOCK_RESET_VALUE" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="PAC_ERRORS_INBAND" value="1" caption="--"/>
+              <param name="PAC_CTRLAPRIV_IMPLEMENTED" value="1" caption="--"/>
+              <param name="PAC_INTFLAGSET_IMPLEMENTED" value="0" caption="--"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="17" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="14" caption="Instance index for PAC"/>
+              <param name="MCLK_ID_APB" value="14" caption="Index for PAC APB clock"/>
+              <param name="PAC_ID" value="14" caption="Index for PAC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PDM" id="test_pdm_v1" name2="test_pdm_v1" version="1.0.0">
+          <instance name="PDM">
+            <signals>
+              <signal group="PDMDIS" function="TST_DIG" pad="PDMDIS"/>
+              <signal group="PDMI" index="0" function="PDMI_TEST" pad="PD07"/>
+              <signal group="PDMI" index="1" function="PDMI_TEST" pad="PD08"/>
+              <signal group="PDMI" index="2" function="PDMI_TEST" pad="PD09"/>
+              <signal group="PDMI" index="3" function="PDMI_TEST" pad="PA00"/>
+              <signal group="PDMO" index="0" function="PDMO_LV_TEST" pad="PB03"/>
+              <signal group="PDMO" index="1" function="PDMO_LV_TEST" pad="PB04"/>
+              <signal group="PDMO" index="2" function="PDMO_LV_TEST" pad="PB05"/>
+              <signal group="PDMO" index="3" function="PDMO_LV_TEST" pad="PB06"/>
+              <signal group="PDMO" index="4" function="PDMO_LV_TEST" pad="PC00"/>
+              <signal group="PDMO" index="5" function="PDMO_LV_TEST" pad="PC01"/>
+              <signal group="PDMO" index="6" function="PDMO_LV_TEST" pad="PC02"/>
+              <signal group="PDMO" index="7" function="PDMO_LV_TEST" pad="PC03"/>
+              <signal group="PDMO0_MV" function="PDMO_MV_TEST" pad="PB03"/>
+              <signal group="PDMO1_MV" function="PDMO_MV_TEST" pad="PB04"/>
+              <signal group="PDMO2_MV" function="PDMO_MV_TEST" pad="PB05"/>
+              <signal group="PDMO3_MV" function="PDMO_MV_TEST" pad="PB06"/>
+              <signal group="PDMO4_MV" function="PDMO_MV_TEST" pad="PC00"/>
+              <signal group="PDMO5_MV" function="PDMO_MV_TEST" pad="PC01"/>
+              <signal group="PDMO6_MV" function="PDMO_MV_TEST" pad="PC02"/>
+              <signal group="PDMO7_MV" function="PDMO_MV_TEST" pad="PC03"/>
+            </signals>
+          </instance>
+        </module>
+        <module name="PM" id="03926" name2="pwr_rpmu_pm_v1" version="1c0">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x45000000"/>
+            <parameters>
+              <param name="BACKUP_IMPLEMENTED" value="1" caption="--"/>
+              <param name="PD_NUM" value="1" caption="Number of Switchable Power Domains2 total domains (PD_CORE_SW and PD_CORE_BU)"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="0" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="3" caption="Instance index for PM"/>
+              <param name="MCLK_ID_APB" value="3" caption="Index for PM APB clock"/>
+              <param name="PAC_ID" value="3" caption="Index for PM registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PORT" id="03720" name2="gpio_port_u2210_v4" version="4a0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x44800000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="32" function="default" pad="PB00"/>
+              <signal group="P" index="33" function="default" pad="PB01"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="36" function="default" pad="PB04"/>
+              <signal group="P" index="37" function="default" pad="PB05"/>
+              <signal group="P" index="38" function="default" pad="PB06"/>
+              <signal group="P" index="39" function="default" pad="PB07"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+              <signal group="P" index="42" function="default" pad="PB10"/>
+              <signal group="P" index="43" function="default" pad="PB11"/>
+              <signal group="P" index="44" function="default" pad="PB12"/>
+              <signal group="P" index="45" function="default" pad="PB13"/>
+              <signal group="P" index="46" function="default" pad="PB14"/>
+              <signal group="P" index="47" function="default" pad="PB15"/>
+              <signal group="P" index="48" function="default" pad="PB16"/>
+              <signal group="P" index="49" function="default" pad="PB17"/>
+              <signal group="P" index="64" function="default" pad="PC00"/>
+              <signal group="P" index="65" function="default" pad="PC01"/>
+              <signal group="P" index="66" function="default" pad="PC02"/>
+              <signal group="P" index="67" function="default" pad="PC03"/>
+              <signal group="P" index="68" function="default" pad="PC04"/>
+              <signal group="P" index="69" function="default" pad="PC05"/>
+              <signal group="P" index="70" function="default" pad="PC06"/>
+              <signal group="P" index="71" function="default" pad="PC07"/>
+              <signal group="P" index="72" function="default" pad="PC08"/>
+              <signal group="P" index="73" function="default" pad="PC09"/>
+              <signal group="P" index="74" function="default" pad="PC10"/>
+              <signal group="P" index="75" function="default" pad="PC11"/>
+              <signal group="P" index="76" function="default" pad="PC12"/>
+              <signal group="P" index="77" function="default" pad="PC13"/>
+              <signal group="P" index="78" function="default" pad="PC14"/>
+              <signal group="P" index="79" function="default" pad="PC15"/>
+              <signal group="P" index="80" function="default" pad="PC16"/>
+              <signal group="P" index="81" function="default" pad="PC17"/>
+              <signal group="P" index="82" function="default" pad="PC18"/>
+              <signal group="P" index="83" function="default" pad="PC19"/>
+              <signal group="P" index="96" function="default" pad="PD00"/>
+              <signal group="P" index="97" function="default" pad="PD01"/>
+              <signal group="P" index="98" function="default" pad="PD02"/>
+              <signal group="P" index="99" function="default" pad="PD03"/>
+              <signal group="P" index="100" function="default" pad="PD04"/>
+              <signal group="P" index="101" function="default" pad="PD05"/>
+              <signal group="P" index="102" function="default" pad="PD06"/>
+              <signal group="P" index="103" function="default" pad="PD07"/>
+              <signal group="P" index="104" function="default" pad="PD08"/>
+              <signal group="P" index="105" function="default" pad="PD09"/>
+              <signal group="P" index="106" function="default" pad="PD10"/>
+              <signal group="P" index="107" function="default" pad="PD11"/>
+              <signal group="P" index="108" function="default" pad="PD12"/>
+              <signal group="P" index="109" function="default" pad="PD13"/>
+              <signal group="P" index="110" function="default" pad="PD14"/>
+              <signal group="P" index="111" function="default" pad="PD15"/>
+              <signal group="P" index="112" function="default" pad="PD16"/>
+              <signal group="P" index="113" function="default" pad="PD17"/>
+              <signal group="P" index="114" function="default" pad="PD18"/>
+              <signal group="P" index="115" function="default" pad="PD19"/>
+              <signal group="P" index="116" function="default" pad="PD20"/>
+            </signals>
+            <parameters>
+              <param name="AHB_IMPLEMENTED" value="0" caption="No AHB bus"/>
+              <param name="BITS" value="117" caption="--"/>
+              <param name="DIR_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DIR_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="DIR RegistersImplemented"/>
+              <param name="DRVSTR" value="0" caption="No DRVSTR bits"/>
+              <param name="DRVSTR_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DRVSTR_IMPLEMENTED" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="PINCFG.DRVSTR0RegistersImplemented"/>
+              <param name="DRVSTR1_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="DRVSTR1_IMPLEMENTED" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="PINCFG.DRVSTR1RegistersImplemented"/>
+              <param name="EVENT_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="Event RegistersImplemented"/>
+              <param name="EV_NUM" value="4" caption="--"/>
+              <param name="GROUPS" value="4" caption="--"/>
+              <param name="HADDR_MSB" value="31" caption="--"/>
+              <param name="INEN_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="INEN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.INENRegistersImplemented"/>
+              <param name="IOBUS_IMPLEMENTED" value="0" caption="No IOBUS"/>
+              <param name="MSB" value="116" caption="PORT_BITS-1"/>
+              <param name="NONSEC_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="NONSEC_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="NONSECRegistersImplemented"/>
+              <param name="ODRAIN" value="1" caption="--"/>
+              <param name="ODRAIN_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="ODRAIN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.ODRAINRegistersImplemented"/>
+              <param name="OUT_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="OUT_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="OUT RegistersImplemented"/>
+              <param name="PIN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="Port PinsImplemented"/>
+              <param name="PMUXBIT0_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x0000000C" caption="--"/>
+              <param name="PMUXBIT0_IMPLEMENTED" value="0x001FFFFF 0x0003FFF9 0x000FFE7F 0x001FFFC3" caption="Bit 0 of PMUX field"/>
+              <param name="PMUXBIT1_DEFAULT_VAL" value="0x00000000 0x00000000 0x000001E0 0x0000000C" caption="--"/>
+              <param name="PMUXBIT1_IMPLEMENTED" value="0x0007FFFF 0x000387F9 0x000FFE7F 0x001FFFF3" caption="Bit 1 of PMUX field"/>
+              <param name="PMUXBIT2_DEFAULT_VAL" value="0x00000000 0x00000000 0x000001E0 0x0000000C" caption="--"/>
+              <param name="PMUXBIT2_IMPLEMENTED" value="0x001BFFFF 0x00007FF9 0x0000067F 0x00003FC3" caption="Bit 2 of PMUX field"/>
+              <param name="PMUXBIT3_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="PMUXBIT3_IMPLEMENTED" value="0x001FFFFF 0x0003FFF9 0x000BFE7F 0x001FDFF3" caption="Bit 3 of PMUX field"/>
+              <param name="PMUXEN_DEFAULT_VAL" value="0x00000000 0x00000000 0x000001E0 0x00000000" caption="--"/>
+              <param name="PMUXEN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.PMUXEN bit"/>
+              <param name="PPP_IMPLEMENTED" value="0" caption="No IOBUS2"/>
+              <param name="PULLEN_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="PULLEN_IMPLEMENTED" value="0x001FFFFF 0x0003FFFF 0x000FFFFF 0x001FFFFF" caption="PINCFG.PULLENRegistersImplemented"/>
+              <param name="SECURE_IMPLEMENTED" value="1" caption="Mixed Secure Enabled"/>
+              <param name="SLEWLIM" value="2" caption="Number of SLEWLIM bit"/>
+              <param name="SLEWLIM_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="SLEWLIM_IMPLEMENTED" value="0x0007C07F 0x00038078 0x000FF87F 0x001FCFC3" caption="PINCFG.SLEWLIM0RegistersImplemented"/>
+              <param name="SLEWLIM1_DEFAULT_VAL" value="0x00000000 0x00000000 0x00000000 0x00000000" caption="--"/>
+              <param name="SLEWLIM1_IMPLEMENTED" value="0x0007C07F 0x00038078 0x000FF87F 0x001FCFC3" caption="PINCFG.SLEWLIM1RegistersImplemented"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="0" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="20" caption="Instance index for PORT"/>
+              <param name="MCLK_ID_APB" value="27" caption="Index for PORT APB clock"/>
+              <param name="PAC_ID" value="20" caption="Index for PORT registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="04743" name2="afe_ptc_ctrl_apb_plrs_v1" version="1a0">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x4482C000"/>
+            <signals>
+              <signal group="PTCXY" index="0" function="P" pad="PD06"/>
+              <signal group="PTCXY" index="1" function="P" pad="PD07"/>
+              <signal group="PTCXY" index="2" function="P" pad="PD08"/>
+              <signal group="PTCXY" index="3" function="P" pad="PD09"/>
+              <signal group="PTCXY" index="4" function="P" pad="PA00"/>
+              <signal group="PTCXY" index="5" function="P" pad="PA01"/>
+              <signal group="PTCXY" index="6" function="P" pad="PA02"/>
+              <signal group="PTCXY" index="7" function="P" pad="PA03"/>
+              <signal group="PTCXY" index="8" function="P" pad="PA04"/>
+              <signal group="PTCXY" index="9" function="P" pad="PA05"/>
+              <signal group="PTCXY" index="10" function="P" pad="PA06"/>
+              <signal group="PTCXY" index="11" function="P" pad="PA07"/>
+              <signal group="PTCXY" index="12" function="P" pad="PA08"/>
+              <signal group="PTCXY" index="13" function="P" pad="PA09"/>
+              <signal group="PTCXY" index="14" function="P" pad="PB00"/>
+              <signal group="PTCXY" index="15" function="P" pad="PB03"/>
+              <signal group="PTCXY" index="16" function="P" pad="PB04"/>
+              <signal group="PTCXY" index="17" function="P" pad="PB05"/>
+              <signal group="PTCXY" index="18" function="P" pad="PB06"/>
+              <signal group="PTCXY" index="19" function="P" pad="PC00"/>
+              <signal group="PTCXY" index="20" function="P" pad="PC01"/>
+              <signal group="PTCXY" index="21" function="P" pad="PC02"/>
+              <signal group="PTCXY" index="22" function="P" pad="PA10"/>
+              <signal group="PTCXY" index="23" function="P" pad="PA11"/>
+              <signal group="PTCXY" index="24" function="P" pad="PA12"/>
+              <signal group="PTCXY" index="25" function="P" pad="PA13"/>
+              <signal group="PTCXY" index="26" function="P" pad="PB07"/>
+              <signal group="PTCXY" index="27" function="P" pad="PB08"/>
+              <signal group="PTCXY" index="28" function="P" pad="PB09"/>
+              <signal group="PTCXY" index="29" function="P" pad="PB10"/>
+              <signal group="PTCXY" index="30" function="P" pad="PC09"/>
+              <signal group="PTCXY" index="31" function="P" pad="PC10"/>
+              <signal group="PTCXY" index="32" function="P" pad="PA14"/>
+              <signal group="PTCXY" index="33" function="P" pad="PA15"/>
+              <signal group="PTCXY" index="34" function="P" pad="PA16"/>
+              <signal group="PTCXY" index="35" function="P" pad="PA17"/>
+              <signal group="DRV" index="0" function="P" pad="PD06"/>
+              <signal group="DRV" index="1" function="P" pad="PD07"/>
+              <signal group="DRV" index="2" function="P" pad="PD08"/>
+              <signal group="DRV" index="3" function="P" pad="PD09"/>
+              <signal group="DRV" index="4" function="P" pad="PA00"/>
+              <signal group="DRV" index="5" function="P" pad="PA01"/>
+              <signal group="DRV" index="6" function="P" pad="PA02"/>
+              <signal group="DRV" index="7" function="P" pad="PA03"/>
+              <signal group="DRV" index="8" function="P" pad="PA04"/>
+              <signal group="DRV" index="9" function="P" pad="PA05"/>
+              <signal group="DRV" index="10" function="P" pad="PA06"/>
+              <signal group="DRV" index="11" function="P" pad="PA07"/>
+              <signal group="DRV" index="12" function="P" pad="PA08"/>
+              <signal group="DRV" index="13" function="P" pad="PA09"/>
+              <signal group="DRV" index="14" function="P" pad="PB00"/>
+              <signal group="DRV" index="15" function="P" pad="PB03"/>
+              <signal group="DRV" index="16" function="P" pad="PB04"/>
+              <signal group="DRV" index="17" function="P" pad="PB05"/>
+              <signal group="DRV" index="18" function="P" pad="PB06"/>
+              <signal group="DRV" index="19" function="P" pad="PC00"/>
+              <signal group="DRV" index="20" function="P" pad="PC01"/>
+              <signal group="DRV" index="21" function="P" pad="PC02"/>
+              <signal group="DRV" index="22" function="P" pad="PA10"/>
+              <signal group="DRV" index="23" function="P" pad="PA11"/>
+              <signal group="DRV" index="24" function="P" pad="PA12"/>
+              <signal group="DRV" index="25" function="P" pad="PA13"/>
+              <signal group="DRV" index="26" function="P" pad="PB07"/>
+              <signal group="DRV" index="27" function="P" pad="PB08"/>
+              <signal group="DRV" index="28" function="P" pad="PB09"/>
+              <signal group="DRV" index="29" function="P" pad="PB10"/>
+              <signal group="DRV" index="30" function="P" pad="PC09"/>
+              <signal group="DRV" index="31" function="P" pad="PC10"/>
+              <signal group="DRV" index="32" function="P" pad="PA14"/>
+              <signal group="DRV" index="33" function="P" pad="PA15"/>
+              <signal group="DRV" index="34" function="P" pad="PA16"/>
+              <signal group="DRV" index="35" function="P" pad="PA17"/>
+              <signal group="ECI" index="0" function="P" pad="PC03"/>
+              <signal group="ECI" index="1" function="P" pad="PC04"/>
+            </signals>
+            <parameters>
+              <param name="PTC_PDATA_MSB" value="31" caption="APB Data Bus Size MSB"/>
+              <param name="PTC_PADDR_MSB" value="12" caption="APB Address Bus Size MSB"/>
+              <param name="PTC_PADDR_SIZE" value="13" caption="Number of bits of the paddr input busPossible Values = PTC_PADDR_MSB -1"/>
+              <param name="PTC_LINES_NUM" value="36" caption="Number of PTC lines desired (0 to 64)"/>
+              <param name="PTC_CAL_IMPLEMENTED" value="1" caption="Defines if the CALIB register is implemented (1 = implemented)"/>
+              <param name="PTC_CAL_SIZE" value="16" caption="Defines Bitfield size for CALIB register"/>
+              <param name="PTC_CAL_PORVAL" value="0x00000000" caption="Defines the CALIB register reset value after POR0x00000000 to 0xFFFFFFFF"/>
+              <param name="PTC_ATEST_IMPLEMENTED" value="1" caption="Defines if the ATEST register is implemented (1 = implemented)"/>
+              <param name="PTC_ATEST_SIZE" value="8" caption="Defines the number of effective bits in ATEST register"/>
+              <param name="PTC_WPCTRL_IMPLEMENTED" value="0" caption="Implement the WPCTRL register for write protection.0 = Use apb_ptc_wrprot to control write protection enable/disable1 = Use WPCTRL register to control write protection enable/disable."/>
+              <param name="PTC_PRIV_IMPLEMENTED" value="1" caption="Implement the PRIV register for privilege/non-privilege bus accesses.0 = Register not present1 = Register present"/>
+              <param name="PTC_WPCTRL_KEY" value="0x505443" caption="WPCTRL 24-bit key value. See register description for usage.Set to a unique value for each macro."/>
+              <param name="GCLK_ID" value="35"/>
+              <param name="DMAC_ID_EOC" value="38"/>
+              <param name="DMAC_ID_SEQ" value="39"/>
+              <param name="DMAC_ID_WCOMP" value="40"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="22" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="41" caption="Instance index for PTC"/>
+              <param name="MCLK_ID_APB" value="51" caption="Index for PTC APB clock"/>
+              <param name="PAC_ID" value="41" caption="Index for PTC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RSTC" id="03926" name2="pwr_rpmu_rstc_v1" version="1c0">
+          <instance name="RSTC">
+            <register-group name="RSTC" name-in-module="RSTC" address-space="base" offset="0x45004000"/>
+            <parameters>
+              <param name="BACKUP_IMPLEMENTED" value="1"/>
+              <param name="CM_DBGRESET_STRETCHED" value="3" caption="Reset stretcher size for Cortex CPU related to DBGRESET."/>
+              <param name="CM_HRESET_N_STRETCHED" value="3" caption="Reset stretcher size for Cortex CPU related to HRESETn."/>
+              <param name="CM_PORESET_STRETCHED" value="3" caption="Reset stretcher size for Cortex CPU related to PORESET."/>
+              <param name="HIB_IMPLEMENTED" value="1"/>
+              <param name="VBAT_IMPLEMENTED" value="0" caption="One if VBAT (Battery backup mode) is supported"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="2" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="5" caption="Instance index for RSTC"/>
+              <param name="MCLK_ID_APB" value="5" caption="Index for RSTC APB clock"/>
+              <param name="PAC_ID" value="5" caption="Index for RSTC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="03608" name2="tmr_rtc_u2250_v3" version="3b0">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x45006000"/>
+            <signals>
+              <signal group="IN" index="0" function="RTC_PAD_IE" pad="PA07"/>
+              <signal group="IN" index="1" function="RTC_PAD_IE" pad="PA08"/>
+              <signal group="IN" index="2" function="RTC_PAD_IE" pad="PA09"/>
+              <signal group="IN" index="3" function="RTC_PAD_IE" pad="PB00"/>
+              <signal group="IN" index="4" function="RTC_PAD_IE" pad="PB07"/>
+              <signal group="IN" index="5" function="RTC_PAD_IE" pad="PB08"/>
+              <signal group="IN" index="6" function="RTC_PAD_IE" pad="PB11"/>
+              <signal group="IN" index="7" function="RTC_PAD_IE" pad="PB12"/>
+              <signal group="OUT" index="0" function="_RTC_PAD_OE_N" pad="PB03"/>
+              <signal group="OUT" index="1" function="_RTC_PAD_OE_N" pad="PB04"/>
+              <signal group="OUT" index="2" function="_RTC_PAD_OE_N" pad="PB05"/>
+              <signal group="OUT" index="3" function="_RTC_PAD_OE_N" pad="PB06"/>
+              <signal group="OUT" index="4" function="_RTC_PAD_OE_N" pad="PB09"/>
+              <signal group="OUT" index="5" function="_RTC_PAD_OE_N" pad="PB10"/>
+              <signal group="OUT" index="6" function="_RTC_PAD_OE_N" pad="PB13"/>
+              <signal group="OUT" index="7" function="_RTC_PAD_OE_N" pad="PB14"/>
+            </signals>
+            <parameters>
+              <param name="NUM_OF_ALARMS" value="2" caption="--"/>
+              <param name="NUM_OF_BKREGS" value="0" caption="--"/>
+              <param name="NUM_OF_COMP16" value="4" caption="=2 * RTC_NUM_OF_ALARMS"/>
+              <param name="NUM_OF_TAMPERS" value="8" caption="--"/>
+              <param name="DMAC_ID_TIMESTAMP" value="3"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="3" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="12" caption="Instance index for RTC"/>
+              <param name="MCLK_ID_APB" value="12" caption="Index for RTC APB clock"/>
+              <param name="PAC_ID" value="12" caption="Index for RTC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SAU" id="SYSTEM_IP" version="1.0.0">
+          <instance name="SAU">
+            <register-group name="SAU" name-in-module="SAU" address-space="base" offset="0xE000EDD0"/>
+          </instance>
+        </module>
+        <module name="SCB" id="SYSTEM_IP" version="1.0.0">
+          <instance name="SCB">
+            <register-group name="SCB" name-in-module="SCB" address-space="base" offset="0xE000ED00"/>
+          </instance>
+        </module>
+        <module name="SERCOM" id="03715" name2="com_sercom_u2201_v6" version="6c0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x44808000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PB15" ioset="2"/>
+              <signal group="PAD" index="0" function="D" pad="PC00" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PB16" ioset="2"/>
+              <signal group="PAD" index="1" function="D" pad="PC01" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PB17" ioset="2"/>
+              <signal group="PAD" index="2" function="D" pad="PC02" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PC11" ioset="2"/>
+              <signal group="PAD" index="3" function="D" pad="PC03" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="DMAC_ID_RX" value="4"/>
+              <param name="DMAC_ID_TX" value="5"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="4" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="26" caption="Instance index for SERCOM0"/>
+              <param name="MCLK_ID_APB" value="36" caption="Index for SERCOM0 APB clock"/>
+              <param name="PAC_ID" value="26" caption="Index for SERCOM0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x4480A000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PC15" ioset="3"/>
+              <signal group="PAD" index="0" function="D" pad="PD01"/>
+              <signal group="PAD" index="1" function="D" pad="PC14" ioset="3"/>
+              <signal group="PAD" index="1" function="D" pad="PD00"/>
+              <signal group="PAD" index="2" function="D" pad="PC13" ioset="3"/>
+              <signal group="PAD" index="2" function="D" pad="PC06" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PD10" ioset="2"/>
+              <signal group="PAD" index="3" function="D" pad="PC12" ioset="3"/>
+              <signal group="PAD" index="3" function="D" pad="PC05" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PD11" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="DMAC_ID_RX" value="6"/>
+              <param name="DMAC_ID_TX" value="7"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="5" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="27" caption="Instance index for SERCOM1"/>
+              <param name="MCLK_ID_APB" value="37" caption="Index for SERCOM1 APB clock"/>
+              <param name="PAC_ID" value="27" caption="Index for SERCOM1 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x4480C000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PC04" ioset="1"/>
+              <signal group="PAD" index="0" function="D" pad="PC19" ioset="2"/>
+              <signal group="PAD" index="1" function="D" pad="PC18" ioset="2"/>
+              <signal group="PAD" index="1" function="D" pad="PD06" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PC17" ioset="2"/>
+              <signal group="PAD" index="2" function="D" pad="PD07" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PC16" ioset="2"/>
+              <signal group="PAD" index="3" function="D" pad="PD08" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="DMAC_ID_RX" value="8"/>
+              <param name="DMAC_ID_TX" value="9"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="6" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="28" caption="Instance index for SERCOM2"/>
+              <param name="MCLK_ID_APB" value="38" caption="Index for SERCOM2 APB clock"/>
+              <param name="PAC_ID" value="28" caption="Index for SERCOM2 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x4480E000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PD16" ioset="2"/>
+              <signal group="PAD" index="0" function="D" pad="PD09" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PA00" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PD15" ioset="2"/>
+              <signal group="PAD" index="2" function="D" pad="PA01" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PD17" ioset="2"/>
+              <signal group="PAD" index="3" function="D" pad="PA02" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PD14" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="1" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="1" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_SLOW" value="20"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="DMAC_ID_RX" value="10"/>
+              <param name="DMAC_ID_TX" value="11"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="7" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="29" caption="Instance index for SERCOM3"/>
+              <param name="MCLK_ID_APB" value="39" caption="Index for SERCOM3 APB clock"/>
+              <param name="PAC_ID" value="29" caption="Index for SERCOM3 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x44820000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA03" ioset="1"/>
+              <signal group="PAD" index="0" function="D" pad="PD19" ioset="2"/>
+              <signal group="PAD" index="1" function="D" pad="PA04" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PD20" ioset="2"/>
+              <signal group="PAD" index="2" function="D" pad="PA05" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PD18" ioset="2"/>
+              <signal group="PAD" index="3" function="D" pad="PA14" ioset="2"/>
+              <signal group="PAD" index="3" function="D" pad="PA06" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="0" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="0" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_CORE" value="28"/>
+              <param name="DMAC_ID_RX" value="24"/>
+              <param name="DMAC_ID_TX" value="25"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="16" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="34" caption="Instance index for SERCOM4"/>
+              <param name="MCLK_ID_APB" value="44" caption="Index for SERCOM4 APB clock"/>
+              <param name="PAC_ID" value="34" caption="Index for SERCOM4 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x44822000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16" ioset="2"/>
+              <signal group="PAD" index="0" function="D" pad="PB03" ioset="1"/>
+              <signal group="PAD" index="1" function="D" pad="PA17" ioset="2"/>
+              <signal group="PAD" index="1" function="D" pad="PB04" ioset="1"/>
+              <signal group="PAD" index="2" function="D" pad="PA18" ioset="2"/>
+              <signal group="PAD" index="2" function="D" pad="PB05" ioset="1"/>
+              <signal group="PAD" index="3" function="D" pad="PA15" ioset="2"/>
+              <signal group="PAD" index="3" function="D" pad="PB06" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CLK_REDUCTION" value="1" caption="Reduce clock options to pin 1 for SPI and USART"/>
+              <param name="DMA" value="1" caption="DMA support implemented?"/>
+              <param name="FIFO_IMPLEMENTED" value="1" caption="FIFO Rx/Tx implemented?"/>
+              <param name="FIFO_SIZE" value="16" caption="Rx-Tx FIFO size in bytes"/>
+              <param name="FSYNC_IMPLEMENTED" value="1" caption="SPI Frame Synch mode implemented?"/>
+              <param name="SPI" value="1" caption="SPI mode implemented?"/>
+              <param name="TWIM" value="0" caption="TWI Master mode implemented?"/>
+              <param name="TWIS" value="0" caption="TWI Slave mode implemented?"/>
+              <param name="ULTRA_IMPLEMENTATION" value="0" caption="ULTRA platform compatibility?"/>
+              <param name="USART" value="1" caption="USART mode implemented?"/>
+              <param name="USART_AUTOBAUD" value="1" caption="USART autobaud implemented?"/>
+              <param name="USART_IRDA" value="1" caption="USART IrDA implemented?"/>
+              <param name="USART_LIN_MASTER" value="1" caption="USART LIN Master mode implemented?"/>
+              <param name="USART_RS485" value="1" caption="USART RS485 mode implemented?"/>
+              <param name="GCLK_ID_CORE" value="29"/>
+              <param name="DMAC_ID_RX" value="26"/>
+              <param name="DMAC_ID_TX" value="27"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="17" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="35" caption="Instance index for SERCOM5"/>
+              <param name="MCLK_ID_APB" value="45" caption="Index for SERCOM5 APB clock"/>
+              <param name="PAC_ID" value="35" caption="Index for SERCOM5 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SUPC" id="03926" name2="pwr_rpmu_supc_v1" version="1c0">
+          <instance name="SUPC">
+            <register-group name="SUPC" name-in-module="SUPC" address-space="base" offset="0x45002000"/>
+            <signals>
+              <signal group="RESETn" function="RES" pad="RESET_N"/>
+              <signal group="SMOR_DTEST" index="0" function="SUPC_VREF_TESTMODE" pad="PD08"/>
+              <signal group="SMOR_DTEST" index="1" function="SUPC_VREF_TESTMODE" pad="PD09"/>
+              <signal group="SMOR_DTEST" index="2" function="SUPC_VREF_TESTMODE" pad="PD07"/>
+              <signal group="SMOR_DTEST" index="3" function="SUPC_VREF_TESTMODE" pad="PA00"/>
+              <signal group="SMOR_DTEST" index="4" function="SUPC_VREF_TESTMODE" pad="PA01"/>
+              <signal group="SMOR_DTEST" index="5" function="SUPC_VREF_TESTMODE" pad="PA02"/>
+              <signal group="SMOR_DTEST" index="6" function="SUPC_VREF_TESTMODE" pad="PA03"/>
+              <signal group="SMOR_DTEST" index="7" function="SUPC_VREF_TESTMODE" pad="PA04"/>
+              <signal group="SMOR_DTEST" index="8" function="SUPC_VREF_TESTMODE" pad="PB03"/>
+              <signal group="SMOR_DTEST" index="9" function="SUPC_VREF_TESTMODE" pad="PB04"/>
+              <signal group="SMOR_DTEST" index="10" function="SUPC_VREF_TESTMODE" pad="PB05"/>
+              <signal group="SMOR_DTEST" index="11" function="SUPC_VREF_TESTMODE" pad="PB06"/>
+              <signal group="SMOR_DTEST" index="12" function="SUPC_VREF_TESTMODE" pad="PC00"/>
+              <signal group="SMOR_DTEST" index="13" function="SUPC_VREF_TESTMODE" pad="PA06"/>
+              <signal group="SMOR_DTEST" index="14" function="SUPC_VREF_TESTMODE" pad="PA07"/>
+              <signal group="SMOR_DTEST" index="15" function="SUPC_VREF_TESTMODE" pad="PC03"/>
+              <signal group="OUT" index="0" function="SUPC" pad="PB04"/>
+              <signal group="OUT" index="1" function="SUPC" pad="PB05"/>
+              <signal group="USERLDO" function="USER_LDO" pad="PD06"/>
+              <signal group="USERLDO_OUT" function="USER_LDO_OP_AMP" pad="USERLDO"/>
+            </signals>
+            <parameters>
+              <param name="ADDVREG_NUM" value="1" caption="Jira PWR109-210"/>
+              <param name="ADDVREG_PLL_NUM" value="0" caption="--"/>
+              <param name="ADDVREG_PLL_START_INDEX" value="1" caption="--"/>
+              <param name="BKOUT_NUM" value="2" caption="--"/>
+              <param name="BORVDDUSB_NUM" value="1" caption="(Jira PWR109-219)"/>
+              <param name="CHRG_PUMP_NUM" value="2" caption="--"/>
+              <param name="IOB_IMPLEMENTED" value="0" caption="--"/>
+              <param name="USER_LDO_IMPLEMENTED" value="1" caption="--"/>
+              <param name="VBAT_IMPLEMENTED" value="0" caption="--"/>
+              <param name="VREGSW_NUM" value="1" caption="--"/>
+              <param name="BRIDGE_ID" value="2" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="1" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="4" caption="Instance index for SUPC"/>
+              <param name="MCLK_ID_APB" value="4" caption="Index for SUPC APB clock"/>
+              <param name="PAC_ID" value="4" caption="Index for SUPC registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SysTick" id="SYSTEM_IP" version="1.0.0">
+          <instance name="SysTick">
+            <register-group name="SysTick" name-in-module="SysTick" address-space="base" offset="0xE000E010"/>
+            <parameters>
+              <param name="__SYST_NUM" value="2" caption="Number of implemented SysTick timers"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="03610" name2="tmr_tcc_u2213_v4" version="4d0">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x44810000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PA19" ioset="2"/>
+              <signal group="WO" index="0" function="F" pad="PB11" ioset="3"/>
+              <signal group="WO" index="0" function="F" pad="PC00" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PA20" ioset="2"/>
+              <signal group="WO" index="1" function="F" pad="PB12" ioset="3"/>
+              <signal group="WO" index="1" function="F" pad="PC01" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="1" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID_TCC01" value="25"/>
+              <param name="DMAC_ID_OVF" value="12"/>
+              <param name="DMAC_ID_MC0" value="13"/>
+              <param name="DMAC_ID_MC1" value="14"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="8" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="30" caption="Instance index for TCC0"/>
+              <param name="MCLK_ID_APB" value="40" caption="Index for TCC0 APB clock"/>
+              <param name="PAC_ID" value="30" caption="Index for TCC0 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x44812000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PC02" ioset="1"/>
+              <signal group="WO" index="0" function="F" pad="PC09" ioset="2"/>
+              <signal group="WO" index="1" function="F" pad="PC03" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PC10" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="2" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID_TCC01" value="25"/>
+              <param name="DMAC_ID_OVF" value="15"/>
+              <param name="DMAC_ID_MC0" value="16"/>
+              <param name="DMAC_ID_MC1" value="17"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="9" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="31" caption="Instance index for TCC1"/>
+              <param name="MCLK_ID_APB" value="41" caption="Index for TCC1 APB clock"/>
+              <param name="PAC_ID" value="31" caption="Index for TCC1 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x44814000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PB09" ioset="2"/>
+              <signal group="WO" index="0" function="F" pad="PC04" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PB08" ioset="2"/>
+              <signal group="WO" index="1" function="F" pad="PC05" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DMAC_ID_MC0" value="19"/>
+              <param name="DMAC_ID_MC1" value="20"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="10" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="32" caption="Instance index for TCC2"/>
+              <param name="MCLK_ID_APB" value="42" caption="Index for TCC2 APB clock"/>
+              <param name="PAC_ID" value="32" caption="Index for TCC2 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC3">
+            <register-group name="TCC3" name-in-module="TCC" address-space="base" offset="0x44816000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PB13" ioset="2"/>
+              <signal group="WO" index="0" function="F" pad="PD00" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PB14" ioset="2"/>
+              <signal group="WO" index="1" function="F" pad="PD01" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DMAC_ID_MC0" value="22"/>
+              <param name="DMAC_ID_MC1" value="23"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="11" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="33" caption="Instance index for TCC3"/>
+              <param name="MCLK_ID_APB" value="43" caption="Index for TCC3 APB clock"/>
+              <param name="PAC_ID" value="33" caption="Index for TCC3 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC4">
+            <register-group name="TCC4" name-in-module="TCC" address-space="base" offset="0x44824000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PA10" ioset="2"/>
+              <signal group="WO" index="0" function="F" pad="PD07" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PA11" ioset="2"/>
+              <signal group="WO" index="1" function="F" pad="PD08" ioset="1"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="DMAC_ID_OVF" value="28"/>
+              <param name="DMAC_ID_MC0" value="29"/>
+              <param name="DMAC_ID_MC1" value="30"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="18" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="36" caption="Instance index for TCC4"/>
+              <param name="MCLK_ID_APB" value="46" caption="Index for TCC4 APB clock"/>
+              <param name="PAC_ID" value="36" caption="Index for TCC4 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC5">
+            <register-group name="TCC5" name-in-module="TCC" address-space="base" offset="0x44826000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PD10" ioset="2"/>
+              <signal group="WO" index="0" function="F" pad="PD09" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PA00" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PD11" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="31"/>
+              <param name="DMAC_ID_OVF" value="31"/>
+              <param name="DMAC_ID_MC0" value="32"/>
+              <param name="DMAC_ID_MC1" value="33"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="19" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="37" caption="Instance index for TCC5"/>
+              <param name="MCLK_ID_APB" value="47" caption="Index for TCC5 APB clock"/>
+              <param name="PAC_ID" value="37" caption="Index for TCC5 registers write protection"/>
+            </parameters>
+          </instance>
+          <instance name="TCC6">
+            <register-group name="TCC6" name-in-module="TCC" address-space="base" offset="0x44828000"/>
+            <signals>
+              <signal group="WO" index="0" function="F" pad="PA01" ioset="1"/>
+              <signal group="WO" index="0" function="F" pad="PD12" ioset="2"/>
+              <signal group="WO" index="1" function="F" pad="PA02" ioset="1"/>
+              <signal group="WO" index="1" function="F" pad="PD13" ioset="2"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
+              <param name="DITHERING" value="0" caption="Dithering feature implemented"/>
+              <param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
+              <param name="MASTER_SLAVE_MODE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
+              <param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
+              <param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
+              <param name="PG" value="0" caption="Pattern Generation feature implemented"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
+              <param name="GCLK_ID" value="32"/>
+              <param name="DMAC_ID_OVF" value="34"/>
+              <param name="DMAC_ID_MC0" value="35"/>
+              <param name="DMAC_ID_MC1" value="36"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="20" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="38" caption="Instance index for TCC6"/>
+              <param name="MCLK_ID_APB" value="48" caption="Index for TCC6 APB clock"/>
+              <param name="PAC_ID" value="38" caption="Index for TCC6 registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TESTVAL" id="test_valio_mapper_v1" name2="test_valio_mapper_v1" version="1.0.0">
+          <instance name="TESTVAL">
+            <signals>
+              <signal group="VALIO" index="0" function="VALIO" pad="PD00"/>
+              <signal group="VALIO" index="1" function="VALIO" pad="PD01"/>
+              <signal group="VALIO" index="2" function="VALIO" pad="PC04"/>
+              <signal group="VALIO" index="3" function="VALIO" pad="PA05"/>
+              <signal group="VALIO" index="4" function="VALIO" pad="PC01"/>
+              <signal group="VALIO" index="5" function="VALIO" pad="PC02"/>
+            </signals>
+          </instance>
+        </module>
+        <module name="USB" id="03613" name2="usb_u2222_v1" version="1d0">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x44832000"/>
+            <signals>
+              <signal group="SOF" function="H" pad="PD01"/>
+              <signal group="USBDM" function="H" pad="PD02"/>
+              <signal group="USBDP" function="H" pad="PD03"/>
+            </signals>
+            <parameters>
+              <param name="AHB_2_USB_FIFO_DEPTH" value="4" caption="bytes number, should be at least 2, and 2^n (4,8,16 ...)"/>
+              <param name="AHB_2_USB_RD_DATA_BITS" value="8" caption="8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode"/>
+              <param name="AHB_2_USB_WR_DATA_BITS" value="32" caption="8, 16 or 32 : here, AHB transfer is made in word mode"/>
+              <param name="AHB_2_USB_WR_THRESHOLD" value="2" caption="as soon as there are N bytes-free inside the fifo, ahb read transfer is requested"/>
+              <param name="DATA_BUS_16_8" value="0" caption="UTMI/SIE data bus size : 0 -&gt; 8 bits, 1 -&gt; 16 bits"/>
+              <param name="EPNUM" value="8" caption="parameter for rtl : max of ENDPOINT and PIPE NUM"/>
+              <param name="EPT_NUM" value="8" caption="Number of USB end points"/>
+              <param name="INITIAL_CONTROL_QOS" value="3" caption="CONTROL QOS RESET value"/>
+              <param name="INITIAL_DATA_QOS" value="3" caption="DATA QOS RESET value"/>
+              <param name="MISSING_SOF_DET_IMPLEMENTED" value="1" caption="48 mHz xPLL feature implemented"/>
+              <param name="PIPE_NUM" value="8" caption="Number of USB pipes"/>
+              <param name="SYSTEM_CLOCK_IS_CKUSB" value="0" caption="Dual (1'b0) or Single (1'b1) clock system"/>
+              <param name="USB_2_AHB_FIFO_DEPTH" value="4" caption="bytes number, should be at least 2, and 2^n (4,8,16 ...)"/>
+              <param name="USB_2_AHB_RD_DATA_BITS" value="16" caption="8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode"/>
+              <param name="USB_2_AHB_RD_THRESHOLD" value="2" caption="as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested"/>
+              <param name="USB_2_AHB_WR_DATA_BITS" value="8" caption="8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode"/>
+              <param name="GCLK_ID" value="38"/>
+              <param name="BRIDGE_ID" value="1" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="25" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="44" caption="Instance index for USB"/>
+              <param name="MCLK_ID_AHB" value="54" caption="Index for USB AHB clock"/>
+              <param name="MCLK_ID_APB" value="55" caption="Index for USB APB clock"/>
+              <param name="PAC_ID" value="44" caption="Index for USB registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="03611" name2="wdt_u2251_v2" version="2b0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x4400E000"/>
+            <parameters>
+              <param name="FUSES_UPDATE_SUPPORT" value="0" caption="WDT Fuse Update Support"/>
+              <param name="BRIDGE_ID" value="0" caption="H2PB Bridge ID"/>
+              <param name="PERIPH_ID" value="7" caption="H2PB Peripheral ID"/>
+              <param name="INSTANCE_ID" value="11" caption="Instance index for WDT"/>
+              <param name="MCLK_ID_APB" value="11" caption="Index for WDT APB clock"/>
+              <param name="PAC_ID" value="11" caption="Index for WDT registers write protection"/>
+            </parameters>
+          </instance>
+        </module>
+      </peripherals>
+      <interrupts>
+        <interrupt name="Reset" index="-15" caption="Reset Vector, invoked on Power up and warm reset"/>
+        <interrupt name="NonMaskableInt" index="-14" caption="Non maskable Interrupt, cannot be stopped or preempted"/>
+        <interrupt name="HardFault" index="-13" caption="Hard Fault, all classes of Fault"/>
+        <interrupt name="SVCall" index="-5" caption="System Service Call via SVC instruction"/>
+        <interrupt name="PendSV" index="-2" caption="Pendable request for system service"/>
+        <interrupt name="SysTick" index="-1" caption="System Tick Timer"/>
+        <interrupt name="FCR" index="0" module-instance="FCR"/>
+        <interrupt name="FCW" index="1" module-instance="FCW"/>
+        <interrupt name="PM" index="2" module-instance="PM"/>
+        <interrupt name="SUPC" index="3" module-instance="SUPC"/>
+        <interrupt name="OSCCTRL_XOSCRDY" index="4" module-instance="OSCCTRL"/>
+        <interrupt name="OSCCTRL_DFLLRDY" index="5" module-instance="OSCCTRL"/>
+        <interrupt name="OSCCTRL_PLLLOCKR_0" index="6" module-instance="OSCCTRL"/>
+        <interrupt name="OSC32KCTRL_XOSC32KRDY" index="7" module-instance="OSC32KCTRL"/>
+        <interrupt name="OSC32KCTRL_XOSC32KFAIL" index="8" module-instance="OSC32KCTRL"/>
+        <interrupt name="MCLK" index="9" module-instance="MCLK"/>
+        <interrupt name="FREQM" index="10" module-instance="FREQM"/>
+        <interrupt name="WDT" index="11" module-instance="WDT"/>
+        <interrupt name="RTC_TAMPER" index="12" module-instance="RTC"/>
+        <interrupt name="RTC_OVF" index="13" module-instance="RTC"/>
+        <interrupt name="RTC_PER0" index="14" module-instance="RTC"/>
+        <interrupt name="RTC_CMP0" index="15" module-instance="RTC"/>
+        <interrupt name="EIC_EXTINT0" index="16" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT1" index="17" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT2" index="18" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT3" index="19" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT4" index="20" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT5" index="21" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT6" index="22" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT7" index="23" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT8" index="24" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT9" index="25" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT10" index="26" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT11" index="27" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT12" index="28" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT13" index="29" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT14" index="30" module-instance="EIC"/>
+        <interrupt name="EIC_EXTINT15" index="31" module-instance="EIC"/>
+        <interrupt name="EIC_NSCHK" index="32" module-instance="EIC"/>
+        <interrupt name="MCRAMC" index="34" module-instance="MCRAMC"/>
+        <interrupt name="CAN0_INT0" index="35" module-instance="CAN0"/>
+        <interrupt name="CAN0_INT1" index="36" module-instance="CAN0"/>
+        <interrupt name="CAN0_BERR" index="37" module-instance="CAN0"/>
+        <interrupt name="CAN1_INT0" index="38" module-instance="CAN1"/>
+        <interrupt name="CAN1_INT1" index="39" module-instance="CAN1"/>
+        <interrupt name="CAN1_BERR" index="40" module-instance="CAN1"/>
+        <interrupt name="PORT" index="41" module-instance="PORT"/>
+        <interrupt name="DMAC_TCMPL0" index="42" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL1" index="43" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL2" index="44" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL3" index="45" module-instance="DMAC"/>
+        <interrupt name="DMAC_TCMPL4" index="46" module-instance="DMAC"/>
+        <interrupt name="HMATRIX2" index="47" module-instance="HMATRIX2"/>
+        <interrupt name="EVSYS_EVD0" index="48" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD1" index="49" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD2" index="50" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD3" index="51" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD4" index="52" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD5" index="53" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD6" index="54" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD7" index="55" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD8" index="56" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD9" index="57" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD10" index="58" module-instance="EVSYS"/>
+        <interrupt name="EVSYS_EVD11" index="59" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_6" index="60" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_5" index="61" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_0" index="62" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_1" index="63" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_2" index="64" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_3" index="65" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM0_4" index="66" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_6" index="67" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_5" index="68" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_0" index="69" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_1" index="70" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_2" index="71" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_3" index="72" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM1_4" index="73" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_6" index="74" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_5" index="75" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_0" index="76" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_1" index="77" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_2" index="78" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_3" index="79" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM2_4" index="80" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_6" index="81" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_5" index="82" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_0" index="83" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_1" index="84" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_2" index="85" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_3" index="86" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM3_4" index="87" module-instance="SERCOM3"/>
+        <interrupt name="TCC0_DFS" index="88" module-instance="TCC0"/>
+        <interrupt name="TCC0_CNT" index="89" module-instance="TCC0"/>
+        <interrupt name="TCC0_MC0" index="90" module-instance="TCC0"/>
+        <interrupt name="TCC0_MC1" index="91" module-instance="TCC0"/>
+        <interrupt name="TCC1_DFS" index="92" module-instance="TCC1"/>
+        <interrupt name="TCC1_CNT" index="93" module-instance="TCC1"/>
+        <interrupt name="TCC1_MC0" index="94" module-instance="TCC1"/>
+        <interrupt name="TCC1_MC1" index="95" module-instance="TCC1"/>
+        <interrupt name="TCC2_DFS" index="96" module-instance="TCC2"/>
+        <interrupt name="TCC2_CNT" index="97" module-instance="TCC2"/>
+        <interrupt name="TCC2_MC0" index="98" module-instance="TCC2"/>
+        <interrupt name="TCC2_MC1" index="99" module-instance="TCC2"/>
+        <interrupt name="TCC3_DFS" index="100" module-instance="TCC3"/>
+        <interrupt name="TCC3_CNT" index="101" module-instance="TCC3"/>
+        <interrupt name="TCC3_MC0" index="102" module-instance="TCC3"/>
+        <interrupt name="TCC3_MC1" index="103" module-instance="TCC3"/>
+        <interrupt name="SERCOM4_6" index="104" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_5" index="105" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_0" index="106" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_1" index="107" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_2" index="108" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_3" index="109" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM4_4" index="110" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_6" index="111" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_5" index="112" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_0" index="113" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_1" index="114" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_2" index="115" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_3" index="116" module-instance="SERCOM5"/>
+        <interrupt name="SERCOM5_4" index="117" module-instance="SERCOM5"/>
+        <interrupt name="TCC4_DFS" index="118" module-instance="TCC4"/>
+        <interrupt name="TCC4_CNT" index="119" module-instance="TCC4"/>
+        <interrupt name="TCC4_MC0" index="120" module-instance="TCC4"/>
+        <interrupt name="TCC4_MC1" index="121" module-instance="TCC4"/>
+        <interrupt name="TCC5_DFS" index="122" module-instance="TCC5"/>
+        <interrupt name="TCC5_CNT" index="123" module-instance="TCC5"/>
+        <interrupt name="TCC5_MC0" index="124" module-instance="TCC5"/>
+        <interrupt name="TCC5_MC1" index="125" module-instance="TCC5"/>
+        <interrupt name="TCC6_DFS" index="126" module-instance="TCC6"/>
+        <interrupt name="TCC6_CNT" index="127" module-instance="TCC6"/>
+        <interrupt name="TCC6_MC0" index="128" module-instance="TCC6"/>
+        <interrupt name="TCC6_MC1" index="129" module-instance="TCC6"/>
+        <interrupt name="ADC_REQ0" index="130" module-instance="ADC"/>
+        <interrupt name="ADC_REQ1" index="131" module-instance="ADC"/>
+        <interrupt name="AC" index="132" module-instance="AC"/>
+        <interrupt name="PTC" index="133" module-instance="PTC"/>
+        <interrupt name="USB_EORSMDNRSM" index="134" module-instance="USB"/>
+        <interrupt name="USB_SOFHSOF" index="135" module-instance="USB"/>
+        <interrupt name="USB_TRCPT00" index="136" module-instance="USB"/>
+        <interrupt name="USB_TRCPT10" index="137" module-instance="USB"/>
+        <interrupt name="AT" index="138" module-instance="AT"/>
+      </interrupts>
+      <events>
+        <generators>
+          <generator name="SUPC_LVDET" index="1" module-instance="SUPC"/>
+          <generator name="OSCCTRL_XOSCFAIL" index="2" module-instance="OSCCTRL"/>
+          <generator name="OSC32KCTRL_XOSC32KFAIL" index="3" module-instance="OSC32KCTRL"/>
+          <generator name="FREQM_DONE" index="4" module-instance="FREQM"/>
+          <generator name="FREQM_WINMON" index="5" module-instance="FREQM"/>
+          <generator name="RTC_PER0" index="6" module-instance="RTC"/>
+          <generator name="RTC_PER1" index="7" module-instance="RTC"/>
+          <generator name="RTC_PER2" index="8" module-instance="RTC"/>
+          <generator name="RTC_PER3" index="9" module-instance="RTC"/>
+          <generator name="RTC_PER4" index="10" module-instance="RTC"/>
+          <generator name="RTC_PER5" index="11" module-instance="RTC"/>
+          <generator name="RTC_PER6" index="12" module-instance="RTC"/>
+          <generator name="RTC_PER7" index="13" module-instance="RTC"/>
+          <generator name="RTC_CMP0" index="14" module-instance="RTC"/>
+          <generator name="RTC_CMP1" index="15" module-instance="RTC"/>
+          <generator name="RTC_CMP2" index="16" module-instance="RTC"/>
+          <generator name="RTC_CMP3" index="17" module-instance="RTC"/>
+          <generator name="RTC_TAMPER" index="18" module-instance="RTC"/>
+          <generator name="RTC_OVF" index="19" module-instance="RTC"/>
+          <generator name="RTC_PERD" index="20" module-instance="RTC"/>
+          <generator name="EIC_EXTINT0" index="21" module-instance="EIC"/>
+          <generator name="EIC_EXTINT1" index="22" module-instance="EIC"/>
+          <generator name="EIC_EXTINT2" index="23" module-instance="EIC"/>
+          <generator name="EIC_EXTINT3" index="24" module-instance="EIC"/>
+          <generator name="EIC_EXTINT4" index="25" module-instance="EIC"/>
+          <generator name="EIC_EXTINT5" index="26" module-instance="EIC"/>
+          <generator name="EIC_EXTINT6" index="27" module-instance="EIC"/>
+          <generator name="EIC_EXTINT7" index="28" module-instance="EIC"/>
+          <generator name="EIC_EXTINT8" index="29" module-instance="EIC"/>
+          <generator name="EIC_EXTINT9" index="30" module-instance="EIC"/>
+          <generator name="EIC_EXTINT10" index="31" module-instance="EIC"/>
+          <generator name="EIC_EXTINT11" index="32" module-instance="EIC"/>
+          <generator name="EIC_EXTINT12" index="33" module-instance="EIC"/>
+          <generator name="EIC_EXTINT13" index="34" module-instance="EIC"/>
+          <generator name="EIC_EXTINT14" index="35" module-instance="EIC"/>
+          <generator name="EIC_EXTINT15" index="36" module-instance="EIC"/>
+          <generator name="DMAC_CH0" index="37" module-instance="DMAC"/>
+          <generator name="DMAC_CH1" index="38" module-instance="DMAC"/>
+          <generator name="DMAC_CH2" index="39" module-instance="DMAC"/>
+          <generator name="DMAC_CH3" index="40" module-instance="DMAC"/>
+          <generator name="TCC0_OVF" index="41" module-instance="TCC0"/>
+          <generator name="TCC0_TRG" index="42" module-instance="TCC0"/>
+          <generator name="TCC0_CNT" index="43" module-instance="TCC0"/>
+          <generator name="TCC0_MC0" index="44" module-instance="TCC0"/>
+          <generator name="TCC0_MC1" index="45" module-instance="TCC0"/>
+          <generator name="TCC1_OVF" index="46" module-instance="TCC1"/>
+          <generator name="TCC1_TRG" index="47" module-instance="TCC1"/>
+          <generator name="TCC1_CNT" index="48" module-instance="TCC1"/>
+          <generator name="TCC1_MC0" index="49" module-instance="TCC1"/>
+          <generator name="TCC1_MC1" index="50" module-instance="TCC1"/>
+          <generator name="TCC2_OVF" index="51" module-instance="TCC2"/>
+          <generator name="TCC2_TRG" index="52" module-instance="TCC2"/>
+          <generator name="TCC2_CNT" index="53" module-instance="TCC2"/>
+          <generator name="TCC2_MC0" index="54" module-instance="TCC2"/>
+          <generator name="TCC2_MC1" index="55" module-instance="TCC2"/>
+          <generator name="TCC3_OVF" index="56" module-instance="TCC3"/>
+          <generator name="TCC3_TRG" index="57" module-instance="TCC3"/>
+          <generator name="TCC3_CNT" index="58" module-instance="TCC3"/>
+          <generator name="TCC3_MC0" index="59" module-instance="TCC3"/>
+          <generator name="TCC3_MC1" index="60" module-instance="TCC3"/>
+          <generator name="TCC4_OVF" index="61" module-instance="TCC4"/>
+          <generator name="TCC4_TRG" index="62" module-instance="TCC4"/>
+          <generator name="TCC4_CNT" index="63" module-instance="TCC4"/>
+          <generator name="TCC4_MC0" index="64" module-instance="TCC4"/>
+          <generator name="TCC4_MC1" index="65" module-instance="TCC4"/>
+          <generator name="TCC5_OVF" index="66" module-instance="TCC5"/>
+          <generator name="TCC5_TRG" index="67" module-instance="TCC5"/>
+          <generator name="TCC5_CNT" index="68" module-instance="TCC5"/>
+          <generator name="TCC5_MC0" index="69" module-instance="TCC5"/>
+          <generator name="TCC5_MC1" index="70" module-instance="TCC5"/>
+          <generator name="TCC6_OVF" index="71" module-instance="TCC6"/>
+          <generator name="TCC6_TRG" index="72" module-instance="TCC6"/>
+          <generator name="TCC6_CNT" index="73" module-instance="TCC6"/>
+          <generator name="TCC6_MC0" index="74" module-instance="TCC6"/>
+          <generator name="TCC6_MC1" index="75" module-instance="TCC6"/>
+          <generator name="ADC_CHRDY" index="76" module-instance="ADC"/>
+          <generator name="ADC_CMP" index="77" module-instance="ADC"/>
+          <generator name="AC_COMP0" index="78" module-instance="AC"/>
+          <generator name="AC_COMP1" index="79" module-instance="AC"/>
+          <generator name="AC_WIN0" index="80" module-instance="AC"/>
+          <generator name="PTC_EOC" index="81" module-instance="PTC"/>
+          <generator name="PTC_WCOMP" index="82" module-instance="PTC"/>
+          <generator name="CCL0_LUTOUT0" index="83" module-instance="CCL0"/>
+          <generator name="CCL0_LUTOUT1" index="84" module-instance="CCL0"/>
+          <generator name="CCL0_LUTOUT2" index="85" module-instance="CCL0"/>
+          <generator name="CCL0_LUTOUT3" index="86" module-instance="CCL0"/>
+          <generator name="CCL1_LUTOUT0" index="87" module-instance="CCL1"/>
+          <generator name="CCL1_LUTOUT1" index="88" module-instance="CCL1"/>
+          <generator name="CCL1_LUTOUT2" index="89" module-instance="CCL1"/>
+          <generator name="CCL1_LUTOUT3" index="90" module-instance="CCL1"/>
+        </generators>
+        <users>
+          <user name="FREQM_START" index="0" module-instance="FREQM"/>
+          <user name="RTC_TAMPER" index="1" module-instance="RTC"/>
+          <user name="PORT_EV0" index="2" module-instance="PORT"/>
+          <user name="PORT_EV1" index="3" module-instance="PORT"/>
+          <user name="PORT_EV2" index="4" module-instance="PORT"/>
+          <user name="PORT_EV3" index="5" module-instance="PORT"/>
+          <user name="DMAC_CH0" index="6" module-instance="DMAC"/>
+          <user name="DMAC_CH1" index="7" module-instance="DMAC"/>
+          <user name="DMAC_CH2" index="8" module-instance="DMAC"/>
+          <user name="DMAC_CH3" index="9" module-instance="DMAC"/>
+          <user name="TCC0_EV0" index="10" module-instance="TCC0"/>
+          <user name="TCC0_EV1" index="11" module-instance="TCC0"/>
+          <user name="TCC0_MC0" index="12" module-instance="TCC0"/>
+          <user name="TCC0_MC1" index="13" module-instance="TCC0"/>
+          <user name="TCC1_EV0" index="14" module-instance="TCC1"/>
+          <user name="TCC1_EV1" index="15" module-instance="TCC1"/>
+          <user name="TCC1_MC0" index="16" module-instance="TCC1"/>
+          <user name="TCC1_MC1" index="17" module-instance="TCC1"/>
+          <user name="TCC2_EV0" index="18" module-instance="TCC2"/>
+          <user name="TCC2_EV1" index="19" module-instance="TCC2"/>
+          <user name="TCC2_MC0" index="20" module-instance="TCC2"/>
+          <user name="TCC2_MC1" index="21" module-instance="TCC2"/>
+          <user name="TCC3_EV0" index="22" module-instance="TCC3"/>
+          <user name="TCC3_EV1" index="23" module-instance="TCC3"/>
+          <user name="TCC3_MC0" index="24" module-instance="TCC3"/>
+          <user name="TCC3_MC1" index="25" module-instance="TCC3"/>
+          <user name="TCC4_EV0" index="26" module-instance="TCC4"/>
+          <user name="TCC4_EV1" index="27" module-instance="TCC4"/>
+          <user name="TCC4_MC0" index="28" module-instance="TCC4"/>
+          <user name="TCC4_MC1" index="29" module-instance="TCC4"/>
+          <user name="TCC5_EV0" index="30" module-instance="TCC5"/>
+          <user name="TCC5_EV1" index="31" module-instance="TCC5"/>
+          <user name="TCC5_MC0" index="32" module-instance="TCC5"/>
+          <user name="TCC5_MC1" index="33" module-instance="TCC5"/>
+          <user name="TCC6_EV0" index="34" module-instance="TCC6"/>
+          <user name="TCC6_EV1" index="35" module-instance="TCC6"/>
+          <user name="TCC6_MC0" index="36" module-instance="TCC6"/>
+          <user name="TCC6_MC1" index="37" module-instance="TCC6"/>
+          <user name="ADC_TRIG0" index="38" module-instance="ADC"/>
+          <user name="ADC_TRIG1" index="39" module-instance="ADC"/>
+          <user name="ADC_TRIG2" index="40" module-instance="ADC"/>
+          <user name="ADC_TRIG3" index="41" module-instance="ADC"/>
+          <user name="ADC_TRIG4" index="42" module-instance="ADC"/>
+          <user name="ADC_TRIG5" index="43" module-instance="ADC"/>
+          <user name="ADC_TRIG6" index="44" module-instance="ADC"/>
+          <user name="ADC_TRIG7" index="45" module-instance="ADC"/>
+          <user name="ADC_TRIG8" index="46" module-instance="ADC"/>
+          <user name="ADC_TRIG9" index="47" module-instance="ADC"/>
+          <user name="ADC_TRIG10" index="48" module-instance="ADC"/>
+          <user name="AC_SOC0" index="49" module-instance="AC"/>
+          <user name="AC_SOC1" index="50" module-instance="AC"/>
+          <user name="PTC_DSEQR" index="51" module-instance="PTC"/>
+          <user name="PTC_STCONV" index="52" module-instance="PTC"/>
+          <user name="CCL0_LUTIN0" index="53" module-instance="CCL0"/>
+          <user name="CCL0_LUTIN1" index="54" module-instance="CCL0"/>
+          <user name="CCL0_LUTIN2" index="55" module-instance="CCL0"/>
+          <user name="CCL0_LUTIN3" index="56" module-instance="CCL0"/>
+          <user name="CCL1_LUTIN0" index="57" module-instance="CCL1"/>
+          <user name="CCL1_LUTIN1" index="58" module-instance="CCL1"/>
+          <user name="CCL1_LUTIN2" index="59" module-instance="CCL1"/>
+          <user name="CCL1_LUTIN3" index="60" module-instance="CCL1"/>
+          <user name="AT_TAMPSRC5" index="61" module-instance="AT"/>
+        </users>
+      </events>
+      <interfaces>
+        <interface name="JTAG" type="samjtag"/>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x0AC00053"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="03784" name2="cmp_ac_u2501_v2" version="2a0" caption="Analog Comparator Controller">
+      <register-group name="CHANNEL" size="0x10">
+        <register name="COMPCTRL" offset="0x0" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Pair n Comparator Control 0">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x8"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x30" values="COMPCTRL__INTSEL"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x7000" values="COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x10000"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0x20000" values="COMPCTRL__SPEED"/>
+          <bitfield name="HYST" caption="Hysteresis Level" mask="0x180000" values="COMPCTRL__HYST"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0xE00000" values="COMPCTRL__FLEN"/>
+          <bitfield name="OUT" caption="Output" mask="0x3000000" values="COMPCTRL__OUT"/>
+          <bitfield name="SUT" caption="Start-up Time" mask="0xFC000000"/>
+        </register>
+        <register name="DACCTRL" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Dac n Control">
+          <bitfield name="VALUE0" caption="DAC0 Output Value" mask="0x7F"/>
+          <bitfield name="SHEN0" caption="DAC0 Sample and Hold Enable Operating Mode" mask="0x8000"/>
+          <bitfield name="VALUE1" caption="DAC1 Output Value" mask="0x7F0000"/>
+          <bitfield name="SHEN1" caption="DAC1 Sample and Hold Enable Operating Mode" mask="0x80000000"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Window Monitor  n Control">
+          <bitfield name="WEN" caption="Window n Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL" caption="Window n Interrupt Selection" mask="0x6" values="WINCTRL__WINTSEL"/>
+        </register>
+      </register-group>
+      <register-group name="AC" caption="Analog Comparator Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Control C">
+          <bitfield name="WIDTH" caption="Sample and Hold Clock Pulse Width" mask="0x3FF"/>
+          <bitfield name="PER" caption="Sample and Hold Clock Period" mask="0x3FF000"/>
+          <bitfield name="PRESCALER" caption="Prescaling Factor" mask="0x7000000" values="CTRLC__PRESCALER"/>
+          <bitfield name="AIPMPEN" caption="Analog Input Charge Pump Enable" mask="0x8000000"/>
+          <bitfield name="CONFIG" caption="Configuration Extension" mask="0xF0000000"/>
+        </register>
+        <register name="EVCTRL" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="INVEI0" caption="Inverted Event Input Enable 0" mask="0x1000000"/>
+          <bitfield name="INVEI1" caption="Inverted Event Input Enable 1" mask="0x2000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x100"/>
+        </register>
+        <register name="STATUSA" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30000" values="STATUSA__WSTATE"/>
+        </register>
+        <register name="STATUSB" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="COMPCTRL0" caption="COMPCTRL 0 Synchronization Busy" mask="0x4"/>
+          <bitfield name="COMPCTRL1" caption="COMPCTRL 1 Synchronization Busy" mask="0x8"/>
+          <bitfield name="WINCTRL0" caption="WINCTRL 0 Synchronization Busy" mask="0x400"/>
+        </register>
+        <register-group name="CHANNEL" name-in-module="CHANNEL" offset="0x30" size="0x10" count="1"/>
+      </register-group>
+      <value-group name="COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="INT0" caption="Internal connection 0, device specific" value="4"/>
+        <value name="BANDGAP" caption="Bangap" value="5"/>
+        <value name="GND" caption="Ground" value="6"/>
+        <value name="INTDAC" caption="Internal DAC" value="7"/>
+      </value-group>
+      <value-group name="COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="INT0" caption="Internal connection 0, device specific" value="4"/>
+        <value name="INT1" caption="Internal connection 1, device specific" value="5"/>
+        <value name="INT2" caption="Internal connection 2, device specific" value="6"/>
+        <value name="INTDAC" caption="Internal DAC" value="7"/>
+      </value-group>
+      <value-group name="COMPCTRL__SPEED">
+        <value name="HIGH" caption="High speed, high power" value="0"/>
+        <value name="LOW" caption="Low speed, low power" value="1"/>
+      </value-group>
+      <value-group name="COMPCTRL__HYST">
+        <value name="HYST10" caption="10mV" value="0"/>
+        <value name="HYST20" caption="20mV" value="1"/>
+        <value name="HYST40" caption="40mV" value="2"/>
+        <value name="HYST60" caption="60mV" value="3"/>
+      </value-group>
+      <value-group name="COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="WINCTRL__WINTSEL">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="CTRLC__PRESCALER">
+        <value name="DIV1" caption="Sampling rate is GCLK_AC (No division)" value="0x0"/>
+        <value name="DIV2" caption="Sampling rate is GCLK_AC/2" value="0x1"/>
+        <value name="DIV4" caption="Sampling rate is GCLK_AC/4" value="0x2"/>
+        <value name="DIV8" caption="Sampling rate is GCLK_AC/8" value="0x3"/>
+        <value name="DIV16" caption="Sampling rate is GCLK_AC/16" value="0x4"/>
+        <value name="DIV32" caption="Sampling rate is GCLK_AC/32" value="0x5"/>
+        <value name="DIV64" caption="Sampling rate is GCLK_AC/64" value="0x6"/>
+        <value name="DIV128" caption="Sampling rate is GCLK_AC/128" value="0x7"/>
+      </value-group>
+      <value-group name="STATUSA__WSTATE">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="03620" name2="adc_msh_ctrl_apb_v1" version="1b0" caption="ADC Controller">
+      <register-group name="CONFIG" size="0x20">
+        <register name="CORCTRL" offset="0x0" rw="RW" size="4" initval="0x00000C00" caption="SARCORE Control">
+          <bitfield name="SAMC" caption="Sample Count" mask="0x3FF"/>
+          <bitfield name="SELRES" caption="Selects Resolution" mask="0xC00" values="CORCTRL__SELRES"/>
+          <bitfield name="EIS" caption="Early Interrupt Select" mask="0x7000"/>
+          <bitfield name="EIRQOVR" caption="Interrupt Type Select" mask="0x8000"/>
+          <bitfield name="STRGSRC" caption="SCAN trigger source selection" mask="0xF0000" values="CORCTRL__STRGSRC"/>
+          <bitfield name="STRGLVL" caption="Scan Trigger Level Sensitivity" mask="0x200000"/>
+          <bitfield name="SCNRTDS" caption="SCAN Re-trigger Disable" mask="0x400000"/>
+          <bitfield name="ADCDIV" caption="Division Ratio for SARCORE clock" mask="0x7F000000"/>
+        </register>
+        <register name="CHNCFG1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 1 (LVL/CMPEN)">
+          <bitfield name="CHNCMPEN" caption="Channel Comparator Enable" mask="0xFFFF"/>
+          <bitfield name="LVL" caption="Channel Level" mask="0xFFFF0000"/>
+        </register>
+        <register name="CHNCFG2" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 2(FRACT/CSS)">
+          <bitfield name="CSS" caption="Channel SCAN Select" mask="0xFFFF"/>
+          <bitfield name="FRACT" caption="Channel Fractional" mask="0xFFFF0000"/>
+        </register>
+        <register name="CHNCFG3" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration3 (SIGN/DIFF)">
+          <bitfield name="DIFF" caption="Differential Mode" mask="0xFFFF"/>
+          <bitfield name="SIGN" caption="SIGN setting" mask="0xFFFF0000"/>
+        </register>
+        <register name="CHNCFG4" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 4 (TRGSRC)">
+          <bitfield name="TRGSRC0" caption="Channel 0 Trigger Source" mask="0xF" values="CHNCFG4__TRGSRC0"/>
+          <bitfield name="TRGSRC1" caption="Channel 1 Trigger Source" mask="0xF0" values="CHNCFG4__TRGSRC1"/>
+          <bitfield name="TRGSRC2" caption="Channel 2 Trigger Source" mask="0xF00" values="CHNCFG4__TRGSRC2"/>
+          <bitfield name="TRGSRC3" caption="Channel 3 Trigger Source" mask="0xF000" values="CHNCFG4__TRGSRC3"/>
+          <bitfield name="TRGSRC4" caption="Channel 4 Trigger Source" mask="0xF0000" values="CHNCFG4__TRGSRC4"/>
+          <bitfield name="TRGSRC5" caption="Channel 5 Trigger Source" mask="0xF00000" values="CHNCFG4__TRGSRC5"/>
+          <bitfield name="TRGSRC6" caption="Channel 6 Trigger Source" mask="0xF000000" values="CHNCFG4__TRGSRC6"/>
+          <bitfield name="TRGSRC7" caption="Channel 7 Trigger Source" mask="0xF0000000" values="CHNCFG4__TRGSRC7"/>
+        </register>
+        <register name="CHNCFG5" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Channel Configuration 5 (TRGSRC)">
+          <bitfield name="TRGSRC8" caption="Channel 8 Trigger Source" mask="0xF" values="CHNCFG5__TRGSRC8"/>
+          <bitfield name="TRGSRC9" caption="Channel 9 Trigger Source" mask="0xF0" values="CHNCFG5__TRGSRC9"/>
+          <bitfield name="TRGSRC10" caption="Channel 10 Trigger Source" mask="0xF00" values="CHNCFG5__TRGSRC10"/>
+          <bitfield name="TRGSRC11" caption="Channel 11 Trigger Source" mask="0xF000" values="CHNCFG5__TRGSRC11"/>
+          <bitfield name="TRGSRC12" caption="Channel 12 Trigger Source" mask="0xF0000" values="CHNCFG5__TRGSRC12"/>
+          <bitfield name="TRGSRC13" caption="Channel 13 Trigger Source" mask="0xF00000" values="CHNCFG5__TRGSRC13"/>
+          <bitfield name="TRGSRC14" caption="Channel 14 Trigger Source" mask="0xF000000" values="CHNCFG5__TRGSRC14"/>
+          <bitfield name="TRGSRC15" caption="Channel 15 Trigger Source" mask="0xF0000000" values="CHNCFG5__TRGSRC15"/>
+        </register>
+        <register name="CALCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="SARCORE Calibration Value">
+          <mode name="DEFAULT"/>
+          <mode name="FUSES_ADC_SARCORE_12BIT_V7A0"/>
+          <mode name="FUSES_ADC_SARCORE_12BIT_V7C0"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_cmbf" caption="Enable Common Mode Buffer" mask="0x1"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_dither" caption="Enable Dither" mask="0x4"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dis_faz" caption="Disable auto-zeroing" mask="0x8"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dis_saz" caption="Disable auto-zeroing" mask="0x10"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dis_laz" caption="Disable auto-zeroing" mask="0x20"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_rdac" caption="Disable Power Cycling" mask="0x40"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="dbg_sel" caption="Debug Bus Select" mask="0x80"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="sel_del" caption="Scan Mode comp_out" mask="0x100"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="t1_dly" caption="Regen Latch Delay" mask="0x600"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="tclk_div" caption="Test Clock Divider" mask="0xF800"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="iadc_1" caption="Current Consumption 1" mask="0x300000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="iadc_2" caption="Current Consumption 2" mask="0xC00000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="icmp_1" caption="Bias Current Stage 1" mask="0x3000000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="icmp_2" caption="Bias Current Stage 2" mask="0xC000000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="icmbf" caption="Bias Current Common Mode Buffer" mask="0x30000000"/>
+          <bitfield modes="FUSES_ADC_SARCORE_12BIT_V7A0 FUSES_ADC_SARCORE_12BIT_V7C0" name="en_ext_bias" caption="Dsiable Internal Bias Circuit" mask="0x80000000"/>
+          <bitfield modes="DEFAULT" name="CALBITS" caption="Calibration Values" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="EVCTRL" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Event conversion input enable" mask="0x1"/>
+          <bitfield name="STARTINV" caption="Start Conversion Invert" mask="0x8"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="CMPEO" caption="Comparator Window Event Out" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group name="INT" size="0x10">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="CMPHIT" caption="Compare Hit Disable" mask="0x10"/>
+          <bitfield name="SOVFL" caption="Synchonizer Overflow Disable" mask="0x80"/>
+          <bitfield name="CHRDYC" caption="Core Current Channel Disable" mask="0x100"/>
+          <bitfield name="FLTRDY" caption="Filter Ready Disable" mask="0x200"/>
+          <bitfield name="CHNERRC" caption="Channel Overwrite Error Disable" mask="0x400"/>
+          <bitfield name="EOSRDY" caption="Endo of Scan Disable" mask="0x800"/>
+          <bitfield name="CHRDY" caption="Channel Ready Disable" mask="0xFFFF0000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="CMPHIT" caption="Compare Hit Enable" mask="0x10"/>
+          <bitfield name="SOVFL" caption="Synchronizer Overflow Enable" mask="0x80"/>
+          <bitfield name="CHRDYC" caption="Current Channel Ready Enable" mask="0x100"/>
+          <bitfield name="FLTRDY" caption="Filter Ready Enable" mask="0x200"/>
+          <bitfield name="CHNERRC" caption="Channel Overwrite Enable" mask="0x400"/>
+          <bitfield name="EOSRDY" caption="End of Scan Enable" mask="0x800"/>
+          <bitfield name="CHRDY" caption="Channel Ready Enable" mask="0xFFFF0000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flags">
+          <bitfield name="CMPINTID" caption="Compare Channel ID" mask="0xF"/>
+          <bitfield name="CMPHIT" caption="Compare Hit" mask="0x10"/>
+          <bitfield name="SOVFL" caption="Synchronizer Overflow" mask="0x80"/>
+          <bitfield name="CHRDYC" caption="Current Channel Ready" mask="0x100"/>
+          <bitfield name="FLTRDY" caption="Filter Ready" mask="0x200"/>
+          <bitfield name="CHNERRC" caption="Channel Overwrite Error" mask="0x400"/>
+          <bitfield name="EOSRDY" caption="End of Scan Ready" mask="0x800"/>
+          <bitfield name="CRDYID" caption="Channel Ready ID" mask="0xF000"/>
+          <bitfield name="CHRDY" caption="Channel Ready" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+      <register-group name="ADC" caption="ADC Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000080" caption="CONTROL A REGISTER">
+          <bitfield name="SWRST" caption="SOFTWARE RESET BIT" mask="0x1"/>
+          <bitfield name="ENABLE" caption="ENABLE BIT" mask="0x2"/>
+          <bitfield name="ANAEN" caption="Analog Enable" mask="0x4"/>
+          <bitfield name="AIPMPEN" caption="Charge Pump Enable" mask="0x10"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL B REGISTER">
+          <bitfield name="ADCHSEL" caption="Software Trigger Channel Select" mask="0xF"/>
+          <bitfield name="ADCORSEL" caption="Software Trigger Core Select" mask="0x30"/>
+          <bitfield name="RQCNVRT" caption="Request Channel Convert" mask="0x40"/>
+          <bitfield name="SAMP" caption="Channel Sample" mask="0x80"/>
+          <bitfield name="GSWTRG" caption="Global Software Trigger" mask="0x100"/>
+          <bitfield name="LSWTRG" caption="Level Global Trigger" mask="0x200"/>
+          <bitfield name="TRGSUSP" caption="Trigger Suspend" mask="0x400"/>
+          <bitfield name="STRGEN" caption="Synchronous Trigger Enable" mask="0x800"/>
+          <bitfield name="SWCNVEN" caption="Software Conversion Enable" mask="0x8000"/>
+        </register>
+        <register name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Control C Register">
+          <bitfield name="CNT" caption="Clock Divider for Synchronous Trigger" mask="0xFFFF"/>
+          <bitfield name="COREINTERLEAVED" caption="Number of Core to Interleave Triggers" mask="0x70000000"/>
+        </register>
+        <register name="CTRLD" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Control D Register">
+          <bitfield name="CTLCKDIV" caption="Control Clock Divider" mask="0x3F00"/>
+          <bitfield name="CHNEN0" caption="Core 0 Digital Channel Enable" mask="0x10000"/>
+          <bitfield name="ANLEN0" caption="Analog and Bias circuitry Enable for core 0" mask="0x100000"/>
+          <bitfield name="WKUPEXP" caption="Wakeup cycles" mask="0xF000000"/>
+          <bitfield name="VREFSEL" caption="Voltage Reference Select" mask="0x70000000" values="CTRLD__VREFSEL"/>
+        </register>
+        <register-group name="CONFIG" name-in-module="CONFIG" offset="0x020" size="0x20" count="1"/>
+        <register name="CMPCTRL" offset="0xB0" rw="RW" size="4" initval="0x00000000" caption="Comparator Control">
+          <bitfield name="ADCMPLO" caption="Low Limit of Digital Comparator" mask="0xFFF"/>
+          <bitfield name="CMPEN" caption="Comparator Enable" mask="0x1000"/>
+          <bitfield name="IELOLO" caption="Enable VAL &lt; CMPLO" mask="0x2000"/>
+          <bitfield name="IELOHI" caption="Enable VAL &gt;= CMPLO" mask="0x4000"/>
+          <bitfield name="IEBTWN" caption="Enable CMPLO &lt;= VAL &lt; CMPHI" mask="0x8000"/>
+          <bitfield name="ADCMPHI" caption="High Limit of Digital Comparator" mask="0xFFF0000"/>
+          <bitfield name="IEHILO" caption="Enable VAL &lt; CMPHI" mask="0x10000000"/>
+          <bitfield name="IEHIHI" caption="Enable VAL &gt;= CMPHI" mask="0x20000000"/>
+        </register>
+        <register name="FLTCTRL" offset="0xC0" rw="RW" size="4" initval="0x00000000" caption="Filter Control">
+          <bitfield name="OVRSAM" caption="Oversampling Ratio" mask="0x7" values="FLTCTRL__OVRSAM"/>
+          <bitfield name="FMODE" caption="Filter Mode" mask="0x8"/>
+          <bitfield name="DATA16EN" caption="16bit Averaging Mode" mask="0x10"/>
+          <bitfield name="FLTEN" caption="Filter Enable" mask="0x100"/>
+          <bitfield name="FLTCHNID" caption="Channel ID" mask="0x3C00"/>
+        </register>
+        <register name="CORCHDATAID" offset="0xD0" rw="RW" size="4" initval="0x00000000" caption="Channel Ready DATA ID">
+          <bitfield name="CHRDYID" caption="Channel Read ID" mask="0xF"/>
+          <bitfield name="CORDYID" caption="Core Read ID" mask="0x30"/>
+        </register>
+        <register name="CHRDYDAT" offset="0xD4" rw="RW" size="4" initval="0x00000000" caption="Channel Ready Data Register">
+          <bitfield name="CHRDYDAT" caption="Channel Output Data" mask="0xFFFF"/>
+          <bitfield name="LVL" caption="Level Setting" mask="0x1000000"/>
+          <bitfield name="DIFF" caption="Differential Setting" mask="0x2000000"/>
+          <bitfield name="SIGN" caption="Sign Setting" mask="0x4000000"/>
+          <bitfield name="FRACT" caption="Fractional Setting" mask="0x8000000"/>
+        </register>
+        <register name="PFFDATA" offset="0xD8" rw="R" size="4" initval="0x00000000" caption="APB FIFO Output Data">
+          <bitfield name="PFFDATA" caption="SARCORE Conversion data from the APB FIFO" mask="0xFFFF"/>
+          <bitfield name="PFFCHNID" caption="Channel ID from APB FIFO" mask="0xF0000"/>
+          <bitfield name="PFFCORID" caption="Core ID from APB FIFO" mask="0x300000"/>
+          <bitfield name="PFFSIGN" caption="Channel Sign from the APB FIFO" mask="0x400000"/>
+          <bitfield name="PFFFRACT" caption="Fractional Setting from APB FIFO" mask="0x800000"/>
+          <bitfield name="PFFCNT" caption="Current Data Entries in APB FIFO" mask="0xFF000000"/>
+        </register>
+        <register name="DMABASE" offset="0xDC" rw="RW" size="4" initval="0x00000000" caption="DMA Sample Base Address">
+          <bitfield name="DMABASE" caption="DMA Sample Value Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DMACTRL" offset="0xE0" rw="RW" size="4" initval="0x00000000" caption="DMA Control Register">
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="DMACR0" caption="DMA CORE0 Enable" mask="0x10"/>
+          <bitfield name="DMABL" caption="DMA System RAM Buffer Length" mask="0x700"/>
+        </register>
+        <register name="PFFCTRL" offset="0xE4" rw="RW" size="4" initval="0x00000000" caption="APB FIFO Control Register">
+          <bitfield name="PFFEN" caption="APB FIFO Enable" mask="0x2"/>
+          <bitfield name="PFFCR0" caption="APB CORE 0 FIFO Enable" mask="0x10"/>
+          <bitfield name="PFFRDYDM" caption="DMA APB FIFO Data Ready" mask="0x10000" values="PFFCTRL__PFFRDYDM"/>
+        </register>
+        <register name="SYNCBUSY" offset="0xE8" rw="R" size="4" initval="0x00000000" caption="CORE SYNC Busy Status Register">
+          <bitfield name="SWRST" caption="Software Reset Sync Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable bit Sync Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB sync busy" mask="0x4"/>
+        </register>
+        <register name="DMAINTENCLR" offset="0xF0" rw="RW" size="4" atomic-op="clear:DMAINTENCLR" initval="0x00000000" caption="DMA Interrupt Enable Clear">
+          <bitfield name="RAF" caption="Ram Buffer A Full" mask="0xF"/>
+          <bitfield name="RBF" caption="Ram Buffer B Full" mask="0xF0"/>
+          <bitfield name="SOVFL" caption="Synchonizer Overflow" mask="0x10000"/>
+        </register>
+        <register name="DMAINTSET" offset="0xF4" rw="RW" size="4" atomic-op="set:DMAINTSET" initval="0x00000000" caption="DMA Interrupt Enable Set">
+          <bitfield name="RAF" caption="Ram Buffer A Full" mask="0xF"/>
+          <bitfield name="RBF" caption="Ram Buffer B Full" mask="0xF0"/>
+          <bitfield name="SOVFL" caption="Synchonizer Overflow" mask="0x10000"/>
+        </register>
+        <register name="DMAINTFLAG" offset="0xF8" rw="RW" size="4" atomic-op="clear:DMAINTFLAG" initval="0x00000000" caption="DMA Interrupt Flag and Status">
+          <bitfield name="RAF" caption="Ram Buffer A Full" mask="0xF"/>
+          <bitfield name="RBF" caption="Ram Buffer B Full" mask="0xF0"/>
+          <bitfield name="EAF" caption="Ram Buffer A Overflow Error" mask="0xF00"/>
+          <bitfield name="EBF" caption="Ram Buffer B Overflow Error" mask="0xF000"/>
+          <bitfield name="SOVFL" caption="Synchronizer overflow" mask="0x10000"/>
+          <bitfield name="DMAERR" caption="DMA Bus Error" mask="0x20000"/>
+        </register>
+        <register name="CTLINTENSET" offset="0xFC" rw="RW" size="4" atomic-op="set:CTLINTENSET" initval="0x00000000" caption="CORE Controller Interrupt Enable Set">
+          <bitfield name="CRRDY0" caption="Core 0 Ready" mask="0x1"/>
+          <bitfield name="VREFUPD" caption="VREF update" mask="0x40"/>
+          <bitfield name="VREFRDY" caption="VREF Ready" mask="0x80"/>
+          <bitfield name="PFFUNF" caption="APB FIFO Underflow" mask="0x100"/>
+          <bitfield name="PFFOVF" caption="APB FIFO Overflow" mask="0x200"/>
+          <bitfield name="PFFRDY" caption="APB FIFO Ready" mask="0x400"/>
+          <bitfield name="PFFHFUL" caption="APB FIFO Half Full" mask="0x800"/>
+        </register>
+        <register name="CTLINTENCLR" offset="0x100" rw="RW" size="4" atomic-op="clear:CTLINTENCLR" initval="0x00000000" caption="CORE Controller Interrupt Enable Clear">
+          <bitfield name="CRRDY0" caption="Core Ready 0 Disable" mask="0x1"/>
+          <bitfield name="VREFUPD" caption="VREF Update" mask="0x40"/>
+          <bitfield name="VREFRDY" caption="VREF Ready" mask="0x80"/>
+          <bitfield name="PFFUNF" caption="APB FIFO underflow" mask="0x100"/>
+          <bitfield name="PFFOVF" caption="APB FIFO overflow" mask="0x200"/>
+          <bitfield name="PFFRDY" caption="APB FIFO Ready" mask="0x400"/>
+          <bitfield name="PFFHFUL" caption="APB FIFO Half Full" mask="0x800"/>
+        </register>
+        <register name="CTLINTFLAG" offset="0x104" rw="RW" size="4" atomic-op="clear:CTLINTFLAG" initval="0x00000000" caption="CORE Controller Interrupt Flags">
+          <bitfield name="CRRDY" caption="Core Ready" mask="0xF"/>
+          <bitfield name="VREFUPD" caption="VREF update" mask="0x40"/>
+          <bitfield name="VREFRDY" caption="VREF Ready" mask="0x80"/>
+          <bitfield name="PFFUNF" caption="APB FIFO underflow" mask="0x100"/>
+          <bitfield name="PFFOVF" caption="APB FIFO overflow" mask="0x200"/>
+          <bitfield name="PFFRDY" caption="APB FIFO Ready" mask="0x400"/>
+          <bitfield name="PFFHFUL" caption="APB FIFO Half Full" mask="0x800"/>
+        </register>
+        <register-group name="INT" name-in-module="INT" offset="0x120" size="0x10" count="1"/>
+        <register name="DBGCTRL" offset="0x168" rw="RW" size="4" initval="0x00000000" caption="Debug Control Register">
+          <bitfield name="DBGRUN" caption="Debug Running State" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="CORCTRL__SELRES">
+        <value name="6_BITS" caption="6 bits" value="0"/>
+        <value name="8_BITS" caption="8 bits" value="1"/>
+        <value name="10_BITS" caption="10 bits" value="2"/>
+        <value name="12_BITS" caption="12 bits (power-on default)" value="3"/>
+      </value-group>
+      <value-group name="CORCTRL__STRGSRC">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC0">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC1">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC2">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC3">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC4">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC5">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC6">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG4__TRGSRC7">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC8">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC9">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC10">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC11">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC12">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC13">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC14">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CHNCFG5__TRGSRC15">
+        <value name="NO_TRIGGER" caption="No Trigger (NOP)" value="0"/>
+        <value name="GLOBAL_SOFTWARE_TRIGGER" caption="Global Software Trigger" value="1"/>
+        <value name="GLOBAL_LEVEL_TRIGGER" caption="Global Level Software Trigger" value="2"/>
+        <value name="SCAN_TRIGGER" caption="SCANTRG - Scan Trigger" value="3"/>
+        <value name="SYNC_TRIGGER" caption="Synchronous Trigger (STRIG)" value="4"/>
+        <value name="EVENT_USER0" caption="ADC Trigger Event User 0" value="5"/>
+        <value name="EVENT_USER1" caption="ADC Trigger Event User 1" value="6"/>
+        <value name="EVENT_USER2" caption="ADC Trigger Event User 2" value="7"/>
+        <value name="EVENT_USER3" caption="ADC Trigger Event User 3" value="8"/>
+        <value name="EVENT_USER4" caption="ADC Trigger Event User 4" value="9"/>
+        <value name="EVENT_USER5" caption="ADC Trigger Event User 5" value="10"/>
+        <value name="EVENT_USER6" caption="ADC Trigger Event User 6" value="11"/>
+        <value name="EVENT_USER7" caption="ADC Trigger Event User 7" value="12"/>
+        <value name="EVENT_USER8" caption="ADC Trigger Event User 8" value="13"/>
+        <value name="EVENT_USER9" caption="ADC Trigger Event User 9" value="14"/>
+        <value name="EVENT_USER10" caption="ADC Trigger Event User 10" value="15"/>
+      </value-group>
+      <value-group name="CTRLD__VREFSEL">
+        <value name="AVDD_AVSS" caption="AVDD and AVSS" value="0"/>
+        <value name="EXTERNAL_VREFH_AVSS" caption="External VREFH and AVSS" value="1"/>
+      </value-group>
+      <value-group name="FLTCTRL__OVRSAM">
+        <value name="4_SAMPLES" caption="(If FMODE is 0) 4 samples (shift sum 1 bit to right, output data is 13-bits) / (If FMODE is 1) 2 samples to be averaged" value="0"/>
+        <value name="16_SAMPLES" caption="(If FMODE is 0) 16 samples (shift sum 2 bits to right, output data is 14-bits) / (If FMODE is 1) 4 samples to be averaged" value="1"/>
+        <value name="64_SAMPLES" caption="(If FMODE is 0) 64 samples (shift sum 3 bits to right, output data is 15-bits) / (If FMODE is 1) 8 samples to be averaged" value="2"/>
+        <value name="256_SAMPLES" caption="(If FMODE is 0) 256 samples (shift sum 4 bits to right, output data is 16-bits) / (If FMODE is 1) 16 samples to be averaged" value="3"/>
+        <value name="2_SAMPLES" caption="(If FMODE is 0) 2 samples (shift sum 0 bits to right, output data is 12.1 format) / (If FMODE is 1) 32 samples to be averaged" value="4"/>
+        <value name="8_SAMPLES" caption="(If FMODE is 0) 8 samples (shift sum 1 bit to right, output data is 13.1 format) / (If FMODE is 1) 64 samples to be averaged" value="5"/>
+        <value name="32_SAMPLES" caption="(If FMODE is 0) 32 samples (shift sum 2 bits to right, output data is 14.1 format) / (If FMODE is 1) 128 samples to be averaged" value="6"/>
+        <value name="128_SAMPLES" caption="(If FMODE is 0) 128 samples (shift sum 3 bits to right, output data is 15.1 format) / (If FMODE is 1) 256 samples to be averaged" value="7"/>
+      </value-group>
+      <value-group name="PFFCTRL__PFFRDYDM">
+        <value name="CTLINTFLAG_PFFHFUL" caption="Selects CTLINTFLAG.PFFHFUL for the ADC DMA PFFRDY trigger signal to the DMAC" value="0"/>
+        <value name="CTLINTFLAG_PFFRDY" caption="Selects CTLINTFLAG.PFFRDY for the ADC DMA PFFRDY trigger signal to the DMAC" value="1"/>
+      </value-group>
+    </module>
+    <module name="AT" id="04932" name2="sec_anti_tamper_v1" version="1a0" caption="Anti-Tamper Controller (AT)">
+      <register-group name="AT" caption="Anti-Tamper Controller (AT)">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control Register A">
+          <bitfield name="SWRST" caption="Software Reset1 = Reset registers , Bus I/F and internal state0 = No effect" mask="0x1"/>
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+          <bitfield name="RUNSTDBY" caption="RUNSTDBY Enable Bit" mask="0x40"/>
+        </register>
+        <register name="TAMPER_KEY" offset="0x100" rw="RW" size="4" count="16" initval="0x00000000" caption="Tamper Key n Register">
+          <bitfield name="TAMPERKEY" caption="Tamper Key Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__LEVELA" offset="0x200" rw="R" size="4" initval="0x00000000" caption="Tamper levels 0 to 7.">
+          <bitfield name="LEVEL0" caption="Level 0." mask="0xF"/>
+          <bitfield name="LEVEL1" caption="Level 1." mask="0xF0"/>
+          <bitfield name="LEVEL2" caption="Level 2." mask="0xF00"/>
+          <bitfield name="LEVEL3" caption="Level 3." mask="0xF000"/>
+          <bitfield name="LEVEL4" caption="Level 4." mask="0xF0000"/>
+          <bitfield name="LEVEL5" caption="Level 5." mask="0xF00000"/>
+          <bitfield name="LEVEL6" caption="Level 6." mask="0xF000000"/>
+          <bitfield name="LEVEL7" caption="Level 7." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__LEVELB" offset="0x204" rw="R" size="4" initval="0x00000000" caption="Tamper levels 8 to 15.">
+          <bitfield name="LEVEL8" caption="Level 8." mask="0xF"/>
+          <bitfield name="LEVEL9" caption="Level 9." mask="0xF0"/>
+          <bitfield name="LEVEL10" caption="Level 10." mask="0xF00"/>
+          <bitfield name="LEVEL11" caption="Level 11." mask="0xF000"/>
+          <bitfield name="LEVEL12" caption="Level 12." mask="0xF0000"/>
+          <bitfield name="LEVEL13" caption="Level 13." mask="0xF00000"/>
+          <bitfield name="LEVEL14" caption="Level 14." mask="0xF000000"/>
+          <bitfield name="LEVEL15" caption="Level 15." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__LEVELC" offset="0x208" rw="R" size="4" initval="0x00000000" caption="Tamper levels 16 to 23.">
+          <bitfield name="LEVEL16" caption="Level 16." mask="0xF"/>
+          <bitfield name="LEVEL17" caption="Level 17." mask="0xF0"/>
+          <bitfield name="LEVEL18" caption="Level 18." mask="0xF00"/>
+          <bitfield name="LEVEL19" caption="Level 19." mask="0xF000"/>
+          <bitfield name="LEVEL20" caption="Level 20." mask="0xF0000"/>
+          <bitfield name="LEVEL21" caption="Level 21." mask="0xF00000"/>
+          <bitfield name="LEVEL22" caption="Level 22." mask="0xF000000"/>
+          <bitfield name="LEVEL23" caption="Level 23." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__LEVELD" offset="0x20C" rw="R" size="4" initval="0x00000000" caption="Tamper levels 24 to 31.">
+          <bitfield name="LEVEL24" caption="Level 24." mask="0xF"/>
+          <bitfield name="LEVEL25" caption="Level 25." mask="0xF0"/>
+          <bitfield name="LEVEL26" caption="Level 26." mask="0xF00"/>
+          <bitfield name="LEVEL27" caption="Level 27." mask="0xF000"/>
+          <bitfield name="LEVEL28" caption="Level 28." mask="0xF0000"/>
+          <bitfield name="LEVEL29" caption="Level 29." mask="0xF00000"/>
+          <bitfield name="LEVEL30" caption="Level 30." mask="0xF000000"/>
+          <bitfield name="LEVEL31" caption="Level 31." mask="0xF0000000"/>
+        </register>
+        <register name="anti_tamper__SETLEVEL" offset="0x210" rw="W" size="4" initval="0x00000000" caption="Set tamper level.">
+          <bitfield name="LEVEL" caption="Tamper level." mask="0x7"/>
+          <bitfield name="ID" caption="Tamper ID." mask="0x1F00"/>
+          <bitfield name="PROTKEY" caption="Protection key (0xA84C)." mask="0xFFFF0000"/>
+        </register>
+        <register name="anti_tamper__FILTERCFG" offset="0x214" rw="RW" size="4" initval="0x00000000" caption="Filter configuration (threshold, period).">
+          <bitfield name="THRESH" caption="Threshold." mask="0x7"/>
+          <bitfield name="PERIOD" caption="Period." mask="0x1F00"/>
+          <bitfield name="PROTKEY" caption="Protection key (0x92F5)." mask="0xFFFF0000"/>
+        </register>
+        <register name="anti_tamper__SOFTTAMP" offset="0x218" rw="RW" size="4" initval="0x00000000" caption="Software triggered tamper.">
+          <bitfield name="ACTIVE" caption="Tamper active." mask="0x1"/>
+          <bitfield name="ID" caption="Tamper ID." mask="0x1F00"/>
+          <bitfield name="PROTKEY" caption="Protection key (0x4BEE)." mask="0xFFFF0000"/>
+        </register>
+        <register name="anti_tamper__RAWSTAT" offset="0x21C" rw="R" size="4" initval="0x00000000" caption="Raw status.">
+          <bitfield name="RAWSTAT" caption="Raw status." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__STAT" offset="0x220" rw="RW" size="4" initval="0x00000001" caption="Status (write to clear).">
+          <bitfield name="STAT" caption="Status (write to clear)." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__TIMESTAMP" offset="0x224" rw="R" size="4" initval="0x00000000" caption="Timestamp for the last tamper.">
+          <bitfield name="TIMESTAMP" caption="Timestamp for the last tamper." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__FILTERCNT" offset="0x228" rw="R" size="4" initval="0x00000000" caption="Current value of filter counter.">
+          <bitfield name="FILTERCNT" caption="Current value of filter counter." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__SOFTINFO" offset="0x22C" rw="RW" size="4" initval="0x00000000" caption="Register for software purpose only.">
+          <bitfield name="SOFTINFO" caption="Register for software purpose only." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="anti_tamper__TAMPERFLAG" offset="0x230" rw="RW" size="4" initval="0x00000000" caption="The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output.">
+          <bitfield name="TAMPERFLAG" caption="The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output." mask="0x1"/>
+        </register>
+        <register name="anti_tamper__SOFTRESET" offset="0x234" rw="R" size="4" atomic-op="set:anti_tamper__SOFTRESET" initval="0x00000000" caption="Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above.">
+          <bitfield name="SOFTRESET" caption="Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above." mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="0" caption="AT registers accessible in privileged and unprivileged modes." value="0"/>
+        <value name="1" caption="AT registers only accessible in privileged mode." value="1"/>
+      </value-group>
+    </module>
+    <module name="BROMC" id="04402" name2="prm_boot_ahb_v2" version="2a0" caption="ARM GF55LPx Boot ROM Controller Macro">
+      <register-group name="BROMC" caption="ARM GF55LPx Boot ROM Controller Macro">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000002" caption="Control A REGISTER">
+          <bitfield name="SWRST" caption="Software Reset bit" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable bit" mask="0x2" values="CTRLA__ENABLE"/>
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+          <bitfield name="PRMWS" caption="ROM Access Time Wait State" mask="0x700" values="CTRLA__PRMWS"/>
+        </register>
+        <register name="UCFG" offset="0x4" rw="R" size="4" initval="0x00000001" caption="User Configuration REGISTER">
+          <bitfield name="BCRCDIS" caption="Boot CRC Disable" mask="0x1" values="UCFG__BCRCDIS"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__ENABLE">
+        <value name="0" caption="Disable ROM read access and power down the ROM. The ROM PGEN input is driven high. The ROM will clamp outputs to 1 and disable all internal current sinks. Refer to the ROM compiler specification for details on powering down the ROM." value="0"/>
+        <value name="1" caption="Enable ROM read access, power up the ROM. The ROM PGEN input is driven low." value="1"/>
+      </value-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="0" caption="Macro register accessible in privileged and unprivileged modes" value="0"/>
+        <value name="1" caption="Macro registers only accessible in privileged mode" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__PRMWS">
+        <value name="0" caption="No wait states, single cycle access" value="0"/>
+        <value name="1" caption="Access time extended 2 clock cycles" value="1"/>
+        <value name="2" caption="Access time extended to 3 clock cycles" value="2"/>
+        <value name="7" caption="Access time extended to 8 clock cycles" value="7"/>
+      </value-group>
+      <value-group name="UCFG__BCRCDIS">
+        <value name="0" caption="Boot ROM content is CRC verified by the ROM controller, status is reported to the DSU. On CRC failure, the controller blocks access to the ROM controller." value="0"/>
+        <value name="1" caption="No CRC verification at Boot." value="1"/>
+      </value-group>
+    </module>
+    <module name="CAN" id="05010" name2="can_fd_apb_v1" version="1a0" caption="Control Area Network">
+      <register-group name="CAN" caption="Control Area Network">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="PRIV" caption="Priveged Access" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run during standby" mask="0x40"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B Register">
+          <bitfield name="OFFSET" caption="Message RAM Base Address Offset." mask="0xFF0000"/>
+        </register>
+        <register name="INTENCLR" offset="0x28" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear register">
+          <bitfield name="DBG" caption="Debug Message Interrupt Disable" mask="0x1"/>
+          <bitfield name="BERR" caption="Bus Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x2C" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set register">
+          <bitfield name="DBG" caption="Debug Message Interrupt Enable" mask="0x1"/>
+          <bitfield name="BERR" caption="Bus Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x30" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear register">
+          <bitfield name="DBG" caption="Debug Message Reception" mask="0x1"/>
+          <bitfield name="BERR" caption="AHB Bus Error Detection" mask="0x2"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x34" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="Interrupt Flag Software Set Register">
+          <bitfield name="DBG" caption="Debug Message Interrupt Flag Set" mask="0x1"/>
+          <bitfield name="BERR" caption="AHB Bus Error Detection Interrupt Flag Set" mask="0x2"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x5C" rw="R" size="4" initval="0x00000000" caption="SYNCBUSY Register">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+        </register>
+        <register name="CREL_MCAN" offset="0x100" rw="R" size="4" initval="0x33000000" caption="Core Release">
+          <bitfield name="DAY" caption="Timestamp day" mask="0xFF"/>
+          <bitfield name="MON" caption="Timestamp month" mask="0xFF00"/>
+          <bitfield name="YEAR" caption="Timestamp year" mask="0xF0000"/>
+          <bitfield name="SUBSTEP" caption="Sub-step of Core Release" mask="0xF00000"/>
+          <bitfield name="STEP" caption="Step of Core Release" mask="0xF000000"/>
+          <bitfield name="REL" caption="Core Release" mask="0xF0000000"/>
+        </register>
+        <register name="ENDN" offset="0x104" rw="R" size="4" initval="0x87654321" caption="Endian">
+          <bitfield name="ETV" caption="Endianness Test Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CUST" offset="0x108" rw="RW" size="4" initval="0x00000000" caption="Customer Register">
+          <bitfield name="CUST" caption="Customer Register" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DBTP" offset="0x10C" rw="RW" size="4" initval="0x00000A33" caption="Fast Bit Timing and Prescaler">
+          <bitfield name="DSJW" caption="Data (Re)Synchronization Jump Width" mask="0xF"/>
+          <bitfield name="DTSEG2" caption="Data time segment after sample point" mask="0xF0"/>
+          <bitfield name="DTSEG1" caption="Data time segment before sample point" mask="0x1F00"/>
+          <bitfield name="DBRP" caption="Data Baud Rate Prescaler" mask="0x1F0000"/>
+          <bitfield name="TDC" caption="Tranceiver Delay Compensation" mask="0x800000"/>
+        </register>
+        <register name="TEST" offset="0x110" rw="RW" size="4" initval="0x00000000" caption="Test">
+          <bitfield name="LBCK" caption="Loop Back Mode" mask="0x10"/>
+          <bitfield name="TX" caption="Control of Transmit Pin" mask="0x60" values="TEST__TX"/>
+          <bitfield name="RX" caption="Receive Pin" mask="0x80"/>
+        </register>
+        <register name="RWD" offset="0x114" rw="RW" size="4" initval="0x00000000" caption="RAM Watchdog">
+          <bitfield name="WDC" caption="Watchdog Configuration" mask="0xFF"/>
+          <bitfield name="WDV" caption="Watchdog Value" mask="0xFF00"/>
+        </register>
+        <register name="CCCR" offset="0x118" rw="RW" access="WSYNC" size="4" initval="0x00000001" caption="CC Control">
+          <bitfield name="INIT" caption="Initialization" mask="0x1"/>
+          <bitfield name="CCE" caption="Configuration Change Enable" mask="0x2"/>
+          <bitfield name="ASM" caption="ASM Restricted Operation Mode" mask="0x4"/>
+          <bitfield name="CSA" caption="Clock Stop Acknowledge" mask="0x8"/>
+          <bitfield name="CSR" caption="Clock Stop Request" mask="0x10"/>
+          <bitfield name="MON" caption="Bus Monitoring Mode" mask="0x20"/>
+          <bitfield name="DAR" caption="Disable Automatic Retransmission" mask="0x40"/>
+          <bitfield name="TEST" caption="Test Mode Enable" mask="0x80"/>
+          <bitfield name="FDOE" caption="FD Operation Enable" mask="0x100"/>
+          <bitfield name="BRSE" caption="Bit Rate Switch Enable" mask="0x200"/>
+          <bitfield name="UTSU" caption="Use Timestamping Unit" mask="0x400"/>
+          <bitfield name="WMM" caption="Wide Message Marker" mask="0x800"/>
+          <bitfield name="PXHD" caption="Protocol Exception Handling Disable" mask="0x1000"/>
+          <bitfield name="EFBI" caption="Edge Filtering during Bus Integration" mask="0x2000"/>
+          <bitfield name="TXP" caption="Transmit Pause" mask="0x4000"/>
+        </register>
+        <register name="NBTP" offset="0x11C" rw="RW" size="4" initval="0x06000A03" caption="Nominal Bit Timing and Prescaler">
+          <bitfield name="NTSEG2" caption="Nominal Time segment after sample point" mask="0x7F"/>
+          <bitfield name="NTSEG1" caption="Nominal Time segment before sample point" mask="0xFF00"/>
+          <bitfield name="NBRP" caption="Nominal Baud Rate Prescaler" mask="0x1FF0000"/>
+          <bitfield name="NSJW" caption="Nominal (Re)Synchronization Jump Width" mask="0xFE000000"/>
+        </register>
+        <register name="TSCC" offset="0x120" rw="RW" size="4" initval="0x00000000" caption="Timestamp Counter Configuration">
+          <bitfield name="TSS" caption="Timestamp Select" mask="0x3" values="TSCC__TSS"/>
+          <bitfield name="TCP" caption="Timestamp Counter Prescaler" mask="0xF0000"/>
+        </register>
+        <register name="TSCV" offset="0x124" rw="R" size="4" initval="0x00000000" caption="Timestamp Counter Value">
+          <bitfield name="TSC" caption="Timestamp Counter" mask="0xFFFF"/>
+        </register>
+        <register name="TOCC" offset="0x128" rw="RW" size="4" initval="0xFFFF0000" caption="Timeout Counter Configuration">
+          <bitfield name="ETOC" caption="Enable Timeout Counter" mask="0x1"/>
+          <bitfield name="TOS" caption="Timeout Select" mask="0x6" values="TOCC__TOS"/>
+          <bitfield name="TOP" caption="Timeout Period" mask="0xFFFF0000"/>
+        </register>
+        <register name="TOCV" offset="0x12C" rw="RW" size="4" initval="0x0000FFFF" caption="Timeout Counter Value">
+          <bitfield name="TOC" caption="Timeout Counter" mask="0xFFFF"/>
+        </register>
+        <register name="ECR" offset="0x140" rw="R" size="4" initval="0x00000000" caption="Error Counter">
+          <bitfield name="TEC" caption="Transmit Error Counter" mask="0xFF"/>
+          <bitfield name="REC" caption="Receive Error Counter" mask="0x7F00"/>
+          <bitfield name="RP" caption="Receive Error Passive" mask="0x8000"/>
+          <bitfield name="CEL" caption="CAN Error Logging" mask="0xFF0000"/>
+        </register>
+        <register name="PSR" offset="0x144" rw="R" size="4" initval="0x00000707" caption="Protocol Status">
+          <bitfield name="LEC" caption="Last Error Code" mask="0x7" values="PSR__LEC"/>
+          <bitfield name="ACT" caption="Activity" mask="0x18" values="PSR__ACT"/>
+          <bitfield name="EP" caption="Error Passive" mask="0x20"/>
+          <bitfield name="EW" caption="Warning Status" mask="0x40"/>
+          <bitfield name="BO" caption="Bus_Off Status" mask="0x80"/>
+          <bitfield name="DLEC" caption="Data Phase Last Error Code" mask="0x700" values="PSR__DLEC"/>
+          <bitfield name="RESI" caption="ESI flag of last received CAN FD Message" mask="0x800"/>
+          <bitfield name="RBRS" caption="BRS flag of last received CAN FD Message" mask="0x1000"/>
+          <bitfield name="RFDF" caption="Received a CAN FD Message" mask="0x2000"/>
+          <bitfield name="PXE" caption="Protocol Exception Event" mask="0x4000"/>
+          <bitfield name="TDCV" caption="Transmitter Delay Compensation Value" mask="0x7F0000"/>
+        </register>
+        <register name="TDCR" offset="0x148" rw="RW" size="4" initval="0x00000000" caption="Extended ID Filter Configuration">
+          <bitfield name="TDCF" caption="Transmitter Delay Compensation Filter Length" mask="0x7F"/>
+          <bitfield name="TDCO" caption="Transmitter Delay Compensation Offset" mask="0x7F00"/>
+        </register>
+        <register name="IR" offset="0x150" rw="RW" size="4" initval="0x00000000" caption="Interrupt">
+          <bitfield name="RF0N" caption="Rx FIFO 0 New Message" mask="0x1"/>
+          <bitfield name="RF0W" caption="Rx FIFO 0 Watermark Reached" mask="0x2"/>
+          <bitfield name="RF0F" caption="Rx FIFO 0 Full" mask="0x4"/>
+          <bitfield name="RF0L" caption="Rx FIFO 0 Message Lost" mask="0x8"/>
+          <bitfield name="RF1N" caption="Rx FIFO 1 New Message" mask="0x10"/>
+          <bitfield name="RF1W" caption="Rx FIFO 1 Watermark Reached" mask="0x20"/>
+          <bitfield name="RF1F" caption="Rx FIFO 1 FIFO Full" mask="0x40"/>
+          <bitfield name="RF1L" caption="Rx FIFO 1 Message Lost" mask="0x80"/>
+          <bitfield name="HPM" caption="High Priority Message" mask="0x100"/>
+          <bitfield name="TC" caption="Timestamp Completed" mask="0x200"/>
+          <bitfield name="TCF" caption="Transmission Cancellation Finished" mask="0x400"/>
+          <bitfield name="TFE" caption="Tx FIFO Empty" mask="0x800"/>
+          <bitfield name="TEFN" caption="Tx Event FIFO New Entry" mask="0x1000"/>
+          <bitfield name="TEFW" caption="Tx Event FIFO Watermark Reached" mask="0x2000"/>
+          <bitfield name="TEFF" caption="Tx Event FIFO Full" mask="0x4000"/>
+          <bitfield name="TEFL" caption="Tx Event FIFO Element Lost" mask="0x8000"/>
+          <bitfield name="TSW" caption="Timestamp Wraparound" mask="0x10000"/>
+          <bitfield name="MRAF" caption="Message RAM Access Failure" mask="0x20000"/>
+          <bitfield name="TOO" caption="Timeout Occurred" mask="0x40000"/>
+          <bitfield name="DRX" caption="Message stored to Dedicated Rx Buffer" mask="0x80000"/>
+          <bitfield name="ELO" caption="Error Logging Overflow" mask="0x400000"/>
+          <bitfield name="EP" caption="Error Passive" mask="0x800000"/>
+          <bitfield name="EW" caption="Warning Status" mask="0x1000000"/>
+          <bitfield name="BO" caption="Bus_Off Status" mask="0x2000000"/>
+          <bitfield name="WDI" caption="Watchdog Interrupt" mask="0x4000000"/>
+          <bitfield name="PEA" caption="Protocol Error in Arbitration Phase" mask="0x8000000"/>
+          <bitfield name="PED" caption="Protocol Error in Data Phase" mask="0x10000000"/>
+          <bitfield name="ARA" caption="Access to Reserved Address" mask="0x20000000"/>
+        </register>
+        <register name="IE" offset="0x154" rw="RW" size="4" initval="0x00000000" caption="Interrupt Enable">
+          <bitfield name="RF0NE" caption="Rx FIFO 0 New Message Interrupt Enable" mask="0x1"/>
+          <bitfield name="RF0WE" caption="Rx FIFO 0 Watermark Reached Interrupt Enable" mask="0x2"/>
+          <bitfield name="RF0FE" caption="Rx FIFO 0 Full Interrupt Enable" mask="0x4"/>
+          <bitfield name="RF0LE" caption="Rx FIFO 0 Message Lost Interrupt Enable" mask="0x8"/>
+          <bitfield name="RF1NE" caption="Rx FIFO 1 New Message Interrupt Enable" mask="0x10"/>
+          <bitfield name="RF1WE" caption="Rx FIFO 1 Watermark Reached Interrupt Enable" mask="0x20"/>
+          <bitfield name="RF1FE" caption="Rx FIFO 1 FIFO Full Interrupt Enable" mask="0x40"/>
+          <bitfield name="RF1LE" caption="Rx FIFO 1 Message Lost Interrupt Enable" mask="0x80"/>
+          <bitfield name="HPME" caption="High Priority Message Interrupt Enable" mask="0x100"/>
+          <bitfield name="TCE" caption="Timestamp Completed Interrupt Enable" mask="0x200"/>
+          <bitfield name="TCFE" caption="Transmission Cancellation Finished Interrupt Enable" mask="0x400"/>
+          <bitfield name="TFEE" caption="Tx FIFO Empty Interrupt Enable" mask="0x800"/>
+          <bitfield name="TEFNE" caption="Tx Event FIFO New Entry Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TEFWE" caption="Tx Event FIFO Watermark Reached Interrupt Enable" mask="0x2000"/>
+          <bitfield name="TEFFE" caption="Tx Event FIFO Full Interrupt Enable" mask="0x4000"/>
+          <bitfield name="TEFLE" caption="Tx Event FIFO Element Lost Interrupt Enable" mask="0x8000"/>
+          <bitfield name="TSWE" caption="Timestamp Wraparound Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MRAFE" caption="Message RAM Access Failure Interrupt Enable" mask="0x20000"/>
+          <bitfield name="TOOE" caption="Timeout Occurred Interrupt Enable" mask="0x40000"/>
+          <bitfield name="DRXE" caption="Message stored to Dedicated Rx Buffer Interrupt Enable" mask="0x80000"/>
+          <bitfield name="ELOE" caption="Error Logging Overflow Interrupt Enable" mask="0x400000"/>
+          <bitfield name="EPE" caption="Error Passive Interrupt Enable" mask="0x800000"/>
+          <bitfield name="EWE" caption="Warning Status Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="BOE" caption="Bus_Off Status Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="WDIE" caption="Watchdog Interrupt Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="PEAE" caption="Protocol Error in Arbitration Phase Enable" mask="0x8000000"/>
+          <bitfield name="PEDE" caption="Protocol Error in Data Phase Enable" mask="0x10000000"/>
+          <bitfield name="ARAE" caption="Access to Reserved Address Enable" mask="0x20000000"/>
+        </register>
+        <register name="ILS" offset="0x158" rw="RW" size="4" initval="0x00000000" caption="Interrupt Line Select">
+          <bitfield name="RF0NL" caption="Rx FIFO 0 New Message Interrupt Line" mask="0x1"/>
+          <bitfield name="RF0WL" caption="Rx FIFO 0 Watermark Reached Interrupt Line" mask="0x2"/>
+          <bitfield name="RF0FL" caption="Rx FIFO 0 Full Interrupt Line" mask="0x4"/>
+          <bitfield name="RF0LL" caption="Rx FIFO 0 Message Lost Interrupt Line" mask="0x8"/>
+          <bitfield name="RF1NL" caption="Rx FIFO 1 New Message Interrupt Line" mask="0x10"/>
+          <bitfield name="RF1WL" caption="Rx FIFO 1 Watermark Reached Interrupt Line" mask="0x20"/>
+          <bitfield name="RF1FL" caption="Rx FIFO 1 FIFO Full Interrupt Line" mask="0x40"/>
+          <bitfield name="RF1LL" caption="Rx FIFO 1 Message Lost Interrupt Line" mask="0x80"/>
+          <bitfield name="HPML" caption="High Priority Message Interrupt Line" mask="0x100"/>
+          <bitfield name="TCL" caption="Timestamp Completed Interrupt Line" mask="0x200"/>
+          <bitfield name="TCFL" caption="Transmission Cancellation Finished Interrupt Line" mask="0x400"/>
+          <bitfield name="TFEL" caption="Tx FIFO Empty Interrupt Line" mask="0x800"/>
+          <bitfield name="TEFNL" caption="Tx Event FIFO New Entry Interrupt Line" mask="0x1000"/>
+          <bitfield name="TEFWL" caption="Tx Event FIFO Watermark Reached Interrupt Line" mask="0x2000"/>
+          <bitfield name="TEFFL" caption="Tx Event FIFO Full Interrupt Line" mask="0x4000"/>
+          <bitfield name="TEFLL" caption="Tx Event FIFO Element Lost Interrupt Line" mask="0x8000"/>
+          <bitfield name="TSWL" caption="Timestamp Wraparound Interrupt Line" mask="0x10000"/>
+          <bitfield name="MRAFL" caption="Message RAM Access Failure Interrupt Line" mask="0x20000"/>
+          <bitfield name="TOOL" caption="Timeout Occurred Interrupt Line" mask="0x40000"/>
+          <bitfield name="DRXL" caption="Message stored to Dedicated Rx Buffer Interrupt Line" mask="0x80000"/>
+          <bitfield name="ELOL" caption="Error Logging Overflow Interrupt Line" mask="0x400000"/>
+          <bitfield name="EPL" caption="Error Passive Interrupt Line" mask="0x800000"/>
+          <bitfield name="EWL" caption="Warning Status Interrupt Line" mask="0x1000000"/>
+          <bitfield name="BOL" caption="Bus_Off Status Interrupt Line" mask="0x2000000"/>
+          <bitfield name="WDIL" caption="Watchdog Interrupt Interrupt Line" mask="0x4000000"/>
+          <bitfield name="PEAL" caption="Protocol Error in Arbitration Phase Line" mask="0x8000000"/>
+          <bitfield name="PEDL" caption="Protocol Error in Data Phase Line" mask="0x10000000"/>
+          <bitfield name="ARAL" caption="Access to Reserved Address Line" mask="0x20000000"/>
+        </register>
+        <register name="ILE" offset="0x15C" rw="RW" size="4" initval="0x00000000" caption="Interrupt Line Enable">
+          <bitfield name="EINT0" caption="Enable Interrupt Line 0" mask="0x1"/>
+          <bitfield name="EINT1" caption="Enable Interrupt Line 1" mask="0x2"/>
+        </register>
+        <register name="GFC" offset="0x180" rw="RW" size="4" initval="0x00000000" caption="Global Filter Configuration">
+          <bitfield name="RRFE" caption="Reject Remote Frames Extended" mask="0x1"/>
+          <bitfield name="RRFS" caption="Reject Remote Frames Standard" mask="0x2"/>
+          <bitfield name="ANFE" caption="Accept Non-matching Frames Extended" mask="0xC" values="GFC__ANFE"/>
+          <bitfield name="ANFS" caption="Accept Non-matching Frames Standard" mask="0x30" values="GFC__ANFS"/>
+        </register>
+        <register name="SIDFC" offset="0x184" rw="RW" size="4" initval="0x00000000" caption="Standard ID Filter Configuration">
+          <bitfield name="FLSSA" caption="Filter List Standard Start Address" mask="0xFFFC"/>
+          <bitfield name="LSS" caption="List Size Standard" mask="0xFF0000"/>
+        </register>
+        <register name="XIDFC" offset="0x188" rw="RW" size="4" initval="0x00000000" caption="Extended ID Filter Configuration">
+          <bitfield name="FLESA" caption="Filter List Extended Start Address" mask="0xFFFC"/>
+          <bitfield name="LSE" caption="List Size Extended" mask="0x7F0000"/>
+        </register>
+        <register name="XIDAM" offset="0x190" rw="RW" size="4" initval="0x1FFFFFFF" caption="Extended ID AND Mask">
+          <bitfield name="EIDM" caption="Extended ID Mask" mask="0x1FFFFFFF"/>
+        </register>
+        <register name="HPMS" offset="0x194" rw="R" size="4" initval="0x00000000" caption="High Priority Message Status">
+          <bitfield name="BIDX" caption="Buffer Index" mask="0x3F"/>
+          <bitfield name="MSI" caption="Message Storage Indicator" mask="0xC0" values="HPMS__MSI"/>
+          <bitfield name="FIDX" caption="Filter Index" mask="0x7F00"/>
+          <bitfield name="FLST" caption="Filter List" mask="0x8000"/>
+        </register>
+        <register name="NDAT1" offset="0x198" rw="RW" size="4" initval="0x00000000" caption="New Data 1">
+          <bitfield name="ND0" caption="New Data 0" mask="0x1"/>
+          <bitfield name="ND1" caption="New Data 1" mask="0x2"/>
+          <bitfield name="ND2" caption="New Data 2" mask="0x4"/>
+          <bitfield name="ND3" caption="New Data 3" mask="0x8"/>
+          <bitfield name="ND4" caption="New Data 4" mask="0x10"/>
+          <bitfield name="ND5" caption="New Data 5" mask="0x20"/>
+          <bitfield name="ND6" caption="New Data 6" mask="0x40"/>
+          <bitfield name="ND7" caption="New Data 7" mask="0x80"/>
+          <bitfield name="ND8" caption="New Data 8" mask="0x100"/>
+          <bitfield name="ND9" caption="New Data 9" mask="0x200"/>
+          <bitfield name="ND10" caption="New Data 10" mask="0x400"/>
+          <bitfield name="ND11" caption="New Data 11" mask="0x800"/>
+          <bitfield name="ND12" caption="New Data 12" mask="0x1000"/>
+          <bitfield name="ND13" caption="New Data 13" mask="0x2000"/>
+          <bitfield name="ND14" caption="New Data 14" mask="0x4000"/>
+          <bitfield name="ND15" caption="New Data 15" mask="0x8000"/>
+          <bitfield name="ND16" caption="New Data 16" mask="0x10000"/>
+          <bitfield name="ND17" caption="New Data 17" mask="0x20000"/>
+          <bitfield name="ND18" caption="New Data 18" mask="0x40000"/>
+          <bitfield name="ND19" caption="New Data 19" mask="0x80000"/>
+          <bitfield name="ND20" caption="New Data 20" mask="0x100000"/>
+          <bitfield name="ND21" caption="New Data 21" mask="0x200000"/>
+          <bitfield name="ND22" caption="New Data 22" mask="0x400000"/>
+          <bitfield name="ND23" caption="New Data 23" mask="0x800000"/>
+          <bitfield name="ND24" caption="New Data 24" mask="0x1000000"/>
+          <bitfield name="ND25" caption="New Data 25" mask="0x2000000"/>
+          <bitfield name="ND26" caption="New Data 26" mask="0x4000000"/>
+          <bitfield name="ND27" caption="New Data 27" mask="0x8000000"/>
+          <bitfield name="ND28" caption="New Data 28" mask="0x10000000"/>
+          <bitfield name="ND29" caption="New Data 29" mask="0x20000000"/>
+          <bitfield name="ND30" caption="New Data 30" mask="0x40000000"/>
+          <bitfield name="ND31" caption="New Data 31" mask="0x80000000"/>
+        </register>
+        <register name="NDAT2" offset="0x19C" rw="RW" size="4" initval="0x00000000" caption="New Data 2">
+          <bitfield name="ND32" caption="New Data 32" mask="0x1"/>
+          <bitfield name="ND33" caption="New Data 33" mask="0x2"/>
+          <bitfield name="ND34" caption="New Data 34" mask="0x4"/>
+          <bitfield name="ND35" caption="New Data 35" mask="0x8"/>
+          <bitfield name="ND36" caption="New Data 36" mask="0x10"/>
+          <bitfield name="ND37" caption="New Data 37" mask="0x20"/>
+          <bitfield name="ND38" caption="New Data 38" mask="0x40"/>
+          <bitfield name="ND39" caption="New Data 39" mask="0x80"/>
+          <bitfield name="ND40" caption="New Data 40" mask="0x100"/>
+          <bitfield name="ND41" caption="New Data 41" mask="0x200"/>
+          <bitfield name="ND42" caption="New Data 42" mask="0x400"/>
+          <bitfield name="ND43" caption="New Data 43" mask="0x800"/>
+          <bitfield name="ND44" caption="New Data 44" mask="0x1000"/>
+          <bitfield name="ND45" caption="New Data 45" mask="0x2000"/>
+          <bitfield name="ND46" caption="New Data 46" mask="0x4000"/>
+          <bitfield name="ND47" caption="New Data 47" mask="0x8000"/>
+          <bitfield name="ND48" caption="New Data 48" mask="0x10000"/>
+          <bitfield name="ND49" caption="New Data 49" mask="0x20000"/>
+          <bitfield name="ND50" caption="New Data 50" mask="0x40000"/>
+          <bitfield name="ND51" caption="New Data 51" mask="0x80000"/>
+          <bitfield name="ND52" caption="New Data 52" mask="0x100000"/>
+          <bitfield name="ND53" caption="New Data 53" mask="0x200000"/>
+          <bitfield name="ND54" caption="New Data 54" mask="0x400000"/>
+          <bitfield name="ND55" caption="New Data 55" mask="0x800000"/>
+          <bitfield name="ND56" caption="New Data 56" mask="0x1000000"/>
+          <bitfield name="ND57" caption="New Data 57" mask="0x2000000"/>
+          <bitfield name="ND58" caption="New Data 58" mask="0x4000000"/>
+          <bitfield name="ND59" caption="New Data 59" mask="0x8000000"/>
+          <bitfield name="ND60" caption="New Data 60" mask="0x10000000"/>
+          <bitfield name="ND61" caption="New Data 61" mask="0x20000000"/>
+          <bitfield name="ND62" caption="New Data 62" mask="0x40000000"/>
+          <bitfield name="ND63" caption="New Data 63" mask="0x80000000"/>
+        </register>
+        <register name="RXF0C" offset="0x1A0" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 0 Configuration">
+          <bitfield name="F0SA" caption="Rx FIFO 0 Start Address" mask="0xFFFC"/>
+          <bitfield name="F0S" caption="Rx FIFO 0 Size" mask="0x7F0000"/>
+          <bitfield name="F0WM" caption="Rx FIFO 0 Watermark" mask="0x7F000000"/>
+          <bitfield name="F0OM" caption="FIFO 0 Operation Mode" mask="0x80000000"/>
+        </register>
+        <register name="RXF0S" offset="0x1A4" rw="R" size="4" initval="0x00000000" caption="Rx FIFO 0 Status">
+          <bitfield name="F0FL" caption="Rx FIFO 0 Fill Level" mask="0x7F"/>
+          <bitfield name="F0GI" caption="Rx FIFO 0 Get Index" mask="0x3F00"/>
+          <bitfield name="F0PI" caption="Rx FIFO 0 Put Index" mask="0x3F0000"/>
+          <bitfield name="F0F" caption="Rx FIFO 0 Full" mask="0x1000000"/>
+          <bitfield name="RF0L" caption="Rx FIFO 0 Message Lost" mask="0x2000000"/>
+        </register>
+        <register name="RXF0A" offset="0x1A8" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 0 Acknowledge">
+          <bitfield name="F0AI" caption="Rx FIFO 0 Acknowledge Index" mask="0x3F"/>
+        </register>
+        <register name="RXBC" offset="0x1AC" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer Configuration">
+          <bitfield name="RBSA" caption="Rx Buffer Start Address" mask="0xFFFC"/>
+        </register>
+        <register name="RXF1C" offset="0x1B0" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 1 Configuration">
+          <bitfield name="F1SA" caption="Rx FIFO 1 Start Address" mask="0xFFFC"/>
+          <bitfield name="F1S" caption="Rx FIFO 1 Size" mask="0x7F0000"/>
+          <bitfield name="F1WM" caption="Rx FIFO 1 Watermark" mask="0x7F000000"/>
+          <bitfield name="F1OM" caption="FIFO 1 Operation Mode" mask="0x80000000"/>
+        </register>
+        <register name="RXF1S" offset="0x1B4" rw="R" size="4" initval="0x00000000" caption="Rx FIFO 1 Status">
+          <bitfield name="F1FL" caption="Rx FIFO 1 Fill Level" mask="0x7F"/>
+          <bitfield name="F1GI" caption="Rx FIFO 1 Get Index" mask="0x3F00"/>
+          <bitfield name="F1PI" caption="Rx FIFO 1 Put Index" mask="0x3F0000"/>
+          <bitfield name="F1F" caption="Rx FIFO 1 Full" mask="0x1000000"/>
+          <bitfield name="RF1L" caption="Rx FIFO 1 Message Lost" mask="0x2000000"/>
+          <bitfield name="DMS" caption="Debug Message Status" mask="0xC0000000" values="RXF1S__DMS"/>
+        </register>
+        <register name="RXF1A" offset="0x1B8" rw="RW" size="4" initval="0x00000000" caption="Rx FIFO 1 Acknowledge">
+          <bitfield name="F1AI" caption="Rx FIFO 1 Acknowledge Index" mask="0x3F"/>
+        </register>
+        <register name="RXESC" offset="0x1BC" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer / FIFO Element Size Configuration">
+          <bitfield name="F0DS" caption="Rx FIFO 0 Data Field Size" mask="0x7" values="RXESC__F0DS"/>
+          <bitfield name="F1DS" caption="Rx FIFO 1 Data Field Size" mask="0x70" values="RXESC__F1DS"/>
+          <bitfield name="RBDS" caption="Rx Buffer Data Field Size" mask="0x700" values="RXESC__RBDS"/>
+        </register>
+        <register name="TXBC" offset="0x1C0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Configuration">
+          <bitfield name="TBSA" caption="Tx Buffers Start Address" mask="0xFFFC"/>
+          <bitfield name="NDTB" caption="Number of Dedicated Transmit Buffers" mask="0x3F0000"/>
+          <bitfield name="TFQS" caption="Transmit FIFO/Queue Size" mask="0x3F000000"/>
+          <bitfield name="TFQM" caption="Tx FIFO/Queue Mode" mask="0x40000000"/>
+        </register>
+        <register name="TXFQS" offset="0x1C4" rw="R" size="4" initval="0x00000000" caption="Tx FIFO / Queue Status">
+          <bitfield name="TFFL" caption="Tx FIFO Free Level" mask="0x3F"/>
+          <bitfield name="TFGI" caption="Tx FIFO Get Index" mask="0x1F00"/>
+          <bitfield name="TFQPI" caption="Tx FIFO/Queue Put Index" mask="0x1F0000"/>
+          <bitfield name="TFQF" caption="Tx FIFO/Queue Full" mask="0x200000"/>
+        </register>
+        <register name="TXESC" offset="0x1C8" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Element Size Configuration">
+          <bitfield name="TBDS" caption="Tx Buffer Data Field Size" mask="0x7" values="TXESC__TBDS"/>
+        </register>
+        <register name="TXBRP" offset="0x1CC" rw="R" size="4" initval="0x00000000" caption="Tx Buffer Request Pending">
+          <bitfield name="TRP0" caption="Transmission Request Pending 0" mask="0x1"/>
+          <bitfield name="TRP1" caption="Transmission Request Pending 1" mask="0x2"/>
+          <bitfield name="TRP2" caption="Transmission Request Pending 2" mask="0x4"/>
+          <bitfield name="TRP3" caption="Transmission Request Pending 3" mask="0x8"/>
+          <bitfield name="TRP4" caption="Transmission Request Pending 4" mask="0x10"/>
+          <bitfield name="TRP5" caption="Transmission Request Pending 5" mask="0x20"/>
+          <bitfield name="TRP6" caption="Transmission Request Pending 6" mask="0x40"/>
+          <bitfield name="TRP7" caption="Transmission Request Pending 7" mask="0x80"/>
+          <bitfield name="TRP8" caption="Transmission Request Pending 8" mask="0x100"/>
+          <bitfield name="TRP9" caption="Transmission Request Pending 9" mask="0x200"/>
+          <bitfield name="TRP10" caption="Transmission Request Pending 10" mask="0x400"/>
+          <bitfield name="TRP11" caption="Transmission Request Pending 11" mask="0x800"/>
+          <bitfield name="TRP12" caption="Transmission Request Pending 12" mask="0x1000"/>
+          <bitfield name="TRP13" caption="Transmission Request Pending 13" mask="0x2000"/>
+          <bitfield name="TRP14" caption="Transmission Request Pending 14" mask="0x4000"/>
+          <bitfield name="TRP15" caption="Transmission Request Pending 15" mask="0x8000"/>
+          <bitfield name="TRP16" caption="Transmission Request Pending 16" mask="0x10000"/>
+          <bitfield name="TRP17" caption="Transmission Request Pending 17" mask="0x20000"/>
+          <bitfield name="TRP18" caption="Transmission Request Pending 18" mask="0x40000"/>
+          <bitfield name="TRP19" caption="Transmission Request Pending 19" mask="0x80000"/>
+          <bitfield name="TRP20" caption="Transmission Request Pending 20" mask="0x100000"/>
+          <bitfield name="TRP21" caption="Transmission Request Pending 21" mask="0x200000"/>
+          <bitfield name="TRP22" caption="Transmission Request Pending 22" mask="0x400000"/>
+          <bitfield name="TRP23" caption="Transmission Request Pending 23" mask="0x800000"/>
+          <bitfield name="TRP24" caption="Transmission Request Pending 24" mask="0x1000000"/>
+          <bitfield name="TRP25" caption="Transmission Request Pending 25" mask="0x2000000"/>
+          <bitfield name="TRP26" caption="Transmission Request Pending 26" mask="0x4000000"/>
+          <bitfield name="TRP27" caption="Transmission Request Pending 27" mask="0x8000000"/>
+          <bitfield name="TRP28" caption="Transmission Request Pending 28" mask="0x10000000"/>
+          <bitfield name="TRP29" caption="Transmission Request Pending 29" mask="0x20000000"/>
+          <bitfield name="TRP30" caption="Transmission Request Pending 30" mask="0x40000000"/>
+          <bitfield name="TRP31" caption="Transmission Request Pending 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBAR" offset="0x1D0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Add Request">
+          <bitfield name="AR0" caption="Add Request 0" mask="0x1"/>
+          <bitfield name="AR1" caption="Add Request 1" mask="0x2"/>
+          <bitfield name="AR2" caption="Add Request 2" mask="0x4"/>
+          <bitfield name="AR3" caption="Add Request 3" mask="0x8"/>
+          <bitfield name="AR4" caption="Add Request 4" mask="0x10"/>
+          <bitfield name="AR5" caption="Add Request 5" mask="0x20"/>
+          <bitfield name="AR6" caption="Add Request 6" mask="0x40"/>
+          <bitfield name="AR7" caption="Add Request 7" mask="0x80"/>
+          <bitfield name="AR8" caption="Add Request 8" mask="0x100"/>
+          <bitfield name="AR9" caption="Add Request 9" mask="0x200"/>
+          <bitfield name="AR10" caption="Add Request 10" mask="0x400"/>
+          <bitfield name="AR11" caption="Add Request 11" mask="0x800"/>
+          <bitfield name="AR12" caption="Add Request 12" mask="0x1000"/>
+          <bitfield name="AR13" caption="Add Request 13" mask="0x2000"/>
+          <bitfield name="AR14" caption="Add Request 14" mask="0x4000"/>
+          <bitfield name="AR15" caption="Add Request 15" mask="0x8000"/>
+          <bitfield name="AR16" caption="Add Request 16" mask="0x10000"/>
+          <bitfield name="AR17" caption="Add Request 17" mask="0x20000"/>
+          <bitfield name="AR18" caption="Add Request 18" mask="0x40000"/>
+          <bitfield name="AR19" caption="Add Request 19" mask="0x80000"/>
+          <bitfield name="AR20" caption="Add Request 20" mask="0x100000"/>
+          <bitfield name="AR21" caption="Add Request 21" mask="0x200000"/>
+          <bitfield name="AR22" caption="Add Request 22" mask="0x400000"/>
+          <bitfield name="AR23" caption="Add Request 23" mask="0x800000"/>
+          <bitfield name="AR24" caption="Add Request 24" mask="0x1000000"/>
+          <bitfield name="AR25" caption="Add Request 25" mask="0x2000000"/>
+          <bitfield name="AR26" caption="Add Request 26" mask="0x4000000"/>
+          <bitfield name="AR27" caption="Add Request 27" mask="0x8000000"/>
+          <bitfield name="AR28" caption="Add Request 28" mask="0x10000000"/>
+          <bitfield name="AR29" caption="Add Request 29" mask="0x20000000"/>
+          <bitfield name="AR30" caption="Add Request 30" mask="0x40000000"/>
+          <bitfield name="AR31" caption="Add Request 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBCR" offset="0x1D4" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Cancellation Request">
+          <bitfield name="CR0" caption="Cancellation Request 0" mask="0x1"/>
+          <bitfield name="CR1" caption="Cancellation Request 1" mask="0x2"/>
+          <bitfield name="CR2" caption="Cancellation Request 2" mask="0x4"/>
+          <bitfield name="CR3" caption="Cancellation Request 3" mask="0x8"/>
+          <bitfield name="CR4" caption="Cancellation Request 4" mask="0x10"/>
+          <bitfield name="CR5" caption="Cancellation Request 5" mask="0x20"/>
+          <bitfield name="CR6" caption="Cancellation Request 6" mask="0x40"/>
+          <bitfield name="CR7" caption="Cancellation Request 7" mask="0x80"/>
+          <bitfield name="CR8" caption="Cancellation Request 8" mask="0x100"/>
+          <bitfield name="CR9" caption="Cancellation Request 9" mask="0x200"/>
+          <bitfield name="CR10" caption="Cancellation Request 10" mask="0x400"/>
+          <bitfield name="CR11" caption="Cancellation Request 11" mask="0x800"/>
+          <bitfield name="CR12" caption="Cancellation Request 12" mask="0x1000"/>
+          <bitfield name="CR13" caption="Cancellation Request 13" mask="0x2000"/>
+          <bitfield name="CR14" caption="Cancellation Request 14" mask="0x4000"/>
+          <bitfield name="CR15" caption="Cancellation Request 15" mask="0x8000"/>
+          <bitfield name="CR16" caption="Cancellation Request 16" mask="0x10000"/>
+          <bitfield name="CR17" caption="Cancellation Request 17" mask="0x20000"/>
+          <bitfield name="CR18" caption="Cancellation Request 18" mask="0x40000"/>
+          <bitfield name="CR19" caption="Cancellation Request 19" mask="0x80000"/>
+          <bitfield name="CR20" caption="Cancellation Request 20" mask="0x100000"/>
+          <bitfield name="CR21" caption="Cancellation Request 21" mask="0x200000"/>
+          <bitfield name="CR22" caption="Cancellation Request 22" mask="0x400000"/>
+          <bitfield name="CR23" caption="Cancellation Request 23" mask="0x800000"/>
+          <bitfield name="CR24" caption="Cancellation Request 24" mask="0x1000000"/>
+          <bitfield name="CR25" caption="Cancellation Request 25" mask="0x2000000"/>
+          <bitfield name="CR26" caption="Cancellation Request 26" mask="0x4000000"/>
+          <bitfield name="CR27" caption="Cancellation Request 27" mask="0x8000000"/>
+          <bitfield name="CR28" caption="Cancellation Request 28" mask="0x10000000"/>
+          <bitfield name="CR29" caption="Cancellation Request 29" mask="0x20000000"/>
+          <bitfield name="CR30" caption="Cancellation Request 30" mask="0x40000000"/>
+          <bitfield name="CR31" caption="Cancellation Request 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBTO" offset="0x1D8" rw="R" size="4" initval="0x00000000" caption="Tx Buffer Transmission Occurred">
+          <bitfield name="TO0" caption="Transmission Occurred 0" mask="0x1"/>
+          <bitfield name="TO1" caption="Transmission Occurred 1" mask="0x2"/>
+          <bitfield name="TO2" caption="Transmission Occurred 2" mask="0x4"/>
+          <bitfield name="TO3" caption="Transmission Occurred 3" mask="0x8"/>
+          <bitfield name="TO4" caption="Transmission Occurred 4" mask="0x10"/>
+          <bitfield name="TO5" caption="Transmission Occurred 5" mask="0x20"/>
+          <bitfield name="TO6" caption="Transmission Occurred 6" mask="0x40"/>
+          <bitfield name="TO7" caption="Transmission Occurred 7" mask="0x80"/>
+          <bitfield name="TO8" caption="Transmission Occurred 8" mask="0x100"/>
+          <bitfield name="TO9" caption="Transmission Occurred 9" mask="0x200"/>
+          <bitfield name="TO10" caption="Transmission Occurred 10" mask="0x400"/>
+          <bitfield name="TO11" caption="Transmission Occurred 11" mask="0x800"/>
+          <bitfield name="TO12" caption="Transmission Occurred 12" mask="0x1000"/>
+          <bitfield name="TO13" caption="Transmission Occurred 13" mask="0x2000"/>
+          <bitfield name="TO14" caption="Transmission Occurred 14" mask="0x4000"/>
+          <bitfield name="TO15" caption="Transmission Occurred 15" mask="0x8000"/>
+          <bitfield name="TO16" caption="Transmission Occurred 16" mask="0x10000"/>
+          <bitfield name="TO17" caption="Transmission Occurred 17" mask="0x20000"/>
+          <bitfield name="TO18" caption="Transmission Occurred 18" mask="0x40000"/>
+          <bitfield name="TO19" caption="Transmission Occurred 19" mask="0x80000"/>
+          <bitfield name="TO20" caption="Transmission Occurred 20" mask="0x100000"/>
+          <bitfield name="TO21" caption="Transmission Occurred 21" mask="0x200000"/>
+          <bitfield name="TO22" caption="Transmission Occurred 22" mask="0x400000"/>
+          <bitfield name="TO23" caption="Transmission Occurred 23" mask="0x800000"/>
+          <bitfield name="TO24" caption="Transmission Occurred 24" mask="0x1000000"/>
+          <bitfield name="TO25" caption="Transmission Occurred 25" mask="0x2000000"/>
+          <bitfield name="TO26" caption="Transmission Occurred 26" mask="0x4000000"/>
+          <bitfield name="TO27" caption="Transmission Occurred 27" mask="0x8000000"/>
+          <bitfield name="TO28" caption="Transmission Occurred 28" mask="0x10000000"/>
+          <bitfield name="TO29" caption="Transmission Occurred 29" mask="0x20000000"/>
+          <bitfield name="TO30" caption="Transmission Occurred 30" mask="0x40000000"/>
+          <bitfield name="TO31" caption="Transmission Occurred 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBCF" offset="0x1DC" rw="R" size="4" initval="0x00000000" caption="Tx Buffer Cancellation Finished">
+          <bitfield name="CF0" caption="Tx Buffer Cancellation Finished 0" mask="0x1"/>
+          <bitfield name="CF1" caption="Tx Buffer Cancellation Finished 1" mask="0x2"/>
+          <bitfield name="CF2" caption="Tx Buffer Cancellation Finished 2" mask="0x4"/>
+          <bitfield name="CF3" caption="Tx Buffer Cancellation Finished 3" mask="0x8"/>
+          <bitfield name="CF4" caption="Tx Buffer Cancellation Finished 4" mask="0x10"/>
+          <bitfield name="CF5" caption="Tx Buffer Cancellation Finished 5" mask="0x20"/>
+          <bitfield name="CF6" caption="Tx Buffer Cancellation Finished 6" mask="0x40"/>
+          <bitfield name="CF7" caption="Tx Buffer Cancellation Finished 7" mask="0x80"/>
+          <bitfield name="CF8" caption="Tx Buffer Cancellation Finished 8" mask="0x100"/>
+          <bitfield name="CF9" caption="Tx Buffer Cancellation Finished 9" mask="0x200"/>
+          <bitfield name="CF10" caption="Tx Buffer Cancellation Finished 10" mask="0x400"/>
+          <bitfield name="CF11" caption="Tx Buffer Cancellation Finished 11" mask="0x800"/>
+          <bitfield name="CF12" caption="Tx Buffer Cancellation Finished 12" mask="0x1000"/>
+          <bitfield name="CF13" caption="Tx Buffer Cancellation Finished 13" mask="0x2000"/>
+          <bitfield name="CF14" caption="Tx Buffer Cancellation Finished 14" mask="0x4000"/>
+          <bitfield name="CF15" caption="Tx Buffer Cancellation Finished 15" mask="0x8000"/>
+          <bitfield name="CF16" caption="Tx Buffer Cancellation Finished 16" mask="0x10000"/>
+          <bitfield name="CF17" caption="Tx Buffer Cancellation Finished 17" mask="0x20000"/>
+          <bitfield name="CF18" caption="Tx Buffer Cancellation Finished 18" mask="0x40000"/>
+          <bitfield name="CF19" caption="Tx Buffer Cancellation Finished 19" mask="0x80000"/>
+          <bitfield name="CF20" caption="Tx Buffer Cancellation Finished 20" mask="0x100000"/>
+          <bitfield name="CF21" caption="Tx Buffer Cancellation Finished 21" mask="0x200000"/>
+          <bitfield name="CF22" caption="Tx Buffer Cancellation Finished 22" mask="0x400000"/>
+          <bitfield name="CF23" caption="Tx Buffer Cancellation Finished 23" mask="0x800000"/>
+          <bitfield name="CF24" caption="Tx Buffer Cancellation Finished 24" mask="0x1000000"/>
+          <bitfield name="CF25" caption="Tx Buffer Cancellation Finished 25" mask="0x2000000"/>
+          <bitfield name="CF26" caption="Tx Buffer Cancellation Finished 26" mask="0x4000000"/>
+          <bitfield name="CF27" caption="Tx Buffer Cancellation Finished 27" mask="0x8000000"/>
+          <bitfield name="CF28" caption="Tx Buffer Cancellation Finished 28" mask="0x10000000"/>
+          <bitfield name="CF29" caption="Tx Buffer Cancellation Finished 29" mask="0x20000000"/>
+          <bitfield name="CF30" caption="Tx Buffer Cancellation Finished 30" mask="0x40000000"/>
+          <bitfield name="CF31" caption="Tx Buffer Cancellation Finished 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBTIE" offset="0x1E0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Transmission Interrupt Enable">
+          <bitfield name="TIE0" caption="Transmission Interrupt Enable 0" mask="0x1"/>
+          <bitfield name="TIE1" caption="Transmission Interrupt Enable 1" mask="0x2"/>
+          <bitfield name="TIE2" caption="Transmission Interrupt Enable 2" mask="0x4"/>
+          <bitfield name="TIE3" caption="Transmission Interrupt Enable 3" mask="0x8"/>
+          <bitfield name="TIE4" caption="Transmission Interrupt Enable 4" mask="0x10"/>
+          <bitfield name="TIE5" caption="Transmission Interrupt Enable 5" mask="0x20"/>
+          <bitfield name="TIE6" caption="Transmission Interrupt Enable 6" mask="0x40"/>
+          <bitfield name="TIE7" caption="Transmission Interrupt Enable 7" mask="0x80"/>
+          <bitfield name="TIE8" caption="Transmission Interrupt Enable 8" mask="0x100"/>
+          <bitfield name="TIE9" caption="Transmission Interrupt Enable 9" mask="0x200"/>
+          <bitfield name="TIE10" caption="Transmission Interrupt Enable 10" mask="0x400"/>
+          <bitfield name="TIE11" caption="Transmission Interrupt Enable 11" mask="0x800"/>
+          <bitfield name="TIE12" caption="Transmission Interrupt Enable 12" mask="0x1000"/>
+          <bitfield name="TIE13" caption="Transmission Interrupt Enable 13" mask="0x2000"/>
+          <bitfield name="TIE14" caption="Transmission Interrupt Enable 14" mask="0x4000"/>
+          <bitfield name="TIE15" caption="Transmission Interrupt Enable 15" mask="0x8000"/>
+          <bitfield name="TIE16" caption="Transmission Interrupt Enable 16" mask="0x10000"/>
+          <bitfield name="TIE17" caption="Transmission Interrupt Enable 17" mask="0x20000"/>
+          <bitfield name="TIE18" caption="Transmission Interrupt Enable 18" mask="0x40000"/>
+          <bitfield name="TIE19" caption="Transmission Interrupt Enable 19" mask="0x80000"/>
+          <bitfield name="TIE20" caption="Transmission Interrupt Enable 20" mask="0x100000"/>
+          <bitfield name="TIE21" caption="Transmission Interrupt Enable 21" mask="0x200000"/>
+          <bitfield name="TIE22" caption="Transmission Interrupt Enable 22" mask="0x400000"/>
+          <bitfield name="TIE23" caption="Transmission Interrupt Enable 23" mask="0x800000"/>
+          <bitfield name="TIE24" caption="Transmission Interrupt Enable 24" mask="0x1000000"/>
+          <bitfield name="TIE25" caption="Transmission Interrupt Enable 25" mask="0x2000000"/>
+          <bitfield name="TIE26" caption="Transmission Interrupt Enable 26" mask="0x4000000"/>
+          <bitfield name="TIE27" caption="Transmission Interrupt Enable 27" mask="0x8000000"/>
+          <bitfield name="TIE28" caption="Transmission Interrupt Enable 28" mask="0x10000000"/>
+          <bitfield name="TIE29" caption="Transmission Interrupt Enable 29" mask="0x20000000"/>
+          <bitfield name="TIE30" caption="Transmission Interrupt Enable 30" mask="0x40000000"/>
+          <bitfield name="TIE31" caption="Transmission Interrupt Enable 31" mask="0x80000000"/>
+        </register>
+        <register name="TXBCIE" offset="0x1E4" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Cancellation Finished Interrupt Enable">
+          <bitfield name="CFIE0" caption="Cancellation Finished Interrupt Enable 0" mask="0x1"/>
+          <bitfield name="CFIE1" caption="Cancellation Finished Interrupt Enable 1" mask="0x2"/>
+          <bitfield name="CFIE2" caption="Cancellation Finished Interrupt Enable 2" mask="0x4"/>
+          <bitfield name="CFIE3" caption="Cancellation Finished Interrupt Enable 3" mask="0x8"/>
+          <bitfield name="CFIE4" caption="Cancellation Finished Interrupt Enable 4" mask="0x10"/>
+          <bitfield name="CFIE5" caption="Cancellation Finished Interrupt Enable 5" mask="0x20"/>
+          <bitfield name="CFIE6" caption="Cancellation Finished Interrupt Enable 6" mask="0x40"/>
+          <bitfield name="CFIE7" caption="Cancellation Finished Interrupt Enable 7" mask="0x80"/>
+          <bitfield name="CFIE8" caption="Cancellation Finished Interrupt Enable 8" mask="0x100"/>
+          <bitfield name="CFIE9" caption="Cancellation Finished Interrupt Enable 9" mask="0x200"/>
+          <bitfield name="CFIE10" caption="Cancellation Finished Interrupt Enable 10" mask="0x400"/>
+          <bitfield name="CFIE11" caption="Cancellation Finished Interrupt Enable 11" mask="0x800"/>
+          <bitfield name="CFIE12" caption="Cancellation Finished Interrupt Enable 12" mask="0x1000"/>
+          <bitfield name="CFIE13" caption="Cancellation Finished Interrupt Enable 13" mask="0x2000"/>
+          <bitfield name="CFIE14" caption="Cancellation Finished Interrupt Enable 14" mask="0x4000"/>
+          <bitfield name="CFIE15" caption="Cancellation Finished Interrupt Enable 15" mask="0x8000"/>
+          <bitfield name="CFIE16" caption="Cancellation Finished Interrupt Enable 16" mask="0x10000"/>
+          <bitfield name="CFIE17" caption="Cancellation Finished Interrupt Enable 17" mask="0x20000"/>
+          <bitfield name="CFIE18" caption="Cancellation Finished Interrupt Enable 18" mask="0x40000"/>
+          <bitfield name="CFIE19" caption="Cancellation Finished Interrupt Enable 19" mask="0x80000"/>
+          <bitfield name="CFIE20" caption="Cancellation Finished Interrupt Enable 20" mask="0x100000"/>
+          <bitfield name="CFIE21" caption="Cancellation Finished Interrupt Enable 21" mask="0x200000"/>
+          <bitfield name="CFIE22" caption="Cancellation Finished Interrupt Enable 22" mask="0x400000"/>
+          <bitfield name="CFIE23" caption="Cancellation Finished Interrupt Enable 23" mask="0x800000"/>
+          <bitfield name="CFIE24" caption="Cancellation Finished Interrupt Enable 24" mask="0x1000000"/>
+          <bitfield name="CFIE25" caption="Cancellation Finished Interrupt Enable 25" mask="0x2000000"/>
+          <bitfield name="CFIE26" caption="Cancellation Finished Interrupt Enable 26" mask="0x4000000"/>
+          <bitfield name="CFIE27" caption="Cancellation Finished Interrupt Enable 27" mask="0x8000000"/>
+          <bitfield name="CFIE28" caption="Cancellation Finished Interrupt Enable 28" mask="0x10000000"/>
+          <bitfield name="CFIE29" caption="Cancellation Finished Interrupt Enable 29" mask="0x20000000"/>
+          <bitfield name="CFIE30" caption="Cancellation Finished Interrupt Enable 30" mask="0x40000000"/>
+          <bitfield name="CFIE31" caption="Cancellation Finished Interrupt Enable 31" mask="0x80000000"/>
+        </register>
+        <register name="TXEFC" offset="0x1F0" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Configuration">
+          <bitfield name="EFSA" caption="Event FIFO Start Address" mask="0xFFFC"/>
+          <bitfield name="EFS" caption="Event FIFO Size" mask="0x3F0000"/>
+          <bitfield name="EFWM" caption="Event FIFO Watermark" mask="0x3F000000"/>
+        </register>
+        <register name="TXEFS" offset="0x1F4" rw="R" size="4" initval="0x00000000" caption="Tx Event FIFO Status">
+          <bitfield name="EFFL" caption="Event FIFO Fill Level" mask="0x3F"/>
+          <bitfield name="EFGI" caption="Event FIFO Get Index" mask="0x1F00"/>
+          <bitfield name="EFPI" caption="Event FIFO Put Index" mask="0x1F0000"/>
+          <bitfield name="EFF" caption="Event FIFO Full" mask="0x1000000"/>
+          <bitfield name="TEFL" caption="Tx Event FIFO Element Lost" mask="0x2000000"/>
+        </register>
+        <register name="TXEFA" offset="0x1F8" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Acknowledge">
+          <bitfield name="EFAI" caption="Event FIFO Acknowledge Index" mask="0x1F"/>
+        </register>
+        <register name="CREL_TSU" offset="0x260" rw="R" size="4" initval="0x10000000" caption="TSU CREL">
+          <bitfield name="DAY" caption="Timestamp Day" mask="0xFF"/>
+          <bitfield name="MON" caption="Timestamp Month" mask="0xFF00"/>
+          <bitfield name="YEAR" caption="Timestamp Year" mask="0xF0000"/>
+          <bitfield name="SUBSTEP" caption="Sub-step of Core Release" mask="0xF00000"/>
+          <bitfield name="STEP" caption="Step of Core Release" mask="0xF000000"/>
+          <bitfield name="REL" caption="Core Release" mask="0xF0000000"/>
+        </register>
+        <register name="TSCFG" offset="0x264" rw="RW" size="4" initval="0x00000000" caption="Timestamp Configuration">
+          <bitfield name="TSUE" caption="Timestamp Unit Enable" mask="0x1"/>
+          <bitfield name="TBCS" caption="Timebase Counter Select" mask="0x2"/>
+          <bitfield name="SCP" caption="Select Capturing Position" mask="0x4"/>
+          <bitfield name="TBPRE" caption="Time Base Prescaler" mask="0xFF00"/>
+        </register>
+        <register name="TSS1" offset="0x268" rw="R" size="4" initval="0x00000000" caption="Timestamp Status 1">
+          <bitfield name="TSL" caption="Timestamp Lost" mask="0xFFFF"/>
+          <bitfield name="TSN" caption="Timestamp New" mask="0xFFFF0000"/>
+        </register>
+        <register name="TSS2" offset="0x26C" rw="R" size="4" initval="0x0000A000" caption="Timestamp Status 2">
+          <bitfield name="TSP" caption="Timestamp Pointer" mask="0xF"/>
+          <bitfield name="NTSG" caption="Number of Timestamps Generic" mask="0x3000"/>
+          <bitfield name="ITBG" caption="Internal Timebase and SOF select Generic" mask="0xC000"/>
+        </register>
+        <register name="TS0" offset="0x270" rw="R" size="4" initval="0x00000000" caption="Timestamp 0">
+          <bitfield name="TS" caption="Timestamp Word TS0" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS1" offset="0x274" rw="R" size="4" initval="0x00000000" caption="Timestamp 1">
+          <bitfield name="TS" caption="Timestamp Word TS1" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS2" offset="0x278" rw="R" size="4" initval="0x00000000" caption="Timestamp 2">
+          <bitfield name="TS" caption="Timestamp Word TS2" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS3" offset="0x27C" rw="R" size="4" initval="0x00000000" caption="Timestamp 3">
+          <bitfield name="TS" caption="Timestamp Word TS0" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS4" offset="0x280" rw="R" size="4" initval="0x00000000" caption="Timestamp 4">
+          <bitfield name="TS" caption="Timestamp Word TS4" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS5" offset="0x284" rw="R" size="4" initval="0x00000000" caption="Timestamp 5">
+          <bitfield name="TS" caption="Timestamp Word TS5" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS6" offset="0x288" rw="R" size="4" initval="0x00000000" caption="Timestamp 6">
+          <bitfield name="TS" caption="Timestamp Word TS6" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS7" offset="0x28C" rw="R" size="4" initval="0x00000000" caption="Timestamp 7">
+          <bitfield name="TS" caption="Timestamp Word TS7" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS8" offset="0x290" rw="R" size="4" initval="0x00000000" caption="Timestamp 8">
+          <bitfield name="TS" caption="Timestamp Word TS8" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS9" offset="0x294" rw="R" size="4" initval="0x00000000" caption="Timestamp 9">
+          <bitfield name="TS" caption="Timestamp Word TS9" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS10" offset="0x298" rw="R" size="4" initval="0x00000000" caption="Timestamp 10">
+          <bitfield name="TS" caption="Timestamp Word TS10" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS11" offset="0x29C" rw="R" size="4" initval="0x00000000" caption="Timestamp 11">
+          <bitfield name="TS" caption="Timestamp Word TS11" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS12" offset="0x2A0" rw="R" size="4" initval="0x00000000" caption="Timestamp 12">
+          <bitfield name="TS" caption="Timestamp Word TS12" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS13" offset="0x2A4" rw="R" size="4" initval="0x00000000" caption="Timestamp 13">
+          <bitfield name="TS" caption="Timestamp Word TS13" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS14" offset="0x2A8" rw="R" size="4" initval="0x00000000" caption="Timestamp 14">
+          <bitfield name="TS" caption="Timestamp Word TS14" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TS15" offset="0x2AC" rw="R" size="4" initval="0x00000000" caption="Timestamp 15">
+          <bitfield name="TS" caption="Timestamp Word TS15" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="ATB" offset="0x2B0" rw="RW" size="4" atomic-op="clear:ATB" initval="0x00000000" caption="Actual Timebase">
+          <bitfield name="TB" caption="Timebase for timestamp generation" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_RXBE" caption="Control Area Network" aligned="4">
+        <register name="R0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer and FIFO Element 0">
+          <bitfield name="ID" caption="Identifier" mask="0x1FFFFFFF"/>
+          <bitfield name="RTR" caption="Remote Transmission Request" mask="0x20000000"/>
+          <bitfield name="XTD" caption="Extended Identifier" mask="0x40000000"/>
+          <bitfield name="ESI" caption="Error State Indicator" mask="0x80000000"/>
+        </register>
+        <register name="R1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Rx Buffer and FIFO Element 1">
+          <bitfield name="RXTS" caption="Rx Timestamp" mask="0xFFFF"/>
+          <bitfield name="DLC" caption="Data Length Code" mask="0xF0000"/>
+          <bitfield name="BRS" caption="Bit Rate Search" mask="0x100000"/>
+          <bitfield name="FDF" caption="FD Format" mask="0x200000"/>
+          <bitfield name="FIDX" caption="Filter Index" mask="0x7F000000"/>
+          <bitfield name="ANMF" caption="Accepted Non-matching Frame" mask="0x80000000"/>
+        </register>
+        <register name="R2" offset="0x8" rw="RW" size="4" count="16" initval="0x00000000" caption="Rx Buffer and FIFO Element Data">
+          <bitfield name="DB0" caption="Data Byte 0" mask="0xFF"/>
+          <bitfield name="DB1" caption="Data Byte 1" mask="0xFF00"/>
+          <bitfield name="DB2" caption="Data Byte 2" mask="0xFF0000"/>
+          <bitfield name="DB3" caption="Data Byte 3" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_SIDFE" caption="Control Area Network" aligned="4">
+        <register name="S0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Standard Message ID Filter Element">
+          <bitfield name="SFID2" caption="Standard Filter ID 2" mask="0x7FF"/>
+          <bitfield name="SFID1" caption="Standard Filter ID 1" mask="0x7FF0000"/>
+          <bitfield name="SFEC" caption="Standard Filter Element Configuration" mask="0x38000000" values="S0__SFEC"/>
+          <bitfield name="SFT" caption="Standard Filter Type" mask="0xC0000000" values="S0__SFT"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_TXBE" caption="Control Area Network" aligned="4">
+        <register name="T0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Element 0">
+          <bitfield name="ID" caption="Identifier" mask="0x1FFFFFFF"/>
+          <bitfield name="RTR" caption="Remote Transmission Request" mask="0x20000000"/>
+          <bitfield name="XTD" caption="Extended Identifier" mask="0x40000000"/>
+          <bitfield name="ESI" caption="Error State Indicator" mask="0x80000000"/>
+        </register>
+        <register name="T1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Tx Buffer Element 1">
+          <bitfield name="MMH" caption="Message Marker Higher Byte" mask="0xFF00"/>
+          <bitfield name="DLC" caption="Identifier" mask="0xF0000"/>
+          <bitfield name="BRS" caption="Bit Rate Search" mask="0x100000"/>
+          <bitfield name="FDF" caption="FD Format" mask="0x200000"/>
+          <bitfield name="TSCE" caption="Time Stamp Capture Enable for TSU" mask="0x400000"/>
+          <bitfield name="EFC" caption="Event FIFO Control" mask="0x800000"/>
+          <bitfield name="MML" caption="Message Marker Lower Byte" mask="0xFF000000"/>
+        </register>
+        <register name="T2" offset="0x8" rw="RW" size="4" count="16" initval="0x00000000" caption="Tx Buffer Element Data">
+          <bitfield name="DB0" caption="Data Byte 0" mask="0xFF"/>
+          <bitfield name="DB1" caption="Data Byte 1" mask="0xFF00"/>
+          <bitfield name="DB2" caption="Data Byte 2" mask="0xFF0000"/>
+          <bitfield name="DB3" caption="Data Byte 3" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_TXEFE" caption="Control Area Network" aligned="4">
+        <register name="E0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Element 0">
+          <bitfield name="ID" caption="Identifier" mask="0x1FFFFFFF"/>
+          <bitfield name="RTR" caption="Remote Transmission Request" mask="0x20000000"/>
+          <bitfield name="XTD" caption="Extended Indentifier" mask="0x40000000"/>
+          <bitfield name="ESI" caption="Error State Indicator" mask="0x80000000"/>
+        </register>
+        <register name="E1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Tx Event FIFO Element 1">
+          <bitfield name="TXTS" caption="Tx Timestamp" mask="0xFFFF"/>
+          <bitfield name="DLC" caption="Data Length Code" mask="0xF0000"/>
+          <bitfield name="BRS" caption="Bit Rate Search" mask="0x100000"/>
+          <bitfield name="FDF" caption="FD Format" mask="0x200000"/>
+          <bitfield name="ET" caption="Event Type" mask="0xC00000" values="E1__ET"/>
+          <bitfield name="MM" caption="Message Marker" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <register-group name="CAN_MRAM_XIDFE" caption="Control Area Network" aligned="4">
+        <register name="F0" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Extended Message ID Filter Element 0">
+          <bitfield name="EFID1" caption="Extended Filter ID 1" mask="0x1FFFFFFF"/>
+          <bitfield name="EFEC" caption="Extended Filter Element Configuration" mask="0xE0000000" values="F0__EFEC"/>
+        </register>
+        <register name="F1" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Extended Message ID Filter Element 1">
+          <bitfield name="EFID2" caption="Extended Filter ID 2" mask="0x1FFFFFFF"/>
+          <bitfield name="EFT" caption="Extended Filter Type" mask="0xC0000000" values="F1__EFT"/>
+        </register>
+      </register-group>
+      <value-group name="TEST__TX">
+        <value name="CORE" caption="TX controlled by CAN core" value="0"/>
+        <value name="SAMPLE" caption="TX monitoring sample point" value="1"/>
+        <value name="DOMINANT" caption="Dominant (0) level at pin CAN_TX" value="2"/>
+        <value name="RECESSIVE" caption="Recessive (1) level at pin CAN_TX" value="3"/>
+      </value-group>
+      <value-group name="TSCC__TSS">
+        <value name="ZERO" caption="Timestamp counter value always 0x0000" value="0"/>
+        <value name="INC" caption="Timestamp counter value incremented by TCP" value="1"/>
+        <value name="EXT" caption="External timestamp counter value used" value="2"/>
+      </value-group>
+      <value-group name="TOCC__TOS">
+        <value name="CONT" caption="Continuout operation" value="0"/>
+        <value name="TXEF" caption="Timeout controlled by TX Event FIFO" value="1"/>
+        <value name="RXF0" caption="Timeout controlled by Rx FIFO 0" value="2"/>
+        <value name="RXF1" caption="Timeout controlled by Rx FIFO 1" value="3"/>
+      </value-group>
+      <value-group name="PSR__LEC">
+        <value name="NONE" caption="No Error" value="0"/>
+        <value name="STUFF" caption="Stuff Error" value="1"/>
+        <value name="FORM" caption="Form Error" value="2"/>
+        <value name="ACK" caption="Ack Error" value="3"/>
+        <value name="BIT1" caption="Bit1 Error" value="4"/>
+        <value name="BIT0" caption="Bit0 Error" value="5"/>
+        <value name="CRC" caption="CRC Error" value="6"/>
+        <value name="NC" caption="No Change" value="7"/>
+      </value-group>
+      <value-group name="PSR__ACT">
+        <value name="SYNC" caption="Node is synchronizing on CAN communication" value="0"/>
+        <value name="IDLE" caption="Node is neither receiver nor transmitter" value="1"/>
+        <value name="RX" caption="Node is operating as receiver" value="2"/>
+        <value name="TX" caption="Node is operating as transmitter" value="3"/>
+      </value-group>
+      <value-group name="PSR__DLEC">
+        <value name="NONE" caption="No Error" value="0"/>
+        <value name="STUFF" caption="Stuff Error" value="1"/>
+        <value name="FORM" caption="Form Error" value="2"/>
+        <value name="ACK" caption="Ack Error" value="3"/>
+        <value name="BIT1" caption="Bit1 Error" value="4"/>
+        <value name="BIT0" caption="Bit0 Error" value="5"/>
+        <value name="CRC" caption="CRC Error" value="6"/>
+        <value name="NC" caption="No Change" value="7"/>
+      </value-group>
+      <value-group name="GFC__ANFE">
+        <value name="RXF0" caption="Accept in Rx FIFO 0" value="0"/>
+        <value name="RXF1" caption="Accept in Rx FIFO 1" value="1"/>
+        <value name="REJECT" caption="Reject" value="2"/>
+      </value-group>
+      <value-group name="GFC__ANFS">
+        <value name="RXF0" caption="Accept in Rx FIFO 0" value="0"/>
+        <value name="RXF1" caption="Accept in Rx FIFO 1" value="1"/>
+        <value name="REJECT" caption="Reject" value="2"/>
+      </value-group>
+      <value-group name="HPMS__MSI">
+        <value name="NONE" caption="No FIFO selected" value="0"/>
+        <value name="LOST" caption="FIFO message lost" value="1"/>
+        <value name="FIFO0" caption="Message stored in FIFO 0" value="2"/>
+        <value name="FIFO1" caption="Message stored in FIFO 1" value="3"/>
+      </value-group>
+      <value-group name="RXF1S__DMS">
+        <value name="IDLE" caption="Idle state" value="0"/>
+        <value name="DBGA" caption="Debug message A received" value="1"/>
+        <value name="DBGB" caption="Debug message A/B received" value="2"/>
+        <value name="DBGC" caption="Debug message A/B/C received, DMA request set" value="3"/>
+      </value-group>
+      <value-group name="RXESC__F0DS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="RXESC__F1DS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="RXESC__RBDS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="TXESC__TBDS">
+        <value name="DATA8" caption="8 byte data field" value="0"/>
+        <value name="DATA12" caption="12 byte data field" value="1"/>
+        <value name="DATA16" caption="16 byte data field" value="2"/>
+        <value name="DATA20" caption="20 byte data field" value="3"/>
+        <value name="DATA24" caption="24 byte data field" value="4"/>
+        <value name="DATA32" caption="32 byte data field" value="5"/>
+        <value name="DATA48" caption="48 byte data field" value="6"/>
+        <value name="DATA64" caption="64 byte data field" value="7"/>
+      </value-group>
+      <value-group name="S0__SFEC">
+        <value name="DISABLE" caption="Disable filter element" value="0"/>
+        <value name="STF0M" caption="Store in Rx FIFO 0 if filter match" value="1"/>
+        <value name="STF1M" caption="Store in Rx FIFO 1 if filter match" value="2"/>
+        <value name="REJECT" caption="Reject ID if filter match" value="3"/>
+        <value name="PRIORITY" caption="Set priority if filter match" value="4"/>
+        <value name="PRIF0M" caption="Set priority and store in FIFO 0 if filter match" value="5"/>
+        <value name="PRIF1M" caption="Set priority and store in FIFO 1 if filter match" value="6"/>
+        <value name="STRXBUF" caption="Store into Rx Buffer" value="7"/>
+      </value-group>
+      <value-group name="S0__SFT">
+        <value name="RANGE" caption="Range filter from SFID1 to SFID2" value="0"/>
+        <value name="DUAL" caption="Dual ID filter for SFID1 or SFID2" value="1"/>
+        <value name="CLASSIC" caption="Classic filter" value="2"/>
+      </value-group>
+      <value-group name="E1__ET">
+        <value name="TXE" caption="Tx event" value="1"/>
+        <value name="TXC" caption="Transmission in spite of cancellation" value="2"/>
+      </value-group>
+      <value-group name="F0__EFEC">
+        <value name="DISABLE" caption="Disable filter element" value="0"/>
+        <value name="STF0M" caption="Store in Rx FIFO 0 if filter match" value="1"/>
+        <value name="STF1M" caption="Store in Rx FIFO 1 if filter match" value="2"/>
+        <value name="REJECT" caption="Reject ID if filter match" value="3"/>
+        <value name="PRIORITY" caption="Set priority if filter match" value="4"/>
+        <value name="PRIF0M" caption="Set priority and store in FIFO 0 if filter match" value="5"/>
+        <value name="PRIF1M" caption="Set priority and store in FIFO 1 if filter match" value="6"/>
+        <value name="STRXBUF" caption="Store into Rx Buffer" value="7"/>
+      </value-group>
+      <value-group name="F1__EFT">
+        <value name="RANGEM" caption="Range filter from EFID1 to EFID2" value="0"/>
+        <value name="DUAL" caption="Dual ID filter for EFID1 or EFID2" value="1"/>
+        <value name="CLASSIC" caption="Classic filter" value="2"/>
+        <value name="RANGE" caption="Range filter from EFID1 to EFID2 with no XIDAM mask" value="3"/>
+      </value-group>
+    </module>
+    <module name="CCL" id="03628" name2="cla_ccl_u2225_v2" version="2b0" caption="Configurable Custom Logic">
+      <register-group name="CCL" caption="Configurable Custom Logic">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1" values="CTRL__SWRST"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2" values="CTRL__ENABLE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40" values="CTRL__RUNSTDBY"/>
+        </register>
+        <register name="SEQCTRL" offset="0x4" rw="RW" size="1" count="2" initval="0x00" caption="SEQ Control x">
+          <bitfield name="SEQSEL" caption="Sequential Selection" mask="0xF" values="SEQCTRL__SEQSEL"/>
+        </register>
+        <register name="LUTCTRL" offset="0x8" rw="RW" size="4" count="4" initval="0x00000000" caption="LUT Control x">
+          <bitfield name="ENABLE" caption="LUT Enable" mask="0x2" values="LUTCTRL__ENABLE"/>
+          <bitfield name="FILTSEL" caption="Filter Selection" mask="0x30" values="LUTCTRL__FILTSEL"/>
+          <bitfield name="EDGESEL" caption="Edge Selection" mask="0x80" values="LUTCTRL__EDGESEL"/>
+          <bitfield name="INSEL0" caption="Input Selection 0" mask="0xF00" values="LUTCTRL__INSEL0"/>
+          <bitfield name="INSEL1" caption="Input Selection 1" mask="0xF000" values="LUTCTRL__INSEL1"/>
+          <bitfield name="INSEL2" caption="Input Selection 2" mask="0xF0000" values="LUTCTRL__INSEL2"/>
+          <bitfield name="INVEI" caption="Inverted Event Input Enable" mask="0x100000" values="LUTCTRL__INVEI"/>
+          <bitfield name="LUTEI" caption="LUT Event Input Enable" mask="0x200000" values="LUTCTRL__LUTEI"/>
+          <bitfield name="LUTEO" caption="LUT Event Output Enable" mask="0x400000" values="LUTCTRL__LUTEO"/>
+          <bitfield name="TRUTH" caption="Truth Value" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <value-group name="CTRL__SWRST">
+        <value name="DISABLE" caption="The peripheral is not reset" value="0"/>
+        <value name="ENABLE" caption="The peripheral is reset" value="1"/>
+      </value-group>
+      <value-group name="CTRL__ENABLE">
+        <value name="DISABLE" caption="The peripheral is disabled" value="0"/>
+        <value name="ENABLE" caption="The peripheral is enabled" value="1"/>
+      </value-group>
+      <value-group name="CTRL__RUNSTDBY">
+        <value name="DISABLE" caption="Generic clock is not required in standby sleep mode" value="0"/>
+        <value name="ENABLE" caption="Generic clock is  required in standby sleep mode" value="1"/>
+      </value-group>
+      <value-group name="SEQCTRL__SEQSEL">
+        <value name="DISABLE" caption="Sequential logic is disabled" value="0"/>
+        <value name="DFF" caption="D flip flop" value="1"/>
+        <value name="JK" caption="JK flip flop" value="2"/>
+        <value name="LATCH" caption="D latch" value="3"/>
+        <value name="RS" caption="RS latch" value="4"/>
+      </value-group>
+      <value-group name="LUTCTRL__ENABLE">
+        <value name="DISABLE" caption="LUT block is disabled" value="0"/>
+        <value name="ENABLE" caption="LUT block is enabled" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__FILTSEL">
+        <value name="DISABLE" caption="Filter disabled" value="0"/>
+        <value name="SYNCH" caption="Synchronizer enabled" value="1"/>
+        <value name="FILTER" caption="Filter enabled" value="2"/>
+      </value-group>
+      <value-group name="LUTCTRL__EDGESEL">
+        <value name="DISABLE" caption="Edge detector is disabled" value="0"/>
+        <value name="ENABLE" caption="Edge detector is enabled" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__INSEL0">
+        <value name="MASK" caption="Masked input" value="0x0"/>
+        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
+        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
+        <value name="EVENT" caption="Event input source" value="0x3"/>
+        <value name="IO" caption="I/O pin input source" value="0x4"/>
+        <value name="PERSEL0" caption="Peripheral 0 input source" value="0x5"/>
+        <value name="PERSEL1" caption="Peripheral 1 input source" value="0x6"/>
+        <value name="PERSEL2" caption="Peripheral 2 input source" value="0x7"/>
+        <value name="PERSEL3" caption="Peripheral 3 input source" value="0x8"/>
+        <value name="PERSEL4" caption="Peripheral 4 input source" value="0x9"/>
+        <value name="PERSEL5" caption="Peripheral 5 input source" value="0xA"/>
+        <value name="ASYNCEVENT" caption="Asynchronous event input source. The EVENT input will bypass edge detection logic." value="0xB"/>
+      </value-group>
+      <value-group name="LUTCTRL__INSEL1">
+        <value name="MASK" caption="Masked input" value="0x0"/>
+        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
+        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
+        <value name="EVENT" caption="Event input source" value="0x3"/>
+        <value name="IO" caption="I/O pin input source" value="0x4"/>
+        <value name="PERSEL0" caption="Peripheral 0 input source" value="0x5"/>
+        <value name="PERSEL1" caption="Peripheral 1 input source" value="0x6"/>
+        <value name="PERSEL2" caption="Peripheral 2 input source" value="0x7"/>
+        <value name="PERSEL3" caption="Peripheral 3 input source" value="0x8"/>
+        <value name="PERSEL4" caption="Peripheral 4 input source" value="0x9"/>
+        <value name="PERSEL5" caption="Peripheral 5 input source" value="0xA"/>
+        <value name="ASYNCEVENT" caption="Asynchronous event input source. The EVENT input will bypass edge detection logic." value="0xB"/>
+      </value-group>
+      <value-group name="LUTCTRL__INSEL2">
+        <value name="MASK" caption="Masked input" value="0x0"/>
+        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
+        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
+        <value name="EVENT" caption="Event input source" value="0x3"/>
+        <value name="IO" caption="I/O pin input source" value="0x4"/>
+        <value name="PERSEL0" caption="Peripheral 0 input source" value="0x5"/>
+        <value name="PERSEL1" caption="Peripheral 1 input source" value="0x6"/>
+        <value name="PERSEL2" caption="Peripheral 2 input source" value="0x7"/>
+        <value name="PERSEL3" caption="Peripheral 3 input source" value="0x8"/>
+        <value name="PERSEL4" caption="Peripheral 4 input source" value="0x9"/>
+        <value name="PERSEL5" caption="Peripheral 5 input source" value="0xA"/>
+        <value name="ASYNCEVENT" caption="Asynchronous event input source. The EVENT input will bypass edge detection logic." value="0xB"/>
+      </value-group>
+      <value-group name="LUTCTRL__INVEI">
+        <value name="NORMAL" caption="Incoming event is not inverted" value="0"/>
+        <value name="INVERTED" caption="Incoming event is inverted" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__LUTEI">
+        <value name="DISABLE" caption="LUT incoming event is disabled" value="0"/>
+        <value name="ENABLE" caption="LUT incoming event is enabled" value="1"/>
+      </value-group>
+      <value-group name="LUTCTRL__LUTEO">
+        <value name="DISABLE" caption="LUT event output is disabled" value="0"/>
+        <value name="ENABLE" caption="LUT event output is enabled" value="1"/>
+      </value-group>
+    </module>
+    <module name="CoreDebug" id="SYSTEM_IP" version="1.0.0" caption="Debug Control Block">
+      <register-group name="CoreDebug" caption="Debug Control Block">
+        <register name="DHCSR" offset="0x0" rw="RW" size="4" access-size="4" caption="Debug Halting Control and Status Register">
+          <bitfield name="C_DEBUGEN" caption="Enable Halting debug" mask="0x1"/>
+          <bitfield name="C_HALT" caption="Halt processor" mask="0x2"/>
+          <bitfield name="C_STEP" caption="Enable single step" mask="0x4"/>
+          <bitfield name="C_MASKINTS" caption="Mask PendSV, SysTick and external configurable interrupts" mask="0x8"/>
+          <bitfield name="S_SNAPSTALL" caption="Snap stall control" mask="0x20"/>
+          <bitfield name="S_REGRDY" caption="Register ready status" mask="0x10000"/>
+          <bitfield name="S_HALT" caption="Halted status" mask="0x20000"/>
+          <bitfield name="S_SLEEP" caption="Sleeping status" mask="0x40000"/>
+          <bitfield name="S_LOCKUP" caption="Lockup status" mask="0x80000"/>
+          <bitfield name="S_SDE" caption="Secure debug enabled" mask="0x100000"/>
+          <bitfield name="S_RETIRE_ST" caption="Retire sticky status" mask="0x1000000"/>
+          <bitfield name="S_RESET_ST" caption="Reset sticky status" mask="0x2000000"/>
+          <bitfield name="S_RESTART_ST" caption="Restart sticky status" mask="0x4000000"/>
+        </register>
+        <register name="DCRSR" offset="0x4" rw="W" size="4" access-size="4" caption="Debug Core Register Select Register">
+          <bitfield name="REGSEL" caption="Register selector" mask="0x7F"/>
+          <bitfield name="REGWnR" caption="Register write/not-read access" mask="0x10000"/>
+        </register>
+        <register name="DEMCR" offset="0xC" rw="RW" size="4" access-size="4" caption="Debug Exception and Monitor Control Register">
+          <bitfield name="VC_CORERESET" caption="Core reset Halting debug vector catch enable" mask="0x1"/>
+          <bitfield name="VC_MMERR" caption="MemManage exception Halting debug vector catch enable" mask="0x10"/>
+          <bitfield name="VC_NOCPERR" caption="UsageFault exception coprocessor access Halting debug vector catch enable" mask="0x20"/>
+          <bitfield name="VC_CHKERR" caption="UsageFault exception checking error Halting debug vector catch enable" mask="0x40"/>
+          <bitfield name="VC_STATERR" caption="UsageFault exception state information error Halting debug vector catch enable" mask="0x80"/>
+          <bitfield name="VC_BUSERR" caption="BusFault exception Halting debug vector catch enable" mask="0x100"/>
+          <bitfield name="VC_INTERR" caption="Excception entry and return faults Halting debug vector catch enable" mask="0x200"/>
+          <bitfield name="VC_HARDERR" caption="HardFault exception Halting debug vector catch enable" mask="0x400"/>
+          <bitfield name="VC_SFERR" caption="SecureFault exception Halting debug vector catch enable" mask="0x800"/>
+          <bitfield name="MON_EN" caption="DebugMonitor enable" mask="0x10000"/>
+          <bitfield name="MON_PEND" caption="DebugMonitor pending state" mask="0x20000"/>
+          <bitfield name="MON_STEP" caption="Enable DebugMonitor stepping" mask="0x40000"/>
+          <bitfield name="MON_REQ" caption="DebugMonitor semaphore bit" mask="0x80000"/>
+          <bitfield name="SDME" caption="Secure DebugMonitor enable" mask="0x100000"/>
+          <bitfield name="TRCENA" caption="Global DWT and ITM features enable" mask="0x1000000"/>
+        </register>
+        <register name="DSCSR" offset="0x18" rw="RW" size="4" access-size="4" caption="Debug Security Control and Status Register">
+          <bitfield name="SBRSELEN" caption="Secure Banked register select enable" mask="0x1"/>
+          <bitfield name="SBRSEL" caption="Secure Banked register select" mask="0x2"/>
+          <bitfield name="CDS" caption="Current domain Secure" mask="0x10000"/>
+          <bitfield name="CDSKEY" caption="CDS field write-enable key" mask="0x20000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="DIB" id="SYSTEM_IP" version="1.0.0" caption="Debug Identification Block">
+      <register-group name="DIB" caption="Debug Identification Block">
+        <register name="DLAR" offset="0x0" rw="W" size="4" access-size="4" caption="SCS Software Lock Access Register">
+          <bitfield name="KEY" caption="Lock access control" mask="0xFFFFFFFF" values="DLAR__KEY"/>
+        </register>
+        <register name="DLSR" offset="0x4" rw="R" size="4" access-size="4" caption="SCS Software Lock Status Register">
+          <bitfield name="SLI" caption="Software Lock implemented" mask="0x1"/>
+          <bitfield name="SLK" caption="Software Lock status" mask="0x2"/>
+          <bitfield name="nTT" caption="Not thirty-two bit" mask="0x4"/>
+        </register>
+        <register name="DAUTHSTATUS" offset="0x8" rw="R" size="4" access-size="4" caption="Debug Authentication Status Register">
+          <bitfield name="NSID" caption="" mask="0x3" values="DAUTHSTATUS__NSID"/>
+          <bitfield name="NSNID" caption="" mask="0xC" values="DAUTHSTATUS__NSNID"/>
+          <bitfield name="SID" caption="" mask="0x30" values="DAUTHSTATUS__SID"/>
+          <bitfield name="SNID" caption="" mask="0xC0" values="DAUTHSTATUS__SNID"/>
+        </register>
+        <register name="DDEVARCH" offset="0xC" rw="R" size="4" access-size="4" initval="0x47702A04" caption="SCS Device Architecture Register">
+          <bitfield name="ARCHPART" caption="Architecture Part" mask="0xFFF"/>
+          <bitfield name="ARCHVER" caption="Architecture Version" mask="0xF000"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF0000"/>
+          <bitfield name="PRESENT" caption="DEVARCH Present" mask="0x100000"/>
+          <bitfield name="ARCHITECT" caption="Architect" mask="0xFFE00000"/>
+        </register>
+        <register name="DDEVTYPE" offset="0x1C" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Device Type Register">
+          <bitfield name="MAJOR" caption="Major type" mask="0xF"/>
+          <bitfield name="SUB" caption="Sub-type" mask="0xF0"/>
+        </register>
+        <register name="DPIDR4" offset="0x20" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 4">
+          <bitfield name="DES_2" caption="JEP106 continuation code" mask="0xF"/>
+          <bitfield name="SIZE" caption="4KB count" mask="0xF0"/>
+        </register>
+        <register name="DPIDR5" offset="0x24" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Peripheral Identification Register 5"/>
+        <register name="DPIDR6" offset="0x28" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Peripheral Identification Register 6"/>
+        <register name="DPIDR7" offset="0x2C" rw="R" size="4" access-size="4" initval="0x00000000" caption="SCS Peripheral Identification Register 7"/>
+        <register name="DPIDR0" offset="0x30" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 0">
+          <bitfield name="PART_0" caption="Part number bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="DPIDR1" offset="0x34" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 1">
+          <bitfield name="PART_1" caption="Part number bits[11:8]" mask="0xF"/>
+          <bitfield name="DES_0" caption="JEP106 identification code bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="DPIDR2" offset="0x38" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 2">
+          <bitfield name="DES_1" caption="JEP106 identification code bits[6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="JEDEC assignee value is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Component revision" mask="0xF0"/>
+        </register>
+        <register name="DPIDR3" offset="0x3C" rw="R" size="4" access-size="4" caption="SCS Peripheral Identification Register 3">
+          <bitfield name="CMOD" caption="Customer Modified" mask="0xF"/>
+          <bitfield name="REVAND" caption="RevAnd" mask="0xF0"/>
+        </register>
+        <register name="DCIDR0" offset="0x40" rw="R" size="4" access-size="4" initval="0x0000000D" caption="SCS Component Identification Register 0">
+          <bitfield name="PRMBL_0" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DCIDR1" offset="0x44" rw="R" size="4" access-size="4" initval="0x00000090" caption="SCS Component Identification Register 1">
+          <bitfield name="PRMBL_1" caption="CoreSight component identification preamble" mask="0xF"/>
+          <bitfield name="CLASS" caption="CoreSight component class" mask="0xF0"/>
+        </register>
+        <register name="DCIDR2" offset="0x48" rw="R" size="4" access-size="4" initval="0x00000005" caption="SCS Component Identification Register 2">
+          <bitfield name="PRMBL_2" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DCIDR3" offset="0x4C" rw="R" size="4" access-size="4" initval="0x000000B1" caption="SCS Component Identification Register 3">
+          <bitfield name="PRMBL_3" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="DLAR__KEY">
+        <value name="UNLOCK" caption="Unlock key value" value="0xC5ACCE55"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__NSID">
+        <value name="NO" caption="Non-secure invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Non-secure invasive debug allowed" value="3"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__NSNID">
+        <value name="NO" caption="Non-secure non-invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Non-secure non-invasive debug allowed" value="3"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__SID">
+        <value name="NOSEC" caption="Security Extension not implemented" value="0"/>
+        <value name="NO" caption="Secure invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Secure invasive debug allowed" value="3"/>
+      </value-group>
+      <value-group name="DAUTHSTATUS__SNID">
+        <value name="NOSEC" caption="Security Extension not implemented" value="0"/>
+        <value name="NO" caption="Secure non-invasive debug prohibited" value="2"/>
+        <value name="YES" caption="Secure non-invasive debug allowed" value="3"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="dma_u2223_v2" name2="dma_u2223_v2" version="2i0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x2A" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0x7"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0x700"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0x70000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0x7000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0x7"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0x7"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Channel run in standby" mask="0x40"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+      <value-group name="CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (BEATSIZE+1) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (BEATSIZE+1) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (BEATSIZE+1) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (BEATSIZE+1) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (BEATSIZE+1) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (BEATSIZE+1) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (BEATSIZE+1) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (BEATSIZE+1) * 128" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="04465" name2="icd_dsu_v1" version="1a0" caption="Polaris Device Services Unit Macro DOS">
+      <register-group name="DSU" caption="Polaris Device Services Unit Macro DOS">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A REGISTER">
+          <bitfield name="PRIV" caption="Privileged Access Only for APB Interface" mask="0x4" values="CTRLA__PRIV"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B REGISTER">
+          <bitfield name="DCCDMALVL0" caption="DMA Trigger n Level" mask="0x1" values="CTRLB__DCCDMALVL"/>
+          <bitfield name="DCCDMALVL1" caption="DMA Trigger n Level" mask="0x2" values="CTRLB__DCCDMALVL"/>
+          <bitfield name="MISC" caption="Device Specific Configuration Register" mask="0xFFFFFF00"/>
+        </register>
+        <register name="CTRLC" offset="0x100" rw="RW" size="4" initval="0x00000000" caption="Control C REGISTER">
+          <bitfield name="DBGRW0" caption="CPUn Debug R/W" mask="0x1" values="CTRLC__DBGRW"/>
+        </register>
+        <register name="STATUSA" offset="0x104" rw="RW" size="4" atomic-op="clear:STATUSA" initval="0x00000000" caption="Status A REGISTER">
+          <bitfield name="DONE" caption="Done Status" mask="0x1" values="STATUSA__DONE"/>
+          <bitfield name="BERR" caption="Bus Error Status" mask="0x4" values="STATUSA__BERR"/>
+          <bitfield name="PERR" caption="Protection Error Status" mask="0x8" values="STATUSA__PERR"/>
+          <bitfield name="ROMCRC" caption="Boot ROM CRC Self-Check Status" mask="0xC0" values="STATUSA__ROMCRC"/>
+          <bitfield name="CRSTEXT0" caption="CPUx Reset Extension Status" mask="0x100" values="STATUSA__CRSTEXT"/>
+          <bitfield name="BREXT0" caption="BootRom 0 Phase Extension Status" mask="0x10000" values="STATUSA__BREXT"/>
+        </register>
+        <register name="STATUSB" offset="0x108" rw="R" size="4" initval="0x00000000" caption="Status B REGISTER">
+          <bitfield name="BCCD0" caption="Boot ROM Communication Channel 0 Dirty" mask="0x1" values="STATUSB__BCCD"/>
+          <bitfield name="BCCD1" caption="Boot ROM Communication Channel 1 Dirty" mask="0x2" values="STATUSB__BCCD"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4" values="STATUSB__DCCD"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8" values="STATUSB__DCCD"/>
+          <bitfield name="DBGPRES" caption="Debugger Present Status" mask="0x100" values="STATUSB__DBGPRES"/>
+          <bitfield name="HPS" caption="Hot-Plugging Status" mask="0x400" values="STATUSB__HPS"/>
+        </register>
+        <register name="BCC" offset="0x110" rw="RW" size="4" count="2" initval="0x00000000" caption="Boot ROM Channel n REGISTER">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x118" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n REGISTER">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x120" rw="RW" size="4" initval="0x00000053" caption="Device Identification Register">
+          <bitfield name="FV" caption="Fixed Value of 1" mask="0x1"/>
+          <bitfield name="MANID" caption="JEDEC Manufacture ID" mask="0xFFE"/>
+          <bitfield name="PNDID" caption="Part Number Device ID" mask="0xFF000"/>
+          <bitfield name="PNMID" caption="Part Number Mask ID" mask="0xFF00000"/>
+          <bitfield name="VER" caption="Version Code" mask="0xF0000000"/>
+        </register>
+        <register name="DAL" offset="0x124" rw="R" size="4" initval="0x00000000" caption="Debugger Access Level REGISTER">
+          <bitfield name="CPU0" caption="CPU 0 Debugger Access Level" mask="0x3" values="DAL__CPU0"/>
+          <bitfield name="CPU1" caption="CPU n Debugger Access Level" mask="0xC" values="DAL__CPU"/>
+          <bitfield name="CPU2" caption="CPU n Debugger Access Level" mask="0x30" values="DAL__CPU"/>
+          <bitfield name="CPU3" caption="CPU n Debugger Access Level" mask="0xC0" values="DAL__CPU"/>
+        </register>
+        <register name="ENTRY0" offset="0x1000" rw="R" size="4" initval="0x9C0FE002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY0__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY0__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY1" offset="0x1004" rw="R" size="4" initval="0xBBFFF002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY1__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY1__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY2" offset="0x1008" rw="R" size="4" initval="0xBBFFF002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY2__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY2__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY3" offset="0x100C" rw="R" size="4" initval="0xBBFFF002" caption="CoreSight ROM Table Entry N Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY3__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY3__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY4" offset="0x1010" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 4 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY4__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY4__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY5" offset="0x1014" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 5 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY5__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY5__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY6" offset="0x1018" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 6 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY6__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY6__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="ENTRY7" offset="0x101C" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 7 Register">
+          <bitfield name="EPRES" caption="CoreSight Entry Present" mask="0x1" values="ENTRY7__EPRES"/>
+          <bitfield name="FMT" caption="CoreSight Rom Table Format" mask="0x2" values="ENTRY7__FMT"/>
+          <bitfield name="ADDOFF" caption="CoreSight ROM Table Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Memory Type Register">
+          <bitfield name="SYSMEM" caption="CoreSight System Memory Present" mask="0x1" values="MEMTYPE__SYSMEM"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 4 Register">
+          <bitfield name="DES2" caption="CoreSight JEP106 Continuation Code" mask="0xF"/>
+          <bitfield name="SIZE" caption="CoreSight Size" mask="0xF0"/>
+        </register>
+        <register name="PID5" offset="0x1FD4" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 5 Register">
+          <bitfield name="RES0" caption="CoreSight Reserved Field" mask="0xFF"/>
+        </register>
+        <register name="PID6" offset="0x1FD8" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 6 Register">
+          <bitfield name="RES0" caption="CoreSight Reserved Field" mask="0xFF"/>
+        </register>
+        <register name="PID7" offset="0x1FDC" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 7 Register">
+          <bitfield name="RES0" caption="CoreSight Reserved Field" mask="0xFF"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="CoreSight Peripheral Identification 0 Register">
+          <bitfield name="PART0" caption="CoreSight Part Number Bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x0000009C" caption="CoreSight Peripheral Identification 1 Register">
+          <bitfield name="PART1" caption="CoreSight Part Number Bits[11:8]" mask="0xF"/>
+          <bitfield name="DES0" caption="CoreSight JEP106 Identification Code Bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x0000000A" caption="CoreSight Peripheral Identification 2 Register">
+          <bitfield name="DES1" caption="CoreSight JEP106 Identification Code Bits [6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="CoreSight JEDEC Assignment" mask="0x8"/>
+          <bitfield name="REVISION" caption="CoreSight Revision" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="CoreSight Peripheral Identification 3 Register">
+          <bitfield name="CMOD" caption="CoreSight Custom Modifier 0" mask="0xF"/>
+          <bitfield name="REVAND" caption="CoreSight REVAND" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="CoreSight Component Identification 0 Register">
+          <bitfield name="PRMBL0" caption="CoreSight Preamble 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="CoreSight Component Identification 1 Register">
+          <bitfield name="PRMBL1" caption="CoreSight Preamble 1" mask="0xF"/>
+          <bitfield name="CCLASS" caption="CoreSight Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="CoreSight Component Identification 2 Register">
+          <bitfield name="PRMBL2" caption="CoreSight Preamble 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="CoreSight Component Identification 3 Register">
+          <bitfield name="PRMBL3" caption="CoreSight Preamble 3" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="0" caption="Internal Address Space registers accessible in privileged and unprivileged modes. Test functions generate unprivileged requests." value="0"/>
+        <value name="1" caption="Internal Address Space registers only accessible in privileged mode. Test functions generate privileged requests." value="1"/>
+      </value-group>
+      <value-group name="CTRLB__DCCDMALVL">
+        <value name="EMPTY" caption="Trigger n rises when DCCn is read and falls when it is written" value="0"/>
+        <value name="FULL" caption="Trigger n rises when DCCn is written and falls when it is read" value="1"/>
+      </value-group>
+      <value-group name="CTRLC__DBGRW">
+        <value name="0" caption="Allow debugger accesses through CPUn to carry the debug attribute (i.e debugger reads are non-destructive)." value="0"/>
+        <value name="1" caption="Debugger accesses through CPUn do not carry the debug attribute (i.e debugger reads are destructive)." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__DONE">
+        <value name="0" caption="DSU is executing a command or idle." value="0"/>
+        <value name="1" caption="TCTRL.CMD command completed" value="1"/>
+      </value-group>
+      <value-group name="STATUSA__BERR">
+        <value name="0" caption="No bus error detected" value="0"/>
+        <value name="1" caption="Bus error incurred while performing the DSU command." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__PERR">
+        <value name="0" caption="No protection error detected" value="0"/>
+        <value name="1" caption="Invalid command written to TCTRL.CMD, partial write to the upper or lower bytes of TCTRL.CMD, or invalid key written to SAFEDOOR." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__ROMCRC">
+        <value name="0" caption="CRC is in progress" value="0"/>
+        <value name="1" caption="CRC completed but failed indicating possible issue with the ROM content. System held in lockup state." value="1"/>
+        <value name="2" caption="CRC completed and passed" value="2"/>
+        <value name="3" caption="CRC never executed because user disabled CRC check through fuse settings." value="3"/>
+      </value-group>
+      <value-group name="STATUSA__CRSTEXT">
+        <value name="0" caption="CPUx released from reset extension." value="0"/>
+        <value name="1" caption="CPUx held in reset extension. Set on Cold-Plugging detection." value="1"/>
+      </value-group>
+      <value-group name="STATUSA__BREXT">
+        <value name="0" caption="Boot ROM Phase Extension released for CPUx." value="0"/>
+        <value name="1" caption="Boot ROM Phase Extension for CPUx. Set on Cold-Plugging detection." value="1"/>
+      </value-group>
+      <value-group name="STATUSB__BCCD">
+        <value name="0" caption="BCCDx.DATA register was read from." value="0"/>
+        <value name="1" caption="BCCDx.DATA register was written to." value="1"/>
+      </value-group>
+      <value-group name="STATUSB__DCCD">
+        <value name="0" caption="DCCDx.DATA register was read from." value="0"/>
+        <value name="1" caption="DCCDx.DATA register was written to." value="1"/>
+      </value-group>
+      <value-group name="STATUSB__DBGPRES">
+        <value name="0" caption="No debugger detected" value="0"/>
+        <value name="1" caption="Debugger probe detected" value="1"/>
+      </value-group>
+      <value-group name="STATUSB__HPS">
+        <value name="0" caption="Hot-Plugging inactive" value="0"/>
+        <value name="1" caption="Hot-Plugging active" value="1"/>
+      </value-group>
+      <value-group name="DAL__CPU0">
+        <value name="SECURED" caption="Debugger targeting CPU0 domain can only access the DSU external address space otherwise debugger access is disabled" value="0"/>
+        <value name="NS_DEBUG" caption="Debugger can access only non-secure regions" value="1"/>
+        <value name="FULL_DEBUG" caption="Debugger can access secure and non-secure regions" value="2"/>
+      </value-group>
+      <value-group name="DAL__CPU">
+        <value name="SECURED" caption="Debugger access is disabled" value="0"/>
+        <value name="NS_DEBUG" caption="Debugger can access only non-secure regions" value="1"/>
+        <value name="FULL_DEBUG" caption="Debugger has full access to debug CPUn" value="2"/>
+        <value name="UNIMPLEMENTED" caption="Unimplemented CPU" value="3"/>
+      </value-group>
+      <value-group name="ENTRY0__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY0__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY1__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY1__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY2__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY2__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY3__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY3__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY4__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY4__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY5__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY5__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY6__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY6__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="ENTRY7__EPRES">
+        <value name="0" caption="Entry not present" value="0"/>
+        <value name="1" caption="Entry present" value="1"/>
+      </value-group>
+      <value-group name="ENTRY7__FMT">
+        <value name="0" caption="8-bit format" value="0"/>
+        <value name="1" caption="32-bit format" value="1"/>
+      </value-group>
+      <value-group name="MEMTYPE__SYSMEM">
+        <value name="0" caption="System memory not present on bus. This is a dedicated debug bus." value="0"/>
+        <value name="1" caption="System memory is also present on this bus" value="1"/>
+      </value-group>
+    </module>
+    <module name="DWT" id="SYSTEM_IP" version="1.0.0" caption="Data Watchpoint and Trace">
+      <register-group name="COMPARATOR" size="0x10">
+        <register name="DWT_COMP" offset="0x0" rw="RW" size="4" access-size="4" caption="DWT Comparator Register n">
+          <bitfield name="VALUE" caption="Cycle/PC/data value or data address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DWT_FUNCTION" offset="0x8" rw="RW" size="4" access-size="4" caption="DWT Function Register x">
+          <bitfield name="MATCH" caption="Match type" mask="0xF"/>
+          <bitfield name="ACTION" caption="Action on match" mask="0x30"/>
+          <bitfield name="DATAVSIZE" caption="Data value size" mask="0xC00"/>
+          <bitfield name="MATCHED" caption="Comparator matched" mask="0x1000000"/>
+          <bitfield name="ID" caption="Identify capability" mask="0xF8000000"/>
+        </register>
+      </register-group>
+      <register-group name="DWT" caption="Data Watchpoint and Trace">
+        <register name="DWT_CTRL" offset="0x0" rw="RW" size="4" access-size="4" initval="0x0B000000" caption="DWT Control Register">
+          <bitfield name="CYCCNTENA" caption="CYCCNT enable" mask="0x1"/>
+          <bitfield name="POSTPRESET" caption="POSTCNT preset" mask="0x1E"/>
+          <bitfield name="POSTINIT" caption="POSTCNT initial" mask="0x1E0"/>
+          <bitfield name="CYCTAP" caption="Cycle count tap" mask="0x200"/>
+          <bitfield name="SYNCTAP" caption="Synchronization tap" mask="0xC00"/>
+          <bitfield name="PCSAMPLENA" caption="PC sample enable" mask="0x1000"/>
+          <bitfield name="EXCTRCENA" caption="Exception trace enable" mask="0x10000"/>
+          <bitfield name="CPIEVTENA" caption="CPI event enable" mask="0x20000"/>
+          <bitfield name="EXCEVTENA" caption="Exception event enable" mask="0x40000"/>
+          <bitfield name="SLEEPEVTENA" caption="Sleep event enable" mask="0x80000"/>
+          <bitfield name="LSUEVTENA" caption="LSU event enable" mask="0x100000"/>
+          <bitfield name="FOLDEVTENA" caption="Fold event enable" mask="0x200000"/>
+          <bitfield name="CYCEVTENA" caption="Cycle event enable" mask="0x400000"/>
+          <bitfield name="CYCDISS" caption="Cycle counter disabled secure" mask="0x800000"/>
+          <bitfield name="NOPRFCNT" caption="No profile counters" mask="0x1000000"/>
+          <bitfield name="NOCYCCNT" caption="No cycle count" mask="0x2000000"/>
+          <bitfield name="NOEXTTRIG" caption="No external triggers" mask="0x4000000"/>
+          <bitfield name="NOTRCPKT" caption="No trace packets" mask="0x8000000"/>
+          <bitfield name="NUMCOMP" caption="Number of comparators" mask="0xF0000000"/>
+        </register>
+        <register name="DWT_PCSR" offset="0x1C" rw="R" size="4" access-size="4" caption="DWT Program Counter Sample Register">
+          <bitfield name="EIASAMPLE" caption="Executed instruction address sample" mask="0xFFFFFFFF"/>
+        </register>
+        <register-group name="COMPARATOR" name-in-module="COMPARATOR" offset="0x020" size="0x10" count="2"/>
+        <register name="DWT_LAR" offset="0xFB0" rw="W" size="4" access-size="4" caption="DWT Software Lock Access Register">
+          <bitfield name="KEY" caption="Lock access control" mask="0xFFFFFFFF" values="DWT_LAR__KEY"/>
+        </register>
+        <register name="DWT_LSR" offset="0xFB4" rw="R" size="4" access-size="4" caption="DWT Software Lock Status Register">
+          <bitfield name="SLI" caption="Software Lock implemented" mask="0x1"/>
+          <bitfield name="SLK" caption="Software Lock status" mask="0x2"/>
+          <bitfield name="nTT" caption="Not thirty-two bit" mask="0x4"/>
+        </register>
+        <register name="DWT_DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" initval="0x47701A02" caption="DWT Device Architecture Register">
+          <bitfield name="ARCHPART" caption="Architecture Part" mask="0xFFF"/>
+          <bitfield name="ARCHVER" caption="Architecture Version" mask="0xF000"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF0000"/>
+          <bitfield name="PRESENT" caption="DEVARCH Present" mask="0x100000"/>
+          <bitfield name="ARCHITECT" caption="Architect" mask="0xFFE00000"/>
+        </register>
+        <register name="DWT_DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Device Type Register">
+          <bitfield name="MAJOR" caption="Major type" mask="0xF"/>
+          <bitfield name="SUB" caption="Sub-type" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR4" offset="0xFD0" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 4">
+          <bitfield name="DES_2" caption="JEP106 continuation code" mask="0xF"/>
+          <bitfield name="SIZE" caption="4KB count" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR5" offset="0xFD4" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Peripheral Identification Register 5"/>
+        <register name="DWT_PIDR6" offset="0xFD8" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Peripheral Identification Register 6"/>
+        <register name="DWT_PIDR7" offset="0xFDC" rw="R" size="4" access-size="4" initval="0x00000000" caption="DWT Peripheral Identification Register 7"/>
+        <register name="DWT_PIDR0" offset="0xFE0" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 0">
+          <bitfield name="PART_0" caption="Part number bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="DWT_PIDR1" offset="0xFE4" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 1">
+          <bitfield name="PART_1" caption="Part number bits[11:8]" mask="0xF"/>
+          <bitfield name="DES_0" caption="JEP106 identification code bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR2" offset="0xFE8" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 2">
+          <bitfield name="DES_1" caption="JEP106 identification code bits[6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="JEDEC assignee value is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Component revision" mask="0xF0"/>
+        </register>
+        <register name="DWT_PIDR3" offset="0xFEC" rw="R" size="4" access-size="4" caption="DWT Peripheral Identification Register 3">
+          <bitfield name="CMOD" caption="Customer Modified" mask="0xF"/>
+          <bitfield name="REVAND" caption="RevAnd" mask="0xF0"/>
+        </register>
+        <register name="DWT_CIDR0" offset="0xFF0" rw="R" size="4" access-size="4" initval="0x0000000D" caption="DWT Component Identification Register 0">
+          <bitfield name="PRMBL_0" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DWT_CIDR1" offset="0xFF4" rw="R" size="4" access-size="4" initval="0x00000090" caption="DWT Component Identification Register 1">
+          <bitfield name="PRMBL_1" caption="CoreSight component identification preamble" mask="0xF"/>
+          <bitfield name="CLASS" caption="CoreSight component class" mask="0xF0"/>
+        </register>
+        <register name="DWT_CIDR2" offset="0xFF8" rw="R" size="4" access-size="4" initval="0x00000005" caption="DWT Component Identification Register 2">
+          <bitfield name="PRMBL_2" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="DWT_CIDR3" offset="0xFFC" rw="R" size="4" access-size="4" initval="0x000000B1" caption="DWT Component Identification Register 3">
+          <bitfield name="PRMBL_3" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="DWT_LAR__KEY">
+        <value name="UNLOCK" caption="Unlock key value" value="0xC5ACCE55"/>
+      </value-group>
+    </module>
+    <module name="EIC" id="03706" name2="int_eic_u2804_v1" version="1b0" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKSEL" caption="Clock Selection" mask="0x10" values="CTRLA__CKSEL"/>
+        </register>
+        <register name="NMICTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense Configuration" mask="0x7" values="NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+          <bitfield name="NMIASYNCH" caption="Asynchronous Edge Detection Mode" mask="0x10" values="NMICTRL__NMIASYNCH"/>
+        </register>
+        <register name="NMIFLAG" offset="0x2" rw="RW" size="2" atomic-op="clear:NMIFLAG" initval="0x0000" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x4" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy Status" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO" caption="External Interrupt Event Output Enable" mask="0xFFFF"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT" caption="External Interrupt Enable" mask="0xFFFF"/>
+          <bitfield name="NSCHK" caption="Non-secure Check Interrupt Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT" caption="External Interrupt Enable" mask="0xFFFF"/>
+          <bitfield name="NSCHK" caption="Non-secure Check Interrupt Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT" caption="External Interrupt" mask="0xFFFF"/>
+          <bitfield name="NSCHK" caption="Non-secure Check Interrupt" mask="0x80000000"/>
+        </register>
+        <register name="ASYNCH" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="External Interrupt Asynchronous Mode">
+          <bitfield name="ASYNCH" caption="Asynchronous Edge Detection Mode" mask="0xFFFF" values="ASYNCH__ASYNCH"/>
+        </register>
+        <register name="CONFIG" offset="0x1C" rw="RW" size="4" count="2" initval="0x00000000" caption="External Interrupt Sense Configuration">
+          <bitfield name="SENSE0" caption="Input Sense Configuration 0" mask="0x7" values="CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter Enable 0" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense Configuration 1" mask="0x70" values="CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter Enable 1" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense Configuration 2" mask="0x700" values="CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter Enable 2" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense Configuration 3" mask="0x7000" values="CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter Enable 3" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense Configuration 4" mask="0x70000" values="CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter Enable 4" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense Configuration 5" mask="0x700000" values="CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter Enable 5" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense Configuration 6" mask="0x7000000" values="CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter Enable 6" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense Configuration 7" mask="0x70000000" values="CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter Enable 7" mask="0x80000000"/>
+        </register>
+        <register name="DEBOUNCEN" offset="0x30" rw="RW" size="4" initval="0x00000000" caption="Debouncer Enable">
+          <bitfield name="DEBOUNCEN" caption="Debouncer Enable" mask="0xFFFF"/>
+        </register>
+        <register name="DPRESCALER" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Debouncer Prescaler">
+          <bitfield name="PRESCALER0" caption="Debouncer Prescaler" mask="0x7" values="DPRESCALER__PRESCALER"/>
+          <bitfield name="STATES0" caption="Debouncer number of states" mask="0x8" values="DPRESCALER__STATES"/>
+          <bitfield name="PRESCALER1" caption="Debouncer Prescaler" mask="0x70" values="DPRESCALER__PRESCALER"/>
+          <bitfield name="STATES1" caption="Debouncer number of states" mask="0x80" values="DPRESCALER__STATES"/>
+          <bitfield name="TICKON" caption="Pin Sampler frequency selection" mask="0x10000" values="DPRESCALER__TICKON"/>
+        </register>
+        <register name="PINSTATE" offset="0x38" rw="R" size="4" initval="0x00000000" caption="Pin State">
+          <bitfield name="PINSTATE" caption="Pin State" mask="0xFFFF"/>
+        </register>
+        <register name="NSCHK" offset="0x3C" rw="RW" size="4" initval="0x00000000" caption="Non-secure Interrupt Check Enable">
+          <bitfield name="EXTINT" caption="External Interrupt Nonsecure Check Enable" mask="0xFFFF"/>
+          <bitfield name="NMI" caption="Non-Maskable External Interrupt Nonsecure Check Enable" mask="0x80000000"/>
+        </register>
+        <register name="NONSEC" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Non-secure Interrupt">
+          <bitfield name="EXTINT" caption="External Interrupt Nonsecure Enable" mask="0xFFFF"/>
+          <bitfield name="NMI" caption="Non-Maskable Interrupt Nonsecure Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__CKSEL">
+        <value name="CLK_GCLK" caption="Clocked by GCLK" value="0"/>
+        <value name="CLK_ULP32K" caption="Clocked by ULP32K" value="1"/>
+      </value-group>
+      <value-group name="NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="NMICTRL__NMIASYNCH">
+        <value name="SYNC" caption="Edge detection is clock synchronously operated" value="0"/>
+        <value name="ASYNC" caption="Edge detection is clock asynchronously operated" value="1"/>
+      </value-group>
+      <value-group name="ASYNCH__ASYNCH">
+        <value name="SYNC" caption="EIC_EXTINTx edge detection is synchronously operated" value="0"/>
+        <value name="ASYNC" caption="EIC_EXTINTx edge detection is asynchronously operated" value="1"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="DPRESCALER__PRESCALER">
+        <value name="DIV2" caption="EIC clock divided by 2" value="0"/>
+        <value name="DIV4" caption="EIC clock divided by 4" value="1"/>
+        <value name="DIV8" caption="EIC clock divided by 8" value="2"/>
+        <value name="DIV16" caption="EIC clock divided by 16" value="3"/>
+        <value name="DIV32" caption="EIC clock divided by 32" value="4"/>
+        <value name="DIV64" caption="EIC clock divided by 64" value="5"/>
+        <value name="DIV128" caption="EIC clock divided by 128" value="6"/>
+        <value name="DIV256" caption="EIC clock divided by 256" value="7"/>
+      </value-group>
+      <value-group name="DPRESCALER__STATES">
+        <value name="LFREQ3" caption="3 low frequency samples" value="0"/>
+        <value name="LFREQ7" caption="7 low frequency samples" value="1"/>
+      </value-group>
+      <value-group name="DPRESCALER__TICKON">
+        <value name="CLK_GCLK_EIC" caption="Bounce sampler is using GCLK_EIC" value="0"/>
+        <value name="CLK_LFREQ" caption="Bounce sampler is using Low Frequency Clock" value="1"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="03601" name2="ptg_evsys_u2504_v2" version="2b0" caption="Event System Interface">
+      <register-group name="CHANNEL" size="0x8">
+        <register name="CHANNEL" offset="0x0" rw="RW" size="4" initval="0x00008000" caption="Channel n Control">
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x300" values="CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC00" values="CHANNEL__EDGSEL"/>
+          <bitfield name="RUNSTDBY" caption="Run in standby" mask="0x4000"/>
+          <bitfield name="ONDEMAND" caption="Generic Clock On Demand" mask="0x8000"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel n Interrupt Enable Clear">
+          <bitfield name="OVR" caption="Channel Overrun Interrupt Disable" mask="0x1"/>
+          <bitfield name="EVD" caption="Channel Event Detected Interrupt Disable" mask="0x2"/>
+        </register>
+        <register name="CHINTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel n Interrupt Enable Set">
+          <bitfield name="OVR" caption="Channel Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EVD" caption="Channel Event Detected Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel n Interrupt Flag Status and Clear">
+          <bitfield name="OVR" caption="Channel Overrun" mask="0x1"/>
+          <bitfield name="EVD" caption="Channel Event Detected" mask="0x2"/>
+        </register>
+        <register name="CHSTATUS" offset="0x7" rw="R" size="1" initval="0x01" caption="Channel n Status">
+          <bitfield name="RDYUSR" caption="Ready User" mask="0x1"/>
+          <bitfield name="BUSYCH" caption="Busy Channel" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRLA" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="SWEVT" offset="0x4" rw="W" size="4" initval="0x00000000" caption="Software Event">
+          <bitfield name="CHANNEL0" caption="Channel 0 Software Selection" mask="0x1"/>
+          <bitfield name="CHANNEL1" caption="Channel 1 Software Selection" mask="0x2"/>
+          <bitfield name="CHANNEL2" caption="Channel 2 Software Selection" mask="0x4"/>
+          <bitfield name="CHANNEL3" caption="Channel 3 Software Selection" mask="0x8"/>
+          <bitfield name="CHANNEL4" caption="Channel 4 Software Selection" mask="0x10"/>
+          <bitfield name="CHANNEL5" caption="Channel 5 Software Selection" mask="0x20"/>
+          <bitfield name="CHANNEL6" caption="Channel 6 Software Selection" mask="0x40"/>
+          <bitfield name="CHANNEL7" caption="Channel 7 Software Selection" mask="0x80"/>
+          <bitfield name="CHANNEL8" caption="Channel 8 Software Selection" mask="0x100"/>
+          <bitfield name="CHANNEL9" caption="Channel 9 Software Selection" mask="0x200"/>
+          <bitfield name="CHANNEL10" caption="Channel 10 Software Selection" mask="0x400"/>
+          <bitfield name="CHANNEL11" caption="Channel 11 Software Selection" mask="0x800"/>
+        </register>
+        <register name="PRICTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Priority Control">
+          <bitfield name="PRI" caption="Channel Priority Number" mask="0xF"/>
+          <bitfield name="RREN" caption="Round-Robin Scheduling Enable" mask="0x80"/>
+        </register>
+        <register name="INTPEND" offset="0x10" rw="RW" size="2" initval="0x4000" caption="Channel Pending Interrupt">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="OVR" caption="Channel Overrun" mask="0x100"/>
+          <bitfield name="EVD" caption="Channel Event Detected" mask="0x200"/>
+          <bitfield name="READY" caption="Ready" mask="0x4000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x14" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x18" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="READYUSR" offset="0x1C" rw="R" size="4" initval="0x00000FFF" caption="Ready Users">
+          <bitfield name="READYUSR0" caption="Ready User for Channel 0" mask="0x1"/>
+          <bitfield name="READYUSR1" caption="Ready User for Channel 1" mask="0x2"/>
+          <bitfield name="READYUSR2" caption="Ready User for Channel 2" mask="0x4"/>
+          <bitfield name="READYUSR3" caption="Ready User for Channel 3" mask="0x8"/>
+          <bitfield name="READYUSR4" caption="Ready User for Channel 4" mask="0x10"/>
+          <bitfield name="READYUSR5" caption="Ready User for Channel 5" mask="0x20"/>
+          <bitfield name="READYUSR6" caption="Ready User for Channel 6" mask="0x40"/>
+          <bitfield name="READYUSR7" caption="Ready User for Channel 7" mask="0x80"/>
+          <bitfield name="READYUSR8" caption="Ready User for Channel 8" mask="0x100"/>
+          <bitfield name="READYUSR9" caption="Ready User for Channel 9" mask="0x200"/>
+          <bitfield name="READYUSR10" caption="Ready User for Channel 10" mask="0x400"/>
+          <bitfield name="READYUSR11" caption="Ready User for Channel 11" mask="0x800"/>
+        </register>
+        <register-group name="CHANNEL" name-in-module="CHANNEL" offset="0x020" size="0x8" count="12"/>
+        <register name="USER" offset="0x120" rw="RW" size="1" count="62" initval="0x00" caption="User Multiplexer n">
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0xF"/>
+        </register>
+      </register-group>
+      <value-group name="CHANNEL__PATH">
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="0x0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="0x1"/>
+      </value-group>
+      <value-group name="CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+    </module>
+    <module name="FCR" id="04972" name2="pfm_ctrlr_apb_v2" version="2a0" caption="Polaris Flash Read Controller">
+      <register-group name="FCR" caption="Polaris Flash Read Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00008000" caption="CTRL A REGISTER">
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+          <bitfield name="FWS" caption="Flash Access Time Defined in terms of AHB Clock Wait States" mask="0xF00" values="CTRLA__FWS"/>
+          <bitfield name="ADRWS" caption="Address Wait State Enable" mask="0x4000" values="CTRLA__ADRWS"/>
+          <bitfield name="AUTOWS" caption="Automatic Wait State Enable." mask="0x8000" values="CTRLA__AUTOWS"/>
+          <bitfield name="RDBUFWS" caption="Read Buffer Wait StatesPer AHB port control of deterministic or zero wait state read buffer access." mask="0x10000" values="CTRLA__RDBUFWS"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CTRL B REGISTER">
+          <bitfield name="PRM" caption="Set NVM Power Reduction Mode" mask="0x1" values="CTRLB__PRM"/>
+          <bitfield name="CHEINV" caption="Cache InvalidateCache invalidation takes 1 clock cycle, but may be delayed by an active read." mask="0x80" values="CTRLB__CHEINV"/>
+          <bitfield name="SLP" caption="NVM Power Reduction Mode selection during System Standby Sleep" mask="0x300" values="CTRLB__SLP"/>
+          <bitfield name="CHEDIS" caption="Cache Disable" mask="0x10000" values="CTRLB__CHEDIS"/>
+          <bitfield name="PREFDIS" caption="Prefetch Disable" mask="0x20000" values="CTRLB__PREFDIS"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Clear Enable" mask="0x1" values="INTENCLR__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Clear Enable" mask="0x100" values="INTENCLR__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Clear Enable" mask="0x200" values="INTENCLR__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Clear Enable" mask="0x10000" values="INTENCLR__FLTCAP"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable SET REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Set Enable" mask="0x1" values="INTENSET__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Set Enable" mask="0x100" values="INTENSET__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Set Enable" mask="0x200" values="INTENSET__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Set Enable" mask="0x10000" values="INTENSET__FLTCAP"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Flag" mask="0x1" values="INTFLAG__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Flag" mask="0x100" values="INTFLAG__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Flag" mask="0x200" values="INTFLAG__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Flag" mask="0x10000" values="INTFLAG__FLTCAP"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="Interrupt Flag Set REGISTER">
+          <bitfield name="SERR" caption="Flash SEC Interrupt Flag" mask="0x1" values="INTFLAGSET__SERR"/>
+          <bitfield name="CRCDONE" caption="CRC Calculation Done Flag" mask="0x100" values="INTFLAGSET__CRCDONE"/>
+          <bitfield name="CRCERR" caption="CRC Error Flag" mask="0x200" values="INTFLAGSET__CRCERR"/>
+          <bitfield name="FLTCAP" caption="ECC Fault Capture Flag" mask="0x10000" values="INTFLAGSET__FLTCAP"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="R" size="4" initval="0xE0000000" caption="Status REGISTER">
+          <bitfield name="PRM" caption="NVM Power Reduction Mode Status" mask="0x1" values="STATUS__PRM"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Debug Control CTRL REGISTER">
+          <bitfield name="CRCRUN" caption="CRC Debug Run Enable" mask="0x1" values="DBGCTRL__CRCRUN"/>
+          <bitfield name="DBGECC" caption="Debug ECC ModeECC errors from debugger reads are:" mask="0x6" values="DBGCTRL__DBGECC"/>
+        </register>
+        <register name="ECCCTRL" offset="0x20" rw="RW" size="4" initval="0x00000040" caption="ECC Control REGISTER">
+          <bitfield name="ECCCTL" caption="NVM ECC Mode Control - restricts one or more NVMOPs" mask="0x30" values="ECCCTRL__ECCCTL"/>
+          <bitfield name="ECCUNLCK" caption="NVM ECC Mode Control Unlock" mask="0x40" values="ECCCTRL__ECCUNLCK"/>
+          <bitfield name="SECCNT" caption="Flash SEC Count" mask="0xFF00"/>
+        </register>
+        <register name="CRCCTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="CRC Control REGISTER">
+          <bitfield name="CRCRST" caption="CRC Reset" mask="0x1" values="CRCCTRL__CRCRST"/>
+          <bitfield name="CRCEN" caption="Start CRC Calculation" mask="0x2" values="CRCCTRL__CRCEN"/>
+          <bitfield name="RUNSTDBY" caption="CRC Run in Standby" mask="0x20" values="CRCCTRL__RUNSTDBY"/>
+        </register>
+        <register name="CRCMODE" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="CRC MODE REGISTER">
+          <bitfield name="PLEN32" caption="Polynomial Length Select" mask="0x1000" values="CRCMODE__PLEN32"/>
+          <bitfield name="AUTOR" caption="CRC Auto Repeat" mask="0x2000" values="CRCMODE__AUTOR"/>
+          <bitfield name="ROUT" caption="CRC Reflected Output" mask="0x4000" values="CRCMODE__ROUT"/>
+          <bitfield name="RIN" caption="CRC Reflected Input" mask="0x8000" values="CRCMODE__RIN"/>
+          <bitfield name="PERIOD" caption="Read Period in PerCLK counts" mask="0xFFF0000"/>
+        </register>
+        <register name="CRCPAUSE" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="CRC Pause REGISTER">
+          <bitfield name="PAUSE" caption="CRC Pause" mask="0x1" values="CRCPAUSE__PAUSE"/>
+        </register>
+        <register name="CRCMADR" offset="0x30" rw="RW" size="4" initval="0x00000000" caption="CRC Message Address REGISTER">
+          <bitfield name="CRCMADR" caption="Message Start Address in Flash" mask="0xFFFFFFF"/>
+        </register>
+        <register name="CRCMLEN" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="CRC Message Length REGISTER">
+          <bitfield name="CRCMLEN" caption="Message Length in Bytes" mask="0xFFFFF"/>
+        </register>
+        <register name="CRCIV" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="CRC Initial Value REGISTER">
+          <bitfield name="CRCIV" caption="CRC Initial Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCACC" offset="0x3C" rw="R" size="4" initval="0x00000000" caption="CRC Accumulator REGISTER">
+          <bitfield name="CRCACC" caption="CRC Accumulator Result" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCPOLY" offset="0x40" rw="RW" size="4" initval="0x00000001" caption="CRC Polynomial REGISTER">
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Coefficients for LFSR" mask="0xFFFFFFFF" values="CRCPOLY__CRCPOLY"/>
+        </register>
+        <register name="CRCFXOR" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="CRC Final XOR REGISTER">
+          <bitfield name="CRCFXOR" caption="CRC Final XOR" mask="0xFFFFFFFF" values="CRCFXOR__CRCFXOR"/>
+        </register>
+        <register name="CRCSUM" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="CRC CheckSUM REGISTER">
+          <bitfield name="CRCSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FFLTCTRL" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Control REGISTER">
+          <bitfield name="FLTRST" caption="Fault Reset" mask="0x1" values="FFLTCTRL__FLTRST"/>
+          <bitfield name="FLTEN" caption="ECC Fault Enable bit" mask="0x2" values="FFLTCTRL__FLTEN"/>
+        </register>
+        <register name="FFLTMODE" offset="0x50" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Mode REGISTER">
+          <bitfield name="CTLFLT" caption="ECC/Parity Control Fault bits" mask="0x700" values="FFLTMODE__CTLFLT"/>
+          <bitfield name="FLTMD" caption="Fault Mode Control" mask="0x7000" values="FFLTMODE__FLTMD"/>
+        </register>
+        <register name="FFLTPTR" offset="0x54" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Pointer REGISTER">
+          <bitfield name="FLTPTR1" caption="Fault 1 Injection Pointer" mask="0xFF"/>
+          <bitfield name="FLTPTR2" caption="Fault 2 Injection Pointer" mask="0xFF0000"/>
+        </register>
+        <register name="FFLTADR" offset="0x58" rw="RW" size="4" initval="0x00000000" caption="Flash ECC Fault Address REGISTER">
+          <bitfield name="FLTADR" caption="Fault Injection Address" mask="0xFFFFFFF"/>
+        </register>
+        <register name="FFLTCAP" offset="0x5C" rw="R" size="4" initval="0x00000000" caption="Flash ECC Fault Capture Address REGISTER">
+          <bitfield name="FLTADR" caption="Fault Capture Address" mask="0xFFFFFFF"/>
+        </register>
+        <register name="FFLTPAR" offset="0x60" rw="R" size="4" initval="0x00000000" caption="Flash ECC Fault Parity REGISTER">
+          <bitfield name="SECIN" caption="The Single Error Parity bits from Flash" mask="0xFF"/>
+          <bitfield name="DEDIN" caption="The Overall Parity from Flash" mask="0x8000"/>
+          <bitfield name="SECOUT" caption="The Calculated Single Error Parity bits" mask="0xFF0000"/>
+          <bitfield name="DEDOUT" caption="The Calculated Overall Parity used in Double Error Detection" mask="0x80000000"/>
+        </register>
+        <register name="FFLTSYN" offset="0x64" rw="R" size="4" initval="0x00000000" caption="Flash ECC Fault Syndrome REGISTER">
+          <bitfield name="SECSYN" caption="Single Error Correction Syndrome" mask="0xFF"/>
+          <bitfield name="DEDSYN" caption="DED Syndrome" mask="0x8000" values="FFLTSYN__DEDSYN"/>
+          <bitfield name="DSERR" caption="Double Error Detected &amp; Single Error Corrected" mask="0x30000" values="FFLTSYN__DSERR"/>
+          <bitfield name="CERR" caption="ECC Control bit Error" mask="0x40000" values="FFLTSYN__CERR"/>
+          <bitfield name="CTLSTAT" caption="Parity vs ECC Control Status" mask="0x7000000" values="FFLTSYN__CTLSTAT"/>
+          <bitfield name="PERR" caption="Per Word (n=3:0) Parity Error Status" mask="0xF0000000" values="FFLTSYN__PERR"/>
+        </register>
+        <register name="CRP" offset="0x68" rw="RW" size="4" initval="0x00C20000" caption="CFM Page Read Protection REGISTER (CFM8)">
+          <bitfield name="BC1ARP" caption="Panel 1 Read Protect BootCfg1A" mask="0x1" values="CRP__BC1ARP"/>
+          <bitfield name="UO1RP" caption="Panel 1 Read Protect UserOTP1" mask="0x2" values="CRP__UO1RP"/>
+          <bitfield name="BC1RP" caption="Panel 1 Read Protect BootCfg1" mask="0x4" values="CRP__BC1RP"/>
+          <bitfield name="RCRP" caption="Panel 1 Read Protect ROMCfg" mask="0x8" values="CRP__RCRP"/>
+          <bitfield name="VSSRP0" caption="Panel 1 Read Protect VSSn" mask="0x10" values="CRP__VSSRP"/>
+          <bitfield name="VSSRP1" caption="Panel 1 Read Protect VSSn" mask="0x20" values="CRP__VSSRP"/>
+          <bitfield name="TRP" caption="Panel 1 Read Protect Test" mask="0x40" values="CRP__TRP"/>
+          <bitfield name="CORP" caption="Panel 1 Read Protect CalOTP" mask="0x80" values="CRP__CORP"/>
+          <bitfield name="BC1ARPLOCK" caption="Panel 1 Lock Read Protection BootCfg1A" mask="0x10000" values="CRP__BC1ARPLOCK"/>
+          <bitfield name="UO1RPLOCK" caption="Panel 1 Lock Read Protection UserOTP1" mask="0x20000" values="CRP__UO1RPLOCK"/>
+          <bitfield name="BC1RPLOCK" caption="Panel 1 Lock Read Protection BootCfg1" mask="0x40000" values="CRP__BC1RPLOCK"/>
+          <bitfield name="RCRPLOCK" caption="Panel 1 Lock Read Protection ROMCfg" mask="0x80000" values="CRP__RCRPLOCK"/>
+          <bitfield name="VSSRPLOCK0" caption="Panel 1 Lock Read Protection VSSn" mask="0x100000" values="CRP__VSSRPLOCK"/>
+          <bitfield name="VSSRPLOCK1" caption="Panel 1 Lock Read Protection VSSn" mask="0x200000" values="CRP__VSSRPLOCK"/>
+          <bitfield name="TRPLOCK" caption="Panel 1 Lock Read Protection Test" mask="0x400000" values="CRP__TRPLOCK"/>
+          <bitfield name="CORPLOCK" caption="Panel 1 Lock Read Protection CalOTP" mask="0x800000" values="CRP__CORPLOCK"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="DISABLE" caption="Macro register accessible in privileged and unprivileged accesses." value="0"/>
+        <value name="ENABLE" caption="Macro registers only accessible in privileged accesses" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__FWS">
+        <value name="0" caption="Zero Wait States" value="0"/>
+        <value name="1" caption="One Wait State" value="1"/>
+        <value name="14" caption="Fourteen Wait States" value="14"/>
+        <value name="15" caption="Fifteen Wait States" value="15"/>
+      </value-group>
+      <value-group name="CTRLA__ADRWS">
+        <value name="ZERO" caption="Add 0 Address Wait States - allowing for higher performance at lower clock frequencies" value="0"/>
+        <value name="ONE" caption="Add 1 Address Wait State - allowing for higher clock frequencies" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__AUTOWS">
+        <value name="DISABLE" caption="Use FWS: Total flash wait states are ADRWS + FWS" value="0"/>
+        <value name="ENABLE" caption="Use Automatic wait states: Total flash wait states are ADRWS + Taws" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__RDBUFWS">
+        <value name="ZEROWS" caption="0 Wait States" value="0"/>
+        <value name="DETERMINISTIC" caption="ADRWS + FWS wait state for hits to AHB read buffer" value="1"/>
+      </value-group>
+      <value-group name="CTRLB__PRM">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="TOGGLE" caption="Toggle the Flash Power Mode" value="1"/>
+      </value-group>
+      <value-group name="CTRLB__CHEINV">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="INV" caption="Invalidate Cache" value="1"/>
+      </value-group>
+      <value-group name="CTRLB__SLP">
+        <value name="MANUAL" caption="Maintain state of STATUS.PRM on entry to Standby" value="0"/>
+        <value name="RSVD01" caption="RSVD" value="1"/>
+        <value name="AUTOFAST" caption="Enter Flash Hibernate on entry to Standby w/ wakeup to Auto Standby" value="2"/>
+        <value name="AUTOSLOW" caption="Enter Flash Hibernate on entry to Standby w/ wakeup on first access" value="3"/>
+      </value-group>
+      <value-group name="CTRLB__CHEDIS">
+        <value name="ENABLE" caption="Cache Enabled; Accesses to flash use AUTOWS/FSW selection." value="0"/>
+        <value name="DISABLE" caption="Cache Disabled; Interface uses RDBUFWS selection." value="1"/>
+      </value-group>
+      <value-group name="CTRLB__PREFDIS">
+        <value name="ENABLE" caption="Predictive Prefetch Enabled" value="0"/>
+        <value name="DISABLE" caption="Predictive Prefetch Disabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__SERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__CRCDONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__CRCERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__FLTCAP">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__SERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CRCDONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CRCERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__FLTCAP">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__SERR">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="SECCNT Count reached" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__CRCDONE">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="Calculation Done" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__CRCERR">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="CRCACC Is Not Equal to the XOR of CRCSUM and CRCFXOR" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__FLTCAP">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="An ECC Fault Capture, related to FLTMD[], occurred" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__SERR">
+        <value name="0" caption="No Interrupt Pending" value="0"/>
+        <value name="1" caption="SECCNT Count reached" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__CRCDONE">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__CRCERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__FLTCAP">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="STATUS__PRM">
+        <value name="0" caption="Flash is Ready (for read or NVMOP)" value="0"/>
+        <value name="1" caption="Flash is Powered Down and wakes on first access (read or NVMOP)" value="1"/>
+      </value-group>
+      <value-group name="DBGCTRL__CRCRUN">
+        <value name="HALT" caption="CRC Logic Halts in Debug Mode" value="0"/>
+        <value name="RUN" caption="CRC Logic Runs in Debug Mode." value="1"/>
+      </value-group>
+      <value-group name="DBGCTRL__DBGECC">
+        <value name="NOERR" caption="Corrected per ECCCTRL; No Bus ERR; INTFLAG, SEC counter, and FLT logic are not updated." value="0"/>
+        <value name="DISABLE" caption="Not corrected; No Bus Error; INTFLAG, SEC counter, and FLT logic are not updated." value="1"/>
+        <value name="ENABLE" caption="Corrected per ECCCTRL; Bus Error, INTFLAG, SEC counter, and FLT logic operates as setup." value="2"/>
+        <value name="RSVD11" caption="Don't use but same as 01 (DISABLE)" value="3"/>
+      </value-group>
+      <value-group name="ECCCTRL__ECCCTL">
+        <value name="STRICT" caption="ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)" value="0"/>
+        <value name="DYNAMIC" caption="Dynamic Writes with Dynamic Reads" value="1"/>
+        <value name="ECC" caption="ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)" value="2"/>
+        <value name="DISABLE" caption="Dynamic Writes with No Error Check Reads" value="3"/>
+      </value-group>
+      <value-group name="ECCCTRL__ECCUNLCK">
+        <value name="LOCKED" caption="ECCUNLCK and ECCCTL[1:0] cannot be written" value="0"/>
+        <value name="UNLOCKED" caption="ECCUNLCK and ECCCTL[1:0] can be written" value="1"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCRST">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="RESET" caption="Resets all CRC SFR bits." value="1"/>
+      </value-group>
+      <value-group name="CRCCTRL__CRCEN">
+        <value name="DISABLE" caption="Stops CRC calculation." value="0"/>
+        <value name="ENABLE" caption="CRC Calculation Enabled (w/ start on write to 1)." value="1"/>
+      </value-group>
+      <value-group name="CRCCTRL__RUNSTDBY">
+        <value name="HALT" caption="CRC Halts in Standby" value="0"/>
+        <value name="RUN" caption="CRC Runs in Standby but only if STATUS.PRM=0 (i.e. Flash is in Auto Standby)" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__PLEN32">
+        <value name="SIXTEEN" caption="Polynomial is 16-bits" value="0"/>
+        <value name="THIRTYTWO" caption="Polynomial is 32-bits" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__AUTOR">
+        <value name="DISABLE" caption="Perform CRC calculation once then set DONE and if needed, CRCERR." value="0"/>
+        <value name="ENABLE" caption="Continually Repeat CRC calculation; stop on error, set CRCDONE and CRCERR" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__ROUT">
+        <value name="DISABLE" caption="The CRCACC is Not Reflected" value="0"/>
+        <value name="ENABLE" caption="The CRCACC is Reflected (before the Final XOR)" value="1"/>
+      </value-group>
+      <value-group name="CRCMODE__RIN">
+        <value name="DISABLE" caption="The LFSR CRC is calculated Most Significant Bit first (Not Reflected)" value="0"/>
+        <value name="ENABLE" caption="The LFSR CRC is calculated Least Significant Bit first (Reflected)" value="1"/>
+      </value-group>
+      <value-group name="CRCPAUSE__PAUSE">
+        <value name="DISABLE" caption="CRC Reads Flash as Required" value="0"/>
+        <value name="ENABLE" caption="Pause CRC Reads of Flash" value="1"/>
+      </value-group>
+      <value-group name="CRCPOLY__CRCPOLY">
+        <value name="0" caption="Disable the XOR input to the shift register at the associated bit position" value="0"/>
+        <value name="1" caption="Enable the XOR input to the shift register at the associated bit position" value="1"/>
+      </value-group>
+      <value-group name="CRCFXOR__CRCFXOR">
+        <value name="0" caption="Disable the Final XOR at the associated bit position" value="0"/>
+        <value name="1" caption="Enable the Final XOR at the associated bit position" value="1"/>
+      </value-group>
+      <value-group name="FFLTCTRL__FLTRST">
+        <value name="NONE" caption="No Action" value="0"/>
+        <value name="RESET" caption="Resets all FLT SFR bits." value="1"/>
+      </value-group>
+      <value-group name="FFLTCTRL__FLTEN">
+        <value name="DISABLE" caption="ECC Fault Injection Disabled" value="0"/>
+        <value name="ENABLE" caption="ECC Fault Injection Enabled (module performs operation selected by FFLTMODE.FLTMD)" value="1"/>
+      </value-group>
+      <value-group name="FFLTMODE__CTLFLT">
+        <value name="0" caption="No Fault Injected" value="0"/>
+        <value name="1" caption="Inject a Fault on to the associated ECC/Parity Control bits (CTL[n])" value="1"/>
+      </value-group>
+      <value-group name="FFLTMODE__FLTMD">
+        <value name="DISABLE" caption="Fault Injection Disabled" value="0"/>
+        <value name="CAPT" caption="Fault Capture Mode Enabled - Captures the address (in FLTADR) and Syndrome in (FLTSYN)" value="2"/>
+        <value name="SINGLEREAD" caption="Single Fault Injection (at bit selected by FLT1PTR) for Reads" value="4"/>
+        <value name="DOUBLEREAD" caption="Double Fault Injection for Reads" value="5"/>
+        <value name="SINGLEWRITE" caption="Single Fault Injection (at bit selected by FLT1PTR) for Writes" value="6"/>
+        <value name="DOUBLEWRITE" caption="Double Fault Injection for Writes" value="7"/>
+      </value-group>
+      <value-group name="FFLTSYN__DEDSYN">
+        <value name="0" caption="Calculated Overall Parity Concurs with Read Overall Parity" value="0"/>
+        <value name="1" caption="Calculated Overall Parity Differs from Read Overall Parity" value="1"/>
+      </value-group>
+      <value-group name="FFLTSYN__DSERR">
+        <value name="NONE" caption="No Errors" value="0"/>
+        <value name="SINGLE" caption="Single Error Corrected" value="1"/>
+        <value name="DOUBLE_10" caption="Double Error Detected" value="2"/>
+        <value name="DOUBLE_11" caption="Double Error Detected" value="3"/>
+      </value-group>
+      <value-group name="FFLTSYN__CERR">
+        <value name="NONE" caption="No Control bit Error (ECCSTAT either 111 or 000)" value="0"/>
+        <value name="SINGLE" caption="Single Control Bit Error" value="1"/>
+      </value-group>
+      <value-group name="FFLTSYN__CTLSTAT">
+        <value name="USEDECC_0" caption="Calculation used ECC (i.e. programming used quad write)" value="0"/>
+        <value name="USEDECC_1" caption="Calculation used ECC (i.e. programming used quad write)" value="1"/>
+        <value name="USEDECC_10" caption="Calculation used ECC (i.e. programming used quad write)" value="2"/>
+        <value name="USEDPARITY_11" caption="Calculation used Parity (i.e. programming used single write)" value="3"/>
+        <value name="USEDECC_100" caption="Calculation used ECC (i.e. programming used quad write)" value="4"/>
+        <value name="USEDPARITY_101" caption="Calculation used Parity (i.e. programming used single write)" value="5"/>
+        <value name="USEDPARITY_110" caption="Calculation used Parity (i.e. programming used single write)" value="6"/>
+        <value name="USEDPARITY_111" caption="Calculation used Parity (i.e. programming used single write)" value="7"/>
+      </value-group>
+      <value-group name="FFLTSYN__PERR">
+        <value name="NONE" caption="No Parity Error on Word n" value="0"/>
+        <value name="ERROR" caption="Parity Error on Word n" value="1"/>
+      </value-group>
+      <value-group name="CRP__BC1ARP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__UO1RP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+      </value-group>
+      <value-group name="CRP__BC1RP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__RCRP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__VSSRP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__TRP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__CORP">
+        <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CRP__BC1ARPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__UO1RPLOCK">
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__BC1RPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__RCRPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__VSSRPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__TRPLOCK">
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CRP__CORPLOCK">
+        <value name="LOCKED" caption="The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+    </module>
+    <module name="FCW" id="04971" name2="pfm_ctrlw_apb_v2" version="2a0" caption="Polaris Flash Write Controller">
+      <register-group name="FCW" caption="Polaris Flash Write Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A REGISTER">
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+        </register>
+        <register name="CTRLOP" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control Operation REGISTER">
+          <bitfield name="NVMOP" caption="NVM Operation" mask="0xF" values="CTRLOP__NVMOP"/>
+          <bitfield name="PREPG" caption="NVM Pre-Program Configuration Bit" mask="0x80" values="CTRLOP__PREPG"/>
+        </register>
+        <register name="MUTEX" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="MUTEX REGISTER">
+          <bitfield name="LOCK" caption="Flash Write Controller (FCW) Lock by Owner" mask="0x1" values="MUTEX__LOCK"/>
+          <bitfield name="OWNER" caption="Flash Write Controller (FCW) Owner ID" mask="0x6" values="MUTEX__OWNER"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Interrupt Enable" mask="0x1" values="INTENCLR__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Interrupt Enable" mask="0x2" values="INTENCLR__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Interrupt Enable" mask="0x4" values="INTENCLR__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Interrupt Enable" mask="0x8" values="INTENCLR__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Interrupt Enable" mask="0x10" values="INTENCLR__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Interrupt Enable" mask="0x20" values="INTENCLR__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Interrupt Enable" mask="0x40" values="INTENCLR__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Interrupt Enable" mask="0x100" values="INTENCLR__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Interrupt Enable" mask="0x1000" values="INTENCLR__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Interrupt Enable" mask="0x2000" values="INTENCLR__WRERR"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Interrupt Set Enable" mask="0x1" values="INTENSET__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Interrupt Set Enable" mask="0x2" values="INTENSET__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Interrupt Set Enable" mask="0x4" values="INTENSET__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Interrupt Set Enable" mask="0x8" values="INTENSET__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Interrupt Enable" mask="0x10" values="INTENSET__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Interrupt Enable" mask="0x20" values="INTENSET__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Interrupt Enable" mask="0x40" values="INTENSET__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Interrupt Enable" mask="0x100" values="INTENSET__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Interrupt Enable" mask="0x1000" values="INTENSET__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Interrupt Enable" mask="0x2000" values="INTENSET__WRERR"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Flag Bit" mask="0x1" values="INTFLAG__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Flag Bit" mask="0x2" values="INTFLAG__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Flag Bit" mask="0x4" values="INTFLAG__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Flag Bit" mask="0x8" values="INTFLAG__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Flag Bit" mask="0x10" values="INTFLAG__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Flag Bit" mask="0x20" values="INTFLAG__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Flag Bit" mask="0x40" values="INTFLAG__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Flag Bit" mask="0x100" values="INTFLAG__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Flag Bit" mask="0x1000" values="INTFLAG__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Flag Bit" mask="0x2000" values="INTFLAG__WRERR"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="Interrupt Flag Set REGISTER">
+          <bitfield name="DONE" caption="NVM Operation Done Set Flag Bit" mask="0x1" values="INTFLAGSET__DONE"/>
+          <bitfield name="KEYERR" caption="Key Error Set Flag Bit" mask="0x2" values="INTFLAGSET__KEYERR"/>
+          <bitfield name="CFGERR" caption="Configuration Error Set Flag Bit" mask="0x4" values="INTFLAGSET__CFGERR"/>
+          <bitfield name="FIFOERR" caption="FIFO Underrun during Row Write Set Flag Bit" mask="0x8" values="INTFLAGSET__FIFOERR"/>
+          <bitfield name="BUSERR" caption="AHB Bus Error during Row Write Set Flag Bit" mask="0x10" values="INTFLAGSET__BUSERR"/>
+          <bitfield name="WPERR" caption="Write Protection Error Set Flag Bit" mask="0x20" values="INTFLAGSET__WPERR"/>
+          <bitfield name="OPERR" caption="NVMOP Error Set Flag Bit" mask="0x40" values="INTFLAGSET__OPERR"/>
+          <bitfield name="HTDPGM" caption="High Temperature Detect Error Set Flag Bit" mask="0x100" values="INTFLAGSET__HTDPGM"/>
+          <bitfield name="RSTERR" caption="Reset or Brown Out Detect Error Set Flag Bit" mask="0x1000" values="INTFLAGSET__RSTERR"/>
+          <bitfield name="WRERR" caption="Write Error Set Flag Bit" mask="0x2000" values="INTFLAGSET__WRERR"/>
+        </register>
+        <register name="STATUS" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="Status REGISTER">
+          <bitfield name="BUSY" caption="NVM Busy Status" mask="0x1" values="STATUS__BUSY"/>
+          <bitfield name="HTDRDY" caption="High Temp Detect Ready Status" mask="0x100" values="STATUS__HTDRDY"/>
+        </register>
+        <register name="KEY" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Feature Unlock Key REGISTER">
+          <bitfield name="FEATURE" caption="Feature Select" mask="0xFF" values="KEY__FEATURE"/>
+          <bitfield name="CODE" caption="Unlock Code" mask="0xFFFFFF00"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Flash Destination Address REGISTER">
+          <bitfield name="ADDR" caption="Flash Address used by NVMOP" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="System Source Address REGISTER">
+          <bitfield name="SRCADDR" caption="Source Data (Word) Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DATA" offset="0x2C" rw="RW" size="4" count="4" initval="0x00000000" caption="Flash Write Data n REGISTER">
+          <bitfield name="DATA" caption="Flash Write Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="SWAP" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="NVM Panel Swap REGISTER">
+          <bitfield name="BFSWAP" caption="BFM Swap Status/Control Bit" mask="0x1" values="SWAP__BFSWAP"/>
+          <bitfield name="BFSLOCK" caption="BFM Swap Lock Bit" mask="0x2" values="SWAP__BFSLOCK"/>
+          <bitfield name="PFSWAP" caption="PFM Swap Status/Control Bit" mask="0x100" values="SWAP__PFSWAP"/>
+          <bitfield name="PFSLOCK" caption="PFM Swap Lock Bit" mask="0x200" values="SWAP__PFSLOCK"/>
+        </register>
+        <register name="PWP" offset="0x50" rw="RW" size="4" count="4" initval="0x00000000" caption="PFM Write Protect Region n REGISTER">
+          <bitfield name="PWPSIZE" caption="PWP Size in 4KB pages" mask="0x7F"/>
+          <bitfield name="PWPMIR" caption="Mirror PWP bit" mask="0x2000" values="PWP__PWPMIR"/>
+          <bitfield name="PWPLOCK" caption="PWP Lock Bit" mask="0x4000" values="PWP__PWPLOCK"/>
+          <bitfield name="PWPEN" caption="PWP Enable Bit" mask="0x8000" values="PWP__PWPEN"/>
+          <bitfield name="PWPBASE" caption="PWP Base Address - 4KB Page Aligned" mask="0x7F0000"/>
+        </register>
+        <register name="LBWP" offset="0x70" rw="RW" size="4" initval="0x00000003" caption="Lower BFM Write Protect REGISTER">
+          <bitfield name="LBWP" caption="Lower Boot Pages Write Protect Bits" mask="0x3" values="LBWP__LBWP"/>
+          <bitfield name="LBWPLOCK" caption="LBWP Lock Bit" mask="0x80000000" values="LBWP__LBWPLOCK"/>
+        </register>
+        <register name="UBWP" offset="0x74" rw="RW" size="4" initval="0x00000003" caption="Upper BFM Write Protect REGISTER">
+          <bitfield name="UBWP" caption="Upper Boot Pages Write Protect Bits" mask="0x3" values="UBWP__UBWP"/>
+          <bitfield name="UBWPLOCK" caption="UBWP Lock Bit" mask="0x80000000" values="UBWP__UBWPLOCK"/>
+        </register>
+        <register name="UOWP" offset="0x78" rw="RW" size="4" initval="0x0000000F" caption="User OTP Write protection REGISTER">
+          <bitfield name="UO1WPR" caption="User OTP Page 1 Write Protect Row Bit" mask="0xF" values="UOWP__UO1WPR"/>
+          <bitfield name="UO1WPRLOCK" caption="User OTP Page 1 WP Row Lock Bit" mask="0xF0000" values="UOWP__UO1WPRLOCK"/>
+        </register>
+        <register name="CWP" offset="0x7C" rw="RW" size="4" initval="0x08C008FD" caption="CFM Page Write Protect REGISTER">
+          <bitfield name="BC1AWP" caption="Panel 1 Write Protect BootCfg1A" mask="0x1" values="CWP__BC1AWP"/>
+          <bitfield name="BC1WP" caption="Panel 1 Write Protect BootCfg1" mask="0x4" values="CWP__BC1WP"/>
+          <bitfield name="RCWP" caption="Panel 1 Write Protect ROMCfg" mask="0x8" values="CWP__RCWP"/>
+          <bitfield name="VSSWP0" caption="Panel 1 Write Protect VSSn" mask="0x10" values="CWP__VSSWP"/>
+          <bitfield name="VSSWP1" caption="Panel 1 Write Protect VSSn" mask="0x20" values="CWP__VSSWP"/>
+          <bitfield name="TWP" caption="Panel 1 Write Protect Test" mask="0x40" values="CWP__TWP"/>
+          <bitfield name="COWP" caption="Panel 1 Write Protect CalOTP" mask="0x80" values="CWP__COWP"/>
+          <bitfield name="BC1AWPLOCK" caption="Panel 1 Lock Write Protection BootCfg1A" mask="0x10000" values="CWP__BC1AWPLOCK"/>
+          <bitfield name="BC1WPLOCK" caption="Panel 1 Lock Write Protection BootCfg1" mask="0x40000" values="CWP__BC1WPLOCK"/>
+          <bitfield name="RCWPLOCK" caption="Panel 1 Lock Write Protection ROMCfg" mask="0x80000" values="CWP__RCWPLOCK"/>
+          <bitfield name="VSSWPLOCK0" caption="Panel 1 Lock Write Protection VSSn" mask="0x100000" values="CWP__VSSWPLOCK"/>
+          <bitfield name="VSSWPLOCK1" caption="Panel 1 Lock Write Protection VSSn" mask="0x200000" values="CWP__VSSWPLOCK"/>
+          <bitfield name="TWPLOCK" caption="Panel 1 Lock Write Protection Test" mask="0x400000" values="CWP__TWPLOCK"/>
+          <bitfield name="COWPLOCK" caption="Panel 1 Lock Write Protection CalOTP" mask="0x800000" values="CWP__COWPLOCK"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="DISABLE" caption="Macro register accessible in privileged and unprivileged accesses." value="0"/>
+        <value name="ENABLE" caption="Macro registers only accessible in privileged accesses" value="1"/>
+      </value-group>
+      <value-group name="CTRLOP__NVMOP">
+        <value name="NOP" caption="No Operation" value="0"/>
+        <value name="SINGLEWRITE" caption="Single (Word) Program Operation: Programs word selected by ADDR" value="1"/>
+        <value name="QUADWRITE" caption="Quad (Word) Program Operation: Programs flash word selected by ADDR" value="2"/>
+        <value name="ROWWRITE" caption="Row Write Operation: Programs row selected by ADDR" value="3"/>
+        <value name="PAGEERASE" caption="Page Erase Operation: Erases page selected by ADDR" value="4"/>
+        <value name="LPFMERASE" caption="Lower PFM Erase Operation: (RSVD NVMOP for Single Panel Devices)" value="5"/>
+        <value name="UPFMERASE" caption="Upper PFM Erase Operation: (RSVD NVMOP for Single Panel Devices)" value="6"/>
+        <value name="PFMERASE" caption="PFM Erase Operation: Upper &amp;amp; Lower PFM Erase" value="7"/>
+        <value name="CE" caption="Chip Erase Operation: Erases PFM+SRF, BFM, CFM (except for CalOTP, Test, VSS pages if HSM is Present, UserOTP, &amp;amp; ROMCFG)." value="14"/>
+      </value-group>
+      <value-group name="CTRLOP__PREPG">
+        <value name="DISABLE" caption="Program Operations exclude Pre-Program step" value="0"/>
+        <value name="ENABLE" caption="Program Operations include Pre-Program step" value="1"/>
+      </value-group>
+      <value-group name="MUTEX__LOCK">
+        <value name="UNLOCK" caption="FCW is not locked" value="0"/>
+        <value name="LOCK" caption="FCW is locked by owner" value="1"/>
+      </value-group>
+      <value-group name="MUTEX__OWNER">
+        <value name="NONE" caption="No Owner - always 0 if LOCK=0" value="0"/>
+        <value name="SYSTEM" caption="The System owns the FCW" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__DONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__KEYERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__CFGERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__FIFOERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__BUSERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__WPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__OPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__HTDPGM">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__RSTERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENCLR__WRERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__DONE">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__KEYERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CFGERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__FIFOERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__BUSERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__WPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__OPERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__HTDPGM">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__RSTERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTENSET__WRERR">
+        <value name="0" caption="Interrupt Disabled" value="0"/>
+        <value name="1" caption="Interrupt Enabled" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__DONE">
+        <value name="0" caption="NVMOP Not Done" value="0"/>
+        <value name="1" caption="NVMOP Done" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__KEYERR">
+        <value name="0" caption="No Key Error" value="0"/>
+        <value name="1" caption="Key Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__CFGERR">
+        <value name="0" caption="No CFG Error" value="0"/>
+        <value name="1" caption="CFC Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__FIFOERR">
+        <value name="0" caption="No FIFO Error" value="0"/>
+        <value name="1" caption="FIFO Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__BUSERR">
+        <value name="0" caption="No Bus Error" value="0"/>
+        <value name="1" caption="Bus Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__WPERR">
+        <value name="0" caption="No Write Protection Error" value="0"/>
+        <value name="1" caption="Write Protection Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__OPERR">
+        <value name="0" caption="No NVMOP Error" value="0"/>
+        <value name="1" caption="Selected Operation is Disabled Error" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__HTDPGM">
+        <value name="0" caption="High Temp NOT Detected" value="0"/>
+        <value name="1" caption="High Temp Detected (possible data corruption, verify operation)" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__RSTERR">
+        <value name="0" caption="No Reset and Voltage level OK during write/erase" value="0"/>
+        <value name="1" caption="A reset or Low Voltage Detected (possible data corruption, verify data)" value="1"/>
+      </value-group>
+      <value-group name="INTFLAG__WRERR">
+        <value name="0" caption="The Write/Erase sequence completed normally" value="0"/>
+        <value name="1" caption="The Write/Erase sequence did not complete successfully" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__DONE">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__KEYERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__CFGERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__FIFOERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__BUSERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__WPERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__OPERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__HTDPGM">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__RSTERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="INTFLAGSET__WRERR">
+        <value name="0" caption="No effect" value="0"/>
+        <value name="1" caption="Set Interrupt Pending" value="1"/>
+      </value-group>
+      <value-group name="STATUS__BUSY">
+        <value name="IDLE" caption="NVM Not Busy" value="0"/>
+        <value name="BUSY" caption="NVM Busy - All SFR bits are not writable" value="1"/>
+      </value-group>
+      <value-group name="STATUS__HTDRDY">
+        <value name="NOTREADY" caption="HTD Not Ready" value="0"/>
+        <value name="READY" caption="HTD Ready" value="1"/>
+      </value-group>
+      <value-group name="KEY__FEATURE">
+        <value name="LOCKALL" caption="No selection, invalid selection, or invalid Key - Locks all SFR protected by KEY register" value="0"/>
+        <value name="WRKEY" caption="WRKEY Value: Unlock SFR bits associated with Write/Erase" value="1"/>
+        <value name="SWAPKEY" caption="SWAPKEY Value: Unlock SFR bits associated with Panel Swapping" value="2"/>
+        <value name="CFGKEY" caption="CFGKEY Value: Unlock SFR bits associated with general Flash configuration" value="4"/>
+      </value-group>
+      <value-group name="SWAP__BFSWAP">
+        <value name="UNSWAP" caption="Upper and Lower BFM Regions are NOT Swapped" value="0"/>
+        <value name="SWAP" caption="Upper and Lower BFM Regions are Swapped" value="1"/>
+      </value-group>
+      <value-group name="SWAP__BFSLOCK">
+        <value name="UNLOCKED" caption="BFSLOCK and BFSWAP can be written" value="0"/>
+        <value name="LOCKED" caption="BFSLOCK and BFSWAP cannot be written" value="1"/>
+      </value-group>
+      <value-group name="SWAP__PFSWAP">
+        <value name="UNSWAP" caption="Upper and Lower PFM Regions are NOT Swapped" value="0"/>
+        <value name="SWAP" caption="Upper and Lower PFM Regions are Swapped" value="1"/>
+      </value-group>
+      <value-group name="SWAP__PFSLOCK">
+        <value name="UNLOCKED" caption="PFSLOCK and PFSWAP can be written" value="0"/>
+        <value name="LOCKED" caption="PFSLOCK and PFSWAP cannot be written" value="1"/>
+      </value-group>
+      <value-group name="PWP__PWPMIR">
+        <value name="UNMIRROR" caption="PWP settings are NOT Mirrored" value="0"/>
+        <value name="MIRROR" caption="PWP settings are Mirrored" value="1"/>
+      </value-group>
+      <value-group name="PWP__PWPLOCK">
+        <value name="UNLOCKED" caption="This register is Not Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="This register is Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="PWP__PWPEN">
+        <value name="DISABLE" caption="PWP is Not Enabled for the defined region" value="0"/>
+        <value name="ENABLE" caption="PWP is Enabled for the defined region" value="1"/>
+      </value-group>
+      <value-group name="LBWP__LBWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Lower Boot Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Lower Boot Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="LBWP__LBWPLOCK">
+        <value name="UNLOCKED" caption="This register is NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="This register is Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="UBWP__UBWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Upper Boot Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Upper Boot Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="UBWP__UBWPLOCK">
+        <value name="UNLOCKED" caption="This register is NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="This register is Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="UOWP__UO1WPR">
+        <value name="DISABLE" caption="Write Protection for User OTP Page 1 Row &quot;n&quot; is Disabled" value="0"/>
+        <value name="ENABLE" caption="Write Protection for User OTP Page 1 Row &quot;n&quot; is Enabled" value="1"/>
+      </value-group>
+      <value-group name="UOWP__UO1WPRLOCK">
+        <value name="UNLOCKED" caption="UO1WPR[n] &amp;amp; UO1WPRLOCK[n] bits are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="UO1WPR[n] &amp;amp; UO1WPRLOCK[n] bits are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1AWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1WP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__RCWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__VSSWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__TWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enable" value="1"/>
+      </value-group>
+      <value-group name="CWP__COWP">
+        <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+        <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1AWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__BC1WPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__RCWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__VSSWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__TWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+      <value-group name="CWP__COWPLOCK">
+        <value name="UNLOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+        <value name="LOCKED" caption="The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+      </value-group>
+    </module>
+    <module name="FPB" id="SYSTEM_IP" version="1.0.0" caption="Flash Patch and Breakpoint">
+      <register-group name="FPB" caption="Flash Patch and Breakpoint">
+        <register name="FP_CTRL" offset="0x0" rw="RW" size="4" access-size="4" caption="Flash Patch Control Register">
+          <bitfield name="ENABLE" caption="Flash Patch global enable" mask="0x1"/>
+          <bitfield name="KEY" caption="FP_CTRL write-enable key" mask="0x2"/>
+          <bitfield name="NUM_CODE" caption="Number of implemented code comparators bits [3:0]" mask="0xF0"/>
+          <bitfield name="NUM_LIT" caption="Number of literal comparators" mask="0xF00"/>
+          <bitfield name="NUM_CODE_1" caption="Number of implemented code comparators bits [6:4]" mask="0x7000"/>
+          <bitfield name="REV" caption="Revision" mask="0xF0000000"/>
+        </register>
+        <register name="FP_REMAP" offset="0x4" rw="R" size="4" access-size="4" caption="Flash Patch Remap Register">
+          <bitfield name="REMAP" caption="Remap address" mask="0x1FFFFFE0"/>
+          <bitfield name="RMPSPT" caption="Remap supported" mask="0x20000000"/>
+        </register>
+        <register name="FP_COMP" offset="0x8" rw="RW" size="4" access-size="4" count="4" caption="Flash Patch Comparator Register n">
+          <mode name="BREAKPOINT"/>
+          <mode name="DEFAULT"/>
+          <bitfield name="BE" caption="Breakpoint enable" mask="0x1"/>
+          <bitfield modes="DEFAULT" name="FPADDR" caption="Flash Patch address" mask="0x1FFFFFFC"/>
+          <bitfield modes="DEFAULT" name="FE" caption="Flash Patch enable" mask="0x80000000"/>
+          <bitfield modes="BREAKPOINT" name="BPADDR" caption="Breakpoint address" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="FP_LAR" offset="0xFB0" rw="W" size="4" access-size="4" caption="FPB Software Lock Access Register">
+          <bitfield name="KEY" caption="Lock access control" mask="0xFFFFFFFF" values="FP_LAR__KEY"/>
+        </register>
+        <register name="FP_LSR" offset="0xFB4" rw="R" size="4" access-size="4" caption="FPB Software Lock Status Register">
+          <bitfield name="SLI" caption="Software Lock implemented" mask="0x1"/>
+          <bitfield name="SLK" caption="Software Lock status" mask="0x2"/>
+          <bitfield name="nTT" caption="Not thirty-two bit" mask="0x4"/>
+        </register>
+        <register name="FP_DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" initval="0x47701A03" caption="FPB Device Architecture Register">
+          <bitfield name="ARCHPART" caption="Architecture Part" mask="0xFFF"/>
+          <bitfield name="ARCHVER" caption="Architecture Version" mask="0xF000"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF0000"/>
+          <bitfield name="PRESENT" caption="DEVARCH Present" mask="0x100000"/>
+          <bitfield name="ARCHITECT" caption="Architect" mask="0xFFE00000"/>
+        </register>
+        <register name="FP_DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" initval="0x00000000" caption="FPB Device Type Register">
+          <bitfield name="MAJOR" caption="Major type" mask="0xF"/>
+          <bitfield name="SUB" caption="Sub-type" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR4" offset="0xFD0" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 4">
+          <bitfield name="DES_2" caption="JEP106 continuation code" mask="0xF"/>
+          <bitfield name="SIZE" caption="4KB count" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR5" offset="0xFD4" rw="R" size="4" access-size="4" initval="0x00000000" caption="FP Peripheral Identification Register 5"/>
+        <register name="FP_PIDR6" offset="0xFD8" rw="R" size="4" access-size="4" initval="0x00000000" caption="FP Peripheral Identification Register 6"/>
+        <register name="FP_PIDR7" offset="0xFDC" rw="R" size="4" access-size="4" initval="0x00000000" caption="FP Peripheral Identification Register 7"/>
+        <register name="FP_PIDR0" offset="0xFE0" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 0">
+          <bitfield name="PART_0" caption="Part number bits[7:0]" mask="0xFF"/>
+        </register>
+        <register name="FP_PIDR1" offset="0xFE4" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 1">
+          <bitfield name="PART_1" caption="Part number bits[11:8]" mask="0xF"/>
+          <bitfield name="DES_0" caption="JEP106 identification code bits [3:0]" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR2" offset="0xFE8" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 2">
+          <bitfield name="DES_1" caption="JEP106 identification code bits[6:4]" mask="0x7"/>
+          <bitfield name="JEDEC" caption="JEDEC assignee value is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Component revision" mask="0xF0"/>
+        </register>
+        <register name="FP_PIDR3" offset="0xFEC" rw="R" size="4" access-size="4" caption="FP Peripheral Identification Register 3">
+          <bitfield name="CMOD" caption="Customer Modified" mask="0xF"/>
+          <bitfield name="REVAND" caption="RevAnd" mask="0xF0"/>
+        </register>
+        <register name="FP_CIDR0" offset="0xFF0" rw="R" size="4" access-size="4" initval="0x0000000D" caption="FP Component Identification Register 0">
+          <bitfield name="PRMBL_0" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="FP_CIDR1" offset="0xFF4" rw="R" size="4" access-size="4" initval="0x00000090" caption="FP Component Identification Register 1">
+          <bitfield name="PRMBL_1" caption="CoreSight component identification preamble" mask="0xF"/>
+          <bitfield name="CLASS" caption="CoreSight component class" mask="0xF0"/>
+        </register>
+        <register name="FP_CIDR2" offset="0xFF8" rw="R" size="4" access-size="4" initval="0x00000005" caption="FP Component Identification Register 2">
+          <bitfield name="PRMBL_2" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+        <register name="FP_CIDR3" offset="0xFFC" rw="R" size="4" access-size="4" initval="0x000000B1" caption="FP Component Identification Register 3">
+          <bitfield name="PRMBL_3" caption="CoreSight component identification preamble" mask="0xFF"/>
+        </register>
+      </register-group>
+      <value-group name="FP_LAR__KEY">
+        <value name="UNLOCK" caption="Unlock key value" value="0xC5ACCE55"/>
+      </value-group>
+    </module>
+    <module name="FREQM" id="03707" name2="clk_freqm_u2257_v3" version="3a0" caption="Frequency Meter">
+      <register-group name="FREQM" caption="Frequency Meter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x80" caption="Control A Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run In Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B Register">
+          <bitfield name="START" caption="Start Measurement" mask="0x1"/>
+        </register>
+        <register name="CFGA" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Config A Register">
+          <bitfield name="REFNUM" caption="Number of Reference Clock Cycles" mask="0xFF"/>
+          <bitfield name="MSRSEL" caption="Measurement Clock Selection" mask="0x700" values="CFGA__MSRSEL"/>
+          <bitfield name="DIVREF" caption="Divide Reference Clock" mask="0x8000" values="CFGA__DIVREF"/>
+        </register>
+        <register name="CTRLC" offset="0x4" rw="RW" size="1" initval="0x00" caption="Control C Register">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="CTRLC__WINMODE"/>
+        </register>
+        <register name="EVCTRL" offset="0x6" rw="RW" size="1" initval="0x00" caption="Event Control Register">
+          <bitfield name="STARTEI" caption="Start Measurement Event Input Enable" mask="0x1"/>
+          <bitfield name="STARTINV" caption="Start Measurement Event Invert Enable" mask="0x2"/>
+          <bitfield name="DONEEO" caption="Measurement Done Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear Register">
+          <bitfield name="DONE" caption="Measurement Done Interrupt Disable" mask="0x1"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Disable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set Register">
+          <bitfield name="DONE" caption="Measurement Done Interrupt Enable" mask="0x1"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0xA" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Register">
+          <bitfield name="DONE" caption="Measurement Done" mask="0x1"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0xB" rw="RW" size="1" initval="0x00" caption="Status Register">
+          <bitfield name="BUSY" caption="FREQM Status" mask="0x1"/>
+          <bitfield name="OVF" caption="Sticky Count Value Overflow" mask="0x2"/>
+        </register>
+        <register name="SYNCBUSY" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="VALUE" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Count Value Register">
+          <bitfield name="VALUE" caption="Measurement Value" mask="0xFFFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="CFGA__MSRSEL">
+        <value name="GCLK" caption="GCLK Input Clock" value="0x0"/>
+        <value name="CPU" caption="CPU Input Clock" value="0x1"/>
+      </value-group>
+      <value-group name="CFGA__DIVREF">
+        <value name="DIV1" caption="The reference clock is divided by 1" value="0x0"/>
+        <value name="DIV8" caption="The reference clock is divided by 8" value="0x1"/>
+      </value-group>
+      <value-group name="CTRLC__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="VALUE &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="VALUE &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="WINLT &lt; VALUE &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="!(WINLT &lt; VALUE &lt; WINUT)" value="0x4"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="fuses" name2="fuses" version="1a0" caption="Defines FUSES module data">
+      <register-group name="FUSES_ROMCFG" caption="Defines FUSES module data">
+        <register name="DAL" offset="0x0" rw="RW" size="4" caption="DEVICE ACCESS LEVEL Register">
+          <bitfield name="DAL_CPU" caption="CPU Device Access Level" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FRCFGBROM" offset="0x400" rw="RW" size="4" caption="PRE-BOOT bromc user Options Register">
+          <bitfield name="BCRCDIS" caption="Boot ROM CRC Disable" mask="0x1"/>
+        </register>
+        <register name="FRCFGMBIST" offset="0x408" rw="RW" size="4" caption="PRE-BOOT MBIST user Options Register">
+          <bitfield name="MOBH" caption="MBIST On Boot Enable for HIBERNATE Only Retaining Memory Groups" mask="0xC" values="FRCFGMBIST__MOBH"/>
+          <bitfield name="MOBB" caption="MBIST On Boot Enable for BACKUP/HIBERNATE Retaining Memory Groups" mask="0x30" values="FRCFGMBIST__MOBB"/>
+</register>
+            <register name="KEYVAL_INTCHK0" offset="0x420" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK1" offset="0x424" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK2" offset="0x428" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK3" offset="0x42C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK4" offset="0x430" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK5" offset="0x434" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK6" offset="0x438" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_INTCHK7" offset="0x43C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_INTCHK7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL0" offset="0x440" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL1" offset="0x444" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL2" offset="0x448" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL3" offset="0x44C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL4" offset="0x450" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL5" offset="0x454" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL6" offset="0x458" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_ALL7" offset="0x45C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_ALL7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR0" offset="0x460" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR1" offset="0x464" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR2" offset="0x468" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR3" offset="0x46C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR4" offset="0x470" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR5" offset="0x474" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR6" offset="0x478" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S_CR7" offset="0x47C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S_CR7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S0" offset="0x480" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S1" offset="0x484" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S2" offset="0x488" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S3" offset="0x48C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S4" offset="0x490" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S5" offset="0x494" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S6" offset="0x498" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_S7" offset="0x49C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_S7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR0" offset="0x4A0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR1" offset="0x4A4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR2" offset="0x4A8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR3" offset="0x4AC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR4" offset="0x4B0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR5" offset="0x4B4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR6" offset="0x4B8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS_CR7" offset="0x4BC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS_CR7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS0" offset="0x4C0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS1" offset="0x4C4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS2" offset="0x4C8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS3" offset="0x4CC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS4" offset="0x4D0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS5" offset="0x4D4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS6" offset="0x4D8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_CE_NS7" offset="0x4DC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_CE_NS7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG0" offset="0x4E0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG1" offset="0x4E4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG2" offset="0x4E8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG3" offset="0x4EC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG4" offset="0x4F0" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG5" offset="0x4F4" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG6" offset="0x4F8" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_PRG_PG7" offset="0x4FC" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_PRG_PG7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_0" offset="0x500" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_1" offset="0x504" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_2" offset="0x508" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_3" offset="0x50C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_4" offset="0x510" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_5" offset="0x514" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_6" offset="0x518" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL1_7" offset="0x51C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL1_7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_0" offset="0x520" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_1" offset="0x524" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_2" offset="0x528" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_3" offset="0x52C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_4" offset="0x530" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_5" offset="0x534" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_6" offset="0x538" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_SDAL0_7" offset="0x53C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_SDAL0_7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL0" offset="0x540" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL0" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL1" offset="0x544" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL1" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL2" offset="0x548" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL2" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL3" offset="0x54C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL3" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL4" offset="0x550" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL4" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL5" offset="0x554" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL5" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL6" offset="0x558" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL6" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="KEYVAL_DAL_EL7" offset="0x55C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="KEYVAL_DAL_EL7" caption="" mask="0xFFFFFFFF"/>
+            </register>
+            <register name="PUF_AC" offset="0xC00" rw="RW" size="4" count="249" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="PUF_AC" caption="" mask="0xFFFFFFFF"/>
+            </register>
+        </register-group>
+        <register-group name="FUSES_BOOTCFG1" caption="Defines FUSES module data">
+            <register name="DEVSIGN" offset="0xC" rw="RW" size="4" initval="0xFFFFFFFF" caption="DEVSIGN">
+            <bitfield name="SEQ" caption="Sequence number" mask="0x0000FFFF"/>
+            <bitfield name="SEQBAR" caption="Sequence number BAR" mask="0xFFFF0000"/>
+            </register>
+            <register name="BOOT_FLAG" offset="0x800" rw="RW" size="4" initval="0xFFFFFFF9" caption="BOOT CODE FLAGS REGISTER">
+            <bitfield name="PUFRETRY" caption="PUF Retry" mask="0x2"/>
+            <bitfield name="PUFSTARTUP" caption="PUF Start Up Mode" mask="0x4"/>
+            <bitfield name="DICEDIS" caption="Device Identifier Composition Engine Disable" mask="0x8"/>
+            <bitfield name="BOOTMODE" caption="Boot Mode" mask="0x10"/>
+            <bitfield name="RAM_INIT_ENB" caption="RAM ECC Enable" mask="0x40"/>
+            <bitfield name="PUFSCORE" caption="PUF Score Value" mask="0x700" values="BOOT_FLAG__PUFSCORE"/>
+            </register>
+            <register name="DICE_CDI_INDEX" offset="0x810" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="DICE_CDI_INDEX" caption="" mask="0x7F"/>
+            </register>
+            <register name="DICE_FW_HASH_INDEX" offset="0x814" rw="RW" size="4" initval="0xFFFFFFFF" caption="Mapped Fuse Register">
+            <bitfield name="DICE_FW_HASH_INDEX" caption="" mask="0x7F"/>
+            </register>
+            <register name="BOOT_GPIOSEL" offset="0x818" rw="RW" size="4" initval="0xFFFFFFFF" caption="BOOT EXTERNAL NOTIFICATION IO PIN REGISTER">
+            <bitfield name="GPIOPINSEL" caption="Selects IO Port Pin for Boot External Notification Signal" mask="0x1F"/>
+            <bitfield name="GPIOPORTSEL" caption="Selects IO Port for Boot External Notification Signal" mask="0x1E0"/>
+            <bitfield name="FLTPOL" caption="Selects IO Port for Boot External Notification Signal" mask="0x200"/>
+            <bitfield name="FLTODRAIN" caption="Open Drain Control for Boot External Notification Signal" mask="0x800"/>
+            <bitfield name="FLTSLEWLIM" caption="Selects Driver Slew Rate Selection for Boot External Notification Signal" mask="0x3000"/>
+            </register>
+            <register name="H2PB0_NONSECCLRA" offset="0x81C" rw="RW" size="4" initval="0xFFFFFFFE" caption="Non-Security Clear Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="H2PB0_NONSECSETA" offset="0x820" rw="RW" size="4" initval="0x00000001" caption="Non-Security SET Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="PAC_WRCTRL_H2PB0" offset="0x830" rw="RW" size="4" initval="0x00000013" caption="Write Control Register">
+            <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+            <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="PAC_WRCTRL_H2PB0__KEY"/>
+            </register>
+            <register name="H2PB1_NONSECCLRA" offset="0x834" rw="RW" size="4" initval="0xFFFFFFFF" caption="Non-Security Clear Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="H2PB1_NONSECSETA" offset="0x838" rw="RW" size="4" initval="0x00000000" caption="Non-Security SET Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="PAC_WRCTRL_H2PB1" offset="0x848" rw="RW" size="4" initval="0x0000002E" caption="Write Control Register">
+            <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+            <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="PAC_WRCTRL_H2PB1__KEY"/>
+            </register>
+            <register name="H2PB2_NONSECCLRA" offset="0x84C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Non-Security Clear Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="H2PB2_NONSECSETA" offset="0x850" rw="RW" size="4" initval="0x00000000" caption="Non-Security SET Register A">
+            <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+            <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+            <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+            <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+            <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+            <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+            <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+            <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+            <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+            <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+            <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+            <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+            <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+            <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+            <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+            <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+            <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+            <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+            <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+            <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+            <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+            <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+            <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+            <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+            <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+            <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+            <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+            <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+            <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+            <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+            <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+            <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+            </register>
+            <register name="PAC_WRCTRL_H2PB2" offset="0x860" rw="RW" size="4" initval="0x0000002F" caption="Write Control Register">
+            <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+            <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="PAC_WRCTRL_H2PB2__KEY"/>
+            </register>
+            <register name="IDAU_RCTRL_BFM" offset="0x864" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control BFM Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control BFM Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control BFM Command" mask="0xFF000000" values="IDAU_RCTRL_BFM_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control BFM Command" mask="0xFF000000" values="IDAU_RCTRL_BFM_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_RCTRL_PFMANS" offset="0x868" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control PFMANS Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control PFMAN Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control PFMAN Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANS_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control PFMAN Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANS_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_RCTRL_PFMANSC" offset="0x86C" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control PFMANSC Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control PFMANSC Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control PFMANSC Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANSC_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control PFMANSC Command" mask="0xFF000000" values="IDAU_RCTRL_PFMANSC_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_RCTRL_DRM" offset="0x870" rw="RW" size="4" initval="0x5C000000" caption="Region Control">
+            <mode name="BLOCK" caption="Block Based Region"/>
+            <mode name="WATERMARK" caption="Watermark Based Region"/>
+            <bitfield modes="BLOCK" name="ARG" caption="IDAU Region Control DRM Command Argument (Block ID)" mask="0x1F"/>
+            <bitfield modes="WATERMARK" name="ARG" caption="IDAU Region Control DRM Command Argument (Watermark)" mask="0xFFFFFF"/>
+            <bitfield modes="BLOCK" name="CMD" caption="IDAU Region Control DRM Command" mask="0xFF000000" values="IDAU_RCTRL_DRM_BLOCK__CMD"/>
+            <bitfield modes="WATERMARK" name="CMD" caption="IDAU Region Control DRM Command" mask="0xFF000000" values="IDAU_RCTRL_DRM_WATERMARK__CMD"/>
+            </register>
+            <register name="IDAU_CTRL_EN" offset="0x874" rw="RW" size="4" initval="0xA5010000" caption="Control">
+            <bitfield name="CMD" caption="IDAU Enable Command Register" mask="0xFFFF0000" values="IDAU_CTRL_EN__CMD"/>
+            </register>
+            <register name="IDAU_CTRL_WLCK" offset="0x878" rw="RW" size="4" initval="0xFFFFFFFF" caption="Control">
+            <bitfield name="CMD" caption="IDAU Write Lock Command Register" mask="0xFFFF0000" values="IDAU_CTRL_WLCK__CMD"/>
+            </register>
+            <register name="FCW_CWP" offset="0x87C" rw="RW" size="4" initval="0x00000000" caption="CFM Page Write Protect REGISTER">
+            <bitfield name="BC1AWP" caption="Panel 1 Write Protect BootCfg1A" mask="0x1" values="FCW_CWP__BC1AWP"/>
+            <bitfield name="BC1WP" caption="Panel 1 Write Protect BootCfg1" mask="0x4" values="FCW_CWP__BC1WP"/>
+            <bitfield name="RCWP" caption="Panel 1 Write Protect ROMCfg" mask="0x8" values="FCW_CWP__RCWP"/>
+            <bitfield name="VSSWP0" caption="Panel 1 Write Protect VSSn" mask="0x10" values="FCW_CWP__VSSWP"/>
+            <bitfield name="VSSWP1" caption="Panel 1 Write Protect VSSn" mask="0x20" values="FCW_CWP__VSSWP"/>
+            <bitfield name="BC1AWPLOCK" caption="Panel 1 Lock Write Protection BootCfg1A" mask="0x10000" values="FCW_CWP__BC1AWPLOCK"/>
+            <bitfield name="BC1WPLOCK" caption="Panel 1 Lock Write Protection BootCfg1" mask="0x40000" values="FCW_CWP__BC1WPLOCK"/>
+            <bitfield name="RCWPLOCK" caption="Panel 1 Lock Write Protection ROMCfg" mask="0x80000" values="FCW_CWP__RCWPLOCK"/>
+            <bitfield name="VSSWPLOCK0" caption="Panel 1 Lock Write Protection VSSn" mask="0x100000" values="FCW_CWP__VSSWPLOCK"/>
+            <bitfield name="VSSWPLOCK1" caption="Panel 1 Lock Write Protection VSSn" mask="0x200000" values="FCW_CWP__VSSWPLOCK"/>
+            </register>
+            <register name="FCR_CRP" offset="0x880" rw="RW" size="4" initval="0x00000000" caption="CFM Page Read Protection Register">
+            <bitfield name="BC1ARP" caption="Panel 1 Read Protect BootCfg1A" mask="0x1" values="FCR_CRP__BC1ARP"/>
+            <bitfield name="BC1RP" caption="Panel 1 Read Protect BootCfg1" mask="0x4" values="FCR_CRP__BC1RP"/>
+            <bitfield name="RCRP" caption="Panel 1 Read Protect ROMCfg" mask="0x8" values="FCR_CRP__RCRP"/>
+            <bitfield name="VSSRP0" caption="Panel 1 Read Protect VSSn" mask="0x10" values="FCR_CRP__VSSRP"/>
+            <bitfield name="VSSRP1" caption="Panel 1 Read Protect VSSn" mask="0x20" values="FCR_CRP__VSSRP"/>
+            <bitfield name="BC1ARPLOCK" caption="Panel 1 Lock Read Protection BootCfg1A" mask="0x10000" values="FCR_CRP__BC1ARPLOCK"/>
+            <bitfield name="BC1RPLOCK" caption="Panel 1 Lock Read Protection BootCfg1" mask="0x40000" values="FCR_CRP__BC1RPLOCK"/>
+            <bitfield name="RCRPLOCK" caption="Panel 1 Lock Read Protection ROMCfg" mask="0x80000" values="FCR_CRP__RCRPLOCK"/>
+            <bitfield name="VSSRPLOCK0" caption="Panel 1 Lock Read Protection VSSn" mask="0x100000" values="FCR_CRP__VSSRPLOCK"/>
+            <bitfield name="VSSRPLOCK1" caption="Panel 1 Lock Read Protection VSSn" mask="0x200000" values="FCR_CRP__VSSRPLOCK"/>
+            </register>
+            <register name="FCR_ECCCTRL" offset="0x884" rw="RW" size="4" initval="0x00000070" caption="ECC Control REGISTER">
+            <bitfield name="ECCCTL" caption="NVM ECC Mode Control - restricts one or more NVMOPs" mask="0x30" values="FCR_ECCCTRL__ECCCTL"/>
+            <bitfield name="ECCUNLCK" caption="NVM ECC Mode Control Unlock" mask="0x40" values="FCR_ECCCTRL__ECCUNLCK"/>
+            <bitfield name="SECCNT" caption="Flash SEC Count" mask="0xFF00"/>
+            </register>
+            <register name="SUPC_BRCFGUSMOR_BOR" offset="0x888" rw="RW" size="4" initval="0x00000000" caption="Boot Rom Configurable SMOR User CFG BOR register">
+            <bitfield name="HYST_BOR_VDDIO" caption="Refer to pwr_smor_[nn]_v2 DOS document for details." mask="0x1" values="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDIO"/>
+            <bitfield name="BOR_TRIP_VDDIO" caption="Nominal BOR Trip, Refer to pwr_smor_[nn]_v2 DOS document for details." mask="0x6" values="SUPC_BRCFGUSMOR_BOR__BOR_TRIP_VDDIO"/>
+            <bitfield name="HYST_BOR_VDDREG" caption="Refer to pwr_smor_[nn]_v2 DOS document for details." mask="0x400" values="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDREG"/>
+            </register>
+            <register name="SUPC_BRCFGUDSSMOR" offset="0x890" rw="RW" size="4" initval="0x00000000" caption="Boot Rom Configurable DSSMOR User CFG register">
+            <bitfield name="BOR_HYST" caption="Refer to pwr_smor_ds_[nn]_v2 DOS document for details." mask="0x1" values="SUPC_BRCFGUDSSMOR__BOR_HYST"/>
+            <bitfield name="BOR_TRIP" caption="Nominal BOR Trip, Refer to pwr_smor_ds_[nn]_v2 DOS document for details." mask="0x6" values="SUPC_BRCFGUDSSMOR__BOR_TRIP"/>
+            </register>
+            <register name="SUPC_BRCFGUCP0" offset="0x894" rw="RW" size="4" initval="0x00000001" caption="Boot Rom Configurable CHARGE PUMP User CFG register">
+            <bitfield name="CP" caption="Refer to vreg_chrg_pump_v4 DOS document for details." mask="0xF" values="SUPC_BRCFGUCP0__CP"/>
+            </register>
+            <register name="WDT_SETUP" offset="0x898" rw="RW" size="4" initval="0x00000000" caption="">
+            <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+            <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+            <bitfield name="RUNSTDBY" caption="Run During Standby" mask="0x40"/>
+            <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+            <bitfield name="PER" caption="Time-Out Period" mask="0xF00" values="WDT_SETUP__PER"/>
+            <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF000" values="WDT_SETUP__WINDOW"/>
+            <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF0000" values="WDT_SETUP__EWOFFSET"/>        </register>
+      </register-group>
+      <register-group name="FUSES_CALOTP" caption="Defines FUSES module data">
+        <register name="F1RR" offset="0x0" rw="R" size="4" caption="PANEL 0 REDUNDANCY RECORD 1-0 Register">
+          <bitfield name="RR0ADDR" caption="Redundancy Replaced Page Address" mask="0x7F"/>
+          <bitfield name="RR0DIS" caption="Redundancy Record 0 enabled" mask="0x8000" values="F1RR__RR0DIS"/>
+          <bitfield name="RR1ADDR" caption="Redundancy Replaced Page Address" mask="0x7F0000"/>
+          <bitfield name="RR1DIS" caption="Redundancy Record 1 enabled" mask="0x80000000" values="F1RR__RR1DIS"/>
+        </register>
+        <register name="FCCFG0" offset="0x80" rw="R" size="4" caption="Calibration Configuration 0 Register">
+          <bitfield name="CFG_SMOR0" caption="SMOR configuration bits" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG1" offset="0x84" rw="R" size="4" caption="Calibration Configuration 1 Register">
+          <bitfield name="CFG_SMOR1" caption="SMOR configuration bits" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG8" offset="0xA0" rw="R" size="4" caption="Calibration Configuration 8 Register">
+          <bitfield name="CFG_DS_SMOR_REF" caption="DSSMOR configuration bits" mask="0xFFFF"/>
+          <bitfield name="CFG_DS_SMOR_CLK" caption="DSSMOR configuration bits" mask="0xFFFF0000"/>
+        </register>
+        <register name="FCCFG16" offset="0xC0" rw="R" size="4" caption="Calibration Configuration 16 Register">
+          <bitfield name="CFG_DFLL48M" caption="Comparator configuration bits" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG17" offset="0xC4" rw="R" size="4" caption="Calibration Configuration 17 Register">
+          <bitfield name="CFG_XTAL_HF" caption="Crystal Oscillator calibration configuration bits" mask="0xFFFF"/>
+        </register>
+        <register name="FCCFG24" offset="0xE0" rw="R" size="4" caption="Calibration Configuration 24 Register">
+          <bitfield name="CFG_CALVREGSW0" caption="99 ma VREG Calibration configuration bits" mask="0xFFFF"/>
+        </register>
+        <register name="FCCFG27" offset="0xEC" rw="R" size="4" caption="Calibration Configuration 27 Register">
+          <bitfield name="CFG_CALVREGRAM" caption="50 ma VREG Calibration configuration bits" mask="0xFFFF0000"/>
+        </register>
+        <register name="FCCFG28" offset="0xF0" rw="R" size="4" caption="Calibration Configuration 28 Register">
+          <bitfield name="CALCP" caption="Charge Pump Calibration  configuration bits for all charge pumps" mask="0xF"/>
+          <bitfield name="CALSUPC" caption="RPMU / SUPC configuration bits" mask="0xFF00"/>
+        </register>
+        <register name="FCCFG29" offset="0xF4" rw="R" size="4" caption="Calibration Configuration 29 Register">
+          <bitfield name="CALUSERLDO" caption="User LDO Calibration  configuration bits" mask="0xFF"/>
+        </register>
+        <register name="FCCFG32" offset="0x100" rw="R" size="4" caption="DSU Device Configuration 0 Register (DEVID)">
+          <bitfield name="PFM_SZ" caption="Program Flash Memory (PFM) Size on Device" mask="0xF" values="FCCFG32__PFM_SZ"/>
+          <bitfield name="DRM_SZ" caption="Data Ram Memory (DRM) Size on Device" mask="0xFF00" values="FCCFG32__DRM_SZ"/>
+          <bitfield name="FPACKAGE" caption="Number of Pins present on the Package" mask="0xF0000" values="FCCFG32__FPACKAGE"/>
+          <bitfield name="DEVSEL" caption="Device Variant Configuration" mask="0xFF000000"/>
+        </register>
+        <register name="FCCFG33" offset="0x104" rw="R" size="4" caption="DSU Device Configuration 1 Register">
+          <bitfield name="ME_HSM" caption="Module enables for Variant configuration" mask="0x80" values="FCCFG33__ME_HSM"/>
+          <bitfield name="ME_TCC0" caption="Module enables for Variant configuration" mask="0x100" values="FCCFG33__ME_TCC0"/>
+          <bitfield name="ME_TCC1" caption="Module enables for Variant configuration" mask="0x200" values="FCCFG33__ME_TCC1"/>
+          <bitfield name="ME_TCC2" caption="Module enables for Variant configuration" mask="0x400" values="FCCFG33__ME_TCC2"/>
+          <bitfield name="ME_TCC3" caption="Module enables for Variant configuration" mask="0x800" values="FCCFG33__ME_TCC3"/>
+          <bitfield name="ME_TCC4" caption="Module enables for Variant configuration" mask="0x1000" values="FCCFG33__ME_TCC4"/>
+          <bitfield name="ME_TCC5" caption="Module enables for Variant configuration" mask="0x2000" values="FCCFG33__ME_TCC5"/>
+          <bitfield name="ME_TCC6" caption="Module enables for Variant configuration" mask="0x4000" values="FCCFG33__ME_TCC6"/>
+          <bitfield name="ME_SERCOM0" caption="Module enables for Variant configuration" mask="0x40000" values="FCCFG33__ME_SERCOM0"/>
+          <bitfield name="ME_SERCOM1" caption="Module enables for Variant configuration" mask="0x80000" values="FCCFG33__ME_SERCOM1"/>
+          <bitfield name="ME_SERCOM2" caption="Module enables for Variant configuration" mask="0x100000" values="FCCFG33__ME_SERCOM2"/>
+          <bitfield name="ME_SERCOM3" caption="Module enables for Variant configuration" mask="0x200000" values="FCCFG33__ME_SERCOM3"/>
+          <bitfield name="ME_SERCOM4" caption="Module enables for Variant configuration" mask="0x400000" values="FCCFG33__ME_SERCOM4"/>
+          <bitfield name="ME_SERCOM5" caption="Module enables for Variant configuration" mask="0x800000" values="FCCFG33__ME_SERCOM5"/>
+          <bitfield name="ME_PTC" caption="Module enables for Variant configuration" mask="0x10000000" values="FCCFG33__ME_PTC"/>
+        </register>
+        <register name="FCCFG34" offset="0x108" rw="R" size="4" caption="DSU Device Configuration 2 Register">
+          <bitfield name="ME_CAN0" caption="Module enables for Variant configuration" mask="0x1" values="FCCFG34__ME_CAN0"/>
+          <bitfield name="ME_CAN1" caption="Module enables for Variant configuration" mask="0x2" values="FCCFG34__ME_CAN1"/>
+          <bitfield name="ME_USBFS" caption="Module enables for Variant configuration" mask="0x200" values="FCCFG34__ME_USBFS"/>
+          <bitfield name="ME_DPA" caption="Module enables for Variant configuration" mask="0x800000" values="FCCFG34__ME_DPA"/>
+          <bitfield name="ME_TRAM" caption="Module enables for Variant configuration" mask="0x40000000" values="FCCFG34__ME_TRAM"/>
+          <bitfield name="ME_PUF" caption="Module enables for Variant configuration" mask="0x80000000" values="FCCFG34__ME_PUF"/>
+        </register>
+        <register name="FCCFG49" offset="0x144" rw="R" size="4" caption="Calibration Configuration 49 Register">
+          <bitfield name="RAMC_EMAW" caption="Write Time Extra Margin Adjust" mask="0x3" values="FCCFG49__RAMC_EMAW"/>
+          <bitfield name="RAMC_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x1C" values="FCCFG49__RAMC_EMA"/>
+          <bitfield name="RAMAB_EMAW" caption="Write Time Extra Margin Adjust" mask="0xC0"/>
+          <bitfield name="RAMAB_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x700"/>
+          <bitfield name="TRAM_EMAW" caption="Write Time Extra Margin Adjust" mask="0x3000"/>
+          <bitfield name="TRAM_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x1C000"/>
+          <bitfield name="TRAM_EMAS" caption="Sense Amp Extra Margin Adjust" mask="0x20000" values="FCCFG49__TRAM_EMAS"/>
+          <bitfield name="BROM_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x700000"/>
+          <bitfield name="PUF_EMAW" caption="Write Time Extra Margin Adjust" mask="0x3000000"/>
+          <bitfield name="PUF_EMA" caption="Cycle and Read Time Extra Margin Adjust" mask="0x1C000000"/>
+          <bitfield name="PUF_EMAS" caption="Sense Amp Extra Margin Adjust" mask="0x20000000" values="FCCFG49__PUF_EMAS"/>
+        </register>
+        <register name="FCCFG56" offset="0x160" rw="R" size="4" caption="Calibration Configuration 56 Register">
+          <bitfield name="BRINGOSC" caption="SUPC Ring-osc depth" mask="0x3" values="FCCFG56__BRINGOSC"/>
+          <bitfield name="DIS_BOR12_RAMON" caption="Disable BOR12 (VREGRAM comparator) when RAM are turned ON when leaving sleep mode" mask="0x10"/>
+          <bitfield name="DIS_BOR12_VSCALING" caption="Disable BOR12 (VREGRAM comparator) when down voltage scaling is on going from 1.2v to 0.8v to workaround VREG undershoot issue" mask="0x20"/>
+          <bitfield name="VLP2FPST" caption="Vreg Low Power to Full Power Stabilization Time" mask="0x30000" values="FCCFG56__VLP2FPST"/>
+          <bitfield name="VLPMST" caption="Vreg LP Mode Stabilization Time" mask="0xC0000" values="FCCFG56__VLPMST"/>
+          <bitfield name="VTONST" caption="Vreg Turned On Stabilization Time" mask="0x300000" values="FCCFG56__VTONST"/>
+          <bitfield name="VPDDST" caption="Vreg Pull Down Disable Stabilization Time" mask="0xC00000" values="FCCFG56__VPDDST"/>
+          <bitfield name="VDVSST" caption="Vreg Down Voltage Scaling Stabilization Time" mask="0x3000000" values="FCCFG56__VDVSST"/>
+        </register>
+        <register name="FCCFG57" offset="0x164" rw="R" size="4" caption="Calibration Configuration 57 Register">
+          <bitfield name="DLYVAL" caption="Delay Value" mask="0x7F"/>
+          <bitfield name="IGNACK" caption="Ignore Acknowledge" mask="0x80" values="FCCFG57__IGNACK"/>
+        </register>
+        <register name="FCCFG58" offset="0x168" rw="R" size="4" caption="Calibration Configuration 58 Register">
+          <bitfield name="BRINGOSC" caption="Backup Ring Oscillator Size Depth" mask="0x3" values="FCCFG58__BRINGOSC"/>
+        </register>
+        <register name="FCCFG59" offset="0x16C" rw="R" size="4" caption="Calibration Configuration 59 Register">
+          <bitfield name="IDAU_EN" caption="IDAU Enabled" mask="0x1" values="FCCFG59__IDAU_EN"/>
+        </register>
+        <register name="FCCFG60" offset="0x170" rw="R" size="4" caption="Calibration Configuration 60 Register">
+          <bitfield name="PUFRAMDNTIME" caption="PUF RAM Power Down Delay Time" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG61" offset="0x174" rw="R" size="4" caption="Calibration Configuration 61 Register">
+          <bitfield name="PUFRAMUPTIME" caption="PUF RAM Power Up Delay Time" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="FCCFG64" offset="0x180" rw="R" size="4" caption="Calibration Configuration 64 Register">
+          <bitfield name="PTC_CALIB_PTC_IBIAS_TRIM" caption="PTC IBIAS TRIM" mask="0x7"/>
+          <bitfield name="PTC_CALIB_PTAT_EN" caption="Enable PTAT current" mask="0x8"/>
+          <bitfield name="PTC_CALIB_EXT_IBIAS_EN" caption="Enable External Bias" mask="0x10"/>
+        </register>
+        <register name="FCCFG65" offset="0x184" rw="R" size="4" caption="Calibration Configuration 65 Register">
+          <bitfield name="EN_CMBF" caption="Enable Common Mode Power Cycling" mask="0x1"/>
+          <bitfield name="EN_DITHER" caption="Enable Dithering" mask="0x4"/>
+          <bitfield name="DIS_FAZ" caption="First Auto Zeroing" mask="0x8"/>
+          <bitfield name="DIS_SAZ" caption="Second Auto Zeroing" mask="0x10"/>
+          <bitfield name="DIS_LAZ" caption="Current Auto Zeroing" mask="0x20"/>
+          <bitfield name="EN_RDAC" caption="RDAC Duty Cycle" mask="0x40"/>
+          <bitfield name="DBG_SEL" caption="Enable Test Output" mask="0x80"/>
+          <bitfield name="SEL_DEL" caption="Select Value to comp_out" mask="0x100"/>
+          <bitfield name="T1_DELAY" caption="Programmable delay, selects the delay between regen and latch" mask="0x600"/>
+          <bitfield name="TCLK_DIV" caption="Programmable divider for adc_clk_div. The division ratio is 256, 128, 64,32, and 16 going from MSB to LSB." mask="0xF800"/>
+          <bitfield name="IADC_1" caption="Controls the current consumption for of the whole ADC" mask="0x300000"/>
+          <bitfield name="IADC_2" caption="Controls the current consumption for of the whole ADC." mask="0xC00000"/>
+          <bitfield name="ICMP_1" caption="Controls the bias current for 1 stage of the comparator. This will control the resolution needed by comparator. More current means less time but at expense of gain." mask="0x3000000"/>
+          <bitfield name="ICMP_2" caption="Controls the bias current for 2 stage of the comparator. This will control the resolution needed by comparator. More current means less time but at expense of gain." mask="0xC000000"/>
+          <bitfield name="ICMBF" caption="Controls the bias current for Common mode buffer amplifier (CMBF)" mask="0x30000000"/>
+          <bitfield name="EN_ATEST" caption="Enable analog test signals" mask="0x40000000"/>
+          <bitfield name="EN_EXT_BIAS" caption="Internal switched capacitor bias current allows to make the bias current proportional to conversion frequency." mask="0x80000000"/>
+        </register>
+        <register name="FCCFG66" offset="0x188" rw="R" size="4" caption="Calibration Configuration 66 Register">
+          <bitfield name="AC_CONFIG" caption="Comparator 0 Calibration Configuration bits.'" mask="0xF"/>
+        </register>
+        <register name="FCCFG68" offset="0x190" rw="R" size="4" caption="Calibration Configuration 68 Register">
+          <bitfield name="TRANSP" caption="USB PAD P Driver Configuration bits.'" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB PAD N Driver Configuration bits.'" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB PAD Rise/Fall Configuration bits.'" mask="0x7000"/>
+        </register>
+      </register-group>
+      <value-group name="FRCFGMBIST__MOBH">
+        <value name="ENABLED_ANY" caption="MOB runs after any non-BACKUP/HIBERNATE exit reset" value="1"/>
+        <value name="ENABLED_POR" caption="MOB runs only after a POR" value="2"/>
+        <value name="DISABLED" caption="MOB Disabled" value="3"/>
+</value-group>
+        <value-group name="BOOT_FLAG__PUFSCORE">
+            <value name="0" caption="0" value="0"/>
+            <value name="1" caption="1" value="1"/>
+            <value name="2" caption="2" value="2"/>
+            <value name="3" caption="3" value="3"/>
+            <value name="4" caption="4" value="4"/>
+            <value name="5" caption="5" value="5"/>
+            <value name="6" caption="6" value="6"/>
+            <value name="7" caption="7" value="7"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB0__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB1__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB2__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_EN__CMD">
+            <value name="ENABLE" caption="Module Enable" value="0xA501"/>
+            <value name="DISABLE" caption="Module Disable" value="0xA502"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_WLCK__CMD">
+            <value name="WLCK" caption="Write Lock" value="0xA503"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCCTL">
+            <value name="STRICT" caption="ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)" value="0"/>
+            <value name="DYNAMIC" caption="Dynamic Writes with Dynamic Reads" value="1"/>
+            <value name="ECC" caption="ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)" value="2"/>
+            <value name="DISABLE" caption="Dynamic Writes with No Error Check Reads" value="3"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCUNLCK">
+            <value name="LOCKED" caption="ECCUNLCK and ECCCTL[1:0] cannot be written" value="0"/>
+            <value name="UNLOCKED" caption="ECCUNLCK and ECCCTL[1:0] can be written" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDIO">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__BOR_TRIP_VDDIO">
+            <value name="0" caption="1.68V (default)" value="0"/>
+            <value name="1" caption="2.2V" value="1"/>
+            <value name="2" caption="2.64V" value="2"/>
+            <value name="3" caption="2.93V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDREG">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_HYST">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_TRIP">
+            <value name="0" caption="1.61V (default)" value="0"/>
+            <value name="1" caption="2.12V" value="1"/>
+            <value name="2" caption="2.55V" value="2"/>
+            <value name="3" caption="2.8V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUCP0__CP">
+            <value name="0" caption="Clock gating trip optimized for low output threshold voltage (3.01V)" value="0"/>
+            <value name="1" caption="Clock gating trip optimized for high output threshold voltage (3.2V) (default)" value="1"/>
+        </value-group>
+        <value-group name="WDT_SETUP__PER">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__WINDOW">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__EWOFFSET">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>      </value-group>
+      <value-group name="FRCFGMBIST__MOBB">
+        <value name="ENABLED_ANY" caption="MOB runs after any non-BACKUP/HIBERNATE exit reset" value="1"/>
+        <value name="ENABLED_POR" caption="MOB runs only after a POR" value="2"/>
+        <value name="DISABLED" caption="MOB Disabled" value="3"/>
+</value-group>
+        <value-group name="BOOT_FLAG__PUFSCORE">
+            <value name="0" caption="0" value="0"/>
+            <value name="1" caption="1" value="1"/>
+            <value name="2" caption="2" value="2"/>
+            <value name="3" caption="3" value="3"/>
+            <value name="4" caption="4" value="4"/>
+            <value name="5" caption="5" value="5"/>
+            <value name="6" caption="6" value="6"/>
+            <value name="7" caption="7" value="7"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB0__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB1__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="PAC_WRCTRL_H2PB2__KEY">
+            <value name="OFF" caption="OFF - No Action" value="0"/>
+            <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+            <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+            <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_BFM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANS_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_PFMANSC_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_BLOCK__CMD">
+            <value name="CLRNONSEC" caption="Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)" value="0x5A"/>
+            <value name="SETNONSEC" caption="Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)" value="0x5B"/>
+        </value-group>
+        <value-group name="IDAU_RCTRL_DRM_WATERMARK__CMD">
+            <value name="WRSZ" caption="Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)" value="0x5C"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_EN__CMD">
+            <value name="ENABLE" caption="Module Enable" value="0xA501"/>
+            <value name="DISABLE" caption="Module Disable" value="0xA502"/>
+        </value-group>
+        <value-group name="IDAU_CTRL_WLCK__CMD">
+            <value name="WLCK" caption="Write Lock" value="0xA503"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWP">
+            <value name="DISABLE" caption="Erase and Write Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Erase and Write Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1AWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__BC1WPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__RCWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCW_CWP__VSSWPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Write Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRP">
+            <value name="DISABLE" caption="Read Protection for this Page is Disabled" value="0"/>
+            <value name="ENABLE" caption="Read Protection for this Page is Enabled" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1ARPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__BC1RPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__RCRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_CRP__VSSRPLOCK">
+            <value name="UNLOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are NOT Locked and can be modified" value="0"/>
+            <value name="LOCKED" caption="The Lock &amp;amp;amp; Read Protect bits for this Page are Locked and cannot be modified" value="1"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCCTL">
+            <value name="STRICT" caption="ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)" value="0"/>
+            <value name="DYNAMIC" caption="Dynamic Writes with Dynamic Reads" value="1"/>
+            <value name="ECC" caption="ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)" value="2"/>
+            <value name="DISABLE" caption="Dynamic Writes with No Error Check Reads" value="3"/>
+        </value-group>
+        <value-group name="FCR_ECCCTRL__ECCUNLCK">
+            <value name="LOCKED" caption="ECCUNLCK and ECCCTL[1:0] cannot be written" value="0"/>
+            <value name="UNLOCKED" caption="ECCUNLCK and ECCCTL[1:0] can be written" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDIO">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__BOR_TRIP_VDDIO">
+            <value name="0" caption="1.68V (default)" value="0"/>
+            <value name="1" caption="2.2V" value="1"/>
+            <value name="2" caption="2.64V" value="2"/>
+            <value name="3" caption="2.93V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUSMOR_BOR__HYST_BOR_VDDREG">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_HYST">
+            <value name="LOW" caption="Low Hysteresis (default)" value="0"/>
+            <value name="HIGH" caption="High Hysteresis" value="1"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUDSSMOR__BOR_TRIP">
+            <value name="0" caption="1.61V (default)" value="0"/>
+            <value name="1" caption="2.12V" value="1"/>
+            <value name="2" caption="2.55V" value="2"/>
+            <value name="3" caption="2.8V" value="3"/>
+        </value-group>
+        <value-group name="SUPC_BRCFGUCP0__CP">
+            <value name="0" caption="Clock gating trip optimized for low output threshold voltage (3.01V)" value="0"/>
+            <value name="1" caption="Clock gating trip optimized for high output threshold voltage (3.2V) (default)" value="1"/>
+        </value-group>
+        <value-group name="WDT_SETUP__PER">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__WINDOW">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+        </value-group>
+        <value-group name="WDT_SETUP__EWOFFSET">
+            <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+            <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+            <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+            <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+            <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+            <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+            <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+            <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+            <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+            <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+            <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+            <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>      </value-group>
+      <value-group name="F1RR__RR0DIS">
+        <value name="0" caption="FCR maps the redundant page 0 into the address defined by RR0ADDR" value="0"/>
+        <value name="1" caption="Redundant page 0 mapping is Disabled" value="1"/>
+      </value-group>
+      <value-group name="F1RR__RR1DIS">
+        <value name="0" caption="FCR maps the redundant page 1 into the address defined by RR1ADDR" value="0"/>
+        <value name="1" caption="Redundant page 1 mapping is Disabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG32__PFM_SZ">
+        <value name="6" caption="512KB" value="6"/>
+      </value-group>
+      <value-group name="FCCFG32__DRM_SZ">
+        <value name="0" caption="Rsvd" value="0"/>
+        <value name="1" caption="128KB" value="1"/>
+      </value-group>
+      <value-group name="FCCFG32__FPACKAGE">
+        <value name="5" caption="48 pins" value="5"/>
+        <value name="6" caption="64 pins" value="6"/>
+        <value name="7" caption="Rsvd" value="7"/>
+        <value name="8" caption="100 pins" value="8"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_HSM">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC0">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC1">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC2">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC3">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC4">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC5">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_TCC6">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM0">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM1">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM2">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM3">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM4">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_SERCOM5">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG33__ME_PTC">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_CAN0">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_CAN1">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_USBFS">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_DPA">
+        <value name="0" caption="DPA is Disabled" value="0"/>
+        <value name="1" caption="DPA functions in HSM is Operational" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_TRAM">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG34__ME_PUF">
+        <value name="0" caption="Module is Disabled" value="0"/>
+        <value name="1" caption="Module is Enabled" value="1"/>
+      </value-group>
+      <value-group name="FCCFG49__RAMC_EMAW">
+        <value name="0" caption="Slowest Access" value="0"/>
+        <value name="1" caption="" value="1"/>
+        <value name="2" caption="" value="2"/>
+        <value name="3" caption="Fastest Access; Default (reset)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG49__RAMC_EMA">
+        <value name="0" caption="" value="0"/>
+        <value name="1" caption="" value="1"/>
+        <value name="2" caption="Slowest Access" value="2"/>
+        <value name="3" caption="" value="3"/>
+        <value name="4" caption="" value="4"/>
+        <value name="5" caption="Fastest Access" value="5"/>
+        <value name="6" caption="" value="6"/>
+        <value name="7" caption="Default (reset)" value="7"/>
+      </value-group>
+      <value-group name="FCCFG49__TRAM_EMAS">
+        <value name="0" caption="Sense Amp Pulse Not Extended" value="0"/>
+        <value name="1" caption="Sense Amp Pulse Extended; Default (reset)" value="1"/>
+      </value-group>
+      <value-group name="FCCFG49__PUF_EMAS">
+        <value name="0" caption="Sense Amp Pulse Not Extended" value="0"/>
+        <value name="1" caption="Sense Amp Pulse Extended; Default (reset)" value="1"/>
+      </value-group>
+      <value-group name="FCCFG56__BRINGOSC">
+        <value name="0" caption="Ring oscillator depth is default (DLY0)" value="0"/>
+        <value name="1" caption="Ring oscillator depth is default + 1 ORDLY15 (DLY1)" value="1"/>
+        <value name="2" caption="Ring oscillator depth is default + 2 ORDLY15 (DLY2)" value="2"/>
+        <value name="3" caption="Ring oscillator depth is default + 3 ORDLY15 (DLY3)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VLP2FPST">
+        <value name="0" caption="5us -32 clock cycles based on 6Mhz clock (5US)" value="0"/>
+        <value name="1" caption="10us -64 clock cycles based on 6Mhz clock (10US)" value="1"/>
+        <value name="2" caption="21us -128 clock cycles based on 6Mhz clock (21US)" value="2"/>
+        <value name="3" caption="1.3us -8 clock cycles based on 6Mhz clock (1US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VLPMST">
+        <value name="0" caption="1.3us -8 clock cycles based on 6Mhz clock (1US)" value="0"/>
+        <value name="1" caption="2.6us -16 clock cycles based on 6Mhz clock (2US)" value="1"/>
+        <value name="2" caption="5us -32 clock cycles based on 6Mhz clock (5US)" value="2"/>
+        <value name="3" caption="0.166us -1 clock cycles based on 6Mhz clock (0US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VTONST">
+        <value name="0" caption="31us -192 clock cycles based on 6Mhz clock (31US)" value="0"/>
+        <value name="1" caption="42us -256 clock cycles based on 6Mhz clock (42US)" value="1"/>
+        <value name="2" caption="84us -512 clock cycles based on 6Mhz clock (84US)" value="2"/>
+        <value name="3" caption="10.6us -64 clock cycles based on 6Mhz clock (10US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VPDDST">
+        <value name="0" caption="21us -128 clock cycles based on 6Mhz clock (21US)" value="0"/>
+        <value name="1" caption="42us -256 clock cycles based on 6Mhz clock (42US)" value="1"/>
+        <value name="2" caption="84us -512 clock cycles based on 6Mhz clock (84US)" value="2"/>
+        <value name="3" caption="10.6us -64 clock cycles based on 6Mhz clock (10US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG56__VDVSST">
+        <value name="0" caption="32us -192 clock cycles based on 6Mhz clock (32US)" value="0"/>
+        <value name="1" caption="42us -256 clock cycles based on 6Mhz clock (42US)" value="1"/>
+        <value name="2" caption="84us -512 clock cycles based on 6Mhz clock (84US)" value="2"/>
+        <value name="3" caption="10us -64 clock cycles based on 6Mhz clock (10US)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG57__IGNACK">
+        <value name="0" caption="Power Switch acknowledge signal is taken into account when entering/exiting retention mode. According to the DLYVAL field, a supplementary delay is also added (from 0 to 127 digital ring oscillator period)" value="0"/>
+        <value name="1" caption="Power Switch acknowledge signal is ignored when entering/exiting retention mode, and is replaced by a overflow counter signal clocked on internal digital ring oscillator. The overflow counter is programmable by using the DLYVAL field" value="1"/>
+      </value-group>
+      <value-group name="FCCFG58__BRINGOSC">
+        <value name="0" caption="Ring Oscillator depth is default (DLY0)" value="0"/>
+        <value name="1" caption="Ring Oscillator depth is default + 1 ORDLY15 (DLY1)" value="1"/>
+        <value name="2" caption="Ring Oscillator depth is default + 2 ORDLU15 (DLY2)" value="2"/>
+        <value name="3" caption="Ring Oscillator depth is default + 3 ORDLY15 (DLY3)" value="3"/>
+      </value-group>
+      <value-group name="FCCFG59__IDAU_EN">
+        <value name="0" caption="GC device. All IDAU regions exempt. The boot code will initialize the IDAU, H2PB and PAC as described in Section 2.9.2" value="0"/>
+        <value name="1" caption="IDAU regions enabled. The boot code will initialize the IDAU, H2PB and PAC to the values set by customer and referred to in USERCFG as described in Section 2.9.3" value="1"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="03588" name2="clk_gclk_u2122_v1" version="1d0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x4" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy bit" mask="0x1"/>
+          <bitfield name="GENCTRL0" caption="Generic Clock Generator Control 0 Synchronization Busy bit" mask="0x4"/>
+          <bitfield name="GENCTRL1" caption="Generic Clock Generator Control 1 Synchronization Busy bit" mask="0x8"/>
+          <bitfield name="GENCTRL2" caption="Generic Clock Generator Control 2 Synchronization Busy bit" mask="0x10"/>
+          <bitfield name="GENCTRL3" caption="Generic Clock Generator Control 3 Synchronization Busy bit" mask="0x20"/>
+          <bitfield name="GENCTRL4" caption="Generic Clock Generator Control 4 Synchronization Busy bit" mask="0x40"/>
+          <bitfield name="GENCTRL5" caption="Generic Clock Generator Control 5 Synchronization Busy bit" mask="0x80"/>
+          <bitfield name="GENCTRL6" caption="Generic Clock Generator Control 6 Synchronization Busy bit" mask="0x100"/>
+          <bitfield name="GENCTRL7" caption="Generic Clock Generator Control 7 Synchronization Busy bit" mask="0x200"/>
+          <bitfield name="GENCTRL8" caption="Generic Clock Generator Control 8 Synchronization Busy bit" mask="0x400"/>
+          <bitfield name="GENCTRL9" caption="Generic Clock Generator Control 9 Synchronization Busy bit" mask="0x800"/>
+          <bitfield name="GENCTRL10" caption="Generic Clock Generator Control 10 Synchronization Busy bit" mask="0x1000"/>
+          <bitfield name="GENCTRL11" caption="Generic Clock Generator Control 11 Synchronization Busy bit" mask="0x2000"/>
+        </register>
+        <register name="GENCTRL" offset="0x20" rw="RW" access="WSYNC" size="4" count="12" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="SRC" caption="Source Select" mask="0xF" values="GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x100"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x200"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x400"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x800"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x1000" values="GENCTRL__DIVSEL"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x2000"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF0000"/>
+        </register>
+        <register name="PCHCTRL" offset="0x80" rw="RW" size="4" count="39" initval="0x00000000" caption="Peripheral Clock Control">
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF" values="PCHCTRL__GEN"/>
+          <bitfield name="CHEN" caption="Channel Enable" mask="0x40"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+      </register-group>
+      <value-group name="GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0x00"/>
+        <value name="GCLK_IN" caption="Generator input pad (GCLK_IO)" value="0x01"/>
+        <value name="GCLK_GEN1" caption="Generic clock generator 1 output" value="0x02"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="0x03"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="0x04"/>
+        <value name="DFLL48M" caption="DFLL oscillator output" value="0x05"/>
+        <value name="PLL0_CLKOUT1" caption="PLL 0 port CLKOUT1" value="0x06"/>
+        <value name="PLL0_CLKOUT2" caption="PLL 0 port CLKOUT2" value="0x07"/>
+        <value name="PLL0_CLKOUT3" caption="PLL 0 port CLKOUT3" value="0x08"/>
+        <value name="PLL0_CLKOUT4" caption="PLL 0 port CLKOUT4" value="0x09"/>
+        <value name="PLL0_CLKOUT5" caption="PLL 0 port CLKOUT5" value="0x0A"/>
+      </value-group>
+      <value-group name="GENCTRL__DIVSEL">
+        <value name="DIV1" caption="Divide input directly by divider factor" value="0"/>
+        <value name="DIV2" caption="Divide input by 2^(divider factor+ 1)" value="1"/>
+      </value-group>
+      <value-group name="PCHCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+        <value name="GCLK8" caption="Generic clock generator 8" value="0x8"/>
+        <value name="GCLK9" caption="Generic clock generator 9" value="0x9"/>
+        <value name="GCLK10" caption="Generic clock generator 10" value="0xA"/>
+        <value name="GCLK11" caption="Generic clock generator 11" value="0xB"/>
+      </value-group>
+    </module>
+    <module name="H2PB" id="04947" name2="bus_ahb2apb_v1" version="1a0" caption="AHB To APB Bridge">
+      <register-group name="H2PB" caption="AHB To APB Bridge">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="H2PB CONTROL Register">
+          <bitfield name="PRIV" caption="PRIV privileged access protection bit" mask="0x4"/>
+          <bitfield name="SECEN" caption="SECEN security enable bit" mask="0x8"/>
+        </register>
+        <register name="NONSECCLRA" offset="0x8" rw="RW" size="4" atomic-op="clear:NONSECCLRA" initval="0x00000000" caption="Non-Security Clear Register A">
+          <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+          <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+          <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+          <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+          <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+          <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+          <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+          <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+          <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+          <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+          <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+          <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+          <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+          <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+          <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+          <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+          <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+          <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+          <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+          <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+          <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+          <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+          <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+          <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+          <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+          <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+          <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+          <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+          <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+          <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+          <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+          <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+        </register>
+        <register name="NONSECSETA" offset="0xC" rw="RW" size="4" atomic-op="set:NONSECSETA" initval="0x00000000" caption="Non-Security SET Register A">
+          <bitfield name="NONSEC0" caption="non-security bit for APB Slave k, k=0..31" mask="0x1"/>
+          <bitfield name="NONSEC1" caption="non-security bit for APB Slave k, k=0..31" mask="0x2"/>
+          <bitfield name="NONSEC2" caption="non-security bit for APB Slave k, k=0..31" mask="0x4"/>
+          <bitfield name="NONSEC3" caption="non-security bit for APB Slave k, k=0..31" mask="0x8"/>
+          <bitfield name="NONSEC4" caption="non-security bit for APB Slave k, k=0..31" mask="0x10"/>
+          <bitfield name="NONSEC5" caption="non-security bit for APB Slave k, k=0..31" mask="0x20"/>
+          <bitfield name="NONSEC6" caption="non-security bit for APB Slave k, k=0..31" mask="0x40"/>
+          <bitfield name="NONSEC7" caption="non-security bit for APB Slave k, k=0..31" mask="0x80"/>
+          <bitfield name="NONSEC8" caption="non-security bit for APB Slave k, k=0..31" mask="0x100"/>
+          <bitfield name="NONSEC9" caption="non-security bit for APB Slave k, k=0..31" mask="0x200"/>
+          <bitfield name="NONSEC10" caption="non-security bit for APB Slave k, k=0..31" mask="0x400"/>
+          <bitfield name="NONSEC11" caption="non-security bit for APB Slave k, k=0..31" mask="0x800"/>
+          <bitfield name="NONSEC12" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000"/>
+          <bitfield name="NONSEC13" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000"/>
+          <bitfield name="NONSEC14" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000"/>
+          <bitfield name="NONSEC15" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000"/>
+          <bitfield name="NONSEC16" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000"/>
+          <bitfield name="NONSEC17" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000"/>
+          <bitfield name="NONSEC18" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000"/>
+          <bitfield name="NONSEC19" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000"/>
+          <bitfield name="NONSEC20" caption="non-security bit for APB Slave k, k=0..31" mask="0x100000"/>
+          <bitfield name="NONSEC21" caption="non-security bit for APB Slave k, k=0..31" mask="0x200000"/>
+          <bitfield name="NONSEC22" caption="non-security bit for APB Slave k, k=0..31" mask="0x400000"/>
+          <bitfield name="NONSEC23" caption="non-security bit for APB Slave k, k=0..31" mask="0x800000"/>
+          <bitfield name="NONSEC24" caption="non-security bit for APB Slave k, k=0..31" mask="0x1000000"/>
+          <bitfield name="NONSEC25" caption="non-security bit for APB Slave k, k=0..31" mask="0x2000000"/>
+          <bitfield name="NONSEC26" caption="non-security bit for APB Slave k, k=0..31" mask="0x4000000"/>
+          <bitfield name="NONSEC27" caption="non-security bit for APB Slave k, k=0..31" mask="0x8000000"/>
+          <bitfield name="NONSEC28" caption="non-security bit for APB Slave k, k=0..31" mask="0x10000000"/>
+          <bitfield name="NONSEC29" caption="non-security bit for APB Slave k, k=0..31" mask="0x20000000"/>
+          <bitfield name="NONSEC30" caption="non-security bit for APB Slave k, k=0..31" mask="0x40000000"/>
+          <bitfield name="NONSEC31" caption="non-security bit for APB Slave k, k=0..31" mask="0x80000000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="HMATRIX2" id="bus_hmatrix2_v5" name2="bus_hmatrix2_v5" version="5f0" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+          <bitfield name="M0PR" caption="Master 0 Priority" mask="0x3"/>
+          <bitfield name="LQOSEN0" caption="Latency Quality Of Service Enable for Master 0" mask="0x4"/>
+          <bitfield name="M1PR" caption="Master 1 Priority" mask="0x30"/>
+          <bitfield name="LQOSEN1" caption="Latency Quality Of Service Enable for Master 1" mask="0x40"/>
+          <bitfield name="M2PR" caption="Master 2 Priority" mask="0x300"/>
+          <bitfield name="LQOSEN2" caption="Latency Quality Of Service Enable for Master 2" mask="0x400"/>
+          <bitfield name="M3PR" caption="Master 3 Priority" mask="0x3000"/>
+          <bitfield name="LQOSEN3" caption="Latency Quality Of Service Enable for Master 3" mask="0x4000"/>
+          <bitfield name="M4PR" caption="Master 4 Priority" mask="0x30000"/>
+          <bitfield name="LQOSEN4" caption="Latency Quality Of Service Enable for Master 4" mask="0x40000"/>
+          <bitfield name="M5PR" caption="Master 5 Priority" mask="0x300000"/>
+          <bitfield name="LQOSEN5" caption="Latency Quality Of Service Enable for Master 5" mask="0x400000"/>
+        </register>
+      </register-group>
+      <register-group name="HMATRIX2" caption="HSB Matrix">
+        <register name="MCFG" offset="0x0" rw="RW" size="4" access-size="4" count="6" initval="0x00000002" caption="Master Configuration">
+          <bitfield name="ULBT" caption="Undefined Length Burst Type" mask="0x7" values="MCFG__ULBT"/>
+        </register>
+        <register name="SCFG" offset="0x40" rw="RW" size="4" access-size="4" count="9" initval="0x00000010" caption="Slave Configuration">
+          <bitfield name="SLOT_CYCLE" caption="Maximum Number of Allowed Cycles for a Burst" mask="0x1FF"/>
+          <bitfield name="DEFMSTR_TYPE" caption="Default Master Type" mask="0x30000" values="SCFG__DEFMSTR_TYPE"/>
+          <bitfield name="FIXED_DEFMSTR" caption="Fixed Index of Default Master" mask="0x3C0000"/>
+        </register>
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" size="0x8" count="9"/>
+        <register name="MRCR" offset="0x100" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Master Remap Control">
+          <bitfield name="RCB0" caption="Remap Command Bit for Master 0" mask="0x1" values="MRCR__RCB"/>
+          <bitfield name="RCB1" caption="Remap Command Bit for Master 1" mask="0x2" values="MRCR__RCB"/>
+          <bitfield name="RCB2" caption="Remap Command Bit for Master 2" mask="0x4" values="MRCR__RCB"/>
+          <bitfield name="RCB3" caption="Remap Command Bit for Master 3" mask="0x8" values="MRCR__RCB"/>
+          <bitfield name="RCB4" caption="Remap Command Bit for Master 4" mask="0x10" values="MRCR__RCB"/>
+          <bitfield name="RCB5" caption="Remap Command Bit for Master 5" mask="0x20" values="MRCR__RCB"/>
+        </register>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="9" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEIER" offset="0x150" rw="W" size="4" access-size="4" atomic-op="set:MEIMR" caption="Master Error Interrupt Enable">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MEIDR" offset="0x154" rw="W" size="4" access-size="4" atomic-op="clear:MEIMR" caption="Master Error Interrupt Disable">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MEIMR" offset="0x158" rw="R" size="4" access-size="4" caption="Master Error Interrupt Mask">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MESR" offset="0x15C" rw="R" size="4" access-size="4" atomic-op="clear:MESR" caption="Master Error Status">
+          <bitfield name="MERR0" caption="Master 0 Access Error" mask="0x1"/>
+          <bitfield name="MERR1" caption="Master 1 Access Error" mask="0x2"/>
+          <bitfield name="MERR2" caption="Master 2 Access Error" mask="0x4"/>
+          <bitfield name="MERR3" caption="Master 3 Access Error" mask="0x8"/>
+          <bitfield name="MERR4" caption="Master 4 Access Error" mask="0x10"/>
+          <bitfield name="MERR5" caption="Master 5 Access Error" mask="0x20"/>
+        </register>
+        <register name="MEAR" offset="0x160" rw="R" size="4" access-size="4" count="6" caption="Master Error Address"/>
+      </register-group>
+      <value-group name="MCFG__ULBT">
+        <value name="INFINITE" caption="Infinite Length" value="0"/>
+        <value name="SINGLE" caption="Single Access" value="1"/>
+        <value name="FOUR_BEAT" caption="Four Beat Burst" value="2"/>
+        <value name="EIGHT_BEAT" caption="Eight Beat Burst" value="3"/>
+        <value name="SIXTEEN_BEAT" caption="Sixteen Beat Burst" value="4"/>
+      </value-group>
+      <value-group name="SCFG__DEFMSTR_TYPE">
+        <value name="NO_DEFAULT" caption="No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst." value="0"/>
+        <value name="LAST_DEFAULT" caption="Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave." value="1"/>
+        <value name="FIXED_DEFAULT" caption="Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave." value="2"/>
+      </value-group>
+      <value-group name="MRCR__RCB">
+        <value name="DIS" caption="Disable remapped address decoding for master" value="0"/>
+        <value name="ENA" caption="Enable remapped address decoding for master" value="1"/>
+      </value-group>
+    </module>
+    <module name="ICB" id="SYSTEM_IP" version="1.0.0" caption="Implementation Control Block">
+      <register-group name="ICB" caption="Implementation Control Block">
+        <register name="ICTR" offset="0x4" rw="R" size="4" access-size="4" caption="Interrupt Controller Type Register">
+          <bitfield name="INTLINESNUM" caption="Interrupt line set number" mask="0xF"/>
+        </register>
+        <register name="ACTLR" offset="0x8" rw="RW" size="4" access-size="4" caption="Auxiliary Control Register"/>
+      </register-group>
+    </module>
+    <module name="MCLK" id="04158" name2="clk_mclk_v1" version="1a0" caption="Polaris Main Clock Controller">
+      <register-group name="MCLK" caption="Polaris Main Clock Controller">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear Register">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable Clear" mask="0x1" values="INTENCLR__CKRDY"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set Register">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable Set" mask="0x1" values="INTENSET__CKRDY"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="W" size="4" atomic-op="clear:INTFLAG" initval="0x00000001" caption="Interrupt Flag Status Register">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Flag" mask="0x1"/>
+        </register>
+        <register name="CLKDIV" offset="0xC" rw="RW" size="4" count="3" initval="0x00000000" caption="Clock Divider Control n Register">
+          <bitfield name="DIV" caption="Clock Domain n Division Factor" mask="0xFF" values="CLKDIV__DIV"/>
+        </register>
+        <register name="CLKMSK" offset="0x3C" rw="RW" size="4" count="9" initval="0x00000000" caption="Peripheral Clock Enable Mask n Register">
+          <bitfield name="MASK0" caption="Peripheral Clock Enable Mask" mask="0x1" values="CLKMSK__MASK"/>
+          <bitfield name="MASK1" caption="Peripheral Clock Enable Mask" mask="0x2" values="CLKMSK__MASK"/>
+          <bitfield name="MASK2" caption="Peripheral Clock Enable Mask" mask="0x4" values="CLKMSK__MASK"/>
+          <bitfield name="MASK3" caption="Peripheral Clock Enable Mask" mask="0x8" values="CLKMSK__MASK"/>
+          <bitfield name="MASK4" caption="Peripheral Clock Enable Mask" mask="0x10" values="CLKMSK__MASK"/>
+          <bitfield name="MASK5" caption="Peripheral Clock Enable Mask" mask="0x20" values="CLKMSK__MASK"/>
+          <bitfield name="MASK6" caption="Peripheral Clock Enable Mask" mask="0x40" values="CLKMSK__MASK"/>
+          <bitfield name="MASK7" caption="Peripheral Clock Enable Mask" mask="0x80" values="CLKMSK__MASK"/>
+          <bitfield name="MASK8" caption="Peripheral Clock Enable Mask" mask="0x100" values="CLKMSK__MASK"/>
+          <bitfield name="MASK9" caption="Peripheral Clock Enable Mask" mask="0x200" values="CLKMSK__MASK"/>
+          <bitfield name="MASK10" caption="Peripheral Clock Enable Mask" mask="0x400" values="CLKMSK__MASK"/>
+          <bitfield name="MASK11" caption="Peripheral Clock Enable Mask" mask="0x800" values="CLKMSK__MASK"/>
+          <bitfield name="MASK12" caption="Peripheral Clock Enable Mask" mask="0x1000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK13" caption="Peripheral Clock Enable Mask" mask="0x2000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK14" caption="Peripheral Clock Enable Mask" mask="0x4000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK15" caption="Peripheral Clock Enable Mask" mask="0x8000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK16" caption="Peripheral Clock Enable Mask" mask="0x10000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK17" caption="Peripheral Clock Enable Mask" mask="0x20000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK18" caption="Peripheral Clock Enable Mask" mask="0x40000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK19" caption="Peripheral Clock Enable Mask" mask="0x80000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK20" caption="Peripheral Clock Enable Mask" mask="0x100000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK21" caption="Peripheral Clock Enable Mask" mask="0x200000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK22" caption="Peripheral Clock Enable Mask" mask="0x400000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK23" caption="Peripheral Clock Enable Mask" mask="0x800000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK24" caption="Peripheral Clock Enable Mask" mask="0x1000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK25" caption="Peripheral Clock Enable Mask" mask="0x2000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK26" caption="Peripheral Clock Enable Mask" mask="0x4000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK27" caption="Peripheral Clock Enable Mask" mask="0x8000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK28" caption="Peripheral Clock Enable Mask" mask="0x10000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK29" caption="Peripheral Clock Enable Mask" mask="0x20000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK30" caption="Peripheral Clock Enable Mask" mask="0x40000000" values="CLKMSK__MASK"/>
+          <bitfield name="MASK31" caption="Peripheral Clock Enable Mask" mask="0x80000000" values="CLKMSK__MASK"/>
+        </register>
+      </register-group>
+      <value-group name="INTENCLR__CKRDY">
+        <value name="0" caption="The Clock Ready interrupt is disabled" value="0"/>
+        <value name="1" caption="The Clock Ready interrupt is enabled." value="1"/>
+      </value-group>
+      <value-group name="INTENSET__CKRDY">
+        <value name="0" caption="The Clock Ready interrupt is disabled." value="0"/>
+        <value name="1" caption="The Clock Ready interrupt is enabled." value="1"/>
+      </value-group>
+      <value-group name="CLKDIV__DIV">
+        <value name="DIV1" caption="Divide by 1" value="1"/>
+        <value name="DIV2" caption="Divide by 2" value="2"/>
+        <value name="DIV4" caption="Divide by 4" value="4"/>
+        <value name="DIV8" caption="Divide by 8" value="8"/>
+        <value name="DIV16" caption="Divide by 16" value="16"/>
+        <value name="DIV32" caption="Divide by 32" value="32"/>
+        <value name="DIV64" caption="Divide by 64" value="64"/>
+        <value name="DIV128" caption="Divide by 128" value="128"/>
+      </value-group>
+      <value-group name="CLKMSK__MASK">
+        <value name="0" caption="Peripheral clock mclk_clk_periph[n*32+x] stopped" value="0"/>
+        <value name="1" caption="Peripheral clock mclk_clk_periph[n*32+x] enabled" value="1"/>
+      </value-group>
+    </module>
+    <module name="MCRAMC" id="04921" name2="drm_mcramc_v5" version="5b0" caption="Multi-Channel RAM Controller">
+      <register-group name="MCRAMC" caption="Multi-Channel RAM Controller">
+        <register name="MCRAMC_CTRLA" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000002" caption="Control Enable A Register">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1" values="MCRAMC_CTRLA__SWRST"/>
+          <bitfield name="ENABLE" caption="ECC Decoder Enable" mask="0x2" values="MCRAMC_CTRLA__ENABLE"/>
+          <bitfield name="PRIV" caption="Priviledged Access Enable" mask="0x4"/>
+          <bitfield name="WS" caption="Wait State Enable" mask="0x100"/>
+        </register>
+        <register name="MCRAMC_INTENCLR" offset="0x8" rw="RW" size="4" access-size="4" atomic-op="clear:MCRAMC_INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear Register">
+          <bitfield name="SERREN" caption="Single Bit Error Interrupt Enable, Clear" mask="0x1"/>
+          <bitfield name="DERREN" caption="Double Bit Error Interrupt Enable, Clear" mask="0x2"/>
+        </register>
+        <register name="MCRAMC_INTENSET" offset="0xC" rw="RW" size="4" access-size="4" atomic-op="set:MCRAMC_INTENSET" initval="0x00000000" caption="Interrupt Enable Set Register">
+          <bitfield name="SERREN" caption="Single Bit Error Interrupt Enable, Set" mask="0x1"/>
+          <bitfield name="DERREN" caption="Double Bit Error Interrupt Enable, Set" mask="0x2"/>
+        </register>
+        <register name="MCRAMC_INTSTA" offset="0x10" rw="RW" size="4" access-size="4" atomic-op="clear:MCRAMC_INTSTA" initval="0x00000000" caption="Interrupt Status Register">
+          <bitfield name="SERR" caption="Single Bit Error" mask="0x1"/>
+          <bitfield name="DERR" caption="Double Bit Error" mask="0x2"/>
+        </register>
+        <register name="MCRAMC_FLTCTRL" offset="0x14" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Fault Injection Control Register">
+          <bitfield name="FLTEN" caption="Fault Injection Enabled" mask="0x2" values="MCRAMC_FLTCTRL__FLTEN"/>
+          <bitfield name="FLTMD" caption="Fault Injection Mode" mask="0x3000"/>
+        </register>
+        <register name="MCRAMC_FLTPTR" offset="0x18" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Fault Injection Pointer Register">
+          <bitfield name="FLT1PTR" caption="Single Fault Injection Bit Pointer" mask="0xFF"/>
+          <bitfield name="FLT2PTR" caption="Double Fault Injection Bit Pointer" mask="0xFF0000"/>
+        </register>
+        <register name="MCRAMC_FLTADR" offset="0x1C" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Fault Injection Address Register">
+          <bitfield name="FLTADR" caption="Fault Address Offset" mask="0xFFFFFF"/>
+        </register>
+        <register name="MCRAMC_ERRCADR" offset="0x20" rw="R" size="4" access-size="4" initval="0x00000000" caption="Error Capture Address Register">
+          <bitfield name="ERCADR" caption="ECC SECDED Error Capture Address" mask="0xFFFFFF"/>
+        </register>
+        <register name="MCRAMC_ERRCPAR" offset="0x24" rw="R" size="4" access-size="4" initval="0x00000000" caption="Error Capture Parity Register">
+          <bitfield name="ERCPAR" caption="ECC SECDED Error Capture Parity" mask="0xFF"/>
+        </register>
+        <register name="MCRAMC_ERRCSYN" offset="0x28" rw="R" size="4" access-size="4" initval="0x00000000" caption="Error Capture Syndrome Register">
+          <bitfield name="ERCSYN" caption="ECC SECDED Error Capture Syndrome" mask="0xFF" values="MCRAMC_ERRCSYN__ERCSYN"/>
+          <bitfield name="ERR1" caption="ECC Single Bit Error" mask="0x4000"/>
+          <bitfield name="ERR2" caption="ECC Double Bit Error" mask="0x8000" values="MCRAMC_ERRCSYN__ERR2"/>
+        </register>
+        <register name="MCRAMC_VERSION" offset="0xFC" rw="R" size="4" access-size="4" initval="0x00000510" caption="Version Register">
+          <bitfield name="VERSION" caption="MCRAMC Version" mask="0xFFF"/>
+          <bitfield name="MFN" caption="Metal Fix Number" mask="0x70000"/>
+        </register>
+      </register-group>
+      <value-group name="MCRAMC_CTRLA__SWRST">
+        <value name="0" caption="No effect." value="0"/>
+        <value name="1" caption="Reset the MCRAMC. A software-triggered hardware reset of the MCRAMC user interface is performed." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_CTRLA__ENABLE">
+        <value name="0" caption="ECC decoding is disabled." value="0"/>
+        <value name="1" caption="ECC decoding is enabled." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_FLTCTRL__FLTEN">
+        <value name="0" caption="Disables fault injection." value="0"/>
+        <value name="1" caption="Enables fault injection at FLTADR address offset as selected by FLTMD and FLTxPTR." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_ERRCSYN__ERCSYN">
+        <value name="0" caption="Not a Single bit error." value="0"/>
+        <value name="1" caption="Single bit error." value="1"/>
+      </value-group>
+      <value-group name="MCRAMC_ERRCSYN__ERR2">
+        <value name="0" caption="Not a Double bit error." value="0"/>
+        <value name="1" caption="Double bit error." value="1"/>
+      </value-group>
+    </module>
+    <module name="MPU" id="SYSTEM_IP" version="1.0.0" caption="Memory Protection Unit">
+      <register-group name="MPU" caption="Memory Protection Unit">
+        <register name="MPU_TYPE" offset="0x0" rw="R" size="4" access-size="4" caption="MPU Type Register">
+          <bitfield name="SEPARATE" caption="Separate instructions and data address regions" mask="0x1"/>
+          <bitfield name="DREGION" caption="Number of MPU data regions" mask="0xFF00"/>
+        </register>
+        <register name="MPU_CTRL" offset="0x4" rw="RW" size="4" access-size="4" caption="MPU Control Register">
+          <bitfield name="ENABLE" caption="MPU enable" mask="0x1"/>
+          <bitfield name="HFNMIENA" caption="HardFault, NMI enable" mask="0x2"/>
+          <bitfield name="PRIVDEFENA" caption="Privileged default enable" mask="0x4"/>
+        </register>
+        <register name="MPU_RNR" offset="0x8" rw="RW" size="4" access-size="4" caption="MPU Region Number Register">
+          <bitfield name="REGION" caption="Selected region number" mask="0xFF"/>
+        </register>
+        <register name="MPU_RBAR" offset="0xC" rw="RW" size="4" access-size="4" caption="MPU Region Base Address Register">
+          <bitfield name="XN" caption="Execute Never" mask="0x1"/>
+          <bitfield name="AP" caption="Access permissions" mask="0x6" values="MPU_RBAR__AP"/>
+          <bitfield name="SH" caption="Shareability" mask="0x18" values="MPU_RBAR__SH"/>
+          <bitfield name="BASE" caption="Base address" mask="0xFFFFFFE0"/>
+        </register>
+        <register name="MPU_RLAR" offset="0x10" rw="RW" size="4" access-size="4" caption="MPU Region Limit Address Register">
+          <bitfield name="EN" caption="Region enable" mask="0x1"/>
+          <bitfield name="AttrInd" caption="Attribute Index" mask="0xE"/>
+          <bitfield name="LIMIT" caption="Limit address" mask="0xFFFFFFE0"/>
+        </register>
+        <register name="MPU_MAIR0" offset="0x30" rw="RW" size="4" access-size="4" caption="MPU Memory Attribute Indirection Register 0">
+          <bitfield name="Attr0" caption="Attribute of MPU region 0" mask="0xFF"/>
+          <bitfield name="Attr1" caption="Attribute of MPU region 1" mask="0xFF00"/>
+          <bitfield name="Attr2" caption="Attribute of MPU region 2" mask="0xFF0000"/>
+          <bitfield name="Attr3" caption="Attribute of MPU region 3" mask="0xFF000000"/>
+        </register>
+        <register name="MPU_MAIR1" offset="0x34" rw="RW" size="4" access-size="4" caption="MPU Memory Attribute Indirection Register 1">
+          <bitfield name="Attr4" caption="Attribute of MPU region 4" mask="0xFF"/>
+          <bitfield name="Attr5" caption="Attribute of MPU region 5" mask="0xFF00"/>
+          <bitfield name="Attr6" caption="Attribute of MPU region 6" mask="0xFF0000"/>
+          <bitfield name="Attr7" caption="Attribute of MPU region 7" mask="0xFF000000"/>
+        </register>
+      </register-group>
+      <value-group name="MPU_RBAR__AP">
+        <value name="RWPRIV" caption="Read/write by privileged code only" value="0"/>
+        <value name="RWANY" caption="Read/write by any privilege level" value="1"/>
+        <value name="RPRIV" caption="Read-only by privileged code only" value="2"/>
+        <value name="RANY" caption="Read-only by any privilege level" value="3"/>
+      </value-group>
+      <value-group name="MPU_RBAR__SH">
+        <value name="NO" caption="Non-shareable" value="0"/>
+        <value name="OUTER" caption="Outer shareable" value="2"/>
+        <value name="INNER" caption="Inner shareable" value="3"/>
+      </value-group>
+    </module>
+    <module name="NVIC" id="SYSTEM_IP" version="1.0.0" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register name="NVIC_ISER" offset="0x0" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Set Enable Register n">
+          <bitfield name="SETENA" caption="Set enable" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ICER" offset="0x80" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Clear Enable Register n">
+          <bitfield name="CLRENA" caption="Clear enable" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ISPR" offset="0x100" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Set Pending Register n">
+          <bitfield name="SETPEND" caption="Set pending" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ICPR" offset="0x180" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Clear Pending Register n">
+          <bitfield name="CLRPEND" caption="Clear pending" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_IABR" offset="0x200" rw="R" size="4" access-size="4" count="5" caption="Interrupt Active Bit Register n">
+          <bitfield name="ACTIVE" caption="Active state" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_ITNS" offset="0x280" rw="RW" size="4" access-size="4" count="5" caption="Interrupt Target Non-secure Register n">
+          <bitfield name="ITNS" caption="Interrupt Targets Non-secure" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NVIC_IPR" offset="0x300" rw="RW" size="4" access-size="4" count="36" caption="Interrupt Priority Register n">
+          <bitfield name="PRI_N0" caption="Priority of interrupt number 4n+0" mask="0xFF"/>
+          <bitfield name="PRI_N1" caption="Priority of interrupt number 4n+1" mask="0xFF00"/>
+          <bitfield name="PRI_N2" caption="Priority of interrupt number 4n+2" mask="0xFF0000"/>
+          <bitfield name="PRI_N3" caption="Priority of interrupt number 4n+3" mask="0xFF000000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="OSC32KCTRL" id="03717" name2="osc_osc32kctrl_u2400_v2" version="2a0" caption="32kHz Oscillators Control">
+      <register-group name="OSC32KCTRL" caption="32kHz Oscillators Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x1"/>
+          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector" mask="0x4"/>
+          <bitfield name="XOSC32KSW" caption="XOSC32K Clock switch" mask="0x8"/>
+        </register>
+        <register name="CLKSELCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Clock Selection Control">
+          <bitfield name="RTCSEL" caption="RTC Clock Selection" mask="0x3" values="CLKSELCTRL__RTCSEL"/>
+          <bitfield name="HSMSEL" caption="HSM Clock Selection" mask="0x30" values="CLKSELCTRL__HSMSEL"/>
+        </register>
+        <register name="CFDCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Clock Failure Detector Control">
+          <bitfield name="CFDEN" caption="Clock Failure Detector Enable" mask="0x1"/>
+          <bitfield name="SWBACK" caption="Clock Switch Back" mask="0x2"/>
+          <bitfield name="CFDPRESC" caption="Clock Failure Detector Prescaler" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="CFDEO" caption="Clock Failure Detector Event Output Enable" mask="0x1"/>
+        </register>
+        <register name="XOSC32K" offset="0x1C" rw="RW" size="4" initval="0x00200080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="ONDEMAND" caption="On Demand Mode" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Startup Mode" mask="0xF00" values="XOSC32K__STARTUP"/>
+          <bitfield name="ENSL" caption="Enable Servo Loop" mask="0x10000"/>
+          <bitfield name="BOOST" caption="Gain Boost" mask="0x20000"/>
+          <bitfield name="CGM" caption="Control Gain Mode" mask="0x3C0000" values="XOSC32K__CGM"/>
+          <bitfield name="CTRLX" caption="Extended Control" mask="0xF000000"/>
+        </register>
+      </register-group>
+      <value-group name="CLKSELCTRL__RTCSEL">
+        <value name="ULP32K" caption="32.768kHz from 32kHz internal ULP oscillator" value="0x0"/>
+        <value name="ULP1K" caption="1.024kHz from 32kHz internal ULP oscillator" value="0x1"/>
+        <value name="XOSC32K" caption="32.768kHz from 32.768kHz external crystal oscillator" value="0x2"/>
+        <value name="XOSC1K" caption="1.024kHz from 32.768kHz internal oscillator" value="0x3"/>
+      </value-group>
+      <value-group name="CLKSELCTRL__HSMSEL">
+        <value name="ULP32K" caption="32.768kHz from 32kHz internal ULP oscillator" value="0x0"/>
+        <value name="XOSC32K" caption="32.768kHz from 32.768kHz external crystal oscillator" value="0x2"/>
+      </value-group>
+      <value-group name="XOSC32K__STARTUP">
+        <value name="1CYCLE" caption="1 ULP clock cycle" value="0x0"/>
+        <value name="16CYCLES" caption="16 ULP clock cycles" value="0x1"/>
+        <value name="32CYCLES" caption="32 ULP clock cycles" value="0x2"/>
+        <value name="2048CYCLES" caption="2048 ULP clock cycles" value="0x3"/>
+        <value name="4096CYCLES" caption="4096 ULP clock cycles" value="0x4"/>
+        <value name="8192CYCLES" caption="8192 ULP clock cycles" value="0x5"/>
+        <value name="16384CYCLES" caption="16384 ULP clock cycles" value="0x6"/>
+        <value name="32768CYCLES" caption="32768 ULP clock cycles" value="0x7"/>
+        <value name="65536CYCLES" caption="65536 ULP clock cycles" value="0x8"/>
+        <value name="131072CYCLES" caption="131072 ULP clock cycles" value="0x9"/>
+        <value name="262144CYCLES" caption="262144 ULP clock cycles" value="0xA"/>
+      </value-group>
+      <value-group name="XOSC32K__CGM">
+        <value name="CGM0" caption="The lower Control Gain Mode value" value="0x0"/>
+        <value name="CGM1" caption="A higher Control Gain Mode value than CGM0" value="0x1"/>
+        <value name="CGM2" caption="A higher Control Gain Mode value than CGM1" value="0x2"/>
+        <value name="CGM3" caption="A higher Control Gain Mode value than CGM2" value="0x3"/>
+        <value name="CGM4" caption="A higher Control Gain Mode value than CGM3" value="0x4"/>
+        <value name="CGM5" caption="A higher Control Gain Mode value than CGM4" value="0x5"/>
+        <value name="CGM6" caption="A higher Control Gain Mode value than CGM5" value="0x6"/>
+        <value name="CGM7" caption="A higher Control Gain Mode value than CGM6" value="0x7"/>
+        <value name="CGM8" caption="A higher Control Gain Mode value than CGM7" value="0x8"/>
+        <value name="CGM9" caption="A higher Control Gain Mode value than CGM8" value="0x9"/>
+        <value name="CGM10" caption="A higher Control Gain Mode value than CGM9" value="0xA"/>
+        <value name="CGM11" caption="A higher Control Gain Mode value than CGM10" value="0xB"/>
+        <value name="CGM12" caption="A higher Control Gain Mode value than CGM11" value="0xC"/>
+        <value name="CGM13" caption="A higher Control Gain Mode value than CGM12" value="0xD"/>
+        <value name="CGM14" caption="A higher Control Gain Mode value than CGM13" value="0xE"/>
+        <value name="CGM15" caption="The highest Control Gain Mode value" value="0xF"/>
+      </value-group>
+    </module>
+    <module name="OSCCTRL" id="03718" name2="osc_oscctrl_u2401_v2" version="2b0" caption="Oscillators Control">
+      <register-group name="OSCCTRL" caption="Oscillators Control">
+        <register name="EVCTRL" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="CFDEO" caption="Clock Failure Detector Event Output Enable" mask="0x1"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure Interrupt Enable" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure Interrupt Enable" mask="0x4"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock Interrupt Enable" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow Interrupt Enable" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure Interrupt Enable" mask="0x2000"/>
+          <bitfield name="PLL0LOCKR" caption="PLL 0 Lock Rise Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="PLL0LOCKF" caption="PLL 0 Lock Fall Interrupt Enable" mask="0x2000000"/>
+        </register>
+        <register name="INTENSET" offset="0x8" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure Interrupt Enable" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure Interrupt Enable" mask="0x4"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock Interrupt Enable" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow Interrupt Enable" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure Interrupt Enable" mask="0x2000"/>
+          <bitfield name="PLL0LOCKR" caption="PLL 0 Lock Rise Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="PLL0LOCKF" caption="PLL 0 Lock Fall Interrupt Enable" mask="0x2000000"/>
+        </register>
+        <register name="INTFLAG" offset="0xC" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure" mask="0x4"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure" mask="0x2000"/>
+          <bitfield name="PLL0LOCKR" caption="PLL 0 Lock Rise" mask="0x1000000"/>
+          <bitfield name="PLL0LOCKF" caption="PLL 0 Lock Fall" mask="0x2000000"/>
+        </register>
+        <register name="STATUS" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSCFAIL" caption="XOSC Startup Failure" mask="0x2"/>
+          <bitfield name="CLKFAIL" caption="XOSC Clock Failure" mask="0x4"/>
+          <bitfield name="XOSCCKSW" caption="XOSC Clock Switch" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x100"/>
+          <bitfield name="DFLLLOCK" caption="DFLL Lock" mask="0x200"/>
+          <bitfield name="DFLLOVF" caption="DFLL Tuner Overflow" mask="0x400"/>
+          <bitfield name="DFLLUNF" caption="DFLL Tuner Underflow" mask="0x800"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x1000"/>
+          <bitfield name="DFLLFAIL" caption="DFLL Startup Failure" mask="0x2000"/>
+          <bitfield name="PLL0LOCK" caption="PLL 0 Lock" mask="0x1000000"/>
+        </register>
+        <register name="XOSCCTRLA" offset="0x14" rw="RW" size="4" initval="0x00000D00" caption="External Multipurpose Crystal Oscillator Control A">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="AGC" caption="Auto Gain Control Loop Enable" mask="0x4"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x8"/>
+          <bitfield name="CFDEN" caption="Clock Failure Detector Enable" mask="0x10"/>
+          <bitfield name="SWBEN" caption="Xosc Clock Switch Back Enable" mask="0x20"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF00" values="XOSCCTRLA__STARTUP"/>
+          <bitfield name="CFDPRESC" caption="Clock Failure Detector Prescaler" mask="0xF0000" values="XOSCCTRLA__CFDPRESC"/>
+          <bitfield name="USBHSDIV" caption="USBHS Referrence Clock Division" mask="0x3000000" values="XOSCCTRLA__USBHSDIV"/>
+          <bitfield name="WRTLOCK" caption="Write Lock for CTRLA register" mask="0x80000000"/>
+        </register>
+        <register name="XOSCCTRLB" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="External Multipurpose Crystal Oscillator Control B">
+          <bitfield name="USRCFG" caption="User Configuration Control Bits" mask="0xFF"/>
+          <bitfield name="WRTLOCK" caption="Write Lock for CTRLB register" mask="0x80000000"/>
+        </register>
+        <register name="DFLLCTRLA" offset="0x2C" rw="RW" size="4" initval="0x00000082" caption="DFLL48M Control A">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x4"/>
+          <bitfield name="LOWFREQ" caption="Low Frequency Mode" mask="0x8"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="DFLLCTRLB" offset="0x30" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="DFLL48M Control B">
+          <bitfield name="LOOPEN" caption="Operating Mode Selection" mask="0x1"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x2"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x4"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x8"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x10"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x20"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x80"/>
+        </register>
+        <register name="DFLLTUNE" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="DFLL48M Tune">
+          <bitfield name="TUNE" caption="Tune Value" mask="0x7F"/>
+        </register>
+        <register name="DFLLDIFF" offset="0x38" rw="R" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Diff">
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF"/>
+        </register>
+        <register name="DFLLMUL" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="STEP" caption="Tune Maximum Step" mask="0x7F0000"/>
+        </register>
+        <register name="PLL0CTRL" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="PLL Control">
+          <bitfield name="ENABLE" caption="PLL Enable" mask="0x2"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x4"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="REFSEL" caption="Reference selection" mask="0x700" values="PLL0CTRL__REFSEL"/>
+          <bitfield name="BWSEL" caption="Bandwidth selection" mask="0x3800" values="PLL0CTRL__BWSEL"/>
+        </register>
+        <register name="PLL0FBDIV" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="PLL Feed-Back Divider">
+          <bitfield name="FBDIV" caption="PLL Feed-Back Divider Factor" mask="0x3FF"/>
+        </register>
+        <register name="PLL0REFDIV" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="PLL reference divider">
+          <bitfield name="REFDIV" caption="PLL reference division factor" mask="0x3F"/>
+        </register>
+        <register name="PLL0POSTDIVA" offset="0x4C" rw="RW" size="4" initval="0x20202020" caption="PLL output clock divider A">
+          <bitfield name="POSTDIV0" caption="PLL output 0 clock division factor" mask="0x3F"/>
+          <bitfield name="OUTEN0" caption="PLL output 0 enable" mask="0x80"/>
+          <bitfield name="POSTDIV1" caption="PLL output 0 clock division factor" mask="0x3F00"/>
+          <bitfield name="OUTEN1" caption="PLL output 0 enable" mask="0x8000"/>
+          <bitfield name="POSTDIV2" caption="PLL output 0 clock division factor" mask="0x3F0000"/>
+          <bitfield name="OUTEN2" caption="PLL output 0 enable" mask="0x800000"/>
+          <bitfield name="POSTDIV3" caption="PLL output 0 clock division factor" mask="0x3F000000"/>
+          <bitfield name="OUTEN3" caption="PLL output 0 enable" mask="0x80000000"/>
+        </register>
+        <register name="PLL0POSTDIVB" offset="0x50" rw="RW" size="4" initval="0x00000020" caption="PLL output clock divider B">
+          <bitfield name="POSTDIV4" caption="PLL output 4 clock division factor" mask="0x3F"/>
+          <bitfield name="OUTEN4" caption="PLL output 4 enable" mask="0x80"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x78" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="DFLLENABLE" caption="DFLL48M ENABLE Synchronization Busy" mask="0x2"/>
+          <bitfield name="DFLLCTRLB" caption="DFLLCTRLB Synchronization Busy" mask="0x4"/>
+          <bitfield name="DFLLTUNE" caption="DFLLTUNE Synchronization Busy" mask="0x8"/>
+          <bitfield name="DFLLDIFF" caption="DFLLDIFF Synchronization Busy" mask="0x10"/>
+          <bitfield name="DFLLMUL" caption="DFLLMUL Synchronization Busy" mask="0x20"/>
+          <bitfield name="FRACDIV0" caption="FRACDIV0 Synchronization Busy" mask="0x40"/>
+          <bitfield name="FRACDIV1" caption="FRACDIV1 Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="XOSCCAL" offset="0x80" rw="RW" size="4" initval="0x00000000" caption="XOSC Calibration Register">
+          <mode name="DEFAULT"/>
+          <mode name="FUSES_OSC_XTAL_HF_AGC_V2"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="FTRANS" caption="Fine Transconductance programmability for Oscillator" mask="0x3"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="KICKEREN" caption="Kicker enable" mask="0x4"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="ENVAMP" caption="envelope amplitude at osci" mask="0x8"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="HYST" caption="loop hysteresis control" mask="0x10"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="CMSEL" caption="clock buffer common mode selection" mask="0x20"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="FLIPPOL" caption="flip output clock polarity" mask="0x40"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="REDGAIN" caption="reduce gain control timer" mask="0x100"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="REDOSC" caption="reduce oscillation debug counter" mask="0x200"/>
+          <bitfield modes="FUSES_OSC_XTAL_HF_AGC_V2" name="SPARES" caption="Spare bits" mask="0xFC00"/>
+          <bitfield modes="DEFAULT" name="CAL" caption="XOSC Calibration" mask="0xFFFF"/>
+        </register>
+        <register name="RC48MCAL0" offset="0x88" rw="RW" size="4" initval="0x00000000" caption="RC48M Calibration 0">
+          <mode name="DEFAULT"/>
+          <mode name="FUSES_OSC_RC48MHZ_V1"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="temp_trim_mv" caption="Temp trim value" mask="0x3F"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="proc_trim_mv" caption="Proc trim value" mask="0x3FC0"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="iosc_boost" caption="IOSC boost" mask="0x10000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="out_buf_sel" caption="Output buffer select" mask="0x20000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="ldo_vout_boost" caption="LDO VOUT boost" mask="0x40000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="cmp_8m_lp" caption="Comparator 8MHz low-power" mask="0x80000"/>
+          <bitfield modes="FUSES_OSC_RC48MHZ_V1" name="cmp_pwr_ctrl" caption="Comparator power control" mask="0x700000"/>
+          <bitfield modes="DEFAULT" name="CAL" caption="RC48M Calibration" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="XOSCCTRLA__STARTUP">
+        <value name="CYCLE1" caption="31 us" value="0"/>
+        <value name="CYCLE2" caption="61 us" value="1"/>
+        <value name="CYCLE4" caption="122 us" value="2"/>
+        <value name="CYCLE8" caption="244 us" value="3"/>
+        <value name="CYCLE16" caption="488 us" value="4"/>
+        <value name="CYCLE32" caption="977 us" value="5"/>
+        <value name="CYCLE64" caption="1953 us" value="6"/>
+        <value name="CYCLE128" caption="3906 us" value="7"/>
+        <value name="CYCLE256" caption="7813 us" value="8"/>
+        <value name="CYCLE512" caption="15625 us" value="9"/>
+        <value name="CYCLE1024" caption="31250 us" value="10"/>
+        <value name="CYCLE2048" caption="62500 us" value="11"/>
+        <value name="CYCLE4096" caption="125000 us" value="12"/>
+        <value name="CYCLE8192" caption="250000 us" value="13"/>
+        <value name="CYCLE16384" caption="500000 us" value="14"/>
+        <value name="CYCLE32768" caption="1000000 us" value="15"/>
+      </value-group>
+      <value-group name="XOSCCTRLA__CFDPRESC">
+        <value name="DIV1" caption="48 MHz" value="0"/>
+        <value name="DIV2" caption="24 MHz" value="1"/>
+        <value name="DIV4" caption="12 MHz" value="2"/>
+        <value name="DIV8" caption="6 MHz" value="3"/>
+        <value name="DIV16" caption="3 MHz" value="4"/>
+        <value name="DIV32" caption="1.5 MHz" value="5"/>
+        <value name="DIV64" caption="0.75 MHz" value="6"/>
+        <value name="DIV128" caption="0.375 MHz" value="7"/>
+        <value name="DIV256" caption="187.5 KHz" value="8"/>
+        <value name="DIV512" caption="93.75 KHz" value="9"/>
+        <value name="DIV1024" caption="46.875 KHz" value="10"/>
+        <value name="DIV2048" caption="23.437 KHz" value="11"/>
+        <value name="DIV4096" caption="11.718 KHz" value="12"/>
+        <value name="DIV8192" caption="5.85 KHz" value="13"/>
+        <value name="DIV16384" caption="2.92 KHz" value="14"/>
+        <value name="DIV32768" caption="1.46 KHz" value="15"/>
+      </value-group>
+      <value-group name="XOSCCTRLA__USBHSDIV">
+        <value name="DIS" caption="USBHS PLL reference XOSC clock is disabled" value="0"/>
+        <value name="DIV1" caption="USBHS PLL reference XOSC clock is divided by 1" value="1"/>
+        <value name="DIV2" caption="USBHS PLL reference XOSC clock is divided by 2" value="2"/>
+        <value name="DIV4" caption="USBHS PLL reference XOSC clock is divided by 4" value="3"/>
+      </value-group>
+      <value-group name="PLL0CTRL__REFSEL">
+        <value name="GCLK" caption="Dedicated GCLK clock reference" value="0x0"/>
+        <value name="XOSC" caption="XOSC clock reference" value="0x1"/>
+        <value name="DFLL48M" caption="DFLL48M clock reference" value="0x2"/>
+      </value-group>
+      <value-group name="PLL0CTRL__BWSEL">
+        <value name="BWSEL0" caption="TBD" value="0x0"/>
+        <value name="BWSEL1" caption="TBD" value="0x1"/>
+        <value name="BWSEL2" caption="TBD" value="0x2"/>
+        <value name="BWSEL3" caption="TBD" value="0x3"/>
+        <value name="BWSEL4" caption="TBD" value="0x4"/>
+        <value name="BWSEL5" caption="TBD" value="0x5"/>
+        <value name="BWSEL6" caption="TBD" value="0x6"/>
+        <value name="BWSEL7" caption="TBD" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PAC" id="04298" name2="sec_pac_apb_v1" version="1a0" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A Register">
+          <bitfield name="PRIV" caption="Privileged Access Only" mask="0x4" values="CTRLA__PRIV"/>
+        </register>
+        <register name="WRCTRL" offset="0x4" rw="W" size="4" initval="0x00000000" caption="Write Control Register">
+          <bitfield name="PERID" caption="Peripheral Identifier" mask="0xFF"/>
+          <bitfield name="KEY" caption="Peripheral Access Control Key" mask="0xFF0000" values="WRCTRL__KEY"/>
+        </register>
+        <register name="STATUS" offset="0x40" rw="R" size="4" count="4" initval="0x00000000" caption="Peripheral Status n Register">
+          <bitfield name="PERID0" caption="PERID Write Protection Status" mask="0x1" values="STATUS__PERID"/>
+          <bitfield name="PERID1" caption="PERID Write Protection Status" mask="0x2" values="STATUS__PERID"/>
+          <bitfield name="PERID2" caption="PERID Write Protection Status" mask="0x4" values="STATUS__PERID"/>
+          <bitfield name="PERID3" caption="PERID Write Protection Status" mask="0x8" values="STATUS__PERID"/>
+          <bitfield name="PERID4" caption="PERID Write Protection Status" mask="0x10" values="STATUS__PERID"/>
+          <bitfield name="PERID5" caption="PERID Write Protection Status" mask="0x20" values="STATUS__PERID"/>
+          <bitfield name="PERID6" caption="PERID Write Protection Status" mask="0x40" values="STATUS__PERID"/>
+          <bitfield name="PERID7" caption="PERID Write Protection Status" mask="0x80" values="STATUS__PERID"/>
+          <bitfield name="PERID8" caption="PERID Write Protection Status" mask="0x100" values="STATUS__PERID"/>
+          <bitfield name="PERID9" caption="PERID Write Protection Status" mask="0x200" values="STATUS__PERID"/>
+          <bitfield name="PERID10" caption="PERID Write Protection Status" mask="0x400" values="STATUS__PERID"/>
+          <bitfield name="PERID11" caption="PERID Write Protection Status" mask="0x800" values="STATUS__PERID"/>
+          <bitfield name="PERID12" caption="PERID Write Protection Status" mask="0x1000" values="STATUS__PERID"/>
+          <bitfield name="PERID13" caption="PERID Write Protection Status" mask="0x2000" values="STATUS__PERID"/>
+          <bitfield name="PERID14" caption="PERID Write Protection Status" mask="0x4000" values="STATUS__PERID"/>
+          <bitfield name="PERID15" caption="PERID Write Protection Status" mask="0x8000" values="STATUS__PERID"/>
+          <bitfield name="PERID16" caption="PERID Write Protection Status" mask="0x10000" values="STATUS__PERID"/>
+          <bitfield name="PERID17" caption="PERID Write Protection Status" mask="0x20000" values="STATUS__PERID"/>
+          <bitfield name="PERID18" caption="PERID Write Protection Status" mask="0x40000" values="STATUS__PERID"/>
+          <bitfield name="PERID19" caption="PERID Write Protection Status" mask="0x80000" values="STATUS__PERID"/>
+          <bitfield name="PERID20" caption="PERID Write Protection Status" mask="0x100000" values="STATUS__PERID"/>
+          <bitfield name="PERID21" caption="PERID Write Protection Status" mask="0x200000" values="STATUS__PERID"/>
+          <bitfield name="PERID22" caption="PERID Write Protection Status" mask="0x400000" values="STATUS__PERID"/>
+          <bitfield name="PERID23" caption="PERID Write Protection Status" mask="0x800000" values="STATUS__PERID"/>
+          <bitfield name="PERID24" caption="PERID Write Protection Status" mask="0x1000000" values="STATUS__PERID"/>
+          <bitfield name="PERID25" caption="PERID Write Protection Status" mask="0x2000000" values="STATUS__PERID"/>
+          <bitfield name="PERID26" caption="PERID Write Protection Status" mask="0x4000000" values="STATUS__PERID"/>
+          <bitfield name="PERID27" caption="PERID Write Protection Status" mask="0x8000000" values="STATUS__PERID"/>
+          <bitfield name="PERID28" caption="PERID Write Protection Status" mask="0x10000000" values="STATUS__PERID"/>
+          <bitfield name="PERID29" caption="PERID Write Protection Status" mask="0x20000000" values="STATUS__PERID"/>
+          <bitfield name="PERID30" caption="PERID Write Protection Status" mask="0x40000000" values="STATUS__PERID"/>
+          <bitfield name="PERID31" caption="PERID Write Protection Status" mask="0x80000000" values="STATUS__PERID"/>
+        </register>
+        <register name="LOCK" offset="0x50" rw="R" size="4" count="4" initval="0x00000000" caption="Peripheral Lock n Register">
+          <bitfield name="PERID0" caption="PERID Write Protection Lock Status" mask="0x1" values="LOCK__PERID"/>
+          <bitfield name="PERID1" caption="PERID Write Protection Lock Status" mask="0x2" values="LOCK__PERID"/>
+          <bitfield name="PERID2" caption="PERID Write Protection Lock Status" mask="0x4" values="LOCK__PERID"/>
+          <bitfield name="PERID3" caption="PERID Write Protection Lock Status" mask="0x8" values="LOCK__PERID"/>
+          <bitfield name="PERID4" caption="PERID Write Protection Lock Status" mask="0x10" values="LOCK__PERID"/>
+          <bitfield name="PERID5" caption="PERID Write Protection Lock Status" mask="0x20" values="LOCK__PERID"/>
+          <bitfield name="PERID6" caption="PERID Write Protection Lock Status" mask="0x40" values="LOCK__PERID"/>
+          <bitfield name="PERID7" caption="PERID Write Protection Lock Status" mask="0x80" values="LOCK__PERID"/>
+          <bitfield name="PERID8" caption="PERID Write Protection Lock Status" mask="0x100" values="LOCK__PERID"/>
+          <bitfield name="PERID9" caption="PERID Write Protection Lock Status" mask="0x200" values="LOCK__PERID"/>
+          <bitfield name="PERID10" caption="PERID Write Protection Lock Status" mask="0x400" values="LOCK__PERID"/>
+          <bitfield name="PERID11" caption="PERID Write Protection Lock Status" mask="0x800" values="LOCK__PERID"/>
+          <bitfield name="PERID12" caption="PERID Write Protection Lock Status" mask="0x1000" values="LOCK__PERID"/>
+          <bitfield name="PERID13" caption="PERID Write Protection Lock Status" mask="0x2000" values="LOCK__PERID"/>
+          <bitfield name="PERID14" caption="PERID Write Protection Lock Status" mask="0x4000" values="LOCK__PERID"/>
+          <bitfield name="PERID15" caption="PERID Write Protection Lock Status" mask="0x8000" values="LOCK__PERID"/>
+          <bitfield name="PERID16" caption="PERID Write Protection Lock Status" mask="0x10000" values="LOCK__PERID"/>
+          <bitfield name="PERID17" caption="PERID Write Protection Lock Status" mask="0x20000" values="LOCK__PERID"/>
+          <bitfield name="PERID18" caption="PERID Write Protection Lock Status" mask="0x40000" values="LOCK__PERID"/>
+          <bitfield name="PERID19" caption="PERID Write Protection Lock Status" mask="0x80000" values="LOCK__PERID"/>
+          <bitfield name="PERID20" caption="PERID Write Protection Lock Status" mask="0x100000" values="LOCK__PERID"/>
+          <bitfield name="PERID21" caption="PERID Write Protection Lock Status" mask="0x200000" values="LOCK__PERID"/>
+          <bitfield name="PERID22" caption="PERID Write Protection Lock Status" mask="0x400000" values="LOCK__PERID"/>
+          <bitfield name="PERID23" caption="PERID Write Protection Lock Status" mask="0x800000" values="LOCK__PERID"/>
+          <bitfield name="PERID24" caption="PERID Write Protection Lock Status" mask="0x1000000" values="LOCK__PERID"/>
+          <bitfield name="PERID25" caption="PERID Write Protection Lock Status" mask="0x2000000" values="LOCK__PERID"/>
+          <bitfield name="PERID26" caption="PERID Write Protection Lock Status" mask="0x4000000" values="LOCK__PERID"/>
+          <bitfield name="PERID27" caption="PERID Write Protection Lock Status" mask="0x8000000" values="LOCK__PERID"/>
+          <bitfield name="PERID28" caption="PERID Write Protection Lock Status" mask="0x10000000" values="LOCK__PERID"/>
+          <bitfield name="PERID29" caption="PERID Write Protection Lock Status" mask="0x20000000" values="LOCK__PERID"/>
+          <bitfield name="PERID30" caption="PERID Write Protection Lock Status" mask="0x40000000" values="LOCK__PERID"/>
+          <bitfield name="PERID31" caption="PERID Write Protection Lock Status" mask="0x80000000" values="LOCK__PERID"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__PRIV">
+        <value name="DISABLE" caption="Macro register accessible in privileged and unprivileged accesses." value="0"/>
+        <value name="ENABLE" caption="Macro registers only accessible in privileged accesses" value="1"/>
+      </value-group>
+      <value-group name="WRCTRL__KEY">
+        <value name="OFF" caption="OFF - No Action" value="0"/>
+        <value name="CLEAR" caption="CLEAR - Clear the peripheral write protection" value="1"/>
+        <value name="SET" caption="SET - Set the peripheral write protection" value="2"/>
+        <value name="LOCK" caption="LOCK - Set and Lock the write protection state of the peripheral until the next reset" value="3"/>
+      </value-group>
+      <value-group name="STATUS__PERID">
+        <value name="0" caption="Write Protection disabled" value="0"/>
+        <value name="1" caption="Write Protection enabled" value="1"/>
+      </value-group>
+      <value-group name="LOCK__PERID">
+        <value name="0" caption="Write Protection Unlocked" value="0"/>
+        <value name="1" caption="Write Protection Locked" value="1"/>
+      </value-group>
+    </module>
+    <module name="PDM" id="test_pdm_v1" name2="test_pdm_v1" version="1.0.0" caption=""/>
+    <module name="PM" id="03926" name2="pwr_rpmu_pm_v1" version="1c0" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="IORET" caption="I/O Retention" mask="0x4" values="CTRLA__IORET"/>
+        </register>
+        <register name="SLEEPCFG" offset="0x1" rw="RW" size="1" initval="0x02" caption="Sleep Configuration">
+          <bitfield name="SLEEPMODE" caption="Sleep Mode" mask="0x7" values="SLEEPCFG__SLEEPMODE"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="SLEEPRDY" caption="Backup Sleep Mode Entry Ready Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="SLEEPRDY" caption="Backup Sleep Mode Entry Ready Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="SLEEPRDY" caption="Backup Sleep Mode Entry Ready" mask="0x1"/>
+        </register>
+        <register name="STDBYCFG" offset="0x8" rw="RW" size="1" initval="0x04" caption="Standby Configuration">
+          <bitfield name="RAMCFG" caption="Ram Configuration" mask="0x1" values="STDBYCFG__RAMCFG"/>
+          <bitfield name="LPRAM" caption="Low Power RAM Enable" mask="0x4"/>
+        </register>
+        <register name="HIBCFG" offset="0x9" rw="RW" size="1" initval="0x04" caption="Hibernate Configuration">
+          <bitfield name="RAMCFG" caption="Ram Configuration" mask="0x1" values="HIBCFG__RAMCFG"/>
+          <bitfield name="LPRAM" caption="Low Power RAM Enable" mask="0x4"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__IORET">
+        <value name="NOIORET" caption="When  the  device  exits  the  HIBERNATE or BACKUP  mode,  the  I/O  line  configuration are released." value="0x0"/>
+        <value name="IORET" caption="When  the  device  exits  the  HIBERNATE or BACKUP  mode,  the  I/O  line  configuration are stretched." value="0x1"/>
+      </value-group>
+      <value-group name="SLEEPCFG__SLEEPMODE">
+        <value name="IDLE" caption="CPU, AHB and APB clocks are OFF" value="2"/>
+        <value name="STANDBY" caption="All Clocks are OFF" value="4"/>
+        <value name="HIBERNATE" caption="Backup domain is ON as well as some PDRAMs" value="5"/>
+        <value name="BACKUP" caption="Only Backup domain is powered ON" value="6"/>
+        <value name="OFF" caption="All power domains are powered OFF" value="7"/>
+      </value-group>
+      <value-group name="STDBYCFG__RAMCFG">
+        <value name="RET" caption="All the RAMs are retained" value="0"/>
+        <value name="OFF" caption="Only the first 32K bytes are retained" value="1"/>
+      </value-group>
+      <value-group name="HIBCFG__RAMCFG">
+        <value name="RET" caption="All the RAMs are retained" value="0x0"/>
+        <value name="OFF" caption="Only the first 32K bytes are retained" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="03720" name2="gpio_port_u2210_v4" version="4a0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="PORT Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="PORT Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="PORT Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="PORT Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="PORT Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="ODRAIN" caption="Open Drain Output" mask="0x80000"/>
+          <bitfield name="SLEWLIM" caption="Output Driver Slew Rate Selection" mask="0x300000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="EVCTRL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="Event Input Control">
+          <bitfield name="PID0" caption="PORT Event Pin Identifier 0" mask="0x1F"/>
+          <bitfield name="EVACT0" caption="PORT Event Action 0" mask="0x60" values="EVCTRL__EVACT0"/>
+          <bitfield name="PORTEI0" caption="PORT Event Input Enable 0" mask="0x80"/>
+          <bitfield name="PID1" caption="PORT Event Pin Identifier 1" mask="0x1F00"/>
+          <bitfield name="EVACT1" caption="PORT Event Action 1" mask="0x6000"/>
+          <bitfield name="PORTEI1" caption="PORT Event Input Enable 1" mask="0x8000"/>
+          <bitfield name="PID2" caption="PORT Event Pin Identifier 2" mask="0x1F0000"/>
+          <bitfield name="EVACT2" caption="PORT Event Action 2" mask="0x600000"/>
+          <bitfield name="PORTEI2" caption="PORT Event Input Enable 2" mask="0x800000"/>
+          <bitfield name="PID3" caption="PORT Event Pin Identifier 3" mask="0x1F000000"/>
+          <bitfield name="EVACT3" caption="PORT Event Action 3" mask="0x60000000"/>
+          <bitfield name="PORTEI3" caption="PORT Event Input Enable 3" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing for Even-Numbered Pin" mask="0xF" values="PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing for Odd-Numbered Pin" mask="0xF0" values="PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="ODRAIN" caption="Open Drain Output" mask="0x8"/>
+          <bitfield name="SLEWLIM" caption="Output Driver Slew Rate Selection" mask="0x30" values="PINCFG__SLEWLIM"/>
+        </register>
+        <register name="INTENCLR" offset="0x60" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="NSCHK" caption="Non-Secure Check Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x64" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="NSCHK" caption="Non-Secure Check Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x68" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="NSCHK" caption="Non-Secure Check" mask="0x1"/>
+        </register>
+        <register name="NONSEC" offset="0x6C" rw="RW" size="4" initval="0x00000000" caption="Security Attribution">
+          <bitfield name="NONSEC" caption="Port Security Attribution" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="NSCHK" offset="0x70" rw="RW" size="4" initval="0x00000000" caption="Security Attribution Check">
+          <bitfield name="NSCHK" caption="Port Security Attribution Check" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" size="0x80" count="4"/>
+      </register-group>
+      <value-group name="EVCTRL__EVACT0">
+        <value name="OUT" caption="Event output to pin" value="0x0"/>
+        <value name="SET" caption="Set output register of pin on event" value="0x1"/>
+        <value name="CLR" caption="Clear output register of pin on event" value="0x2"/>
+        <value name="TGL" caption="Toggle output register of pin on event" value="0x3"/>
+      </value-group>
+      <value-group name="PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0"/>
+        <value name="B" caption="Peripheral function B selected" value="1"/>
+        <value name="D" caption="Peripheral function D selected" value="3"/>
+        <value name="F" caption="Peripheral function F selected" value="5"/>
+        <value name="H" caption="Peripheral function H selected" value="7"/>
+        <value name="I" caption="Peripheral function I selected" value="8"/>
+        <value name="K" caption="Peripheral function K selected" value="10"/>
+        <value name="P" caption="Peripheral function P selected" value="15"/>
+      </value-group>
+      <value-group name="PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0"/>
+        <value name="B" caption="Peripheral function B selected" value="1"/>
+        <value name="D" caption="Peripheral function D selected" value="3"/>
+        <value name="F" caption="Peripheral function F selected" value="5"/>
+        <value name="H" caption="Peripheral function H selected" value="7"/>
+        <value name="I" caption="Peripheral function I selected" value="8"/>
+        <value name="K" caption="Peripheral function K selected" value="10"/>
+        <value name="P" caption="Peripheral function P selected" value="15"/>
+      </value-group>
+      <value-group name="PINCFG__SLEWLIM">
+        <value name="FAST" caption="Slew rate control disabled (fast rise/fall time operation)" value="0x0"/>
+        <value name="SLOW4" caption="Slew rate control enabled (4x slower)" value="0x1"/>
+        <value name="SLOW8" caption="Slew rate control enabled (8x slower)" value="0x2"/>
+        <value name="SLOW12" caption="Slew rate control enabled (12x slower)" value="0x3"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="04743" name2="afe_ptc_ctrl_apb_plrs_v1" version="1a0" caption="Polaris Peripheral Touch Controller">
+      <register-group name="PTC" caption="Polaris Peripheral Touch Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="CONTROL ENABLE REGISTER">
+          <bitfield name="SWRST" caption="Software Reset for this macro." mask="0x1" values="CTRLA__SWRST"/>
+          <bitfield name="ENABLE" caption="PTC -- Enable" mask="0x2" values="CTRLA__ENABLE"/>
+          <bitfield name="PRIV" caption="Privileged Access Only -- provides filtering of privilege/non-privilege bus accesses to SFR registers" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run In Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="EVENT CONTROL REGISTER">
+          <bitfield name="STCONVEI" caption="Start Conversion Event Input Enable" mask="0x1"/>
+          <bitfield name="DSEQREI" caption="DMA Sequencing Restart Event Input Enable" mask="0x2"/>
+          <bitfield name="STCONVINV" caption="Start Conversion Event Invert Enable" mask="0x4"/>
+          <bitfield name="DSEQRINV" caption="DMA Sequencing Restart Event Invert Enable" mask="0x8"/>
+          <bitfield name="EOCEO" caption="End of Conversion Event Output Enable" mask="0x10"/>
+          <bitfield name="WCOMPEO" caption="Window Comparator Event Output Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="DEBUG CONTROL Register">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="CTRLB" offset="0xC" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL B Register">
+          <bitfield name="CTSM" caption="Capacitive Touch Sensing Mode" mask="0x7"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x10"/>
+          <bitfield name="SDS" caption="Sampling Delay Selection." mask="0xF00"/>
+          <bitfield name="ASDV" caption="Automatic Sampling Delay Variation." mask="0x1000"/>
+          <bitfield name="CCDS" caption="Channel Change Delay Selection" mask="0x6000"/>
+          <bitfield name="RSEL" caption="Resistor Selection" mask="0x700000"/>
+        </register>
+        <register name="CTRLC" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL C Register">
+          <bitfield name="CCF" caption="Compensation Capacitor Fine Value" mask="0x1F"/>
+          <bitfield name="CCC" caption="Compensation Capacitor Coarse Value" mask="0x1F00"/>
+          <bitfield name="CI" caption="Integration Capacitor Value" mask="0x1F0000"/>
+          <bitfield name="CSD" caption="Charge Share Delay Value" mask="0xFF000000"/>
+        </register>
+        <register name="CTRLD" offset="0x14" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="CONTROL D Register">
+          <bitfield name="DAN" caption="Digital Accumulation Number" mask="0x7"/>
+          <bitfield name="AAN" caption="Analog Accumulation Number" mask="0xF00"/>
+          <bitfield name="WINCM" caption="Window Comparator Mode" mask="0x70000"/>
+          <bitfield name="WINSS" caption="Window Single Sample" mask="0x80000"/>
+          <bitfield name="EXTCIEN" caption="External Integration Capacitor Enable" mask="0x300000"/>
+          <bitfield name="POLICC" caption="Polarity of Internal Compensation Capacitor" mask="0x800000"/>
+          <bitfield name="DSEN" caption="DSEN Driven Shield Enable." mask="0x1000000"/>
+          <bitfield name="DSEQSTOP" caption="Stop DMA Sequence" mask="0x80000000"/>
+        </register>
+        <register name="CTRLE" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="CONTROL E REGISTER">
+          <bitfield name="AIPMPEN" caption="Analog Input Charge Pump Enable" mask="0x10"/>
+          <bitfield name="PRSC" caption="This field defines the PTC clock relative to the peripheral clock according to the table below." mask="0x700"/>
+          <bitfield name="WKUPEXP" caption="Wake-Up Exponent" mask="0xF000"/>
+        </register>
+        <register name="SWTRIG" offset="0x1C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Software Trigger Register">
+          <bitfield name="STCONV" caption="Start Conversion" mask="0x1"/>
+        </register>
+        <register name="WINLT" offset="0x20" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Window Comparator Low Threshold Register">
+          <bitfield name="WCLT" caption="Window Comparator Low Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINHT" offset="0x24" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Window Comparator High Threshold Register">
+          <bitfield name="WCHT" caption="Window Comparator High Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="PINEN1" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="PTC Line Enable 1 Register">
+          <bitfield name="PINEN" caption="PTC-Line 31-0 Enable" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PINEN2" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="PTC Line Enable 2 Register">
+          <bitfield name="PINEN" caption="PTC-Line 63-32 Enable" mask="0xF"/>
+        </register>
+        <register name="XSEL1" offset="0x30" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="X Line Selection 1 Register">
+          <bitfield name="XSEL" caption="X-Line Selection [31:0]" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="XSEL2" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="X Line Selection 2 Register">
+          <bitfield name="XSEL" caption="X-Line Selection [63:32]" mask="0xF"/>
+        </register>
+        <register name="YSEL1" offset="0x38" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Y Line Selection 1 Register">
+          <bitfield name="YSEL" caption="Y-Line Selection [31:0]" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="YSEL2" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Y Line Selection 2 Register">
+          <bitfield name="YSEL" caption="Y-Line Selection [63:32]" mask="0xF"/>
+        </register>
+        <register name="POLCTRL1" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Polarity Control 1 Register">
+          <bitfield name="POLARITY" caption="Choose X/Y lines Polarity [31:0]" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="POLCTRL2" offset="0x44" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Polarity Control 2 Register">
+          <bitfield name="POLARITY" caption="Choose X/Y lines Polarity [63:32]" mask="0xF"/>
+        </register>
+        <register name="INTENCLR" offset="0x48" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="INTERRUPT ENABLE CLEAR Register">
+          <bitfield name="EOC" caption="End of Conversion Enable Clear." mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Enable Clear." mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Enable Clear." mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x4C" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="INTERRUPT ENABLE SET Register">
+          <bitfield name="EOC" caption="End of Conversion Enable Set." mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Enable Set." mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Enable Set." mask="0x80"/>
+        </register>
+        <register name="INTFLAGSET" offset="0x50" rw="RW" size="4" atomic-op="clear:INTFLAGSET" initval="0x00000000" caption="INTERRUPT FLAG SET Register">
+          <bitfield name="EOC" caption="End of Conversion Enable Set." mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Enable Set." mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Enable Set." mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x54" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="INTERRUPT FLAG STATUS and CLEAR Register">
+          <bitfield name="EOC" caption="End of Conversion Flag" mask="0x1"/>
+          <bitfield name="WCOMP" caption="Window Comparator Flag" mask="0x2"/>
+          <bitfield name="ACRRDY" caption="Analog Core Ready Flag" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x58" rw="R" size="4" initval="0x00000000" caption="STATUS Register">
+          <bitfield name="PTCBUSY" caption="PTC Busy Status" mask="0x1"/>
+          <bitfield name="DAD" caption="Digital Accumulation Done" mask="0x80"/>
+          <bitfield name="WCC" caption="Window Comparator Counter" mask="0x7F00"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x5C" rw="R" size="4" initval="0x00000000" caption="Synchronization Register">
+          <bitfield name="SWRST" caption="SWRST Synchronization Busy --- Synchronizing Busy bit for swrst" mask="0x1"/>
+          <bitfield name="ENABLE" caption="ENABLE Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Control B Synchronization Busy" mask="0x4"/>
+          <bitfield name="CTRLC" caption="Control C Synchronization Busy" mask="0x8"/>
+          <bitfield name="CTRLD" caption="Control D Synchronization Busy" mask="0x10"/>
+          <bitfield name="SWTRIG" caption="Software Trigger Synchronization Busy" mask="0x20"/>
+          <bitfield name="WINLT" caption="Window Comparator Low Threshold Synchronization Busy" mask="0x40"/>
+          <bitfield name="WINHT" caption="Window Comparator High Threshold Synchronization Busy" mask="0x80"/>
+          <bitfield name="XSEL1" caption="X-lines Selection 1 Synchronization Busy" mask="0x100"/>
+          <bitfield name="XSEL2" caption="X-lines Selection 2 Synchronization Busy" mask="0x200"/>
+          <bitfield name="YSEL1" caption="Y-lines Selection 1 Synchronization Busy" mask="0x400"/>
+          <bitfield name="YSEL2" caption="Y-lines Selection 2 Synchronization Busy" mask="0x800"/>
+          <bitfield name="POLCTRL1" caption="Polarity Control 1 Synchronization Busy" mask="0x1000"/>
+          <bitfield name="POLCTRL2" caption="Polarity Control 2 Synchronization Busy" mask="0x2000"/>
+        </register>
+        <register name="DSEQCTRL" offset="0x60" rw="RW" size="4" initval="0x00000000" caption="DMA SEQUENCE CTRL Register">
+          <bitfield name="CTRLD" caption="Control D." mask="0x1"/>
+          <bitfield name="WINLT" caption="Window Comparator Low Threshold" mask="0x2"/>
+          <bitfield name="WINHT" caption="Window Comparator High Threshold" mask="0x4"/>
+          <bitfield name="XSEL" caption="X-line n Selection lower/upper half word" mask="0x78"/>
+          <bitfield name="YSEL" caption="Y-line n Selection lower/uper half word" mask="0x780"/>
+          <bitfield name="POL" caption="Polarity n lower/upper half word" mask="0x7800"/>
+          <bitfield name="CC" caption="Compensation Capacitor" mask="0x8000"/>
+          <bitfield name="CI" caption="Integration Capacitor" mask="0x10000"/>
+          <bitfield name="CSD" caption="Charge Share Delay" mask="0x20000"/>
+          <bitfield name="AUTOSTART" caption="PTC Auto-Start Conversion." mask="0x80000000"/>
+        </register>
+        <register name="DSEQSTAT" offset="0x64" rw="R" size="4" initval="0x00000000" caption="DMA SEQUENCE STATUS - Register">
+          <bitfield name="CTRLD" caption="Control D." mask="0x1"/>
+          <bitfield name="WINLT" caption="Window Comparator Low Threshold" mask="0x2"/>
+          <bitfield name="WINHT" caption="Window Comparator High Threshold" mask="0x4"/>
+          <bitfield name="XSEL" caption="X-line n  Selection lower/upper half word" mask="0x78"/>
+          <bitfield name="YSEL" caption="Y-line n Selection lower/upper half word" mask="0x780"/>
+          <bitfield name="POL" caption="Polarity n lower/upper half word" mask="0x7800"/>
+          <bitfield name="CC" caption="Compensation Capacitor" mask="0x8000"/>
+          <bitfield name="CI" caption="Integration Capacitor" mask="0x10000"/>
+          <bitfield name="CSD" caption="Charge Share Delay" mask="0x20000"/>
+          <bitfield name="BUSY" caption="Sequencing Busy" mask="0x80000000"/>
+        </register>
+        <register name="DSEQDATA" offset="0x68" rw="W" size="4" initval="0x00000000" caption="DMA SEQUENCE DATA - Register">
+          <bitfield name="DATA" caption="DMA Sequential Data." mask="0xFFFFFFFF"/>
+        </register>
+        <register name="RESULT" offset="0x6C" rw="R" size="4" initval="0x00000000" caption="Register">
+          <bitfield name="RES" caption="Result Conversion Value." mask="0xFFF"/>
+          <bitfield name="ACCRES" caption="Accumulated Result Conversion Value." mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__SWRST">
+        <value name="0" caption="There is no reset operation ongoing" value="0"/>
+        <value name="1" caption="The reset operation is ongoing" value="1"/>
+      </value-group>
+      <value-group name="CTRLA__ENABLE">
+        <value name="0" caption="Disable module. System clock is only requested for bus transactions. GCLK is never requested." value="0"/>
+        <value name="1" caption="Enable module by allowing both the generic clock and system clock requests based on the incoming clock requests from the SIB." value="1"/>
+      </value-group>
+    </module>
+    <module name="RSTC" id="03926" name2="pwr_rpmu_rstc_v1" version="1c0" caption="Reset Controller">
+      <register-group name="RSTC" caption="Reset Controller">
+        <register name="RCAUSE" offset="0x0" rw="R" size="2" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="PORCORE" caption="Brown Out CORE Detector Reset" mask="0x2"/>
+          <bitfield name="BORVDDREG" caption="Brown Out VDDREG Detector Reset" mask="0x4"/>
+          <bitfield name="BORVDDA" caption="Brown Out VDDA Detector Reset" mask="0x8"/>
+          <bitfield name="BORVDDIO" caption="Brown Out VDDIO Detector Reset" mask="0x10"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x20"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x40"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x80"/>
+          <bitfield name="BACKUP" caption="Backup Reset" mask="0x100"/>
+          <bitfield name="LOCKUP" caption="Lockup Reset" mask="0x200"/>
+        </register>
+        <register name="BKUPEXIT" offset="0x2" rw="R" size="1" initval="0x00" caption="Backup Exit Source. Implemented only if RSTC_BACKUP_IMPLEMENTED=1">
+          <bitfield name="RTC" caption="Real Timer Counter Interrupt" mask="0x2"/>
+          <bitfield name="HIB0" caption="Hibernate" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Debug Control">
+          <bitfield name="LCKUPDIS" caption="Lockup Disable" mask="0x1"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="RTC" id="03608" name2="tmr_rtc_u2250_v3" version="3b0" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <mode name="MODE2" qualifier="RTC.MODE2.CTRLA.MODE" value="2" caption="Clock/Calendar with Alarm"/>
+        <register modes="MODE2" name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="MODE2_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register modes="MODE2" name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="MODE2_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group name="RTC" caption="Real-Time Counter">
+        <mode name="MODE0" qualifier="RTC.MODE0.CTRLA.MODE" value="0" caption="32-bit Counter with Single 32-bit Compare"/>
+        <mode name="MODE1" qualifier="RTC.MODE1.CTRLA.MODE" value="1" caption="16-bit Counter with Two 16-bit Compares"/>
+        <mode name="MODE2" qualifier="RTC.MODE2.CTRLA.MODE" value="2" caption="Clock/Calendar with Alarm"/>
+        <register modes="MODE0" name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="MODE0_CTRLA__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="MODE0_CTRLA__PRESCALER"/>
+          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
+          <bitfield name="COUNTSYNC" caption="Count Read Synchronization Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="MODE1_CTRLA__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="MODE1_CTRLA__PRESCALER"/>
+          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
+          <bitfield name="COUNTSYNC" caption="Count Read Synchronization Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="MODE2_CTRLA__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="MODE2_CTRLA__PRESCALER"/>
+          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
+          <bitfield name="CLOCKSYNC" caption="Clock Read Synchronization Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE0 Control B">
+          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
+          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
+          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
+          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
+          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
+          <bitfield name="DEBF" caption="Debounce Frequency" mask="0x700" values="MODE0_CTRLB__DEBF"/>
+          <bitfield name="ACTF" caption="Active Layer Frequency" mask="0x7000" values="MODE0_CTRLB__ACTF"/>
+          <bitfield name="SEPTO" caption="Separate Tamper Outputs" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE1 Control B">
+          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
+          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
+          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
+          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
+          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
+          <bitfield name="DEBF" caption="Debounce Frequency" mask="0x700" values="MODE1_CTRLB__DEBF"/>
+          <bitfield name="ACTF" caption="Active Layer Frequency" mask="0x7000" values="MODE1_CTRLB__ACTF"/>
+          <bitfield name="SEPTO" caption="Separate Tamper Outputs" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE2 Control B">
+          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
+          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
+          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
+          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
+          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
+          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
+          <bitfield name="DEBF" caption="Debounce Frequency" mask="0x700" values="MODE2_CTRLB__DEBF"/>
+          <bitfield name="ACTF" caption="Active Layer Frequency" mask="0x7000" values="MODE2_CTRLB__ACTF"/>
+          <bitfield name="SEPTO" caption="Separate Tamper Outputs" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
+          <bitfield name="PERDEO" caption="Periodic Interval Daily Event Output Enable" mask="0x1000000"/>
+        </register>
+        <register modes="MODE1" name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="CMPEO2" caption="Compare 2 Event Output Enable" mask="0x400"/>
+          <bitfield name="CMPEO3" caption="Compare 3 Event Output Enable" mask="0x800"/>
+          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
+          <bitfield name="PERDEO" caption="Periodic Interval Daily Event Output Enable" mask="0x1000000"/>
+        </register>
+        <register modes="MODE2" name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="ALARMEO1" caption="Alarm 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
+          <bitfield name="PERDEO" caption="Periodic Interval Daily Event Output Enable" mask="0x1000000"/>
+        </register>
+        <register modes="MODE0" name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="CMP2" caption="Compare 2 Interrupt Enable" mask="0x400"/>
+          <bitfield name="CMP3" caption="Compare 3 Interrupt Enable" mask="0x800"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="ALARM1" caption="Alarm 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="CMP2" caption="Compare 2 Interrupt Enable" mask="0x400"/>
+          <bitfield name="CMP3" caption="Compare 3 Interrupt Enable" mask="0x800"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="PER0" caption="Periodic Interval 0 Enable" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1 Enable" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2 Enable" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3 Enable" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4 Enable" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5 Enable" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6 Enable" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7 Enable" mask="0x80"/>
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="ALARM1" caption="Alarm 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
+        </register>
+        <register modes="MODE0" name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
+        </register>
+        <register modes="MODE1" name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
+          <bitfield name="CMP0" caption="Compare 0" mask="0x100"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x200"/>
+          <bitfield name="CMP2" caption="Compare 2" mask="0x400"/>
+          <bitfield name="CMP3" caption="Compare 3" mask="0x800"/>
+          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
+        </register>
+        <register modes="MODE2" name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
+          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
+          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
+          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
+          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
+          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
+          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
+          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x100"/>
+          <bitfield name="ALARM1" caption="Alarm 1" mask="0x200"/>
+          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
+        </register>
+        <register name="DBGCTRL" offset="0xE" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register modes="MODE0" name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE0 Synchronization Busy Status">
+          <bitfield name="SWRST" caption="Software Reset Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
+          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
+          <bitfield name="COUNT" caption="COUNT Register Busy" mask="0x8"/>
+          <bitfield name="COMP0" caption="COMP 0 Register Busy" mask="0x20"/>
+          <bitfield name="COMP1" caption="COMP 1 Register Busy" mask="0x40"/>
+          <bitfield name="COUNTSYNC" caption="Count Synchronization Enable Bit Busy" mask="0x8000"/>
+          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
+          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
+          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
+          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
+        </register>
+        <register modes="MODE1" name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE1 Synchronization Busy Status">
+          <bitfield name="SWRST" caption="Software Reset Bit Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
+          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
+          <bitfield name="COUNT" caption="COUNT Register Busy" mask="0x8"/>
+          <bitfield name="PER" caption="PER Register Busy" mask="0x10"/>
+          <bitfield name="COMP0" caption="COMP 0 Register Busy" mask="0x20"/>
+          <bitfield name="COMP1" caption="COMP 1 Register Busy" mask="0x40"/>
+          <bitfield name="COMP2" caption="COMP 2 Register Busy" mask="0x80"/>
+          <bitfield name="COMP3" caption="COMP 3 Register Busy" mask="0x100"/>
+          <bitfield name="COUNTSYNC" caption="Count Synchronization Enable Bit Busy" mask="0x8000"/>
+          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
+          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
+          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
+          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
+        </register>
+        <register modes="MODE2" name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE2 Synchronization Busy Status">
+          <bitfield name="SWRST" caption="Software Reset Bit Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
+          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
+          <bitfield name="CLOCK" caption="CLOCK Register Busy" mask="0x8"/>
+          <bitfield name="ALARM0" caption="ALARM 0 Register Busy" mask="0x20"/>
+          <bitfield name="ALARM1" caption="ALARM 1 Register Busy" mask="0x40"/>
+          <bitfield name="MASK0" caption="MASK 0 Register Busy" mask="0x800"/>
+          <bitfield name="MASK1" caption="MASK 1 Register Busy" mask="0x1000"/>
+          <bitfield name="CLOCKSYNC" caption="Clock Synchronization Enable Bit Busy" mask="0x8000"/>
+          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
+          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
+          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
+          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
+        </register>
+        <register name="FREQCORR" offset="0x14" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register modes="MODE0" name="COUNT" offset="0x18" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="MODE1" name="COUNT" offset="0x18" rw="RW" access="RSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register modes="MODE2" name="CLOCK" offset="0x18" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register modes="MODE1" name="PER" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register modes="MODE0" name="COMP" offset="0x20" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="MODE1" name="COMP" offset="0x20" rw="RW" access="WSYNC" size="2" count="4" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+        <register-group modes="MODE2" name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x20" size="0x8" count="2"/>
+        <register name="GP" offset="0x40" rw="RW" access="WSYNC" size="4" count="4" initval="0x00000000" caption="General Purpose">
+          <bitfield name="GP" caption="General Purpose" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="TAMPCTRL" offset="0x60" rw="RW" size="4" initval="0x00000000" caption="Tamper Control">
+          <bitfield name="IN0ACT" caption="Tamper Input 0 Action" mask="0x3" values="TAMPCTRL__IN0ACT"/>
+          <bitfield name="IN1ACT" caption="Tamper Input 1 Action" mask="0xC" values="TAMPCTRL__IN1ACT"/>
+          <bitfield name="IN2ACT" caption="Tamper Input 2 Action" mask="0x30" values="TAMPCTRL__IN2ACT"/>
+          <bitfield name="IN3ACT" caption="Tamper Input 3 Action" mask="0xC0" values="TAMPCTRL__IN3ACT"/>
+          <bitfield name="IN4ACT" caption="Tamper Input 4 Action" mask="0x300" values="TAMPCTRL__IN4ACT"/>
+          <bitfield name="IN5ACT" caption="Tamper Input 5 Action" mask="0xC00" values="TAMPCTRL__IN5ACT"/>
+          <bitfield name="IN6ACT" caption="Tamper Input 6 Action" mask="0x3000" values="TAMPCTRL__IN6ACT"/>
+          <bitfield name="IN7ACT" caption="Tamper Input 7 Action" mask="0xC000" values="TAMPCTRL__IN7ACT"/>
+          <bitfield name="TAMLVL0" caption="Tamper Level Select 0" mask="0x10000"/>
+          <bitfield name="TAMLVL1" caption="Tamper Level Select 1" mask="0x20000"/>
+          <bitfield name="TAMLVL2" caption="Tamper Level Select 2" mask="0x40000"/>
+          <bitfield name="TAMLVL3" caption="Tamper Level Select 3" mask="0x80000"/>
+          <bitfield name="TAMLVL4" caption="Tamper Level Select 4" mask="0x100000"/>
+          <bitfield name="TAMLVL5" caption="Tamper Level Select 5" mask="0x200000"/>
+          <bitfield name="TAMLVL6" caption="Tamper Level Select 6" mask="0x400000"/>
+          <bitfield name="TAMLVL7" caption="Tamper Level Select 7" mask="0x800000"/>
+          <bitfield name="DEBNC0" caption="Debouncer Enable 0" mask="0x1000000"/>
+          <bitfield name="DEBNC1" caption="Debouncer Enable 1" mask="0x2000000"/>
+          <bitfield name="DEBNC2" caption="Debouncer Enable 2" mask="0x4000000"/>
+          <bitfield name="DEBNC3" caption="Debouncer Enable 3" mask="0x8000000"/>
+          <bitfield name="DEBNC4" caption="Debouncer Enable 4" mask="0x10000000"/>
+          <bitfield name="DEBNC5" caption="Debouncer Enable 5" mask="0x20000000"/>
+          <bitfield name="DEBNC6" caption="Debouncer Enable 6" mask="0x40000000"/>
+          <bitfield name="DEBNC7" caption="Debouncer Enable 7" mask="0x80000000"/>
+        </register>
+        <register modes="MODE0" name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" ocd-rw="" size="4" initval="0x00000000" caption="MODE0 Timestamp">
+          <bitfield name="COUNT" caption="Count Timestamp Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="MODE1" name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" ocd-rw="" size="4" initval="0x00000000" caption="MODE1 Timestamp">
+          <bitfield name="COUNT" caption="Count Timestamp Value" mask="0xFFFF"/>
+        </register>
+        <register modes="MODE2" name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" ocd-rw="" size="4" initval="0x00000000" caption="MODE2 Timestamp">
+          <bitfield name="SECOND" caption="Second Timestamp Value" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute Timestamp Value" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour Timestamp Value" mask="0x1F000"/>
+          <bitfield name="DAY" caption="Day Timestamp Value" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month Timestamp Value" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year Timestamp Value" mask="0xFC000000"/>
+        </register>
+        <register name="TAMPID" offset="0x68" rw="RW" size="4" atomic-op="clear:TAMPID" initval="0x00000000" caption="Tamper ID">
+          <bitfield name="TAMPID0" caption="Tamper Input 0 Detected" mask="0x1"/>
+          <bitfield name="TAMPID1" caption="Tamper Input 1 Detected" mask="0x2"/>
+          <bitfield name="TAMPID2" caption="Tamper Input 2 Detected" mask="0x4"/>
+          <bitfield name="TAMPID3" caption="Tamper Input 3 Detected" mask="0x8"/>
+          <bitfield name="TAMPID4" caption="Tamper Input 4 Detected" mask="0x10"/>
+          <bitfield name="TAMPID5" caption="Tamper Input 5 Detected" mask="0x20"/>
+          <bitfield name="TAMPID6" caption="Tamper Input 6 Detected" mask="0x40"/>
+          <bitfield name="TAMPID7" caption="Tamper Input 7 Detected" mask="0x80"/>
+          <bitfield name="TAMPEVT" caption="Tamper Event Detected" mask="0x80000000"/>
+        </register>
+        <register name="TAMPCTRLB" offset="0x6C" rw="RW" size="4" initval="0x00000000" caption="Tamper Control B">
+          <bitfield name="ALSI0" caption="Active Layer Select Internal 0" mask="0x1"/>
+          <bitfield name="ALSI1" caption="Active Layer Select Internal 1" mask="0x2"/>
+          <bitfield name="ALSI2" caption="Active Layer Select Internal 2" mask="0x4"/>
+          <bitfield name="ALSI3" caption="Active Layer Select Internal 3" mask="0x8"/>
+          <bitfield name="ALSI4" caption="Active Layer Select Internal 4" mask="0x10"/>
+          <bitfield name="ALSI5" caption="Active Layer Select Internal 5" mask="0x20"/>
+          <bitfield name="ALSI6" caption="Active Layer Select Internal 6" mask="0x40"/>
+          <bitfield name="ALSI7" caption="Active Layer Select Internal 7" mask="0x80"/>
+        </register>
+      </register-group>
+      <value-group name="MODE2_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="MODE2_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+      <value-group name="MODE0_CTRLA__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="MODE0_CTRLA__PRESCALER">
+        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x1"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x2"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x3"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x4"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x5"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x6"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x7"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x8"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x9"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
+      </value-group>
+      <value-group name="MODE1_CTRLA__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="2"/>
+      </value-group>
+      <value-group name="MODE1_CTRLA__PRESCALER">
+        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0"/>
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="1"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="2"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="3"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="4"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="5"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="6"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="7"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="8"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="9"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
+      </value-group>
+      <value-group name="MODE2_CTRLA__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="2"/>
+      </value-group>
+      <value-group name="MODE2_CTRLA__PRESCALER">
+        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x1"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x2"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x3"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x4"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x5"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x6"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x7"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x8"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x9"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
+      </value-group>
+      <value-group name="MODE0_CTRLB__DEBF">
+        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE0_CTRLB__ACTF">
+        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE1_CTRLB__DEBF">
+        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE1_CTRLB__ACTF">
+        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE2_CTRLB__DEBF">
+        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="MODE2_CTRLB__ACTF">
+        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
+        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
+        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
+        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
+        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
+        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
+        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
+        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN0ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN1ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN2ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN3ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN4ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN4 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN5ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN5 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN6ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN6 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+      <value-group name="TAMPCTRL__IN7ACT">
+        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
+        <value name="WAKE" caption="Wake and set Tamper flag" value="0x1"/>
+        <value name="CAPTURE" caption="Capture timestamp and set Tamper flag" value="0x2"/>
+        <value name="ACTL" caption="Compare IN7 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag" value="0x3"/>
+      </value-group>
+    </module>
+    <module name="SAU" id="SYSTEM_IP" version="1.0.0" caption="Security Attribution Unit">
+      <register-group name="SAU" caption="Security Attribution Unit">
+        <register name="SAU_CTRL" offset="0x0" rw="RW" size="4" access-size="4" caption="SAU Control Register">
+          <bitfield name="ENABLE" caption="SAU enable" mask="0x1"/>
+          <bitfield name="ALLNS" caption="All Non-secure" mask="0x2"/>
+        </register>
+        <register name="SAU_TYPE" offset="0x4" rw="R" size="4" access-size="4" caption="SAU Type Register">
+          <bitfield name="SREGION" caption="Number of SAU regions" mask="0xFF"/>
+        </register>
+        <register name="SAU_RNR" offset="0x8" rw="RW" size="4" access-size="4" caption="SAU Region Number Register">
+          <bitfield name="REGION" caption="Selected SAU region number" mask="0xFF"/>
+        </register>
+        <register name="SAU_RBAR" offset="0xC" rw="RW" size="4" access-size="4" caption="SAU Region Base Address Register">
+          <bitfield name="BADDR" caption="Base address" mask="0xFFFFFFE0"/>
+        </register>
+        <register name="SAU_RLAR" offset="0x10" rw="RW" size="4" access-size="4" caption="SAU Region Limit Address Register">
+          <bitfield name="ENABLE" caption="SAU region enable" mask="0x1"/>
+          <bitfield name="NSC" caption="Non-secure callable region" mask="0x2"/>
+          <bitfield name="LADDR" caption="Limit address" mask="0xFFFFFFE0"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="SCB" id="SYSTEM_IP" version="1.0.0" caption="System Control Block">
+      <register-group name="SCB" caption="System Control Block">
+        <register name="CPUID" offset="0x0" rw="R" size="4" access-size="4" caption="CPUID base register">
+          <bitfield name="Revision" caption="Revision number" mask="0xF"/>
+          <bitfield name="PartNo" caption="Part number, 0xD20=Cortex-M23" mask="0xFFF0"/>
+          <bitfield name="Architecture" caption="Architecture version, 0xC=ARMv8-M Base Line, 0xF=ARMv8-M Main Line" mask="0xF0000"/>
+          <bitfield name="Variant" caption="Variant number" mask="0xF00000"/>
+          <bitfield name="Implementer" caption="Implementer code, ARM=0x41" mask="0xFF000000"/>
+        </register>
+        <register name="ICSR" offset="0x4" rw="RW" size="4" access-size="4" caption="Interrupt Control and State Register">
+          <bitfield name="VECTACTIVE" caption="Vector active" mask="0x1FF"/>
+          <bitfield name="RETTOBASE" caption="Return to base" mask="0x800"/>
+          <bitfield name="VECTPENDING" caption="Vector pending" mask="0x1FF000"/>
+          <bitfield name="ISRPENDING" caption="Interrupt pending" mask="0x400000"/>
+          <bitfield name="ISRPREEMPT" caption="Interrupt preempt" mask="0x800000"/>
+          <bitfield name="PENDSTCLR" caption="Pend SysTick clear" mask="0x2000000" values="ICSR__PENDSTCLR"/>
+          <bitfield name="PENDSTSET" caption="Pend SysTick set" mask="0x4000000" values="ICSR__PENDSTSET"/>
+          <bitfield name="PENDSVCLR" caption="Pend PendSV clear" mask="0x8000000" values="ICSR__PENDSVCLR"/>
+          <bitfield name="PENDSVSET" caption="Pend PendSV set" mask="0x10000000" values="ICSR__PENDSVSET"/>
+          <bitfield name="PENDNMICLR" caption="Pend NMI clear" mask="0x40000000"/>
+          <bitfield name="PENDNMISET" caption="Pend NMI set" mask="0x80000000" values="ICSR__PENDNMISET"/>
+        </register>
+        <register name="VTOR" offset="0x8" rw="RW" size="4" access-size="4" caption="Vector Table Offset Register">
+          <bitfield name="TBLOFF" caption="Vector table base offset" mask="0xFFFFFF80"/>
+        </register>
+        <register name="AIRCR" offset="0xC" rw="RW" size="4" access-size="4" caption="Application Interrupt and Reset Control Register">
+          <bitfield name="VECTCLRACTIVE" caption="Debug: Clear Active State" mask="0x2" values="AIRCR__VECTCLRACTIVE"/>
+          <bitfield name="SYSRESETREQ" caption="System Reset Request" mask="0x4" values="AIRCR__SYSRESETREQ"/>
+          <bitfield name="SYSRESETREQS" caption="System Reset Request Secure only" mask="0x8" values="AIRCR__SYSRESETREQS"/>
+          <bitfield name="BFHFNMINS" caption="BusFault, HardFault and NMI Non-secure enable" mask="0x2000" values="AIRCR__BFHFNMINS"/>
+          <bitfield name="PRIS" caption="Prioritize Secure Exceptions" mask="0x4000" values="AIRCR__PRIS"/>
+          <bitfield name="ENDIANNESS" caption="Data Endianness, 0=little, 1=big" mask="0x8000" values="AIRCR__ENDIANNESS"/>
+          <bitfield name="VECTKEY" caption="Register Key (0x05FA)" mask="0xFFFF0000"/>
+        </register>
+        <register name="SCR" offset="0x10" rw="RW" size="4" access-size="4" caption="System Control Register">
+          <bitfield name="SLEEPONEXIT" caption="Sleep on exit" mask="0x2" values="SCR__SLEEPONEXIT"/>
+          <bitfield name="SLEEPDEEP" caption="Sleep deep" mask="0x4" values="SCR__SLEEPDEEP"/>
+          <bitfield name="SLEEPDEEPS" caption="Sleep deep secure" mask="0x8"/>
+          <bitfield name="SEVONPEND" caption="Send Event on Pending bit" mask="0x10" values="SCR__SEVONPEND"/>
+        </register>
+        <register name="CCR" offset="0x14" rw="RW" size="4" access-size="4" caption="Configuration and Control Register">
+          <bitfield name="USERSETMPEND" caption="User set main pending" mask="0x2"/>
+          <bitfield name="UNALIGN_TRP" caption="Unaligned trap" mask="0x8" values="CCR__UNALIGN_TRP"/>
+          <bitfield name="DIV_0_TRP" caption="Divide by zero trap" mask="0x10"/>
+          <bitfield name="BFHFNMIGN" caption="BusFault in HardFault or NMI ignore" mask="0x100"/>
+          <bitfield name="STKOFHFNMIGN" caption="Stack overflow in HardFault and NMI ignore" mask="0x400"/>
+          <bitfield name="DC" caption="Data cache enable" mask="0x10000"/>
+          <bitfield name="IC" caption="Instruction cache enable" mask="0x20000"/>
+          <bitfield name="BP" caption="Branch prediction enable" mask="0x40000"/>
+        </register>
+        <register name="SHPR2" offset="0x1C" rw="RW" size="4" access-size="4" caption="System Handler Priority Register 2">
+          <bitfield name="PRI_11" caption="Priority of system handler 11, SVCall" mask="0xFF000000"/>
+        </register>
+        <register name="SHPR3" offset="0x20" rw="RW" size="4" access-size="4" caption="System Handler Priority Register 3">
+          <bitfield name="PRI_12" caption="Priority of system handler 12, DebugMonitor" mask="0xFF"/>
+          <bitfield name="PRI_14" caption="Priority of system handler 14, PendSV" mask="0xFF0000"/>
+          <bitfield name="PRI_15" caption="Priority of system handler 15, SysTick" mask="0xFF000000"/>
+        </register>
+        <register name="SHCSR" offset="0x24" rw="RW" size="4" access-size="4" caption="System Handler Control and State Register">
+          <bitfield name="HARDFAULTACT" caption="HardFault exception active state" mask="0x4"/>
+          <bitfield name="NMIACT" caption="NMI exception active state" mask="0x20"/>
+          <bitfield name="SVCALLACT" caption="SVCall exception active state" mask="0x80"/>
+          <bitfield name="PENDSVACT" caption="PendSV exception active state" mask="0x400"/>
+          <bitfield name="SYSTICKACT" caption="SysTick exception active state" mask="0x800"/>
+          <bitfield name="SVCALLPENDED" caption="SVCall exception pended state" mask="0x8000"/>
+          <bitfield name="HARDFAULTPENDED" caption="HardFault exception pended state" mask="0x200000"/>
+        </register>
+        <register name="DFSR" offset="0x30" rw="RW" size="4" access-size="4" caption="Debug Fault Status Register">
+          <bitfield name="HALTED" caption="Halt or step event" mask="0x1"/>
+          <bitfield name="BKPT" caption="Breakpoint event" mask="0x2"/>
+          <bitfield name="DWTTRAP" caption="Watchpoint event" mask="0x4"/>
+          <bitfield name="VCATCH" caption="Vector Catch event" mask="0x8"/>
+          <bitfield name="EXTERNAL" caption="External event" mask="0x10"/>
+        </register>
+        <register name="AFSR" offset="0x3C" rw="RW" size="4" access-size="4" caption="Auxiliary Fault Status Register"/>
+        <register name="CLIDR" offset="0x78" rw="R" size="4" access-size="4" caption="Cache Level ID Register">
+          <bitfield name="Ctype1" caption="Cache type at level 1" mask="0x7" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype2" caption="Cache type at level 2" mask="0x38" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype3" caption="Cache type at level 3" mask="0x1C0" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype4" caption="Cache type at level 4" mask="0xE00" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype5" caption="Cache type at level 5" mask="0x7000" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype6" caption="Cache type at level 6" mask="0x38000" values="CLIDR__Ctype"/>
+          <bitfield name="Ctype7" caption="Cache type at level 7" mask="0x1C0000" values="CLIDR__Ctype"/>
+          <bitfield name="LoUIS" caption="Level of Unification Inner Shareable" mask="0xE00000"/>
+          <bitfield name="LoC" caption="Level of Coherence" mask="0x7000000"/>
+          <bitfield name="LoUU" caption="Level of Unification Uniprocessor" mask="0x38000000"/>
+          <bitfield name="ICB" caption="Inner cache boundary" mask="0xC0000000" values="CLIDR__ICB"/>
+        </register>
+        <register name="CTR" offset="0x7C" rw="R" size="4" access-size="4" caption="Cache Type Register">
+          <bitfield name="IminLine" caption="Instruction cache minimum line length" mask="0xF"/>
+          <bitfield name="DminLine" caption="Data cache minimum line length" mask="0xF0000"/>
+          <bitfield name="ERG" caption="Exclusives Reservation Granule" mask="0xF00000"/>
+          <bitfield name="CWG" caption="Cache Write-back Granule" mask="0xF000000"/>
+          <bitfield name="Format" caption="Cache Type Register format" mask="0xE0000000" values="CTR__Format"/>
+        </register>
+        <register name="CCSIDR" offset="0x80" rw="R" size="4" access-size="4" caption="Current Cache Size ID register">
+          <bitfield name="LineSize" caption="log2(number of words per line) - 2" mask="0x7"/>
+          <bitfield name="Associativity" caption="Associativity - 1" mask="0x1FF8"/>
+          <bitfield name="NumSets" caption="Number of sets - 1" mask="0xFFFE000"/>
+          <bitfield name="WA" caption="Write-Allocate" mask="0x10000000"/>
+          <bitfield name="RA" caption="Read-Allocate" mask="0x20000000"/>
+          <bitfield name="WB" caption="Write-Back" mask="0x40000000"/>
+          <bitfield name="WT" caption="Write-Through" mask="0x80000000"/>
+        </register>
+        <register name="CSSELR" offset="0x84" rw="RW" size="4" access-size="4" caption="Cache Size Selection Register">
+          <bitfield name="InD" caption="Instruction not Data" mask="0x1"/>
+          <bitfield name="Level" caption="Cache level - 1" mask="0xE"/>
+        </register>
+      </register-group>
+      <value-group name="ICSR__PENDSTCLR">
+        <value name="VALUE_0" caption="No effect" value="0"/>
+        <value name="VALUE_1" caption="Removes the pending state from the SysTick exception" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDSTSET">
+        <value name="VALUE_0" caption="Write: no effect; read: SysTick exception is not pending" value="0"/>
+        <value name="VALUE_1" caption="Write: changes SysTick exception state to pending; read: SysTick exception is pending" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDSVCLR">
+        <value name="VALUE_0" caption="No effect" value="0"/>
+        <value name="VALUE_1" caption="Removes the pending state from the PendSV exception" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDSVSET">
+        <value name="VALUE_0" caption="Write: no effect; read: PendSV exception is not pending" value="0"/>
+        <value name="VALUE_1" caption="Write: changes PendSV exception state to pending; read: PendSV exception is pending" value="1"/>
+      </value-group>
+      <value-group name="ICSR__PENDNMISET">
+        <value name="VALUE_0" caption="Write: no effect; read: NMI exception is not pending" value="0"/>
+        <value name="VALUE_1" caption="Write: changes NMI exception state to pending; read: NMI exception is pending" value="1"/>
+      </value-group>
+      <value-group name="AIRCR__VECTCLRACTIVE">
+        <value name="NO" caption="Do not clear active state" value="0x0"/>
+        <value name="YES" caption="Clear active state" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__SYSRESETREQ">
+        <value name="NO" caption="Do not request a system reset" value="0"/>
+        <value name="YES" caption="Request a system reset" value="1"/>
+      </value-group>
+      <value-group name="AIRCR__SYSRESETREQS">
+        <value name="BOTH" caption="SYSRESETREQ functionality is available to both Security states" value="0x0"/>
+        <value name="SECURE" caption="SYSRESETREQ functionality is only available to Secure state" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__BFHFNMINS">
+        <value name="SECURE" caption="BusFault, HardFault, and NMI are Secure" value="0x0"/>
+        <value name="NON_SECURE" caption="BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__PRIS">
+        <value name="SAME" caption="Priority ranges of Secure and Non-secure exceptions are identical" value="0x0"/>
+        <value name="NS_DEPRIO" caption="Non-secure exceptions are de-prioritized" value="0x1"/>
+      </value-group>
+      <value-group name="AIRCR__ENDIANNESS">
+        <value name="LITTLE" caption="Little-endian" value="0"/>
+        <value name="BIG" caption="Big-endian" value="1"/>
+      </value-group>
+      <value-group name="SCR__SLEEPONEXIT">
+        <value name="VALUE_0" caption="O not sleep when returning to Thread mode" value="0"/>
+        <value name="VALUE_1" caption="Enter sleep, or deep sleep, on return from an ISR" value="1"/>
+      </value-group>
+      <value-group name="SCR__SLEEPDEEP">
+        <value name="VALUE_0" caption="Sleep" value="0"/>
+        <value name="VALUE_1" caption="Deep sleep" value="1"/>
+      </value-group>
+      <value-group name="SCR__SEVONPEND">
+        <value name="VALUE_0" caption="Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded" value="0"/>
+        <value name="VALUE_1" caption="Enabled events and all interrupts, including disabled interrupts, can wakeup the processor" value="1"/>
+      </value-group>
+      <value-group name="CCR__UNALIGN_TRP">
+        <value name="VALUE_0" caption="Do not trap unaligned halfword and word accesses" value="0"/>
+        <value name="VALUE_1" caption="Trap unaligned halfword and word accesses" value="1"/>
+      </value-group>
+      <value-group name="CLIDR__Ctype">
+        <value name="NO" caption="No cache" value="0"/>
+        <value name="IC" caption="Instruction cache only" value="1"/>
+        <value name="DC" caption="Data cache only" value="2"/>
+        <value name="SEPARATE" caption="Separate instruction and data caches" value="3"/>
+        <value name="UNIFIED" caption="Unified cache" value="4"/>
+      </value-group>
+      <value-group name="CLIDR__ICB">
+        <value name="NO" caption="Not disclosed in this mechanism" value="0"/>
+        <value name="L1" caption="L1 cache is the highest inner level" value="1"/>
+        <value name="L2" caption="L2 cache is the highest inner level" value="2"/>
+        <value name="L3" caption="L3 cache is the highest inner level" value="3"/>
+      </value-group>
+      <value-group name="CTR__Format">
+        <value name="NO" caption="No cache type information provided" value="0"/>
+        <value name="YES" caption="Cache type information is provided" value="4"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="03715" name2="com_sercom_u2201_v6" version="6c0" caption="Serial Communication Interface">
+      <register-group name="SERCOM" caption="Serial Communication Interface">
+        <mode name="I2CM" qualifier="SERCOM.I2CM_CTRLA.MODE" value="5" caption="I2C Master Mode"/>
+        <mode name="I2CS" qualifier="SERCOM.I2CS_CTRLA.MODE" value="4" caption="I2C Slave Mode"/>
+        <mode name="SPI" qualifier="SERCOM.SPI_CTRLA.MODE" mask="6" value="2" caption="SPI Mode"/>
+        <mode name="USART" qualifier="SERCOM.USART_CTRLA.MODE" mask="6" value="0" caption="USART Mode"/>
+        <register modes="I2CM" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="FILTSEL" caption="Input Filter Selection" mask="0x300" values="I2CM_CTRLA__FILTSEL"/>
+          <bitfield name="SLEWRATE" caption="Slew Rate Selection" mask="0xC00" values="I2CM_CTRLA__SLEWRATE"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SMBUSEN" caption="SMBUS Input Buffer Enable" mask="0x20000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000" values="I2CM_CTRLA__SDAHOLD"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000" values="I2CM_CTRLA__SPEED"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000" values="I2CM_CTRLA__INACTOUT"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register modes="I2CS" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="FILTSEL" caption="Input Filter Selection" mask="0x300"/>
+          <bitfield name="SLEWRATE" caption="Slew Rate Selection" mask="0xC00" values="I2CS_CTRLA__SLEWRATE"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SMBUSEN" caption="SMBUS Input Buffer Enable" mask="0x20000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000" values="I2CS_CTRLA__SDAHOLD"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000" values="I2CS_CTRLA__SPEED"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register modes="SPI" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000" values="SPI_CTRLA__DOPO"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000" values="SPI_CTRLA__DIPO"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000" values="SPI_CTRLA__FORM"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000" values="SPI_CTRLA__CPHA"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000" values="SPI_CTRLA__CPOL"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000" values="SPI_CTRLA__DORD"/>
+        </register>
+        <register modes="USART" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="TXINV" caption="Transmit Data Invert" mask="0x200" values="USART_CTRLA__TXINV"/>
+          <bitfield name="RXINV" caption="Receive Data Invert" mask="0x400" values="USART_CTRLA__RXINV"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000" values="USART_CTRLA__SAMPR"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000" values="USART_CTRLA__TXPO"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000" values="USART_CTRLA__RXPO"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000" values="USART_CTRLA__FORM"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000" values="USART_CTRLA__CMODE"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000" values="USART_CTRLA__DORD"/>
+        </register>
+        <register modes="I2CM" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="I2CM_CTRLB__FIFOCLR"/>
+        </register>
+        <register modes="I2CS" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000" values="I2CS_CTRLB__AMODE"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="I2CS_CTRLB__FIFOCLR"/>
+        </register>
+        <register modes="SPI" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7" values="SPI_CTRLB__CHSIZE"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200" values="SPI_CTRLB__SSDE"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000" values="SPI_CTRLB__MSSEN"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000" values="SPI_CTRLB__AMODE"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="SPI_CTRLB__FIFOCLR"/>
+        </register>
+        <register modes="USART" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7" values="USART_CTRLB__CHSIZE"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40" values="USART_CTRLB__SBMODE"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400" values="USART_CTRLB__ENC"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000" values="USART_CTRLB__PMODE"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+          <bitfield name="FIFOCLR" caption="FIFO Clear" mask="0xC00000" values="USART_CTRLB__FIFOCLR"/>
+          <bitfield name="LINCMD" caption="LIN Command" mask="0x3000000" values="USART_CTRLB__LINCMD"/>
+        </register>
+        <register modes="I2CM" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="I2CM Control C">
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="I2CM_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="I2CM_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="I2CS" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="I2CS Control C">
+          <bitfield name="SDASETUP" caption="SDA Setup Time" mask="0xF"/>
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="I2CS_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="I2CS_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="SPI" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="SPI Control C">
+          <bitfield name="ICSPACE" caption="Inter-Character Spacing" mask="0x3F"/>
+          <bitfield name="FSES" caption="Frame Synch Edge Select" mask="0x100"/>
+          <bitfield name="FSLEN" caption="Frame Synch Length" mask="0x200" values="SPI_CTRLC__FSLEN"/>
+          <bitfield name="FSPOL" caption="Frame Synch Polarity" mask="0x400" values="SPI_CTRLC__FSPOL"/>
+          <bitfield name="IGNTUR" caption="Ignore Transmit Underrun" mask="0x800"/>
+          <bitfield name="FRMEN" caption="Frame mode enable" mask="0x10000"/>
+          <bitfield name="FMODE" caption="Frame mode" mask="0x20000" values="SPI_CTRLC__FMODE"/>
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="SPI_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="SPI_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="USART" name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="USART Control C">
+          <bitfield name="GTIME" caption="Guard Time" mask="0x7"/>
+          <bitfield name="BRKLEN" caption="LIN Master Break Length" mask="0x300" values="USART_CTRLC__BRKLEN"/>
+          <bitfield name="HDRDLY" caption="LIN Master Header Delay" mask="0xC00" values="USART_CTRLC__HDRDLY"/>
+          <bitfield name="INACK" caption="Inhibit Not Acknowledge" mask="0x10000"/>
+          <bitfield name="DSNACK" caption="Disable Successive NACK" mask="0x20000"/>
+          <bitfield name="MAXITER" caption="Maximum Iterations" mask="0x700000"/>
+          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x3000000"/>
+          <bitfield name="FIFOEN" caption="FIFO Enable" mask="0x8000000"/>
+          <bitfield name="RXTRHOLD" caption="Receive FIFO Threshold" mask="0x30000000" values="USART_CTRLC__RXTRHOLD"/>
+          <bitfield name="TXTRHOLD" caption="Transmit FIFO Threshold" mask="0xC0000000" values="USART_CTRLC__TXTRHOLD"/>
+        </register>
+        <register modes="I2CM" name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register modes="SPI" name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register modes="USART" name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT" qualifier="SERCOM.USART.CTRLA.FORM" value="0" caption="Default"/>
+          <mode name="FRAC" qualifier="SERCOM.USART.CTRLA.FORM" value="4" caption="Fractional Baud mode"/>
+          <mode name="FRACFP" qualifier="SERCOM.USART.CTRLA.FORM" value="5" caption="Fractional Baud with Parity mode"/>
+          <mode name="USARTFP" qualifier="SERCOM.USART.CTRLA.FORM" value="1" caption="USART Frame with Parity mode"/>
+          <bitfield modes="FRAC FRACFP" name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+          <bitfield modes="FRAC FRACFP" name="FP" caption="Fractional Part" mask="0xE000"/>
+          <bitfield modes="DEFAULT USARTFP" name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+        </register>
+        <register modes="USART" name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register modes="I2CM" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Disable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="I2CS" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Disable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="SPI" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="USART" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Enable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="I2CS" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt Enable" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="SPI" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="USART" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="I2CS" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="TXFE" caption="Tx FIFO Empty Interrupt" mask="0x8"/>
+          <bitfield name="RXFF" caption="Rx FIFO Full Interrupt" mask="0x10"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="SPI" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="USART" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="STATUS" offset="0x1A" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register modes="I2CS" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+          <bitfield name="LENERR" caption="Transaction Length Error" mask="0x800"/>
+        </register>
+        <register modes="SPI" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="TUR" caption="Frame Transmit Underrun" mask="0x8"/>
+          <bitfield name="LENERR" caption="Transaction Length Error" mask="0x800"/>
+        </register>
+        <register modes="USART" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+          <bitfield name="TXE" caption="Transmitter Empty" mask="0x40"/>
+          <bitfield name="ITER" caption="Maximum Number of Repetitions Reached" mask="0x80"/>
+        </register>
+        <register modes="I2CM" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+          <bitfield name="LENGTH" caption="Length Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="I2CS" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+          <bitfield name="LENGTH" caption="Length Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="SPI" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+          <bitfield name="LENGTH" caption="LENGTH Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="USART" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+          <bitfield name="RXERRCNT" caption="RXERRCNT Synchronization Busy" mask="0x8"/>
+          <bitfield name="LENGTH" caption="LENGTH Synchronization Busy" mask="0x10"/>
+        </register>
+        <register modes="USART" name="RXERRCNT" offset="0x20" rw="R" access="RSYNC" size="1" initval="0x00" caption="USART Receive Error Count"/>
+        <register modes="I2CS" name="LENGTH" offset="0x22" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="I2CS Length">
+          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
+          <bitfield name="LENEN" caption="Data Length Enable" mask="0x100"/>
+        </register>
+        <register modes="SPI" name="LENGTH" offset="0x22" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="SPI Length">
+          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
+          <bitfield name="LENEN" caption="Data Length Enable" mask="0x100"/>
+        </register>
+        <register modes="USART" name="LENGTH" offset="0x22" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="USART Length">
+          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
+          <bitfield name="LENEN" caption="Data Length Enable" mask="0x300" values="USART_LENGTH__LENEN"/>
+        </register>
+        <register modes="I2CM" name="ADDR" offset="0x24" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register modes="I2CS" name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register modes="SPI" name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register modes="I2CM" name="DATA" offset="0x28" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="I2CS" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="SPI" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="USART" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="I2CM" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+        <register modes="SPI" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+        <register modes="USART" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+        <register modes="I2CM" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="I2CM FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="I2CS" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="I2CS FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="SPI" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="SPI FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="USART" name="FIFOSPACE" offset="0x34" rw="R" size="2" initval="0x0000" caption="USART FIFO Space">
+          <bitfield name="TXSPACE" caption="Tx FIFO Empty Space" mask="0x1F"/>
+          <bitfield name="RXSPACE" caption="Rx FIFO Filled Space" mask="0x1F00"/>
+        </register>
+        <register modes="I2CM" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="I2CM FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+        <register modes="I2CS" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="I2CS FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+        <register modes="SPI" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="SPI FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+        <register modes="USART" name="FIFOPTR" offset="0x36" rw="RW" size="2" initval="0x0000" caption="USART FIFO CPU Pointers">
+          <bitfield name="CPUWRPTR" caption="CPU FIFO Write Pointer" mask="0xF"/>
+          <bitfield name="CPURDPTR" caption="CPU FIFO Read Pointer" mask="0xF00"/>
+        </register>
+      </register-group>
+      <value-group name="I2CM_CTRLA__MODE">
+        <value name="I2C_MASTER" caption="I2C host mode operation" value="5"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__FILTSEL">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="50NS" caption="Minimum 50ns filter" value="0x2"/>
+        <value name="10NS" caption="Minimum 10ns filter" value="0x3"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__SLEWRATE">
+        <value name="SMM" caption="Standard mode" value="0x0"/>
+        <value name="FM" caption="Fast mode" value="0x1"/>
+        <value name="FMP" caption="Fast mode plus" value="0x2"/>
+        <value name="HS" caption="High-speed mode" value="0x3"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__SDAHOLD">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="75NS" caption="50ns - 100ns hold time" value="0x1"/>
+        <value name="450NS" caption="300ns - 600ns hold time" value="0x2"/>
+        <value name="600NS" caption="400ns - 800ns hold time" value="0x3"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__SPEED">
+        <value name="SM" caption="Standard-Mode (SM) and Fast-Mode (FM)" value="0x0"/>
+        <value name="FMP" caption="Fast-Mode Plus (FM+)" value="0x1"/>
+        <value name="HS" caption="High-Speed Mode" value="0x2"/>
+      </value-group>
+      <value-group name="I2CM_CTRLA__INACTOUT">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="55US" caption="5-6 SCL cycle time-out" value="0x1"/>
+        <value name="105US" caption="10-11 SCL cycle time-out" value="0x2"/>
+        <value name="205US" caption="20-21-6 SCL cycle time-out" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__MODE">
+        <value name="I2C_SLAVE" caption="I2C client mode operation" value="0x4"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__SLEWRATE">
+        <value name="SM" caption="Standard mode" value="0x0"/>
+        <value name="FM" caption="Fast mode" value="0x1"/>
+        <value name="FMP" caption="Fast mode plus" value="0x2"/>
+        <value name="HS" caption="High-speed mode" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__SDAHOLD">
+        <value name="DIS" caption="Disable" value="0x0"/>
+        <value name="75NS" caption="50ns - 100ns hold time" value="0x1"/>
+        <value name="450NS" caption="300ns - 600ns hold time" value="0x2"/>
+        <value name="600NS" caption="400ns - 800ns hold time" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLA__SPEED">
+        <value name="SM" caption="Standard-Mode (SM) and Fast-Mode (FM)" value="0x0"/>
+        <value name="FMP" caption="Fast-Mode Plus (FM+)" value="0x1"/>
+        <value name="HS" caption="High-Speed Mode" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__MODE">
+        <value name="SLAVE" caption="SPI slave operation" value="0x2"/>
+        <value name="MASTER" caption="SPI master operation" value="0x3"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__DOPO">
+        <value name="PAD0" caption="DO on PAD[0], SCK on PAD[1] and SS on PAD[2]" value="0x0"/>
+        <value name="PAD3" caption="DO on PAD[3], SCK on PAD[1] and SS on PAD[2]" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__DIPO">
+        <value name="PAD0" caption="SERCOM PAD0 is used as data input" value="0x0"/>
+        <value name="PAD1" caption="SERCOM PAD1 is used as data input" value="0x1"/>
+        <value name="PAD2" caption="SERCOM PAD2 is used as data input" value="0x2"/>
+        <value name="PAD3" caption="SERCOM PAD3 is used as data input" value="0x3"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__FORM">
+        <value name="SPI" caption="SPI frame" value="0x0"/>
+        <value name="ADDR" caption="SPI frame with address" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__CPHA">
+        <value name="LEADING_EDGE" caption="The data is sampled on a leading SCK edge and changed on a trailing SCK edge" value="0x0"/>
+        <value name="TRAILING_EDGE" caption="The data is sampled on a trailing SCK edge and changed on a leading SCK edge" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__CPOL">
+        <value name="LOW" caption="SCK is low when idle" value="0x0"/>
+        <value name="HIGH" caption="SCK is high when idle" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLA__DORD">
+        <value name="MSB" caption="MSB is transmitted first" value="0x0"/>
+        <value name="LSB" caption="LSB is transmitted first" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__MODE">
+        <value name="EXTCLK" caption="USART with external clock" value="0x0"/>
+        <value name="INTCLK" caption="Usart with internal clock" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__TXINV">
+        <value name="DISABLE" caption="TxD is not inverted" value="0x0"/>
+        <value name="INV" caption="TxD is inverted" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__RXINV">
+        <value name="DISABLE" caption="RxD is not inverted" value="0x0"/>
+        <value name="INV" caption="RxD is inverted" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__SAMPR">
+        <value name="ARITHM16X" caption="16x oversampling using arithmetic baud rate generation" value="0x0"/>
+        <value name="FRAC16X" caption="16x oversampling using fractional baud rate generation" value="0x1"/>
+        <value name="ARITHM8X" caption="8x oversampling using arithmetic baud rate generation" value="0x2"/>
+        <value name="FRAC8X" caption="8x oversampling using fractional baud rate generation" value="0x3"/>
+        <value name="ARITHM3X" caption="3x oversampling using arithmetic baud rate generation" value="0x4"/>
+      </value-group>
+      <value-group name="USART_CTRLA__TXPO">
+        <value name="PAD0" caption="PAD[0] = TxD; PAD[1] = XCK" value="0x0"/>
+        <value name="PAD2" caption="PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS" value="0x2"/>
+        <value name="PAD3" caption="PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLA__RXPO">
+        <value name="PAD0" caption="SERCOM PAD0 is used for data reception" value="0x0"/>
+        <value name="PAD1" caption="SERCOM PAD1 is used for data reception" value="0x1"/>
+        <value name="PAD2" caption="SERCOM PAD2 is used for data reception" value="0x2"/>
+        <value name="PAD3" caption="SERCOM PAD3 is used for data reception" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLA__FORM">
+        <value name="USART" caption="USART frame" value="0x0"/>
+        <value name="USARTP" caption="USART frame with parity" value="0x1"/>
+        <value name="LINBRKGEN" caption="LIN Master Break and Synck generation" value="0x2"/>
+        <value name="LINBRKDET" caption="LIN Slave break detection and auto-baud" value="0x4"/>
+        <value name="BRKDET" caption="Break detection and auto-baud with parity" value="0x5"/>
+      </value-group>
+      <value-group name="USART_CTRLA__CMODE">
+        <value name="ASYNC" caption="Asynchronous communication." value="0x0"/>
+        <value name="SYNC" caption="Synchronous communication." value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLA__DORD">
+        <value name="MSB" caption="MSB is transmitted first." value="0x0"/>
+        <value name="LSB" caption="LSB is transmitted first." value="0x1"/>
+      </value-group>
+      <value-group name="I2CM_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="I2CS_CTRLB__AMODE">
+        <value name="MASK" caption="The slave responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK" value="0x0"/>
+        <value name="2ADDRS" caption="The slave responds to the two unique addresses in ADDR and ADDRMASK" value="0x1"/>
+        <value name="RANGE" caption="The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit" value="0x2"/>
+      </value-group>
+      <value-group name="I2CS_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__CHSIZE">
+        <value name="8BITS" caption="8-bits character" value="0x0"/>
+        <value name="9BITS" caption="9-bits character" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__SSDE">
+        <value name="DISABLE" caption="SS low detector is disabled" value="0x0"/>
+        <value name="ENABLE" caption="SS low detector is enabled" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__MSSEN">
+        <value name="DISABLE" caption="Hardware SS control is disabled" value="0x0"/>
+        <value name="ENABLE" caption="Hardware SS control is enabled" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__AMODE">
+        <value name="MASK" caption="ADDRMASK is used as a mask to the AADR register" value="0x0"/>
+        <value name="2ADDRS" caption="The slave responds to the two unique addresses in ADDR and ADDRMASK" value="0x1"/>
+        <value name="RANGE" caption="The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLB__CHSIZE">
+        <value name="8BITS" caption="8-bits character" value="0x0"/>
+        <value name="9BITS" caption="9-bits character" value="0x1"/>
+        <value name="5BITS" caption="5-bits character" value="0x5"/>
+        <value name="6BITS" caption="6-bits character" value="0x6"/>
+        <value name="7BITS" caption="7-bits character" value="0x7"/>
+      </value-group>
+      <value-group name="USART_CTRLB__SBMODE">
+        <value name="ONE" caption="One stop bit" value="0x0"/>
+        <value name="TWO" caption="Two stop bits" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLB__ENC">
+        <value name="DISABLE" caption="Data is not encoded" value="0x0"/>
+        <value name="IRDA" caption="Data is IrDA encoded" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLB__PMODE">
+        <value name="EVEN" caption="Even parity" value="0x0"/>
+        <value name="ODD" caption="Odd parity" value="0x1"/>
+      </value-group>
+      <value-group name="USART_CTRLB__FIFOCLR">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="TXFIFO" caption="Clear TX FIFO" value="0x1"/>
+        <value name="RXFIFO" caption="Clear RX FIFO" value="0x2"/>
+        <value name="BOTH" caption="Clear both TX and RF FIFOs" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLB__LINCMD">
+        <value name="NONE" caption="Normal USART transmission" value="0x0"/>
+        <value name="SOFTWARE_CONTROL_TRANSMIT_CMD" caption="Break field is transmitted when DATA is written" value="0x1"/>
+        <value name="AUTO_TRANSMIT_CMD" caption="Break, synch and identifier are automaticcaly transmitted when DATA is written with the identifier" value="0x2"/>
+      </value-group>
+      <value-group name="I2CM_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="I2CM_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x2"/>
+      </value-group>
+      <value-group name="I2CS_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="I2CS_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__FSLEN">
+        <value name="STROBE" caption="One SCK pulse" value="0x0"/>
+        <value name="LEVEL" caption="One frame duration" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__FSPOL">
+        <value name="HIGH" caption="VCC-level valid polarity" value="0x0"/>
+        <value name="LOW" caption="GND-level valid polarity" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__FMODE">
+        <value name="MASTER" caption="Frame Master" value="0x0"/>
+        <value name="SLAVE" caption="Frame Slave" value="0x1"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="SPI_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated as long as the FIFO is empty" value="0x2"/>
+      </value-group>
+      <value-group name="USART_CTRLC__BRKLEN">
+        <value name="13BITS" caption="Break field transmission is 13 bit times" value="0x0"/>
+        <value name="17BITS" caption="Break field transmission is 17 bit times" value="0x1"/>
+        <value name="21BITS" caption="Break field transmission is 21 bit times" value="0x2"/>
+        <value name="26BITS" caption="Break field transmission is 26 bit times" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLC__HDRDLY">
+        <value name="1BIT" caption="Delay between break and sync transmission is 1-bit time" value="0x0"/>
+        <value name="4BITS" caption="Delay between break and sync transmission is 4-bit time" value="0x1"/>
+        <value name="8BITS" caption="Delay between break and sync transmission is 8-bit time" value="0x2"/>
+        <value name="14BITS" caption="Delay between break and sync transmission is 14-bit time" value="0x3"/>
+      </value-group>
+      <value-group name="USART_CTRLC__RXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated when DATA is present in the FIFO" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when FIFO is half-full" value="0x1"/>
+        <value name="FULL" caption="Interrupt and DMA triggers are generated when FIFO is full" value="0x2"/>
+      </value-group>
+      <value-group name="USART_CTRLC__TXTRHOLD">
+        <value name="DEFAULT" caption="Interrupt and DMA triggers are generated as long as the FIFO is not full" value="0x0"/>
+        <value name="HALF" caption="Interrupt and DMA triggers are generated when half FIFO space is free" value="0x1"/>
+        <value name="EMPTY" caption="Interrupt and DMA triggers are generated when the FIFO is empty" value="0x2"/>
+      </value-group>
+      <value-group name="USART_LENGTH__LENEN">
+        <value name="DISABLE" caption="Length counter is disabled" value="0x0"/>
+        <value name="TX" caption="Length counter is enabled for transmit" value="0x1"/>
+        <value name="RX" caption="Length counter is enabled for receive" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="SUPC" id="03926" name2="pwr_rpmu_supc_v1" version="1c0" caption="Supply Controller">
+      <register-group name="SUPC" caption="Supply Controller">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="LVDET" caption="Low Voltage Detector Interrupt Enable" mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO Regulator Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Interrupt Enable" mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Interrupt Enable" mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="LVDET" caption="Low Voltage Detector Interrupt Enable" mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO Regulator Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Interrupt Enable" mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Interrupt Enable" mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Interrupt Enable" mask="0x100"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="LVDET" caption="Low Voltage Detector Interrupt. Set to one if VDDIO crosses the treshold voltage in the good direction according to LVD.DIR." mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Interrupt. Set to one if LVD is ready to operate." mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO Regulator Ready Interrupt. Set to one if ULDO is ready meaning that output voltage is correct." mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Interrupt. Is set to one if overheat condition is detected." mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Interrupt. Set to one if VDDUSB issue is detected." mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct." mask="0x100"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Flag status">
+          <bitfield name="LVDET" caption="Low Voltage Detector Status." mask="0x1"/>
+          <bitfield name="LVDRDY" caption="Low Voltage Detector Ready Status" mask="0x2"/>
+          <bitfield name="ULDORDY" caption="User LDO regulator Status. It corresponds to vreg_ready_mv signal from ULDO." mask="0x4"/>
+          <bitfield name="ULDOOVHEAT" caption="User LDO Regulator OverHeat Status. It corresponds to vreg_overheat_event_mv signal from ULDO." mask="0x8"/>
+          <bitfield name="BORVDDUSB" caption="BORVDDUSB Status. One if VDDUSB is OK. It corresponds to bor_vddusb_n_mv signal of SMOR." mask="0x20"/>
+          <bitfield name="ADDVREGRDY0" caption="Additional Regulator ready 0 Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator." mask="0x100"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Synchronisation Busy">
+          <bitfield name="BOR" caption="BOR Synchronization Busy" mask="0x1"/>
+        </register>
+        <register name="BOR" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="BOR Control">
+          <bitfield name="DCBORPSEL" caption="Duty Cycle BOR Prescaler Select" mask="0x70" values="BOR__DCBORPSEL"/>
+          <bitfield name="BORFILT" caption="BOR filtering" mask="0x300" values="BOR__BORFILT"/>
+        </register>
+        <register name="LVD" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="LVD Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="DIR" caption="Direction" mask="0x4" values="LVD__DIR"/>
+          <bitfield name="OEVEN" caption="Output Event Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x10"/>
+          <bitfield name="LEVEL" caption="Threshold Level. See &quot;pwr_smor_[nn]_v1 DOS&quot; - level section to get details." mask="0xF0000"/>
+        </register>
+        <register name="VREGCTRL" offset="0x1C" rw="RW" size="4" initval="0x00000004" caption="VREG Control">
+          <bitfield name="VREGOUT" caption="VREG Output Control in RUN mode only. Enable by production fuse by CALSUPC.VREGOUTEN" mask="0x3" values="VREGCTRL__VREGOUT"/>
+          <bitfield name="OFFSTDBY" caption="Off in Standby Control for VREGSW[N-1]. Useful for Riverside only." mask="0x4" values="VREGCTRL__OFFSTDBY"/>
+          <bitfield name="LVSTDBY" caption="Low Voltage Standby Enable" mask="0x10" values="VREGCTRL__LVSTDBY"/>
+          <bitfield name="LVHIB" caption="Low Voltage Hibernate Enable" mask="0x20" values="VREGCTRL__LVHIB"/>
+          <bitfield name="CPEN" caption="Charge Pump Enable and Auto-enable." mask="0x300"/>
+          <bitfield name="ULDOEN" caption="User LDO Voltage Regulator Enable" mask="0x1000"/>
+          <bitfield name="ULDOSTDBY" caption="User LDO Voltage Regulator Configuration" mask="0x2000" values="VREGCTRL__ULDOSTDBY"/>
+          <bitfield name="ULDOLEVEL" caption="User LDO Voltage Level Selection" mask="0xC000" values="VREGCTRL__ULDOLEVEL"/>
+          <bitfield name="AVREGEN" caption="Additional Voltage Regulator Enable" mask="0x10000"/>
+          <bitfield name="AVREGSTDBY" caption="Additional Voltage Regulator Configuration" mask="0x1000000" values="VREGCTRL__AVREGSTDBY"/>
+          <bitfield name="SRAM_VLD" caption="SRAM VALID Status Bit" mask="0x40000000"/>
+          <bitfield name="BKUP_VLD" caption="Backup Domain Valid Status Bit" mask="0x80000000"/>
+        </register>
+        <register name="VREFCTRL" offset="0x20" rw="RW" size="4" initval="0x00000002" caption="VREF Control">
+          <bitfield name="LPSTDBY" caption="Bandgap and Regulators Low Power Standby Enable" mask="0x1" values="VREFCTRL__LPSTDBY"/>
+          <bitfield name="LPHIB" caption="Bandgap and Regulators Low Power Hibernate Enable" mask="0x2" values="VREFCTRL__LPHIB"/>
+          <bitfield name="TSEN" caption="Temperature Sensor Output Enable" mask="0x10"/>
+        </register>
+        <register name="BKOUT" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="Backup Output Control">
+          <bitfield name="EN0" caption="Enable Output" mask="0x1"/>
+          <bitfield name="EN1" caption="Enable Output" mask="0x4"/>
+          <bitfield name="CLR0" caption="Clear Output" mask="0x100"/>
+          <bitfield name="CLR1" caption="Clear Output" mask="0x400"/>
+          <bitfield name="SET0" caption="Set Output" mask="0x10000"/>
+          <bitfield name="SET1" caption="Set Output" mask="0x40000"/>
+          <bitfield name="TGLOM0" caption="Toggle Output Mode" mask="0x3000000" values="BKOUT__TGLOM"/>
+          <bitfield name="TGLOM1" caption="Toggle Output Mode" mask="0xC000000" values="BKOUT__TGLOM"/>
+        </register>
+        <register name="BKIN" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Backup Input Control">
+          <bitfield name="BKIN" caption="Backup Input Value" mask="0x3"/>
+        </register>
+      </register-group>
+      <value-group name="BOR__DCBORPSEL">
+        <value name="NODIV" caption="Not Divided" value="0x0"/>
+        <value name="DIV2" caption="Divide clock by 2" value="0x1"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x2"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x3"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x4"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x5"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x6"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x7"/>
+      </value-group>
+      <value-group name="BOR__BORFILT">
+        <value name="NOFILT" caption="No digital filtering" value="0x0"/>
+        <value name="FILT32US" caption="32us filtering" value="0x1"/>
+        <value name="FILT125US" caption="125us filtering" value="0x2"/>
+        <value name="FILT250US" caption="250us filtering" value="0x3"/>
+      </value-group>
+      <value-group name="LVD__DIR">
+        <value name="rising" caption="Rising detection" value="0x0"/>
+        <value name="falling" caption="Falling detection" value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__VREGOUT">
+        <value name="1p2v" caption="In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.2v." value="0x0"/>
+        <value name="1p0v" caption="In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.0v." value="0x1"/>
+        <value name="0p8v" caption="In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 0.8v." value="0x2"/>
+      </value-group>
+      <value-group name="VREGCTRL__OFFSTDBY">
+        <value name="OFF" caption="In standby mode, VREGSW1,2,3 are OFF" value="0x0"/>
+        <value name="ON" caption="In standby mode, VREGSW1,2,3 are ON" value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__LVSTDBY">
+        <value name="1p2v" caption="In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 1.2v." value="0x0"/>
+        <value name="0p8v" caption="In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 0.8v." value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__LVHIB">
+        <value name="1p2v" caption="In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 1.2v." value="0x0"/>
+        <value name="0p8v" caption="In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 0.8v" value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__ULDOSTDBY">
+        <value name="OFFINSTDBY" caption="Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well." value="0x0"/>
+        <value name="ONINSTDBY" caption="Regulator is ON in Standby mode. is OFF from Hibernate mode. It is OFF in backup mode as well." value="0x1"/>
+      </value-group>
+      <value-group name="VREGCTRL__ULDOLEVEL">
+        <value name="1p2v" caption="Vout = 1.2v" value="0x0"/>
+        <value name="1p5v" caption="Vout = 1.5v" value="0x1"/>
+        <value name="1p8v" caption="Vout = 1.8v" value="0x2"/>
+        <value name="2p5v" caption="Vout = 2.5v" value="0x3"/>
+      </value-group>
+      <value-group name="VREGCTRL__AVREGSTDBY">
+        <value name="OFFINSTDBY" caption="Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well." value="0x0"/>
+        <value name="ONINSTDBY" caption="Regulator is ON in Standby mode if AVREGEN bit is set. is OFF from Hibernate mode. It is OFF in backup mode as well." value="0x1"/>
+      </value-group>
+      <value-group name="VREFCTRL__LPSTDBY">
+        <value name="FullPower" caption="In standby mode, bandgap and enabled regulator(s) are set to nominal power mode." value="0x0"/>
+        <value name="LowPower" caption="In standby mode, bandgap and enabled regulator(s) are set to low power mode." value="0x1"/>
+      </value-group>
+      <value-group name="VREFCTRL__LPHIB">
+        <value name="FullPower" caption="In hibernate mode, bandgap is set to nominal power mode. As a consequence, enabled regulator(s) are set to nominal power mode." value="0x0"/>
+        <value name="LowPower" caption="In hibernate mode, bandgap is set to low power mode. As a consequence, enabled regulator(s) are set to low power mode." value="0x1"/>
+      </value-group>
+      <value-group name="BKOUT__TGLOM">
+        <value name="DISABLE" caption="The output does not toggle." value="0x0"/>
+        <value name="RTCTGL" caption="The output toggles on RTC event." value="0x1"/>
+        <value name="BKUPTGL" caption="The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software." value="0x2"/>
+      </value-group>
+    </module>
+    <module name="SysTick" id="SYSTEM_IP" version="1.0.0" caption="SysTick Timer">
+      <register-group name="SysTick" caption="SysTick Timer">
+        <register name="SYST_CSR" offset="0x0" rw="RW" size="4" access-size="4" caption="SysTick Control and Status Register">
+          <bitfield name="ENABLE" caption="SysTick enable" mask="0x1"/>
+          <bitfield name="TICKINT" caption="Tick interrupt" mask="0x2"/>
+          <bitfield name="CLKSOURCE" caption="Clock source" mask="0x4"/>
+          <bitfield name="COUNTFLAG" caption="Count flag" mask="0x10000"/>
+        </register>
+        <register name="SYST_RVR" offset="0x4" rw="RW" size="4" access-size="4" caption="SysTick Reload Value Register">
+          <bitfield name="RELOAD" caption="Counter reload value" mask="0x1000000"/>
+        </register>
+        <register name="SYST_CVR" offset="0x8" rw="RW" size="4" access-size="4" caption="SysTick Current Value Register">
+          <bitfield name="CURRENT" caption="Current counter value" mask="0x1000000"/>
+        </register>
+        <register name="SYST_CALIB" offset="0xC" rw="R" size="4" access-size="4" caption="SysTick Calibration Value Register">
+          <bitfield name="TENMS" caption="Ten milliseconds" mask="0xFFFFFF"/>
+          <bitfield name="SKEW" caption="Skew" mask="0x40000000"/>
+          <bitfield name="NOREF" caption="No reference" mask="0x80000000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="TCC" id="03610" name2="tmr_tcc_u2213_v4" version="4d0" caption="Timer Counter for Control Applications">
+      <register-group name="TCC" caption="Timer Counter for Control Applications">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="MSYNC" caption="Master Synchronization (only for TCC Slave Instance)" mask="0x8000"/>
+          <bitfield name="FCYCLE" caption="Full Cycle" mask="0x10000"/>
+          <bitfield name="DMAOS" caption="DMA One-shot Trigger Mode" mask="0x800000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="RWSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period Busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKPRESC" caption="Fault A Blanking Prescaler" mask="0x8000"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKPRESC" caption="Fault B Blanking Prescaler" mask="0x8000"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="UFS" caption="Non-Recoverable Update Fault Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="UFS" caption="Non-Recoverable Update Fault Interrupt Enable" mask="0x400"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="UFS" caption="Non-Recoverable Update Fault" mask="0x400"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" access="RWSYNC" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="UFS" caption="Non-recoverable Update Fault State" mask="0x4"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBUFV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="PERBUFV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBUFV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBUFV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH6" name="COUNT" caption="Counter Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="COUNT" caption="Counter Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="COUNT" caption="Counter Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x70" values="WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0x0000FFFF" caption="Period">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHER" caption="Dithering Cycle Number" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHER" caption="Dithering Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHER" caption="Dithering Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="PER" caption="Period Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="PER" caption="Period Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="PER" caption="Period Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="PER" caption="Period Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHER" caption="Dithering Cycle Number" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHER" caption="Dithering Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHER" caption="Dithering Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="CC" caption="Channel Compare/Capture Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="CC" caption="Channel Compare/Capture Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="CC" caption="Channel Compare/Capture Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="CC" caption="Channel Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+        <register name="PERBUF" offset="0x6C" rw="RW" access="WSYNC" size="4" initval="0x0000FFFF" caption="Period Buffer">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="PERBUF" caption="Period Buffer Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="PERBUF" caption="Period Buffer Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="PERBUF" caption="Period Buffer Value" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="PERBUF" caption="Period Buffer Value" mask="0xFFFF"/>
+        </register>
+        <register name="CCBUF" offset="0x70" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DEFAULT" qualifier="TCC.CTRLA.RESOLUTION" value="0"/>
+          <mode name="DITH4" qualifier="TCC.CTRLA.RESOLUTION" value="1"/>
+          <mode name="DITH5" qualifier="TCC.CTRLA.RESOLUTION" value="2"/>
+          <mode name="DITH6" qualifier="TCC.CTRLA.RESOLUTION" value="3"/>
+          <bitfield modes="DITH4" name="DITHERBUF" caption="Channel Compare/Capture Buffer Value" mask="0xF"/>
+          <bitfield modes="DITH5" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+          <bitfield modes="DITH6" name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+          <bitfield modes="DITH6" name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFC0"/>
+          <bitfield modes="DITH5" name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFE0"/>
+          <bitfield modes="DITH4" name="CCBUF" caption="Dithering Buffer Cycle Number" mask="0xFFF0"/>
+          <bitfield modes="DEFAULT" name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update or double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+        <value name="DMAOS" caption="One-shot DMA trigger" value="5"/>
+      </value-group>
+      <value-group name="CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update or double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+        <value name="DMAOS" caption="One-shot DMA trigger" value="5"/>
+      </value-group>
+      <value-group name="FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__BLANK">
+        <value name="START" caption="Blanking applied from start of the ramp" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+        <value name="CAPTMARK" caption="Capture with ramp index as MSB value" value="7"/>
+      </value-group>
+      <value-group name="FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__BLANK">
+        <value name="START" caption="Blanking applied from start of the ramp" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+        <value name="CAPTMARK" caption="Capture with ramp index as MSB value" value="7"/>
+      </value-group>
+      <value-group name="EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="STAMP" caption="Stamp capture" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DPWM" caption="Dual compare PWM" value="3"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+        <value name="RAMP2C" caption="Critical RAMP2 operation" value="3"/>
+        <value name="RAMP2CS" caption="Critical Swapped RAMP2 operation" value="4"/>
+      </value-group>
+    </module>
+    <module name="TESTVAL" id="test_valio_mapper_v1" name2="test_valio_mapper_v1" version="1.0.0" caption=""/>
+    <module name="USB" id="03613" name2="usb_u2222_v1" version="1d0" caption="Full-Speed Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <register modes="DEVICE" name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="DEVICE" name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register modes="DEVICE" name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register modes="DEVICE" name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register modes="HOST" name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register modes="HOST" name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register modes="HOST" name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register modes="HOST" name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register modes="HOST" name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register modes="HOST" name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <register modes="DEVICE" name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register modes="DEVICE" name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register modes="DEVICE" name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register modes="HOST" name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register modes="HOST" name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register modes="HOST" name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register modes="HOST" name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register modes="HOST" name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group name="USB" caption="Full-Speed Universal Serial Bus">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x0F" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC"/>
+        </register>
+        <register modes="DEVICE" name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register modes="HOST" name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="HOST_CTRLB__SPDCONF"/>
+          <bitfield name="AUTORESUME" caption="Auto Resume Enable" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register modes="DEVICE" name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register modes="DEVICE" name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register modes="HOST" name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register modes="DEVICE" name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register modes="HOST" name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register modes="HOST" name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register modes="DEVICE" name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register modes="HOST" name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register modes="DEVICE" name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register modes="HOST" name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register modes="DEVICE" name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register modes="HOST" name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register modes="DEVICE" name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register modes="HOST" name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group modes="DEVICE" name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" size="0x20" count="8"/>
+        <register-group modes="HOST" name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" size="0x20" count="8"/>
+      </register-group>
+      <register-group name="USB_DESCRIPTOR" caption="Full-Speed Universal Serial Bus">
+        <mode name="DEVICE" qualifier="USB.CTRLA.MODE" value="0" caption="USB is Device"/>
+        <mode name="HOST" qualifier="USB.CTRLA.MODE" value="1" caption="USB is Host"/>
+        <register-group modes="DEVICE" name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" size="0x10" count="2"/>
+        <register-group modes="HOST" name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" size="0x10" count="2"/>
+      </register-group>
+      <value-group name="CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="LS" caption="Low-speed mode" value="0x1"/>
+        <value name="HS" caption="High-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="03611" name2="wdt_u2251_v2" version="2b0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run During Standby" mask="0x40"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="WEN" caption="Window Enable Synchronization Busy" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run During Standby Synchronization Busy" mask="0x8"/>
+          <bitfield name="ALWAYSON" caption="Always-On Synchronization Busy" mask="0x10"/>
+          <bitfield name="CLEAR" caption="Clear Synchronization Busy" mask="0x20"/>
+        </register>
+        <register name="CLEAR" offset="0xC" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="CONFIG__PER">
+        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="CONFIG__WINDOW">
+        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="EWCTRL__EWOFFSET">
+        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
+        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
+        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
+        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
+        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
+        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
+        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
+        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
+        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
+        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
+        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
+        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  </modules>
+  <pinouts>
+    <pinout name="P100" caption="P100">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA14"/>
+      <pin position="3" pad="PA01"/>
+      <pin position="4" pad="PA15"/>
+      <pin position="5" pad="PA02"/>
+      <pin position="6" pad="VSSIO1"/>
+      <pin position="7" pad="VDDIO"/>
+      <pin position="8" pad="PA10"/>
+      <pin position="9" pad="PA11"/>
+      <pin position="10" pad="PA12"/>
+      <pin position="11" pad="PA16"/>
+      <pin position="12" pad="PA17"/>
+      <pin position="13" pad="PA18"/>
+      <pin position="14" pad="PA03"/>
+      <pin position="15" pad="PA04"/>
+      <pin position="16" pad="PA05"/>
+      <pin position="17" pad="PA06"/>
+      <pin position="18" pad="PA13"/>
+      <pin position="19" pad="VDDIO"/>
+      <pin position="20" pad="VSSIO3"/>
+      <pin position="21" pad="PA07"/>
+      <pin position="22" pad="PA08"/>
+      <pin position="23" pad="PA09"/>
+      <pin position="24" pad="PA20"/>
+      <pin position="25" pad="PA19"/>
+      <pin position="26" pad="PB00"/>
+      <pin position="27" pad="PB07"/>
+      <pin position="28" pad="AVDD"/>
+      <pin position="29" pad="AVSS"/>
+      <pin position="30" pad="PB01"/>
+      <pin position="31" pad="PB02"/>
+      <pin position="32" pad="VDDIO"/>
+      <pin position="33" pad="VSSIO4"/>
+      <pin position="34" pad="VDDREG"/>
+      <pin position="35" pad="PB11"/>
+      <pin position="36" pad="PB12"/>
+      <pin position="37" pad="PB13"/>
+      <pin position="38" pad="PB14"/>
+      <pin position="39" pad="PB03"/>
+      <pin position="40" pad="PB04"/>
+      <pin position="41" pad="PB05"/>
+      <pin position="42" pad="PB08"/>
+      <pin position="43" pad="PB09"/>
+      <pin position="44" pad="PB06"/>
+      <pin position="45" pad="VSSIO5"/>
+      <pin position="46" pad="VDDIO"/>
+      <pin position="47" pad="PB15"/>
+      <pin position="48" pad="PB16"/>
+      <pin position="49" pad="PB17"/>
+      <pin position="50" pad="PB10"/>
+      <pin position="51" pad="PC00"/>
+      <pin position="52" pad="PC11"/>
+      <pin position="53" pad="PC12"/>
+      <pin position="54" pad="PC01"/>
+      <pin position="55" pad="PC13"/>
+      <pin position="56" pad="VDDIO"/>
+      <pin position="57" pad="VSSIO6"/>
+      <pin position="58" pad="PC02"/>
+      <pin position="59" pad="PC14"/>
+      <pin position="60" pad="PC15"/>
+      <pin position="61" pad="PC03"/>
+      <pin position="62" pad="PC16"/>
+      <pin position="63" pad="PC09"/>
+      <pin position="64" pad="PC04"/>
+      <pin position="65" pad="PC17"/>
+      <pin position="66" pad="PC10"/>
+      <pin position="67" pad="RESET_N"/>
+      <pin position="68" pad="VDDIO"/>
+      <pin position="69" pad="VSSIO7"/>
+      <pin position="70" pad="PC18"/>
+      <pin position="71" pad="PC19"/>
+      <pin position="72" pad="PC05"/>
+      <pin position="73" pad="PC06"/>
+      <pin position="74" pad="PC07"/>
+      <pin position="75" pad="PC08"/>
+      <pin position="76" pad="PD00"/>
+      <pin position="77" pad="PD10"/>
+      <pin position="78" pad="PD14"/>
+      <pin position="79" pad="PD11"/>
+      <pin position="80" pad="PD01"/>
+      <pin position="81" pad="VSSIO8"/>
+      <pin position="82" pad="VDDIO"/>
+      <pin position="83" pad="PD02"/>
+      <pin position="84" pad="PD03"/>
+      <pin position="85" pad="PD15"/>
+      <pin position="86" pad="PD16"/>
+      <pin position="87" pad="PD17"/>
+      <pin position="88" pad="PD12"/>
+      <pin position="89" pad="PD18"/>
+      <pin position="90" pad="PD13"/>
+      <pin position="91" pad="VSSIO"/>
+      <pin position="92" pad="VDDF"/>
+      <pin position="93" pad="USERLDO"/>
+      <pin position="94" pad="PD07"/>
+      <pin position="95" pad="PD19"/>
+      <pin position="96" pad="PD04"/>
+      <pin position="97" pad="PD05"/>
+      <pin position="98" pad="PD08"/>
+      <pin position="99" pad="PD20"/>
+      <pin position="100" pad="PD09"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component-version.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component-version.h
new file mode 100644
index 00000000..85dfe4a8
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component-version.h
@@ -0,0 +1,56 @@
+/*
+ * Component version header file
+ *
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef _COMPONENT_VERSION_H_INCLUDED
+#define _COMPONENT_VERSION_H_INCLUDED
+
+#define COMPONENT_VERSION_MAJOR 1
+#define COMPONENT_VERSION_MINOR 0
+
+//
+// The COMPONENT_VERSION define is composed of the major and the minor version number.
+//
+// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
+// The rest of the COMPONENT_VERSION is the major version.
+//
+#define COMPONENT_VERSION 10000
+
+//
+// The build number does not refer to the component, but to the build number
+// of the device pack that provides the component.
+//
+#define BUILD_NUMBER 27
+
+//
+// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
+//
+#define COMPONENT_VERSION_STRING "1.0"
+
+//
+// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
+//
+// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
+//
+//     "%Y-%m-%d %H:%M:%S"
+//
+//
+#define COMPONENT_DATE_STRING "2025-02-25 07:33:43"
+
+#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
+
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/ac.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/ac.h
new file mode 100644
index 00000000..c776d0ca
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/ac.h
@@ -0,0 +1,464 @@
+/*
+ * Component description for AC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_AC_COMPONENT_H_
+#define _PIC32CMGC00_AC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                       SOFTWARE API DEFINITION FOR AC                       */
+/* ************************************************************************** */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x00) (R/W 32) Pair n Comparator Control 0 -------- */
+#define AC_COMPCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (AC_COMPCTRL) Pair n Comparator Control 0  Reset Value */
+
+#define AC_COMPCTRL_ENABLE_Pos                _UINT32_(1)                                          /* (AC_COMPCTRL) Enable Position */
+#define AC_COMPCTRL_ENABLE_Msk                (_UINT32_(0x1) << AC_COMPCTRL_ENABLE_Pos)            /* (AC_COMPCTRL) Enable Mask */
+#define AC_COMPCTRL_ENABLE(value)             (AC_COMPCTRL_ENABLE_Msk & (_UINT32_(value) << AC_COMPCTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the AC_COMPCTRL register */
+#define AC_COMPCTRL_SINGLE_Pos                _UINT32_(3)                                          /* (AC_COMPCTRL) Single-Shot Mode Position */
+#define AC_COMPCTRL_SINGLE_Msk                (_UINT32_(0x1) << AC_COMPCTRL_SINGLE_Pos)            /* (AC_COMPCTRL) Single-Shot Mode Mask */
+#define AC_COMPCTRL_SINGLE(value)             (AC_COMPCTRL_SINGLE_Msk & (_UINT32_(value) << AC_COMPCTRL_SINGLE_Pos)) /* Assignment of value for SINGLE in the AC_COMPCTRL register */
+#define AC_COMPCTRL_INTSEL_Pos                _UINT32_(4)                                          /* (AC_COMPCTRL) Interrupt Selection Position */
+#define AC_COMPCTRL_INTSEL_Msk                (_UINT32_(0x3) << AC_COMPCTRL_INTSEL_Pos)            /* (AC_COMPCTRL) Interrupt Selection Mask */
+#define AC_COMPCTRL_INTSEL(value)             (AC_COMPCTRL_INTSEL_Msk & (_UINT32_(value) << AC_COMPCTRL_INTSEL_Pos)) /* Assignment of value for INTSEL in the AC_COMPCTRL register */
+#define   AC_COMPCTRL_INTSEL_TOGGLE_Val       _UINT32_(0x0)                                        /* (AC_COMPCTRL) Interrupt on comparator output toggle  */
+#define   AC_COMPCTRL_INTSEL_RISING_Val       _UINT32_(0x1)                                        /* (AC_COMPCTRL) Interrupt on comparator output rising  */
+#define   AC_COMPCTRL_INTSEL_FALLING_Val      _UINT32_(0x2)                                        /* (AC_COMPCTRL) Interrupt on comparator output falling  */
+#define   AC_COMPCTRL_INTSEL_EOC_Val          _UINT32_(0x3)                                        /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only)  */
+#define AC_COMPCTRL_INTSEL_TOGGLE             (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output toggle Position */
+#define AC_COMPCTRL_INTSEL_RISING             (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output rising Position */
+#define AC_COMPCTRL_INTSEL_FALLING            (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output falling Position */
+#define AC_COMPCTRL_INTSEL_EOC                (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */
+#define AC_COMPCTRL_RUNSTDBY_Pos              _UINT32_(6)                                          /* (AC_COMPCTRL) Run in Standby Position */
+#define AC_COMPCTRL_RUNSTDBY_Msk              (_UINT32_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)          /* (AC_COMPCTRL) Run in Standby Mask */
+#define AC_COMPCTRL_RUNSTDBY(value)           (AC_COMPCTRL_RUNSTDBY_Msk & (_UINT32_(value) << AC_COMPCTRL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the AC_COMPCTRL register */
+#define AC_COMPCTRL_MUXNEG_Pos                _UINT32_(8)                                          /* (AC_COMPCTRL) Negative Input Mux Selection Position */
+#define AC_COMPCTRL_MUXNEG_Msk                (_UINT32_(0x7) << AC_COMPCTRL_MUXNEG_Pos)            /* (AC_COMPCTRL) Negative Input Mux Selection Mask */
+#define AC_COMPCTRL_MUXNEG(value)             (AC_COMPCTRL_MUXNEG_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXNEG_Pos)) /* Assignment of value for MUXNEG in the AC_COMPCTRL register */
+#define   AC_COMPCTRL_MUXNEG_PIN0_Val         _UINT32_(0x0)                                        /* (AC_COMPCTRL) I/O pin 0  */
+#define   AC_COMPCTRL_MUXNEG_PIN1_Val         _UINT32_(0x1)                                        /* (AC_COMPCTRL) I/O pin 1  */
+#define   AC_COMPCTRL_MUXNEG_PIN2_Val         _UINT32_(0x2)                                        /* (AC_COMPCTRL) I/O pin 2  */
+#define   AC_COMPCTRL_MUXNEG_PIN3_Val         _UINT32_(0x3)                                        /* (AC_COMPCTRL) I/O pin 3  */
+#define   AC_COMPCTRL_MUXNEG_INT0_Val         _UINT32_(0x4)                                        /* (AC_COMPCTRL) Internal connection 0, device specific  */
+#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val      _UINT32_(0x5)                                        /* (AC_COMPCTRL) Bangap  */
+#define   AC_COMPCTRL_MUXNEG_GND_Val          _UINT32_(0x6)                                        /* (AC_COMPCTRL) Ground  */
+#define   AC_COMPCTRL_MUXNEG_INTDAC_Val       _UINT32_(0x7)                                        /* (AC_COMPCTRL) Internal DAC  */
+#define AC_COMPCTRL_MUXNEG_PIN0               (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */
+#define AC_COMPCTRL_MUXNEG_PIN1               (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */
+#define AC_COMPCTRL_MUXNEG_PIN2               (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */
+#define AC_COMPCTRL_MUXNEG_PIN3               (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */
+#define AC_COMPCTRL_MUXNEG_INT0               (AC_COMPCTRL_MUXNEG_INT0_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Internal connection 0, device specific Position */
+#define AC_COMPCTRL_MUXNEG_BANDGAP            (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Bangap Position */
+#define AC_COMPCTRL_MUXNEG_GND                (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Ground Position */
+#define AC_COMPCTRL_MUXNEG_INTDAC             (AC_COMPCTRL_MUXNEG_INTDAC_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Internal DAC Position */
+#define AC_COMPCTRL_MUXPOS_Pos                _UINT32_(12)                                         /* (AC_COMPCTRL) Positive Input Mux Selection Position */
+#define AC_COMPCTRL_MUXPOS_Msk                (_UINT32_(0x7) << AC_COMPCTRL_MUXPOS_Pos)            /* (AC_COMPCTRL) Positive Input Mux Selection Mask */
+#define AC_COMPCTRL_MUXPOS(value)             (AC_COMPCTRL_MUXPOS_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXPOS_Pos)) /* Assignment of value for MUXPOS in the AC_COMPCTRL register */
+#define   AC_COMPCTRL_MUXPOS_PIN0_Val         _UINT32_(0x0)                                        /* (AC_COMPCTRL) I/O pin 0  */
+#define   AC_COMPCTRL_MUXPOS_PIN1_Val         _UINT32_(0x1)                                        /* (AC_COMPCTRL) I/O pin 1  */
+#define   AC_COMPCTRL_MUXPOS_PIN2_Val         _UINT32_(0x2)                                        /* (AC_COMPCTRL) I/O pin 2  */
+#define   AC_COMPCTRL_MUXPOS_PIN3_Val         _UINT32_(0x3)                                        /* (AC_COMPCTRL) I/O pin 3  */
+#define   AC_COMPCTRL_MUXPOS_INT0_Val         _UINT32_(0x4)                                        /* (AC_COMPCTRL) Internal connection 0, device specific  */
+#define   AC_COMPCTRL_MUXPOS_INT1_Val         _UINT32_(0x5)                                        /* (AC_COMPCTRL) Internal connection 1, device specific  */
+#define   AC_COMPCTRL_MUXPOS_INT2_Val         _UINT32_(0x6)                                        /* (AC_COMPCTRL) Internal connection 2, device specific  */
+#define   AC_COMPCTRL_MUXPOS_INTDAC_Val       _UINT32_(0x7)                                        /* (AC_COMPCTRL) Internal DAC  */
+#define AC_COMPCTRL_MUXPOS_PIN0               (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */
+#define AC_COMPCTRL_MUXPOS_PIN1               (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */
+#define AC_COMPCTRL_MUXPOS_PIN2               (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */
+#define AC_COMPCTRL_MUXPOS_PIN3               (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */
+#define AC_COMPCTRL_MUXPOS_INT0               (AC_COMPCTRL_MUXPOS_INT0_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) Internal connection 0, device specific Position */
+#define AC_COMPCTRL_MUXPOS_INT1               (AC_COMPCTRL_MUXPOS_INT1_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) Internal connection 1, device specific Position */
+#define AC_COMPCTRL_MUXPOS_INT2               (AC_COMPCTRL_MUXPOS_INT2_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) Internal connection 2, device specific Position */
+#define AC_COMPCTRL_MUXPOS_INTDAC             (AC_COMPCTRL_MUXPOS_INTDAC_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) Internal DAC Position */
+#define AC_COMPCTRL_SWAP_Pos                  _UINT32_(16)                                         /* (AC_COMPCTRL) Swap Inputs and Invert Position */
+#define AC_COMPCTRL_SWAP_Msk                  (_UINT32_(0x1) << AC_COMPCTRL_SWAP_Pos)              /* (AC_COMPCTRL) Swap Inputs and Invert Mask */
+#define AC_COMPCTRL_SWAP(value)               (AC_COMPCTRL_SWAP_Msk & (_UINT32_(value) << AC_COMPCTRL_SWAP_Pos)) /* Assignment of value for SWAP in the AC_COMPCTRL register */
+#define AC_COMPCTRL_SPEED_Pos                 _UINT32_(17)                                         /* (AC_COMPCTRL) Speed Selection Position */
+#define AC_COMPCTRL_SPEED_Msk                 (_UINT32_(0x1) << AC_COMPCTRL_SPEED_Pos)             /* (AC_COMPCTRL) Speed Selection Mask */
+#define AC_COMPCTRL_SPEED(value)              (AC_COMPCTRL_SPEED_Msk & (_UINT32_(value) << AC_COMPCTRL_SPEED_Pos)) /* Assignment of value for SPEED in the AC_COMPCTRL register */
+#define   AC_COMPCTRL_SPEED_HIGH_Val          _UINT32_(0x0)                                        /* (AC_COMPCTRL) High speed, high power  */
+#define   AC_COMPCTRL_SPEED_LOW_Val           _UINT32_(0x1)                                        /* (AC_COMPCTRL) Low speed, low power  */
+#define AC_COMPCTRL_SPEED_HIGH                (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) High speed, high power Position */
+#define AC_COMPCTRL_SPEED_LOW                 (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Low speed, low power Position */
+#define AC_COMPCTRL_HYST_Pos                  _UINT32_(19)                                         /* (AC_COMPCTRL) Hysteresis Level Position */
+#define AC_COMPCTRL_HYST_Msk                  (_UINT32_(0x3) << AC_COMPCTRL_HYST_Pos)              /* (AC_COMPCTRL) Hysteresis Level Mask */
+#define AC_COMPCTRL_HYST(value)               (AC_COMPCTRL_HYST_Msk & (_UINT32_(value) << AC_COMPCTRL_HYST_Pos)) /* Assignment of value for HYST in the AC_COMPCTRL register */
+#define   AC_COMPCTRL_HYST_HYST10_Val         _UINT32_(0x0)                                        /* (AC_COMPCTRL) 10mV  */
+#define   AC_COMPCTRL_HYST_HYST20_Val         _UINT32_(0x1)                                        /* (AC_COMPCTRL) 20mV  */
+#define   AC_COMPCTRL_HYST_HYST40_Val         _UINT32_(0x2)                                        /* (AC_COMPCTRL) 40mV  */
+#define   AC_COMPCTRL_HYST_HYST60_Val         _UINT32_(0x3)                                        /* (AC_COMPCTRL) 60mV  */
+#define AC_COMPCTRL_HYST_HYST10               (AC_COMPCTRL_HYST_HYST10_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 10mV Position */
+#define AC_COMPCTRL_HYST_HYST20               (AC_COMPCTRL_HYST_HYST20_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 20mV Position */
+#define AC_COMPCTRL_HYST_HYST40               (AC_COMPCTRL_HYST_HYST40_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 40mV Position */
+#define AC_COMPCTRL_HYST_HYST60               (AC_COMPCTRL_HYST_HYST60_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 60mV Position */
+#define AC_COMPCTRL_FLEN_Pos                  _UINT32_(21)                                         /* (AC_COMPCTRL) Filter Length Position */
+#define AC_COMPCTRL_FLEN_Msk                  (_UINT32_(0x7) << AC_COMPCTRL_FLEN_Pos)              /* (AC_COMPCTRL) Filter Length Mask */
+#define AC_COMPCTRL_FLEN(value)               (AC_COMPCTRL_FLEN_Msk & (_UINT32_(value) << AC_COMPCTRL_FLEN_Pos)) /* Assignment of value for FLEN in the AC_COMPCTRL register */
+#define   AC_COMPCTRL_FLEN_OFF_Val            _UINT32_(0x0)                                        /* (AC_COMPCTRL) No filtering  */
+#define   AC_COMPCTRL_FLEN_MAJ3_Val           _UINT32_(0x1)                                        /* (AC_COMPCTRL) 3-bit majority function (2 of 3)  */
+#define   AC_COMPCTRL_FLEN_MAJ5_Val           _UINT32_(0x2)                                        /* (AC_COMPCTRL) 5-bit majority function (3 of 5)  */
+#define AC_COMPCTRL_FLEN_OFF                  (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)   /* (AC_COMPCTRL) No filtering Position */
+#define AC_COMPCTRL_FLEN_MAJ3                 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)  /* (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */
+#define AC_COMPCTRL_FLEN_MAJ5                 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)  /* (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */
+#define AC_COMPCTRL_OUT_Pos                   _UINT32_(24)                                         /* (AC_COMPCTRL) Output Position */
+#define AC_COMPCTRL_OUT_Msk                   (_UINT32_(0x3) << AC_COMPCTRL_OUT_Pos)               /* (AC_COMPCTRL) Output Mask */
+#define AC_COMPCTRL_OUT(value)                (AC_COMPCTRL_OUT_Msk & (_UINT32_(value) << AC_COMPCTRL_OUT_Pos)) /* Assignment of value for OUT in the AC_COMPCTRL register */
+#define   AC_COMPCTRL_OUT_OFF_Val             _UINT32_(0x0)                                        /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port  */
+#define   AC_COMPCTRL_OUT_ASYNC_Val           _UINT32_(0x1)                                        /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port  */
+#define   AC_COMPCTRL_OUT_SYNC_Val            _UINT32_(0x2)                                        /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port  */
+#define AC_COMPCTRL_OUT_OFF                   (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)     /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */
+#define AC_COMPCTRL_OUT_ASYNC                 (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)   /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */
+#define AC_COMPCTRL_OUT_SYNC                  (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)    /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */
+#define AC_COMPCTRL_SUT_Pos                   _UINT32_(26)                                         /* (AC_COMPCTRL) Start-up Time Position */
+#define AC_COMPCTRL_SUT_Msk                   (_UINT32_(0x3F) << AC_COMPCTRL_SUT_Pos)              /* (AC_COMPCTRL) Start-up Time Mask */
+#define AC_COMPCTRL_SUT(value)                (AC_COMPCTRL_SUT_Msk & (_UINT32_(value) << AC_COMPCTRL_SUT_Pos)) /* Assignment of value for SUT in the AC_COMPCTRL register */
+#define AC_COMPCTRL_Msk                       _UINT32_(0xFFFB777A)                                 /* (AC_COMPCTRL) Register Mask  */
+
+
+/* -------- AC_DACCTRL : (AC Offset: 0x08) (R/W 32) Dac n Control -------- */
+#define AC_DACCTRL_RESETVALUE                 _UINT32_(0x00)                                       /*  (AC_DACCTRL) Dac n Control  Reset Value */
+
+#define AC_DACCTRL_VALUE0_Pos                 _UINT32_(0)                                          /* (AC_DACCTRL) DAC0 Output Value Position */
+#define AC_DACCTRL_VALUE0_Msk                 (_UINT32_(0x7F) << AC_DACCTRL_VALUE0_Pos)            /* (AC_DACCTRL) DAC0 Output Value Mask */
+#define AC_DACCTRL_VALUE0(value)              (AC_DACCTRL_VALUE0_Msk & (_UINT32_(value) << AC_DACCTRL_VALUE0_Pos)) /* Assignment of value for VALUE0 in the AC_DACCTRL register */
+#define AC_DACCTRL_SHEN0_Pos                  _UINT32_(15)                                         /* (AC_DACCTRL) DAC0 Sample and Hold Enable Operating Mode Position */
+#define AC_DACCTRL_SHEN0_Msk                  (_UINT32_(0x1) << AC_DACCTRL_SHEN0_Pos)              /* (AC_DACCTRL) DAC0 Sample and Hold Enable Operating Mode Mask */
+#define AC_DACCTRL_SHEN0(value)               (AC_DACCTRL_SHEN0_Msk & (_UINT32_(value) << AC_DACCTRL_SHEN0_Pos)) /* Assignment of value for SHEN0 in the AC_DACCTRL register */
+#define AC_DACCTRL_VALUE1_Pos                 _UINT32_(16)                                         /* (AC_DACCTRL) DAC1 Output Value Position */
+#define AC_DACCTRL_VALUE1_Msk                 (_UINT32_(0x7F) << AC_DACCTRL_VALUE1_Pos)            /* (AC_DACCTRL) DAC1 Output Value Mask */
+#define AC_DACCTRL_VALUE1(value)              (AC_DACCTRL_VALUE1_Msk & (_UINT32_(value) << AC_DACCTRL_VALUE1_Pos)) /* Assignment of value for VALUE1 in the AC_DACCTRL register */
+#define AC_DACCTRL_SHEN1_Pos                  _UINT32_(31)                                         /* (AC_DACCTRL) DAC1 Sample and Hold Enable Operating Mode Position */
+#define AC_DACCTRL_SHEN1_Msk                  (_UINT32_(0x1) << AC_DACCTRL_SHEN1_Pos)              /* (AC_DACCTRL) DAC1 Sample and Hold Enable Operating Mode Mask */
+#define AC_DACCTRL_SHEN1(value)               (AC_DACCTRL_SHEN1_Msk & (_UINT32_(value) << AC_DACCTRL_SHEN1_Pos)) /* Assignment of value for SHEN1 in the AC_DACCTRL register */
+#define AC_DACCTRL_Msk                        _UINT32_(0x807F807F)                                 /* (AC_DACCTRL) Register Mask  */
+
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 32) Window Monitor  n Control -------- */
+#define AC_WINCTRL_RESETVALUE                 _UINT32_(0x00)                                       /*  (AC_WINCTRL) Window Monitor  n Control  Reset Value */
+
+#define AC_WINCTRL_WEN_Pos                    _UINT32_(0)                                          /* (AC_WINCTRL) Window n Mode Enable Position */
+#define AC_WINCTRL_WEN_Msk                    (_UINT32_(0x1) << AC_WINCTRL_WEN_Pos)                /* (AC_WINCTRL) Window n Mode Enable Mask */
+#define AC_WINCTRL_WEN(value)                 (AC_WINCTRL_WEN_Msk & (_UINT32_(value) << AC_WINCTRL_WEN_Pos)) /* Assignment of value for WEN in the AC_WINCTRL register */
+#define AC_WINCTRL_WINTSEL_Pos                _UINT32_(1)                                          /* (AC_WINCTRL) Window n Interrupt Selection Position */
+#define AC_WINCTRL_WINTSEL_Msk                (_UINT32_(0x3) << AC_WINCTRL_WINTSEL_Pos)            /* (AC_WINCTRL) Window n Interrupt Selection Mask */
+#define AC_WINCTRL_WINTSEL(value)             (AC_WINCTRL_WINTSEL_Msk & (_UINT32_(value) << AC_WINCTRL_WINTSEL_Pos)) /* Assignment of value for WINTSEL in the AC_WINCTRL register */
+#define   AC_WINCTRL_WINTSEL_ABOVE_Val        _UINT32_(0x0)                                        /* (AC_WINCTRL) Interrupt on signal above window  */
+#define   AC_WINCTRL_WINTSEL_INSIDE_Val       _UINT32_(0x1)                                        /* (AC_WINCTRL) Interrupt on signal inside window  */
+#define   AC_WINCTRL_WINTSEL_BELOW_Val        _UINT32_(0x2)                                        /* (AC_WINCTRL) Interrupt on signal below window  */
+#define   AC_WINCTRL_WINTSEL_OUTSIDE_Val      _UINT32_(0x3)                                        /* (AC_WINCTRL) Interrupt on signal outside window  */
+#define AC_WINCTRL_WINTSEL_ABOVE              (AC_WINCTRL_WINTSEL_ABOVE_Val << AC_WINCTRL_WINTSEL_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */
+#define AC_WINCTRL_WINTSEL_INSIDE             (AC_WINCTRL_WINTSEL_INSIDE_Val << AC_WINCTRL_WINTSEL_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */
+#define AC_WINCTRL_WINTSEL_BELOW              (AC_WINCTRL_WINTSEL_BELOW_Val << AC_WINCTRL_WINTSEL_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */
+#define AC_WINCTRL_WINTSEL_OUTSIDE            (AC_WINCTRL_WINTSEL_OUTSIDE_Val << AC_WINCTRL_WINTSEL_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */
+#define AC_WINCTRL_Msk                        _UINT32_(0x00000007)                                 /* (AC_WINCTRL) Register Mask  */
+
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 32) Control A -------- */
+#define AC_CTRLA_RESETVALUE                   _UINT32_(0x00)                                       /*  (AC_CTRLA) Control A  Reset Value */
+
+#define AC_CTRLA_SWRST_Pos                    _UINT32_(0)                                          /* (AC_CTRLA) Software Reset Position */
+#define AC_CTRLA_SWRST_Msk                    (_UINT32_(0x1) << AC_CTRLA_SWRST_Pos)                /* (AC_CTRLA) Software Reset Mask */
+#define AC_CTRLA_SWRST(value)                 (AC_CTRLA_SWRST_Msk & (_UINT32_(value) << AC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the AC_CTRLA register */
+#define AC_CTRLA_ENABLE_Pos                   _UINT32_(1)                                          /* (AC_CTRLA) Enable Position */
+#define AC_CTRLA_ENABLE_Msk                   (_UINT32_(0x1) << AC_CTRLA_ENABLE_Pos)               /* (AC_CTRLA) Enable Mask */
+#define AC_CTRLA_ENABLE(value)                (AC_CTRLA_ENABLE_Msk & (_UINT32_(value) << AC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the AC_CTRLA register */
+#define AC_CTRLA_Msk                          _UINT32_(0x00000003)                                 /* (AC_CTRLA) Register Mask  */
+
+
+/* -------- AC_CTRLB : (AC Offset: 0x04) (R/W 32) Control B -------- */
+#define AC_CTRLB_RESETVALUE                   _UINT32_(0x00)                                       /*  (AC_CTRLB) Control B  Reset Value */
+
+#define AC_CTRLB_START0_Pos                   _UINT32_(0)                                          /* (AC_CTRLB) Comparator 0 Start Comparison Position */
+#define AC_CTRLB_START0_Msk                   (_UINT32_(0x1) << AC_CTRLB_START0_Pos)               /* (AC_CTRLB) Comparator 0 Start Comparison Mask */
+#define AC_CTRLB_START0(value)                (AC_CTRLB_START0_Msk & (_UINT32_(value) << AC_CTRLB_START0_Pos)) /* Assignment of value for START0 in the AC_CTRLB register */
+#define AC_CTRLB_START1_Pos                   _UINT32_(1)                                          /* (AC_CTRLB) Comparator 1 Start Comparison Position */
+#define AC_CTRLB_START1_Msk                   (_UINT32_(0x1) << AC_CTRLB_START1_Pos)               /* (AC_CTRLB) Comparator 1 Start Comparison Mask */
+#define AC_CTRLB_START1(value)                (AC_CTRLB_START1_Msk & (_UINT32_(value) << AC_CTRLB_START1_Pos)) /* Assignment of value for START1 in the AC_CTRLB register */
+#define AC_CTRLB_Msk                          _UINT32_(0x00000003)                                 /* (AC_CTRLB) Register Mask  */
+
+#define AC_CTRLB_START_Pos                    _UINT32_(0)                                          /* (AC_CTRLB Position) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk                    (_UINT32_(0x3) << AC_CTRLB_START_Pos)                /* (AC_CTRLB Mask) START */
+#define AC_CTRLB_START(value)                 (AC_CTRLB_START_Msk & (_UINT32_(value) << AC_CTRLB_START_Pos)) 
+
+/* -------- AC_CTRLC : (AC Offset: 0x08) (R/W 32) Control C -------- */
+#define AC_CTRLC_RESETVALUE                   _UINT32_(0x00)                                       /*  (AC_CTRLC) Control C  Reset Value */
+
+#define AC_CTRLC_WIDTH_Pos                    _UINT32_(0)                                          /* (AC_CTRLC) Sample and Hold Clock Pulse Width Position */
+#define AC_CTRLC_WIDTH_Msk                    (_UINT32_(0x3FF) << AC_CTRLC_WIDTH_Pos)              /* (AC_CTRLC) Sample and Hold Clock Pulse Width Mask */
+#define AC_CTRLC_WIDTH(value)                 (AC_CTRLC_WIDTH_Msk & (_UINT32_(value) << AC_CTRLC_WIDTH_Pos)) /* Assignment of value for WIDTH in the AC_CTRLC register */
+#define AC_CTRLC_PER_Pos                      _UINT32_(12)                                         /* (AC_CTRLC) Sample and Hold Clock Period Position */
+#define AC_CTRLC_PER_Msk                      (_UINT32_(0x3FF) << AC_CTRLC_PER_Pos)                /* (AC_CTRLC) Sample and Hold Clock Period Mask */
+#define AC_CTRLC_PER(value)                   (AC_CTRLC_PER_Msk & (_UINT32_(value) << AC_CTRLC_PER_Pos)) /* Assignment of value for PER in the AC_CTRLC register */
+#define AC_CTRLC_PRESCALER_Pos                _UINT32_(24)                                         /* (AC_CTRLC) Prescaling Factor Position */
+#define AC_CTRLC_PRESCALER_Msk                (_UINT32_(0x7) << AC_CTRLC_PRESCALER_Pos)            /* (AC_CTRLC) Prescaling Factor Mask */
+#define AC_CTRLC_PRESCALER(value)             (AC_CTRLC_PRESCALER_Msk & (_UINT32_(value) << AC_CTRLC_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the AC_CTRLC register */
+#define   AC_CTRLC_PRESCALER_DIV1_Val         _UINT32_(0x0)                                        /* (AC_CTRLC) Sampling rate is GCLK_AC (No division)  */
+#define   AC_CTRLC_PRESCALER_DIV2_Val         _UINT32_(0x1)                                        /* (AC_CTRLC) Sampling rate is GCLK_AC/2  */
+#define   AC_CTRLC_PRESCALER_DIV4_Val         _UINT32_(0x2)                                        /* (AC_CTRLC) Sampling rate is GCLK_AC/4  */
+#define   AC_CTRLC_PRESCALER_DIV8_Val         _UINT32_(0x3)                                        /* (AC_CTRLC) Sampling rate is GCLK_AC/8  */
+#define   AC_CTRLC_PRESCALER_DIV16_Val        _UINT32_(0x4)                                        /* (AC_CTRLC) Sampling rate is GCLK_AC/16  */
+#define   AC_CTRLC_PRESCALER_DIV32_Val        _UINT32_(0x5)                                        /* (AC_CTRLC) Sampling rate is GCLK_AC/32  */
+#define   AC_CTRLC_PRESCALER_DIV64_Val        _UINT32_(0x6)                                        /* (AC_CTRLC) Sampling rate is GCLK_AC/64  */
+#define   AC_CTRLC_PRESCALER_DIV128_Val       _UINT32_(0x7)                                        /* (AC_CTRLC) Sampling rate is GCLK_AC/128  */
+#define AC_CTRLC_PRESCALER_DIV1               (AC_CTRLC_PRESCALER_DIV1_Val << AC_CTRLC_PRESCALER_Pos) /* (AC_CTRLC) Sampling rate is GCLK_AC (No division) Position */
+#define AC_CTRLC_PRESCALER_DIV2               (AC_CTRLC_PRESCALER_DIV2_Val << AC_CTRLC_PRESCALER_Pos) /* (AC_CTRLC) Sampling rate is GCLK_AC/2 Position */
+#define AC_CTRLC_PRESCALER_DIV4               (AC_CTRLC_PRESCALER_DIV4_Val << AC_CTRLC_PRESCALER_Pos) /* (AC_CTRLC) Sampling rate is GCLK_AC/4 Position */
+#define AC_CTRLC_PRESCALER_DIV8               (AC_CTRLC_PRESCALER_DIV8_Val << AC_CTRLC_PRESCALER_Pos) /* (AC_CTRLC) Sampling rate is GCLK_AC/8 Position */
+#define AC_CTRLC_PRESCALER_DIV16              (AC_CTRLC_PRESCALER_DIV16_Val << AC_CTRLC_PRESCALER_Pos) /* (AC_CTRLC) Sampling rate is GCLK_AC/16 Position */
+#define AC_CTRLC_PRESCALER_DIV32              (AC_CTRLC_PRESCALER_DIV32_Val << AC_CTRLC_PRESCALER_Pos) /* (AC_CTRLC) Sampling rate is GCLK_AC/32 Position */
+#define AC_CTRLC_PRESCALER_DIV64              (AC_CTRLC_PRESCALER_DIV64_Val << AC_CTRLC_PRESCALER_Pos) /* (AC_CTRLC) Sampling rate is GCLK_AC/64 Position */
+#define AC_CTRLC_PRESCALER_DIV128             (AC_CTRLC_PRESCALER_DIV128_Val << AC_CTRLC_PRESCALER_Pos) /* (AC_CTRLC) Sampling rate is GCLK_AC/128 Position */
+#define AC_CTRLC_AIPMPEN_Pos                  _UINT32_(27)                                         /* (AC_CTRLC) Analog Input Charge Pump Enable Position */
+#define AC_CTRLC_AIPMPEN_Msk                  (_UINT32_(0x1) << AC_CTRLC_AIPMPEN_Pos)              /* (AC_CTRLC) Analog Input Charge Pump Enable Mask */
+#define AC_CTRLC_AIPMPEN(value)               (AC_CTRLC_AIPMPEN_Msk & (_UINT32_(value) << AC_CTRLC_AIPMPEN_Pos)) /* Assignment of value for AIPMPEN in the AC_CTRLC register */
+#define AC_CTRLC_CONFIG_Pos                   _UINT32_(28)                                         /* (AC_CTRLC) Configuration Extension Position */
+#define AC_CTRLC_CONFIG_Msk                   (_UINT32_(0xF) << AC_CTRLC_CONFIG_Pos)               /* (AC_CTRLC) Configuration Extension Mask */
+#define AC_CTRLC_CONFIG(value)                (AC_CTRLC_CONFIG_Msk & (_UINT32_(value) << AC_CTRLC_CONFIG_Pos)) /* Assignment of value for CONFIG in the AC_CTRLC register */
+#define AC_CTRLC_Msk                          _UINT32_(0xFF3FF3FF)                                 /* (AC_CTRLC) Register Mask  */
+
+
+/* -------- AC_EVCTRL : (AC Offset: 0x0C) (R/W 32) Event Control -------- */
+#define AC_EVCTRL_RESETVALUE                  _UINT32_(0x00)                                       /*  (AC_EVCTRL) Event Control  Reset Value */
+
+#define AC_EVCTRL_COMPEO0_Pos                 _UINT32_(0)                                          /* (AC_EVCTRL) Comparator 0 Event Output Enable Position */
+#define AC_EVCTRL_COMPEO0_Msk                 (_UINT32_(0x1) << AC_EVCTRL_COMPEO0_Pos)             /* (AC_EVCTRL) Comparator 0 Event Output Enable Mask */
+#define AC_EVCTRL_COMPEO0(value)              (AC_EVCTRL_COMPEO0_Msk & (_UINT32_(value) << AC_EVCTRL_COMPEO0_Pos)) /* Assignment of value for COMPEO0 in the AC_EVCTRL register */
+#define AC_EVCTRL_COMPEO1_Pos                 _UINT32_(1)                                          /* (AC_EVCTRL) Comparator 1 Event Output Enable Position */
+#define AC_EVCTRL_COMPEO1_Msk                 (_UINT32_(0x1) << AC_EVCTRL_COMPEO1_Pos)             /* (AC_EVCTRL) Comparator 1 Event Output Enable Mask */
+#define AC_EVCTRL_COMPEO1(value)              (AC_EVCTRL_COMPEO1_Msk & (_UINT32_(value) << AC_EVCTRL_COMPEO1_Pos)) /* Assignment of value for COMPEO1 in the AC_EVCTRL register */
+#define AC_EVCTRL_WINEO0_Pos                  _UINT32_(8)                                          /* (AC_EVCTRL) Window 0 Event Output Enable Position */
+#define AC_EVCTRL_WINEO0_Msk                  (_UINT32_(0x1) << AC_EVCTRL_WINEO0_Pos)              /* (AC_EVCTRL) Window 0 Event Output Enable Mask */
+#define AC_EVCTRL_WINEO0(value)               (AC_EVCTRL_WINEO0_Msk & (_UINT32_(value) << AC_EVCTRL_WINEO0_Pos)) /* Assignment of value for WINEO0 in the AC_EVCTRL register */
+#define AC_EVCTRL_COMPEI0_Pos                 _UINT32_(16)                                         /* (AC_EVCTRL) Comparator 0 Event Input Enable Position */
+#define AC_EVCTRL_COMPEI0_Msk                 (_UINT32_(0x1) << AC_EVCTRL_COMPEI0_Pos)             /* (AC_EVCTRL) Comparator 0 Event Input Enable Mask */
+#define AC_EVCTRL_COMPEI0(value)              (AC_EVCTRL_COMPEI0_Msk & (_UINT32_(value) << AC_EVCTRL_COMPEI0_Pos)) /* Assignment of value for COMPEI0 in the AC_EVCTRL register */
+#define AC_EVCTRL_COMPEI1_Pos                 _UINT32_(17)                                         /* (AC_EVCTRL) Comparator 1 Event Input Enable Position */
+#define AC_EVCTRL_COMPEI1_Msk                 (_UINT32_(0x1) << AC_EVCTRL_COMPEI1_Pos)             /* (AC_EVCTRL) Comparator 1 Event Input Enable Mask */
+#define AC_EVCTRL_COMPEI1(value)              (AC_EVCTRL_COMPEI1_Msk & (_UINT32_(value) << AC_EVCTRL_COMPEI1_Pos)) /* Assignment of value for COMPEI1 in the AC_EVCTRL register */
+#define AC_EVCTRL_INVEI0_Pos                  _UINT32_(24)                                         /* (AC_EVCTRL) Inverted Event Input Enable 0 Position */
+#define AC_EVCTRL_INVEI0_Msk                  (_UINT32_(0x1) << AC_EVCTRL_INVEI0_Pos)              /* (AC_EVCTRL) Inverted Event Input Enable 0 Mask */
+#define AC_EVCTRL_INVEI0(value)               (AC_EVCTRL_INVEI0_Msk & (_UINT32_(value) << AC_EVCTRL_INVEI0_Pos)) /* Assignment of value for INVEI0 in the AC_EVCTRL register */
+#define AC_EVCTRL_INVEI1_Pos                  _UINT32_(25)                                         /* (AC_EVCTRL) Inverted Event Input Enable 1 Position */
+#define AC_EVCTRL_INVEI1_Msk                  (_UINT32_(0x1) << AC_EVCTRL_INVEI1_Pos)              /* (AC_EVCTRL) Inverted Event Input Enable 1 Mask */
+#define AC_EVCTRL_INVEI1(value)               (AC_EVCTRL_INVEI1_Msk & (_UINT32_(value) << AC_EVCTRL_INVEI1_Pos)) /* Assignment of value for INVEI1 in the AC_EVCTRL register */
+#define AC_EVCTRL_Msk                         _UINT32_(0x03030103)                                 /* (AC_EVCTRL) Register Mask  */
+
+#define AC_EVCTRL_COMPEO_Pos                  _UINT32_(0)                                          /* (AC_EVCTRL Position) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk                  (_UINT32_(0x3) << AC_EVCTRL_COMPEO_Pos)              /* (AC_EVCTRL Mask) COMPEO */
+#define AC_EVCTRL_COMPEO(value)               (AC_EVCTRL_COMPEO_Msk & (_UINT32_(value) << AC_EVCTRL_COMPEO_Pos)) 
+#define AC_EVCTRL_WINEO_Pos                   _UINT32_(8)                                          /* (AC_EVCTRL Position) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk                   (_UINT32_(0x1) << AC_EVCTRL_WINEO_Pos)               /* (AC_EVCTRL Mask) WINEO */
+#define AC_EVCTRL_WINEO(value)                (AC_EVCTRL_WINEO_Msk & (_UINT32_(value) << AC_EVCTRL_WINEO_Pos)) 
+#define AC_EVCTRL_COMPEI_Pos                  _UINT32_(16)                                         /* (AC_EVCTRL Position) Comparator x Event Input Enable */
+#define AC_EVCTRL_COMPEI_Msk                  (_UINT32_(0x3) << AC_EVCTRL_COMPEI_Pos)              /* (AC_EVCTRL Mask) COMPEI */
+#define AC_EVCTRL_COMPEI(value)               (AC_EVCTRL_COMPEI_Msk & (_UINT32_(value) << AC_EVCTRL_COMPEI_Pos)) 
+#define AC_EVCTRL_INVEI_Pos                   _UINT32_(24)                                         /* (AC_EVCTRL Position) Inverted Event Input Enable x */
+#define AC_EVCTRL_INVEI_Msk                   (_UINT32_(0x3) << AC_EVCTRL_INVEI_Pos)               /* (AC_EVCTRL Mask) INVEI */
+#define AC_EVCTRL_INVEI(value)                (AC_EVCTRL_INVEI_Msk & (_UINT32_(value) << AC_EVCTRL_INVEI_Pos)) 
+
+/* -------- AC_INTENCLR : (AC Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
+#define AC_INTENCLR_RESETVALUE                _UINT32_(0x00)                                       /*  (AC_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define AC_INTENCLR_COMP0_Pos                 _UINT32_(0)                                          /* (AC_INTENCLR) Comparator 0 Interrupt Enable Position */
+#define AC_INTENCLR_COMP0_Msk                 (_UINT32_(0x1) << AC_INTENCLR_COMP0_Pos)             /* (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */
+#define AC_INTENCLR_COMP0(value)              (AC_INTENCLR_COMP0_Msk & (_UINT32_(value) << AC_INTENCLR_COMP0_Pos)) /* Assignment of value for COMP0 in the AC_INTENCLR register */
+#define AC_INTENCLR_COMP1_Pos                 _UINT32_(1)                                          /* (AC_INTENCLR) Comparator 1 Interrupt Enable Position */
+#define AC_INTENCLR_COMP1_Msk                 (_UINT32_(0x1) << AC_INTENCLR_COMP1_Pos)             /* (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */
+#define AC_INTENCLR_COMP1(value)              (AC_INTENCLR_COMP1_Msk & (_UINT32_(value) << AC_INTENCLR_COMP1_Pos)) /* Assignment of value for COMP1 in the AC_INTENCLR register */
+#define AC_INTENCLR_WIN0_Pos                  _UINT32_(8)                                          /* (AC_INTENCLR) Window 0 Interrupt Enable Position */
+#define AC_INTENCLR_WIN0_Msk                  (_UINT32_(0x1) << AC_INTENCLR_WIN0_Pos)              /* (AC_INTENCLR) Window 0 Interrupt Enable Mask */
+#define AC_INTENCLR_WIN0(value)               (AC_INTENCLR_WIN0_Msk & (_UINT32_(value) << AC_INTENCLR_WIN0_Pos)) /* Assignment of value for WIN0 in the AC_INTENCLR register */
+#define AC_INTENCLR_Msk                       _UINT32_(0x00000103)                                 /* (AC_INTENCLR) Register Mask  */
+
+#define AC_INTENCLR_COMP_Pos                  _UINT32_(0)                                          /* (AC_INTENCLR Position) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk                  (_UINT32_(0x3) << AC_INTENCLR_COMP_Pos)              /* (AC_INTENCLR Mask) COMP */
+#define AC_INTENCLR_COMP(value)               (AC_INTENCLR_COMP_Msk & (_UINT32_(value) << AC_INTENCLR_COMP_Pos)) 
+#define AC_INTENCLR_WIN_Pos                   _UINT32_(8)                                          /* (AC_INTENCLR Position) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk                   (_UINT32_(0x1) << AC_INTENCLR_WIN_Pos)               /* (AC_INTENCLR Mask) WIN */
+#define AC_INTENCLR_WIN(value)                (AC_INTENCLR_WIN_Msk & (_UINT32_(value) << AC_INTENCLR_WIN_Pos)) 
+
+/* -------- AC_INTENSET : (AC Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
+#define AC_INTENSET_RESETVALUE                _UINT32_(0x00)                                       /*  (AC_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define AC_INTENSET_COMP0_Pos                 _UINT32_(0)                                          /* (AC_INTENSET) Comparator 0 Interrupt Enable Position */
+#define AC_INTENSET_COMP0_Msk                 (_UINT32_(0x1) << AC_INTENSET_COMP0_Pos)             /* (AC_INTENSET) Comparator 0 Interrupt Enable Mask */
+#define AC_INTENSET_COMP0(value)              (AC_INTENSET_COMP0_Msk & (_UINT32_(value) << AC_INTENSET_COMP0_Pos)) /* Assignment of value for COMP0 in the AC_INTENSET register */
+#define AC_INTENSET_COMP1_Pos                 _UINT32_(1)                                          /* (AC_INTENSET) Comparator 1 Interrupt Enable Position */
+#define AC_INTENSET_COMP1_Msk                 (_UINT32_(0x1) << AC_INTENSET_COMP1_Pos)             /* (AC_INTENSET) Comparator 1 Interrupt Enable Mask */
+#define AC_INTENSET_COMP1(value)              (AC_INTENSET_COMP1_Msk & (_UINT32_(value) << AC_INTENSET_COMP1_Pos)) /* Assignment of value for COMP1 in the AC_INTENSET register */
+#define AC_INTENSET_WIN0_Pos                  _UINT32_(8)                                          /* (AC_INTENSET) Window 0 Interrupt Enable Position */
+#define AC_INTENSET_WIN0_Msk                  (_UINT32_(0x1) << AC_INTENSET_WIN0_Pos)              /* (AC_INTENSET) Window 0 Interrupt Enable Mask */
+#define AC_INTENSET_WIN0(value)               (AC_INTENSET_WIN0_Msk & (_UINT32_(value) << AC_INTENSET_WIN0_Pos)) /* Assignment of value for WIN0 in the AC_INTENSET register */
+#define AC_INTENSET_Msk                       _UINT32_(0x00000103)                                 /* (AC_INTENSET) Register Mask  */
+
+#define AC_INTENSET_COMP_Pos                  _UINT32_(0)                                          /* (AC_INTENSET Position) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk                  (_UINT32_(0x3) << AC_INTENSET_COMP_Pos)              /* (AC_INTENSET Mask) COMP */
+#define AC_INTENSET_COMP(value)               (AC_INTENSET_COMP_Msk & (_UINT32_(value) << AC_INTENSET_COMP_Pos)) 
+#define AC_INTENSET_WIN_Pos                   _UINT32_(8)                                          /* (AC_INTENSET Position) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk                   (_UINT32_(0x1) << AC_INTENSET_WIN_Pos)               /* (AC_INTENSET Mask) WIN */
+#define AC_INTENSET_WIN(value)                (AC_INTENSET_WIN_Msk & (_UINT32_(value) << AC_INTENSET_WIN_Pos)) 
+
+/* -------- AC_INTFLAG : (AC Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
+#define AC_INTFLAG_RESETVALUE                 _UINT32_(0x00)                                       /*  (AC_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define AC_INTFLAG_COMP0_Pos                  _UINT32_(0)                                          /* (AC_INTFLAG) Comparator 0 Position */
+#define AC_INTFLAG_COMP0_Msk                  (_UINT32_(0x1) << AC_INTFLAG_COMP0_Pos)              /* (AC_INTFLAG) Comparator 0 Mask */
+#define AC_INTFLAG_COMP0(value)               (AC_INTFLAG_COMP0_Msk & (_UINT32_(value) << AC_INTFLAG_COMP0_Pos)) /* Assignment of value for COMP0 in the AC_INTFLAG register */
+#define AC_INTFLAG_COMP1_Pos                  _UINT32_(1)                                          /* (AC_INTFLAG) Comparator 1 Position */
+#define AC_INTFLAG_COMP1_Msk                  (_UINT32_(0x1) << AC_INTFLAG_COMP1_Pos)              /* (AC_INTFLAG) Comparator 1 Mask */
+#define AC_INTFLAG_COMP1(value)               (AC_INTFLAG_COMP1_Msk & (_UINT32_(value) << AC_INTFLAG_COMP1_Pos)) /* Assignment of value for COMP1 in the AC_INTFLAG register */
+#define AC_INTFLAG_WIN0_Pos                   _UINT32_(8)                                          /* (AC_INTFLAG) Window 0 Position */
+#define AC_INTFLAG_WIN0_Msk                   (_UINT32_(0x1) << AC_INTFLAG_WIN0_Pos)               /* (AC_INTFLAG) Window 0 Mask */
+#define AC_INTFLAG_WIN0(value)                (AC_INTFLAG_WIN0_Msk & (_UINT32_(value) << AC_INTFLAG_WIN0_Pos)) /* Assignment of value for WIN0 in the AC_INTFLAG register */
+#define AC_INTFLAG_Msk                        _UINT32_(0x00000103)                                 /* (AC_INTFLAG) Register Mask  */
+
+#define AC_INTFLAG_COMP_Pos                   _UINT32_(0)                                          /* (AC_INTFLAG Position) Comparator x */
+#define AC_INTFLAG_COMP_Msk                   (_UINT32_(0x3) << AC_INTFLAG_COMP_Pos)               /* (AC_INTFLAG Mask) COMP */
+#define AC_INTFLAG_COMP(value)                (AC_INTFLAG_COMP_Msk & (_UINT32_(value) << AC_INTFLAG_COMP_Pos)) 
+#define AC_INTFLAG_WIN_Pos                    _UINT32_(8)                                          /* (AC_INTFLAG Position) Window x */
+#define AC_INTFLAG_WIN_Msk                    (_UINT32_(0x1) << AC_INTFLAG_WIN_Pos)                /* (AC_INTFLAG Mask) WIN */
+#define AC_INTFLAG_WIN(value)                 (AC_INTFLAG_WIN_Msk & (_UINT32_(value) << AC_INTFLAG_WIN_Pos)) 
+
+/* -------- AC_STATUSA : (AC Offset: 0x1C) ( R/ 32) Status A -------- */
+#define AC_STATUSA_RESETVALUE                 _UINT32_(0x00)                                       /*  (AC_STATUSA) Status A  Reset Value */
+
+#define AC_STATUSA_STATE0_Pos                 _UINT32_(0)                                          /* (AC_STATUSA) Comparator 0 Current State Position */
+#define AC_STATUSA_STATE0_Msk                 (_UINT32_(0x1) << AC_STATUSA_STATE0_Pos)             /* (AC_STATUSA) Comparator 0 Current State Mask */
+#define AC_STATUSA_STATE0(value)              (AC_STATUSA_STATE0_Msk & (_UINT32_(value) << AC_STATUSA_STATE0_Pos)) /* Assignment of value for STATE0 in the AC_STATUSA register */
+#define AC_STATUSA_STATE1_Pos                 _UINT32_(1)                                          /* (AC_STATUSA) Comparator 1 Current State Position */
+#define AC_STATUSA_STATE1_Msk                 (_UINT32_(0x1) << AC_STATUSA_STATE1_Pos)             /* (AC_STATUSA) Comparator 1 Current State Mask */
+#define AC_STATUSA_STATE1(value)              (AC_STATUSA_STATE1_Msk & (_UINT32_(value) << AC_STATUSA_STATE1_Pos)) /* Assignment of value for STATE1 in the AC_STATUSA register */
+#define AC_STATUSA_WSTATE0_Pos                _UINT32_(16)                                         /* (AC_STATUSA) Window 0 Current State Position */
+#define AC_STATUSA_WSTATE0_Msk                (_UINT32_(0x3) << AC_STATUSA_WSTATE0_Pos)            /* (AC_STATUSA) Window 0 Current State Mask */
+#define AC_STATUSA_WSTATE0(value)             (AC_STATUSA_WSTATE0_Msk & (_UINT32_(value) << AC_STATUSA_WSTATE0_Pos)) /* Assignment of value for WSTATE0 in the AC_STATUSA register */
+#define   AC_STATUSA_WSTATE0_ABOVE_Val        _UINT32_(0x0)                                        /* (AC_STATUSA) Signal is above window  */
+#define   AC_STATUSA_WSTATE0_INSIDE_Val       _UINT32_(0x1)                                        /* (AC_STATUSA) Signal is inside window  */
+#define   AC_STATUSA_WSTATE0_BELOW_Val        _UINT32_(0x2)                                        /* (AC_STATUSA) Signal is below window  */
+#define AC_STATUSA_WSTATE0_ABOVE              (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is above window Position */
+#define AC_STATUSA_WSTATE0_INSIDE             (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is inside window Position */
+#define AC_STATUSA_WSTATE0_BELOW              (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is below window Position */
+#define AC_STATUSA_Msk                        _UINT32_(0x00030003)                                 /* (AC_STATUSA) Register Mask  */
+
+#define AC_STATUSA_STATE_Pos                  _UINT32_(0)                                          /* (AC_STATUSA Position) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk                  (_UINT32_(0x3) << AC_STATUSA_STATE_Pos)              /* (AC_STATUSA Mask) STATE */
+#define AC_STATUSA_STATE(value)               (AC_STATUSA_STATE_Msk & (_UINT32_(value) << AC_STATUSA_STATE_Pos)) 
+
+/* -------- AC_STATUSB : (AC Offset: 0x20) ( R/ 32) Status B -------- */
+#define AC_STATUSB_RESETVALUE                 _UINT32_(0x00)                                       /*  (AC_STATUSB) Status B  Reset Value */
+
+#define AC_STATUSB_READY0_Pos                 _UINT32_(0)                                          /* (AC_STATUSB) Comparator 0 Ready Position */
+#define AC_STATUSB_READY0_Msk                 (_UINT32_(0x1) << AC_STATUSB_READY0_Pos)             /* (AC_STATUSB) Comparator 0 Ready Mask */
+#define AC_STATUSB_READY0(value)              (AC_STATUSB_READY0_Msk & (_UINT32_(value) << AC_STATUSB_READY0_Pos)) /* Assignment of value for READY0 in the AC_STATUSB register */
+#define AC_STATUSB_READY1_Pos                 _UINT32_(1)                                          /* (AC_STATUSB) Comparator 1 Ready Position */
+#define AC_STATUSB_READY1_Msk                 (_UINT32_(0x1) << AC_STATUSB_READY1_Pos)             /* (AC_STATUSB) Comparator 1 Ready Mask */
+#define AC_STATUSB_READY1(value)              (AC_STATUSB_READY1_Msk & (_UINT32_(value) << AC_STATUSB_READY1_Pos)) /* Assignment of value for READY1 in the AC_STATUSB register */
+#define AC_STATUSB_Msk                        _UINT32_(0x00000003)                                 /* (AC_STATUSB) Register Mask  */
+
+#define AC_STATUSB_READY_Pos                  _UINT32_(0)                                          /* (AC_STATUSB Position) Comparator x Ready */
+#define AC_STATUSB_READY_Msk                  (_UINT32_(0x3) << AC_STATUSB_READY_Pos)              /* (AC_STATUSB Mask) READY */
+#define AC_STATUSB_READY(value)               (AC_STATUSB_READY_Msk & (_UINT32_(value) << AC_STATUSB_READY_Pos)) 
+
+/* -------- AC_DBGCTRL : (AC Offset: 0x24) (R/W 32) Debug Control -------- */
+#define AC_DBGCTRL_RESETVALUE                 _UINT32_(0x00)                                       /*  (AC_DBGCTRL) Debug Control  Reset Value */
+
+#define AC_DBGCTRL_DBGRUN_Pos                 _UINT32_(0)                                          /* (AC_DBGCTRL) Debug Run Position */
+#define AC_DBGCTRL_DBGRUN_Msk                 (_UINT32_(0x1) << AC_DBGCTRL_DBGRUN_Pos)             /* (AC_DBGCTRL) Debug Run Mask */
+#define AC_DBGCTRL_DBGRUN(value)              (AC_DBGCTRL_DBGRUN_Msk & (_UINT32_(value) << AC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the AC_DBGCTRL register */
+#define AC_DBGCTRL_Msk                        _UINT32_(0x00000001)                                 /* (AC_DBGCTRL) Register Mask  */
+
+
+/* -------- AC_SYNCBUSY : (AC Offset: 0x28) ( R/ 32) Synchronization Busy -------- */
+#define AC_SYNCBUSY_RESETVALUE                _UINT32_(0x00)                                       /*  (AC_SYNCBUSY) Synchronization Busy  Reset Value */
+
+#define AC_SYNCBUSY_SWRST_Pos                 _UINT32_(0)                                          /* (AC_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define AC_SYNCBUSY_SWRST_Msk                 (_UINT32_(0x1) << AC_SYNCBUSY_SWRST_Pos)             /* (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define AC_SYNCBUSY_SWRST(value)              (AC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << AC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the AC_SYNCBUSY register */
+#define AC_SYNCBUSY_ENABLE_Pos                _UINT32_(1)                                          /* (AC_SYNCBUSY) Enable Synchronization Busy Position */
+#define AC_SYNCBUSY_ENABLE_Msk                (_UINT32_(0x1) << AC_SYNCBUSY_ENABLE_Pos)            /* (AC_SYNCBUSY) Enable Synchronization Busy Mask */
+#define AC_SYNCBUSY_ENABLE(value)             (AC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << AC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the AC_SYNCBUSY register */
+#define AC_SYNCBUSY_COMPCTRL0_Pos             _UINT32_(2)                                          /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */
+#define AC_SYNCBUSY_COMPCTRL0_Msk             (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos)         /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */
+#define AC_SYNCBUSY_COMPCTRL0(value)          (AC_SYNCBUSY_COMPCTRL0_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL0_Pos)) /* Assignment of value for COMPCTRL0 in the AC_SYNCBUSY register */
+#define AC_SYNCBUSY_COMPCTRL1_Pos             _UINT32_(3)                                          /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */
+#define AC_SYNCBUSY_COMPCTRL1_Msk             (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos)         /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */
+#define AC_SYNCBUSY_COMPCTRL1(value)          (AC_SYNCBUSY_COMPCTRL1_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL1_Pos)) /* Assignment of value for COMPCTRL1 in the AC_SYNCBUSY register */
+#define AC_SYNCBUSY_WINCTRL0_Pos              _UINT32_(10)                                         /* (AC_SYNCBUSY) WINCTRL 0 Synchronization Busy Position */
+#define AC_SYNCBUSY_WINCTRL0_Msk              (_UINT32_(0x1) << AC_SYNCBUSY_WINCTRL0_Pos)          /* (AC_SYNCBUSY) WINCTRL 0 Synchronization Busy Mask */
+#define AC_SYNCBUSY_WINCTRL0(value)           (AC_SYNCBUSY_WINCTRL0_Msk & (_UINT32_(value) << AC_SYNCBUSY_WINCTRL0_Pos)) /* Assignment of value for WINCTRL0 in the AC_SYNCBUSY register */
+#define AC_SYNCBUSY_Msk                       _UINT32_(0x0000040F)                                 /* (AC_SYNCBUSY) Register Mask  */
+
+#define AC_SYNCBUSY_COMPCTRL_Pos              _UINT32_(2)                                          /* (AC_SYNCBUSY Position) COMPCTRL x Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL_Msk              (_UINT32_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)          /* (AC_SYNCBUSY Mask) COMPCTRL */
+#define AC_SYNCBUSY_COMPCTRL(value)           (AC_SYNCBUSY_COMPCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL_Pos)) 
+#define AC_SYNCBUSY_WINCTRL_Pos               _UINT32_(10)                                         /* (AC_SYNCBUSY Position) WINCTRL x Synchronization Busy */
+#define AC_SYNCBUSY_WINCTRL_Msk               (_UINT32_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)           /* (AC_SYNCBUSY Mask) WINCTRL */
+#define AC_SYNCBUSY_WINCTRL(value)            (AC_SYNCBUSY_WINCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_WINCTRL_Pos)) 
+
+/* AC register offsets definitions */
+#define AC_COMPCTRL_REG_OFST           _UINT32_(0x00)      /* (AC_COMPCTRL) Pair n Comparator Control 0 Offset */
+#define AC_COMPCTRL0_REG_OFST          _UINT32_(0x00)      /* (AC_COMPCTRL0) Pair n Comparator Control 0 Offset */
+#define AC_COMPCTRL1_REG_OFST          _UINT32_(0x04)      /* (AC_COMPCTRL1) Pair n Comparator Control 0 Offset */
+#define AC_DACCTRL_REG_OFST            _UINT32_(0x08)      /* (AC_DACCTRL) Dac n Control Offset */
+#define AC_WINCTRL_REG_OFST            _UINT32_(0x0C)      /* (AC_WINCTRL) Window Monitor  n Control Offset */
+#define AC_CTRLA_REG_OFST              _UINT32_(0x00)      /* (AC_CTRLA) Control A Offset */
+#define AC_CTRLB_REG_OFST              _UINT32_(0x04)      /* (AC_CTRLB) Control B Offset */
+#define AC_CTRLC_REG_OFST              _UINT32_(0x08)      /* (AC_CTRLC) Control C Offset */
+#define AC_EVCTRL_REG_OFST             _UINT32_(0x0C)      /* (AC_EVCTRL) Event Control Offset */
+#define AC_INTENCLR_REG_OFST           _UINT32_(0x10)      /* (AC_INTENCLR) Interrupt Enable Clear Offset */
+#define AC_INTENSET_REG_OFST           _UINT32_(0x14)      /* (AC_INTENSET) Interrupt Enable Set Offset */
+#define AC_INTFLAG_REG_OFST            _UINT32_(0x18)      /* (AC_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define AC_STATUSA_REG_OFST            _UINT32_(0x1C)      /* (AC_STATUSA) Status A Offset */
+#define AC_STATUSB_REG_OFST            _UINT32_(0x20)      /* (AC_STATUSB) Status B Offset */
+#define AC_DBGCTRL_REG_OFST            _UINT32_(0x24)      /* (AC_DBGCTRL) Debug Control Offset */
+#define AC_SYNCBUSY_REG_OFST           _UINT32_(0x28)      /* (AC_SYNCBUSY) Synchronization Busy Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* CHANNEL register API structure */
+typedef struct
+{
+  __IO  uint32_t                       AC_COMPCTRL[2];     /* Offset: 0x00 (R/W  32) Pair n Comparator Control 0 */
+  __IO  uint32_t                       AC_DACCTRL;         /* Offset: 0x08 (R/W  32) Dac n Control */
+  __IO  uint32_t                       AC_WINCTRL;         /* Offset: 0x0C (R/W  32) Window Monitor  n Control */
+} ac_channel_registers_t;
+
+#define AC_CHANNEL_NUMBER 1
+
+/* AC register API structure */
+typedef struct
+{  /* Analog Comparator Controller */
+  __IO  uint32_t                       AC_CTRLA;           /* Offset: 0x00 (R/W  32) Control A */
+  __IO  uint32_t                       AC_CTRLB;           /* Offset: 0x04 (R/W  32) Control B */
+  __IO  uint32_t                       AC_CTRLC;           /* Offset: 0x08 (R/W  32) Control C */
+  __IO  uint32_t                       AC_EVCTRL;          /* Offset: 0x0C (R/W  32) Event Control */
+  __IO  uint32_t                       AC_INTENCLR;        /* Offset: 0x10 (R/W  32) Interrupt Enable Clear */
+  __IO  uint32_t                       AC_INTENSET;        /* Offset: 0x14 (R/W  32) Interrupt Enable Set */
+  __IO  uint32_t                       AC_INTFLAG;         /* Offset: 0x18 (R/W  32) Interrupt Flag Status and Clear */
+  __I   uint32_t                       AC_STATUSA;         /* Offset: 0x1C (R/   32) Status A */
+  __I   uint32_t                       AC_STATUSB;         /* Offset: 0x20 (R/   32) Status B */
+  __IO  uint32_t                       AC_DBGCTRL;         /* Offset: 0x24 (R/W  32) Debug Control */
+  __I   uint32_t                       AC_SYNCBUSY;        /* Offset: 0x28 (R/   32) Synchronization Busy */
+  __I   uint8_t                        Reserved1[0x04];
+        ac_channel_registers_t         CHANNEL[AC_CHANNEL_NUMBER]; /* Offset: 0x30  */
+} ac_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_AC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/adc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/adc.h
new file mode 100644
index 00000000..dfc18a29
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/adc.h
@@ -0,0 +1,1457 @@
+/*
+ * Component description for ADC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_ADC_COMPONENT_H_
+#define _PIC32CMGC00_ADC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR ADC                       */
+/* ************************************************************************** */
+
+/* -------- ADC_CORCTRL : (ADC Offset: 0x00) (R/W 32) SARCORE Control -------- */
+#define ADC_CORCTRL_RESETVALUE                _UINT32_(0xC00)                                      /*  (ADC_CORCTRL) SARCORE Control  Reset Value */
+
+#define ADC_CORCTRL_SAMC_Pos                  _UINT32_(0)                                          /* (ADC_CORCTRL) Sample Count Position */
+#define ADC_CORCTRL_SAMC_Msk                  (_UINT32_(0x3FF) << ADC_CORCTRL_SAMC_Pos)            /* (ADC_CORCTRL) Sample Count Mask */
+#define ADC_CORCTRL_SAMC(value)               (ADC_CORCTRL_SAMC_Msk & (_UINT32_(value) << ADC_CORCTRL_SAMC_Pos)) /* Assignment of value for SAMC in the ADC_CORCTRL register */
+#define ADC_CORCTRL_SELRES_Pos                _UINT32_(10)                                         /* (ADC_CORCTRL) Selects Resolution Position */
+#define ADC_CORCTRL_SELRES_Msk                (_UINT32_(0x3) << ADC_CORCTRL_SELRES_Pos)            /* (ADC_CORCTRL) Selects Resolution Mask */
+#define ADC_CORCTRL_SELRES(value)             (ADC_CORCTRL_SELRES_Msk & (_UINT32_(value) << ADC_CORCTRL_SELRES_Pos)) /* Assignment of value for SELRES in the ADC_CORCTRL register */
+#define   ADC_CORCTRL_SELRES_6_BITS_Val       _UINT32_(0x0)                                        /* (ADC_CORCTRL) 6 bits  */
+#define   ADC_CORCTRL_SELRES_8_BITS_Val       _UINT32_(0x1)                                        /* (ADC_CORCTRL) 8 bits  */
+#define   ADC_CORCTRL_SELRES_10_BITS_Val      _UINT32_(0x2)                                        /* (ADC_CORCTRL) 10 bits  */
+#define   ADC_CORCTRL_SELRES_12_BITS_Val      _UINT32_(0x3)                                        /* (ADC_CORCTRL) 12 bits (power-on default)  */
+#define ADC_CORCTRL_SELRES_6_BITS             (ADC_CORCTRL_SELRES_6_BITS_Val << ADC_CORCTRL_SELRES_Pos) /* (ADC_CORCTRL) 6 bits Position */
+#define ADC_CORCTRL_SELRES_8_BITS             (ADC_CORCTRL_SELRES_8_BITS_Val << ADC_CORCTRL_SELRES_Pos) /* (ADC_CORCTRL) 8 bits Position */
+#define ADC_CORCTRL_SELRES_10_BITS            (ADC_CORCTRL_SELRES_10_BITS_Val << ADC_CORCTRL_SELRES_Pos) /* (ADC_CORCTRL) 10 bits Position */
+#define ADC_CORCTRL_SELRES_12_BITS            (ADC_CORCTRL_SELRES_12_BITS_Val << ADC_CORCTRL_SELRES_Pos) /* (ADC_CORCTRL) 12 bits (power-on default) Position */
+#define ADC_CORCTRL_EIS_Pos                   _UINT32_(12)                                         /* (ADC_CORCTRL) Early Interrupt Select Position */
+#define ADC_CORCTRL_EIS_Msk                   (_UINT32_(0x7) << ADC_CORCTRL_EIS_Pos)               /* (ADC_CORCTRL) Early Interrupt Select Mask */
+#define ADC_CORCTRL_EIS(value)                (ADC_CORCTRL_EIS_Msk & (_UINT32_(value) << ADC_CORCTRL_EIS_Pos)) /* Assignment of value for EIS in the ADC_CORCTRL register */
+#define ADC_CORCTRL_EIRQOVR_Pos               _UINT32_(15)                                         /* (ADC_CORCTRL) Interrupt Type Select Position */
+#define ADC_CORCTRL_EIRQOVR_Msk               (_UINT32_(0x1) << ADC_CORCTRL_EIRQOVR_Pos)           /* (ADC_CORCTRL) Interrupt Type Select Mask */
+#define ADC_CORCTRL_EIRQOVR(value)            (ADC_CORCTRL_EIRQOVR_Msk & (_UINT32_(value) << ADC_CORCTRL_EIRQOVR_Pos)) /* Assignment of value for EIRQOVR in the ADC_CORCTRL register */
+#define ADC_CORCTRL_STRGSRC_Pos               _UINT32_(16)                                         /* (ADC_CORCTRL) SCAN trigger source selection Position */
+#define ADC_CORCTRL_STRGSRC_Msk               (_UINT32_(0xF) << ADC_CORCTRL_STRGSRC_Pos)           /* (ADC_CORCTRL) SCAN trigger source selection Mask */
+#define ADC_CORCTRL_STRGSRC(value)            (ADC_CORCTRL_STRGSRC_Msk & (_UINT32_(value) << ADC_CORCTRL_STRGSRC_Pos)) /* Assignment of value for STRGSRC in the ADC_CORCTRL register */
+#define   ADC_CORCTRL_STRGSRC_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CORCTRL) No Trigger (NOP)  */
+#define   ADC_CORCTRL_STRGSRC_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CORCTRL) Global Software Trigger  */
+#define   ADC_CORCTRL_STRGSRC_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CORCTRL) Global Level Software Trigger  */
+#define   ADC_CORCTRL_STRGSRC_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CORCTRL) Synchronous Trigger (STRIG)  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CORCTRL) ADC Trigger Event User 0  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CORCTRL) ADC Trigger Event User 1  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CORCTRL) ADC Trigger Event User 2  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CORCTRL) ADC Trigger Event User 3  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CORCTRL) ADC Trigger Event User 4  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CORCTRL) ADC Trigger Event User 5  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CORCTRL) ADC Trigger Event User 6  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CORCTRL) ADC Trigger Event User 7  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CORCTRL) ADC Trigger Event User 8  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CORCTRL) ADC Trigger Event User 9  */
+#define   ADC_CORCTRL_STRGSRC_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CORCTRL) ADC Trigger Event User 10  */
+#define ADC_CORCTRL_STRGSRC_NO_TRIGGER        (ADC_CORCTRL_STRGSRC_NO_TRIGGER_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) No Trigger (NOP) Position */
+#define ADC_CORCTRL_STRGSRC_GLOBAL_SOFTWARE_TRIGGER (ADC_CORCTRL_STRGSRC_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) Global Software Trigger Position */
+#define ADC_CORCTRL_STRGSRC_GLOBAL_LEVEL_TRIGGER (ADC_CORCTRL_STRGSRC_GLOBAL_LEVEL_TRIGGER_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) Global Level Software Trigger Position */
+#define ADC_CORCTRL_STRGSRC_SYNC_TRIGGER      (ADC_CORCTRL_STRGSRC_SYNC_TRIGGER_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) Synchronous Trigger (STRIG) Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER0       (ADC_CORCTRL_STRGSRC_EVENT_USER0_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 0 Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER1       (ADC_CORCTRL_STRGSRC_EVENT_USER1_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 1 Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER2       (ADC_CORCTRL_STRGSRC_EVENT_USER2_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 2 Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER3       (ADC_CORCTRL_STRGSRC_EVENT_USER3_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 3 Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER4       (ADC_CORCTRL_STRGSRC_EVENT_USER4_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 4 Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER5       (ADC_CORCTRL_STRGSRC_EVENT_USER5_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 5 Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER6       (ADC_CORCTRL_STRGSRC_EVENT_USER6_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 6 Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER7       (ADC_CORCTRL_STRGSRC_EVENT_USER7_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 7 Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER8       (ADC_CORCTRL_STRGSRC_EVENT_USER8_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 8 Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER9       (ADC_CORCTRL_STRGSRC_EVENT_USER9_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 9 Position */
+#define ADC_CORCTRL_STRGSRC_EVENT_USER10      (ADC_CORCTRL_STRGSRC_EVENT_USER10_Val << ADC_CORCTRL_STRGSRC_Pos) /* (ADC_CORCTRL) ADC Trigger Event User 10 Position */
+#define ADC_CORCTRL_STRGLVL_Pos               _UINT32_(21)                                         /* (ADC_CORCTRL) Scan Trigger Level Sensitivity Position */
+#define ADC_CORCTRL_STRGLVL_Msk               (_UINT32_(0x1) << ADC_CORCTRL_STRGLVL_Pos)           /* (ADC_CORCTRL) Scan Trigger Level Sensitivity Mask */
+#define ADC_CORCTRL_STRGLVL(value)            (ADC_CORCTRL_STRGLVL_Msk & (_UINT32_(value) << ADC_CORCTRL_STRGLVL_Pos)) /* Assignment of value for STRGLVL in the ADC_CORCTRL register */
+#define ADC_CORCTRL_SCNRTDS_Pos               _UINT32_(22)                                         /* (ADC_CORCTRL) SCAN Re-trigger Disable Position */
+#define ADC_CORCTRL_SCNRTDS_Msk               (_UINT32_(0x1) << ADC_CORCTRL_SCNRTDS_Pos)           /* (ADC_CORCTRL) SCAN Re-trigger Disable Mask */
+#define ADC_CORCTRL_SCNRTDS(value)            (ADC_CORCTRL_SCNRTDS_Msk & (_UINT32_(value) << ADC_CORCTRL_SCNRTDS_Pos)) /* Assignment of value for SCNRTDS in the ADC_CORCTRL register */
+#define ADC_CORCTRL_ADCDIV_Pos                _UINT32_(24)                                         /* (ADC_CORCTRL) Division Ratio for SARCORE clock Position */
+#define ADC_CORCTRL_ADCDIV_Msk                (_UINT32_(0x7F) << ADC_CORCTRL_ADCDIV_Pos)           /* (ADC_CORCTRL) Division Ratio for SARCORE clock Mask */
+#define ADC_CORCTRL_ADCDIV(value)             (ADC_CORCTRL_ADCDIV_Msk & (_UINT32_(value) << ADC_CORCTRL_ADCDIV_Pos)) /* Assignment of value for ADCDIV in the ADC_CORCTRL register */
+#define ADC_CORCTRL_Msk                       _UINT32_(0x7F6FFFFF)                                 /* (ADC_CORCTRL) Register Mask  */
+
+
+/* -------- ADC_CHNCFG1 : (ADC Offset: 0x04) (R/W 32) Channel Configuration 1 (LVL/CMPEN) -------- */
+#define ADC_CHNCFG1_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_CHNCFG1) Channel Configuration 1 (LVL/CMPEN)  Reset Value */
+
+#define ADC_CHNCFG1_CHNCMPEN_Pos              _UINT32_(0)                                          /* (ADC_CHNCFG1) Channel Comparator Enable Position */
+#define ADC_CHNCFG1_CHNCMPEN_Msk              (_UINT32_(0xFFFF) << ADC_CHNCFG1_CHNCMPEN_Pos)       /* (ADC_CHNCFG1) Channel Comparator Enable Mask */
+#define ADC_CHNCFG1_CHNCMPEN(value)           (ADC_CHNCFG1_CHNCMPEN_Msk & (_UINT32_(value) << ADC_CHNCFG1_CHNCMPEN_Pos)) /* Assignment of value for CHNCMPEN in the ADC_CHNCFG1 register */
+#define ADC_CHNCFG1_LVL_Pos                   _UINT32_(16)                                         /* (ADC_CHNCFG1) Channel Level Position */
+#define ADC_CHNCFG1_LVL_Msk                   (_UINT32_(0xFFFF) << ADC_CHNCFG1_LVL_Pos)            /* (ADC_CHNCFG1) Channel Level Mask */
+#define ADC_CHNCFG1_LVL(value)                (ADC_CHNCFG1_LVL_Msk & (_UINT32_(value) << ADC_CHNCFG1_LVL_Pos)) /* Assignment of value for LVL in the ADC_CHNCFG1 register */
+#define ADC_CHNCFG1_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (ADC_CHNCFG1) Register Mask  */
+
+
+/* -------- ADC_CHNCFG2 : (ADC Offset: 0x08) (R/W 32) Channel Configuration 2(FRACT/CSS) -------- */
+#define ADC_CHNCFG2_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_CHNCFG2) Channel Configuration 2(FRACT/CSS)  Reset Value */
+
+#define ADC_CHNCFG2_CSS_Pos                   _UINT32_(0)                                          /* (ADC_CHNCFG2) Channel SCAN Select Position */
+#define ADC_CHNCFG2_CSS_Msk                   (_UINT32_(0xFFFF) << ADC_CHNCFG2_CSS_Pos)            /* (ADC_CHNCFG2) Channel SCAN Select Mask */
+#define ADC_CHNCFG2_CSS(value)                (ADC_CHNCFG2_CSS_Msk & (_UINT32_(value) << ADC_CHNCFG2_CSS_Pos)) /* Assignment of value for CSS in the ADC_CHNCFG2 register */
+#define ADC_CHNCFG2_FRACT_Pos                 _UINT32_(16)                                         /* (ADC_CHNCFG2) Channel Fractional Position */
+#define ADC_CHNCFG2_FRACT_Msk                 (_UINT32_(0xFFFF) << ADC_CHNCFG2_FRACT_Pos)          /* (ADC_CHNCFG2) Channel Fractional Mask */
+#define ADC_CHNCFG2_FRACT(value)              (ADC_CHNCFG2_FRACT_Msk & (_UINT32_(value) << ADC_CHNCFG2_FRACT_Pos)) /* Assignment of value for FRACT in the ADC_CHNCFG2 register */
+#define ADC_CHNCFG2_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (ADC_CHNCFG2) Register Mask  */
+
+
+/* -------- ADC_CHNCFG3 : (ADC Offset: 0x0C) (R/W 32) Channel Configuration3 (SIGN/DIFF) -------- */
+#define ADC_CHNCFG3_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_CHNCFG3) Channel Configuration3 (SIGN/DIFF)  Reset Value */
+
+#define ADC_CHNCFG3_DIFF_Pos                  _UINT32_(0)                                          /* (ADC_CHNCFG3) Differential Mode Position */
+#define ADC_CHNCFG3_DIFF_Msk                  (_UINT32_(0xFFFF) << ADC_CHNCFG3_DIFF_Pos)           /* (ADC_CHNCFG3) Differential Mode Mask */
+#define ADC_CHNCFG3_DIFF(value)               (ADC_CHNCFG3_DIFF_Msk & (_UINT32_(value) << ADC_CHNCFG3_DIFF_Pos)) /* Assignment of value for DIFF in the ADC_CHNCFG3 register */
+#define ADC_CHNCFG3_SIGN_Pos                  _UINT32_(16)                                         /* (ADC_CHNCFG3) SIGN setting Position */
+#define ADC_CHNCFG3_SIGN_Msk                  (_UINT32_(0xFFFF) << ADC_CHNCFG3_SIGN_Pos)           /* (ADC_CHNCFG3) SIGN setting Mask */
+#define ADC_CHNCFG3_SIGN(value)               (ADC_CHNCFG3_SIGN_Msk & (_UINT32_(value) << ADC_CHNCFG3_SIGN_Pos)) /* Assignment of value for SIGN in the ADC_CHNCFG3 register */
+#define ADC_CHNCFG3_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (ADC_CHNCFG3) Register Mask  */
+
+
+/* -------- ADC_CHNCFG4 : (ADC Offset: 0x10) (R/W 32) Channel Configuration 4 (TRGSRC) -------- */
+#define ADC_CHNCFG4_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_CHNCFG4) Channel Configuration 4 (TRGSRC)  Reset Value */
+
+#define ADC_CHNCFG4_TRGSRC0_Pos               _UINT32_(0)                                          /* (ADC_CHNCFG4) Channel 0 Trigger Source Position */
+#define ADC_CHNCFG4_TRGSRC0_Msk               (_UINT32_(0xF) << ADC_CHNCFG4_TRGSRC0_Pos)           /* (ADC_CHNCFG4) Channel 0 Trigger Source Mask */
+#define ADC_CHNCFG4_TRGSRC0(value)            (ADC_CHNCFG4_TRGSRC0_Msk & (_UINT32_(value) << ADC_CHNCFG4_TRGSRC0_Pos)) /* Assignment of value for TRGSRC0 in the ADC_CHNCFG4 register */
+#define   ADC_CHNCFG4_TRGSRC0_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CHNCFG4) No Trigger (NOP)  */
+#define   ADC_CHNCFG4_TRGSRC0_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG4) Global Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC0_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG4) Global Level Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC0_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG4) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG4_TRGSRC0_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG4) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG4_TRGSRC0_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 10  */
+#define ADC_CHNCFG4_TRGSRC0_NO_TRIGGER        (ADC_CHNCFG4_TRGSRC0_NO_TRIGGER_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) No Trigger (NOP) Position */
+#define ADC_CHNCFG4_TRGSRC0_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG4_TRGSRC0_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) Global Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC0_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG4_TRGSRC0_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) Global Level Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC0_SCAN_TRIGGER      (ADC_CHNCFG4_TRGSRC0_SCAN_TRIGGER_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG4_TRGSRC0_SYNC_TRIGGER      (ADC_CHNCFG4_TRGSRC0_SYNC_TRIGGER_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER0       (ADC_CHNCFG4_TRGSRC0_EVENT_USER0_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER1       (ADC_CHNCFG4_TRGSRC0_EVENT_USER1_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER2       (ADC_CHNCFG4_TRGSRC0_EVENT_USER2_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER3       (ADC_CHNCFG4_TRGSRC0_EVENT_USER3_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER4       (ADC_CHNCFG4_TRGSRC0_EVENT_USER4_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER5       (ADC_CHNCFG4_TRGSRC0_EVENT_USER5_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER6       (ADC_CHNCFG4_TRGSRC0_EVENT_USER6_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER7       (ADC_CHNCFG4_TRGSRC0_EVENT_USER7_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER8       (ADC_CHNCFG4_TRGSRC0_EVENT_USER8_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER9       (ADC_CHNCFG4_TRGSRC0_EVENT_USER9_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG4_TRGSRC0_EVENT_USER10      (ADC_CHNCFG4_TRGSRC0_EVENT_USER10_Val << ADC_CHNCFG4_TRGSRC0_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG4_TRGSRC1_Pos               _UINT32_(4)                                          /* (ADC_CHNCFG4) Channel 1 Trigger Source Position */
+#define ADC_CHNCFG4_TRGSRC1_Msk               (_UINT32_(0xF) << ADC_CHNCFG4_TRGSRC1_Pos)           /* (ADC_CHNCFG4) Channel 1 Trigger Source Mask */
+#define ADC_CHNCFG4_TRGSRC1(value)            (ADC_CHNCFG4_TRGSRC1_Msk & (_UINT32_(value) << ADC_CHNCFG4_TRGSRC1_Pos)) /* Assignment of value for TRGSRC1 in the ADC_CHNCFG4 register */
+#define   ADC_CHNCFG4_TRGSRC1_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CHNCFG4) No Trigger (NOP)  */
+#define   ADC_CHNCFG4_TRGSRC1_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG4) Global Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC1_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG4) Global Level Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC1_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG4) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG4_TRGSRC1_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG4) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG4_TRGSRC1_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 10  */
+#define ADC_CHNCFG4_TRGSRC1_NO_TRIGGER        (ADC_CHNCFG4_TRGSRC1_NO_TRIGGER_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) No Trigger (NOP) Position */
+#define ADC_CHNCFG4_TRGSRC1_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG4_TRGSRC1_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) Global Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC1_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG4_TRGSRC1_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) Global Level Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC1_SCAN_TRIGGER      (ADC_CHNCFG4_TRGSRC1_SCAN_TRIGGER_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG4_TRGSRC1_SYNC_TRIGGER      (ADC_CHNCFG4_TRGSRC1_SYNC_TRIGGER_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER0       (ADC_CHNCFG4_TRGSRC1_EVENT_USER0_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER1       (ADC_CHNCFG4_TRGSRC1_EVENT_USER1_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER2       (ADC_CHNCFG4_TRGSRC1_EVENT_USER2_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER3       (ADC_CHNCFG4_TRGSRC1_EVENT_USER3_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER4       (ADC_CHNCFG4_TRGSRC1_EVENT_USER4_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER5       (ADC_CHNCFG4_TRGSRC1_EVENT_USER5_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER6       (ADC_CHNCFG4_TRGSRC1_EVENT_USER6_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER7       (ADC_CHNCFG4_TRGSRC1_EVENT_USER7_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER8       (ADC_CHNCFG4_TRGSRC1_EVENT_USER8_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER9       (ADC_CHNCFG4_TRGSRC1_EVENT_USER9_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG4_TRGSRC1_EVENT_USER10      (ADC_CHNCFG4_TRGSRC1_EVENT_USER10_Val << ADC_CHNCFG4_TRGSRC1_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG4_TRGSRC2_Pos               _UINT32_(8)                                          /* (ADC_CHNCFG4) Channel 2 Trigger Source Position */
+#define ADC_CHNCFG4_TRGSRC2_Msk               (_UINT32_(0xF) << ADC_CHNCFG4_TRGSRC2_Pos)           /* (ADC_CHNCFG4) Channel 2 Trigger Source Mask */
+#define ADC_CHNCFG4_TRGSRC2(value)            (ADC_CHNCFG4_TRGSRC2_Msk & (_UINT32_(value) << ADC_CHNCFG4_TRGSRC2_Pos)) /* Assignment of value for TRGSRC2 in the ADC_CHNCFG4 register */
+#define   ADC_CHNCFG4_TRGSRC2_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CHNCFG4) No Trigger (NOP)  */
+#define   ADC_CHNCFG4_TRGSRC2_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG4) Global Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC2_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG4) Global Level Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC2_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG4) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG4_TRGSRC2_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG4) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG4_TRGSRC2_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 10  */
+#define ADC_CHNCFG4_TRGSRC2_NO_TRIGGER        (ADC_CHNCFG4_TRGSRC2_NO_TRIGGER_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) No Trigger (NOP) Position */
+#define ADC_CHNCFG4_TRGSRC2_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG4_TRGSRC2_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) Global Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC2_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG4_TRGSRC2_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) Global Level Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC2_SCAN_TRIGGER      (ADC_CHNCFG4_TRGSRC2_SCAN_TRIGGER_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG4_TRGSRC2_SYNC_TRIGGER      (ADC_CHNCFG4_TRGSRC2_SYNC_TRIGGER_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER0       (ADC_CHNCFG4_TRGSRC2_EVENT_USER0_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER1       (ADC_CHNCFG4_TRGSRC2_EVENT_USER1_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER2       (ADC_CHNCFG4_TRGSRC2_EVENT_USER2_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER3       (ADC_CHNCFG4_TRGSRC2_EVENT_USER3_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER4       (ADC_CHNCFG4_TRGSRC2_EVENT_USER4_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER5       (ADC_CHNCFG4_TRGSRC2_EVENT_USER5_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER6       (ADC_CHNCFG4_TRGSRC2_EVENT_USER6_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER7       (ADC_CHNCFG4_TRGSRC2_EVENT_USER7_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER8       (ADC_CHNCFG4_TRGSRC2_EVENT_USER8_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER9       (ADC_CHNCFG4_TRGSRC2_EVENT_USER9_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG4_TRGSRC2_EVENT_USER10      (ADC_CHNCFG4_TRGSRC2_EVENT_USER10_Val << ADC_CHNCFG4_TRGSRC2_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG4_TRGSRC3_Pos               _UINT32_(12)                                         /* (ADC_CHNCFG4) Channel 3 Trigger Source Position */
+#define ADC_CHNCFG4_TRGSRC3_Msk               (_UINT32_(0xF) << ADC_CHNCFG4_TRGSRC3_Pos)           /* (ADC_CHNCFG4) Channel 3 Trigger Source Mask */
+#define ADC_CHNCFG4_TRGSRC3(value)            (ADC_CHNCFG4_TRGSRC3_Msk & (_UINT32_(value) << ADC_CHNCFG4_TRGSRC3_Pos)) /* Assignment of value for TRGSRC3 in the ADC_CHNCFG4 register */
+#define   ADC_CHNCFG4_TRGSRC3_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CHNCFG4) No Trigger (NOP)  */
+#define   ADC_CHNCFG4_TRGSRC3_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG4) Global Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC3_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG4) Global Level Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC3_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG4) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG4_TRGSRC3_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG4) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG4_TRGSRC3_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 10  */
+#define ADC_CHNCFG4_TRGSRC3_NO_TRIGGER        (ADC_CHNCFG4_TRGSRC3_NO_TRIGGER_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) No Trigger (NOP) Position */
+#define ADC_CHNCFG4_TRGSRC3_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG4_TRGSRC3_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) Global Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC3_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG4_TRGSRC3_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) Global Level Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC3_SCAN_TRIGGER      (ADC_CHNCFG4_TRGSRC3_SCAN_TRIGGER_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG4_TRGSRC3_SYNC_TRIGGER      (ADC_CHNCFG4_TRGSRC3_SYNC_TRIGGER_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER0       (ADC_CHNCFG4_TRGSRC3_EVENT_USER0_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER1       (ADC_CHNCFG4_TRGSRC3_EVENT_USER1_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER2       (ADC_CHNCFG4_TRGSRC3_EVENT_USER2_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER3       (ADC_CHNCFG4_TRGSRC3_EVENT_USER3_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER4       (ADC_CHNCFG4_TRGSRC3_EVENT_USER4_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER5       (ADC_CHNCFG4_TRGSRC3_EVENT_USER5_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER6       (ADC_CHNCFG4_TRGSRC3_EVENT_USER6_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER7       (ADC_CHNCFG4_TRGSRC3_EVENT_USER7_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER8       (ADC_CHNCFG4_TRGSRC3_EVENT_USER8_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER9       (ADC_CHNCFG4_TRGSRC3_EVENT_USER9_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG4_TRGSRC3_EVENT_USER10      (ADC_CHNCFG4_TRGSRC3_EVENT_USER10_Val << ADC_CHNCFG4_TRGSRC3_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG4_TRGSRC4_Pos               _UINT32_(16)                                         /* (ADC_CHNCFG4) Channel 4 Trigger Source Position */
+#define ADC_CHNCFG4_TRGSRC4_Msk               (_UINT32_(0xF) << ADC_CHNCFG4_TRGSRC4_Pos)           /* (ADC_CHNCFG4) Channel 4 Trigger Source Mask */
+#define ADC_CHNCFG4_TRGSRC4(value)            (ADC_CHNCFG4_TRGSRC4_Msk & (_UINT32_(value) << ADC_CHNCFG4_TRGSRC4_Pos)) /* Assignment of value for TRGSRC4 in the ADC_CHNCFG4 register */
+#define   ADC_CHNCFG4_TRGSRC4_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CHNCFG4) No Trigger (NOP)  */
+#define   ADC_CHNCFG4_TRGSRC4_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG4) Global Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC4_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG4) Global Level Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC4_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG4) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG4_TRGSRC4_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG4) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG4_TRGSRC4_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 10  */
+#define ADC_CHNCFG4_TRGSRC4_NO_TRIGGER        (ADC_CHNCFG4_TRGSRC4_NO_TRIGGER_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) No Trigger (NOP) Position */
+#define ADC_CHNCFG4_TRGSRC4_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG4_TRGSRC4_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) Global Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC4_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG4_TRGSRC4_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) Global Level Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC4_SCAN_TRIGGER      (ADC_CHNCFG4_TRGSRC4_SCAN_TRIGGER_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG4_TRGSRC4_SYNC_TRIGGER      (ADC_CHNCFG4_TRGSRC4_SYNC_TRIGGER_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER0       (ADC_CHNCFG4_TRGSRC4_EVENT_USER0_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER1       (ADC_CHNCFG4_TRGSRC4_EVENT_USER1_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER2       (ADC_CHNCFG4_TRGSRC4_EVENT_USER2_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER3       (ADC_CHNCFG4_TRGSRC4_EVENT_USER3_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER4       (ADC_CHNCFG4_TRGSRC4_EVENT_USER4_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER5       (ADC_CHNCFG4_TRGSRC4_EVENT_USER5_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER6       (ADC_CHNCFG4_TRGSRC4_EVENT_USER6_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER7       (ADC_CHNCFG4_TRGSRC4_EVENT_USER7_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER8       (ADC_CHNCFG4_TRGSRC4_EVENT_USER8_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER9       (ADC_CHNCFG4_TRGSRC4_EVENT_USER9_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG4_TRGSRC4_EVENT_USER10      (ADC_CHNCFG4_TRGSRC4_EVENT_USER10_Val << ADC_CHNCFG4_TRGSRC4_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG4_TRGSRC5_Pos               _UINT32_(20)                                         /* (ADC_CHNCFG4) Channel 5 Trigger Source Position */
+#define ADC_CHNCFG4_TRGSRC5_Msk               (_UINT32_(0xF) << ADC_CHNCFG4_TRGSRC5_Pos)           /* (ADC_CHNCFG4) Channel 5 Trigger Source Mask */
+#define ADC_CHNCFG4_TRGSRC5(value)            (ADC_CHNCFG4_TRGSRC5_Msk & (_UINT32_(value) << ADC_CHNCFG4_TRGSRC5_Pos)) /* Assignment of value for TRGSRC5 in the ADC_CHNCFG4 register */
+#define   ADC_CHNCFG4_TRGSRC5_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CHNCFG4) No Trigger (NOP)  */
+#define   ADC_CHNCFG4_TRGSRC5_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG4) Global Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC5_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG4) Global Level Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC5_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG4) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG4_TRGSRC5_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG4) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG4_TRGSRC5_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 10  */
+#define ADC_CHNCFG4_TRGSRC5_NO_TRIGGER        (ADC_CHNCFG4_TRGSRC5_NO_TRIGGER_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) No Trigger (NOP) Position */
+#define ADC_CHNCFG4_TRGSRC5_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG4_TRGSRC5_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) Global Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC5_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG4_TRGSRC5_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) Global Level Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC5_SCAN_TRIGGER      (ADC_CHNCFG4_TRGSRC5_SCAN_TRIGGER_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG4_TRGSRC5_SYNC_TRIGGER      (ADC_CHNCFG4_TRGSRC5_SYNC_TRIGGER_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER0       (ADC_CHNCFG4_TRGSRC5_EVENT_USER0_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER1       (ADC_CHNCFG4_TRGSRC5_EVENT_USER1_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER2       (ADC_CHNCFG4_TRGSRC5_EVENT_USER2_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER3       (ADC_CHNCFG4_TRGSRC5_EVENT_USER3_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER4       (ADC_CHNCFG4_TRGSRC5_EVENT_USER4_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER5       (ADC_CHNCFG4_TRGSRC5_EVENT_USER5_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER6       (ADC_CHNCFG4_TRGSRC5_EVENT_USER6_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER7       (ADC_CHNCFG4_TRGSRC5_EVENT_USER7_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER8       (ADC_CHNCFG4_TRGSRC5_EVENT_USER8_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER9       (ADC_CHNCFG4_TRGSRC5_EVENT_USER9_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG4_TRGSRC5_EVENT_USER10      (ADC_CHNCFG4_TRGSRC5_EVENT_USER10_Val << ADC_CHNCFG4_TRGSRC5_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG4_TRGSRC6_Pos               _UINT32_(24)                                         /* (ADC_CHNCFG4) Channel 6 Trigger Source Position */
+#define ADC_CHNCFG4_TRGSRC6_Msk               (_UINT32_(0xF) << ADC_CHNCFG4_TRGSRC6_Pos)           /* (ADC_CHNCFG4) Channel 6 Trigger Source Mask */
+#define ADC_CHNCFG4_TRGSRC6(value)            (ADC_CHNCFG4_TRGSRC6_Msk & (_UINT32_(value) << ADC_CHNCFG4_TRGSRC6_Pos)) /* Assignment of value for TRGSRC6 in the ADC_CHNCFG4 register */
+#define   ADC_CHNCFG4_TRGSRC6_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CHNCFG4) No Trigger (NOP)  */
+#define   ADC_CHNCFG4_TRGSRC6_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG4) Global Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC6_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG4) Global Level Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC6_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG4) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG4_TRGSRC6_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG4) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG4_TRGSRC6_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 10  */
+#define ADC_CHNCFG4_TRGSRC6_NO_TRIGGER        (ADC_CHNCFG4_TRGSRC6_NO_TRIGGER_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) No Trigger (NOP) Position */
+#define ADC_CHNCFG4_TRGSRC6_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG4_TRGSRC6_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) Global Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC6_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG4_TRGSRC6_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) Global Level Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC6_SCAN_TRIGGER      (ADC_CHNCFG4_TRGSRC6_SCAN_TRIGGER_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG4_TRGSRC6_SYNC_TRIGGER      (ADC_CHNCFG4_TRGSRC6_SYNC_TRIGGER_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER0       (ADC_CHNCFG4_TRGSRC6_EVENT_USER0_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER1       (ADC_CHNCFG4_TRGSRC6_EVENT_USER1_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER2       (ADC_CHNCFG4_TRGSRC6_EVENT_USER2_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER3       (ADC_CHNCFG4_TRGSRC6_EVENT_USER3_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER4       (ADC_CHNCFG4_TRGSRC6_EVENT_USER4_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER5       (ADC_CHNCFG4_TRGSRC6_EVENT_USER5_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER6       (ADC_CHNCFG4_TRGSRC6_EVENT_USER6_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER7       (ADC_CHNCFG4_TRGSRC6_EVENT_USER7_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER8       (ADC_CHNCFG4_TRGSRC6_EVENT_USER8_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER9       (ADC_CHNCFG4_TRGSRC6_EVENT_USER9_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG4_TRGSRC6_EVENT_USER10      (ADC_CHNCFG4_TRGSRC6_EVENT_USER10_Val << ADC_CHNCFG4_TRGSRC6_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG4_TRGSRC7_Pos               _UINT32_(28)                                         /* (ADC_CHNCFG4) Channel 7 Trigger Source Position */
+#define ADC_CHNCFG4_TRGSRC7_Msk               (_UINT32_(0xF) << ADC_CHNCFG4_TRGSRC7_Pos)           /* (ADC_CHNCFG4) Channel 7 Trigger Source Mask */
+#define ADC_CHNCFG4_TRGSRC7(value)            (ADC_CHNCFG4_TRGSRC7_Msk & (_UINT32_(value) << ADC_CHNCFG4_TRGSRC7_Pos)) /* Assignment of value for TRGSRC7 in the ADC_CHNCFG4 register */
+#define   ADC_CHNCFG4_TRGSRC7_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CHNCFG4) No Trigger (NOP)  */
+#define   ADC_CHNCFG4_TRGSRC7_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG4) Global Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC7_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG4) Global Level Software Trigger  */
+#define   ADC_CHNCFG4_TRGSRC7_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG4) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG4_TRGSRC7_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG4) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG4_TRGSRC7_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG4) ADC Trigger Event User 10  */
+#define ADC_CHNCFG4_TRGSRC7_NO_TRIGGER        (ADC_CHNCFG4_TRGSRC7_NO_TRIGGER_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) No Trigger (NOP) Position */
+#define ADC_CHNCFG4_TRGSRC7_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG4_TRGSRC7_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) Global Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC7_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG4_TRGSRC7_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) Global Level Software Trigger Position */
+#define ADC_CHNCFG4_TRGSRC7_SCAN_TRIGGER      (ADC_CHNCFG4_TRGSRC7_SCAN_TRIGGER_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG4_TRGSRC7_SYNC_TRIGGER      (ADC_CHNCFG4_TRGSRC7_SYNC_TRIGGER_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER0       (ADC_CHNCFG4_TRGSRC7_EVENT_USER0_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER1       (ADC_CHNCFG4_TRGSRC7_EVENT_USER1_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER2       (ADC_CHNCFG4_TRGSRC7_EVENT_USER2_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER3       (ADC_CHNCFG4_TRGSRC7_EVENT_USER3_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER4       (ADC_CHNCFG4_TRGSRC7_EVENT_USER4_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER5       (ADC_CHNCFG4_TRGSRC7_EVENT_USER5_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER6       (ADC_CHNCFG4_TRGSRC7_EVENT_USER6_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER7       (ADC_CHNCFG4_TRGSRC7_EVENT_USER7_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER8       (ADC_CHNCFG4_TRGSRC7_EVENT_USER8_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER9       (ADC_CHNCFG4_TRGSRC7_EVENT_USER9_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG4_TRGSRC7_EVENT_USER10      (ADC_CHNCFG4_TRGSRC7_EVENT_USER10_Val << ADC_CHNCFG4_TRGSRC7_Pos) /* (ADC_CHNCFG4) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG4_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (ADC_CHNCFG4) Register Mask  */
+
+
+/* -------- ADC_CHNCFG5 : (ADC Offset: 0x14) (R/W 32) Channel Configuration 5 (TRGSRC) -------- */
+#define ADC_CHNCFG5_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_CHNCFG5) Channel Configuration 5 (TRGSRC)  Reset Value */
+
+#define ADC_CHNCFG5_TRGSRC8_Pos               _UINT32_(0)                                          /* (ADC_CHNCFG5) Channel 8 Trigger Source Position */
+#define ADC_CHNCFG5_TRGSRC8_Msk               (_UINT32_(0xF) << ADC_CHNCFG5_TRGSRC8_Pos)           /* (ADC_CHNCFG5) Channel 8 Trigger Source Mask */
+#define ADC_CHNCFG5_TRGSRC8(value)            (ADC_CHNCFG5_TRGSRC8_Msk & (_UINT32_(value) << ADC_CHNCFG5_TRGSRC8_Pos)) /* Assignment of value for TRGSRC8 in the ADC_CHNCFG5 register */
+#define   ADC_CHNCFG5_TRGSRC8_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CHNCFG5) No Trigger (NOP)  */
+#define   ADC_CHNCFG5_TRGSRC8_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG5) Global Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC8_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG5) Global Level Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC8_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG5) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG5_TRGSRC8_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG5) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG5_TRGSRC8_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 10  */
+#define ADC_CHNCFG5_TRGSRC8_NO_TRIGGER        (ADC_CHNCFG5_TRGSRC8_NO_TRIGGER_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) No Trigger (NOP) Position */
+#define ADC_CHNCFG5_TRGSRC8_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG5_TRGSRC8_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) Global Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC8_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG5_TRGSRC8_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) Global Level Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC8_SCAN_TRIGGER      (ADC_CHNCFG5_TRGSRC8_SCAN_TRIGGER_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG5_TRGSRC8_SYNC_TRIGGER      (ADC_CHNCFG5_TRGSRC8_SYNC_TRIGGER_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER0       (ADC_CHNCFG5_TRGSRC8_EVENT_USER0_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER1       (ADC_CHNCFG5_TRGSRC8_EVENT_USER1_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER2       (ADC_CHNCFG5_TRGSRC8_EVENT_USER2_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER3       (ADC_CHNCFG5_TRGSRC8_EVENT_USER3_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER4       (ADC_CHNCFG5_TRGSRC8_EVENT_USER4_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER5       (ADC_CHNCFG5_TRGSRC8_EVENT_USER5_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER6       (ADC_CHNCFG5_TRGSRC8_EVENT_USER6_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER7       (ADC_CHNCFG5_TRGSRC8_EVENT_USER7_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER8       (ADC_CHNCFG5_TRGSRC8_EVENT_USER8_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER9       (ADC_CHNCFG5_TRGSRC8_EVENT_USER9_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG5_TRGSRC8_EVENT_USER10      (ADC_CHNCFG5_TRGSRC8_EVENT_USER10_Val << ADC_CHNCFG5_TRGSRC8_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG5_TRGSRC9_Pos               _UINT32_(4)                                          /* (ADC_CHNCFG5) Channel 9 Trigger Source Position */
+#define ADC_CHNCFG5_TRGSRC9_Msk               (_UINT32_(0xF) << ADC_CHNCFG5_TRGSRC9_Pos)           /* (ADC_CHNCFG5) Channel 9 Trigger Source Mask */
+#define ADC_CHNCFG5_TRGSRC9(value)            (ADC_CHNCFG5_TRGSRC9_Msk & (_UINT32_(value) << ADC_CHNCFG5_TRGSRC9_Pos)) /* Assignment of value for TRGSRC9 in the ADC_CHNCFG5 register */
+#define   ADC_CHNCFG5_TRGSRC9_NO_TRIGGER_Val  _UINT32_(0x0)                                        /* (ADC_CHNCFG5) No Trigger (NOP)  */
+#define   ADC_CHNCFG5_TRGSRC9_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG5) Global Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC9_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG5) Global Level Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC9_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG5) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG5_TRGSRC9_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG5) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG5_TRGSRC9_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 10  */
+#define ADC_CHNCFG5_TRGSRC9_NO_TRIGGER        (ADC_CHNCFG5_TRGSRC9_NO_TRIGGER_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) No Trigger (NOP) Position */
+#define ADC_CHNCFG5_TRGSRC9_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG5_TRGSRC9_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) Global Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC9_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG5_TRGSRC9_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) Global Level Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC9_SCAN_TRIGGER      (ADC_CHNCFG5_TRGSRC9_SCAN_TRIGGER_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG5_TRGSRC9_SYNC_TRIGGER      (ADC_CHNCFG5_TRGSRC9_SYNC_TRIGGER_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER0       (ADC_CHNCFG5_TRGSRC9_EVENT_USER0_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER1       (ADC_CHNCFG5_TRGSRC9_EVENT_USER1_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER2       (ADC_CHNCFG5_TRGSRC9_EVENT_USER2_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER3       (ADC_CHNCFG5_TRGSRC9_EVENT_USER3_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER4       (ADC_CHNCFG5_TRGSRC9_EVENT_USER4_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER5       (ADC_CHNCFG5_TRGSRC9_EVENT_USER5_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER6       (ADC_CHNCFG5_TRGSRC9_EVENT_USER6_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER7       (ADC_CHNCFG5_TRGSRC9_EVENT_USER7_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER8       (ADC_CHNCFG5_TRGSRC9_EVENT_USER8_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER9       (ADC_CHNCFG5_TRGSRC9_EVENT_USER9_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG5_TRGSRC9_EVENT_USER10      (ADC_CHNCFG5_TRGSRC9_EVENT_USER10_Val << ADC_CHNCFG5_TRGSRC9_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG5_TRGSRC10_Pos              _UINT32_(8)                                          /* (ADC_CHNCFG5) Channel 10 Trigger Source Position */
+#define ADC_CHNCFG5_TRGSRC10_Msk              (_UINT32_(0xF) << ADC_CHNCFG5_TRGSRC10_Pos)          /* (ADC_CHNCFG5) Channel 10 Trigger Source Mask */
+#define ADC_CHNCFG5_TRGSRC10(value)           (ADC_CHNCFG5_TRGSRC10_Msk & (_UINT32_(value) << ADC_CHNCFG5_TRGSRC10_Pos)) /* Assignment of value for TRGSRC10 in the ADC_CHNCFG5 register */
+#define   ADC_CHNCFG5_TRGSRC10_NO_TRIGGER_Val _UINT32_(0x0)                                        /* (ADC_CHNCFG5) No Trigger (NOP)  */
+#define   ADC_CHNCFG5_TRGSRC10_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG5) Global Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC10_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG5) Global Level Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC10_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG5) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG5_TRGSRC10_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG5) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG5_TRGSRC10_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 10  */
+#define ADC_CHNCFG5_TRGSRC10_NO_TRIGGER       (ADC_CHNCFG5_TRGSRC10_NO_TRIGGER_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) No Trigger (NOP) Position */
+#define ADC_CHNCFG5_TRGSRC10_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG5_TRGSRC10_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) Global Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC10_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG5_TRGSRC10_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) Global Level Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC10_SCAN_TRIGGER     (ADC_CHNCFG5_TRGSRC10_SCAN_TRIGGER_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG5_TRGSRC10_SYNC_TRIGGER     (ADC_CHNCFG5_TRGSRC10_SYNC_TRIGGER_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER0      (ADC_CHNCFG5_TRGSRC10_EVENT_USER0_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER1      (ADC_CHNCFG5_TRGSRC10_EVENT_USER1_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER2      (ADC_CHNCFG5_TRGSRC10_EVENT_USER2_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER3      (ADC_CHNCFG5_TRGSRC10_EVENT_USER3_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER4      (ADC_CHNCFG5_TRGSRC10_EVENT_USER4_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER5      (ADC_CHNCFG5_TRGSRC10_EVENT_USER5_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER6      (ADC_CHNCFG5_TRGSRC10_EVENT_USER6_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER7      (ADC_CHNCFG5_TRGSRC10_EVENT_USER7_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER8      (ADC_CHNCFG5_TRGSRC10_EVENT_USER8_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER9      (ADC_CHNCFG5_TRGSRC10_EVENT_USER9_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG5_TRGSRC10_EVENT_USER10     (ADC_CHNCFG5_TRGSRC10_EVENT_USER10_Val << ADC_CHNCFG5_TRGSRC10_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG5_TRGSRC11_Pos              _UINT32_(12)                                         /* (ADC_CHNCFG5) Channel 11 Trigger Source Position */
+#define ADC_CHNCFG5_TRGSRC11_Msk              (_UINT32_(0xF) << ADC_CHNCFG5_TRGSRC11_Pos)          /* (ADC_CHNCFG5) Channel 11 Trigger Source Mask */
+#define ADC_CHNCFG5_TRGSRC11(value)           (ADC_CHNCFG5_TRGSRC11_Msk & (_UINT32_(value) << ADC_CHNCFG5_TRGSRC11_Pos)) /* Assignment of value for TRGSRC11 in the ADC_CHNCFG5 register */
+#define   ADC_CHNCFG5_TRGSRC11_NO_TRIGGER_Val _UINT32_(0x0)                                        /* (ADC_CHNCFG5) No Trigger (NOP)  */
+#define   ADC_CHNCFG5_TRGSRC11_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG5) Global Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC11_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG5) Global Level Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC11_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG5) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG5_TRGSRC11_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG5) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG5_TRGSRC11_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 10  */
+#define ADC_CHNCFG5_TRGSRC11_NO_TRIGGER       (ADC_CHNCFG5_TRGSRC11_NO_TRIGGER_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) No Trigger (NOP) Position */
+#define ADC_CHNCFG5_TRGSRC11_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG5_TRGSRC11_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) Global Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC11_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG5_TRGSRC11_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) Global Level Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC11_SCAN_TRIGGER     (ADC_CHNCFG5_TRGSRC11_SCAN_TRIGGER_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG5_TRGSRC11_SYNC_TRIGGER     (ADC_CHNCFG5_TRGSRC11_SYNC_TRIGGER_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER0      (ADC_CHNCFG5_TRGSRC11_EVENT_USER0_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER1      (ADC_CHNCFG5_TRGSRC11_EVENT_USER1_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER2      (ADC_CHNCFG5_TRGSRC11_EVENT_USER2_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER3      (ADC_CHNCFG5_TRGSRC11_EVENT_USER3_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER4      (ADC_CHNCFG5_TRGSRC11_EVENT_USER4_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER5      (ADC_CHNCFG5_TRGSRC11_EVENT_USER5_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER6      (ADC_CHNCFG5_TRGSRC11_EVENT_USER6_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER7      (ADC_CHNCFG5_TRGSRC11_EVENT_USER7_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER8      (ADC_CHNCFG5_TRGSRC11_EVENT_USER8_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER9      (ADC_CHNCFG5_TRGSRC11_EVENT_USER9_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG5_TRGSRC11_EVENT_USER10     (ADC_CHNCFG5_TRGSRC11_EVENT_USER10_Val << ADC_CHNCFG5_TRGSRC11_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG5_TRGSRC12_Pos              _UINT32_(16)                                         /* (ADC_CHNCFG5) Channel 12 Trigger Source Position */
+#define ADC_CHNCFG5_TRGSRC12_Msk              (_UINT32_(0xF) << ADC_CHNCFG5_TRGSRC12_Pos)          /* (ADC_CHNCFG5) Channel 12 Trigger Source Mask */
+#define ADC_CHNCFG5_TRGSRC12(value)           (ADC_CHNCFG5_TRGSRC12_Msk & (_UINT32_(value) << ADC_CHNCFG5_TRGSRC12_Pos)) /* Assignment of value for TRGSRC12 in the ADC_CHNCFG5 register */
+#define   ADC_CHNCFG5_TRGSRC12_NO_TRIGGER_Val _UINT32_(0x0)                                        /* (ADC_CHNCFG5) No Trigger (NOP)  */
+#define   ADC_CHNCFG5_TRGSRC12_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG5) Global Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC12_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG5) Global Level Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC12_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG5) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG5_TRGSRC12_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG5) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG5_TRGSRC12_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 10  */
+#define ADC_CHNCFG5_TRGSRC12_NO_TRIGGER       (ADC_CHNCFG5_TRGSRC12_NO_TRIGGER_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) No Trigger (NOP) Position */
+#define ADC_CHNCFG5_TRGSRC12_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG5_TRGSRC12_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) Global Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC12_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG5_TRGSRC12_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) Global Level Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC12_SCAN_TRIGGER     (ADC_CHNCFG5_TRGSRC12_SCAN_TRIGGER_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG5_TRGSRC12_SYNC_TRIGGER     (ADC_CHNCFG5_TRGSRC12_SYNC_TRIGGER_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER0      (ADC_CHNCFG5_TRGSRC12_EVENT_USER0_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER1      (ADC_CHNCFG5_TRGSRC12_EVENT_USER1_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER2      (ADC_CHNCFG5_TRGSRC12_EVENT_USER2_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER3      (ADC_CHNCFG5_TRGSRC12_EVENT_USER3_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER4      (ADC_CHNCFG5_TRGSRC12_EVENT_USER4_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER5      (ADC_CHNCFG5_TRGSRC12_EVENT_USER5_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER6      (ADC_CHNCFG5_TRGSRC12_EVENT_USER6_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER7      (ADC_CHNCFG5_TRGSRC12_EVENT_USER7_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER8      (ADC_CHNCFG5_TRGSRC12_EVENT_USER8_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER9      (ADC_CHNCFG5_TRGSRC12_EVENT_USER9_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG5_TRGSRC12_EVENT_USER10     (ADC_CHNCFG5_TRGSRC12_EVENT_USER10_Val << ADC_CHNCFG5_TRGSRC12_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG5_TRGSRC13_Pos              _UINT32_(20)                                         /* (ADC_CHNCFG5) Channel 13 Trigger Source Position */
+#define ADC_CHNCFG5_TRGSRC13_Msk              (_UINT32_(0xF) << ADC_CHNCFG5_TRGSRC13_Pos)          /* (ADC_CHNCFG5) Channel 13 Trigger Source Mask */
+#define ADC_CHNCFG5_TRGSRC13(value)           (ADC_CHNCFG5_TRGSRC13_Msk & (_UINT32_(value) << ADC_CHNCFG5_TRGSRC13_Pos)) /* Assignment of value for TRGSRC13 in the ADC_CHNCFG5 register */
+#define   ADC_CHNCFG5_TRGSRC13_NO_TRIGGER_Val _UINT32_(0x0)                                        /* (ADC_CHNCFG5) No Trigger (NOP)  */
+#define   ADC_CHNCFG5_TRGSRC13_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG5) Global Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC13_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG5) Global Level Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC13_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG5) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG5_TRGSRC13_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG5) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG5_TRGSRC13_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 10  */
+#define ADC_CHNCFG5_TRGSRC13_NO_TRIGGER       (ADC_CHNCFG5_TRGSRC13_NO_TRIGGER_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) No Trigger (NOP) Position */
+#define ADC_CHNCFG5_TRGSRC13_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG5_TRGSRC13_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) Global Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC13_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG5_TRGSRC13_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) Global Level Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC13_SCAN_TRIGGER     (ADC_CHNCFG5_TRGSRC13_SCAN_TRIGGER_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG5_TRGSRC13_SYNC_TRIGGER     (ADC_CHNCFG5_TRGSRC13_SYNC_TRIGGER_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER0      (ADC_CHNCFG5_TRGSRC13_EVENT_USER0_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER1      (ADC_CHNCFG5_TRGSRC13_EVENT_USER1_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER2      (ADC_CHNCFG5_TRGSRC13_EVENT_USER2_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER3      (ADC_CHNCFG5_TRGSRC13_EVENT_USER3_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER4      (ADC_CHNCFG5_TRGSRC13_EVENT_USER4_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER5      (ADC_CHNCFG5_TRGSRC13_EVENT_USER5_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER6      (ADC_CHNCFG5_TRGSRC13_EVENT_USER6_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER7      (ADC_CHNCFG5_TRGSRC13_EVENT_USER7_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER8      (ADC_CHNCFG5_TRGSRC13_EVENT_USER8_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER9      (ADC_CHNCFG5_TRGSRC13_EVENT_USER9_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG5_TRGSRC13_EVENT_USER10     (ADC_CHNCFG5_TRGSRC13_EVENT_USER10_Val << ADC_CHNCFG5_TRGSRC13_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG5_TRGSRC14_Pos              _UINT32_(24)                                         /* (ADC_CHNCFG5) Channel 14 Trigger Source Position */
+#define ADC_CHNCFG5_TRGSRC14_Msk              (_UINT32_(0xF) << ADC_CHNCFG5_TRGSRC14_Pos)          /* (ADC_CHNCFG5) Channel 14 Trigger Source Mask */
+#define ADC_CHNCFG5_TRGSRC14(value)           (ADC_CHNCFG5_TRGSRC14_Msk & (_UINT32_(value) << ADC_CHNCFG5_TRGSRC14_Pos)) /* Assignment of value for TRGSRC14 in the ADC_CHNCFG5 register */
+#define   ADC_CHNCFG5_TRGSRC14_NO_TRIGGER_Val _UINT32_(0x0)                                        /* (ADC_CHNCFG5) No Trigger (NOP)  */
+#define   ADC_CHNCFG5_TRGSRC14_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG5) Global Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC14_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG5) Global Level Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC14_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG5) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG5_TRGSRC14_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG5) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG5_TRGSRC14_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 10  */
+#define ADC_CHNCFG5_TRGSRC14_NO_TRIGGER       (ADC_CHNCFG5_TRGSRC14_NO_TRIGGER_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) No Trigger (NOP) Position */
+#define ADC_CHNCFG5_TRGSRC14_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG5_TRGSRC14_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) Global Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC14_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG5_TRGSRC14_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) Global Level Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC14_SCAN_TRIGGER     (ADC_CHNCFG5_TRGSRC14_SCAN_TRIGGER_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG5_TRGSRC14_SYNC_TRIGGER     (ADC_CHNCFG5_TRGSRC14_SYNC_TRIGGER_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER0      (ADC_CHNCFG5_TRGSRC14_EVENT_USER0_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER1      (ADC_CHNCFG5_TRGSRC14_EVENT_USER1_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER2      (ADC_CHNCFG5_TRGSRC14_EVENT_USER2_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER3      (ADC_CHNCFG5_TRGSRC14_EVENT_USER3_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER4      (ADC_CHNCFG5_TRGSRC14_EVENT_USER4_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER5      (ADC_CHNCFG5_TRGSRC14_EVENT_USER5_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER6      (ADC_CHNCFG5_TRGSRC14_EVENT_USER6_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER7      (ADC_CHNCFG5_TRGSRC14_EVENT_USER7_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER8      (ADC_CHNCFG5_TRGSRC14_EVENT_USER8_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER9      (ADC_CHNCFG5_TRGSRC14_EVENT_USER9_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG5_TRGSRC14_EVENT_USER10     (ADC_CHNCFG5_TRGSRC14_EVENT_USER10_Val << ADC_CHNCFG5_TRGSRC14_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG5_TRGSRC15_Pos              _UINT32_(28)                                         /* (ADC_CHNCFG5) Channel 15 Trigger Source Position */
+#define ADC_CHNCFG5_TRGSRC15_Msk              (_UINT32_(0xF) << ADC_CHNCFG5_TRGSRC15_Pos)          /* (ADC_CHNCFG5) Channel 15 Trigger Source Mask */
+#define ADC_CHNCFG5_TRGSRC15(value)           (ADC_CHNCFG5_TRGSRC15_Msk & (_UINT32_(value) << ADC_CHNCFG5_TRGSRC15_Pos)) /* Assignment of value for TRGSRC15 in the ADC_CHNCFG5 register */
+#define   ADC_CHNCFG5_TRGSRC15_NO_TRIGGER_Val _UINT32_(0x0)                                        /* (ADC_CHNCFG5) No Trigger (NOP)  */
+#define   ADC_CHNCFG5_TRGSRC15_GLOBAL_SOFTWARE_TRIGGER_Val _UINT32_(0x1)                                        /* (ADC_CHNCFG5) Global Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC15_GLOBAL_LEVEL_TRIGGER_Val _UINT32_(0x2)                                        /* (ADC_CHNCFG5) Global Level Software Trigger  */
+#define   ADC_CHNCFG5_TRGSRC15_SCAN_TRIGGER_Val _UINT32_(0x3)                                        /* (ADC_CHNCFG5) SCANTRG - Scan Trigger  */
+#define   ADC_CHNCFG5_TRGSRC15_SYNC_TRIGGER_Val _UINT32_(0x4)                                        /* (ADC_CHNCFG5) Synchronous Trigger (STRIG)  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER0_Val _UINT32_(0x5)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 0  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER1_Val _UINT32_(0x6)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 1  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER2_Val _UINT32_(0x7)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 2  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER3_Val _UINT32_(0x8)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 3  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER4_Val _UINT32_(0x9)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 4  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER5_Val _UINT32_(0xA)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 5  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER6_Val _UINT32_(0xB)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 6  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER7_Val _UINT32_(0xC)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 7  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER8_Val _UINT32_(0xD)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 8  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER9_Val _UINT32_(0xE)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 9  */
+#define   ADC_CHNCFG5_TRGSRC15_EVENT_USER10_Val _UINT32_(0xF)                                        /* (ADC_CHNCFG5) ADC Trigger Event User 10  */
+#define ADC_CHNCFG5_TRGSRC15_NO_TRIGGER       (ADC_CHNCFG5_TRGSRC15_NO_TRIGGER_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) No Trigger (NOP) Position */
+#define ADC_CHNCFG5_TRGSRC15_GLOBAL_SOFTWARE_TRIGGER (ADC_CHNCFG5_TRGSRC15_GLOBAL_SOFTWARE_TRIGGER_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) Global Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC15_GLOBAL_LEVEL_TRIGGER (ADC_CHNCFG5_TRGSRC15_GLOBAL_LEVEL_TRIGGER_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) Global Level Software Trigger Position */
+#define ADC_CHNCFG5_TRGSRC15_SCAN_TRIGGER     (ADC_CHNCFG5_TRGSRC15_SCAN_TRIGGER_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) SCANTRG - Scan Trigger Position */
+#define ADC_CHNCFG5_TRGSRC15_SYNC_TRIGGER     (ADC_CHNCFG5_TRGSRC15_SYNC_TRIGGER_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) Synchronous Trigger (STRIG) Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER0      (ADC_CHNCFG5_TRGSRC15_EVENT_USER0_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 0 Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER1      (ADC_CHNCFG5_TRGSRC15_EVENT_USER1_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 1 Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER2      (ADC_CHNCFG5_TRGSRC15_EVENT_USER2_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 2 Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER3      (ADC_CHNCFG5_TRGSRC15_EVENT_USER3_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 3 Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER4      (ADC_CHNCFG5_TRGSRC15_EVENT_USER4_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 4 Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER5      (ADC_CHNCFG5_TRGSRC15_EVENT_USER5_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 5 Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER6      (ADC_CHNCFG5_TRGSRC15_EVENT_USER6_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 6 Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER7      (ADC_CHNCFG5_TRGSRC15_EVENT_USER7_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 7 Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER8      (ADC_CHNCFG5_TRGSRC15_EVENT_USER8_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 8 Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER9      (ADC_CHNCFG5_TRGSRC15_EVENT_USER9_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 9 Position */
+#define ADC_CHNCFG5_TRGSRC15_EVENT_USER10     (ADC_CHNCFG5_TRGSRC15_EVENT_USER10_Val << ADC_CHNCFG5_TRGSRC15_Pos) /* (ADC_CHNCFG5) ADC Trigger Event User 10 Position */
+#define ADC_CHNCFG5_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (ADC_CHNCFG5) Register Mask  */
+
+
+/* -------- ADC_CALCTRL : (ADC Offset: 0x18) (R/W 32) SARCORE Calibration Value -------- */
+#define ADC_CALCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_CALCTRL) SARCORE Calibration Value  Reset Value */
+
+#define ADC_CALCTRL_CALBITS_Pos               _UINT32_(0)                                          /* (ADC_CALCTRL) Calibration Values Position */
+#define ADC_CALCTRL_CALBITS_Msk               (_UINT32_(0xFFFFFFFF) << ADC_CALCTRL_CALBITS_Pos)    /* (ADC_CALCTRL) Calibration Values Mask */
+#define ADC_CALCTRL_CALBITS(value)            (ADC_CALCTRL_CALBITS_Msk & (_UINT32_(value) << ADC_CALCTRL_CALBITS_Pos)) /* Assignment of value for CALBITS in the ADC_CALCTRL register */
+#define ADC_CALCTRL_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (ADC_CALCTRL) Register Mask  */
+
+/* FUSES_ADC_SARCORE_12BIT_V7A0 mode */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_cmbf_Pos _UINT32_(0)                                          /* (ADC_CALCTRL) Enable Common Mode Buffer Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_cmbf_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_cmbf_Pos) /* (ADC_CALCTRL) Enable Common Mode Buffer Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_cmbf(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_cmbf_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_cmbf_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_dither_Pos _UINT32_(2)                                          /* (ADC_CALCTRL) Enable Dither Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_dither_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_dither_Pos) /* (ADC_CALCTRL) Enable Dither Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_dither(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_dither_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_dither_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_faz_Pos _UINT32_(3)                                          /* (ADC_CALCTRL) Disable auto-zeroing Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_faz_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_faz_Pos) /* (ADC_CALCTRL) Disable auto-zeroing Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_faz(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_faz_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_faz_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_saz_Pos _UINT32_(4)                                          /* (ADC_CALCTRL) Disable auto-zeroing Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_saz_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_saz_Pos) /* (ADC_CALCTRL) Disable auto-zeroing Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_saz(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_saz_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_saz_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_laz_Pos _UINT32_(5)                                          /* (ADC_CALCTRL) Disable auto-zeroing Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_laz_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_laz_Pos) /* (ADC_CALCTRL) Disable auto-zeroing Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_laz(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_laz_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dis_laz_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_rdac_Pos _UINT32_(6)                                          /* (ADC_CALCTRL) Disable Power Cycling Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_rdac_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_rdac_Pos) /* (ADC_CALCTRL) Disable Power Cycling Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_rdac(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_rdac_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_rdac_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dbg_sel_Pos _UINT32_(7)                                          /* (ADC_CALCTRL) Debug Bus Select Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dbg_sel_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dbg_sel_Pos) /* (ADC_CALCTRL) Debug Bus Select Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dbg_sel(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dbg_sel_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_dbg_sel_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_sel_del_Pos _UINT32_(8)                                          /* (ADC_CALCTRL) Scan Mode comp_out Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_sel_del_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_sel_del_Pos) /* (ADC_CALCTRL) Scan Mode comp_out Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_sel_del(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_sel_del_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_sel_del_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_t1_dly_Pos _UINT32_(9)                                          /* (ADC_CALCTRL) Regen Latch Delay Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_t1_dly_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_t1_dly_Pos) /* (ADC_CALCTRL) Regen Latch Delay Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_t1_dly(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_t1_dly_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_t1_dly_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_tclk_div_Pos _UINT32_(11)                                         /* (ADC_CALCTRL) Test Clock Divider Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_tclk_div_Msk (_UINT32_(0x1F) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_tclk_div_Pos) /* (ADC_CALCTRL) Test Clock Divider Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_tclk_div(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_tclk_div_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_tclk_div_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_1_Pos _UINT32_(20)                                         /* (ADC_CALCTRL) Current Consumption 1 Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_1_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_1_Pos) /* (ADC_CALCTRL) Current Consumption 1 Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_1(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_1_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_1_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_2_Pos _UINT32_(22)                                         /* (ADC_CALCTRL) Current Consumption 2 Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_2_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_2_Pos) /* (ADC_CALCTRL) Current Consumption 2 Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_2(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_2_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_iadc_2_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_1_Pos _UINT32_(24)                                         /* (ADC_CALCTRL) Bias Current Stage 1 Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_1_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_1_Pos) /* (ADC_CALCTRL) Bias Current Stage 1 Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_1(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_1_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_1_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_2_Pos _UINT32_(26)                                         /* (ADC_CALCTRL) Bias Current Stage 2 Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_2_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_2_Pos) /* (ADC_CALCTRL) Bias Current Stage 2 Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_2(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_2_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmp_2_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmbf_Pos _UINT32_(28)                                         /* (ADC_CALCTRL) Bias Current Common Mode Buffer Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmbf_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmbf_Pos) /* (ADC_CALCTRL) Bias Current Common Mode Buffer Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmbf(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmbf_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_icmbf_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_ext_bias_Pos _UINT32_(31)                                         /* (ADC_CALCTRL) Dsiable Internal Bias Circuit Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_ext_bias_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_ext_bias_Pos) /* (ADC_CALCTRL) Dsiable Internal Bias Circuit Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_ext_bias(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_ext_bias_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_en_ext_bias_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_Msk _UINT32_(0xBFF0FFFD)                                 /* (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0) Register Mask  */
+
+/* FUSES_ADC_SARCORE_12BIT_V7C0 mode */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_cmbf_Pos _UINT32_(0)                                          /* (ADC_CALCTRL) Enable Common Mode Buffer Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_cmbf_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_cmbf_Pos) /* (ADC_CALCTRL) Enable Common Mode Buffer Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_cmbf(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_cmbf_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_cmbf_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_dither_Pos _UINT32_(2)                                          /* (ADC_CALCTRL) Enable Dither Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_dither_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_dither_Pos) /* (ADC_CALCTRL) Enable Dither Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_dither(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_dither_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_dither_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_faz_Pos _UINT32_(3)                                          /* (ADC_CALCTRL) Disable auto-zeroing Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_faz_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_faz_Pos) /* (ADC_CALCTRL) Disable auto-zeroing Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_faz(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_faz_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_faz_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_saz_Pos _UINT32_(4)                                          /* (ADC_CALCTRL) Disable auto-zeroing Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_saz_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_saz_Pos) /* (ADC_CALCTRL) Disable auto-zeroing Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_saz(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_saz_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_saz_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_laz_Pos _UINT32_(5)                                          /* (ADC_CALCTRL) Disable auto-zeroing Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_laz_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_laz_Pos) /* (ADC_CALCTRL) Disable auto-zeroing Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_laz(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_laz_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dis_laz_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_rdac_Pos _UINT32_(6)                                          /* (ADC_CALCTRL) Disable Power Cycling Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_rdac_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_rdac_Pos) /* (ADC_CALCTRL) Disable Power Cycling Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_rdac(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_rdac_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_rdac_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dbg_sel_Pos _UINT32_(7)                                          /* (ADC_CALCTRL) Debug Bus Select Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dbg_sel_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dbg_sel_Pos) /* (ADC_CALCTRL) Debug Bus Select Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dbg_sel(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dbg_sel_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_dbg_sel_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_sel_del_Pos _UINT32_(8)                                          /* (ADC_CALCTRL) Scan Mode comp_out Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_sel_del_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_sel_del_Pos) /* (ADC_CALCTRL) Scan Mode comp_out Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_sel_del(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_sel_del_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_sel_del_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_t1_dly_Pos _UINT32_(9)                                          /* (ADC_CALCTRL) Regen Latch Delay Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_t1_dly_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_t1_dly_Pos) /* (ADC_CALCTRL) Regen Latch Delay Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_t1_dly(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_t1_dly_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_t1_dly_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_tclk_div_Pos _UINT32_(11)                                         /* (ADC_CALCTRL) Test Clock Divider Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_tclk_div_Msk (_UINT32_(0x1F) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_tclk_div_Pos) /* (ADC_CALCTRL) Test Clock Divider Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_tclk_div(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_tclk_div_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_tclk_div_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_1_Pos _UINT32_(20)                                         /* (ADC_CALCTRL) Current Consumption 1 Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_1_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_1_Pos) /* (ADC_CALCTRL) Current Consumption 1 Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_1(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_1_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_1_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_2_Pos _UINT32_(22)                                         /* (ADC_CALCTRL) Current Consumption 2 Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_2_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_2_Pos) /* (ADC_CALCTRL) Current Consumption 2 Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_2(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_2_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_iadc_2_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_1_Pos _UINT32_(24)                                         /* (ADC_CALCTRL) Bias Current Stage 1 Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_1_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_1_Pos) /* (ADC_CALCTRL) Bias Current Stage 1 Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_1(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_1_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_1_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_2_Pos _UINT32_(26)                                         /* (ADC_CALCTRL) Bias Current Stage 2 Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_2_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_2_Pos) /* (ADC_CALCTRL) Bias Current Stage 2 Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_2(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_2_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmp_2_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmbf_Pos _UINT32_(28)                                         /* (ADC_CALCTRL) Bias Current Common Mode Buffer Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmbf_Msk (_UINT32_(0x3) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmbf_Pos) /* (ADC_CALCTRL) Bias Current Common Mode Buffer Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmbf(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmbf_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_icmbf_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_ext_bias_Pos _UINT32_(31)                                         /* (ADC_CALCTRL) Dsiable Internal Bias Circuit Position */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_ext_bias_Msk (_UINT32_(0x1) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_ext_bias_Pos) /* (ADC_CALCTRL) Dsiable Internal Bias Circuit Mask */
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_ext_bias(value) (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_ext_bias_Msk & (_UINT32_(value) << ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_en_ext_bias_Pos))
+#define ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_Msk _UINT32_(0xBFF0FFFD)                                 /* (ADC_CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0) Register Mask  */
+
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x1C) (R/W 32) Event Control -------- */
+#define ADC_EVCTRL_RESETVALUE                 _UINT32_(0x00)                                       /*  (ADC_EVCTRL) Event Control  Reset Value */
+
+#define ADC_EVCTRL_STARTEI_Pos                _UINT32_(0)                                          /* (ADC_EVCTRL) Start Event conversion input enable Position */
+#define ADC_EVCTRL_STARTEI_Msk                (_UINT32_(0x1) << ADC_EVCTRL_STARTEI_Pos)            /* (ADC_EVCTRL) Start Event conversion input enable Mask */
+#define ADC_EVCTRL_STARTEI(value)             (ADC_EVCTRL_STARTEI_Msk & (_UINT32_(value) << ADC_EVCTRL_STARTEI_Pos)) /* Assignment of value for STARTEI in the ADC_EVCTRL register */
+#define ADC_EVCTRL_STARTINV_Pos               _UINT32_(3)                                          /* (ADC_EVCTRL) Start Conversion Invert Position */
+#define ADC_EVCTRL_STARTINV_Msk               (_UINT32_(0x1) << ADC_EVCTRL_STARTINV_Pos)           /* (ADC_EVCTRL) Start Conversion Invert Mask */
+#define ADC_EVCTRL_STARTINV(value)            (ADC_EVCTRL_STARTINV_Msk & (_UINT32_(value) << ADC_EVCTRL_STARTINV_Pos)) /* Assignment of value for STARTINV in the ADC_EVCTRL register */
+#define ADC_EVCTRL_RESRDYEO_Pos               _UINT32_(4)                                          /* (ADC_EVCTRL) Result Ready Event Out Position */
+#define ADC_EVCTRL_RESRDYEO_Msk               (_UINT32_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)           /* (ADC_EVCTRL) Result Ready Event Out Mask */
+#define ADC_EVCTRL_RESRDYEO(value)            (ADC_EVCTRL_RESRDYEO_Msk & (_UINT32_(value) << ADC_EVCTRL_RESRDYEO_Pos)) /* Assignment of value for RESRDYEO in the ADC_EVCTRL register */
+#define ADC_EVCTRL_CMPEO_Pos                  _UINT32_(5)                                          /* (ADC_EVCTRL) Comparator Window Event Out Position */
+#define ADC_EVCTRL_CMPEO_Msk                  (_UINT32_(0x1) << ADC_EVCTRL_CMPEO_Pos)              /* (ADC_EVCTRL) Comparator Window Event Out Mask */
+#define ADC_EVCTRL_CMPEO(value)               (ADC_EVCTRL_CMPEO_Msk & (_UINT32_(value) << ADC_EVCTRL_CMPEO_Pos)) /* Assignment of value for CMPEO in the ADC_EVCTRL register */
+#define ADC_EVCTRL_Msk                        _UINT32_(0x00000039)                                 /* (ADC_EVCTRL) Register Mask  */
+
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#define ADC_INTENCLR_RESETVALUE               _UINT32_(0x00)                                       /*  (ADC_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define ADC_INTENCLR_CMPHIT_Pos               _UINT32_(4)                                          /* (ADC_INTENCLR) Compare Hit Disable Position */
+#define ADC_INTENCLR_CMPHIT_Msk               (_UINT32_(0x1) << ADC_INTENCLR_CMPHIT_Pos)           /* (ADC_INTENCLR) Compare Hit Disable Mask */
+#define ADC_INTENCLR_CMPHIT(value)            (ADC_INTENCLR_CMPHIT_Msk & (_UINT32_(value) << ADC_INTENCLR_CMPHIT_Pos)) /* Assignment of value for CMPHIT in the ADC_INTENCLR register */
+#define ADC_INTENCLR_SOVFL_Pos                _UINT32_(7)                                          /* (ADC_INTENCLR) Synchonizer Overflow Disable Position */
+#define ADC_INTENCLR_SOVFL_Msk                (_UINT32_(0x1) << ADC_INTENCLR_SOVFL_Pos)            /* (ADC_INTENCLR) Synchonizer Overflow Disable Mask */
+#define ADC_INTENCLR_SOVFL(value)             (ADC_INTENCLR_SOVFL_Msk & (_UINT32_(value) << ADC_INTENCLR_SOVFL_Pos)) /* Assignment of value for SOVFL in the ADC_INTENCLR register */
+#define ADC_INTENCLR_CHRDYC_Pos               _UINT32_(8)                                          /* (ADC_INTENCLR) Core Current Channel Disable Position */
+#define ADC_INTENCLR_CHRDYC_Msk               (_UINT32_(0x1) << ADC_INTENCLR_CHRDYC_Pos)           /* (ADC_INTENCLR) Core Current Channel Disable Mask */
+#define ADC_INTENCLR_CHRDYC(value)            (ADC_INTENCLR_CHRDYC_Msk & (_UINT32_(value) << ADC_INTENCLR_CHRDYC_Pos)) /* Assignment of value for CHRDYC in the ADC_INTENCLR register */
+#define ADC_INTENCLR_FLTRDY_Pos               _UINT32_(9)                                          /* (ADC_INTENCLR) Filter Ready Disable Position */
+#define ADC_INTENCLR_FLTRDY_Msk               (_UINT32_(0x1) << ADC_INTENCLR_FLTRDY_Pos)           /* (ADC_INTENCLR) Filter Ready Disable Mask */
+#define ADC_INTENCLR_FLTRDY(value)            (ADC_INTENCLR_FLTRDY_Msk & (_UINT32_(value) << ADC_INTENCLR_FLTRDY_Pos)) /* Assignment of value for FLTRDY in the ADC_INTENCLR register */
+#define ADC_INTENCLR_CHNERRC_Pos              _UINT32_(10)                                         /* (ADC_INTENCLR) Channel Overwrite Error Disable Position */
+#define ADC_INTENCLR_CHNERRC_Msk              (_UINT32_(0x1) << ADC_INTENCLR_CHNERRC_Pos)          /* (ADC_INTENCLR) Channel Overwrite Error Disable Mask */
+#define ADC_INTENCLR_CHNERRC(value)           (ADC_INTENCLR_CHNERRC_Msk & (_UINT32_(value) << ADC_INTENCLR_CHNERRC_Pos)) /* Assignment of value for CHNERRC in the ADC_INTENCLR register */
+#define ADC_INTENCLR_EOSRDY_Pos               _UINT32_(11)                                         /* (ADC_INTENCLR) Endo of Scan Disable Position */
+#define ADC_INTENCLR_EOSRDY_Msk               (_UINT32_(0x1) << ADC_INTENCLR_EOSRDY_Pos)           /* (ADC_INTENCLR) Endo of Scan Disable Mask */
+#define ADC_INTENCLR_EOSRDY(value)            (ADC_INTENCLR_EOSRDY_Msk & (_UINT32_(value) << ADC_INTENCLR_EOSRDY_Pos)) /* Assignment of value for EOSRDY in the ADC_INTENCLR register */
+#define ADC_INTENCLR_CHRDY_Pos                _UINT32_(16)                                         /* (ADC_INTENCLR) Channel Ready Disable Position */
+#define ADC_INTENCLR_CHRDY_Msk                (_UINT32_(0xFFFF) << ADC_INTENCLR_CHRDY_Pos)         /* (ADC_INTENCLR) Channel Ready Disable Mask */
+#define ADC_INTENCLR_CHRDY(value)             (ADC_INTENCLR_CHRDY_Msk & (_UINT32_(value) << ADC_INTENCLR_CHRDY_Pos)) /* Assignment of value for CHRDY in the ADC_INTENCLR register */
+#define ADC_INTENCLR_Msk                      _UINT32_(0xFFFF0F90)                                 /* (ADC_INTENCLR) Register Mask  */
+
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#define ADC_INTENSET_RESETVALUE               _UINT32_(0x00)                                       /*  (ADC_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define ADC_INTENSET_CMPHIT_Pos               _UINT32_(4)                                          /* (ADC_INTENSET) Compare Hit Enable Position */
+#define ADC_INTENSET_CMPHIT_Msk               (_UINT32_(0x1) << ADC_INTENSET_CMPHIT_Pos)           /* (ADC_INTENSET) Compare Hit Enable Mask */
+#define ADC_INTENSET_CMPHIT(value)            (ADC_INTENSET_CMPHIT_Msk & (_UINT32_(value) << ADC_INTENSET_CMPHIT_Pos)) /* Assignment of value for CMPHIT in the ADC_INTENSET register */
+#define ADC_INTENSET_SOVFL_Pos                _UINT32_(7)                                          /* (ADC_INTENSET) Synchronizer Overflow Enable Position */
+#define ADC_INTENSET_SOVFL_Msk                (_UINT32_(0x1) << ADC_INTENSET_SOVFL_Pos)            /* (ADC_INTENSET) Synchronizer Overflow Enable Mask */
+#define ADC_INTENSET_SOVFL(value)             (ADC_INTENSET_SOVFL_Msk & (_UINT32_(value) << ADC_INTENSET_SOVFL_Pos)) /* Assignment of value for SOVFL in the ADC_INTENSET register */
+#define ADC_INTENSET_CHRDYC_Pos               _UINT32_(8)                                          /* (ADC_INTENSET) Current Channel Ready Enable Position */
+#define ADC_INTENSET_CHRDYC_Msk               (_UINT32_(0x1) << ADC_INTENSET_CHRDYC_Pos)           /* (ADC_INTENSET) Current Channel Ready Enable Mask */
+#define ADC_INTENSET_CHRDYC(value)            (ADC_INTENSET_CHRDYC_Msk & (_UINT32_(value) << ADC_INTENSET_CHRDYC_Pos)) /* Assignment of value for CHRDYC in the ADC_INTENSET register */
+#define ADC_INTENSET_FLTRDY_Pos               _UINT32_(9)                                          /* (ADC_INTENSET) Filter Ready Enable Position */
+#define ADC_INTENSET_FLTRDY_Msk               (_UINT32_(0x1) << ADC_INTENSET_FLTRDY_Pos)           /* (ADC_INTENSET) Filter Ready Enable Mask */
+#define ADC_INTENSET_FLTRDY(value)            (ADC_INTENSET_FLTRDY_Msk & (_UINT32_(value) << ADC_INTENSET_FLTRDY_Pos)) /* Assignment of value for FLTRDY in the ADC_INTENSET register */
+#define ADC_INTENSET_CHNERRC_Pos              _UINT32_(10)                                         /* (ADC_INTENSET) Channel Overwrite Enable Position */
+#define ADC_INTENSET_CHNERRC_Msk              (_UINT32_(0x1) << ADC_INTENSET_CHNERRC_Pos)          /* (ADC_INTENSET) Channel Overwrite Enable Mask */
+#define ADC_INTENSET_CHNERRC(value)           (ADC_INTENSET_CHNERRC_Msk & (_UINT32_(value) << ADC_INTENSET_CHNERRC_Pos)) /* Assignment of value for CHNERRC in the ADC_INTENSET register */
+#define ADC_INTENSET_EOSRDY_Pos               _UINT32_(11)                                         /* (ADC_INTENSET) End of Scan Enable Position */
+#define ADC_INTENSET_EOSRDY_Msk               (_UINT32_(0x1) << ADC_INTENSET_EOSRDY_Pos)           /* (ADC_INTENSET) End of Scan Enable Mask */
+#define ADC_INTENSET_EOSRDY(value)            (ADC_INTENSET_EOSRDY_Msk & (_UINT32_(value) << ADC_INTENSET_EOSRDY_Pos)) /* Assignment of value for EOSRDY in the ADC_INTENSET register */
+#define ADC_INTENSET_CHRDY_Pos                _UINT32_(16)                                         /* (ADC_INTENSET) Channel Ready Enable Position */
+#define ADC_INTENSET_CHRDY_Msk                (_UINT32_(0xFFFF) << ADC_INTENSET_CHRDY_Pos)         /* (ADC_INTENSET) Channel Ready Enable Mask */
+#define ADC_INTENSET_CHRDY(value)             (ADC_INTENSET_CHRDY_Msk & (_UINT32_(value) << ADC_INTENSET_CHRDY_Pos)) /* Assignment of value for CHRDY in the ADC_INTENSET register */
+#define ADC_INTENSET_Msk                      _UINT32_(0xFFFF0F90)                                 /* (ADC_INTENSET) Register Mask  */
+
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x08) (R/W 32) Interrupt Flags -------- */
+#define ADC_INTFLAG_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_INTFLAG) Interrupt Flags  Reset Value */
+
+#define ADC_INTFLAG_CMPINTID_Pos              _UINT32_(0)                                          /* (ADC_INTFLAG) Compare Channel ID Position */
+#define ADC_INTFLAG_CMPINTID_Msk              (_UINT32_(0xF) << ADC_INTFLAG_CMPINTID_Pos)          /* (ADC_INTFLAG) Compare Channel ID Mask */
+#define ADC_INTFLAG_CMPINTID(value)           (ADC_INTFLAG_CMPINTID_Msk & (_UINT32_(value) << ADC_INTFLAG_CMPINTID_Pos)) /* Assignment of value for CMPINTID in the ADC_INTFLAG register */
+#define ADC_INTFLAG_CMPHIT_Pos                _UINT32_(4)                                          /* (ADC_INTFLAG) Compare Hit Position */
+#define ADC_INTFLAG_CMPHIT_Msk                (_UINT32_(0x1) << ADC_INTFLAG_CMPHIT_Pos)            /* (ADC_INTFLAG) Compare Hit Mask */
+#define ADC_INTFLAG_CMPHIT(value)             (ADC_INTFLAG_CMPHIT_Msk & (_UINT32_(value) << ADC_INTFLAG_CMPHIT_Pos)) /* Assignment of value for CMPHIT in the ADC_INTFLAG register */
+#define ADC_INTFLAG_SOVFL_Pos                 _UINT32_(7)                                          /* (ADC_INTFLAG) Synchronizer Overflow Position */
+#define ADC_INTFLAG_SOVFL_Msk                 (_UINT32_(0x1) << ADC_INTFLAG_SOVFL_Pos)             /* (ADC_INTFLAG) Synchronizer Overflow Mask */
+#define ADC_INTFLAG_SOVFL(value)              (ADC_INTFLAG_SOVFL_Msk & (_UINT32_(value) << ADC_INTFLAG_SOVFL_Pos)) /* Assignment of value for SOVFL in the ADC_INTFLAG register */
+#define ADC_INTFLAG_CHRDYC_Pos                _UINT32_(8)                                          /* (ADC_INTFLAG) Current Channel Ready Position */
+#define ADC_INTFLAG_CHRDYC_Msk                (_UINT32_(0x1) << ADC_INTFLAG_CHRDYC_Pos)            /* (ADC_INTFLAG) Current Channel Ready Mask */
+#define ADC_INTFLAG_CHRDYC(value)             (ADC_INTFLAG_CHRDYC_Msk & (_UINT32_(value) << ADC_INTFLAG_CHRDYC_Pos)) /* Assignment of value for CHRDYC in the ADC_INTFLAG register */
+#define ADC_INTFLAG_FLTRDY_Pos                _UINT32_(9)                                          /* (ADC_INTFLAG) Filter Ready Position */
+#define ADC_INTFLAG_FLTRDY_Msk                (_UINT32_(0x1) << ADC_INTFLAG_FLTRDY_Pos)            /* (ADC_INTFLAG) Filter Ready Mask */
+#define ADC_INTFLAG_FLTRDY(value)             (ADC_INTFLAG_FLTRDY_Msk & (_UINT32_(value) << ADC_INTFLAG_FLTRDY_Pos)) /* Assignment of value for FLTRDY in the ADC_INTFLAG register */
+#define ADC_INTFLAG_CHNERRC_Pos               _UINT32_(10)                                         /* (ADC_INTFLAG) Channel Overwrite Error Position */
+#define ADC_INTFLAG_CHNERRC_Msk               (_UINT32_(0x1) << ADC_INTFLAG_CHNERRC_Pos)           /* (ADC_INTFLAG) Channel Overwrite Error Mask */
+#define ADC_INTFLAG_CHNERRC(value)            (ADC_INTFLAG_CHNERRC_Msk & (_UINT32_(value) << ADC_INTFLAG_CHNERRC_Pos)) /* Assignment of value for CHNERRC in the ADC_INTFLAG register */
+#define ADC_INTFLAG_EOSRDY_Pos                _UINT32_(11)                                         /* (ADC_INTFLAG) End of Scan Ready Position */
+#define ADC_INTFLAG_EOSRDY_Msk                (_UINT32_(0x1) << ADC_INTFLAG_EOSRDY_Pos)            /* (ADC_INTFLAG) End of Scan Ready Mask */
+#define ADC_INTFLAG_EOSRDY(value)             (ADC_INTFLAG_EOSRDY_Msk & (_UINT32_(value) << ADC_INTFLAG_EOSRDY_Pos)) /* Assignment of value for EOSRDY in the ADC_INTFLAG register */
+#define ADC_INTFLAG_CRDYID_Pos                _UINT32_(12)                                         /* (ADC_INTFLAG) Channel Ready ID Position */
+#define ADC_INTFLAG_CRDYID_Msk                (_UINT32_(0xF) << ADC_INTFLAG_CRDYID_Pos)            /* (ADC_INTFLAG) Channel Ready ID Mask */
+#define ADC_INTFLAG_CRDYID(value)             (ADC_INTFLAG_CRDYID_Msk & (_UINT32_(value) << ADC_INTFLAG_CRDYID_Pos)) /* Assignment of value for CRDYID in the ADC_INTFLAG register */
+#define ADC_INTFLAG_CHRDY_Pos                 _UINT32_(16)                                         /* (ADC_INTFLAG) Channel Ready Position */
+#define ADC_INTFLAG_CHRDY_Msk                 (_UINT32_(0xFFFF) << ADC_INTFLAG_CHRDY_Pos)          /* (ADC_INTFLAG) Channel Ready Mask */
+#define ADC_INTFLAG_CHRDY(value)              (ADC_INTFLAG_CHRDY_Msk & (_UINT32_(value) << ADC_INTFLAG_CHRDY_Pos)) /* Assignment of value for CHRDY in the ADC_INTFLAG register */
+#define ADC_INTFLAG_Msk                       _UINT32_(0xFFFFFF9F)                                 /* (ADC_INTFLAG) Register Mask  */
+
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 32) CONTROL A REGISTER -------- */
+#define ADC_CTRLA_RESETVALUE                  _UINT32_(0x80)                                       /*  (ADC_CTRLA) CONTROL A REGISTER  Reset Value */
+
+#define ADC_CTRLA_SWRST_Pos                   _UINT32_(0)                                          /* (ADC_CTRLA) SOFTWARE RESET BIT Position */
+#define ADC_CTRLA_SWRST_Msk                   (_UINT32_(0x1) << ADC_CTRLA_SWRST_Pos)               /* (ADC_CTRLA) SOFTWARE RESET BIT Mask */
+#define ADC_CTRLA_SWRST(value)                (ADC_CTRLA_SWRST_Msk & (_UINT32_(value) << ADC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the ADC_CTRLA register */
+#define ADC_CTRLA_ENABLE_Pos                  _UINT32_(1)                                          /* (ADC_CTRLA) ENABLE BIT Position */
+#define ADC_CTRLA_ENABLE_Msk                  (_UINT32_(0x1) << ADC_CTRLA_ENABLE_Pos)              /* (ADC_CTRLA) ENABLE BIT Mask */
+#define ADC_CTRLA_ENABLE(value)               (ADC_CTRLA_ENABLE_Msk & (_UINT32_(value) << ADC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the ADC_CTRLA register */
+#define ADC_CTRLA_ANAEN_Pos                   _UINT32_(2)                                          /* (ADC_CTRLA) Analog Enable Position */
+#define ADC_CTRLA_ANAEN_Msk                   (_UINT32_(0x1) << ADC_CTRLA_ANAEN_Pos)               /* (ADC_CTRLA) Analog Enable Mask */
+#define ADC_CTRLA_ANAEN(value)                (ADC_CTRLA_ANAEN_Msk & (_UINT32_(value) << ADC_CTRLA_ANAEN_Pos)) /* Assignment of value for ANAEN in the ADC_CTRLA register */
+#define ADC_CTRLA_AIPMPEN_Pos                 _UINT32_(4)                                          /* (ADC_CTRLA) Charge Pump Enable Position */
+#define ADC_CTRLA_AIPMPEN_Msk                 (_UINT32_(0x1) << ADC_CTRLA_AIPMPEN_Pos)             /* (ADC_CTRLA) Charge Pump Enable Mask */
+#define ADC_CTRLA_AIPMPEN(value)              (ADC_CTRLA_AIPMPEN_Msk & (_UINT32_(value) << ADC_CTRLA_AIPMPEN_Pos)) /* Assignment of value for AIPMPEN in the ADC_CTRLA register */
+#define ADC_CTRLA_RUNSTDBY_Pos                _UINT32_(6)                                          /* (ADC_CTRLA) Run in Standby Position */
+#define ADC_CTRLA_RUNSTDBY_Msk                (_UINT32_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)            /* (ADC_CTRLA) Run in Standby Mask */
+#define ADC_CTRLA_RUNSTDBY(value)             (ADC_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << ADC_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the ADC_CTRLA register */
+#define ADC_CTRLA_ONDEMAND_Pos                _UINT32_(7)                                          /* (ADC_CTRLA) On Demand Control Position */
+#define ADC_CTRLA_ONDEMAND_Msk                (_UINT32_(0x1) << ADC_CTRLA_ONDEMAND_Pos)            /* (ADC_CTRLA) On Demand Control Mask */
+#define ADC_CTRLA_ONDEMAND(value)             (ADC_CTRLA_ONDEMAND_Msk & (_UINT32_(value) << ADC_CTRLA_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the ADC_CTRLA register */
+#define ADC_CTRLA_Msk                         _UINT32_(0x000000D7)                                 /* (ADC_CTRLA) Register Mask  */
+
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 32) CONTROL B REGISTER -------- */
+#define ADC_CTRLB_RESETVALUE                  _UINT32_(0x00)                                       /*  (ADC_CTRLB) CONTROL B REGISTER  Reset Value */
+
+#define ADC_CTRLB_ADCHSEL_Pos                 _UINT32_(0)                                          /* (ADC_CTRLB) Software Trigger Channel Select Position */
+#define ADC_CTRLB_ADCHSEL_Msk                 (_UINT32_(0xF) << ADC_CTRLB_ADCHSEL_Pos)             /* (ADC_CTRLB) Software Trigger Channel Select Mask */
+#define ADC_CTRLB_ADCHSEL(value)              (ADC_CTRLB_ADCHSEL_Msk & (_UINT32_(value) << ADC_CTRLB_ADCHSEL_Pos)) /* Assignment of value for ADCHSEL in the ADC_CTRLB register */
+#define ADC_CTRLB_ADCORSEL_Pos                _UINT32_(4)                                          /* (ADC_CTRLB) Software Trigger Core Select Position */
+#define ADC_CTRLB_ADCORSEL_Msk                (_UINT32_(0x3) << ADC_CTRLB_ADCORSEL_Pos)            /* (ADC_CTRLB) Software Trigger Core Select Mask */
+#define ADC_CTRLB_ADCORSEL(value)             (ADC_CTRLB_ADCORSEL_Msk & (_UINT32_(value) << ADC_CTRLB_ADCORSEL_Pos)) /* Assignment of value for ADCORSEL in the ADC_CTRLB register */
+#define ADC_CTRLB_RQCNVRT_Pos                 _UINT32_(6)                                          /* (ADC_CTRLB) Request Channel Convert Position */
+#define ADC_CTRLB_RQCNVRT_Msk                 (_UINT32_(0x1) << ADC_CTRLB_RQCNVRT_Pos)             /* (ADC_CTRLB) Request Channel Convert Mask */
+#define ADC_CTRLB_RQCNVRT(value)              (ADC_CTRLB_RQCNVRT_Msk & (_UINT32_(value) << ADC_CTRLB_RQCNVRT_Pos)) /* Assignment of value for RQCNVRT in the ADC_CTRLB register */
+#define ADC_CTRLB_SAMP_Pos                    _UINT32_(7)                                          /* (ADC_CTRLB) Channel Sample Position */
+#define ADC_CTRLB_SAMP_Msk                    (_UINT32_(0x1) << ADC_CTRLB_SAMP_Pos)                /* (ADC_CTRLB) Channel Sample Mask */
+#define ADC_CTRLB_SAMP(value)                 (ADC_CTRLB_SAMP_Msk & (_UINT32_(value) << ADC_CTRLB_SAMP_Pos)) /* Assignment of value for SAMP in the ADC_CTRLB register */
+#define ADC_CTRLB_GSWTRG_Pos                  _UINT32_(8)                                          /* (ADC_CTRLB) Global Software Trigger Position */
+#define ADC_CTRLB_GSWTRG_Msk                  (_UINT32_(0x1) << ADC_CTRLB_GSWTRG_Pos)              /* (ADC_CTRLB) Global Software Trigger Mask */
+#define ADC_CTRLB_GSWTRG(value)               (ADC_CTRLB_GSWTRG_Msk & (_UINT32_(value) << ADC_CTRLB_GSWTRG_Pos)) /* Assignment of value for GSWTRG in the ADC_CTRLB register */
+#define ADC_CTRLB_LSWTRG_Pos                  _UINT32_(9)                                          /* (ADC_CTRLB) Level Global Trigger Position */
+#define ADC_CTRLB_LSWTRG_Msk                  (_UINT32_(0x1) << ADC_CTRLB_LSWTRG_Pos)              /* (ADC_CTRLB) Level Global Trigger Mask */
+#define ADC_CTRLB_LSWTRG(value)               (ADC_CTRLB_LSWTRG_Msk & (_UINT32_(value) << ADC_CTRLB_LSWTRG_Pos)) /* Assignment of value for LSWTRG in the ADC_CTRLB register */
+#define ADC_CTRLB_TRGSUSP_Pos                 _UINT32_(10)                                         /* (ADC_CTRLB) Trigger Suspend Position */
+#define ADC_CTRLB_TRGSUSP_Msk                 (_UINT32_(0x1) << ADC_CTRLB_TRGSUSP_Pos)             /* (ADC_CTRLB) Trigger Suspend Mask */
+#define ADC_CTRLB_TRGSUSP(value)              (ADC_CTRLB_TRGSUSP_Msk & (_UINT32_(value) << ADC_CTRLB_TRGSUSP_Pos)) /* Assignment of value for TRGSUSP in the ADC_CTRLB register */
+#define ADC_CTRLB_STRGEN_Pos                  _UINT32_(11)                                         /* (ADC_CTRLB) Synchronous Trigger Enable Position */
+#define ADC_CTRLB_STRGEN_Msk                  (_UINT32_(0x1) << ADC_CTRLB_STRGEN_Pos)              /* (ADC_CTRLB) Synchronous Trigger Enable Mask */
+#define ADC_CTRLB_STRGEN(value)               (ADC_CTRLB_STRGEN_Msk & (_UINT32_(value) << ADC_CTRLB_STRGEN_Pos)) /* Assignment of value for STRGEN in the ADC_CTRLB register */
+#define ADC_CTRLB_SWCNVEN_Pos                 _UINT32_(15)                                         /* (ADC_CTRLB) Software Conversion Enable Position */
+#define ADC_CTRLB_SWCNVEN_Msk                 (_UINT32_(0x1) << ADC_CTRLB_SWCNVEN_Pos)             /* (ADC_CTRLB) Software Conversion Enable Mask */
+#define ADC_CTRLB_SWCNVEN(value)              (ADC_CTRLB_SWCNVEN_Msk & (_UINT32_(value) << ADC_CTRLB_SWCNVEN_Pos)) /* Assignment of value for SWCNVEN in the ADC_CTRLB register */
+#define ADC_CTRLB_Msk                         _UINT32_(0x00008FFF)                                 /* (ADC_CTRLB) Register Mask  */
+
+
+/* -------- ADC_CTRLC : (ADC Offset: 0x08) (R/W 32) Control C Register -------- */
+#define ADC_CTRLC_RESETVALUE                  _UINT32_(0x00)                                       /*  (ADC_CTRLC) Control C Register  Reset Value */
+
+#define ADC_CTRLC_CNT_Pos                     _UINT32_(0)                                          /* (ADC_CTRLC) Clock Divider for Synchronous Trigger Position */
+#define ADC_CTRLC_CNT_Msk                     (_UINT32_(0xFFFF) << ADC_CTRLC_CNT_Pos)              /* (ADC_CTRLC) Clock Divider for Synchronous Trigger Mask */
+#define ADC_CTRLC_CNT(value)                  (ADC_CTRLC_CNT_Msk & (_UINT32_(value) << ADC_CTRLC_CNT_Pos)) /* Assignment of value for CNT in the ADC_CTRLC register */
+#define ADC_CTRLC_COREINTERLEAVED_Pos         _UINT32_(28)                                         /* (ADC_CTRLC) Number of Core to Interleave Triggers Position */
+#define ADC_CTRLC_COREINTERLEAVED_Msk         (_UINT32_(0x7) << ADC_CTRLC_COREINTERLEAVED_Pos)     /* (ADC_CTRLC) Number of Core to Interleave Triggers Mask */
+#define ADC_CTRLC_COREINTERLEAVED(value)      (ADC_CTRLC_COREINTERLEAVED_Msk & (_UINT32_(value) << ADC_CTRLC_COREINTERLEAVED_Pos)) /* Assignment of value for COREINTERLEAVED in the ADC_CTRLC register */
+#define ADC_CTRLC_Msk                         _UINT32_(0x7000FFFF)                                 /* (ADC_CTRLC) Register Mask  */
+
+
+/* -------- ADC_CTRLD : (ADC Offset: 0x10) (R/W 32) Control D Register -------- */
+#define ADC_CTRLD_RESETVALUE                  _UINT32_(0x00)                                       /*  (ADC_CTRLD) Control D Register  Reset Value */
+
+#define ADC_CTRLD_CTLCKDIV_Pos                _UINT32_(8)                                          /* (ADC_CTRLD) Control Clock Divider Position */
+#define ADC_CTRLD_CTLCKDIV_Msk                (_UINT32_(0x3F) << ADC_CTRLD_CTLCKDIV_Pos)           /* (ADC_CTRLD) Control Clock Divider Mask */
+#define ADC_CTRLD_CTLCKDIV(value)             (ADC_CTRLD_CTLCKDIV_Msk & (_UINT32_(value) << ADC_CTRLD_CTLCKDIV_Pos)) /* Assignment of value for CTLCKDIV in the ADC_CTRLD register */
+#define ADC_CTRLD_CHNEN0_Pos                  _UINT32_(16)                                         /* (ADC_CTRLD) Core 0 Digital Channel Enable Position */
+#define ADC_CTRLD_CHNEN0_Msk                  (_UINT32_(0x1) << ADC_CTRLD_CHNEN0_Pos)              /* (ADC_CTRLD) Core 0 Digital Channel Enable Mask */
+#define ADC_CTRLD_CHNEN0(value)               (ADC_CTRLD_CHNEN0_Msk & (_UINT32_(value) << ADC_CTRLD_CHNEN0_Pos)) /* Assignment of value for CHNEN0 in the ADC_CTRLD register */
+#define ADC_CTRLD_ANLEN0_Pos                  _UINT32_(20)                                         /* (ADC_CTRLD) Analog and Bias circuitry Enable for core 0 Position */
+#define ADC_CTRLD_ANLEN0_Msk                  (_UINT32_(0x1) << ADC_CTRLD_ANLEN0_Pos)              /* (ADC_CTRLD) Analog and Bias circuitry Enable for core 0 Mask */
+#define ADC_CTRLD_ANLEN0(value)               (ADC_CTRLD_ANLEN0_Msk & (_UINT32_(value) << ADC_CTRLD_ANLEN0_Pos)) /* Assignment of value for ANLEN0 in the ADC_CTRLD register */
+#define ADC_CTRLD_WKUPEXP_Pos                 _UINT32_(24)                                         /* (ADC_CTRLD) Wakeup cycles Position */
+#define ADC_CTRLD_WKUPEXP_Msk                 (_UINT32_(0xF) << ADC_CTRLD_WKUPEXP_Pos)             /* (ADC_CTRLD) Wakeup cycles Mask */
+#define ADC_CTRLD_WKUPEXP(value)              (ADC_CTRLD_WKUPEXP_Msk & (_UINT32_(value) << ADC_CTRLD_WKUPEXP_Pos)) /* Assignment of value for WKUPEXP in the ADC_CTRLD register */
+#define ADC_CTRLD_VREFSEL_Pos                 _UINT32_(28)                                         /* (ADC_CTRLD) Voltage Reference Select Position */
+#define ADC_CTRLD_VREFSEL_Msk                 (_UINT32_(0x7) << ADC_CTRLD_VREFSEL_Pos)             /* (ADC_CTRLD) Voltage Reference Select Mask */
+#define ADC_CTRLD_VREFSEL(value)              (ADC_CTRLD_VREFSEL_Msk & (_UINT32_(value) << ADC_CTRLD_VREFSEL_Pos)) /* Assignment of value for VREFSEL in the ADC_CTRLD register */
+#define   ADC_CTRLD_VREFSEL_AVDD_AVSS_Val     _UINT32_(0x0)                                        /* (ADC_CTRLD) AVDD and AVSS  */
+#define   ADC_CTRLD_VREFSEL_EXTERNAL_VREFH_AVSS_Val _UINT32_(0x1)                                        /* (ADC_CTRLD) External VREFH and AVSS  */
+#define ADC_CTRLD_VREFSEL_AVDD_AVSS           (ADC_CTRLD_VREFSEL_AVDD_AVSS_Val << ADC_CTRLD_VREFSEL_Pos) /* (ADC_CTRLD) AVDD and AVSS Position */
+#define ADC_CTRLD_VREFSEL_EXTERNAL_VREFH_AVSS (ADC_CTRLD_VREFSEL_EXTERNAL_VREFH_AVSS_Val << ADC_CTRLD_VREFSEL_Pos) /* (ADC_CTRLD) External VREFH and AVSS Position */
+#define ADC_CTRLD_Msk                         _UINT32_(0x7F113F00)                                 /* (ADC_CTRLD) Register Mask  */
+
+#define ADC_CTRLD_CHNEN_Pos                   _UINT32_(16)                                         /* (ADC_CTRLD Position) Core x Digital Channel Enable */
+#define ADC_CTRLD_CHNEN_Msk                   (_UINT32_(0x1) << ADC_CTRLD_CHNEN_Pos)               /* (ADC_CTRLD Mask) CHNEN */
+#define ADC_CTRLD_CHNEN(value)                (ADC_CTRLD_CHNEN_Msk & (_UINT32_(value) << ADC_CTRLD_CHNEN_Pos)) 
+#define ADC_CTRLD_ANLEN_Pos                   _UINT32_(20)                                         /* (ADC_CTRLD Position) Analog and Bias circuitry Enable for core x */
+#define ADC_CTRLD_ANLEN_Msk                   (_UINT32_(0x1) << ADC_CTRLD_ANLEN_Pos)               /* (ADC_CTRLD Mask) ANLEN */
+#define ADC_CTRLD_ANLEN(value)                (ADC_CTRLD_ANLEN_Msk & (_UINT32_(value) << ADC_CTRLD_ANLEN_Pos)) 
+
+/* -------- ADC_CMPCTRL : (ADC Offset: 0xB0) (R/W 32) Comparator Control -------- */
+#define ADC_CMPCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_CMPCTRL) Comparator Control  Reset Value */
+
+#define ADC_CMPCTRL_ADCMPLO_Pos               _UINT32_(0)                                          /* (ADC_CMPCTRL) Low Limit of Digital Comparator Position */
+#define ADC_CMPCTRL_ADCMPLO_Msk               (_UINT32_(0xFFF) << ADC_CMPCTRL_ADCMPLO_Pos)         /* (ADC_CMPCTRL) Low Limit of Digital Comparator Mask */
+#define ADC_CMPCTRL_ADCMPLO(value)            (ADC_CMPCTRL_ADCMPLO_Msk & (_UINT32_(value) << ADC_CMPCTRL_ADCMPLO_Pos)) /* Assignment of value for ADCMPLO in the ADC_CMPCTRL register */
+#define ADC_CMPCTRL_CMPEN_Pos                 _UINT32_(12)                                         /* (ADC_CMPCTRL) Comparator Enable Position */
+#define ADC_CMPCTRL_CMPEN_Msk                 (_UINT32_(0x1) << ADC_CMPCTRL_CMPEN_Pos)             /* (ADC_CMPCTRL) Comparator Enable Mask */
+#define ADC_CMPCTRL_CMPEN(value)              (ADC_CMPCTRL_CMPEN_Msk & (_UINT32_(value) << ADC_CMPCTRL_CMPEN_Pos)) /* Assignment of value for CMPEN in the ADC_CMPCTRL register */
+#define ADC_CMPCTRL_IELOLO_Pos                _UINT32_(13)                                         /* (ADC_CMPCTRL) Enable VAL < CMPLO Position */
+#define ADC_CMPCTRL_IELOLO_Msk                (_UINT32_(0x1) << ADC_CMPCTRL_IELOLO_Pos)            /* (ADC_CMPCTRL) Enable VAL < CMPLO Mask */
+#define ADC_CMPCTRL_IELOLO(value)             (ADC_CMPCTRL_IELOLO_Msk & (_UINT32_(value) << ADC_CMPCTRL_IELOLO_Pos)) /* Assignment of value for IELOLO in the ADC_CMPCTRL register */
+#define ADC_CMPCTRL_IELOHI_Pos                _UINT32_(14)                                         /* (ADC_CMPCTRL) Enable VAL >= CMPLO Position */
+#define ADC_CMPCTRL_IELOHI_Msk                (_UINT32_(0x1) << ADC_CMPCTRL_IELOHI_Pos)            /* (ADC_CMPCTRL) Enable VAL >= CMPLO Mask */
+#define ADC_CMPCTRL_IELOHI(value)             (ADC_CMPCTRL_IELOHI_Msk & (_UINT32_(value) << ADC_CMPCTRL_IELOHI_Pos)) /* Assignment of value for IELOHI in the ADC_CMPCTRL register */
+#define ADC_CMPCTRL_IEBTWN_Pos                _UINT32_(15)                                         /* (ADC_CMPCTRL) Enable CMPLO <= VAL < CMPHI Position */
+#define ADC_CMPCTRL_IEBTWN_Msk                (_UINT32_(0x1) << ADC_CMPCTRL_IEBTWN_Pos)            /* (ADC_CMPCTRL) Enable CMPLO <= VAL < CMPHI Mask */
+#define ADC_CMPCTRL_IEBTWN(value)             (ADC_CMPCTRL_IEBTWN_Msk & (_UINT32_(value) << ADC_CMPCTRL_IEBTWN_Pos)) /* Assignment of value for IEBTWN in the ADC_CMPCTRL register */
+#define ADC_CMPCTRL_ADCMPHI_Pos               _UINT32_(16)                                         /* (ADC_CMPCTRL) High Limit of Digital Comparator Position */
+#define ADC_CMPCTRL_ADCMPHI_Msk               (_UINT32_(0xFFF) << ADC_CMPCTRL_ADCMPHI_Pos)         /* (ADC_CMPCTRL) High Limit of Digital Comparator Mask */
+#define ADC_CMPCTRL_ADCMPHI(value)            (ADC_CMPCTRL_ADCMPHI_Msk & (_UINT32_(value) << ADC_CMPCTRL_ADCMPHI_Pos)) /* Assignment of value for ADCMPHI in the ADC_CMPCTRL register */
+#define ADC_CMPCTRL_IEHILO_Pos                _UINT32_(28)                                         /* (ADC_CMPCTRL) Enable VAL < CMPHI Position */
+#define ADC_CMPCTRL_IEHILO_Msk                (_UINT32_(0x1) << ADC_CMPCTRL_IEHILO_Pos)            /* (ADC_CMPCTRL) Enable VAL < CMPHI Mask */
+#define ADC_CMPCTRL_IEHILO(value)             (ADC_CMPCTRL_IEHILO_Msk & (_UINT32_(value) << ADC_CMPCTRL_IEHILO_Pos)) /* Assignment of value for IEHILO in the ADC_CMPCTRL register */
+#define ADC_CMPCTRL_IEHIHI_Pos                _UINT32_(29)                                         /* (ADC_CMPCTRL) Enable VAL >= CMPHI Position */
+#define ADC_CMPCTRL_IEHIHI_Msk                (_UINT32_(0x1) << ADC_CMPCTRL_IEHIHI_Pos)            /* (ADC_CMPCTRL) Enable VAL >= CMPHI Mask */
+#define ADC_CMPCTRL_IEHIHI(value)             (ADC_CMPCTRL_IEHIHI_Msk & (_UINT32_(value) << ADC_CMPCTRL_IEHIHI_Pos)) /* Assignment of value for IEHIHI in the ADC_CMPCTRL register */
+#define ADC_CMPCTRL_Msk                       _UINT32_(0x3FFFFFFF)                                 /* (ADC_CMPCTRL) Register Mask  */
+
+
+/* -------- ADC_FLTCTRL : (ADC Offset: 0xC0) (R/W 32) Filter Control -------- */
+#define ADC_FLTCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_FLTCTRL) Filter Control  Reset Value */
+
+#define ADC_FLTCTRL_OVRSAM_Pos                _UINT32_(0)                                          /* (ADC_FLTCTRL) Oversampling Ratio Position */
+#define ADC_FLTCTRL_OVRSAM_Msk                (_UINT32_(0x7) << ADC_FLTCTRL_OVRSAM_Pos)            /* (ADC_FLTCTRL) Oversampling Ratio Mask */
+#define ADC_FLTCTRL_OVRSAM(value)             (ADC_FLTCTRL_OVRSAM_Msk & (_UINT32_(value) << ADC_FLTCTRL_OVRSAM_Pos)) /* Assignment of value for OVRSAM in the ADC_FLTCTRL register */
+#define   ADC_FLTCTRL_OVRSAM_4_SAMPLES_Val    _UINT32_(0x0)                                        /* (ADC_FLTCTRL) (If FMODE is 0) 4 samples (shift sum 1 bit to right, output data is 13-bits) / (If FMODE is 1) 2 samples to be averaged  */
+#define   ADC_FLTCTRL_OVRSAM_16_SAMPLES_Val   _UINT32_(0x1)                                        /* (ADC_FLTCTRL) (If FMODE is 0) 16 samples (shift sum 2 bits to right, output data is 14-bits) / (If FMODE is 1) 4 samples to be averaged  */
+#define   ADC_FLTCTRL_OVRSAM_64_SAMPLES_Val   _UINT32_(0x2)                                        /* (ADC_FLTCTRL) (If FMODE is 0) 64 samples (shift sum 3 bits to right, output data is 15-bits) / (If FMODE is 1) 8 samples to be averaged  */
+#define   ADC_FLTCTRL_OVRSAM_256_SAMPLES_Val  _UINT32_(0x3)                                        /* (ADC_FLTCTRL) (If FMODE is 0) 256 samples (shift sum 4 bits to right, output data is 16-bits) / (If FMODE is 1) 16 samples to be averaged  */
+#define   ADC_FLTCTRL_OVRSAM_2_SAMPLES_Val    _UINT32_(0x4)                                        /* (ADC_FLTCTRL) (If FMODE is 0) 2 samples (shift sum 0 bits to right, output data is 12.1 format) / (If FMODE is 1) 32 samples to be averaged  */
+#define   ADC_FLTCTRL_OVRSAM_8_SAMPLES_Val    _UINT32_(0x5)                                        /* (ADC_FLTCTRL) (If FMODE is 0) 8 samples (shift sum 1 bit to right, output data is 13.1 format) / (If FMODE is 1) 64 samples to be averaged  */
+#define   ADC_FLTCTRL_OVRSAM_32_SAMPLES_Val   _UINT32_(0x6)                                        /* (ADC_FLTCTRL) (If FMODE is 0) 32 samples (shift sum 2 bits to right, output data is 14.1 format) / (If FMODE is 1) 128 samples to be averaged  */
+#define   ADC_FLTCTRL_OVRSAM_128_SAMPLES_Val  _UINT32_(0x7)                                        /* (ADC_FLTCTRL) (If FMODE is 0) 128 samples (shift sum 3 bits to right, output data is 15.1 format) / (If FMODE is 1) 256 samples to be averaged  */
+#define ADC_FLTCTRL_OVRSAM_4_SAMPLES          (ADC_FLTCTRL_OVRSAM_4_SAMPLES_Val << ADC_FLTCTRL_OVRSAM_Pos) /* (ADC_FLTCTRL) (If FMODE is 0) 4 samples (shift sum 1 bit to right, output data is 13-bits) / (If FMODE is 1) 2 samples to be averaged Position */
+#define ADC_FLTCTRL_OVRSAM_16_SAMPLES         (ADC_FLTCTRL_OVRSAM_16_SAMPLES_Val << ADC_FLTCTRL_OVRSAM_Pos) /* (ADC_FLTCTRL) (If FMODE is 0) 16 samples (shift sum 2 bits to right, output data is 14-bits) / (If FMODE is 1) 4 samples to be averaged Position */
+#define ADC_FLTCTRL_OVRSAM_64_SAMPLES         (ADC_FLTCTRL_OVRSAM_64_SAMPLES_Val << ADC_FLTCTRL_OVRSAM_Pos) /* (ADC_FLTCTRL) (If FMODE is 0) 64 samples (shift sum 3 bits to right, output data is 15-bits) / (If FMODE is 1) 8 samples to be averaged Position */
+#define ADC_FLTCTRL_OVRSAM_256_SAMPLES        (ADC_FLTCTRL_OVRSAM_256_SAMPLES_Val << ADC_FLTCTRL_OVRSAM_Pos) /* (ADC_FLTCTRL) (If FMODE is 0) 256 samples (shift sum 4 bits to right, output data is 16-bits) / (If FMODE is 1) 16 samples to be averaged Position */
+#define ADC_FLTCTRL_OVRSAM_2_SAMPLES          (ADC_FLTCTRL_OVRSAM_2_SAMPLES_Val << ADC_FLTCTRL_OVRSAM_Pos) /* (ADC_FLTCTRL) (If FMODE is 0) 2 samples (shift sum 0 bits to right, output data is 12.1 format) / (If FMODE is 1) 32 samples to be averaged Position */
+#define ADC_FLTCTRL_OVRSAM_8_SAMPLES          (ADC_FLTCTRL_OVRSAM_8_SAMPLES_Val << ADC_FLTCTRL_OVRSAM_Pos) /* (ADC_FLTCTRL) (If FMODE is 0) 8 samples (shift sum 1 bit to right, output data is 13.1 format) / (If FMODE is 1) 64 samples to be averaged Position */
+#define ADC_FLTCTRL_OVRSAM_32_SAMPLES         (ADC_FLTCTRL_OVRSAM_32_SAMPLES_Val << ADC_FLTCTRL_OVRSAM_Pos) /* (ADC_FLTCTRL) (If FMODE is 0) 32 samples (shift sum 2 bits to right, output data is 14.1 format) / (If FMODE is 1) 128 samples to be averaged Position */
+#define ADC_FLTCTRL_OVRSAM_128_SAMPLES        (ADC_FLTCTRL_OVRSAM_128_SAMPLES_Val << ADC_FLTCTRL_OVRSAM_Pos) /* (ADC_FLTCTRL) (If FMODE is 0) 128 samples (shift sum 3 bits to right, output data is 15.1 format) / (If FMODE is 1) 256 samples to be averaged Position */
+#define ADC_FLTCTRL_FMODE_Pos                 _UINT32_(3)                                          /* (ADC_FLTCTRL) Filter Mode Position */
+#define ADC_FLTCTRL_FMODE_Msk                 (_UINT32_(0x1) << ADC_FLTCTRL_FMODE_Pos)             /* (ADC_FLTCTRL) Filter Mode Mask */
+#define ADC_FLTCTRL_FMODE(value)              (ADC_FLTCTRL_FMODE_Msk & (_UINT32_(value) << ADC_FLTCTRL_FMODE_Pos)) /* Assignment of value for FMODE in the ADC_FLTCTRL register */
+#define ADC_FLTCTRL_DATA16EN_Pos              _UINT32_(4)                                          /* (ADC_FLTCTRL) 16bit Averaging Mode Position */
+#define ADC_FLTCTRL_DATA16EN_Msk              (_UINT32_(0x1) << ADC_FLTCTRL_DATA16EN_Pos)          /* (ADC_FLTCTRL) 16bit Averaging Mode Mask */
+#define ADC_FLTCTRL_DATA16EN(value)           (ADC_FLTCTRL_DATA16EN_Msk & (_UINT32_(value) << ADC_FLTCTRL_DATA16EN_Pos)) /* Assignment of value for DATA16EN in the ADC_FLTCTRL register */
+#define ADC_FLTCTRL_FLTEN_Pos                 _UINT32_(8)                                          /* (ADC_FLTCTRL) Filter Enable Position */
+#define ADC_FLTCTRL_FLTEN_Msk                 (_UINT32_(0x1) << ADC_FLTCTRL_FLTEN_Pos)             /* (ADC_FLTCTRL) Filter Enable Mask */
+#define ADC_FLTCTRL_FLTEN(value)              (ADC_FLTCTRL_FLTEN_Msk & (_UINT32_(value) << ADC_FLTCTRL_FLTEN_Pos)) /* Assignment of value for FLTEN in the ADC_FLTCTRL register */
+#define ADC_FLTCTRL_FLTCHNID_Pos              _UINT32_(10)                                         /* (ADC_FLTCTRL) Channel ID Position */
+#define ADC_FLTCTRL_FLTCHNID_Msk              (_UINT32_(0xF) << ADC_FLTCTRL_FLTCHNID_Pos)          /* (ADC_FLTCTRL) Channel ID Mask */
+#define ADC_FLTCTRL_FLTCHNID(value)           (ADC_FLTCTRL_FLTCHNID_Msk & (_UINT32_(value) << ADC_FLTCTRL_FLTCHNID_Pos)) /* Assignment of value for FLTCHNID in the ADC_FLTCTRL register */
+#define ADC_FLTCTRL_Msk                       _UINT32_(0x00003D1F)                                 /* (ADC_FLTCTRL) Register Mask  */
+
+
+/* -------- ADC_CORCHDATAID : (ADC Offset: 0xD0) (R/W 32) Channel Ready DATA ID -------- */
+#define ADC_CORCHDATAID_RESETVALUE            _UINT32_(0x00)                                       /*  (ADC_CORCHDATAID) Channel Ready DATA ID  Reset Value */
+
+#define ADC_CORCHDATAID_CHRDYID_Pos           _UINT32_(0)                                          /* (ADC_CORCHDATAID) Channel Read ID Position */
+#define ADC_CORCHDATAID_CHRDYID_Msk           (_UINT32_(0xF) << ADC_CORCHDATAID_CHRDYID_Pos)       /* (ADC_CORCHDATAID) Channel Read ID Mask */
+#define ADC_CORCHDATAID_CHRDYID(value)        (ADC_CORCHDATAID_CHRDYID_Msk & (_UINT32_(value) << ADC_CORCHDATAID_CHRDYID_Pos)) /* Assignment of value for CHRDYID in the ADC_CORCHDATAID register */
+#define ADC_CORCHDATAID_CORDYID_Pos           _UINT32_(4)                                          /* (ADC_CORCHDATAID) Core Read ID Position */
+#define ADC_CORCHDATAID_CORDYID_Msk           (_UINT32_(0x3) << ADC_CORCHDATAID_CORDYID_Pos)       /* (ADC_CORCHDATAID) Core Read ID Mask */
+#define ADC_CORCHDATAID_CORDYID(value)        (ADC_CORCHDATAID_CORDYID_Msk & (_UINT32_(value) << ADC_CORCHDATAID_CORDYID_Pos)) /* Assignment of value for CORDYID in the ADC_CORCHDATAID register */
+#define ADC_CORCHDATAID_Msk                   _UINT32_(0x0000003F)                                 /* (ADC_CORCHDATAID) Register Mask  */
+
+
+/* -------- ADC_CHRDYDAT : (ADC Offset: 0xD4) (R/W 32) Channel Ready Data Register -------- */
+#define ADC_CHRDYDAT_RESETVALUE               _UINT32_(0x00)                                       /*  (ADC_CHRDYDAT) Channel Ready Data Register  Reset Value */
+
+#define ADC_CHRDYDAT_CHRDYDAT_Pos             _UINT32_(0)                                          /* (ADC_CHRDYDAT) Channel Output Data Position */
+#define ADC_CHRDYDAT_CHRDYDAT_Msk             (_UINT32_(0xFFFF) << ADC_CHRDYDAT_CHRDYDAT_Pos)      /* (ADC_CHRDYDAT) Channel Output Data Mask */
+#define ADC_CHRDYDAT_CHRDYDAT(value)          (ADC_CHRDYDAT_CHRDYDAT_Msk & (_UINT32_(value) << ADC_CHRDYDAT_CHRDYDAT_Pos)) /* Assignment of value for CHRDYDAT in the ADC_CHRDYDAT register */
+#define ADC_CHRDYDAT_LVL_Pos                  _UINT32_(24)                                         /* (ADC_CHRDYDAT) Level Setting Position */
+#define ADC_CHRDYDAT_LVL_Msk                  (_UINT32_(0x1) << ADC_CHRDYDAT_LVL_Pos)              /* (ADC_CHRDYDAT) Level Setting Mask */
+#define ADC_CHRDYDAT_LVL(value)               (ADC_CHRDYDAT_LVL_Msk & (_UINT32_(value) << ADC_CHRDYDAT_LVL_Pos)) /* Assignment of value for LVL in the ADC_CHRDYDAT register */
+#define ADC_CHRDYDAT_DIFF_Pos                 _UINT32_(25)                                         /* (ADC_CHRDYDAT) Differential Setting Position */
+#define ADC_CHRDYDAT_DIFF_Msk                 (_UINT32_(0x1) << ADC_CHRDYDAT_DIFF_Pos)             /* (ADC_CHRDYDAT) Differential Setting Mask */
+#define ADC_CHRDYDAT_DIFF(value)              (ADC_CHRDYDAT_DIFF_Msk & (_UINT32_(value) << ADC_CHRDYDAT_DIFF_Pos)) /* Assignment of value for DIFF in the ADC_CHRDYDAT register */
+#define ADC_CHRDYDAT_SIGN_Pos                 _UINT32_(26)                                         /* (ADC_CHRDYDAT) Sign Setting Position */
+#define ADC_CHRDYDAT_SIGN_Msk                 (_UINT32_(0x1) << ADC_CHRDYDAT_SIGN_Pos)             /* (ADC_CHRDYDAT) Sign Setting Mask */
+#define ADC_CHRDYDAT_SIGN(value)              (ADC_CHRDYDAT_SIGN_Msk & (_UINT32_(value) << ADC_CHRDYDAT_SIGN_Pos)) /* Assignment of value for SIGN in the ADC_CHRDYDAT register */
+#define ADC_CHRDYDAT_FRACT_Pos                _UINT32_(27)                                         /* (ADC_CHRDYDAT) Fractional Setting Position */
+#define ADC_CHRDYDAT_FRACT_Msk                (_UINT32_(0x1) << ADC_CHRDYDAT_FRACT_Pos)            /* (ADC_CHRDYDAT) Fractional Setting Mask */
+#define ADC_CHRDYDAT_FRACT(value)             (ADC_CHRDYDAT_FRACT_Msk & (_UINT32_(value) << ADC_CHRDYDAT_FRACT_Pos)) /* Assignment of value for FRACT in the ADC_CHRDYDAT register */
+#define ADC_CHRDYDAT_Msk                      _UINT32_(0x0F00FFFF)                                 /* (ADC_CHRDYDAT) Register Mask  */
+
+
+/* -------- ADC_PFFDATA : (ADC Offset: 0xD8) ( R/ 32) APB FIFO Output Data -------- */
+#define ADC_PFFDATA_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_PFFDATA) APB FIFO Output Data  Reset Value */
+
+#define ADC_PFFDATA_PFFDATA_Pos               _UINT32_(0)                                          /* (ADC_PFFDATA) SARCORE Conversion data from the APB FIFO Position */
+#define ADC_PFFDATA_PFFDATA_Msk               (_UINT32_(0xFFFF) << ADC_PFFDATA_PFFDATA_Pos)        /* (ADC_PFFDATA) SARCORE Conversion data from the APB FIFO Mask */
+#define ADC_PFFDATA_PFFDATA(value)            (ADC_PFFDATA_PFFDATA_Msk & (_UINT32_(value) << ADC_PFFDATA_PFFDATA_Pos)) /* Assignment of value for PFFDATA in the ADC_PFFDATA register */
+#define ADC_PFFDATA_PFFCHNID_Pos              _UINT32_(16)                                         /* (ADC_PFFDATA) Channel ID from APB FIFO Position */
+#define ADC_PFFDATA_PFFCHNID_Msk              (_UINT32_(0xF) << ADC_PFFDATA_PFFCHNID_Pos)          /* (ADC_PFFDATA) Channel ID from APB FIFO Mask */
+#define ADC_PFFDATA_PFFCHNID(value)           (ADC_PFFDATA_PFFCHNID_Msk & (_UINT32_(value) << ADC_PFFDATA_PFFCHNID_Pos)) /* Assignment of value for PFFCHNID in the ADC_PFFDATA register */
+#define ADC_PFFDATA_PFFCORID_Pos              _UINT32_(20)                                         /* (ADC_PFFDATA) Core ID from APB FIFO Position */
+#define ADC_PFFDATA_PFFCORID_Msk              (_UINT32_(0x3) << ADC_PFFDATA_PFFCORID_Pos)          /* (ADC_PFFDATA) Core ID from APB FIFO Mask */
+#define ADC_PFFDATA_PFFCORID(value)           (ADC_PFFDATA_PFFCORID_Msk & (_UINT32_(value) << ADC_PFFDATA_PFFCORID_Pos)) /* Assignment of value for PFFCORID in the ADC_PFFDATA register */
+#define ADC_PFFDATA_PFFSIGN_Pos               _UINT32_(22)                                         /* (ADC_PFFDATA) Channel Sign from the APB FIFO Position */
+#define ADC_PFFDATA_PFFSIGN_Msk               (_UINT32_(0x1) << ADC_PFFDATA_PFFSIGN_Pos)           /* (ADC_PFFDATA) Channel Sign from the APB FIFO Mask */
+#define ADC_PFFDATA_PFFSIGN(value)            (ADC_PFFDATA_PFFSIGN_Msk & (_UINT32_(value) << ADC_PFFDATA_PFFSIGN_Pos)) /* Assignment of value for PFFSIGN in the ADC_PFFDATA register */
+#define ADC_PFFDATA_PFFFRACT_Pos              _UINT32_(23)                                         /* (ADC_PFFDATA) Fractional Setting from APB FIFO Position */
+#define ADC_PFFDATA_PFFFRACT_Msk              (_UINT32_(0x1) << ADC_PFFDATA_PFFFRACT_Pos)          /* (ADC_PFFDATA) Fractional Setting from APB FIFO Mask */
+#define ADC_PFFDATA_PFFFRACT(value)           (ADC_PFFDATA_PFFFRACT_Msk & (_UINT32_(value) << ADC_PFFDATA_PFFFRACT_Pos)) /* Assignment of value for PFFFRACT in the ADC_PFFDATA register */
+#define ADC_PFFDATA_PFFCNT_Pos                _UINT32_(24)                                         /* (ADC_PFFDATA) Current Data Entries in APB FIFO Position */
+#define ADC_PFFDATA_PFFCNT_Msk                (_UINT32_(0xFF) << ADC_PFFDATA_PFFCNT_Pos)           /* (ADC_PFFDATA) Current Data Entries in APB FIFO Mask */
+#define ADC_PFFDATA_PFFCNT(value)             (ADC_PFFDATA_PFFCNT_Msk & (_UINT32_(value) << ADC_PFFDATA_PFFCNT_Pos)) /* Assignment of value for PFFCNT in the ADC_PFFDATA register */
+#define ADC_PFFDATA_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (ADC_PFFDATA) Register Mask  */
+
+
+/* -------- ADC_DMABASE : (ADC Offset: 0xDC) (R/W 32) DMA Sample Base Address -------- */
+#define ADC_DMABASE_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_DMABASE) DMA Sample Base Address  Reset Value */
+
+#define ADC_DMABASE_DMABASE_Pos               _UINT32_(0)                                          /* (ADC_DMABASE) DMA Sample Value Base Address Position */
+#define ADC_DMABASE_DMABASE_Msk               (_UINT32_(0xFFFFFFFF) << ADC_DMABASE_DMABASE_Pos)    /* (ADC_DMABASE) DMA Sample Value Base Address Mask */
+#define ADC_DMABASE_DMABASE(value)            (ADC_DMABASE_DMABASE_Msk & (_UINT32_(value) << ADC_DMABASE_DMABASE_Pos)) /* Assignment of value for DMABASE in the ADC_DMABASE register */
+#define ADC_DMABASE_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (ADC_DMABASE) Register Mask  */
+
+
+/* -------- ADC_DMACTRL : (ADC Offset: 0xE0) (R/W 32) DMA Control Register -------- */
+#define ADC_DMACTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_DMACTRL) DMA Control Register  Reset Value */
+
+#define ADC_DMACTRL_DMAEN_Pos                 _UINT32_(1)                                          /* (ADC_DMACTRL) DMA Enable Position */
+#define ADC_DMACTRL_DMAEN_Msk                 (_UINT32_(0x1) << ADC_DMACTRL_DMAEN_Pos)             /* (ADC_DMACTRL) DMA Enable Mask */
+#define ADC_DMACTRL_DMAEN(value)              (ADC_DMACTRL_DMAEN_Msk & (_UINT32_(value) << ADC_DMACTRL_DMAEN_Pos)) /* Assignment of value for DMAEN in the ADC_DMACTRL register */
+#define ADC_DMACTRL_DMACR0_Pos                _UINT32_(4)                                          /* (ADC_DMACTRL) DMA CORE0 Enable Position */
+#define ADC_DMACTRL_DMACR0_Msk                (_UINT32_(0x1) << ADC_DMACTRL_DMACR0_Pos)            /* (ADC_DMACTRL) DMA CORE0 Enable Mask */
+#define ADC_DMACTRL_DMACR0(value)             (ADC_DMACTRL_DMACR0_Msk & (_UINT32_(value) << ADC_DMACTRL_DMACR0_Pos)) /* Assignment of value for DMACR0 in the ADC_DMACTRL register */
+#define ADC_DMACTRL_DMABL_Pos                 _UINT32_(8)                                          /* (ADC_DMACTRL) DMA System RAM Buffer Length Position */
+#define ADC_DMACTRL_DMABL_Msk                 (_UINT32_(0x7) << ADC_DMACTRL_DMABL_Pos)             /* (ADC_DMACTRL) DMA System RAM Buffer Length Mask */
+#define ADC_DMACTRL_DMABL(value)              (ADC_DMACTRL_DMABL_Msk & (_UINT32_(value) << ADC_DMACTRL_DMABL_Pos)) /* Assignment of value for DMABL in the ADC_DMACTRL register */
+#define ADC_DMACTRL_Msk                       _UINT32_(0x00000712)                                 /* (ADC_DMACTRL) Register Mask  */
+
+#define ADC_DMACTRL_DMACR_Pos                 _UINT32_(4)                                          /* (ADC_DMACTRL Position) DMA COREx Enable */
+#define ADC_DMACTRL_DMACR_Msk                 (_UINT32_(0x1) << ADC_DMACTRL_DMACR_Pos)             /* (ADC_DMACTRL Mask) DMACR */
+#define ADC_DMACTRL_DMACR(value)              (ADC_DMACTRL_DMACR_Msk & (_UINT32_(value) << ADC_DMACTRL_DMACR_Pos)) 
+
+/* -------- ADC_PFFCTRL : (ADC Offset: 0xE4) (R/W 32) APB FIFO Control Register -------- */
+#define ADC_PFFCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_PFFCTRL) APB FIFO Control Register  Reset Value */
+
+#define ADC_PFFCTRL_PFFEN_Pos                 _UINT32_(1)                                          /* (ADC_PFFCTRL) APB FIFO Enable Position */
+#define ADC_PFFCTRL_PFFEN_Msk                 (_UINT32_(0x1) << ADC_PFFCTRL_PFFEN_Pos)             /* (ADC_PFFCTRL) APB FIFO Enable Mask */
+#define ADC_PFFCTRL_PFFEN(value)              (ADC_PFFCTRL_PFFEN_Msk & (_UINT32_(value) << ADC_PFFCTRL_PFFEN_Pos)) /* Assignment of value for PFFEN in the ADC_PFFCTRL register */
+#define ADC_PFFCTRL_PFFCR0_Pos                _UINT32_(4)                                          /* (ADC_PFFCTRL) APB CORE 0 FIFO Enable Position */
+#define ADC_PFFCTRL_PFFCR0_Msk                (_UINT32_(0x1) << ADC_PFFCTRL_PFFCR0_Pos)            /* (ADC_PFFCTRL) APB CORE 0 FIFO Enable Mask */
+#define ADC_PFFCTRL_PFFCR0(value)             (ADC_PFFCTRL_PFFCR0_Msk & (_UINT32_(value) << ADC_PFFCTRL_PFFCR0_Pos)) /* Assignment of value for PFFCR0 in the ADC_PFFCTRL register */
+#define ADC_PFFCTRL_PFFRDYDM_Pos              _UINT32_(16)                                         /* (ADC_PFFCTRL) DMA APB FIFO Data Ready Position */
+#define ADC_PFFCTRL_PFFRDYDM_Msk              (_UINT32_(0x1) << ADC_PFFCTRL_PFFRDYDM_Pos)          /* (ADC_PFFCTRL) DMA APB FIFO Data Ready Mask */
+#define ADC_PFFCTRL_PFFRDYDM(value)           (ADC_PFFCTRL_PFFRDYDM_Msk & (_UINT32_(value) << ADC_PFFCTRL_PFFRDYDM_Pos)) /* Assignment of value for PFFRDYDM in the ADC_PFFCTRL register */
+#define   ADC_PFFCTRL_PFFRDYDM_CTLINTFLAG_PFFHFUL_Val _UINT32_(0x0)                                        /* (ADC_PFFCTRL) Selects CTLINTFLAG.PFFHFUL for the ADC DMA PFFRDY trigger signal to the DMAC  */
+#define   ADC_PFFCTRL_PFFRDYDM_CTLINTFLAG_PFFRDY_Val _UINT32_(0x1)                                        /* (ADC_PFFCTRL) Selects CTLINTFLAG.PFFRDY for the ADC DMA PFFRDY trigger signal to the DMAC  */
+#define ADC_PFFCTRL_PFFRDYDM_CTLINTFLAG_PFFHFUL (ADC_PFFCTRL_PFFRDYDM_CTLINTFLAG_PFFHFUL_Val << ADC_PFFCTRL_PFFRDYDM_Pos) /* (ADC_PFFCTRL) Selects CTLINTFLAG.PFFHFUL for the ADC DMA PFFRDY trigger signal to the DMAC Position */
+#define ADC_PFFCTRL_PFFRDYDM_CTLINTFLAG_PFFRDY (ADC_PFFCTRL_PFFRDYDM_CTLINTFLAG_PFFRDY_Val << ADC_PFFCTRL_PFFRDYDM_Pos) /* (ADC_PFFCTRL) Selects CTLINTFLAG.PFFRDY for the ADC DMA PFFRDY trigger signal to the DMAC Position */
+#define ADC_PFFCTRL_Msk                       _UINT32_(0x00010012)                                 /* (ADC_PFFCTRL) Register Mask  */
+
+#define ADC_PFFCTRL_PFFCR_Pos                 _UINT32_(4)                                          /* (ADC_PFFCTRL Position) APB CORE x FIFO Enable */
+#define ADC_PFFCTRL_PFFCR_Msk                 (_UINT32_(0x1) << ADC_PFFCTRL_PFFCR_Pos)             /* (ADC_PFFCTRL Mask) PFFCR */
+#define ADC_PFFCTRL_PFFCR(value)              (ADC_PFFCTRL_PFFCR_Msk & (_UINT32_(value) << ADC_PFFCTRL_PFFCR_Pos)) 
+
+/* -------- ADC_SYNCBUSY : (ADC Offset: 0xE8) ( R/ 32) CORE SYNC Busy Status Register -------- */
+#define ADC_SYNCBUSY_RESETVALUE               _UINT32_(0x00)                                       /*  (ADC_SYNCBUSY) CORE SYNC Busy Status Register  Reset Value */
+
+#define ADC_SYNCBUSY_SWRST_Pos                _UINT32_(0)                                          /* (ADC_SYNCBUSY) Software Reset Sync Busy Position */
+#define ADC_SYNCBUSY_SWRST_Msk                (_UINT32_(0x1) << ADC_SYNCBUSY_SWRST_Pos)            /* (ADC_SYNCBUSY) Software Reset Sync Busy Mask */
+#define ADC_SYNCBUSY_SWRST(value)             (ADC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << ADC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the ADC_SYNCBUSY register */
+#define ADC_SYNCBUSY_ENABLE_Pos               _UINT32_(1)                                          /* (ADC_SYNCBUSY) Enable bit Sync Busy Position */
+#define ADC_SYNCBUSY_ENABLE_Msk               (_UINT32_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)           /* (ADC_SYNCBUSY) Enable bit Sync Busy Mask */
+#define ADC_SYNCBUSY_ENABLE(value)            (ADC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << ADC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the ADC_SYNCBUSY register */
+#define ADC_SYNCBUSY_CTRLB_Pos                _UINT32_(2)                                          /* (ADC_SYNCBUSY) CTRLB sync busy Position */
+#define ADC_SYNCBUSY_CTRLB_Msk                (_UINT32_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)            /* (ADC_SYNCBUSY) CTRLB sync busy Mask */
+#define ADC_SYNCBUSY_CTRLB(value)             (ADC_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << ADC_SYNCBUSY_CTRLB_Pos)) /* Assignment of value for CTRLB in the ADC_SYNCBUSY register */
+#define ADC_SYNCBUSY_Msk                      _UINT32_(0x00000007)                                 /* (ADC_SYNCBUSY) Register Mask  */
+
+
+/* -------- ADC_DMAINTENCLR : (ADC Offset: 0xF0) (R/W 32) DMA Interrupt Enable Clear -------- */
+#define ADC_DMAINTENCLR_RESETVALUE            _UINT32_(0x00)                                       /*  (ADC_DMAINTENCLR) DMA Interrupt Enable Clear  Reset Value */
+
+#define ADC_DMAINTENCLR_RAF_Pos               _UINT32_(0)                                          /* (ADC_DMAINTENCLR) Ram Buffer A Full Position */
+#define ADC_DMAINTENCLR_RAF_Msk               (_UINT32_(0xF) << ADC_DMAINTENCLR_RAF_Pos)           /* (ADC_DMAINTENCLR) Ram Buffer A Full Mask */
+#define ADC_DMAINTENCLR_RAF(value)            (ADC_DMAINTENCLR_RAF_Msk & (_UINT32_(value) << ADC_DMAINTENCLR_RAF_Pos)) /* Assignment of value for RAF in the ADC_DMAINTENCLR register */
+#define ADC_DMAINTENCLR_RBF_Pos               _UINT32_(4)                                          /* (ADC_DMAINTENCLR) Ram Buffer B Full Position */
+#define ADC_DMAINTENCLR_RBF_Msk               (_UINT32_(0xF) << ADC_DMAINTENCLR_RBF_Pos)           /* (ADC_DMAINTENCLR) Ram Buffer B Full Mask */
+#define ADC_DMAINTENCLR_RBF(value)            (ADC_DMAINTENCLR_RBF_Msk & (_UINT32_(value) << ADC_DMAINTENCLR_RBF_Pos)) /* Assignment of value for RBF in the ADC_DMAINTENCLR register */
+#define ADC_DMAINTENCLR_SOVFL_Pos             _UINT32_(16)                                         /* (ADC_DMAINTENCLR) Synchonizer Overflow Position */
+#define ADC_DMAINTENCLR_SOVFL_Msk             (_UINT32_(0x1) << ADC_DMAINTENCLR_SOVFL_Pos)         /* (ADC_DMAINTENCLR) Synchonizer Overflow Mask */
+#define ADC_DMAINTENCLR_SOVFL(value)          (ADC_DMAINTENCLR_SOVFL_Msk & (_UINT32_(value) << ADC_DMAINTENCLR_SOVFL_Pos)) /* Assignment of value for SOVFL in the ADC_DMAINTENCLR register */
+#define ADC_DMAINTENCLR_Msk                   _UINT32_(0x000100FF)                                 /* (ADC_DMAINTENCLR) Register Mask  */
+
+
+/* -------- ADC_DMAINTSET : (ADC Offset: 0xF4) (R/W 32) DMA Interrupt Enable Set -------- */
+#define ADC_DMAINTSET_RESETVALUE              _UINT32_(0x00)                                       /*  (ADC_DMAINTSET) DMA Interrupt Enable Set  Reset Value */
+
+#define ADC_DMAINTSET_RAF_Pos                 _UINT32_(0)                                          /* (ADC_DMAINTSET) Ram Buffer A Full Position */
+#define ADC_DMAINTSET_RAF_Msk                 (_UINT32_(0xF) << ADC_DMAINTSET_RAF_Pos)             /* (ADC_DMAINTSET) Ram Buffer A Full Mask */
+#define ADC_DMAINTSET_RAF(value)              (ADC_DMAINTSET_RAF_Msk & (_UINT32_(value) << ADC_DMAINTSET_RAF_Pos)) /* Assignment of value for RAF in the ADC_DMAINTSET register */
+#define ADC_DMAINTSET_RBF_Pos                 _UINT32_(4)                                          /* (ADC_DMAINTSET) Ram Buffer B Full Position */
+#define ADC_DMAINTSET_RBF_Msk                 (_UINT32_(0xF) << ADC_DMAINTSET_RBF_Pos)             /* (ADC_DMAINTSET) Ram Buffer B Full Mask */
+#define ADC_DMAINTSET_RBF(value)              (ADC_DMAINTSET_RBF_Msk & (_UINT32_(value) << ADC_DMAINTSET_RBF_Pos)) /* Assignment of value for RBF in the ADC_DMAINTSET register */
+#define ADC_DMAINTSET_SOVFL_Pos               _UINT32_(16)                                         /* (ADC_DMAINTSET) Synchonizer Overflow Position */
+#define ADC_DMAINTSET_SOVFL_Msk               (_UINT32_(0x1) << ADC_DMAINTSET_SOVFL_Pos)           /* (ADC_DMAINTSET) Synchonizer Overflow Mask */
+#define ADC_DMAINTSET_SOVFL(value)            (ADC_DMAINTSET_SOVFL_Msk & (_UINT32_(value) << ADC_DMAINTSET_SOVFL_Pos)) /* Assignment of value for SOVFL in the ADC_DMAINTSET register */
+#define ADC_DMAINTSET_Msk                     _UINT32_(0x000100FF)                                 /* (ADC_DMAINTSET) Register Mask  */
+
+
+/* -------- ADC_DMAINTFLAG : (ADC Offset: 0xF8) (R/W 32) DMA Interrupt Flag and Status -------- */
+#define ADC_DMAINTFLAG_RESETVALUE             _UINT32_(0x00)                                       /*  (ADC_DMAINTFLAG) DMA Interrupt Flag and Status  Reset Value */
+
+#define ADC_DMAINTFLAG_RAF_Pos                _UINT32_(0)                                          /* (ADC_DMAINTFLAG) Ram Buffer A Full Position */
+#define ADC_DMAINTFLAG_RAF_Msk                (_UINT32_(0xF) << ADC_DMAINTFLAG_RAF_Pos)            /* (ADC_DMAINTFLAG) Ram Buffer A Full Mask */
+#define ADC_DMAINTFLAG_RAF(value)             (ADC_DMAINTFLAG_RAF_Msk & (_UINT32_(value) << ADC_DMAINTFLAG_RAF_Pos)) /* Assignment of value for RAF in the ADC_DMAINTFLAG register */
+#define ADC_DMAINTFLAG_RBF_Pos                _UINT32_(4)                                          /* (ADC_DMAINTFLAG) Ram Buffer B Full Position */
+#define ADC_DMAINTFLAG_RBF_Msk                (_UINT32_(0xF) << ADC_DMAINTFLAG_RBF_Pos)            /* (ADC_DMAINTFLAG) Ram Buffer B Full Mask */
+#define ADC_DMAINTFLAG_RBF(value)             (ADC_DMAINTFLAG_RBF_Msk & (_UINT32_(value) << ADC_DMAINTFLAG_RBF_Pos)) /* Assignment of value for RBF in the ADC_DMAINTFLAG register */
+#define ADC_DMAINTFLAG_EAF_Pos                _UINT32_(8)                                          /* (ADC_DMAINTFLAG) Ram Buffer A Overflow Error Position */
+#define ADC_DMAINTFLAG_EAF_Msk                (_UINT32_(0xF) << ADC_DMAINTFLAG_EAF_Pos)            /* (ADC_DMAINTFLAG) Ram Buffer A Overflow Error Mask */
+#define ADC_DMAINTFLAG_EAF(value)             (ADC_DMAINTFLAG_EAF_Msk & (_UINT32_(value) << ADC_DMAINTFLAG_EAF_Pos)) /* Assignment of value for EAF in the ADC_DMAINTFLAG register */
+#define ADC_DMAINTFLAG_EBF_Pos                _UINT32_(12)                                         /* (ADC_DMAINTFLAG) Ram Buffer B Overflow Error Position */
+#define ADC_DMAINTFLAG_EBF_Msk                (_UINT32_(0xF) << ADC_DMAINTFLAG_EBF_Pos)            /* (ADC_DMAINTFLAG) Ram Buffer B Overflow Error Mask */
+#define ADC_DMAINTFLAG_EBF(value)             (ADC_DMAINTFLAG_EBF_Msk & (_UINT32_(value) << ADC_DMAINTFLAG_EBF_Pos)) /* Assignment of value for EBF in the ADC_DMAINTFLAG register */
+#define ADC_DMAINTFLAG_SOVFL_Pos              _UINT32_(16)                                         /* (ADC_DMAINTFLAG) Synchronizer overflow Position */
+#define ADC_DMAINTFLAG_SOVFL_Msk              (_UINT32_(0x1) << ADC_DMAINTFLAG_SOVFL_Pos)          /* (ADC_DMAINTFLAG) Synchronizer overflow Mask */
+#define ADC_DMAINTFLAG_SOVFL(value)           (ADC_DMAINTFLAG_SOVFL_Msk & (_UINT32_(value) << ADC_DMAINTFLAG_SOVFL_Pos)) /* Assignment of value for SOVFL in the ADC_DMAINTFLAG register */
+#define ADC_DMAINTFLAG_DMAERR_Pos             _UINT32_(17)                                         /* (ADC_DMAINTFLAG) DMA Bus Error Position */
+#define ADC_DMAINTFLAG_DMAERR_Msk             (_UINT32_(0x1) << ADC_DMAINTFLAG_DMAERR_Pos)         /* (ADC_DMAINTFLAG) DMA Bus Error Mask */
+#define ADC_DMAINTFLAG_DMAERR(value)          (ADC_DMAINTFLAG_DMAERR_Msk & (_UINT32_(value) << ADC_DMAINTFLAG_DMAERR_Pos)) /* Assignment of value for DMAERR in the ADC_DMAINTFLAG register */
+#define ADC_DMAINTFLAG_Msk                    _UINT32_(0x0003FFFF)                                 /* (ADC_DMAINTFLAG) Register Mask  */
+
+
+/* -------- ADC_CTLINTENSET : (ADC Offset: 0xFC) (R/W 32) CORE Controller Interrupt Enable Set -------- */
+#define ADC_CTLINTENSET_RESETVALUE            _UINT32_(0x00)                                       /*  (ADC_CTLINTENSET) CORE Controller Interrupt Enable Set  Reset Value */
+
+#define ADC_CTLINTENSET_CRRDY0_Pos            _UINT32_(0)                                          /* (ADC_CTLINTENSET) Core 0 Ready Position */
+#define ADC_CTLINTENSET_CRRDY0_Msk            (_UINT32_(0x1) << ADC_CTLINTENSET_CRRDY0_Pos)        /* (ADC_CTLINTENSET) Core 0 Ready Mask */
+#define ADC_CTLINTENSET_CRRDY0(value)         (ADC_CTLINTENSET_CRRDY0_Msk & (_UINT32_(value) << ADC_CTLINTENSET_CRRDY0_Pos)) /* Assignment of value for CRRDY0 in the ADC_CTLINTENSET register */
+#define ADC_CTLINTENSET_VREFUPD_Pos           _UINT32_(6)                                          /* (ADC_CTLINTENSET) VREF update Position */
+#define ADC_CTLINTENSET_VREFUPD_Msk           (_UINT32_(0x1) << ADC_CTLINTENSET_VREFUPD_Pos)       /* (ADC_CTLINTENSET) VREF update Mask */
+#define ADC_CTLINTENSET_VREFUPD(value)        (ADC_CTLINTENSET_VREFUPD_Msk & (_UINT32_(value) << ADC_CTLINTENSET_VREFUPD_Pos)) /* Assignment of value for VREFUPD in the ADC_CTLINTENSET register */
+#define ADC_CTLINTENSET_VREFRDY_Pos           _UINT32_(7)                                          /* (ADC_CTLINTENSET) VREF Ready Position */
+#define ADC_CTLINTENSET_VREFRDY_Msk           (_UINT32_(0x1) << ADC_CTLINTENSET_VREFRDY_Pos)       /* (ADC_CTLINTENSET) VREF Ready Mask */
+#define ADC_CTLINTENSET_VREFRDY(value)        (ADC_CTLINTENSET_VREFRDY_Msk & (_UINT32_(value) << ADC_CTLINTENSET_VREFRDY_Pos)) /* Assignment of value for VREFRDY in the ADC_CTLINTENSET register */
+#define ADC_CTLINTENSET_PFFUNF_Pos            _UINT32_(8)                                          /* (ADC_CTLINTENSET) APB FIFO Underflow Position */
+#define ADC_CTLINTENSET_PFFUNF_Msk            (_UINT32_(0x1) << ADC_CTLINTENSET_PFFUNF_Pos)        /* (ADC_CTLINTENSET) APB FIFO Underflow Mask */
+#define ADC_CTLINTENSET_PFFUNF(value)         (ADC_CTLINTENSET_PFFUNF_Msk & (_UINT32_(value) << ADC_CTLINTENSET_PFFUNF_Pos)) /* Assignment of value for PFFUNF in the ADC_CTLINTENSET register */
+#define ADC_CTLINTENSET_PFFOVF_Pos            _UINT32_(9)                                          /* (ADC_CTLINTENSET) APB FIFO Overflow Position */
+#define ADC_CTLINTENSET_PFFOVF_Msk            (_UINT32_(0x1) << ADC_CTLINTENSET_PFFOVF_Pos)        /* (ADC_CTLINTENSET) APB FIFO Overflow Mask */
+#define ADC_CTLINTENSET_PFFOVF(value)         (ADC_CTLINTENSET_PFFOVF_Msk & (_UINT32_(value) << ADC_CTLINTENSET_PFFOVF_Pos)) /* Assignment of value for PFFOVF in the ADC_CTLINTENSET register */
+#define ADC_CTLINTENSET_PFFRDY_Pos            _UINT32_(10)                                         /* (ADC_CTLINTENSET) APB FIFO Ready Position */
+#define ADC_CTLINTENSET_PFFRDY_Msk            (_UINT32_(0x1) << ADC_CTLINTENSET_PFFRDY_Pos)        /* (ADC_CTLINTENSET) APB FIFO Ready Mask */
+#define ADC_CTLINTENSET_PFFRDY(value)         (ADC_CTLINTENSET_PFFRDY_Msk & (_UINT32_(value) << ADC_CTLINTENSET_PFFRDY_Pos)) /* Assignment of value for PFFRDY in the ADC_CTLINTENSET register */
+#define ADC_CTLINTENSET_PFFHFUL_Pos           _UINT32_(11)                                         /* (ADC_CTLINTENSET) APB FIFO Half Full Position */
+#define ADC_CTLINTENSET_PFFHFUL_Msk           (_UINT32_(0x1) << ADC_CTLINTENSET_PFFHFUL_Pos)       /* (ADC_CTLINTENSET) APB FIFO Half Full Mask */
+#define ADC_CTLINTENSET_PFFHFUL(value)        (ADC_CTLINTENSET_PFFHFUL_Msk & (_UINT32_(value) << ADC_CTLINTENSET_PFFHFUL_Pos)) /* Assignment of value for PFFHFUL in the ADC_CTLINTENSET register */
+#define ADC_CTLINTENSET_Msk                   _UINT32_(0x00000FC1)                                 /* (ADC_CTLINTENSET) Register Mask  */
+
+#define ADC_CTLINTENSET_CRRDY_Pos             _UINT32_(0)                                          /* (ADC_CTLINTENSET Position) Core x Ready */
+#define ADC_CTLINTENSET_CRRDY_Msk             (_UINT32_(0x1) << ADC_CTLINTENSET_CRRDY_Pos)         /* (ADC_CTLINTENSET Mask) CRRDY */
+#define ADC_CTLINTENSET_CRRDY(value)          (ADC_CTLINTENSET_CRRDY_Msk & (_UINT32_(value) << ADC_CTLINTENSET_CRRDY_Pos)) 
+
+/* -------- ADC_CTLINTENCLR : (ADC Offset: 0x100) (R/W 32) CORE Controller Interrupt Enable Clear -------- */
+#define ADC_CTLINTENCLR_RESETVALUE            _UINT32_(0x00)                                       /*  (ADC_CTLINTENCLR) CORE Controller Interrupt Enable Clear  Reset Value */
+
+#define ADC_CTLINTENCLR_CRRDY0_Pos            _UINT32_(0)                                          /* (ADC_CTLINTENCLR) Core Ready 0 Disable Position */
+#define ADC_CTLINTENCLR_CRRDY0_Msk            (_UINT32_(0x1) << ADC_CTLINTENCLR_CRRDY0_Pos)        /* (ADC_CTLINTENCLR) Core Ready 0 Disable Mask */
+#define ADC_CTLINTENCLR_CRRDY0(value)         (ADC_CTLINTENCLR_CRRDY0_Msk & (_UINT32_(value) << ADC_CTLINTENCLR_CRRDY0_Pos)) /* Assignment of value for CRRDY0 in the ADC_CTLINTENCLR register */
+#define ADC_CTLINTENCLR_VREFUPD_Pos           _UINT32_(6)                                          /* (ADC_CTLINTENCLR) VREF Update Position */
+#define ADC_CTLINTENCLR_VREFUPD_Msk           (_UINT32_(0x1) << ADC_CTLINTENCLR_VREFUPD_Pos)       /* (ADC_CTLINTENCLR) VREF Update Mask */
+#define ADC_CTLINTENCLR_VREFUPD(value)        (ADC_CTLINTENCLR_VREFUPD_Msk & (_UINT32_(value) << ADC_CTLINTENCLR_VREFUPD_Pos)) /* Assignment of value for VREFUPD in the ADC_CTLINTENCLR register */
+#define ADC_CTLINTENCLR_VREFRDY_Pos           _UINT32_(7)                                          /* (ADC_CTLINTENCLR) VREF Ready Position */
+#define ADC_CTLINTENCLR_VREFRDY_Msk           (_UINT32_(0x1) << ADC_CTLINTENCLR_VREFRDY_Pos)       /* (ADC_CTLINTENCLR) VREF Ready Mask */
+#define ADC_CTLINTENCLR_VREFRDY(value)        (ADC_CTLINTENCLR_VREFRDY_Msk & (_UINT32_(value) << ADC_CTLINTENCLR_VREFRDY_Pos)) /* Assignment of value for VREFRDY in the ADC_CTLINTENCLR register */
+#define ADC_CTLINTENCLR_PFFUNF_Pos            _UINT32_(8)                                          /* (ADC_CTLINTENCLR) APB FIFO underflow Position */
+#define ADC_CTLINTENCLR_PFFUNF_Msk            (_UINT32_(0x1) << ADC_CTLINTENCLR_PFFUNF_Pos)        /* (ADC_CTLINTENCLR) APB FIFO underflow Mask */
+#define ADC_CTLINTENCLR_PFFUNF(value)         (ADC_CTLINTENCLR_PFFUNF_Msk & (_UINT32_(value) << ADC_CTLINTENCLR_PFFUNF_Pos)) /* Assignment of value for PFFUNF in the ADC_CTLINTENCLR register */
+#define ADC_CTLINTENCLR_PFFOVF_Pos            _UINT32_(9)                                          /* (ADC_CTLINTENCLR) APB FIFO overflow Position */
+#define ADC_CTLINTENCLR_PFFOVF_Msk            (_UINT32_(0x1) << ADC_CTLINTENCLR_PFFOVF_Pos)        /* (ADC_CTLINTENCLR) APB FIFO overflow Mask */
+#define ADC_CTLINTENCLR_PFFOVF(value)         (ADC_CTLINTENCLR_PFFOVF_Msk & (_UINT32_(value) << ADC_CTLINTENCLR_PFFOVF_Pos)) /* Assignment of value for PFFOVF in the ADC_CTLINTENCLR register */
+#define ADC_CTLINTENCLR_PFFRDY_Pos            _UINT32_(10)                                         /* (ADC_CTLINTENCLR) APB FIFO Ready Position */
+#define ADC_CTLINTENCLR_PFFRDY_Msk            (_UINT32_(0x1) << ADC_CTLINTENCLR_PFFRDY_Pos)        /* (ADC_CTLINTENCLR) APB FIFO Ready Mask */
+#define ADC_CTLINTENCLR_PFFRDY(value)         (ADC_CTLINTENCLR_PFFRDY_Msk & (_UINT32_(value) << ADC_CTLINTENCLR_PFFRDY_Pos)) /* Assignment of value for PFFRDY in the ADC_CTLINTENCLR register */
+#define ADC_CTLINTENCLR_PFFHFUL_Pos           _UINT32_(11)                                         /* (ADC_CTLINTENCLR) APB FIFO Half Full Position */
+#define ADC_CTLINTENCLR_PFFHFUL_Msk           (_UINT32_(0x1) << ADC_CTLINTENCLR_PFFHFUL_Pos)       /* (ADC_CTLINTENCLR) APB FIFO Half Full Mask */
+#define ADC_CTLINTENCLR_PFFHFUL(value)        (ADC_CTLINTENCLR_PFFHFUL_Msk & (_UINT32_(value) << ADC_CTLINTENCLR_PFFHFUL_Pos)) /* Assignment of value for PFFHFUL in the ADC_CTLINTENCLR register */
+#define ADC_CTLINTENCLR_Msk                   _UINT32_(0x00000FC1)                                 /* (ADC_CTLINTENCLR) Register Mask  */
+
+#define ADC_CTLINTENCLR_CRRDY_Pos             _UINT32_(0)                                          /* (ADC_CTLINTENCLR Position) Core Ready x Disable */
+#define ADC_CTLINTENCLR_CRRDY_Msk             (_UINT32_(0x1) << ADC_CTLINTENCLR_CRRDY_Pos)         /* (ADC_CTLINTENCLR Mask) CRRDY */
+#define ADC_CTLINTENCLR_CRRDY(value)          (ADC_CTLINTENCLR_CRRDY_Msk & (_UINT32_(value) << ADC_CTLINTENCLR_CRRDY_Pos)) 
+
+/* -------- ADC_CTLINTFLAG : (ADC Offset: 0x104) (R/W 32) CORE Controller Interrupt Flags -------- */
+#define ADC_CTLINTFLAG_RESETVALUE             _UINT32_(0x00)                                       /*  (ADC_CTLINTFLAG) CORE Controller Interrupt Flags  Reset Value */
+
+#define ADC_CTLINTFLAG_CRRDY_Pos              _UINT32_(0)                                          /* (ADC_CTLINTFLAG) Core Ready Position */
+#define ADC_CTLINTFLAG_CRRDY_Msk              (_UINT32_(0xF) << ADC_CTLINTFLAG_CRRDY_Pos)          /* (ADC_CTLINTFLAG) Core Ready Mask */
+#define ADC_CTLINTFLAG_CRRDY(value)           (ADC_CTLINTFLAG_CRRDY_Msk & (_UINT32_(value) << ADC_CTLINTFLAG_CRRDY_Pos)) /* Assignment of value for CRRDY in the ADC_CTLINTFLAG register */
+#define ADC_CTLINTFLAG_VREFUPD_Pos            _UINT32_(6)                                          /* (ADC_CTLINTFLAG) VREF update Position */
+#define ADC_CTLINTFLAG_VREFUPD_Msk            (_UINT32_(0x1) << ADC_CTLINTFLAG_VREFUPD_Pos)        /* (ADC_CTLINTFLAG) VREF update Mask */
+#define ADC_CTLINTFLAG_VREFUPD(value)         (ADC_CTLINTFLAG_VREFUPD_Msk & (_UINT32_(value) << ADC_CTLINTFLAG_VREFUPD_Pos)) /* Assignment of value for VREFUPD in the ADC_CTLINTFLAG register */
+#define ADC_CTLINTFLAG_VREFRDY_Pos            _UINT32_(7)                                          /* (ADC_CTLINTFLAG) VREF Ready Position */
+#define ADC_CTLINTFLAG_VREFRDY_Msk            (_UINT32_(0x1) << ADC_CTLINTFLAG_VREFRDY_Pos)        /* (ADC_CTLINTFLAG) VREF Ready Mask */
+#define ADC_CTLINTFLAG_VREFRDY(value)         (ADC_CTLINTFLAG_VREFRDY_Msk & (_UINT32_(value) << ADC_CTLINTFLAG_VREFRDY_Pos)) /* Assignment of value for VREFRDY in the ADC_CTLINTFLAG register */
+#define ADC_CTLINTFLAG_PFFUNF_Pos             _UINT32_(8)                                          /* (ADC_CTLINTFLAG) APB FIFO underflow Position */
+#define ADC_CTLINTFLAG_PFFUNF_Msk             (_UINT32_(0x1) << ADC_CTLINTFLAG_PFFUNF_Pos)         /* (ADC_CTLINTFLAG) APB FIFO underflow Mask */
+#define ADC_CTLINTFLAG_PFFUNF(value)          (ADC_CTLINTFLAG_PFFUNF_Msk & (_UINT32_(value) << ADC_CTLINTFLAG_PFFUNF_Pos)) /* Assignment of value for PFFUNF in the ADC_CTLINTFLAG register */
+#define ADC_CTLINTFLAG_PFFOVF_Pos             _UINT32_(9)                                          /* (ADC_CTLINTFLAG) APB FIFO overflow Position */
+#define ADC_CTLINTFLAG_PFFOVF_Msk             (_UINT32_(0x1) << ADC_CTLINTFLAG_PFFOVF_Pos)         /* (ADC_CTLINTFLAG) APB FIFO overflow Mask */
+#define ADC_CTLINTFLAG_PFFOVF(value)          (ADC_CTLINTFLAG_PFFOVF_Msk & (_UINT32_(value) << ADC_CTLINTFLAG_PFFOVF_Pos)) /* Assignment of value for PFFOVF in the ADC_CTLINTFLAG register */
+#define ADC_CTLINTFLAG_PFFRDY_Pos             _UINT32_(10)                                         /* (ADC_CTLINTFLAG) APB FIFO Ready Position */
+#define ADC_CTLINTFLAG_PFFRDY_Msk             (_UINT32_(0x1) << ADC_CTLINTFLAG_PFFRDY_Pos)         /* (ADC_CTLINTFLAG) APB FIFO Ready Mask */
+#define ADC_CTLINTFLAG_PFFRDY(value)          (ADC_CTLINTFLAG_PFFRDY_Msk & (_UINT32_(value) << ADC_CTLINTFLAG_PFFRDY_Pos)) /* Assignment of value for PFFRDY in the ADC_CTLINTFLAG register */
+#define ADC_CTLINTFLAG_PFFHFUL_Pos            _UINT32_(11)                                         /* (ADC_CTLINTFLAG) APB FIFO Half Full Position */
+#define ADC_CTLINTFLAG_PFFHFUL_Msk            (_UINT32_(0x1) << ADC_CTLINTFLAG_PFFHFUL_Pos)        /* (ADC_CTLINTFLAG) APB FIFO Half Full Mask */
+#define ADC_CTLINTFLAG_PFFHFUL(value)         (ADC_CTLINTFLAG_PFFHFUL_Msk & (_UINT32_(value) << ADC_CTLINTFLAG_PFFHFUL_Pos)) /* Assignment of value for PFFHFUL in the ADC_CTLINTFLAG register */
+#define ADC_CTLINTFLAG_Msk                    _UINT32_(0x00000FCF)                                 /* (ADC_CTLINTFLAG) Register Mask  */
+
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x168) (R/W 32) Debug Control Register -------- */
+#define ADC_DBGCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (ADC_DBGCTRL) Debug Control Register  Reset Value */
+
+#define ADC_DBGCTRL_DBGRUN_Pos                _UINT32_(0)                                          /* (ADC_DBGCTRL) Debug Running State Position */
+#define ADC_DBGCTRL_DBGRUN_Msk                (_UINT32_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)            /* (ADC_DBGCTRL) Debug Running State Mask */
+#define ADC_DBGCTRL_DBGRUN(value)             (ADC_DBGCTRL_DBGRUN_Msk & (_UINT32_(value) << ADC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the ADC_DBGCTRL register */
+#define ADC_DBGCTRL_Msk                       _UINT32_(0x00000001)                                 /* (ADC_DBGCTRL) Register Mask  */
+
+
+/* ADC register offsets definitions */
+#define ADC_CORCTRL_REG_OFST           _UINT32_(0x00)      /* (ADC_CORCTRL) SARCORE Control Offset */
+#define ADC_CHNCFG1_REG_OFST           _UINT32_(0x04)      /* (ADC_CHNCFG1) Channel Configuration 1 (LVL/CMPEN) Offset */
+#define ADC_CHNCFG2_REG_OFST           _UINT32_(0x08)      /* (ADC_CHNCFG2) Channel Configuration 2(FRACT/CSS) Offset */
+#define ADC_CHNCFG3_REG_OFST           _UINT32_(0x0C)      /* (ADC_CHNCFG3) Channel Configuration3 (SIGN/DIFF) Offset */
+#define ADC_CHNCFG4_REG_OFST           _UINT32_(0x10)      /* (ADC_CHNCFG4) Channel Configuration 4 (TRGSRC) Offset */
+#define ADC_CHNCFG5_REG_OFST           _UINT32_(0x14)      /* (ADC_CHNCFG5) Channel Configuration 5 (TRGSRC) Offset */
+#define ADC_CALCTRL_REG_OFST           _UINT32_(0x18)      /* (ADC_CALCTRL) SARCORE Calibration Value Offset */
+#define ADC_EVCTRL_REG_OFST            _UINT32_(0x1C)      /* (ADC_EVCTRL) Event Control Offset */
+#define ADC_INTENCLR_REG_OFST          _UINT32_(0x00)      /* (ADC_INTENCLR) Interrupt Enable Clear Offset */
+#define ADC_INTENSET_REG_OFST          _UINT32_(0x04)      /* (ADC_INTENSET) Interrupt Enable Set Offset */
+#define ADC_INTFLAG_REG_OFST           _UINT32_(0x08)      /* (ADC_INTFLAG) Interrupt Flags Offset */
+#define ADC_CTRLA_REG_OFST             _UINT32_(0x00)      /* (ADC_CTRLA) CONTROL A REGISTER Offset */
+#define ADC_CTRLB_REG_OFST             _UINT32_(0x04)      /* (ADC_CTRLB) CONTROL B REGISTER Offset */
+#define ADC_CTRLC_REG_OFST             _UINT32_(0x08)      /* (ADC_CTRLC) Control C Register Offset */
+#define ADC_CTRLD_REG_OFST             _UINT32_(0x10)      /* (ADC_CTRLD) Control D Register Offset */
+#define ADC_CMPCTRL_REG_OFST           _UINT32_(0xB0)      /* (ADC_CMPCTRL) Comparator Control Offset */
+#define ADC_FLTCTRL_REG_OFST           _UINT32_(0xC0)      /* (ADC_FLTCTRL) Filter Control Offset */
+#define ADC_CORCHDATAID_REG_OFST       _UINT32_(0xD0)      /* (ADC_CORCHDATAID) Channel Ready DATA ID Offset */
+#define ADC_CHRDYDAT_REG_OFST          _UINT32_(0xD4)      /* (ADC_CHRDYDAT) Channel Ready Data Register Offset */
+#define ADC_PFFDATA_REG_OFST           _UINT32_(0xD8)      /* (ADC_PFFDATA) APB FIFO Output Data Offset */
+#define ADC_DMABASE_REG_OFST           _UINT32_(0xDC)      /* (ADC_DMABASE) DMA Sample Base Address Offset */
+#define ADC_DMACTRL_REG_OFST           _UINT32_(0xE0)      /* (ADC_DMACTRL) DMA Control Register Offset */
+#define ADC_PFFCTRL_REG_OFST           _UINT32_(0xE4)      /* (ADC_PFFCTRL) APB FIFO Control Register Offset */
+#define ADC_SYNCBUSY_REG_OFST          _UINT32_(0xE8)      /* (ADC_SYNCBUSY) CORE SYNC Busy Status Register Offset */
+#define ADC_DMAINTENCLR_REG_OFST       _UINT32_(0xF0)      /* (ADC_DMAINTENCLR) DMA Interrupt Enable Clear Offset */
+#define ADC_DMAINTSET_REG_OFST         _UINT32_(0xF4)      /* (ADC_DMAINTSET) DMA Interrupt Enable Set Offset */
+#define ADC_DMAINTFLAG_REG_OFST        _UINT32_(0xF8)      /* (ADC_DMAINTFLAG) DMA Interrupt Flag and Status Offset */
+#define ADC_CTLINTENSET_REG_OFST       _UINT32_(0xFC)      /* (ADC_CTLINTENSET) CORE Controller Interrupt Enable Set Offset */
+#define ADC_CTLINTENCLR_REG_OFST       _UINT32_(0x100)     /* (ADC_CTLINTENCLR) CORE Controller Interrupt Enable Clear Offset */
+#define ADC_CTLINTFLAG_REG_OFST        _UINT32_(0x104)     /* (ADC_CTLINTFLAG) CORE Controller Interrupt Flags Offset */
+#define ADC_DBGCTRL_REG_OFST           _UINT32_(0x168)     /* (ADC_DBGCTRL) Debug Control Register Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* CONFIG register API structure */
+typedef struct
+{
+  __IO  uint32_t                       ADC_CORCTRL;        /* Offset: 0x00 (R/W  32) SARCORE Control */
+  __IO  uint32_t                       ADC_CHNCFG1;        /* Offset: 0x04 (R/W  32) Channel Configuration 1 (LVL/CMPEN) */
+  __IO  uint32_t                       ADC_CHNCFG2;        /* Offset: 0x08 (R/W  32) Channel Configuration 2(FRACT/CSS) */
+  __IO  uint32_t                       ADC_CHNCFG3;        /* Offset: 0x0C (R/W  32) Channel Configuration3 (SIGN/DIFF) */
+  __IO  uint32_t                       ADC_CHNCFG4;        /* Offset: 0x10 (R/W  32) Channel Configuration 4 (TRGSRC) */
+  __IO  uint32_t                       ADC_CHNCFG5;        /* Offset: 0x14 (R/W  32) Channel Configuration 5 (TRGSRC) */
+  __IO  uint32_t                       ADC_CALCTRL;        /* Offset: 0x18 (R/W  32) SARCORE Calibration Value */
+  __IO  uint32_t                       ADC_EVCTRL;         /* Offset: 0x1C (R/W  32) Event Control */
+} adc_config_registers_t;
+
+/* INT register API structure */
+typedef struct
+{
+  __IO  uint32_t                       ADC_INTENCLR;       /* Offset: 0x00 (R/W  32) Interrupt Enable Clear */
+  __IO  uint32_t                       ADC_INTENSET;       /* Offset: 0x04 (R/W  32) Interrupt Enable Set */
+  __IO  uint32_t                       ADC_INTFLAG;        /* Offset: 0x08 (R/W  32) Interrupt Flags */
+  __I   uint8_t                        Reserved1[0x04];
+} adc_int_registers_t;
+
+#define ADC_CONFIG_NUMBER 1
+
+#define ADC_INT_NUMBER 1
+
+/* ADC register API structure */
+typedef struct
+{  /* ADC Controller */
+  __IO  uint32_t                       ADC_CTRLA;          /* Offset: 0x00 (R/W  32) CONTROL A REGISTER */
+  __IO  uint32_t                       ADC_CTRLB;          /* Offset: 0x04 (R/W  32) CONTROL B REGISTER */
+  __IO  uint32_t                       ADC_CTRLC;          /* Offset: 0x08 (R/W  32) Control C Register */
+  __I   uint8_t                        Reserved1[0x04];
+  __IO  uint32_t                       ADC_CTRLD;          /* Offset: 0x10 (R/W  32) Control D Register */
+  __I   uint8_t                        Reserved2[0x0C];
+        adc_config_registers_t         CONFIG[ADC_CONFIG_NUMBER]; /* Offset: 0x20  */
+  __I   uint8_t                        Reserved3[0x70];
+  __IO  uint32_t                       ADC_CMPCTRL;        /* Offset: 0xB0 (R/W  32) Comparator Control */
+  __I   uint8_t                        Reserved4[0x0C];
+  __IO  uint32_t                       ADC_FLTCTRL;        /* Offset: 0xC0 (R/W  32) Filter Control */
+  __I   uint8_t                        Reserved5[0x0C];
+  __IO  uint32_t                       ADC_CORCHDATAID;    /* Offset: 0xD0 (R/W  32) Channel Ready DATA ID */
+  __IO  uint32_t                       ADC_CHRDYDAT;       /* Offset: 0xD4 (R/W  32) Channel Ready Data Register */
+  __I   uint32_t                       ADC_PFFDATA;        /* Offset: 0xD8 (R/   32) APB FIFO Output Data */
+  __IO  uint32_t                       ADC_DMABASE;        /* Offset: 0xDC (R/W  32) DMA Sample Base Address */
+  __IO  uint32_t                       ADC_DMACTRL;        /* Offset: 0xE0 (R/W  32) DMA Control Register */
+  __IO  uint32_t                       ADC_PFFCTRL;        /* Offset: 0xE4 (R/W  32) APB FIFO Control Register */
+  __I   uint32_t                       ADC_SYNCBUSY;       /* Offset: 0xE8 (R/   32) CORE SYNC Busy Status Register */
+  __I   uint8_t                        Reserved6[0x04];
+  __IO  uint32_t                       ADC_DMAINTENCLR;    /* Offset: 0xF0 (R/W  32) DMA Interrupt Enable Clear */
+  __IO  uint32_t                       ADC_DMAINTSET;      /* Offset: 0xF4 (R/W  32) DMA Interrupt Enable Set */
+  __IO  uint32_t                       ADC_DMAINTFLAG;     /* Offset: 0xF8 (R/W  32) DMA Interrupt Flag and Status */
+  __IO  uint32_t                       ADC_CTLINTENSET;    /* Offset: 0xFC (R/W  32) CORE Controller Interrupt Enable Set */
+  __IO  uint32_t                       ADC_CTLINTENCLR;    /* Offset: 0x100 (R/W  32) CORE Controller Interrupt Enable Clear */
+  __IO  uint32_t                       ADC_CTLINTFLAG;     /* Offset: 0x104 (R/W  32) CORE Controller Interrupt Flags */
+  __I   uint8_t                        Reserved7[0x18];
+        adc_int_registers_t            INT[ADC_INT_NUMBER]; /* Offset: 0x120  */
+  __I   uint8_t                        Reserved8[0x38];
+  __IO  uint32_t                       ADC_DBGCTRL;        /* Offset: 0x168 (R/W  32) Debug Control Register */
+} adc_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_ADC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/at.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/at.h
new file mode 100644
index 00000000..9f82aaa7
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/at.h
@@ -0,0 +1,346 @@
+/*
+ * Component description for AT
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_AT_COMPONENT_H_
+#define _PIC32CMGC00_AT_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                       SOFTWARE API DEFINITION FOR AT                       */
+/* ************************************************************************** */
+
+/* -------- AT_CTRLA : (AT Offset: 0x00) (R/W 32) Control Register A -------- */
+#define AT_CTRLA_RESETVALUE                   _UINT32_(0x00)                                       /*  (AT_CTRLA) Control Register A  Reset Value */
+
+#define AT_CTRLA_SWRST_Pos                    _UINT32_(0)                                          /* (AT_CTRLA) Software Reset1 = Reset registers , Bus I/F and internal state0 = No effect Position */
+#define AT_CTRLA_SWRST_Msk                    (_UINT32_(0x1) << AT_CTRLA_SWRST_Pos)                /* (AT_CTRLA) Software Reset1 = Reset registers , Bus I/F and internal state0 = No effect Mask */
+#define AT_CTRLA_SWRST(value)                 (AT_CTRLA_SWRST_Msk & (_UINT32_(value) << AT_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the AT_CTRLA register */
+#define AT_CTRLA_PRIV_Pos                     _UINT32_(2)                                          /* (AT_CTRLA) Privileged Access Only Position */
+#define AT_CTRLA_PRIV_Msk                     (_UINT32_(0x1) << AT_CTRLA_PRIV_Pos)                 /* (AT_CTRLA) Privileged Access Only Mask */
+#define AT_CTRLA_PRIV(value)                  (AT_CTRLA_PRIV_Msk & (_UINT32_(value) << AT_CTRLA_PRIV_Pos)) /* Assignment of value for PRIV in the AT_CTRLA register */
+#define   AT_CTRLA_PRIV_0_Val                 _UINT32_(0x0)                                        /* (AT_CTRLA) AT registers accessible in privileged and unprivileged modes.  */
+#define   AT_CTRLA_PRIV_1_Val                 _UINT32_(0x1)                                        /* (AT_CTRLA) AT registers only accessible in privileged mode.  */
+#define AT_CTRLA_PRIV_0                       (AT_CTRLA_PRIV_0_Val << AT_CTRLA_PRIV_Pos)           /* (AT_CTRLA) AT registers accessible in privileged and unprivileged modes. Position */
+#define AT_CTRLA_PRIV_1                       (AT_CTRLA_PRIV_1_Val << AT_CTRLA_PRIV_Pos)           /* (AT_CTRLA) AT registers only accessible in privileged mode. Position */
+#define AT_CTRLA_RUNSTDBY_Pos                 _UINT32_(6)                                          /* (AT_CTRLA) RUNSTDBY Enable Bit Position */
+#define AT_CTRLA_RUNSTDBY_Msk                 (_UINT32_(0x1) << AT_CTRLA_RUNSTDBY_Pos)             /* (AT_CTRLA) RUNSTDBY Enable Bit Mask */
+#define AT_CTRLA_RUNSTDBY(value)              (AT_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << AT_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the AT_CTRLA register */
+#define AT_CTRLA_Msk                          _UINT32_(0x00000045)                                 /* (AT_CTRLA) Register Mask  */
+
+
+/* -------- AT_TAMPER_KEY : (AT Offset: 0x100) (R/W 32) Tamper Key n Register -------- */
+#define AT_TAMPER_KEY_RESETVALUE              _UINT32_(0x00)                                       /*  (AT_TAMPER_KEY) Tamper Key n Register  Reset Value */
+
+#define AT_TAMPER_KEY_TAMPERKEY_Pos           _UINT32_(0)                                          /* (AT_TAMPER_KEY) Tamper Key Value Position */
+#define AT_TAMPER_KEY_TAMPERKEY_Msk           (_UINT32_(0xFFFFFFFF) << AT_TAMPER_KEY_TAMPERKEY_Pos) /* (AT_TAMPER_KEY) Tamper Key Value Mask */
+#define AT_TAMPER_KEY_TAMPERKEY(value)        (AT_TAMPER_KEY_TAMPERKEY_Msk & (_UINT32_(value) << AT_TAMPER_KEY_TAMPERKEY_Pos)) /* Assignment of value for TAMPERKEY in the AT_TAMPER_KEY register */
+#define AT_TAMPER_KEY_Msk                     _UINT32_(0xFFFFFFFF)                                 /* (AT_TAMPER_KEY) Register Mask  */
+
+
+/* -------- AT_anti_tamper__LEVELA : (AT Offset: 0x200) ( R/ 32) Tamper levels 0 to 7. -------- */
+#define AT_anti_tamper__LEVELA_RESETVALUE     _UINT32_(0x00)                                       /*  (AT_anti_tamper__LEVELA) Tamper levels 0 to 7.  Reset Value */
+
+#define AT_anti_tamper__LEVELA_LEVEL0_Pos     _UINT32_(0)                                          /* (AT_anti_tamper__LEVELA) Level 0. Position */
+#define AT_anti_tamper__LEVELA_LEVEL0_Msk     (_UINT32_(0xF) << AT_anti_tamper__LEVELA_LEVEL0_Pos) /* (AT_anti_tamper__LEVELA) Level 0. Mask */
+#define AT_anti_tamper__LEVELA_LEVEL0(value)  (AT_anti_tamper__LEVELA_LEVEL0_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELA_LEVEL0_Pos)) /* Assignment of value for LEVEL0 in the AT_anti_tamper__LEVELA register */
+#define AT_anti_tamper__LEVELA_LEVEL1_Pos     _UINT32_(4)                                          /* (AT_anti_tamper__LEVELA) Level 1. Position */
+#define AT_anti_tamper__LEVELA_LEVEL1_Msk     (_UINT32_(0xF) << AT_anti_tamper__LEVELA_LEVEL1_Pos) /* (AT_anti_tamper__LEVELA) Level 1. Mask */
+#define AT_anti_tamper__LEVELA_LEVEL1(value)  (AT_anti_tamper__LEVELA_LEVEL1_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELA_LEVEL1_Pos)) /* Assignment of value for LEVEL1 in the AT_anti_tamper__LEVELA register */
+#define AT_anti_tamper__LEVELA_LEVEL2_Pos     _UINT32_(8)                                          /* (AT_anti_tamper__LEVELA) Level 2. Position */
+#define AT_anti_tamper__LEVELA_LEVEL2_Msk     (_UINT32_(0xF) << AT_anti_tamper__LEVELA_LEVEL2_Pos) /* (AT_anti_tamper__LEVELA) Level 2. Mask */
+#define AT_anti_tamper__LEVELA_LEVEL2(value)  (AT_anti_tamper__LEVELA_LEVEL2_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELA_LEVEL2_Pos)) /* Assignment of value for LEVEL2 in the AT_anti_tamper__LEVELA register */
+#define AT_anti_tamper__LEVELA_LEVEL3_Pos     _UINT32_(12)                                         /* (AT_anti_tamper__LEVELA) Level 3. Position */
+#define AT_anti_tamper__LEVELA_LEVEL3_Msk     (_UINT32_(0xF) << AT_anti_tamper__LEVELA_LEVEL3_Pos) /* (AT_anti_tamper__LEVELA) Level 3. Mask */
+#define AT_anti_tamper__LEVELA_LEVEL3(value)  (AT_anti_tamper__LEVELA_LEVEL3_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELA_LEVEL3_Pos)) /* Assignment of value for LEVEL3 in the AT_anti_tamper__LEVELA register */
+#define AT_anti_tamper__LEVELA_LEVEL4_Pos     _UINT32_(16)                                         /* (AT_anti_tamper__LEVELA) Level 4. Position */
+#define AT_anti_tamper__LEVELA_LEVEL4_Msk     (_UINT32_(0xF) << AT_anti_tamper__LEVELA_LEVEL4_Pos) /* (AT_anti_tamper__LEVELA) Level 4. Mask */
+#define AT_anti_tamper__LEVELA_LEVEL4(value)  (AT_anti_tamper__LEVELA_LEVEL4_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELA_LEVEL4_Pos)) /* Assignment of value for LEVEL4 in the AT_anti_tamper__LEVELA register */
+#define AT_anti_tamper__LEVELA_LEVEL5_Pos     _UINT32_(20)                                         /* (AT_anti_tamper__LEVELA) Level 5. Position */
+#define AT_anti_tamper__LEVELA_LEVEL5_Msk     (_UINT32_(0xF) << AT_anti_tamper__LEVELA_LEVEL5_Pos) /* (AT_anti_tamper__LEVELA) Level 5. Mask */
+#define AT_anti_tamper__LEVELA_LEVEL5(value)  (AT_anti_tamper__LEVELA_LEVEL5_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELA_LEVEL5_Pos)) /* Assignment of value for LEVEL5 in the AT_anti_tamper__LEVELA register */
+#define AT_anti_tamper__LEVELA_LEVEL6_Pos     _UINT32_(24)                                         /* (AT_anti_tamper__LEVELA) Level 6. Position */
+#define AT_anti_tamper__LEVELA_LEVEL6_Msk     (_UINT32_(0xF) << AT_anti_tamper__LEVELA_LEVEL6_Pos) /* (AT_anti_tamper__LEVELA) Level 6. Mask */
+#define AT_anti_tamper__LEVELA_LEVEL6(value)  (AT_anti_tamper__LEVELA_LEVEL6_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELA_LEVEL6_Pos)) /* Assignment of value for LEVEL6 in the AT_anti_tamper__LEVELA register */
+#define AT_anti_tamper__LEVELA_LEVEL7_Pos     _UINT32_(28)                                         /* (AT_anti_tamper__LEVELA) Level 7. Position */
+#define AT_anti_tamper__LEVELA_LEVEL7_Msk     (_UINT32_(0xF) << AT_anti_tamper__LEVELA_LEVEL7_Pos) /* (AT_anti_tamper__LEVELA) Level 7. Mask */
+#define AT_anti_tamper__LEVELA_LEVEL7(value)  (AT_anti_tamper__LEVELA_LEVEL7_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELA_LEVEL7_Pos)) /* Assignment of value for LEVEL7 in the AT_anti_tamper__LEVELA register */
+#define AT_anti_tamper__LEVELA_Msk            _UINT32_(0xFFFFFFFF)                                 /* (AT_anti_tamper__LEVELA) Register Mask  */
+
+
+/* -------- AT_anti_tamper__LEVELB : (AT Offset: 0x204) ( R/ 32) Tamper levels 8 to 15. -------- */
+#define AT_anti_tamper__LEVELB_RESETVALUE     _UINT32_(0x00)                                       /*  (AT_anti_tamper__LEVELB) Tamper levels 8 to 15.  Reset Value */
+
+#define AT_anti_tamper__LEVELB_LEVEL8_Pos     _UINT32_(0)                                          /* (AT_anti_tamper__LEVELB) Level 8. Position */
+#define AT_anti_tamper__LEVELB_LEVEL8_Msk     (_UINT32_(0xF) << AT_anti_tamper__LEVELB_LEVEL8_Pos) /* (AT_anti_tamper__LEVELB) Level 8. Mask */
+#define AT_anti_tamper__LEVELB_LEVEL8(value)  (AT_anti_tamper__LEVELB_LEVEL8_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELB_LEVEL8_Pos)) /* Assignment of value for LEVEL8 in the AT_anti_tamper__LEVELB register */
+#define AT_anti_tamper__LEVELB_LEVEL9_Pos     _UINT32_(4)                                          /* (AT_anti_tamper__LEVELB) Level 9. Position */
+#define AT_anti_tamper__LEVELB_LEVEL9_Msk     (_UINT32_(0xF) << AT_anti_tamper__LEVELB_LEVEL9_Pos) /* (AT_anti_tamper__LEVELB) Level 9. Mask */
+#define AT_anti_tamper__LEVELB_LEVEL9(value)  (AT_anti_tamper__LEVELB_LEVEL9_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELB_LEVEL9_Pos)) /* Assignment of value for LEVEL9 in the AT_anti_tamper__LEVELB register */
+#define AT_anti_tamper__LEVELB_LEVEL10_Pos    _UINT32_(8)                                          /* (AT_anti_tamper__LEVELB) Level 10. Position */
+#define AT_anti_tamper__LEVELB_LEVEL10_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELB_LEVEL10_Pos) /* (AT_anti_tamper__LEVELB) Level 10. Mask */
+#define AT_anti_tamper__LEVELB_LEVEL10(value) (AT_anti_tamper__LEVELB_LEVEL10_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELB_LEVEL10_Pos)) /* Assignment of value for LEVEL10 in the AT_anti_tamper__LEVELB register */
+#define AT_anti_tamper__LEVELB_LEVEL11_Pos    _UINT32_(12)                                         /* (AT_anti_tamper__LEVELB) Level 11. Position */
+#define AT_anti_tamper__LEVELB_LEVEL11_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELB_LEVEL11_Pos) /* (AT_anti_tamper__LEVELB) Level 11. Mask */
+#define AT_anti_tamper__LEVELB_LEVEL11(value) (AT_anti_tamper__LEVELB_LEVEL11_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELB_LEVEL11_Pos)) /* Assignment of value for LEVEL11 in the AT_anti_tamper__LEVELB register */
+#define AT_anti_tamper__LEVELB_LEVEL12_Pos    _UINT32_(16)                                         /* (AT_anti_tamper__LEVELB) Level 12. Position */
+#define AT_anti_tamper__LEVELB_LEVEL12_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELB_LEVEL12_Pos) /* (AT_anti_tamper__LEVELB) Level 12. Mask */
+#define AT_anti_tamper__LEVELB_LEVEL12(value) (AT_anti_tamper__LEVELB_LEVEL12_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELB_LEVEL12_Pos)) /* Assignment of value for LEVEL12 in the AT_anti_tamper__LEVELB register */
+#define AT_anti_tamper__LEVELB_LEVEL13_Pos    _UINT32_(20)                                         /* (AT_anti_tamper__LEVELB) Level 13. Position */
+#define AT_anti_tamper__LEVELB_LEVEL13_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELB_LEVEL13_Pos) /* (AT_anti_tamper__LEVELB) Level 13. Mask */
+#define AT_anti_tamper__LEVELB_LEVEL13(value) (AT_anti_tamper__LEVELB_LEVEL13_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELB_LEVEL13_Pos)) /* Assignment of value for LEVEL13 in the AT_anti_tamper__LEVELB register */
+#define AT_anti_tamper__LEVELB_LEVEL14_Pos    _UINT32_(24)                                         /* (AT_anti_tamper__LEVELB) Level 14. Position */
+#define AT_anti_tamper__LEVELB_LEVEL14_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELB_LEVEL14_Pos) /* (AT_anti_tamper__LEVELB) Level 14. Mask */
+#define AT_anti_tamper__LEVELB_LEVEL14(value) (AT_anti_tamper__LEVELB_LEVEL14_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELB_LEVEL14_Pos)) /* Assignment of value for LEVEL14 in the AT_anti_tamper__LEVELB register */
+#define AT_anti_tamper__LEVELB_LEVEL15_Pos    _UINT32_(28)                                         /* (AT_anti_tamper__LEVELB) Level 15. Position */
+#define AT_anti_tamper__LEVELB_LEVEL15_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELB_LEVEL15_Pos) /* (AT_anti_tamper__LEVELB) Level 15. Mask */
+#define AT_anti_tamper__LEVELB_LEVEL15(value) (AT_anti_tamper__LEVELB_LEVEL15_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELB_LEVEL15_Pos)) /* Assignment of value for LEVEL15 in the AT_anti_tamper__LEVELB register */
+#define AT_anti_tamper__LEVELB_Msk            _UINT32_(0xFFFFFFFF)                                 /* (AT_anti_tamper__LEVELB) Register Mask  */
+
+
+/* -------- AT_anti_tamper__LEVELC : (AT Offset: 0x208) ( R/ 32) Tamper levels 16 to 23. -------- */
+#define AT_anti_tamper__LEVELC_RESETVALUE     _UINT32_(0x00)                                       /*  (AT_anti_tamper__LEVELC) Tamper levels 16 to 23.  Reset Value */
+
+#define AT_anti_tamper__LEVELC_LEVEL16_Pos    _UINT32_(0)                                          /* (AT_anti_tamper__LEVELC) Level 16. Position */
+#define AT_anti_tamper__LEVELC_LEVEL16_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELC_LEVEL16_Pos) /* (AT_anti_tamper__LEVELC) Level 16. Mask */
+#define AT_anti_tamper__LEVELC_LEVEL16(value) (AT_anti_tamper__LEVELC_LEVEL16_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELC_LEVEL16_Pos)) /* Assignment of value for LEVEL16 in the AT_anti_tamper__LEVELC register */
+#define AT_anti_tamper__LEVELC_LEVEL17_Pos    _UINT32_(4)                                          /* (AT_anti_tamper__LEVELC) Level 17. Position */
+#define AT_anti_tamper__LEVELC_LEVEL17_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELC_LEVEL17_Pos) /* (AT_anti_tamper__LEVELC) Level 17. Mask */
+#define AT_anti_tamper__LEVELC_LEVEL17(value) (AT_anti_tamper__LEVELC_LEVEL17_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELC_LEVEL17_Pos)) /* Assignment of value for LEVEL17 in the AT_anti_tamper__LEVELC register */
+#define AT_anti_tamper__LEVELC_LEVEL18_Pos    _UINT32_(8)                                          /* (AT_anti_tamper__LEVELC) Level 18. Position */
+#define AT_anti_tamper__LEVELC_LEVEL18_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELC_LEVEL18_Pos) /* (AT_anti_tamper__LEVELC) Level 18. Mask */
+#define AT_anti_tamper__LEVELC_LEVEL18(value) (AT_anti_tamper__LEVELC_LEVEL18_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELC_LEVEL18_Pos)) /* Assignment of value for LEVEL18 in the AT_anti_tamper__LEVELC register */
+#define AT_anti_tamper__LEVELC_LEVEL19_Pos    _UINT32_(12)                                         /* (AT_anti_tamper__LEVELC) Level 19. Position */
+#define AT_anti_tamper__LEVELC_LEVEL19_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELC_LEVEL19_Pos) /* (AT_anti_tamper__LEVELC) Level 19. Mask */
+#define AT_anti_tamper__LEVELC_LEVEL19(value) (AT_anti_tamper__LEVELC_LEVEL19_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELC_LEVEL19_Pos)) /* Assignment of value for LEVEL19 in the AT_anti_tamper__LEVELC register */
+#define AT_anti_tamper__LEVELC_LEVEL20_Pos    _UINT32_(16)                                         /* (AT_anti_tamper__LEVELC) Level 20. Position */
+#define AT_anti_tamper__LEVELC_LEVEL20_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELC_LEVEL20_Pos) /* (AT_anti_tamper__LEVELC) Level 20. Mask */
+#define AT_anti_tamper__LEVELC_LEVEL20(value) (AT_anti_tamper__LEVELC_LEVEL20_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELC_LEVEL20_Pos)) /* Assignment of value for LEVEL20 in the AT_anti_tamper__LEVELC register */
+#define AT_anti_tamper__LEVELC_LEVEL21_Pos    _UINT32_(20)                                         /* (AT_anti_tamper__LEVELC) Level 21. Position */
+#define AT_anti_tamper__LEVELC_LEVEL21_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELC_LEVEL21_Pos) /* (AT_anti_tamper__LEVELC) Level 21. Mask */
+#define AT_anti_tamper__LEVELC_LEVEL21(value) (AT_anti_tamper__LEVELC_LEVEL21_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELC_LEVEL21_Pos)) /* Assignment of value for LEVEL21 in the AT_anti_tamper__LEVELC register */
+#define AT_anti_tamper__LEVELC_LEVEL22_Pos    _UINT32_(24)                                         /* (AT_anti_tamper__LEVELC) Level 22. Position */
+#define AT_anti_tamper__LEVELC_LEVEL22_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELC_LEVEL22_Pos) /* (AT_anti_tamper__LEVELC) Level 22. Mask */
+#define AT_anti_tamper__LEVELC_LEVEL22(value) (AT_anti_tamper__LEVELC_LEVEL22_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELC_LEVEL22_Pos)) /* Assignment of value for LEVEL22 in the AT_anti_tamper__LEVELC register */
+#define AT_anti_tamper__LEVELC_LEVEL23_Pos    _UINT32_(28)                                         /* (AT_anti_tamper__LEVELC) Level 23. Position */
+#define AT_anti_tamper__LEVELC_LEVEL23_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELC_LEVEL23_Pos) /* (AT_anti_tamper__LEVELC) Level 23. Mask */
+#define AT_anti_tamper__LEVELC_LEVEL23(value) (AT_anti_tamper__LEVELC_LEVEL23_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELC_LEVEL23_Pos)) /* Assignment of value for LEVEL23 in the AT_anti_tamper__LEVELC register */
+#define AT_anti_tamper__LEVELC_Msk            _UINT32_(0xFFFFFFFF)                                 /* (AT_anti_tamper__LEVELC) Register Mask  */
+
+
+/* -------- AT_anti_tamper__LEVELD : (AT Offset: 0x20C) ( R/ 32) Tamper levels 24 to 31. -------- */
+#define AT_anti_tamper__LEVELD_RESETVALUE     _UINT32_(0x00)                                       /*  (AT_anti_tamper__LEVELD) Tamper levels 24 to 31.  Reset Value */
+
+#define AT_anti_tamper__LEVELD_LEVEL24_Pos    _UINT32_(0)                                          /* (AT_anti_tamper__LEVELD) Level 24. Position */
+#define AT_anti_tamper__LEVELD_LEVEL24_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELD_LEVEL24_Pos) /* (AT_anti_tamper__LEVELD) Level 24. Mask */
+#define AT_anti_tamper__LEVELD_LEVEL24(value) (AT_anti_tamper__LEVELD_LEVEL24_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELD_LEVEL24_Pos)) /* Assignment of value for LEVEL24 in the AT_anti_tamper__LEVELD register */
+#define AT_anti_tamper__LEVELD_LEVEL25_Pos    _UINT32_(4)                                          /* (AT_anti_tamper__LEVELD) Level 25. Position */
+#define AT_anti_tamper__LEVELD_LEVEL25_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELD_LEVEL25_Pos) /* (AT_anti_tamper__LEVELD) Level 25. Mask */
+#define AT_anti_tamper__LEVELD_LEVEL25(value) (AT_anti_tamper__LEVELD_LEVEL25_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELD_LEVEL25_Pos)) /* Assignment of value for LEVEL25 in the AT_anti_tamper__LEVELD register */
+#define AT_anti_tamper__LEVELD_LEVEL26_Pos    _UINT32_(8)                                          /* (AT_anti_tamper__LEVELD) Level 26. Position */
+#define AT_anti_tamper__LEVELD_LEVEL26_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELD_LEVEL26_Pos) /* (AT_anti_tamper__LEVELD) Level 26. Mask */
+#define AT_anti_tamper__LEVELD_LEVEL26(value) (AT_anti_tamper__LEVELD_LEVEL26_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELD_LEVEL26_Pos)) /* Assignment of value for LEVEL26 in the AT_anti_tamper__LEVELD register */
+#define AT_anti_tamper__LEVELD_LEVEL27_Pos    _UINT32_(12)                                         /* (AT_anti_tamper__LEVELD) Level 27. Position */
+#define AT_anti_tamper__LEVELD_LEVEL27_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELD_LEVEL27_Pos) /* (AT_anti_tamper__LEVELD) Level 27. Mask */
+#define AT_anti_tamper__LEVELD_LEVEL27(value) (AT_anti_tamper__LEVELD_LEVEL27_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELD_LEVEL27_Pos)) /* Assignment of value for LEVEL27 in the AT_anti_tamper__LEVELD register */
+#define AT_anti_tamper__LEVELD_LEVEL28_Pos    _UINT32_(16)                                         /* (AT_anti_tamper__LEVELD) Level 28. Position */
+#define AT_anti_tamper__LEVELD_LEVEL28_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELD_LEVEL28_Pos) /* (AT_anti_tamper__LEVELD) Level 28. Mask */
+#define AT_anti_tamper__LEVELD_LEVEL28(value) (AT_anti_tamper__LEVELD_LEVEL28_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELD_LEVEL28_Pos)) /* Assignment of value for LEVEL28 in the AT_anti_tamper__LEVELD register */
+#define AT_anti_tamper__LEVELD_LEVEL29_Pos    _UINT32_(20)                                         /* (AT_anti_tamper__LEVELD) Level 29. Position */
+#define AT_anti_tamper__LEVELD_LEVEL29_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELD_LEVEL29_Pos) /* (AT_anti_tamper__LEVELD) Level 29. Mask */
+#define AT_anti_tamper__LEVELD_LEVEL29(value) (AT_anti_tamper__LEVELD_LEVEL29_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELD_LEVEL29_Pos)) /* Assignment of value for LEVEL29 in the AT_anti_tamper__LEVELD register */
+#define AT_anti_tamper__LEVELD_LEVEL30_Pos    _UINT32_(24)                                         /* (AT_anti_tamper__LEVELD) Level 30. Position */
+#define AT_anti_tamper__LEVELD_LEVEL30_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELD_LEVEL30_Pos) /* (AT_anti_tamper__LEVELD) Level 30. Mask */
+#define AT_anti_tamper__LEVELD_LEVEL30(value) (AT_anti_tamper__LEVELD_LEVEL30_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELD_LEVEL30_Pos)) /* Assignment of value for LEVEL30 in the AT_anti_tamper__LEVELD register */
+#define AT_anti_tamper__LEVELD_LEVEL31_Pos    _UINT32_(28)                                         /* (AT_anti_tamper__LEVELD) Level 31. Position */
+#define AT_anti_tamper__LEVELD_LEVEL31_Msk    (_UINT32_(0xF) << AT_anti_tamper__LEVELD_LEVEL31_Pos) /* (AT_anti_tamper__LEVELD) Level 31. Mask */
+#define AT_anti_tamper__LEVELD_LEVEL31(value) (AT_anti_tamper__LEVELD_LEVEL31_Msk & (_UINT32_(value) << AT_anti_tamper__LEVELD_LEVEL31_Pos)) /* Assignment of value for LEVEL31 in the AT_anti_tamper__LEVELD register */
+#define AT_anti_tamper__LEVELD_Msk            _UINT32_(0xFFFFFFFF)                                 /* (AT_anti_tamper__LEVELD) Register Mask  */
+
+
+/* -------- AT_anti_tamper__SETLEVEL : (AT Offset: 0x210) ( /W 32) Set tamper level. -------- */
+#define AT_anti_tamper__SETLEVEL_RESETVALUE   _UINT32_(0x00)                                       /*  (AT_anti_tamper__SETLEVEL) Set tamper level.  Reset Value */
+
+#define AT_anti_tamper__SETLEVEL_LEVEL_Pos    _UINT32_(0)                                          /* (AT_anti_tamper__SETLEVEL) Tamper level. Position */
+#define AT_anti_tamper__SETLEVEL_LEVEL_Msk    (_UINT32_(0x7) << AT_anti_tamper__SETLEVEL_LEVEL_Pos) /* (AT_anti_tamper__SETLEVEL) Tamper level. Mask */
+#define AT_anti_tamper__SETLEVEL_LEVEL(value) (AT_anti_tamper__SETLEVEL_LEVEL_Msk & (_UINT32_(value) << AT_anti_tamper__SETLEVEL_LEVEL_Pos)) /* Assignment of value for LEVEL in the AT_anti_tamper__SETLEVEL register */
+#define AT_anti_tamper__SETLEVEL_ID_Pos       _UINT32_(8)                                          /* (AT_anti_tamper__SETLEVEL) Tamper ID. Position */
+#define AT_anti_tamper__SETLEVEL_ID_Msk       (_UINT32_(0x1F) << AT_anti_tamper__SETLEVEL_ID_Pos)  /* (AT_anti_tamper__SETLEVEL) Tamper ID. Mask */
+#define AT_anti_tamper__SETLEVEL_ID(value)    (AT_anti_tamper__SETLEVEL_ID_Msk & (_UINT32_(value) << AT_anti_tamper__SETLEVEL_ID_Pos)) /* Assignment of value for ID in the AT_anti_tamper__SETLEVEL register */
+#define AT_anti_tamper__SETLEVEL_PROTKEY_Pos  _UINT32_(16)                                         /* (AT_anti_tamper__SETLEVEL) Protection key (0xA84C). Position */
+#define AT_anti_tamper__SETLEVEL_PROTKEY_Msk  (_UINT32_(0xFFFF) << AT_anti_tamper__SETLEVEL_PROTKEY_Pos) /* (AT_anti_tamper__SETLEVEL) Protection key (0xA84C). Mask */
+#define AT_anti_tamper__SETLEVEL_PROTKEY(value) (AT_anti_tamper__SETLEVEL_PROTKEY_Msk & (_UINT32_(value) << AT_anti_tamper__SETLEVEL_PROTKEY_Pos)) /* Assignment of value for PROTKEY in the AT_anti_tamper__SETLEVEL register */
+#define AT_anti_tamper__SETLEVEL_Msk          _UINT32_(0xFFFF1F07)                                 /* (AT_anti_tamper__SETLEVEL) Register Mask  */
+
+
+/* -------- AT_anti_tamper__FILTERCFG : (AT Offset: 0x214) (R/W 32) Filter configuration (threshold, period). -------- */
+#define AT_anti_tamper__FILTERCFG_RESETVALUE  _UINT32_(0x00)                                       /*  (AT_anti_tamper__FILTERCFG) Filter configuration (threshold, period).  Reset Value */
+
+#define AT_anti_tamper__FILTERCFG_THRESH_Pos  _UINT32_(0)                                          /* (AT_anti_tamper__FILTERCFG) Threshold. Position */
+#define AT_anti_tamper__FILTERCFG_THRESH_Msk  (_UINT32_(0x7) << AT_anti_tamper__FILTERCFG_THRESH_Pos) /* (AT_anti_tamper__FILTERCFG) Threshold. Mask */
+#define AT_anti_tamper__FILTERCFG_THRESH(value) (AT_anti_tamper__FILTERCFG_THRESH_Msk & (_UINT32_(value) << AT_anti_tamper__FILTERCFG_THRESH_Pos)) /* Assignment of value for THRESH in the AT_anti_tamper__FILTERCFG register */
+#define AT_anti_tamper__FILTERCFG_PERIOD_Pos  _UINT32_(8)                                          /* (AT_anti_tamper__FILTERCFG) Period. Position */
+#define AT_anti_tamper__FILTERCFG_PERIOD_Msk  (_UINT32_(0x1F) << AT_anti_tamper__FILTERCFG_PERIOD_Pos) /* (AT_anti_tamper__FILTERCFG) Period. Mask */
+#define AT_anti_tamper__FILTERCFG_PERIOD(value) (AT_anti_tamper__FILTERCFG_PERIOD_Msk & (_UINT32_(value) << AT_anti_tamper__FILTERCFG_PERIOD_Pos)) /* Assignment of value for PERIOD in the AT_anti_tamper__FILTERCFG register */
+#define AT_anti_tamper__FILTERCFG_PROTKEY_Pos _UINT32_(16)                                         /* (AT_anti_tamper__FILTERCFG) Protection key (0x92F5). Position */
+#define AT_anti_tamper__FILTERCFG_PROTKEY_Msk (_UINT32_(0xFFFF) << AT_anti_tamper__FILTERCFG_PROTKEY_Pos) /* (AT_anti_tamper__FILTERCFG) Protection key (0x92F5). Mask */
+#define AT_anti_tamper__FILTERCFG_PROTKEY(value) (AT_anti_tamper__FILTERCFG_PROTKEY_Msk & (_UINT32_(value) << AT_anti_tamper__FILTERCFG_PROTKEY_Pos)) /* Assignment of value for PROTKEY in the AT_anti_tamper__FILTERCFG register */
+#define AT_anti_tamper__FILTERCFG_Msk         _UINT32_(0xFFFF1F07)                                 /* (AT_anti_tamper__FILTERCFG) Register Mask  */
+
+
+/* -------- AT_anti_tamper__SOFTTAMP : (AT Offset: 0x218) (R/W 32) Software triggered tamper. -------- */
+#define AT_anti_tamper__SOFTTAMP_RESETVALUE   _UINT32_(0x00)                                       /*  (AT_anti_tamper__SOFTTAMP) Software triggered tamper.  Reset Value */
+
+#define AT_anti_tamper__SOFTTAMP_ACTIVE_Pos   _UINT32_(0)                                          /* (AT_anti_tamper__SOFTTAMP) Tamper active. Position */
+#define AT_anti_tamper__SOFTTAMP_ACTIVE_Msk   (_UINT32_(0x1) << AT_anti_tamper__SOFTTAMP_ACTIVE_Pos) /* (AT_anti_tamper__SOFTTAMP) Tamper active. Mask */
+#define AT_anti_tamper__SOFTTAMP_ACTIVE(value) (AT_anti_tamper__SOFTTAMP_ACTIVE_Msk & (_UINT32_(value) << AT_anti_tamper__SOFTTAMP_ACTIVE_Pos)) /* Assignment of value for ACTIVE in the AT_anti_tamper__SOFTTAMP register */
+#define AT_anti_tamper__SOFTTAMP_ID_Pos       _UINT32_(8)                                          /* (AT_anti_tamper__SOFTTAMP) Tamper ID. Position */
+#define AT_anti_tamper__SOFTTAMP_ID_Msk       (_UINT32_(0x1F) << AT_anti_tamper__SOFTTAMP_ID_Pos)  /* (AT_anti_tamper__SOFTTAMP) Tamper ID. Mask */
+#define AT_anti_tamper__SOFTTAMP_ID(value)    (AT_anti_tamper__SOFTTAMP_ID_Msk & (_UINT32_(value) << AT_anti_tamper__SOFTTAMP_ID_Pos)) /* Assignment of value for ID in the AT_anti_tamper__SOFTTAMP register */
+#define AT_anti_tamper__SOFTTAMP_PROTKEY_Pos  _UINT32_(16)                                         /* (AT_anti_tamper__SOFTTAMP) Protection key (0x4BEE). Position */
+#define AT_anti_tamper__SOFTTAMP_PROTKEY_Msk  (_UINT32_(0xFFFF) << AT_anti_tamper__SOFTTAMP_PROTKEY_Pos) /* (AT_anti_tamper__SOFTTAMP) Protection key (0x4BEE). Mask */
+#define AT_anti_tamper__SOFTTAMP_PROTKEY(value) (AT_anti_tamper__SOFTTAMP_PROTKEY_Msk & (_UINT32_(value) << AT_anti_tamper__SOFTTAMP_PROTKEY_Pos)) /* Assignment of value for PROTKEY in the AT_anti_tamper__SOFTTAMP register */
+#define AT_anti_tamper__SOFTTAMP_Msk          _UINT32_(0xFFFF1F01)                                 /* (AT_anti_tamper__SOFTTAMP) Register Mask  */
+
+
+/* -------- AT_anti_tamper__RAWSTAT : (AT Offset: 0x21C) ( R/ 32) Raw status. -------- */
+#define AT_anti_tamper__RAWSTAT_RESETVALUE    _UINT32_(0x00)                                       /*  (AT_anti_tamper__RAWSTAT) Raw status.  Reset Value */
+
+#define AT_anti_tamper__RAWSTAT_RAWSTAT_Pos   _UINT32_(0)                                          /* (AT_anti_tamper__RAWSTAT) Raw status. Position */
+#define AT_anti_tamper__RAWSTAT_RAWSTAT_Msk   (_UINT32_(0xFFFFFFFF) << AT_anti_tamper__RAWSTAT_RAWSTAT_Pos) /* (AT_anti_tamper__RAWSTAT) Raw status. Mask */
+#define AT_anti_tamper__RAWSTAT_RAWSTAT(value) (AT_anti_tamper__RAWSTAT_RAWSTAT_Msk & (_UINT32_(value) << AT_anti_tamper__RAWSTAT_RAWSTAT_Pos)) /* Assignment of value for RAWSTAT in the AT_anti_tamper__RAWSTAT register */
+#define AT_anti_tamper__RAWSTAT_Msk           _UINT32_(0xFFFFFFFF)                                 /* (AT_anti_tamper__RAWSTAT) Register Mask  */
+
+
+/* -------- AT_anti_tamper__STAT : (AT Offset: 0x220) (R/W 32) Status (write to clear). -------- */
+#define AT_anti_tamper__STAT_RESETVALUE       _UINT32_(0x01)                                       /*  (AT_anti_tamper__STAT) Status (write to clear).  Reset Value */
+
+#define AT_anti_tamper__STAT_STAT_Pos         _UINT32_(0)                                          /* (AT_anti_tamper__STAT) Status (write to clear). Position */
+#define AT_anti_tamper__STAT_STAT_Msk         (_UINT32_(0xFFFFFFFF) << AT_anti_tamper__STAT_STAT_Pos) /* (AT_anti_tamper__STAT) Status (write to clear). Mask */
+#define AT_anti_tamper__STAT_STAT(value)      (AT_anti_tamper__STAT_STAT_Msk & (_UINT32_(value) << AT_anti_tamper__STAT_STAT_Pos)) /* Assignment of value for STAT in the AT_anti_tamper__STAT register */
+#define AT_anti_tamper__STAT_Msk              _UINT32_(0xFFFFFFFF)                                 /* (AT_anti_tamper__STAT) Register Mask  */
+
+
+/* -------- AT_anti_tamper__TIMESTAMP : (AT Offset: 0x224) ( R/ 32) Timestamp for the last tamper. -------- */
+#define AT_anti_tamper__TIMESTAMP_RESETVALUE  _UINT32_(0x00)                                       /*  (AT_anti_tamper__TIMESTAMP) Timestamp for the last tamper.  Reset Value */
+
+#define AT_anti_tamper__TIMESTAMP_TIMESTAMP_Pos _UINT32_(0)                                          /* (AT_anti_tamper__TIMESTAMP) Timestamp for the last tamper. Position */
+#define AT_anti_tamper__TIMESTAMP_TIMESTAMP_Msk (_UINT32_(0xFFFFFFFF) << AT_anti_tamper__TIMESTAMP_TIMESTAMP_Pos) /* (AT_anti_tamper__TIMESTAMP) Timestamp for the last tamper. Mask */
+#define AT_anti_tamper__TIMESTAMP_TIMESTAMP(value) (AT_anti_tamper__TIMESTAMP_TIMESTAMP_Msk & (_UINT32_(value) << AT_anti_tamper__TIMESTAMP_TIMESTAMP_Pos)) /* Assignment of value for TIMESTAMP in the AT_anti_tamper__TIMESTAMP register */
+#define AT_anti_tamper__TIMESTAMP_Msk         _UINT32_(0xFFFFFFFF)                                 /* (AT_anti_tamper__TIMESTAMP) Register Mask  */
+
+
+/* -------- AT_anti_tamper__FILTERCNT : (AT Offset: 0x228) ( R/ 32) Current value of filter counter. -------- */
+#define AT_anti_tamper__FILTERCNT_RESETVALUE  _UINT32_(0x00)                                       /*  (AT_anti_tamper__FILTERCNT) Current value of filter counter.  Reset Value */
+
+#define AT_anti_tamper__FILTERCNT_FILTERCNT_Pos _UINT32_(0)                                          /* (AT_anti_tamper__FILTERCNT) Current value of filter counter. Position */
+#define AT_anti_tamper__FILTERCNT_FILTERCNT_Msk (_UINT32_(0xFFFFFFFF) << AT_anti_tamper__FILTERCNT_FILTERCNT_Pos) /* (AT_anti_tamper__FILTERCNT) Current value of filter counter. Mask */
+#define AT_anti_tamper__FILTERCNT_FILTERCNT(value) (AT_anti_tamper__FILTERCNT_FILTERCNT_Msk & (_UINT32_(value) << AT_anti_tamper__FILTERCNT_FILTERCNT_Pos)) /* Assignment of value for FILTERCNT in the AT_anti_tamper__FILTERCNT register */
+#define AT_anti_tamper__FILTERCNT_Msk         _UINT32_(0xFFFFFFFF)                                 /* (AT_anti_tamper__FILTERCNT) Register Mask  */
+
+
+/* -------- AT_anti_tamper__SOFTINFO : (AT Offset: 0x22C) (R/W 32) Register for software purpose only. -------- */
+#define AT_anti_tamper__SOFTINFO_RESETVALUE   _UINT32_(0x00)                                       /*  (AT_anti_tamper__SOFTINFO) Register for software purpose only.  Reset Value */
+
+#define AT_anti_tamper__SOFTINFO_SOFTINFO_Pos _UINT32_(0)                                          /* (AT_anti_tamper__SOFTINFO) Register for software purpose only. Position */
+#define AT_anti_tamper__SOFTINFO_SOFTINFO_Msk (_UINT32_(0xFFFFFFFF) << AT_anti_tamper__SOFTINFO_SOFTINFO_Pos) /* (AT_anti_tamper__SOFTINFO) Register for software purpose only. Mask */
+#define AT_anti_tamper__SOFTINFO_SOFTINFO(value) (AT_anti_tamper__SOFTINFO_SOFTINFO_Msk & (_UINT32_(value) << AT_anti_tamper__SOFTINFO_SOFTINFO_Pos)) /* Assignment of value for SOFTINFO in the AT_anti_tamper__SOFTINFO register */
+#define AT_anti_tamper__SOFTINFO_Msk          _UINT32_(0xFFFFFFFF)                                 /* (AT_anti_tamper__SOFTINFO) Register Mask  */
+
+
+/* -------- AT_anti_tamper__TAMPERFLAG : (AT Offset: 0x230) (R/W 32) The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output. -------- */
+#define AT_anti_tamper__TAMPERFLAG_RESETVALUE _UINT32_(0x00)                                       /*  (AT_anti_tamper__TAMPERFLAG) The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output.  Reset Value */
+
+#define AT_anti_tamper__TAMPERFLAG_TAMPERFLAG_Pos _UINT32_(0)                                          /* (AT_anti_tamper__TAMPERFLAG) The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output. Position */
+#define AT_anti_tamper__TAMPERFLAG_TAMPERFLAG_Msk (_UINT32_(0x1) << AT_anti_tamper__TAMPERFLAG_TAMPERFLAG_Pos) /* (AT_anti_tamper__TAMPERFLAG) The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output. Mask */
+#define AT_anti_tamper__TAMPERFLAG_TAMPERFLAG(value) (AT_anti_tamper__TAMPERFLAG_TAMPERFLAG_Msk & (_UINT32_(value) << AT_anti_tamper__TAMPERFLAG_TAMPERFLAG_Pos)) /* Assignment of value for TAMPERFLAG in the AT_anti_tamper__TAMPERFLAG register */
+#define AT_anti_tamper__TAMPERFLAG_Msk        _UINT32_(0x00000001)                                 /* (AT_anti_tamper__TAMPERFLAG) Register Mask  */
+
+
+/* -------- AT_anti_tamper__SOFTRESET : (AT Offset: 0x234) ( R/ 32) Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above. -------- */
+#define AT_anti_tamper__SOFTRESET_RESETVALUE  _UINT32_(0x00)                                       /*  (AT_anti_tamper__SOFTRESET) Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above.  Reset Value */
+
+#define AT_anti_tamper__SOFTRESET_SOFTRESET_Pos _UINT32_(0)                                          /* (AT_anti_tamper__SOFTRESET) Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above. Position */
+#define AT_anti_tamper__SOFTRESET_SOFTRESET_Msk (_UINT32_(0x1) << AT_anti_tamper__SOFTRESET_SOFTRESET_Pos) /* (AT_anti_tamper__SOFTRESET) Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above. Mask */
+#define AT_anti_tamper__SOFTRESET_SOFTRESET(value) (AT_anti_tamper__SOFTRESET_SOFTRESET_Msk & (_UINT32_(value) << AT_anti_tamper__SOFTRESET_SOFTRESET_Pos)) /* Assignment of value for SOFTRESET in the AT_anti_tamper__SOFTRESET register */
+#define AT_anti_tamper__SOFTRESET_Msk         _UINT32_(0x00000001)                                 /* (AT_anti_tamper__SOFTRESET) Register Mask  */
+
+
+/* AT register offsets definitions */
+#define AT_CTRLA_REG_OFST              _UINT32_(0x00)      /* (AT_CTRLA) Control Register A Offset */
+#define AT_TAMPER_KEY_REG_OFST         _UINT32_(0x100)     /* (AT_TAMPER_KEY) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY0_REG_OFST        _UINT32_(0x100)     /* (AT_TAMPER_KEY0) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY1_REG_OFST        _UINT32_(0x104)     /* (AT_TAMPER_KEY1) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY2_REG_OFST        _UINT32_(0x108)     /* (AT_TAMPER_KEY2) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY3_REG_OFST        _UINT32_(0x10C)     /* (AT_TAMPER_KEY3) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY4_REG_OFST        _UINT32_(0x110)     /* (AT_TAMPER_KEY4) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY5_REG_OFST        _UINT32_(0x114)     /* (AT_TAMPER_KEY5) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY6_REG_OFST        _UINT32_(0x118)     /* (AT_TAMPER_KEY6) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY7_REG_OFST        _UINT32_(0x11C)     /* (AT_TAMPER_KEY7) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY8_REG_OFST        _UINT32_(0x120)     /* (AT_TAMPER_KEY8) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY9_REG_OFST        _UINT32_(0x124)     /* (AT_TAMPER_KEY9) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY10_REG_OFST       _UINT32_(0x128)     /* (AT_TAMPER_KEY10) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY11_REG_OFST       _UINT32_(0x12C)     /* (AT_TAMPER_KEY11) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY12_REG_OFST       _UINT32_(0x130)     /* (AT_TAMPER_KEY12) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY13_REG_OFST       _UINT32_(0x134)     /* (AT_TAMPER_KEY13) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY14_REG_OFST       _UINT32_(0x138)     /* (AT_TAMPER_KEY14) Tamper Key n Register Offset */
+#define AT_TAMPER_KEY15_REG_OFST       _UINT32_(0x13C)     /* (AT_TAMPER_KEY15) Tamper Key n Register Offset */
+#define AT_anti_tamper__LEVELA_REG_OFST _UINT32_(0x200)     /* (AT_anti_tamper__LEVELA) Tamper levels 0 to 7. Offset */
+#define AT_anti_tamper__LEVELB_REG_OFST _UINT32_(0x204)     /* (AT_anti_tamper__LEVELB) Tamper levels 8 to 15. Offset */
+#define AT_anti_tamper__LEVELC_REG_OFST _UINT32_(0x208)     /* (AT_anti_tamper__LEVELC) Tamper levels 16 to 23. Offset */
+#define AT_anti_tamper__LEVELD_REG_OFST _UINT32_(0x20C)     /* (AT_anti_tamper__LEVELD) Tamper levels 24 to 31. Offset */
+#define AT_anti_tamper__SETLEVEL_REG_OFST _UINT32_(0x210)     /* (AT_anti_tamper__SETLEVEL) Set tamper level. Offset */
+#define AT_anti_tamper__FILTERCFG_REG_OFST _UINT32_(0x214)     /* (AT_anti_tamper__FILTERCFG) Filter configuration (threshold, period). Offset */
+#define AT_anti_tamper__SOFTTAMP_REG_OFST _UINT32_(0x218)     /* (AT_anti_tamper__SOFTTAMP) Software triggered tamper. Offset */
+#define AT_anti_tamper__RAWSTAT_REG_OFST _UINT32_(0x21C)     /* (AT_anti_tamper__RAWSTAT) Raw status. Offset */
+#define AT_anti_tamper__STAT_REG_OFST  _UINT32_(0x220)     /* (AT_anti_tamper__STAT) Status (write to clear). Offset */
+#define AT_anti_tamper__TIMESTAMP_REG_OFST _UINT32_(0x224)     /* (AT_anti_tamper__TIMESTAMP) Timestamp for the last tamper. Offset */
+#define AT_anti_tamper__FILTERCNT_REG_OFST _UINT32_(0x228)     /* (AT_anti_tamper__FILTERCNT) Current value of filter counter. Offset */
+#define AT_anti_tamper__SOFTINFO_REG_OFST _UINT32_(0x22C)     /* (AT_anti_tamper__SOFTINFO) Register for software purpose only. Offset */
+#define AT_anti_tamper__TAMPERFLAG_REG_OFST _UINT32_(0x230)     /* (AT_anti_tamper__TAMPERFLAG) The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output. Offset */
+#define AT_anti_tamper__SOFTRESET_REG_OFST _UINT32_(0x234)     /* (AT_anti_tamper__SOFTRESET) Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above. Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* AT register API structure */
+typedef struct
+{  /* Anti-Tamper Controller (AT) */
+  __IO  uint32_t                       AT_CTRLA;           /* Offset: 0x00 (R/W  32) Control Register A */
+  __I   uint8_t                        Reserved1[0xFC];
+  __IO  uint32_t                       AT_TAMPER_KEY[16];  /* Offset: 0x100 (R/W  32) Tamper Key n Register */
+  __I   uint8_t                        Reserved2[0xC0];
+  __I   uint32_t                       AT_anti_tamper__LEVELA; /* Offset: 0x200 (R/   32) Tamper levels 0 to 7. */
+  __I   uint32_t                       AT_anti_tamper__LEVELB; /* Offset: 0x204 (R/   32) Tamper levels 8 to 15. */
+  __I   uint32_t                       AT_anti_tamper__LEVELC; /* Offset: 0x208 (R/   32) Tamper levels 16 to 23. */
+  __I   uint32_t                       AT_anti_tamper__LEVELD; /* Offset: 0x20C (R/   32) Tamper levels 24 to 31. */
+  __O   uint32_t                       AT_anti_tamper__SETLEVEL; /* Offset: 0x210 ( /W  32) Set tamper level. */
+  __IO  uint32_t                       AT_anti_tamper__FILTERCFG; /* Offset: 0x214 (R/W  32) Filter configuration (threshold, period). */
+  __IO  uint32_t                       AT_anti_tamper__SOFTTAMP; /* Offset: 0x218 (R/W  32) Software triggered tamper. */
+  __I   uint32_t                       AT_anti_tamper__RAWSTAT; /* Offset: 0x21C (R/   32) Raw status. */
+  __IO  uint32_t                       AT_anti_tamper__STAT; /* Offset: 0x220 (R/W  32) Status (write to clear). */
+  __I   uint32_t                       AT_anti_tamper__TIMESTAMP; /* Offset: 0x224 (R/   32) Timestamp for the last tamper. */
+  __I   uint32_t                       AT_anti_tamper__FILTERCNT; /* Offset: 0x228 (R/   32) Current value of filter counter. */
+  __IO  uint32_t                       AT_anti_tamper__SOFTINFO; /* Offset: 0x22C (R/W  32) Register for software purpose only. */
+  __IO  uint32_t                       AT_anti_tamper__TAMPERFLAG; /* Offset: 0x230 (R/W  32) The 1-bit TAMPERFLAG register directly controls the TAMPER_FLAG output. */
+  __I   uint32_t                       AT_anti_tamper__SOFTRESET; /* Offset: 0x234 (R/   32) Reading the SOFTLVL4 register returns 1 if any active soft tamper has a level of 4 or above. */
+} at_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_AT_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/bromc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/bromc.h
new file mode 100644
index 00000000..daca39cb
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/bromc.h
@@ -0,0 +1,91 @@
+/*
+ * Component description for BROMC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_BROMC_COMPONENT_H_
+#define _PIC32CMGC00_BROMC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                     SOFTWARE API DEFINITION FOR BROMC                      */
+/* ************************************************************************** */
+
+/* -------- BROMC_CTRLA : (BROMC Offset: 0x00) (R/W 32) Control A REGISTER -------- */
+#define BROMC_CTRLA_RESETVALUE                _UINT32_(0x02)                                       /*  (BROMC_CTRLA) Control A REGISTER  Reset Value */
+
+#define BROMC_CTRLA_SWRST_Pos                 _UINT32_(0)                                          /* (BROMC_CTRLA) Software Reset bit Position */
+#define BROMC_CTRLA_SWRST_Msk                 (_UINT32_(0x1) << BROMC_CTRLA_SWRST_Pos)             /* (BROMC_CTRLA) Software Reset bit Mask */
+#define BROMC_CTRLA_SWRST(value)              (BROMC_CTRLA_SWRST_Msk & (_UINT32_(value) << BROMC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the BROMC_CTRLA register */
+#define BROMC_CTRLA_ENABLE_Pos                _UINT32_(1)                                          /* (BROMC_CTRLA) Enable bit Position */
+#define BROMC_CTRLA_ENABLE_Msk                (_UINT32_(0x1) << BROMC_CTRLA_ENABLE_Pos)            /* (BROMC_CTRLA) Enable bit Mask */
+#define BROMC_CTRLA_ENABLE(value)             (BROMC_CTRLA_ENABLE_Msk & (_UINT32_(value) << BROMC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the BROMC_CTRLA register */
+#define   BROMC_CTRLA_ENABLE_0_Val            _UINT32_(0x0)                                        /* (BROMC_CTRLA) Disable ROM read access and power down the ROM. The ROM PGEN input is driven high. The ROM will clamp outputs to 1 and disable all internal current sinks. Refer to the ROM compiler specification for details on powering down the ROM.  */
+#define   BROMC_CTRLA_ENABLE_1_Val            _UINT32_(0x1)                                        /* (BROMC_CTRLA) Enable ROM read access, power up the ROM. The ROM PGEN input is driven low.  */
+#define BROMC_CTRLA_ENABLE_0                  (BROMC_CTRLA_ENABLE_0_Val << BROMC_CTRLA_ENABLE_Pos) /* (BROMC_CTRLA) Disable ROM read access and power down the ROM. The ROM PGEN input is driven high. The ROM will clamp outputs to 1 and disable all internal current sinks. Refer to the ROM compiler specification for details on powering down the ROM. Position */
+#define BROMC_CTRLA_ENABLE_1                  (BROMC_CTRLA_ENABLE_1_Val << BROMC_CTRLA_ENABLE_Pos) /* (BROMC_CTRLA) Enable ROM read access, power up the ROM. The ROM PGEN input is driven low. Position */
+#define BROMC_CTRLA_PRIV_Pos                  _UINT32_(2)                                          /* (BROMC_CTRLA) Privileged Access Only Position */
+#define BROMC_CTRLA_PRIV_Msk                  (_UINT32_(0x1) << BROMC_CTRLA_PRIV_Pos)              /* (BROMC_CTRLA) Privileged Access Only Mask */
+#define BROMC_CTRLA_PRIV(value)               (BROMC_CTRLA_PRIV_Msk & (_UINT32_(value) << BROMC_CTRLA_PRIV_Pos)) /* Assignment of value for PRIV in the BROMC_CTRLA register */
+#define   BROMC_CTRLA_PRIV_0_Val              _UINT32_(0x0)                                        /* (BROMC_CTRLA) Macro register accessible in privileged and unprivileged modes  */
+#define   BROMC_CTRLA_PRIV_1_Val              _UINT32_(0x1)                                        /* (BROMC_CTRLA) Macro registers only accessible in privileged mode  */
+#define BROMC_CTRLA_PRIV_0                    (BROMC_CTRLA_PRIV_0_Val << BROMC_CTRLA_PRIV_Pos)     /* (BROMC_CTRLA) Macro register accessible in privileged and unprivileged modes Position */
+#define BROMC_CTRLA_PRIV_1                    (BROMC_CTRLA_PRIV_1_Val << BROMC_CTRLA_PRIV_Pos)     /* (BROMC_CTRLA) Macro registers only accessible in privileged mode Position */
+#define BROMC_CTRLA_PRMWS_Pos                 _UINT32_(8)                                          /* (BROMC_CTRLA) ROM Access Time Wait State Position */
+#define BROMC_CTRLA_PRMWS_Msk                 (_UINT32_(0x7) << BROMC_CTRLA_PRMWS_Pos)             /* (BROMC_CTRLA) ROM Access Time Wait State Mask */
+#define BROMC_CTRLA_PRMWS(value)              (BROMC_CTRLA_PRMWS_Msk & (_UINT32_(value) << BROMC_CTRLA_PRMWS_Pos)) /* Assignment of value for PRMWS in the BROMC_CTRLA register */
+#define   BROMC_CTRLA_PRMWS_0_Val             _UINT32_(0x0)                                        /* (BROMC_CTRLA) No wait states, single cycle access  */
+#define   BROMC_CTRLA_PRMWS_1_Val             _UINT32_(0x1)                                        /* (BROMC_CTRLA) Access time extended 2 clock cycles  */
+#define   BROMC_CTRLA_PRMWS_2_Val             _UINT32_(0x2)                                        /* (BROMC_CTRLA) Access time extended to 3 clock cycles  */
+#define   BROMC_CTRLA_PRMWS_7_Val             _UINT32_(0x7)                                        /* (BROMC_CTRLA) Access time extended to 8 clock cycles  */
+#define BROMC_CTRLA_PRMWS_0                   (BROMC_CTRLA_PRMWS_0_Val << BROMC_CTRLA_PRMWS_Pos)   /* (BROMC_CTRLA) No wait states, single cycle access Position */
+#define BROMC_CTRLA_PRMWS_1                   (BROMC_CTRLA_PRMWS_1_Val << BROMC_CTRLA_PRMWS_Pos)   /* (BROMC_CTRLA) Access time extended 2 clock cycles Position */
+#define BROMC_CTRLA_PRMWS_2                   (BROMC_CTRLA_PRMWS_2_Val << BROMC_CTRLA_PRMWS_Pos)   /* (BROMC_CTRLA) Access time extended to 3 clock cycles Position */
+#define BROMC_CTRLA_PRMWS_7                   (BROMC_CTRLA_PRMWS_7_Val << BROMC_CTRLA_PRMWS_Pos)   /* (BROMC_CTRLA) Access time extended to 8 clock cycles Position */
+#define BROMC_CTRLA_Msk                       _UINT32_(0x00000707)                                 /* (BROMC_CTRLA) Register Mask  */
+
+
+/* -------- BROMC_UCFG : (BROMC Offset: 0x04) ( R/ 32) User Configuration REGISTER -------- */
+#define BROMC_UCFG_RESETVALUE                 _UINT32_(0x01)                                       /*  (BROMC_UCFG) User Configuration REGISTER  Reset Value */
+
+#define BROMC_UCFG_BCRCDIS_Pos                _UINT32_(0)                                          /* (BROMC_UCFG) Boot CRC Disable Position */
+#define BROMC_UCFG_BCRCDIS_Msk                (_UINT32_(0x1) << BROMC_UCFG_BCRCDIS_Pos)            /* (BROMC_UCFG) Boot CRC Disable Mask */
+#define BROMC_UCFG_BCRCDIS(value)             (BROMC_UCFG_BCRCDIS_Msk & (_UINT32_(value) << BROMC_UCFG_BCRCDIS_Pos)) /* Assignment of value for BCRCDIS in the BROMC_UCFG register */
+#define   BROMC_UCFG_BCRCDIS_0_Val            _UINT32_(0x0)                                        /* (BROMC_UCFG) Boot ROM content is CRC verified by the ROM controller, status is reported to the DSU. On CRC failure, the controller blocks access to the ROM controller.  */
+#define   BROMC_UCFG_BCRCDIS_1_Val            _UINT32_(0x1)                                        /* (BROMC_UCFG) No CRC verification at Boot.  */
+#define BROMC_UCFG_BCRCDIS_0                  (BROMC_UCFG_BCRCDIS_0_Val << BROMC_UCFG_BCRCDIS_Pos) /* (BROMC_UCFG) Boot ROM content is CRC verified by the ROM controller, status is reported to the DSU. On CRC failure, the controller blocks access to the ROM controller. Position */
+#define BROMC_UCFG_BCRCDIS_1                  (BROMC_UCFG_BCRCDIS_1_Val << BROMC_UCFG_BCRCDIS_Pos) /* (BROMC_UCFG) No CRC verification at Boot. Position */
+#define BROMC_UCFG_Msk                        _UINT32_(0x00000001)                                 /* (BROMC_UCFG) Register Mask  */
+
+
+/* BROMC register offsets definitions */
+#define BROMC_CTRLA_REG_OFST           _UINT32_(0x00)      /* (BROMC_CTRLA) Control A REGISTER Offset */
+#define BROMC_UCFG_REG_OFST            _UINT32_(0x04)      /* (BROMC_UCFG) User Configuration REGISTER Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* BROMC register API structure */
+typedef struct
+{  /* ARM GF55LPx Boot ROM Controller Macro */
+  __IO  uint32_t                       BROMC_CTRLA;        /* Offset: 0x00 (R/W  32) Control A REGISTER */
+  __I   uint32_t                       BROMC_UCFG;         /* Offset: 0x04 (R/   32) User Configuration REGISTER */
+} bromc_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_BROMC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/can.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/can.h
new file mode 100644
index 00000000..8f154afa
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/can.h
@@ -0,0 +1,2797 @@
+/*
+ * Component description for CAN
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_CAN_COMPONENT_H_
+#define _PIC32CMGC00_CAN_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR CAN                       */
+/* ************************************************************************** */
+
+/* -------- CAN_R0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer and FIFO Element 0 -------- */
+#define CAN_R0_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_R0) Rx Buffer and FIFO Element 0  Reset Value */
+
+#define CAN_R0_ID_Pos                         _UINT32_(0)                                          /* (CAN_R0) Identifier Position */
+#define CAN_R0_ID_Msk                         (_UINT32_(0x1FFFFFFF) << CAN_R0_ID_Pos)              /* (CAN_R0) Identifier Mask */
+#define CAN_R0_ID(value)                      (CAN_R0_ID_Msk & (_UINT32_(value) << CAN_R0_ID_Pos)) /* Assignment of value for ID in the CAN_R0 register */
+#define CAN_R0_RTR_Pos                        _UINT32_(29)                                         /* (CAN_R0) Remote Transmission Request Position */
+#define CAN_R0_RTR_Msk                        (_UINT32_(0x1) << CAN_R0_RTR_Pos)                    /* (CAN_R0) Remote Transmission Request Mask */
+#define CAN_R0_RTR(value)                     (CAN_R0_RTR_Msk & (_UINT32_(value) << CAN_R0_RTR_Pos)) /* Assignment of value for RTR in the CAN_R0 register */
+#define CAN_R0_XTD_Pos                        _UINT32_(30)                                         /* (CAN_R0) Extended Identifier Position */
+#define CAN_R0_XTD_Msk                        (_UINT32_(0x1) << CAN_R0_XTD_Pos)                    /* (CAN_R0) Extended Identifier Mask */
+#define CAN_R0_XTD(value)                     (CAN_R0_XTD_Msk & (_UINT32_(value) << CAN_R0_XTD_Pos)) /* Assignment of value for XTD in the CAN_R0 register */
+#define CAN_R0_ESI_Pos                        _UINT32_(31)                                         /* (CAN_R0) Error State Indicator Position */
+#define CAN_R0_ESI_Msk                        (_UINT32_(0x1) << CAN_R0_ESI_Pos)                    /* (CAN_R0) Error State Indicator Mask */
+#define CAN_R0_ESI(value)                     (CAN_R0_ESI_Msk & (_UINT32_(value) << CAN_R0_ESI_Pos)) /* Assignment of value for ESI in the CAN_R0 register */
+#define CAN_R0_Msk                            _UINT32_(0xFFFFFFFF)                                 /* (CAN_R0) Register Mask  */
+
+
+/* -------- CAN_R1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer and FIFO Element 1 -------- */
+#define CAN_R1_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_R1) Rx Buffer and FIFO Element 1  Reset Value */
+
+#define CAN_R1_RXTS_Pos                       _UINT32_(0)                                          /* (CAN_R1) Rx Timestamp Position */
+#define CAN_R1_RXTS_Msk                       (_UINT32_(0xFFFF) << CAN_R1_RXTS_Pos)                /* (CAN_R1) Rx Timestamp Mask */
+#define CAN_R1_RXTS(value)                    (CAN_R1_RXTS_Msk & (_UINT32_(value) << CAN_R1_RXTS_Pos)) /* Assignment of value for RXTS in the CAN_R1 register */
+#define CAN_R1_DLC_Pos                        _UINT32_(16)                                         /* (CAN_R1) Data Length Code Position */
+#define CAN_R1_DLC_Msk                        (_UINT32_(0xF) << CAN_R1_DLC_Pos)                    /* (CAN_R1) Data Length Code Mask */
+#define CAN_R1_DLC(value)                     (CAN_R1_DLC_Msk & (_UINT32_(value) << CAN_R1_DLC_Pos)) /* Assignment of value for DLC in the CAN_R1 register */
+#define CAN_R1_BRS_Pos                        _UINT32_(20)                                         /* (CAN_R1) Bit Rate Search Position */
+#define CAN_R1_BRS_Msk                        (_UINT32_(0x1) << CAN_R1_BRS_Pos)                    /* (CAN_R1) Bit Rate Search Mask */
+#define CAN_R1_BRS(value)                     (CAN_R1_BRS_Msk & (_UINT32_(value) << CAN_R1_BRS_Pos)) /* Assignment of value for BRS in the CAN_R1 register */
+#define CAN_R1_FDF_Pos                        _UINT32_(21)                                         /* (CAN_R1) FD Format Position */
+#define CAN_R1_FDF_Msk                        (_UINT32_(0x1) << CAN_R1_FDF_Pos)                    /* (CAN_R1) FD Format Mask */
+#define CAN_R1_FDF(value)                     (CAN_R1_FDF_Msk & (_UINT32_(value) << CAN_R1_FDF_Pos)) /* Assignment of value for FDF in the CAN_R1 register */
+#define CAN_R1_FIDX_Pos                       _UINT32_(24)                                         /* (CAN_R1) Filter Index Position */
+#define CAN_R1_FIDX_Msk                       (_UINT32_(0x7F) << CAN_R1_FIDX_Pos)                  /* (CAN_R1) Filter Index Mask */
+#define CAN_R1_FIDX(value)                    (CAN_R1_FIDX_Msk & (_UINT32_(value) << CAN_R1_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_R1 register */
+#define CAN_R1_ANMF_Pos                       _UINT32_(31)                                         /* (CAN_R1) Accepted Non-matching Frame Position */
+#define CAN_R1_ANMF_Msk                       (_UINT32_(0x1) << CAN_R1_ANMF_Pos)                   /* (CAN_R1) Accepted Non-matching Frame Mask */
+#define CAN_R1_ANMF(value)                    (CAN_R1_ANMF_Msk & (_UINT32_(value) << CAN_R1_ANMF_Pos)) /* Assignment of value for ANMF in the CAN_R1 register */
+#define CAN_R1_Msk                            _UINT32_(0xFF3FFFFF)                                 /* (CAN_R1) Register Mask  */
+
+
+/* -------- CAN_R2 : (CAN Offset: 0x08) (R/W 32) Rx Buffer and FIFO Element Data -------- */
+#define CAN_R2_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_R2) Rx Buffer and FIFO Element Data  Reset Value */
+
+#define CAN_R2_DB0_Pos                        _UINT32_(0)                                          /* (CAN_R2) Data Byte 0 Position */
+#define CAN_R2_DB0_Msk                        (_UINT32_(0xFF) << CAN_R2_DB0_Pos)                   /* (CAN_R2) Data Byte 0 Mask */
+#define CAN_R2_DB0(value)                     (CAN_R2_DB0_Msk & (_UINT32_(value) << CAN_R2_DB0_Pos)) /* Assignment of value for DB0 in the CAN_R2 register */
+#define CAN_R2_DB1_Pos                        _UINT32_(8)                                          /* (CAN_R2) Data Byte 1 Position */
+#define CAN_R2_DB1_Msk                        (_UINT32_(0xFF) << CAN_R2_DB1_Pos)                   /* (CAN_R2) Data Byte 1 Mask */
+#define CAN_R2_DB1(value)                     (CAN_R2_DB1_Msk & (_UINT32_(value) << CAN_R2_DB1_Pos)) /* Assignment of value for DB1 in the CAN_R2 register */
+#define CAN_R2_DB2_Pos                        _UINT32_(16)                                         /* (CAN_R2) Data Byte 2 Position */
+#define CAN_R2_DB2_Msk                        (_UINT32_(0xFF) << CAN_R2_DB2_Pos)                   /* (CAN_R2) Data Byte 2 Mask */
+#define CAN_R2_DB2(value)                     (CAN_R2_DB2_Msk & (_UINT32_(value) << CAN_R2_DB2_Pos)) /* Assignment of value for DB2 in the CAN_R2 register */
+#define CAN_R2_DB3_Pos                        _UINT32_(24)                                         /* (CAN_R2) Data Byte 3 Position */
+#define CAN_R2_DB3_Msk                        (_UINT32_(0xFF) << CAN_R2_DB3_Pos)                   /* (CAN_R2) Data Byte 3 Mask */
+#define CAN_R2_DB3(value)                     (CAN_R2_DB3_Msk & (_UINT32_(value) << CAN_R2_DB3_Pos)) /* Assignment of value for DB3 in the CAN_R2 register */
+#define CAN_R2_Msk                            _UINT32_(0xFFFFFFFF)                                 /* (CAN_R2) Register Mask  */
+
+
+/* -------- CAN_S0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */
+#define CAN_S0_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_S0) Standard Message ID Filter Element  Reset Value */
+
+#define CAN_S0_SFID2_Pos                      _UINT32_(0)                                          /* (CAN_S0) Standard Filter ID 2 Position */
+#define CAN_S0_SFID2_Msk                      (_UINT32_(0x7FF) << CAN_S0_SFID2_Pos)                /* (CAN_S0) Standard Filter ID 2 Mask */
+#define CAN_S0_SFID2(value)                   (CAN_S0_SFID2_Msk & (_UINT32_(value) << CAN_S0_SFID2_Pos)) /* Assignment of value for SFID2 in the CAN_S0 register */
+#define CAN_S0_SFID1_Pos                      _UINT32_(16)                                         /* (CAN_S0) Standard Filter ID 1 Position */
+#define CAN_S0_SFID1_Msk                      (_UINT32_(0x7FF) << CAN_S0_SFID1_Pos)                /* (CAN_S0) Standard Filter ID 1 Mask */
+#define CAN_S0_SFID1(value)                   (CAN_S0_SFID1_Msk & (_UINT32_(value) << CAN_S0_SFID1_Pos)) /* Assignment of value for SFID1 in the CAN_S0 register */
+#define CAN_S0_SFEC_Pos                       _UINT32_(27)                                         /* (CAN_S0) Standard Filter Element Configuration Position */
+#define CAN_S0_SFEC_Msk                       (_UINT32_(0x7) << CAN_S0_SFEC_Pos)                   /* (CAN_S0) Standard Filter Element Configuration Mask */
+#define CAN_S0_SFEC(value)                    (CAN_S0_SFEC_Msk & (_UINT32_(value) << CAN_S0_SFEC_Pos)) /* Assignment of value for SFEC in the CAN_S0 register */
+#define   CAN_S0_SFEC_DISABLE_Val             _UINT32_(0x0)                                        /* (CAN_S0) Disable filter element  */
+#define   CAN_S0_SFEC_STF0M_Val               _UINT32_(0x1)                                        /* (CAN_S0) Store in Rx FIFO 0 if filter match  */
+#define   CAN_S0_SFEC_STF1M_Val               _UINT32_(0x2)                                        /* (CAN_S0) Store in Rx FIFO 1 if filter match  */
+#define   CAN_S0_SFEC_REJECT_Val              _UINT32_(0x3)                                        /* (CAN_S0) Reject ID if filter match  */
+#define   CAN_S0_SFEC_PRIORITY_Val            _UINT32_(0x4)                                        /* (CAN_S0) Set priority if filter match  */
+#define   CAN_S0_SFEC_PRIF0M_Val              _UINT32_(0x5)                                        /* (CAN_S0) Set priority and store in FIFO 0 if filter match  */
+#define   CAN_S0_SFEC_PRIF1M_Val              _UINT32_(0x6)                                        /* (CAN_S0) Set priority and store in FIFO 1 if filter match  */
+#define   CAN_S0_SFEC_STRXBUF_Val             _UINT32_(0x7)                                        /* (CAN_S0) Store into Rx Buffer  */
+#define CAN_S0_SFEC_DISABLE                   (CAN_S0_SFEC_DISABLE_Val << CAN_S0_SFEC_Pos)         /* (CAN_S0) Disable filter element Position */
+#define CAN_S0_SFEC_STF0M                     (CAN_S0_SFEC_STF0M_Val << CAN_S0_SFEC_Pos)           /* (CAN_S0) Store in Rx FIFO 0 if filter match Position */
+#define CAN_S0_SFEC_STF1M                     (CAN_S0_SFEC_STF1M_Val << CAN_S0_SFEC_Pos)           /* (CAN_S0) Store in Rx FIFO 1 if filter match Position */
+#define CAN_S0_SFEC_REJECT                    (CAN_S0_SFEC_REJECT_Val << CAN_S0_SFEC_Pos)          /* (CAN_S0) Reject ID if filter match Position */
+#define CAN_S0_SFEC_PRIORITY                  (CAN_S0_SFEC_PRIORITY_Val << CAN_S0_SFEC_Pos)        /* (CAN_S0) Set priority if filter match Position */
+#define CAN_S0_SFEC_PRIF0M                    (CAN_S0_SFEC_PRIF0M_Val << CAN_S0_SFEC_Pos)          /* (CAN_S0) Set priority and store in FIFO 0 if filter match Position */
+#define CAN_S0_SFEC_PRIF1M                    (CAN_S0_SFEC_PRIF1M_Val << CAN_S0_SFEC_Pos)          /* (CAN_S0) Set priority and store in FIFO 1 if filter match Position */
+#define CAN_S0_SFEC_STRXBUF                   (CAN_S0_SFEC_STRXBUF_Val << CAN_S0_SFEC_Pos)         /* (CAN_S0) Store into Rx Buffer Position */
+#define CAN_S0_SFT_Pos                        _UINT32_(30)                                         /* (CAN_S0) Standard Filter Type Position */
+#define CAN_S0_SFT_Msk                        (_UINT32_(0x3) << CAN_S0_SFT_Pos)                    /* (CAN_S0) Standard Filter Type Mask */
+#define CAN_S0_SFT(value)                     (CAN_S0_SFT_Msk & (_UINT32_(value) << CAN_S0_SFT_Pos)) /* Assignment of value for SFT in the CAN_S0 register */
+#define   CAN_S0_SFT_RANGE_Val                _UINT32_(0x0)                                        /* (CAN_S0) Range filter from SFID1 to SFID2  */
+#define   CAN_S0_SFT_DUAL_Val                 _UINT32_(0x1)                                        /* (CAN_S0) Dual ID filter for SFID1 or SFID2  */
+#define   CAN_S0_SFT_CLASSIC_Val              _UINT32_(0x2)                                        /* (CAN_S0) Classic filter  */
+#define CAN_S0_SFT_RANGE                      (CAN_S0_SFT_RANGE_Val << CAN_S0_SFT_Pos)             /* (CAN_S0) Range filter from SFID1 to SFID2 Position */
+#define CAN_S0_SFT_DUAL                       (CAN_S0_SFT_DUAL_Val << CAN_S0_SFT_Pos)              /* (CAN_S0) Dual ID filter for SFID1 or SFID2 Position */
+#define CAN_S0_SFT_CLASSIC                    (CAN_S0_SFT_CLASSIC_Val << CAN_S0_SFT_Pos)           /* (CAN_S0) Classic filter Position */
+#define CAN_S0_Msk                            _UINT32_(0xFFFF07FF)                                 /* (CAN_S0) Register Mask  */
+
+
+/* -------- CAN_T0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */
+#define CAN_T0_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_T0) Tx Buffer Element 0  Reset Value */
+
+#define CAN_T0_ID_Pos                         _UINT32_(0)                                          /* (CAN_T0) Identifier Position */
+#define CAN_T0_ID_Msk                         (_UINT32_(0x1FFFFFFF) << CAN_T0_ID_Pos)              /* (CAN_T0) Identifier Mask */
+#define CAN_T0_ID(value)                      (CAN_T0_ID_Msk & (_UINT32_(value) << CAN_T0_ID_Pos)) /* Assignment of value for ID in the CAN_T0 register */
+#define CAN_T0_RTR_Pos                        _UINT32_(29)                                         /* (CAN_T0) Remote Transmission Request Position */
+#define CAN_T0_RTR_Msk                        (_UINT32_(0x1) << CAN_T0_RTR_Pos)                    /* (CAN_T0) Remote Transmission Request Mask */
+#define CAN_T0_RTR(value)                     (CAN_T0_RTR_Msk & (_UINT32_(value) << CAN_T0_RTR_Pos)) /* Assignment of value for RTR in the CAN_T0 register */
+#define CAN_T0_XTD_Pos                        _UINT32_(30)                                         /* (CAN_T0) Extended Identifier Position */
+#define CAN_T0_XTD_Msk                        (_UINT32_(0x1) << CAN_T0_XTD_Pos)                    /* (CAN_T0) Extended Identifier Mask */
+#define CAN_T0_XTD(value)                     (CAN_T0_XTD_Msk & (_UINT32_(value) << CAN_T0_XTD_Pos)) /* Assignment of value for XTD in the CAN_T0 register */
+#define CAN_T0_ESI_Pos                        _UINT32_(31)                                         /* (CAN_T0) Error State Indicator Position */
+#define CAN_T0_ESI_Msk                        (_UINT32_(0x1) << CAN_T0_ESI_Pos)                    /* (CAN_T0) Error State Indicator Mask */
+#define CAN_T0_ESI(value)                     (CAN_T0_ESI_Msk & (_UINT32_(value) << CAN_T0_ESI_Pos)) /* Assignment of value for ESI in the CAN_T0 register */
+#define CAN_T0_Msk                            _UINT32_(0xFFFFFFFF)                                 /* (CAN_T0) Register Mask  */
+
+
+/* -------- CAN_T1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */
+#define CAN_T1_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_T1) Tx Buffer Element 1  Reset Value */
+
+#define CAN_T1_MMH_Pos                        _UINT32_(8)                                          /* (CAN_T1) Message Marker Higher Byte Position */
+#define CAN_T1_MMH_Msk                        (_UINT32_(0xFF) << CAN_T1_MMH_Pos)                   /* (CAN_T1) Message Marker Higher Byte Mask */
+#define CAN_T1_MMH(value)                     (CAN_T1_MMH_Msk & (_UINT32_(value) << CAN_T1_MMH_Pos)) /* Assignment of value for MMH in the CAN_T1 register */
+#define CAN_T1_DLC_Pos                        _UINT32_(16)                                         /* (CAN_T1) Identifier Position */
+#define CAN_T1_DLC_Msk                        (_UINT32_(0xF) << CAN_T1_DLC_Pos)                    /* (CAN_T1) Identifier Mask */
+#define CAN_T1_DLC(value)                     (CAN_T1_DLC_Msk & (_UINT32_(value) << CAN_T1_DLC_Pos)) /* Assignment of value for DLC in the CAN_T1 register */
+#define CAN_T1_BRS_Pos                        _UINT32_(20)                                         /* (CAN_T1) Bit Rate Search Position */
+#define CAN_T1_BRS_Msk                        (_UINT32_(0x1) << CAN_T1_BRS_Pos)                    /* (CAN_T1) Bit Rate Search Mask */
+#define CAN_T1_BRS(value)                     (CAN_T1_BRS_Msk & (_UINT32_(value) << CAN_T1_BRS_Pos)) /* Assignment of value for BRS in the CAN_T1 register */
+#define CAN_T1_FDF_Pos                        _UINT32_(21)                                         /* (CAN_T1) FD Format Position */
+#define CAN_T1_FDF_Msk                        (_UINT32_(0x1) << CAN_T1_FDF_Pos)                    /* (CAN_T1) FD Format Mask */
+#define CAN_T1_FDF(value)                     (CAN_T1_FDF_Msk & (_UINT32_(value) << CAN_T1_FDF_Pos)) /* Assignment of value for FDF in the CAN_T1 register */
+#define CAN_T1_TSCE_Pos                       _UINT32_(22)                                         /* (CAN_T1) Time Stamp Capture Enable for TSU Position */
+#define CAN_T1_TSCE_Msk                       (_UINT32_(0x1) << CAN_T1_TSCE_Pos)                   /* (CAN_T1) Time Stamp Capture Enable for TSU Mask */
+#define CAN_T1_TSCE(value)                    (CAN_T1_TSCE_Msk & (_UINT32_(value) << CAN_T1_TSCE_Pos)) /* Assignment of value for TSCE in the CAN_T1 register */
+#define CAN_T1_EFC_Pos                        _UINT32_(23)                                         /* (CAN_T1) Event FIFO Control Position */
+#define CAN_T1_EFC_Msk                        (_UINT32_(0x1) << CAN_T1_EFC_Pos)                    /* (CAN_T1) Event FIFO Control Mask */
+#define CAN_T1_EFC(value)                     (CAN_T1_EFC_Msk & (_UINT32_(value) << CAN_T1_EFC_Pos)) /* Assignment of value for EFC in the CAN_T1 register */
+#define CAN_T1_MML_Pos                        _UINT32_(24)                                         /* (CAN_T1) Message Marker Lower Byte Position */
+#define CAN_T1_MML_Msk                        (_UINT32_(0xFF) << CAN_T1_MML_Pos)                   /* (CAN_T1) Message Marker Lower Byte Mask */
+#define CAN_T1_MML(value)                     (CAN_T1_MML_Msk & (_UINT32_(value) << CAN_T1_MML_Pos)) /* Assignment of value for MML in the CAN_T1 register */
+#define CAN_T1_Msk                            _UINT32_(0xFFFFFF00)                                 /* (CAN_T1) Register Mask  */
+
+
+/* -------- CAN_T2 : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */
+#define CAN_T2_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_T2) Tx Buffer Element Data  Reset Value */
+
+#define CAN_T2_DB0_Pos                        _UINT32_(0)                                          /* (CAN_T2) Data Byte 0 Position */
+#define CAN_T2_DB0_Msk                        (_UINT32_(0xFF) << CAN_T2_DB0_Pos)                   /* (CAN_T2) Data Byte 0 Mask */
+#define CAN_T2_DB0(value)                     (CAN_T2_DB0_Msk & (_UINT32_(value) << CAN_T2_DB0_Pos)) /* Assignment of value for DB0 in the CAN_T2 register */
+#define CAN_T2_DB1_Pos                        _UINT32_(8)                                          /* (CAN_T2) Data Byte 1 Position */
+#define CAN_T2_DB1_Msk                        (_UINT32_(0xFF) << CAN_T2_DB1_Pos)                   /* (CAN_T2) Data Byte 1 Mask */
+#define CAN_T2_DB1(value)                     (CAN_T2_DB1_Msk & (_UINT32_(value) << CAN_T2_DB1_Pos)) /* Assignment of value for DB1 in the CAN_T2 register */
+#define CAN_T2_DB2_Pos                        _UINT32_(16)                                         /* (CAN_T2) Data Byte 2 Position */
+#define CAN_T2_DB2_Msk                        (_UINT32_(0xFF) << CAN_T2_DB2_Pos)                   /* (CAN_T2) Data Byte 2 Mask */
+#define CAN_T2_DB2(value)                     (CAN_T2_DB2_Msk & (_UINT32_(value) << CAN_T2_DB2_Pos)) /* Assignment of value for DB2 in the CAN_T2 register */
+#define CAN_T2_DB3_Pos                        _UINT32_(24)                                         /* (CAN_T2) Data Byte 3 Position */
+#define CAN_T2_DB3_Msk                        (_UINT32_(0xFF) << CAN_T2_DB3_Pos)                   /* (CAN_T2) Data Byte 3 Mask */
+#define CAN_T2_DB3(value)                     (CAN_T2_DB3_Msk & (_UINT32_(value) << CAN_T2_DB3_Pos)) /* Assignment of value for DB3 in the CAN_T2 register */
+#define CAN_T2_Msk                            _UINT32_(0xFFFFFFFF)                                 /* (CAN_T2) Register Mask  */
+
+
+/* -------- CAN_E0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */
+#define CAN_E0_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_E0) Tx Event FIFO Element 0  Reset Value */
+
+#define CAN_E0_ID_Pos                         _UINT32_(0)                                          /* (CAN_E0) Identifier Position */
+#define CAN_E0_ID_Msk                         (_UINT32_(0x1FFFFFFF) << CAN_E0_ID_Pos)              /* (CAN_E0) Identifier Mask */
+#define CAN_E0_ID(value)                      (CAN_E0_ID_Msk & (_UINT32_(value) << CAN_E0_ID_Pos)) /* Assignment of value for ID in the CAN_E0 register */
+#define CAN_E0_RTR_Pos                        _UINT32_(29)                                         /* (CAN_E0) Remote Transmission Request Position */
+#define CAN_E0_RTR_Msk                        (_UINT32_(0x1) << CAN_E0_RTR_Pos)                    /* (CAN_E0) Remote Transmission Request Mask */
+#define CAN_E0_RTR(value)                     (CAN_E0_RTR_Msk & (_UINT32_(value) << CAN_E0_RTR_Pos)) /* Assignment of value for RTR in the CAN_E0 register */
+#define CAN_E0_XTD_Pos                        _UINT32_(30)                                         /* (CAN_E0) Extended Indentifier Position */
+#define CAN_E0_XTD_Msk                        (_UINT32_(0x1) << CAN_E0_XTD_Pos)                    /* (CAN_E0) Extended Indentifier Mask */
+#define CAN_E0_XTD(value)                     (CAN_E0_XTD_Msk & (_UINT32_(value) << CAN_E0_XTD_Pos)) /* Assignment of value for XTD in the CAN_E0 register */
+#define CAN_E0_ESI_Pos                        _UINT32_(31)                                         /* (CAN_E0) Error State Indicator Position */
+#define CAN_E0_ESI_Msk                        (_UINT32_(0x1) << CAN_E0_ESI_Pos)                    /* (CAN_E0) Error State Indicator Mask */
+#define CAN_E0_ESI(value)                     (CAN_E0_ESI_Msk & (_UINT32_(value) << CAN_E0_ESI_Pos)) /* Assignment of value for ESI in the CAN_E0 register */
+#define CAN_E0_Msk                            _UINT32_(0xFFFFFFFF)                                 /* (CAN_E0) Register Mask  */
+
+
+/* -------- CAN_E1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */
+#define CAN_E1_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_E1) Tx Event FIFO Element 1  Reset Value */
+
+#define CAN_E1_TXTS_Pos                       _UINT32_(0)                                          /* (CAN_E1) Tx Timestamp Position */
+#define CAN_E1_TXTS_Msk                       (_UINT32_(0xFFFF) << CAN_E1_TXTS_Pos)                /* (CAN_E1) Tx Timestamp Mask */
+#define CAN_E1_TXTS(value)                    (CAN_E1_TXTS_Msk & (_UINT32_(value) << CAN_E1_TXTS_Pos)) /* Assignment of value for TXTS in the CAN_E1 register */
+#define CAN_E1_DLC_Pos                        _UINT32_(16)                                         /* (CAN_E1) Data Length Code Position */
+#define CAN_E1_DLC_Msk                        (_UINT32_(0xF) << CAN_E1_DLC_Pos)                    /* (CAN_E1) Data Length Code Mask */
+#define CAN_E1_DLC(value)                     (CAN_E1_DLC_Msk & (_UINT32_(value) << CAN_E1_DLC_Pos)) /* Assignment of value for DLC in the CAN_E1 register */
+#define CAN_E1_BRS_Pos                        _UINT32_(20)                                         /* (CAN_E1) Bit Rate Search Position */
+#define CAN_E1_BRS_Msk                        (_UINT32_(0x1) << CAN_E1_BRS_Pos)                    /* (CAN_E1) Bit Rate Search Mask */
+#define CAN_E1_BRS(value)                     (CAN_E1_BRS_Msk & (_UINT32_(value) << CAN_E1_BRS_Pos)) /* Assignment of value for BRS in the CAN_E1 register */
+#define CAN_E1_FDF_Pos                        _UINT32_(21)                                         /* (CAN_E1) FD Format Position */
+#define CAN_E1_FDF_Msk                        (_UINT32_(0x1) << CAN_E1_FDF_Pos)                    /* (CAN_E1) FD Format Mask */
+#define CAN_E1_FDF(value)                     (CAN_E1_FDF_Msk & (_UINT32_(value) << CAN_E1_FDF_Pos)) /* Assignment of value for FDF in the CAN_E1 register */
+#define CAN_E1_ET_Pos                         _UINT32_(22)                                         /* (CAN_E1) Event Type Position */
+#define CAN_E1_ET_Msk                         (_UINT32_(0x3) << CAN_E1_ET_Pos)                     /* (CAN_E1) Event Type Mask */
+#define CAN_E1_ET(value)                      (CAN_E1_ET_Msk & (_UINT32_(value) << CAN_E1_ET_Pos)) /* Assignment of value for ET in the CAN_E1 register */
+#define   CAN_E1_ET_TXE_Val                   _UINT32_(0x1)                                        /* (CAN_E1) Tx event  */
+#define   CAN_E1_ET_TXC_Val                   _UINT32_(0x2)                                        /* (CAN_E1) Transmission in spite of cancellation  */
+#define CAN_E1_ET_TXE                         (CAN_E1_ET_TXE_Val << CAN_E1_ET_Pos)                 /* (CAN_E1) Tx event Position */
+#define CAN_E1_ET_TXC                         (CAN_E1_ET_TXC_Val << CAN_E1_ET_Pos)                 /* (CAN_E1) Transmission in spite of cancellation Position */
+#define CAN_E1_MM_Pos                         _UINT32_(24)                                         /* (CAN_E1) Message Marker Position */
+#define CAN_E1_MM_Msk                         (_UINT32_(0xFF) << CAN_E1_MM_Pos)                    /* (CAN_E1) Message Marker Mask */
+#define CAN_E1_MM(value)                      (CAN_E1_MM_Msk & (_UINT32_(value) << CAN_E1_MM_Pos)) /* Assignment of value for MM in the CAN_E1 register */
+#define CAN_E1_Msk                            _UINT32_(0xFFFFFFFF)                                 /* (CAN_E1) Register Mask  */
+
+
+/* -------- CAN_F0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */
+#define CAN_F0_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_F0) Extended Message ID Filter Element 0  Reset Value */
+
+#define CAN_F0_EFID1_Pos                      _UINT32_(0)                                          /* (CAN_F0) Extended Filter ID 1 Position */
+#define CAN_F0_EFID1_Msk                      (_UINT32_(0x1FFFFFFF) << CAN_F0_EFID1_Pos)           /* (CAN_F0) Extended Filter ID 1 Mask */
+#define CAN_F0_EFID1(value)                   (CAN_F0_EFID1_Msk & (_UINT32_(value) << CAN_F0_EFID1_Pos)) /* Assignment of value for EFID1 in the CAN_F0 register */
+#define CAN_F0_EFEC_Pos                       _UINT32_(29)                                         /* (CAN_F0) Extended Filter Element Configuration Position */
+#define CAN_F0_EFEC_Msk                       (_UINT32_(0x7) << CAN_F0_EFEC_Pos)                   /* (CAN_F0) Extended Filter Element Configuration Mask */
+#define CAN_F0_EFEC(value)                    (CAN_F0_EFEC_Msk & (_UINT32_(value) << CAN_F0_EFEC_Pos)) /* Assignment of value for EFEC in the CAN_F0 register */
+#define   CAN_F0_EFEC_DISABLE_Val             _UINT32_(0x0)                                        /* (CAN_F0) Disable filter element  */
+#define   CAN_F0_EFEC_STF0M_Val               _UINT32_(0x1)                                        /* (CAN_F0) Store in Rx FIFO 0 if filter match  */
+#define   CAN_F0_EFEC_STF1M_Val               _UINT32_(0x2)                                        /* (CAN_F0) Store in Rx FIFO 1 if filter match  */
+#define   CAN_F0_EFEC_REJECT_Val              _UINT32_(0x3)                                        /* (CAN_F0) Reject ID if filter match  */
+#define   CAN_F0_EFEC_PRIORITY_Val            _UINT32_(0x4)                                        /* (CAN_F0) Set priority if filter match  */
+#define   CAN_F0_EFEC_PRIF0M_Val              _UINT32_(0x5)                                        /* (CAN_F0) Set priority and store in FIFO 0 if filter match  */
+#define   CAN_F0_EFEC_PRIF1M_Val              _UINT32_(0x6)                                        /* (CAN_F0) Set priority and store in FIFO 1 if filter match  */
+#define   CAN_F0_EFEC_STRXBUF_Val             _UINT32_(0x7)                                        /* (CAN_F0) Store into Rx Buffer  */
+#define CAN_F0_EFEC_DISABLE                   (CAN_F0_EFEC_DISABLE_Val << CAN_F0_EFEC_Pos)         /* (CAN_F0) Disable filter element Position */
+#define CAN_F0_EFEC_STF0M                     (CAN_F0_EFEC_STF0M_Val << CAN_F0_EFEC_Pos)           /* (CAN_F0) Store in Rx FIFO 0 if filter match Position */
+#define CAN_F0_EFEC_STF1M                     (CAN_F0_EFEC_STF1M_Val << CAN_F0_EFEC_Pos)           /* (CAN_F0) Store in Rx FIFO 1 if filter match Position */
+#define CAN_F0_EFEC_REJECT                    (CAN_F0_EFEC_REJECT_Val << CAN_F0_EFEC_Pos)          /* (CAN_F0) Reject ID if filter match Position */
+#define CAN_F0_EFEC_PRIORITY                  (CAN_F0_EFEC_PRIORITY_Val << CAN_F0_EFEC_Pos)        /* (CAN_F0) Set priority if filter match Position */
+#define CAN_F0_EFEC_PRIF0M                    (CAN_F0_EFEC_PRIF0M_Val << CAN_F0_EFEC_Pos)          /* (CAN_F0) Set priority and store in FIFO 0 if filter match Position */
+#define CAN_F0_EFEC_PRIF1M                    (CAN_F0_EFEC_PRIF1M_Val << CAN_F0_EFEC_Pos)          /* (CAN_F0) Set priority and store in FIFO 1 if filter match Position */
+#define CAN_F0_EFEC_STRXBUF                   (CAN_F0_EFEC_STRXBUF_Val << CAN_F0_EFEC_Pos)         /* (CAN_F0) Store into Rx Buffer Position */
+#define CAN_F0_Msk                            _UINT32_(0xFFFFFFFF)                                 /* (CAN_F0) Register Mask  */
+
+
+/* -------- CAN_F1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */
+#define CAN_F1_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_F1) Extended Message ID Filter Element 1  Reset Value */
+
+#define CAN_F1_EFID2_Pos                      _UINT32_(0)                                          /* (CAN_F1) Extended Filter ID 2 Position */
+#define CAN_F1_EFID2_Msk                      (_UINT32_(0x1FFFFFFF) << CAN_F1_EFID2_Pos)           /* (CAN_F1) Extended Filter ID 2 Mask */
+#define CAN_F1_EFID2(value)                   (CAN_F1_EFID2_Msk & (_UINT32_(value) << CAN_F1_EFID2_Pos)) /* Assignment of value for EFID2 in the CAN_F1 register */
+#define CAN_F1_EFT_Pos                        _UINT32_(30)                                         /* (CAN_F1) Extended Filter Type Position */
+#define CAN_F1_EFT_Msk                        (_UINT32_(0x3) << CAN_F1_EFT_Pos)                    /* (CAN_F1) Extended Filter Type Mask */
+#define CAN_F1_EFT(value)                     (CAN_F1_EFT_Msk & (_UINT32_(value) << CAN_F1_EFT_Pos)) /* Assignment of value for EFT in the CAN_F1 register */
+#define   CAN_F1_EFT_RANGEM_Val               _UINT32_(0x0)                                        /* (CAN_F1) Range filter from EFID1 to EFID2  */
+#define   CAN_F1_EFT_DUAL_Val                 _UINT32_(0x1)                                        /* (CAN_F1) Dual ID filter for EFID1 or EFID2  */
+#define   CAN_F1_EFT_CLASSIC_Val              _UINT32_(0x2)                                        /* (CAN_F1) Classic filter  */
+#define   CAN_F1_EFT_RANGE_Val                _UINT32_(0x3)                                        /* (CAN_F1) Range filter from EFID1 to EFID2 with no XIDAM mask  */
+#define CAN_F1_EFT_RANGEM                     (CAN_F1_EFT_RANGEM_Val << CAN_F1_EFT_Pos)            /* (CAN_F1) Range filter from EFID1 to EFID2 Position */
+#define CAN_F1_EFT_DUAL                       (CAN_F1_EFT_DUAL_Val << CAN_F1_EFT_Pos)              /* (CAN_F1) Dual ID filter for EFID1 or EFID2 Position */
+#define CAN_F1_EFT_CLASSIC                    (CAN_F1_EFT_CLASSIC_Val << CAN_F1_EFT_Pos)           /* (CAN_F1) Classic filter Position */
+#define CAN_F1_EFT_RANGE                      (CAN_F1_EFT_RANGE_Val << CAN_F1_EFT_Pos)             /* (CAN_F1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */
+#define CAN_F1_Msk                            _UINT32_(0xDFFFFFFF)                                 /* (CAN_F1) Register Mask  */
+
+
+/* -------- CAN_CTRLA : (CAN Offset: 0x00) (R/W 32) Control A Register -------- */
+#define CAN_CTRLA_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_CTRLA) Control A Register  Reset Value */
+
+#define CAN_CTRLA_SWRST_Pos                   _UINT32_(0)                                          /* (CAN_CTRLA) Software Reset Position */
+#define CAN_CTRLA_SWRST_Msk                   (_UINT32_(0x1) << CAN_CTRLA_SWRST_Pos)               /* (CAN_CTRLA) Software Reset Mask */
+#define CAN_CTRLA_SWRST(value)                (CAN_CTRLA_SWRST_Msk & (_UINT32_(value) << CAN_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the CAN_CTRLA register */
+#define CAN_CTRLA_PRIV_Pos                    _UINT32_(2)                                          /* (CAN_CTRLA) Priveged Access Position */
+#define CAN_CTRLA_PRIV_Msk                    (_UINT32_(0x1) << CAN_CTRLA_PRIV_Pos)                /* (CAN_CTRLA) Priveged Access Mask */
+#define CAN_CTRLA_PRIV(value)                 (CAN_CTRLA_PRIV_Msk & (_UINT32_(value) << CAN_CTRLA_PRIV_Pos)) /* Assignment of value for PRIV in the CAN_CTRLA register */
+#define CAN_CTRLA_RUNSTDBY_Pos                _UINT32_(6)                                          /* (CAN_CTRLA) Run during standby Position */
+#define CAN_CTRLA_RUNSTDBY_Msk                (_UINT32_(0x1) << CAN_CTRLA_RUNSTDBY_Pos)            /* (CAN_CTRLA) Run during standby Mask */
+#define CAN_CTRLA_RUNSTDBY(value)             (CAN_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << CAN_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the CAN_CTRLA register */
+#define CAN_CTRLA_Msk                         _UINT32_(0x00000045)                                 /* (CAN_CTRLA) Register Mask  */
+
+
+/* -------- CAN_CTRLB : (CAN Offset: 0x04) (R/W 32) Control B Register -------- */
+#define CAN_CTRLB_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_CTRLB) Control B Register  Reset Value */
+
+#define CAN_CTRLB_OFFSET_Pos                  _UINT32_(16)                                         /* (CAN_CTRLB) Message RAM Base Address Offset. Position */
+#define CAN_CTRLB_OFFSET_Msk                  (_UINT32_(0xFF) << CAN_CTRLB_OFFSET_Pos)             /* (CAN_CTRLB) Message RAM Base Address Offset. Mask */
+#define CAN_CTRLB_OFFSET(value)               (CAN_CTRLB_OFFSET_Msk & (_UINT32_(value) << CAN_CTRLB_OFFSET_Pos)) /* Assignment of value for OFFSET in the CAN_CTRLB register */
+#define CAN_CTRLB_Msk                         _UINT32_(0x00FF0000)                                 /* (CAN_CTRLB) Register Mask  */
+
+
+/* -------- CAN_INTENCLR : (CAN Offset: 0x28) (R/W 32) Interrupt Enable Clear register -------- */
+#define CAN_INTENCLR_RESETVALUE               _UINT32_(0x00)                                       /*  (CAN_INTENCLR) Interrupt Enable Clear register  Reset Value */
+
+#define CAN_INTENCLR_DBG_Pos                  _UINT32_(0)                                          /* (CAN_INTENCLR) Debug Message Interrupt Disable Position */
+#define CAN_INTENCLR_DBG_Msk                  (_UINT32_(0x1) << CAN_INTENCLR_DBG_Pos)              /* (CAN_INTENCLR) Debug Message Interrupt Disable Mask */
+#define CAN_INTENCLR_DBG(value)               (CAN_INTENCLR_DBG_Msk & (_UINT32_(value) << CAN_INTENCLR_DBG_Pos)) /* Assignment of value for DBG in the CAN_INTENCLR register */
+#define CAN_INTENCLR_BERR_Pos                 _UINT32_(1)                                          /* (CAN_INTENCLR) Bus Error Interrupt Enable Position */
+#define CAN_INTENCLR_BERR_Msk                 (_UINT32_(0x1) << CAN_INTENCLR_BERR_Pos)             /* (CAN_INTENCLR) Bus Error Interrupt Enable Mask */
+#define CAN_INTENCLR_BERR(value)              (CAN_INTENCLR_BERR_Msk & (_UINT32_(value) << CAN_INTENCLR_BERR_Pos)) /* Assignment of value for BERR in the CAN_INTENCLR register */
+#define CAN_INTENCLR_Msk                      _UINT32_(0x00000003)                                 /* (CAN_INTENCLR) Register Mask  */
+
+
+/* -------- CAN_INTENSET : (CAN Offset: 0x2C) (R/W 32) Interrupt Enable Set register -------- */
+#define CAN_INTENSET_RESETVALUE               _UINT32_(0x00)                                       /*  (CAN_INTENSET) Interrupt Enable Set register  Reset Value */
+
+#define CAN_INTENSET_DBG_Pos                  _UINT32_(0)                                          /* (CAN_INTENSET) Debug Message Interrupt Enable Position */
+#define CAN_INTENSET_DBG_Msk                  (_UINT32_(0x1) << CAN_INTENSET_DBG_Pos)              /* (CAN_INTENSET) Debug Message Interrupt Enable Mask */
+#define CAN_INTENSET_DBG(value)               (CAN_INTENSET_DBG_Msk & (_UINT32_(value) << CAN_INTENSET_DBG_Pos)) /* Assignment of value for DBG in the CAN_INTENSET register */
+#define CAN_INTENSET_BERR_Pos                 _UINT32_(1)                                          /* (CAN_INTENSET) Bus Error Interrupt Enable Position */
+#define CAN_INTENSET_BERR_Msk                 (_UINT32_(0x1) << CAN_INTENSET_BERR_Pos)             /* (CAN_INTENSET) Bus Error Interrupt Enable Mask */
+#define CAN_INTENSET_BERR(value)              (CAN_INTENSET_BERR_Msk & (_UINT32_(value) << CAN_INTENSET_BERR_Pos)) /* Assignment of value for BERR in the CAN_INTENSET register */
+#define CAN_INTENSET_Msk                      _UINT32_(0x00000003)                                 /* (CAN_INTENSET) Register Mask  */
+
+
+/* -------- CAN_INTFLAG : (CAN Offset: 0x30) (R/W 32) Interrupt Flag Status and Clear register -------- */
+#define CAN_INTFLAG_RESETVALUE                _UINT32_(0x00)                                       /*  (CAN_INTFLAG) Interrupt Flag Status and Clear register  Reset Value */
+
+#define CAN_INTFLAG_DBG_Pos                   _UINT32_(0)                                          /* (CAN_INTFLAG) Debug Message Reception Position */
+#define CAN_INTFLAG_DBG_Msk                   (_UINT32_(0x1) << CAN_INTFLAG_DBG_Pos)               /* (CAN_INTFLAG) Debug Message Reception Mask */
+#define CAN_INTFLAG_DBG(value)                (CAN_INTFLAG_DBG_Msk & (_UINT32_(value) << CAN_INTFLAG_DBG_Pos)) /* Assignment of value for DBG in the CAN_INTFLAG register */
+#define CAN_INTFLAG_BERR_Pos                  _UINT32_(1)                                          /* (CAN_INTFLAG) AHB Bus Error Detection Position */
+#define CAN_INTFLAG_BERR_Msk                  (_UINT32_(0x1) << CAN_INTFLAG_BERR_Pos)              /* (CAN_INTFLAG) AHB Bus Error Detection Mask */
+#define CAN_INTFLAG_BERR(value)               (CAN_INTFLAG_BERR_Msk & (_UINT32_(value) << CAN_INTFLAG_BERR_Pos)) /* Assignment of value for BERR in the CAN_INTFLAG register */
+#define CAN_INTFLAG_Msk                       _UINT32_(0x00000003)                                 /* (CAN_INTFLAG) Register Mask  */
+
+
+/* -------- CAN_INTFLAGSET : (CAN Offset: 0x34) (R/W 32) Interrupt Flag Software Set Register -------- */
+#define CAN_INTFLAGSET_RESETVALUE             _UINT32_(0x00)                                       /*  (CAN_INTFLAGSET) Interrupt Flag Software Set Register  Reset Value */
+
+#define CAN_INTFLAGSET_DBG_Pos                _UINT32_(0)                                          /* (CAN_INTFLAGSET) Debug Message Interrupt Flag Set Position */
+#define CAN_INTFLAGSET_DBG_Msk                (_UINT32_(0x1) << CAN_INTFLAGSET_DBG_Pos)            /* (CAN_INTFLAGSET) Debug Message Interrupt Flag Set Mask */
+#define CAN_INTFLAGSET_DBG(value)             (CAN_INTFLAGSET_DBG_Msk & (_UINT32_(value) << CAN_INTFLAGSET_DBG_Pos)) /* Assignment of value for DBG in the CAN_INTFLAGSET register */
+#define CAN_INTFLAGSET_BERR_Pos               _UINT32_(1)                                          /* (CAN_INTFLAGSET) AHB Bus Error Detection Interrupt Flag Set Position */
+#define CAN_INTFLAGSET_BERR_Msk               (_UINT32_(0x1) << CAN_INTFLAGSET_BERR_Pos)           /* (CAN_INTFLAGSET) AHB Bus Error Detection Interrupt Flag Set Mask */
+#define CAN_INTFLAGSET_BERR(value)            (CAN_INTFLAGSET_BERR_Msk & (_UINT32_(value) << CAN_INTFLAGSET_BERR_Pos)) /* Assignment of value for BERR in the CAN_INTFLAGSET register */
+#define CAN_INTFLAGSET_Msk                    _UINT32_(0x00000003)                                 /* (CAN_INTFLAGSET) Register Mask  */
+
+
+/* -------- CAN_SYNCBUSY : (CAN Offset: 0x5C) ( R/ 32) SYNCBUSY Register -------- */
+#define CAN_SYNCBUSY_RESETVALUE               _UINT32_(0x00)                                       /*  (CAN_SYNCBUSY) SYNCBUSY Register  Reset Value */
+
+#define CAN_SYNCBUSY_SWRST_Pos                _UINT32_(0)                                          /* (CAN_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define CAN_SYNCBUSY_SWRST_Msk                (_UINT32_(0x1) << CAN_SYNCBUSY_SWRST_Pos)            /* (CAN_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define CAN_SYNCBUSY_SWRST(value)             (CAN_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << CAN_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the CAN_SYNCBUSY register */
+#define CAN_SYNCBUSY_Msk                      _UINT32_(0x00000001)                                 /* (CAN_SYNCBUSY) Register Mask  */
+
+
+/* -------- CAN_CREL_MCAN : (CAN Offset: 0x100) ( R/ 32) Core Release -------- */
+#define CAN_CREL_MCAN_RESETVALUE              _UINT32_(0x33000000)                                 /*  (CAN_CREL_MCAN) Core Release  Reset Value */
+
+#define CAN_CREL_MCAN_DAY_Pos                 _UINT32_(0)                                          /* (CAN_CREL_MCAN) Timestamp day Position */
+#define CAN_CREL_MCAN_DAY_Msk                 (_UINT32_(0xFF) << CAN_CREL_MCAN_DAY_Pos)            /* (CAN_CREL_MCAN) Timestamp day Mask */
+#define CAN_CREL_MCAN_DAY(value)              (CAN_CREL_MCAN_DAY_Msk & (_UINT32_(value) << CAN_CREL_MCAN_DAY_Pos)) /* Assignment of value for DAY in the CAN_CREL_MCAN register */
+#define CAN_CREL_MCAN_MON_Pos                 _UINT32_(8)                                          /* (CAN_CREL_MCAN) Timestamp month Position */
+#define CAN_CREL_MCAN_MON_Msk                 (_UINT32_(0xFF) << CAN_CREL_MCAN_MON_Pos)            /* (CAN_CREL_MCAN) Timestamp month Mask */
+#define CAN_CREL_MCAN_MON(value)              (CAN_CREL_MCAN_MON_Msk & (_UINT32_(value) << CAN_CREL_MCAN_MON_Pos)) /* Assignment of value for MON in the CAN_CREL_MCAN register */
+#define CAN_CREL_MCAN_YEAR_Pos                _UINT32_(16)                                         /* (CAN_CREL_MCAN) Timestamp year Position */
+#define CAN_CREL_MCAN_YEAR_Msk                (_UINT32_(0xF) << CAN_CREL_MCAN_YEAR_Pos)            /* (CAN_CREL_MCAN) Timestamp year Mask */
+#define CAN_CREL_MCAN_YEAR(value)             (CAN_CREL_MCAN_YEAR_Msk & (_UINT32_(value) << CAN_CREL_MCAN_YEAR_Pos)) /* Assignment of value for YEAR in the CAN_CREL_MCAN register */
+#define CAN_CREL_MCAN_SUBSTEP_Pos             _UINT32_(20)                                         /* (CAN_CREL_MCAN) Sub-step of Core Release Position */
+#define CAN_CREL_MCAN_SUBSTEP_Msk             (_UINT32_(0xF) << CAN_CREL_MCAN_SUBSTEP_Pos)         /* (CAN_CREL_MCAN) Sub-step of Core Release Mask */
+#define CAN_CREL_MCAN_SUBSTEP(value)          (CAN_CREL_MCAN_SUBSTEP_Msk & (_UINT32_(value) << CAN_CREL_MCAN_SUBSTEP_Pos)) /* Assignment of value for SUBSTEP in the CAN_CREL_MCAN register */
+#define CAN_CREL_MCAN_STEP_Pos                _UINT32_(24)                                         /* (CAN_CREL_MCAN) Step of Core Release Position */
+#define CAN_CREL_MCAN_STEP_Msk                (_UINT32_(0xF) << CAN_CREL_MCAN_STEP_Pos)            /* (CAN_CREL_MCAN) Step of Core Release Mask */
+#define CAN_CREL_MCAN_STEP(value)             (CAN_CREL_MCAN_STEP_Msk & (_UINT32_(value) << CAN_CREL_MCAN_STEP_Pos)) /* Assignment of value for STEP in the CAN_CREL_MCAN register */
+#define CAN_CREL_MCAN_REL_Pos                 _UINT32_(28)                                         /* (CAN_CREL_MCAN) Core Release Position */
+#define CAN_CREL_MCAN_REL_Msk                 (_UINT32_(0xF) << CAN_CREL_MCAN_REL_Pos)             /* (CAN_CREL_MCAN) Core Release Mask */
+#define CAN_CREL_MCAN_REL(value)              (CAN_CREL_MCAN_REL_Msk & (_UINT32_(value) << CAN_CREL_MCAN_REL_Pos)) /* Assignment of value for REL in the CAN_CREL_MCAN register */
+#define CAN_CREL_MCAN_Msk                     _UINT32_(0xFFFFFFFF)                                 /* (CAN_CREL_MCAN) Register Mask  */
+
+
+/* -------- CAN_ENDN : (CAN Offset: 0x104) ( R/ 32) Endian -------- */
+#define CAN_ENDN_RESETVALUE                   _UINT32_(0x87654321)                                 /*  (CAN_ENDN) Endian  Reset Value */
+
+#define CAN_ENDN_ETV_Pos                      _UINT32_(0)                                          /* (CAN_ENDN) Endianness Test Value Position */
+#define CAN_ENDN_ETV_Msk                      (_UINT32_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos)           /* (CAN_ENDN) Endianness Test Value Mask */
+#define CAN_ENDN_ETV(value)                   (CAN_ENDN_ETV_Msk & (_UINT32_(value) << CAN_ENDN_ETV_Pos)) /* Assignment of value for ETV in the CAN_ENDN register */
+#define CAN_ENDN_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (CAN_ENDN) Register Mask  */
+
+
+/* -------- CAN_CUST : (CAN Offset: 0x108) (R/W 32) Customer Register -------- */
+#define CAN_CUST_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_CUST) Customer Register  Reset Value */
+
+#define CAN_CUST_CUST_Pos                     _UINT32_(0)                                          /* (CAN_CUST) Customer Register Position */
+#define CAN_CUST_CUST_Msk                     (_UINT32_(0xFFFFFFFF) << CAN_CUST_CUST_Pos)          /* (CAN_CUST) Customer Register Mask */
+#define CAN_CUST_CUST(value)                  (CAN_CUST_CUST_Msk & (_UINT32_(value) << CAN_CUST_CUST_Pos)) /* Assignment of value for CUST in the CAN_CUST register */
+#define CAN_CUST_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (CAN_CUST) Register Mask  */
+
+
+/* -------- CAN_DBTP : (CAN Offset: 0x10C) (R/W 32) Fast Bit Timing and Prescaler -------- */
+#define CAN_DBTP_RESETVALUE                   _UINT32_(0xA33)                                      /*  (CAN_DBTP) Fast Bit Timing and Prescaler  Reset Value */
+
+#define CAN_DBTP_DSJW_Pos                     _UINT32_(0)                                          /* (CAN_DBTP) Data (Re)Synchronization Jump Width Position */
+#define CAN_DBTP_DSJW_Msk                     (_UINT32_(0xF) << CAN_DBTP_DSJW_Pos)                 /* (CAN_DBTP) Data (Re)Synchronization Jump Width Mask */
+#define CAN_DBTP_DSJW(value)                  (CAN_DBTP_DSJW_Msk & (_UINT32_(value) << CAN_DBTP_DSJW_Pos)) /* Assignment of value for DSJW in the CAN_DBTP register */
+#define CAN_DBTP_DTSEG2_Pos                   _UINT32_(4)                                          /* (CAN_DBTP) Data time segment after sample point Position */
+#define CAN_DBTP_DTSEG2_Msk                   (_UINT32_(0xF) << CAN_DBTP_DTSEG2_Pos)               /* (CAN_DBTP) Data time segment after sample point Mask */
+#define CAN_DBTP_DTSEG2(value)                (CAN_DBTP_DTSEG2_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG2_Pos)) /* Assignment of value for DTSEG2 in the CAN_DBTP register */
+#define CAN_DBTP_DTSEG1_Pos                   _UINT32_(8)                                          /* (CAN_DBTP) Data time segment before sample point Position */
+#define CAN_DBTP_DTSEG1_Msk                   (_UINT32_(0x1F) << CAN_DBTP_DTSEG1_Pos)              /* (CAN_DBTP) Data time segment before sample point Mask */
+#define CAN_DBTP_DTSEG1(value)                (CAN_DBTP_DTSEG1_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG1_Pos)) /* Assignment of value for DTSEG1 in the CAN_DBTP register */
+#define CAN_DBTP_DBRP_Pos                     _UINT32_(16)                                         /* (CAN_DBTP) Data Baud Rate Prescaler Position */
+#define CAN_DBTP_DBRP_Msk                     (_UINT32_(0x1F) << CAN_DBTP_DBRP_Pos)                /* (CAN_DBTP) Data Baud Rate Prescaler Mask */
+#define CAN_DBTP_DBRP(value)                  (CAN_DBTP_DBRP_Msk & (_UINT32_(value) << CAN_DBTP_DBRP_Pos)) /* Assignment of value for DBRP in the CAN_DBTP register */
+#define CAN_DBTP_TDC_Pos                      _UINT32_(23)                                         /* (CAN_DBTP) Tranceiver Delay Compensation Position */
+#define CAN_DBTP_TDC_Msk                      (_UINT32_(0x1) << CAN_DBTP_TDC_Pos)                  /* (CAN_DBTP) Tranceiver Delay Compensation Mask */
+#define CAN_DBTP_TDC(value)                   (CAN_DBTP_TDC_Msk & (_UINT32_(value) << CAN_DBTP_TDC_Pos)) /* Assignment of value for TDC in the CAN_DBTP register */
+#define CAN_DBTP_Msk                          _UINT32_(0x009F1FFF)                                 /* (CAN_DBTP) Register Mask  */
+
+
+/* -------- CAN_TEST : (CAN Offset: 0x110) (R/W 32) Test -------- */
+#define CAN_TEST_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TEST) Test  Reset Value */
+
+#define CAN_TEST_LBCK_Pos                     _UINT32_(4)                                          /* (CAN_TEST) Loop Back Mode Position */
+#define CAN_TEST_LBCK_Msk                     (_UINT32_(0x1) << CAN_TEST_LBCK_Pos)                 /* (CAN_TEST) Loop Back Mode Mask */
+#define CAN_TEST_LBCK(value)                  (CAN_TEST_LBCK_Msk & (_UINT32_(value) << CAN_TEST_LBCK_Pos)) /* Assignment of value for LBCK in the CAN_TEST register */
+#define CAN_TEST_TX_Pos                       _UINT32_(5)                                          /* (CAN_TEST) Control of Transmit Pin Position */
+#define CAN_TEST_TX_Msk                       (_UINT32_(0x3) << CAN_TEST_TX_Pos)                   /* (CAN_TEST) Control of Transmit Pin Mask */
+#define CAN_TEST_TX(value)                    (CAN_TEST_TX_Msk & (_UINT32_(value) << CAN_TEST_TX_Pos)) /* Assignment of value for TX in the CAN_TEST register */
+#define   CAN_TEST_TX_CORE_Val                _UINT32_(0x0)                                        /* (CAN_TEST) TX controlled by CAN core  */
+#define   CAN_TEST_TX_SAMPLE_Val              _UINT32_(0x1)                                        /* (CAN_TEST) TX monitoring sample point  */
+#define   CAN_TEST_TX_DOMINANT_Val            _UINT32_(0x2)                                        /* (CAN_TEST) Dominant (0) level at pin CAN_TX  */
+#define   CAN_TEST_TX_RECESSIVE_Val           _UINT32_(0x3)                                        /* (CAN_TEST) Recessive (1) level at pin CAN_TX  */
+#define CAN_TEST_TX_CORE                      (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos)            /* (CAN_TEST) TX controlled by CAN core Position */
+#define CAN_TEST_TX_SAMPLE                    (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos)          /* (CAN_TEST) TX monitoring sample point Position */
+#define CAN_TEST_TX_DOMINANT                  (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos)        /* (CAN_TEST) Dominant (0) level at pin CAN_TX Position */
+#define CAN_TEST_TX_RECESSIVE                 (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos)       /* (CAN_TEST) Recessive (1) level at pin CAN_TX Position */
+#define CAN_TEST_RX_Pos                       _UINT32_(7)                                          /* (CAN_TEST) Receive Pin Position */
+#define CAN_TEST_RX_Msk                       (_UINT32_(0x1) << CAN_TEST_RX_Pos)                   /* (CAN_TEST) Receive Pin Mask */
+#define CAN_TEST_RX(value)                    (CAN_TEST_RX_Msk & (_UINT32_(value) << CAN_TEST_RX_Pos)) /* Assignment of value for RX in the CAN_TEST register */
+#define CAN_TEST_Msk                          _UINT32_(0x000000F0)                                 /* (CAN_TEST) Register Mask  */
+
+
+/* -------- CAN_RWD : (CAN Offset: 0x114) (R/W 32) RAM Watchdog -------- */
+#define CAN_RWD_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_RWD) RAM Watchdog  Reset Value */
+
+#define CAN_RWD_WDC_Pos                       _UINT32_(0)                                          /* (CAN_RWD) Watchdog Configuration Position */
+#define CAN_RWD_WDC_Msk                       (_UINT32_(0xFF) << CAN_RWD_WDC_Pos)                  /* (CAN_RWD) Watchdog Configuration Mask */
+#define CAN_RWD_WDC(value)                    (CAN_RWD_WDC_Msk & (_UINT32_(value) << CAN_RWD_WDC_Pos)) /* Assignment of value for WDC in the CAN_RWD register */
+#define CAN_RWD_WDV_Pos                       _UINT32_(8)                                          /* (CAN_RWD) Watchdog Value Position */
+#define CAN_RWD_WDV_Msk                       (_UINT32_(0xFF) << CAN_RWD_WDV_Pos)                  /* (CAN_RWD) Watchdog Value Mask */
+#define CAN_RWD_WDV(value)                    (CAN_RWD_WDV_Msk & (_UINT32_(value) << CAN_RWD_WDV_Pos)) /* Assignment of value for WDV in the CAN_RWD register */
+#define CAN_RWD_Msk                           _UINT32_(0x0000FFFF)                                 /* (CAN_RWD) Register Mask  */
+
+
+/* -------- CAN_CCCR : (CAN Offset: 0x118) (R/W 32) CC Control -------- */
+#define CAN_CCCR_RESETVALUE                   _UINT32_(0x01)                                       /*  (CAN_CCCR) CC Control  Reset Value */
+
+#define CAN_CCCR_INIT_Pos                     _UINT32_(0)                                          /* (CAN_CCCR) Initialization Position */
+#define CAN_CCCR_INIT_Msk                     (_UINT32_(0x1) << CAN_CCCR_INIT_Pos)                 /* (CAN_CCCR) Initialization Mask */
+#define CAN_CCCR_INIT(value)                  (CAN_CCCR_INIT_Msk & (_UINT32_(value) << CAN_CCCR_INIT_Pos)) /* Assignment of value for INIT in the CAN_CCCR register */
+#define CAN_CCCR_CCE_Pos                      _UINT32_(1)                                          /* (CAN_CCCR) Configuration Change Enable Position */
+#define CAN_CCCR_CCE_Msk                      (_UINT32_(0x1) << CAN_CCCR_CCE_Pos)                  /* (CAN_CCCR) Configuration Change Enable Mask */
+#define CAN_CCCR_CCE(value)                   (CAN_CCCR_CCE_Msk & (_UINT32_(value) << CAN_CCCR_CCE_Pos)) /* Assignment of value for CCE in the CAN_CCCR register */
+#define CAN_CCCR_ASM_Pos                      _UINT32_(2)                                          /* (CAN_CCCR) ASM Restricted Operation Mode Position */
+#define CAN_CCCR_ASM_Msk                      (_UINT32_(0x1) << CAN_CCCR_ASM_Pos)                  /* (CAN_CCCR) ASM Restricted Operation Mode Mask */
+#define CAN_CCCR_ASM(value)                   (CAN_CCCR_ASM_Msk & (_UINT32_(value) << CAN_CCCR_ASM_Pos)) /* Assignment of value for ASM in the CAN_CCCR register */
+#define CAN_CCCR_CSA_Pos                      _UINT32_(3)                                          /* (CAN_CCCR) Clock Stop Acknowledge Position */
+#define CAN_CCCR_CSA_Msk                      (_UINT32_(0x1) << CAN_CCCR_CSA_Pos)                  /* (CAN_CCCR) Clock Stop Acknowledge Mask */
+#define CAN_CCCR_CSA(value)                   (CAN_CCCR_CSA_Msk & (_UINT32_(value) << CAN_CCCR_CSA_Pos)) /* Assignment of value for CSA in the CAN_CCCR register */
+#define CAN_CCCR_CSR_Pos                      _UINT32_(4)                                          /* (CAN_CCCR) Clock Stop Request Position */
+#define CAN_CCCR_CSR_Msk                      (_UINT32_(0x1) << CAN_CCCR_CSR_Pos)                  /* (CAN_CCCR) Clock Stop Request Mask */
+#define CAN_CCCR_CSR(value)                   (CAN_CCCR_CSR_Msk & (_UINT32_(value) << CAN_CCCR_CSR_Pos)) /* Assignment of value for CSR in the CAN_CCCR register */
+#define CAN_CCCR_MON_Pos                      _UINT32_(5)                                          /* (CAN_CCCR) Bus Monitoring Mode Position */
+#define CAN_CCCR_MON_Msk                      (_UINT32_(0x1) << CAN_CCCR_MON_Pos)                  /* (CAN_CCCR) Bus Monitoring Mode Mask */
+#define CAN_CCCR_MON(value)                   (CAN_CCCR_MON_Msk & (_UINT32_(value) << CAN_CCCR_MON_Pos)) /* Assignment of value for MON in the CAN_CCCR register */
+#define CAN_CCCR_DAR_Pos                      _UINT32_(6)                                          /* (CAN_CCCR) Disable Automatic Retransmission Position */
+#define CAN_CCCR_DAR_Msk                      (_UINT32_(0x1) << CAN_CCCR_DAR_Pos)                  /* (CAN_CCCR) Disable Automatic Retransmission Mask */
+#define CAN_CCCR_DAR(value)                   (CAN_CCCR_DAR_Msk & (_UINT32_(value) << CAN_CCCR_DAR_Pos)) /* Assignment of value for DAR in the CAN_CCCR register */
+#define CAN_CCCR_TEST_Pos                     _UINT32_(7)                                          /* (CAN_CCCR) Test Mode Enable Position */
+#define CAN_CCCR_TEST_Msk                     (_UINT32_(0x1) << CAN_CCCR_TEST_Pos)                 /* (CAN_CCCR) Test Mode Enable Mask */
+#define CAN_CCCR_TEST(value)                  (CAN_CCCR_TEST_Msk & (_UINT32_(value) << CAN_CCCR_TEST_Pos)) /* Assignment of value for TEST in the CAN_CCCR register */
+#define CAN_CCCR_FDOE_Pos                     _UINT32_(8)                                          /* (CAN_CCCR) FD Operation Enable Position */
+#define CAN_CCCR_FDOE_Msk                     (_UINT32_(0x1) << CAN_CCCR_FDOE_Pos)                 /* (CAN_CCCR) FD Operation Enable Mask */
+#define CAN_CCCR_FDOE(value)                  (CAN_CCCR_FDOE_Msk & (_UINT32_(value) << CAN_CCCR_FDOE_Pos)) /* Assignment of value for FDOE in the CAN_CCCR register */
+#define CAN_CCCR_BRSE_Pos                     _UINT32_(9)                                          /* (CAN_CCCR) Bit Rate Switch Enable Position */
+#define CAN_CCCR_BRSE_Msk                     (_UINT32_(0x1) << CAN_CCCR_BRSE_Pos)                 /* (CAN_CCCR) Bit Rate Switch Enable Mask */
+#define CAN_CCCR_BRSE(value)                  (CAN_CCCR_BRSE_Msk & (_UINT32_(value) << CAN_CCCR_BRSE_Pos)) /* Assignment of value for BRSE in the CAN_CCCR register */
+#define CAN_CCCR_UTSU_Pos                     _UINT32_(10)                                         /* (CAN_CCCR) Use Timestamping Unit Position */
+#define CAN_CCCR_UTSU_Msk                     (_UINT32_(0x1) << CAN_CCCR_UTSU_Pos)                 /* (CAN_CCCR) Use Timestamping Unit Mask */
+#define CAN_CCCR_UTSU(value)                  (CAN_CCCR_UTSU_Msk & (_UINT32_(value) << CAN_CCCR_UTSU_Pos)) /* Assignment of value for UTSU in the CAN_CCCR register */
+#define CAN_CCCR_WMM_Pos                      _UINT32_(11)                                         /* (CAN_CCCR) Wide Message Marker Position */
+#define CAN_CCCR_WMM_Msk                      (_UINT32_(0x1) << CAN_CCCR_WMM_Pos)                  /* (CAN_CCCR) Wide Message Marker Mask */
+#define CAN_CCCR_WMM(value)                   (CAN_CCCR_WMM_Msk & (_UINT32_(value) << CAN_CCCR_WMM_Pos)) /* Assignment of value for WMM in the CAN_CCCR register */
+#define CAN_CCCR_PXHD_Pos                     _UINT32_(12)                                         /* (CAN_CCCR) Protocol Exception Handling Disable Position */
+#define CAN_CCCR_PXHD_Msk                     (_UINT32_(0x1) << CAN_CCCR_PXHD_Pos)                 /* (CAN_CCCR) Protocol Exception Handling Disable Mask */
+#define CAN_CCCR_PXHD(value)                  (CAN_CCCR_PXHD_Msk & (_UINT32_(value) << CAN_CCCR_PXHD_Pos)) /* Assignment of value for PXHD in the CAN_CCCR register */
+#define CAN_CCCR_EFBI_Pos                     _UINT32_(13)                                         /* (CAN_CCCR) Edge Filtering during Bus Integration Position */
+#define CAN_CCCR_EFBI_Msk                     (_UINT32_(0x1) << CAN_CCCR_EFBI_Pos)                 /* (CAN_CCCR) Edge Filtering during Bus Integration Mask */
+#define CAN_CCCR_EFBI(value)                  (CAN_CCCR_EFBI_Msk & (_UINT32_(value) << CAN_CCCR_EFBI_Pos)) /* Assignment of value for EFBI in the CAN_CCCR register */
+#define CAN_CCCR_TXP_Pos                      _UINT32_(14)                                         /* (CAN_CCCR) Transmit Pause Position */
+#define CAN_CCCR_TXP_Msk                      (_UINT32_(0x1) << CAN_CCCR_TXP_Pos)                  /* (CAN_CCCR) Transmit Pause Mask */
+#define CAN_CCCR_TXP(value)                   (CAN_CCCR_TXP_Msk & (_UINT32_(value) << CAN_CCCR_TXP_Pos)) /* Assignment of value for TXP in the CAN_CCCR register */
+#define CAN_CCCR_Msk                          _UINT32_(0x00007FFF)                                 /* (CAN_CCCR) Register Mask  */
+
+
+/* -------- CAN_NBTP : (CAN Offset: 0x11C) (R/W 32) Nominal Bit Timing and Prescaler -------- */
+#define CAN_NBTP_RESETVALUE                   _UINT32_(0x6000A03)                                  /*  (CAN_NBTP) Nominal Bit Timing and Prescaler  Reset Value */
+
+#define CAN_NBTP_NTSEG2_Pos                   _UINT32_(0)                                          /* (CAN_NBTP) Nominal Time segment after sample point Position */
+#define CAN_NBTP_NTSEG2_Msk                   (_UINT32_(0x7F) << CAN_NBTP_NTSEG2_Pos)              /* (CAN_NBTP) Nominal Time segment after sample point Mask */
+#define CAN_NBTP_NTSEG2(value)                (CAN_NBTP_NTSEG2_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG2_Pos)) /* Assignment of value for NTSEG2 in the CAN_NBTP register */
+#define CAN_NBTP_NTSEG1_Pos                   _UINT32_(8)                                          /* (CAN_NBTP) Nominal Time segment before sample point Position */
+#define CAN_NBTP_NTSEG1_Msk                   (_UINT32_(0xFF) << CAN_NBTP_NTSEG1_Pos)              /* (CAN_NBTP) Nominal Time segment before sample point Mask */
+#define CAN_NBTP_NTSEG1(value)                (CAN_NBTP_NTSEG1_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG1_Pos)) /* Assignment of value for NTSEG1 in the CAN_NBTP register */
+#define CAN_NBTP_NBRP_Pos                     _UINT32_(16)                                         /* (CAN_NBTP) Nominal Baud Rate Prescaler Position */
+#define CAN_NBTP_NBRP_Msk                     (_UINT32_(0x1FF) << CAN_NBTP_NBRP_Pos)               /* (CAN_NBTP) Nominal Baud Rate Prescaler Mask */
+#define CAN_NBTP_NBRP(value)                  (CAN_NBTP_NBRP_Msk & (_UINT32_(value) << CAN_NBTP_NBRP_Pos)) /* Assignment of value for NBRP in the CAN_NBTP register */
+#define CAN_NBTP_NSJW_Pos                     _UINT32_(25)                                         /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Position */
+#define CAN_NBTP_NSJW_Msk                     (_UINT32_(0x7F) << CAN_NBTP_NSJW_Pos)                /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Mask */
+#define CAN_NBTP_NSJW(value)                  (CAN_NBTP_NSJW_Msk & (_UINT32_(value) << CAN_NBTP_NSJW_Pos)) /* Assignment of value for NSJW in the CAN_NBTP register */
+#define CAN_NBTP_Msk                          _UINT32_(0xFFFFFF7F)                                 /* (CAN_NBTP) Register Mask  */
+
+
+/* -------- CAN_TSCC : (CAN Offset: 0x120) (R/W 32) Timestamp Counter Configuration -------- */
+#define CAN_TSCC_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TSCC) Timestamp Counter Configuration  Reset Value */
+
+#define CAN_TSCC_TSS_Pos                      _UINT32_(0)                                          /* (CAN_TSCC) Timestamp Select Position */
+#define CAN_TSCC_TSS_Msk                      (_UINT32_(0x3) << CAN_TSCC_TSS_Pos)                  /* (CAN_TSCC) Timestamp Select Mask */
+#define CAN_TSCC_TSS(value)                   (CAN_TSCC_TSS_Msk & (_UINT32_(value) << CAN_TSCC_TSS_Pos)) /* Assignment of value for TSS in the CAN_TSCC register */
+#define   CAN_TSCC_TSS_ZERO_Val               _UINT32_(0x0)                                        /* (CAN_TSCC) Timestamp counter value always 0x0000  */
+#define   CAN_TSCC_TSS_INC_Val                _UINT32_(0x1)                                        /* (CAN_TSCC) Timestamp counter value incremented by TCP  */
+#define   CAN_TSCC_TSS_EXT_Val                _UINT32_(0x2)                                        /* (CAN_TSCC) External timestamp counter value used  */
+#define CAN_TSCC_TSS_ZERO                     (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos)          /* (CAN_TSCC) Timestamp counter value always 0x0000 Position */
+#define CAN_TSCC_TSS_INC                      (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos)           /* (CAN_TSCC) Timestamp counter value incremented by TCP Position */
+#define CAN_TSCC_TSS_EXT                      (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos)           /* (CAN_TSCC) External timestamp counter value used Position */
+#define CAN_TSCC_TCP_Pos                      _UINT32_(16)                                         /* (CAN_TSCC) Timestamp Counter Prescaler Position */
+#define CAN_TSCC_TCP_Msk                      (_UINT32_(0xF) << CAN_TSCC_TCP_Pos)                  /* (CAN_TSCC) Timestamp Counter Prescaler Mask */
+#define CAN_TSCC_TCP(value)                   (CAN_TSCC_TCP_Msk & (_UINT32_(value) << CAN_TSCC_TCP_Pos)) /* Assignment of value for TCP in the CAN_TSCC register */
+#define CAN_TSCC_Msk                          _UINT32_(0x000F0003)                                 /* (CAN_TSCC) Register Mask  */
+
+
+/* -------- CAN_TSCV : (CAN Offset: 0x124) ( R/ 32) Timestamp Counter Value -------- */
+#define CAN_TSCV_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TSCV) Timestamp Counter Value  Reset Value */
+
+#define CAN_TSCV_TSC_Pos                      _UINT32_(0)                                          /* (CAN_TSCV) Timestamp Counter Position */
+#define CAN_TSCV_TSC_Msk                      (_UINT32_(0xFFFF) << CAN_TSCV_TSC_Pos)               /* (CAN_TSCV) Timestamp Counter Mask */
+#define CAN_TSCV_TSC(value)                   (CAN_TSCV_TSC_Msk & (_UINT32_(value) << CAN_TSCV_TSC_Pos)) /* Assignment of value for TSC in the CAN_TSCV register */
+#define CAN_TSCV_Msk                          _UINT32_(0x0000FFFF)                                 /* (CAN_TSCV) Register Mask  */
+
+
+/* -------- CAN_TOCC : (CAN Offset: 0x128) (R/W 32) Timeout Counter Configuration -------- */
+#define CAN_TOCC_RESETVALUE                   _UINT32_(0xFFFF0000)                                 /*  (CAN_TOCC) Timeout Counter Configuration  Reset Value */
+
+#define CAN_TOCC_ETOC_Pos                     _UINT32_(0)                                          /* (CAN_TOCC) Enable Timeout Counter Position */
+#define CAN_TOCC_ETOC_Msk                     (_UINT32_(0x1) << CAN_TOCC_ETOC_Pos)                 /* (CAN_TOCC) Enable Timeout Counter Mask */
+#define CAN_TOCC_ETOC(value)                  (CAN_TOCC_ETOC_Msk & (_UINT32_(value) << CAN_TOCC_ETOC_Pos)) /* Assignment of value for ETOC in the CAN_TOCC register */
+#define CAN_TOCC_TOS_Pos                      _UINT32_(1)                                          /* (CAN_TOCC) Timeout Select Position */
+#define CAN_TOCC_TOS_Msk                      (_UINT32_(0x3) << CAN_TOCC_TOS_Pos)                  /* (CAN_TOCC) Timeout Select Mask */
+#define CAN_TOCC_TOS(value)                   (CAN_TOCC_TOS_Msk & (_UINT32_(value) << CAN_TOCC_TOS_Pos)) /* Assignment of value for TOS in the CAN_TOCC register */
+#define   CAN_TOCC_TOS_CONT_Val               _UINT32_(0x0)                                        /* (CAN_TOCC) Continuout operation  */
+#define   CAN_TOCC_TOS_TXEF_Val               _UINT32_(0x1)                                        /* (CAN_TOCC) Timeout controlled by TX Event FIFO  */
+#define   CAN_TOCC_TOS_RXF0_Val               _UINT32_(0x2)                                        /* (CAN_TOCC) Timeout controlled by Rx FIFO 0  */
+#define   CAN_TOCC_TOS_RXF1_Val               _UINT32_(0x3)                                        /* (CAN_TOCC) Timeout controlled by Rx FIFO 1  */
+#define CAN_TOCC_TOS_CONT                     (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos)          /* (CAN_TOCC) Continuout operation Position */
+#define CAN_TOCC_TOS_TXEF                     (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos)          /* (CAN_TOCC) Timeout controlled by TX Event FIFO Position */
+#define CAN_TOCC_TOS_RXF0                     (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos)          /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 Position */
+#define CAN_TOCC_TOS_RXF1                     (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos)          /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 Position */
+#define CAN_TOCC_TOP_Pos                      _UINT32_(16)                                         /* (CAN_TOCC) Timeout Period Position */
+#define CAN_TOCC_TOP_Msk                      (_UINT32_(0xFFFF) << CAN_TOCC_TOP_Pos)               /* (CAN_TOCC) Timeout Period Mask */
+#define CAN_TOCC_TOP(value)                   (CAN_TOCC_TOP_Msk & (_UINT32_(value) << CAN_TOCC_TOP_Pos)) /* Assignment of value for TOP in the CAN_TOCC register */
+#define CAN_TOCC_Msk                          _UINT32_(0xFFFF0007)                                 /* (CAN_TOCC) Register Mask  */
+
+
+/* -------- CAN_TOCV : (CAN Offset: 0x12C) (R/W 32) Timeout Counter Value -------- */
+#define CAN_TOCV_RESETVALUE                   _UINT32_(0xFFFF)                                     /*  (CAN_TOCV) Timeout Counter Value  Reset Value */
+
+#define CAN_TOCV_TOC_Pos                      _UINT32_(0)                                          /* (CAN_TOCV) Timeout Counter Position */
+#define CAN_TOCV_TOC_Msk                      (_UINT32_(0xFFFF) << CAN_TOCV_TOC_Pos)               /* (CAN_TOCV) Timeout Counter Mask */
+#define CAN_TOCV_TOC(value)                   (CAN_TOCV_TOC_Msk & (_UINT32_(value) << CAN_TOCV_TOC_Pos)) /* Assignment of value for TOC in the CAN_TOCV register */
+#define CAN_TOCV_Msk                          _UINT32_(0x0000FFFF)                                 /* (CAN_TOCV) Register Mask  */
+
+
+/* -------- CAN_ECR : (CAN Offset: 0x140) ( R/ 32) Error Counter -------- */
+#define CAN_ECR_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_ECR) Error Counter  Reset Value */
+
+#define CAN_ECR_TEC_Pos                       _UINT32_(0)                                          /* (CAN_ECR) Transmit Error Counter Position */
+#define CAN_ECR_TEC_Msk                       (_UINT32_(0xFF) << CAN_ECR_TEC_Pos)                  /* (CAN_ECR) Transmit Error Counter Mask */
+#define CAN_ECR_TEC(value)                    (CAN_ECR_TEC_Msk & (_UINT32_(value) << CAN_ECR_TEC_Pos)) /* Assignment of value for TEC in the CAN_ECR register */
+#define CAN_ECR_REC_Pos                       _UINT32_(8)                                          /* (CAN_ECR) Receive Error Counter Position */
+#define CAN_ECR_REC_Msk                       (_UINT32_(0x7F) << CAN_ECR_REC_Pos)                  /* (CAN_ECR) Receive Error Counter Mask */
+#define CAN_ECR_REC(value)                    (CAN_ECR_REC_Msk & (_UINT32_(value) << CAN_ECR_REC_Pos)) /* Assignment of value for REC in the CAN_ECR register */
+#define CAN_ECR_RP_Pos                        _UINT32_(15)                                         /* (CAN_ECR) Receive Error Passive Position */
+#define CAN_ECR_RP_Msk                        (_UINT32_(0x1) << CAN_ECR_RP_Pos)                    /* (CAN_ECR) Receive Error Passive Mask */
+#define CAN_ECR_RP(value)                     (CAN_ECR_RP_Msk & (_UINT32_(value) << CAN_ECR_RP_Pos)) /* Assignment of value for RP in the CAN_ECR register */
+#define CAN_ECR_CEL_Pos                       _UINT32_(16)                                         /* (CAN_ECR) CAN Error Logging Position */
+#define CAN_ECR_CEL_Msk                       (_UINT32_(0xFF) << CAN_ECR_CEL_Pos)                  /* (CAN_ECR) CAN Error Logging Mask */
+#define CAN_ECR_CEL(value)                    (CAN_ECR_CEL_Msk & (_UINT32_(value) << CAN_ECR_CEL_Pos)) /* Assignment of value for CEL in the CAN_ECR register */
+#define CAN_ECR_Msk                           _UINT32_(0x00FFFFFF)                                 /* (CAN_ECR) Register Mask  */
+
+
+/* -------- CAN_PSR : (CAN Offset: 0x144) ( R/ 32) Protocol Status -------- */
+#define CAN_PSR_RESETVALUE                    _UINT32_(0x707)                                      /*  (CAN_PSR) Protocol Status  Reset Value */
+
+#define CAN_PSR_LEC_Pos                       _UINT32_(0)                                          /* (CAN_PSR) Last Error Code Position */
+#define CAN_PSR_LEC_Msk                       (_UINT32_(0x7) << CAN_PSR_LEC_Pos)                   /* (CAN_PSR) Last Error Code Mask */
+#define CAN_PSR_LEC(value)                    (CAN_PSR_LEC_Msk & (_UINT32_(value) << CAN_PSR_LEC_Pos)) /* Assignment of value for LEC in the CAN_PSR register */
+#define   CAN_PSR_LEC_NONE_Val                _UINT32_(0x0)                                        /* (CAN_PSR) No Error  */
+#define   CAN_PSR_LEC_STUFF_Val               _UINT32_(0x1)                                        /* (CAN_PSR) Stuff Error  */
+#define   CAN_PSR_LEC_FORM_Val                _UINT32_(0x2)                                        /* (CAN_PSR) Form Error  */
+#define   CAN_PSR_LEC_ACK_Val                 _UINT32_(0x3)                                        /* (CAN_PSR) Ack Error  */
+#define   CAN_PSR_LEC_BIT1_Val                _UINT32_(0x4)                                        /* (CAN_PSR) Bit1 Error  */
+#define   CAN_PSR_LEC_BIT0_Val                _UINT32_(0x5)                                        /* (CAN_PSR) Bit0 Error  */
+#define   CAN_PSR_LEC_CRC_Val                 _UINT32_(0x6)                                        /* (CAN_PSR) CRC Error  */
+#define   CAN_PSR_LEC_NC_Val                  _UINT32_(0x7)                                        /* (CAN_PSR) No Change  */
+#define CAN_PSR_LEC_NONE                      (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos)            /* (CAN_PSR) No Error Position */
+#define CAN_PSR_LEC_STUFF                     (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos)           /* (CAN_PSR) Stuff Error Position */
+#define CAN_PSR_LEC_FORM                      (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos)            /* (CAN_PSR) Form Error Position */
+#define CAN_PSR_LEC_ACK                       (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos)             /* (CAN_PSR) Ack Error Position */
+#define CAN_PSR_LEC_BIT1                      (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos)            /* (CAN_PSR) Bit1 Error Position */
+#define CAN_PSR_LEC_BIT0                      (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos)            /* (CAN_PSR) Bit0 Error Position */
+#define CAN_PSR_LEC_CRC                       (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos)             /* (CAN_PSR) CRC Error Position */
+#define CAN_PSR_LEC_NC                        (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos)              /* (CAN_PSR) No Change Position */
+#define CAN_PSR_ACT_Pos                       _UINT32_(3)                                          /* (CAN_PSR) Activity Position */
+#define CAN_PSR_ACT_Msk                       (_UINT32_(0x3) << CAN_PSR_ACT_Pos)                   /* (CAN_PSR) Activity Mask */
+#define CAN_PSR_ACT(value)                    (CAN_PSR_ACT_Msk & (_UINT32_(value) << CAN_PSR_ACT_Pos)) /* Assignment of value for ACT in the CAN_PSR register */
+#define   CAN_PSR_ACT_SYNC_Val                _UINT32_(0x0)                                        /* (CAN_PSR) Node is synchronizing on CAN communication  */
+#define   CAN_PSR_ACT_IDLE_Val                _UINT32_(0x1)                                        /* (CAN_PSR) Node is neither receiver nor transmitter  */
+#define   CAN_PSR_ACT_RX_Val                  _UINT32_(0x2)                                        /* (CAN_PSR) Node is operating as receiver  */
+#define   CAN_PSR_ACT_TX_Val                  _UINT32_(0x3)                                        /* (CAN_PSR) Node is operating as transmitter  */
+#define CAN_PSR_ACT_SYNC                      (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos)            /* (CAN_PSR) Node is synchronizing on CAN communication Position */
+#define CAN_PSR_ACT_IDLE                      (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos)            /* (CAN_PSR) Node is neither receiver nor transmitter Position */
+#define CAN_PSR_ACT_RX                        (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos)              /* (CAN_PSR) Node is operating as receiver Position */
+#define CAN_PSR_ACT_TX                        (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos)              /* (CAN_PSR) Node is operating as transmitter Position */
+#define CAN_PSR_EP_Pos                        _UINT32_(5)                                          /* (CAN_PSR) Error Passive Position */
+#define CAN_PSR_EP_Msk                        (_UINT32_(0x1) << CAN_PSR_EP_Pos)                    /* (CAN_PSR) Error Passive Mask */
+#define CAN_PSR_EP(value)                     (CAN_PSR_EP_Msk & (_UINT32_(value) << CAN_PSR_EP_Pos)) /* Assignment of value for EP in the CAN_PSR register */
+#define CAN_PSR_EW_Pos                        _UINT32_(6)                                          /* (CAN_PSR) Warning Status Position */
+#define CAN_PSR_EW_Msk                        (_UINT32_(0x1) << CAN_PSR_EW_Pos)                    /* (CAN_PSR) Warning Status Mask */
+#define CAN_PSR_EW(value)                     (CAN_PSR_EW_Msk & (_UINT32_(value) << CAN_PSR_EW_Pos)) /* Assignment of value for EW in the CAN_PSR register */
+#define CAN_PSR_BO_Pos                        _UINT32_(7)                                          /* (CAN_PSR) Bus_Off Status Position */
+#define CAN_PSR_BO_Msk                        (_UINT32_(0x1) << CAN_PSR_BO_Pos)                    /* (CAN_PSR) Bus_Off Status Mask */
+#define CAN_PSR_BO(value)                     (CAN_PSR_BO_Msk & (_UINT32_(value) << CAN_PSR_BO_Pos)) /* Assignment of value for BO in the CAN_PSR register */
+#define CAN_PSR_DLEC_Pos                      _UINT32_(8)                                          /* (CAN_PSR) Data Phase Last Error Code Position */
+#define CAN_PSR_DLEC_Msk                      (_UINT32_(0x7) << CAN_PSR_DLEC_Pos)                  /* (CAN_PSR) Data Phase Last Error Code Mask */
+#define CAN_PSR_DLEC(value)                   (CAN_PSR_DLEC_Msk & (_UINT32_(value) << CAN_PSR_DLEC_Pos)) /* Assignment of value for DLEC in the CAN_PSR register */
+#define   CAN_PSR_DLEC_NONE_Val               _UINT32_(0x0)                                        /* (CAN_PSR) No Error  */
+#define   CAN_PSR_DLEC_STUFF_Val              _UINT32_(0x1)                                        /* (CAN_PSR) Stuff Error  */
+#define   CAN_PSR_DLEC_FORM_Val               _UINT32_(0x2)                                        /* (CAN_PSR) Form Error  */
+#define   CAN_PSR_DLEC_ACK_Val                _UINT32_(0x3)                                        /* (CAN_PSR) Ack Error  */
+#define   CAN_PSR_DLEC_BIT1_Val               _UINT32_(0x4)                                        /* (CAN_PSR) Bit1 Error  */
+#define   CAN_PSR_DLEC_BIT0_Val               _UINT32_(0x5)                                        /* (CAN_PSR) Bit0 Error  */
+#define   CAN_PSR_DLEC_CRC_Val                _UINT32_(0x6)                                        /* (CAN_PSR) CRC Error  */
+#define   CAN_PSR_DLEC_NC_Val                 _UINT32_(0x7)                                        /* (CAN_PSR) No Change  */
+#define CAN_PSR_DLEC_NONE                     (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos)          /* (CAN_PSR) No Error Position */
+#define CAN_PSR_DLEC_STUFF                    (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos)         /* (CAN_PSR) Stuff Error Position */
+#define CAN_PSR_DLEC_FORM                     (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos)          /* (CAN_PSR) Form Error Position */
+#define CAN_PSR_DLEC_ACK                      (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos)           /* (CAN_PSR) Ack Error Position */
+#define CAN_PSR_DLEC_BIT1                     (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos)          /* (CAN_PSR) Bit1 Error Position */
+#define CAN_PSR_DLEC_BIT0                     (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos)          /* (CAN_PSR) Bit0 Error Position */
+#define CAN_PSR_DLEC_CRC                      (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos)           /* (CAN_PSR) CRC Error Position */
+#define CAN_PSR_DLEC_NC                       (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos)            /* (CAN_PSR) No Change Position */
+#define CAN_PSR_RESI_Pos                      _UINT32_(11)                                         /* (CAN_PSR) ESI flag of last received CAN FD Message Position */
+#define CAN_PSR_RESI_Msk                      (_UINT32_(0x1) << CAN_PSR_RESI_Pos)                  /* (CAN_PSR) ESI flag of last received CAN FD Message Mask */
+#define CAN_PSR_RESI(value)                   (CAN_PSR_RESI_Msk & (_UINT32_(value) << CAN_PSR_RESI_Pos)) /* Assignment of value for RESI in the CAN_PSR register */
+#define CAN_PSR_RBRS_Pos                      _UINT32_(12)                                         /* (CAN_PSR) BRS flag of last received CAN FD Message Position */
+#define CAN_PSR_RBRS_Msk                      (_UINT32_(0x1) << CAN_PSR_RBRS_Pos)                  /* (CAN_PSR) BRS flag of last received CAN FD Message Mask */
+#define CAN_PSR_RBRS(value)                   (CAN_PSR_RBRS_Msk & (_UINT32_(value) << CAN_PSR_RBRS_Pos)) /* Assignment of value for RBRS in the CAN_PSR register */
+#define CAN_PSR_RFDF_Pos                      _UINT32_(13)                                         /* (CAN_PSR) Received a CAN FD Message Position */
+#define CAN_PSR_RFDF_Msk                      (_UINT32_(0x1) << CAN_PSR_RFDF_Pos)                  /* (CAN_PSR) Received a CAN FD Message Mask */
+#define CAN_PSR_RFDF(value)                   (CAN_PSR_RFDF_Msk & (_UINT32_(value) << CAN_PSR_RFDF_Pos)) /* Assignment of value for RFDF in the CAN_PSR register */
+#define CAN_PSR_PXE_Pos                       _UINT32_(14)                                         /* (CAN_PSR) Protocol Exception Event Position */
+#define CAN_PSR_PXE_Msk                       (_UINT32_(0x1) << CAN_PSR_PXE_Pos)                   /* (CAN_PSR) Protocol Exception Event Mask */
+#define CAN_PSR_PXE(value)                    (CAN_PSR_PXE_Msk & (_UINT32_(value) << CAN_PSR_PXE_Pos)) /* Assignment of value for PXE in the CAN_PSR register */
+#define CAN_PSR_TDCV_Pos                      _UINT32_(16)                                         /* (CAN_PSR) Transmitter Delay Compensation Value Position */
+#define CAN_PSR_TDCV_Msk                      (_UINT32_(0x7F) << CAN_PSR_TDCV_Pos)                 /* (CAN_PSR) Transmitter Delay Compensation Value Mask */
+#define CAN_PSR_TDCV(value)                   (CAN_PSR_TDCV_Msk & (_UINT32_(value) << CAN_PSR_TDCV_Pos)) /* Assignment of value for TDCV in the CAN_PSR register */
+#define CAN_PSR_Msk                           _UINT32_(0x007F7FFF)                                 /* (CAN_PSR) Register Mask  */
+
+
+/* -------- CAN_TDCR : (CAN Offset: 0x148) (R/W 32) Extended ID Filter Configuration -------- */
+#define CAN_TDCR_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TDCR) Extended ID Filter Configuration  Reset Value */
+
+#define CAN_TDCR_TDCF_Pos                     _UINT32_(0)                                          /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Position */
+#define CAN_TDCR_TDCF_Msk                     (_UINT32_(0x7F) << CAN_TDCR_TDCF_Pos)                /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Mask */
+#define CAN_TDCR_TDCF(value)                  (CAN_TDCR_TDCF_Msk & (_UINT32_(value) << CAN_TDCR_TDCF_Pos)) /* Assignment of value for TDCF in the CAN_TDCR register */
+#define CAN_TDCR_TDCO_Pos                     _UINT32_(8)                                          /* (CAN_TDCR) Transmitter Delay Compensation Offset Position */
+#define CAN_TDCR_TDCO_Msk                     (_UINT32_(0x7F) << CAN_TDCR_TDCO_Pos)                /* (CAN_TDCR) Transmitter Delay Compensation Offset Mask */
+#define CAN_TDCR_TDCO(value)                  (CAN_TDCR_TDCO_Msk & (_UINT32_(value) << CAN_TDCR_TDCO_Pos)) /* Assignment of value for TDCO in the CAN_TDCR register */
+#define CAN_TDCR_Msk                          _UINT32_(0x00007F7F)                                 /* (CAN_TDCR) Register Mask  */
+
+
+/* -------- CAN_IR : (CAN Offset: 0x150) (R/W 32) Interrupt -------- */
+#define CAN_IR_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_IR) Interrupt  Reset Value */
+
+#define CAN_IR_RF0N_Pos                       _UINT32_(0)                                          /* (CAN_IR) Rx FIFO 0 New Message Position */
+#define CAN_IR_RF0N_Msk                       (_UINT32_(0x1) << CAN_IR_RF0N_Pos)                   /* (CAN_IR) Rx FIFO 0 New Message Mask */
+#define CAN_IR_RF0N(value)                    (CAN_IR_RF0N_Msk & (_UINT32_(value) << CAN_IR_RF0N_Pos)) /* Assignment of value for RF0N in the CAN_IR register */
+#define CAN_IR_RF0W_Pos                       _UINT32_(1)                                          /* (CAN_IR) Rx FIFO 0 Watermark Reached Position */
+#define CAN_IR_RF0W_Msk                       (_UINT32_(0x1) << CAN_IR_RF0W_Pos)                   /* (CAN_IR) Rx FIFO 0 Watermark Reached Mask */
+#define CAN_IR_RF0W(value)                    (CAN_IR_RF0W_Msk & (_UINT32_(value) << CAN_IR_RF0W_Pos)) /* Assignment of value for RF0W in the CAN_IR register */
+#define CAN_IR_RF0F_Pos                       _UINT32_(2)                                          /* (CAN_IR) Rx FIFO 0 Full Position */
+#define CAN_IR_RF0F_Msk                       (_UINT32_(0x1) << CAN_IR_RF0F_Pos)                   /* (CAN_IR) Rx FIFO 0 Full Mask */
+#define CAN_IR_RF0F(value)                    (CAN_IR_RF0F_Msk & (_UINT32_(value) << CAN_IR_RF0F_Pos)) /* Assignment of value for RF0F in the CAN_IR register */
+#define CAN_IR_RF0L_Pos                       _UINT32_(3)                                          /* (CAN_IR) Rx FIFO 0 Message Lost Position */
+#define CAN_IR_RF0L_Msk                       (_UINT32_(0x1) << CAN_IR_RF0L_Pos)                   /* (CAN_IR) Rx FIFO 0 Message Lost Mask */
+#define CAN_IR_RF0L(value)                    (CAN_IR_RF0L_Msk & (_UINT32_(value) << CAN_IR_RF0L_Pos)) /* Assignment of value for RF0L in the CAN_IR register */
+#define CAN_IR_RF1N_Pos                       _UINT32_(4)                                          /* (CAN_IR) Rx FIFO 1 New Message Position */
+#define CAN_IR_RF1N_Msk                       (_UINT32_(0x1) << CAN_IR_RF1N_Pos)                   /* (CAN_IR) Rx FIFO 1 New Message Mask */
+#define CAN_IR_RF1N(value)                    (CAN_IR_RF1N_Msk & (_UINT32_(value) << CAN_IR_RF1N_Pos)) /* Assignment of value for RF1N in the CAN_IR register */
+#define CAN_IR_RF1W_Pos                       _UINT32_(5)                                          /* (CAN_IR) Rx FIFO 1 Watermark Reached Position */
+#define CAN_IR_RF1W_Msk                       (_UINT32_(0x1) << CAN_IR_RF1W_Pos)                   /* (CAN_IR) Rx FIFO 1 Watermark Reached Mask */
+#define CAN_IR_RF1W(value)                    (CAN_IR_RF1W_Msk & (_UINT32_(value) << CAN_IR_RF1W_Pos)) /* Assignment of value for RF1W in the CAN_IR register */
+#define CAN_IR_RF1F_Pos                       _UINT32_(6)                                          /* (CAN_IR) Rx FIFO 1 FIFO Full Position */
+#define CAN_IR_RF1F_Msk                       (_UINT32_(0x1) << CAN_IR_RF1F_Pos)                   /* (CAN_IR) Rx FIFO 1 FIFO Full Mask */
+#define CAN_IR_RF1F(value)                    (CAN_IR_RF1F_Msk & (_UINT32_(value) << CAN_IR_RF1F_Pos)) /* Assignment of value for RF1F in the CAN_IR register */
+#define CAN_IR_RF1L_Pos                       _UINT32_(7)                                          /* (CAN_IR) Rx FIFO 1 Message Lost Position */
+#define CAN_IR_RF1L_Msk                       (_UINT32_(0x1) << CAN_IR_RF1L_Pos)                   /* (CAN_IR) Rx FIFO 1 Message Lost Mask */
+#define CAN_IR_RF1L(value)                    (CAN_IR_RF1L_Msk & (_UINT32_(value) << CAN_IR_RF1L_Pos)) /* Assignment of value for RF1L in the CAN_IR register */
+#define CAN_IR_HPM_Pos                        _UINT32_(8)                                          /* (CAN_IR) High Priority Message Position */
+#define CAN_IR_HPM_Msk                        (_UINT32_(0x1) << CAN_IR_HPM_Pos)                    /* (CAN_IR) High Priority Message Mask */
+#define CAN_IR_HPM(value)                     (CAN_IR_HPM_Msk & (_UINT32_(value) << CAN_IR_HPM_Pos)) /* Assignment of value for HPM in the CAN_IR register */
+#define CAN_IR_TC_Pos                         _UINT32_(9)                                          /* (CAN_IR) Timestamp Completed Position */
+#define CAN_IR_TC_Msk                         (_UINT32_(0x1) << CAN_IR_TC_Pos)                     /* (CAN_IR) Timestamp Completed Mask */
+#define CAN_IR_TC(value)                      (CAN_IR_TC_Msk & (_UINT32_(value) << CAN_IR_TC_Pos)) /* Assignment of value for TC in the CAN_IR register */
+#define CAN_IR_TCF_Pos                        _UINT32_(10)                                         /* (CAN_IR) Transmission Cancellation Finished Position */
+#define CAN_IR_TCF_Msk                        (_UINT32_(0x1) << CAN_IR_TCF_Pos)                    /* (CAN_IR) Transmission Cancellation Finished Mask */
+#define CAN_IR_TCF(value)                     (CAN_IR_TCF_Msk & (_UINT32_(value) << CAN_IR_TCF_Pos)) /* Assignment of value for TCF in the CAN_IR register */
+#define CAN_IR_TFE_Pos                        _UINT32_(11)                                         /* (CAN_IR) Tx FIFO Empty Position */
+#define CAN_IR_TFE_Msk                        (_UINT32_(0x1) << CAN_IR_TFE_Pos)                    /* (CAN_IR) Tx FIFO Empty Mask */
+#define CAN_IR_TFE(value)                     (CAN_IR_TFE_Msk & (_UINT32_(value) << CAN_IR_TFE_Pos)) /* Assignment of value for TFE in the CAN_IR register */
+#define CAN_IR_TEFN_Pos                       _UINT32_(12)                                         /* (CAN_IR) Tx Event FIFO New Entry Position */
+#define CAN_IR_TEFN_Msk                       (_UINT32_(0x1) << CAN_IR_TEFN_Pos)                   /* (CAN_IR) Tx Event FIFO New Entry Mask */
+#define CAN_IR_TEFN(value)                    (CAN_IR_TEFN_Msk & (_UINT32_(value) << CAN_IR_TEFN_Pos)) /* Assignment of value for TEFN in the CAN_IR register */
+#define CAN_IR_TEFW_Pos                       _UINT32_(13)                                         /* (CAN_IR) Tx Event FIFO Watermark Reached Position */
+#define CAN_IR_TEFW_Msk                       (_UINT32_(0x1) << CAN_IR_TEFW_Pos)                   /* (CAN_IR) Tx Event FIFO Watermark Reached Mask */
+#define CAN_IR_TEFW(value)                    (CAN_IR_TEFW_Msk & (_UINT32_(value) << CAN_IR_TEFW_Pos)) /* Assignment of value for TEFW in the CAN_IR register */
+#define CAN_IR_TEFF_Pos                       _UINT32_(14)                                         /* (CAN_IR) Tx Event FIFO Full Position */
+#define CAN_IR_TEFF_Msk                       (_UINT32_(0x1) << CAN_IR_TEFF_Pos)                   /* (CAN_IR) Tx Event FIFO Full Mask */
+#define CAN_IR_TEFF(value)                    (CAN_IR_TEFF_Msk & (_UINT32_(value) << CAN_IR_TEFF_Pos)) /* Assignment of value for TEFF in the CAN_IR register */
+#define CAN_IR_TEFL_Pos                       _UINT32_(15)                                         /* (CAN_IR) Tx Event FIFO Element Lost Position */
+#define CAN_IR_TEFL_Msk                       (_UINT32_(0x1) << CAN_IR_TEFL_Pos)                   /* (CAN_IR) Tx Event FIFO Element Lost Mask */
+#define CAN_IR_TEFL(value)                    (CAN_IR_TEFL_Msk & (_UINT32_(value) << CAN_IR_TEFL_Pos)) /* Assignment of value for TEFL in the CAN_IR register */
+#define CAN_IR_TSW_Pos                        _UINT32_(16)                                         /* (CAN_IR) Timestamp Wraparound Position */
+#define CAN_IR_TSW_Msk                        (_UINT32_(0x1) << CAN_IR_TSW_Pos)                    /* (CAN_IR) Timestamp Wraparound Mask */
+#define CAN_IR_TSW(value)                     (CAN_IR_TSW_Msk & (_UINT32_(value) << CAN_IR_TSW_Pos)) /* Assignment of value for TSW in the CAN_IR register */
+#define CAN_IR_MRAF_Pos                       _UINT32_(17)                                         /* (CAN_IR) Message RAM Access Failure Position */
+#define CAN_IR_MRAF_Msk                       (_UINT32_(0x1) << CAN_IR_MRAF_Pos)                   /* (CAN_IR) Message RAM Access Failure Mask */
+#define CAN_IR_MRAF(value)                    (CAN_IR_MRAF_Msk & (_UINT32_(value) << CAN_IR_MRAF_Pos)) /* Assignment of value for MRAF in the CAN_IR register */
+#define CAN_IR_TOO_Pos                        _UINT32_(18)                                         /* (CAN_IR) Timeout Occurred Position */
+#define CAN_IR_TOO_Msk                        (_UINT32_(0x1) << CAN_IR_TOO_Pos)                    /* (CAN_IR) Timeout Occurred Mask */
+#define CAN_IR_TOO(value)                     (CAN_IR_TOO_Msk & (_UINT32_(value) << CAN_IR_TOO_Pos)) /* Assignment of value for TOO in the CAN_IR register */
+#define CAN_IR_DRX_Pos                        _UINT32_(19)                                         /* (CAN_IR) Message stored to Dedicated Rx Buffer Position */
+#define CAN_IR_DRX_Msk                        (_UINT32_(0x1) << CAN_IR_DRX_Pos)                    /* (CAN_IR) Message stored to Dedicated Rx Buffer Mask */
+#define CAN_IR_DRX(value)                     (CAN_IR_DRX_Msk & (_UINT32_(value) << CAN_IR_DRX_Pos)) /* Assignment of value for DRX in the CAN_IR register */
+#define CAN_IR_ELO_Pos                        _UINT32_(22)                                         /* (CAN_IR) Error Logging Overflow Position */
+#define CAN_IR_ELO_Msk                        (_UINT32_(0x1) << CAN_IR_ELO_Pos)                    /* (CAN_IR) Error Logging Overflow Mask */
+#define CAN_IR_ELO(value)                     (CAN_IR_ELO_Msk & (_UINT32_(value) << CAN_IR_ELO_Pos)) /* Assignment of value for ELO in the CAN_IR register */
+#define CAN_IR_EP_Pos                         _UINT32_(23)                                         /* (CAN_IR) Error Passive Position */
+#define CAN_IR_EP_Msk                         (_UINT32_(0x1) << CAN_IR_EP_Pos)                     /* (CAN_IR) Error Passive Mask */
+#define CAN_IR_EP(value)                      (CAN_IR_EP_Msk & (_UINT32_(value) << CAN_IR_EP_Pos)) /* Assignment of value for EP in the CAN_IR register */
+#define CAN_IR_EW_Pos                         _UINT32_(24)                                         /* (CAN_IR) Warning Status Position */
+#define CAN_IR_EW_Msk                         (_UINT32_(0x1) << CAN_IR_EW_Pos)                     /* (CAN_IR) Warning Status Mask */
+#define CAN_IR_EW(value)                      (CAN_IR_EW_Msk & (_UINT32_(value) << CAN_IR_EW_Pos)) /* Assignment of value for EW in the CAN_IR register */
+#define CAN_IR_BO_Pos                         _UINT32_(25)                                         /* (CAN_IR) Bus_Off Status Position */
+#define CAN_IR_BO_Msk                         (_UINT32_(0x1) << CAN_IR_BO_Pos)                     /* (CAN_IR) Bus_Off Status Mask */
+#define CAN_IR_BO(value)                      (CAN_IR_BO_Msk & (_UINT32_(value) << CAN_IR_BO_Pos)) /* Assignment of value for BO in the CAN_IR register */
+#define CAN_IR_WDI_Pos                        _UINT32_(26)                                         /* (CAN_IR) Watchdog Interrupt Position */
+#define CAN_IR_WDI_Msk                        (_UINT32_(0x1) << CAN_IR_WDI_Pos)                    /* (CAN_IR) Watchdog Interrupt Mask */
+#define CAN_IR_WDI(value)                     (CAN_IR_WDI_Msk & (_UINT32_(value) << CAN_IR_WDI_Pos)) /* Assignment of value for WDI in the CAN_IR register */
+#define CAN_IR_PEA_Pos                        _UINT32_(27)                                         /* (CAN_IR) Protocol Error in Arbitration Phase Position */
+#define CAN_IR_PEA_Msk                        (_UINT32_(0x1) << CAN_IR_PEA_Pos)                    /* (CAN_IR) Protocol Error in Arbitration Phase Mask */
+#define CAN_IR_PEA(value)                     (CAN_IR_PEA_Msk & (_UINT32_(value) << CAN_IR_PEA_Pos)) /* Assignment of value for PEA in the CAN_IR register */
+#define CAN_IR_PED_Pos                        _UINT32_(28)                                         /* (CAN_IR) Protocol Error in Data Phase Position */
+#define CAN_IR_PED_Msk                        (_UINT32_(0x1) << CAN_IR_PED_Pos)                    /* (CAN_IR) Protocol Error in Data Phase Mask */
+#define CAN_IR_PED(value)                     (CAN_IR_PED_Msk & (_UINT32_(value) << CAN_IR_PED_Pos)) /* Assignment of value for PED in the CAN_IR register */
+#define CAN_IR_ARA_Pos                        _UINT32_(29)                                         /* (CAN_IR) Access to Reserved Address Position */
+#define CAN_IR_ARA_Msk                        (_UINT32_(0x1) << CAN_IR_ARA_Pos)                    /* (CAN_IR) Access to Reserved Address Mask */
+#define CAN_IR_ARA(value)                     (CAN_IR_ARA_Msk & (_UINT32_(value) << CAN_IR_ARA_Pos)) /* Assignment of value for ARA in the CAN_IR register */
+#define CAN_IR_Msk                            _UINT32_(0x3FCFFFFF)                                 /* (CAN_IR) Register Mask  */
+
+
+/* -------- CAN_IE : (CAN Offset: 0x154) (R/W 32) Interrupt Enable -------- */
+#define CAN_IE_RESETVALUE                     _UINT32_(0x00)                                       /*  (CAN_IE) Interrupt Enable  Reset Value */
+
+#define CAN_IE_RF0NE_Pos                      _UINT32_(0)                                          /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Position */
+#define CAN_IE_RF0NE_Msk                      (_UINT32_(0x1) << CAN_IE_RF0NE_Pos)                  /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Mask */
+#define CAN_IE_RF0NE(value)                   (CAN_IE_RF0NE_Msk & (_UINT32_(value) << CAN_IE_RF0NE_Pos)) /* Assignment of value for RF0NE in the CAN_IE register */
+#define CAN_IE_RF0WE_Pos                      _UINT32_(1)                                          /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Position */
+#define CAN_IE_RF0WE_Msk                      (_UINT32_(0x1) << CAN_IE_RF0WE_Pos)                  /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Mask */
+#define CAN_IE_RF0WE(value)                   (CAN_IE_RF0WE_Msk & (_UINT32_(value) << CAN_IE_RF0WE_Pos)) /* Assignment of value for RF0WE in the CAN_IE register */
+#define CAN_IE_RF0FE_Pos                      _UINT32_(2)                                          /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Position */
+#define CAN_IE_RF0FE_Msk                      (_UINT32_(0x1) << CAN_IE_RF0FE_Pos)                  /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Mask */
+#define CAN_IE_RF0FE(value)                   (CAN_IE_RF0FE_Msk & (_UINT32_(value) << CAN_IE_RF0FE_Pos)) /* Assignment of value for RF0FE in the CAN_IE register */
+#define CAN_IE_RF0LE_Pos                      _UINT32_(3)                                          /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Position */
+#define CAN_IE_RF0LE_Msk                      (_UINT32_(0x1) << CAN_IE_RF0LE_Pos)                  /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Mask */
+#define CAN_IE_RF0LE(value)                   (CAN_IE_RF0LE_Msk & (_UINT32_(value) << CAN_IE_RF0LE_Pos)) /* Assignment of value for RF0LE in the CAN_IE register */
+#define CAN_IE_RF1NE_Pos                      _UINT32_(4)                                          /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Position */
+#define CAN_IE_RF1NE_Msk                      (_UINT32_(0x1) << CAN_IE_RF1NE_Pos)                  /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Mask */
+#define CAN_IE_RF1NE(value)                   (CAN_IE_RF1NE_Msk & (_UINT32_(value) << CAN_IE_RF1NE_Pos)) /* Assignment of value for RF1NE in the CAN_IE register */
+#define CAN_IE_RF1WE_Pos                      _UINT32_(5)                                          /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Position */
+#define CAN_IE_RF1WE_Msk                      (_UINT32_(0x1) << CAN_IE_RF1WE_Pos)                  /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Mask */
+#define CAN_IE_RF1WE(value)                   (CAN_IE_RF1WE_Msk & (_UINT32_(value) << CAN_IE_RF1WE_Pos)) /* Assignment of value for RF1WE in the CAN_IE register */
+#define CAN_IE_RF1FE_Pos                      _UINT32_(6)                                          /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Position */
+#define CAN_IE_RF1FE_Msk                      (_UINT32_(0x1) << CAN_IE_RF1FE_Pos)                  /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Mask */
+#define CAN_IE_RF1FE(value)                   (CAN_IE_RF1FE_Msk & (_UINT32_(value) << CAN_IE_RF1FE_Pos)) /* Assignment of value for RF1FE in the CAN_IE register */
+#define CAN_IE_RF1LE_Pos                      _UINT32_(7)                                          /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Position */
+#define CAN_IE_RF1LE_Msk                      (_UINT32_(0x1) << CAN_IE_RF1LE_Pos)                  /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Mask */
+#define CAN_IE_RF1LE(value)                   (CAN_IE_RF1LE_Msk & (_UINT32_(value) << CAN_IE_RF1LE_Pos)) /* Assignment of value for RF1LE in the CAN_IE register */
+#define CAN_IE_HPME_Pos                       _UINT32_(8)                                          /* (CAN_IE) High Priority Message Interrupt Enable Position */
+#define CAN_IE_HPME_Msk                       (_UINT32_(0x1) << CAN_IE_HPME_Pos)                   /* (CAN_IE) High Priority Message Interrupt Enable Mask */
+#define CAN_IE_HPME(value)                    (CAN_IE_HPME_Msk & (_UINT32_(value) << CAN_IE_HPME_Pos)) /* Assignment of value for HPME in the CAN_IE register */
+#define CAN_IE_TCE_Pos                        _UINT32_(9)                                          /* (CAN_IE) Timestamp Completed Interrupt Enable Position */
+#define CAN_IE_TCE_Msk                        (_UINT32_(0x1) << CAN_IE_TCE_Pos)                    /* (CAN_IE) Timestamp Completed Interrupt Enable Mask */
+#define CAN_IE_TCE(value)                     (CAN_IE_TCE_Msk & (_UINT32_(value) << CAN_IE_TCE_Pos)) /* Assignment of value for TCE in the CAN_IE register */
+#define CAN_IE_TCFE_Pos                       _UINT32_(10)                                         /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Position */
+#define CAN_IE_TCFE_Msk                       (_UINT32_(0x1) << CAN_IE_TCFE_Pos)                   /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */
+#define CAN_IE_TCFE(value)                    (CAN_IE_TCFE_Msk & (_UINT32_(value) << CAN_IE_TCFE_Pos)) /* Assignment of value for TCFE in the CAN_IE register */
+#define CAN_IE_TFEE_Pos                       _UINT32_(11)                                         /* (CAN_IE) Tx FIFO Empty Interrupt Enable Position */
+#define CAN_IE_TFEE_Msk                       (_UINT32_(0x1) << CAN_IE_TFEE_Pos)                   /* (CAN_IE) Tx FIFO Empty Interrupt Enable Mask */
+#define CAN_IE_TFEE(value)                    (CAN_IE_TFEE_Msk & (_UINT32_(value) << CAN_IE_TFEE_Pos)) /* Assignment of value for TFEE in the CAN_IE register */
+#define CAN_IE_TEFNE_Pos                      _UINT32_(12)                                         /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */
+#define CAN_IE_TEFNE_Msk                      (_UINT32_(0x1) << CAN_IE_TEFNE_Pos)                  /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */
+#define CAN_IE_TEFNE(value)                   (CAN_IE_TEFNE_Msk & (_UINT32_(value) << CAN_IE_TEFNE_Pos)) /* Assignment of value for TEFNE in the CAN_IE register */
+#define CAN_IE_TEFWE_Pos                      _UINT32_(13)                                         /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */
+#define CAN_IE_TEFWE_Msk                      (_UINT32_(0x1) << CAN_IE_TEFWE_Pos)                  /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */
+#define CAN_IE_TEFWE(value)                   (CAN_IE_TEFWE_Msk & (_UINT32_(value) << CAN_IE_TEFWE_Pos)) /* Assignment of value for TEFWE in the CAN_IE register */
+#define CAN_IE_TEFFE_Pos                      _UINT32_(14)                                         /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Position */
+#define CAN_IE_TEFFE_Msk                      (_UINT32_(0x1) << CAN_IE_TEFFE_Pos)                  /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Mask */
+#define CAN_IE_TEFFE(value)                   (CAN_IE_TEFFE_Msk & (_UINT32_(value) << CAN_IE_TEFFE_Pos)) /* Assignment of value for TEFFE in the CAN_IE register */
+#define CAN_IE_TEFLE_Pos                      _UINT32_(15)                                         /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Position */
+#define CAN_IE_TEFLE_Msk                      (_UINT32_(0x1) << CAN_IE_TEFLE_Pos)                  /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Mask */
+#define CAN_IE_TEFLE(value)                   (CAN_IE_TEFLE_Msk & (_UINT32_(value) << CAN_IE_TEFLE_Pos)) /* Assignment of value for TEFLE in the CAN_IE register */
+#define CAN_IE_TSWE_Pos                       _UINT32_(16)                                         /* (CAN_IE) Timestamp Wraparound Interrupt Enable Position */
+#define CAN_IE_TSWE_Msk                       (_UINT32_(0x1) << CAN_IE_TSWE_Pos)                   /* (CAN_IE) Timestamp Wraparound Interrupt Enable Mask */
+#define CAN_IE_TSWE(value)                    (CAN_IE_TSWE_Msk & (_UINT32_(value) << CAN_IE_TSWE_Pos)) /* Assignment of value for TSWE in the CAN_IE register */
+#define CAN_IE_MRAFE_Pos                      _UINT32_(17)                                         /* (CAN_IE) Message RAM Access Failure Interrupt Enable Position */
+#define CAN_IE_MRAFE_Msk                      (_UINT32_(0x1) << CAN_IE_MRAFE_Pos)                  /* (CAN_IE) Message RAM Access Failure Interrupt Enable Mask */
+#define CAN_IE_MRAFE(value)                   (CAN_IE_MRAFE_Msk & (_UINT32_(value) << CAN_IE_MRAFE_Pos)) /* Assignment of value for MRAFE in the CAN_IE register */
+#define CAN_IE_TOOE_Pos                       _UINT32_(18)                                         /* (CAN_IE) Timeout Occurred Interrupt Enable Position */
+#define CAN_IE_TOOE_Msk                       (_UINT32_(0x1) << CAN_IE_TOOE_Pos)                   /* (CAN_IE) Timeout Occurred Interrupt Enable Mask */
+#define CAN_IE_TOOE(value)                    (CAN_IE_TOOE_Msk & (_UINT32_(value) << CAN_IE_TOOE_Pos)) /* Assignment of value for TOOE in the CAN_IE register */
+#define CAN_IE_DRXE_Pos                       _UINT32_(19)                                         /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Position */
+#define CAN_IE_DRXE_Msk                       (_UINT32_(0x1) << CAN_IE_DRXE_Pos)                   /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Mask */
+#define CAN_IE_DRXE(value)                    (CAN_IE_DRXE_Msk & (_UINT32_(value) << CAN_IE_DRXE_Pos)) /* Assignment of value for DRXE in the CAN_IE register */
+#define CAN_IE_ELOE_Pos                       _UINT32_(22)                                         /* (CAN_IE) Error Logging Overflow Interrupt Enable Position */
+#define CAN_IE_ELOE_Msk                       (_UINT32_(0x1) << CAN_IE_ELOE_Pos)                   /* (CAN_IE) Error Logging Overflow Interrupt Enable Mask */
+#define CAN_IE_ELOE(value)                    (CAN_IE_ELOE_Msk & (_UINT32_(value) << CAN_IE_ELOE_Pos)) /* Assignment of value for ELOE in the CAN_IE register */
+#define CAN_IE_EPE_Pos                        _UINT32_(23)                                         /* (CAN_IE) Error Passive Interrupt Enable Position */
+#define CAN_IE_EPE_Msk                        (_UINT32_(0x1) << CAN_IE_EPE_Pos)                    /* (CAN_IE) Error Passive Interrupt Enable Mask */
+#define CAN_IE_EPE(value)                     (CAN_IE_EPE_Msk & (_UINT32_(value) << CAN_IE_EPE_Pos)) /* Assignment of value for EPE in the CAN_IE register */
+#define CAN_IE_EWE_Pos                        _UINT32_(24)                                         /* (CAN_IE) Warning Status Interrupt Enable Position */
+#define CAN_IE_EWE_Msk                        (_UINT32_(0x1) << CAN_IE_EWE_Pos)                    /* (CAN_IE) Warning Status Interrupt Enable Mask */
+#define CAN_IE_EWE(value)                     (CAN_IE_EWE_Msk & (_UINT32_(value) << CAN_IE_EWE_Pos)) /* Assignment of value for EWE in the CAN_IE register */
+#define CAN_IE_BOE_Pos                        _UINT32_(25)                                         /* (CAN_IE) Bus_Off Status Interrupt Enable Position */
+#define CAN_IE_BOE_Msk                        (_UINT32_(0x1) << CAN_IE_BOE_Pos)                    /* (CAN_IE) Bus_Off Status Interrupt Enable Mask */
+#define CAN_IE_BOE(value)                     (CAN_IE_BOE_Msk & (_UINT32_(value) << CAN_IE_BOE_Pos)) /* Assignment of value for BOE in the CAN_IE register */
+#define CAN_IE_WDIE_Pos                       _UINT32_(26)                                         /* (CAN_IE) Watchdog Interrupt Interrupt Enable Position */
+#define CAN_IE_WDIE_Msk                       (_UINT32_(0x1) << CAN_IE_WDIE_Pos)                   /* (CAN_IE) Watchdog Interrupt Interrupt Enable Mask */
+#define CAN_IE_WDIE(value)                    (CAN_IE_WDIE_Msk & (_UINT32_(value) << CAN_IE_WDIE_Pos)) /* Assignment of value for WDIE in the CAN_IE register */
+#define CAN_IE_PEAE_Pos                       _UINT32_(27)                                         /* (CAN_IE) Protocol Error in Arbitration Phase Enable Position */
+#define CAN_IE_PEAE_Msk                       (_UINT32_(0x1) << CAN_IE_PEAE_Pos)                   /* (CAN_IE) Protocol Error in Arbitration Phase Enable Mask */
+#define CAN_IE_PEAE(value)                    (CAN_IE_PEAE_Msk & (_UINT32_(value) << CAN_IE_PEAE_Pos)) /* Assignment of value for PEAE in the CAN_IE register */
+#define CAN_IE_PEDE_Pos                       _UINT32_(28)                                         /* (CAN_IE) Protocol Error in Data Phase Enable Position */
+#define CAN_IE_PEDE_Msk                       (_UINT32_(0x1) << CAN_IE_PEDE_Pos)                   /* (CAN_IE) Protocol Error in Data Phase Enable Mask */
+#define CAN_IE_PEDE(value)                    (CAN_IE_PEDE_Msk & (_UINT32_(value) << CAN_IE_PEDE_Pos)) /* Assignment of value for PEDE in the CAN_IE register */
+#define CAN_IE_ARAE_Pos                       _UINT32_(29)                                         /* (CAN_IE) Access to Reserved Address Enable Position */
+#define CAN_IE_ARAE_Msk                       (_UINT32_(0x1) << CAN_IE_ARAE_Pos)                   /* (CAN_IE) Access to Reserved Address Enable Mask */
+#define CAN_IE_ARAE(value)                    (CAN_IE_ARAE_Msk & (_UINT32_(value) << CAN_IE_ARAE_Pos)) /* Assignment of value for ARAE in the CAN_IE register */
+#define CAN_IE_Msk                            _UINT32_(0x3FCFFFFF)                                 /* (CAN_IE) Register Mask  */
+
+
+/* -------- CAN_ILS : (CAN Offset: 0x158) (R/W 32) Interrupt Line Select -------- */
+#define CAN_ILS_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_ILS) Interrupt Line Select  Reset Value */
+
+#define CAN_ILS_RF0NL_Pos                     _UINT32_(0)                                          /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Position */
+#define CAN_ILS_RF0NL_Msk                     (_UINT32_(0x1) << CAN_ILS_RF0NL_Pos)                 /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Mask */
+#define CAN_ILS_RF0NL(value)                  (CAN_ILS_RF0NL_Msk & (_UINT32_(value) << CAN_ILS_RF0NL_Pos)) /* Assignment of value for RF0NL in the CAN_ILS register */
+#define CAN_ILS_RF0WL_Pos                     _UINT32_(1)                                          /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Position */
+#define CAN_ILS_RF0WL_Msk                     (_UINT32_(0x1) << CAN_ILS_RF0WL_Pos)                 /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Mask */
+#define CAN_ILS_RF0WL(value)                  (CAN_ILS_RF0WL_Msk & (_UINT32_(value) << CAN_ILS_RF0WL_Pos)) /* Assignment of value for RF0WL in the CAN_ILS register */
+#define CAN_ILS_RF0FL_Pos                     _UINT32_(2)                                          /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Position */
+#define CAN_ILS_RF0FL_Msk                     (_UINT32_(0x1) << CAN_ILS_RF0FL_Pos)                 /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Mask */
+#define CAN_ILS_RF0FL(value)                  (CAN_ILS_RF0FL_Msk & (_UINT32_(value) << CAN_ILS_RF0FL_Pos)) /* Assignment of value for RF0FL in the CAN_ILS register */
+#define CAN_ILS_RF0LL_Pos                     _UINT32_(3)                                          /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Position */
+#define CAN_ILS_RF0LL_Msk                     (_UINT32_(0x1) << CAN_ILS_RF0LL_Pos)                 /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Mask */
+#define CAN_ILS_RF0LL(value)                  (CAN_ILS_RF0LL_Msk & (_UINT32_(value) << CAN_ILS_RF0LL_Pos)) /* Assignment of value for RF0LL in the CAN_ILS register */
+#define CAN_ILS_RF1NL_Pos                     _UINT32_(4)                                          /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Position */
+#define CAN_ILS_RF1NL_Msk                     (_UINT32_(0x1) << CAN_ILS_RF1NL_Pos)                 /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Mask */
+#define CAN_ILS_RF1NL(value)                  (CAN_ILS_RF1NL_Msk & (_UINT32_(value) << CAN_ILS_RF1NL_Pos)) /* Assignment of value for RF1NL in the CAN_ILS register */
+#define CAN_ILS_RF1WL_Pos                     _UINT32_(5)                                          /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Position */
+#define CAN_ILS_RF1WL_Msk                     (_UINT32_(0x1) << CAN_ILS_RF1WL_Pos)                 /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Mask */
+#define CAN_ILS_RF1WL(value)                  (CAN_ILS_RF1WL_Msk & (_UINT32_(value) << CAN_ILS_RF1WL_Pos)) /* Assignment of value for RF1WL in the CAN_ILS register */
+#define CAN_ILS_RF1FL_Pos                     _UINT32_(6)                                          /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Position */
+#define CAN_ILS_RF1FL_Msk                     (_UINT32_(0x1) << CAN_ILS_RF1FL_Pos)                 /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Mask */
+#define CAN_ILS_RF1FL(value)                  (CAN_ILS_RF1FL_Msk & (_UINT32_(value) << CAN_ILS_RF1FL_Pos)) /* Assignment of value for RF1FL in the CAN_ILS register */
+#define CAN_ILS_RF1LL_Pos                     _UINT32_(7)                                          /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Position */
+#define CAN_ILS_RF1LL_Msk                     (_UINT32_(0x1) << CAN_ILS_RF1LL_Pos)                 /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Mask */
+#define CAN_ILS_RF1LL(value)                  (CAN_ILS_RF1LL_Msk & (_UINT32_(value) << CAN_ILS_RF1LL_Pos)) /* Assignment of value for RF1LL in the CAN_ILS register */
+#define CAN_ILS_HPML_Pos                      _UINT32_(8)                                          /* (CAN_ILS) High Priority Message Interrupt Line Position */
+#define CAN_ILS_HPML_Msk                      (_UINT32_(0x1) << CAN_ILS_HPML_Pos)                  /* (CAN_ILS) High Priority Message Interrupt Line Mask */
+#define CAN_ILS_HPML(value)                   (CAN_ILS_HPML_Msk & (_UINT32_(value) << CAN_ILS_HPML_Pos)) /* Assignment of value for HPML in the CAN_ILS register */
+#define CAN_ILS_TCL_Pos                       _UINT32_(9)                                          /* (CAN_ILS) Timestamp Completed Interrupt Line Position */
+#define CAN_ILS_TCL_Msk                       (_UINT32_(0x1) << CAN_ILS_TCL_Pos)                   /* (CAN_ILS) Timestamp Completed Interrupt Line Mask */
+#define CAN_ILS_TCL(value)                    (CAN_ILS_TCL_Msk & (_UINT32_(value) << CAN_ILS_TCL_Pos)) /* Assignment of value for TCL in the CAN_ILS register */
+#define CAN_ILS_TCFL_Pos                      _UINT32_(10)                                         /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Position */
+#define CAN_ILS_TCFL_Msk                      (_UINT32_(0x1) << CAN_ILS_TCFL_Pos)                  /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */
+#define CAN_ILS_TCFL(value)                   (CAN_ILS_TCFL_Msk & (_UINT32_(value) << CAN_ILS_TCFL_Pos)) /* Assignment of value for TCFL in the CAN_ILS register */
+#define CAN_ILS_TFEL_Pos                      _UINT32_(11)                                         /* (CAN_ILS) Tx FIFO Empty Interrupt Line Position */
+#define CAN_ILS_TFEL_Msk                      (_UINT32_(0x1) << CAN_ILS_TFEL_Pos)                  /* (CAN_ILS) Tx FIFO Empty Interrupt Line Mask */
+#define CAN_ILS_TFEL(value)                   (CAN_ILS_TFEL_Msk & (_UINT32_(value) << CAN_ILS_TFEL_Pos)) /* Assignment of value for TFEL in the CAN_ILS register */
+#define CAN_ILS_TEFNL_Pos                     _UINT32_(12)                                         /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */
+#define CAN_ILS_TEFNL_Msk                     (_UINT32_(0x1) << CAN_ILS_TEFNL_Pos)                 /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */
+#define CAN_ILS_TEFNL(value)                  (CAN_ILS_TEFNL_Msk & (_UINT32_(value) << CAN_ILS_TEFNL_Pos)) /* Assignment of value for TEFNL in the CAN_ILS register */
+#define CAN_ILS_TEFWL_Pos                     _UINT32_(13)                                         /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */
+#define CAN_ILS_TEFWL_Msk                     (_UINT32_(0x1) << CAN_ILS_TEFWL_Pos)                 /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */
+#define CAN_ILS_TEFWL(value)                  (CAN_ILS_TEFWL_Msk & (_UINT32_(value) << CAN_ILS_TEFWL_Pos)) /* Assignment of value for TEFWL in the CAN_ILS register */
+#define CAN_ILS_TEFFL_Pos                     _UINT32_(14)                                         /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Position */
+#define CAN_ILS_TEFFL_Msk                     (_UINT32_(0x1) << CAN_ILS_TEFFL_Pos)                 /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Mask */
+#define CAN_ILS_TEFFL(value)                  (CAN_ILS_TEFFL_Msk & (_UINT32_(value) << CAN_ILS_TEFFL_Pos)) /* Assignment of value for TEFFL in the CAN_ILS register */
+#define CAN_ILS_TEFLL_Pos                     _UINT32_(15)                                         /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Position */
+#define CAN_ILS_TEFLL_Msk                     (_UINT32_(0x1) << CAN_ILS_TEFLL_Pos)                 /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Mask */
+#define CAN_ILS_TEFLL(value)                  (CAN_ILS_TEFLL_Msk & (_UINT32_(value) << CAN_ILS_TEFLL_Pos)) /* Assignment of value for TEFLL in the CAN_ILS register */
+#define CAN_ILS_TSWL_Pos                      _UINT32_(16)                                         /* (CAN_ILS) Timestamp Wraparound Interrupt Line Position */
+#define CAN_ILS_TSWL_Msk                      (_UINT32_(0x1) << CAN_ILS_TSWL_Pos)                  /* (CAN_ILS) Timestamp Wraparound Interrupt Line Mask */
+#define CAN_ILS_TSWL(value)                   (CAN_ILS_TSWL_Msk & (_UINT32_(value) << CAN_ILS_TSWL_Pos)) /* Assignment of value for TSWL in the CAN_ILS register */
+#define CAN_ILS_MRAFL_Pos                     _UINT32_(17)                                         /* (CAN_ILS) Message RAM Access Failure Interrupt Line Position */
+#define CAN_ILS_MRAFL_Msk                     (_UINT32_(0x1) << CAN_ILS_MRAFL_Pos)                 /* (CAN_ILS) Message RAM Access Failure Interrupt Line Mask */
+#define CAN_ILS_MRAFL(value)                  (CAN_ILS_MRAFL_Msk & (_UINT32_(value) << CAN_ILS_MRAFL_Pos)) /* Assignment of value for MRAFL in the CAN_ILS register */
+#define CAN_ILS_TOOL_Pos                      _UINT32_(18)                                         /* (CAN_ILS) Timeout Occurred Interrupt Line Position */
+#define CAN_ILS_TOOL_Msk                      (_UINT32_(0x1) << CAN_ILS_TOOL_Pos)                  /* (CAN_ILS) Timeout Occurred Interrupt Line Mask */
+#define CAN_ILS_TOOL(value)                   (CAN_ILS_TOOL_Msk & (_UINT32_(value) << CAN_ILS_TOOL_Pos)) /* Assignment of value for TOOL in the CAN_ILS register */
+#define CAN_ILS_DRXL_Pos                      _UINT32_(19)                                         /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Position */
+#define CAN_ILS_DRXL_Msk                      (_UINT32_(0x1) << CAN_ILS_DRXL_Pos)                  /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Mask */
+#define CAN_ILS_DRXL(value)                   (CAN_ILS_DRXL_Msk & (_UINT32_(value) << CAN_ILS_DRXL_Pos)) /* Assignment of value for DRXL in the CAN_ILS register */
+#define CAN_ILS_ELOL_Pos                      _UINT32_(22)                                         /* (CAN_ILS) Error Logging Overflow Interrupt Line Position */
+#define CAN_ILS_ELOL_Msk                      (_UINT32_(0x1) << CAN_ILS_ELOL_Pos)                  /* (CAN_ILS) Error Logging Overflow Interrupt Line Mask */
+#define CAN_ILS_ELOL(value)                   (CAN_ILS_ELOL_Msk & (_UINT32_(value) << CAN_ILS_ELOL_Pos)) /* Assignment of value for ELOL in the CAN_ILS register */
+#define CAN_ILS_EPL_Pos                       _UINT32_(23)                                         /* (CAN_ILS) Error Passive Interrupt Line Position */
+#define CAN_ILS_EPL_Msk                       (_UINT32_(0x1) << CAN_ILS_EPL_Pos)                   /* (CAN_ILS) Error Passive Interrupt Line Mask */
+#define CAN_ILS_EPL(value)                    (CAN_ILS_EPL_Msk & (_UINT32_(value) << CAN_ILS_EPL_Pos)) /* Assignment of value for EPL in the CAN_ILS register */
+#define CAN_ILS_EWL_Pos                       _UINT32_(24)                                         /* (CAN_ILS) Warning Status Interrupt Line Position */
+#define CAN_ILS_EWL_Msk                       (_UINT32_(0x1) << CAN_ILS_EWL_Pos)                   /* (CAN_ILS) Warning Status Interrupt Line Mask */
+#define CAN_ILS_EWL(value)                    (CAN_ILS_EWL_Msk & (_UINT32_(value) << CAN_ILS_EWL_Pos)) /* Assignment of value for EWL in the CAN_ILS register */
+#define CAN_ILS_BOL_Pos                       _UINT32_(25)                                         /* (CAN_ILS) Bus_Off Status Interrupt Line Position */
+#define CAN_ILS_BOL_Msk                       (_UINT32_(0x1) << CAN_ILS_BOL_Pos)                   /* (CAN_ILS) Bus_Off Status Interrupt Line Mask */
+#define CAN_ILS_BOL(value)                    (CAN_ILS_BOL_Msk & (_UINT32_(value) << CAN_ILS_BOL_Pos)) /* Assignment of value for BOL in the CAN_ILS register */
+#define CAN_ILS_WDIL_Pos                      _UINT32_(26)                                         /* (CAN_ILS) Watchdog Interrupt Interrupt Line Position */
+#define CAN_ILS_WDIL_Msk                      (_UINT32_(0x1) << CAN_ILS_WDIL_Pos)                  /* (CAN_ILS) Watchdog Interrupt Interrupt Line Mask */
+#define CAN_ILS_WDIL(value)                   (CAN_ILS_WDIL_Msk & (_UINT32_(value) << CAN_ILS_WDIL_Pos)) /* Assignment of value for WDIL in the CAN_ILS register */
+#define CAN_ILS_PEAL_Pos                      _UINT32_(27)                                         /* (CAN_ILS) Protocol Error in Arbitration Phase Line Position */
+#define CAN_ILS_PEAL_Msk                      (_UINT32_(0x1) << CAN_ILS_PEAL_Pos)                  /* (CAN_ILS) Protocol Error in Arbitration Phase Line Mask */
+#define CAN_ILS_PEAL(value)                   (CAN_ILS_PEAL_Msk & (_UINT32_(value) << CAN_ILS_PEAL_Pos)) /* Assignment of value for PEAL in the CAN_ILS register */
+#define CAN_ILS_PEDL_Pos                      _UINT32_(28)                                         /* (CAN_ILS) Protocol Error in Data Phase Line Position */
+#define CAN_ILS_PEDL_Msk                      (_UINT32_(0x1) << CAN_ILS_PEDL_Pos)                  /* (CAN_ILS) Protocol Error in Data Phase Line Mask */
+#define CAN_ILS_PEDL(value)                   (CAN_ILS_PEDL_Msk & (_UINT32_(value) << CAN_ILS_PEDL_Pos)) /* Assignment of value for PEDL in the CAN_ILS register */
+#define CAN_ILS_ARAL_Pos                      _UINT32_(29)                                         /* (CAN_ILS) Access to Reserved Address Line Position */
+#define CAN_ILS_ARAL_Msk                      (_UINT32_(0x1) << CAN_ILS_ARAL_Pos)                  /* (CAN_ILS) Access to Reserved Address Line Mask */
+#define CAN_ILS_ARAL(value)                   (CAN_ILS_ARAL_Msk & (_UINT32_(value) << CAN_ILS_ARAL_Pos)) /* Assignment of value for ARAL in the CAN_ILS register */
+#define CAN_ILS_Msk                           _UINT32_(0x3FCFFFFF)                                 /* (CAN_ILS) Register Mask  */
+
+
+/* -------- CAN_ILE : (CAN Offset: 0x15C) (R/W 32) Interrupt Line Enable -------- */
+#define CAN_ILE_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_ILE) Interrupt Line Enable  Reset Value */
+
+#define CAN_ILE_EINT0_Pos                     _UINT32_(0)                                          /* (CAN_ILE) Enable Interrupt Line 0 Position */
+#define CAN_ILE_EINT0_Msk                     (_UINT32_(0x1) << CAN_ILE_EINT0_Pos)                 /* (CAN_ILE) Enable Interrupt Line 0 Mask */
+#define CAN_ILE_EINT0(value)                  (CAN_ILE_EINT0_Msk & (_UINT32_(value) << CAN_ILE_EINT0_Pos)) /* Assignment of value for EINT0 in the CAN_ILE register */
+#define CAN_ILE_EINT1_Pos                     _UINT32_(1)                                          /* (CAN_ILE) Enable Interrupt Line 1 Position */
+#define CAN_ILE_EINT1_Msk                     (_UINT32_(0x1) << CAN_ILE_EINT1_Pos)                 /* (CAN_ILE) Enable Interrupt Line 1 Mask */
+#define CAN_ILE_EINT1(value)                  (CAN_ILE_EINT1_Msk & (_UINT32_(value) << CAN_ILE_EINT1_Pos)) /* Assignment of value for EINT1 in the CAN_ILE register */
+#define CAN_ILE_Msk                           _UINT32_(0x00000003)                                 /* (CAN_ILE) Register Mask  */
+
+#define CAN_ILE_EINT_Pos                      _UINT32_(0)                                          /* (CAN_ILE Position) Enable Interrupt Line x */
+#define CAN_ILE_EINT_Msk                      (_UINT32_(0x3) << CAN_ILE_EINT_Pos)                  /* (CAN_ILE Mask) EINT */
+#define CAN_ILE_EINT(value)                   (CAN_ILE_EINT_Msk & (_UINT32_(value) << CAN_ILE_EINT_Pos)) 
+
+/* -------- CAN_GFC : (CAN Offset: 0x180) (R/W 32) Global Filter Configuration -------- */
+#define CAN_GFC_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_GFC) Global Filter Configuration  Reset Value */
+
+#define CAN_GFC_RRFE_Pos                      _UINT32_(0)                                          /* (CAN_GFC) Reject Remote Frames Extended Position */
+#define CAN_GFC_RRFE_Msk                      (_UINT32_(0x1) << CAN_GFC_RRFE_Pos)                  /* (CAN_GFC) Reject Remote Frames Extended Mask */
+#define CAN_GFC_RRFE(value)                   (CAN_GFC_RRFE_Msk & (_UINT32_(value) << CAN_GFC_RRFE_Pos)) /* Assignment of value for RRFE in the CAN_GFC register */
+#define CAN_GFC_RRFS_Pos                      _UINT32_(1)                                          /* (CAN_GFC) Reject Remote Frames Standard Position */
+#define CAN_GFC_RRFS_Msk                      (_UINT32_(0x1) << CAN_GFC_RRFS_Pos)                  /* (CAN_GFC) Reject Remote Frames Standard Mask */
+#define CAN_GFC_RRFS(value)                   (CAN_GFC_RRFS_Msk & (_UINT32_(value) << CAN_GFC_RRFS_Pos)) /* Assignment of value for RRFS in the CAN_GFC register */
+#define CAN_GFC_ANFE_Pos                      _UINT32_(2)                                          /* (CAN_GFC) Accept Non-matching Frames Extended Position */
+#define CAN_GFC_ANFE_Msk                      (_UINT32_(0x3) << CAN_GFC_ANFE_Pos)                  /* (CAN_GFC) Accept Non-matching Frames Extended Mask */
+#define CAN_GFC_ANFE(value)                   (CAN_GFC_ANFE_Msk & (_UINT32_(value) << CAN_GFC_ANFE_Pos)) /* Assignment of value for ANFE in the CAN_GFC register */
+#define   CAN_GFC_ANFE_RXF0_Val               _UINT32_(0x0)                                        /* (CAN_GFC) Accept in Rx FIFO 0  */
+#define   CAN_GFC_ANFE_RXF1_Val               _UINT32_(0x1)                                        /* (CAN_GFC) Accept in Rx FIFO 1  */
+#define   CAN_GFC_ANFE_REJECT_Val             _UINT32_(0x2)                                        /* (CAN_GFC) Reject  */
+#define CAN_GFC_ANFE_RXF0                     (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos)          /* (CAN_GFC) Accept in Rx FIFO 0 Position */
+#define CAN_GFC_ANFE_RXF1                     (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos)          /* (CAN_GFC) Accept in Rx FIFO 1 Position */
+#define CAN_GFC_ANFE_REJECT                   (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos)        /* (CAN_GFC) Reject Position */
+#define CAN_GFC_ANFS_Pos                      _UINT32_(4)                                          /* (CAN_GFC) Accept Non-matching Frames Standard Position */
+#define CAN_GFC_ANFS_Msk                      (_UINT32_(0x3) << CAN_GFC_ANFS_Pos)                  /* (CAN_GFC) Accept Non-matching Frames Standard Mask */
+#define CAN_GFC_ANFS(value)                   (CAN_GFC_ANFS_Msk & (_UINT32_(value) << CAN_GFC_ANFS_Pos)) /* Assignment of value for ANFS in the CAN_GFC register */
+#define   CAN_GFC_ANFS_RXF0_Val               _UINT32_(0x0)                                        /* (CAN_GFC) Accept in Rx FIFO 0  */
+#define   CAN_GFC_ANFS_RXF1_Val               _UINT32_(0x1)                                        /* (CAN_GFC) Accept in Rx FIFO 1  */
+#define   CAN_GFC_ANFS_REJECT_Val             _UINT32_(0x2)                                        /* (CAN_GFC) Reject  */
+#define CAN_GFC_ANFS_RXF0                     (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos)          /* (CAN_GFC) Accept in Rx FIFO 0 Position */
+#define CAN_GFC_ANFS_RXF1                     (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos)          /* (CAN_GFC) Accept in Rx FIFO 1 Position */
+#define CAN_GFC_ANFS_REJECT                   (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos)        /* (CAN_GFC) Reject Position */
+#define CAN_GFC_Msk                           _UINT32_(0x0000003F)                                 /* (CAN_GFC) Register Mask  */
+
+
+/* -------- CAN_SIDFC : (CAN Offset: 0x184) (R/W 32) Standard ID Filter Configuration -------- */
+#define CAN_SIDFC_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_SIDFC) Standard ID Filter Configuration  Reset Value */
+
+#define CAN_SIDFC_FLSSA_Pos                   _UINT32_(2)                                          /* (CAN_SIDFC) Filter List Standard Start Address Position */
+#define CAN_SIDFC_FLSSA_Msk                   (_UINT32_(0x3FFF) << CAN_SIDFC_FLSSA_Pos)            /* (CAN_SIDFC) Filter List Standard Start Address Mask */
+#define CAN_SIDFC_FLSSA(value)                (CAN_SIDFC_FLSSA_Msk & (_UINT32_(value) << CAN_SIDFC_FLSSA_Pos)) /* Assignment of value for FLSSA in the CAN_SIDFC register */
+#define CAN_SIDFC_LSS_Pos                     _UINT32_(16)                                         /* (CAN_SIDFC) List Size Standard Position */
+#define CAN_SIDFC_LSS_Msk                     (_UINT32_(0xFF) << CAN_SIDFC_LSS_Pos)                /* (CAN_SIDFC) List Size Standard Mask */
+#define CAN_SIDFC_LSS(value)                  (CAN_SIDFC_LSS_Msk & (_UINT32_(value) << CAN_SIDFC_LSS_Pos)) /* Assignment of value for LSS in the CAN_SIDFC register */
+#define CAN_SIDFC_Msk                         _UINT32_(0x00FFFFFC)                                 /* (CAN_SIDFC) Register Mask  */
+
+
+/* -------- CAN_XIDFC : (CAN Offset: 0x188) (R/W 32) Extended ID Filter Configuration -------- */
+#define CAN_XIDFC_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_XIDFC) Extended ID Filter Configuration  Reset Value */
+
+#define CAN_XIDFC_FLESA_Pos                   _UINT32_(2)                                          /* (CAN_XIDFC) Filter List Extended Start Address Position */
+#define CAN_XIDFC_FLESA_Msk                   (_UINT32_(0x3FFF) << CAN_XIDFC_FLESA_Pos)            /* (CAN_XIDFC) Filter List Extended Start Address Mask */
+#define CAN_XIDFC_FLESA(value)                (CAN_XIDFC_FLESA_Msk & (_UINT32_(value) << CAN_XIDFC_FLESA_Pos)) /* Assignment of value for FLESA in the CAN_XIDFC register */
+#define CAN_XIDFC_LSE_Pos                     _UINT32_(16)                                         /* (CAN_XIDFC) List Size Extended Position */
+#define CAN_XIDFC_LSE_Msk                     (_UINT32_(0x7F) << CAN_XIDFC_LSE_Pos)                /* (CAN_XIDFC) List Size Extended Mask */
+#define CAN_XIDFC_LSE(value)                  (CAN_XIDFC_LSE_Msk & (_UINT32_(value) << CAN_XIDFC_LSE_Pos)) /* Assignment of value for LSE in the CAN_XIDFC register */
+#define CAN_XIDFC_Msk                         _UINT32_(0x007FFFFC)                                 /* (CAN_XIDFC) Register Mask  */
+
+
+/* -------- CAN_XIDAM : (CAN Offset: 0x190) (R/W 32) Extended ID AND Mask -------- */
+#define CAN_XIDAM_RESETVALUE                  _UINT32_(0x1FFFFFFF)                                 /*  (CAN_XIDAM) Extended ID AND Mask  Reset Value */
+
+#define CAN_XIDAM_EIDM_Pos                    _UINT32_(0)                                          /* (CAN_XIDAM) Extended ID Mask Position */
+#define CAN_XIDAM_EIDM_Msk                    (_UINT32_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos)         /* (CAN_XIDAM) Extended ID Mask Mask */
+#define CAN_XIDAM_EIDM(value)                 (CAN_XIDAM_EIDM_Msk & (_UINT32_(value) << CAN_XIDAM_EIDM_Pos)) /* Assignment of value for EIDM in the CAN_XIDAM register */
+#define CAN_XIDAM_Msk                         _UINT32_(0x1FFFFFFF)                                 /* (CAN_XIDAM) Register Mask  */
+
+
+/* -------- CAN_HPMS : (CAN Offset: 0x194) ( R/ 32) High Priority Message Status -------- */
+#define CAN_HPMS_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_HPMS) High Priority Message Status  Reset Value */
+
+#define CAN_HPMS_BIDX_Pos                     _UINT32_(0)                                          /* (CAN_HPMS) Buffer Index Position */
+#define CAN_HPMS_BIDX_Msk                     (_UINT32_(0x3F) << CAN_HPMS_BIDX_Pos)                /* (CAN_HPMS) Buffer Index Mask */
+#define CAN_HPMS_BIDX(value)                  (CAN_HPMS_BIDX_Msk & (_UINT32_(value) << CAN_HPMS_BIDX_Pos)) /* Assignment of value for BIDX in the CAN_HPMS register */
+#define CAN_HPMS_MSI_Pos                      _UINT32_(6)                                          /* (CAN_HPMS) Message Storage Indicator Position */
+#define CAN_HPMS_MSI_Msk                      (_UINT32_(0x3) << CAN_HPMS_MSI_Pos)                  /* (CAN_HPMS) Message Storage Indicator Mask */
+#define CAN_HPMS_MSI(value)                   (CAN_HPMS_MSI_Msk & (_UINT32_(value) << CAN_HPMS_MSI_Pos)) /* Assignment of value for MSI in the CAN_HPMS register */
+#define   CAN_HPMS_MSI_NONE_Val               _UINT32_(0x0)                                        /* (CAN_HPMS) No FIFO selected  */
+#define   CAN_HPMS_MSI_LOST_Val               _UINT32_(0x1)                                        /* (CAN_HPMS) FIFO message lost  */
+#define   CAN_HPMS_MSI_FIFO0_Val              _UINT32_(0x2)                                        /* (CAN_HPMS) Message stored in FIFO 0  */
+#define   CAN_HPMS_MSI_FIFO1_Val              _UINT32_(0x3)                                        /* (CAN_HPMS) Message stored in FIFO 1  */
+#define CAN_HPMS_MSI_NONE                     (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos)          /* (CAN_HPMS) No FIFO selected Position */
+#define CAN_HPMS_MSI_LOST                     (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos)          /* (CAN_HPMS) FIFO message lost Position */
+#define CAN_HPMS_MSI_FIFO0                    (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos)         /* (CAN_HPMS) Message stored in FIFO 0 Position */
+#define CAN_HPMS_MSI_FIFO1                    (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos)         /* (CAN_HPMS) Message stored in FIFO 1 Position */
+#define CAN_HPMS_FIDX_Pos                     _UINT32_(8)                                          /* (CAN_HPMS) Filter Index Position */
+#define CAN_HPMS_FIDX_Msk                     (_UINT32_(0x7F) << CAN_HPMS_FIDX_Pos)                /* (CAN_HPMS) Filter Index Mask */
+#define CAN_HPMS_FIDX(value)                  (CAN_HPMS_FIDX_Msk & (_UINT32_(value) << CAN_HPMS_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_HPMS register */
+#define CAN_HPMS_FLST_Pos                     _UINT32_(15)                                         /* (CAN_HPMS) Filter List Position */
+#define CAN_HPMS_FLST_Msk                     (_UINT32_(0x1) << CAN_HPMS_FLST_Pos)                 /* (CAN_HPMS) Filter List Mask */
+#define CAN_HPMS_FLST(value)                  (CAN_HPMS_FLST_Msk & (_UINT32_(value) << CAN_HPMS_FLST_Pos)) /* Assignment of value for FLST in the CAN_HPMS register */
+#define CAN_HPMS_Msk                          _UINT32_(0x0000FFFF)                                 /* (CAN_HPMS) Register Mask  */
+
+
+/* -------- CAN_NDAT1 : (CAN Offset: 0x198) (R/W 32) New Data 1 -------- */
+#define CAN_NDAT1_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_NDAT1) New Data 1  Reset Value */
+
+#define CAN_NDAT1_ND0_Pos                     _UINT32_(0)                                          /* (CAN_NDAT1) New Data 0 Position */
+#define CAN_NDAT1_ND0_Msk                     (_UINT32_(0x1) << CAN_NDAT1_ND0_Pos)                 /* (CAN_NDAT1) New Data 0 Mask */
+#define CAN_NDAT1_ND0(value)                  (CAN_NDAT1_ND0_Msk & (_UINT32_(value) << CAN_NDAT1_ND0_Pos)) /* Assignment of value for ND0 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND1_Pos                     _UINT32_(1)                                          /* (CAN_NDAT1) New Data 1 Position */
+#define CAN_NDAT1_ND1_Msk                     (_UINT32_(0x1) << CAN_NDAT1_ND1_Pos)                 /* (CAN_NDAT1) New Data 1 Mask */
+#define CAN_NDAT1_ND1(value)                  (CAN_NDAT1_ND1_Msk & (_UINT32_(value) << CAN_NDAT1_ND1_Pos)) /* Assignment of value for ND1 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND2_Pos                     _UINT32_(2)                                          /* (CAN_NDAT1) New Data 2 Position */
+#define CAN_NDAT1_ND2_Msk                     (_UINT32_(0x1) << CAN_NDAT1_ND2_Pos)                 /* (CAN_NDAT1) New Data 2 Mask */
+#define CAN_NDAT1_ND2(value)                  (CAN_NDAT1_ND2_Msk & (_UINT32_(value) << CAN_NDAT1_ND2_Pos)) /* Assignment of value for ND2 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND3_Pos                     _UINT32_(3)                                          /* (CAN_NDAT1) New Data 3 Position */
+#define CAN_NDAT1_ND3_Msk                     (_UINT32_(0x1) << CAN_NDAT1_ND3_Pos)                 /* (CAN_NDAT1) New Data 3 Mask */
+#define CAN_NDAT1_ND3(value)                  (CAN_NDAT1_ND3_Msk & (_UINT32_(value) << CAN_NDAT1_ND3_Pos)) /* Assignment of value for ND3 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND4_Pos                     _UINT32_(4)                                          /* (CAN_NDAT1) New Data 4 Position */
+#define CAN_NDAT1_ND4_Msk                     (_UINT32_(0x1) << CAN_NDAT1_ND4_Pos)                 /* (CAN_NDAT1) New Data 4 Mask */
+#define CAN_NDAT1_ND4(value)                  (CAN_NDAT1_ND4_Msk & (_UINT32_(value) << CAN_NDAT1_ND4_Pos)) /* Assignment of value for ND4 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND5_Pos                     _UINT32_(5)                                          /* (CAN_NDAT1) New Data 5 Position */
+#define CAN_NDAT1_ND5_Msk                     (_UINT32_(0x1) << CAN_NDAT1_ND5_Pos)                 /* (CAN_NDAT1) New Data 5 Mask */
+#define CAN_NDAT1_ND5(value)                  (CAN_NDAT1_ND5_Msk & (_UINT32_(value) << CAN_NDAT1_ND5_Pos)) /* Assignment of value for ND5 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND6_Pos                     _UINT32_(6)                                          /* (CAN_NDAT1) New Data 6 Position */
+#define CAN_NDAT1_ND6_Msk                     (_UINT32_(0x1) << CAN_NDAT1_ND6_Pos)                 /* (CAN_NDAT1) New Data 6 Mask */
+#define CAN_NDAT1_ND6(value)                  (CAN_NDAT1_ND6_Msk & (_UINT32_(value) << CAN_NDAT1_ND6_Pos)) /* Assignment of value for ND6 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND7_Pos                     _UINT32_(7)                                          /* (CAN_NDAT1) New Data 7 Position */
+#define CAN_NDAT1_ND7_Msk                     (_UINT32_(0x1) << CAN_NDAT1_ND7_Pos)                 /* (CAN_NDAT1) New Data 7 Mask */
+#define CAN_NDAT1_ND7(value)                  (CAN_NDAT1_ND7_Msk & (_UINT32_(value) << CAN_NDAT1_ND7_Pos)) /* Assignment of value for ND7 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND8_Pos                     _UINT32_(8)                                          /* (CAN_NDAT1) New Data 8 Position */
+#define CAN_NDAT1_ND8_Msk                     (_UINT32_(0x1) << CAN_NDAT1_ND8_Pos)                 /* (CAN_NDAT1) New Data 8 Mask */
+#define CAN_NDAT1_ND8(value)                  (CAN_NDAT1_ND8_Msk & (_UINT32_(value) << CAN_NDAT1_ND8_Pos)) /* Assignment of value for ND8 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND9_Pos                     _UINT32_(9)                                          /* (CAN_NDAT1) New Data 9 Position */
+#define CAN_NDAT1_ND9_Msk                     (_UINT32_(0x1) << CAN_NDAT1_ND9_Pos)                 /* (CAN_NDAT1) New Data 9 Mask */
+#define CAN_NDAT1_ND9(value)                  (CAN_NDAT1_ND9_Msk & (_UINT32_(value) << CAN_NDAT1_ND9_Pos)) /* Assignment of value for ND9 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND10_Pos                    _UINT32_(10)                                         /* (CAN_NDAT1) New Data 10 Position */
+#define CAN_NDAT1_ND10_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND10_Pos)                /* (CAN_NDAT1) New Data 10 Mask */
+#define CAN_NDAT1_ND10(value)                 (CAN_NDAT1_ND10_Msk & (_UINT32_(value) << CAN_NDAT1_ND10_Pos)) /* Assignment of value for ND10 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND11_Pos                    _UINT32_(11)                                         /* (CAN_NDAT1) New Data 11 Position */
+#define CAN_NDAT1_ND11_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND11_Pos)                /* (CAN_NDAT1) New Data 11 Mask */
+#define CAN_NDAT1_ND11(value)                 (CAN_NDAT1_ND11_Msk & (_UINT32_(value) << CAN_NDAT1_ND11_Pos)) /* Assignment of value for ND11 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND12_Pos                    _UINT32_(12)                                         /* (CAN_NDAT1) New Data 12 Position */
+#define CAN_NDAT1_ND12_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND12_Pos)                /* (CAN_NDAT1) New Data 12 Mask */
+#define CAN_NDAT1_ND12(value)                 (CAN_NDAT1_ND12_Msk & (_UINT32_(value) << CAN_NDAT1_ND12_Pos)) /* Assignment of value for ND12 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND13_Pos                    _UINT32_(13)                                         /* (CAN_NDAT1) New Data 13 Position */
+#define CAN_NDAT1_ND13_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND13_Pos)                /* (CAN_NDAT1) New Data 13 Mask */
+#define CAN_NDAT1_ND13(value)                 (CAN_NDAT1_ND13_Msk & (_UINT32_(value) << CAN_NDAT1_ND13_Pos)) /* Assignment of value for ND13 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND14_Pos                    _UINT32_(14)                                         /* (CAN_NDAT1) New Data 14 Position */
+#define CAN_NDAT1_ND14_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND14_Pos)                /* (CAN_NDAT1) New Data 14 Mask */
+#define CAN_NDAT1_ND14(value)                 (CAN_NDAT1_ND14_Msk & (_UINT32_(value) << CAN_NDAT1_ND14_Pos)) /* Assignment of value for ND14 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND15_Pos                    _UINT32_(15)                                         /* (CAN_NDAT1) New Data 15 Position */
+#define CAN_NDAT1_ND15_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND15_Pos)                /* (CAN_NDAT1) New Data 15 Mask */
+#define CAN_NDAT1_ND15(value)                 (CAN_NDAT1_ND15_Msk & (_UINT32_(value) << CAN_NDAT1_ND15_Pos)) /* Assignment of value for ND15 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND16_Pos                    _UINT32_(16)                                         /* (CAN_NDAT1) New Data 16 Position */
+#define CAN_NDAT1_ND16_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND16_Pos)                /* (CAN_NDAT1) New Data 16 Mask */
+#define CAN_NDAT1_ND16(value)                 (CAN_NDAT1_ND16_Msk & (_UINT32_(value) << CAN_NDAT1_ND16_Pos)) /* Assignment of value for ND16 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND17_Pos                    _UINT32_(17)                                         /* (CAN_NDAT1) New Data 17 Position */
+#define CAN_NDAT1_ND17_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND17_Pos)                /* (CAN_NDAT1) New Data 17 Mask */
+#define CAN_NDAT1_ND17(value)                 (CAN_NDAT1_ND17_Msk & (_UINT32_(value) << CAN_NDAT1_ND17_Pos)) /* Assignment of value for ND17 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND18_Pos                    _UINT32_(18)                                         /* (CAN_NDAT1) New Data 18 Position */
+#define CAN_NDAT1_ND18_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND18_Pos)                /* (CAN_NDAT1) New Data 18 Mask */
+#define CAN_NDAT1_ND18(value)                 (CAN_NDAT1_ND18_Msk & (_UINT32_(value) << CAN_NDAT1_ND18_Pos)) /* Assignment of value for ND18 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND19_Pos                    _UINT32_(19)                                         /* (CAN_NDAT1) New Data 19 Position */
+#define CAN_NDAT1_ND19_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND19_Pos)                /* (CAN_NDAT1) New Data 19 Mask */
+#define CAN_NDAT1_ND19(value)                 (CAN_NDAT1_ND19_Msk & (_UINT32_(value) << CAN_NDAT1_ND19_Pos)) /* Assignment of value for ND19 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND20_Pos                    _UINT32_(20)                                         /* (CAN_NDAT1) New Data 20 Position */
+#define CAN_NDAT1_ND20_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND20_Pos)                /* (CAN_NDAT1) New Data 20 Mask */
+#define CAN_NDAT1_ND20(value)                 (CAN_NDAT1_ND20_Msk & (_UINT32_(value) << CAN_NDAT1_ND20_Pos)) /* Assignment of value for ND20 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND21_Pos                    _UINT32_(21)                                         /* (CAN_NDAT1) New Data 21 Position */
+#define CAN_NDAT1_ND21_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND21_Pos)                /* (CAN_NDAT1) New Data 21 Mask */
+#define CAN_NDAT1_ND21(value)                 (CAN_NDAT1_ND21_Msk & (_UINT32_(value) << CAN_NDAT1_ND21_Pos)) /* Assignment of value for ND21 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND22_Pos                    _UINT32_(22)                                         /* (CAN_NDAT1) New Data 22 Position */
+#define CAN_NDAT1_ND22_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND22_Pos)                /* (CAN_NDAT1) New Data 22 Mask */
+#define CAN_NDAT1_ND22(value)                 (CAN_NDAT1_ND22_Msk & (_UINT32_(value) << CAN_NDAT1_ND22_Pos)) /* Assignment of value for ND22 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND23_Pos                    _UINT32_(23)                                         /* (CAN_NDAT1) New Data 23 Position */
+#define CAN_NDAT1_ND23_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND23_Pos)                /* (CAN_NDAT1) New Data 23 Mask */
+#define CAN_NDAT1_ND23(value)                 (CAN_NDAT1_ND23_Msk & (_UINT32_(value) << CAN_NDAT1_ND23_Pos)) /* Assignment of value for ND23 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND24_Pos                    _UINT32_(24)                                         /* (CAN_NDAT1) New Data 24 Position */
+#define CAN_NDAT1_ND24_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND24_Pos)                /* (CAN_NDAT1) New Data 24 Mask */
+#define CAN_NDAT1_ND24(value)                 (CAN_NDAT1_ND24_Msk & (_UINT32_(value) << CAN_NDAT1_ND24_Pos)) /* Assignment of value for ND24 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND25_Pos                    _UINT32_(25)                                         /* (CAN_NDAT1) New Data 25 Position */
+#define CAN_NDAT1_ND25_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND25_Pos)                /* (CAN_NDAT1) New Data 25 Mask */
+#define CAN_NDAT1_ND25(value)                 (CAN_NDAT1_ND25_Msk & (_UINT32_(value) << CAN_NDAT1_ND25_Pos)) /* Assignment of value for ND25 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND26_Pos                    _UINT32_(26)                                         /* (CAN_NDAT1) New Data 26 Position */
+#define CAN_NDAT1_ND26_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND26_Pos)                /* (CAN_NDAT1) New Data 26 Mask */
+#define CAN_NDAT1_ND26(value)                 (CAN_NDAT1_ND26_Msk & (_UINT32_(value) << CAN_NDAT1_ND26_Pos)) /* Assignment of value for ND26 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND27_Pos                    _UINT32_(27)                                         /* (CAN_NDAT1) New Data 27 Position */
+#define CAN_NDAT1_ND27_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND27_Pos)                /* (CAN_NDAT1) New Data 27 Mask */
+#define CAN_NDAT1_ND27(value)                 (CAN_NDAT1_ND27_Msk & (_UINT32_(value) << CAN_NDAT1_ND27_Pos)) /* Assignment of value for ND27 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND28_Pos                    _UINT32_(28)                                         /* (CAN_NDAT1) New Data 28 Position */
+#define CAN_NDAT1_ND28_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND28_Pos)                /* (CAN_NDAT1) New Data 28 Mask */
+#define CAN_NDAT1_ND28(value)                 (CAN_NDAT1_ND28_Msk & (_UINT32_(value) << CAN_NDAT1_ND28_Pos)) /* Assignment of value for ND28 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND29_Pos                    _UINT32_(29)                                         /* (CAN_NDAT1) New Data 29 Position */
+#define CAN_NDAT1_ND29_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND29_Pos)                /* (CAN_NDAT1) New Data 29 Mask */
+#define CAN_NDAT1_ND29(value)                 (CAN_NDAT1_ND29_Msk & (_UINT32_(value) << CAN_NDAT1_ND29_Pos)) /* Assignment of value for ND29 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND30_Pos                    _UINT32_(30)                                         /* (CAN_NDAT1) New Data 30 Position */
+#define CAN_NDAT1_ND30_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND30_Pos)                /* (CAN_NDAT1) New Data 30 Mask */
+#define CAN_NDAT1_ND30(value)                 (CAN_NDAT1_ND30_Msk & (_UINT32_(value) << CAN_NDAT1_ND30_Pos)) /* Assignment of value for ND30 in the CAN_NDAT1 register */
+#define CAN_NDAT1_ND31_Pos                    _UINT32_(31)                                         /* (CAN_NDAT1) New Data 31 Position */
+#define CAN_NDAT1_ND31_Msk                    (_UINT32_(0x1) << CAN_NDAT1_ND31_Pos)                /* (CAN_NDAT1) New Data 31 Mask */
+#define CAN_NDAT1_ND31(value)                 (CAN_NDAT1_ND31_Msk & (_UINT32_(value) << CAN_NDAT1_ND31_Pos)) /* Assignment of value for ND31 in the CAN_NDAT1 register */
+#define CAN_NDAT1_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (CAN_NDAT1) Register Mask  */
+
+#define CAN_NDAT1_ND_Pos                      _UINT32_(0)                                          /* (CAN_NDAT1 Position) New Data 3x */
+#define CAN_NDAT1_ND_Msk                      (_UINT32_(0xFFFFFFFF) << CAN_NDAT1_ND_Pos)           /* (CAN_NDAT1 Mask) ND */
+#define CAN_NDAT1_ND(value)                   (CAN_NDAT1_ND_Msk & (_UINT32_(value) << CAN_NDAT1_ND_Pos)) 
+
+/* -------- CAN_NDAT2 : (CAN Offset: 0x19C) (R/W 32) New Data 2 -------- */
+#define CAN_NDAT2_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_NDAT2) New Data 2  Reset Value */
+
+#define CAN_NDAT2_ND32_Pos                    _UINT32_(0)                                          /* (CAN_NDAT2) New Data 32 Position */
+#define CAN_NDAT2_ND32_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND32_Pos)                /* (CAN_NDAT2) New Data 32 Mask */
+#define CAN_NDAT2_ND32(value)                 (CAN_NDAT2_ND32_Msk & (_UINT32_(value) << CAN_NDAT2_ND32_Pos)) /* Assignment of value for ND32 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND33_Pos                    _UINT32_(1)                                          /* (CAN_NDAT2) New Data 33 Position */
+#define CAN_NDAT2_ND33_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND33_Pos)                /* (CAN_NDAT2) New Data 33 Mask */
+#define CAN_NDAT2_ND33(value)                 (CAN_NDAT2_ND33_Msk & (_UINT32_(value) << CAN_NDAT2_ND33_Pos)) /* Assignment of value for ND33 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND34_Pos                    _UINT32_(2)                                          /* (CAN_NDAT2) New Data 34 Position */
+#define CAN_NDAT2_ND34_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND34_Pos)                /* (CAN_NDAT2) New Data 34 Mask */
+#define CAN_NDAT2_ND34(value)                 (CAN_NDAT2_ND34_Msk & (_UINT32_(value) << CAN_NDAT2_ND34_Pos)) /* Assignment of value for ND34 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND35_Pos                    _UINT32_(3)                                          /* (CAN_NDAT2) New Data 35 Position */
+#define CAN_NDAT2_ND35_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND35_Pos)                /* (CAN_NDAT2) New Data 35 Mask */
+#define CAN_NDAT2_ND35(value)                 (CAN_NDAT2_ND35_Msk & (_UINT32_(value) << CAN_NDAT2_ND35_Pos)) /* Assignment of value for ND35 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND36_Pos                    _UINT32_(4)                                          /* (CAN_NDAT2) New Data 36 Position */
+#define CAN_NDAT2_ND36_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND36_Pos)                /* (CAN_NDAT2) New Data 36 Mask */
+#define CAN_NDAT2_ND36(value)                 (CAN_NDAT2_ND36_Msk & (_UINT32_(value) << CAN_NDAT2_ND36_Pos)) /* Assignment of value for ND36 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND37_Pos                    _UINT32_(5)                                          /* (CAN_NDAT2) New Data 37 Position */
+#define CAN_NDAT2_ND37_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND37_Pos)                /* (CAN_NDAT2) New Data 37 Mask */
+#define CAN_NDAT2_ND37(value)                 (CAN_NDAT2_ND37_Msk & (_UINT32_(value) << CAN_NDAT2_ND37_Pos)) /* Assignment of value for ND37 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND38_Pos                    _UINT32_(6)                                          /* (CAN_NDAT2) New Data 38 Position */
+#define CAN_NDAT2_ND38_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND38_Pos)                /* (CAN_NDAT2) New Data 38 Mask */
+#define CAN_NDAT2_ND38(value)                 (CAN_NDAT2_ND38_Msk & (_UINT32_(value) << CAN_NDAT2_ND38_Pos)) /* Assignment of value for ND38 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND39_Pos                    _UINT32_(7)                                          /* (CAN_NDAT2) New Data 39 Position */
+#define CAN_NDAT2_ND39_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND39_Pos)                /* (CAN_NDAT2) New Data 39 Mask */
+#define CAN_NDAT2_ND39(value)                 (CAN_NDAT2_ND39_Msk & (_UINT32_(value) << CAN_NDAT2_ND39_Pos)) /* Assignment of value for ND39 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND40_Pos                    _UINT32_(8)                                          /* (CAN_NDAT2) New Data 40 Position */
+#define CAN_NDAT2_ND40_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND40_Pos)                /* (CAN_NDAT2) New Data 40 Mask */
+#define CAN_NDAT2_ND40(value)                 (CAN_NDAT2_ND40_Msk & (_UINT32_(value) << CAN_NDAT2_ND40_Pos)) /* Assignment of value for ND40 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND41_Pos                    _UINT32_(9)                                          /* (CAN_NDAT2) New Data 41 Position */
+#define CAN_NDAT2_ND41_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND41_Pos)                /* (CAN_NDAT2) New Data 41 Mask */
+#define CAN_NDAT2_ND41(value)                 (CAN_NDAT2_ND41_Msk & (_UINT32_(value) << CAN_NDAT2_ND41_Pos)) /* Assignment of value for ND41 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND42_Pos                    _UINT32_(10)                                         /* (CAN_NDAT2) New Data 42 Position */
+#define CAN_NDAT2_ND42_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND42_Pos)                /* (CAN_NDAT2) New Data 42 Mask */
+#define CAN_NDAT2_ND42(value)                 (CAN_NDAT2_ND42_Msk & (_UINT32_(value) << CAN_NDAT2_ND42_Pos)) /* Assignment of value for ND42 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND43_Pos                    _UINT32_(11)                                         /* (CAN_NDAT2) New Data 43 Position */
+#define CAN_NDAT2_ND43_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND43_Pos)                /* (CAN_NDAT2) New Data 43 Mask */
+#define CAN_NDAT2_ND43(value)                 (CAN_NDAT2_ND43_Msk & (_UINT32_(value) << CAN_NDAT2_ND43_Pos)) /* Assignment of value for ND43 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND44_Pos                    _UINT32_(12)                                         /* (CAN_NDAT2) New Data 44 Position */
+#define CAN_NDAT2_ND44_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND44_Pos)                /* (CAN_NDAT2) New Data 44 Mask */
+#define CAN_NDAT2_ND44(value)                 (CAN_NDAT2_ND44_Msk & (_UINT32_(value) << CAN_NDAT2_ND44_Pos)) /* Assignment of value for ND44 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND45_Pos                    _UINT32_(13)                                         /* (CAN_NDAT2) New Data 45 Position */
+#define CAN_NDAT2_ND45_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND45_Pos)                /* (CAN_NDAT2) New Data 45 Mask */
+#define CAN_NDAT2_ND45(value)                 (CAN_NDAT2_ND45_Msk & (_UINT32_(value) << CAN_NDAT2_ND45_Pos)) /* Assignment of value for ND45 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND46_Pos                    _UINT32_(14)                                         /* (CAN_NDAT2) New Data 46 Position */
+#define CAN_NDAT2_ND46_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND46_Pos)                /* (CAN_NDAT2) New Data 46 Mask */
+#define CAN_NDAT2_ND46(value)                 (CAN_NDAT2_ND46_Msk & (_UINT32_(value) << CAN_NDAT2_ND46_Pos)) /* Assignment of value for ND46 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND47_Pos                    _UINT32_(15)                                         /* (CAN_NDAT2) New Data 47 Position */
+#define CAN_NDAT2_ND47_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND47_Pos)                /* (CAN_NDAT2) New Data 47 Mask */
+#define CAN_NDAT2_ND47(value)                 (CAN_NDAT2_ND47_Msk & (_UINT32_(value) << CAN_NDAT2_ND47_Pos)) /* Assignment of value for ND47 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND48_Pos                    _UINT32_(16)                                         /* (CAN_NDAT2) New Data 48 Position */
+#define CAN_NDAT2_ND48_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND48_Pos)                /* (CAN_NDAT2) New Data 48 Mask */
+#define CAN_NDAT2_ND48(value)                 (CAN_NDAT2_ND48_Msk & (_UINT32_(value) << CAN_NDAT2_ND48_Pos)) /* Assignment of value for ND48 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND49_Pos                    _UINT32_(17)                                         /* (CAN_NDAT2) New Data 49 Position */
+#define CAN_NDAT2_ND49_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND49_Pos)                /* (CAN_NDAT2) New Data 49 Mask */
+#define CAN_NDAT2_ND49(value)                 (CAN_NDAT2_ND49_Msk & (_UINT32_(value) << CAN_NDAT2_ND49_Pos)) /* Assignment of value for ND49 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND50_Pos                    _UINT32_(18)                                         /* (CAN_NDAT2) New Data 50 Position */
+#define CAN_NDAT2_ND50_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND50_Pos)                /* (CAN_NDAT2) New Data 50 Mask */
+#define CAN_NDAT2_ND50(value)                 (CAN_NDAT2_ND50_Msk & (_UINT32_(value) << CAN_NDAT2_ND50_Pos)) /* Assignment of value for ND50 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND51_Pos                    _UINT32_(19)                                         /* (CAN_NDAT2) New Data 51 Position */
+#define CAN_NDAT2_ND51_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND51_Pos)                /* (CAN_NDAT2) New Data 51 Mask */
+#define CAN_NDAT2_ND51(value)                 (CAN_NDAT2_ND51_Msk & (_UINT32_(value) << CAN_NDAT2_ND51_Pos)) /* Assignment of value for ND51 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND52_Pos                    _UINT32_(20)                                         /* (CAN_NDAT2) New Data 52 Position */
+#define CAN_NDAT2_ND52_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND52_Pos)                /* (CAN_NDAT2) New Data 52 Mask */
+#define CAN_NDAT2_ND52(value)                 (CAN_NDAT2_ND52_Msk & (_UINT32_(value) << CAN_NDAT2_ND52_Pos)) /* Assignment of value for ND52 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND53_Pos                    _UINT32_(21)                                         /* (CAN_NDAT2) New Data 53 Position */
+#define CAN_NDAT2_ND53_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND53_Pos)                /* (CAN_NDAT2) New Data 53 Mask */
+#define CAN_NDAT2_ND53(value)                 (CAN_NDAT2_ND53_Msk & (_UINT32_(value) << CAN_NDAT2_ND53_Pos)) /* Assignment of value for ND53 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND54_Pos                    _UINT32_(22)                                         /* (CAN_NDAT2) New Data 54 Position */
+#define CAN_NDAT2_ND54_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND54_Pos)                /* (CAN_NDAT2) New Data 54 Mask */
+#define CAN_NDAT2_ND54(value)                 (CAN_NDAT2_ND54_Msk & (_UINT32_(value) << CAN_NDAT2_ND54_Pos)) /* Assignment of value for ND54 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND55_Pos                    _UINT32_(23)                                         /* (CAN_NDAT2) New Data 55 Position */
+#define CAN_NDAT2_ND55_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND55_Pos)                /* (CAN_NDAT2) New Data 55 Mask */
+#define CAN_NDAT2_ND55(value)                 (CAN_NDAT2_ND55_Msk & (_UINT32_(value) << CAN_NDAT2_ND55_Pos)) /* Assignment of value for ND55 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND56_Pos                    _UINT32_(24)                                         /* (CAN_NDAT2) New Data 56 Position */
+#define CAN_NDAT2_ND56_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND56_Pos)                /* (CAN_NDAT2) New Data 56 Mask */
+#define CAN_NDAT2_ND56(value)                 (CAN_NDAT2_ND56_Msk & (_UINT32_(value) << CAN_NDAT2_ND56_Pos)) /* Assignment of value for ND56 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND57_Pos                    _UINT32_(25)                                         /* (CAN_NDAT2) New Data 57 Position */
+#define CAN_NDAT2_ND57_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND57_Pos)                /* (CAN_NDAT2) New Data 57 Mask */
+#define CAN_NDAT2_ND57(value)                 (CAN_NDAT2_ND57_Msk & (_UINT32_(value) << CAN_NDAT2_ND57_Pos)) /* Assignment of value for ND57 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND58_Pos                    _UINT32_(26)                                         /* (CAN_NDAT2) New Data 58 Position */
+#define CAN_NDAT2_ND58_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND58_Pos)                /* (CAN_NDAT2) New Data 58 Mask */
+#define CAN_NDAT2_ND58(value)                 (CAN_NDAT2_ND58_Msk & (_UINT32_(value) << CAN_NDAT2_ND58_Pos)) /* Assignment of value for ND58 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND59_Pos                    _UINT32_(27)                                         /* (CAN_NDAT2) New Data 59 Position */
+#define CAN_NDAT2_ND59_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND59_Pos)                /* (CAN_NDAT2) New Data 59 Mask */
+#define CAN_NDAT2_ND59(value)                 (CAN_NDAT2_ND59_Msk & (_UINT32_(value) << CAN_NDAT2_ND59_Pos)) /* Assignment of value for ND59 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND60_Pos                    _UINT32_(28)                                         /* (CAN_NDAT2) New Data 60 Position */
+#define CAN_NDAT2_ND60_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND60_Pos)                /* (CAN_NDAT2) New Data 60 Mask */
+#define CAN_NDAT2_ND60(value)                 (CAN_NDAT2_ND60_Msk & (_UINT32_(value) << CAN_NDAT2_ND60_Pos)) /* Assignment of value for ND60 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND61_Pos                    _UINT32_(29)                                         /* (CAN_NDAT2) New Data 61 Position */
+#define CAN_NDAT2_ND61_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND61_Pos)                /* (CAN_NDAT2) New Data 61 Mask */
+#define CAN_NDAT2_ND61(value)                 (CAN_NDAT2_ND61_Msk & (_UINT32_(value) << CAN_NDAT2_ND61_Pos)) /* Assignment of value for ND61 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND62_Pos                    _UINT32_(30)                                         /* (CAN_NDAT2) New Data 62 Position */
+#define CAN_NDAT2_ND62_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND62_Pos)                /* (CAN_NDAT2) New Data 62 Mask */
+#define CAN_NDAT2_ND62(value)                 (CAN_NDAT2_ND62_Msk & (_UINT32_(value) << CAN_NDAT2_ND62_Pos)) /* Assignment of value for ND62 in the CAN_NDAT2 register */
+#define CAN_NDAT2_ND63_Pos                    _UINT32_(31)                                         /* (CAN_NDAT2) New Data 63 Position */
+#define CAN_NDAT2_ND63_Msk                    (_UINT32_(0x1) << CAN_NDAT2_ND63_Pos)                /* (CAN_NDAT2) New Data 63 Mask */
+#define CAN_NDAT2_ND63(value)                 (CAN_NDAT2_ND63_Msk & (_UINT32_(value) << CAN_NDAT2_ND63_Pos)) /* Assignment of value for ND63 in the CAN_NDAT2 register */
+#define CAN_NDAT2_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (CAN_NDAT2) Register Mask  */
+
+#define CAN_NDAT2_ND_Pos                      _UINT32_(0)                                          /* (CAN_NDAT2 Position) New Data 63 */
+#define CAN_NDAT2_ND_Msk                      (_UINT32_(0xFFFFFFFF) << CAN_NDAT2_ND_Pos)           /* (CAN_NDAT2 Mask) ND */
+#define CAN_NDAT2_ND(value)                   (CAN_NDAT2_ND_Msk & (_UINT32_(value) << CAN_NDAT2_ND_Pos)) 
+
+/* -------- CAN_RXF0C : (CAN Offset: 0x1A0) (R/W 32) Rx FIFO 0 Configuration -------- */
+#define CAN_RXF0C_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_RXF0C) Rx FIFO 0 Configuration  Reset Value */
+
+#define CAN_RXF0C_F0SA_Pos                    _UINT32_(2)                                          /* (CAN_RXF0C) Rx FIFO 0 Start Address Position */
+#define CAN_RXF0C_F0SA_Msk                    (_UINT32_(0x3FFF) << CAN_RXF0C_F0SA_Pos)             /* (CAN_RXF0C) Rx FIFO 0 Start Address Mask */
+#define CAN_RXF0C_F0SA(value)                 (CAN_RXF0C_F0SA_Msk & (_UINT32_(value) << CAN_RXF0C_F0SA_Pos)) /* Assignment of value for F0SA in the CAN_RXF0C register */
+#define CAN_RXF0C_F0S_Pos                     _UINT32_(16)                                         /* (CAN_RXF0C) Rx FIFO 0 Size Position */
+#define CAN_RXF0C_F0S_Msk                     (_UINT32_(0x7F) << CAN_RXF0C_F0S_Pos)                /* (CAN_RXF0C) Rx FIFO 0 Size Mask */
+#define CAN_RXF0C_F0S(value)                  (CAN_RXF0C_F0S_Msk & (_UINT32_(value) << CAN_RXF0C_F0S_Pos)) /* Assignment of value for F0S in the CAN_RXF0C register */
+#define CAN_RXF0C_F0WM_Pos                    _UINT32_(24)                                         /* (CAN_RXF0C) Rx FIFO 0 Watermark Position */
+#define CAN_RXF0C_F0WM_Msk                    (_UINT32_(0x7F) << CAN_RXF0C_F0WM_Pos)               /* (CAN_RXF0C) Rx FIFO 0 Watermark Mask */
+#define CAN_RXF0C_F0WM(value)                 (CAN_RXF0C_F0WM_Msk & (_UINT32_(value) << CAN_RXF0C_F0WM_Pos)) /* Assignment of value for F0WM in the CAN_RXF0C register */
+#define CAN_RXF0C_F0OM_Pos                    _UINT32_(31)                                         /* (CAN_RXF0C) FIFO 0 Operation Mode Position */
+#define CAN_RXF0C_F0OM_Msk                    (_UINT32_(0x1) << CAN_RXF0C_F0OM_Pos)                /* (CAN_RXF0C) FIFO 0 Operation Mode Mask */
+#define CAN_RXF0C_F0OM(value)                 (CAN_RXF0C_F0OM_Msk & (_UINT32_(value) << CAN_RXF0C_F0OM_Pos)) /* Assignment of value for F0OM in the CAN_RXF0C register */
+#define CAN_RXF0C_Msk                         _UINT32_(0xFF7FFFFC)                                 /* (CAN_RXF0C) Register Mask  */
+
+
+/* -------- CAN_RXF0S : (CAN Offset: 0x1A4) ( R/ 32) Rx FIFO 0 Status -------- */
+#define CAN_RXF0S_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_RXF0S) Rx FIFO 0 Status  Reset Value */
+
+#define CAN_RXF0S_F0FL_Pos                    _UINT32_(0)                                          /* (CAN_RXF0S) Rx FIFO 0 Fill Level Position */
+#define CAN_RXF0S_F0FL_Msk                    (_UINT32_(0x7F) << CAN_RXF0S_F0FL_Pos)               /* (CAN_RXF0S) Rx FIFO 0 Fill Level Mask */
+#define CAN_RXF0S_F0FL(value)                 (CAN_RXF0S_F0FL_Msk & (_UINT32_(value) << CAN_RXF0S_F0FL_Pos)) /* Assignment of value for F0FL in the CAN_RXF0S register */
+#define CAN_RXF0S_F0GI_Pos                    _UINT32_(8)                                          /* (CAN_RXF0S) Rx FIFO 0 Get Index Position */
+#define CAN_RXF0S_F0GI_Msk                    (_UINT32_(0x3F) << CAN_RXF0S_F0GI_Pos)               /* (CAN_RXF0S) Rx FIFO 0 Get Index Mask */
+#define CAN_RXF0S_F0GI(value)                 (CAN_RXF0S_F0GI_Msk & (_UINT32_(value) << CAN_RXF0S_F0GI_Pos)) /* Assignment of value for F0GI in the CAN_RXF0S register */
+#define CAN_RXF0S_F0PI_Pos                    _UINT32_(16)                                         /* (CAN_RXF0S) Rx FIFO 0 Put Index Position */
+#define CAN_RXF0S_F0PI_Msk                    (_UINT32_(0x3F) << CAN_RXF0S_F0PI_Pos)               /* (CAN_RXF0S) Rx FIFO 0 Put Index Mask */
+#define CAN_RXF0S_F0PI(value)                 (CAN_RXF0S_F0PI_Msk & (_UINT32_(value) << CAN_RXF0S_F0PI_Pos)) /* Assignment of value for F0PI in the CAN_RXF0S register */
+#define CAN_RXF0S_F0F_Pos                     _UINT32_(24)                                         /* (CAN_RXF0S) Rx FIFO 0 Full Position */
+#define CAN_RXF0S_F0F_Msk                     (_UINT32_(0x1) << CAN_RXF0S_F0F_Pos)                 /* (CAN_RXF0S) Rx FIFO 0 Full Mask */
+#define CAN_RXF0S_F0F(value)                  (CAN_RXF0S_F0F_Msk & (_UINT32_(value) << CAN_RXF0S_F0F_Pos)) /* Assignment of value for F0F in the CAN_RXF0S register */
+#define CAN_RXF0S_RF0L_Pos                    _UINT32_(25)                                         /* (CAN_RXF0S) Rx FIFO 0 Message Lost Position */
+#define CAN_RXF0S_RF0L_Msk                    (_UINT32_(0x1) << CAN_RXF0S_RF0L_Pos)                /* (CAN_RXF0S) Rx FIFO 0 Message Lost Mask */
+#define CAN_RXF0S_RF0L(value)                 (CAN_RXF0S_RF0L_Msk & (_UINT32_(value) << CAN_RXF0S_RF0L_Pos)) /* Assignment of value for RF0L in the CAN_RXF0S register */
+#define CAN_RXF0S_Msk                         _UINT32_(0x033F3F7F)                                 /* (CAN_RXF0S) Register Mask  */
+
+
+/* -------- CAN_RXF0A : (CAN Offset: 0x1A8) (R/W 32) Rx FIFO 0 Acknowledge -------- */
+#define CAN_RXF0A_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_RXF0A) Rx FIFO 0 Acknowledge  Reset Value */
+
+#define CAN_RXF0A_F0AI_Pos                    _UINT32_(0)                                          /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Position */
+#define CAN_RXF0A_F0AI_Msk                    (_UINT32_(0x3F) << CAN_RXF0A_F0AI_Pos)               /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Mask */
+#define CAN_RXF0A_F0AI(value)                 (CAN_RXF0A_F0AI_Msk & (_UINT32_(value) << CAN_RXF0A_F0AI_Pos)) /* Assignment of value for F0AI in the CAN_RXF0A register */
+#define CAN_RXF0A_Msk                         _UINT32_(0x0000003F)                                 /* (CAN_RXF0A) Register Mask  */
+
+
+/* -------- CAN_RXBC : (CAN Offset: 0x1AC) (R/W 32) Rx Buffer Configuration -------- */
+#define CAN_RXBC_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_RXBC) Rx Buffer Configuration  Reset Value */
+
+#define CAN_RXBC_RBSA_Pos                     _UINT32_(2)                                          /* (CAN_RXBC) Rx Buffer Start Address Position */
+#define CAN_RXBC_RBSA_Msk                     (_UINT32_(0x3FFF) << CAN_RXBC_RBSA_Pos)              /* (CAN_RXBC) Rx Buffer Start Address Mask */
+#define CAN_RXBC_RBSA(value)                  (CAN_RXBC_RBSA_Msk & (_UINT32_(value) << CAN_RXBC_RBSA_Pos)) /* Assignment of value for RBSA in the CAN_RXBC register */
+#define CAN_RXBC_Msk                          _UINT32_(0x0000FFFC)                                 /* (CAN_RXBC) Register Mask  */
+
+
+/* -------- CAN_RXF1C : (CAN Offset: 0x1B0) (R/W 32) Rx FIFO 1 Configuration -------- */
+#define CAN_RXF1C_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_RXF1C) Rx FIFO 1 Configuration  Reset Value */
+
+#define CAN_RXF1C_F1SA_Pos                    _UINT32_(2)                                          /* (CAN_RXF1C) Rx FIFO 1 Start Address Position */
+#define CAN_RXF1C_F1SA_Msk                    (_UINT32_(0x3FFF) << CAN_RXF1C_F1SA_Pos)             /* (CAN_RXF1C) Rx FIFO 1 Start Address Mask */
+#define CAN_RXF1C_F1SA(value)                 (CAN_RXF1C_F1SA_Msk & (_UINT32_(value) << CAN_RXF1C_F1SA_Pos)) /* Assignment of value for F1SA in the CAN_RXF1C register */
+#define CAN_RXF1C_F1S_Pos                     _UINT32_(16)                                         /* (CAN_RXF1C) Rx FIFO 1 Size Position */
+#define CAN_RXF1C_F1S_Msk                     (_UINT32_(0x7F) << CAN_RXF1C_F1S_Pos)                /* (CAN_RXF1C) Rx FIFO 1 Size Mask */
+#define CAN_RXF1C_F1S(value)                  (CAN_RXF1C_F1S_Msk & (_UINT32_(value) << CAN_RXF1C_F1S_Pos)) /* Assignment of value for F1S in the CAN_RXF1C register */
+#define CAN_RXF1C_F1WM_Pos                    _UINT32_(24)                                         /* (CAN_RXF1C) Rx FIFO 1 Watermark Position */
+#define CAN_RXF1C_F1WM_Msk                    (_UINT32_(0x7F) << CAN_RXF1C_F1WM_Pos)               /* (CAN_RXF1C) Rx FIFO 1 Watermark Mask */
+#define CAN_RXF1C_F1WM(value)                 (CAN_RXF1C_F1WM_Msk & (_UINT32_(value) << CAN_RXF1C_F1WM_Pos)) /* Assignment of value for F1WM in the CAN_RXF1C register */
+#define CAN_RXF1C_F1OM_Pos                    _UINT32_(31)                                         /* (CAN_RXF1C) FIFO 1 Operation Mode Position */
+#define CAN_RXF1C_F1OM_Msk                    (_UINT32_(0x1) << CAN_RXF1C_F1OM_Pos)                /* (CAN_RXF1C) FIFO 1 Operation Mode Mask */
+#define CAN_RXF1C_F1OM(value)                 (CAN_RXF1C_F1OM_Msk & (_UINT32_(value) << CAN_RXF1C_F1OM_Pos)) /* Assignment of value for F1OM in the CAN_RXF1C register */
+#define CAN_RXF1C_Msk                         _UINT32_(0xFF7FFFFC)                                 /* (CAN_RXF1C) Register Mask  */
+
+
+/* -------- CAN_RXF1S : (CAN Offset: 0x1B4) ( R/ 32) Rx FIFO 1 Status -------- */
+#define CAN_RXF1S_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_RXF1S) Rx FIFO 1 Status  Reset Value */
+
+#define CAN_RXF1S_F1FL_Pos                    _UINT32_(0)                                          /* (CAN_RXF1S) Rx FIFO 1 Fill Level Position */
+#define CAN_RXF1S_F1FL_Msk                    (_UINT32_(0x7F) << CAN_RXF1S_F1FL_Pos)               /* (CAN_RXF1S) Rx FIFO 1 Fill Level Mask */
+#define CAN_RXF1S_F1FL(value)                 (CAN_RXF1S_F1FL_Msk & (_UINT32_(value) << CAN_RXF1S_F1FL_Pos)) /* Assignment of value for F1FL in the CAN_RXF1S register */
+#define CAN_RXF1S_F1GI_Pos                    _UINT32_(8)                                          /* (CAN_RXF1S) Rx FIFO 1 Get Index Position */
+#define CAN_RXF1S_F1GI_Msk                    (_UINT32_(0x3F) << CAN_RXF1S_F1GI_Pos)               /* (CAN_RXF1S) Rx FIFO 1 Get Index Mask */
+#define CAN_RXF1S_F1GI(value)                 (CAN_RXF1S_F1GI_Msk & (_UINT32_(value) << CAN_RXF1S_F1GI_Pos)) /* Assignment of value for F1GI in the CAN_RXF1S register */
+#define CAN_RXF1S_F1PI_Pos                    _UINT32_(16)                                         /* (CAN_RXF1S) Rx FIFO 1 Put Index Position */
+#define CAN_RXF1S_F1PI_Msk                    (_UINT32_(0x3F) << CAN_RXF1S_F1PI_Pos)               /* (CAN_RXF1S) Rx FIFO 1 Put Index Mask */
+#define CAN_RXF1S_F1PI(value)                 (CAN_RXF1S_F1PI_Msk & (_UINT32_(value) << CAN_RXF1S_F1PI_Pos)) /* Assignment of value for F1PI in the CAN_RXF1S register */
+#define CAN_RXF1S_F1F_Pos                     _UINT32_(24)                                         /* (CAN_RXF1S) Rx FIFO 1 Full Position */
+#define CAN_RXF1S_F1F_Msk                     (_UINT32_(0x1) << CAN_RXF1S_F1F_Pos)                 /* (CAN_RXF1S) Rx FIFO 1 Full Mask */
+#define CAN_RXF1S_F1F(value)                  (CAN_RXF1S_F1F_Msk & (_UINT32_(value) << CAN_RXF1S_F1F_Pos)) /* Assignment of value for F1F in the CAN_RXF1S register */
+#define CAN_RXF1S_RF1L_Pos                    _UINT32_(25)                                         /* (CAN_RXF1S) Rx FIFO 1 Message Lost Position */
+#define CAN_RXF1S_RF1L_Msk                    (_UINT32_(0x1) << CAN_RXF1S_RF1L_Pos)                /* (CAN_RXF1S) Rx FIFO 1 Message Lost Mask */
+#define CAN_RXF1S_RF1L(value)                 (CAN_RXF1S_RF1L_Msk & (_UINT32_(value) << CAN_RXF1S_RF1L_Pos)) /* Assignment of value for RF1L in the CAN_RXF1S register */
+#define CAN_RXF1S_DMS_Pos                     _UINT32_(30)                                         /* (CAN_RXF1S) Debug Message Status Position */
+#define CAN_RXF1S_DMS_Msk                     (_UINT32_(0x3) << CAN_RXF1S_DMS_Pos)                 /* (CAN_RXF1S) Debug Message Status Mask */
+#define CAN_RXF1S_DMS(value)                  (CAN_RXF1S_DMS_Msk & (_UINT32_(value) << CAN_RXF1S_DMS_Pos)) /* Assignment of value for DMS in the CAN_RXF1S register */
+#define   CAN_RXF1S_DMS_IDLE_Val              _UINT32_(0x0)                                        /* (CAN_RXF1S) Idle state  */
+#define   CAN_RXF1S_DMS_DBGA_Val              _UINT32_(0x1)                                        /* (CAN_RXF1S) Debug message A received  */
+#define   CAN_RXF1S_DMS_DBGB_Val              _UINT32_(0x2)                                        /* (CAN_RXF1S) Debug message A/B received  */
+#define   CAN_RXF1S_DMS_DBGC_Val              _UINT32_(0x3)                                        /* (CAN_RXF1S) Debug message A/B/C received, DMA request set  */
+#define CAN_RXF1S_DMS_IDLE                    (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos)        /* (CAN_RXF1S) Idle state Position */
+#define CAN_RXF1S_DMS_DBGA                    (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos)        /* (CAN_RXF1S) Debug message A received Position */
+#define CAN_RXF1S_DMS_DBGB                    (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos)        /* (CAN_RXF1S) Debug message A/B received Position */
+#define CAN_RXF1S_DMS_DBGC                    (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos)        /* (CAN_RXF1S) Debug message A/B/C received, DMA request set Position */
+#define CAN_RXF1S_Msk                         _UINT32_(0xC33F3F7F)                                 /* (CAN_RXF1S) Register Mask  */
+
+
+/* -------- CAN_RXF1A : (CAN Offset: 0x1B8) (R/W 32) Rx FIFO 1 Acknowledge -------- */
+#define CAN_RXF1A_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_RXF1A) Rx FIFO 1 Acknowledge  Reset Value */
+
+#define CAN_RXF1A_F1AI_Pos                    _UINT32_(0)                                          /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Position */
+#define CAN_RXF1A_F1AI_Msk                    (_UINT32_(0x3F) << CAN_RXF1A_F1AI_Pos)               /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Mask */
+#define CAN_RXF1A_F1AI(value)                 (CAN_RXF1A_F1AI_Msk & (_UINT32_(value) << CAN_RXF1A_F1AI_Pos)) /* Assignment of value for F1AI in the CAN_RXF1A register */
+#define CAN_RXF1A_Msk                         _UINT32_(0x0000003F)                                 /* (CAN_RXF1A) Register Mask  */
+
+
+/* -------- CAN_RXESC : (CAN Offset: 0x1BC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */
+#define CAN_RXESC_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration  Reset Value */
+
+#define CAN_RXESC_F0DS_Pos                    _UINT32_(0)                                          /* (CAN_RXESC) Rx FIFO 0 Data Field Size Position */
+#define CAN_RXESC_F0DS_Msk                    (_UINT32_(0x7) << CAN_RXESC_F0DS_Pos)                /* (CAN_RXESC) Rx FIFO 0 Data Field Size Mask */
+#define CAN_RXESC_F0DS(value)                 (CAN_RXESC_F0DS_Msk & (_UINT32_(value) << CAN_RXESC_F0DS_Pos)) /* Assignment of value for F0DS in the CAN_RXESC register */
+#define   CAN_RXESC_F0DS_DATA8_Val            _UINT32_(0x0)                                        /* (CAN_RXESC) 8 byte data field  */
+#define   CAN_RXESC_F0DS_DATA12_Val           _UINT32_(0x1)                                        /* (CAN_RXESC) 12 byte data field  */
+#define   CAN_RXESC_F0DS_DATA16_Val           _UINT32_(0x2)                                        /* (CAN_RXESC) 16 byte data field  */
+#define   CAN_RXESC_F0DS_DATA20_Val           _UINT32_(0x3)                                        /* (CAN_RXESC) 20 byte data field  */
+#define   CAN_RXESC_F0DS_DATA24_Val           _UINT32_(0x4)                                        /* (CAN_RXESC) 24 byte data field  */
+#define   CAN_RXESC_F0DS_DATA32_Val           _UINT32_(0x5)                                        /* (CAN_RXESC) 32 byte data field  */
+#define   CAN_RXESC_F0DS_DATA48_Val           _UINT32_(0x6)                                        /* (CAN_RXESC) 48 byte data field  */
+#define   CAN_RXESC_F0DS_DATA64_Val           _UINT32_(0x7)                                        /* (CAN_RXESC) 64 byte data field  */
+#define CAN_RXESC_F0DS_DATA8                  (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos)     /* (CAN_RXESC) 8 byte data field Position */
+#define CAN_RXESC_F0DS_DATA12                 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos)    /* (CAN_RXESC) 12 byte data field Position */
+#define CAN_RXESC_F0DS_DATA16                 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos)    /* (CAN_RXESC) 16 byte data field Position */
+#define CAN_RXESC_F0DS_DATA20                 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos)    /* (CAN_RXESC) 20 byte data field Position */
+#define CAN_RXESC_F0DS_DATA24                 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos)    /* (CAN_RXESC) 24 byte data field Position */
+#define CAN_RXESC_F0DS_DATA32                 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos)    /* (CAN_RXESC) 32 byte data field Position */
+#define CAN_RXESC_F0DS_DATA48                 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos)    /* (CAN_RXESC) 48 byte data field Position */
+#define CAN_RXESC_F0DS_DATA64                 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos)    /* (CAN_RXESC) 64 byte data field Position */
+#define CAN_RXESC_F1DS_Pos                    _UINT32_(4)                                          /* (CAN_RXESC) Rx FIFO 1 Data Field Size Position */
+#define CAN_RXESC_F1DS_Msk                    (_UINT32_(0x7) << CAN_RXESC_F1DS_Pos)                /* (CAN_RXESC) Rx FIFO 1 Data Field Size Mask */
+#define CAN_RXESC_F1DS(value)                 (CAN_RXESC_F1DS_Msk & (_UINT32_(value) << CAN_RXESC_F1DS_Pos)) /* Assignment of value for F1DS in the CAN_RXESC register */
+#define   CAN_RXESC_F1DS_DATA8_Val            _UINT32_(0x0)                                        /* (CAN_RXESC) 8 byte data field  */
+#define   CAN_RXESC_F1DS_DATA12_Val           _UINT32_(0x1)                                        /* (CAN_RXESC) 12 byte data field  */
+#define   CAN_RXESC_F1DS_DATA16_Val           _UINT32_(0x2)                                        /* (CAN_RXESC) 16 byte data field  */
+#define   CAN_RXESC_F1DS_DATA20_Val           _UINT32_(0x3)                                        /* (CAN_RXESC) 20 byte data field  */
+#define   CAN_RXESC_F1DS_DATA24_Val           _UINT32_(0x4)                                        /* (CAN_RXESC) 24 byte data field  */
+#define   CAN_RXESC_F1DS_DATA32_Val           _UINT32_(0x5)                                        /* (CAN_RXESC) 32 byte data field  */
+#define   CAN_RXESC_F1DS_DATA48_Val           _UINT32_(0x6)                                        /* (CAN_RXESC) 48 byte data field  */
+#define   CAN_RXESC_F1DS_DATA64_Val           _UINT32_(0x7)                                        /* (CAN_RXESC) 64 byte data field  */
+#define CAN_RXESC_F1DS_DATA8                  (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos)     /* (CAN_RXESC) 8 byte data field Position */
+#define CAN_RXESC_F1DS_DATA12                 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos)    /* (CAN_RXESC) 12 byte data field Position */
+#define CAN_RXESC_F1DS_DATA16                 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos)    /* (CAN_RXESC) 16 byte data field Position */
+#define CAN_RXESC_F1DS_DATA20                 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos)    /* (CAN_RXESC) 20 byte data field Position */
+#define CAN_RXESC_F1DS_DATA24                 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos)    /* (CAN_RXESC) 24 byte data field Position */
+#define CAN_RXESC_F1DS_DATA32                 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos)    /* (CAN_RXESC) 32 byte data field Position */
+#define CAN_RXESC_F1DS_DATA48                 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos)    /* (CAN_RXESC) 48 byte data field Position */
+#define CAN_RXESC_F1DS_DATA64                 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos)    /* (CAN_RXESC) 64 byte data field Position */
+#define CAN_RXESC_RBDS_Pos                    _UINT32_(8)                                          /* (CAN_RXESC) Rx Buffer Data Field Size Position */
+#define CAN_RXESC_RBDS_Msk                    (_UINT32_(0x7) << CAN_RXESC_RBDS_Pos)                /* (CAN_RXESC) Rx Buffer Data Field Size Mask */
+#define CAN_RXESC_RBDS(value)                 (CAN_RXESC_RBDS_Msk & (_UINT32_(value) << CAN_RXESC_RBDS_Pos)) /* Assignment of value for RBDS in the CAN_RXESC register */
+#define   CAN_RXESC_RBDS_DATA8_Val            _UINT32_(0x0)                                        /* (CAN_RXESC) 8 byte data field  */
+#define   CAN_RXESC_RBDS_DATA12_Val           _UINT32_(0x1)                                        /* (CAN_RXESC) 12 byte data field  */
+#define   CAN_RXESC_RBDS_DATA16_Val           _UINT32_(0x2)                                        /* (CAN_RXESC) 16 byte data field  */
+#define   CAN_RXESC_RBDS_DATA20_Val           _UINT32_(0x3)                                        /* (CAN_RXESC) 20 byte data field  */
+#define   CAN_RXESC_RBDS_DATA24_Val           _UINT32_(0x4)                                        /* (CAN_RXESC) 24 byte data field  */
+#define   CAN_RXESC_RBDS_DATA32_Val           _UINT32_(0x5)                                        /* (CAN_RXESC) 32 byte data field  */
+#define   CAN_RXESC_RBDS_DATA48_Val           _UINT32_(0x6)                                        /* (CAN_RXESC) 48 byte data field  */
+#define   CAN_RXESC_RBDS_DATA64_Val           _UINT32_(0x7)                                        /* (CAN_RXESC) 64 byte data field  */
+#define CAN_RXESC_RBDS_DATA8                  (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos)     /* (CAN_RXESC) 8 byte data field Position */
+#define CAN_RXESC_RBDS_DATA12                 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos)    /* (CAN_RXESC) 12 byte data field Position */
+#define CAN_RXESC_RBDS_DATA16                 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos)    /* (CAN_RXESC) 16 byte data field Position */
+#define CAN_RXESC_RBDS_DATA20                 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos)    /* (CAN_RXESC) 20 byte data field Position */
+#define CAN_RXESC_RBDS_DATA24                 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos)    /* (CAN_RXESC) 24 byte data field Position */
+#define CAN_RXESC_RBDS_DATA32                 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos)    /* (CAN_RXESC) 32 byte data field Position */
+#define CAN_RXESC_RBDS_DATA48                 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos)    /* (CAN_RXESC) 48 byte data field Position */
+#define CAN_RXESC_RBDS_DATA64                 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos)    /* (CAN_RXESC) 64 byte data field Position */
+#define CAN_RXESC_Msk                         _UINT32_(0x00000777)                                 /* (CAN_RXESC) Register Mask  */
+
+
+/* -------- CAN_TXBC : (CAN Offset: 0x1C0) (R/W 32) Tx Buffer Configuration -------- */
+#define CAN_TXBC_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TXBC) Tx Buffer Configuration  Reset Value */
+
+#define CAN_TXBC_TBSA_Pos                     _UINT32_(2)                                          /* (CAN_TXBC) Tx Buffers Start Address Position */
+#define CAN_TXBC_TBSA_Msk                     (_UINT32_(0x3FFF) << CAN_TXBC_TBSA_Pos)              /* (CAN_TXBC) Tx Buffers Start Address Mask */
+#define CAN_TXBC_TBSA(value)                  (CAN_TXBC_TBSA_Msk & (_UINT32_(value) << CAN_TXBC_TBSA_Pos)) /* Assignment of value for TBSA in the CAN_TXBC register */
+#define CAN_TXBC_NDTB_Pos                     _UINT32_(16)                                         /* (CAN_TXBC) Number of Dedicated Transmit Buffers Position */
+#define CAN_TXBC_NDTB_Msk                     (_UINT32_(0x3F) << CAN_TXBC_NDTB_Pos)                /* (CAN_TXBC) Number of Dedicated Transmit Buffers Mask */
+#define CAN_TXBC_NDTB(value)                  (CAN_TXBC_NDTB_Msk & (_UINT32_(value) << CAN_TXBC_NDTB_Pos)) /* Assignment of value for NDTB in the CAN_TXBC register */
+#define CAN_TXBC_TFQS_Pos                     _UINT32_(24)                                         /* (CAN_TXBC) Transmit FIFO/Queue Size Position */
+#define CAN_TXBC_TFQS_Msk                     (_UINT32_(0x3F) << CAN_TXBC_TFQS_Pos)                /* (CAN_TXBC) Transmit FIFO/Queue Size Mask */
+#define CAN_TXBC_TFQS(value)                  (CAN_TXBC_TFQS_Msk & (_UINT32_(value) << CAN_TXBC_TFQS_Pos)) /* Assignment of value for TFQS in the CAN_TXBC register */
+#define CAN_TXBC_TFQM_Pos                     _UINT32_(30)                                         /* (CAN_TXBC) Tx FIFO/Queue Mode Position */
+#define CAN_TXBC_TFQM_Msk                     (_UINT32_(0x1) << CAN_TXBC_TFQM_Pos)                 /* (CAN_TXBC) Tx FIFO/Queue Mode Mask */
+#define CAN_TXBC_TFQM(value)                  (CAN_TXBC_TFQM_Msk & (_UINT32_(value) << CAN_TXBC_TFQM_Pos)) /* Assignment of value for TFQM in the CAN_TXBC register */
+#define CAN_TXBC_Msk                          _UINT32_(0x7F3FFFFC)                                 /* (CAN_TXBC) Register Mask  */
+
+
+/* -------- CAN_TXFQS : (CAN Offset: 0x1C4) ( R/ 32) Tx FIFO / Queue Status -------- */
+#define CAN_TXFQS_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TXFQS) Tx FIFO / Queue Status  Reset Value */
+
+#define CAN_TXFQS_TFFL_Pos                    _UINT32_(0)                                          /* (CAN_TXFQS) Tx FIFO Free Level Position */
+#define CAN_TXFQS_TFFL_Msk                    (_UINT32_(0x3F) << CAN_TXFQS_TFFL_Pos)               /* (CAN_TXFQS) Tx FIFO Free Level Mask */
+#define CAN_TXFQS_TFFL(value)                 (CAN_TXFQS_TFFL_Msk & (_UINT32_(value) << CAN_TXFQS_TFFL_Pos)) /* Assignment of value for TFFL in the CAN_TXFQS register */
+#define CAN_TXFQS_TFGI_Pos                    _UINT32_(8)                                          /* (CAN_TXFQS) Tx FIFO Get Index Position */
+#define CAN_TXFQS_TFGI_Msk                    (_UINT32_(0x1F) << CAN_TXFQS_TFGI_Pos)               /* (CAN_TXFQS) Tx FIFO Get Index Mask */
+#define CAN_TXFQS_TFGI(value)                 (CAN_TXFQS_TFGI_Msk & (_UINT32_(value) << CAN_TXFQS_TFGI_Pos)) /* Assignment of value for TFGI in the CAN_TXFQS register */
+#define CAN_TXFQS_TFQPI_Pos                   _UINT32_(16)                                         /* (CAN_TXFQS) Tx FIFO/Queue Put Index Position */
+#define CAN_TXFQS_TFQPI_Msk                   (_UINT32_(0x1F) << CAN_TXFQS_TFQPI_Pos)              /* (CAN_TXFQS) Tx FIFO/Queue Put Index Mask */
+#define CAN_TXFQS_TFQPI(value)                (CAN_TXFQS_TFQPI_Msk & (_UINT32_(value) << CAN_TXFQS_TFQPI_Pos)) /* Assignment of value for TFQPI in the CAN_TXFQS register */
+#define CAN_TXFQS_TFQF_Pos                    _UINT32_(21)                                         /* (CAN_TXFQS) Tx FIFO/Queue Full Position */
+#define CAN_TXFQS_TFQF_Msk                    (_UINT32_(0x1) << CAN_TXFQS_TFQF_Pos)                /* (CAN_TXFQS) Tx FIFO/Queue Full Mask */
+#define CAN_TXFQS_TFQF(value)                 (CAN_TXFQS_TFQF_Msk & (_UINT32_(value) << CAN_TXFQS_TFQF_Pos)) /* Assignment of value for TFQF in the CAN_TXFQS register */
+#define CAN_TXFQS_Msk                         _UINT32_(0x003F1F3F)                                 /* (CAN_TXFQS) Register Mask  */
+
+
+/* -------- CAN_TXESC : (CAN Offset: 0x1C8) (R/W 32) Tx Buffer Element Size Configuration -------- */
+#define CAN_TXESC_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TXESC) Tx Buffer Element Size Configuration  Reset Value */
+
+#define CAN_TXESC_TBDS_Pos                    _UINT32_(0)                                          /* (CAN_TXESC) Tx Buffer Data Field Size Position */
+#define CAN_TXESC_TBDS_Msk                    (_UINT32_(0x7) << CAN_TXESC_TBDS_Pos)                /* (CAN_TXESC) Tx Buffer Data Field Size Mask */
+#define CAN_TXESC_TBDS(value)                 (CAN_TXESC_TBDS_Msk & (_UINT32_(value) << CAN_TXESC_TBDS_Pos)) /* Assignment of value for TBDS in the CAN_TXESC register */
+#define   CAN_TXESC_TBDS_DATA8_Val            _UINT32_(0x0)                                        /* (CAN_TXESC) 8 byte data field  */
+#define   CAN_TXESC_TBDS_DATA12_Val           _UINT32_(0x1)                                        /* (CAN_TXESC) 12 byte data field  */
+#define   CAN_TXESC_TBDS_DATA16_Val           _UINT32_(0x2)                                        /* (CAN_TXESC) 16 byte data field  */
+#define   CAN_TXESC_TBDS_DATA20_Val           _UINT32_(0x3)                                        /* (CAN_TXESC) 20 byte data field  */
+#define   CAN_TXESC_TBDS_DATA24_Val           _UINT32_(0x4)                                        /* (CAN_TXESC) 24 byte data field  */
+#define   CAN_TXESC_TBDS_DATA32_Val           _UINT32_(0x5)                                        /* (CAN_TXESC) 32 byte data field  */
+#define   CAN_TXESC_TBDS_DATA48_Val           _UINT32_(0x6)                                        /* (CAN_TXESC) 48 byte data field  */
+#define   CAN_TXESC_TBDS_DATA64_Val           _UINT32_(0x7)                                        /* (CAN_TXESC) 64 byte data field  */
+#define CAN_TXESC_TBDS_DATA8                  (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos)     /* (CAN_TXESC) 8 byte data field Position */
+#define CAN_TXESC_TBDS_DATA12                 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos)    /* (CAN_TXESC) 12 byte data field Position */
+#define CAN_TXESC_TBDS_DATA16                 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos)    /* (CAN_TXESC) 16 byte data field Position */
+#define CAN_TXESC_TBDS_DATA20                 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos)    /* (CAN_TXESC) 20 byte data field Position */
+#define CAN_TXESC_TBDS_DATA24                 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos)    /* (CAN_TXESC) 24 byte data field Position */
+#define CAN_TXESC_TBDS_DATA32                 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos)    /* (CAN_TXESC) 32 byte data field Position */
+#define CAN_TXESC_TBDS_DATA48                 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos)    /* (CAN_TXESC) 48 byte data field Position */
+#define CAN_TXESC_TBDS_DATA64                 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos)    /* (CAN_TXESC) 64 byte data field Position */
+#define CAN_TXESC_Msk                         _UINT32_(0x00000007)                                 /* (CAN_TXESC) Register Mask  */
+
+
+/* -------- CAN_TXBRP : (CAN Offset: 0x1CC) ( R/ 32) Tx Buffer Request Pending -------- */
+#define CAN_TXBRP_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TXBRP) Tx Buffer Request Pending  Reset Value */
+
+#define CAN_TXBRP_TRP0_Pos                    _UINT32_(0)                                          /* (CAN_TXBRP) Transmission Request Pending 0 Position */
+#define CAN_TXBRP_TRP0_Msk                    (_UINT32_(0x1) << CAN_TXBRP_TRP0_Pos)                /* (CAN_TXBRP) Transmission Request Pending 0 Mask */
+#define CAN_TXBRP_TRP0(value)                 (CAN_TXBRP_TRP0_Msk & (_UINT32_(value) << CAN_TXBRP_TRP0_Pos)) /* Assignment of value for TRP0 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP1_Pos                    _UINT32_(1)                                          /* (CAN_TXBRP) Transmission Request Pending 1 Position */
+#define CAN_TXBRP_TRP1_Msk                    (_UINT32_(0x1) << CAN_TXBRP_TRP1_Pos)                /* (CAN_TXBRP) Transmission Request Pending 1 Mask */
+#define CAN_TXBRP_TRP1(value)                 (CAN_TXBRP_TRP1_Msk & (_UINT32_(value) << CAN_TXBRP_TRP1_Pos)) /* Assignment of value for TRP1 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP2_Pos                    _UINT32_(2)                                          /* (CAN_TXBRP) Transmission Request Pending 2 Position */
+#define CAN_TXBRP_TRP2_Msk                    (_UINT32_(0x1) << CAN_TXBRP_TRP2_Pos)                /* (CAN_TXBRP) Transmission Request Pending 2 Mask */
+#define CAN_TXBRP_TRP2(value)                 (CAN_TXBRP_TRP2_Msk & (_UINT32_(value) << CAN_TXBRP_TRP2_Pos)) /* Assignment of value for TRP2 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP3_Pos                    _UINT32_(3)                                          /* (CAN_TXBRP) Transmission Request Pending 3 Position */
+#define CAN_TXBRP_TRP3_Msk                    (_UINT32_(0x1) << CAN_TXBRP_TRP3_Pos)                /* (CAN_TXBRP) Transmission Request Pending 3 Mask */
+#define CAN_TXBRP_TRP3(value)                 (CAN_TXBRP_TRP3_Msk & (_UINT32_(value) << CAN_TXBRP_TRP3_Pos)) /* Assignment of value for TRP3 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP4_Pos                    _UINT32_(4)                                          /* (CAN_TXBRP) Transmission Request Pending 4 Position */
+#define CAN_TXBRP_TRP4_Msk                    (_UINT32_(0x1) << CAN_TXBRP_TRP4_Pos)                /* (CAN_TXBRP) Transmission Request Pending 4 Mask */
+#define CAN_TXBRP_TRP4(value)                 (CAN_TXBRP_TRP4_Msk & (_UINT32_(value) << CAN_TXBRP_TRP4_Pos)) /* Assignment of value for TRP4 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP5_Pos                    _UINT32_(5)                                          /* (CAN_TXBRP) Transmission Request Pending 5 Position */
+#define CAN_TXBRP_TRP5_Msk                    (_UINT32_(0x1) << CAN_TXBRP_TRP5_Pos)                /* (CAN_TXBRP) Transmission Request Pending 5 Mask */
+#define CAN_TXBRP_TRP5(value)                 (CAN_TXBRP_TRP5_Msk & (_UINT32_(value) << CAN_TXBRP_TRP5_Pos)) /* Assignment of value for TRP5 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP6_Pos                    _UINT32_(6)                                          /* (CAN_TXBRP) Transmission Request Pending 6 Position */
+#define CAN_TXBRP_TRP6_Msk                    (_UINT32_(0x1) << CAN_TXBRP_TRP6_Pos)                /* (CAN_TXBRP) Transmission Request Pending 6 Mask */
+#define CAN_TXBRP_TRP6(value)                 (CAN_TXBRP_TRP6_Msk & (_UINT32_(value) << CAN_TXBRP_TRP6_Pos)) /* Assignment of value for TRP6 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP7_Pos                    _UINT32_(7)                                          /* (CAN_TXBRP) Transmission Request Pending 7 Position */
+#define CAN_TXBRP_TRP7_Msk                    (_UINT32_(0x1) << CAN_TXBRP_TRP7_Pos)                /* (CAN_TXBRP) Transmission Request Pending 7 Mask */
+#define CAN_TXBRP_TRP7(value)                 (CAN_TXBRP_TRP7_Msk & (_UINT32_(value) << CAN_TXBRP_TRP7_Pos)) /* Assignment of value for TRP7 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP8_Pos                    _UINT32_(8)                                          /* (CAN_TXBRP) Transmission Request Pending 8 Position */
+#define CAN_TXBRP_TRP8_Msk                    (_UINT32_(0x1) << CAN_TXBRP_TRP8_Pos)                /* (CAN_TXBRP) Transmission Request Pending 8 Mask */
+#define CAN_TXBRP_TRP8(value)                 (CAN_TXBRP_TRP8_Msk & (_UINT32_(value) << CAN_TXBRP_TRP8_Pos)) /* Assignment of value for TRP8 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP9_Pos                    _UINT32_(9)                                          /* (CAN_TXBRP) Transmission Request Pending 9 Position */
+#define CAN_TXBRP_TRP9_Msk                    (_UINT32_(0x1) << CAN_TXBRP_TRP9_Pos)                /* (CAN_TXBRP) Transmission Request Pending 9 Mask */
+#define CAN_TXBRP_TRP9(value)                 (CAN_TXBRP_TRP9_Msk & (_UINT32_(value) << CAN_TXBRP_TRP9_Pos)) /* Assignment of value for TRP9 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP10_Pos                   _UINT32_(10)                                         /* (CAN_TXBRP) Transmission Request Pending 10 Position */
+#define CAN_TXBRP_TRP10_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP10_Pos)               /* (CAN_TXBRP) Transmission Request Pending 10 Mask */
+#define CAN_TXBRP_TRP10(value)                (CAN_TXBRP_TRP10_Msk & (_UINT32_(value) << CAN_TXBRP_TRP10_Pos)) /* Assignment of value for TRP10 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP11_Pos                   _UINT32_(11)                                         /* (CAN_TXBRP) Transmission Request Pending 11 Position */
+#define CAN_TXBRP_TRP11_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP11_Pos)               /* (CAN_TXBRP) Transmission Request Pending 11 Mask */
+#define CAN_TXBRP_TRP11(value)                (CAN_TXBRP_TRP11_Msk & (_UINT32_(value) << CAN_TXBRP_TRP11_Pos)) /* Assignment of value for TRP11 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP12_Pos                   _UINT32_(12)                                         /* (CAN_TXBRP) Transmission Request Pending 12 Position */
+#define CAN_TXBRP_TRP12_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP12_Pos)               /* (CAN_TXBRP) Transmission Request Pending 12 Mask */
+#define CAN_TXBRP_TRP12(value)                (CAN_TXBRP_TRP12_Msk & (_UINT32_(value) << CAN_TXBRP_TRP12_Pos)) /* Assignment of value for TRP12 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP13_Pos                   _UINT32_(13)                                         /* (CAN_TXBRP) Transmission Request Pending 13 Position */
+#define CAN_TXBRP_TRP13_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP13_Pos)               /* (CAN_TXBRP) Transmission Request Pending 13 Mask */
+#define CAN_TXBRP_TRP13(value)                (CAN_TXBRP_TRP13_Msk & (_UINT32_(value) << CAN_TXBRP_TRP13_Pos)) /* Assignment of value for TRP13 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP14_Pos                   _UINT32_(14)                                         /* (CAN_TXBRP) Transmission Request Pending 14 Position */
+#define CAN_TXBRP_TRP14_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP14_Pos)               /* (CAN_TXBRP) Transmission Request Pending 14 Mask */
+#define CAN_TXBRP_TRP14(value)                (CAN_TXBRP_TRP14_Msk & (_UINT32_(value) << CAN_TXBRP_TRP14_Pos)) /* Assignment of value for TRP14 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP15_Pos                   _UINT32_(15)                                         /* (CAN_TXBRP) Transmission Request Pending 15 Position */
+#define CAN_TXBRP_TRP15_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP15_Pos)               /* (CAN_TXBRP) Transmission Request Pending 15 Mask */
+#define CAN_TXBRP_TRP15(value)                (CAN_TXBRP_TRP15_Msk & (_UINT32_(value) << CAN_TXBRP_TRP15_Pos)) /* Assignment of value for TRP15 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP16_Pos                   _UINT32_(16)                                         /* (CAN_TXBRP) Transmission Request Pending 16 Position */
+#define CAN_TXBRP_TRP16_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP16_Pos)               /* (CAN_TXBRP) Transmission Request Pending 16 Mask */
+#define CAN_TXBRP_TRP16(value)                (CAN_TXBRP_TRP16_Msk & (_UINT32_(value) << CAN_TXBRP_TRP16_Pos)) /* Assignment of value for TRP16 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP17_Pos                   _UINT32_(17)                                         /* (CAN_TXBRP) Transmission Request Pending 17 Position */
+#define CAN_TXBRP_TRP17_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP17_Pos)               /* (CAN_TXBRP) Transmission Request Pending 17 Mask */
+#define CAN_TXBRP_TRP17(value)                (CAN_TXBRP_TRP17_Msk & (_UINT32_(value) << CAN_TXBRP_TRP17_Pos)) /* Assignment of value for TRP17 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP18_Pos                   _UINT32_(18)                                         /* (CAN_TXBRP) Transmission Request Pending 18 Position */
+#define CAN_TXBRP_TRP18_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP18_Pos)               /* (CAN_TXBRP) Transmission Request Pending 18 Mask */
+#define CAN_TXBRP_TRP18(value)                (CAN_TXBRP_TRP18_Msk & (_UINT32_(value) << CAN_TXBRP_TRP18_Pos)) /* Assignment of value for TRP18 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP19_Pos                   _UINT32_(19)                                         /* (CAN_TXBRP) Transmission Request Pending 19 Position */
+#define CAN_TXBRP_TRP19_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP19_Pos)               /* (CAN_TXBRP) Transmission Request Pending 19 Mask */
+#define CAN_TXBRP_TRP19(value)                (CAN_TXBRP_TRP19_Msk & (_UINT32_(value) << CAN_TXBRP_TRP19_Pos)) /* Assignment of value for TRP19 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP20_Pos                   _UINT32_(20)                                         /* (CAN_TXBRP) Transmission Request Pending 20 Position */
+#define CAN_TXBRP_TRP20_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP20_Pos)               /* (CAN_TXBRP) Transmission Request Pending 20 Mask */
+#define CAN_TXBRP_TRP20(value)                (CAN_TXBRP_TRP20_Msk & (_UINT32_(value) << CAN_TXBRP_TRP20_Pos)) /* Assignment of value for TRP20 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP21_Pos                   _UINT32_(21)                                         /* (CAN_TXBRP) Transmission Request Pending 21 Position */
+#define CAN_TXBRP_TRP21_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP21_Pos)               /* (CAN_TXBRP) Transmission Request Pending 21 Mask */
+#define CAN_TXBRP_TRP21(value)                (CAN_TXBRP_TRP21_Msk & (_UINT32_(value) << CAN_TXBRP_TRP21_Pos)) /* Assignment of value for TRP21 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP22_Pos                   _UINT32_(22)                                         /* (CAN_TXBRP) Transmission Request Pending 22 Position */
+#define CAN_TXBRP_TRP22_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP22_Pos)               /* (CAN_TXBRP) Transmission Request Pending 22 Mask */
+#define CAN_TXBRP_TRP22(value)                (CAN_TXBRP_TRP22_Msk & (_UINT32_(value) << CAN_TXBRP_TRP22_Pos)) /* Assignment of value for TRP22 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP23_Pos                   _UINT32_(23)                                         /* (CAN_TXBRP) Transmission Request Pending 23 Position */
+#define CAN_TXBRP_TRP23_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP23_Pos)               /* (CAN_TXBRP) Transmission Request Pending 23 Mask */
+#define CAN_TXBRP_TRP23(value)                (CAN_TXBRP_TRP23_Msk & (_UINT32_(value) << CAN_TXBRP_TRP23_Pos)) /* Assignment of value for TRP23 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP24_Pos                   _UINT32_(24)                                         /* (CAN_TXBRP) Transmission Request Pending 24 Position */
+#define CAN_TXBRP_TRP24_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP24_Pos)               /* (CAN_TXBRP) Transmission Request Pending 24 Mask */
+#define CAN_TXBRP_TRP24(value)                (CAN_TXBRP_TRP24_Msk & (_UINT32_(value) << CAN_TXBRP_TRP24_Pos)) /* Assignment of value for TRP24 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP25_Pos                   _UINT32_(25)                                         /* (CAN_TXBRP) Transmission Request Pending 25 Position */
+#define CAN_TXBRP_TRP25_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP25_Pos)               /* (CAN_TXBRP) Transmission Request Pending 25 Mask */
+#define CAN_TXBRP_TRP25(value)                (CAN_TXBRP_TRP25_Msk & (_UINT32_(value) << CAN_TXBRP_TRP25_Pos)) /* Assignment of value for TRP25 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP26_Pos                   _UINT32_(26)                                         /* (CAN_TXBRP) Transmission Request Pending 26 Position */
+#define CAN_TXBRP_TRP26_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP26_Pos)               /* (CAN_TXBRP) Transmission Request Pending 26 Mask */
+#define CAN_TXBRP_TRP26(value)                (CAN_TXBRP_TRP26_Msk & (_UINT32_(value) << CAN_TXBRP_TRP26_Pos)) /* Assignment of value for TRP26 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP27_Pos                   _UINT32_(27)                                         /* (CAN_TXBRP) Transmission Request Pending 27 Position */
+#define CAN_TXBRP_TRP27_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP27_Pos)               /* (CAN_TXBRP) Transmission Request Pending 27 Mask */
+#define CAN_TXBRP_TRP27(value)                (CAN_TXBRP_TRP27_Msk & (_UINT32_(value) << CAN_TXBRP_TRP27_Pos)) /* Assignment of value for TRP27 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP28_Pos                   _UINT32_(28)                                         /* (CAN_TXBRP) Transmission Request Pending 28 Position */
+#define CAN_TXBRP_TRP28_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP28_Pos)               /* (CAN_TXBRP) Transmission Request Pending 28 Mask */
+#define CAN_TXBRP_TRP28(value)                (CAN_TXBRP_TRP28_Msk & (_UINT32_(value) << CAN_TXBRP_TRP28_Pos)) /* Assignment of value for TRP28 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP29_Pos                   _UINT32_(29)                                         /* (CAN_TXBRP) Transmission Request Pending 29 Position */
+#define CAN_TXBRP_TRP29_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP29_Pos)               /* (CAN_TXBRP) Transmission Request Pending 29 Mask */
+#define CAN_TXBRP_TRP29(value)                (CAN_TXBRP_TRP29_Msk & (_UINT32_(value) << CAN_TXBRP_TRP29_Pos)) /* Assignment of value for TRP29 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP30_Pos                   _UINT32_(30)                                         /* (CAN_TXBRP) Transmission Request Pending 30 Position */
+#define CAN_TXBRP_TRP30_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP30_Pos)               /* (CAN_TXBRP) Transmission Request Pending 30 Mask */
+#define CAN_TXBRP_TRP30(value)                (CAN_TXBRP_TRP30_Msk & (_UINT32_(value) << CAN_TXBRP_TRP30_Pos)) /* Assignment of value for TRP30 in the CAN_TXBRP register */
+#define CAN_TXBRP_TRP31_Pos                   _UINT32_(31)                                         /* (CAN_TXBRP) Transmission Request Pending 31 Position */
+#define CAN_TXBRP_TRP31_Msk                   (_UINT32_(0x1) << CAN_TXBRP_TRP31_Pos)               /* (CAN_TXBRP) Transmission Request Pending 31 Mask */
+#define CAN_TXBRP_TRP31(value)                (CAN_TXBRP_TRP31_Msk & (_UINT32_(value) << CAN_TXBRP_TRP31_Pos)) /* Assignment of value for TRP31 in the CAN_TXBRP register */
+#define CAN_TXBRP_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (CAN_TXBRP) Register Mask  */
+
+#define CAN_TXBRP_TRP_Pos                     _UINT32_(0)                                          /* (CAN_TXBRP Position) Transmission Request Pending 3x */
+#define CAN_TXBRP_TRP_Msk                     (_UINT32_(0xFFFFFFFF) << CAN_TXBRP_TRP_Pos)          /* (CAN_TXBRP Mask) TRP */
+#define CAN_TXBRP_TRP(value)                  (CAN_TXBRP_TRP_Msk & (_UINT32_(value) << CAN_TXBRP_TRP_Pos)) 
+
+/* -------- CAN_TXBAR : (CAN Offset: 0x1D0) (R/W 32) Tx Buffer Add Request -------- */
+#define CAN_TXBAR_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TXBAR) Tx Buffer Add Request  Reset Value */
+
+#define CAN_TXBAR_AR0_Pos                     _UINT32_(0)                                          /* (CAN_TXBAR) Add Request 0 Position */
+#define CAN_TXBAR_AR0_Msk                     (_UINT32_(0x1) << CAN_TXBAR_AR0_Pos)                 /* (CAN_TXBAR) Add Request 0 Mask */
+#define CAN_TXBAR_AR0(value)                  (CAN_TXBAR_AR0_Msk & (_UINT32_(value) << CAN_TXBAR_AR0_Pos)) /* Assignment of value for AR0 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR1_Pos                     _UINT32_(1)                                          /* (CAN_TXBAR) Add Request 1 Position */
+#define CAN_TXBAR_AR1_Msk                     (_UINT32_(0x1) << CAN_TXBAR_AR1_Pos)                 /* (CAN_TXBAR) Add Request 1 Mask */
+#define CAN_TXBAR_AR1(value)                  (CAN_TXBAR_AR1_Msk & (_UINT32_(value) << CAN_TXBAR_AR1_Pos)) /* Assignment of value for AR1 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR2_Pos                     _UINT32_(2)                                          /* (CAN_TXBAR) Add Request 2 Position */
+#define CAN_TXBAR_AR2_Msk                     (_UINT32_(0x1) << CAN_TXBAR_AR2_Pos)                 /* (CAN_TXBAR) Add Request 2 Mask */
+#define CAN_TXBAR_AR2(value)                  (CAN_TXBAR_AR2_Msk & (_UINT32_(value) << CAN_TXBAR_AR2_Pos)) /* Assignment of value for AR2 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR3_Pos                     _UINT32_(3)                                          /* (CAN_TXBAR) Add Request 3 Position */
+#define CAN_TXBAR_AR3_Msk                     (_UINT32_(0x1) << CAN_TXBAR_AR3_Pos)                 /* (CAN_TXBAR) Add Request 3 Mask */
+#define CAN_TXBAR_AR3(value)                  (CAN_TXBAR_AR3_Msk & (_UINT32_(value) << CAN_TXBAR_AR3_Pos)) /* Assignment of value for AR3 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR4_Pos                     _UINT32_(4)                                          /* (CAN_TXBAR) Add Request 4 Position */
+#define CAN_TXBAR_AR4_Msk                     (_UINT32_(0x1) << CAN_TXBAR_AR4_Pos)                 /* (CAN_TXBAR) Add Request 4 Mask */
+#define CAN_TXBAR_AR4(value)                  (CAN_TXBAR_AR4_Msk & (_UINT32_(value) << CAN_TXBAR_AR4_Pos)) /* Assignment of value for AR4 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR5_Pos                     _UINT32_(5)                                          /* (CAN_TXBAR) Add Request 5 Position */
+#define CAN_TXBAR_AR5_Msk                     (_UINT32_(0x1) << CAN_TXBAR_AR5_Pos)                 /* (CAN_TXBAR) Add Request 5 Mask */
+#define CAN_TXBAR_AR5(value)                  (CAN_TXBAR_AR5_Msk & (_UINT32_(value) << CAN_TXBAR_AR5_Pos)) /* Assignment of value for AR5 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR6_Pos                     _UINT32_(6)                                          /* (CAN_TXBAR) Add Request 6 Position */
+#define CAN_TXBAR_AR6_Msk                     (_UINT32_(0x1) << CAN_TXBAR_AR6_Pos)                 /* (CAN_TXBAR) Add Request 6 Mask */
+#define CAN_TXBAR_AR6(value)                  (CAN_TXBAR_AR6_Msk & (_UINT32_(value) << CAN_TXBAR_AR6_Pos)) /* Assignment of value for AR6 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR7_Pos                     _UINT32_(7)                                          /* (CAN_TXBAR) Add Request 7 Position */
+#define CAN_TXBAR_AR7_Msk                     (_UINT32_(0x1) << CAN_TXBAR_AR7_Pos)                 /* (CAN_TXBAR) Add Request 7 Mask */
+#define CAN_TXBAR_AR7(value)                  (CAN_TXBAR_AR7_Msk & (_UINT32_(value) << CAN_TXBAR_AR7_Pos)) /* Assignment of value for AR7 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR8_Pos                     _UINT32_(8)                                          /* (CAN_TXBAR) Add Request 8 Position */
+#define CAN_TXBAR_AR8_Msk                     (_UINT32_(0x1) << CAN_TXBAR_AR8_Pos)                 /* (CAN_TXBAR) Add Request 8 Mask */
+#define CAN_TXBAR_AR8(value)                  (CAN_TXBAR_AR8_Msk & (_UINT32_(value) << CAN_TXBAR_AR8_Pos)) /* Assignment of value for AR8 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR9_Pos                     _UINT32_(9)                                          /* (CAN_TXBAR) Add Request 9 Position */
+#define CAN_TXBAR_AR9_Msk                     (_UINT32_(0x1) << CAN_TXBAR_AR9_Pos)                 /* (CAN_TXBAR) Add Request 9 Mask */
+#define CAN_TXBAR_AR9(value)                  (CAN_TXBAR_AR9_Msk & (_UINT32_(value) << CAN_TXBAR_AR9_Pos)) /* Assignment of value for AR9 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR10_Pos                    _UINT32_(10)                                         /* (CAN_TXBAR) Add Request 10 Position */
+#define CAN_TXBAR_AR10_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR10_Pos)                /* (CAN_TXBAR) Add Request 10 Mask */
+#define CAN_TXBAR_AR10(value)                 (CAN_TXBAR_AR10_Msk & (_UINT32_(value) << CAN_TXBAR_AR10_Pos)) /* Assignment of value for AR10 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR11_Pos                    _UINT32_(11)                                         /* (CAN_TXBAR) Add Request 11 Position */
+#define CAN_TXBAR_AR11_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR11_Pos)                /* (CAN_TXBAR) Add Request 11 Mask */
+#define CAN_TXBAR_AR11(value)                 (CAN_TXBAR_AR11_Msk & (_UINT32_(value) << CAN_TXBAR_AR11_Pos)) /* Assignment of value for AR11 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR12_Pos                    _UINT32_(12)                                         /* (CAN_TXBAR) Add Request 12 Position */
+#define CAN_TXBAR_AR12_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR12_Pos)                /* (CAN_TXBAR) Add Request 12 Mask */
+#define CAN_TXBAR_AR12(value)                 (CAN_TXBAR_AR12_Msk & (_UINT32_(value) << CAN_TXBAR_AR12_Pos)) /* Assignment of value for AR12 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR13_Pos                    _UINT32_(13)                                         /* (CAN_TXBAR) Add Request 13 Position */
+#define CAN_TXBAR_AR13_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR13_Pos)                /* (CAN_TXBAR) Add Request 13 Mask */
+#define CAN_TXBAR_AR13(value)                 (CAN_TXBAR_AR13_Msk & (_UINT32_(value) << CAN_TXBAR_AR13_Pos)) /* Assignment of value for AR13 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR14_Pos                    _UINT32_(14)                                         /* (CAN_TXBAR) Add Request 14 Position */
+#define CAN_TXBAR_AR14_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR14_Pos)                /* (CAN_TXBAR) Add Request 14 Mask */
+#define CAN_TXBAR_AR14(value)                 (CAN_TXBAR_AR14_Msk & (_UINT32_(value) << CAN_TXBAR_AR14_Pos)) /* Assignment of value for AR14 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR15_Pos                    _UINT32_(15)                                         /* (CAN_TXBAR) Add Request 15 Position */
+#define CAN_TXBAR_AR15_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR15_Pos)                /* (CAN_TXBAR) Add Request 15 Mask */
+#define CAN_TXBAR_AR15(value)                 (CAN_TXBAR_AR15_Msk & (_UINT32_(value) << CAN_TXBAR_AR15_Pos)) /* Assignment of value for AR15 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR16_Pos                    _UINT32_(16)                                         /* (CAN_TXBAR) Add Request 16 Position */
+#define CAN_TXBAR_AR16_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR16_Pos)                /* (CAN_TXBAR) Add Request 16 Mask */
+#define CAN_TXBAR_AR16(value)                 (CAN_TXBAR_AR16_Msk & (_UINT32_(value) << CAN_TXBAR_AR16_Pos)) /* Assignment of value for AR16 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR17_Pos                    _UINT32_(17)                                         /* (CAN_TXBAR) Add Request 17 Position */
+#define CAN_TXBAR_AR17_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR17_Pos)                /* (CAN_TXBAR) Add Request 17 Mask */
+#define CAN_TXBAR_AR17(value)                 (CAN_TXBAR_AR17_Msk & (_UINT32_(value) << CAN_TXBAR_AR17_Pos)) /* Assignment of value for AR17 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR18_Pos                    _UINT32_(18)                                         /* (CAN_TXBAR) Add Request 18 Position */
+#define CAN_TXBAR_AR18_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR18_Pos)                /* (CAN_TXBAR) Add Request 18 Mask */
+#define CAN_TXBAR_AR18(value)                 (CAN_TXBAR_AR18_Msk & (_UINT32_(value) << CAN_TXBAR_AR18_Pos)) /* Assignment of value for AR18 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR19_Pos                    _UINT32_(19)                                         /* (CAN_TXBAR) Add Request 19 Position */
+#define CAN_TXBAR_AR19_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR19_Pos)                /* (CAN_TXBAR) Add Request 19 Mask */
+#define CAN_TXBAR_AR19(value)                 (CAN_TXBAR_AR19_Msk & (_UINT32_(value) << CAN_TXBAR_AR19_Pos)) /* Assignment of value for AR19 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR20_Pos                    _UINT32_(20)                                         /* (CAN_TXBAR) Add Request 20 Position */
+#define CAN_TXBAR_AR20_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR20_Pos)                /* (CAN_TXBAR) Add Request 20 Mask */
+#define CAN_TXBAR_AR20(value)                 (CAN_TXBAR_AR20_Msk & (_UINT32_(value) << CAN_TXBAR_AR20_Pos)) /* Assignment of value for AR20 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR21_Pos                    _UINT32_(21)                                         /* (CAN_TXBAR) Add Request 21 Position */
+#define CAN_TXBAR_AR21_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR21_Pos)                /* (CAN_TXBAR) Add Request 21 Mask */
+#define CAN_TXBAR_AR21(value)                 (CAN_TXBAR_AR21_Msk & (_UINT32_(value) << CAN_TXBAR_AR21_Pos)) /* Assignment of value for AR21 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR22_Pos                    _UINT32_(22)                                         /* (CAN_TXBAR) Add Request 22 Position */
+#define CAN_TXBAR_AR22_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR22_Pos)                /* (CAN_TXBAR) Add Request 22 Mask */
+#define CAN_TXBAR_AR22(value)                 (CAN_TXBAR_AR22_Msk & (_UINT32_(value) << CAN_TXBAR_AR22_Pos)) /* Assignment of value for AR22 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR23_Pos                    _UINT32_(23)                                         /* (CAN_TXBAR) Add Request 23 Position */
+#define CAN_TXBAR_AR23_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR23_Pos)                /* (CAN_TXBAR) Add Request 23 Mask */
+#define CAN_TXBAR_AR23(value)                 (CAN_TXBAR_AR23_Msk & (_UINT32_(value) << CAN_TXBAR_AR23_Pos)) /* Assignment of value for AR23 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR24_Pos                    _UINT32_(24)                                         /* (CAN_TXBAR) Add Request 24 Position */
+#define CAN_TXBAR_AR24_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR24_Pos)                /* (CAN_TXBAR) Add Request 24 Mask */
+#define CAN_TXBAR_AR24(value)                 (CAN_TXBAR_AR24_Msk & (_UINT32_(value) << CAN_TXBAR_AR24_Pos)) /* Assignment of value for AR24 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR25_Pos                    _UINT32_(25)                                         /* (CAN_TXBAR) Add Request 25 Position */
+#define CAN_TXBAR_AR25_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR25_Pos)                /* (CAN_TXBAR) Add Request 25 Mask */
+#define CAN_TXBAR_AR25(value)                 (CAN_TXBAR_AR25_Msk & (_UINT32_(value) << CAN_TXBAR_AR25_Pos)) /* Assignment of value for AR25 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR26_Pos                    _UINT32_(26)                                         /* (CAN_TXBAR) Add Request 26 Position */
+#define CAN_TXBAR_AR26_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR26_Pos)                /* (CAN_TXBAR) Add Request 26 Mask */
+#define CAN_TXBAR_AR26(value)                 (CAN_TXBAR_AR26_Msk & (_UINT32_(value) << CAN_TXBAR_AR26_Pos)) /* Assignment of value for AR26 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR27_Pos                    _UINT32_(27)                                         /* (CAN_TXBAR) Add Request 27 Position */
+#define CAN_TXBAR_AR27_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR27_Pos)                /* (CAN_TXBAR) Add Request 27 Mask */
+#define CAN_TXBAR_AR27(value)                 (CAN_TXBAR_AR27_Msk & (_UINT32_(value) << CAN_TXBAR_AR27_Pos)) /* Assignment of value for AR27 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR28_Pos                    _UINT32_(28)                                         /* (CAN_TXBAR) Add Request 28 Position */
+#define CAN_TXBAR_AR28_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR28_Pos)                /* (CAN_TXBAR) Add Request 28 Mask */
+#define CAN_TXBAR_AR28(value)                 (CAN_TXBAR_AR28_Msk & (_UINT32_(value) << CAN_TXBAR_AR28_Pos)) /* Assignment of value for AR28 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR29_Pos                    _UINT32_(29)                                         /* (CAN_TXBAR) Add Request 29 Position */
+#define CAN_TXBAR_AR29_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR29_Pos)                /* (CAN_TXBAR) Add Request 29 Mask */
+#define CAN_TXBAR_AR29(value)                 (CAN_TXBAR_AR29_Msk & (_UINT32_(value) << CAN_TXBAR_AR29_Pos)) /* Assignment of value for AR29 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR30_Pos                    _UINT32_(30)                                         /* (CAN_TXBAR) Add Request 30 Position */
+#define CAN_TXBAR_AR30_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR30_Pos)                /* (CAN_TXBAR) Add Request 30 Mask */
+#define CAN_TXBAR_AR30(value)                 (CAN_TXBAR_AR30_Msk & (_UINT32_(value) << CAN_TXBAR_AR30_Pos)) /* Assignment of value for AR30 in the CAN_TXBAR register */
+#define CAN_TXBAR_AR31_Pos                    _UINT32_(31)                                         /* (CAN_TXBAR) Add Request 31 Position */
+#define CAN_TXBAR_AR31_Msk                    (_UINT32_(0x1) << CAN_TXBAR_AR31_Pos)                /* (CAN_TXBAR) Add Request 31 Mask */
+#define CAN_TXBAR_AR31(value)                 (CAN_TXBAR_AR31_Msk & (_UINT32_(value) << CAN_TXBAR_AR31_Pos)) /* Assignment of value for AR31 in the CAN_TXBAR register */
+#define CAN_TXBAR_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (CAN_TXBAR) Register Mask  */
+
+#define CAN_TXBAR_AR_Pos                      _UINT32_(0)                                          /* (CAN_TXBAR Position) Add Request 3x */
+#define CAN_TXBAR_AR_Msk                      (_UINT32_(0xFFFFFFFF) << CAN_TXBAR_AR_Pos)           /* (CAN_TXBAR Mask) AR */
+#define CAN_TXBAR_AR(value)                   (CAN_TXBAR_AR_Msk & (_UINT32_(value) << CAN_TXBAR_AR_Pos)) 
+
+/* -------- CAN_TXBCR : (CAN Offset: 0x1D4) (R/W 32) Tx Buffer Cancellation Request -------- */
+#define CAN_TXBCR_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TXBCR) Tx Buffer Cancellation Request  Reset Value */
+
+#define CAN_TXBCR_CR0_Pos                     _UINT32_(0)                                          /* (CAN_TXBCR) Cancellation Request 0 Position */
+#define CAN_TXBCR_CR0_Msk                     (_UINT32_(0x1) << CAN_TXBCR_CR0_Pos)                 /* (CAN_TXBCR) Cancellation Request 0 Mask */
+#define CAN_TXBCR_CR0(value)                  (CAN_TXBCR_CR0_Msk & (_UINT32_(value) << CAN_TXBCR_CR0_Pos)) /* Assignment of value for CR0 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR1_Pos                     _UINT32_(1)                                          /* (CAN_TXBCR) Cancellation Request 1 Position */
+#define CAN_TXBCR_CR1_Msk                     (_UINT32_(0x1) << CAN_TXBCR_CR1_Pos)                 /* (CAN_TXBCR) Cancellation Request 1 Mask */
+#define CAN_TXBCR_CR1(value)                  (CAN_TXBCR_CR1_Msk & (_UINT32_(value) << CAN_TXBCR_CR1_Pos)) /* Assignment of value for CR1 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR2_Pos                     _UINT32_(2)                                          /* (CAN_TXBCR) Cancellation Request 2 Position */
+#define CAN_TXBCR_CR2_Msk                     (_UINT32_(0x1) << CAN_TXBCR_CR2_Pos)                 /* (CAN_TXBCR) Cancellation Request 2 Mask */
+#define CAN_TXBCR_CR2(value)                  (CAN_TXBCR_CR2_Msk & (_UINT32_(value) << CAN_TXBCR_CR2_Pos)) /* Assignment of value for CR2 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR3_Pos                     _UINT32_(3)                                          /* (CAN_TXBCR) Cancellation Request 3 Position */
+#define CAN_TXBCR_CR3_Msk                     (_UINT32_(0x1) << CAN_TXBCR_CR3_Pos)                 /* (CAN_TXBCR) Cancellation Request 3 Mask */
+#define CAN_TXBCR_CR3(value)                  (CAN_TXBCR_CR3_Msk & (_UINT32_(value) << CAN_TXBCR_CR3_Pos)) /* Assignment of value for CR3 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR4_Pos                     _UINT32_(4)                                          /* (CAN_TXBCR) Cancellation Request 4 Position */
+#define CAN_TXBCR_CR4_Msk                     (_UINT32_(0x1) << CAN_TXBCR_CR4_Pos)                 /* (CAN_TXBCR) Cancellation Request 4 Mask */
+#define CAN_TXBCR_CR4(value)                  (CAN_TXBCR_CR4_Msk & (_UINT32_(value) << CAN_TXBCR_CR4_Pos)) /* Assignment of value for CR4 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR5_Pos                     _UINT32_(5)                                          /* (CAN_TXBCR) Cancellation Request 5 Position */
+#define CAN_TXBCR_CR5_Msk                     (_UINT32_(0x1) << CAN_TXBCR_CR5_Pos)                 /* (CAN_TXBCR) Cancellation Request 5 Mask */
+#define CAN_TXBCR_CR5(value)                  (CAN_TXBCR_CR5_Msk & (_UINT32_(value) << CAN_TXBCR_CR5_Pos)) /* Assignment of value for CR5 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR6_Pos                     _UINT32_(6)                                          /* (CAN_TXBCR) Cancellation Request 6 Position */
+#define CAN_TXBCR_CR6_Msk                     (_UINT32_(0x1) << CAN_TXBCR_CR6_Pos)                 /* (CAN_TXBCR) Cancellation Request 6 Mask */
+#define CAN_TXBCR_CR6(value)                  (CAN_TXBCR_CR6_Msk & (_UINT32_(value) << CAN_TXBCR_CR6_Pos)) /* Assignment of value for CR6 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR7_Pos                     _UINT32_(7)                                          /* (CAN_TXBCR) Cancellation Request 7 Position */
+#define CAN_TXBCR_CR7_Msk                     (_UINT32_(0x1) << CAN_TXBCR_CR7_Pos)                 /* (CAN_TXBCR) Cancellation Request 7 Mask */
+#define CAN_TXBCR_CR7(value)                  (CAN_TXBCR_CR7_Msk & (_UINT32_(value) << CAN_TXBCR_CR7_Pos)) /* Assignment of value for CR7 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR8_Pos                     _UINT32_(8)                                          /* (CAN_TXBCR) Cancellation Request 8 Position */
+#define CAN_TXBCR_CR8_Msk                     (_UINT32_(0x1) << CAN_TXBCR_CR8_Pos)                 /* (CAN_TXBCR) Cancellation Request 8 Mask */
+#define CAN_TXBCR_CR8(value)                  (CAN_TXBCR_CR8_Msk & (_UINT32_(value) << CAN_TXBCR_CR8_Pos)) /* Assignment of value for CR8 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR9_Pos                     _UINT32_(9)                                          /* (CAN_TXBCR) Cancellation Request 9 Position */
+#define CAN_TXBCR_CR9_Msk                     (_UINT32_(0x1) << CAN_TXBCR_CR9_Pos)                 /* (CAN_TXBCR) Cancellation Request 9 Mask */
+#define CAN_TXBCR_CR9(value)                  (CAN_TXBCR_CR9_Msk & (_UINT32_(value) << CAN_TXBCR_CR9_Pos)) /* Assignment of value for CR9 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR10_Pos                    _UINT32_(10)                                         /* (CAN_TXBCR) Cancellation Request 10 Position */
+#define CAN_TXBCR_CR10_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR10_Pos)                /* (CAN_TXBCR) Cancellation Request 10 Mask */
+#define CAN_TXBCR_CR10(value)                 (CAN_TXBCR_CR10_Msk & (_UINT32_(value) << CAN_TXBCR_CR10_Pos)) /* Assignment of value for CR10 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR11_Pos                    _UINT32_(11)                                         /* (CAN_TXBCR) Cancellation Request 11 Position */
+#define CAN_TXBCR_CR11_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR11_Pos)                /* (CAN_TXBCR) Cancellation Request 11 Mask */
+#define CAN_TXBCR_CR11(value)                 (CAN_TXBCR_CR11_Msk & (_UINT32_(value) << CAN_TXBCR_CR11_Pos)) /* Assignment of value for CR11 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR12_Pos                    _UINT32_(12)                                         /* (CAN_TXBCR) Cancellation Request 12 Position */
+#define CAN_TXBCR_CR12_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR12_Pos)                /* (CAN_TXBCR) Cancellation Request 12 Mask */
+#define CAN_TXBCR_CR12(value)                 (CAN_TXBCR_CR12_Msk & (_UINT32_(value) << CAN_TXBCR_CR12_Pos)) /* Assignment of value for CR12 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR13_Pos                    _UINT32_(13)                                         /* (CAN_TXBCR) Cancellation Request 13 Position */
+#define CAN_TXBCR_CR13_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR13_Pos)                /* (CAN_TXBCR) Cancellation Request 13 Mask */
+#define CAN_TXBCR_CR13(value)                 (CAN_TXBCR_CR13_Msk & (_UINT32_(value) << CAN_TXBCR_CR13_Pos)) /* Assignment of value for CR13 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR14_Pos                    _UINT32_(14)                                         /* (CAN_TXBCR) Cancellation Request 14 Position */
+#define CAN_TXBCR_CR14_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR14_Pos)                /* (CAN_TXBCR) Cancellation Request 14 Mask */
+#define CAN_TXBCR_CR14(value)                 (CAN_TXBCR_CR14_Msk & (_UINT32_(value) << CAN_TXBCR_CR14_Pos)) /* Assignment of value for CR14 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR15_Pos                    _UINT32_(15)                                         /* (CAN_TXBCR) Cancellation Request 15 Position */
+#define CAN_TXBCR_CR15_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR15_Pos)                /* (CAN_TXBCR) Cancellation Request 15 Mask */
+#define CAN_TXBCR_CR15(value)                 (CAN_TXBCR_CR15_Msk & (_UINT32_(value) << CAN_TXBCR_CR15_Pos)) /* Assignment of value for CR15 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR16_Pos                    _UINT32_(16)                                         /* (CAN_TXBCR) Cancellation Request 16 Position */
+#define CAN_TXBCR_CR16_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR16_Pos)                /* (CAN_TXBCR) Cancellation Request 16 Mask */
+#define CAN_TXBCR_CR16(value)                 (CAN_TXBCR_CR16_Msk & (_UINT32_(value) << CAN_TXBCR_CR16_Pos)) /* Assignment of value for CR16 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR17_Pos                    _UINT32_(17)                                         /* (CAN_TXBCR) Cancellation Request 17 Position */
+#define CAN_TXBCR_CR17_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR17_Pos)                /* (CAN_TXBCR) Cancellation Request 17 Mask */
+#define CAN_TXBCR_CR17(value)                 (CAN_TXBCR_CR17_Msk & (_UINT32_(value) << CAN_TXBCR_CR17_Pos)) /* Assignment of value for CR17 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR18_Pos                    _UINT32_(18)                                         /* (CAN_TXBCR) Cancellation Request 18 Position */
+#define CAN_TXBCR_CR18_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR18_Pos)                /* (CAN_TXBCR) Cancellation Request 18 Mask */
+#define CAN_TXBCR_CR18(value)                 (CAN_TXBCR_CR18_Msk & (_UINT32_(value) << CAN_TXBCR_CR18_Pos)) /* Assignment of value for CR18 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR19_Pos                    _UINT32_(19)                                         /* (CAN_TXBCR) Cancellation Request 19 Position */
+#define CAN_TXBCR_CR19_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR19_Pos)                /* (CAN_TXBCR) Cancellation Request 19 Mask */
+#define CAN_TXBCR_CR19(value)                 (CAN_TXBCR_CR19_Msk & (_UINT32_(value) << CAN_TXBCR_CR19_Pos)) /* Assignment of value for CR19 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR20_Pos                    _UINT32_(20)                                         /* (CAN_TXBCR) Cancellation Request 20 Position */
+#define CAN_TXBCR_CR20_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR20_Pos)                /* (CAN_TXBCR) Cancellation Request 20 Mask */
+#define CAN_TXBCR_CR20(value)                 (CAN_TXBCR_CR20_Msk & (_UINT32_(value) << CAN_TXBCR_CR20_Pos)) /* Assignment of value for CR20 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR21_Pos                    _UINT32_(21)                                         /* (CAN_TXBCR) Cancellation Request 21 Position */
+#define CAN_TXBCR_CR21_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR21_Pos)                /* (CAN_TXBCR) Cancellation Request 21 Mask */
+#define CAN_TXBCR_CR21(value)                 (CAN_TXBCR_CR21_Msk & (_UINT32_(value) << CAN_TXBCR_CR21_Pos)) /* Assignment of value for CR21 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR22_Pos                    _UINT32_(22)                                         /* (CAN_TXBCR) Cancellation Request 22 Position */
+#define CAN_TXBCR_CR22_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR22_Pos)                /* (CAN_TXBCR) Cancellation Request 22 Mask */
+#define CAN_TXBCR_CR22(value)                 (CAN_TXBCR_CR22_Msk & (_UINT32_(value) << CAN_TXBCR_CR22_Pos)) /* Assignment of value for CR22 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR23_Pos                    _UINT32_(23)                                         /* (CAN_TXBCR) Cancellation Request 23 Position */
+#define CAN_TXBCR_CR23_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR23_Pos)                /* (CAN_TXBCR) Cancellation Request 23 Mask */
+#define CAN_TXBCR_CR23(value)                 (CAN_TXBCR_CR23_Msk & (_UINT32_(value) << CAN_TXBCR_CR23_Pos)) /* Assignment of value for CR23 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR24_Pos                    _UINT32_(24)                                         /* (CAN_TXBCR) Cancellation Request 24 Position */
+#define CAN_TXBCR_CR24_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR24_Pos)                /* (CAN_TXBCR) Cancellation Request 24 Mask */
+#define CAN_TXBCR_CR24(value)                 (CAN_TXBCR_CR24_Msk & (_UINT32_(value) << CAN_TXBCR_CR24_Pos)) /* Assignment of value for CR24 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR25_Pos                    _UINT32_(25)                                         /* (CAN_TXBCR) Cancellation Request 25 Position */
+#define CAN_TXBCR_CR25_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR25_Pos)                /* (CAN_TXBCR) Cancellation Request 25 Mask */
+#define CAN_TXBCR_CR25(value)                 (CAN_TXBCR_CR25_Msk & (_UINT32_(value) << CAN_TXBCR_CR25_Pos)) /* Assignment of value for CR25 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR26_Pos                    _UINT32_(26)                                         /* (CAN_TXBCR) Cancellation Request 26 Position */
+#define CAN_TXBCR_CR26_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR26_Pos)                /* (CAN_TXBCR) Cancellation Request 26 Mask */
+#define CAN_TXBCR_CR26(value)                 (CAN_TXBCR_CR26_Msk & (_UINT32_(value) << CAN_TXBCR_CR26_Pos)) /* Assignment of value for CR26 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR27_Pos                    _UINT32_(27)                                         /* (CAN_TXBCR) Cancellation Request 27 Position */
+#define CAN_TXBCR_CR27_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR27_Pos)                /* (CAN_TXBCR) Cancellation Request 27 Mask */
+#define CAN_TXBCR_CR27(value)                 (CAN_TXBCR_CR27_Msk & (_UINT32_(value) << CAN_TXBCR_CR27_Pos)) /* Assignment of value for CR27 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR28_Pos                    _UINT32_(28)                                         /* (CAN_TXBCR) Cancellation Request 28 Position */
+#define CAN_TXBCR_CR28_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR28_Pos)                /* (CAN_TXBCR) Cancellation Request 28 Mask */
+#define CAN_TXBCR_CR28(value)                 (CAN_TXBCR_CR28_Msk & (_UINT32_(value) << CAN_TXBCR_CR28_Pos)) /* Assignment of value for CR28 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR29_Pos                    _UINT32_(29)                                         /* (CAN_TXBCR) Cancellation Request 29 Position */
+#define CAN_TXBCR_CR29_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR29_Pos)                /* (CAN_TXBCR) Cancellation Request 29 Mask */
+#define CAN_TXBCR_CR29(value)                 (CAN_TXBCR_CR29_Msk & (_UINT32_(value) << CAN_TXBCR_CR29_Pos)) /* Assignment of value for CR29 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR30_Pos                    _UINT32_(30)                                         /* (CAN_TXBCR) Cancellation Request 30 Position */
+#define CAN_TXBCR_CR30_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR30_Pos)                /* (CAN_TXBCR) Cancellation Request 30 Mask */
+#define CAN_TXBCR_CR30(value)                 (CAN_TXBCR_CR30_Msk & (_UINT32_(value) << CAN_TXBCR_CR30_Pos)) /* Assignment of value for CR30 in the CAN_TXBCR register */
+#define CAN_TXBCR_CR31_Pos                    _UINT32_(31)                                         /* (CAN_TXBCR) Cancellation Request 31 Position */
+#define CAN_TXBCR_CR31_Msk                    (_UINT32_(0x1) << CAN_TXBCR_CR31_Pos)                /* (CAN_TXBCR) Cancellation Request 31 Mask */
+#define CAN_TXBCR_CR31(value)                 (CAN_TXBCR_CR31_Msk & (_UINT32_(value) << CAN_TXBCR_CR31_Pos)) /* Assignment of value for CR31 in the CAN_TXBCR register */
+#define CAN_TXBCR_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (CAN_TXBCR) Register Mask  */
+
+#define CAN_TXBCR_CR_Pos                      _UINT32_(0)                                          /* (CAN_TXBCR Position) Cancellation Request 3x */
+#define CAN_TXBCR_CR_Msk                      (_UINT32_(0xFFFFFFFF) << CAN_TXBCR_CR_Pos)           /* (CAN_TXBCR Mask) CR */
+#define CAN_TXBCR_CR(value)                   (CAN_TXBCR_CR_Msk & (_UINT32_(value) << CAN_TXBCR_CR_Pos)) 
+
+/* -------- CAN_TXBTO : (CAN Offset: 0x1D8) ( R/ 32) Tx Buffer Transmission Occurred -------- */
+#define CAN_TXBTO_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TXBTO) Tx Buffer Transmission Occurred  Reset Value */
+
+#define CAN_TXBTO_TO0_Pos                     _UINT32_(0)                                          /* (CAN_TXBTO) Transmission Occurred 0 Position */
+#define CAN_TXBTO_TO0_Msk                     (_UINT32_(0x1) << CAN_TXBTO_TO0_Pos)                 /* (CAN_TXBTO) Transmission Occurred 0 Mask */
+#define CAN_TXBTO_TO0(value)                  (CAN_TXBTO_TO0_Msk & (_UINT32_(value) << CAN_TXBTO_TO0_Pos)) /* Assignment of value for TO0 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO1_Pos                     _UINT32_(1)                                          /* (CAN_TXBTO) Transmission Occurred 1 Position */
+#define CAN_TXBTO_TO1_Msk                     (_UINT32_(0x1) << CAN_TXBTO_TO1_Pos)                 /* (CAN_TXBTO) Transmission Occurred 1 Mask */
+#define CAN_TXBTO_TO1(value)                  (CAN_TXBTO_TO1_Msk & (_UINT32_(value) << CAN_TXBTO_TO1_Pos)) /* Assignment of value for TO1 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO2_Pos                     _UINT32_(2)                                          /* (CAN_TXBTO) Transmission Occurred 2 Position */
+#define CAN_TXBTO_TO2_Msk                     (_UINT32_(0x1) << CAN_TXBTO_TO2_Pos)                 /* (CAN_TXBTO) Transmission Occurred 2 Mask */
+#define CAN_TXBTO_TO2(value)                  (CAN_TXBTO_TO2_Msk & (_UINT32_(value) << CAN_TXBTO_TO2_Pos)) /* Assignment of value for TO2 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO3_Pos                     _UINT32_(3)                                          /* (CAN_TXBTO) Transmission Occurred 3 Position */
+#define CAN_TXBTO_TO3_Msk                     (_UINT32_(0x1) << CAN_TXBTO_TO3_Pos)                 /* (CAN_TXBTO) Transmission Occurred 3 Mask */
+#define CAN_TXBTO_TO3(value)                  (CAN_TXBTO_TO3_Msk & (_UINT32_(value) << CAN_TXBTO_TO3_Pos)) /* Assignment of value for TO3 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO4_Pos                     _UINT32_(4)                                          /* (CAN_TXBTO) Transmission Occurred 4 Position */
+#define CAN_TXBTO_TO4_Msk                     (_UINT32_(0x1) << CAN_TXBTO_TO4_Pos)                 /* (CAN_TXBTO) Transmission Occurred 4 Mask */
+#define CAN_TXBTO_TO4(value)                  (CAN_TXBTO_TO4_Msk & (_UINT32_(value) << CAN_TXBTO_TO4_Pos)) /* Assignment of value for TO4 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO5_Pos                     _UINT32_(5)                                          /* (CAN_TXBTO) Transmission Occurred 5 Position */
+#define CAN_TXBTO_TO5_Msk                     (_UINT32_(0x1) << CAN_TXBTO_TO5_Pos)                 /* (CAN_TXBTO) Transmission Occurred 5 Mask */
+#define CAN_TXBTO_TO5(value)                  (CAN_TXBTO_TO5_Msk & (_UINT32_(value) << CAN_TXBTO_TO5_Pos)) /* Assignment of value for TO5 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO6_Pos                     _UINT32_(6)                                          /* (CAN_TXBTO) Transmission Occurred 6 Position */
+#define CAN_TXBTO_TO6_Msk                     (_UINT32_(0x1) << CAN_TXBTO_TO6_Pos)                 /* (CAN_TXBTO) Transmission Occurred 6 Mask */
+#define CAN_TXBTO_TO6(value)                  (CAN_TXBTO_TO6_Msk & (_UINT32_(value) << CAN_TXBTO_TO6_Pos)) /* Assignment of value for TO6 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO7_Pos                     _UINT32_(7)                                          /* (CAN_TXBTO) Transmission Occurred 7 Position */
+#define CAN_TXBTO_TO7_Msk                     (_UINT32_(0x1) << CAN_TXBTO_TO7_Pos)                 /* (CAN_TXBTO) Transmission Occurred 7 Mask */
+#define CAN_TXBTO_TO7(value)                  (CAN_TXBTO_TO7_Msk & (_UINT32_(value) << CAN_TXBTO_TO7_Pos)) /* Assignment of value for TO7 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO8_Pos                     _UINT32_(8)                                          /* (CAN_TXBTO) Transmission Occurred 8 Position */
+#define CAN_TXBTO_TO8_Msk                     (_UINT32_(0x1) << CAN_TXBTO_TO8_Pos)                 /* (CAN_TXBTO) Transmission Occurred 8 Mask */
+#define CAN_TXBTO_TO8(value)                  (CAN_TXBTO_TO8_Msk & (_UINT32_(value) << CAN_TXBTO_TO8_Pos)) /* Assignment of value for TO8 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO9_Pos                     _UINT32_(9)                                          /* (CAN_TXBTO) Transmission Occurred 9 Position */
+#define CAN_TXBTO_TO9_Msk                     (_UINT32_(0x1) << CAN_TXBTO_TO9_Pos)                 /* (CAN_TXBTO) Transmission Occurred 9 Mask */
+#define CAN_TXBTO_TO9(value)                  (CAN_TXBTO_TO9_Msk & (_UINT32_(value) << CAN_TXBTO_TO9_Pos)) /* Assignment of value for TO9 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO10_Pos                    _UINT32_(10)                                         /* (CAN_TXBTO) Transmission Occurred 10 Position */
+#define CAN_TXBTO_TO10_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO10_Pos)                /* (CAN_TXBTO) Transmission Occurred 10 Mask */
+#define CAN_TXBTO_TO10(value)                 (CAN_TXBTO_TO10_Msk & (_UINT32_(value) << CAN_TXBTO_TO10_Pos)) /* Assignment of value for TO10 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO11_Pos                    _UINT32_(11)                                         /* (CAN_TXBTO) Transmission Occurred 11 Position */
+#define CAN_TXBTO_TO11_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO11_Pos)                /* (CAN_TXBTO) Transmission Occurred 11 Mask */
+#define CAN_TXBTO_TO11(value)                 (CAN_TXBTO_TO11_Msk & (_UINT32_(value) << CAN_TXBTO_TO11_Pos)) /* Assignment of value for TO11 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO12_Pos                    _UINT32_(12)                                         /* (CAN_TXBTO) Transmission Occurred 12 Position */
+#define CAN_TXBTO_TO12_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO12_Pos)                /* (CAN_TXBTO) Transmission Occurred 12 Mask */
+#define CAN_TXBTO_TO12(value)                 (CAN_TXBTO_TO12_Msk & (_UINT32_(value) << CAN_TXBTO_TO12_Pos)) /* Assignment of value for TO12 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO13_Pos                    _UINT32_(13)                                         /* (CAN_TXBTO) Transmission Occurred 13 Position */
+#define CAN_TXBTO_TO13_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO13_Pos)                /* (CAN_TXBTO) Transmission Occurred 13 Mask */
+#define CAN_TXBTO_TO13(value)                 (CAN_TXBTO_TO13_Msk & (_UINT32_(value) << CAN_TXBTO_TO13_Pos)) /* Assignment of value for TO13 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO14_Pos                    _UINT32_(14)                                         /* (CAN_TXBTO) Transmission Occurred 14 Position */
+#define CAN_TXBTO_TO14_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO14_Pos)                /* (CAN_TXBTO) Transmission Occurred 14 Mask */
+#define CAN_TXBTO_TO14(value)                 (CAN_TXBTO_TO14_Msk & (_UINT32_(value) << CAN_TXBTO_TO14_Pos)) /* Assignment of value for TO14 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO15_Pos                    _UINT32_(15)                                         /* (CAN_TXBTO) Transmission Occurred 15 Position */
+#define CAN_TXBTO_TO15_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO15_Pos)                /* (CAN_TXBTO) Transmission Occurred 15 Mask */
+#define CAN_TXBTO_TO15(value)                 (CAN_TXBTO_TO15_Msk & (_UINT32_(value) << CAN_TXBTO_TO15_Pos)) /* Assignment of value for TO15 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO16_Pos                    _UINT32_(16)                                         /* (CAN_TXBTO) Transmission Occurred 16 Position */
+#define CAN_TXBTO_TO16_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO16_Pos)                /* (CAN_TXBTO) Transmission Occurred 16 Mask */
+#define CAN_TXBTO_TO16(value)                 (CAN_TXBTO_TO16_Msk & (_UINT32_(value) << CAN_TXBTO_TO16_Pos)) /* Assignment of value for TO16 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO17_Pos                    _UINT32_(17)                                         /* (CAN_TXBTO) Transmission Occurred 17 Position */
+#define CAN_TXBTO_TO17_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO17_Pos)                /* (CAN_TXBTO) Transmission Occurred 17 Mask */
+#define CAN_TXBTO_TO17(value)                 (CAN_TXBTO_TO17_Msk & (_UINT32_(value) << CAN_TXBTO_TO17_Pos)) /* Assignment of value for TO17 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO18_Pos                    _UINT32_(18)                                         /* (CAN_TXBTO) Transmission Occurred 18 Position */
+#define CAN_TXBTO_TO18_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO18_Pos)                /* (CAN_TXBTO) Transmission Occurred 18 Mask */
+#define CAN_TXBTO_TO18(value)                 (CAN_TXBTO_TO18_Msk & (_UINT32_(value) << CAN_TXBTO_TO18_Pos)) /* Assignment of value for TO18 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO19_Pos                    _UINT32_(19)                                         /* (CAN_TXBTO) Transmission Occurred 19 Position */
+#define CAN_TXBTO_TO19_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO19_Pos)                /* (CAN_TXBTO) Transmission Occurred 19 Mask */
+#define CAN_TXBTO_TO19(value)                 (CAN_TXBTO_TO19_Msk & (_UINT32_(value) << CAN_TXBTO_TO19_Pos)) /* Assignment of value for TO19 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO20_Pos                    _UINT32_(20)                                         /* (CAN_TXBTO) Transmission Occurred 20 Position */
+#define CAN_TXBTO_TO20_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO20_Pos)                /* (CAN_TXBTO) Transmission Occurred 20 Mask */
+#define CAN_TXBTO_TO20(value)                 (CAN_TXBTO_TO20_Msk & (_UINT32_(value) << CAN_TXBTO_TO20_Pos)) /* Assignment of value for TO20 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO21_Pos                    _UINT32_(21)                                         /* (CAN_TXBTO) Transmission Occurred 21 Position */
+#define CAN_TXBTO_TO21_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO21_Pos)                /* (CAN_TXBTO) Transmission Occurred 21 Mask */
+#define CAN_TXBTO_TO21(value)                 (CAN_TXBTO_TO21_Msk & (_UINT32_(value) << CAN_TXBTO_TO21_Pos)) /* Assignment of value for TO21 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO22_Pos                    _UINT32_(22)                                         /* (CAN_TXBTO) Transmission Occurred 22 Position */
+#define CAN_TXBTO_TO22_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO22_Pos)                /* (CAN_TXBTO) Transmission Occurred 22 Mask */
+#define CAN_TXBTO_TO22(value)                 (CAN_TXBTO_TO22_Msk & (_UINT32_(value) << CAN_TXBTO_TO22_Pos)) /* Assignment of value for TO22 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO23_Pos                    _UINT32_(23)                                         /* (CAN_TXBTO) Transmission Occurred 23 Position */
+#define CAN_TXBTO_TO23_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO23_Pos)                /* (CAN_TXBTO) Transmission Occurred 23 Mask */
+#define CAN_TXBTO_TO23(value)                 (CAN_TXBTO_TO23_Msk & (_UINT32_(value) << CAN_TXBTO_TO23_Pos)) /* Assignment of value for TO23 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO24_Pos                    _UINT32_(24)                                         /* (CAN_TXBTO) Transmission Occurred 24 Position */
+#define CAN_TXBTO_TO24_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO24_Pos)                /* (CAN_TXBTO) Transmission Occurred 24 Mask */
+#define CAN_TXBTO_TO24(value)                 (CAN_TXBTO_TO24_Msk & (_UINT32_(value) << CAN_TXBTO_TO24_Pos)) /* Assignment of value for TO24 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO25_Pos                    _UINT32_(25)                                         /* (CAN_TXBTO) Transmission Occurred 25 Position */
+#define CAN_TXBTO_TO25_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO25_Pos)                /* (CAN_TXBTO) Transmission Occurred 25 Mask */
+#define CAN_TXBTO_TO25(value)                 (CAN_TXBTO_TO25_Msk & (_UINT32_(value) << CAN_TXBTO_TO25_Pos)) /* Assignment of value for TO25 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO26_Pos                    _UINT32_(26)                                         /* (CAN_TXBTO) Transmission Occurred 26 Position */
+#define CAN_TXBTO_TO26_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO26_Pos)                /* (CAN_TXBTO) Transmission Occurred 26 Mask */
+#define CAN_TXBTO_TO26(value)                 (CAN_TXBTO_TO26_Msk & (_UINT32_(value) << CAN_TXBTO_TO26_Pos)) /* Assignment of value for TO26 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO27_Pos                    _UINT32_(27)                                         /* (CAN_TXBTO) Transmission Occurred 27 Position */
+#define CAN_TXBTO_TO27_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO27_Pos)                /* (CAN_TXBTO) Transmission Occurred 27 Mask */
+#define CAN_TXBTO_TO27(value)                 (CAN_TXBTO_TO27_Msk & (_UINT32_(value) << CAN_TXBTO_TO27_Pos)) /* Assignment of value for TO27 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO28_Pos                    _UINT32_(28)                                         /* (CAN_TXBTO) Transmission Occurred 28 Position */
+#define CAN_TXBTO_TO28_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO28_Pos)                /* (CAN_TXBTO) Transmission Occurred 28 Mask */
+#define CAN_TXBTO_TO28(value)                 (CAN_TXBTO_TO28_Msk & (_UINT32_(value) << CAN_TXBTO_TO28_Pos)) /* Assignment of value for TO28 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO29_Pos                    _UINT32_(29)                                         /* (CAN_TXBTO) Transmission Occurred 29 Position */
+#define CAN_TXBTO_TO29_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO29_Pos)                /* (CAN_TXBTO) Transmission Occurred 29 Mask */
+#define CAN_TXBTO_TO29(value)                 (CAN_TXBTO_TO29_Msk & (_UINT32_(value) << CAN_TXBTO_TO29_Pos)) /* Assignment of value for TO29 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO30_Pos                    _UINT32_(30)                                         /* (CAN_TXBTO) Transmission Occurred 30 Position */
+#define CAN_TXBTO_TO30_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO30_Pos)                /* (CAN_TXBTO) Transmission Occurred 30 Mask */
+#define CAN_TXBTO_TO30(value)                 (CAN_TXBTO_TO30_Msk & (_UINT32_(value) << CAN_TXBTO_TO30_Pos)) /* Assignment of value for TO30 in the CAN_TXBTO register */
+#define CAN_TXBTO_TO31_Pos                    _UINT32_(31)                                         /* (CAN_TXBTO) Transmission Occurred 31 Position */
+#define CAN_TXBTO_TO31_Msk                    (_UINT32_(0x1) << CAN_TXBTO_TO31_Pos)                /* (CAN_TXBTO) Transmission Occurred 31 Mask */
+#define CAN_TXBTO_TO31(value)                 (CAN_TXBTO_TO31_Msk & (_UINT32_(value) << CAN_TXBTO_TO31_Pos)) /* Assignment of value for TO31 in the CAN_TXBTO register */
+#define CAN_TXBTO_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (CAN_TXBTO) Register Mask  */
+
+#define CAN_TXBTO_TO_Pos                      _UINT32_(0)                                          /* (CAN_TXBTO Position) Transmission Occurred 3x */
+#define CAN_TXBTO_TO_Msk                      (_UINT32_(0xFFFFFFFF) << CAN_TXBTO_TO_Pos)           /* (CAN_TXBTO Mask) TO */
+#define CAN_TXBTO_TO(value)                   (CAN_TXBTO_TO_Msk & (_UINT32_(value) << CAN_TXBTO_TO_Pos)) 
+
+/* -------- CAN_TXBCF : (CAN Offset: 0x1DC) ( R/ 32) Tx Buffer Cancellation Finished -------- */
+#define CAN_TXBCF_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TXBCF) Tx Buffer Cancellation Finished  Reset Value */
+
+#define CAN_TXBCF_CF0_Pos                     _UINT32_(0)                                          /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Position */
+#define CAN_TXBCF_CF0_Msk                     (_UINT32_(0x1) << CAN_TXBCF_CF0_Pos)                 /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Mask */
+#define CAN_TXBCF_CF0(value)                  (CAN_TXBCF_CF0_Msk & (_UINT32_(value) << CAN_TXBCF_CF0_Pos)) /* Assignment of value for CF0 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF1_Pos                     _UINT32_(1)                                          /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Position */
+#define CAN_TXBCF_CF1_Msk                     (_UINT32_(0x1) << CAN_TXBCF_CF1_Pos)                 /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Mask */
+#define CAN_TXBCF_CF1(value)                  (CAN_TXBCF_CF1_Msk & (_UINT32_(value) << CAN_TXBCF_CF1_Pos)) /* Assignment of value for CF1 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF2_Pos                     _UINT32_(2)                                          /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Position */
+#define CAN_TXBCF_CF2_Msk                     (_UINT32_(0x1) << CAN_TXBCF_CF2_Pos)                 /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Mask */
+#define CAN_TXBCF_CF2(value)                  (CAN_TXBCF_CF2_Msk & (_UINT32_(value) << CAN_TXBCF_CF2_Pos)) /* Assignment of value for CF2 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF3_Pos                     _UINT32_(3)                                          /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Position */
+#define CAN_TXBCF_CF3_Msk                     (_UINT32_(0x1) << CAN_TXBCF_CF3_Pos)                 /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Mask */
+#define CAN_TXBCF_CF3(value)                  (CAN_TXBCF_CF3_Msk & (_UINT32_(value) << CAN_TXBCF_CF3_Pos)) /* Assignment of value for CF3 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF4_Pos                     _UINT32_(4)                                          /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Position */
+#define CAN_TXBCF_CF4_Msk                     (_UINT32_(0x1) << CAN_TXBCF_CF4_Pos)                 /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Mask */
+#define CAN_TXBCF_CF4(value)                  (CAN_TXBCF_CF4_Msk & (_UINT32_(value) << CAN_TXBCF_CF4_Pos)) /* Assignment of value for CF4 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF5_Pos                     _UINT32_(5)                                          /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Position */
+#define CAN_TXBCF_CF5_Msk                     (_UINT32_(0x1) << CAN_TXBCF_CF5_Pos)                 /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Mask */
+#define CAN_TXBCF_CF5(value)                  (CAN_TXBCF_CF5_Msk & (_UINT32_(value) << CAN_TXBCF_CF5_Pos)) /* Assignment of value for CF5 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF6_Pos                     _UINT32_(6)                                          /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Position */
+#define CAN_TXBCF_CF6_Msk                     (_UINT32_(0x1) << CAN_TXBCF_CF6_Pos)                 /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Mask */
+#define CAN_TXBCF_CF6(value)                  (CAN_TXBCF_CF6_Msk & (_UINT32_(value) << CAN_TXBCF_CF6_Pos)) /* Assignment of value for CF6 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF7_Pos                     _UINT32_(7)                                          /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Position */
+#define CAN_TXBCF_CF7_Msk                     (_UINT32_(0x1) << CAN_TXBCF_CF7_Pos)                 /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Mask */
+#define CAN_TXBCF_CF7(value)                  (CAN_TXBCF_CF7_Msk & (_UINT32_(value) << CAN_TXBCF_CF7_Pos)) /* Assignment of value for CF7 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF8_Pos                     _UINT32_(8)                                          /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Position */
+#define CAN_TXBCF_CF8_Msk                     (_UINT32_(0x1) << CAN_TXBCF_CF8_Pos)                 /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Mask */
+#define CAN_TXBCF_CF8(value)                  (CAN_TXBCF_CF8_Msk & (_UINT32_(value) << CAN_TXBCF_CF8_Pos)) /* Assignment of value for CF8 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF9_Pos                     _UINT32_(9)                                          /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Position */
+#define CAN_TXBCF_CF9_Msk                     (_UINT32_(0x1) << CAN_TXBCF_CF9_Pos)                 /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Mask */
+#define CAN_TXBCF_CF9(value)                  (CAN_TXBCF_CF9_Msk & (_UINT32_(value) << CAN_TXBCF_CF9_Pos)) /* Assignment of value for CF9 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF10_Pos                    _UINT32_(10)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Position */
+#define CAN_TXBCF_CF10_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF10_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Mask */
+#define CAN_TXBCF_CF10(value)                 (CAN_TXBCF_CF10_Msk & (_UINT32_(value) << CAN_TXBCF_CF10_Pos)) /* Assignment of value for CF10 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF11_Pos                    _UINT32_(11)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Position */
+#define CAN_TXBCF_CF11_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF11_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Mask */
+#define CAN_TXBCF_CF11(value)                 (CAN_TXBCF_CF11_Msk & (_UINT32_(value) << CAN_TXBCF_CF11_Pos)) /* Assignment of value for CF11 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF12_Pos                    _UINT32_(12)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Position */
+#define CAN_TXBCF_CF12_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF12_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Mask */
+#define CAN_TXBCF_CF12(value)                 (CAN_TXBCF_CF12_Msk & (_UINT32_(value) << CAN_TXBCF_CF12_Pos)) /* Assignment of value for CF12 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF13_Pos                    _UINT32_(13)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Position */
+#define CAN_TXBCF_CF13_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF13_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Mask */
+#define CAN_TXBCF_CF13(value)                 (CAN_TXBCF_CF13_Msk & (_UINT32_(value) << CAN_TXBCF_CF13_Pos)) /* Assignment of value for CF13 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF14_Pos                    _UINT32_(14)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Position */
+#define CAN_TXBCF_CF14_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF14_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Mask */
+#define CAN_TXBCF_CF14(value)                 (CAN_TXBCF_CF14_Msk & (_UINT32_(value) << CAN_TXBCF_CF14_Pos)) /* Assignment of value for CF14 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF15_Pos                    _UINT32_(15)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Position */
+#define CAN_TXBCF_CF15_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF15_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Mask */
+#define CAN_TXBCF_CF15(value)                 (CAN_TXBCF_CF15_Msk & (_UINT32_(value) << CAN_TXBCF_CF15_Pos)) /* Assignment of value for CF15 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF16_Pos                    _UINT32_(16)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Position */
+#define CAN_TXBCF_CF16_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF16_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Mask */
+#define CAN_TXBCF_CF16(value)                 (CAN_TXBCF_CF16_Msk & (_UINT32_(value) << CAN_TXBCF_CF16_Pos)) /* Assignment of value for CF16 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF17_Pos                    _UINT32_(17)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Position */
+#define CAN_TXBCF_CF17_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF17_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Mask */
+#define CAN_TXBCF_CF17(value)                 (CAN_TXBCF_CF17_Msk & (_UINT32_(value) << CAN_TXBCF_CF17_Pos)) /* Assignment of value for CF17 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF18_Pos                    _UINT32_(18)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Position */
+#define CAN_TXBCF_CF18_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF18_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Mask */
+#define CAN_TXBCF_CF18(value)                 (CAN_TXBCF_CF18_Msk & (_UINT32_(value) << CAN_TXBCF_CF18_Pos)) /* Assignment of value for CF18 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF19_Pos                    _UINT32_(19)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Position */
+#define CAN_TXBCF_CF19_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF19_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Mask */
+#define CAN_TXBCF_CF19(value)                 (CAN_TXBCF_CF19_Msk & (_UINT32_(value) << CAN_TXBCF_CF19_Pos)) /* Assignment of value for CF19 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF20_Pos                    _UINT32_(20)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Position */
+#define CAN_TXBCF_CF20_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF20_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Mask */
+#define CAN_TXBCF_CF20(value)                 (CAN_TXBCF_CF20_Msk & (_UINT32_(value) << CAN_TXBCF_CF20_Pos)) /* Assignment of value for CF20 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF21_Pos                    _UINT32_(21)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Position */
+#define CAN_TXBCF_CF21_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF21_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Mask */
+#define CAN_TXBCF_CF21(value)                 (CAN_TXBCF_CF21_Msk & (_UINT32_(value) << CAN_TXBCF_CF21_Pos)) /* Assignment of value for CF21 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF22_Pos                    _UINT32_(22)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Position */
+#define CAN_TXBCF_CF22_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF22_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Mask */
+#define CAN_TXBCF_CF22(value)                 (CAN_TXBCF_CF22_Msk & (_UINT32_(value) << CAN_TXBCF_CF22_Pos)) /* Assignment of value for CF22 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF23_Pos                    _UINT32_(23)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Position */
+#define CAN_TXBCF_CF23_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF23_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Mask */
+#define CAN_TXBCF_CF23(value)                 (CAN_TXBCF_CF23_Msk & (_UINT32_(value) << CAN_TXBCF_CF23_Pos)) /* Assignment of value for CF23 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF24_Pos                    _UINT32_(24)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Position */
+#define CAN_TXBCF_CF24_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF24_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Mask */
+#define CAN_TXBCF_CF24(value)                 (CAN_TXBCF_CF24_Msk & (_UINT32_(value) << CAN_TXBCF_CF24_Pos)) /* Assignment of value for CF24 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF25_Pos                    _UINT32_(25)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Position */
+#define CAN_TXBCF_CF25_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF25_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Mask */
+#define CAN_TXBCF_CF25(value)                 (CAN_TXBCF_CF25_Msk & (_UINT32_(value) << CAN_TXBCF_CF25_Pos)) /* Assignment of value for CF25 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF26_Pos                    _UINT32_(26)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Position */
+#define CAN_TXBCF_CF26_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF26_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Mask */
+#define CAN_TXBCF_CF26(value)                 (CAN_TXBCF_CF26_Msk & (_UINT32_(value) << CAN_TXBCF_CF26_Pos)) /* Assignment of value for CF26 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF27_Pos                    _UINT32_(27)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Position */
+#define CAN_TXBCF_CF27_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF27_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Mask */
+#define CAN_TXBCF_CF27(value)                 (CAN_TXBCF_CF27_Msk & (_UINT32_(value) << CAN_TXBCF_CF27_Pos)) /* Assignment of value for CF27 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF28_Pos                    _UINT32_(28)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Position */
+#define CAN_TXBCF_CF28_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF28_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Mask */
+#define CAN_TXBCF_CF28(value)                 (CAN_TXBCF_CF28_Msk & (_UINT32_(value) << CAN_TXBCF_CF28_Pos)) /* Assignment of value for CF28 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF29_Pos                    _UINT32_(29)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Position */
+#define CAN_TXBCF_CF29_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF29_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Mask */
+#define CAN_TXBCF_CF29(value)                 (CAN_TXBCF_CF29_Msk & (_UINT32_(value) << CAN_TXBCF_CF29_Pos)) /* Assignment of value for CF29 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF30_Pos                    _UINT32_(30)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Position */
+#define CAN_TXBCF_CF30_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF30_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Mask */
+#define CAN_TXBCF_CF30(value)                 (CAN_TXBCF_CF30_Msk & (_UINT32_(value) << CAN_TXBCF_CF30_Pos)) /* Assignment of value for CF30 in the CAN_TXBCF register */
+#define CAN_TXBCF_CF31_Pos                    _UINT32_(31)                                         /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Position */
+#define CAN_TXBCF_CF31_Msk                    (_UINT32_(0x1) << CAN_TXBCF_CF31_Pos)                /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Mask */
+#define CAN_TXBCF_CF31(value)                 (CAN_TXBCF_CF31_Msk & (_UINT32_(value) << CAN_TXBCF_CF31_Pos)) /* Assignment of value for CF31 in the CAN_TXBCF register */
+#define CAN_TXBCF_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (CAN_TXBCF) Register Mask  */
+
+#define CAN_TXBCF_CF_Pos                      _UINT32_(0)                                          /* (CAN_TXBCF Position) Tx Buffer Cancellation Finished 3x */
+#define CAN_TXBCF_CF_Msk                      (_UINT32_(0xFFFFFFFF) << CAN_TXBCF_CF_Pos)           /* (CAN_TXBCF Mask) CF */
+#define CAN_TXBCF_CF(value)                   (CAN_TXBCF_CF_Msk & (_UINT32_(value) << CAN_TXBCF_CF_Pos)) 
+
+/* -------- CAN_TXBTIE : (CAN Offset: 0x1E0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */
+#define CAN_TXBTIE_RESETVALUE                 _UINT32_(0x00)                                       /*  (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable  Reset Value */
+
+#define CAN_TXBTIE_TIE0_Pos                   _UINT32_(0)                                          /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Position */
+#define CAN_TXBTIE_TIE0_Msk                   (_UINT32_(0x1) << CAN_TXBTIE_TIE0_Pos)               /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Mask */
+#define CAN_TXBTIE_TIE0(value)                (CAN_TXBTIE_TIE0_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE0_Pos)) /* Assignment of value for TIE0 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE1_Pos                   _UINT32_(1)                                          /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Position */
+#define CAN_TXBTIE_TIE1_Msk                   (_UINT32_(0x1) << CAN_TXBTIE_TIE1_Pos)               /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Mask */
+#define CAN_TXBTIE_TIE1(value)                (CAN_TXBTIE_TIE1_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE1_Pos)) /* Assignment of value for TIE1 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE2_Pos                   _UINT32_(2)                                          /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Position */
+#define CAN_TXBTIE_TIE2_Msk                   (_UINT32_(0x1) << CAN_TXBTIE_TIE2_Pos)               /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Mask */
+#define CAN_TXBTIE_TIE2(value)                (CAN_TXBTIE_TIE2_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE2_Pos)) /* Assignment of value for TIE2 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE3_Pos                   _UINT32_(3)                                          /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Position */
+#define CAN_TXBTIE_TIE3_Msk                   (_UINT32_(0x1) << CAN_TXBTIE_TIE3_Pos)               /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Mask */
+#define CAN_TXBTIE_TIE3(value)                (CAN_TXBTIE_TIE3_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE3_Pos)) /* Assignment of value for TIE3 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE4_Pos                   _UINT32_(4)                                          /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Position */
+#define CAN_TXBTIE_TIE4_Msk                   (_UINT32_(0x1) << CAN_TXBTIE_TIE4_Pos)               /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Mask */
+#define CAN_TXBTIE_TIE4(value)                (CAN_TXBTIE_TIE4_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE4_Pos)) /* Assignment of value for TIE4 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE5_Pos                   _UINT32_(5)                                          /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Position */
+#define CAN_TXBTIE_TIE5_Msk                   (_UINT32_(0x1) << CAN_TXBTIE_TIE5_Pos)               /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Mask */
+#define CAN_TXBTIE_TIE5(value)                (CAN_TXBTIE_TIE5_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE5_Pos)) /* Assignment of value for TIE5 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE6_Pos                   _UINT32_(6)                                          /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Position */
+#define CAN_TXBTIE_TIE6_Msk                   (_UINT32_(0x1) << CAN_TXBTIE_TIE6_Pos)               /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Mask */
+#define CAN_TXBTIE_TIE6(value)                (CAN_TXBTIE_TIE6_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE6_Pos)) /* Assignment of value for TIE6 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE7_Pos                   _UINT32_(7)                                          /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Position */
+#define CAN_TXBTIE_TIE7_Msk                   (_UINT32_(0x1) << CAN_TXBTIE_TIE7_Pos)               /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Mask */
+#define CAN_TXBTIE_TIE7(value)                (CAN_TXBTIE_TIE7_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE7_Pos)) /* Assignment of value for TIE7 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE8_Pos                   _UINT32_(8)                                          /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Position */
+#define CAN_TXBTIE_TIE8_Msk                   (_UINT32_(0x1) << CAN_TXBTIE_TIE8_Pos)               /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Mask */
+#define CAN_TXBTIE_TIE8(value)                (CAN_TXBTIE_TIE8_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE8_Pos)) /* Assignment of value for TIE8 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE9_Pos                   _UINT32_(9)                                          /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Position */
+#define CAN_TXBTIE_TIE9_Msk                   (_UINT32_(0x1) << CAN_TXBTIE_TIE9_Pos)               /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Mask */
+#define CAN_TXBTIE_TIE9(value)                (CAN_TXBTIE_TIE9_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE9_Pos)) /* Assignment of value for TIE9 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE10_Pos                  _UINT32_(10)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Position */
+#define CAN_TXBTIE_TIE10_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE10_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Mask */
+#define CAN_TXBTIE_TIE10(value)               (CAN_TXBTIE_TIE10_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE10_Pos)) /* Assignment of value for TIE10 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE11_Pos                  _UINT32_(11)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Position */
+#define CAN_TXBTIE_TIE11_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE11_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Mask */
+#define CAN_TXBTIE_TIE11(value)               (CAN_TXBTIE_TIE11_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE11_Pos)) /* Assignment of value for TIE11 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE12_Pos                  _UINT32_(12)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Position */
+#define CAN_TXBTIE_TIE12_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE12_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Mask */
+#define CAN_TXBTIE_TIE12(value)               (CAN_TXBTIE_TIE12_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE12_Pos)) /* Assignment of value for TIE12 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE13_Pos                  _UINT32_(13)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Position */
+#define CAN_TXBTIE_TIE13_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE13_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Mask */
+#define CAN_TXBTIE_TIE13(value)               (CAN_TXBTIE_TIE13_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE13_Pos)) /* Assignment of value for TIE13 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE14_Pos                  _UINT32_(14)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Position */
+#define CAN_TXBTIE_TIE14_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE14_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Mask */
+#define CAN_TXBTIE_TIE14(value)               (CAN_TXBTIE_TIE14_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE14_Pos)) /* Assignment of value for TIE14 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE15_Pos                  _UINT32_(15)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Position */
+#define CAN_TXBTIE_TIE15_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE15_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Mask */
+#define CAN_TXBTIE_TIE15(value)               (CAN_TXBTIE_TIE15_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE15_Pos)) /* Assignment of value for TIE15 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE16_Pos                  _UINT32_(16)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Position */
+#define CAN_TXBTIE_TIE16_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE16_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Mask */
+#define CAN_TXBTIE_TIE16(value)               (CAN_TXBTIE_TIE16_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE16_Pos)) /* Assignment of value for TIE16 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE17_Pos                  _UINT32_(17)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Position */
+#define CAN_TXBTIE_TIE17_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE17_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Mask */
+#define CAN_TXBTIE_TIE17(value)               (CAN_TXBTIE_TIE17_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE17_Pos)) /* Assignment of value for TIE17 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE18_Pos                  _UINT32_(18)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Position */
+#define CAN_TXBTIE_TIE18_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE18_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Mask */
+#define CAN_TXBTIE_TIE18(value)               (CAN_TXBTIE_TIE18_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE18_Pos)) /* Assignment of value for TIE18 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE19_Pos                  _UINT32_(19)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Position */
+#define CAN_TXBTIE_TIE19_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE19_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Mask */
+#define CAN_TXBTIE_TIE19(value)               (CAN_TXBTIE_TIE19_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE19_Pos)) /* Assignment of value for TIE19 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE20_Pos                  _UINT32_(20)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Position */
+#define CAN_TXBTIE_TIE20_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE20_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Mask */
+#define CAN_TXBTIE_TIE20(value)               (CAN_TXBTIE_TIE20_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE20_Pos)) /* Assignment of value for TIE20 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE21_Pos                  _UINT32_(21)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Position */
+#define CAN_TXBTIE_TIE21_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE21_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Mask */
+#define CAN_TXBTIE_TIE21(value)               (CAN_TXBTIE_TIE21_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE21_Pos)) /* Assignment of value for TIE21 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE22_Pos                  _UINT32_(22)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Position */
+#define CAN_TXBTIE_TIE22_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE22_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Mask */
+#define CAN_TXBTIE_TIE22(value)               (CAN_TXBTIE_TIE22_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE22_Pos)) /* Assignment of value for TIE22 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE23_Pos                  _UINT32_(23)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Position */
+#define CAN_TXBTIE_TIE23_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE23_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Mask */
+#define CAN_TXBTIE_TIE23(value)               (CAN_TXBTIE_TIE23_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE23_Pos)) /* Assignment of value for TIE23 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE24_Pos                  _UINT32_(24)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Position */
+#define CAN_TXBTIE_TIE24_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE24_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Mask */
+#define CAN_TXBTIE_TIE24(value)               (CAN_TXBTIE_TIE24_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE24_Pos)) /* Assignment of value for TIE24 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE25_Pos                  _UINT32_(25)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Position */
+#define CAN_TXBTIE_TIE25_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE25_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Mask */
+#define CAN_TXBTIE_TIE25(value)               (CAN_TXBTIE_TIE25_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE25_Pos)) /* Assignment of value for TIE25 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE26_Pos                  _UINT32_(26)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Position */
+#define CAN_TXBTIE_TIE26_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE26_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Mask */
+#define CAN_TXBTIE_TIE26(value)               (CAN_TXBTIE_TIE26_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE26_Pos)) /* Assignment of value for TIE26 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE27_Pos                  _UINT32_(27)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Position */
+#define CAN_TXBTIE_TIE27_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE27_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Mask */
+#define CAN_TXBTIE_TIE27(value)               (CAN_TXBTIE_TIE27_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE27_Pos)) /* Assignment of value for TIE27 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE28_Pos                  _UINT32_(28)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Position */
+#define CAN_TXBTIE_TIE28_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE28_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Mask */
+#define CAN_TXBTIE_TIE28(value)               (CAN_TXBTIE_TIE28_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE28_Pos)) /* Assignment of value for TIE28 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE29_Pos                  _UINT32_(29)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Position */
+#define CAN_TXBTIE_TIE29_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE29_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Mask */
+#define CAN_TXBTIE_TIE29(value)               (CAN_TXBTIE_TIE29_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE29_Pos)) /* Assignment of value for TIE29 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE30_Pos                  _UINT32_(30)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Position */
+#define CAN_TXBTIE_TIE30_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE30_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Mask */
+#define CAN_TXBTIE_TIE30(value)               (CAN_TXBTIE_TIE30_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE30_Pos)) /* Assignment of value for TIE30 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_TIE31_Pos                  _UINT32_(31)                                         /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Position */
+#define CAN_TXBTIE_TIE31_Msk                  (_UINT32_(0x1) << CAN_TXBTIE_TIE31_Pos)              /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Mask */
+#define CAN_TXBTIE_TIE31(value)               (CAN_TXBTIE_TIE31_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE31_Pos)) /* Assignment of value for TIE31 in the CAN_TXBTIE register */
+#define CAN_TXBTIE_Msk                        _UINT32_(0xFFFFFFFF)                                 /* (CAN_TXBTIE) Register Mask  */
+
+#define CAN_TXBTIE_TIE_Pos                    _UINT32_(0)                                          /* (CAN_TXBTIE Position) Transmission Interrupt Enable 3x */
+#define CAN_TXBTIE_TIE_Msk                    (_UINT32_(0xFFFFFFFF) << CAN_TXBTIE_TIE_Pos)         /* (CAN_TXBTIE Mask) TIE */
+#define CAN_TXBTIE_TIE(value)                 (CAN_TXBTIE_TIE_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE_Pos)) 
+
+/* -------- CAN_TXBCIE : (CAN Offset: 0x1E4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */
+#define CAN_TXBCIE_RESETVALUE                 _UINT32_(0x00)                                       /*  (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable  Reset Value */
+
+#define CAN_TXBCIE_CFIE0_Pos                  _UINT32_(0)                                          /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Position */
+#define CAN_TXBCIE_CFIE0_Msk                  (_UINT32_(0x1) << CAN_TXBCIE_CFIE0_Pos)              /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Mask */
+#define CAN_TXBCIE_CFIE0(value)               (CAN_TXBCIE_CFIE0_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE0_Pos)) /* Assignment of value for CFIE0 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE1_Pos                  _UINT32_(1)                                          /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Position */
+#define CAN_TXBCIE_CFIE1_Msk                  (_UINT32_(0x1) << CAN_TXBCIE_CFIE1_Pos)              /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Mask */
+#define CAN_TXBCIE_CFIE1(value)               (CAN_TXBCIE_CFIE1_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE1_Pos)) /* Assignment of value for CFIE1 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE2_Pos                  _UINT32_(2)                                          /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Position */
+#define CAN_TXBCIE_CFIE2_Msk                  (_UINT32_(0x1) << CAN_TXBCIE_CFIE2_Pos)              /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Mask */
+#define CAN_TXBCIE_CFIE2(value)               (CAN_TXBCIE_CFIE2_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE2_Pos)) /* Assignment of value for CFIE2 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE3_Pos                  _UINT32_(3)                                          /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Position */
+#define CAN_TXBCIE_CFIE3_Msk                  (_UINT32_(0x1) << CAN_TXBCIE_CFIE3_Pos)              /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Mask */
+#define CAN_TXBCIE_CFIE3(value)               (CAN_TXBCIE_CFIE3_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE3_Pos)) /* Assignment of value for CFIE3 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE4_Pos                  _UINT32_(4)                                          /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Position */
+#define CAN_TXBCIE_CFIE4_Msk                  (_UINT32_(0x1) << CAN_TXBCIE_CFIE4_Pos)              /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Mask */
+#define CAN_TXBCIE_CFIE4(value)               (CAN_TXBCIE_CFIE4_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE4_Pos)) /* Assignment of value for CFIE4 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE5_Pos                  _UINT32_(5)                                          /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Position */
+#define CAN_TXBCIE_CFIE5_Msk                  (_UINT32_(0x1) << CAN_TXBCIE_CFIE5_Pos)              /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Mask */
+#define CAN_TXBCIE_CFIE5(value)               (CAN_TXBCIE_CFIE5_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE5_Pos)) /* Assignment of value for CFIE5 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE6_Pos                  _UINT32_(6)                                          /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Position */
+#define CAN_TXBCIE_CFIE6_Msk                  (_UINT32_(0x1) << CAN_TXBCIE_CFIE6_Pos)              /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Mask */
+#define CAN_TXBCIE_CFIE6(value)               (CAN_TXBCIE_CFIE6_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE6_Pos)) /* Assignment of value for CFIE6 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE7_Pos                  _UINT32_(7)                                          /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Position */
+#define CAN_TXBCIE_CFIE7_Msk                  (_UINT32_(0x1) << CAN_TXBCIE_CFIE7_Pos)              /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Mask */
+#define CAN_TXBCIE_CFIE7(value)               (CAN_TXBCIE_CFIE7_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE7_Pos)) /* Assignment of value for CFIE7 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE8_Pos                  _UINT32_(8)                                          /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Position */
+#define CAN_TXBCIE_CFIE8_Msk                  (_UINT32_(0x1) << CAN_TXBCIE_CFIE8_Pos)              /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Mask */
+#define CAN_TXBCIE_CFIE8(value)               (CAN_TXBCIE_CFIE8_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE8_Pos)) /* Assignment of value for CFIE8 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE9_Pos                  _UINT32_(9)                                          /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Position */
+#define CAN_TXBCIE_CFIE9_Msk                  (_UINT32_(0x1) << CAN_TXBCIE_CFIE9_Pos)              /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Mask */
+#define CAN_TXBCIE_CFIE9(value)               (CAN_TXBCIE_CFIE9_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE9_Pos)) /* Assignment of value for CFIE9 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE10_Pos                 _UINT32_(10)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Position */
+#define CAN_TXBCIE_CFIE10_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE10_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Mask */
+#define CAN_TXBCIE_CFIE10(value)              (CAN_TXBCIE_CFIE10_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE10_Pos)) /* Assignment of value for CFIE10 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE11_Pos                 _UINT32_(11)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Position */
+#define CAN_TXBCIE_CFIE11_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE11_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Mask */
+#define CAN_TXBCIE_CFIE11(value)              (CAN_TXBCIE_CFIE11_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE11_Pos)) /* Assignment of value for CFIE11 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE12_Pos                 _UINT32_(12)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Position */
+#define CAN_TXBCIE_CFIE12_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE12_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Mask */
+#define CAN_TXBCIE_CFIE12(value)              (CAN_TXBCIE_CFIE12_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE12_Pos)) /* Assignment of value for CFIE12 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE13_Pos                 _UINT32_(13)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Position */
+#define CAN_TXBCIE_CFIE13_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE13_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Mask */
+#define CAN_TXBCIE_CFIE13(value)              (CAN_TXBCIE_CFIE13_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE13_Pos)) /* Assignment of value for CFIE13 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE14_Pos                 _UINT32_(14)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Position */
+#define CAN_TXBCIE_CFIE14_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE14_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Mask */
+#define CAN_TXBCIE_CFIE14(value)              (CAN_TXBCIE_CFIE14_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE14_Pos)) /* Assignment of value for CFIE14 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE15_Pos                 _UINT32_(15)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Position */
+#define CAN_TXBCIE_CFIE15_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE15_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Mask */
+#define CAN_TXBCIE_CFIE15(value)              (CAN_TXBCIE_CFIE15_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE15_Pos)) /* Assignment of value for CFIE15 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE16_Pos                 _UINT32_(16)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Position */
+#define CAN_TXBCIE_CFIE16_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE16_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Mask */
+#define CAN_TXBCIE_CFIE16(value)              (CAN_TXBCIE_CFIE16_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE16_Pos)) /* Assignment of value for CFIE16 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE17_Pos                 _UINT32_(17)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Position */
+#define CAN_TXBCIE_CFIE17_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE17_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Mask */
+#define CAN_TXBCIE_CFIE17(value)              (CAN_TXBCIE_CFIE17_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE17_Pos)) /* Assignment of value for CFIE17 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE18_Pos                 _UINT32_(18)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Position */
+#define CAN_TXBCIE_CFIE18_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE18_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Mask */
+#define CAN_TXBCIE_CFIE18(value)              (CAN_TXBCIE_CFIE18_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE18_Pos)) /* Assignment of value for CFIE18 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE19_Pos                 _UINT32_(19)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Position */
+#define CAN_TXBCIE_CFIE19_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE19_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Mask */
+#define CAN_TXBCIE_CFIE19(value)              (CAN_TXBCIE_CFIE19_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE19_Pos)) /* Assignment of value for CFIE19 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE20_Pos                 _UINT32_(20)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Position */
+#define CAN_TXBCIE_CFIE20_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE20_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Mask */
+#define CAN_TXBCIE_CFIE20(value)              (CAN_TXBCIE_CFIE20_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE20_Pos)) /* Assignment of value for CFIE20 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE21_Pos                 _UINT32_(21)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Position */
+#define CAN_TXBCIE_CFIE21_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE21_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Mask */
+#define CAN_TXBCIE_CFIE21(value)              (CAN_TXBCIE_CFIE21_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE21_Pos)) /* Assignment of value for CFIE21 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE22_Pos                 _UINT32_(22)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Position */
+#define CAN_TXBCIE_CFIE22_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE22_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Mask */
+#define CAN_TXBCIE_CFIE22(value)              (CAN_TXBCIE_CFIE22_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE22_Pos)) /* Assignment of value for CFIE22 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE23_Pos                 _UINT32_(23)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Position */
+#define CAN_TXBCIE_CFIE23_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE23_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Mask */
+#define CAN_TXBCIE_CFIE23(value)              (CAN_TXBCIE_CFIE23_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE23_Pos)) /* Assignment of value for CFIE23 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE24_Pos                 _UINT32_(24)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Position */
+#define CAN_TXBCIE_CFIE24_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE24_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Mask */
+#define CAN_TXBCIE_CFIE24(value)              (CAN_TXBCIE_CFIE24_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE24_Pos)) /* Assignment of value for CFIE24 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE25_Pos                 _UINT32_(25)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Position */
+#define CAN_TXBCIE_CFIE25_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE25_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Mask */
+#define CAN_TXBCIE_CFIE25(value)              (CAN_TXBCIE_CFIE25_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE25_Pos)) /* Assignment of value for CFIE25 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE26_Pos                 _UINT32_(26)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Position */
+#define CAN_TXBCIE_CFIE26_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE26_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Mask */
+#define CAN_TXBCIE_CFIE26(value)              (CAN_TXBCIE_CFIE26_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE26_Pos)) /* Assignment of value for CFIE26 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE27_Pos                 _UINT32_(27)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Position */
+#define CAN_TXBCIE_CFIE27_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE27_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Mask */
+#define CAN_TXBCIE_CFIE27(value)              (CAN_TXBCIE_CFIE27_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE27_Pos)) /* Assignment of value for CFIE27 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE28_Pos                 _UINT32_(28)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Position */
+#define CAN_TXBCIE_CFIE28_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE28_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Mask */
+#define CAN_TXBCIE_CFIE28(value)              (CAN_TXBCIE_CFIE28_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE28_Pos)) /* Assignment of value for CFIE28 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE29_Pos                 _UINT32_(29)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Position */
+#define CAN_TXBCIE_CFIE29_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE29_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Mask */
+#define CAN_TXBCIE_CFIE29(value)              (CAN_TXBCIE_CFIE29_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE29_Pos)) /* Assignment of value for CFIE29 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE30_Pos                 _UINT32_(30)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Position */
+#define CAN_TXBCIE_CFIE30_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE30_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Mask */
+#define CAN_TXBCIE_CFIE30(value)              (CAN_TXBCIE_CFIE30_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE30_Pos)) /* Assignment of value for CFIE30 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_CFIE31_Pos                 _UINT32_(31)                                         /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Position */
+#define CAN_TXBCIE_CFIE31_Msk                 (_UINT32_(0x1) << CAN_TXBCIE_CFIE31_Pos)             /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Mask */
+#define CAN_TXBCIE_CFIE31(value)              (CAN_TXBCIE_CFIE31_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE31_Pos)) /* Assignment of value for CFIE31 in the CAN_TXBCIE register */
+#define CAN_TXBCIE_Msk                        _UINT32_(0xFFFFFFFF)                                 /* (CAN_TXBCIE) Register Mask  */
+
+#define CAN_TXBCIE_CFIE_Pos                   _UINT32_(0)                                          /* (CAN_TXBCIE Position) Cancellation Finished Interrupt Enable 3x */
+#define CAN_TXBCIE_CFIE_Msk                   (_UINT32_(0xFFFFFFFF) << CAN_TXBCIE_CFIE_Pos)        /* (CAN_TXBCIE Mask) CFIE */
+#define CAN_TXBCIE_CFIE(value)                (CAN_TXBCIE_CFIE_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE_Pos)) 
+
+/* -------- CAN_TXEFC : (CAN Offset: 0x1F0) (R/W 32) Tx Event FIFO Configuration -------- */
+#define CAN_TXEFC_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TXEFC) Tx Event FIFO Configuration  Reset Value */
+
+#define CAN_TXEFC_EFSA_Pos                    _UINT32_(2)                                          /* (CAN_TXEFC) Event FIFO Start Address Position */
+#define CAN_TXEFC_EFSA_Msk                    (_UINT32_(0x3FFF) << CAN_TXEFC_EFSA_Pos)             /* (CAN_TXEFC) Event FIFO Start Address Mask */
+#define CAN_TXEFC_EFSA(value)                 (CAN_TXEFC_EFSA_Msk & (_UINT32_(value) << CAN_TXEFC_EFSA_Pos)) /* Assignment of value for EFSA in the CAN_TXEFC register */
+#define CAN_TXEFC_EFS_Pos                     _UINT32_(16)                                         /* (CAN_TXEFC) Event FIFO Size Position */
+#define CAN_TXEFC_EFS_Msk                     (_UINT32_(0x3F) << CAN_TXEFC_EFS_Pos)                /* (CAN_TXEFC) Event FIFO Size Mask */
+#define CAN_TXEFC_EFS(value)                  (CAN_TXEFC_EFS_Msk & (_UINT32_(value) << CAN_TXEFC_EFS_Pos)) /* Assignment of value for EFS in the CAN_TXEFC register */
+#define CAN_TXEFC_EFWM_Pos                    _UINT32_(24)                                         /* (CAN_TXEFC) Event FIFO Watermark Position */
+#define CAN_TXEFC_EFWM_Msk                    (_UINT32_(0x3F) << CAN_TXEFC_EFWM_Pos)               /* (CAN_TXEFC) Event FIFO Watermark Mask */
+#define CAN_TXEFC_EFWM(value)                 (CAN_TXEFC_EFWM_Msk & (_UINT32_(value) << CAN_TXEFC_EFWM_Pos)) /* Assignment of value for EFWM in the CAN_TXEFC register */
+#define CAN_TXEFC_Msk                         _UINT32_(0x3F3FFFFC)                                 /* (CAN_TXEFC) Register Mask  */
+
+
+/* -------- CAN_TXEFS : (CAN Offset: 0x1F4) ( R/ 32) Tx Event FIFO Status -------- */
+#define CAN_TXEFS_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TXEFS) Tx Event FIFO Status  Reset Value */
+
+#define CAN_TXEFS_EFFL_Pos                    _UINT32_(0)                                          /* (CAN_TXEFS) Event FIFO Fill Level Position */
+#define CAN_TXEFS_EFFL_Msk                    (_UINT32_(0x3F) << CAN_TXEFS_EFFL_Pos)               /* (CAN_TXEFS) Event FIFO Fill Level Mask */
+#define CAN_TXEFS_EFFL(value)                 (CAN_TXEFS_EFFL_Msk & (_UINT32_(value) << CAN_TXEFS_EFFL_Pos)) /* Assignment of value for EFFL in the CAN_TXEFS register */
+#define CAN_TXEFS_EFGI_Pos                    _UINT32_(8)                                          /* (CAN_TXEFS) Event FIFO Get Index Position */
+#define CAN_TXEFS_EFGI_Msk                    (_UINT32_(0x1F) << CAN_TXEFS_EFGI_Pos)               /* (CAN_TXEFS) Event FIFO Get Index Mask */
+#define CAN_TXEFS_EFGI(value)                 (CAN_TXEFS_EFGI_Msk & (_UINT32_(value) << CAN_TXEFS_EFGI_Pos)) /* Assignment of value for EFGI in the CAN_TXEFS register */
+#define CAN_TXEFS_EFPI_Pos                    _UINT32_(16)                                         /* (CAN_TXEFS) Event FIFO Put Index Position */
+#define CAN_TXEFS_EFPI_Msk                    (_UINT32_(0x1F) << CAN_TXEFS_EFPI_Pos)               /* (CAN_TXEFS) Event FIFO Put Index Mask */
+#define CAN_TXEFS_EFPI(value)                 (CAN_TXEFS_EFPI_Msk & (_UINT32_(value) << CAN_TXEFS_EFPI_Pos)) /* Assignment of value for EFPI in the CAN_TXEFS register */
+#define CAN_TXEFS_EFF_Pos                     _UINT32_(24)                                         /* (CAN_TXEFS) Event FIFO Full Position */
+#define CAN_TXEFS_EFF_Msk                     (_UINT32_(0x1) << CAN_TXEFS_EFF_Pos)                 /* (CAN_TXEFS) Event FIFO Full Mask */
+#define CAN_TXEFS_EFF(value)                  (CAN_TXEFS_EFF_Msk & (_UINT32_(value) << CAN_TXEFS_EFF_Pos)) /* Assignment of value for EFF in the CAN_TXEFS register */
+#define CAN_TXEFS_TEFL_Pos                    _UINT32_(25)                                         /* (CAN_TXEFS) Tx Event FIFO Element Lost Position */
+#define CAN_TXEFS_TEFL_Msk                    (_UINT32_(0x1) << CAN_TXEFS_TEFL_Pos)                /* (CAN_TXEFS) Tx Event FIFO Element Lost Mask */
+#define CAN_TXEFS_TEFL(value)                 (CAN_TXEFS_TEFL_Msk & (_UINT32_(value) << CAN_TXEFS_TEFL_Pos)) /* Assignment of value for TEFL in the CAN_TXEFS register */
+#define CAN_TXEFS_Msk                         _UINT32_(0x031F1F3F)                                 /* (CAN_TXEFS) Register Mask  */
+
+
+/* -------- CAN_TXEFA : (CAN Offset: 0x1F8) (R/W 32) Tx Event FIFO Acknowledge -------- */
+#define CAN_TXEFA_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TXEFA) Tx Event FIFO Acknowledge  Reset Value */
+
+#define CAN_TXEFA_EFAI_Pos                    _UINT32_(0)                                          /* (CAN_TXEFA) Event FIFO Acknowledge Index Position */
+#define CAN_TXEFA_EFAI_Msk                    (_UINT32_(0x1F) << CAN_TXEFA_EFAI_Pos)               /* (CAN_TXEFA) Event FIFO Acknowledge Index Mask */
+#define CAN_TXEFA_EFAI(value)                 (CAN_TXEFA_EFAI_Msk & (_UINT32_(value) << CAN_TXEFA_EFAI_Pos)) /* Assignment of value for EFAI in the CAN_TXEFA register */
+#define CAN_TXEFA_Msk                         _UINT32_(0x0000001F)                                 /* (CAN_TXEFA) Register Mask  */
+
+
+/* -------- CAN_CREL_TSU : (CAN Offset: 0x260) ( R/ 32) TSU CREL -------- */
+#define CAN_CREL_TSU_RESETVALUE               _UINT32_(0x10000000)                                 /*  (CAN_CREL_TSU) TSU CREL  Reset Value */
+
+#define CAN_CREL_TSU_DAY_Pos                  _UINT32_(0)                                          /* (CAN_CREL_TSU) Timestamp Day Position */
+#define CAN_CREL_TSU_DAY_Msk                  (_UINT32_(0xFF) << CAN_CREL_TSU_DAY_Pos)             /* (CAN_CREL_TSU) Timestamp Day Mask */
+#define CAN_CREL_TSU_DAY(value)               (CAN_CREL_TSU_DAY_Msk & (_UINT32_(value) << CAN_CREL_TSU_DAY_Pos)) /* Assignment of value for DAY in the CAN_CREL_TSU register */
+#define CAN_CREL_TSU_MON_Pos                  _UINT32_(8)                                          /* (CAN_CREL_TSU) Timestamp Month Position */
+#define CAN_CREL_TSU_MON_Msk                  (_UINT32_(0xFF) << CAN_CREL_TSU_MON_Pos)             /* (CAN_CREL_TSU) Timestamp Month Mask */
+#define CAN_CREL_TSU_MON(value)               (CAN_CREL_TSU_MON_Msk & (_UINT32_(value) << CAN_CREL_TSU_MON_Pos)) /* Assignment of value for MON in the CAN_CREL_TSU register */
+#define CAN_CREL_TSU_YEAR_Pos                 _UINT32_(16)                                         /* (CAN_CREL_TSU) Timestamp Year Position */
+#define CAN_CREL_TSU_YEAR_Msk                 (_UINT32_(0xF) << CAN_CREL_TSU_YEAR_Pos)             /* (CAN_CREL_TSU) Timestamp Year Mask */
+#define CAN_CREL_TSU_YEAR(value)              (CAN_CREL_TSU_YEAR_Msk & (_UINT32_(value) << CAN_CREL_TSU_YEAR_Pos)) /* Assignment of value for YEAR in the CAN_CREL_TSU register */
+#define CAN_CREL_TSU_SUBSTEP_Pos              _UINT32_(20)                                         /* (CAN_CREL_TSU) Sub-step of Core Release Position */
+#define CAN_CREL_TSU_SUBSTEP_Msk              (_UINT32_(0xF) << CAN_CREL_TSU_SUBSTEP_Pos)          /* (CAN_CREL_TSU) Sub-step of Core Release Mask */
+#define CAN_CREL_TSU_SUBSTEP(value)           (CAN_CREL_TSU_SUBSTEP_Msk & (_UINT32_(value) << CAN_CREL_TSU_SUBSTEP_Pos)) /* Assignment of value for SUBSTEP in the CAN_CREL_TSU register */
+#define CAN_CREL_TSU_STEP_Pos                 _UINT32_(24)                                         /* (CAN_CREL_TSU) Step of Core Release Position */
+#define CAN_CREL_TSU_STEP_Msk                 (_UINT32_(0xF) << CAN_CREL_TSU_STEP_Pos)             /* (CAN_CREL_TSU) Step of Core Release Mask */
+#define CAN_CREL_TSU_STEP(value)              (CAN_CREL_TSU_STEP_Msk & (_UINT32_(value) << CAN_CREL_TSU_STEP_Pos)) /* Assignment of value for STEP in the CAN_CREL_TSU register */
+#define CAN_CREL_TSU_REL_Pos                  _UINT32_(28)                                         /* (CAN_CREL_TSU) Core Release Position */
+#define CAN_CREL_TSU_REL_Msk                  (_UINT32_(0xF) << CAN_CREL_TSU_REL_Pos)              /* (CAN_CREL_TSU) Core Release Mask */
+#define CAN_CREL_TSU_REL(value)               (CAN_CREL_TSU_REL_Msk & (_UINT32_(value) << CAN_CREL_TSU_REL_Pos)) /* Assignment of value for REL in the CAN_CREL_TSU register */
+#define CAN_CREL_TSU_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (CAN_CREL_TSU) Register Mask  */
+
+
+/* -------- CAN_TSCFG : (CAN Offset: 0x264) (R/W 32) Timestamp Configuration -------- */
+#define CAN_TSCFG_RESETVALUE                  _UINT32_(0x00)                                       /*  (CAN_TSCFG) Timestamp Configuration  Reset Value */
+
+#define CAN_TSCFG_TSUE_Pos                    _UINT32_(0)                                          /* (CAN_TSCFG) Timestamp Unit Enable Position */
+#define CAN_TSCFG_TSUE_Msk                    (_UINT32_(0x1) << CAN_TSCFG_TSUE_Pos)                /* (CAN_TSCFG) Timestamp Unit Enable Mask */
+#define CAN_TSCFG_TSUE(value)                 (CAN_TSCFG_TSUE_Msk & (_UINT32_(value) << CAN_TSCFG_TSUE_Pos)) /* Assignment of value for TSUE in the CAN_TSCFG register */
+#define CAN_TSCFG_TBCS_Pos                    _UINT32_(1)                                          /* (CAN_TSCFG) Timebase Counter Select Position */
+#define CAN_TSCFG_TBCS_Msk                    (_UINT32_(0x1) << CAN_TSCFG_TBCS_Pos)                /* (CAN_TSCFG) Timebase Counter Select Mask */
+#define CAN_TSCFG_TBCS(value)                 (CAN_TSCFG_TBCS_Msk & (_UINT32_(value) << CAN_TSCFG_TBCS_Pos)) /* Assignment of value for TBCS in the CAN_TSCFG register */
+#define CAN_TSCFG_SCP_Pos                     _UINT32_(2)                                          /* (CAN_TSCFG) Select Capturing Position Position */
+#define CAN_TSCFG_SCP_Msk                     (_UINT32_(0x1) << CAN_TSCFG_SCP_Pos)                 /* (CAN_TSCFG) Select Capturing Position Mask */
+#define CAN_TSCFG_SCP(value)                  (CAN_TSCFG_SCP_Msk & (_UINT32_(value) << CAN_TSCFG_SCP_Pos)) /* Assignment of value for SCP in the CAN_TSCFG register */
+#define CAN_TSCFG_TBPRE_Pos                   _UINT32_(8)                                          /* (CAN_TSCFG) Time Base Prescaler Position */
+#define CAN_TSCFG_TBPRE_Msk                   (_UINT32_(0xFF) << CAN_TSCFG_TBPRE_Pos)              /* (CAN_TSCFG) Time Base Prescaler Mask */
+#define CAN_TSCFG_TBPRE(value)                (CAN_TSCFG_TBPRE_Msk & (_UINT32_(value) << CAN_TSCFG_TBPRE_Pos)) /* Assignment of value for TBPRE in the CAN_TSCFG register */
+#define CAN_TSCFG_Msk                         _UINT32_(0x0000FF07)                                 /* (CAN_TSCFG) Register Mask  */
+
+
+/* -------- CAN_TSS1 : (CAN Offset: 0x268) ( R/ 32) Timestamp Status 1 -------- */
+#define CAN_TSS1_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TSS1) Timestamp Status 1  Reset Value */
+
+#define CAN_TSS1_TSL_Pos                      _UINT32_(0)                                          /* (CAN_TSS1) Timestamp Lost Position */
+#define CAN_TSS1_TSL_Msk                      (_UINT32_(0xFFFF) << CAN_TSS1_TSL_Pos)               /* (CAN_TSS1) Timestamp Lost Mask */
+#define CAN_TSS1_TSL(value)                   (CAN_TSS1_TSL_Msk & (_UINT32_(value) << CAN_TSS1_TSL_Pos)) /* Assignment of value for TSL in the CAN_TSS1 register */
+#define CAN_TSS1_TSN_Pos                      _UINT32_(16)                                         /* (CAN_TSS1) Timestamp New Position */
+#define CAN_TSS1_TSN_Msk                      (_UINT32_(0xFFFF) << CAN_TSS1_TSN_Pos)               /* (CAN_TSS1) Timestamp New Mask */
+#define CAN_TSS1_TSN(value)                   (CAN_TSS1_TSN_Msk & (_UINT32_(value) << CAN_TSS1_TSN_Pos)) /* Assignment of value for TSN in the CAN_TSS1 register */
+#define CAN_TSS1_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (CAN_TSS1) Register Mask  */
+
+
+/* -------- CAN_TSS2 : (CAN Offset: 0x26C) ( R/ 32) Timestamp Status 2 -------- */
+#define CAN_TSS2_RESETVALUE                   _UINT32_(0xA000)                                     /*  (CAN_TSS2) Timestamp Status 2  Reset Value */
+
+#define CAN_TSS2_TSP_Pos                      _UINT32_(0)                                          /* (CAN_TSS2) Timestamp Pointer Position */
+#define CAN_TSS2_TSP_Msk                      (_UINT32_(0xF) << CAN_TSS2_TSP_Pos)                  /* (CAN_TSS2) Timestamp Pointer Mask */
+#define CAN_TSS2_TSP(value)                   (CAN_TSS2_TSP_Msk & (_UINT32_(value) << CAN_TSS2_TSP_Pos)) /* Assignment of value for TSP in the CAN_TSS2 register */
+#define CAN_TSS2_NTSG_Pos                     _UINT32_(12)                                         /* (CAN_TSS2) Number of Timestamps Generic Position */
+#define CAN_TSS2_NTSG_Msk                     (_UINT32_(0x3) << CAN_TSS2_NTSG_Pos)                 /* (CAN_TSS2) Number of Timestamps Generic Mask */
+#define CAN_TSS2_NTSG(value)                  (CAN_TSS2_NTSG_Msk & (_UINT32_(value) << CAN_TSS2_NTSG_Pos)) /* Assignment of value for NTSG in the CAN_TSS2 register */
+#define CAN_TSS2_ITBG_Pos                     _UINT32_(14)                                         /* (CAN_TSS2) Internal Timebase and SOF select Generic Position */
+#define CAN_TSS2_ITBG_Msk                     (_UINT32_(0x3) << CAN_TSS2_ITBG_Pos)                 /* (CAN_TSS2) Internal Timebase and SOF select Generic Mask */
+#define CAN_TSS2_ITBG(value)                  (CAN_TSS2_ITBG_Msk & (_UINT32_(value) << CAN_TSS2_ITBG_Pos)) /* Assignment of value for ITBG in the CAN_TSS2 register */
+#define CAN_TSS2_Msk                          _UINT32_(0x0000F00F)                                 /* (CAN_TSS2) Register Mask  */
+
+
+/* -------- CAN_TS0 : (CAN Offset: 0x270) ( R/ 32) Timestamp 0 -------- */
+#define CAN_TS0_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_TS0) Timestamp 0  Reset Value */
+
+#define CAN_TS0_TS_Pos                        _UINT32_(0)                                          /* (CAN_TS0) Timestamp Word TS0 Position */
+#define CAN_TS0_TS_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_TS0_TS_Pos)             /* (CAN_TS0) Timestamp Word TS0 Mask */
+#define CAN_TS0_TS(value)                     (CAN_TS0_TS_Msk & (_UINT32_(value) << CAN_TS0_TS_Pos)) /* Assignment of value for TS in the CAN_TS0 register */
+#define CAN_TS0_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS0) Register Mask  */
+
+
+/* -------- CAN_TS1 : (CAN Offset: 0x274) ( R/ 32) Timestamp 1 -------- */
+#define CAN_TS1_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_TS1) Timestamp 1  Reset Value */
+
+#define CAN_TS1_TS_Pos                        _UINT32_(0)                                          /* (CAN_TS1) Timestamp Word TS1 Position */
+#define CAN_TS1_TS_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_TS1_TS_Pos)             /* (CAN_TS1) Timestamp Word TS1 Mask */
+#define CAN_TS1_TS(value)                     (CAN_TS1_TS_Msk & (_UINT32_(value) << CAN_TS1_TS_Pos)) /* Assignment of value for TS in the CAN_TS1 register */
+#define CAN_TS1_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS1) Register Mask  */
+
+
+/* -------- CAN_TS2 : (CAN Offset: 0x278) ( R/ 32) Timestamp 2 -------- */
+#define CAN_TS2_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_TS2) Timestamp 2  Reset Value */
+
+#define CAN_TS2_TS_Pos                        _UINT32_(0)                                          /* (CAN_TS2) Timestamp Word TS2 Position */
+#define CAN_TS2_TS_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_TS2_TS_Pos)             /* (CAN_TS2) Timestamp Word TS2 Mask */
+#define CAN_TS2_TS(value)                     (CAN_TS2_TS_Msk & (_UINT32_(value) << CAN_TS2_TS_Pos)) /* Assignment of value for TS in the CAN_TS2 register */
+#define CAN_TS2_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS2) Register Mask  */
+
+
+/* -------- CAN_TS3 : (CAN Offset: 0x27C) ( R/ 32) Timestamp 3 -------- */
+#define CAN_TS3_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_TS3) Timestamp 3  Reset Value */
+
+#define CAN_TS3_TS_Pos                        _UINT32_(0)                                          /* (CAN_TS3) Timestamp Word TS0 Position */
+#define CAN_TS3_TS_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_TS3_TS_Pos)             /* (CAN_TS3) Timestamp Word TS0 Mask */
+#define CAN_TS3_TS(value)                     (CAN_TS3_TS_Msk & (_UINT32_(value) << CAN_TS3_TS_Pos)) /* Assignment of value for TS in the CAN_TS3 register */
+#define CAN_TS3_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS3) Register Mask  */
+
+
+/* -------- CAN_TS4 : (CAN Offset: 0x280) ( R/ 32) Timestamp 4 -------- */
+#define CAN_TS4_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_TS4) Timestamp 4  Reset Value */
+
+#define CAN_TS4_TS_Pos                        _UINT32_(0)                                          /* (CAN_TS4) Timestamp Word TS4 Position */
+#define CAN_TS4_TS_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_TS4_TS_Pos)             /* (CAN_TS4) Timestamp Word TS4 Mask */
+#define CAN_TS4_TS(value)                     (CAN_TS4_TS_Msk & (_UINT32_(value) << CAN_TS4_TS_Pos)) /* Assignment of value for TS in the CAN_TS4 register */
+#define CAN_TS4_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS4) Register Mask  */
+
+
+/* -------- CAN_TS5 : (CAN Offset: 0x284) ( R/ 32) Timestamp 5 -------- */
+#define CAN_TS5_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_TS5) Timestamp 5  Reset Value */
+
+#define CAN_TS5_TS_Pos                        _UINT32_(0)                                          /* (CAN_TS5) Timestamp Word TS5 Position */
+#define CAN_TS5_TS_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_TS5_TS_Pos)             /* (CAN_TS5) Timestamp Word TS5 Mask */
+#define CAN_TS5_TS(value)                     (CAN_TS5_TS_Msk & (_UINT32_(value) << CAN_TS5_TS_Pos)) /* Assignment of value for TS in the CAN_TS5 register */
+#define CAN_TS5_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS5) Register Mask  */
+
+
+/* -------- CAN_TS6 : (CAN Offset: 0x288) ( R/ 32) Timestamp 6 -------- */
+#define CAN_TS6_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_TS6) Timestamp 6  Reset Value */
+
+#define CAN_TS6_TS_Pos                        _UINT32_(0)                                          /* (CAN_TS6) Timestamp Word TS6 Position */
+#define CAN_TS6_TS_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_TS6_TS_Pos)             /* (CAN_TS6) Timestamp Word TS6 Mask */
+#define CAN_TS6_TS(value)                     (CAN_TS6_TS_Msk & (_UINT32_(value) << CAN_TS6_TS_Pos)) /* Assignment of value for TS in the CAN_TS6 register */
+#define CAN_TS6_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS6) Register Mask  */
+
+
+/* -------- CAN_TS7 : (CAN Offset: 0x28C) ( R/ 32) Timestamp 7 -------- */
+#define CAN_TS7_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_TS7) Timestamp 7  Reset Value */
+
+#define CAN_TS7_TS_Pos                        _UINT32_(0)                                          /* (CAN_TS7) Timestamp Word TS7 Position */
+#define CAN_TS7_TS_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_TS7_TS_Pos)             /* (CAN_TS7) Timestamp Word TS7 Mask */
+#define CAN_TS7_TS(value)                     (CAN_TS7_TS_Msk & (_UINT32_(value) << CAN_TS7_TS_Pos)) /* Assignment of value for TS in the CAN_TS7 register */
+#define CAN_TS7_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS7) Register Mask  */
+
+
+/* -------- CAN_TS8 : (CAN Offset: 0x290) ( R/ 32) Timestamp 8 -------- */
+#define CAN_TS8_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_TS8) Timestamp 8  Reset Value */
+
+#define CAN_TS8_TS_Pos                        _UINT32_(0)                                          /* (CAN_TS8) Timestamp Word TS8 Position */
+#define CAN_TS8_TS_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_TS8_TS_Pos)             /* (CAN_TS8) Timestamp Word TS8 Mask */
+#define CAN_TS8_TS(value)                     (CAN_TS8_TS_Msk & (_UINT32_(value) << CAN_TS8_TS_Pos)) /* Assignment of value for TS in the CAN_TS8 register */
+#define CAN_TS8_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS8) Register Mask  */
+
+
+/* -------- CAN_TS9 : (CAN Offset: 0x294) ( R/ 32) Timestamp 9 -------- */
+#define CAN_TS9_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_TS9) Timestamp 9  Reset Value */
+
+#define CAN_TS9_TS_Pos                        _UINT32_(0)                                          /* (CAN_TS9) Timestamp Word TS9 Position */
+#define CAN_TS9_TS_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_TS9_TS_Pos)             /* (CAN_TS9) Timestamp Word TS9 Mask */
+#define CAN_TS9_TS(value)                     (CAN_TS9_TS_Msk & (_UINT32_(value) << CAN_TS9_TS_Pos)) /* Assignment of value for TS in the CAN_TS9 register */
+#define CAN_TS9_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS9) Register Mask  */
+
+
+/* -------- CAN_TS10 : (CAN Offset: 0x298) ( R/ 32) Timestamp 10 -------- */
+#define CAN_TS10_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TS10) Timestamp 10  Reset Value */
+
+#define CAN_TS10_TS_Pos                       _UINT32_(0)                                          /* (CAN_TS10) Timestamp Word TS10 Position */
+#define CAN_TS10_TS_Msk                       (_UINT32_(0xFFFFFFFF) << CAN_TS10_TS_Pos)            /* (CAN_TS10) Timestamp Word TS10 Mask */
+#define CAN_TS10_TS(value)                    (CAN_TS10_TS_Msk & (_UINT32_(value) << CAN_TS10_TS_Pos)) /* Assignment of value for TS in the CAN_TS10 register */
+#define CAN_TS10_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS10) Register Mask  */
+
+
+/* -------- CAN_TS11 : (CAN Offset: 0x29C) ( R/ 32) Timestamp 11 -------- */
+#define CAN_TS11_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TS11) Timestamp 11  Reset Value */
+
+#define CAN_TS11_TS_Pos                       _UINT32_(0)                                          /* (CAN_TS11) Timestamp Word TS11 Position */
+#define CAN_TS11_TS_Msk                       (_UINT32_(0xFFFFFFFF) << CAN_TS11_TS_Pos)            /* (CAN_TS11) Timestamp Word TS11 Mask */
+#define CAN_TS11_TS(value)                    (CAN_TS11_TS_Msk & (_UINT32_(value) << CAN_TS11_TS_Pos)) /* Assignment of value for TS in the CAN_TS11 register */
+#define CAN_TS11_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS11) Register Mask  */
+
+
+/* -------- CAN_TS12 : (CAN Offset: 0x2A0) ( R/ 32) Timestamp 12 -------- */
+#define CAN_TS12_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TS12) Timestamp 12  Reset Value */
+
+#define CAN_TS12_TS_Pos                       _UINT32_(0)                                          /* (CAN_TS12) Timestamp Word TS12 Position */
+#define CAN_TS12_TS_Msk                       (_UINT32_(0xFFFFFFFF) << CAN_TS12_TS_Pos)            /* (CAN_TS12) Timestamp Word TS12 Mask */
+#define CAN_TS12_TS(value)                    (CAN_TS12_TS_Msk & (_UINT32_(value) << CAN_TS12_TS_Pos)) /* Assignment of value for TS in the CAN_TS12 register */
+#define CAN_TS12_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS12) Register Mask  */
+
+
+/* -------- CAN_TS13 : (CAN Offset: 0x2A4) ( R/ 32) Timestamp 13 -------- */
+#define CAN_TS13_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TS13) Timestamp 13  Reset Value */
+
+#define CAN_TS13_TS_Pos                       _UINT32_(0)                                          /* (CAN_TS13) Timestamp Word TS13 Position */
+#define CAN_TS13_TS_Msk                       (_UINT32_(0xFFFFFFFF) << CAN_TS13_TS_Pos)            /* (CAN_TS13) Timestamp Word TS13 Mask */
+#define CAN_TS13_TS(value)                    (CAN_TS13_TS_Msk & (_UINT32_(value) << CAN_TS13_TS_Pos)) /* Assignment of value for TS in the CAN_TS13 register */
+#define CAN_TS13_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS13) Register Mask  */
+
+
+/* -------- CAN_TS14 : (CAN Offset: 0x2A8) ( R/ 32) Timestamp 14 -------- */
+#define CAN_TS14_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TS14) Timestamp 14  Reset Value */
+
+#define CAN_TS14_TS_Pos                       _UINT32_(0)                                          /* (CAN_TS14) Timestamp Word TS14 Position */
+#define CAN_TS14_TS_Msk                       (_UINT32_(0xFFFFFFFF) << CAN_TS14_TS_Pos)            /* (CAN_TS14) Timestamp Word TS14 Mask */
+#define CAN_TS14_TS(value)                    (CAN_TS14_TS_Msk & (_UINT32_(value) << CAN_TS14_TS_Pos)) /* Assignment of value for TS in the CAN_TS14 register */
+#define CAN_TS14_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS14) Register Mask  */
+
+
+/* -------- CAN_TS15 : (CAN Offset: 0x2AC) ( R/ 32) Timestamp 15 -------- */
+#define CAN_TS15_RESETVALUE                   _UINT32_(0x00)                                       /*  (CAN_TS15) Timestamp 15  Reset Value */
+
+#define CAN_TS15_TS_Pos                       _UINT32_(0)                                          /* (CAN_TS15) Timestamp Word TS15 Position */
+#define CAN_TS15_TS_Msk                       (_UINT32_(0xFFFFFFFF) << CAN_TS15_TS_Pos)            /* (CAN_TS15) Timestamp Word TS15 Mask */
+#define CAN_TS15_TS(value)                    (CAN_TS15_TS_Msk & (_UINT32_(value) << CAN_TS15_TS_Pos)) /* Assignment of value for TS in the CAN_TS15 register */
+#define CAN_TS15_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (CAN_TS15) Register Mask  */
+
+
+/* -------- CAN_ATB : (CAN Offset: 0x2B0) (R/W 32) Actual Timebase -------- */
+#define CAN_ATB_RESETVALUE                    _UINT32_(0x00)                                       /*  (CAN_ATB) Actual Timebase  Reset Value */
+
+#define CAN_ATB_TB_Pos                        _UINT32_(0)                                          /* (CAN_ATB) Timebase for timestamp generation Position */
+#define CAN_ATB_TB_Msk                        (_UINT32_(0xFFFFFFFF) << CAN_ATB_TB_Pos)             /* (CAN_ATB) Timebase for timestamp generation Mask */
+#define CAN_ATB_TB(value)                     (CAN_ATB_TB_Msk & (_UINT32_(value) << CAN_ATB_TB_Pos)) /* Assignment of value for TB in the CAN_ATB register */
+#define CAN_ATB_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (CAN_ATB) Register Mask  */
+
+
+/* CAN register offsets definitions */
+#define CAN_R0_REG_OFST                _UINT32_(0x00)      /* (CAN_R0) Rx Buffer and FIFO Element 0 Offset */
+#define CAN_R1_REG_OFST                _UINT32_(0x04)      /* (CAN_R1) Rx Buffer and FIFO Element 1 Offset */
+#define CAN_R2_REG_OFST                _UINT32_(0x08)      /* (CAN_R2) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_0_REG_OFST              _UINT32_(0x08)      /* (CAN_R2_0) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_1_REG_OFST              _UINT32_(0x0C)      /* (CAN_R2_1) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_2_REG_OFST              _UINT32_(0x10)      /* (CAN_R2_2) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_3_REG_OFST              _UINT32_(0x14)      /* (CAN_R2_3) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_4_REG_OFST              _UINT32_(0x18)      /* (CAN_R2_4) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_5_REG_OFST              _UINT32_(0x1C)      /* (CAN_R2_5) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_6_REG_OFST              _UINT32_(0x20)      /* (CAN_R2_6) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_7_REG_OFST              _UINT32_(0x24)      /* (CAN_R2_7) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_8_REG_OFST              _UINT32_(0x28)      /* (CAN_R2_8) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_9_REG_OFST              _UINT32_(0x2C)      /* (CAN_R2_9) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_10_REG_OFST             _UINT32_(0x30)      /* (CAN_R2_10) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_11_REG_OFST             _UINT32_(0x34)      /* (CAN_R2_11) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_12_REG_OFST             _UINT32_(0x38)      /* (CAN_R2_12) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_13_REG_OFST             _UINT32_(0x3C)      /* (CAN_R2_13) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_14_REG_OFST             _UINT32_(0x40)      /* (CAN_R2_14) Rx Buffer and FIFO Element Data Offset */
+#define CAN_R2_15_REG_OFST             _UINT32_(0x44)      /* (CAN_R2_15) Rx Buffer and FIFO Element Data Offset */
+#define CAN_S0_REG_OFST                _UINT32_(0x00)      /* (CAN_S0) Standard Message ID Filter Element Offset */
+#define CAN_T0_REG_OFST                _UINT32_(0x00)      /* (CAN_T0) Tx Buffer Element 0 Offset */
+#define CAN_T1_REG_OFST                _UINT32_(0x04)      /* (CAN_T1) Tx Buffer Element 1 Offset */
+#define CAN_T2_REG_OFST                _UINT32_(0x08)      /* (CAN_T2) Tx Buffer Element Data Offset */
+#define CAN_T2_0_REG_OFST              _UINT32_(0x08)      /* (CAN_T2_0) Tx Buffer Element Data Offset */
+#define CAN_T2_1_REG_OFST              _UINT32_(0x0C)      /* (CAN_T2_1) Tx Buffer Element Data Offset */
+#define CAN_T2_2_REG_OFST              _UINT32_(0x10)      /* (CAN_T2_2) Tx Buffer Element Data Offset */
+#define CAN_T2_3_REG_OFST              _UINT32_(0x14)      /* (CAN_T2_3) Tx Buffer Element Data Offset */
+#define CAN_T2_4_REG_OFST              _UINT32_(0x18)      /* (CAN_T2_4) Tx Buffer Element Data Offset */
+#define CAN_T2_5_REG_OFST              _UINT32_(0x1C)      /* (CAN_T2_5) Tx Buffer Element Data Offset */
+#define CAN_T2_6_REG_OFST              _UINT32_(0x20)      /* (CAN_T2_6) Tx Buffer Element Data Offset */
+#define CAN_T2_7_REG_OFST              _UINT32_(0x24)      /* (CAN_T2_7) Tx Buffer Element Data Offset */
+#define CAN_T2_8_REG_OFST              _UINT32_(0x28)      /* (CAN_T2_8) Tx Buffer Element Data Offset */
+#define CAN_T2_9_REG_OFST              _UINT32_(0x2C)      /* (CAN_T2_9) Tx Buffer Element Data Offset */
+#define CAN_T2_10_REG_OFST             _UINT32_(0x30)      /* (CAN_T2_10) Tx Buffer Element Data Offset */
+#define CAN_T2_11_REG_OFST             _UINT32_(0x34)      /* (CAN_T2_11) Tx Buffer Element Data Offset */
+#define CAN_T2_12_REG_OFST             _UINT32_(0x38)      /* (CAN_T2_12) Tx Buffer Element Data Offset */
+#define CAN_T2_13_REG_OFST             _UINT32_(0x3C)      /* (CAN_T2_13) Tx Buffer Element Data Offset */
+#define CAN_T2_14_REG_OFST             _UINT32_(0x40)      /* (CAN_T2_14) Tx Buffer Element Data Offset */
+#define CAN_T2_15_REG_OFST             _UINT32_(0x44)      /* (CAN_T2_15) Tx Buffer Element Data Offset */
+#define CAN_E0_REG_OFST                _UINT32_(0x00)      /* (CAN_E0) Tx Event FIFO Element 0 Offset */
+#define CAN_E1_REG_OFST                _UINT32_(0x04)      /* (CAN_E1) Tx Event FIFO Element 1 Offset */
+#define CAN_F0_REG_OFST                _UINT32_(0x00)      /* (CAN_F0) Extended Message ID Filter Element 0 Offset */
+#define CAN_F1_REG_OFST                _UINT32_(0x04)      /* (CAN_F1) Extended Message ID Filter Element 1 Offset */
+#define CAN_CTRLA_REG_OFST             _UINT32_(0x00)      /* (CAN_CTRLA) Control A Register Offset */
+#define CAN_CTRLB_REG_OFST             _UINT32_(0x04)      /* (CAN_CTRLB) Control B Register Offset */
+#define CAN_INTENCLR_REG_OFST          _UINT32_(0x28)      /* (CAN_INTENCLR) Interrupt Enable Clear register Offset */
+#define CAN_INTENSET_REG_OFST          _UINT32_(0x2C)      /* (CAN_INTENSET) Interrupt Enable Set register Offset */
+#define CAN_INTFLAG_REG_OFST           _UINT32_(0x30)      /* (CAN_INTFLAG) Interrupt Flag Status and Clear register Offset */
+#define CAN_INTFLAGSET_REG_OFST        _UINT32_(0x34)      /* (CAN_INTFLAGSET) Interrupt Flag Software Set Register Offset */
+#define CAN_SYNCBUSY_REG_OFST          _UINT32_(0x5C)      /* (CAN_SYNCBUSY) SYNCBUSY Register Offset */
+#define CAN_CREL_MCAN_REG_OFST         _UINT32_(0x100)     /* (CAN_CREL_MCAN) Core Release Offset */
+#define CAN_ENDN_REG_OFST              _UINT32_(0x104)     /* (CAN_ENDN) Endian Offset */
+#define CAN_CUST_REG_OFST              _UINT32_(0x108)     /* (CAN_CUST) Customer Register Offset */
+#define CAN_DBTP_REG_OFST              _UINT32_(0x10C)     /* (CAN_DBTP) Fast Bit Timing and Prescaler Offset */
+#define CAN_TEST_REG_OFST              _UINT32_(0x110)     /* (CAN_TEST) Test Offset */
+#define CAN_RWD_REG_OFST               _UINT32_(0x114)     /* (CAN_RWD) RAM Watchdog Offset */
+#define CAN_CCCR_REG_OFST              _UINT32_(0x118)     /* (CAN_CCCR) CC Control Offset */
+#define CAN_NBTP_REG_OFST              _UINT32_(0x11C)     /* (CAN_NBTP) Nominal Bit Timing and Prescaler Offset */
+#define CAN_TSCC_REG_OFST              _UINT32_(0x120)     /* (CAN_TSCC) Timestamp Counter Configuration Offset */
+#define CAN_TSCV_REG_OFST              _UINT32_(0x124)     /* (CAN_TSCV) Timestamp Counter Value Offset */
+#define CAN_TOCC_REG_OFST              _UINT32_(0x128)     /* (CAN_TOCC) Timeout Counter Configuration Offset */
+#define CAN_TOCV_REG_OFST              _UINT32_(0x12C)     /* (CAN_TOCV) Timeout Counter Value Offset */
+#define CAN_ECR_REG_OFST               _UINT32_(0x140)     /* (CAN_ECR) Error Counter Offset */
+#define CAN_PSR_REG_OFST               _UINT32_(0x144)     /* (CAN_PSR) Protocol Status Offset */
+#define CAN_TDCR_REG_OFST              _UINT32_(0x148)     /* (CAN_TDCR) Extended ID Filter Configuration Offset */
+#define CAN_IR_REG_OFST                _UINT32_(0x150)     /* (CAN_IR) Interrupt Offset */
+#define CAN_IE_REG_OFST                _UINT32_(0x154)     /* (CAN_IE) Interrupt Enable Offset */
+#define CAN_ILS_REG_OFST               _UINT32_(0x158)     /* (CAN_ILS) Interrupt Line Select Offset */
+#define CAN_ILE_REG_OFST               _UINT32_(0x15C)     /* (CAN_ILE) Interrupt Line Enable Offset */
+#define CAN_GFC_REG_OFST               _UINT32_(0x180)     /* (CAN_GFC) Global Filter Configuration Offset */
+#define CAN_SIDFC_REG_OFST             _UINT32_(0x184)     /* (CAN_SIDFC) Standard ID Filter Configuration Offset */
+#define CAN_XIDFC_REG_OFST             _UINT32_(0x188)     /* (CAN_XIDFC) Extended ID Filter Configuration Offset */
+#define CAN_XIDAM_REG_OFST             _UINT32_(0x190)     /* (CAN_XIDAM) Extended ID AND Mask Offset */
+#define CAN_HPMS_REG_OFST              _UINT32_(0x194)     /* (CAN_HPMS) High Priority Message Status Offset */
+#define CAN_NDAT1_REG_OFST             _UINT32_(0x198)     /* (CAN_NDAT1) New Data 1 Offset */
+#define CAN_NDAT2_REG_OFST             _UINT32_(0x19C)     /* (CAN_NDAT2) New Data 2 Offset */
+#define CAN_RXF0C_REG_OFST             _UINT32_(0x1A0)     /* (CAN_RXF0C) Rx FIFO 0 Configuration Offset */
+#define CAN_RXF0S_REG_OFST             _UINT32_(0x1A4)     /* (CAN_RXF0S) Rx FIFO 0 Status Offset */
+#define CAN_RXF0A_REG_OFST             _UINT32_(0x1A8)     /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Offset */
+#define CAN_RXBC_REG_OFST              _UINT32_(0x1AC)     /* (CAN_RXBC) Rx Buffer Configuration Offset */
+#define CAN_RXF1C_REG_OFST             _UINT32_(0x1B0)     /* (CAN_RXF1C) Rx FIFO 1 Configuration Offset */
+#define CAN_RXF1S_REG_OFST             _UINT32_(0x1B4)     /* (CAN_RXF1S) Rx FIFO 1 Status Offset */
+#define CAN_RXF1A_REG_OFST             _UINT32_(0x1B8)     /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Offset */
+#define CAN_RXESC_REG_OFST             _UINT32_(0x1BC)     /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Offset */
+#define CAN_TXBC_REG_OFST              _UINT32_(0x1C0)     /* (CAN_TXBC) Tx Buffer Configuration Offset */
+#define CAN_TXFQS_REG_OFST             _UINT32_(0x1C4)     /* (CAN_TXFQS) Tx FIFO / Queue Status Offset */
+#define CAN_TXESC_REG_OFST             _UINT32_(0x1C8)     /* (CAN_TXESC) Tx Buffer Element Size Configuration Offset */
+#define CAN_TXBRP_REG_OFST             _UINT32_(0x1CC)     /* (CAN_TXBRP) Tx Buffer Request Pending Offset */
+#define CAN_TXBAR_REG_OFST             _UINT32_(0x1D0)     /* (CAN_TXBAR) Tx Buffer Add Request Offset */
+#define CAN_TXBCR_REG_OFST             _UINT32_(0x1D4)     /* (CAN_TXBCR) Tx Buffer Cancellation Request Offset */
+#define CAN_TXBTO_REG_OFST             _UINT32_(0x1D8)     /* (CAN_TXBTO) Tx Buffer Transmission Occurred Offset */
+#define CAN_TXBCF_REG_OFST             _UINT32_(0x1DC)     /* (CAN_TXBCF) Tx Buffer Cancellation Finished Offset */
+#define CAN_TXBTIE_REG_OFST            _UINT32_(0x1E0)     /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Offset */
+#define CAN_TXBCIE_REG_OFST            _UINT32_(0x1E4)     /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Offset */
+#define CAN_TXEFC_REG_OFST             _UINT32_(0x1F0)     /* (CAN_TXEFC) Tx Event FIFO Configuration Offset */
+#define CAN_TXEFS_REG_OFST             _UINT32_(0x1F4)     /* (CAN_TXEFS) Tx Event FIFO Status Offset */
+#define CAN_TXEFA_REG_OFST             _UINT32_(0x1F8)     /* (CAN_TXEFA) Tx Event FIFO Acknowledge Offset */
+#define CAN_CREL_TSU_REG_OFST          _UINT32_(0x260)     /* (CAN_CREL_TSU) TSU CREL Offset */
+#define CAN_TSCFG_REG_OFST             _UINT32_(0x264)     /* (CAN_TSCFG) Timestamp Configuration Offset */
+#define CAN_TSS1_REG_OFST              _UINT32_(0x268)     /* (CAN_TSS1) Timestamp Status 1 Offset */
+#define CAN_TSS2_REG_OFST              _UINT32_(0x26C)     /* (CAN_TSS2) Timestamp Status 2 Offset */
+#define CAN_TS0_REG_OFST               _UINT32_(0x270)     /* (CAN_TS0) Timestamp 0 Offset */
+#define CAN_TS1_REG_OFST               _UINT32_(0x274)     /* (CAN_TS1) Timestamp 1 Offset */
+#define CAN_TS2_REG_OFST               _UINT32_(0x278)     /* (CAN_TS2) Timestamp 2 Offset */
+#define CAN_TS3_REG_OFST               _UINT32_(0x27C)     /* (CAN_TS3) Timestamp 3 Offset */
+#define CAN_TS4_REG_OFST               _UINT32_(0x280)     /* (CAN_TS4) Timestamp 4 Offset */
+#define CAN_TS5_REG_OFST               _UINT32_(0x284)     /* (CAN_TS5) Timestamp 5 Offset */
+#define CAN_TS6_REG_OFST               _UINT32_(0x288)     /* (CAN_TS6) Timestamp 6 Offset */
+#define CAN_TS7_REG_OFST               _UINT32_(0x28C)     /* (CAN_TS7) Timestamp 7 Offset */
+#define CAN_TS8_REG_OFST               _UINT32_(0x290)     /* (CAN_TS8) Timestamp 8 Offset */
+#define CAN_TS9_REG_OFST               _UINT32_(0x294)     /* (CAN_TS9) Timestamp 9 Offset */
+#define CAN_TS10_REG_OFST              _UINT32_(0x298)     /* (CAN_TS10) Timestamp 10 Offset */
+#define CAN_TS11_REG_OFST              _UINT32_(0x29C)     /* (CAN_TS11) Timestamp 11 Offset */
+#define CAN_TS12_REG_OFST              _UINT32_(0x2A0)     /* (CAN_TS12) Timestamp 12 Offset */
+#define CAN_TS13_REG_OFST              _UINT32_(0x2A4)     /* (CAN_TS13) Timestamp 13 Offset */
+#define CAN_TS14_REG_OFST              _UINT32_(0x2A8)     /* (CAN_TS14) Timestamp 14 Offset */
+#define CAN_TS15_REG_OFST              _UINT32_(0x2AC)     /* (CAN_TS15) Timestamp 15 Offset */
+#define CAN_ATB_REG_OFST               _UINT32_(0x2B0)     /* (CAN_ATB) Actual Timebase Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* CAN_MRAM_RXBE register API structure */
+typedef struct
+{  /* Control Area Network */
+  __IO  uint32_t                       CAN_R0;             /* Offset: 0x00 (R/W  32) Rx Buffer and FIFO Element 0 */
+  __IO  uint32_t                       CAN_R1;             /* Offset: 0x04 (R/W  32) Rx Buffer and FIFO Element 1 */
+  __IO  uint32_t                       CAN_R2[16];         /* Offset: 0x08 (R/W  32) Rx Buffer and FIFO Element Data */
+} can_mram_rxbe_registers_t
+#ifdef __GNUC__
+  __attribute__ ((aligned (4)))
+#endif
+;
+
+/* CAN_MRAM_SIDFE register API structure */
+typedef struct
+{  /* Control Area Network */
+  __IO  uint32_t                       CAN_S0;             /* Offset: 0x00 (R/W  32) Standard Message ID Filter Element */
+} can_mram_sidfe_registers_t
+#ifdef __GNUC__
+  __attribute__ ((aligned (4)))
+#endif
+;
+
+/* CAN_MRAM_TXBE register API structure */
+typedef struct
+{  /* Control Area Network */
+  __IO  uint32_t                       CAN_T0;             /* Offset: 0x00 (R/W  32) Tx Buffer Element 0 */
+  __IO  uint32_t                       CAN_T1;             /* Offset: 0x04 (R/W  32) Tx Buffer Element 1 */
+  __IO  uint32_t                       CAN_T2[16];         /* Offset: 0x08 (R/W  32) Tx Buffer Element Data */
+} can_mram_txbe_registers_t
+#ifdef __GNUC__
+  __attribute__ ((aligned (4)))
+#endif
+;
+
+/* CAN_MRAM_TXEFE register API structure */
+typedef struct
+{  /* Control Area Network */
+  __IO  uint32_t                       CAN_E0;             /* Offset: 0x00 (R/W  32) Tx Event FIFO Element 0 */
+  __IO  uint32_t                       CAN_E1;             /* Offset: 0x04 (R/W  32) Tx Event FIFO Element 1 */
+} can_mram_txefe_registers_t
+#ifdef __GNUC__
+  __attribute__ ((aligned (4)))
+#endif
+;
+
+/* CAN_MRAM_XIDFE register API structure */
+typedef struct
+{  /* Control Area Network */
+  __IO  uint32_t                       CAN_F0;             /* Offset: 0x00 (R/W  32) Extended Message ID Filter Element 0 */
+  __IO  uint32_t                       CAN_F1;             /* Offset: 0x04 (R/W  32) Extended Message ID Filter Element 1 */
+} can_mram_xidfe_registers_t
+#ifdef __GNUC__
+  __attribute__ ((aligned (4)))
+#endif
+;
+
+/* CAN register API structure */
+typedef struct
+{  /* Control Area Network */
+  __IO  uint32_t                       CAN_CTRLA;          /* Offset: 0x00 (R/W  32) Control A Register */
+  __IO  uint32_t                       CAN_CTRLB;          /* Offset: 0x04 (R/W  32) Control B Register */
+  __I   uint8_t                        Reserved1[0x20];
+  __IO  uint32_t                       CAN_INTENCLR;       /* Offset: 0x28 (R/W  32) Interrupt Enable Clear register */
+  __IO  uint32_t                       CAN_INTENSET;       /* Offset: 0x2C (R/W  32) Interrupt Enable Set register */
+  __IO  uint32_t                       CAN_INTFLAG;        /* Offset: 0x30 (R/W  32) Interrupt Flag Status and Clear register */
+  __IO  uint32_t                       CAN_INTFLAGSET;     /* Offset: 0x34 (R/W  32) Interrupt Flag Software Set Register */
+  __I   uint8_t                        Reserved2[0x24];
+  __I   uint32_t                       CAN_SYNCBUSY;       /* Offset: 0x5C (R/   32) SYNCBUSY Register */
+  __I   uint8_t                        Reserved3[0xA0];
+  __I   uint32_t                       CAN_CREL_MCAN;      /* Offset: 0x100 (R/   32) Core Release */
+  __I   uint32_t                       CAN_ENDN;           /* Offset: 0x104 (R/   32) Endian */
+  __IO  uint32_t                       CAN_CUST;           /* Offset: 0x108 (R/W  32) Customer Register */
+  __IO  uint32_t                       CAN_DBTP;           /* Offset: 0x10C (R/W  32) Fast Bit Timing and Prescaler */
+  __IO  uint32_t                       CAN_TEST;           /* Offset: 0x110 (R/W  32) Test */
+  __IO  uint32_t                       CAN_RWD;            /* Offset: 0x114 (R/W  32) RAM Watchdog */
+  __IO  uint32_t                       CAN_CCCR;           /* Offset: 0x118 (R/W  32) CC Control */
+  __IO  uint32_t                       CAN_NBTP;           /* Offset: 0x11C (R/W  32) Nominal Bit Timing and Prescaler */
+  __IO  uint32_t                       CAN_TSCC;           /* Offset: 0x120 (R/W  32) Timestamp Counter Configuration */
+  __I   uint32_t                       CAN_TSCV;           /* Offset: 0x124 (R/   32) Timestamp Counter Value */
+  __IO  uint32_t                       CAN_TOCC;           /* Offset: 0x128 (R/W  32) Timeout Counter Configuration */
+  __IO  uint32_t                       CAN_TOCV;           /* Offset: 0x12C (R/W  32) Timeout Counter Value */
+  __I   uint8_t                        Reserved4[0x10];
+  __I   uint32_t                       CAN_ECR;            /* Offset: 0x140 (R/   32) Error Counter */
+  __I   uint32_t                       CAN_PSR;            /* Offset: 0x144 (R/   32) Protocol Status */
+  __IO  uint32_t                       CAN_TDCR;           /* Offset: 0x148 (R/W  32) Extended ID Filter Configuration */
+  __I   uint8_t                        Reserved5[0x04];
+  __IO  uint32_t                       CAN_IR;             /* Offset: 0x150 (R/W  32) Interrupt */
+  __IO  uint32_t                       CAN_IE;             /* Offset: 0x154 (R/W  32) Interrupt Enable */
+  __IO  uint32_t                       CAN_ILS;            /* Offset: 0x158 (R/W  32) Interrupt Line Select */
+  __IO  uint32_t                       CAN_ILE;            /* Offset: 0x15C (R/W  32) Interrupt Line Enable */
+  __I   uint8_t                        Reserved6[0x20];
+  __IO  uint32_t                       CAN_GFC;            /* Offset: 0x180 (R/W  32) Global Filter Configuration */
+  __IO  uint32_t                       CAN_SIDFC;          /* Offset: 0x184 (R/W  32) Standard ID Filter Configuration */
+  __IO  uint32_t                       CAN_XIDFC;          /* Offset: 0x188 (R/W  32) Extended ID Filter Configuration */
+  __I   uint8_t                        Reserved7[0x04];
+  __IO  uint32_t                       CAN_XIDAM;          /* Offset: 0x190 (R/W  32) Extended ID AND Mask */
+  __I   uint32_t                       CAN_HPMS;           /* Offset: 0x194 (R/   32) High Priority Message Status */
+  __IO  uint32_t                       CAN_NDAT1;          /* Offset: 0x198 (R/W  32) New Data 1 */
+  __IO  uint32_t                       CAN_NDAT2;          /* Offset: 0x19C (R/W  32) New Data 2 */
+  __IO  uint32_t                       CAN_RXF0C;          /* Offset: 0x1A0 (R/W  32) Rx FIFO 0 Configuration */
+  __I   uint32_t                       CAN_RXF0S;          /* Offset: 0x1A4 (R/   32) Rx FIFO 0 Status */
+  __IO  uint32_t                       CAN_RXF0A;          /* Offset: 0x1A8 (R/W  32) Rx FIFO 0 Acknowledge */
+  __IO  uint32_t                       CAN_RXBC;           /* Offset: 0x1AC (R/W  32) Rx Buffer Configuration */
+  __IO  uint32_t                       CAN_RXF1C;          /* Offset: 0x1B0 (R/W  32) Rx FIFO 1 Configuration */
+  __I   uint32_t                       CAN_RXF1S;          /* Offset: 0x1B4 (R/   32) Rx FIFO 1 Status */
+  __IO  uint32_t                       CAN_RXF1A;          /* Offset: 0x1B8 (R/W  32) Rx FIFO 1 Acknowledge */
+  __IO  uint32_t                       CAN_RXESC;          /* Offset: 0x1BC (R/W  32) Rx Buffer / FIFO Element Size Configuration */
+  __IO  uint32_t                       CAN_TXBC;           /* Offset: 0x1C0 (R/W  32) Tx Buffer Configuration */
+  __I   uint32_t                       CAN_TXFQS;          /* Offset: 0x1C4 (R/   32) Tx FIFO / Queue Status */
+  __IO  uint32_t                       CAN_TXESC;          /* Offset: 0x1C8 (R/W  32) Tx Buffer Element Size Configuration */
+  __I   uint32_t                       CAN_TXBRP;          /* Offset: 0x1CC (R/   32) Tx Buffer Request Pending */
+  __IO  uint32_t                       CAN_TXBAR;          /* Offset: 0x1D0 (R/W  32) Tx Buffer Add Request */
+  __IO  uint32_t                       CAN_TXBCR;          /* Offset: 0x1D4 (R/W  32) Tx Buffer Cancellation Request */
+  __I   uint32_t                       CAN_TXBTO;          /* Offset: 0x1D8 (R/   32) Tx Buffer Transmission Occurred */
+  __I   uint32_t                       CAN_TXBCF;          /* Offset: 0x1DC (R/   32) Tx Buffer Cancellation Finished */
+  __IO  uint32_t                       CAN_TXBTIE;         /* Offset: 0x1E0 (R/W  32) Tx Buffer Transmission Interrupt Enable */
+  __IO  uint32_t                       CAN_TXBCIE;         /* Offset: 0x1E4 (R/W  32) Tx Buffer Cancellation Finished Interrupt Enable */
+  __I   uint8_t                        Reserved8[0x08];
+  __IO  uint32_t                       CAN_TXEFC;          /* Offset: 0x1F0 (R/W  32) Tx Event FIFO Configuration */
+  __I   uint32_t                       CAN_TXEFS;          /* Offset: 0x1F4 (R/   32) Tx Event FIFO Status */
+  __IO  uint32_t                       CAN_TXEFA;          /* Offset: 0x1F8 (R/W  32) Tx Event FIFO Acknowledge */
+  __I   uint8_t                        Reserved9[0x64];
+  __I   uint32_t                       CAN_CREL_TSU;       /* Offset: 0x260 (R/   32) TSU CREL */
+  __IO  uint32_t                       CAN_TSCFG;          /* Offset: 0x264 (R/W  32) Timestamp Configuration */
+  __I   uint32_t                       CAN_TSS1;           /* Offset: 0x268 (R/   32) Timestamp Status 1 */
+  __I   uint32_t                       CAN_TSS2;           /* Offset: 0x26C (R/   32) Timestamp Status 2 */
+  __I   uint32_t                       CAN_TS0;            /* Offset: 0x270 (R/   32) Timestamp 0 */
+  __I   uint32_t                       CAN_TS1;            /* Offset: 0x274 (R/   32) Timestamp 1 */
+  __I   uint32_t                       CAN_TS2;            /* Offset: 0x278 (R/   32) Timestamp 2 */
+  __I   uint32_t                       CAN_TS3;            /* Offset: 0x27C (R/   32) Timestamp 3 */
+  __I   uint32_t                       CAN_TS4;            /* Offset: 0x280 (R/   32) Timestamp 4 */
+  __I   uint32_t                       CAN_TS5;            /* Offset: 0x284 (R/   32) Timestamp 5 */
+  __I   uint32_t                       CAN_TS6;            /* Offset: 0x288 (R/   32) Timestamp 6 */
+  __I   uint32_t                       CAN_TS7;            /* Offset: 0x28C (R/   32) Timestamp 7 */
+  __I   uint32_t                       CAN_TS8;            /* Offset: 0x290 (R/   32) Timestamp 8 */
+  __I   uint32_t                       CAN_TS9;            /* Offset: 0x294 (R/   32) Timestamp 9 */
+  __I   uint32_t                       CAN_TS10;           /* Offset: 0x298 (R/   32) Timestamp 10 */
+  __I   uint32_t                       CAN_TS11;           /* Offset: 0x29C (R/   32) Timestamp 11 */
+  __I   uint32_t                       CAN_TS12;           /* Offset: 0x2A0 (R/   32) Timestamp 12 */
+  __I   uint32_t                       CAN_TS13;           /* Offset: 0x2A4 (R/   32) Timestamp 13 */
+  __I   uint32_t                       CAN_TS14;           /* Offset: 0x2A8 (R/   32) Timestamp 14 */
+  __I   uint32_t                       CAN_TS15;           /* Offset: 0x2AC (R/   32) Timestamp 15 */
+  __IO  uint32_t                       CAN_ATB;            /* Offset: 0x2B0 (R/W  32) Actual Timebase */
+} can_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_CAN_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/ccl.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/ccl.h
new file mode 100644
index 00000000..16cd1f69
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/ccl.h
@@ -0,0 +1,234 @@
+/*
+ * Component description for CCL
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_CCL_COMPONENT_H_
+#define _PIC32CMGC00_CCL_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR CCL                       */
+/* ************************************************************************** */
+
+/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */
+#define CCL_CTRL_RESETVALUE                   _UINT8_(0x00)                                        /*  (CCL_CTRL) Control  Reset Value */
+
+#define CCL_CTRL_SWRST_Pos                    _UINT8_(0)                                           /* (CCL_CTRL) Software Reset Position */
+#define CCL_CTRL_SWRST_Msk                    (_UINT8_(0x1) << CCL_CTRL_SWRST_Pos)                 /* (CCL_CTRL) Software Reset Mask */
+#define CCL_CTRL_SWRST(value)                 (CCL_CTRL_SWRST_Msk & (_UINT8_(value) << CCL_CTRL_SWRST_Pos)) /* Assignment of value for SWRST in the CCL_CTRL register */
+#define   CCL_CTRL_SWRST_DISABLE_Val          _UINT8_(0x0)                                         /* (CCL_CTRL) The peripheral is not reset  */
+#define   CCL_CTRL_SWRST_ENABLE_Val           _UINT8_(0x1)                                         /* (CCL_CTRL) The peripheral is reset  */
+#define CCL_CTRL_SWRST_DISABLE                (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos)   /* (CCL_CTRL) The peripheral is not reset Position */
+#define CCL_CTRL_SWRST_ENABLE                 (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos)    /* (CCL_CTRL) The peripheral is reset Position */
+#define CCL_CTRL_ENABLE_Pos                   _UINT8_(1)                                           /* (CCL_CTRL) Enable Position */
+#define CCL_CTRL_ENABLE_Msk                   (_UINT8_(0x1) << CCL_CTRL_ENABLE_Pos)                /* (CCL_CTRL) Enable Mask */
+#define CCL_CTRL_ENABLE(value)                (CCL_CTRL_ENABLE_Msk & (_UINT8_(value) << CCL_CTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the CCL_CTRL register */
+#define   CCL_CTRL_ENABLE_DISABLE_Val         _UINT8_(0x0)                                         /* (CCL_CTRL) The peripheral is disabled  */
+#define   CCL_CTRL_ENABLE_ENABLE_Val          _UINT8_(0x1)                                         /* (CCL_CTRL) The peripheral is enabled  */
+#define CCL_CTRL_ENABLE_DISABLE               (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is disabled Position */
+#define CCL_CTRL_ENABLE_ENABLE                (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos)  /* (CCL_CTRL) The peripheral is enabled Position */
+#define CCL_CTRL_RUNSTDBY_Pos                 _UINT8_(6)                                           /* (CCL_CTRL) Run in Standby Position */
+#define CCL_CTRL_RUNSTDBY_Msk                 (_UINT8_(0x1) << CCL_CTRL_RUNSTDBY_Pos)              /* (CCL_CTRL) Run in Standby Mask */
+#define CCL_CTRL_RUNSTDBY(value)              (CCL_CTRL_RUNSTDBY_Msk & (_UINT8_(value) << CCL_CTRL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the CCL_CTRL register */
+#define   CCL_CTRL_RUNSTDBY_DISABLE_Val       _UINT8_(0x0)                                         /* (CCL_CTRL) Generic clock is not required in standby sleep mode  */
+#define   CCL_CTRL_RUNSTDBY_ENABLE_Val        _UINT8_(0x1)                                         /* (CCL_CTRL) Generic clock is  required in standby sleep mode  */
+#define CCL_CTRL_RUNSTDBY_DISABLE             (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is not required in standby sleep mode Position */
+#define CCL_CTRL_RUNSTDBY_ENABLE              (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is  required in standby sleep mode Position */
+#define CCL_CTRL_Msk                          _UINT8_(0x43)                                        /* (CCL_CTRL) Register Mask  */
+
+
+/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */
+#define CCL_SEQCTRL_RESETVALUE                _UINT8_(0x00)                                        /*  (CCL_SEQCTRL) SEQ Control x  Reset Value */
+
+#define CCL_SEQCTRL_SEQSEL_Pos                _UINT8_(0)                                           /* (CCL_SEQCTRL) Sequential Selection Position */
+#define CCL_SEQCTRL_SEQSEL_Msk                (_UINT8_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)             /* (CCL_SEQCTRL) Sequential Selection Mask */
+#define CCL_SEQCTRL_SEQSEL(value)             (CCL_SEQCTRL_SEQSEL_Msk & (_UINT8_(value) << CCL_SEQCTRL_SEQSEL_Pos)) /* Assignment of value for SEQSEL in the CCL_SEQCTRL register */
+#define   CCL_SEQCTRL_SEQSEL_DISABLE_Val      _UINT8_(0x0)                                         /* (CCL_SEQCTRL) Sequential logic is disabled  */
+#define   CCL_SEQCTRL_SEQSEL_DFF_Val          _UINT8_(0x1)                                         /* (CCL_SEQCTRL) D flip flop  */
+#define   CCL_SEQCTRL_SEQSEL_JK_Val           _UINT8_(0x2)                                         /* (CCL_SEQCTRL) JK flip flop  */
+#define   CCL_SEQCTRL_SEQSEL_LATCH_Val        _UINT8_(0x3)                                         /* (CCL_SEQCTRL) D latch  */
+#define   CCL_SEQCTRL_SEQSEL_RS_Val           _UINT8_(0x4)                                         /* (CCL_SEQCTRL) RS latch  */
+#define CCL_SEQCTRL_SEQSEL_DISABLE            (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential logic is disabled Position */
+#define CCL_SEQCTRL_SEQSEL_DFF                (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D flip flop Position */
+#define CCL_SEQCTRL_SEQSEL_JK                 (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) JK flip flop Position */
+#define CCL_SEQCTRL_SEQSEL_LATCH              (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D latch Position */
+#define CCL_SEQCTRL_SEQSEL_RS                 (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) RS latch Position */
+#define CCL_SEQCTRL_Msk                       _UINT8_(0x0F)                                        /* (CCL_SEQCTRL) Register Mask  */
+
+
+/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */
+#define CCL_LUTCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (CCL_LUTCTRL) LUT Control x  Reset Value */
+
+#define CCL_LUTCTRL_ENABLE_Pos                _UINT32_(1)                                          /* (CCL_LUTCTRL) LUT Enable Position */
+#define CCL_LUTCTRL_ENABLE_Msk                (_UINT32_(0x1) << CCL_LUTCTRL_ENABLE_Pos)            /* (CCL_LUTCTRL) LUT Enable Mask */
+#define CCL_LUTCTRL_ENABLE(value)             (CCL_LUTCTRL_ENABLE_Msk & (_UINT32_(value) << CCL_LUTCTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the CCL_LUTCTRL register */
+#define   CCL_LUTCTRL_ENABLE_DISABLE_Val      _UINT32_(0x0)                                        /* (CCL_LUTCTRL) LUT block is disabled  */
+#define   CCL_LUTCTRL_ENABLE_ENABLE_Val       _UINT32_(0x1)                                        /* (CCL_LUTCTRL) LUT block is enabled  */
+#define CCL_LUTCTRL_ENABLE_DISABLE            (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is disabled Position */
+#define CCL_LUTCTRL_ENABLE_ENABLE             (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is enabled Position */
+#define CCL_LUTCTRL_FILTSEL_Pos               _UINT32_(4)                                          /* (CCL_LUTCTRL) Filter Selection Position */
+#define CCL_LUTCTRL_FILTSEL_Msk               (_UINT32_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)           /* (CCL_LUTCTRL) Filter Selection Mask */
+#define CCL_LUTCTRL_FILTSEL(value)            (CCL_LUTCTRL_FILTSEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_FILTSEL_Pos)) /* Assignment of value for FILTSEL in the CCL_LUTCTRL register */
+#define   CCL_LUTCTRL_FILTSEL_DISABLE_Val     _UINT32_(0x0)                                        /* (CCL_LUTCTRL) Filter disabled  */
+#define   CCL_LUTCTRL_FILTSEL_SYNCH_Val       _UINT32_(0x1)                                        /* (CCL_LUTCTRL) Synchronizer enabled  */
+#define   CCL_LUTCTRL_FILTSEL_FILTER_Val      _UINT32_(0x2)                                        /* (CCL_LUTCTRL) Filter enabled  */
+#define CCL_LUTCTRL_FILTSEL_DISABLE           (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter disabled Position */
+#define CCL_LUTCTRL_FILTSEL_SYNCH             (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Synchronizer enabled Position */
+#define CCL_LUTCTRL_FILTSEL_FILTER            (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter enabled Position */
+#define CCL_LUTCTRL_EDGESEL_Pos               _UINT32_(7)                                          /* (CCL_LUTCTRL) Edge Selection Position */
+#define CCL_LUTCTRL_EDGESEL_Msk               (_UINT32_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)           /* (CCL_LUTCTRL) Edge Selection Mask */
+#define CCL_LUTCTRL_EDGESEL(value)            (CCL_LUTCTRL_EDGESEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_EDGESEL_Pos)) /* Assignment of value for EDGESEL in the CCL_LUTCTRL register */
+#define   CCL_LUTCTRL_EDGESEL_DISABLE_Val     _UINT32_(0x0)                                        /* (CCL_LUTCTRL) Edge detector is disabled  */
+#define   CCL_LUTCTRL_EDGESEL_ENABLE_Val      _UINT32_(0x1)                                        /* (CCL_LUTCTRL) Edge detector is enabled  */
+#define CCL_LUTCTRL_EDGESEL_DISABLE           (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is disabled Position */
+#define CCL_LUTCTRL_EDGESEL_ENABLE            (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is enabled Position */
+#define CCL_LUTCTRL_INSEL0_Pos                _UINT32_(8)                                          /* (CCL_LUTCTRL) Input Selection 0 Position */
+#define CCL_LUTCTRL_INSEL0_Msk                (_UINT32_(0xF) << CCL_LUTCTRL_INSEL0_Pos)            /* (CCL_LUTCTRL) Input Selection 0 Mask */
+#define CCL_LUTCTRL_INSEL0(value)             (CCL_LUTCTRL_INSEL0_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL0_Pos)) /* Assignment of value for INSEL0 in the CCL_LUTCTRL register */
+#define   CCL_LUTCTRL_INSEL0_MASK_Val         _UINT32_(0x0)                                        /* (CCL_LUTCTRL) Masked input  */
+#define   CCL_LUTCTRL_INSEL0_FEEDBACK_Val     _UINT32_(0x1)                                        /* (CCL_LUTCTRL) Feedback input source  */
+#define   CCL_LUTCTRL_INSEL0_LINK_Val         _UINT32_(0x2)                                        /* (CCL_LUTCTRL) Linked LUT input source  */
+#define   CCL_LUTCTRL_INSEL0_EVENT_Val        _UINT32_(0x3)                                        /* (CCL_LUTCTRL) Event input source  */
+#define   CCL_LUTCTRL_INSEL0_IO_Val           _UINT32_(0x4)                                        /* (CCL_LUTCTRL) I/O pin input source  */
+#define   CCL_LUTCTRL_INSEL0_PERSEL0_Val      _UINT32_(0x5)                                        /* (CCL_LUTCTRL) Peripheral 0 input source  */
+#define   CCL_LUTCTRL_INSEL0_PERSEL1_Val      _UINT32_(0x6)                                        /* (CCL_LUTCTRL) Peripheral 1 input source  */
+#define   CCL_LUTCTRL_INSEL0_PERSEL2_Val      _UINT32_(0x7)                                        /* (CCL_LUTCTRL) Peripheral 2 input source  */
+#define   CCL_LUTCTRL_INSEL0_PERSEL3_Val      _UINT32_(0x8)                                        /* (CCL_LUTCTRL) Peripheral 3 input source  */
+#define   CCL_LUTCTRL_INSEL0_PERSEL4_Val      _UINT32_(0x9)                                        /* (CCL_LUTCTRL) Peripheral 4 input source  */
+#define   CCL_LUTCTRL_INSEL0_PERSEL5_Val      _UINT32_(0xA)                                        /* (CCL_LUTCTRL) Peripheral 5 input source  */
+#define   CCL_LUTCTRL_INSEL0_ASYNCEVENT_Val   _UINT32_(0xB)                                        /* (CCL_LUTCTRL) Asynchronous event input source. The EVENT input will bypass edge detection logic.  */
+#define CCL_LUTCTRL_INSEL0_MASK               (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Masked input Position */
+#define CCL_LUTCTRL_INSEL0_FEEDBACK           (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Feedback input source Position */
+#define CCL_LUTCTRL_INSEL0_LINK               (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */
+#define CCL_LUTCTRL_INSEL0_EVENT              (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Event input source Position */
+#define CCL_LUTCTRL_INSEL0_IO                 (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */
+#define CCL_LUTCTRL_INSEL0_PERSEL0            (CCL_LUTCTRL_INSEL0_PERSEL0_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Peripheral 0 input source Position */
+#define CCL_LUTCTRL_INSEL0_PERSEL1            (CCL_LUTCTRL_INSEL0_PERSEL1_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Peripheral 1 input source Position */
+#define CCL_LUTCTRL_INSEL0_PERSEL2            (CCL_LUTCTRL_INSEL0_PERSEL2_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Peripheral 2 input source Position */
+#define CCL_LUTCTRL_INSEL0_PERSEL3            (CCL_LUTCTRL_INSEL0_PERSEL3_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Peripheral 3 input source Position */
+#define CCL_LUTCTRL_INSEL0_PERSEL4            (CCL_LUTCTRL_INSEL0_PERSEL4_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Peripheral 4 input source Position */
+#define CCL_LUTCTRL_INSEL0_PERSEL5            (CCL_LUTCTRL_INSEL0_PERSEL5_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Peripheral 5 input source Position */
+#define CCL_LUTCTRL_INSEL0_ASYNCEVENT         (CCL_LUTCTRL_INSEL0_ASYNCEVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Asynchronous event input source. The EVENT input will bypass edge detection logic. Position */
+#define CCL_LUTCTRL_INSEL1_Pos                _UINT32_(12)                                         /* (CCL_LUTCTRL) Input Selection 1 Position */
+#define CCL_LUTCTRL_INSEL1_Msk                (_UINT32_(0xF) << CCL_LUTCTRL_INSEL1_Pos)            /* (CCL_LUTCTRL) Input Selection 1 Mask */
+#define CCL_LUTCTRL_INSEL1(value)             (CCL_LUTCTRL_INSEL1_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL1_Pos)) /* Assignment of value for INSEL1 in the CCL_LUTCTRL register */
+#define   CCL_LUTCTRL_INSEL1_MASK_Val         _UINT32_(0x0)                                        /* (CCL_LUTCTRL) Masked input  */
+#define   CCL_LUTCTRL_INSEL1_FEEDBACK_Val     _UINT32_(0x1)                                        /* (CCL_LUTCTRL) Feedback input source  */
+#define   CCL_LUTCTRL_INSEL1_LINK_Val         _UINT32_(0x2)                                        /* (CCL_LUTCTRL) Linked LUT input source  */
+#define   CCL_LUTCTRL_INSEL1_EVENT_Val        _UINT32_(0x3)                                        /* (CCL_LUTCTRL) Event input source  */
+#define   CCL_LUTCTRL_INSEL1_IO_Val           _UINT32_(0x4)                                        /* (CCL_LUTCTRL) I/O pin input source  */
+#define   CCL_LUTCTRL_INSEL1_PERSEL0_Val      _UINT32_(0x5)                                        /* (CCL_LUTCTRL) Peripheral 0 input source  */
+#define   CCL_LUTCTRL_INSEL1_PERSEL1_Val      _UINT32_(0x6)                                        /* (CCL_LUTCTRL) Peripheral 1 input source  */
+#define   CCL_LUTCTRL_INSEL1_PERSEL2_Val      _UINT32_(0x7)                                        /* (CCL_LUTCTRL) Peripheral 2 input source  */
+#define   CCL_LUTCTRL_INSEL1_PERSEL3_Val      _UINT32_(0x8)                                        /* (CCL_LUTCTRL) Peripheral 3 input source  */
+#define   CCL_LUTCTRL_INSEL1_PERSEL4_Val      _UINT32_(0x9)                                        /* (CCL_LUTCTRL) Peripheral 4 input source  */
+#define   CCL_LUTCTRL_INSEL1_PERSEL5_Val      _UINT32_(0xA)                                        /* (CCL_LUTCTRL) Peripheral 5 input source  */
+#define   CCL_LUTCTRL_INSEL1_ASYNCEVENT_Val   _UINT32_(0xB)                                        /* (CCL_LUTCTRL) Asynchronous event input source. The EVENT input will bypass edge detection logic.  */
+#define CCL_LUTCTRL_INSEL1_MASK               (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Masked input Position */
+#define CCL_LUTCTRL_INSEL1_FEEDBACK           (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Feedback input source Position */
+#define CCL_LUTCTRL_INSEL1_LINK               (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */
+#define CCL_LUTCTRL_INSEL1_EVENT              (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Event input source Position */
+#define CCL_LUTCTRL_INSEL1_IO                 (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */
+#define CCL_LUTCTRL_INSEL1_PERSEL0            (CCL_LUTCTRL_INSEL1_PERSEL0_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Peripheral 0 input source Position */
+#define CCL_LUTCTRL_INSEL1_PERSEL1            (CCL_LUTCTRL_INSEL1_PERSEL1_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Peripheral 1 input source Position */
+#define CCL_LUTCTRL_INSEL1_PERSEL2            (CCL_LUTCTRL_INSEL1_PERSEL2_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Peripheral 2 input source Position */
+#define CCL_LUTCTRL_INSEL1_PERSEL3            (CCL_LUTCTRL_INSEL1_PERSEL3_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Peripheral 3 input source Position */
+#define CCL_LUTCTRL_INSEL1_PERSEL4            (CCL_LUTCTRL_INSEL1_PERSEL4_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Peripheral 4 input source Position */
+#define CCL_LUTCTRL_INSEL1_PERSEL5            (CCL_LUTCTRL_INSEL1_PERSEL5_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Peripheral 5 input source Position */
+#define CCL_LUTCTRL_INSEL1_ASYNCEVENT         (CCL_LUTCTRL_INSEL1_ASYNCEVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Asynchronous event input source. The EVENT input will bypass edge detection logic. Position */
+#define CCL_LUTCTRL_INSEL2_Pos                _UINT32_(16)                                         /* (CCL_LUTCTRL) Input Selection 2 Position */
+#define CCL_LUTCTRL_INSEL2_Msk                (_UINT32_(0xF) << CCL_LUTCTRL_INSEL2_Pos)            /* (CCL_LUTCTRL) Input Selection 2 Mask */
+#define CCL_LUTCTRL_INSEL2(value)             (CCL_LUTCTRL_INSEL2_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL2_Pos)) /* Assignment of value for INSEL2 in the CCL_LUTCTRL register */
+#define   CCL_LUTCTRL_INSEL2_MASK_Val         _UINT32_(0x0)                                        /* (CCL_LUTCTRL) Masked input  */
+#define   CCL_LUTCTRL_INSEL2_FEEDBACK_Val     _UINT32_(0x1)                                        /* (CCL_LUTCTRL) Feedback input source  */
+#define   CCL_LUTCTRL_INSEL2_LINK_Val         _UINT32_(0x2)                                        /* (CCL_LUTCTRL) Linked LUT input source  */
+#define   CCL_LUTCTRL_INSEL2_EVENT_Val        _UINT32_(0x3)                                        /* (CCL_LUTCTRL) Event input source  */
+#define   CCL_LUTCTRL_INSEL2_IO_Val           _UINT32_(0x4)                                        /* (CCL_LUTCTRL) I/O pin input source  */
+#define   CCL_LUTCTRL_INSEL2_PERSEL0_Val      _UINT32_(0x5)                                        /* (CCL_LUTCTRL) Peripheral 0 input source  */
+#define   CCL_LUTCTRL_INSEL2_PERSEL1_Val      _UINT32_(0x6)                                        /* (CCL_LUTCTRL) Peripheral 1 input source  */
+#define   CCL_LUTCTRL_INSEL2_PERSEL2_Val      _UINT32_(0x7)                                        /* (CCL_LUTCTRL) Peripheral 2 input source  */
+#define   CCL_LUTCTRL_INSEL2_PERSEL3_Val      _UINT32_(0x8)                                        /* (CCL_LUTCTRL) Peripheral 3 input source  */
+#define   CCL_LUTCTRL_INSEL2_PERSEL4_Val      _UINT32_(0x9)                                        /* (CCL_LUTCTRL) Peripheral 4 input source  */
+#define   CCL_LUTCTRL_INSEL2_PERSEL5_Val      _UINT32_(0xA)                                        /* (CCL_LUTCTRL) Peripheral 5 input source  */
+#define   CCL_LUTCTRL_INSEL2_ASYNCEVENT_Val   _UINT32_(0xB)                                        /* (CCL_LUTCTRL) Asynchronous event input source. The EVENT input will bypass edge detection logic.  */
+#define CCL_LUTCTRL_INSEL2_MASK               (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Masked input Position */
+#define CCL_LUTCTRL_INSEL2_FEEDBACK           (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Feedback input source Position */
+#define CCL_LUTCTRL_INSEL2_LINK               (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */
+#define CCL_LUTCTRL_INSEL2_EVENT              (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Event input source Position */
+#define CCL_LUTCTRL_INSEL2_IO                 (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */
+#define CCL_LUTCTRL_INSEL2_PERSEL0            (CCL_LUTCTRL_INSEL2_PERSEL0_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Peripheral 0 input source Position */
+#define CCL_LUTCTRL_INSEL2_PERSEL1            (CCL_LUTCTRL_INSEL2_PERSEL1_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Peripheral 1 input source Position */
+#define CCL_LUTCTRL_INSEL2_PERSEL2            (CCL_LUTCTRL_INSEL2_PERSEL2_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Peripheral 2 input source Position */
+#define CCL_LUTCTRL_INSEL2_PERSEL3            (CCL_LUTCTRL_INSEL2_PERSEL3_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Peripheral 3 input source Position */
+#define CCL_LUTCTRL_INSEL2_PERSEL4            (CCL_LUTCTRL_INSEL2_PERSEL4_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Peripheral 4 input source Position */
+#define CCL_LUTCTRL_INSEL2_PERSEL5            (CCL_LUTCTRL_INSEL2_PERSEL5_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Peripheral 5 input source Position */
+#define CCL_LUTCTRL_INSEL2_ASYNCEVENT         (CCL_LUTCTRL_INSEL2_ASYNCEVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Asynchronous event input source. The EVENT input will bypass edge detection logic. Position */
+#define CCL_LUTCTRL_INVEI_Pos                 _UINT32_(20)                                         /* (CCL_LUTCTRL) Inverted Event Input Enable Position */
+#define CCL_LUTCTRL_INVEI_Msk                 (_UINT32_(0x1) << CCL_LUTCTRL_INVEI_Pos)             /* (CCL_LUTCTRL) Inverted Event Input Enable Mask */
+#define CCL_LUTCTRL_INVEI(value)              (CCL_LUTCTRL_INVEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_INVEI_Pos)) /* Assignment of value for INVEI in the CCL_LUTCTRL register */
+#define   CCL_LUTCTRL_INVEI_NORMAL_Val        _UINT32_(0x0)                                        /* (CCL_LUTCTRL) Incoming event is not inverted  */
+#define   CCL_LUTCTRL_INVEI_INVERTED_Val      _UINT32_(0x1)                                        /* (CCL_LUTCTRL) Incoming event is inverted  */
+#define CCL_LUTCTRL_INVEI_NORMAL              (CCL_LUTCTRL_INVEI_NORMAL_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is not inverted Position */
+#define CCL_LUTCTRL_INVEI_INVERTED            (CCL_LUTCTRL_INVEI_INVERTED_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is inverted Position */
+#define CCL_LUTCTRL_LUTEI_Pos                 _UINT32_(21)                                         /* (CCL_LUTCTRL) LUT Event Input Enable Position */
+#define CCL_LUTCTRL_LUTEI_Msk                 (_UINT32_(0x1) << CCL_LUTCTRL_LUTEI_Pos)             /* (CCL_LUTCTRL) LUT Event Input Enable Mask */
+#define CCL_LUTCTRL_LUTEI(value)              (CCL_LUTCTRL_LUTEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEI_Pos)) /* Assignment of value for LUTEI in the CCL_LUTCTRL register */
+#define   CCL_LUTCTRL_LUTEI_DISABLE_Val       _UINT32_(0x0)                                        /* (CCL_LUTCTRL) LUT incoming event is disabled  */
+#define   CCL_LUTCTRL_LUTEI_ENABLE_Val        _UINT32_(0x1)                                        /* (CCL_LUTCTRL) LUT incoming event is enabled  */
+#define CCL_LUTCTRL_LUTEI_DISABLE             (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is disabled Position */
+#define CCL_LUTCTRL_LUTEI_ENABLE              (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is enabled Position */
+#define CCL_LUTCTRL_LUTEO_Pos                 _UINT32_(22)                                         /* (CCL_LUTCTRL) LUT Event Output Enable Position */
+#define CCL_LUTCTRL_LUTEO_Msk                 (_UINT32_(0x1) << CCL_LUTCTRL_LUTEO_Pos)             /* (CCL_LUTCTRL) LUT Event Output Enable Mask */
+#define CCL_LUTCTRL_LUTEO(value)              (CCL_LUTCTRL_LUTEO_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEO_Pos)) /* Assignment of value for LUTEO in the CCL_LUTCTRL register */
+#define   CCL_LUTCTRL_LUTEO_DISABLE_Val       _UINT32_(0x0)                                        /* (CCL_LUTCTRL) LUT event output is disabled  */
+#define   CCL_LUTCTRL_LUTEO_ENABLE_Val        _UINT32_(0x1)                                        /* (CCL_LUTCTRL) LUT event output is enabled  */
+#define CCL_LUTCTRL_LUTEO_DISABLE             (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is disabled Position */
+#define CCL_LUTCTRL_LUTEO_ENABLE              (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is enabled Position */
+#define CCL_LUTCTRL_TRUTH_Pos                 _UINT32_(24)                                         /* (CCL_LUTCTRL) Truth Value Position */
+#define CCL_LUTCTRL_TRUTH_Msk                 (_UINT32_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)            /* (CCL_LUTCTRL) Truth Value Mask */
+#define CCL_LUTCTRL_TRUTH(value)              (CCL_LUTCTRL_TRUTH_Msk & (_UINT32_(value) << CCL_LUTCTRL_TRUTH_Pos)) /* Assignment of value for TRUTH in the CCL_LUTCTRL register */
+#define CCL_LUTCTRL_Msk                       _UINT32_(0xFF7FFFB2)                                 /* (CCL_LUTCTRL) Register Mask  */
+
+
+/* CCL register offsets definitions */
+#define CCL_CTRL_REG_OFST              _UINT32_(0x00)      /* (CCL_CTRL) Control Offset */
+#define CCL_SEQCTRL_REG_OFST           _UINT32_(0x04)      /* (CCL_SEQCTRL) SEQ Control x Offset */
+#define CCL_SEQCTRL0_REG_OFST          _UINT32_(0x04)      /* (CCL_SEQCTRL0) SEQ Control x Offset */
+#define CCL_SEQCTRL1_REG_OFST          _UINT32_(0x05)      /* (CCL_SEQCTRL1) SEQ Control x Offset */
+#define CCL_LUTCTRL_REG_OFST           _UINT32_(0x08)      /* (CCL_LUTCTRL) LUT Control x Offset */
+#define CCL_LUTCTRL0_REG_OFST          _UINT32_(0x08)      /* (CCL_LUTCTRL0) LUT Control x Offset */
+#define CCL_LUTCTRL1_REG_OFST          _UINT32_(0x0C)      /* (CCL_LUTCTRL1) LUT Control x Offset */
+#define CCL_LUTCTRL2_REG_OFST          _UINT32_(0x10)      /* (CCL_LUTCTRL2) LUT Control x Offset */
+#define CCL_LUTCTRL3_REG_OFST          _UINT32_(0x14)      /* (CCL_LUTCTRL3) LUT Control x Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* CCL register API structure */
+typedef struct
+{  /* Configurable Custom Logic */
+  __IO  uint8_t                        CCL_CTRL;           /* Offset: 0x00 (R/W  8) Control */
+  __I   uint8_t                        Reserved1[0x03];
+  __IO  uint8_t                        CCL_SEQCTRL[2];     /* Offset: 0x04 (R/W  8) SEQ Control x */
+  __I   uint8_t                        Reserved2[0x02];
+  __IO  uint32_t                       CCL_LUTCTRL[4];     /* Offset: 0x08 (R/W  32) LUT Control x */
+} ccl_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_CCL_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/dmac.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/dmac.h
new file mode 100644
index 00000000..f28c0349
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/dmac.h
@@ -0,0 +1,725 @@
+/*
+ * Component description for DMAC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_DMAC_COMPONENT_H_
+#define _PIC32CMGC00_DMAC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR DMAC                      */
+/* ************************************************************************** */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#define DMAC_BTCTRL_RESETVALUE                _UINT16_(0x00)                                       /*  (DMAC_BTCTRL) Block Transfer Control  Reset Value */
+
+#define DMAC_BTCTRL_VALID_Pos                 _UINT16_(0)                                          /* (DMAC_BTCTRL) Descriptor Valid Position */
+#define DMAC_BTCTRL_VALID_Msk                 (_UINT16_(0x1) << DMAC_BTCTRL_VALID_Pos)             /* (DMAC_BTCTRL) Descriptor Valid Mask */
+#define DMAC_BTCTRL_VALID(value)              (DMAC_BTCTRL_VALID_Msk & (_UINT16_(value) << DMAC_BTCTRL_VALID_Pos)) /* Assignment of value for VALID in the DMAC_BTCTRL register */
+#define DMAC_BTCTRL_EVOSEL_Pos                _UINT16_(1)                                          /* (DMAC_BTCTRL) Event Output Selection Position */
+#define DMAC_BTCTRL_EVOSEL_Msk                (_UINT16_(0x3) << DMAC_BTCTRL_EVOSEL_Pos)            /* (DMAC_BTCTRL) Event Output Selection Mask */
+#define DMAC_BTCTRL_EVOSEL(value)             (DMAC_BTCTRL_EVOSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_EVOSEL_Pos)) /* Assignment of value for EVOSEL in the DMAC_BTCTRL register */
+#define   DMAC_BTCTRL_EVOSEL_DISABLE_Val      _UINT16_(0x0)                                        /* (DMAC_BTCTRL) Event generation disabled  */
+#define   DMAC_BTCTRL_EVOSEL_BLOCK_Val        _UINT16_(0x1)                                        /* (DMAC_BTCTRL) Event strobe when block transfer complete  */
+#define   DMAC_BTCTRL_EVOSEL_BEAT_Val         _UINT16_(0x3)                                        /* (DMAC_BTCTRL) Event strobe when beat transfer complete  */
+#define DMAC_BTCTRL_EVOSEL_DISABLE            (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event generation disabled Position */
+#define DMAC_BTCTRL_EVOSEL_BLOCK              (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event strobe when block transfer complete Position */
+#define DMAC_BTCTRL_EVOSEL_BEAT               (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event strobe when beat transfer complete Position */
+#define DMAC_BTCTRL_BLOCKACT_Pos              _UINT16_(3)                                          /* (DMAC_BTCTRL) Block Action Position */
+#define DMAC_BTCTRL_BLOCKACT_Msk              (_UINT16_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)          /* (DMAC_BTCTRL) Block Action Mask */
+#define DMAC_BTCTRL_BLOCKACT(value)           (DMAC_BTCTRL_BLOCKACT_Msk & (_UINT16_(value) << DMAC_BTCTRL_BLOCKACT_Pos)) /* Assignment of value for BLOCKACT in the DMAC_BTCTRL register */
+#define   DMAC_BTCTRL_BLOCKACT_NOACT_Val      _UINT16_(0x0)                                        /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction  */
+#define   DMAC_BTCTRL_BLOCKACT_INT_Val        _UINT16_(0x1)                                        /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt  */
+#define   DMAC_BTCTRL_BLOCKACT_SUSPEND_Val    _UINT16_(0x2)                                        /* (DMAC_BTCTRL) Channel suspend operation is completed  */
+#define   DMAC_BTCTRL_BLOCKACT_BOTH_Val       _UINT16_(0x3)                                        /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt  */
+#define DMAC_BTCTRL_BLOCKACT_NOACT            (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction Position */
+#define DMAC_BTCTRL_BLOCKACT_INT              (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt Position */
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND          (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel suspend operation is completed Position */
+#define DMAC_BTCTRL_BLOCKACT_BOTH             (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */
+#define DMAC_BTCTRL_BEATSIZE_Pos              _UINT16_(8)                                          /* (DMAC_BTCTRL) Beat Size Position */
+#define DMAC_BTCTRL_BEATSIZE_Msk              (_UINT16_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)          /* (DMAC_BTCTRL) Beat Size Mask */
+#define DMAC_BTCTRL_BEATSIZE(value)           (DMAC_BTCTRL_BEATSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_BEATSIZE_Pos)) /* Assignment of value for BEATSIZE in the DMAC_BTCTRL register */
+#define   DMAC_BTCTRL_BEATSIZE_BYTE_Val       _UINT16_(0x0)                                        /* (DMAC_BTCTRL) 8-bit bus transfer  */
+#define   DMAC_BTCTRL_BEATSIZE_HWORD_Val      _UINT16_(0x1)                                        /* (DMAC_BTCTRL) 16-bit bus transfer  */
+#define   DMAC_BTCTRL_BEATSIZE_WORD_Val       _UINT16_(0x2)                                        /* (DMAC_BTCTRL) 32-bit bus transfer  */
+#define DMAC_BTCTRL_BEATSIZE_BYTE             (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 8-bit bus transfer Position */
+#define DMAC_BTCTRL_BEATSIZE_HWORD            (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 16-bit bus transfer Position */
+#define DMAC_BTCTRL_BEATSIZE_WORD             (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 32-bit bus transfer Position */
+#define DMAC_BTCTRL_SRCINC_Pos                _UINT16_(10)                                         /* (DMAC_BTCTRL) Source Address Increment Enable Position */
+#define DMAC_BTCTRL_SRCINC_Msk                (_UINT16_(0x1) << DMAC_BTCTRL_SRCINC_Pos)            /* (DMAC_BTCTRL) Source Address Increment Enable Mask */
+#define DMAC_BTCTRL_SRCINC(value)             (DMAC_BTCTRL_SRCINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_SRCINC_Pos)) /* Assignment of value for SRCINC in the DMAC_BTCTRL register */
+#define DMAC_BTCTRL_DSTINC_Pos                _UINT16_(11)                                         /* (DMAC_BTCTRL) Destination Address Increment Enable Position */
+#define DMAC_BTCTRL_DSTINC_Msk                (_UINT16_(0x1) << DMAC_BTCTRL_DSTINC_Pos)            /* (DMAC_BTCTRL) Destination Address Increment Enable Mask */
+#define DMAC_BTCTRL_DSTINC(value)             (DMAC_BTCTRL_DSTINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_DSTINC_Pos)) /* Assignment of value for DSTINC in the DMAC_BTCTRL register */
+#define DMAC_BTCTRL_STEPSEL_Pos               _UINT16_(12)                                         /* (DMAC_BTCTRL) Step Selection Position */
+#define DMAC_BTCTRL_STEPSEL_Msk               (_UINT16_(0x1) << DMAC_BTCTRL_STEPSEL_Pos)           /* (DMAC_BTCTRL) Step Selection Mask */
+#define DMAC_BTCTRL_STEPSEL(value)            (DMAC_BTCTRL_STEPSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSEL_Pos)) /* Assignment of value for STEPSEL in the DMAC_BTCTRL register */
+#define   DMAC_BTCTRL_STEPSEL_DST_Val         _UINT16_(0x0)                                        /* (DMAC_BTCTRL) Step size settings apply to the destination address  */
+#define   DMAC_BTCTRL_STEPSEL_SRC_Val         _UINT16_(0x1)                                        /* (DMAC_BTCTRL) Step size settings apply to the source address  */
+#define DMAC_BTCTRL_STEPSEL_DST               (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the destination address Position */
+#define DMAC_BTCTRL_STEPSEL_SRC               (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the source address Position */
+#define DMAC_BTCTRL_STEPSIZE_Pos              _UINT16_(13)                                         /* (DMAC_BTCTRL) Address Increment Step Size Position */
+#define DMAC_BTCTRL_STEPSIZE_Msk              (_UINT16_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)          /* (DMAC_BTCTRL) Address Increment Step Size Mask */
+#define DMAC_BTCTRL_STEPSIZE(value)           (DMAC_BTCTRL_STEPSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSIZE_Pos)) /* Assignment of value for STEPSIZE in the DMAC_BTCTRL register */
+#define   DMAC_BTCTRL_STEPSIZE_X1_Val         _UINT16_(0x0)                                        /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 1  */
+#define   DMAC_BTCTRL_STEPSIZE_X2_Val         _UINT16_(0x1)                                        /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 2  */
+#define   DMAC_BTCTRL_STEPSIZE_X4_Val         _UINT16_(0x2)                                        /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 4  */
+#define   DMAC_BTCTRL_STEPSIZE_X8_Val         _UINT16_(0x3)                                        /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 8  */
+#define   DMAC_BTCTRL_STEPSIZE_X16_Val        _UINT16_(0x4)                                        /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 16  */
+#define   DMAC_BTCTRL_STEPSIZE_X32_Val        _UINT16_(0x5)                                        /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 32  */
+#define   DMAC_BTCTRL_STEPSIZE_X64_Val        _UINT16_(0x6)                                        /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 64  */
+#define   DMAC_BTCTRL_STEPSIZE_X128_Val       _UINT16_(0x7)                                        /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 128  */
+#define DMAC_BTCTRL_STEPSIZE_X1               (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 1 Position */
+#define DMAC_BTCTRL_STEPSIZE_X2               (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 2 Position */
+#define DMAC_BTCTRL_STEPSIZE_X4               (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 4 Position */
+#define DMAC_BTCTRL_STEPSIZE_X8               (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 8 Position */
+#define DMAC_BTCTRL_STEPSIZE_X16              (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 16 Position */
+#define DMAC_BTCTRL_STEPSIZE_X32              (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 32 Position */
+#define DMAC_BTCTRL_STEPSIZE_X64              (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 64 Position */
+#define DMAC_BTCTRL_STEPSIZE_X128             (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 128 Position */
+#define DMAC_BTCTRL_Msk                       _UINT16_(0xFF1F)                                     /* (DMAC_BTCTRL) Register Mask  */
+
+
+/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
+#define DMAC_BTCNT_BTCNT_Pos                  _UINT16_(0)                                          /* (DMAC_BTCNT) Block Transfer Count Position */
+#define DMAC_BTCNT_BTCNT_Msk                  (_UINT16_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)           /* (DMAC_BTCNT) Block Transfer Count Mask */
+#define DMAC_BTCNT_BTCNT(value)               (DMAC_BTCNT_BTCNT_Msk & (_UINT16_(value) << DMAC_BTCNT_BTCNT_Pos)) /* Assignment of value for BTCNT in the DMAC_BTCNT register */
+#define DMAC_BTCNT_Msk                        _UINT16_(0xFFFF)                                     /* (DMAC_BTCNT) Register Mask  */
+
+
+/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
+#define DMAC_SRCADDR_SRCADDR_Pos              _UINT32_(0)                                          /* (DMAC_SRCADDR) Transfer Source Address Position */
+#define DMAC_SRCADDR_SRCADDR_Msk              (_UINT32_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)   /* (DMAC_SRCADDR) Transfer Source Address Mask */
+#define DMAC_SRCADDR_SRCADDR(value)           (DMAC_SRCADDR_SRCADDR_Msk & (_UINT32_(value) << DMAC_SRCADDR_SRCADDR_Pos)) /* Assignment of value for SRCADDR in the DMAC_SRCADDR register */
+#define DMAC_SRCADDR_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (DMAC_SRCADDR) Register Mask  */
+
+
+/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
+#define DMAC_DSTADDR_DSTADDR_Pos              _UINT32_(0)                                          /* (DMAC_DSTADDR) Transfer Destination Address Position */
+#define DMAC_DSTADDR_DSTADDR_Msk              (_UINT32_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)   /* (DMAC_DSTADDR) Transfer Destination Address Mask */
+#define DMAC_DSTADDR_DSTADDR(value)           (DMAC_DSTADDR_DSTADDR_Msk & (_UINT32_(value) << DMAC_DSTADDR_DSTADDR_Pos)) /* Assignment of value for DSTADDR in the DMAC_DSTADDR register */
+#define DMAC_DSTADDR_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (DMAC_DSTADDR) Register Mask  */
+
+
+/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
+#define DMAC_DESCADDR_DESCADDR_Pos            _UINT32_(0)                                          /* (DMAC_DESCADDR) Next Descriptor Address Position */
+#define DMAC_DESCADDR_DESCADDR_Msk            (_UINT32_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos) /* (DMAC_DESCADDR) Next Descriptor Address Mask */
+#define DMAC_DESCADDR_DESCADDR(value)         (DMAC_DESCADDR_DESCADDR_Msk & (_UINT32_(value) << DMAC_DESCADDR_DESCADDR_Pos)) /* Assignment of value for DESCADDR in the DMAC_DESCADDR register */
+#define DMAC_DESCADDR_Msk                     _UINT32_(0xFFFFFFFF)                                 /* (DMAC_DESCADDR) Register Mask  */
+
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#define DMAC_CTRL_RESETVALUE                  _UINT16_(0x00)                                       /*  (DMAC_CTRL) Control  Reset Value */
+
+#define DMAC_CTRL_SWRST_Pos                   _UINT16_(0)                                          /* (DMAC_CTRL) Software Reset Position */
+#define DMAC_CTRL_SWRST_Msk                   (_UINT16_(0x1) << DMAC_CTRL_SWRST_Pos)               /* (DMAC_CTRL) Software Reset Mask */
+#define DMAC_CTRL_SWRST(value)                (DMAC_CTRL_SWRST_Msk & (_UINT16_(value) << DMAC_CTRL_SWRST_Pos)) /* Assignment of value for SWRST in the DMAC_CTRL register */
+#define DMAC_CTRL_DMAENABLE_Pos               _UINT16_(1)                                          /* (DMAC_CTRL) DMA Enable Position */
+#define DMAC_CTRL_DMAENABLE_Msk               (_UINT16_(0x1) << DMAC_CTRL_DMAENABLE_Pos)           /* (DMAC_CTRL) DMA Enable Mask */
+#define DMAC_CTRL_DMAENABLE(value)            (DMAC_CTRL_DMAENABLE_Msk & (_UINT16_(value) << DMAC_CTRL_DMAENABLE_Pos)) /* Assignment of value for DMAENABLE in the DMAC_CTRL register */
+#define DMAC_CTRL_CRCENABLE_Pos               _UINT16_(2)                                          /* (DMAC_CTRL) CRC Enable Position */
+#define DMAC_CTRL_CRCENABLE_Msk               (_UINT16_(0x1) << DMAC_CTRL_CRCENABLE_Pos)           /* (DMAC_CTRL) CRC Enable Mask */
+#define DMAC_CTRL_CRCENABLE(value)            (DMAC_CTRL_CRCENABLE_Msk & (_UINT16_(value) << DMAC_CTRL_CRCENABLE_Pos)) /* Assignment of value for CRCENABLE in the DMAC_CTRL register */
+#define DMAC_CTRL_LVLEN0_Pos                  _UINT16_(8)                                          /* (DMAC_CTRL) Priority Level 0 Enable Position */
+#define DMAC_CTRL_LVLEN0_Msk                  (_UINT16_(0x1) << DMAC_CTRL_LVLEN0_Pos)              /* (DMAC_CTRL) Priority Level 0 Enable Mask */
+#define DMAC_CTRL_LVLEN0(value)               (DMAC_CTRL_LVLEN0_Msk & (_UINT16_(value) << DMAC_CTRL_LVLEN0_Pos)) /* Assignment of value for LVLEN0 in the DMAC_CTRL register */
+#define DMAC_CTRL_LVLEN1_Pos                  _UINT16_(9)                                          /* (DMAC_CTRL) Priority Level 1 Enable Position */
+#define DMAC_CTRL_LVLEN1_Msk                  (_UINT16_(0x1) << DMAC_CTRL_LVLEN1_Pos)              /* (DMAC_CTRL) Priority Level 1 Enable Mask */
+#define DMAC_CTRL_LVLEN1(value)               (DMAC_CTRL_LVLEN1_Msk & (_UINT16_(value) << DMAC_CTRL_LVLEN1_Pos)) /* Assignment of value for LVLEN1 in the DMAC_CTRL register */
+#define DMAC_CTRL_LVLEN2_Pos                  _UINT16_(10)                                         /* (DMAC_CTRL) Priority Level 2 Enable Position */
+#define DMAC_CTRL_LVLEN2_Msk                  (_UINT16_(0x1) << DMAC_CTRL_LVLEN2_Pos)              /* (DMAC_CTRL) Priority Level 2 Enable Mask */
+#define DMAC_CTRL_LVLEN2(value)               (DMAC_CTRL_LVLEN2_Msk & (_UINT16_(value) << DMAC_CTRL_LVLEN2_Pos)) /* Assignment of value for LVLEN2 in the DMAC_CTRL register */
+#define DMAC_CTRL_LVLEN3_Pos                  _UINT16_(11)                                         /* (DMAC_CTRL) Priority Level 3 Enable Position */
+#define DMAC_CTRL_LVLEN3_Msk                  (_UINT16_(0x1) << DMAC_CTRL_LVLEN3_Pos)              /* (DMAC_CTRL) Priority Level 3 Enable Mask */
+#define DMAC_CTRL_LVLEN3(value)               (DMAC_CTRL_LVLEN3_Msk & (_UINT16_(value) << DMAC_CTRL_LVLEN3_Pos)) /* Assignment of value for LVLEN3 in the DMAC_CTRL register */
+#define DMAC_CTRL_Msk                         _UINT16_(0x0F07)                                     /* (DMAC_CTRL) Register Mask  */
+
+#define DMAC_CTRL_LVLEN_Pos                   _UINT16_(8)                                          /* (DMAC_CTRL Position) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN_Msk                   (_UINT16_(0xF) << DMAC_CTRL_LVLEN_Pos)               /* (DMAC_CTRL Mask) LVLEN */
+#define DMAC_CTRL_LVLEN(value)                (DMAC_CTRL_LVLEN_Msk & (_UINT16_(value) << DMAC_CTRL_LVLEN_Pos)) 
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#define DMAC_CRCCTRL_RESETVALUE               _UINT16_(0x00)                                       /*  (DMAC_CRCCTRL) CRC Control  Reset Value */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos          _UINT16_(0)                                          /* (DMAC_CRCCTRL) CRC Beat Size Position */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk          (_UINT16_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)      /* (DMAC_CRCCTRL) CRC Beat Size Mask */
+#define DMAC_CRCCTRL_CRCBEATSIZE(value)       (DMAC_CRCCTRL_CRCBEATSIZE_Msk & (_UINT16_(value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) /* Assignment of value for CRCBEATSIZE in the DMAC_CRCCTRL register */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val   _UINT16_(0x0)                                        /* (DMAC_CRCCTRL) 8-bit bus transfer  */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val  _UINT16_(0x1)                                        /* (DMAC_CRCCTRL) 16-bit bus transfer  */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val   _UINT16_(0x2)                                        /* (DMAC_CRCCTRL) 32-bit bus transfer  */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE         (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) /* (DMAC_CRCCTRL) 8-bit bus transfer Position */
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD        (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) /* (DMAC_CRCCTRL) 16-bit bus transfer Position */
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD         (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) /* (DMAC_CRCCTRL) 32-bit bus transfer Position */
+#define DMAC_CRCCTRL_CRCPOLY_Pos              _UINT16_(2)                                          /* (DMAC_CRCCTRL) CRC Polynomial Type Position */
+#define DMAC_CRCCTRL_CRCPOLY_Msk              (_UINT16_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)          /* (DMAC_CRCCTRL) CRC Polynomial Type Mask */
+#define DMAC_CRCCTRL_CRCPOLY(value)           (DMAC_CRCCTRL_CRCPOLY_Msk & (_UINT16_(value) << DMAC_CRCCTRL_CRCPOLY_Pos)) /* Assignment of value for CRCPOLY in the DMAC_CRCCTRL register */
+#define   DMAC_CRCCTRL_CRCPOLY_CRC16_Val      _UINT16_(0x0)                                        /* (DMAC_CRCCTRL) CRC-16 (CRC-CCITT)  */
+#define   DMAC_CRCCTRL_CRCPOLY_CRC32_Val      _UINT16_(0x1)                                        /* (DMAC_CRCCTRL) CRC32 (IEEE 802.3)  */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16            (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) /* (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) Position */
+#define DMAC_CRCCTRL_CRCPOLY_CRC32            (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) /* (DMAC_CRCCTRL) CRC32 (IEEE 802.3) Position */
+#define DMAC_CRCCTRL_CRCSRC_Pos               _UINT16_(8)                                          /* (DMAC_CRCCTRL) CRC Input Source Position */
+#define DMAC_CRCCTRL_CRCSRC_Msk               (_UINT16_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)          /* (DMAC_CRCCTRL) CRC Input Source Mask */
+#define DMAC_CRCCTRL_CRCSRC(value)            (DMAC_CRCCTRL_CRCSRC_Msk & (_UINT16_(value) << DMAC_CRCCTRL_CRCSRC_Pos)) /* Assignment of value for CRCSRC in the DMAC_CRCCTRL register */
+#define   DMAC_CRCCTRL_CRCSRC_NOACT_Val       _UINT16_(0x0)                                        /* (DMAC_CRCCTRL) No action  */
+#define   DMAC_CRCCTRL_CRCSRC_IO_Val          _UINT16_(0x1)                                        /* (DMAC_CRCCTRL) I/O interface  */
+#define DMAC_CRCCTRL_CRCSRC_NOACT             (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) /* (DMAC_CRCCTRL) No action Position */
+#define DMAC_CRCCTRL_CRCSRC_IO                (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) /* (DMAC_CRCCTRL) I/O interface Position */
+#define DMAC_CRCCTRL_Msk                      _UINT16_(0x3F0F)                                     /* (DMAC_CRCCTRL) Register Mask  */
+
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#define DMAC_CRCDATAIN_RESETVALUE             _UINT32_(0x00)                                       /*  (DMAC_CRCDATAIN) CRC Data Input  Reset Value */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos          _UINT32_(0)                                          /* (DMAC_CRCDATAIN) CRC Data Input Position */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk          (_UINT32_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) /* (DMAC_CRCDATAIN) CRC Data Input Mask */
+#define DMAC_CRCDATAIN_CRCDATAIN(value)       (DMAC_CRCDATAIN_CRCDATAIN_Msk & (_UINT32_(value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) /* Assignment of value for CRCDATAIN in the DMAC_CRCDATAIN register */
+#define DMAC_CRCDATAIN_Msk                    _UINT32_(0xFFFFFFFF)                                 /* (DMAC_CRCDATAIN) Register Mask  */
+
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#define DMAC_CRCCHKSUM_RESETVALUE             _UINT32_(0x00)                                       /*  (DMAC_CRCCHKSUM) CRC Checksum  Reset Value */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos          _UINT32_(0)                                          /* (DMAC_CRCCHKSUM) CRC Checksum Position */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk          (_UINT32_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) /* (DMAC_CRCCHKSUM) CRC Checksum Mask */
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value)       (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & (_UINT32_(value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) /* Assignment of value for CRCCHKSUM in the DMAC_CRCCHKSUM register */
+#define DMAC_CRCCHKSUM_Msk                    _UINT32_(0xFFFFFFFF)                                 /* (DMAC_CRCCHKSUM) Register Mask  */
+
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
+#define DMAC_CRCSTATUS_RESETVALUE             _UINT8_(0x00)                                        /*  (DMAC_CRCSTATUS) CRC Status  Reset Value */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos            _UINT8_(0)                                           /* (DMAC_CRCSTATUS) CRC Module Busy Position */
+#define DMAC_CRCSTATUS_CRCBUSY_Msk            (_UINT8_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)         /* (DMAC_CRCSTATUS) CRC Module Busy Mask */
+#define DMAC_CRCSTATUS_CRCBUSY(value)         (DMAC_CRCSTATUS_CRCBUSY_Msk & (_UINT8_(value) << DMAC_CRCSTATUS_CRCBUSY_Pos)) /* Assignment of value for CRCBUSY in the DMAC_CRCSTATUS register */
+#define DMAC_CRCSTATUS_CRCZERO_Pos            _UINT8_(1)                                           /* (DMAC_CRCSTATUS) CRC Zero Position */
+#define DMAC_CRCSTATUS_CRCZERO_Msk            (_UINT8_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)         /* (DMAC_CRCSTATUS) CRC Zero Mask */
+#define DMAC_CRCSTATUS_CRCZERO(value)         (DMAC_CRCSTATUS_CRCZERO_Msk & (_UINT8_(value) << DMAC_CRCSTATUS_CRCZERO_Pos)) /* Assignment of value for CRCZERO in the DMAC_CRCSTATUS register */
+#define DMAC_CRCSTATUS_Msk                    _UINT8_(0x03)                                        /* (DMAC_CRCSTATUS) Register Mask  */
+
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
+#define DMAC_DBGCTRL_RESETVALUE               _UINT8_(0x00)                                        /*  (DMAC_DBGCTRL) Debug Control  Reset Value */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos               _UINT8_(0)                                           /* (DMAC_DBGCTRL) Debug Run Position */
+#define DMAC_DBGCTRL_DBGRUN_Msk               (_UINT8_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)            /* (DMAC_DBGCTRL) Debug Run Mask */
+#define DMAC_DBGCTRL_DBGRUN(value)            (DMAC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << DMAC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the DMAC_DBGCTRL register */
+#define DMAC_DBGCTRL_Msk                      _UINT8_(0x01)                                        /* (DMAC_DBGCTRL) Register Mask  */
+
+
+/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
+#define DMAC_QOSCTRL_RESETVALUE               _UINT8_(0x2A)                                        /*  (DMAC_QOSCTRL) QOS Control  Reset Value */
+
+#define DMAC_QOSCTRL_WRBQOS_Pos               _UINT8_(0)                                           /* (DMAC_QOSCTRL) Write-Back Quality of Service Position */
+#define DMAC_QOSCTRL_WRBQOS_Msk               (_UINT8_(0x3) << DMAC_QOSCTRL_WRBQOS_Pos)            /* (DMAC_QOSCTRL) Write-Back Quality of Service Mask */
+#define DMAC_QOSCTRL_WRBQOS(value)            (DMAC_QOSCTRL_WRBQOS_Msk & (_UINT8_(value) << DMAC_QOSCTRL_WRBQOS_Pos)) /* Assignment of value for WRBQOS in the DMAC_QOSCTRL register */
+#define   DMAC_QOSCTRL_WRBQOS_DISABLE_Val     _UINT8_(0x0)                                         /* (DMAC_QOSCTRL) Background (no sensitive operation)  */
+#define   DMAC_QOSCTRL_WRBQOS_LOW_Val         _UINT8_(0x1)                                         /* (DMAC_QOSCTRL) Sensitive Bandwidth  */
+#define   DMAC_QOSCTRL_WRBQOS_MEDIUM_Val      _UINT8_(0x2)                                         /* (DMAC_QOSCTRL) Sensitive Latency  */
+#define   DMAC_QOSCTRL_WRBQOS_HIGH_Val        _UINT8_(0x3)                                         /* (DMAC_QOSCTRL) Critical Latency  */
+#define DMAC_QOSCTRL_WRBQOS_DISABLE           (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) /* (DMAC_QOSCTRL) Background (no sensitive operation) Position */
+#define DMAC_QOSCTRL_WRBQOS_LOW               (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) /* (DMAC_QOSCTRL) Sensitive Bandwidth Position */
+#define DMAC_QOSCTRL_WRBQOS_MEDIUM            (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) /* (DMAC_QOSCTRL) Sensitive Latency Position */
+#define DMAC_QOSCTRL_WRBQOS_HIGH              (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) /* (DMAC_QOSCTRL) Critical Latency Position */
+#define DMAC_QOSCTRL_FQOS_Pos                 _UINT8_(2)                                           /* (DMAC_QOSCTRL) Fetch Quality of Service Position */
+#define DMAC_QOSCTRL_FQOS_Msk                 (_UINT8_(0x3) << DMAC_QOSCTRL_FQOS_Pos)              /* (DMAC_QOSCTRL) Fetch Quality of Service Mask */
+#define DMAC_QOSCTRL_FQOS(value)              (DMAC_QOSCTRL_FQOS_Msk & (_UINT8_(value) << DMAC_QOSCTRL_FQOS_Pos)) /* Assignment of value for FQOS in the DMAC_QOSCTRL register */
+#define   DMAC_QOSCTRL_FQOS_DISABLE_Val       _UINT8_(0x0)                                         /* (DMAC_QOSCTRL) Background (no sensitive operation)  */
+#define   DMAC_QOSCTRL_FQOS_LOW_Val           _UINT8_(0x1)                                         /* (DMAC_QOSCTRL) Sensitive Bandwidth  */
+#define   DMAC_QOSCTRL_FQOS_MEDIUM_Val        _UINT8_(0x2)                                         /* (DMAC_QOSCTRL) Sensitive Latency  */
+#define   DMAC_QOSCTRL_FQOS_HIGH_Val          _UINT8_(0x3)                                         /* (DMAC_QOSCTRL) Critical Latency  */
+#define DMAC_QOSCTRL_FQOS_DISABLE             (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) /* (DMAC_QOSCTRL) Background (no sensitive operation) Position */
+#define DMAC_QOSCTRL_FQOS_LOW                 (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) /* (DMAC_QOSCTRL) Sensitive Bandwidth Position */
+#define DMAC_QOSCTRL_FQOS_MEDIUM              (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) /* (DMAC_QOSCTRL) Sensitive Latency Position */
+#define DMAC_QOSCTRL_FQOS_HIGH                (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) /* (DMAC_QOSCTRL) Critical Latency Position */
+#define DMAC_QOSCTRL_DQOS_Pos                 _UINT8_(4)                                           /* (DMAC_QOSCTRL) Data Transfer Quality of Service Position */
+#define DMAC_QOSCTRL_DQOS_Msk                 (_UINT8_(0x3) << DMAC_QOSCTRL_DQOS_Pos)              /* (DMAC_QOSCTRL) Data Transfer Quality of Service Mask */
+#define DMAC_QOSCTRL_DQOS(value)              (DMAC_QOSCTRL_DQOS_Msk & (_UINT8_(value) << DMAC_QOSCTRL_DQOS_Pos)) /* Assignment of value for DQOS in the DMAC_QOSCTRL register */
+#define   DMAC_QOSCTRL_DQOS_DISABLE_Val       _UINT8_(0x0)                                         /* (DMAC_QOSCTRL) Background (no sensitive operation)  */
+#define   DMAC_QOSCTRL_DQOS_LOW_Val           _UINT8_(0x1)                                         /* (DMAC_QOSCTRL) Sensitive Bandwidth  */
+#define   DMAC_QOSCTRL_DQOS_MEDIUM_Val        _UINT8_(0x2)                                         /* (DMAC_QOSCTRL) Sensitive Latency  */
+#define   DMAC_QOSCTRL_DQOS_HIGH_Val          _UINT8_(0x3)                                         /* (DMAC_QOSCTRL) Critical Latency  */
+#define DMAC_QOSCTRL_DQOS_DISABLE             (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) /* (DMAC_QOSCTRL) Background (no sensitive operation) Position */
+#define DMAC_QOSCTRL_DQOS_LOW                 (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) /* (DMAC_QOSCTRL) Sensitive Bandwidth Position */
+#define DMAC_QOSCTRL_DQOS_MEDIUM              (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) /* (DMAC_QOSCTRL) Sensitive Latency Position */
+#define DMAC_QOSCTRL_DQOS_HIGH                (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) /* (DMAC_QOSCTRL) Critical Latency Position */
+#define DMAC_QOSCTRL_Msk                      _UINT8_(0x3F)                                        /* (DMAC_QOSCTRL) Register Mask  */
+
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#define DMAC_SWTRIGCTRL_RESETVALUE            _UINT32_(0x00)                                       /*  (DMAC_SWTRIGCTRL) Software Trigger Control  Reset Value */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos           _UINT32_(0)                                          /* (DMAC_SWTRIGCTRL) Channel 0 Software Trigger Position */
+#define DMAC_SWTRIGCTRL_SWTRIG0_Msk           (_UINT32_(0x1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)       /* (DMAC_SWTRIGCTRL) Channel 0 Software Trigger Mask */
+#define DMAC_SWTRIGCTRL_SWTRIG0(value)        (DMAC_SWTRIGCTRL_SWTRIG0_Msk & (_UINT32_(value) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)) /* Assignment of value for SWTRIG0 in the DMAC_SWTRIGCTRL register */
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos           _UINT32_(1)                                          /* (DMAC_SWTRIGCTRL) Channel 1 Software Trigger Position */
+#define DMAC_SWTRIGCTRL_SWTRIG1_Msk           (_UINT32_(0x1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)       /* (DMAC_SWTRIGCTRL) Channel 1 Software Trigger Mask */
+#define DMAC_SWTRIGCTRL_SWTRIG1(value)        (DMAC_SWTRIGCTRL_SWTRIG1_Msk & (_UINT32_(value) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)) /* Assignment of value for SWTRIG1 in the DMAC_SWTRIGCTRL register */
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos           _UINT32_(2)                                          /* (DMAC_SWTRIGCTRL) Channel 2 Software Trigger Position */
+#define DMAC_SWTRIGCTRL_SWTRIG2_Msk           (_UINT32_(0x1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)       /* (DMAC_SWTRIGCTRL) Channel 2 Software Trigger Mask */
+#define DMAC_SWTRIGCTRL_SWTRIG2(value)        (DMAC_SWTRIGCTRL_SWTRIG2_Msk & (_UINT32_(value) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)) /* Assignment of value for SWTRIG2 in the DMAC_SWTRIGCTRL register */
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos           _UINT32_(3)                                          /* (DMAC_SWTRIGCTRL) Channel 3 Software Trigger Position */
+#define DMAC_SWTRIGCTRL_SWTRIG3_Msk           (_UINT32_(0x1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)       /* (DMAC_SWTRIGCTRL) Channel 3 Software Trigger Mask */
+#define DMAC_SWTRIGCTRL_SWTRIG3(value)        (DMAC_SWTRIGCTRL_SWTRIG3_Msk & (_UINT32_(value) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)) /* Assignment of value for SWTRIG3 in the DMAC_SWTRIGCTRL register */
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos           _UINT32_(4)                                          /* (DMAC_SWTRIGCTRL) Channel 4 Software Trigger Position */
+#define DMAC_SWTRIGCTRL_SWTRIG4_Msk           (_UINT32_(0x1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)       /* (DMAC_SWTRIGCTRL) Channel 4 Software Trigger Mask */
+#define DMAC_SWTRIGCTRL_SWTRIG4(value)        (DMAC_SWTRIGCTRL_SWTRIG4_Msk & (_UINT32_(value) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)) /* Assignment of value for SWTRIG4 in the DMAC_SWTRIGCTRL register */
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos           _UINT32_(5)                                          /* (DMAC_SWTRIGCTRL) Channel 5 Software Trigger Position */
+#define DMAC_SWTRIGCTRL_SWTRIG5_Msk           (_UINT32_(0x1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)       /* (DMAC_SWTRIGCTRL) Channel 5 Software Trigger Mask */
+#define DMAC_SWTRIGCTRL_SWTRIG5(value)        (DMAC_SWTRIGCTRL_SWTRIG5_Msk & (_UINT32_(value) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)) /* Assignment of value for SWTRIG5 in the DMAC_SWTRIGCTRL register */
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos           _UINT32_(6)                                          /* (DMAC_SWTRIGCTRL) Channel 6 Software Trigger Position */
+#define DMAC_SWTRIGCTRL_SWTRIG6_Msk           (_UINT32_(0x1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)       /* (DMAC_SWTRIGCTRL) Channel 6 Software Trigger Mask */
+#define DMAC_SWTRIGCTRL_SWTRIG6(value)        (DMAC_SWTRIGCTRL_SWTRIG6_Msk & (_UINT32_(value) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)) /* Assignment of value for SWTRIG6 in the DMAC_SWTRIGCTRL register */
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos           _UINT32_(7)                                          /* (DMAC_SWTRIGCTRL) Channel 7 Software Trigger Position */
+#define DMAC_SWTRIGCTRL_SWTRIG7_Msk           (_UINT32_(0x1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)       /* (DMAC_SWTRIGCTRL) Channel 7 Software Trigger Mask */
+#define DMAC_SWTRIGCTRL_SWTRIG7(value)        (DMAC_SWTRIGCTRL_SWTRIG7_Msk & (_UINT32_(value) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)) /* Assignment of value for SWTRIG7 in the DMAC_SWTRIGCTRL register */
+#define DMAC_SWTRIGCTRL_Msk                   _UINT32_(0x000000FF)                                 /* (DMAC_SWTRIGCTRL) Register Mask  */
+
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos            _UINT32_(0)                                          /* (DMAC_SWTRIGCTRL Position) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk            (_UINT32_(0xFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)       /* (DMAC_SWTRIGCTRL Mask) SWTRIG */
+#define DMAC_SWTRIGCTRL_SWTRIG(value)         (DMAC_SWTRIGCTRL_SWTRIG_Msk & (_UINT32_(value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) 
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#define DMAC_PRICTRL0_RESETVALUE              _UINT32_(0x00)                                       /*  (DMAC_PRICTRL0) Priority Control 0  Reset Value */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos             _UINT32_(0)                                          /* (DMAC_PRICTRL0) Level 0 Channel Priority Number Position */
+#define DMAC_PRICTRL0_LVLPRI0_Msk             (_UINT32_(0x7) << DMAC_PRICTRL0_LVLPRI0_Pos)         /* (DMAC_PRICTRL0) Level 0 Channel Priority Number Mask */
+#define DMAC_PRICTRL0_LVLPRI0(value)          (DMAC_PRICTRL0_LVLPRI0_Msk & (_UINT32_(value) << DMAC_PRICTRL0_LVLPRI0_Pos)) /* Assignment of value for LVLPRI0 in the DMAC_PRICTRL0 register */
+#define DMAC_PRICTRL0_RRLVLEN0_Pos            _UINT32_(7)                                          /* (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable Position */
+#define DMAC_PRICTRL0_RRLVLEN0_Msk            (_UINT32_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)        /* (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable Mask */
+#define DMAC_PRICTRL0_RRLVLEN0(value)         (DMAC_PRICTRL0_RRLVLEN0_Msk & (_UINT32_(value) << DMAC_PRICTRL0_RRLVLEN0_Pos)) /* Assignment of value for RRLVLEN0 in the DMAC_PRICTRL0 register */
+#define DMAC_PRICTRL0_LVLPRI1_Pos             _UINT32_(8)                                          /* (DMAC_PRICTRL0) Level 1 Channel Priority Number Position */
+#define DMAC_PRICTRL0_LVLPRI1_Msk             (_UINT32_(0x7) << DMAC_PRICTRL0_LVLPRI1_Pos)         /* (DMAC_PRICTRL0) Level 1 Channel Priority Number Mask */
+#define DMAC_PRICTRL0_LVLPRI1(value)          (DMAC_PRICTRL0_LVLPRI1_Msk & (_UINT32_(value) << DMAC_PRICTRL0_LVLPRI1_Pos)) /* Assignment of value for LVLPRI1 in the DMAC_PRICTRL0 register */
+#define DMAC_PRICTRL0_RRLVLEN1_Pos            _UINT32_(15)                                         /* (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable Position */
+#define DMAC_PRICTRL0_RRLVLEN1_Msk            (_UINT32_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)        /* (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable Mask */
+#define DMAC_PRICTRL0_RRLVLEN1(value)         (DMAC_PRICTRL0_RRLVLEN1_Msk & (_UINT32_(value) << DMAC_PRICTRL0_RRLVLEN1_Pos)) /* Assignment of value for RRLVLEN1 in the DMAC_PRICTRL0 register */
+#define DMAC_PRICTRL0_LVLPRI2_Pos             _UINT32_(16)                                         /* (DMAC_PRICTRL0) Level 2 Channel Priority Number Position */
+#define DMAC_PRICTRL0_LVLPRI2_Msk             (_UINT32_(0x7) << DMAC_PRICTRL0_LVLPRI2_Pos)         /* (DMAC_PRICTRL0) Level 2 Channel Priority Number Mask */
+#define DMAC_PRICTRL0_LVLPRI2(value)          (DMAC_PRICTRL0_LVLPRI2_Msk & (_UINT32_(value) << DMAC_PRICTRL0_LVLPRI2_Pos)) /* Assignment of value for LVLPRI2 in the DMAC_PRICTRL0 register */
+#define DMAC_PRICTRL0_RRLVLEN2_Pos            _UINT32_(23)                                         /* (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable Position */
+#define DMAC_PRICTRL0_RRLVLEN2_Msk            (_UINT32_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)        /* (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable Mask */
+#define DMAC_PRICTRL0_RRLVLEN2(value)         (DMAC_PRICTRL0_RRLVLEN2_Msk & (_UINT32_(value) << DMAC_PRICTRL0_RRLVLEN2_Pos)) /* Assignment of value for RRLVLEN2 in the DMAC_PRICTRL0 register */
+#define DMAC_PRICTRL0_LVLPRI3_Pos             _UINT32_(24)                                         /* (DMAC_PRICTRL0) Level 3 Channel Priority Number Position */
+#define DMAC_PRICTRL0_LVLPRI3_Msk             (_UINT32_(0x7) << DMAC_PRICTRL0_LVLPRI3_Pos)         /* (DMAC_PRICTRL0) Level 3 Channel Priority Number Mask */
+#define DMAC_PRICTRL0_LVLPRI3(value)          (DMAC_PRICTRL0_LVLPRI3_Msk & (_UINT32_(value) << DMAC_PRICTRL0_LVLPRI3_Pos)) /* Assignment of value for LVLPRI3 in the DMAC_PRICTRL0 register */
+#define DMAC_PRICTRL0_RRLVLEN3_Pos            _UINT32_(31)                                         /* (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable Position */
+#define DMAC_PRICTRL0_RRLVLEN3_Msk            (_UINT32_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)        /* (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable Mask */
+#define DMAC_PRICTRL0_RRLVLEN3(value)         (DMAC_PRICTRL0_RRLVLEN3_Msk & (_UINT32_(value) << DMAC_PRICTRL0_RRLVLEN3_Pos)) /* Assignment of value for RRLVLEN3 in the DMAC_PRICTRL0 register */
+#define DMAC_PRICTRL0_Msk                     _UINT32_(0x87878787)                                 /* (DMAC_PRICTRL0) Register Mask  */
+
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#define DMAC_INTPEND_RESETVALUE               _UINT16_(0x00)                                       /*  (DMAC_INTPEND) Interrupt Pending  Reset Value */
+
+#define DMAC_INTPEND_ID_Pos                   _UINT16_(0)                                          /* (DMAC_INTPEND) Channel ID Position */
+#define DMAC_INTPEND_ID_Msk                   (_UINT16_(0x7) << DMAC_INTPEND_ID_Pos)               /* (DMAC_INTPEND) Channel ID Mask */
+#define DMAC_INTPEND_ID(value)                (DMAC_INTPEND_ID_Msk & (_UINT16_(value) << DMAC_INTPEND_ID_Pos)) /* Assignment of value for ID in the DMAC_INTPEND register */
+#define DMAC_INTPEND_TERR_Pos                 _UINT16_(8)                                          /* (DMAC_INTPEND) Transfer Error Position */
+#define DMAC_INTPEND_TERR_Msk                 (_UINT16_(0x1) << DMAC_INTPEND_TERR_Pos)             /* (DMAC_INTPEND) Transfer Error Mask */
+#define DMAC_INTPEND_TERR(value)              (DMAC_INTPEND_TERR_Msk & (_UINT16_(value) << DMAC_INTPEND_TERR_Pos)) /* Assignment of value for TERR in the DMAC_INTPEND register */
+#define DMAC_INTPEND_TCMPL_Pos                _UINT16_(9)                                          /* (DMAC_INTPEND) Transfer Complete Position */
+#define DMAC_INTPEND_TCMPL_Msk                (_UINT16_(0x1) << DMAC_INTPEND_TCMPL_Pos)            /* (DMAC_INTPEND) Transfer Complete Mask */
+#define DMAC_INTPEND_TCMPL(value)             (DMAC_INTPEND_TCMPL_Msk & (_UINT16_(value) << DMAC_INTPEND_TCMPL_Pos)) /* Assignment of value for TCMPL in the DMAC_INTPEND register */
+#define DMAC_INTPEND_SUSP_Pos                 _UINT16_(10)                                         /* (DMAC_INTPEND) Channel Suspend Position */
+#define DMAC_INTPEND_SUSP_Msk                 (_UINT16_(0x1) << DMAC_INTPEND_SUSP_Pos)             /* (DMAC_INTPEND) Channel Suspend Mask */
+#define DMAC_INTPEND_SUSP(value)              (DMAC_INTPEND_SUSP_Msk & (_UINT16_(value) << DMAC_INTPEND_SUSP_Pos)) /* Assignment of value for SUSP in the DMAC_INTPEND register */
+#define DMAC_INTPEND_FERR_Pos                 _UINT16_(13)                                         /* (DMAC_INTPEND) Fetch Error Position */
+#define DMAC_INTPEND_FERR_Msk                 (_UINT16_(0x1) << DMAC_INTPEND_FERR_Pos)             /* (DMAC_INTPEND) Fetch Error Mask */
+#define DMAC_INTPEND_FERR(value)              (DMAC_INTPEND_FERR_Msk & (_UINT16_(value) << DMAC_INTPEND_FERR_Pos)) /* Assignment of value for FERR in the DMAC_INTPEND register */
+#define DMAC_INTPEND_BUSY_Pos                 _UINT16_(14)                                         /* (DMAC_INTPEND) Busy Position */
+#define DMAC_INTPEND_BUSY_Msk                 (_UINT16_(0x1) << DMAC_INTPEND_BUSY_Pos)             /* (DMAC_INTPEND) Busy Mask */
+#define DMAC_INTPEND_BUSY(value)              (DMAC_INTPEND_BUSY_Msk & (_UINT16_(value) << DMAC_INTPEND_BUSY_Pos)) /* Assignment of value for BUSY in the DMAC_INTPEND register */
+#define DMAC_INTPEND_PEND_Pos                 _UINT16_(15)                                         /* (DMAC_INTPEND) Pending Position */
+#define DMAC_INTPEND_PEND_Msk                 (_UINT16_(0x1) << DMAC_INTPEND_PEND_Pos)             /* (DMAC_INTPEND) Pending Mask */
+#define DMAC_INTPEND_PEND(value)              (DMAC_INTPEND_PEND_Msk & (_UINT16_(value) << DMAC_INTPEND_PEND_Pos)) /* Assignment of value for PEND in the DMAC_INTPEND register */
+#define DMAC_INTPEND_Msk                      _UINT16_(0xE707)                                     /* (DMAC_INTPEND) Register Mask  */
+
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) ( R/ 32) Interrupt Status -------- */
+#define DMAC_INTSTATUS_RESETVALUE             _UINT32_(0x00)                                       /*  (DMAC_INTSTATUS) Interrupt Status  Reset Value */
+
+#define DMAC_INTSTATUS_CHINT0_Pos             _UINT32_(0)                                          /* (DMAC_INTSTATUS) Channel 0 Pending Interrupt Position */
+#define DMAC_INTSTATUS_CHINT0_Msk             (_UINT32_(0x1) << DMAC_INTSTATUS_CHINT0_Pos)         /* (DMAC_INTSTATUS) Channel 0 Pending Interrupt Mask */
+#define DMAC_INTSTATUS_CHINT0(value)          (DMAC_INTSTATUS_CHINT0_Msk & (_UINT32_(value) << DMAC_INTSTATUS_CHINT0_Pos)) /* Assignment of value for CHINT0 in the DMAC_INTSTATUS register */
+#define DMAC_INTSTATUS_CHINT1_Pos             _UINT32_(1)                                          /* (DMAC_INTSTATUS) Channel 1 Pending Interrupt Position */
+#define DMAC_INTSTATUS_CHINT1_Msk             (_UINT32_(0x1) << DMAC_INTSTATUS_CHINT1_Pos)         /* (DMAC_INTSTATUS) Channel 1 Pending Interrupt Mask */
+#define DMAC_INTSTATUS_CHINT1(value)          (DMAC_INTSTATUS_CHINT1_Msk & (_UINT32_(value) << DMAC_INTSTATUS_CHINT1_Pos)) /* Assignment of value for CHINT1 in the DMAC_INTSTATUS register */
+#define DMAC_INTSTATUS_CHINT2_Pos             _UINT32_(2)                                          /* (DMAC_INTSTATUS) Channel 2 Pending Interrupt Position */
+#define DMAC_INTSTATUS_CHINT2_Msk             (_UINT32_(0x1) << DMAC_INTSTATUS_CHINT2_Pos)         /* (DMAC_INTSTATUS) Channel 2 Pending Interrupt Mask */
+#define DMAC_INTSTATUS_CHINT2(value)          (DMAC_INTSTATUS_CHINT2_Msk & (_UINT32_(value) << DMAC_INTSTATUS_CHINT2_Pos)) /* Assignment of value for CHINT2 in the DMAC_INTSTATUS register */
+#define DMAC_INTSTATUS_CHINT3_Pos             _UINT32_(3)                                          /* (DMAC_INTSTATUS) Channel 3 Pending Interrupt Position */
+#define DMAC_INTSTATUS_CHINT3_Msk             (_UINT32_(0x1) << DMAC_INTSTATUS_CHINT3_Pos)         /* (DMAC_INTSTATUS) Channel 3 Pending Interrupt Mask */
+#define DMAC_INTSTATUS_CHINT3(value)          (DMAC_INTSTATUS_CHINT3_Msk & (_UINT32_(value) << DMAC_INTSTATUS_CHINT3_Pos)) /* Assignment of value for CHINT3 in the DMAC_INTSTATUS register */
+#define DMAC_INTSTATUS_CHINT4_Pos             _UINT32_(4)                                          /* (DMAC_INTSTATUS) Channel 4 Pending Interrupt Position */
+#define DMAC_INTSTATUS_CHINT4_Msk             (_UINT32_(0x1) << DMAC_INTSTATUS_CHINT4_Pos)         /* (DMAC_INTSTATUS) Channel 4 Pending Interrupt Mask */
+#define DMAC_INTSTATUS_CHINT4(value)          (DMAC_INTSTATUS_CHINT4_Msk & (_UINT32_(value) << DMAC_INTSTATUS_CHINT4_Pos)) /* Assignment of value for CHINT4 in the DMAC_INTSTATUS register */
+#define DMAC_INTSTATUS_CHINT5_Pos             _UINT32_(5)                                          /* (DMAC_INTSTATUS) Channel 5 Pending Interrupt Position */
+#define DMAC_INTSTATUS_CHINT5_Msk             (_UINT32_(0x1) << DMAC_INTSTATUS_CHINT5_Pos)         /* (DMAC_INTSTATUS) Channel 5 Pending Interrupt Mask */
+#define DMAC_INTSTATUS_CHINT5(value)          (DMAC_INTSTATUS_CHINT5_Msk & (_UINT32_(value) << DMAC_INTSTATUS_CHINT5_Pos)) /* Assignment of value for CHINT5 in the DMAC_INTSTATUS register */
+#define DMAC_INTSTATUS_CHINT6_Pos             _UINT32_(6)                                          /* (DMAC_INTSTATUS) Channel 6 Pending Interrupt Position */
+#define DMAC_INTSTATUS_CHINT6_Msk             (_UINT32_(0x1) << DMAC_INTSTATUS_CHINT6_Pos)         /* (DMAC_INTSTATUS) Channel 6 Pending Interrupt Mask */
+#define DMAC_INTSTATUS_CHINT6(value)          (DMAC_INTSTATUS_CHINT6_Msk & (_UINT32_(value) << DMAC_INTSTATUS_CHINT6_Pos)) /* Assignment of value for CHINT6 in the DMAC_INTSTATUS register */
+#define DMAC_INTSTATUS_CHINT7_Pos             _UINT32_(7)                                          /* (DMAC_INTSTATUS) Channel 7 Pending Interrupt Position */
+#define DMAC_INTSTATUS_CHINT7_Msk             (_UINT32_(0x1) << DMAC_INTSTATUS_CHINT7_Pos)         /* (DMAC_INTSTATUS) Channel 7 Pending Interrupt Mask */
+#define DMAC_INTSTATUS_CHINT7(value)          (DMAC_INTSTATUS_CHINT7_Msk & (_UINT32_(value) << DMAC_INTSTATUS_CHINT7_Pos)) /* Assignment of value for CHINT7 in the DMAC_INTSTATUS register */
+#define DMAC_INTSTATUS_Msk                    _UINT32_(0x000000FF)                                 /* (DMAC_INTSTATUS) Register Mask  */
+
+#define DMAC_INTSTATUS_CHINT_Pos              _UINT32_(0)                                          /* (DMAC_INTSTATUS Position) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk              (_UINT32_(0xFF) << DMAC_INTSTATUS_CHINT_Pos)         /* (DMAC_INTSTATUS Mask) CHINT */
+#define DMAC_INTSTATUS_CHINT(value)           (DMAC_INTSTATUS_CHINT_Msk & (_UINT32_(value) << DMAC_INTSTATUS_CHINT_Pos)) 
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) ( R/ 32) Busy Channels -------- */
+#define DMAC_BUSYCH_RESETVALUE                _UINT32_(0x00)                                       /*  (DMAC_BUSYCH) Busy Channels  Reset Value */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos               _UINT32_(0)                                          /* (DMAC_BUSYCH) Busy Channel 0 Position */
+#define DMAC_BUSYCH_BUSYCH0_Msk               (_UINT32_(0x1) << DMAC_BUSYCH_BUSYCH0_Pos)           /* (DMAC_BUSYCH) Busy Channel 0 Mask */
+#define DMAC_BUSYCH_BUSYCH0(value)            (DMAC_BUSYCH_BUSYCH0_Msk & (_UINT32_(value) << DMAC_BUSYCH_BUSYCH0_Pos)) /* Assignment of value for BUSYCH0 in the DMAC_BUSYCH register */
+#define DMAC_BUSYCH_BUSYCH1_Pos               _UINT32_(1)                                          /* (DMAC_BUSYCH) Busy Channel 1 Position */
+#define DMAC_BUSYCH_BUSYCH1_Msk               (_UINT32_(0x1) << DMAC_BUSYCH_BUSYCH1_Pos)           /* (DMAC_BUSYCH) Busy Channel 1 Mask */
+#define DMAC_BUSYCH_BUSYCH1(value)            (DMAC_BUSYCH_BUSYCH1_Msk & (_UINT32_(value) << DMAC_BUSYCH_BUSYCH1_Pos)) /* Assignment of value for BUSYCH1 in the DMAC_BUSYCH register */
+#define DMAC_BUSYCH_BUSYCH2_Pos               _UINT32_(2)                                          /* (DMAC_BUSYCH) Busy Channel 2 Position */
+#define DMAC_BUSYCH_BUSYCH2_Msk               (_UINT32_(0x1) << DMAC_BUSYCH_BUSYCH2_Pos)           /* (DMAC_BUSYCH) Busy Channel 2 Mask */
+#define DMAC_BUSYCH_BUSYCH2(value)            (DMAC_BUSYCH_BUSYCH2_Msk & (_UINT32_(value) << DMAC_BUSYCH_BUSYCH2_Pos)) /* Assignment of value for BUSYCH2 in the DMAC_BUSYCH register */
+#define DMAC_BUSYCH_BUSYCH3_Pos               _UINT32_(3)                                          /* (DMAC_BUSYCH) Busy Channel 3 Position */
+#define DMAC_BUSYCH_BUSYCH3_Msk               (_UINT32_(0x1) << DMAC_BUSYCH_BUSYCH3_Pos)           /* (DMAC_BUSYCH) Busy Channel 3 Mask */
+#define DMAC_BUSYCH_BUSYCH3(value)            (DMAC_BUSYCH_BUSYCH3_Msk & (_UINT32_(value) << DMAC_BUSYCH_BUSYCH3_Pos)) /* Assignment of value for BUSYCH3 in the DMAC_BUSYCH register */
+#define DMAC_BUSYCH_BUSYCH4_Pos               _UINT32_(4)                                          /* (DMAC_BUSYCH) Busy Channel 4 Position */
+#define DMAC_BUSYCH_BUSYCH4_Msk               (_UINT32_(0x1) << DMAC_BUSYCH_BUSYCH4_Pos)           /* (DMAC_BUSYCH) Busy Channel 4 Mask */
+#define DMAC_BUSYCH_BUSYCH4(value)            (DMAC_BUSYCH_BUSYCH4_Msk & (_UINT32_(value) << DMAC_BUSYCH_BUSYCH4_Pos)) /* Assignment of value for BUSYCH4 in the DMAC_BUSYCH register */
+#define DMAC_BUSYCH_BUSYCH5_Pos               _UINT32_(5)                                          /* (DMAC_BUSYCH) Busy Channel 5 Position */
+#define DMAC_BUSYCH_BUSYCH5_Msk               (_UINT32_(0x1) << DMAC_BUSYCH_BUSYCH5_Pos)           /* (DMAC_BUSYCH) Busy Channel 5 Mask */
+#define DMAC_BUSYCH_BUSYCH5(value)            (DMAC_BUSYCH_BUSYCH5_Msk & (_UINT32_(value) << DMAC_BUSYCH_BUSYCH5_Pos)) /* Assignment of value for BUSYCH5 in the DMAC_BUSYCH register */
+#define DMAC_BUSYCH_BUSYCH6_Pos               _UINT32_(6)                                          /* (DMAC_BUSYCH) Busy Channel 6 Position */
+#define DMAC_BUSYCH_BUSYCH6_Msk               (_UINT32_(0x1) << DMAC_BUSYCH_BUSYCH6_Pos)           /* (DMAC_BUSYCH) Busy Channel 6 Mask */
+#define DMAC_BUSYCH_BUSYCH6(value)            (DMAC_BUSYCH_BUSYCH6_Msk & (_UINT32_(value) << DMAC_BUSYCH_BUSYCH6_Pos)) /* Assignment of value for BUSYCH6 in the DMAC_BUSYCH register */
+#define DMAC_BUSYCH_BUSYCH7_Pos               _UINT32_(7)                                          /* (DMAC_BUSYCH) Busy Channel 7 Position */
+#define DMAC_BUSYCH_BUSYCH7_Msk               (_UINT32_(0x1) << DMAC_BUSYCH_BUSYCH7_Pos)           /* (DMAC_BUSYCH) Busy Channel 7 Mask */
+#define DMAC_BUSYCH_BUSYCH7(value)            (DMAC_BUSYCH_BUSYCH7_Msk & (_UINT32_(value) << DMAC_BUSYCH_BUSYCH7_Pos)) /* Assignment of value for BUSYCH7 in the DMAC_BUSYCH register */
+#define DMAC_BUSYCH_Msk                       _UINT32_(0x000000FF)                                 /* (DMAC_BUSYCH) Register Mask  */
+
+#define DMAC_BUSYCH_BUSYCH_Pos                _UINT32_(0)                                          /* (DMAC_BUSYCH Position) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH_Msk                (_UINT32_(0xFF) << DMAC_BUSYCH_BUSYCH_Pos)           /* (DMAC_BUSYCH Mask) BUSYCH */
+#define DMAC_BUSYCH_BUSYCH(value)             (DMAC_BUSYCH_BUSYCH_Msk & (_UINT32_(value) << DMAC_BUSYCH_BUSYCH_Pos)) 
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) ( R/ 32) Pending Channels -------- */
+#define DMAC_PENDCH_RESETVALUE                _UINT32_(0x00)                                       /*  (DMAC_PENDCH) Pending Channels  Reset Value */
+
+#define DMAC_PENDCH_PENDCH0_Pos               _UINT32_(0)                                          /* (DMAC_PENDCH) Pending Channel 0 Position */
+#define DMAC_PENDCH_PENDCH0_Msk               (_UINT32_(0x1) << DMAC_PENDCH_PENDCH0_Pos)           /* (DMAC_PENDCH) Pending Channel 0 Mask */
+#define DMAC_PENDCH_PENDCH0(value)            (DMAC_PENDCH_PENDCH0_Msk & (_UINT32_(value) << DMAC_PENDCH_PENDCH0_Pos)) /* Assignment of value for PENDCH0 in the DMAC_PENDCH register */
+#define DMAC_PENDCH_PENDCH1_Pos               _UINT32_(1)                                          /* (DMAC_PENDCH) Pending Channel 1 Position */
+#define DMAC_PENDCH_PENDCH1_Msk               (_UINT32_(0x1) << DMAC_PENDCH_PENDCH1_Pos)           /* (DMAC_PENDCH) Pending Channel 1 Mask */
+#define DMAC_PENDCH_PENDCH1(value)            (DMAC_PENDCH_PENDCH1_Msk & (_UINT32_(value) << DMAC_PENDCH_PENDCH1_Pos)) /* Assignment of value for PENDCH1 in the DMAC_PENDCH register */
+#define DMAC_PENDCH_PENDCH2_Pos               _UINT32_(2)                                          /* (DMAC_PENDCH) Pending Channel 2 Position */
+#define DMAC_PENDCH_PENDCH2_Msk               (_UINT32_(0x1) << DMAC_PENDCH_PENDCH2_Pos)           /* (DMAC_PENDCH) Pending Channel 2 Mask */
+#define DMAC_PENDCH_PENDCH2(value)            (DMAC_PENDCH_PENDCH2_Msk & (_UINT32_(value) << DMAC_PENDCH_PENDCH2_Pos)) /* Assignment of value for PENDCH2 in the DMAC_PENDCH register */
+#define DMAC_PENDCH_PENDCH3_Pos               _UINT32_(3)                                          /* (DMAC_PENDCH) Pending Channel 3 Position */
+#define DMAC_PENDCH_PENDCH3_Msk               (_UINT32_(0x1) << DMAC_PENDCH_PENDCH3_Pos)           /* (DMAC_PENDCH) Pending Channel 3 Mask */
+#define DMAC_PENDCH_PENDCH3(value)            (DMAC_PENDCH_PENDCH3_Msk & (_UINT32_(value) << DMAC_PENDCH_PENDCH3_Pos)) /* Assignment of value for PENDCH3 in the DMAC_PENDCH register */
+#define DMAC_PENDCH_PENDCH4_Pos               _UINT32_(4)                                          /* (DMAC_PENDCH) Pending Channel 4 Position */
+#define DMAC_PENDCH_PENDCH4_Msk               (_UINT32_(0x1) << DMAC_PENDCH_PENDCH4_Pos)           /* (DMAC_PENDCH) Pending Channel 4 Mask */
+#define DMAC_PENDCH_PENDCH4(value)            (DMAC_PENDCH_PENDCH4_Msk & (_UINT32_(value) << DMAC_PENDCH_PENDCH4_Pos)) /* Assignment of value for PENDCH4 in the DMAC_PENDCH register */
+#define DMAC_PENDCH_PENDCH5_Pos               _UINT32_(5)                                          /* (DMAC_PENDCH) Pending Channel 5 Position */
+#define DMAC_PENDCH_PENDCH5_Msk               (_UINT32_(0x1) << DMAC_PENDCH_PENDCH5_Pos)           /* (DMAC_PENDCH) Pending Channel 5 Mask */
+#define DMAC_PENDCH_PENDCH5(value)            (DMAC_PENDCH_PENDCH5_Msk & (_UINT32_(value) << DMAC_PENDCH_PENDCH5_Pos)) /* Assignment of value for PENDCH5 in the DMAC_PENDCH register */
+#define DMAC_PENDCH_PENDCH6_Pos               _UINT32_(6)                                          /* (DMAC_PENDCH) Pending Channel 6 Position */
+#define DMAC_PENDCH_PENDCH6_Msk               (_UINT32_(0x1) << DMAC_PENDCH_PENDCH6_Pos)           /* (DMAC_PENDCH) Pending Channel 6 Mask */
+#define DMAC_PENDCH_PENDCH6(value)            (DMAC_PENDCH_PENDCH6_Msk & (_UINT32_(value) << DMAC_PENDCH_PENDCH6_Pos)) /* Assignment of value for PENDCH6 in the DMAC_PENDCH register */
+#define DMAC_PENDCH_PENDCH7_Pos               _UINT32_(7)                                          /* (DMAC_PENDCH) Pending Channel 7 Position */
+#define DMAC_PENDCH_PENDCH7_Msk               (_UINT32_(0x1) << DMAC_PENDCH_PENDCH7_Pos)           /* (DMAC_PENDCH) Pending Channel 7 Mask */
+#define DMAC_PENDCH_PENDCH7(value)            (DMAC_PENDCH_PENDCH7_Msk & (_UINT32_(value) << DMAC_PENDCH_PENDCH7_Pos)) /* Assignment of value for PENDCH7 in the DMAC_PENDCH register */
+#define DMAC_PENDCH_Msk                       _UINT32_(0x000000FF)                                 /* (DMAC_PENDCH) Register Mask  */
+
+#define DMAC_PENDCH_PENDCH_Pos                _UINT32_(0)                                          /* (DMAC_PENDCH Position) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH_Msk                (_UINT32_(0xFF) << DMAC_PENDCH_PENDCH_Pos)           /* (DMAC_PENDCH Mask) PENDCH */
+#define DMAC_PENDCH_PENDCH(value)             (DMAC_PENDCH_PENDCH_Msk & (_UINT32_(value) << DMAC_PENDCH_PENDCH_Pos)) 
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) ( R/ 32) Active Channel and Levels -------- */
+#define DMAC_ACTIVE_RESETVALUE                _UINT32_(0x00)                                       /*  (DMAC_ACTIVE) Active Channel and Levels  Reset Value */
+
+#define DMAC_ACTIVE_LVLEX0_Pos                _UINT32_(0)                                          /* (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing Position */
+#define DMAC_ACTIVE_LVLEX0_Msk                (_UINT32_(0x1) << DMAC_ACTIVE_LVLEX0_Pos)            /* (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing Mask */
+#define DMAC_ACTIVE_LVLEX0(value)             (DMAC_ACTIVE_LVLEX0_Msk & (_UINT32_(value) << DMAC_ACTIVE_LVLEX0_Pos)) /* Assignment of value for LVLEX0 in the DMAC_ACTIVE register */
+#define DMAC_ACTIVE_LVLEX1_Pos                _UINT32_(1)                                          /* (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing Position */
+#define DMAC_ACTIVE_LVLEX1_Msk                (_UINT32_(0x1) << DMAC_ACTIVE_LVLEX1_Pos)            /* (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing Mask */
+#define DMAC_ACTIVE_LVLEX1(value)             (DMAC_ACTIVE_LVLEX1_Msk & (_UINT32_(value) << DMAC_ACTIVE_LVLEX1_Pos)) /* Assignment of value for LVLEX1 in the DMAC_ACTIVE register */
+#define DMAC_ACTIVE_LVLEX2_Pos                _UINT32_(2)                                          /* (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing Position */
+#define DMAC_ACTIVE_LVLEX2_Msk                (_UINT32_(0x1) << DMAC_ACTIVE_LVLEX2_Pos)            /* (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing Mask */
+#define DMAC_ACTIVE_LVLEX2(value)             (DMAC_ACTIVE_LVLEX2_Msk & (_UINT32_(value) << DMAC_ACTIVE_LVLEX2_Pos)) /* Assignment of value for LVLEX2 in the DMAC_ACTIVE register */
+#define DMAC_ACTIVE_LVLEX3_Pos                _UINT32_(3)                                          /* (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing Position */
+#define DMAC_ACTIVE_LVLEX3_Msk                (_UINT32_(0x1) << DMAC_ACTIVE_LVLEX3_Pos)            /* (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing Mask */
+#define DMAC_ACTIVE_LVLEX3(value)             (DMAC_ACTIVE_LVLEX3_Msk & (_UINT32_(value) << DMAC_ACTIVE_LVLEX3_Pos)) /* Assignment of value for LVLEX3 in the DMAC_ACTIVE register */
+#define DMAC_ACTIVE_ID_Pos                    _UINT32_(8)                                          /* (DMAC_ACTIVE) Active Channel ID Position */
+#define DMAC_ACTIVE_ID_Msk                    (_UINT32_(0x1F) << DMAC_ACTIVE_ID_Pos)               /* (DMAC_ACTIVE) Active Channel ID Mask */
+#define DMAC_ACTIVE_ID(value)                 (DMAC_ACTIVE_ID_Msk & (_UINT32_(value) << DMAC_ACTIVE_ID_Pos)) /* Assignment of value for ID in the DMAC_ACTIVE register */
+#define DMAC_ACTIVE_ABUSY_Pos                 _UINT32_(15)                                         /* (DMAC_ACTIVE) Active Channel Busy Position */
+#define DMAC_ACTIVE_ABUSY_Msk                 (_UINT32_(0x1) << DMAC_ACTIVE_ABUSY_Pos)             /* (DMAC_ACTIVE) Active Channel Busy Mask */
+#define DMAC_ACTIVE_ABUSY(value)              (DMAC_ACTIVE_ABUSY_Msk & (_UINT32_(value) << DMAC_ACTIVE_ABUSY_Pos)) /* Assignment of value for ABUSY in the DMAC_ACTIVE register */
+#define DMAC_ACTIVE_BTCNT_Pos                 _UINT32_(16)                                         /* (DMAC_ACTIVE) Active Channel Block Transfer Count Position */
+#define DMAC_ACTIVE_BTCNT_Msk                 (_UINT32_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)          /* (DMAC_ACTIVE) Active Channel Block Transfer Count Mask */
+#define DMAC_ACTIVE_BTCNT(value)              (DMAC_ACTIVE_BTCNT_Msk & (_UINT32_(value) << DMAC_ACTIVE_BTCNT_Pos)) /* Assignment of value for BTCNT in the DMAC_ACTIVE register */
+#define DMAC_ACTIVE_Msk                       _UINT32_(0xFFFF9F0F)                                 /* (DMAC_ACTIVE) Register Mask  */
+
+#define DMAC_ACTIVE_LVLEX_Pos                 _UINT32_(0)                                          /* (DMAC_ACTIVE Position) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk                 (_UINT32_(0xF) << DMAC_ACTIVE_LVLEX_Pos)             /* (DMAC_ACTIVE Mask) LVLEX */
+#define DMAC_ACTIVE_LVLEX(value)              (DMAC_ACTIVE_LVLEX_Msk & (_UINT32_(value) << DMAC_ACTIVE_LVLEX_Pos)) 
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#define DMAC_BASEADDR_RESETVALUE              _UINT32_(0x00)                                       /*  (DMAC_BASEADDR) Descriptor Memory Section Base Address  Reset Value */
+
+#define DMAC_BASEADDR_BASEADDR_Pos            _UINT32_(0)                                          /* (DMAC_BASEADDR) Descriptor Memory Base Address Position */
+#define DMAC_BASEADDR_BASEADDR_Msk            (_UINT32_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) /* (DMAC_BASEADDR) Descriptor Memory Base Address Mask */
+#define DMAC_BASEADDR_BASEADDR(value)         (DMAC_BASEADDR_BASEADDR_Msk & (_UINT32_(value) << DMAC_BASEADDR_BASEADDR_Pos)) /* Assignment of value for BASEADDR in the DMAC_BASEADDR register */
+#define DMAC_BASEADDR_Msk                     _UINT32_(0xFFFFFFFF)                                 /* (DMAC_BASEADDR) Register Mask  */
+
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#define DMAC_WRBADDR_RESETVALUE               _UINT32_(0x00)                                       /*  (DMAC_WRBADDR) Write-Back Memory Section Base Address  Reset Value */
+
+#define DMAC_WRBADDR_WRBADDR_Pos              _UINT32_(0)                                          /* (DMAC_WRBADDR) Write-Back Memory Base Address Position */
+#define DMAC_WRBADDR_WRBADDR_Msk              (_UINT32_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)   /* (DMAC_WRBADDR) Write-Back Memory Base Address Mask */
+#define DMAC_WRBADDR_WRBADDR(value)           (DMAC_WRBADDR_WRBADDR_Msk & (_UINT32_(value) << DMAC_WRBADDR_WRBADDR_Pos)) /* Assignment of value for WRBADDR in the DMAC_WRBADDR register */
+#define DMAC_WRBADDR_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (DMAC_WRBADDR) Register Mask  */
+
+
+/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
+#define DMAC_CHID_RESETVALUE                  _UINT8_(0x00)                                        /*  (DMAC_CHID) Channel ID  Reset Value */
+
+#define DMAC_CHID_ID_Pos                      _UINT8_(0)                                           /* (DMAC_CHID) Channel ID Position */
+#define DMAC_CHID_ID_Msk                      (_UINT8_(0x7) << DMAC_CHID_ID_Pos)                   /* (DMAC_CHID) Channel ID Mask */
+#define DMAC_CHID_ID(value)                   (DMAC_CHID_ID_Msk & (_UINT8_(value) << DMAC_CHID_ID_Pos)) /* Assignment of value for ID in the DMAC_CHID register */
+#define DMAC_CHID_Msk                         _UINT8_(0x07)                                        /* (DMAC_CHID) Register Mask  */
+
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
+#define DMAC_CHCTRLA_RESETVALUE               _UINT8_(0x00)                                        /*  (DMAC_CHCTRLA) Channel Control A  Reset Value */
+
+#define DMAC_CHCTRLA_SWRST_Pos                _UINT8_(0)                                           /* (DMAC_CHCTRLA) Channel Software Reset Position */
+#define DMAC_CHCTRLA_SWRST_Msk                (_UINT8_(0x1) << DMAC_CHCTRLA_SWRST_Pos)             /* (DMAC_CHCTRLA) Channel Software Reset Mask */
+#define DMAC_CHCTRLA_SWRST(value)             (DMAC_CHCTRLA_SWRST_Msk & (_UINT8_(value) << DMAC_CHCTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the DMAC_CHCTRLA register */
+#define DMAC_CHCTRLA_ENABLE_Pos               _UINT8_(1)                                           /* (DMAC_CHCTRLA) Channel Enable Position */
+#define DMAC_CHCTRLA_ENABLE_Msk               (_UINT8_(0x1) << DMAC_CHCTRLA_ENABLE_Pos)            /* (DMAC_CHCTRLA) Channel Enable Mask */
+#define DMAC_CHCTRLA_ENABLE(value)            (DMAC_CHCTRLA_ENABLE_Msk & (_UINT8_(value) << DMAC_CHCTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the DMAC_CHCTRLA register */
+#define DMAC_CHCTRLA_RUNSTDBY_Pos             _UINT8_(6)                                           /* (DMAC_CHCTRLA) Channel run in standby Position */
+#define DMAC_CHCTRLA_RUNSTDBY_Msk             (_UINT8_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos)          /* (DMAC_CHCTRLA) Channel run in standby Mask */
+#define DMAC_CHCTRLA_RUNSTDBY(value)          (DMAC_CHCTRLA_RUNSTDBY_Msk & (_UINT8_(value) << DMAC_CHCTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the DMAC_CHCTRLA register */
+#define DMAC_CHCTRLA_Msk                      _UINT8_(0x43)                                        /* (DMAC_CHCTRLA) Register Mask  */
+
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
+#define DMAC_CHCTRLB_RESETVALUE               _UINT32_(0x00)                                       /*  (DMAC_CHCTRLB) Channel Control B  Reset Value */
+
+#define DMAC_CHCTRLB_EVACT_Pos                _UINT32_(0)                                          /* (DMAC_CHCTRLB) Event Input Action Position */
+#define DMAC_CHCTRLB_EVACT_Msk                (_UINT32_(0x7) << DMAC_CHCTRLB_EVACT_Pos)            /* (DMAC_CHCTRLB) Event Input Action Mask */
+#define DMAC_CHCTRLB_EVACT(value)             (DMAC_CHCTRLB_EVACT_Msk & (_UINT32_(value) << DMAC_CHCTRLB_EVACT_Pos)) /* Assignment of value for EVACT in the DMAC_CHCTRLB register */
+#define   DMAC_CHCTRLB_EVACT_NOACT_Val        _UINT32_(0x0)                                        /* (DMAC_CHCTRLB) No action  */
+#define   DMAC_CHCTRLB_EVACT_TRIG_Val         _UINT32_(0x1)                                        /* (DMAC_CHCTRLB) Transfer and periodic transfer trigger  */
+#define   DMAC_CHCTRLB_EVACT_CTRIG_Val        _UINT32_(0x2)                                        /* (DMAC_CHCTRLB) Conditional transfer trigger  */
+#define   DMAC_CHCTRLB_EVACT_CBLOCK_Val       _UINT32_(0x3)                                        /* (DMAC_CHCTRLB) Conditional block transfer  */
+#define   DMAC_CHCTRLB_EVACT_SUSPEND_Val      _UINT32_(0x4)                                        /* (DMAC_CHCTRLB) Channel suspend operation  */
+#define   DMAC_CHCTRLB_EVACT_RESUME_Val       _UINT32_(0x5)                                        /* (DMAC_CHCTRLB) Channel resume operation  */
+#define   DMAC_CHCTRLB_EVACT_SSKIP_Val        _UINT32_(0x6)                                        /* (DMAC_CHCTRLB) Skip next block suspend action  */
+#define DMAC_CHCTRLB_EVACT_NOACT              (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) /* (DMAC_CHCTRLB) No action Position */
+#define DMAC_CHCTRLB_EVACT_TRIG               (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) /* (DMAC_CHCTRLB) Transfer and periodic transfer trigger Position */
+#define DMAC_CHCTRLB_EVACT_CTRIG              (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) /* (DMAC_CHCTRLB) Conditional transfer trigger Position */
+#define DMAC_CHCTRLB_EVACT_CBLOCK             (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) /* (DMAC_CHCTRLB) Conditional block transfer Position */
+#define DMAC_CHCTRLB_EVACT_SUSPEND            (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) /* (DMAC_CHCTRLB) Channel suspend operation Position */
+#define DMAC_CHCTRLB_EVACT_RESUME             (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) /* (DMAC_CHCTRLB) Channel resume operation Position */
+#define DMAC_CHCTRLB_EVACT_SSKIP              (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) /* (DMAC_CHCTRLB) Skip next block suspend action Position */
+#define DMAC_CHCTRLB_EVIE_Pos                 _UINT32_(3)                                          /* (DMAC_CHCTRLB) Channel Event Input Enable Position */
+#define DMAC_CHCTRLB_EVIE_Msk                 (_UINT32_(0x1) << DMAC_CHCTRLB_EVIE_Pos)             /* (DMAC_CHCTRLB) Channel Event Input Enable Mask */
+#define DMAC_CHCTRLB_EVIE(value)              (DMAC_CHCTRLB_EVIE_Msk & (_UINT32_(value) << DMAC_CHCTRLB_EVIE_Pos)) /* Assignment of value for EVIE in the DMAC_CHCTRLB register */
+#define DMAC_CHCTRLB_EVOE_Pos                 _UINT32_(4)                                          /* (DMAC_CHCTRLB) Channel Event Output Enable Position */
+#define DMAC_CHCTRLB_EVOE_Msk                 (_UINT32_(0x1) << DMAC_CHCTRLB_EVOE_Pos)             /* (DMAC_CHCTRLB) Channel Event Output Enable Mask */
+#define DMAC_CHCTRLB_EVOE(value)              (DMAC_CHCTRLB_EVOE_Msk & (_UINT32_(value) << DMAC_CHCTRLB_EVOE_Pos)) /* Assignment of value for EVOE in the DMAC_CHCTRLB register */
+#define DMAC_CHCTRLB_LVL_Pos                  _UINT32_(5)                                          /* (DMAC_CHCTRLB) Channel Arbitration Level Position */
+#define DMAC_CHCTRLB_LVL_Msk                  (_UINT32_(0x3) << DMAC_CHCTRLB_LVL_Pos)              /* (DMAC_CHCTRLB) Channel Arbitration Level Mask */
+#define DMAC_CHCTRLB_LVL(value)               (DMAC_CHCTRLB_LVL_Msk & (_UINT32_(value) << DMAC_CHCTRLB_LVL_Pos)) /* Assignment of value for LVL in the DMAC_CHCTRLB register */
+#define DMAC_CHCTRLB_TRIGSRC_Pos              _UINT32_(8)                                          /* (DMAC_CHCTRLB) Trigger Source Position */
+#define DMAC_CHCTRLB_TRIGSRC_Msk              (_UINT32_(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos)         /* (DMAC_CHCTRLB) Trigger Source Mask */
+#define DMAC_CHCTRLB_TRIGSRC(value)           (DMAC_CHCTRLB_TRIGSRC_Msk & (_UINT32_(value) << DMAC_CHCTRLB_TRIGSRC_Pos)) /* Assignment of value for TRIGSRC in the DMAC_CHCTRLB register */
+#define   DMAC_CHCTRLB_TRIGSRC_DISABLE_Val    _UINT32_(0x0)                                        /* (DMAC_CHCTRLB) Only software/event triggers  */
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE          (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) /* (DMAC_CHCTRLB) Only software/event triggers Position */
+#define DMAC_CHCTRLB_TRIGACT_Pos              _UINT32_(22)                                         /* (DMAC_CHCTRLB) Trigger Action Position */
+#define DMAC_CHCTRLB_TRIGACT_Msk              (_UINT32_(0x3) << DMAC_CHCTRLB_TRIGACT_Pos)          /* (DMAC_CHCTRLB) Trigger Action Mask */
+#define DMAC_CHCTRLB_TRIGACT(value)           (DMAC_CHCTRLB_TRIGACT_Msk & (_UINT32_(value) << DMAC_CHCTRLB_TRIGACT_Pos)) /* Assignment of value for TRIGACT in the DMAC_CHCTRLB register */
+#define   DMAC_CHCTRLB_TRIGACT_BLOCK_Val      _UINT32_(0x0)                                        /* (DMAC_CHCTRLB) One trigger required for each block transfer  */
+#define   DMAC_CHCTRLB_TRIGACT_BEAT_Val       _UINT32_(0x2)                                        /* (DMAC_CHCTRLB) One trigger required for each beat transfer  */
+#define   DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _UINT32_(0x3)                                        /* (DMAC_CHCTRLB) One trigger required for each transaction  */
+#define DMAC_CHCTRLB_TRIGACT_BLOCK            (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) /* (DMAC_CHCTRLB) One trigger required for each block transfer Position */
+#define DMAC_CHCTRLB_TRIGACT_BEAT             (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) /* (DMAC_CHCTRLB) One trigger required for each beat transfer Position */
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION      (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) /* (DMAC_CHCTRLB) One trigger required for each transaction Position */
+#define DMAC_CHCTRLB_CMD_Pos                  _UINT32_(24)                                         /* (DMAC_CHCTRLB) Software Command Position */
+#define DMAC_CHCTRLB_CMD_Msk                  (_UINT32_(0x3) << DMAC_CHCTRLB_CMD_Pos)              /* (DMAC_CHCTRLB) Software Command Mask */
+#define DMAC_CHCTRLB_CMD(value)               (DMAC_CHCTRLB_CMD_Msk & (_UINT32_(value) << DMAC_CHCTRLB_CMD_Pos)) /* Assignment of value for CMD in the DMAC_CHCTRLB register */
+#define   DMAC_CHCTRLB_CMD_NOACT_Val          _UINT32_(0x0)                                        /* (DMAC_CHCTRLB) No action  */
+#define   DMAC_CHCTRLB_CMD_SUSPEND_Val        _UINT32_(0x1)                                        /* (DMAC_CHCTRLB) Channel suspend operation  */
+#define   DMAC_CHCTRLB_CMD_RESUME_Val         _UINT32_(0x2)                                        /* (DMAC_CHCTRLB) Channel resume operation  */
+#define DMAC_CHCTRLB_CMD_NOACT                (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) /* (DMAC_CHCTRLB) No action Position */
+#define DMAC_CHCTRLB_CMD_SUSPEND              (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) /* (DMAC_CHCTRLB) Channel suspend operation Position */
+#define DMAC_CHCTRLB_CMD_RESUME               (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) /* (DMAC_CHCTRLB) Channel resume operation Position */
+#define DMAC_CHCTRLB_Msk                      _UINT32_(0x03C03F7F)                                 /* (DMAC_CHCTRLB) Register Mask  */
+
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
+#define DMAC_CHINTENCLR_RESETVALUE            _UINT8_(0x00)                                        /*  (DMAC_CHINTENCLR) Channel Interrupt Enable Clear  Reset Value */
+
+#define DMAC_CHINTENCLR_TERR_Pos              _UINT8_(0)                                           /* (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable Position */
+#define DMAC_CHINTENCLR_TERR_Msk              (_UINT8_(0x1) << DMAC_CHINTENCLR_TERR_Pos)           /* (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable Mask */
+#define DMAC_CHINTENCLR_TERR(value)           (DMAC_CHINTENCLR_TERR_Msk & (_UINT8_(value) << DMAC_CHINTENCLR_TERR_Pos)) /* Assignment of value for TERR in the DMAC_CHINTENCLR register */
+#define DMAC_CHINTENCLR_TCMPL_Pos             _UINT8_(1)                                           /* (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable Position */
+#define DMAC_CHINTENCLR_TCMPL_Msk             (_UINT8_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)          /* (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable Mask */
+#define DMAC_CHINTENCLR_TCMPL(value)          (DMAC_CHINTENCLR_TCMPL_Msk & (_UINT8_(value) << DMAC_CHINTENCLR_TCMPL_Pos)) /* Assignment of value for TCMPL in the DMAC_CHINTENCLR register */
+#define DMAC_CHINTENCLR_SUSP_Pos              _UINT8_(2)                                           /* (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable Position */
+#define DMAC_CHINTENCLR_SUSP_Msk              (_UINT8_(0x1) << DMAC_CHINTENCLR_SUSP_Pos)           /* (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable Mask */
+#define DMAC_CHINTENCLR_SUSP(value)           (DMAC_CHINTENCLR_SUSP_Msk & (_UINT8_(value) << DMAC_CHINTENCLR_SUSP_Pos)) /* Assignment of value for SUSP in the DMAC_CHINTENCLR register */
+#define DMAC_CHINTENCLR_Msk                   _UINT8_(0x07)                                        /* (DMAC_CHINTENCLR) Register Mask  */
+
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
+#define DMAC_CHINTENSET_RESETVALUE            _UINT8_(0x00)                                        /*  (DMAC_CHINTENSET) Channel Interrupt Enable Set  Reset Value */
+
+#define DMAC_CHINTENSET_TERR_Pos              _UINT8_(0)                                           /* (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable Position */
+#define DMAC_CHINTENSET_TERR_Msk              (_UINT8_(0x1) << DMAC_CHINTENSET_TERR_Pos)           /* (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable Mask */
+#define DMAC_CHINTENSET_TERR(value)           (DMAC_CHINTENSET_TERR_Msk & (_UINT8_(value) << DMAC_CHINTENSET_TERR_Pos)) /* Assignment of value for TERR in the DMAC_CHINTENSET register */
+#define DMAC_CHINTENSET_TCMPL_Pos             _UINT8_(1)                                           /* (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable Position */
+#define DMAC_CHINTENSET_TCMPL_Msk             (_UINT8_(0x1) << DMAC_CHINTENSET_TCMPL_Pos)          /* (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable Mask */
+#define DMAC_CHINTENSET_TCMPL(value)          (DMAC_CHINTENSET_TCMPL_Msk & (_UINT8_(value) << DMAC_CHINTENSET_TCMPL_Pos)) /* Assignment of value for TCMPL in the DMAC_CHINTENSET register */
+#define DMAC_CHINTENSET_SUSP_Pos              _UINT8_(2)                                           /* (DMAC_CHINTENSET) Channel Suspend Interrupt Enable Position */
+#define DMAC_CHINTENSET_SUSP_Msk              (_UINT8_(0x1) << DMAC_CHINTENSET_SUSP_Pos)           /* (DMAC_CHINTENSET) Channel Suspend Interrupt Enable Mask */
+#define DMAC_CHINTENSET_SUSP(value)           (DMAC_CHINTENSET_SUSP_Msk & (_UINT8_(value) << DMAC_CHINTENSET_SUSP_Pos)) /* Assignment of value for SUSP in the DMAC_CHINTENSET register */
+#define DMAC_CHINTENSET_Msk                   _UINT8_(0x07)                                        /* (DMAC_CHINTENSET) Register Mask  */
+
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
+#define DMAC_CHINTFLAG_RESETVALUE             _UINT8_(0x00)                                        /*  (DMAC_CHINTFLAG) Channel Interrupt Flag Status and Clear  Reset Value */
+
+#define DMAC_CHINTFLAG_TERR_Pos               _UINT8_(0)                                           /* (DMAC_CHINTFLAG) Channel Transfer Error Position */
+#define DMAC_CHINTFLAG_TERR_Msk               (_UINT8_(0x1) << DMAC_CHINTFLAG_TERR_Pos)            /* (DMAC_CHINTFLAG) Channel Transfer Error Mask */
+#define DMAC_CHINTFLAG_TERR(value)            (DMAC_CHINTFLAG_TERR_Msk & (_UINT8_(value) << DMAC_CHINTFLAG_TERR_Pos)) /* Assignment of value for TERR in the DMAC_CHINTFLAG register */
+#define DMAC_CHINTFLAG_TCMPL_Pos              _UINT8_(1)                                           /* (DMAC_CHINTFLAG) Channel Transfer Complete Position */
+#define DMAC_CHINTFLAG_TCMPL_Msk              (_UINT8_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)           /* (DMAC_CHINTFLAG) Channel Transfer Complete Mask */
+#define DMAC_CHINTFLAG_TCMPL(value)           (DMAC_CHINTFLAG_TCMPL_Msk & (_UINT8_(value) << DMAC_CHINTFLAG_TCMPL_Pos)) /* Assignment of value for TCMPL in the DMAC_CHINTFLAG register */
+#define DMAC_CHINTFLAG_SUSP_Pos               _UINT8_(2)                                           /* (DMAC_CHINTFLAG) Channel Suspend Position */
+#define DMAC_CHINTFLAG_SUSP_Msk               (_UINT8_(0x1) << DMAC_CHINTFLAG_SUSP_Pos)            /* (DMAC_CHINTFLAG) Channel Suspend Mask */
+#define DMAC_CHINTFLAG_SUSP(value)            (DMAC_CHINTFLAG_SUSP_Msk & (_UINT8_(value) << DMAC_CHINTFLAG_SUSP_Pos)) /* Assignment of value for SUSP in the DMAC_CHINTFLAG register */
+#define DMAC_CHINTFLAG_Msk                    _UINT8_(0x07)                                        /* (DMAC_CHINTFLAG) Register Mask  */
+
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) ( R/ 8) Channel Status -------- */
+#define DMAC_CHSTATUS_RESETVALUE              _UINT8_(0x00)                                        /*  (DMAC_CHSTATUS) Channel Status  Reset Value */
+
+#define DMAC_CHSTATUS_PEND_Pos                _UINT8_(0)                                           /* (DMAC_CHSTATUS) Channel Pending Position */
+#define DMAC_CHSTATUS_PEND_Msk                (_UINT8_(0x1) << DMAC_CHSTATUS_PEND_Pos)             /* (DMAC_CHSTATUS) Channel Pending Mask */
+#define DMAC_CHSTATUS_PEND(value)             (DMAC_CHSTATUS_PEND_Msk & (_UINT8_(value) << DMAC_CHSTATUS_PEND_Pos)) /* Assignment of value for PEND in the DMAC_CHSTATUS register */
+#define DMAC_CHSTATUS_BUSY_Pos                _UINT8_(1)                                           /* (DMAC_CHSTATUS) Channel Busy Position */
+#define DMAC_CHSTATUS_BUSY_Msk                (_UINT8_(0x1) << DMAC_CHSTATUS_BUSY_Pos)             /* (DMAC_CHSTATUS) Channel Busy Mask */
+#define DMAC_CHSTATUS_BUSY(value)             (DMAC_CHSTATUS_BUSY_Msk & (_UINT8_(value) << DMAC_CHSTATUS_BUSY_Pos)) /* Assignment of value for BUSY in the DMAC_CHSTATUS register */
+#define DMAC_CHSTATUS_FERR_Pos                _UINT8_(2)                                           /* (DMAC_CHSTATUS) Channel Fetch Error Position */
+#define DMAC_CHSTATUS_FERR_Msk                (_UINT8_(0x1) << DMAC_CHSTATUS_FERR_Pos)             /* (DMAC_CHSTATUS) Channel Fetch Error Mask */
+#define DMAC_CHSTATUS_FERR(value)             (DMAC_CHSTATUS_FERR_Msk & (_UINT8_(value) << DMAC_CHSTATUS_FERR_Pos)) /* Assignment of value for FERR in the DMAC_CHSTATUS register */
+#define DMAC_CHSTATUS_Msk                     _UINT8_(0x07)                                        /* (DMAC_CHSTATUS) Register Mask  */
+
+
+/* DMAC register offsets definitions */
+#define DMAC_BTCTRL_REG_OFST           _UINT32_(0x00)      /* (DMAC_BTCTRL) Block Transfer Control Offset */
+#define DMAC_BTCNT_REG_OFST            _UINT32_(0x02)      /* (DMAC_BTCNT) Block Transfer Count Offset */
+#define DMAC_SRCADDR_REG_OFST          _UINT32_(0x04)      /* (DMAC_SRCADDR) Block Transfer Source Address Offset */
+#define DMAC_DSTADDR_REG_OFST          _UINT32_(0x08)      /* (DMAC_DSTADDR) Block Transfer Destination Address Offset */
+#define DMAC_DESCADDR_REG_OFST         _UINT32_(0x0C)      /* (DMAC_DESCADDR) Next Descriptor Address Offset */
+#define DMAC_CTRL_REG_OFST             _UINT32_(0x00)      /* (DMAC_CTRL) Control Offset */
+#define DMAC_CRCCTRL_REG_OFST          _UINT32_(0x02)      /* (DMAC_CRCCTRL) CRC Control Offset */
+#define DMAC_CRCDATAIN_REG_OFST        _UINT32_(0x04)      /* (DMAC_CRCDATAIN) CRC Data Input Offset */
+#define DMAC_CRCCHKSUM_REG_OFST        _UINT32_(0x08)      /* (DMAC_CRCCHKSUM) CRC Checksum Offset */
+#define DMAC_CRCSTATUS_REG_OFST        _UINT32_(0x0C)      /* (DMAC_CRCSTATUS) CRC Status Offset */
+#define DMAC_DBGCTRL_REG_OFST          _UINT32_(0x0D)      /* (DMAC_DBGCTRL) Debug Control Offset */
+#define DMAC_QOSCTRL_REG_OFST          _UINT32_(0x0E)      /* (DMAC_QOSCTRL) QOS Control Offset */
+#define DMAC_SWTRIGCTRL_REG_OFST       _UINT32_(0x10)      /* (DMAC_SWTRIGCTRL) Software Trigger Control Offset */
+#define DMAC_PRICTRL0_REG_OFST         _UINT32_(0x14)      /* (DMAC_PRICTRL0) Priority Control 0 Offset */
+#define DMAC_INTPEND_REG_OFST          _UINT32_(0x20)      /* (DMAC_INTPEND) Interrupt Pending Offset */
+#define DMAC_INTSTATUS_REG_OFST        _UINT32_(0x24)      /* (DMAC_INTSTATUS) Interrupt Status Offset */
+#define DMAC_BUSYCH_REG_OFST           _UINT32_(0x28)      /* (DMAC_BUSYCH) Busy Channels Offset */
+#define DMAC_PENDCH_REG_OFST           _UINT32_(0x2C)      /* (DMAC_PENDCH) Pending Channels Offset */
+#define DMAC_ACTIVE_REG_OFST           _UINT32_(0x30)      /* (DMAC_ACTIVE) Active Channel and Levels Offset */
+#define DMAC_BASEADDR_REG_OFST         _UINT32_(0x34)      /* (DMAC_BASEADDR) Descriptor Memory Section Base Address Offset */
+#define DMAC_WRBADDR_REG_OFST          _UINT32_(0x38)      /* (DMAC_WRBADDR) Write-Back Memory Section Base Address Offset */
+#define DMAC_CHID_REG_OFST             _UINT32_(0x3F)      /* (DMAC_CHID) Channel ID Offset */
+#define DMAC_CHCTRLA_REG_OFST          _UINT32_(0x40)      /* (DMAC_CHCTRLA) Channel Control A Offset */
+#define DMAC_CHCTRLB_REG_OFST          _UINT32_(0x44)      /* (DMAC_CHCTRLB) Channel Control B Offset */
+#define DMAC_CHINTENCLR_REG_OFST       _UINT32_(0x4C)      /* (DMAC_CHINTENCLR) Channel Interrupt Enable Clear Offset */
+#define DMAC_CHINTENSET_REG_OFST       _UINT32_(0x4D)      /* (DMAC_CHINTENSET) Channel Interrupt Enable Set Offset */
+#define DMAC_CHINTFLAG_REG_OFST        _UINT32_(0x4E)      /* (DMAC_CHINTFLAG) Channel Interrupt Flag Status and Clear Offset */
+#define DMAC_CHSTATUS_REG_OFST         _UINT32_(0x4F)      /* (DMAC_CHSTATUS) Channel Status Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* DMAC_DESCRIPTOR register API structure */
+typedef struct
+{  /* Direct Memory Access Controller */
+  __IO  uint16_t                       DMAC_BTCTRL;        /* Offset: 0x00 (R/W  16) Block Transfer Control */
+  __IO  uint16_t                       DMAC_BTCNT;         /* Offset: 0x02 (R/W  16) Block Transfer Count */
+  __IO  uint32_t                       DMAC_SRCADDR;       /* Offset: 0x04 (R/W  32) Block Transfer Source Address */
+  __IO  uint32_t                       DMAC_DSTADDR;       /* Offset: 0x08 (R/W  32) Block Transfer Destination Address */
+  __IO  uint32_t                       DMAC_DESCADDR;      /* Offset: 0x0C (R/W  32) Next Descriptor Address */
+} dmac_descriptor_registers_t
+#ifdef __GNUC__
+  __attribute__ ((aligned (8)))
+#endif
+;
+
+/* DMAC register API structure */
+typedef struct
+{  /* Direct Memory Access Controller */
+  __IO  uint16_t                       DMAC_CTRL;          /* Offset: 0x00 (R/W  16) Control */
+  __IO  uint16_t                       DMAC_CRCCTRL;       /* Offset: 0x02 (R/W  16) CRC Control */
+  __IO  uint32_t                       DMAC_CRCDATAIN;     /* Offset: 0x04 (R/W  32) CRC Data Input */
+  __IO  uint32_t                       DMAC_CRCCHKSUM;     /* Offset: 0x08 (R/W  32) CRC Checksum */
+  __IO  uint8_t                        DMAC_CRCSTATUS;     /* Offset: 0x0C (R/W  8) CRC Status */
+  __IO  uint8_t                        DMAC_DBGCTRL;       /* Offset: 0x0D (R/W  8) Debug Control */
+  __IO  uint8_t                        DMAC_QOSCTRL;       /* Offset: 0x0E (R/W  8) QOS Control */
+  __I   uint8_t                        Reserved1[0x01];
+  __IO  uint32_t                       DMAC_SWTRIGCTRL;    /* Offset: 0x10 (R/W  32) Software Trigger Control */
+  __IO  uint32_t                       DMAC_PRICTRL0;      /* Offset: 0x14 (R/W  32) Priority Control 0 */
+  __I   uint8_t                        Reserved2[0x08];
+  __IO  uint16_t                       DMAC_INTPEND;       /* Offset: 0x20 (R/W  16) Interrupt Pending */
+  __I   uint8_t                        Reserved3[0x02];
+  __I   uint32_t                       DMAC_INTSTATUS;     /* Offset: 0x24 (R/   32) Interrupt Status */
+  __I   uint32_t                       DMAC_BUSYCH;        /* Offset: 0x28 (R/   32) Busy Channels */
+  __I   uint32_t                       DMAC_PENDCH;        /* Offset: 0x2C (R/   32) Pending Channels */
+  __I   uint32_t                       DMAC_ACTIVE;        /* Offset: 0x30 (R/   32) Active Channel and Levels */
+  __IO  uint32_t                       DMAC_BASEADDR;      /* Offset: 0x34 (R/W  32) Descriptor Memory Section Base Address */
+  __IO  uint32_t                       DMAC_WRBADDR;       /* Offset: 0x38 (R/W  32) Write-Back Memory Section Base Address */
+  __I   uint8_t                        Reserved4[0x03];
+  __IO  uint8_t                        DMAC_CHID;          /* Offset: 0x3F (R/W  8) Channel ID */
+  __IO  uint8_t                        DMAC_CHCTRLA;       /* Offset: 0x40 (R/W  8) Channel Control A */
+  __I   uint8_t                        Reserved5[0x03];
+  __IO  uint32_t                       DMAC_CHCTRLB;       /* Offset: 0x44 (R/W  32) Channel Control B */
+  __I   uint8_t                        Reserved6[0x04];
+  __IO  uint8_t                        DMAC_CHINTENCLR;    /* Offset: 0x4C (R/W  8) Channel Interrupt Enable Clear */
+  __IO  uint8_t                        DMAC_CHINTENSET;    /* Offset: 0x4D (R/W  8) Channel Interrupt Enable Set */
+  __IO  uint8_t                        DMAC_CHINTFLAG;     /* Offset: 0x4E (R/W  8) Channel Interrupt Flag Status and Clear */
+  __I   uint8_t                        DMAC_CHSTATUS;      /* Offset: 0x4F (R/   8) Channel Status */
+} dmac_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* DMAC_DESCRIPTOR memory section attribute */
+#define SECTION_DMAC_DESCRIPTOR
+
+#endif /* _PIC32CMGC00_DMAC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/dsu.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/dsu.h
new file mode 100644
index 00000000..1c857ead
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/dsu.h
@@ -0,0 +1,685 @@
+/*
+ * Component description for DSU
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_DSU_COMPONENT_H_
+#define _PIC32CMGC00_DSU_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR DSU                       */
+/* ************************************************************************** */
+
+/* -------- DSU_CTRLA : (DSU Offset: 0x00) (R/W 32) Control A REGISTER -------- */
+#define DSU_CTRLA_RESETVALUE                  _UINT32_(0x00)                                       /*  (DSU_CTRLA) Control A REGISTER  Reset Value */
+
+#define DSU_CTRLA_PRIV_Pos                    _UINT32_(2)                                          /* (DSU_CTRLA) Privileged Access Only for APB Interface Position */
+#define DSU_CTRLA_PRIV_Msk                    (_UINT32_(0x1) << DSU_CTRLA_PRIV_Pos)                /* (DSU_CTRLA) Privileged Access Only for APB Interface Mask */
+#define DSU_CTRLA_PRIV(value)                 (DSU_CTRLA_PRIV_Msk & (_UINT32_(value) << DSU_CTRLA_PRIV_Pos)) /* Assignment of value for PRIV in the DSU_CTRLA register */
+#define   DSU_CTRLA_PRIV_0_Val                _UINT32_(0x0)                                        /* (DSU_CTRLA) Internal Address Space registers accessible in privileged and unprivileged modes. Test functions generate unprivileged requests.  */
+#define   DSU_CTRLA_PRIV_1_Val                _UINT32_(0x1)                                        /* (DSU_CTRLA) Internal Address Space registers only accessible in privileged mode. Test functions generate privileged requests.  */
+#define DSU_CTRLA_PRIV_0                      (DSU_CTRLA_PRIV_0_Val << DSU_CTRLA_PRIV_Pos)         /* (DSU_CTRLA) Internal Address Space registers accessible in privileged and unprivileged modes. Test functions generate unprivileged requests. Position */
+#define DSU_CTRLA_PRIV_1                      (DSU_CTRLA_PRIV_1_Val << DSU_CTRLA_PRIV_Pos)         /* (DSU_CTRLA) Internal Address Space registers only accessible in privileged mode. Test functions generate privileged requests. Position */
+#define DSU_CTRLA_Msk                         _UINT32_(0x00000004)                                 /* (DSU_CTRLA) Register Mask  */
+
+
+/* -------- DSU_CTRLB : (DSU Offset: 0x04) (R/W 32) Control B REGISTER -------- */
+#define DSU_CTRLB_RESETVALUE                  _UINT32_(0x00)                                       /*  (DSU_CTRLB) Control B REGISTER  Reset Value */
+
+#define DSU_CTRLB_DCCDMALVL0_Pos              _UINT32_(0)                                          /* (DSU_CTRLB) DMA Trigger n Level Position */
+#define DSU_CTRLB_DCCDMALVL0_Msk              (_UINT32_(0x1) << DSU_CTRLB_DCCDMALVL0_Pos)          /* (DSU_CTRLB) DMA Trigger n Level Mask */
+#define DSU_CTRLB_DCCDMALVL0(value)           (DSU_CTRLB_DCCDMALVL0_Msk & (_UINT32_(value) << DSU_CTRLB_DCCDMALVL0_Pos)) /* Assignment of value for DCCDMALVL0 in the DSU_CTRLB register */
+#define   DSU_CTRLB_DCCDMALVL0_EMPTY_Val      _UINT32_(0x0)                                        /* (DSU_CTRLB) Trigger n rises when DCCn is read and falls when it is written  */
+#define   DSU_CTRLB_DCCDMALVL0_FULL_Val       _UINT32_(0x1)                                        /* (DSU_CTRLB) Trigger n rises when DCCn is written and falls when it is read  */
+#define DSU_CTRLB_DCCDMALVL0_EMPTY            (DSU_CTRLB_DCCDMALVL0_EMPTY_Val << DSU_CTRLB_DCCDMALVL0_Pos) /* (DSU_CTRLB) Trigger n rises when DCCn is read and falls when it is written Position */
+#define DSU_CTRLB_DCCDMALVL0_FULL             (DSU_CTRLB_DCCDMALVL0_FULL_Val << DSU_CTRLB_DCCDMALVL0_Pos) /* (DSU_CTRLB) Trigger n rises when DCCn is written and falls when it is read Position */
+#define DSU_CTRLB_DCCDMALVL1_Pos              _UINT32_(1)                                          /* (DSU_CTRLB) DMA Trigger n Level Position */
+#define DSU_CTRLB_DCCDMALVL1_Msk              (_UINT32_(0x1) << DSU_CTRLB_DCCDMALVL1_Pos)          /* (DSU_CTRLB) DMA Trigger n Level Mask */
+#define DSU_CTRLB_DCCDMALVL1(value)           (DSU_CTRLB_DCCDMALVL1_Msk & (_UINT32_(value) << DSU_CTRLB_DCCDMALVL1_Pos)) /* Assignment of value for DCCDMALVL1 in the DSU_CTRLB register */
+#define   DSU_CTRLB_DCCDMALVL1_EMPTY_Val      _UINT32_(0x0)                                        /* (DSU_CTRLB) Trigger n rises when DCCn is read and falls when it is written  */
+#define   DSU_CTRLB_DCCDMALVL1_FULL_Val       _UINT32_(0x1)                                        /* (DSU_CTRLB) Trigger n rises when DCCn is written and falls when it is read  */
+#define DSU_CTRLB_DCCDMALVL1_EMPTY            (DSU_CTRLB_DCCDMALVL1_EMPTY_Val << DSU_CTRLB_DCCDMALVL1_Pos) /* (DSU_CTRLB) Trigger n rises when DCCn is read and falls when it is written Position */
+#define DSU_CTRLB_DCCDMALVL1_FULL             (DSU_CTRLB_DCCDMALVL1_FULL_Val << DSU_CTRLB_DCCDMALVL1_Pos) /* (DSU_CTRLB) Trigger n rises when DCCn is written and falls when it is read Position */
+#define DSU_CTRLB_MISC_Pos                    _UINT32_(8)                                          /* (DSU_CTRLB) Device Specific Configuration Register Position */
+#define DSU_CTRLB_MISC_Msk                    (_UINT32_(0xFFFFFF) << DSU_CTRLB_MISC_Pos)           /* (DSU_CTRLB) Device Specific Configuration Register Mask */
+#define DSU_CTRLB_MISC(value)                 (DSU_CTRLB_MISC_Msk & (_UINT32_(value) << DSU_CTRLB_MISC_Pos)) /* Assignment of value for MISC in the DSU_CTRLB register */
+#define DSU_CTRLB_Msk                         _UINT32_(0xFFFFFF03)                                 /* (DSU_CTRLB) Register Mask  */
+
+#define DSU_CTRLB_DCCDMALVL_Pos               _UINT32_(0)                                          /* (DSU_CTRLB Position) DMA Trigger n Level */
+#define DSU_CTRLB_DCCDMALVL_Msk               (_UINT32_(0x3) << DSU_CTRLB_DCCDMALVL_Pos)           /* (DSU_CTRLB Mask) DCCDMALVL */
+#define DSU_CTRLB_DCCDMALVL(value)            (DSU_CTRLB_DCCDMALVL_Msk & (_UINT32_(value) << DSU_CTRLB_DCCDMALVL_Pos)) 
+
+/* -------- DSU_CTRLC : (DSU Offset: 0x100) (R/W 32) Control C REGISTER -------- */
+#define DSU_CTRLC_RESETVALUE                  _UINT32_(0x00)                                       /*  (DSU_CTRLC) Control C REGISTER  Reset Value */
+
+#define DSU_CTRLC_DBGRW0_Pos                  _UINT32_(0)                                          /* (DSU_CTRLC) CPUn Debug R/W Position */
+#define DSU_CTRLC_DBGRW0_Msk                  (_UINT32_(0x1) << DSU_CTRLC_DBGRW0_Pos)              /* (DSU_CTRLC) CPUn Debug R/W Mask */
+#define DSU_CTRLC_DBGRW0(value)               (DSU_CTRLC_DBGRW0_Msk & (_UINT32_(value) << DSU_CTRLC_DBGRW0_Pos)) /* Assignment of value for DBGRW0 in the DSU_CTRLC register */
+#define   DSU_CTRLC_DBGRW0_0_Val              _UINT32_(0x0)                                        /* (DSU_CTRLC) Allow debugger accesses through CPUn to carry the debug attribute (i.e debugger reads are non-destructive).  */
+#define   DSU_CTRLC_DBGRW0_1_Val              _UINT32_(0x1)                                        /* (DSU_CTRLC) Debugger accesses through CPUn do not carry the debug attribute (i.e debugger reads are destructive).  */
+#define DSU_CTRLC_DBGRW0_0                    (DSU_CTRLC_DBGRW0_0_Val << DSU_CTRLC_DBGRW0_Pos)     /* (DSU_CTRLC) Allow debugger accesses through CPUn to carry the debug attribute (i.e debugger reads are non-destructive). Position */
+#define DSU_CTRLC_DBGRW0_1                    (DSU_CTRLC_DBGRW0_1_Val << DSU_CTRLC_DBGRW0_Pos)     /* (DSU_CTRLC) Debugger accesses through CPUn do not carry the debug attribute (i.e debugger reads are destructive). Position */
+#define DSU_CTRLC_Msk                         _UINT32_(0x00000001)                                 /* (DSU_CTRLC) Register Mask  */
+
+#define DSU_CTRLC_DBGRW_Pos                   _UINT32_(0)                                          /* (DSU_CTRLC Position) CPUn Debug R/W */
+#define DSU_CTRLC_DBGRW_Msk                   (_UINT32_(0x1) << DSU_CTRLC_DBGRW_Pos)               /* (DSU_CTRLC Mask) DBGRW */
+#define DSU_CTRLC_DBGRW(value)                (DSU_CTRLC_DBGRW_Msk & (_UINT32_(value) << DSU_CTRLC_DBGRW_Pos)) 
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x104) (R/W 32) Status A REGISTER -------- */
+#define DSU_STATUSA_RESETVALUE                _UINT32_(0x00)                                       /*  (DSU_STATUSA) Status A REGISTER  Reset Value */
+
+#define DSU_STATUSA_DONE_Pos                  _UINT32_(0)                                          /* (DSU_STATUSA) Done Status Position */
+#define DSU_STATUSA_DONE_Msk                  (_UINT32_(0x1) << DSU_STATUSA_DONE_Pos)              /* (DSU_STATUSA) Done Status Mask */
+#define DSU_STATUSA_DONE(value)               (DSU_STATUSA_DONE_Msk & (_UINT32_(value) << DSU_STATUSA_DONE_Pos)) /* Assignment of value for DONE in the DSU_STATUSA register */
+#define   DSU_STATUSA_DONE_0_Val              _UINT32_(0x0)                                        /* (DSU_STATUSA) DSU is executing a command or idle.  */
+#define   DSU_STATUSA_DONE_1_Val              _UINT32_(0x1)                                        /* (DSU_STATUSA) TCTRL.CMD command completed  */
+#define DSU_STATUSA_DONE_0                    (DSU_STATUSA_DONE_0_Val << DSU_STATUSA_DONE_Pos)     /* (DSU_STATUSA) DSU is executing a command or idle. Position */
+#define DSU_STATUSA_DONE_1                    (DSU_STATUSA_DONE_1_Val << DSU_STATUSA_DONE_Pos)     /* (DSU_STATUSA) TCTRL.CMD command completed Position */
+#define DSU_STATUSA_BERR_Pos                  _UINT32_(2)                                          /* (DSU_STATUSA) Bus Error Status Position */
+#define DSU_STATUSA_BERR_Msk                  (_UINT32_(0x1) << DSU_STATUSA_BERR_Pos)              /* (DSU_STATUSA) Bus Error Status Mask */
+#define DSU_STATUSA_BERR(value)               (DSU_STATUSA_BERR_Msk & (_UINT32_(value) << DSU_STATUSA_BERR_Pos)) /* Assignment of value for BERR in the DSU_STATUSA register */
+#define   DSU_STATUSA_BERR_0_Val              _UINT32_(0x0)                                        /* (DSU_STATUSA) No bus error detected  */
+#define   DSU_STATUSA_BERR_1_Val              _UINT32_(0x1)                                        /* (DSU_STATUSA) Bus error incurred while performing the DSU command.  */
+#define DSU_STATUSA_BERR_0                    (DSU_STATUSA_BERR_0_Val << DSU_STATUSA_BERR_Pos)     /* (DSU_STATUSA) No bus error detected Position */
+#define DSU_STATUSA_BERR_1                    (DSU_STATUSA_BERR_1_Val << DSU_STATUSA_BERR_Pos)     /* (DSU_STATUSA) Bus error incurred while performing the DSU command. Position */
+#define DSU_STATUSA_PERR_Pos                  _UINT32_(3)                                          /* (DSU_STATUSA) Protection Error Status Position */
+#define DSU_STATUSA_PERR_Msk                  (_UINT32_(0x1) << DSU_STATUSA_PERR_Pos)              /* (DSU_STATUSA) Protection Error Status Mask */
+#define DSU_STATUSA_PERR(value)               (DSU_STATUSA_PERR_Msk & (_UINT32_(value) << DSU_STATUSA_PERR_Pos)) /* Assignment of value for PERR in the DSU_STATUSA register */
+#define   DSU_STATUSA_PERR_0_Val              _UINT32_(0x0)                                        /* (DSU_STATUSA) No protection error detected  */
+#define   DSU_STATUSA_PERR_1_Val              _UINT32_(0x1)                                        /* (DSU_STATUSA) Invalid command written to TCTRL.CMD, partial write to the upper or lower bytes of TCTRL.CMD, or invalid key written to SAFEDOOR.  */
+#define DSU_STATUSA_PERR_0                    (DSU_STATUSA_PERR_0_Val << DSU_STATUSA_PERR_Pos)     /* (DSU_STATUSA) No protection error detected Position */
+#define DSU_STATUSA_PERR_1                    (DSU_STATUSA_PERR_1_Val << DSU_STATUSA_PERR_Pos)     /* (DSU_STATUSA) Invalid command written to TCTRL.CMD, partial write to the upper or lower bytes of TCTRL.CMD, or invalid key written to SAFEDOOR. Position */
+#define DSU_STATUSA_ROMCRC_Pos                _UINT32_(6)                                          /* (DSU_STATUSA) Boot ROM CRC Self-Check Status Position */
+#define DSU_STATUSA_ROMCRC_Msk                (_UINT32_(0x3) << DSU_STATUSA_ROMCRC_Pos)            /* (DSU_STATUSA) Boot ROM CRC Self-Check Status Mask */
+#define DSU_STATUSA_ROMCRC(value)             (DSU_STATUSA_ROMCRC_Msk & (_UINT32_(value) << DSU_STATUSA_ROMCRC_Pos)) /* Assignment of value for ROMCRC in the DSU_STATUSA register */
+#define   DSU_STATUSA_ROMCRC_0_Val            _UINT32_(0x0)                                        /* (DSU_STATUSA) CRC is in progress  */
+#define   DSU_STATUSA_ROMCRC_1_Val            _UINT32_(0x1)                                        /* (DSU_STATUSA) CRC completed but failed indicating possible issue with the ROM content. System held in lockup state.  */
+#define   DSU_STATUSA_ROMCRC_2_Val            _UINT32_(0x2)                                        /* (DSU_STATUSA) CRC completed and passed  */
+#define   DSU_STATUSA_ROMCRC_3_Val            _UINT32_(0x3)                                        /* (DSU_STATUSA) CRC never executed because user disabled CRC check through fuse settings.  */
+#define DSU_STATUSA_ROMCRC_0                  (DSU_STATUSA_ROMCRC_0_Val << DSU_STATUSA_ROMCRC_Pos) /* (DSU_STATUSA) CRC is in progress Position */
+#define DSU_STATUSA_ROMCRC_1                  (DSU_STATUSA_ROMCRC_1_Val << DSU_STATUSA_ROMCRC_Pos) /* (DSU_STATUSA) CRC completed but failed indicating possible issue with the ROM content. System held in lockup state. Position */
+#define DSU_STATUSA_ROMCRC_2                  (DSU_STATUSA_ROMCRC_2_Val << DSU_STATUSA_ROMCRC_Pos) /* (DSU_STATUSA) CRC completed and passed Position */
+#define DSU_STATUSA_ROMCRC_3                  (DSU_STATUSA_ROMCRC_3_Val << DSU_STATUSA_ROMCRC_Pos) /* (DSU_STATUSA) CRC never executed because user disabled CRC check through fuse settings. Position */
+#define DSU_STATUSA_CRSTEXT0_Pos              _UINT32_(8)                                          /* (DSU_STATUSA) CPUx Reset Extension Status Position */
+#define DSU_STATUSA_CRSTEXT0_Msk              (_UINT32_(0x1) << DSU_STATUSA_CRSTEXT0_Pos)          /* (DSU_STATUSA) CPUx Reset Extension Status Mask */
+#define DSU_STATUSA_CRSTEXT0(value)           (DSU_STATUSA_CRSTEXT0_Msk & (_UINT32_(value) << DSU_STATUSA_CRSTEXT0_Pos)) /* Assignment of value for CRSTEXT0 in the DSU_STATUSA register */
+#define   DSU_STATUSA_CRSTEXT0_0_Val          _UINT32_(0x0)                                        /* (DSU_STATUSA) CPUx released from reset extension.  */
+#define   DSU_STATUSA_CRSTEXT0_1_Val          _UINT32_(0x1)                                        /* (DSU_STATUSA) CPUx held in reset extension. Set on Cold-Plugging detection.  */
+#define DSU_STATUSA_CRSTEXT0_0                (DSU_STATUSA_CRSTEXT0_0_Val << DSU_STATUSA_CRSTEXT0_Pos) /* (DSU_STATUSA) CPUx released from reset extension. Position */
+#define DSU_STATUSA_CRSTEXT0_1                (DSU_STATUSA_CRSTEXT0_1_Val << DSU_STATUSA_CRSTEXT0_Pos) /* (DSU_STATUSA) CPUx held in reset extension. Set on Cold-Plugging detection. Position */
+#define DSU_STATUSA_BREXT0_Pos                _UINT32_(16)                                         /* (DSU_STATUSA) BootRom 0 Phase Extension Status Position */
+#define DSU_STATUSA_BREXT0_Msk                (_UINT32_(0x1) << DSU_STATUSA_BREXT0_Pos)            /* (DSU_STATUSA) BootRom 0 Phase Extension Status Mask */
+#define DSU_STATUSA_BREXT0(value)             (DSU_STATUSA_BREXT0_Msk & (_UINT32_(value) << DSU_STATUSA_BREXT0_Pos)) /* Assignment of value for BREXT0 in the DSU_STATUSA register */
+#define   DSU_STATUSA_BREXT0_0_Val            _UINT32_(0x0)                                        /* (DSU_STATUSA) Boot ROM Phase Extension released for CPUx.  */
+#define   DSU_STATUSA_BREXT0_1_Val            _UINT32_(0x1)                                        /* (DSU_STATUSA) Boot ROM Phase Extension for CPUx. Set on Cold-Plugging detection.  */
+#define DSU_STATUSA_BREXT0_0                  (DSU_STATUSA_BREXT0_0_Val << DSU_STATUSA_BREXT0_Pos) /* (DSU_STATUSA) Boot ROM Phase Extension released for CPUx. Position */
+#define DSU_STATUSA_BREXT0_1                  (DSU_STATUSA_BREXT0_1_Val << DSU_STATUSA_BREXT0_Pos) /* (DSU_STATUSA) Boot ROM Phase Extension for CPUx. Set on Cold-Plugging detection. Position */
+#define DSU_STATUSA_Msk                       _UINT32_(0x000101CD)                                 /* (DSU_STATUSA) Register Mask  */
+
+#define DSU_STATUSA_CRSTEXT_Pos               _UINT32_(8)                                          /* (DSU_STATUSA Position) CPUx Reset Extension Status */
+#define DSU_STATUSA_CRSTEXT_Msk               (_UINT32_(0x1) << DSU_STATUSA_CRSTEXT_Pos)           /* (DSU_STATUSA Mask) CRSTEXT */
+#define DSU_STATUSA_CRSTEXT(value)            (DSU_STATUSA_CRSTEXT_Msk & (_UINT32_(value) << DSU_STATUSA_CRSTEXT_Pos)) 
+#define DSU_STATUSA_BREXT_Pos                 _UINT32_(16)                                         /* (DSU_STATUSA Position) BootRom x Phase Extension Status */
+#define DSU_STATUSA_BREXT_Msk                 (_UINT32_(0x1) << DSU_STATUSA_BREXT_Pos)             /* (DSU_STATUSA Mask) BREXT */
+#define DSU_STATUSA_BREXT(value)              (DSU_STATUSA_BREXT_Msk & (_UINT32_(value) << DSU_STATUSA_BREXT_Pos)) 
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x108) ( R/ 32) Status B REGISTER -------- */
+#define DSU_STATUSB_RESETVALUE                _UINT32_(0x00)                                       /*  (DSU_STATUSB) Status B REGISTER  Reset Value */
+
+#define DSU_STATUSB_BCCD0_Pos                 _UINT32_(0)                                          /* (DSU_STATUSB) Boot ROM Communication Channel 0 Dirty Position */
+#define DSU_STATUSB_BCCD0_Msk                 (_UINT32_(0x1) << DSU_STATUSB_BCCD0_Pos)             /* (DSU_STATUSB) Boot ROM Communication Channel 0 Dirty Mask */
+#define DSU_STATUSB_BCCD0(value)              (DSU_STATUSB_BCCD0_Msk & (_UINT32_(value) << DSU_STATUSB_BCCD0_Pos)) /* Assignment of value for BCCD0 in the DSU_STATUSB register */
+#define   DSU_STATUSB_BCCD0_0_Val             _UINT32_(0x0)                                        /* (DSU_STATUSB) BCCDx.DATA register was read from.  */
+#define   DSU_STATUSB_BCCD0_1_Val             _UINT32_(0x1)                                        /* (DSU_STATUSB) BCCDx.DATA register was written to.  */
+#define DSU_STATUSB_BCCD0_0                   (DSU_STATUSB_BCCD0_0_Val << DSU_STATUSB_BCCD0_Pos)   /* (DSU_STATUSB) BCCDx.DATA register was read from. Position */
+#define DSU_STATUSB_BCCD0_1                   (DSU_STATUSB_BCCD0_1_Val << DSU_STATUSB_BCCD0_Pos)   /* (DSU_STATUSB) BCCDx.DATA register was written to. Position */
+#define DSU_STATUSB_BCCD1_Pos                 _UINT32_(1)                                          /* (DSU_STATUSB) Boot ROM Communication Channel 1 Dirty Position */
+#define DSU_STATUSB_BCCD1_Msk                 (_UINT32_(0x1) << DSU_STATUSB_BCCD1_Pos)             /* (DSU_STATUSB) Boot ROM Communication Channel 1 Dirty Mask */
+#define DSU_STATUSB_BCCD1(value)              (DSU_STATUSB_BCCD1_Msk & (_UINT32_(value) << DSU_STATUSB_BCCD1_Pos)) /* Assignment of value for BCCD1 in the DSU_STATUSB register */
+#define   DSU_STATUSB_BCCD1_0_Val             _UINT32_(0x0)                                        /* (DSU_STATUSB) BCCDx.DATA register was read from.  */
+#define   DSU_STATUSB_BCCD1_1_Val             _UINT32_(0x1)                                        /* (DSU_STATUSB) BCCDx.DATA register was written to.  */
+#define DSU_STATUSB_BCCD1_0                   (DSU_STATUSB_BCCD1_0_Val << DSU_STATUSB_BCCD1_Pos)   /* (DSU_STATUSB) BCCDx.DATA register was read from. Position */
+#define DSU_STATUSB_BCCD1_1                   (DSU_STATUSB_BCCD1_1_Val << DSU_STATUSB_BCCD1_Pos)   /* (DSU_STATUSB) BCCDx.DATA register was written to. Position */
+#define DSU_STATUSB_DCCD0_Pos                 _UINT32_(2)                                          /* (DSU_STATUSB) Debug Communication Channel 0 Dirty Position */
+#define DSU_STATUSB_DCCD0_Msk                 (_UINT32_(0x1) << DSU_STATUSB_DCCD0_Pos)             /* (DSU_STATUSB) Debug Communication Channel 0 Dirty Mask */
+#define DSU_STATUSB_DCCD0(value)              (DSU_STATUSB_DCCD0_Msk & (_UINT32_(value) << DSU_STATUSB_DCCD0_Pos)) /* Assignment of value for DCCD0 in the DSU_STATUSB register */
+#define   DSU_STATUSB_DCCD0_0_Val             _UINT32_(0x0)                                        /* (DSU_STATUSB) DCCDx.DATA register was read from.  */
+#define   DSU_STATUSB_DCCD0_1_Val             _UINT32_(0x1)                                        /* (DSU_STATUSB) DCCDx.DATA register was written to.  */
+#define DSU_STATUSB_DCCD0_0                   (DSU_STATUSB_DCCD0_0_Val << DSU_STATUSB_DCCD0_Pos)   /* (DSU_STATUSB) DCCDx.DATA register was read from. Position */
+#define DSU_STATUSB_DCCD0_1                   (DSU_STATUSB_DCCD0_1_Val << DSU_STATUSB_DCCD0_Pos)   /* (DSU_STATUSB) DCCDx.DATA register was written to. Position */
+#define DSU_STATUSB_DCCD1_Pos                 _UINT32_(3)                                          /* (DSU_STATUSB) Debug Communication Channel 1 Dirty Position */
+#define DSU_STATUSB_DCCD1_Msk                 (_UINT32_(0x1) << DSU_STATUSB_DCCD1_Pos)             /* (DSU_STATUSB) Debug Communication Channel 1 Dirty Mask */
+#define DSU_STATUSB_DCCD1(value)              (DSU_STATUSB_DCCD1_Msk & (_UINT32_(value) << DSU_STATUSB_DCCD1_Pos)) /* Assignment of value for DCCD1 in the DSU_STATUSB register */
+#define   DSU_STATUSB_DCCD1_0_Val             _UINT32_(0x0)                                        /* (DSU_STATUSB) DCCDx.DATA register was read from.  */
+#define   DSU_STATUSB_DCCD1_1_Val             _UINT32_(0x1)                                        /* (DSU_STATUSB) DCCDx.DATA register was written to.  */
+#define DSU_STATUSB_DCCD1_0                   (DSU_STATUSB_DCCD1_0_Val << DSU_STATUSB_DCCD1_Pos)   /* (DSU_STATUSB) DCCDx.DATA register was read from. Position */
+#define DSU_STATUSB_DCCD1_1                   (DSU_STATUSB_DCCD1_1_Val << DSU_STATUSB_DCCD1_Pos)   /* (DSU_STATUSB) DCCDx.DATA register was written to. Position */
+#define DSU_STATUSB_DBGPRES_Pos               _UINT32_(8)                                          /* (DSU_STATUSB) Debugger Present Status Position */
+#define DSU_STATUSB_DBGPRES_Msk               (_UINT32_(0x1) << DSU_STATUSB_DBGPRES_Pos)           /* (DSU_STATUSB) Debugger Present Status Mask */
+#define DSU_STATUSB_DBGPRES(value)            (DSU_STATUSB_DBGPRES_Msk & (_UINT32_(value) << DSU_STATUSB_DBGPRES_Pos)) /* Assignment of value for DBGPRES in the DSU_STATUSB register */
+#define   DSU_STATUSB_DBGPRES_0_Val           _UINT32_(0x0)                                        /* (DSU_STATUSB) No debugger detected  */
+#define   DSU_STATUSB_DBGPRES_1_Val           _UINT32_(0x1)                                        /* (DSU_STATUSB) Debugger probe detected  */
+#define DSU_STATUSB_DBGPRES_0                 (DSU_STATUSB_DBGPRES_0_Val << DSU_STATUSB_DBGPRES_Pos) /* (DSU_STATUSB) No debugger detected Position */
+#define DSU_STATUSB_DBGPRES_1                 (DSU_STATUSB_DBGPRES_1_Val << DSU_STATUSB_DBGPRES_Pos) /* (DSU_STATUSB) Debugger probe detected Position */
+#define DSU_STATUSB_HPS_Pos                   _UINT32_(10)                                         /* (DSU_STATUSB) Hot-Plugging Status Position */
+#define DSU_STATUSB_HPS_Msk                   (_UINT32_(0x1) << DSU_STATUSB_HPS_Pos)               /* (DSU_STATUSB) Hot-Plugging Status Mask */
+#define DSU_STATUSB_HPS(value)                (DSU_STATUSB_HPS_Msk & (_UINT32_(value) << DSU_STATUSB_HPS_Pos)) /* Assignment of value for HPS in the DSU_STATUSB register */
+#define   DSU_STATUSB_HPS_0_Val               _UINT32_(0x0)                                        /* (DSU_STATUSB) Hot-Plugging inactive  */
+#define   DSU_STATUSB_HPS_1_Val               _UINT32_(0x1)                                        /* (DSU_STATUSB) Hot-Plugging active  */
+#define DSU_STATUSB_HPS_0                     (DSU_STATUSB_HPS_0_Val << DSU_STATUSB_HPS_Pos)       /* (DSU_STATUSB) Hot-Plugging inactive Position */
+#define DSU_STATUSB_HPS_1                     (DSU_STATUSB_HPS_1_Val << DSU_STATUSB_HPS_Pos)       /* (DSU_STATUSB) Hot-Plugging active Position */
+#define DSU_STATUSB_Msk                       _UINT32_(0x0000050F)                                 /* (DSU_STATUSB) Register Mask  */
+
+#define DSU_STATUSB_BCCD_Pos                  _UINT32_(0)                                          /* (DSU_STATUSB Position) Boot ROM Communication Channel x Dirty */
+#define DSU_STATUSB_BCCD_Msk                  (_UINT32_(0x3) << DSU_STATUSB_BCCD_Pos)              /* (DSU_STATUSB Mask) BCCD */
+#define DSU_STATUSB_BCCD(value)               (DSU_STATUSB_BCCD_Msk & (_UINT32_(value) << DSU_STATUSB_BCCD_Pos)) 
+#define DSU_STATUSB_DCCD_Pos                  _UINT32_(2)                                          /* (DSU_STATUSB Position) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk                  (_UINT32_(0x3) << DSU_STATUSB_DCCD_Pos)              /* (DSU_STATUSB Mask) DCCD */
+#define DSU_STATUSB_DCCD(value)               (DSU_STATUSB_DCCD_Msk & (_UINT32_(value) << DSU_STATUSB_DCCD_Pos)) 
+
+/* -------- DSU_BCC : (DSU Offset: 0x110) (R/W 32) Boot ROM Channel n REGISTER -------- */
+#define DSU_BCC_RESETVALUE                    _UINT32_(0x00)                                       /*  (DSU_BCC) Boot ROM Channel n REGISTER  Reset Value */
+
+#define DSU_BCC_DATA_Pos                      _UINT32_(0)                                          /* (DSU_BCC) Data Position */
+#define DSU_BCC_DATA_Msk                      (_UINT32_(0xFFFFFFFF) << DSU_BCC_DATA_Pos)           /* (DSU_BCC) Data Mask */
+#define DSU_BCC_DATA(value)                   (DSU_BCC_DATA_Msk & (_UINT32_(value) << DSU_BCC_DATA_Pos)) /* Assignment of value for DATA in the DSU_BCC register */
+#define DSU_BCC_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (DSU_BCC) Register Mask  */
+
+
+/* -------- DSU_DCC : (DSU Offset: 0x118) (R/W 32) Debug Communication Channel n REGISTER -------- */
+#define DSU_DCC_RESETVALUE                    _UINT32_(0x00)                                       /*  (DSU_DCC) Debug Communication Channel n REGISTER  Reset Value */
+
+#define DSU_DCC_DATA_Pos                      _UINT32_(0)                                          /* (DSU_DCC) Data Position */
+#define DSU_DCC_DATA_Msk                      (_UINT32_(0xFFFFFFFF) << DSU_DCC_DATA_Pos)           /* (DSU_DCC) Data Mask */
+#define DSU_DCC_DATA(value)                   (DSU_DCC_DATA_Msk & (_UINT32_(value) << DSU_DCC_DATA_Pos)) /* Assignment of value for DATA in the DSU_DCC register */
+#define DSU_DCC_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (DSU_DCC) Register Mask  */
+
+
+/* -------- DSU_DID : (DSU Offset: 0x120) (R/W 32) Device Identification Register -------- */
+#define DSU_DID_RESETVALUE                    _UINT32_(0x53)                                       /*  (DSU_DID) Device Identification Register  Reset Value */
+
+#define DSU_DID_FV_Pos                        _UINT32_(0)                                          /* (DSU_DID) Fixed Value of 1 Position */
+#define DSU_DID_FV_Msk                        (_UINT32_(0x1) << DSU_DID_FV_Pos)                    /* (DSU_DID) Fixed Value of 1 Mask */
+#define DSU_DID_FV(value)                     (DSU_DID_FV_Msk & (_UINT32_(value) << DSU_DID_FV_Pos)) /* Assignment of value for FV in the DSU_DID register */
+#define DSU_DID_MANID_Pos                     _UINT32_(1)                                          /* (DSU_DID) JEDEC Manufacture ID Position */
+#define DSU_DID_MANID_Msk                     (_UINT32_(0x7FF) << DSU_DID_MANID_Pos)               /* (DSU_DID) JEDEC Manufacture ID Mask */
+#define DSU_DID_MANID(value)                  (DSU_DID_MANID_Msk & (_UINT32_(value) << DSU_DID_MANID_Pos)) /* Assignment of value for MANID in the DSU_DID register */
+#define DSU_DID_PNDID_Pos                     _UINT32_(12)                                         /* (DSU_DID) Part Number Device ID Position */
+#define DSU_DID_PNDID_Msk                     (_UINT32_(0xFF) << DSU_DID_PNDID_Pos)                /* (DSU_DID) Part Number Device ID Mask */
+#define DSU_DID_PNDID(value)                  (DSU_DID_PNDID_Msk & (_UINT32_(value) << DSU_DID_PNDID_Pos)) /* Assignment of value for PNDID in the DSU_DID register */
+#define DSU_DID_PNMID_Pos                     _UINT32_(20)                                         /* (DSU_DID) Part Number Mask ID Position */
+#define DSU_DID_PNMID_Msk                     (_UINT32_(0xFF) << DSU_DID_PNMID_Pos)                /* (DSU_DID) Part Number Mask ID Mask */
+#define DSU_DID_PNMID(value)                  (DSU_DID_PNMID_Msk & (_UINT32_(value) << DSU_DID_PNMID_Pos)) /* Assignment of value for PNMID in the DSU_DID register */
+#define DSU_DID_VER_Pos                       _UINT32_(28)                                         /* (DSU_DID) Version Code Position */
+#define DSU_DID_VER_Msk                       (_UINT32_(0xF) << DSU_DID_VER_Pos)                   /* (DSU_DID) Version Code Mask */
+#define DSU_DID_VER(value)                    (DSU_DID_VER_Msk & (_UINT32_(value) << DSU_DID_VER_Pos)) /* Assignment of value for VER in the DSU_DID register */
+#define DSU_DID_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (DSU_DID) Register Mask  */
+
+
+/* -------- DSU_DAL : (DSU Offset: 0x124) ( R/ 32) Debugger Access Level REGISTER -------- */
+#define DSU_DAL_RESETVALUE                    _UINT32_(0x00)                                       /*  (DSU_DAL) Debugger Access Level REGISTER  Reset Value */
+
+#define DSU_DAL_CPU0_Pos                      _UINT32_(0)                                          /* (DSU_DAL) CPU 0 Debugger Access Level Position */
+#define DSU_DAL_CPU0_Msk                      (_UINT32_(0x3) << DSU_DAL_CPU0_Pos)                  /* (DSU_DAL) CPU 0 Debugger Access Level Mask */
+#define DSU_DAL_CPU0(value)                   (DSU_DAL_CPU0_Msk & (_UINT32_(value) << DSU_DAL_CPU0_Pos)) /* Assignment of value for CPU0 in the DSU_DAL register */
+#define   DSU_DAL_CPU0_SECURED_Val            _UINT32_(0x0)                                        /* (DSU_DAL) Debugger targeting CPU0 domain can only access the DSU external address space otherwise debugger access is disabled  */
+#define   DSU_DAL_CPU0_NS_DEBUG_Val           _UINT32_(0x1)                                        /* (DSU_DAL) Debugger can access only non-secure regions  */
+#define   DSU_DAL_CPU0_FULL_DEBUG_Val         _UINT32_(0x2)                                        /* (DSU_DAL) Debugger can access secure and non-secure regions  */
+#define DSU_DAL_CPU0_SECURED                  (DSU_DAL_CPU0_SECURED_Val << DSU_DAL_CPU0_Pos)       /* (DSU_DAL) Debugger targeting CPU0 domain can only access the DSU external address space otherwise debugger access is disabled Position */
+#define DSU_DAL_CPU0_NS_DEBUG                 (DSU_DAL_CPU0_NS_DEBUG_Val << DSU_DAL_CPU0_Pos)      /* (DSU_DAL) Debugger can access only non-secure regions Position */
+#define DSU_DAL_CPU0_FULL_DEBUG               (DSU_DAL_CPU0_FULL_DEBUG_Val << DSU_DAL_CPU0_Pos)    /* (DSU_DAL) Debugger can access secure and non-secure regions Position */
+#define DSU_DAL_CPU1_Pos                      _UINT32_(2)                                          /* (DSU_DAL) CPU n Debugger Access Level Position */
+#define DSU_DAL_CPU1_Msk                      (_UINT32_(0x3) << DSU_DAL_CPU1_Pos)                  /* (DSU_DAL) CPU n Debugger Access Level Mask */
+#define DSU_DAL_CPU1(value)                   (DSU_DAL_CPU1_Msk & (_UINT32_(value) << DSU_DAL_CPU1_Pos)) /* Assignment of value for CPU1 in the DSU_DAL register */
+#define   DSU_DAL_CPU1_SECURED_Val            _UINT32_(0x0)                                        /* (DSU_DAL) Debugger access is disabled  */
+#define   DSU_DAL_CPU1_NS_DEBUG_Val           _UINT32_(0x1)                                        /* (DSU_DAL) Debugger can access only non-secure regions  */
+#define   DSU_DAL_CPU1_FULL_DEBUG_Val         _UINT32_(0x2)                                        /* (DSU_DAL) Debugger has full access to debug CPUn  */
+#define   DSU_DAL_CPU1_UNIMPLEMENTED_Val      _UINT32_(0x3)                                        /* (DSU_DAL) Unimplemented CPU  */
+#define DSU_DAL_CPU1_SECURED                  (DSU_DAL_CPU1_SECURED_Val << DSU_DAL_CPU1_Pos)       /* (DSU_DAL) Debugger access is disabled Position */
+#define DSU_DAL_CPU1_NS_DEBUG                 (DSU_DAL_CPU1_NS_DEBUG_Val << DSU_DAL_CPU1_Pos)      /* (DSU_DAL) Debugger can access only non-secure regions Position */
+#define DSU_DAL_CPU1_FULL_DEBUG               (DSU_DAL_CPU1_FULL_DEBUG_Val << DSU_DAL_CPU1_Pos)    /* (DSU_DAL) Debugger has full access to debug CPUn Position */
+#define DSU_DAL_CPU1_UNIMPLEMENTED            (DSU_DAL_CPU1_UNIMPLEMENTED_Val << DSU_DAL_CPU1_Pos) /* (DSU_DAL) Unimplemented CPU Position */
+#define DSU_DAL_CPU2_Pos                      _UINT32_(4)                                          /* (DSU_DAL) CPU n Debugger Access Level Position */
+#define DSU_DAL_CPU2_Msk                      (_UINT32_(0x3) << DSU_DAL_CPU2_Pos)                  /* (DSU_DAL) CPU n Debugger Access Level Mask */
+#define DSU_DAL_CPU2(value)                   (DSU_DAL_CPU2_Msk & (_UINT32_(value) << DSU_DAL_CPU2_Pos)) /* Assignment of value for CPU2 in the DSU_DAL register */
+#define   DSU_DAL_CPU2_SECURED_Val            _UINT32_(0x0)                                        /* (DSU_DAL) Debugger access is disabled  */
+#define   DSU_DAL_CPU2_NS_DEBUG_Val           _UINT32_(0x1)                                        /* (DSU_DAL) Debugger can access only non-secure regions  */
+#define   DSU_DAL_CPU2_FULL_DEBUG_Val         _UINT32_(0x2)                                        /* (DSU_DAL) Debugger has full access to debug CPUn  */
+#define   DSU_DAL_CPU2_UNIMPLEMENTED_Val      _UINT32_(0x3)                                        /* (DSU_DAL) Unimplemented CPU  */
+#define DSU_DAL_CPU2_SECURED                  (DSU_DAL_CPU2_SECURED_Val << DSU_DAL_CPU2_Pos)       /* (DSU_DAL) Debugger access is disabled Position */
+#define DSU_DAL_CPU2_NS_DEBUG                 (DSU_DAL_CPU2_NS_DEBUG_Val << DSU_DAL_CPU2_Pos)      /* (DSU_DAL) Debugger can access only non-secure regions Position */
+#define DSU_DAL_CPU2_FULL_DEBUG               (DSU_DAL_CPU2_FULL_DEBUG_Val << DSU_DAL_CPU2_Pos)    /* (DSU_DAL) Debugger has full access to debug CPUn Position */
+#define DSU_DAL_CPU2_UNIMPLEMENTED            (DSU_DAL_CPU2_UNIMPLEMENTED_Val << DSU_DAL_CPU2_Pos) /* (DSU_DAL) Unimplemented CPU Position */
+#define DSU_DAL_CPU3_Pos                      _UINT32_(6)                                          /* (DSU_DAL) CPU n Debugger Access Level Position */
+#define DSU_DAL_CPU3_Msk                      (_UINT32_(0x3) << DSU_DAL_CPU3_Pos)                  /* (DSU_DAL) CPU n Debugger Access Level Mask */
+#define DSU_DAL_CPU3(value)                   (DSU_DAL_CPU3_Msk & (_UINT32_(value) << DSU_DAL_CPU3_Pos)) /* Assignment of value for CPU3 in the DSU_DAL register */
+#define   DSU_DAL_CPU3_SECURED_Val            _UINT32_(0x0)                                        /* (DSU_DAL) Debugger access is disabled  */
+#define   DSU_DAL_CPU3_NS_DEBUG_Val           _UINT32_(0x1)                                        /* (DSU_DAL) Debugger can access only non-secure regions  */
+#define   DSU_DAL_CPU3_FULL_DEBUG_Val         _UINT32_(0x2)                                        /* (DSU_DAL) Debugger has full access to debug CPUn  */
+#define   DSU_DAL_CPU3_UNIMPLEMENTED_Val      _UINT32_(0x3)                                        /* (DSU_DAL) Unimplemented CPU  */
+#define DSU_DAL_CPU3_SECURED                  (DSU_DAL_CPU3_SECURED_Val << DSU_DAL_CPU3_Pos)       /* (DSU_DAL) Debugger access is disabled Position */
+#define DSU_DAL_CPU3_NS_DEBUG                 (DSU_DAL_CPU3_NS_DEBUG_Val << DSU_DAL_CPU3_Pos)      /* (DSU_DAL) Debugger can access only non-secure regions Position */
+#define DSU_DAL_CPU3_FULL_DEBUG               (DSU_DAL_CPU3_FULL_DEBUG_Val << DSU_DAL_CPU3_Pos)    /* (DSU_DAL) Debugger has full access to debug CPUn Position */
+#define DSU_DAL_CPU3_UNIMPLEMENTED            (DSU_DAL_CPU3_UNIMPLEMENTED_Val << DSU_DAL_CPU3_Pos) /* (DSU_DAL) Unimplemented CPU Position */
+#define DSU_DAL_Msk                           _UINT32_(0x000000FF)                                 /* (DSU_DAL) Register Mask  */
+
+
+/* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) ( R/ 32) CoreSight ROM Table Entry N Register -------- */
+#define DSU_ENTRY0_RESETVALUE                 _UINT32_(0x9C0FE002)                                 /*  (DSU_ENTRY0) CoreSight ROM Table Entry N Register  Reset Value */
+
+#define DSU_ENTRY0_EPRES_Pos                  _UINT32_(0)                                          /* (DSU_ENTRY0) CoreSight Entry Present Position */
+#define DSU_ENTRY0_EPRES_Msk                  (_UINT32_(0x1) << DSU_ENTRY0_EPRES_Pos)              /* (DSU_ENTRY0) CoreSight Entry Present Mask */
+#define DSU_ENTRY0_EPRES(value)               (DSU_ENTRY0_EPRES_Msk & (_UINT32_(value) << DSU_ENTRY0_EPRES_Pos)) /* Assignment of value for EPRES in the DSU_ENTRY0 register */
+#define   DSU_ENTRY0_EPRES_0_Val              _UINT32_(0x0)                                        /* (DSU_ENTRY0) Entry not present  */
+#define   DSU_ENTRY0_EPRES_1_Val              _UINT32_(0x1)                                        /* (DSU_ENTRY0) Entry present  */
+#define DSU_ENTRY0_EPRES_0                    (DSU_ENTRY0_EPRES_0_Val << DSU_ENTRY0_EPRES_Pos)     /* (DSU_ENTRY0) Entry not present Position */
+#define DSU_ENTRY0_EPRES_1                    (DSU_ENTRY0_EPRES_1_Val << DSU_ENTRY0_EPRES_Pos)     /* (DSU_ENTRY0) Entry present Position */
+#define DSU_ENTRY0_FMT_Pos                    _UINT32_(1)                                          /* (DSU_ENTRY0) CoreSight Rom Table Format Position */
+#define DSU_ENTRY0_FMT_Msk                    (_UINT32_(0x1) << DSU_ENTRY0_FMT_Pos)                /* (DSU_ENTRY0) CoreSight Rom Table Format Mask */
+#define DSU_ENTRY0_FMT(value)                 (DSU_ENTRY0_FMT_Msk & (_UINT32_(value) << DSU_ENTRY0_FMT_Pos)) /* Assignment of value for FMT in the DSU_ENTRY0 register */
+#define   DSU_ENTRY0_FMT_0_Val                _UINT32_(0x0)                                        /* (DSU_ENTRY0) 8-bit format  */
+#define   DSU_ENTRY0_FMT_1_Val                _UINT32_(0x1)                                        /* (DSU_ENTRY0) 32-bit format  */
+#define DSU_ENTRY0_FMT_0                      (DSU_ENTRY0_FMT_0_Val << DSU_ENTRY0_FMT_Pos)         /* (DSU_ENTRY0) 8-bit format Position */
+#define DSU_ENTRY0_FMT_1                      (DSU_ENTRY0_FMT_1_Val << DSU_ENTRY0_FMT_Pos)         /* (DSU_ENTRY0) 32-bit format Position */
+#define DSU_ENTRY0_ADDOFF_Pos                 _UINT32_(12)                                         /* (DSU_ENTRY0) CoreSight ROM Table Address Offset Position */
+#define DSU_ENTRY0_ADDOFF_Msk                 (_UINT32_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos)         /* (DSU_ENTRY0) CoreSight ROM Table Address Offset Mask */
+#define DSU_ENTRY0_ADDOFF(value)              (DSU_ENTRY0_ADDOFF_Msk & (_UINT32_(value) << DSU_ENTRY0_ADDOFF_Pos)) /* Assignment of value for ADDOFF in the DSU_ENTRY0 register */
+#define DSU_ENTRY0_Msk                        _UINT32_(0xFFFFF003)                                 /* (DSU_ENTRY0) Register Mask  */
+
+
+/* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) ( R/ 32) CoreSight ROM Table Entry N Register -------- */
+#define DSU_ENTRY1_RESETVALUE                 _UINT32_(0xBBFFF002)                                 /*  (DSU_ENTRY1) CoreSight ROM Table Entry N Register  Reset Value */
+
+#define DSU_ENTRY1_EPRES_Pos                  _UINT32_(0)                                          /* (DSU_ENTRY1) CoreSight Entry Present Position */
+#define DSU_ENTRY1_EPRES_Msk                  (_UINT32_(0x1) << DSU_ENTRY1_EPRES_Pos)              /* (DSU_ENTRY1) CoreSight Entry Present Mask */
+#define DSU_ENTRY1_EPRES(value)               (DSU_ENTRY1_EPRES_Msk & (_UINT32_(value) << DSU_ENTRY1_EPRES_Pos)) /* Assignment of value for EPRES in the DSU_ENTRY1 register */
+#define   DSU_ENTRY1_EPRES_0_Val              _UINT32_(0x0)                                        /* (DSU_ENTRY1) Entry not present  */
+#define   DSU_ENTRY1_EPRES_1_Val              _UINT32_(0x1)                                        /* (DSU_ENTRY1) Entry present  */
+#define DSU_ENTRY1_EPRES_0                    (DSU_ENTRY1_EPRES_0_Val << DSU_ENTRY1_EPRES_Pos)     /* (DSU_ENTRY1) Entry not present Position */
+#define DSU_ENTRY1_EPRES_1                    (DSU_ENTRY1_EPRES_1_Val << DSU_ENTRY1_EPRES_Pos)     /* (DSU_ENTRY1) Entry present Position */
+#define DSU_ENTRY1_FMT_Pos                    _UINT32_(1)                                          /* (DSU_ENTRY1) CoreSight Rom Table Format Position */
+#define DSU_ENTRY1_FMT_Msk                    (_UINT32_(0x1) << DSU_ENTRY1_FMT_Pos)                /* (DSU_ENTRY1) CoreSight Rom Table Format Mask */
+#define DSU_ENTRY1_FMT(value)                 (DSU_ENTRY1_FMT_Msk & (_UINT32_(value) << DSU_ENTRY1_FMT_Pos)) /* Assignment of value for FMT in the DSU_ENTRY1 register */
+#define   DSU_ENTRY1_FMT_0_Val                _UINT32_(0x0)                                        /* (DSU_ENTRY1) 8-bit format  */
+#define   DSU_ENTRY1_FMT_1_Val                _UINT32_(0x1)                                        /* (DSU_ENTRY1) 32-bit format  */
+#define DSU_ENTRY1_FMT_0                      (DSU_ENTRY1_FMT_0_Val << DSU_ENTRY1_FMT_Pos)         /* (DSU_ENTRY1) 8-bit format Position */
+#define DSU_ENTRY1_FMT_1                      (DSU_ENTRY1_FMT_1_Val << DSU_ENTRY1_FMT_Pos)         /* (DSU_ENTRY1) 32-bit format Position */
+#define DSU_ENTRY1_ADDOFF_Pos                 _UINT32_(12)                                         /* (DSU_ENTRY1) CoreSight ROM Table Address Offset Position */
+#define DSU_ENTRY1_ADDOFF_Msk                 (_UINT32_(0xFFFFF) << DSU_ENTRY1_ADDOFF_Pos)         /* (DSU_ENTRY1) CoreSight ROM Table Address Offset Mask */
+#define DSU_ENTRY1_ADDOFF(value)              (DSU_ENTRY1_ADDOFF_Msk & (_UINT32_(value) << DSU_ENTRY1_ADDOFF_Pos)) /* Assignment of value for ADDOFF in the DSU_ENTRY1 register */
+#define DSU_ENTRY1_Msk                        _UINT32_(0xFFFFF003)                                 /* (DSU_ENTRY1) Register Mask  */
+
+
+/* -------- DSU_ENTRY2 : (DSU Offset: 0x1008) ( R/ 32) CoreSight ROM Table Entry N Register -------- */
+#define DSU_ENTRY2_RESETVALUE                 _UINT32_(0xBBFFF002)                                 /*  (DSU_ENTRY2) CoreSight ROM Table Entry N Register  Reset Value */
+
+#define DSU_ENTRY2_EPRES_Pos                  _UINT32_(0)                                          /* (DSU_ENTRY2) CoreSight Entry Present Position */
+#define DSU_ENTRY2_EPRES_Msk                  (_UINT32_(0x1) << DSU_ENTRY2_EPRES_Pos)              /* (DSU_ENTRY2) CoreSight Entry Present Mask */
+#define DSU_ENTRY2_EPRES(value)               (DSU_ENTRY2_EPRES_Msk & (_UINT32_(value) << DSU_ENTRY2_EPRES_Pos)) /* Assignment of value for EPRES in the DSU_ENTRY2 register */
+#define   DSU_ENTRY2_EPRES_0_Val              _UINT32_(0x0)                                        /* (DSU_ENTRY2) Entry not present  */
+#define   DSU_ENTRY2_EPRES_1_Val              _UINT32_(0x1)                                        /* (DSU_ENTRY2) Entry present  */
+#define DSU_ENTRY2_EPRES_0                    (DSU_ENTRY2_EPRES_0_Val << DSU_ENTRY2_EPRES_Pos)     /* (DSU_ENTRY2) Entry not present Position */
+#define DSU_ENTRY2_EPRES_1                    (DSU_ENTRY2_EPRES_1_Val << DSU_ENTRY2_EPRES_Pos)     /* (DSU_ENTRY2) Entry present Position */
+#define DSU_ENTRY2_FMT_Pos                    _UINT32_(1)                                          /* (DSU_ENTRY2) CoreSight Rom Table Format Position */
+#define DSU_ENTRY2_FMT_Msk                    (_UINT32_(0x1) << DSU_ENTRY2_FMT_Pos)                /* (DSU_ENTRY2) CoreSight Rom Table Format Mask */
+#define DSU_ENTRY2_FMT(value)                 (DSU_ENTRY2_FMT_Msk & (_UINT32_(value) << DSU_ENTRY2_FMT_Pos)) /* Assignment of value for FMT in the DSU_ENTRY2 register */
+#define   DSU_ENTRY2_FMT_0_Val                _UINT32_(0x0)                                        /* (DSU_ENTRY2) 8-bit format  */
+#define   DSU_ENTRY2_FMT_1_Val                _UINT32_(0x1)                                        /* (DSU_ENTRY2) 32-bit format  */
+#define DSU_ENTRY2_FMT_0                      (DSU_ENTRY2_FMT_0_Val << DSU_ENTRY2_FMT_Pos)         /* (DSU_ENTRY2) 8-bit format Position */
+#define DSU_ENTRY2_FMT_1                      (DSU_ENTRY2_FMT_1_Val << DSU_ENTRY2_FMT_Pos)         /* (DSU_ENTRY2) 32-bit format Position */
+#define DSU_ENTRY2_ADDOFF_Pos                 _UINT32_(12)                                         /* (DSU_ENTRY2) CoreSight ROM Table Address Offset Position */
+#define DSU_ENTRY2_ADDOFF_Msk                 (_UINT32_(0xFFFFF) << DSU_ENTRY2_ADDOFF_Pos)         /* (DSU_ENTRY2) CoreSight ROM Table Address Offset Mask */
+#define DSU_ENTRY2_ADDOFF(value)              (DSU_ENTRY2_ADDOFF_Msk & (_UINT32_(value) << DSU_ENTRY2_ADDOFF_Pos)) /* Assignment of value for ADDOFF in the DSU_ENTRY2 register */
+#define DSU_ENTRY2_Msk                        _UINT32_(0xFFFFF003)                                 /* (DSU_ENTRY2) Register Mask  */
+
+
+/* -------- DSU_ENTRY3 : (DSU Offset: 0x100C) ( R/ 32) CoreSight ROM Table Entry N Register -------- */
+#define DSU_ENTRY3_RESETVALUE                 _UINT32_(0xBBFFF002)                                 /*  (DSU_ENTRY3) CoreSight ROM Table Entry N Register  Reset Value */
+
+#define DSU_ENTRY3_EPRES_Pos                  _UINT32_(0)                                          /* (DSU_ENTRY3) CoreSight Entry Present Position */
+#define DSU_ENTRY3_EPRES_Msk                  (_UINT32_(0x1) << DSU_ENTRY3_EPRES_Pos)              /* (DSU_ENTRY3) CoreSight Entry Present Mask */
+#define DSU_ENTRY3_EPRES(value)               (DSU_ENTRY3_EPRES_Msk & (_UINT32_(value) << DSU_ENTRY3_EPRES_Pos)) /* Assignment of value for EPRES in the DSU_ENTRY3 register */
+#define   DSU_ENTRY3_EPRES_0_Val              _UINT32_(0x0)                                        /* (DSU_ENTRY3) Entry not present  */
+#define   DSU_ENTRY3_EPRES_1_Val              _UINT32_(0x1)                                        /* (DSU_ENTRY3) Entry present  */
+#define DSU_ENTRY3_EPRES_0                    (DSU_ENTRY3_EPRES_0_Val << DSU_ENTRY3_EPRES_Pos)     /* (DSU_ENTRY3) Entry not present Position */
+#define DSU_ENTRY3_EPRES_1                    (DSU_ENTRY3_EPRES_1_Val << DSU_ENTRY3_EPRES_Pos)     /* (DSU_ENTRY3) Entry present Position */
+#define DSU_ENTRY3_FMT_Pos                    _UINT32_(1)                                          /* (DSU_ENTRY3) CoreSight Rom Table Format Position */
+#define DSU_ENTRY3_FMT_Msk                    (_UINT32_(0x1) << DSU_ENTRY3_FMT_Pos)                /* (DSU_ENTRY3) CoreSight Rom Table Format Mask */
+#define DSU_ENTRY3_FMT(value)                 (DSU_ENTRY3_FMT_Msk & (_UINT32_(value) << DSU_ENTRY3_FMT_Pos)) /* Assignment of value for FMT in the DSU_ENTRY3 register */
+#define   DSU_ENTRY3_FMT_0_Val                _UINT32_(0x0)                                        /* (DSU_ENTRY3) 8-bit format  */
+#define   DSU_ENTRY3_FMT_1_Val                _UINT32_(0x1)                                        /* (DSU_ENTRY3) 32-bit format  */
+#define DSU_ENTRY3_FMT_0                      (DSU_ENTRY3_FMT_0_Val << DSU_ENTRY3_FMT_Pos)         /* (DSU_ENTRY3) 8-bit format Position */
+#define DSU_ENTRY3_FMT_1                      (DSU_ENTRY3_FMT_1_Val << DSU_ENTRY3_FMT_Pos)         /* (DSU_ENTRY3) 32-bit format Position */
+#define DSU_ENTRY3_ADDOFF_Pos                 _UINT32_(12)                                         /* (DSU_ENTRY3) CoreSight ROM Table Address Offset Position */
+#define DSU_ENTRY3_ADDOFF_Msk                 (_UINT32_(0xFFFFF) << DSU_ENTRY3_ADDOFF_Pos)         /* (DSU_ENTRY3) CoreSight ROM Table Address Offset Mask */
+#define DSU_ENTRY3_ADDOFF(value)              (DSU_ENTRY3_ADDOFF_Msk & (_UINT32_(value) << DSU_ENTRY3_ADDOFF_Pos)) /* Assignment of value for ADDOFF in the DSU_ENTRY3 register */
+#define DSU_ENTRY3_Msk                        _UINT32_(0xFFFFF003)                                 /* (DSU_ENTRY3) Register Mask  */
+
+
+/* -------- DSU_ENTRY4 : (DSU Offset: 0x1010) ( R/ 32) CoreSight ROM Table Entry 4 Register -------- */
+#define DSU_ENTRY4_RESETVALUE                 _UINT32_(0x00)                                       /*  (DSU_ENTRY4) CoreSight ROM Table Entry 4 Register  Reset Value */
+
+#define DSU_ENTRY4_EPRES_Pos                  _UINT32_(0)                                          /* (DSU_ENTRY4) CoreSight Entry Present Position */
+#define DSU_ENTRY4_EPRES_Msk                  (_UINT32_(0x1) << DSU_ENTRY4_EPRES_Pos)              /* (DSU_ENTRY4) CoreSight Entry Present Mask */
+#define DSU_ENTRY4_EPRES(value)               (DSU_ENTRY4_EPRES_Msk & (_UINT32_(value) << DSU_ENTRY4_EPRES_Pos)) /* Assignment of value for EPRES in the DSU_ENTRY4 register */
+#define   DSU_ENTRY4_EPRES_0_Val              _UINT32_(0x0)                                        /* (DSU_ENTRY4) Entry not present  */
+#define   DSU_ENTRY4_EPRES_1_Val              _UINT32_(0x1)                                        /* (DSU_ENTRY4) Entry present  */
+#define DSU_ENTRY4_EPRES_0                    (DSU_ENTRY4_EPRES_0_Val << DSU_ENTRY4_EPRES_Pos)     /* (DSU_ENTRY4) Entry not present Position */
+#define DSU_ENTRY4_EPRES_1                    (DSU_ENTRY4_EPRES_1_Val << DSU_ENTRY4_EPRES_Pos)     /* (DSU_ENTRY4) Entry present Position */
+#define DSU_ENTRY4_FMT_Pos                    _UINT32_(1)                                          /* (DSU_ENTRY4) CoreSight Rom Table Format Position */
+#define DSU_ENTRY4_FMT_Msk                    (_UINT32_(0x1) << DSU_ENTRY4_FMT_Pos)                /* (DSU_ENTRY4) CoreSight Rom Table Format Mask */
+#define DSU_ENTRY4_FMT(value)                 (DSU_ENTRY4_FMT_Msk & (_UINT32_(value) << DSU_ENTRY4_FMT_Pos)) /* Assignment of value for FMT in the DSU_ENTRY4 register */
+#define   DSU_ENTRY4_FMT_0_Val                _UINT32_(0x0)                                        /* (DSU_ENTRY4) 8-bit format  */
+#define   DSU_ENTRY4_FMT_1_Val                _UINT32_(0x1)                                        /* (DSU_ENTRY4) 32-bit format  */
+#define DSU_ENTRY4_FMT_0                      (DSU_ENTRY4_FMT_0_Val << DSU_ENTRY4_FMT_Pos)         /* (DSU_ENTRY4) 8-bit format Position */
+#define DSU_ENTRY4_FMT_1                      (DSU_ENTRY4_FMT_1_Val << DSU_ENTRY4_FMT_Pos)         /* (DSU_ENTRY4) 32-bit format Position */
+#define DSU_ENTRY4_ADDOFF_Pos                 _UINT32_(12)                                         /* (DSU_ENTRY4) CoreSight ROM Table Address Offset Position */
+#define DSU_ENTRY4_ADDOFF_Msk                 (_UINT32_(0xFFFFF) << DSU_ENTRY4_ADDOFF_Pos)         /* (DSU_ENTRY4) CoreSight ROM Table Address Offset Mask */
+#define DSU_ENTRY4_ADDOFF(value)              (DSU_ENTRY4_ADDOFF_Msk & (_UINT32_(value) << DSU_ENTRY4_ADDOFF_Pos)) /* Assignment of value for ADDOFF in the DSU_ENTRY4 register */
+#define DSU_ENTRY4_Msk                        _UINT32_(0xFFFFF003)                                 /* (DSU_ENTRY4) Register Mask  */
+
+
+/* -------- DSU_ENTRY5 : (DSU Offset: 0x1014) ( R/ 32) CoreSight ROM Table Entry 5 Register -------- */
+#define DSU_ENTRY5_RESETVALUE                 _UINT32_(0x00)                                       /*  (DSU_ENTRY5) CoreSight ROM Table Entry 5 Register  Reset Value */
+
+#define DSU_ENTRY5_EPRES_Pos                  _UINT32_(0)                                          /* (DSU_ENTRY5) CoreSight Entry Present Position */
+#define DSU_ENTRY5_EPRES_Msk                  (_UINT32_(0x1) << DSU_ENTRY5_EPRES_Pos)              /* (DSU_ENTRY5) CoreSight Entry Present Mask */
+#define DSU_ENTRY5_EPRES(value)               (DSU_ENTRY5_EPRES_Msk & (_UINT32_(value) << DSU_ENTRY5_EPRES_Pos)) /* Assignment of value for EPRES in the DSU_ENTRY5 register */
+#define   DSU_ENTRY5_EPRES_0_Val              _UINT32_(0x0)                                        /* (DSU_ENTRY5) Entry not present  */
+#define   DSU_ENTRY5_EPRES_1_Val              _UINT32_(0x1)                                        /* (DSU_ENTRY5) Entry present  */
+#define DSU_ENTRY5_EPRES_0                    (DSU_ENTRY5_EPRES_0_Val << DSU_ENTRY5_EPRES_Pos)     /* (DSU_ENTRY5) Entry not present Position */
+#define DSU_ENTRY5_EPRES_1                    (DSU_ENTRY5_EPRES_1_Val << DSU_ENTRY5_EPRES_Pos)     /* (DSU_ENTRY5) Entry present Position */
+#define DSU_ENTRY5_FMT_Pos                    _UINT32_(1)                                          /* (DSU_ENTRY5) CoreSight Rom Table Format Position */
+#define DSU_ENTRY5_FMT_Msk                    (_UINT32_(0x1) << DSU_ENTRY5_FMT_Pos)                /* (DSU_ENTRY5) CoreSight Rom Table Format Mask */
+#define DSU_ENTRY5_FMT(value)                 (DSU_ENTRY5_FMT_Msk & (_UINT32_(value) << DSU_ENTRY5_FMT_Pos)) /* Assignment of value for FMT in the DSU_ENTRY5 register */
+#define   DSU_ENTRY5_FMT_0_Val                _UINT32_(0x0)                                        /* (DSU_ENTRY5) 8-bit format  */
+#define   DSU_ENTRY5_FMT_1_Val                _UINT32_(0x1)                                        /* (DSU_ENTRY5) 32-bit format  */
+#define DSU_ENTRY5_FMT_0                      (DSU_ENTRY5_FMT_0_Val << DSU_ENTRY5_FMT_Pos)         /* (DSU_ENTRY5) 8-bit format Position */
+#define DSU_ENTRY5_FMT_1                      (DSU_ENTRY5_FMT_1_Val << DSU_ENTRY5_FMT_Pos)         /* (DSU_ENTRY5) 32-bit format Position */
+#define DSU_ENTRY5_ADDOFF_Pos                 _UINT32_(12)                                         /* (DSU_ENTRY5) CoreSight ROM Table Address Offset Position */
+#define DSU_ENTRY5_ADDOFF_Msk                 (_UINT32_(0xFFFFF) << DSU_ENTRY5_ADDOFF_Pos)         /* (DSU_ENTRY5) CoreSight ROM Table Address Offset Mask */
+#define DSU_ENTRY5_ADDOFF(value)              (DSU_ENTRY5_ADDOFF_Msk & (_UINT32_(value) << DSU_ENTRY5_ADDOFF_Pos)) /* Assignment of value for ADDOFF in the DSU_ENTRY5 register */
+#define DSU_ENTRY5_Msk                        _UINT32_(0xFFFFF003)                                 /* (DSU_ENTRY5) Register Mask  */
+
+
+/* -------- DSU_ENTRY6 : (DSU Offset: 0x1018) ( R/ 32) CoreSight ROM Table Entry 6 Register -------- */
+#define DSU_ENTRY6_RESETVALUE                 _UINT32_(0x00)                                       /*  (DSU_ENTRY6) CoreSight ROM Table Entry 6 Register  Reset Value */
+
+#define DSU_ENTRY6_EPRES_Pos                  _UINT32_(0)                                          /* (DSU_ENTRY6) CoreSight Entry Present Position */
+#define DSU_ENTRY6_EPRES_Msk                  (_UINT32_(0x1) << DSU_ENTRY6_EPRES_Pos)              /* (DSU_ENTRY6) CoreSight Entry Present Mask */
+#define DSU_ENTRY6_EPRES(value)               (DSU_ENTRY6_EPRES_Msk & (_UINT32_(value) << DSU_ENTRY6_EPRES_Pos)) /* Assignment of value for EPRES in the DSU_ENTRY6 register */
+#define   DSU_ENTRY6_EPRES_0_Val              _UINT32_(0x0)                                        /* (DSU_ENTRY6) Entry not present  */
+#define   DSU_ENTRY6_EPRES_1_Val              _UINT32_(0x1)                                        /* (DSU_ENTRY6) Entry present  */
+#define DSU_ENTRY6_EPRES_0                    (DSU_ENTRY6_EPRES_0_Val << DSU_ENTRY6_EPRES_Pos)     /* (DSU_ENTRY6) Entry not present Position */
+#define DSU_ENTRY6_EPRES_1                    (DSU_ENTRY6_EPRES_1_Val << DSU_ENTRY6_EPRES_Pos)     /* (DSU_ENTRY6) Entry present Position */
+#define DSU_ENTRY6_FMT_Pos                    _UINT32_(1)                                          /* (DSU_ENTRY6) CoreSight Rom Table Format Position */
+#define DSU_ENTRY6_FMT_Msk                    (_UINT32_(0x1) << DSU_ENTRY6_FMT_Pos)                /* (DSU_ENTRY6) CoreSight Rom Table Format Mask */
+#define DSU_ENTRY6_FMT(value)                 (DSU_ENTRY6_FMT_Msk & (_UINT32_(value) << DSU_ENTRY6_FMT_Pos)) /* Assignment of value for FMT in the DSU_ENTRY6 register */
+#define   DSU_ENTRY6_FMT_0_Val                _UINT32_(0x0)                                        /* (DSU_ENTRY6) 8-bit format  */
+#define   DSU_ENTRY6_FMT_1_Val                _UINT32_(0x1)                                        /* (DSU_ENTRY6) 32-bit format  */
+#define DSU_ENTRY6_FMT_0                      (DSU_ENTRY6_FMT_0_Val << DSU_ENTRY6_FMT_Pos)         /* (DSU_ENTRY6) 8-bit format Position */
+#define DSU_ENTRY6_FMT_1                      (DSU_ENTRY6_FMT_1_Val << DSU_ENTRY6_FMT_Pos)         /* (DSU_ENTRY6) 32-bit format Position */
+#define DSU_ENTRY6_ADDOFF_Pos                 _UINT32_(12)                                         /* (DSU_ENTRY6) CoreSight ROM Table Address Offset Position */
+#define DSU_ENTRY6_ADDOFF_Msk                 (_UINT32_(0xFFFFF) << DSU_ENTRY6_ADDOFF_Pos)         /* (DSU_ENTRY6) CoreSight ROM Table Address Offset Mask */
+#define DSU_ENTRY6_ADDOFF(value)              (DSU_ENTRY6_ADDOFF_Msk & (_UINT32_(value) << DSU_ENTRY6_ADDOFF_Pos)) /* Assignment of value for ADDOFF in the DSU_ENTRY6 register */
+#define DSU_ENTRY6_Msk                        _UINT32_(0xFFFFF003)                                 /* (DSU_ENTRY6) Register Mask  */
+
+
+/* -------- DSU_ENTRY7 : (DSU Offset: 0x101C) ( R/ 32) CoreSight ROM Table Entry 7 Register -------- */
+#define DSU_ENTRY7_RESETVALUE                 _UINT32_(0x00)                                       /*  (DSU_ENTRY7) CoreSight ROM Table Entry 7 Register  Reset Value */
+
+#define DSU_ENTRY7_EPRES_Pos                  _UINT32_(0)                                          /* (DSU_ENTRY7) CoreSight Entry Present Position */
+#define DSU_ENTRY7_EPRES_Msk                  (_UINT32_(0x1) << DSU_ENTRY7_EPRES_Pos)              /* (DSU_ENTRY7) CoreSight Entry Present Mask */
+#define DSU_ENTRY7_EPRES(value)               (DSU_ENTRY7_EPRES_Msk & (_UINT32_(value) << DSU_ENTRY7_EPRES_Pos)) /* Assignment of value for EPRES in the DSU_ENTRY7 register */
+#define   DSU_ENTRY7_EPRES_0_Val              _UINT32_(0x0)                                        /* (DSU_ENTRY7) Entry not present  */
+#define   DSU_ENTRY7_EPRES_1_Val              _UINT32_(0x1)                                        /* (DSU_ENTRY7) Entry present  */
+#define DSU_ENTRY7_EPRES_0                    (DSU_ENTRY7_EPRES_0_Val << DSU_ENTRY7_EPRES_Pos)     /* (DSU_ENTRY7) Entry not present Position */
+#define DSU_ENTRY7_EPRES_1                    (DSU_ENTRY7_EPRES_1_Val << DSU_ENTRY7_EPRES_Pos)     /* (DSU_ENTRY7) Entry present Position */
+#define DSU_ENTRY7_FMT_Pos                    _UINT32_(1)                                          /* (DSU_ENTRY7) CoreSight Rom Table Format Position */
+#define DSU_ENTRY7_FMT_Msk                    (_UINT32_(0x1) << DSU_ENTRY7_FMT_Pos)                /* (DSU_ENTRY7) CoreSight Rom Table Format Mask */
+#define DSU_ENTRY7_FMT(value)                 (DSU_ENTRY7_FMT_Msk & (_UINT32_(value) << DSU_ENTRY7_FMT_Pos)) /* Assignment of value for FMT in the DSU_ENTRY7 register */
+#define   DSU_ENTRY7_FMT_0_Val                _UINT32_(0x0)                                        /* (DSU_ENTRY7) 8-bit format  */
+#define   DSU_ENTRY7_FMT_1_Val                _UINT32_(0x1)                                        /* (DSU_ENTRY7) 32-bit format  */
+#define DSU_ENTRY7_FMT_0                      (DSU_ENTRY7_FMT_0_Val << DSU_ENTRY7_FMT_Pos)         /* (DSU_ENTRY7) 8-bit format Position */
+#define DSU_ENTRY7_FMT_1                      (DSU_ENTRY7_FMT_1_Val << DSU_ENTRY7_FMT_Pos)         /* (DSU_ENTRY7) 32-bit format Position */
+#define DSU_ENTRY7_ADDOFF_Pos                 _UINT32_(12)                                         /* (DSU_ENTRY7) CoreSight ROM Table Address Offset Position */
+#define DSU_ENTRY7_ADDOFF_Msk                 (_UINT32_(0xFFFFF) << DSU_ENTRY7_ADDOFF_Pos)         /* (DSU_ENTRY7) CoreSight ROM Table Address Offset Mask */
+#define DSU_ENTRY7_ADDOFF(value)              (DSU_ENTRY7_ADDOFF_Msk & (_UINT32_(value) << DSU_ENTRY7_ADDOFF_Pos)) /* Assignment of value for ADDOFF in the DSU_ENTRY7 register */
+#define DSU_ENTRY7_Msk                        _UINT32_(0xFFFFF003)                                 /* (DSU_ENTRY7) Register Mask  */
+
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) ( R/ 32) CoreSight ROM Table Memory Type Register -------- */
+#define DSU_MEMTYPE_RESETVALUE                _UINT32_(0x00)                                       /*  (DSU_MEMTYPE) CoreSight ROM Table Memory Type Register  Reset Value */
+
+#define DSU_MEMTYPE_SYSMEM_Pos                _UINT32_(0)                                          /* (DSU_MEMTYPE) CoreSight System Memory Present Position */
+#define DSU_MEMTYPE_SYSMEM_Msk                (_UINT32_(0x1) << DSU_MEMTYPE_SYSMEM_Pos)            /* (DSU_MEMTYPE) CoreSight System Memory Present Mask */
+#define DSU_MEMTYPE_SYSMEM(value)             (DSU_MEMTYPE_SYSMEM_Msk & (_UINT32_(value) << DSU_MEMTYPE_SYSMEM_Pos)) /* Assignment of value for SYSMEM in the DSU_MEMTYPE register */
+#define   DSU_MEMTYPE_SYSMEM_0_Val            _UINT32_(0x0)                                        /* (DSU_MEMTYPE) System memory not present on bus. This is a dedicated debug bus.  */
+#define   DSU_MEMTYPE_SYSMEM_1_Val            _UINT32_(0x1)                                        /* (DSU_MEMTYPE) System memory is also present on this bus  */
+#define DSU_MEMTYPE_SYSMEM_0                  (DSU_MEMTYPE_SYSMEM_0_Val << DSU_MEMTYPE_SYSMEM_Pos) /* (DSU_MEMTYPE) System memory not present on bus. This is a dedicated debug bus. Position */
+#define DSU_MEMTYPE_SYSMEM_1                  (DSU_MEMTYPE_SYSMEM_1_Val << DSU_MEMTYPE_SYSMEM_Pos) /* (DSU_MEMTYPE) System memory is also present on this bus Position */
+#define DSU_MEMTYPE_Msk                       _UINT32_(0x00000001)                                 /* (DSU_MEMTYPE) Register Mask  */
+
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) ( R/ 32) CoreSight Peripheral Identification 4 Register -------- */
+#define DSU_PID4_RESETVALUE                   _UINT32_(0x00)                                       /*  (DSU_PID4) CoreSight Peripheral Identification 4 Register  Reset Value */
+
+#define DSU_PID4_DES2_Pos                     _UINT32_(0)                                          /* (DSU_PID4) CoreSight JEP106 Continuation Code Position */
+#define DSU_PID4_DES2_Msk                     (_UINT32_(0xF) << DSU_PID4_DES2_Pos)                 /* (DSU_PID4) CoreSight JEP106 Continuation Code Mask */
+#define DSU_PID4_DES2(value)                  (DSU_PID4_DES2_Msk & (_UINT32_(value) << DSU_PID4_DES2_Pos)) /* Assignment of value for DES2 in the DSU_PID4 register */
+#define DSU_PID4_SIZE_Pos                     _UINT32_(4)                                          /* (DSU_PID4) CoreSight Size Position */
+#define DSU_PID4_SIZE_Msk                     (_UINT32_(0xF) << DSU_PID4_SIZE_Pos)                 /* (DSU_PID4) CoreSight Size Mask */
+#define DSU_PID4_SIZE(value)                  (DSU_PID4_SIZE_Msk & (_UINT32_(value) << DSU_PID4_SIZE_Pos)) /* Assignment of value for SIZE in the DSU_PID4 register */
+#define DSU_PID4_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_PID4) Register Mask  */
+
+
+/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) ( R/ 32) CoreSight Peripheral Identification 5 Register -------- */
+#define DSU_PID5_RESETVALUE                   _UINT32_(0x00)                                       /*  (DSU_PID5) CoreSight Peripheral Identification 5 Register  Reset Value */
+
+#define DSU_PID5_RES0_Pos                     _UINT32_(0)                                          /* (DSU_PID5) CoreSight Reserved Field Position */
+#define DSU_PID5_RES0_Msk                     (_UINT32_(0xFF) << DSU_PID5_RES0_Pos)                /* (DSU_PID5) CoreSight Reserved Field Mask */
+#define DSU_PID5_RES0(value)                  (DSU_PID5_RES0_Msk & (_UINT32_(value) << DSU_PID5_RES0_Pos)) /* Assignment of value for RES0 in the DSU_PID5 register */
+#define DSU_PID5_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_PID5) Register Mask  */
+
+
+/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) ( R/ 32) CoreSight Peripheral Identification 6 Register -------- */
+#define DSU_PID6_RESETVALUE                   _UINT32_(0x00)                                       /*  (DSU_PID6) CoreSight Peripheral Identification 6 Register  Reset Value */
+
+#define DSU_PID6_RES0_Pos                     _UINT32_(0)                                          /* (DSU_PID6) CoreSight Reserved Field Position */
+#define DSU_PID6_RES0_Msk                     (_UINT32_(0xFF) << DSU_PID6_RES0_Pos)                /* (DSU_PID6) CoreSight Reserved Field Mask */
+#define DSU_PID6_RES0(value)                  (DSU_PID6_RES0_Msk & (_UINT32_(value) << DSU_PID6_RES0_Pos)) /* Assignment of value for RES0 in the DSU_PID6 register */
+#define DSU_PID6_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_PID6) Register Mask  */
+
+
+/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) ( R/ 32) CoreSight Peripheral Identification 7 Register -------- */
+#define DSU_PID7_RESETVALUE                   _UINT32_(0x00)                                       /*  (DSU_PID7) CoreSight Peripheral Identification 7 Register  Reset Value */
+
+#define DSU_PID7_RES0_Pos                     _UINT32_(0)                                          /* (DSU_PID7) CoreSight Reserved Field Position */
+#define DSU_PID7_RES0_Msk                     (_UINT32_(0xFF) << DSU_PID7_RES0_Pos)                /* (DSU_PID7) CoreSight Reserved Field Mask */
+#define DSU_PID7_RES0(value)                  (DSU_PID7_RES0_Msk & (_UINT32_(value) << DSU_PID7_RES0_Pos)) /* Assignment of value for RES0 in the DSU_PID7 register */
+#define DSU_PID7_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_PID7) Register Mask  */
+
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) ( R/ 32) CoreSight Peripheral Identification 0 Register -------- */
+#define DSU_PID0_RESETVALUE                   _UINT32_(0xD0)                                       /*  (DSU_PID0) CoreSight Peripheral Identification 0 Register  Reset Value */
+
+#define DSU_PID0_PART0_Pos                    _UINT32_(0)                                          /* (DSU_PID0) CoreSight Part Number Bits[7:0] Position */
+#define DSU_PID0_PART0_Msk                    (_UINT32_(0xFF) << DSU_PID0_PART0_Pos)               /* (DSU_PID0) CoreSight Part Number Bits[7:0] Mask */
+#define DSU_PID0_PART0(value)                 (DSU_PID0_PART0_Msk & (_UINT32_(value) << DSU_PID0_PART0_Pos)) /* Assignment of value for PART0 in the DSU_PID0 register */
+#define DSU_PID0_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_PID0) Register Mask  */
+
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) ( R/ 32) CoreSight Peripheral Identification 1 Register -------- */
+#define DSU_PID1_RESETVALUE                   _UINT32_(0x9C)                                       /*  (DSU_PID1) CoreSight Peripheral Identification 1 Register  Reset Value */
+
+#define DSU_PID1_PART1_Pos                    _UINT32_(0)                                          /* (DSU_PID1) CoreSight Part Number Bits[11:8] Position */
+#define DSU_PID1_PART1_Msk                    (_UINT32_(0xF) << DSU_PID1_PART1_Pos)                /* (DSU_PID1) CoreSight Part Number Bits[11:8] Mask */
+#define DSU_PID1_PART1(value)                 (DSU_PID1_PART1_Msk & (_UINT32_(value) << DSU_PID1_PART1_Pos)) /* Assignment of value for PART1 in the DSU_PID1 register */
+#define DSU_PID1_DES0_Pos                     _UINT32_(4)                                          /* (DSU_PID1) CoreSight JEP106 Identification Code Bits [3:0] Position */
+#define DSU_PID1_DES0_Msk                     (_UINT32_(0xF) << DSU_PID1_DES0_Pos)                 /* (DSU_PID1) CoreSight JEP106 Identification Code Bits [3:0] Mask */
+#define DSU_PID1_DES0(value)                  (DSU_PID1_DES0_Msk & (_UINT32_(value) << DSU_PID1_DES0_Pos)) /* Assignment of value for DES0 in the DSU_PID1 register */
+#define DSU_PID1_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_PID1) Register Mask  */
+
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) ( R/ 32) CoreSight Peripheral Identification 2 Register -------- */
+#define DSU_PID2_RESETVALUE                   _UINT32_(0x0A)                                       /*  (DSU_PID2) CoreSight Peripheral Identification 2 Register  Reset Value */
+
+#define DSU_PID2_DES1_Pos                     _UINT32_(0)                                          /* (DSU_PID2) CoreSight JEP106 Identification Code Bits [6:4] Position */
+#define DSU_PID2_DES1_Msk                     (_UINT32_(0x7) << DSU_PID2_DES1_Pos)                 /* (DSU_PID2) CoreSight JEP106 Identification Code Bits [6:4] Mask */
+#define DSU_PID2_DES1(value)                  (DSU_PID2_DES1_Msk & (_UINT32_(value) << DSU_PID2_DES1_Pos)) /* Assignment of value for DES1 in the DSU_PID2 register */
+#define DSU_PID2_JEDEC_Pos                    _UINT32_(3)                                          /* (DSU_PID2) CoreSight JEDEC Assignment Position */
+#define DSU_PID2_JEDEC_Msk                    (_UINT32_(0x1) << DSU_PID2_JEDEC_Pos)                /* (DSU_PID2) CoreSight JEDEC Assignment Mask */
+#define DSU_PID2_JEDEC(value)                 (DSU_PID2_JEDEC_Msk & (_UINT32_(value) << DSU_PID2_JEDEC_Pos)) /* Assignment of value for JEDEC in the DSU_PID2 register */
+#define DSU_PID2_REVISION_Pos                 _UINT32_(4)                                          /* (DSU_PID2) CoreSight Revision Position */
+#define DSU_PID2_REVISION_Msk                 (_UINT32_(0xF) << DSU_PID2_REVISION_Pos)             /* (DSU_PID2) CoreSight Revision Mask */
+#define DSU_PID2_REVISION(value)              (DSU_PID2_REVISION_Msk & (_UINT32_(value) << DSU_PID2_REVISION_Pos)) /* Assignment of value for REVISION in the DSU_PID2 register */
+#define DSU_PID2_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_PID2) Register Mask  */
+
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) ( R/ 32) CoreSight Peripheral Identification 3 Register -------- */
+#define DSU_PID3_RESETVALUE                   _UINT32_(0x00)                                       /*  (DSU_PID3) CoreSight Peripheral Identification 3 Register  Reset Value */
+
+#define DSU_PID3_CMOD_Pos                     _UINT32_(0)                                          /* (DSU_PID3) CoreSight Custom Modifier 0 Position */
+#define DSU_PID3_CMOD_Msk                     (_UINT32_(0xF) << DSU_PID3_CMOD_Pos)                 /* (DSU_PID3) CoreSight Custom Modifier 0 Mask */
+#define DSU_PID3_CMOD(value)                  (DSU_PID3_CMOD_Msk & (_UINT32_(value) << DSU_PID3_CMOD_Pos)) /* Assignment of value for CMOD in the DSU_PID3 register */
+#define DSU_PID3_REVAND_Pos                   _UINT32_(4)                                          /* (DSU_PID3) CoreSight REVAND Position */
+#define DSU_PID3_REVAND_Msk                   (_UINT32_(0xF) << DSU_PID3_REVAND_Pos)               /* (DSU_PID3) CoreSight REVAND Mask */
+#define DSU_PID3_REVAND(value)                (DSU_PID3_REVAND_Msk & (_UINT32_(value) << DSU_PID3_REVAND_Pos)) /* Assignment of value for REVAND in the DSU_PID3 register */
+#define DSU_PID3_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_PID3) Register Mask  */
+
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) ( R/ 32) CoreSight Component Identification 0 Register -------- */
+#define DSU_CID0_RESETVALUE                   _UINT32_(0x0D)                                       /*  (DSU_CID0) CoreSight Component Identification 0 Register  Reset Value */
+
+#define DSU_CID0_PRMBL0_Pos                   _UINT32_(0)                                          /* (DSU_CID0) CoreSight Preamble 0 Position */
+#define DSU_CID0_PRMBL0_Msk                   (_UINT32_(0xFF) << DSU_CID0_PRMBL0_Pos)              /* (DSU_CID0) CoreSight Preamble 0 Mask */
+#define DSU_CID0_PRMBL0(value)                (DSU_CID0_PRMBL0_Msk & (_UINT32_(value) << DSU_CID0_PRMBL0_Pos)) /* Assignment of value for PRMBL0 in the DSU_CID0 register */
+#define DSU_CID0_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_CID0) Register Mask  */
+
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) ( R/ 32) CoreSight Component Identification 1 Register -------- */
+#define DSU_CID1_RESETVALUE                   _UINT32_(0x10)                                       /*  (DSU_CID1) CoreSight Component Identification 1 Register  Reset Value */
+
+#define DSU_CID1_PRMBL1_Pos                   _UINT32_(0)                                          /* (DSU_CID1) CoreSight Preamble 1 Position */
+#define DSU_CID1_PRMBL1_Msk                   (_UINT32_(0xF) << DSU_CID1_PRMBL1_Pos)               /* (DSU_CID1) CoreSight Preamble 1 Mask */
+#define DSU_CID1_PRMBL1(value)                (DSU_CID1_PRMBL1_Msk & (_UINT32_(value) << DSU_CID1_PRMBL1_Pos)) /* Assignment of value for PRMBL1 in the DSU_CID1 register */
+#define DSU_CID1_CCLASS_Pos                   _UINT32_(4)                                          /* (DSU_CID1) CoreSight Component Class Position */
+#define DSU_CID1_CCLASS_Msk                   (_UINT32_(0xF) << DSU_CID1_CCLASS_Pos)               /* (DSU_CID1) CoreSight Component Class Mask */
+#define DSU_CID1_CCLASS(value)                (DSU_CID1_CCLASS_Msk & (_UINT32_(value) << DSU_CID1_CCLASS_Pos)) /* Assignment of value for CCLASS in the DSU_CID1 register */
+#define DSU_CID1_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_CID1) Register Mask  */
+
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) ( R/ 32) CoreSight Component Identification 2 Register -------- */
+#define DSU_CID2_RESETVALUE                   _UINT32_(0x05)                                       /*  (DSU_CID2) CoreSight Component Identification 2 Register  Reset Value */
+
+#define DSU_CID2_PRMBL2_Pos                   _UINT32_(0)                                          /* (DSU_CID2) CoreSight Preamble 2 Position */
+#define DSU_CID2_PRMBL2_Msk                   (_UINT32_(0xFF) << DSU_CID2_PRMBL2_Pos)              /* (DSU_CID2) CoreSight Preamble 2 Mask */
+#define DSU_CID2_PRMBL2(value)                (DSU_CID2_PRMBL2_Msk & (_UINT32_(value) << DSU_CID2_PRMBL2_Pos)) /* Assignment of value for PRMBL2 in the DSU_CID2 register */
+#define DSU_CID2_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_CID2) Register Mask  */
+
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) ( R/ 32) CoreSight Component Identification 3 Register -------- */
+#define DSU_CID3_RESETVALUE                   _UINT32_(0xB1)                                       /*  (DSU_CID3) CoreSight Component Identification 3 Register  Reset Value */
+
+#define DSU_CID3_PRMBL3_Pos                   _UINT32_(0)                                          /* (DSU_CID3) CoreSight Preamble 3 Position */
+#define DSU_CID3_PRMBL3_Msk                   (_UINT32_(0xFF) << DSU_CID3_PRMBL3_Pos)              /* (DSU_CID3) CoreSight Preamble 3 Mask */
+#define DSU_CID3_PRMBL3(value)                (DSU_CID3_PRMBL3_Msk & (_UINT32_(value) << DSU_CID3_PRMBL3_Pos)) /* Assignment of value for PRMBL3 in the DSU_CID3 register */
+#define DSU_CID3_Msk                          _UINT32_(0x000000FF)                                 /* (DSU_CID3) Register Mask  */
+
+
+/* DSU register offsets definitions */
+#define DSU_CTRLA_REG_OFST             _UINT32_(0x00)      /* (DSU_CTRLA) Control A REGISTER Offset */
+#define DSU_CTRLB_REG_OFST             _UINT32_(0x04)      /* (DSU_CTRLB) Control B REGISTER Offset */
+#define DSU_CTRLC_REG_OFST             _UINT32_(0x100)     /* (DSU_CTRLC) Control C REGISTER Offset */
+#define DSU_STATUSA_REG_OFST           _UINT32_(0x104)     /* (DSU_STATUSA) Status A REGISTER Offset */
+#define DSU_STATUSB_REG_OFST           _UINT32_(0x108)     /* (DSU_STATUSB) Status B REGISTER Offset */
+#define DSU_BCC_REG_OFST               _UINT32_(0x110)     /* (DSU_BCC) Boot ROM Channel n REGISTER Offset */
+#define DSU_BCC0_REG_OFST              _UINT32_(0x110)     /* (DSU_BCC0) Boot ROM Channel n REGISTER Offset */
+#define DSU_BCC1_REG_OFST              _UINT32_(0x114)     /* (DSU_BCC1) Boot ROM Channel n REGISTER Offset */
+#define DSU_DCC_REG_OFST               _UINT32_(0x118)     /* (DSU_DCC) Debug Communication Channel n REGISTER Offset */
+#define DSU_DCC0_REG_OFST              _UINT32_(0x118)     /* (DSU_DCC0) Debug Communication Channel n REGISTER Offset */
+#define DSU_DCC1_REG_OFST              _UINT32_(0x11C)     /* (DSU_DCC1) Debug Communication Channel n REGISTER Offset */
+#define DSU_DID_REG_OFST               _UINT32_(0x120)     /* (DSU_DID) Device Identification Register Offset */
+#define DSU_DAL_REG_OFST               _UINT32_(0x124)     /* (DSU_DAL) Debugger Access Level REGISTER Offset */
+#define DSU_ENTRY0_REG_OFST            _UINT32_(0x1000)    /* (DSU_ENTRY0) CoreSight ROM Table Entry N Register Offset */
+#define DSU_ENTRY1_REG_OFST            _UINT32_(0x1004)    /* (DSU_ENTRY1) CoreSight ROM Table Entry N Register Offset */
+#define DSU_ENTRY2_REG_OFST            _UINT32_(0x1008)    /* (DSU_ENTRY2) CoreSight ROM Table Entry N Register Offset */
+#define DSU_ENTRY3_REG_OFST            _UINT32_(0x100C)    /* (DSU_ENTRY3) CoreSight ROM Table Entry N Register Offset */
+#define DSU_ENTRY4_REG_OFST            _UINT32_(0x1010)    /* (DSU_ENTRY4) CoreSight ROM Table Entry 4 Register Offset */
+#define DSU_ENTRY5_REG_OFST            _UINT32_(0x1014)    /* (DSU_ENTRY5) CoreSight ROM Table Entry 5 Register Offset */
+#define DSU_ENTRY6_REG_OFST            _UINT32_(0x1018)    /* (DSU_ENTRY6) CoreSight ROM Table Entry 6 Register Offset */
+#define DSU_ENTRY7_REG_OFST            _UINT32_(0x101C)    /* (DSU_ENTRY7) CoreSight ROM Table Entry 7 Register Offset */
+#define DSU_MEMTYPE_REG_OFST           _UINT32_(0x1FCC)    /* (DSU_MEMTYPE) CoreSight ROM Table Memory Type Register Offset */
+#define DSU_PID4_REG_OFST              _UINT32_(0x1FD0)    /* (DSU_PID4) CoreSight Peripheral Identification 4 Register Offset */
+#define DSU_PID5_REG_OFST              _UINT32_(0x1FD4)    /* (DSU_PID5) CoreSight Peripheral Identification 5 Register Offset */
+#define DSU_PID6_REG_OFST              _UINT32_(0x1FD8)    /* (DSU_PID6) CoreSight Peripheral Identification 6 Register Offset */
+#define DSU_PID7_REG_OFST              _UINT32_(0x1FDC)    /* (DSU_PID7) CoreSight Peripheral Identification 7 Register Offset */
+#define DSU_PID0_REG_OFST              _UINT32_(0x1FE0)    /* (DSU_PID0) CoreSight Peripheral Identification 0 Register Offset */
+#define DSU_PID1_REG_OFST              _UINT32_(0x1FE4)    /* (DSU_PID1) CoreSight Peripheral Identification 1 Register Offset */
+#define DSU_PID2_REG_OFST              _UINT32_(0x1FE8)    /* (DSU_PID2) CoreSight Peripheral Identification 2 Register Offset */
+#define DSU_PID3_REG_OFST              _UINT32_(0x1FEC)    /* (DSU_PID3) CoreSight Peripheral Identification 3 Register Offset */
+#define DSU_CID0_REG_OFST              _UINT32_(0x1FF0)    /* (DSU_CID0) CoreSight Component Identification 0 Register Offset */
+#define DSU_CID1_REG_OFST              _UINT32_(0x1FF4)    /* (DSU_CID1) CoreSight Component Identification 1 Register Offset */
+#define DSU_CID2_REG_OFST              _UINT32_(0x1FF8)    /* (DSU_CID2) CoreSight Component Identification 2 Register Offset */
+#define DSU_CID3_REG_OFST              _UINT32_(0x1FFC)    /* (DSU_CID3) CoreSight Component Identification 3 Register Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* DSU register API structure */
+typedef struct
+{  /* Polaris Device Services Unit Macro DOS */
+  __IO  uint32_t                       DSU_CTRLA;          /* Offset: 0x00 (R/W  32) Control A REGISTER */
+  __IO  uint32_t                       DSU_CTRLB;          /* Offset: 0x04 (R/W  32) Control B REGISTER */
+  __I   uint8_t                        Reserved1[0xF8];
+  __IO  uint32_t                       DSU_CTRLC;          /* Offset: 0x100 (R/W  32) Control C REGISTER */
+  __IO  uint32_t                       DSU_STATUSA;        /* Offset: 0x104 (R/W  32) Status A REGISTER */
+  __I   uint32_t                       DSU_STATUSB;        /* Offset: 0x108 (R/   32) Status B REGISTER */
+  __I   uint8_t                        Reserved2[0x04];
+  __IO  uint32_t                       DSU_BCC[2];         /* Offset: 0x110 (R/W  32) Boot ROM Channel n REGISTER */
+  __IO  uint32_t                       DSU_DCC[2];         /* Offset: 0x118 (R/W  32) Debug Communication Channel n REGISTER */
+  __IO  uint32_t                       DSU_DID;            /* Offset: 0x120 (R/W  32) Device Identification Register */
+  __I   uint32_t                       DSU_DAL;            /* Offset: 0x124 (R/   32) Debugger Access Level REGISTER */
+  __I   uint8_t                        Reserved3[0xED8];
+  __I   uint32_t                       DSU_ENTRY0;         /* Offset: 0x1000 (R/   32) CoreSight ROM Table Entry N Register */
+  __I   uint32_t                       DSU_ENTRY1;         /* Offset: 0x1004 (R/   32) CoreSight ROM Table Entry N Register */
+  __I   uint32_t                       DSU_ENTRY2;         /* Offset: 0x1008 (R/   32) CoreSight ROM Table Entry N Register */
+  __I   uint32_t                       DSU_ENTRY3;         /* Offset: 0x100C (R/   32) CoreSight ROM Table Entry N Register */
+  __I   uint32_t                       DSU_ENTRY4;         /* Offset: 0x1010 (R/   32) CoreSight ROM Table Entry 4 Register */
+  __I   uint32_t                       DSU_ENTRY5;         /* Offset: 0x1014 (R/   32) CoreSight ROM Table Entry 5 Register */
+  __I   uint32_t                       DSU_ENTRY6;         /* Offset: 0x1018 (R/   32) CoreSight ROM Table Entry 6 Register */
+  __I   uint32_t                       DSU_ENTRY7;         /* Offset: 0x101C (R/   32) CoreSight ROM Table Entry 7 Register */
+  __I   uint8_t                        Reserved4[0xFAC];
+  __I   uint32_t                       DSU_MEMTYPE;        /* Offset: 0x1FCC (R/   32) CoreSight ROM Table Memory Type Register */
+  __I   uint32_t                       DSU_PID4;           /* Offset: 0x1FD0 (R/   32) CoreSight Peripheral Identification 4 Register */
+  __I   uint32_t                       DSU_PID5;           /* Offset: 0x1FD4 (R/   32) CoreSight Peripheral Identification 5 Register */
+  __I   uint32_t                       DSU_PID6;           /* Offset: 0x1FD8 (R/   32) CoreSight Peripheral Identification 6 Register */
+  __I   uint32_t                       DSU_PID7;           /* Offset: 0x1FDC (R/   32) CoreSight Peripheral Identification 7 Register */
+  __I   uint32_t                       DSU_PID0;           /* Offset: 0x1FE0 (R/   32) CoreSight Peripheral Identification 0 Register */
+  __I   uint32_t                       DSU_PID1;           /* Offset: 0x1FE4 (R/   32) CoreSight Peripheral Identification 1 Register */
+  __I   uint32_t                       DSU_PID2;           /* Offset: 0x1FE8 (R/   32) CoreSight Peripheral Identification 2 Register */
+  __I   uint32_t                       DSU_PID3;           /* Offset: 0x1FEC (R/   32) CoreSight Peripheral Identification 3 Register */
+  __I   uint32_t                       DSU_CID0;           /* Offset: 0x1FF0 (R/   32) CoreSight Component Identification 0 Register */
+  __I   uint32_t                       DSU_CID1;           /* Offset: 0x1FF4 (R/   32) CoreSight Component Identification 1 Register */
+  __I   uint32_t                       DSU_CID2;           /* Offset: 0x1FF8 (R/   32) CoreSight Component Identification 2 Register */
+  __I   uint32_t                       DSU_CID3;           /* Offset: 0x1FFC (R/   32) CoreSight Component Identification 3 Register */
+} dsu_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_DSU_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/eic.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/eic.h
new file mode 100644
index 00000000..d1f06d71
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/eic.h
@@ -0,0 +1,459 @@
+/*
+ * Component description for EIC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_EIC_COMPONENT_H_
+#define _PIC32CMGC00_EIC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR EIC                       */
+/* ************************************************************************** */
+
+/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control A -------- */
+#define EIC_CTRLA_RESETVALUE                  _UINT8_(0x00)                                        /*  (EIC_CTRLA) Control A  Reset Value */
+
+#define EIC_CTRLA_SWRST_Pos                   _UINT8_(0)                                           /* (EIC_CTRLA) Software Reset Position */
+#define EIC_CTRLA_SWRST_Msk                   (_UINT8_(0x1) << EIC_CTRLA_SWRST_Pos)                /* (EIC_CTRLA) Software Reset Mask */
+#define EIC_CTRLA_SWRST(value)                (EIC_CTRLA_SWRST_Msk & (_UINT8_(value) << EIC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the EIC_CTRLA register */
+#define EIC_CTRLA_ENABLE_Pos                  _UINT8_(1)                                           /* (EIC_CTRLA) Enable Position */
+#define EIC_CTRLA_ENABLE_Msk                  (_UINT8_(0x1) << EIC_CTRLA_ENABLE_Pos)               /* (EIC_CTRLA) Enable Mask */
+#define EIC_CTRLA_ENABLE(value)               (EIC_CTRLA_ENABLE_Msk & (_UINT8_(value) << EIC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the EIC_CTRLA register */
+#define EIC_CTRLA_CKSEL_Pos                   _UINT8_(4)                                           /* (EIC_CTRLA) Clock Selection Position */
+#define EIC_CTRLA_CKSEL_Msk                   (_UINT8_(0x1) << EIC_CTRLA_CKSEL_Pos)                /* (EIC_CTRLA) Clock Selection Mask */
+#define EIC_CTRLA_CKSEL(value)                (EIC_CTRLA_CKSEL_Msk & (_UINT8_(value) << EIC_CTRLA_CKSEL_Pos)) /* Assignment of value for CKSEL in the EIC_CTRLA register */
+#define   EIC_CTRLA_CKSEL_CLK_GCLK_Val        _UINT8_(0x0)                                         /* (EIC_CTRLA) Clocked by GCLK  */
+#define   EIC_CTRLA_CKSEL_CLK_ULP32K_Val      _UINT8_(0x1)                                         /* (EIC_CTRLA) Clocked by ULP32K  */
+#define EIC_CTRLA_CKSEL_CLK_GCLK              (EIC_CTRLA_CKSEL_CLK_GCLK_Val << EIC_CTRLA_CKSEL_Pos) /* (EIC_CTRLA) Clocked by GCLK Position */
+#define EIC_CTRLA_CKSEL_CLK_ULP32K            (EIC_CTRLA_CKSEL_CLK_ULP32K_Val << EIC_CTRLA_CKSEL_Pos) /* (EIC_CTRLA) Clocked by ULP32K Position */
+#define EIC_CTRLA_Msk                         _UINT8_(0x13)                                        /* (EIC_CTRLA) Register Mask  */
+
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) Non-Maskable Interrupt Control -------- */
+#define EIC_NMICTRL_RESETVALUE                _UINT8_(0x00)                                        /*  (EIC_NMICTRL) Non-Maskable Interrupt Control  Reset Value */
+
+#define EIC_NMICTRL_NMISENSE_Pos              _UINT8_(0)                                           /* (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration Position */
+#define EIC_NMICTRL_NMISENSE_Msk              (_UINT8_(0x7) << EIC_NMICTRL_NMISENSE_Pos)           /* (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration Mask */
+#define EIC_NMICTRL_NMISENSE(value)           (EIC_NMICTRL_NMISENSE_Msk & (_UINT8_(value) << EIC_NMICTRL_NMISENSE_Pos)) /* Assignment of value for NMISENSE in the EIC_NMICTRL register */
+#define   EIC_NMICTRL_NMISENSE_NONE_Val       _UINT8_(0x0)                                         /* (EIC_NMICTRL) No detection  */
+#define   EIC_NMICTRL_NMISENSE_RISE_Val       _UINT8_(0x1)                                         /* (EIC_NMICTRL) Rising-edge detection  */
+#define   EIC_NMICTRL_NMISENSE_FALL_Val       _UINT8_(0x2)                                         /* (EIC_NMICTRL) Falling-edge detection  */
+#define   EIC_NMICTRL_NMISENSE_BOTH_Val       _UINT8_(0x3)                                         /* (EIC_NMICTRL) Both-edges detection  */
+#define   EIC_NMICTRL_NMISENSE_HIGH_Val       _UINT8_(0x4)                                         /* (EIC_NMICTRL) High-level detection  */
+#define   EIC_NMICTRL_NMISENSE_LOW_Val        _UINT8_(0x5)                                         /* (EIC_NMICTRL) Low-level detection  */
+#define EIC_NMICTRL_NMISENSE_NONE             (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) No detection Position */
+#define EIC_NMICTRL_NMISENSE_RISE             (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) Rising-edge detection Position */
+#define EIC_NMICTRL_NMISENSE_FALL             (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) Falling-edge detection Position */
+#define EIC_NMICTRL_NMISENSE_BOTH             (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) Both-edges detection Position */
+#define EIC_NMICTRL_NMISENSE_HIGH             (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) High-level detection Position */
+#define EIC_NMICTRL_NMISENSE_LOW              (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) /* (EIC_NMICTRL) Low-level detection Position */
+#define EIC_NMICTRL_NMIFILTEN_Pos             _UINT8_(3)                                           /* (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable Position */
+#define EIC_NMICTRL_NMIFILTEN_Msk             (_UINT8_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)          /* (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable Mask */
+#define EIC_NMICTRL_NMIFILTEN(value)          (EIC_NMICTRL_NMIFILTEN_Msk & (_UINT8_(value) << EIC_NMICTRL_NMIFILTEN_Pos)) /* Assignment of value for NMIFILTEN in the EIC_NMICTRL register */
+#define EIC_NMICTRL_NMIASYNCH_Pos             _UINT8_(4)                                           /* (EIC_NMICTRL) Asynchronous Edge Detection Mode Position */
+#define EIC_NMICTRL_NMIASYNCH_Msk             (_UINT8_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)          /* (EIC_NMICTRL) Asynchronous Edge Detection Mode Mask */
+#define EIC_NMICTRL_NMIASYNCH(value)          (EIC_NMICTRL_NMIASYNCH_Msk & (_UINT8_(value) << EIC_NMICTRL_NMIASYNCH_Pos)) /* Assignment of value for NMIASYNCH in the EIC_NMICTRL register */
+#define   EIC_NMICTRL_NMIASYNCH_SYNC_Val      _UINT8_(0x0)                                         /* (EIC_NMICTRL) Edge detection is clock synchronously operated  */
+#define   EIC_NMICTRL_NMIASYNCH_ASYNC_Val     _UINT8_(0x1)                                         /* (EIC_NMICTRL) Edge detection is clock asynchronously operated  */
+#define EIC_NMICTRL_NMIASYNCH_SYNC            (EIC_NMICTRL_NMIASYNCH_SYNC_Val << EIC_NMICTRL_NMIASYNCH_Pos) /* (EIC_NMICTRL) Edge detection is clock synchronously operated Position */
+#define EIC_NMICTRL_NMIASYNCH_ASYNC           (EIC_NMICTRL_NMIASYNCH_ASYNC_Val << EIC_NMICTRL_NMIASYNCH_Pos) /* (EIC_NMICTRL) Edge detection is clock asynchronously operated Position */
+#define EIC_NMICTRL_Msk                       _UINT8_(0x1F)                                        /* (EIC_NMICTRL) Register Mask  */
+
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */
+#define EIC_NMIFLAG_RESETVALUE                _UINT16_(0x00)                                       /*  (EIC_NMIFLAG) Non-Maskable Interrupt Flag Status and Clear  Reset Value */
+
+#define EIC_NMIFLAG_NMI_Pos                   _UINT16_(0)                                          /* (EIC_NMIFLAG) Non-Maskable Interrupt Position */
+#define EIC_NMIFLAG_NMI_Msk                   (_UINT16_(0x1) << EIC_NMIFLAG_NMI_Pos)               /* (EIC_NMIFLAG) Non-Maskable Interrupt Mask */
+#define EIC_NMIFLAG_NMI(value)                (EIC_NMIFLAG_NMI_Msk & (_UINT16_(value) << EIC_NMIFLAG_NMI_Pos)) /* Assignment of value for NMI in the EIC_NMIFLAG register */
+#define EIC_NMIFLAG_Msk                       _UINT16_(0x0001)                                     /* (EIC_NMIFLAG) Register Mask  */
+
+
+/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) ( R/ 32) Synchronization Busy -------- */
+#define EIC_SYNCBUSY_RESETVALUE               _UINT32_(0x00)                                       /*  (EIC_SYNCBUSY) Synchronization Busy  Reset Value */
+
+#define EIC_SYNCBUSY_SWRST_Pos                _UINT32_(0)                                          /* (EIC_SYNCBUSY) Software Reset Synchronization Busy Status Position */
+#define EIC_SYNCBUSY_SWRST_Msk                (_UINT32_(0x1) << EIC_SYNCBUSY_SWRST_Pos)            /* (EIC_SYNCBUSY) Software Reset Synchronization Busy Status Mask */
+#define EIC_SYNCBUSY_SWRST(value)             (EIC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << EIC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the EIC_SYNCBUSY register */
+#define EIC_SYNCBUSY_ENABLE_Pos               _UINT32_(1)                                          /* (EIC_SYNCBUSY) Enable Synchronization Busy Status Position */
+#define EIC_SYNCBUSY_ENABLE_Msk               (_UINT32_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)           /* (EIC_SYNCBUSY) Enable Synchronization Busy Status Mask */
+#define EIC_SYNCBUSY_ENABLE(value)            (EIC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << EIC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the EIC_SYNCBUSY register */
+#define EIC_SYNCBUSY_Msk                      _UINT32_(0x00000003)                                 /* (EIC_SYNCBUSY) Register Mask  */
+
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
+#define EIC_EVCTRL_RESETVALUE                 _UINT32_(0x00)                                       /*  (EIC_EVCTRL) Event Control  Reset Value */
+
+#define EIC_EVCTRL_EXTINTEO_Pos               _UINT32_(0)                                          /* (EIC_EVCTRL) External Interrupt Event Output Enable Position */
+#define EIC_EVCTRL_EXTINTEO_Msk               (_UINT32_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)        /* (EIC_EVCTRL) External Interrupt Event Output Enable Mask */
+#define EIC_EVCTRL_EXTINTEO(value)            (EIC_EVCTRL_EXTINTEO_Msk & (_UINT32_(value) << EIC_EVCTRL_EXTINTEO_Pos)) /* Assignment of value for EXTINTEO in the EIC_EVCTRL register */
+#define EIC_EVCTRL_Msk                        _UINT32_(0x0000FFFF)                                 /* (EIC_EVCTRL) Register Mask  */
+
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
+#define EIC_INTENCLR_RESETVALUE               _UINT32_(0x00)                                       /*  (EIC_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define EIC_INTENCLR_EXTINT_Pos               _UINT32_(0)                                          /* (EIC_INTENCLR) External Interrupt Enable Position */
+#define EIC_INTENCLR_EXTINT_Msk               (_UINT32_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)        /* (EIC_INTENCLR) External Interrupt Enable Mask */
+#define EIC_INTENCLR_EXTINT(value)            (EIC_INTENCLR_EXTINT_Msk & (_UINT32_(value) << EIC_INTENCLR_EXTINT_Pos)) /* Assignment of value for EXTINT in the EIC_INTENCLR register */
+#define EIC_INTENCLR_NSCHK_Pos                _UINT32_(31)                                         /* (EIC_INTENCLR) Non-secure Check Interrupt Enable Position */
+#define EIC_INTENCLR_NSCHK_Msk                (_UINT32_(0x1) << EIC_INTENCLR_NSCHK_Pos)            /* (EIC_INTENCLR) Non-secure Check Interrupt Enable Mask */
+#define EIC_INTENCLR_NSCHK(value)             (EIC_INTENCLR_NSCHK_Msk & (_UINT32_(value) << EIC_INTENCLR_NSCHK_Pos)) /* Assignment of value for NSCHK in the EIC_INTENCLR register */
+#define EIC_INTENCLR_Msk                      _UINT32_(0x8000FFFF)                                 /* (EIC_INTENCLR) Register Mask  */
+
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
+#define EIC_INTENSET_RESETVALUE               _UINT32_(0x00)                                       /*  (EIC_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define EIC_INTENSET_EXTINT_Pos               _UINT32_(0)                                          /* (EIC_INTENSET) External Interrupt Enable Position */
+#define EIC_INTENSET_EXTINT_Msk               (_UINT32_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)        /* (EIC_INTENSET) External Interrupt Enable Mask */
+#define EIC_INTENSET_EXTINT(value)            (EIC_INTENSET_EXTINT_Msk & (_UINT32_(value) << EIC_INTENSET_EXTINT_Pos)) /* Assignment of value for EXTINT in the EIC_INTENSET register */
+#define EIC_INTENSET_NSCHK_Pos                _UINT32_(31)                                         /* (EIC_INTENSET) Non-secure Check Interrupt Enable Position */
+#define EIC_INTENSET_NSCHK_Msk                (_UINT32_(0x1) << EIC_INTENSET_NSCHK_Pos)            /* (EIC_INTENSET) Non-secure Check Interrupt Enable Mask */
+#define EIC_INTENSET_NSCHK(value)             (EIC_INTENSET_NSCHK_Msk & (_UINT32_(value) << EIC_INTENSET_NSCHK_Pos)) /* Assignment of value for NSCHK in the EIC_INTENSET register */
+#define EIC_INTENSET_Msk                      _UINT32_(0x8000FFFF)                                 /* (EIC_INTENSET) Register Mask  */
+
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
+#define EIC_INTFLAG_RESETVALUE                _UINT32_(0x00)                                       /*  (EIC_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define EIC_INTFLAG_EXTINT_Pos                _UINT32_(0)                                          /* (EIC_INTFLAG) External Interrupt Position */
+#define EIC_INTFLAG_EXTINT_Msk                (_UINT32_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)         /* (EIC_INTFLAG) External Interrupt Mask */
+#define EIC_INTFLAG_EXTINT(value)             (EIC_INTFLAG_EXTINT_Msk & (_UINT32_(value) << EIC_INTFLAG_EXTINT_Pos)) /* Assignment of value for EXTINT in the EIC_INTFLAG register */
+#define EIC_INTFLAG_NSCHK_Pos                 _UINT32_(31)                                         /* (EIC_INTFLAG) Non-secure Check Interrupt Position */
+#define EIC_INTFLAG_NSCHK_Msk                 (_UINT32_(0x1) << EIC_INTFLAG_NSCHK_Pos)             /* (EIC_INTFLAG) Non-secure Check Interrupt Mask */
+#define EIC_INTFLAG_NSCHK(value)              (EIC_INTFLAG_NSCHK_Msk & (_UINT32_(value) << EIC_INTFLAG_NSCHK_Pos)) /* Assignment of value for NSCHK in the EIC_INTFLAG register */
+#define EIC_INTFLAG_Msk                       _UINT32_(0x8000FFFF)                                 /* (EIC_INTFLAG) Register Mask  */
+
+
+/* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */
+#define EIC_ASYNCH_RESETVALUE                 _UINT32_(0x00)                                       /*  (EIC_ASYNCH) External Interrupt Asynchronous Mode  Reset Value */
+
+#define EIC_ASYNCH_ASYNCH_Pos                 _UINT32_(0)                                          /* (EIC_ASYNCH) Asynchronous Edge Detection Mode Position */
+#define EIC_ASYNCH_ASYNCH_Msk                 (_UINT32_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)          /* (EIC_ASYNCH) Asynchronous Edge Detection Mode Mask */
+#define EIC_ASYNCH_ASYNCH(value)              (EIC_ASYNCH_ASYNCH_Msk & (_UINT32_(value) << EIC_ASYNCH_ASYNCH_Pos)) /* Assignment of value for ASYNCH in the EIC_ASYNCH register */
+#define   EIC_ASYNCH_ASYNCH_SYNC_Val          _UINT32_(0x0)                                        /* (EIC_ASYNCH) EIC_EXTINTx edge detection is synchronously operated  */
+#define   EIC_ASYNCH_ASYNCH_ASYNC_Val         _UINT32_(0x1)                                        /* (EIC_ASYNCH) EIC_EXTINTx edge detection is asynchronously operated  */
+#define EIC_ASYNCH_ASYNCH_SYNC                (EIC_ASYNCH_ASYNCH_SYNC_Val << EIC_ASYNCH_ASYNCH_Pos) /* (EIC_ASYNCH) EIC_EXTINTx edge detection is synchronously operated Position */
+#define EIC_ASYNCH_ASYNCH_ASYNC               (EIC_ASYNCH_ASYNCH_ASYNC_Val << EIC_ASYNCH_ASYNCH_Pos) /* (EIC_ASYNCH) EIC_EXTINTx edge detection is asynchronously operated Position */
+#define EIC_ASYNCH_Msk                        _UINT32_(0x0000FFFF)                                 /* (EIC_ASYNCH) Register Mask  */
+
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */
+#define EIC_CONFIG_RESETVALUE                 _UINT32_(0x00)                                       /*  (EIC_CONFIG) External Interrupt Sense Configuration  Reset Value */
+
+#define EIC_CONFIG_SENSE0_Pos                 _UINT32_(0)                                          /* (EIC_CONFIG) Input Sense Configuration 0 Position */
+#define EIC_CONFIG_SENSE0_Msk                 (_UINT32_(0x7) << EIC_CONFIG_SENSE0_Pos)             /* (EIC_CONFIG) Input Sense Configuration 0 Mask */
+#define EIC_CONFIG_SENSE0(value)              (EIC_CONFIG_SENSE0_Msk & (_UINT32_(value) << EIC_CONFIG_SENSE0_Pos)) /* Assignment of value for SENSE0 in the EIC_CONFIG register */
+#define   EIC_CONFIG_SENSE0_NONE_Val          _UINT32_(0x0)                                        /* (EIC_CONFIG) No detection  */
+#define   EIC_CONFIG_SENSE0_RISE_Val          _UINT32_(0x1)                                        /* (EIC_CONFIG) Rising edge detection  */
+#define   EIC_CONFIG_SENSE0_FALL_Val          _UINT32_(0x2)                                        /* (EIC_CONFIG) Falling edge detection  */
+#define   EIC_CONFIG_SENSE0_BOTH_Val          _UINT32_(0x3)                                        /* (EIC_CONFIG) Both edges detection  */
+#define   EIC_CONFIG_SENSE0_HIGH_Val          _UINT32_(0x4)                                        /* (EIC_CONFIG) High level detection  */
+#define   EIC_CONFIG_SENSE0_LOW_Val           _UINT32_(0x5)                                        /* (EIC_CONFIG) Low level detection  */
+#define EIC_CONFIG_SENSE0_NONE                (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos) /* (EIC_CONFIG) No detection Position */
+#define EIC_CONFIG_SENSE0_RISE                (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos) /* (EIC_CONFIG) Rising edge detection Position */
+#define EIC_CONFIG_SENSE0_FALL                (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos) /* (EIC_CONFIG) Falling edge detection Position */
+#define EIC_CONFIG_SENSE0_BOTH                (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos) /* (EIC_CONFIG) Both edges detection Position */
+#define EIC_CONFIG_SENSE0_HIGH                (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos) /* (EIC_CONFIG) High level detection Position */
+#define EIC_CONFIG_SENSE0_LOW                 (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos) /* (EIC_CONFIG) Low level detection Position */
+#define EIC_CONFIG_FILTEN0_Pos                _UINT32_(3)                                          /* (EIC_CONFIG) Filter Enable 0 Position */
+#define EIC_CONFIG_FILTEN0_Msk                (_UINT32_(0x1) << EIC_CONFIG_FILTEN0_Pos)            /* (EIC_CONFIG) Filter Enable 0 Mask */
+#define EIC_CONFIG_FILTEN0(value)             (EIC_CONFIG_FILTEN0_Msk & (_UINT32_(value) << EIC_CONFIG_FILTEN0_Pos)) /* Assignment of value for FILTEN0 in the EIC_CONFIG register */
+#define EIC_CONFIG_SENSE1_Pos                 _UINT32_(4)                                          /* (EIC_CONFIG) Input Sense Configuration 1 Position */
+#define EIC_CONFIG_SENSE1_Msk                 (_UINT32_(0x7) << EIC_CONFIG_SENSE1_Pos)             /* (EIC_CONFIG) Input Sense Configuration 1 Mask */
+#define EIC_CONFIG_SENSE1(value)              (EIC_CONFIG_SENSE1_Msk & (_UINT32_(value) << EIC_CONFIG_SENSE1_Pos)) /* Assignment of value for SENSE1 in the EIC_CONFIG register */
+#define   EIC_CONFIG_SENSE1_NONE_Val          _UINT32_(0x0)                                        /* (EIC_CONFIG) No detection  */
+#define   EIC_CONFIG_SENSE1_RISE_Val          _UINT32_(0x1)                                        /* (EIC_CONFIG) Rising edge detection  */
+#define   EIC_CONFIG_SENSE1_FALL_Val          _UINT32_(0x2)                                        /* (EIC_CONFIG) Falling edge detection  */
+#define   EIC_CONFIG_SENSE1_BOTH_Val          _UINT32_(0x3)                                        /* (EIC_CONFIG) Both edges detection  */
+#define   EIC_CONFIG_SENSE1_HIGH_Val          _UINT32_(0x4)                                        /* (EIC_CONFIG) High level detection  */
+#define   EIC_CONFIG_SENSE1_LOW_Val           _UINT32_(0x5)                                        /* (EIC_CONFIG) Low level detection  */
+#define EIC_CONFIG_SENSE1_NONE                (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos) /* (EIC_CONFIG) No detection Position */
+#define EIC_CONFIG_SENSE1_RISE                (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos) /* (EIC_CONFIG) Rising edge detection Position */
+#define EIC_CONFIG_SENSE1_FALL                (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos) /* (EIC_CONFIG) Falling edge detection Position */
+#define EIC_CONFIG_SENSE1_BOTH                (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos) /* (EIC_CONFIG) Both edges detection Position */
+#define EIC_CONFIG_SENSE1_HIGH                (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos) /* (EIC_CONFIG) High level detection Position */
+#define EIC_CONFIG_SENSE1_LOW                 (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos) /* (EIC_CONFIG) Low level detection Position */
+#define EIC_CONFIG_FILTEN1_Pos                _UINT32_(7)                                          /* (EIC_CONFIG) Filter Enable 1 Position */
+#define EIC_CONFIG_FILTEN1_Msk                (_UINT32_(0x1) << EIC_CONFIG_FILTEN1_Pos)            /* (EIC_CONFIG) Filter Enable 1 Mask */
+#define EIC_CONFIG_FILTEN1(value)             (EIC_CONFIG_FILTEN1_Msk & (_UINT32_(value) << EIC_CONFIG_FILTEN1_Pos)) /* Assignment of value for FILTEN1 in the EIC_CONFIG register */
+#define EIC_CONFIG_SENSE2_Pos                 _UINT32_(8)                                          /* (EIC_CONFIG) Input Sense Configuration 2 Position */
+#define EIC_CONFIG_SENSE2_Msk                 (_UINT32_(0x7) << EIC_CONFIG_SENSE2_Pos)             /* (EIC_CONFIG) Input Sense Configuration 2 Mask */
+#define EIC_CONFIG_SENSE2(value)              (EIC_CONFIG_SENSE2_Msk & (_UINT32_(value) << EIC_CONFIG_SENSE2_Pos)) /* Assignment of value for SENSE2 in the EIC_CONFIG register */
+#define   EIC_CONFIG_SENSE2_NONE_Val          _UINT32_(0x0)                                        /* (EIC_CONFIG) No detection  */
+#define   EIC_CONFIG_SENSE2_RISE_Val          _UINT32_(0x1)                                        /* (EIC_CONFIG) Rising edge detection  */
+#define   EIC_CONFIG_SENSE2_FALL_Val          _UINT32_(0x2)                                        /* (EIC_CONFIG) Falling edge detection  */
+#define   EIC_CONFIG_SENSE2_BOTH_Val          _UINT32_(0x3)                                        /* (EIC_CONFIG) Both edges detection  */
+#define   EIC_CONFIG_SENSE2_HIGH_Val          _UINT32_(0x4)                                        /* (EIC_CONFIG) High level detection  */
+#define   EIC_CONFIG_SENSE2_LOW_Val           _UINT32_(0x5)                                        /* (EIC_CONFIG) Low level detection  */
+#define EIC_CONFIG_SENSE2_NONE                (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos) /* (EIC_CONFIG) No detection Position */
+#define EIC_CONFIG_SENSE2_RISE                (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos) /* (EIC_CONFIG) Rising edge detection Position */
+#define EIC_CONFIG_SENSE2_FALL                (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos) /* (EIC_CONFIG) Falling edge detection Position */
+#define EIC_CONFIG_SENSE2_BOTH                (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos) /* (EIC_CONFIG) Both edges detection Position */
+#define EIC_CONFIG_SENSE2_HIGH                (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos) /* (EIC_CONFIG) High level detection Position */
+#define EIC_CONFIG_SENSE2_LOW                 (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos) /* (EIC_CONFIG) Low level detection Position */
+#define EIC_CONFIG_FILTEN2_Pos                _UINT32_(11)                                         /* (EIC_CONFIG) Filter Enable 2 Position */
+#define EIC_CONFIG_FILTEN2_Msk                (_UINT32_(0x1) << EIC_CONFIG_FILTEN2_Pos)            /* (EIC_CONFIG) Filter Enable 2 Mask */
+#define EIC_CONFIG_FILTEN2(value)             (EIC_CONFIG_FILTEN2_Msk & (_UINT32_(value) << EIC_CONFIG_FILTEN2_Pos)) /* Assignment of value for FILTEN2 in the EIC_CONFIG register */
+#define EIC_CONFIG_SENSE3_Pos                 _UINT32_(12)                                         /* (EIC_CONFIG) Input Sense Configuration 3 Position */
+#define EIC_CONFIG_SENSE3_Msk                 (_UINT32_(0x7) << EIC_CONFIG_SENSE3_Pos)             /* (EIC_CONFIG) Input Sense Configuration 3 Mask */
+#define EIC_CONFIG_SENSE3(value)              (EIC_CONFIG_SENSE3_Msk & (_UINT32_(value) << EIC_CONFIG_SENSE3_Pos)) /* Assignment of value for SENSE3 in the EIC_CONFIG register */
+#define   EIC_CONFIG_SENSE3_NONE_Val          _UINT32_(0x0)                                        /* (EIC_CONFIG) No detection  */
+#define   EIC_CONFIG_SENSE3_RISE_Val          _UINT32_(0x1)                                        /* (EIC_CONFIG) Rising edge detection  */
+#define   EIC_CONFIG_SENSE3_FALL_Val          _UINT32_(0x2)                                        /* (EIC_CONFIG) Falling edge detection  */
+#define   EIC_CONFIG_SENSE3_BOTH_Val          _UINT32_(0x3)                                        /* (EIC_CONFIG) Both edges detection  */
+#define   EIC_CONFIG_SENSE3_HIGH_Val          _UINT32_(0x4)                                        /* (EIC_CONFIG) High level detection  */
+#define   EIC_CONFIG_SENSE3_LOW_Val           _UINT32_(0x5)                                        /* (EIC_CONFIG) Low level detection  */
+#define EIC_CONFIG_SENSE3_NONE                (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos) /* (EIC_CONFIG) No detection Position */
+#define EIC_CONFIG_SENSE3_RISE                (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos) /* (EIC_CONFIG) Rising edge detection Position */
+#define EIC_CONFIG_SENSE3_FALL                (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos) /* (EIC_CONFIG) Falling edge detection Position */
+#define EIC_CONFIG_SENSE3_BOTH                (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos) /* (EIC_CONFIG) Both edges detection Position */
+#define EIC_CONFIG_SENSE3_HIGH                (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos) /* (EIC_CONFIG) High level detection Position */
+#define EIC_CONFIG_SENSE3_LOW                 (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos) /* (EIC_CONFIG) Low level detection Position */
+#define EIC_CONFIG_FILTEN3_Pos                _UINT32_(15)                                         /* (EIC_CONFIG) Filter Enable 3 Position */
+#define EIC_CONFIG_FILTEN3_Msk                (_UINT32_(0x1) << EIC_CONFIG_FILTEN3_Pos)            /* (EIC_CONFIG) Filter Enable 3 Mask */
+#define EIC_CONFIG_FILTEN3(value)             (EIC_CONFIG_FILTEN3_Msk & (_UINT32_(value) << EIC_CONFIG_FILTEN3_Pos)) /* Assignment of value for FILTEN3 in the EIC_CONFIG register */
+#define EIC_CONFIG_SENSE4_Pos                 _UINT32_(16)                                         /* (EIC_CONFIG) Input Sense Configuration 4 Position */
+#define EIC_CONFIG_SENSE4_Msk                 (_UINT32_(0x7) << EIC_CONFIG_SENSE4_Pos)             /* (EIC_CONFIG) Input Sense Configuration 4 Mask */
+#define EIC_CONFIG_SENSE4(value)              (EIC_CONFIG_SENSE4_Msk & (_UINT32_(value) << EIC_CONFIG_SENSE4_Pos)) /* Assignment of value for SENSE4 in the EIC_CONFIG register */
+#define   EIC_CONFIG_SENSE4_NONE_Val          _UINT32_(0x0)                                        /* (EIC_CONFIG) No detection  */
+#define   EIC_CONFIG_SENSE4_RISE_Val          _UINT32_(0x1)                                        /* (EIC_CONFIG) Rising edge detection  */
+#define   EIC_CONFIG_SENSE4_FALL_Val          _UINT32_(0x2)                                        /* (EIC_CONFIG) Falling edge detection  */
+#define   EIC_CONFIG_SENSE4_BOTH_Val          _UINT32_(0x3)                                        /* (EIC_CONFIG) Both edges detection  */
+#define   EIC_CONFIG_SENSE4_HIGH_Val          _UINT32_(0x4)                                        /* (EIC_CONFIG) High level detection  */
+#define   EIC_CONFIG_SENSE4_LOW_Val           _UINT32_(0x5)                                        /* (EIC_CONFIG) Low level detection  */
+#define EIC_CONFIG_SENSE4_NONE                (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos) /* (EIC_CONFIG) No detection Position */
+#define EIC_CONFIG_SENSE4_RISE                (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos) /* (EIC_CONFIG) Rising edge detection Position */
+#define EIC_CONFIG_SENSE4_FALL                (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos) /* (EIC_CONFIG) Falling edge detection Position */
+#define EIC_CONFIG_SENSE4_BOTH                (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos) /* (EIC_CONFIG) Both edges detection Position */
+#define EIC_CONFIG_SENSE4_HIGH                (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos) /* (EIC_CONFIG) High level detection Position */
+#define EIC_CONFIG_SENSE4_LOW                 (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos) /* (EIC_CONFIG) Low level detection Position */
+#define EIC_CONFIG_FILTEN4_Pos                _UINT32_(19)                                         /* (EIC_CONFIG) Filter Enable 4 Position */
+#define EIC_CONFIG_FILTEN4_Msk                (_UINT32_(0x1) << EIC_CONFIG_FILTEN4_Pos)            /* (EIC_CONFIG) Filter Enable 4 Mask */
+#define EIC_CONFIG_FILTEN4(value)             (EIC_CONFIG_FILTEN4_Msk & (_UINT32_(value) << EIC_CONFIG_FILTEN4_Pos)) /* Assignment of value for FILTEN4 in the EIC_CONFIG register */
+#define EIC_CONFIG_SENSE5_Pos                 _UINT32_(20)                                         /* (EIC_CONFIG) Input Sense Configuration 5 Position */
+#define EIC_CONFIG_SENSE5_Msk                 (_UINT32_(0x7) << EIC_CONFIG_SENSE5_Pos)             /* (EIC_CONFIG) Input Sense Configuration 5 Mask */
+#define EIC_CONFIG_SENSE5(value)              (EIC_CONFIG_SENSE5_Msk & (_UINT32_(value) << EIC_CONFIG_SENSE5_Pos)) /* Assignment of value for SENSE5 in the EIC_CONFIG register */
+#define   EIC_CONFIG_SENSE5_NONE_Val          _UINT32_(0x0)                                        /* (EIC_CONFIG) No detection  */
+#define   EIC_CONFIG_SENSE5_RISE_Val          _UINT32_(0x1)                                        /* (EIC_CONFIG) Rising edge detection  */
+#define   EIC_CONFIG_SENSE5_FALL_Val          _UINT32_(0x2)                                        /* (EIC_CONFIG) Falling edge detection  */
+#define   EIC_CONFIG_SENSE5_BOTH_Val          _UINT32_(0x3)                                        /* (EIC_CONFIG) Both edges detection  */
+#define   EIC_CONFIG_SENSE5_HIGH_Val          _UINT32_(0x4)                                        /* (EIC_CONFIG) High level detection  */
+#define   EIC_CONFIG_SENSE5_LOW_Val           _UINT32_(0x5)                                        /* (EIC_CONFIG) Low level detection  */
+#define EIC_CONFIG_SENSE5_NONE                (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos) /* (EIC_CONFIG) No detection Position */
+#define EIC_CONFIG_SENSE5_RISE                (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos) /* (EIC_CONFIG) Rising edge detection Position */
+#define EIC_CONFIG_SENSE5_FALL                (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos) /* (EIC_CONFIG) Falling edge detection Position */
+#define EIC_CONFIG_SENSE5_BOTH                (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos) /* (EIC_CONFIG) Both edges detection Position */
+#define EIC_CONFIG_SENSE5_HIGH                (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos) /* (EIC_CONFIG) High level detection Position */
+#define EIC_CONFIG_SENSE5_LOW                 (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos) /* (EIC_CONFIG) Low level detection Position */
+#define EIC_CONFIG_FILTEN5_Pos                _UINT32_(23)                                         /* (EIC_CONFIG) Filter Enable 5 Position */
+#define EIC_CONFIG_FILTEN5_Msk                (_UINT32_(0x1) << EIC_CONFIG_FILTEN5_Pos)            /* (EIC_CONFIG) Filter Enable 5 Mask */
+#define EIC_CONFIG_FILTEN5(value)             (EIC_CONFIG_FILTEN5_Msk & (_UINT32_(value) << EIC_CONFIG_FILTEN5_Pos)) /* Assignment of value for FILTEN5 in the EIC_CONFIG register */
+#define EIC_CONFIG_SENSE6_Pos                 _UINT32_(24)                                         /* (EIC_CONFIG) Input Sense Configuration 6 Position */
+#define EIC_CONFIG_SENSE6_Msk                 (_UINT32_(0x7) << EIC_CONFIG_SENSE6_Pos)             /* (EIC_CONFIG) Input Sense Configuration 6 Mask */
+#define EIC_CONFIG_SENSE6(value)              (EIC_CONFIG_SENSE6_Msk & (_UINT32_(value) << EIC_CONFIG_SENSE6_Pos)) /* Assignment of value for SENSE6 in the EIC_CONFIG register */
+#define   EIC_CONFIG_SENSE6_NONE_Val          _UINT32_(0x0)                                        /* (EIC_CONFIG) No detection  */
+#define   EIC_CONFIG_SENSE6_RISE_Val          _UINT32_(0x1)                                        /* (EIC_CONFIG) Rising edge detection  */
+#define   EIC_CONFIG_SENSE6_FALL_Val          _UINT32_(0x2)                                        /* (EIC_CONFIG) Falling edge detection  */
+#define   EIC_CONFIG_SENSE6_BOTH_Val          _UINT32_(0x3)                                        /* (EIC_CONFIG) Both edges detection  */
+#define   EIC_CONFIG_SENSE6_HIGH_Val          _UINT32_(0x4)                                        /* (EIC_CONFIG) High level detection  */
+#define   EIC_CONFIG_SENSE6_LOW_Val           _UINT32_(0x5)                                        /* (EIC_CONFIG) Low level detection  */
+#define EIC_CONFIG_SENSE6_NONE                (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos) /* (EIC_CONFIG) No detection Position */
+#define EIC_CONFIG_SENSE6_RISE                (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos) /* (EIC_CONFIG) Rising edge detection Position */
+#define EIC_CONFIG_SENSE6_FALL                (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos) /* (EIC_CONFIG) Falling edge detection Position */
+#define EIC_CONFIG_SENSE6_BOTH                (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos) /* (EIC_CONFIG) Both edges detection Position */
+#define EIC_CONFIG_SENSE6_HIGH                (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos) /* (EIC_CONFIG) High level detection Position */
+#define EIC_CONFIG_SENSE6_LOW                 (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos) /* (EIC_CONFIG) Low level detection Position */
+#define EIC_CONFIG_FILTEN6_Pos                _UINT32_(27)                                         /* (EIC_CONFIG) Filter Enable 6 Position */
+#define EIC_CONFIG_FILTEN6_Msk                (_UINT32_(0x1) << EIC_CONFIG_FILTEN6_Pos)            /* (EIC_CONFIG) Filter Enable 6 Mask */
+#define EIC_CONFIG_FILTEN6(value)             (EIC_CONFIG_FILTEN6_Msk & (_UINT32_(value) << EIC_CONFIG_FILTEN6_Pos)) /* Assignment of value for FILTEN6 in the EIC_CONFIG register */
+#define EIC_CONFIG_SENSE7_Pos                 _UINT32_(28)                                         /* (EIC_CONFIG) Input Sense Configuration 7 Position */
+#define EIC_CONFIG_SENSE7_Msk                 (_UINT32_(0x7) << EIC_CONFIG_SENSE7_Pos)             /* (EIC_CONFIG) Input Sense Configuration 7 Mask */
+#define EIC_CONFIG_SENSE7(value)              (EIC_CONFIG_SENSE7_Msk & (_UINT32_(value) << EIC_CONFIG_SENSE7_Pos)) /* Assignment of value for SENSE7 in the EIC_CONFIG register */
+#define   EIC_CONFIG_SENSE7_NONE_Val          _UINT32_(0x0)                                        /* (EIC_CONFIG) No detection  */
+#define   EIC_CONFIG_SENSE7_RISE_Val          _UINT32_(0x1)                                        /* (EIC_CONFIG) Rising edge detection  */
+#define   EIC_CONFIG_SENSE7_FALL_Val          _UINT32_(0x2)                                        /* (EIC_CONFIG) Falling edge detection  */
+#define   EIC_CONFIG_SENSE7_BOTH_Val          _UINT32_(0x3)                                        /* (EIC_CONFIG) Both edges detection  */
+#define   EIC_CONFIG_SENSE7_HIGH_Val          _UINT32_(0x4)                                        /* (EIC_CONFIG) High level detection  */
+#define   EIC_CONFIG_SENSE7_LOW_Val           _UINT32_(0x5)                                        /* (EIC_CONFIG) Low level detection  */
+#define EIC_CONFIG_SENSE7_NONE                (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos) /* (EIC_CONFIG) No detection Position */
+#define EIC_CONFIG_SENSE7_RISE                (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos) /* (EIC_CONFIG) Rising edge detection Position */
+#define EIC_CONFIG_SENSE7_FALL                (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos) /* (EIC_CONFIG) Falling edge detection Position */
+#define EIC_CONFIG_SENSE7_BOTH                (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos) /* (EIC_CONFIG) Both edges detection Position */
+#define EIC_CONFIG_SENSE7_HIGH                (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos) /* (EIC_CONFIG) High level detection Position */
+#define EIC_CONFIG_SENSE7_LOW                 (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos) /* (EIC_CONFIG) Low level detection Position */
+#define EIC_CONFIG_FILTEN7_Pos                _UINT32_(31)                                         /* (EIC_CONFIG) Filter Enable 7 Position */
+#define EIC_CONFIG_FILTEN7_Msk                (_UINT32_(0x1) << EIC_CONFIG_FILTEN7_Pos)            /* (EIC_CONFIG) Filter Enable 7 Mask */
+#define EIC_CONFIG_FILTEN7(value)             (EIC_CONFIG_FILTEN7_Msk & (_UINT32_(value) << EIC_CONFIG_FILTEN7_Pos)) /* Assignment of value for FILTEN7 in the EIC_CONFIG register */
+#define EIC_CONFIG_Msk                        _UINT32_(0xFFFFFFFF)                                 /* (EIC_CONFIG) Register Mask  */
+
+
+/* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */
+#define EIC_DEBOUNCEN_RESETVALUE              _UINT32_(0x00)                                       /*  (EIC_DEBOUNCEN) Debouncer Enable  Reset Value */
+
+#define EIC_DEBOUNCEN_DEBOUNCEN_Pos           _UINT32_(0)                                          /* (EIC_DEBOUNCEN) Debouncer Enable Position */
+#define EIC_DEBOUNCEN_DEBOUNCEN_Msk           (_UINT32_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)    /* (EIC_DEBOUNCEN) Debouncer Enable Mask */
+#define EIC_DEBOUNCEN_DEBOUNCEN(value)        (EIC_DEBOUNCEN_DEBOUNCEN_Msk & (_UINT32_(value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)) /* Assignment of value for DEBOUNCEN in the EIC_DEBOUNCEN register */
+#define EIC_DEBOUNCEN_Msk                     _UINT32_(0x0000FFFF)                                 /* (EIC_DEBOUNCEN) Register Mask  */
+
+
+/* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */
+#define EIC_DPRESCALER_RESETVALUE             _UINT32_(0x00)                                       /*  (EIC_DPRESCALER) Debouncer Prescaler  Reset Value */
+
+#define EIC_DPRESCALER_PRESCALER0_Pos         _UINT32_(0)                                          /* (EIC_DPRESCALER) Debouncer Prescaler Position */
+#define EIC_DPRESCALER_PRESCALER0_Msk         (_UINT32_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos)     /* (EIC_DPRESCALER) Debouncer Prescaler Mask */
+#define EIC_DPRESCALER_PRESCALER0(value)      (EIC_DPRESCALER_PRESCALER0_Msk & (_UINT32_(value) << EIC_DPRESCALER_PRESCALER0_Pos)) /* Assignment of value for PRESCALER0 in the EIC_DPRESCALER register */
+#define   EIC_DPRESCALER_PRESCALER0_DIV2_Val  _UINT32_(0x0)                                        /* (EIC_DPRESCALER) EIC clock divided by 2  */
+#define   EIC_DPRESCALER_PRESCALER0_DIV4_Val  _UINT32_(0x1)                                        /* (EIC_DPRESCALER) EIC clock divided by 4  */
+#define   EIC_DPRESCALER_PRESCALER0_DIV8_Val  _UINT32_(0x2)                                        /* (EIC_DPRESCALER) EIC clock divided by 8  */
+#define   EIC_DPRESCALER_PRESCALER0_DIV16_Val _UINT32_(0x3)                                        /* (EIC_DPRESCALER) EIC clock divided by 16  */
+#define   EIC_DPRESCALER_PRESCALER0_DIV32_Val _UINT32_(0x4)                                        /* (EIC_DPRESCALER) EIC clock divided by 32  */
+#define   EIC_DPRESCALER_PRESCALER0_DIV64_Val _UINT32_(0x5)                                        /* (EIC_DPRESCALER) EIC clock divided by 64  */
+#define   EIC_DPRESCALER_PRESCALER0_DIV128_Val _UINT32_(0x6)                                        /* (EIC_DPRESCALER) EIC clock divided by 128  */
+#define   EIC_DPRESCALER_PRESCALER0_DIV256_Val _UINT32_(0x7)                                        /* (EIC_DPRESCALER) EIC clock divided by 256  */
+#define EIC_DPRESCALER_PRESCALER0_DIV2        (EIC_DPRESCALER_PRESCALER0_DIV2_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 2 Position */
+#define EIC_DPRESCALER_PRESCALER0_DIV4        (EIC_DPRESCALER_PRESCALER0_DIV4_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 4 Position */
+#define EIC_DPRESCALER_PRESCALER0_DIV8        (EIC_DPRESCALER_PRESCALER0_DIV8_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 8 Position */
+#define EIC_DPRESCALER_PRESCALER0_DIV16       (EIC_DPRESCALER_PRESCALER0_DIV16_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 16 Position */
+#define EIC_DPRESCALER_PRESCALER0_DIV32       (EIC_DPRESCALER_PRESCALER0_DIV32_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 32 Position */
+#define EIC_DPRESCALER_PRESCALER0_DIV64       (EIC_DPRESCALER_PRESCALER0_DIV64_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 64 Position */
+#define EIC_DPRESCALER_PRESCALER0_DIV128      (EIC_DPRESCALER_PRESCALER0_DIV128_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 128 Position */
+#define EIC_DPRESCALER_PRESCALER0_DIV256      (EIC_DPRESCALER_PRESCALER0_DIV256_Val << EIC_DPRESCALER_PRESCALER0_Pos) /* (EIC_DPRESCALER) EIC clock divided by 256 Position */
+#define EIC_DPRESCALER_STATES0_Pos            _UINT32_(3)                                          /* (EIC_DPRESCALER) Debouncer number of states Position */
+#define EIC_DPRESCALER_STATES0_Msk            (_UINT32_(0x1) << EIC_DPRESCALER_STATES0_Pos)        /* (EIC_DPRESCALER) Debouncer number of states Mask */
+#define EIC_DPRESCALER_STATES0(value)         (EIC_DPRESCALER_STATES0_Msk & (_UINT32_(value) << EIC_DPRESCALER_STATES0_Pos)) /* Assignment of value for STATES0 in the EIC_DPRESCALER register */
+#define   EIC_DPRESCALER_STATES0_LFREQ3_Val   _UINT32_(0x0)                                        /* (EIC_DPRESCALER) 3 low frequency samples  */
+#define   EIC_DPRESCALER_STATES0_LFREQ7_Val   _UINT32_(0x1)                                        /* (EIC_DPRESCALER) 7 low frequency samples  */
+#define EIC_DPRESCALER_STATES0_LFREQ3         (EIC_DPRESCALER_STATES0_LFREQ3_Val << EIC_DPRESCALER_STATES0_Pos) /* (EIC_DPRESCALER) 3 low frequency samples Position */
+#define EIC_DPRESCALER_STATES0_LFREQ7         (EIC_DPRESCALER_STATES0_LFREQ7_Val << EIC_DPRESCALER_STATES0_Pos) /* (EIC_DPRESCALER) 7 low frequency samples Position */
+#define EIC_DPRESCALER_PRESCALER1_Pos         _UINT32_(4)                                          /* (EIC_DPRESCALER) Debouncer Prescaler Position */
+#define EIC_DPRESCALER_PRESCALER1_Msk         (_UINT32_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos)     /* (EIC_DPRESCALER) Debouncer Prescaler Mask */
+#define EIC_DPRESCALER_PRESCALER1(value)      (EIC_DPRESCALER_PRESCALER1_Msk & (_UINT32_(value) << EIC_DPRESCALER_PRESCALER1_Pos)) /* Assignment of value for PRESCALER1 in the EIC_DPRESCALER register */
+#define   EIC_DPRESCALER_PRESCALER1_DIV2_Val  _UINT32_(0x0)                                        /* (EIC_DPRESCALER) EIC clock divided by 2  */
+#define   EIC_DPRESCALER_PRESCALER1_DIV4_Val  _UINT32_(0x1)                                        /* (EIC_DPRESCALER) EIC clock divided by 4  */
+#define   EIC_DPRESCALER_PRESCALER1_DIV8_Val  _UINT32_(0x2)                                        /* (EIC_DPRESCALER) EIC clock divided by 8  */
+#define   EIC_DPRESCALER_PRESCALER1_DIV16_Val _UINT32_(0x3)                                        /* (EIC_DPRESCALER) EIC clock divided by 16  */
+#define   EIC_DPRESCALER_PRESCALER1_DIV32_Val _UINT32_(0x4)                                        /* (EIC_DPRESCALER) EIC clock divided by 32  */
+#define   EIC_DPRESCALER_PRESCALER1_DIV64_Val _UINT32_(0x5)                                        /* (EIC_DPRESCALER) EIC clock divided by 64  */
+#define   EIC_DPRESCALER_PRESCALER1_DIV128_Val _UINT32_(0x6)                                        /* (EIC_DPRESCALER) EIC clock divided by 128  */
+#define   EIC_DPRESCALER_PRESCALER1_DIV256_Val _UINT32_(0x7)                                        /* (EIC_DPRESCALER) EIC clock divided by 256  */
+#define EIC_DPRESCALER_PRESCALER1_DIV2        (EIC_DPRESCALER_PRESCALER1_DIV2_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 2 Position */
+#define EIC_DPRESCALER_PRESCALER1_DIV4        (EIC_DPRESCALER_PRESCALER1_DIV4_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 4 Position */
+#define EIC_DPRESCALER_PRESCALER1_DIV8        (EIC_DPRESCALER_PRESCALER1_DIV8_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 8 Position */
+#define EIC_DPRESCALER_PRESCALER1_DIV16       (EIC_DPRESCALER_PRESCALER1_DIV16_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 16 Position */
+#define EIC_DPRESCALER_PRESCALER1_DIV32       (EIC_DPRESCALER_PRESCALER1_DIV32_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 32 Position */
+#define EIC_DPRESCALER_PRESCALER1_DIV64       (EIC_DPRESCALER_PRESCALER1_DIV64_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 64 Position */
+#define EIC_DPRESCALER_PRESCALER1_DIV128      (EIC_DPRESCALER_PRESCALER1_DIV128_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 128 Position */
+#define EIC_DPRESCALER_PRESCALER1_DIV256      (EIC_DPRESCALER_PRESCALER1_DIV256_Val << EIC_DPRESCALER_PRESCALER1_Pos) /* (EIC_DPRESCALER) EIC clock divided by 256 Position */
+#define EIC_DPRESCALER_STATES1_Pos            _UINT32_(7)                                          /* (EIC_DPRESCALER) Debouncer number of states Position */
+#define EIC_DPRESCALER_STATES1_Msk            (_UINT32_(0x1) << EIC_DPRESCALER_STATES1_Pos)        /* (EIC_DPRESCALER) Debouncer number of states Mask */
+#define EIC_DPRESCALER_STATES1(value)         (EIC_DPRESCALER_STATES1_Msk & (_UINT32_(value) << EIC_DPRESCALER_STATES1_Pos)) /* Assignment of value for STATES1 in the EIC_DPRESCALER register */
+#define   EIC_DPRESCALER_STATES1_LFREQ3_Val   _UINT32_(0x0)                                        /* (EIC_DPRESCALER) 3 low frequency samples  */
+#define   EIC_DPRESCALER_STATES1_LFREQ7_Val   _UINT32_(0x1)                                        /* (EIC_DPRESCALER) 7 low frequency samples  */
+#define EIC_DPRESCALER_STATES1_LFREQ3         (EIC_DPRESCALER_STATES1_LFREQ3_Val << EIC_DPRESCALER_STATES1_Pos) /* (EIC_DPRESCALER) 3 low frequency samples Position */
+#define EIC_DPRESCALER_STATES1_LFREQ7         (EIC_DPRESCALER_STATES1_LFREQ7_Val << EIC_DPRESCALER_STATES1_Pos) /* (EIC_DPRESCALER) 7 low frequency samples Position */
+#define EIC_DPRESCALER_TICKON_Pos             _UINT32_(16)                                         /* (EIC_DPRESCALER) Pin Sampler frequency selection Position */
+#define EIC_DPRESCALER_TICKON_Msk             (_UINT32_(0x1) << EIC_DPRESCALER_TICKON_Pos)         /* (EIC_DPRESCALER) Pin Sampler frequency selection Mask */
+#define EIC_DPRESCALER_TICKON(value)          (EIC_DPRESCALER_TICKON_Msk & (_UINT32_(value) << EIC_DPRESCALER_TICKON_Pos)) /* Assignment of value for TICKON in the EIC_DPRESCALER register */
+#define   EIC_DPRESCALER_TICKON_CLK_GCLK_EIC_Val _UINT32_(0x0)                                        /* (EIC_DPRESCALER) Bounce sampler is using GCLK_EIC  */
+#define   EIC_DPRESCALER_TICKON_CLK_LFREQ_Val _UINT32_(0x1)                                        /* (EIC_DPRESCALER) Bounce sampler is using Low Frequency Clock  */
+#define EIC_DPRESCALER_TICKON_CLK_GCLK_EIC    (EIC_DPRESCALER_TICKON_CLK_GCLK_EIC_Val << EIC_DPRESCALER_TICKON_Pos) /* (EIC_DPRESCALER) Bounce sampler is using GCLK_EIC Position */
+#define EIC_DPRESCALER_TICKON_CLK_LFREQ       (EIC_DPRESCALER_TICKON_CLK_LFREQ_Val << EIC_DPRESCALER_TICKON_Pos) /* (EIC_DPRESCALER) Bounce sampler is using Low Frequency Clock Position */
+#define EIC_DPRESCALER_Msk                    _UINT32_(0x000100FF)                                 /* (EIC_DPRESCALER) Register Mask  */
+
+
+/* -------- EIC_PINSTATE : (EIC Offset: 0x38) ( R/ 32) Pin State -------- */
+#define EIC_PINSTATE_RESETVALUE               _UINT32_(0x00)                                       /*  (EIC_PINSTATE) Pin State  Reset Value */
+
+#define EIC_PINSTATE_PINSTATE_Pos             _UINT32_(0)                                          /* (EIC_PINSTATE) Pin State Position */
+#define EIC_PINSTATE_PINSTATE_Msk             (_UINT32_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos)      /* (EIC_PINSTATE) Pin State Mask */
+#define EIC_PINSTATE_PINSTATE(value)          (EIC_PINSTATE_PINSTATE_Msk & (_UINT32_(value) << EIC_PINSTATE_PINSTATE_Pos)) /* Assignment of value for PINSTATE in the EIC_PINSTATE register */
+#define EIC_PINSTATE_Msk                      _UINT32_(0x0000FFFF)                                 /* (EIC_PINSTATE) Register Mask  */
+
+
+/* -------- EIC_NSCHK : (EIC Offset: 0x3C) (R/W 32) Non-secure Interrupt Check Enable -------- */
+#define EIC_NSCHK_RESETVALUE                  _UINT32_(0x00)                                       /*  (EIC_NSCHK) Non-secure Interrupt Check Enable  Reset Value */
+
+#define EIC_NSCHK_EXTINT_Pos                  _UINT32_(0)                                          /* (EIC_NSCHK) External Interrupt Nonsecure Check Enable Position */
+#define EIC_NSCHK_EXTINT_Msk                  (_UINT32_(0xFFFF) << EIC_NSCHK_EXTINT_Pos)           /* (EIC_NSCHK) External Interrupt Nonsecure Check Enable Mask */
+#define EIC_NSCHK_EXTINT(value)               (EIC_NSCHK_EXTINT_Msk & (_UINT32_(value) << EIC_NSCHK_EXTINT_Pos)) /* Assignment of value for EXTINT in the EIC_NSCHK register */
+#define EIC_NSCHK_NMI_Pos                     _UINT32_(31)                                         /* (EIC_NSCHK) Non-Maskable External Interrupt Nonsecure Check Enable Position */
+#define EIC_NSCHK_NMI_Msk                     (_UINT32_(0x1) << EIC_NSCHK_NMI_Pos)                 /* (EIC_NSCHK) Non-Maskable External Interrupt Nonsecure Check Enable Mask */
+#define EIC_NSCHK_NMI(value)                  (EIC_NSCHK_NMI_Msk & (_UINT32_(value) << EIC_NSCHK_NMI_Pos)) /* Assignment of value for NMI in the EIC_NSCHK register */
+#define EIC_NSCHK_Msk                         _UINT32_(0x8000FFFF)                                 /* (EIC_NSCHK) Register Mask  */
+
+
+/* -------- EIC_NONSEC : (EIC Offset: 0x40) (R/W 32) Non-secure Interrupt -------- */
+#define EIC_NONSEC_RESETVALUE                 _UINT32_(0x00)                                       /*  (EIC_NONSEC) Non-secure Interrupt  Reset Value */
+
+#define EIC_NONSEC_EXTINT_Pos                 _UINT32_(0)                                          /* (EIC_NONSEC) External Interrupt Nonsecure Enable Position */
+#define EIC_NONSEC_EXTINT_Msk                 (_UINT32_(0xFFFF) << EIC_NONSEC_EXTINT_Pos)          /* (EIC_NONSEC) External Interrupt Nonsecure Enable Mask */
+#define EIC_NONSEC_EXTINT(value)              (EIC_NONSEC_EXTINT_Msk & (_UINT32_(value) << EIC_NONSEC_EXTINT_Pos)) /* Assignment of value for EXTINT in the EIC_NONSEC register */
+#define EIC_NONSEC_NMI_Pos                    _UINT32_(31)                                         /* (EIC_NONSEC) Non-Maskable Interrupt Nonsecure Enable Position */
+#define EIC_NONSEC_NMI_Msk                    (_UINT32_(0x1) << EIC_NONSEC_NMI_Pos)                /* (EIC_NONSEC) Non-Maskable Interrupt Nonsecure Enable Mask */
+#define EIC_NONSEC_NMI(value)                 (EIC_NONSEC_NMI_Msk & (_UINT32_(value) << EIC_NONSEC_NMI_Pos)) /* Assignment of value for NMI in the EIC_NONSEC register */
+#define EIC_NONSEC_Msk                        _UINT32_(0x8000FFFF)                                 /* (EIC_NONSEC) Register Mask  */
+
+
+/* EIC register offsets definitions */
+#define EIC_CTRLA_REG_OFST             _UINT32_(0x00)      /* (EIC_CTRLA) Control A Offset */
+#define EIC_NMICTRL_REG_OFST           _UINT32_(0x01)      /* (EIC_NMICTRL) Non-Maskable Interrupt Control Offset */
+#define EIC_NMIFLAG_REG_OFST           _UINT32_(0x02)      /* (EIC_NMIFLAG) Non-Maskable Interrupt Flag Status and Clear Offset */
+#define EIC_SYNCBUSY_REG_OFST          _UINT32_(0x04)      /* (EIC_SYNCBUSY) Synchronization Busy Offset */
+#define EIC_EVCTRL_REG_OFST            _UINT32_(0x08)      /* (EIC_EVCTRL) Event Control Offset */
+#define EIC_INTENCLR_REG_OFST          _UINT32_(0x0C)      /* (EIC_INTENCLR) Interrupt Enable Clear Offset */
+#define EIC_INTENSET_REG_OFST          _UINT32_(0x10)      /* (EIC_INTENSET) Interrupt Enable Set Offset */
+#define EIC_INTFLAG_REG_OFST           _UINT32_(0x14)      /* (EIC_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define EIC_ASYNCH_REG_OFST            _UINT32_(0x18)      /* (EIC_ASYNCH) External Interrupt Asynchronous Mode Offset */
+#define EIC_CONFIG_REG_OFST            _UINT32_(0x1C)      /* (EIC_CONFIG) External Interrupt Sense Configuration Offset */
+#define EIC_CONFIG0_REG_OFST           _UINT32_(0x1C)      /* (EIC_CONFIG0) External Interrupt Sense Configuration Offset */
+#define EIC_CONFIG1_REG_OFST           _UINT32_(0x20)      /* (EIC_CONFIG1) External Interrupt Sense Configuration Offset */
+#define EIC_DEBOUNCEN_REG_OFST         _UINT32_(0x30)      /* (EIC_DEBOUNCEN) Debouncer Enable Offset */
+#define EIC_DPRESCALER_REG_OFST        _UINT32_(0x34)      /* (EIC_DPRESCALER) Debouncer Prescaler Offset */
+#define EIC_PINSTATE_REG_OFST          _UINT32_(0x38)      /* (EIC_PINSTATE) Pin State Offset */
+#define EIC_NSCHK_REG_OFST             _UINT32_(0x3C)      /* (EIC_NSCHK) Non-secure Interrupt Check Enable Offset */
+#define EIC_NONSEC_REG_OFST            _UINT32_(0x40)      /* (EIC_NONSEC) Non-secure Interrupt Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* EIC register API structure */
+typedef struct
+{  /* External Interrupt Controller */
+  __IO  uint8_t                        EIC_CTRLA;          /* Offset: 0x00 (R/W  8) Control A */
+  __IO  uint8_t                        EIC_NMICTRL;        /* Offset: 0x01 (R/W  8) Non-Maskable Interrupt Control */
+  __IO  uint16_t                       EIC_NMIFLAG;        /* Offset: 0x02 (R/W  16) Non-Maskable Interrupt Flag Status and Clear */
+  __I   uint32_t                       EIC_SYNCBUSY;       /* Offset: 0x04 (R/   32) Synchronization Busy */
+  __IO  uint32_t                       EIC_EVCTRL;         /* Offset: 0x08 (R/W  32) Event Control */
+  __IO  uint32_t                       EIC_INTENCLR;       /* Offset: 0x0C (R/W  32) Interrupt Enable Clear */
+  __IO  uint32_t                       EIC_INTENSET;       /* Offset: 0x10 (R/W  32) Interrupt Enable Set */
+  __IO  uint32_t                       EIC_INTFLAG;        /* Offset: 0x14 (R/W  32) Interrupt Flag Status and Clear */
+  __IO  uint32_t                       EIC_ASYNCH;         /* Offset: 0x18 (R/W  32) External Interrupt Asynchronous Mode */
+  __IO  uint32_t                       EIC_CONFIG[2];      /* Offset: 0x1C (R/W  32) External Interrupt Sense Configuration */
+  __I   uint8_t                        Reserved1[0x0C];
+  __IO  uint32_t                       EIC_DEBOUNCEN;      /* Offset: 0x30 (R/W  32) Debouncer Enable */
+  __IO  uint32_t                       EIC_DPRESCALER;     /* Offset: 0x34 (R/W  32) Debouncer Prescaler */
+  __I   uint32_t                       EIC_PINSTATE;       /* Offset: 0x38 (R/   32) Pin State */
+  __IO  uint32_t                       EIC_NSCHK;          /* Offset: 0x3C (R/W  32) Non-secure Interrupt Check Enable */
+  __IO  uint32_t                       EIC_NONSEC;         /* Offset: 0x40 (R/W  32) Non-secure Interrupt */
+} eic_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_EIC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/evsys.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/evsys.h
new file mode 100644
index 00000000..ba195078
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/evsys.h
@@ -0,0 +1,452 @@
+/*
+ * Component description for EVSYS
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_EVSYS_COMPONENT_H_
+#define _PIC32CMGC00_EVSYS_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                     SOFTWARE API DEFINITION FOR EVSYS                      */
+/* ************************************************************************** */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x00) (R/W 32) Channel n Control -------- */
+#define EVSYS_CHANNEL_RESETVALUE              _UINT32_(0x8000)                                     /*  (EVSYS_CHANNEL) Channel n Control  Reset Value */
+
+#define EVSYS_CHANNEL_EVGEN_Pos               _UINT32_(0)                                          /* (EVSYS_CHANNEL) Event Generator Selection Position */
+#define EVSYS_CHANNEL_EVGEN_Msk               (_UINT32_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)          /* (EVSYS_CHANNEL) Event Generator Selection Mask */
+#define EVSYS_CHANNEL_EVGEN(value)            (EVSYS_CHANNEL_EVGEN_Msk & (_UINT32_(value) << EVSYS_CHANNEL_EVGEN_Pos)) /* Assignment of value for EVGEN in the EVSYS_CHANNEL register */
+#define EVSYS_CHANNEL_PATH_Pos                _UINT32_(8)                                          /* (EVSYS_CHANNEL) Path Selection Position */
+#define EVSYS_CHANNEL_PATH_Msk                (_UINT32_(0x3) << EVSYS_CHANNEL_PATH_Pos)            /* (EVSYS_CHANNEL) Path Selection Mask */
+#define EVSYS_CHANNEL_PATH(value)             (EVSYS_CHANNEL_PATH_Msk & (_UINT32_(value) << EVSYS_CHANNEL_PATH_Pos)) /* Assignment of value for PATH in the EVSYS_CHANNEL register */
+#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _UINT32_(0x0)                                        /* (EVSYS_CHANNEL) Asynchronous path  */
+#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _UINT32_(0x1)                                        /* (EVSYS_CHANNEL) Resynchronized path  */
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS       (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) /* (EVSYS_CHANNEL) Asynchronous path Position */
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED     (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) /* (EVSYS_CHANNEL) Resynchronized path Position */
+#define EVSYS_CHANNEL_EDGSEL_Pos              _UINT32_(10)                                         /* (EVSYS_CHANNEL) Edge Detection Selection Position */
+#define EVSYS_CHANNEL_EDGSEL_Msk              (_UINT32_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)          /* (EVSYS_CHANNEL) Edge Detection Selection Mask */
+#define EVSYS_CHANNEL_EDGSEL(value)           (EVSYS_CHANNEL_EDGSEL_Msk & (_UINT32_(value) << EVSYS_CHANNEL_EDGSEL_Pos)) /* Assignment of value for EDGSEL in the EVSYS_CHANNEL register */
+#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _UINT32_(0x0)                                        /* (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path  */
+#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _UINT32_(0x1)                                        /* (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path  */
+#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _UINT32_(0x2)                                        /* (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path  */
+#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _UINT32_(0x3)                                        /* (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path  */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT    (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) /* (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path Position */
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE      (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) /* (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path Position */
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE     (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) /* (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path Position */
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES       (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) /* (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path Position */
+#define EVSYS_CHANNEL_RUNSTDBY_Pos            _UINT32_(14)                                         /* (EVSYS_CHANNEL) Run in standby Position */
+#define EVSYS_CHANNEL_RUNSTDBY_Msk            (_UINT32_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)        /* (EVSYS_CHANNEL) Run in standby Mask */
+#define EVSYS_CHANNEL_RUNSTDBY(value)         (EVSYS_CHANNEL_RUNSTDBY_Msk & (_UINT32_(value) << EVSYS_CHANNEL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the EVSYS_CHANNEL register */
+#define EVSYS_CHANNEL_ONDEMAND_Pos            _UINT32_(15)                                         /* (EVSYS_CHANNEL) Generic Clock On Demand Position */
+#define EVSYS_CHANNEL_ONDEMAND_Msk            (_UINT32_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)        /* (EVSYS_CHANNEL) Generic Clock On Demand Mask */
+#define EVSYS_CHANNEL_ONDEMAND(value)         (EVSYS_CHANNEL_ONDEMAND_Msk & (_UINT32_(value) << EVSYS_CHANNEL_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the EVSYS_CHANNEL register */
+#define EVSYS_CHANNEL_Msk                     _UINT32_(0x0000CF7F)                                 /* (EVSYS_CHANNEL) Register Mask  */
+
+
+/* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x04) (R/W 8) Channel n Interrupt Enable Clear -------- */
+#define EVSYS_CHINTENCLR_RESETVALUE           _UINT8_(0x00)                                        /*  (EVSYS_CHINTENCLR) Channel n Interrupt Enable Clear  Reset Value */
+
+#define EVSYS_CHINTENCLR_OVR_Pos              _UINT8_(0)                                           /* (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable Position */
+#define EVSYS_CHINTENCLR_OVR_Msk              (_UINT8_(0x1) << EVSYS_CHINTENCLR_OVR_Pos)           /* (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable Mask */
+#define EVSYS_CHINTENCLR_OVR(value)           (EVSYS_CHINTENCLR_OVR_Msk & (_UINT8_(value) << EVSYS_CHINTENCLR_OVR_Pos)) /* Assignment of value for OVR in the EVSYS_CHINTENCLR register */
+#define EVSYS_CHINTENCLR_EVD_Pos              _UINT8_(1)                                           /* (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable Position */
+#define EVSYS_CHINTENCLR_EVD_Msk              (_UINT8_(0x1) << EVSYS_CHINTENCLR_EVD_Pos)           /* (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable Mask */
+#define EVSYS_CHINTENCLR_EVD(value)           (EVSYS_CHINTENCLR_EVD_Msk & (_UINT8_(value) << EVSYS_CHINTENCLR_EVD_Pos)) /* Assignment of value for EVD in the EVSYS_CHINTENCLR register */
+#define EVSYS_CHINTENCLR_Msk                  _UINT8_(0x03)                                        /* (EVSYS_CHINTENCLR) Register Mask  */
+
+
+/* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x05) (R/W 8) Channel n Interrupt Enable Set -------- */
+#define EVSYS_CHINTENSET_RESETVALUE           _UINT8_(0x00)                                        /*  (EVSYS_CHINTENSET) Channel n Interrupt Enable Set  Reset Value */
+
+#define EVSYS_CHINTENSET_OVR_Pos              _UINT8_(0)                                           /* (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable Position */
+#define EVSYS_CHINTENSET_OVR_Msk              (_UINT8_(0x1) << EVSYS_CHINTENSET_OVR_Pos)           /* (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable Mask */
+#define EVSYS_CHINTENSET_OVR(value)           (EVSYS_CHINTENSET_OVR_Msk & (_UINT8_(value) << EVSYS_CHINTENSET_OVR_Pos)) /* Assignment of value for OVR in the EVSYS_CHINTENSET register */
+#define EVSYS_CHINTENSET_EVD_Pos              _UINT8_(1)                                           /* (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable Position */
+#define EVSYS_CHINTENSET_EVD_Msk              (_UINT8_(0x1) << EVSYS_CHINTENSET_EVD_Pos)           /* (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable Mask */
+#define EVSYS_CHINTENSET_EVD(value)           (EVSYS_CHINTENSET_EVD_Msk & (_UINT8_(value) << EVSYS_CHINTENSET_EVD_Pos)) /* Assignment of value for EVD in the EVSYS_CHINTENSET register */
+#define EVSYS_CHINTENSET_Msk                  _UINT8_(0x03)                                        /* (EVSYS_CHINTENSET) Register Mask  */
+
+
+/* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x06) (R/W 8) Channel n Interrupt Flag Status and Clear -------- */
+#define EVSYS_CHINTFLAG_RESETVALUE            _UINT8_(0x00)                                        /*  (EVSYS_CHINTFLAG) Channel n Interrupt Flag Status and Clear  Reset Value */
+
+#define EVSYS_CHINTFLAG_OVR_Pos               _UINT8_(0)                                           /* (EVSYS_CHINTFLAG) Channel Overrun Position */
+#define EVSYS_CHINTFLAG_OVR_Msk               (_UINT8_(0x1) << EVSYS_CHINTFLAG_OVR_Pos)            /* (EVSYS_CHINTFLAG) Channel Overrun Mask */
+#define EVSYS_CHINTFLAG_OVR(value)            (EVSYS_CHINTFLAG_OVR_Msk & (_UINT8_(value) << EVSYS_CHINTFLAG_OVR_Pos)) /* Assignment of value for OVR in the EVSYS_CHINTFLAG register */
+#define EVSYS_CHINTFLAG_EVD_Pos               _UINT8_(1)                                           /* (EVSYS_CHINTFLAG) Channel Event Detected Position */
+#define EVSYS_CHINTFLAG_EVD_Msk               (_UINT8_(0x1) << EVSYS_CHINTFLAG_EVD_Pos)            /* (EVSYS_CHINTFLAG) Channel Event Detected Mask */
+#define EVSYS_CHINTFLAG_EVD(value)            (EVSYS_CHINTFLAG_EVD_Msk & (_UINT8_(value) << EVSYS_CHINTFLAG_EVD_Pos)) /* Assignment of value for EVD in the EVSYS_CHINTFLAG register */
+#define EVSYS_CHINTFLAG_Msk                   _UINT8_(0x03)                                        /* (EVSYS_CHINTFLAG) Register Mask  */
+
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x07) ( R/ 8) Channel n Status -------- */
+#define EVSYS_CHSTATUS_RESETVALUE             _UINT8_(0x01)                                        /*  (EVSYS_CHSTATUS) Channel n Status  Reset Value */
+
+#define EVSYS_CHSTATUS_RDYUSR_Pos             _UINT8_(0)                                           /* (EVSYS_CHSTATUS) Ready User Position */
+#define EVSYS_CHSTATUS_RDYUSR_Msk             (_UINT8_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos)          /* (EVSYS_CHSTATUS) Ready User Mask */
+#define EVSYS_CHSTATUS_RDYUSR(value)          (EVSYS_CHSTATUS_RDYUSR_Msk & (_UINT8_(value) << EVSYS_CHSTATUS_RDYUSR_Pos)) /* Assignment of value for RDYUSR in the EVSYS_CHSTATUS register */
+#define EVSYS_CHSTATUS_BUSYCH_Pos             _UINT8_(1)                                           /* (EVSYS_CHSTATUS) Busy Channel Position */
+#define EVSYS_CHSTATUS_BUSYCH_Msk             (_UINT8_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos)          /* (EVSYS_CHSTATUS) Busy Channel Mask */
+#define EVSYS_CHSTATUS_BUSYCH(value)          (EVSYS_CHSTATUS_BUSYCH_Msk & (_UINT8_(value) << EVSYS_CHSTATUS_BUSYCH_Pos)) /* Assignment of value for BUSYCH in the EVSYS_CHSTATUS register */
+#define EVSYS_CHSTATUS_Msk                    _UINT8_(0x03)                                        /* (EVSYS_CHSTATUS) Register Mask  */
+
+
+/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
+#define EVSYS_CTRLA_RESETVALUE                _UINT8_(0x00)                                        /*  (EVSYS_CTRLA) Control  Reset Value */
+
+#define EVSYS_CTRLA_SWRST_Pos                 _UINT8_(0)                                           /* (EVSYS_CTRLA) Software Reset Position */
+#define EVSYS_CTRLA_SWRST_Msk                 (_UINT8_(0x1) << EVSYS_CTRLA_SWRST_Pos)              /* (EVSYS_CTRLA) Software Reset Mask */
+#define EVSYS_CTRLA_SWRST(value)              (EVSYS_CTRLA_SWRST_Msk & (_UINT8_(value) << EVSYS_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the EVSYS_CTRLA register */
+#define EVSYS_CTRLA_Msk                       _UINT8_(0x01)                                        /* (EVSYS_CTRLA) Register Mask  */
+
+
+/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x04) ( /W 32) Software Event -------- */
+#define EVSYS_SWEVT_RESETVALUE                _UINT32_(0x00)                                       /*  (EVSYS_SWEVT) Software Event  Reset Value */
+
+#define EVSYS_SWEVT_CHANNEL0_Pos              _UINT32_(0)                                          /* (EVSYS_SWEVT) Channel 0 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL0_Msk              (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL0_Pos)          /* (EVSYS_SWEVT) Channel 0 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL0(value)           (EVSYS_SWEVT_CHANNEL0_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL0_Pos)) /* Assignment of value for CHANNEL0 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL1_Pos              _UINT32_(1)                                          /* (EVSYS_SWEVT) Channel 1 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL1_Msk              (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL1_Pos)          /* (EVSYS_SWEVT) Channel 1 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL1(value)           (EVSYS_SWEVT_CHANNEL1_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL1_Pos)) /* Assignment of value for CHANNEL1 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL2_Pos              _UINT32_(2)                                          /* (EVSYS_SWEVT) Channel 2 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL2_Msk              (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL2_Pos)          /* (EVSYS_SWEVT) Channel 2 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL2(value)           (EVSYS_SWEVT_CHANNEL2_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL2_Pos)) /* Assignment of value for CHANNEL2 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL3_Pos              _UINT32_(3)                                          /* (EVSYS_SWEVT) Channel 3 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL3_Msk              (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL3_Pos)          /* (EVSYS_SWEVT) Channel 3 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL3(value)           (EVSYS_SWEVT_CHANNEL3_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL3_Pos)) /* Assignment of value for CHANNEL3 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL4_Pos              _UINT32_(4)                                          /* (EVSYS_SWEVT) Channel 4 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL4_Msk              (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL4_Pos)          /* (EVSYS_SWEVT) Channel 4 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL4(value)           (EVSYS_SWEVT_CHANNEL4_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL4_Pos)) /* Assignment of value for CHANNEL4 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL5_Pos              _UINT32_(5)                                          /* (EVSYS_SWEVT) Channel 5 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL5_Msk              (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL5_Pos)          /* (EVSYS_SWEVT) Channel 5 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL5(value)           (EVSYS_SWEVT_CHANNEL5_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL5_Pos)) /* Assignment of value for CHANNEL5 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL6_Pos              _UINT32_(6)                                          /* (EVSYS_SWEVT) Channel 6 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL6_Msk              (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL6_Pos)          /* (EVSYS_SWEVT) Channel 6 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL6(value)           (EVSYS_SWEVT_CHANNEL6_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL6_Pos)) /* Assignment of value for CHANNEL6 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL7_Pos              _UINT32_(7)                                          /* (EVSYS_SWEVT) Channel 7 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL7_Msk              (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL7_Pos)          /* (EVSYS_SWEVT) Channel 7 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL7(value)           (EVSYS_SWEVT_CHANNEL7_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL7_Pos)) /* Assignment of value for CHANNEL7 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL8_Pos              _UINT32_(8)                                          /* (EVSYS_SWEVT) Channel 8 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL8_Msk              (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL8_Pos)          /* (EVSYS_SWEVT) Channel 8 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL8(value)           (EVSYS_SWEVT_CHANNEL8_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL8_Pos)) /* Assignment of value for CHANNEL8 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL9_Pos              _UINT32_(9)                                          /* (EVSYS_SWEVT) Channel 9 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL9_Msk              (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL9_Pos)          /* (EVSYS_SWEVT) Channel 9 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL9(value)           (EVSYS_SWEVT_CHANNEL9_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL9_Pos)) /* Assignment of value for CHANNEL9 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL10_Pos             _UINT32_(10)                                         /* (EVSYS_SWEVT) Channel 10 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL10_Msk             (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL10_Pos)         /* (EVSYS_SWEVT) Channel 10 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL10(value)          (EVSYS_SWEVT_CHANNEL10_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL10_Pos)) /* Assignment of value for CHANNEL10 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_CHANNEL11_Pos             _UINT32_(11)                                         /* (EVSYS_SWEVT) Channel 11 Software Selection Position */
+#define EVSYS_SWEVT_CHANNEL11_Msk             (_UINT32_(0x1) << EVSYS_SWEVT_CHANNEL11_Pos)         /* (EVSYS_SWEVT) Channel 11 Software Selection Mask */
+#define EVSYS_SWEVT_CHANNEL11(value)          (EVSYS_SWEVT_CHANNEL11_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL11_Pos)) /* Assignment of value for CHANNEL11 in the EVSYS_SWEVT register */
+#define EVSYS_SWEVT_Msk                       _UINT32_(0x00000FFF)                                 /* (EVSYS_SWEVT) Register Mask  */
+
+#define EVSYS_SWEVT_CHANNEL_Pos               _UINT32_(0)                                          /* (EVSYS_SWEVT Position) Channel xx Software Selection */
+#define EVSYS_SWEVT_CHANNEL_Msk               (_UINT32_(0xFFF) << EVSYS_SWEVT_CHANNEL_Pos)         /* (EVSYS_SWEVT Mask) CHANNEL */
+#define EVSYS_SWEVT_CHANNEL(value)            (EVSYS_SWEVT_CHANNEL_Msk & (_UINT32_(value) << EVSYS_SWEVT_CHANNEL_Pos)) 
+
+/* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x08) (R/W 8) Priority Control -------- */
+#define EVSYS_PRICTRL_RESETVALUE              _UINT8_(0x00)                                        /*  (EVSYS_PRICTRL) Priority Control  Reset Value */
+
+#define EVSYS_PRICTRL_PRI_Pos                 _UINT8_(0)                                           /* (EVSYS_PRICTRL) Channel Priority Number Position */
+#define EVSYS_PRICTRL_PRI_Msk                 (_UINT8_(0xF) << EVSYS_PRICTRL_PRI_Pos)              /* (EVSYS_PRICTRL) Channel Priority Number Mask */
+#define EVSYS_PRICTRL_PRI(value)              (EVSYS_PRICTRL_PRI_Msk & (_UINT8_(value) << EVSYS_PRICTRL_PRI_Pos)) /* Assignment of value for PRI in the EVSYS_PRICTRL register */
+#define EVSYS_PRICTRL_RREN_Pos                _UINT8_(7)                                           /* (EVSYS_PRICTRL) Round-Robin Scheduling Enable Position */
+#define EVSYS_PRICTRL_RREN_Msk                (_UINT8_(0x1) << EVSYS_PRICTRL_RREN_Pos)             /* (EVSYS_PRICTRL) Round-Robin Scheduling Enable Mask */
+#define EVSYS_PRICTRL_RREN(value)             (EVSYS_PRICTRL_RREN_Msk & (_UINT8_(value) << EVSYS_PRICTRL_RREN_Pos)) /* Assignment of value for RREN in the EVSYS_PRICTRL register */
+#define EVSYS_PRICTRL_Msk                     _UINT8_(0x8F)                                        /* (EVSYS_PRICTRL) Register Mask  */
+
+
+/* -------- EVSYS_INTPEND : (EVSYS Offset: 0x10) (R/W 16) Channel Pending Interrupt -------- */
+#define EVSYS_INTPEND_RESETVALUE              _UINT16_(0x4000)                                     /*  (EVSYS_INTPEND) Channel Pending Interrupt  Reset Value */
+
+#define EVSYS_INTPEND_ID_Pos                  _UINT16_(0)                                          /* (EVSYS_INTPEND) Channel ID Position */
+#define EVSYS_INTPEND_ID_Msk                  (_UINT16_(0xF) << EVSYS_INTPEND_ID_Pos)              /* (EVSYS_INTPEND) Channel ID Mask */
+#define EVSYS_INTPEND_ID(value)               (EVSYS_INTPEND_ID_Msk & (_UINT16_(value) << EVSYS_INTPEND_ID_Pos)) /* Assignment of value for ID in the EVSYS_INTPEND register */
+#define EVSYS_INTPEND_OVR_Pos                 _UINT16_(8)                                          /* (EVSYS_INTPEND) Channel Overrun Position */
+#define EVSYS_INTPEND_OVR_Msk                 (_UINT16_(0x1) << EVSYS_INTPEND_OVR_Pos)             /* (EVSYS_INTPEND) Channel Overrun Mask */
+#define EVSYS_INTPEND_OVR(value)              (EVSYS_INTPEND_OVR_Msk & (_UINT16_(value) << EVSYS_INTPEND_OVR_Pos)) /* Assignment of value for OVR in the EVSYS_INTPEND register */
+#define EVSYS_INTPEND_EVD_Pos                 _UINT16_(9)                                          /* (EVSYS_INTPEND) Channel Event Detected Position */
+#define EVSYS_INTPEND_EVD_Msk                 (_UINT16_(0x1) << EVSYS_INTPEND_EVD_Pos)             /* (EVSYS_INTPEND) Channel Event Detected Mask */
+#define EVSYS_INTPEND_EVD(value)              (EVSYS_INTPEND_EVD_Msk & (_UINT16_(value) << EVSYS_INTPEND_EVD_Pos)) /* Assignment of value for EVD in the EVSYS_INTPEND register */
+#define EVSYS_INTPEND_READY_Pos               _UINT16_(14)                                         /* (EVSYS_INTPEND) Ready Position */
+#define EVSYS_INTPEND_READY_Msk               (_UINT16_(0x1) << EVSYS_INTPEND_READY_Pos)           /* (EVSYS_INTPEND) Ready Mask */
+#define EVSYS_INTPEND_READY(value)            (EVSYS_INTPEND_READY_Msk & (_UINT16_(value) << EVSYS_INTPEND_READY_Pos)) /* Assignment of value for READY in the EVSYS_INTPEND register */
+#define EVSYS_INTPEND_BUSY_Pos                _UINT16_(15)                                         /* (EVSYS_INTPEND) Busy Position */
+#define EVSYS_INTPEND_BUSY_Msk                (_UINT16_(0x1) << EVSYS_INTPEND_BUSY_Pos)            /* (EVSYS_INTPEND) Busy Mask */
+#define EVSYS_INTPEND_BUSY(value)             (EVSYS_INTPEND_BUSY_Msk & (_UINT16_(value) << EVSYS_INTPEND_BUSY_Pos)) /* Assignment of value for BUSY in the EVSYS_INTPEND register */
+#define EVSYS_INTPEND_Msk                     _UINT16_(0xC30F)                                     /* (EVSYS_INTPEND) Register Mask  */
+
+
+/* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x14) ( R/ 32) Interrupt Status -------- */
+#define EVSYS_INTSTATUS_RESETVALUE            _UINT32_(0x00)                                       /*  (EVSYS_INTSTATUS) Interrupt Status  Reset Value */
+
+#define EVSYS_INTSTATUS_CHINT0_Pos            _UINT32_(0)                                          /* (EVSYS_INTSTATUS) Channel 0 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT0_Msk            (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT0_Pos)        /* (EVSYS_INTSTATUS) Channel 0 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT0(value)         (EVSYS_INTSTATUS_CHINT0_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT0_Pos)) /* Assignment of value for CHINT0 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT1_Pos            _UINT32_(1)                                          /* (EVSYS_INTSTATUS) Channel 1 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT1_Msk            (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT1_Pos)        /* (EVSYS_INTSTATUS) Channel 1 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT1(value)         (EVSYS_INTSTATUS_CHINT1_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT1_Pos)) /* Assignment of value for CHINT1 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT2_Pos            _UINT32_(2)                                          /* (EVSYS_INTSTATUS) Channel 2 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT2_Msk            (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT2_Pos)        /* (EVSYS_INTSTATUS) Channel 2 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT2(value)         (EVSYS_INTSTATUS_CHINT2_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT2_Pos)) /* Assignment of value for CHINT2 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT3_Pos            _UINT32_(3)                                          /* (EVSYS_INTSTATUS) Channel 3 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT3_Msk            (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT3_Pos)        /* (EVSYS_INTSTATUS) Channel 3 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT3(value)         (EVSYS_INTSTATUS_CHINT3_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT3_Pos)) /* Assignment of value for CHINT3 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT4_Pos            _UINT32_(4)                                          /* (EVSYS_INTSTATUS) Channel 4 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT4_Msk            (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT4_Pos)        /* (EVSYS_INTSTATUS) Channel 4 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT4(value)         (EVSYS_INTSTATUS_CHINT4_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT4_Pos)) /* Assignment of value for CHINT4 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT5_Pos            _UINT32_(5)                                          /* (EVSYS_INTSTATUS) Channel 5 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT5_Msk            (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT5_Pos)        /* (EVSYS_INTSTATUS) Channel 5 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT5(value)         (EVSYS_INTSTATUS_CHINT5_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT5_Pos)) /* Assignment of value for CHINT5 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT6_Pos            _UINT32_(6)                                          /* (EVSYS_INTSTATUS) Channel 6 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT6_Msk            (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT6_Pos)        /* (EVSYS_INTSTATUS) Channel 6 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT6(value)         (EVSYS_INTSTATUS_CHINT6_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT6_Pos)) /* Assignment of value for CHINT6 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT7_Pos            _UINT32_(7)                                          /* (EVSYS_INTSTATUS) Channel 7 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT7_Msk            (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT7_Pos)        /* (EVSYS_INTSTATUS) Channel 7 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT7(value)         (EVSYS_INTSTATUS_CHINT7_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT7_Pos)) /* Assignment of value for CHINT7 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT8_Pos            _UINT32_(8)                                          /* (EVSYS_INTSTATUS) Channel 8 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT8_Msk            (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT8_Pos)        /* (EVSYS_INTSTATUS) Channel 8 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT8(value)         (EVSYS_INTSTATUS_CHINT8_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT8_Pos)) /* Assignment of value for CHINT8 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT9_Pos            _UINT32_(9)                                          /* (EVSYS_INTSTATUS) Channel 9 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT9_Msk            (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT9_Pos)        /* (EVSYS_INTSTATUS) Channel 9 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT9(value)         (EVSYS_INTSTATUS_CHINT9_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT9_Pos)) /* Assignment of value for CHINT9 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT10_Pos           _UINT32_(10)                                         /* (EVSYS_INTSTATUS) Channel 10 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT10_Msk           (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT10_Pos)       /* (EVSYS_INTSTATUS) Channel 10 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT10(value)        (EVSYS_INTSTATUS_CHINT10_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT10_Pos)) /* Assignment of value for CHINT10 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_CHINT11_Pos           _UINT32_(11)                                         /* (EVSYS_INTSTATUS) Channel 11 Pending Interrupt Position */
+#define EVSYS_INTSTATUS_CHINT11_Msk           (_UINT32_(0x1) << EVSYS_INTSTATUS_CHINT11_Pos)       /* (EVSYS_INTSTATUS) Channel 11 Pending Interrupt Mask */
+#define EVSYS_INTSTATUS_CHINT11(value)        (EVSYS_INTSTATUS_CHINT11_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT11_Pos)) /* Assignment of value for CHINT11 in the EVSYS_INTSTATUS register */
+#define EVSYS_INTSTATUS_Msk                   _UINT32_(0x00000FFF)                                 /* (EVSYS_INTSTATUS) Register Mask  */
+
+#define EVSYS_INTSTATUS_CHINT_Pos             _UINT32_(0)                                          /* (EVSYS_INTSTATUS Position) Channel xx Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT_Msk             (_UINT32_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos)       /* (EVSYS_INTSTATUS Mask) CHINT */
+#define EVSYS_INTSTATUS_CHINT(value)          (EVSYS_INTSTATUS_CHINT_Msk & (_UINT32_(value) << EVSYS_INTSTATUS_CHINT_Pos)) 
+
+/* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x18) ( R/ 32) Busy Channels -------- */
+#define EVSYS_BUSYCH_RESETVALUE               _UINT32_(0x00)                                       /*  (EVSYS_BUSYCH) Busy Channels  Reset Value */
+
+#define EVSYS_BUSYCH_BUSYCH0_Pos              _UINT32_(0)                                          /* (EVSYS_BUSYCH) Busy Channel 0 Position */
+#define EVSYS_BUSYCH_BUSYCH0_Msk              (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH0_Pos)          /* (EVSYS_BUSYCH) Busy Channel 0 Mask */
+#define EVSYS_BUSYCH_BUSYCH0(value)           (EVSYS_BUSYCH_BUSYCH0_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH0_Pos)) /* Assignment of value for BUSYCH0 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH1_Pos              _UINT32_(1)                                          /* (EVSYS_BUSYCH) Busy Channel 1 Position */
+#define EVSYS_BUSYCH_BUSYCH1_Msk              (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH1_Pos)          /* (EVSYS_BUSYCH) Busy Channel 1 Mask */
+#define EVSYS_BUSYCH_BUSYCH1(value)           (EVSYS_BUSYCH_BUSYCH1_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH1_Pos)) /* Assignment of value for BUSYCH1 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH2_Pos              _UINT32_(2)                                          /* (EVSYS_BUSYCH) Busy Channel 2 Position */
+#define EVSYS_BUSYCH_BUSYCH2_Msk              (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH2_Pos)          /* (EVSYS_BUSYCH) Busy Channel 2 Mask */
+#define EVSYS_BUSYCH_BUSYCH2(value)           (EVSYS_BUSYCH_BUSYCH2_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH2_Pos)) /* Assignment of value for BUSYCH2 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH3_Pos              _UINT32_(3)                                          /* (EVSYS_BUSYCH) Busy Channel 3 Position */
+#define EVSYS_BUSYCH_BUSYCH3_Msk              (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH3_Pos)          /* (EVSYS_BUSYCH) Busy Channel 3 Mask */
+#define EVSYS_BUSYCH_BUSYCH3(value)           (EVSYS_BUSYCH_BUSYCH3_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH3_Pos)) /* Assignment of value for BUSYCH3 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH4_Pos              _UINT32_(4)                                          /* (EVSYS_BUSYCH) Busy Channel 4 Position */
+#define EVSYS_BUSYCH_BUSYCH4_Msk              (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH4_Pos)          /* (EVSYS_BUSYCH) Busy Channel 4 Mask */
+#define EVSYS_BUSYCH_BUSYCH4(value)           (EVSYS_BUSYCH_BUSYCH4_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH4_Pos)) /* Assignment of value for BUSYCH4 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH5_Pos              _UINT32_(5)                                          /* (EVSYS_BUSYCH) Busy Channel 5 Position */
+#define EVSYS_BUSYCH_BUSYCH5_Msk              (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH5_Pos)          /* (EVSYS_BUSYCH) Busy Channel 5 Mask */
+#define EVSYS_BUSYCH_BUSYCH5(value)           (EVSYS_BUSYCH_BUSYCH5_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH5_Pos)) /* Assignment of value for BUSYCH5 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH6_Pos              _UINT32_(6)                                          /* (EVSYS_BUSYCH) Busy Channel 6 Position */
+#define EVSYS_BUSYCH_BUSYCH6_Msk              (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH6_Pos)          /* (EVSYS_BUSYCH) Busy Channel 6 Mask */
+#define EVSYS_BUSYCH_BUSYCH6(value)           (EVSYS_BUSYCH_BUSYCH6_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH6_Pos)) /* Assignment of value for BUSYCH6 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH7_Pos              _UINT32_(7)                                          /* (EVSYS_BUSYCH) Busy Channel 7 Position */
+#define EVSYS_BUSYCH_BUSYCH7_Msk              (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH7_Pos)          /* (EVSYS_BUSYCH) Busy Channel 7 Mask */
+#define EVSYS_BUSYCH_BUSYCH7(value)           (EVSYS_BUSYCH_BUSYCH7_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH7_Pos)) /* Assignment of value for BUSYCH7 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH8_Pos              _UINT32_(8)                                          /* (EVSYS_BUSYCH) Busy Channel 8 Position */
+#define EVSYS_BUSYCH_BUSYCH8_Msk              (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH8_Pos)          /* (EVSYS_BUSYCH) Busy Channel 8 Mask */
+#define EVSYS_BUSYCH_BUSYCH8(value)           (EVSYS_BUSYCH_BUSYCH8_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH8_Pos)) /* Assignment of value for BUSYCH8 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH9_Pos              _UINT32_(9)                                          /* (EVSYS_BUSYCH) Busy Channel 9 Position */
+#define EVSYS_BUSYCH_BUSYCH9_Msk              (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH9_Pos)          /* (EVSYS_BUSYCH) Busy Channel 9 Mask */
+#define EVSYS_BUSYCH_BUSYCH9(value)           (EVSYS_BUSYCH_BUSYCH9_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH9_Pos)) /* Assignment of value for BUSYCH9 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH10_Pos             _UINT32_(10)                                         /* (EVSYS_BUSYCH) Busy Channel 10 Position */
+#define EVSYS_BUSYCH_BUSYCH10_Msk             (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH10_Pos)         /* (EVSYS_BUSYCH) Busy Channel 10 Mask */
+#define EVSYS_BUSYCH_BUSYCH10(value)          (EVSYS_BUSYCH_BUSYCH10_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH10_Pos)) /* Assignment of value for BUSYCH10 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_BUSYCH11_Pos             _UINT32_(11)                                         /* (EVSYS_BUSYCH) Busy Channel 11 Position */
+#define EVSYS_BUSYCH_BUSYCH11_Msk             (_UINT32_(0x1) << EVSYS_BUSYCH_BUSYCH11_Pos)         /* (EVSYS_BUSYCH) Busy Channel 11 Mask */
+#define EVSYS_BUSYCH_BUSYCH11(value)          (EVSYS_BUSYCH_BUSYCH11_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH11_Pos)) /* Assignment of value for BUSYCH11 in the EVSYS_BUSYCH register */
+#define EVSYS_BUSYCH_Msk                      _UINT32_(0x00000FFF)                                 /* (EVSYS_BUSYCH) Register Mask  */
+
+#define EVSYS_BUSYCH_BUSYCH_Pos               _UINT32_(0)                                          /* (EVSYS_BUSYCH Position) Busy Channel xx */
+#define EVSYS_BUSYCH_BUSYCH_Msk               (_UINT32_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos)         /* (EVSYS_BUSYCH Mask) BUSYCH */
+#define EVSYS_BUSYCH_BUSYCH(value)            (EVSYS_BUSYCH_BUSYCH_Msk & (_UINT32_(value) << EVSYS_BUSYCH_BUSYCH_Pos)) 
+
+/* -------- EVSYS_READYUSR : (EVSYS Offset: 0x1C) ( R/ 32) Ready Users -------- */
+#define EVSYS_READYUSR_RESETVALUE             _UINT32_(0xFFF)                                      /*  (EVSYS_READYUSR) Ready Users  Reset Value */
+
+#define EVSYS_READYUSR_READYUSR0_Pos          _UINT32_(0)                                          /* (EVSYS_READYUSR) Ready User for Channel 0 Position */
+#define EVSYS_READYUSR_READYUSR0_Msk          (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR0_Pos)      /* (EVSYS_READYUSR) Ready User for Channel 0 Mask */
+#define EVSYS_READYUSR_READYUSR0(value)       (EVSYS_READYUSR_READYUSR0_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR0_Pos)) /* Assignment of value for READYUSR0 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR1_Pos          _UINT32_(1)                                          /* (EVSYS_READYUSR) Ready User for Channel 1 Position */
+#define EVSYS_READYUSR_READYUSR1_Msk          (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR1_Pos)      /* (EVSYS_READYUSR) Ready User for Channel 1 Mask */
+#define EVSYS_READYUSR_READYUSR1(value)       (EVSYS_READYUSR_READYUSR1_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR1_Pos)) /* Assignment of value for READYUSR1 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR2_Pos          _UINT32_(2)                                          /* (EVSYS_READYUSR) Ready User for Channel 2 Position */
+#define EVSYS_READYUSR_READYUSR2_Msk          (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR2_Pos)      /* (EVSYS_READYUSR) Ready User for Channel 2 Mask */
+#define EVSYS_READYUSR_READYUSR2(value)       (EVSYS_READYUSR_READYUSR2_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR2_Pos)) /* Assignment of value for READYUSR2 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR3_Pos          _UINT32_(3)                                          /* (EVSYS_READYUSR) Ready User for Channel 3 Position */
+#define EVSYS_READYUSR_READYUSR3_Msk          (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR3_Pos)      /* (EVSYS_READYUSR) Ready User for Channel 3 Mask */
+#define EVSYS_READYUSR_READYUSR3(value)       (EVSYS_READYUSR_READYUSR3_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR3_Pos)) /* Assignment of value for READYUSR3 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR4_Pos          _UINT32_(4)                                          /* (EVSYS_READYUSR) Ready User for Channel 4 Position */
+#define EVSYS_READYUSR_READYUSR4_Msk          (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR4_Pos)      /* (EVSYS_READYUSR) Ready User for Channel 4 Mask */
+#define EVSYS_READYUSR_READYUSR4(value)       (EVSYS_READYUSR_READYUSR4_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR4_Pos)) /* Assignment of value for READYUSR4 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR5_Pos          _UINT32_(5)                                          /* (EVSYS_READYUSR) Ready User for Channel 5 Position */
+#define EVSYS_READYUSR_READYUSR5_Msk          (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR5_Pos)      /* (EVSYS_READYUSR) Ready User for Channel 5 Mask */
+#define EVSYS_READYUSR_READYUSR5(value)       (EVSYS_READYUSR_READYUSR5_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR5_Pos)) /* Assignment of value for READYUSR5 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR6_Pos          _UINT32_(6)                                          /* (EVSYS_READYUSR) Ready User for Channel 6 Position */
+#define EVSYS_READYUSR_READYUSR6_Msk          (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR6_Pos)      /* (EVSYS_READYUSR) Ready User for Channel 6 Mask */
+#define EVSYS_READYUSR_READYUSR6(value)       (EVSYS_READYUSR_READYUSR6_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR6_Pos)) /* Assignment of value for READYUSR6 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR7_Pos          _UINT32_(7)                                          /* (EVSYS_READYUSR) Ready User for Channel 7 Position */
+#define EVSYS_READYUSR_READYUSR7_Msk          (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR7_Pos)      /* (EVSYS_READYUSR) Ready User for Channel 7 Mask */
+#define EVSYS_READYUSR_READYUSR7(value)       (EVSYS_READYUSR_READYUSR7_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR7_Pos)) /* Assignment of value for READYUSR7 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR8_Pos          _UINT32_(8)                                          /* (EVSYS_READYUSR) Ready User for Channel 8 Position */
+#define EVSYS_READYUSR_READYUSR8_Msk          (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR8_Pos)      /* (EVSYS_READYUSR) Ready User for Channel 8 Mask */
+#define EVSYS_READYUSR_READYUSR8(value)       (EVSYS_READYUSR_READYUSR8_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR8_Pos)) /* Assignment of value for READYUSR8 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR9_Pos          _UINT32_(9)                                          /* (EVSYS_READYUSR) Ready User for Channel 9 Position */
+#define EVSYS_READYUSR_READYUSR9_Msk          (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR9_Pos)      /* (EVSYS_READYUSR) Ready User for Channel 9 Mask */
+#define EVSYS_READYUSR_READYUSR9(value)       (EVSYS_READYUSR_READYUSR9_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR9_Pos)) /* Assignment of value for READYUSR9 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR10_Pos         _UINT32_(10)                                         /* (EVSYS_READYUSR) Ready User for Channel 10 Position */
+#define EVSYS_READYUSR_READYUSR10_Msk         (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR10_Pos)     /* (EVSYS_READYUSR) Ready User for Channel 10 Mask */
+#define EVSYS_READYUSR_READYUSR10(value)      (EVSYS_READYUSR_READYUSR10_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR10_Pos)) /* Assignment of value for READYUSR10 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_READYUSR11_Pos         _UINT32_(11)                                         /* (EVSYS_READYUSR) Ready User for Channel 11 Position */
+#define EVSYS_READYUSR_READYUSR11_Msk         (_UINT32_(0x1) << EVSYS_READYUSR_READYUSR11_Pos)     /* (EVSYS_READYUSR) Ready User for Channel 11 Mask */
+#define EVSYS_READYUSR_READYUSR11(value)      (EVSYS_READYUSR_READYUSR11_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR11_Pos)) /* Assignment of value for READYUSR11 in the EVSYS_READYUSR register */
+#define EVSYS_READYUSR_Msk                    _UINT32_(0x00000FFF)                                 /* (EVSYS_READYUSR) Register Mask  */
+
+#define EVSYS_READYUSR_READYUSR_Pos           _UINT32_(0)                                          /* (EVSYS_READYUSR Position) Ready User for Channel xx */
+#define EVSYS_READYUSR_READYUSR_Msk           (_UINT32_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos)     /* (EVSYS_READYUSR Mask) READYUSR */
+#define EVSYS_READYUSR_READYUSR(value)        (EVSYS_READYUSR_READYUSR_Msk & (_UINT32_(value) << EVSYS_READYUSR_READYUSR_Pos)) 
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 8) User Multiplexer n -------- */
+#define EVSYS_USER_RESETVALUE                 _UINT8_(0x00)                                        /*  (EVSYS_USER) User Multiplexer n  Reset Value */
+
+#define EVSYS_USER_CHANNEL_Pos                _UINT8_(0)                                           /* (EVSYS_USER) Channel Event Selection Position */
+#define EVSYS_USER_CHANNEL_Msk                (_UINT8_(0xF) << EVSYS_USER_CHANNEL_Pos)             /* (EVSYS_USER) Channel Event Selection Mask */
+#define EVSYS_USER_CHANNEL(value)             (EVSYS_USER_CHANNEL_Msk & (_UINT8_(value) << EVSYS_USER_CHANNEL_Pos)) /* Assignment of value for CHANNEL in the EVSYS_USER register */
+#define EVSYS_USER_Msk                        _UINT8_(0x0F)                                        /* (EVSYS_USER) Register Mask  */
+
+
+/* EVSYS register offsets definitions */
+#define EVSYS_CHANNEL_REG_OFST         _UINT32_(0x00)      /* (EVSYS_CHANNEL) Channel n Control Offset */
+#define EVSYS_CHINTENCLR_REG_OFST      _UINT32_(0x04)      /* (EVSYS_CHINTENCLR) Channel n Interrupt Enable Clear Offset */
+#define EVSYS_CHINTENSET_REG_OFST      _UINT32_(0x05)      /* (EVSYS_CHINTENSET) Channel n Interrupt Enable Set Offset */
+#define EVSYS_CHINTFLAG_REG_OFST       _UINT32_(0x06)      /* (EVSYS_CHINTFLAG) Channel n Interrupt Flag Status and Clear Offset */
+#define EVSYS_CHSTATUS_REG_OFST        _UINT32_(0x07)      /* (EVSYS_CHSTATUS) Channel n Status Offset */
+#define EVSYS_CTRLA_REG_OFST           _UINT32_(0x00)      /* (EVSYS_CTRLA) Control Offset */
+#define EVSYS_SWEVT_REG_OFST           _UINT32_(0x04)      /* (EVSYS_SWEVT) Software Event Offset */
+#define EVSYS_PRICTRL_REG_OFST         _UINT32_(0x08)      /* (EVSYS_PRICTRL) Priority Control Offset */
+#define EVSYS_INTPEND_REG_OFST         _UINT32_(0x10)      /* (EVSYS_INTPEND) Channel Pending Interrupt Offset */
+#define EVSYS_INTSTATUS_REG_OFST       _UINT32_(0x14)      /* (EVSYS_INTSTATUS) Interrupt Status Offset */
+#define EVSYS_BUSYCH_REG_OFST          _UINT32_(0x18)      /* (EVSYS_BUSYCH) Busy Channels Offset */
+#define EVSYS_READYUSR_REG_OFST        _UINT32_(0x1C)      /* (EVSYS_READYUSR) Ready Users Offset */
+#define EVSYS_USER_REG_OFST            _UINT32_(0x120)     /* (EVSYS_USER) User Multiplexer n Offset */
+#define EVSYS_USER0_REG_OFST           _UINT32_(0x120)     /* (EVSYS_USER0) User Multiplexer n Offset */
+#define EVSYS_USER1_REG_OFST           _UINT32_(0x121)     /* (EVSYS_USER1) User Multiplexer n Offset */
+#define EVSYS_USER2_REG_OFST           _UINT32_(0x122)     /* (EVSYS_USER2) User Multiplexer n Offset */
+#define EVSYS_USER3_REG_OFST           _UINT32_(0x123)     /* (EVSYS_USER3) User Multiplexer n Offset */
+#define EVSYS_USER4_REG_OFST           _UINT32_(0x124)     /* (EVSYS_USER4) User Multiplexer n Offset */
+#define EVSYS_USER5_REG_OFST           _UINT32_(0x125)     /* (EVSYS_USER5) User Multiplexer n Offset */
+#define EVSYS_USER6_REG_OFST           _UINT32_(0x126)     /* (EVSYS_USER6) User Multiplexer n Offset */
+#define EVSYS_USER7_REG_OFST           _UINT32_(0x127)     /* (EVSYS_USER7) User Multiplexer n Offset */
+#define EVSYS_USER8_REG_OFST           _UINT32_(0x128)     /* (EVSYS_USER8) User Multiplexer n Offset */
+#define EVSYS_USER9_REG_OFST           _UINT32_(0x129)     /* (EVSYS_USER9) User Multiplexer n Offset */
+#define EVSYS_USER10_REG_OFST          _UINT32_(0x12A)     /* (EVSYS_USER10) User Multiplexer n Offset */
+#define EVSYS_USER11_REG_OFST          _UINT32_(0x12B)     /* (EVSYS_USER11) User Multiplexer n Offset */
+#define EVSYS_USER12_REG_OFST          _UINT32_(0x12C)     /* (EVSYS_USER12) User Multiplexer n Offset */
+#define EVSYS_USER13_REG_OFST          _UINT32_(0x12D)     /* (EVSYS_USER13) User Multiplexer n Offset */
+#define EVSYS_USER14_REG_OFST          _UINT32_(0x12E)     /* (EVSYS_USER14) User Multiplexer n Offset */
+#define EVSYS_USER15_REG_OFST          _UINT32_(0x12F)     /* (EVSYS_USER15) User Multiplexer n Offset */
+#define EVSYS_USER16_REG_OFST          _UINT32_(0x130)     /* (EVSYS_USER16) User Multiplexer n Offset */
+#define EVSYS_USER17_REG_OFST          _UINT32_(0x131)     /* (EVSYS_USER17) User Multiplexer n Offset */
+#define EVSYS_USER18_REG_OFST          _UINT32_(0x132)     /* (EVSYS_USER18) User Multiplexer n Offset */
+#define EVSYS_USER19_REG_OFST          _UINT32_(0x133)     /* (EVSYS_USER19) User Multiplexer n Offset */
+#define EVSYS_USER20_REG_OFST          _UINT32_(0x134)     /* (EVSYS_USER20) User Multiplexer n Offset */
+#define EVSYS_USER21_REG_OFST          _UINT32_(0x135)     /* (EVSYS_USER21) User Multiplexer n Offset */
+#define EVSYS_USER22_REG_OFST          _UINT32_(0x136)     /* (EVSYS_USER22) User Multiplexer n Offset */
+#define EVSYS_USER23_REG_OFST          _UINT32_(0x137)     /* (EVSYS_USER23) User Multiplexer n Offset */
+#define EVSYS_USER24_REG_OFST          _UINT32_(0x138)     /* (EVSYS_USER24) User Multiplexer n Offset */
+#define EVSYS_USER25_REG_OFST          _UINT32_(0x139)     /* (EVSYS_USER25) User Multiplexer n Offset */
+#define EVSYS_USER26_REG_OFST          _UINT32_(0x13A)     /* (EVSYS_USER26) User Multiplexer n Offset */
+#define EVSYS_USER27_REG_OFST          _UINT32_(0x13B)     /* (EVSYS_USER27) User Multiplexer n Offset */
+#define EVSYS_USER28_REG_OFST          _UINT32_(0x13C)     /* (EVSYS_USER28) User Multiplexer n Offset */
+#define EVSYS_USER29_REG_OFST          _UINT32_(0x13D)     /* (EVSYS_USER29) User Multiplexer n Offset */
+#define EVSYS_USER30_REG_OFST          _UINT32_(0x13E)     /* (EVSYS_USER30) User Multiplexer n Offset */
+#define EVSYS_USER31_REG_OFST          _UINT32_(0x13F)     /* (EVSYS_USER31) User Multiplexer n Offset */
+#define EVSYS_USER32_REG_OFST          _UINT32_(0x140)     /* (EVSYS_USER32) User Multiplexer n Offset */
+#define EVSYS_USER33_REG_OFST          _UINT32_(0x141)     /* (EVSYS_USER33) User Multiplexer n Offset */
+#define EVSYS_USER34_REG_OFST          _UINT32_(0x142)     /* (EVSYS_USER34) User Multiplexer n Offset */
+#define EVSYS_USER35_REG_OFST          _UINT32_(0x143)     /* (EVSYS_USER35) User Multiplexer n Offset */
+#define EVSYS_USER36_REG_OFST          _UINT32_(0x144)     /* (EVSYS_USER36) User Multiplexer n Offset */
+#define EVSYS_USER37_REG_OFST          _UINT32_(0x145)     /* (EVSYS_USER37) User Multiplexer n Offset */
+#define EVSYS_USER38_REG_OFST          _UINT32_(0x146)     /* (EVSYS_USER38) User Multiplexer n Offset */
+#define EVSYS_USER39_REG_OFST          _UINT32_(0x147)     /* (EVSYS_USER39) User Multiplexer n Offset */
+#define EVSYS_USER40_REG_OFST          _UINT32_(0x148)     /* (EVSYS_USER40) User Multiplexer n Offset */
+#define EVSYS_USER41_REG_OFST          _UINT32_(0x149)     /* (EVSYS_USER41) User Multiplexer n Offset */
+#define EVSYS_USER42_REG_OFST          _UINT32_(0x14A)     /* (EVSYS_USER42) User Multiplexer n Offset */
+#define EVSYS_USER43_REG_OFST          _UINT32_(0x14B)     /* (EVSYS_USER43) User Multiplexer n Offset */
+#define EVSYS_USER44_REG_OFST          _UINT32_(0x14C)     /* (EVSYS_USER44) User Multiplexer n Offset */
+#define EVSYS_USER45_REG_OFST          _UINT32_(0x14D)     /* (EVSYS_USER45) User Multiplexer n Offset */
+#define EVSYS_USER46_REG_OFST          _UINT32_(0x14E)     /* (EVSYS_USER46) User Multiplexer n Offset */
+#define EVSYS_USER47_REG_OFST          _UINT32_(0x14F)     /* (EVSYS_USER47) User Multiplexer n Offset */
+#define EVSYS_USER48_REG_OFST          _UINT32_(0x150)     /* (EVSYS_USER48) User Multiplexer n Offset */
+#define EVSYS_USER49_REG_OFST          _UINT32_(0x151)     /* (EVSYS_USER49) User Multiplexer n Offset */
+#define EVSYS_USER50_REG_OFST          _UINT32_(0x152)     /* (EVSYS_USER50) User Multiplexer n Offset */
+#define EVSYS_USER51_REG_OFST          _UINT32_(0x153)     /* (EVSYS_USER51) User Multiplexer n Offset */
+#define EVSYS_USER52_REG_OFST          _UINT32_(0x154)     /* (EVSYS_USER52) User Multiplexer n Offset */
+#define EVSYS_USER53_REG_OFST          _UINT32_(0x155)     /* (EVSYS_USER53) User Multiplexer n Offset */
+#define EVSYS_USER54_REG_OFST          _UINT32_(0x156)     /* (EVSYS_USER54) User Multiplexer n Offset */
+#define EVSYS_USER55_REG_OFST          _UINT32_(0x157)     /* (EVSYS_USER55) User Multiplexer n Offset */
+#define EVSYS_USER56_REG_OFST          _UINT32_(0x158)     /* (EVSYS_USER56) User Multiplexer n Offset */
+#define EVSYS_USER57_REG_OFST          _UINT32_(0x159)     /* (EVSYS_USER57) User Multiplexer n Offset */
+#define EVSYS_USER58_REG_OFST          _UINT32_(0x15A)     /* (EVSYS_USER58) User Multiplexer n Offset */
+#define EVSYS_USER59_REG_OFST          _UINT32_(0x15B)     /* (EVSYS_USER59) User Multiplexer n Offset */
+#define EVSYS_USER60_REG_OFST          _UINT32_(0x15C)     /* (EVSYS_USER60) User Multiplexer n Offset */
+#define EVSYS_USER61_REG_OFST          _UINT32_(0x15D)     /* (EVSYS_USER61) User Multiplexer n Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* CHANNEL register API structure */
+typedef struct
+{
+  __IO  uint32_t                       EVSYS_CHANNEL;      /* Offset: 0x00 (R/W  32) Channel n Control */
+  __IO  uint8_t                        EVSYS_CHINTENCLR;   /* Offset: 0x04 (R/W  8) Channel n Interrupt Enable Clear */
+  __IO  uint8_t                        EVSYS_CHINTENSET;   /* Offset: 0x05 (R/W  8) Channel n Interrupt Enable Set */
+  __IO  uint8_t                        EVSYS_CHINTFLAG;    /* Offset: 0x06 (R/W  8) Channel n Interrupt Flag Status and Clear */
+  __I   uint8_t                        EVSYS_CHSTATUS;     /* Offset: 0x07 (R/   8) Channel n Status */
+} evsys_channel_registers_t;
+
+#define EVSYS_CHANNEL_NUMBER 12
+
+/* EVSYS register API structure */
+typedef struct
+{  /* Event System Interface */
+  __O   uint8_t                        EVSYS_CTRLA;        /* Offset: 0x00 ( /W  8) Control */
+  __I   uint8_t                        Reserved1[0x03];
+  __O   uint32_t                       EVSYS_SWEVT;        /* Offset: 0x04 ( /W  32) Software Event */
+  __IO  uint8_t                        EVSYS_PRICTRL;      /* Offset: 0x08 (R/W  8) Priority Control */
+  __I   uint8_t                        Reserved2[0x07];
+  __IO  uint16_t                       EVSYS_INTPEND;      /* Offset: 0x10 (R/W  16) Channel Pending Interrupt */
+  __I   uint8_t                        Reserved3[0x02];
+  __I   uint32_t                       EVSYS_INTSTATUS;    /* Offset: 0x14 (R/   32) Interrupt Status */
+  __I   uint32_t                       EVSYS_BUSYCH;       /* Offset: 0x18 (R/   32) Busy Channels */
+  __I   uint32_t                       EVSYS_READYUSR;     /* Offset: 0x1C (R/   32) Ready Users */
+        evsys_channel_registers_t      CHANNEL[EVSYS_CHANNEL_NUMBER]; /* Offset: 0x20  */
+  __I   uint8_t                        Reserved4[0xA0];
+  __IO  uint8_t                        EVSYS_USER[62];     /* Offset: 0x120 (R/W  8) User Multiplexer n */
+} evsys_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_EVSYS_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/fcr.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/fcr.h
new file mode 100644
index 00000000..f8faaf78
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/fcr.h
@@ -0,0 +1,807 @@
+/*
+ * Component description for FCR
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_FCR_COMPONENT_H_
+#define _PIC32CMGC00_FCR_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR FCR                       */
+/* ************************************************************************** */
+
+/* -------- FCR_CTRLA : (FCR Offset: 0x00) (R/W 32) CTRL A REGISTER -------- */
+#define FCR_CTRLA_RESETVALUE                  _UINT32_(0x8000)                                     /*  (FCR_CTRLA) CTRL A REGISTER  Reset Value */
+
+#define FCR_CTRLA_PRIV_Pos                    _UINT32_(2)                                          /* (FCR_CTRLA) Privileged Access Only Position */
+#define FCR_CTRLA_PRIV_Msk                    (_UINT32_(0x1) << FCR_CTRLA_PRIV_Pos)                /* (FCR_CTRLA) Privileged Access Only Mask */
+#define FCR_CTRLA_PRIV(value)                 (FCR_CTRLA_PRIV_Msk & (_UINT32_(value) << FCR_CTRLA_PRIV_Pos)) /* Assignment of value for PRIV in the FCR_CTRLA register */
+#define   FCR_CTRLA_PRIV_DISABLE_Val          _UINT32_(0x0)                                        /* (FCR_CTRLA) Macro register accessible in privileged and unprivileged accesses.  */
+#define   FCR_CTRLA_PRIV_ENABLE_Val           _UINT32_(0x1)                                        /* (FCR_CTRLA) Macro registers only accessible in privileged accesses  */
+#define FCR_CTRLA_PRIV_DISABLE                (FCR_CTRLA_PRIV_DISABLE_Val << FCR_CTRLA_PRIV_Pos)   /* (FCR_CTRLA) Macro register accessible in privileged and unprivileged accesses. Position */
+#define FCR_CTRLA_PRIV_ENABLE                 (FCR_CTRLA_PRIV_ENABLE_Val << FCR_CTRLA_PRIV_Pos)    /* (FCR_CTRLA) Macro registers only accessible in privileged accesses Position */
+#define FCR_CTRLA_FWS_Pos                     _UINT32_(8)                                          /* (FCR_CTRLA) Flash Access Time Defined in terms of AHB Clock Wait States Position */
+#define FCR_CTRLA_FWS_Msk                     (_UINT32_(0xF) << FCR_CTRLA_FWS_Pos)                 /* (FCR_CTRLA) Flash Access Time Defined in terms of AHB Clock Wait States Mask */
+#define FCR_CTRLA_FWS(value)                  (FCR_CTRLA_FWS_Msk & (_UINT32_(value) << FCR_CTRLA_FWS_Pos)) /* Assignment of value for FWS in the FCR_CTRLA register */
+#define   FCR_CTRLA_FWS_0_Val                 _UINT32_(0x0)                                        /* (FCR_CTRLA) Zero Wait States  */
+#define   FCR_CTRLA_FWS_1_Val                 _UINT32_(0x1)                                        /* (FCR_CTRLA) One Wait State  */
+#define   FCR_CTRLA_FWS_14_Val                _UINT32_(0xE)                                        /* (FCR_CTRLA) Fourteen Wait States  */
+#define   FCR_CTRLA_FWS_15_Val                _UINT32_(0xF)                                        /* (FCR_CTRLA) Fifteen Wait States  */
+#define FCR_CTRLA_FWS_0                       (FCR_CTRLA_FWS_0_Val << FCR_CTRLA_FWS_Pos)           /* (FCR_CTRLA) Zero Wait States Position */
+#define FCR_CTRLA_FWS_1                       (FCR_CTRLA_FWS_1_Val << FCR_CTRLA_FWS_Pos)           /* (FCR_CTRLA) One Wait State Position */
+#define FCR_CTRLA_FWS_14                      (FCR_CTRLA_FWS_14_Val << FCR_CTRLA_FWS_Pos)          /* (FCR_CTRLA) Fourteen Wait States Position */
+#define FCR_CTRLA_FWS_15                      (FCR_CTRLA_FWS_15_Val << FCR_CTRLA_FWS_Pos)          /* (FCR_CTRLA) Fifteen Wait States Position */
+#define FCR_CTRLA_ADRWS_Pos                   _UINT32_(14)                                         /* (FCR_CTRLA) Address Wait State Enable Position */
+#define FCR_CTRLA_ADRWS_Msk                   (_UINT32_(0x1) << FCR_CTRLA_ADRWS_Pos)               /* (FCR_CTRLA) Address Wait State Enable Mask */
+#define FCR_CTRLA_ADRWS(value)                (FCR_CTRLA_ADRWS_Msk & (_UINT32_(value) << FCR_CTRLA_ADRWS_Pos)) /* Assignment of value for ADRWS in the FCR_CTRLA register */
+#define   FCR_CTRLA_ADRWS_ZERO_Val            _UINT32_(0x0)                                        /* (FCR_CTRLA) Add 0 Address Wait States - allowing for higher performance at lower clock frequencies  */
+#define   FCR_CTRLA_ADRWS_ONE_Val             _UINT32_(0x1)                                        /* (FCR_CTRLA) Add 1 Address Wait State - allowing for higher clock frequencies  */
+#define FCR_CTRLA_ADRWS_ZERO                  (FCR_CTRLA_ADRWS_ZERO_Val << FCR_CTRLA_ADRWS_Pos)    /* (FCR_CTRLA) Add 0 Address Wait States - allowing for higher performance at lower clock frequencies Position */
+#define FCR_CTRLA_ADRWS_ONE                   (FCR_CTRLA_ADRWS_ONE_Val << FCR_CTRLA_ADRWS_Pos)     /* (FCR_CTRLA) Add 1 Address Wait State - allowing for higher clock frequencies Position */
+#define FCR_CTRLA_AUTOWS_Pos                  _UINT32_(15)                                         /* (FCR_CTRLA) Automatic Wait State Enable. Position */
+#define FCR_CTRLA_AUTOWS_Msk                  (_UINT32_(0x1) << FCR_CTRLA_AUTOWS_Pos)              /* (FCR_CTRLA) Automatic Wait State Enable. Mask */
+#define FCR_CTRLA_AUTOWS(value)               (FCR_CTRLA_AUTOWS_Msk & (_UINT32_(value) << FCR_CTRLA_AUTOWS_Pos)) /* Assignment of value for AUTOWS in the FCR_CTRLA register */
+#define   FCR_CTRLA_AUTOWS_DISABLE_Val        _UINT32_(0x0)                                        /* (FCR_CTRLA) Use FWS: Total flash wait states are ADRWS + FWS  */
+#define   FCR_CTRLA_AUTOWS_ENABLE_Val         _UINT32_(0x1)                                        /* (FCR_CTRLA) Use Automatic wait states: Total flash wait states are ADRWS + Taws  */
+#define FCR_CTRLA_AUTOWS_DISABLE              (FCR_CTRLA_AUTOWS_DISABLE_Val << FCR_CTRLA_AUTOWS_Pos) /* (FCR_CTRLA) Use FWS: Total flash wait states are ADRWS + FWS Position */
+#define FCR_CTRLA_AUTOWS_ENABLE               (FCR_CTRLA_AUTOWS_ENABLE_Val << FCR_CTRLA_AUTOWS_Pos) /* (FCR_CTRLA) Use Automatic wait states: Total flash wait states are ADRWS + Taws Position */
+#define FCR_CTRLA_RDBUFWS_Pos                 _UINT32_(16)                                         /* (FCR_CTRLA) Read Buffer Wait StatesPer AHB port control of deterministic or zero wait state read buffer access. Position */
+#define FCR_CTRLA_RDBUFWS_Msk                 (_UINT32_(0x1) << FCR_CTRLA_RDBUFWS_Pos)             /* (FCR_CTRLA) Read Buffer Wait StatesPer AHB port control of deterministic or zero wait state read buffer access. Mask */
+#define FCR_CTRLA_RDBUFWS(value)              (FCR_CTRLA_RDBUFWS_Msk & (_UINT32_(value) << FCR_CTRLA_RDBUFWS_Pos)) /* Assignment of value for RDBUFWS in the FCR_CTRLA register */
+#define   FCR_CTRLA_RDBUFWS_ZEROWS_Val        _UINT32_(0x0)                                        /* (FCR_CTRLA) 0 Wait States  */
+#define   FCR_CTRLA_RDBUFWS_DETERMINISTIC_Val _UINT32_(0x1)                                        /* (FCR_CTRLA) ADRWS + FWS wait state for hits to AHB read buffer  */
+#define FCR_CTRLA_RDBUFWS_ZEROWS              (FCR_CTRLA_RDBUFWS_ZEROWS_Val << FCR_CTRLA_RDBUFWS_Pos) /* (FCR_CTRLA) 0 Wait States Position */
+#define FCR_CTRLA_RDBUFWS_DETERMINISTIC       (FCR_CTRLA_RDBUFWS_DETERMINISTIC_Val << FCR_CTRLA_RDBUFWS_Pos) /* (FCR_CTRLA) ADRWS + FWS wait state for hits to AHB read buffer Position */
+#define FCR_CTRLA_Msk                         _UINT32_(0x0001CF04)                                 /* (FCR_CTRLA) Register Mask  */
+
+
+/* -------- FCR_CTRLB : (FCR Offset: 0x04) (R/W 32) CTRL B REGISTER -------- */
+#define FCR_CTRLB_RESETVALUE                  _UINT32_(0x00)                                       /*  (FCR_CTRLB) CTRL B REGISTER  Reset Value */
+
+#define FCR_CTRLB_PRM_Pos                     _UINT32_(0)                                          /* (FCR_CTRLB) Set NVM Power Reduction Mode Position */
+#define FCR_CTRLB_PRM_Msk                     (_UINT32_(0x1) << FCR_CTRLB_PRM_Pos)                 /* (FCR_CTRLB) Set NVM Power Reduction Mode Mask */
+#define FCR_CTRLB_PRM(value)                  (FCR_CTRLB_PRM_Msk & (_UINT32_(value) << FCR_CTRLB_PRM_Pos)) /* Assignment of value for PRM in the FCR_CTRLB register */
+#define   FCR_CTRLB_PRM_NONE_Val              _UINT32_(0x0)                                        /* (FCR_CTRLB) No Action  */
+#define   FCR_CTRLB_PRM_TOGGLE_Val            _UINT32_(0x1)                                        /* (FCR_CTRLB) Toggle the Flash Power Mode  */
+#define FCR_CTRLB_PRM_NONE                    (FCR_CTRLB_PRM_NONE_Val << FCR_CTRLB_PRM_Pos)        /* (FCR_CTRLB) No Action Position */
+#define FCR_CTRLB_PRM_TOGGLE                  (FCR_CTRLB_PRM_TOGGLE_Val << FCR_CTRLB_PRM_Pos)      /* (FCR_CTRLB) Toggle the Flash Power Mode Position */
+#define FCR_CTRLB_CHEINV_Pos                  _UINT32_(7)                                          /* (FCR_CTRLB) Cache InvalidateCache invalidation takes 1 clock cycle, but may be delayed by an active read. Position */
+#define FCR_CTRLB_CHEINV_Msk                  (_UINT32_(0x1) << FCR_CTRLB_CHEINV_Pos)              /* (FCR_CTRLB) Cache InvalidateCache invalidation takes 1 clock cycle, but may be delayed by an active read. Mask */
+#define FCR_CTRLB_CHEINV(value)               (FCR_CTRLB_CHEINV_Msk & (_UINT32_(value) << FCR_CTRLB_CHEINV_Pos)) /* Assignment of value for CHEINV in the FCR_CTRLB register */
+#define   FCR_CTRLB_CHEINV_NONE_Val           _UINT32_(0x0)                                        /* (FCR_CTRLB) No Action  */
+#define   FCR_CTRLB_CHEINV_INV_Val            _UINT32_(0x1)                                        /* (FCR_CTRLB) Invalidate Cache  */
+#define FCR_CTRLB_CHEINV_NONE                 (FCR_CTRLB_CHEINV_NONE_Val << FCR_CTRLB_CHEINV_Pos)  /* (FCR_CTRLB) No Action Position */
+#define FCR_CTRLB_CHEINV_INV                  (FCR_CTRLB_CHEINV_INV_Val << FCR_CTRLB_CHEINV_Pos)   /* (FCR_CTRLB) Invalidate Cache Position */
+#define FCR_CTRLB_SLP_Pos                     _UINT32_(8)                                          /* (FCR_CTRLB) NVM Power Reduction Mode selection during System Standby Sleep Position */
+#define FCR_CTRLB_SLP_Msk                     (_UINT32_(0x3) << FCR_CTRLB_SLP_Pos)                 /* (FCR_CTRLB) NVM Power Reduction Mode selection during System Standby Sleep Mask */
+#define FCR_CTRLB_SLP(value)                  (FCR_CTRLB_SLP_Msk & (_UINT32_(value) << FCR_CTRLB_SLP_Pos)) /* Assignment of value for SLP in the FCR_CTRLB register */
+#define   FCR_CTRLB_SLP_MANUAL_Val            _UINT32_(0x0)                                        /* (FCR_CTRLB) Maintain state of STATUS.PRM on entry to Standby  */
+#define   FCR_CTRLB_SLP_RSVD01_Val            _UINT32_(0x1)                                        /* (FCR_CTRLB) RSVD  */
+#define   FCR_CTRLB_SLP_AUTOFAST_Val          _UINT32_(0x2)                                        /* (FCR_CTRLB) Enter Flash Hibernate on entry to Standby w/ wakeup to Auto Standby  */
+#define   FCR_CTRLB_SLP_AUTOSLOW_Val          _UINT32_(0x3)                                        /* (FCR_CTRLB) Enter Flash Hibernate on entry to Standby w/ wakeup on first access  */
+#define FCR_CTRLB_SLP_MANUAL                  (FCR_CTRLB_SLP_MANUAL_Val << FCR_CTRLB_SLP_Pos)      /* (FCR_CTRLB) Maintain state of STATUS.PRM on entry to Standby Position */
+#define FCR_CTRLB_SLP_RSVD01                  (FCR_CTRLB_SLP_RSVD01_Val << FCR_CTRLB_SLP_Pos)      /* (FCR_CTRLB) RSVD Position */
+#define FCR_CTRLB_SLP_AUTOFAST                (FCR_CTRLB_SLP_AUTOFAST_Val << FCR_CTRLB_SLP_Pos)    /* (FCR_CTRLB) Enter Flash Hibernate on entry to Standby w/ wakeup to Auto Standby Position */
+#define FCR_CTRLB_SLP_AUTOSLOW                (FCR_CTRLB_SLP_AUTOSLOW_Val << FCR_CTRLB_SLP_Pos)    /* (FCR_CTRLB) Enter Flash Hibernate on entry to Standby w/ wakeup on first access Position */
+#define FCR_CTRLB_CHEDIS_Pos                  _UINT32_(16)                                         /* (FCR_CTRLB) Cache Disable Position */
+#define FCR_CTRLB_CHEDIS_Msk                  (_UINT32_(0x1) << FCR_CTRLB_CHEDIS_Pos)              /* (FCR_CTRLB) Cache Disable Mask */
+#define FCR_CTRLB_CHEDIS(value)               (FCR_CTRLB_CHEDIS_Msk & (_UINT32_(value) << FCR_CTRLB_CHEDIS_Pos)) /* Assignment of value for CHEDIS in the FCR_CTRLB register */
+#define   FCR_CTRLB_CHEDIS_ENABLE_Val         _UINT32_(0x0)                                        /* (FCR_CTRLB) Cache Enabled; Accesses to flash use AUTOWS/FSW selection.  */
+#define   FCR_CTRLB_CHEDIS_DISABLE_Val        _UINT32_(0x1)                                        /* (FCR_CTRLB) Cache Disabled; Interface uses RDBUFWS selection.  */
+#define FCR_CTRLB_CHEDIS_ENABLE               (FCR_CTRLB_CHEDIS_ENABLE_Val << FCR_CTRLB_CHEDIS_Pos) /* (FCR_CTRLB) Cache Enabled; Accesses to flash use AUTOWS/FSW selection. Position */
+#define FCR_CTRLB_CHEDIS_DISABLE              (FCR_CTRLB_CHEDIS_DISABLE_Val << FCR_CTRLB_CHEDIS_Pos) /* (FCR_CTRLB) Cache Disabled; Interface uses RDBUFWS selection. Position */
+#define FCR_CTRLB_PREFDIS_Pos                 _UINT32_(17)                                         /* (FCR_CTRLB) Prefetch Disable Position */
+#define FCR_CTRLB_PREFDIS_Msk                 (_UINT32_(0x1) << FCR_CTRLB_PREFDIS_Pos)             /* (FCR_CTRLB) Prefetch Disable Mask */
+#define FCR_CTRLB_PREFDIS(value)              (FCR_CTRLB_PREFDIS_Msk & (_UINT32_(value) << FCR_CTRLB_PREFDIS_Pos)) /* Assignment of value for PREFDIS in the FCR_CTRLB register */
+#define   FCR_CTRLB_PREFDIS_ENABLE_Val        _UINT32_(0x0)                                        /* (FCR_CTRLB) Predictive Prefetch Enabled  */
+#define   FCR_CTRLB_PREFDIS_DISABLE_Val       _UINT32_(0x1)                                        /* (FCR_CTRLB) Predictive Prefetch Disabled  */
+#define FCR_CTRLB_PREFDIS_ENABLE              (FCR_CTRLB_PREFDIS_ENABLE_Val << FCR_CTRLB_PREFDIS_Pos) /* (FCR_CTRLB) Predictive Prefetch Enabled Position */
+#define FCR_CTRLB_PREFDIS_DISABLE             (FCR_CTRLB_PREFDIS_DISABLE_Val << FCR_CTRLB_PREFDIS_Pos) /* (FCR_CTRLB) Predictive Prefetch Disabled Position */
+#define FCR_CTRLB_Msk                         _UINT32_(0x00030381)                                 /* (FCR_CTRLB) Register Mask  */
+
+
+/* -------- FCR_INTENCLR : (FCR Offset: 0x08) (R/W 32) Interrupt Enable Clear REGISTER -------- */
+#define FCR_INTENCLR_RESETVALUE               _UINT32_(0x00)                                       /*  (FCR_INTENCLR) Interrupt Enable Clear REGISTER  Reset Value */
+
+#define FCR_INTENCLR_SERR_Pos                 _UINT32_(0)                                          /* (FCR_INTENCLR) Flash SEC Interrupt Clear Enable Position */
+#define FCR_INTENCLR_SERR_Msk                 (_UINT32_(0x1) << FCR_INTENCLR_SERR_Pos)             /* (FCR_INTENCLR) Flash SEC Interrupt Clear Enable Mask */
+#define FCR_INTENCLR_SERR(value)              (FCR_INTENCLR_SERR_Msk & (_UINT32_(value) << FCR_INTENCLR_SERR_Pos)) /* Assignment of value for SERR in the FCR_INTENCLR register */
+#define   FCR_INTENCLR_SERR_0_Val             _UINT32_(0x0)                                        /* (FCR_INTENCLR) Interrupt Disabled  */
+#define   FCR_INTENCLR_SERR_1_Val             _UINT32_(0x1)                                        /* (FCR_INTENCLR) Interrupt Enabled  */
+#define FCR_INTENCLR_SERR_0                   (FCR_INTENCLR_SERR_0_Val << FCR_INTENCLR_SERR_Pos)   /* (FCR_INTENCLR) Interrupt Disabled Position */
+#define FCR_INTENCLR_SERR_1                   (FCR_INTENCLR_SERR_1_Val << FCR_INTENCLR_SERR_Pos)   /* (FCR_INTENCLR) Interrupt Enabled Position */
+#define FCR_INTENCLR_CRCDONE_Pos              _UINT32_(8)                                          /* (FCR_INTENCLR) CRC Calculation Done Clear Enable Position */
+#define FCR_INTENCLR_CRCDONE_Msk              (_UINT32_(0x1) << FCR_INTENCLR_CRCDONE_Pos)          /* (FCR_INTENCLR) CRC Calculation Done Clear Enable Mask */
+#define FCR_INTENCLR_CRCDONE(value)           (FCR_INTENCLR_CRCDONE_Msk & (_UINT32_(value) << FCR_INTENCLR_CRCDONE_Pos)) /* Assignment of value for CRCDONE in the FCR_INTENCLR register */
+#define   FCR_INTENCLR_CRCDONE_0_Val          _UINT32_(0x0)                                        /* (FCR_INTENCLR) Interrupt Disabled  */
+#define   FCR_INTENCLR_CRCDONE_1_Val          _UINT32_(0x1)                                        /* (FCR_INTENCLR) Interrupt Enabled  */
+#define FCR_INTENCLR_CRCDONE_0                (FCR_INTENCLR_CRCDONE_0_Val << FCR_INTENCLR_CRCDONE_Pos) /* (FCR_INTENCLR) Interrupt Disabled Position */
+#define FCR_INTENCLR_CRCDONE_1                (FCR_INTENCLR_CRCDONE_1_Val << FCR_INTENCLR_CRCDONE_Pos) /* (FCR_INTENCLR) Interrupt Enabled Position */
+#define FCR_INTENCLR_CRCERR_Pos               _UINT32_(9)                                          /* (FCR_INTENCLR) CRC Error Clear Enable Position */
+#define FCR_INTENCLR_CRCERR_Msk               (_UINT32_(0x1) << FCR_INTENCLR_CRCERR_Pos)           /* (FCR_INTENCLR) CRC Error Clear Enable Mask */
+#define FCR_INTENCLR_CRCERR(value)            (FCR_INTENCLR_CRCERR_Msk & (_UINT32_(value) << FCR_INTENCLR_CRCERR_Pos)) /* Assignment of value for CRCERR in the FCR_INTENCLR register */
+#define   FCR_INTENCLR_CRCERR_0_Val           _UINT32_(0x0)                                        /* (FCR_INTENCLR) Interrupt Disabled  */
+#define   FCR_INTENCLR_CRCERR_1_Val           _UINT32_(0x1)                                        /* (FCR_INTENCLR) Interrupt Enabled  */
+#define FCR_INTENCLR_CRCERR_0                 (FCR_INTENCLR_CRCERR_0_Val << FCR_INTENCLR_CRCERR_Pos) /* (FCR_INTENCLR) Interrupt Disabled Position */
+#define FCR_INTENCLR_CRCERR_1                 (FCR_INTENCLR_CRCERR_1_Val << FCR_INTENCLR_CRCERR_Pos) /* (FCR_INTENCLR) Interrupt Enabled Position */
+#define FCR_INTENCLR_FLTCAP_Pos               _UINT32_(16)                                         /* (FCR_INTENCLR) ECC Fault Capture Clear Enable Position */
+#define FCR_INTENCLR_FLTCAP_Msk               (_UINT32_(0x1) << FCR_INTENCLR_FLTCAP_Pos)           /* (FCR_INTENCLR) ECC Fault Capture Clear Enable Mask */
+#define FCR_INTENCLR_FLTCAP(value)            (FCR_INTENCLR_FLTCAP_Msk & (_UINT32_(value) << FCR_INTENCLR_FLTCAP_Pos)) /* Assignment of value for FLTCAP in the FCR_INTENCLR register */
+#define   FCR_INTENCLR_FLTCAP_0_Val           _UINT32_(0x0)                                        /* (FCR_INTENCLR) Interrupt Disabled  */
+#define   FCR_INTENCLR_FLTCAP_1_Val           _UINT32_(0x1)                                        /* (FCR_INTENCLR) Interrupt Enabled  */
+#define FCR_INTENCLR_FLTCAP_0                 (FCR_INTENCLR_FLTCAP_0_Val << FCR_INTENCLR_FLTCAP_Pos) /* (FCR_INTENCLR) Interrupt Disabled Position */
+#define FCR_INTENCLR_FLTCAP_1                 (FCR_INTENCLR_FLTCAP_1_Val << FCR_INTENCLR_FLTCAP_Pos) /* (FCR_INTENCLR) Interrupt Enabled Position */
+#define FCR_INTENCLR_Msk                      _UINT32_(0x00010301)                                 /* (FCR_INTENCLR) Register Mask  */
+
+
+/* -------- FCR_INTENSET : (FCR Offset: 0x0C) (R/W 32) Interrupt Enable SET REGISTER -------- */
+#define FCR_INTENSET_RESETVALUE               _UINT32_(0x00)                                       /*  (FCR_INTENSET) Interrupt Enable SET REGISTER  Reset Value */
+
+#define FCR_INTENSET_SERR_Pos                 _UINT32_(0)                                          /* (FCR_INTENSET) Flash SEC Interrupt Set Enable Position */
+#define FCR_INTENSET_SERR_Msk                 (_UINT32_(0x1) << FCR_INTENSET_SERR_Pos)             /* (FCR_INTENSET) Flash SEC Interrupt Set Enable Mask */
+#define FCR_INTENSET_SERR(value)              (FCR_INTENSET_SERR_Msk & (_UINT32_(value) << FCR_INTENSET_SERR_Pos)) /* Assignment of value for SERR in the FCR_INTENSET register */
+#define   FCR_INTENSET_SERR_0_Val             _UINT32_(0x0)                                        /* (FCR_INTENSET) Interrupt Disabled  */
+#define   FCR_INTENSET_SERR_1_Val             _UINT32_(0x1)                                        /* (FCR_INTENSET) Interrupt Enabled  */
+#define FCR_INTENSET_SERR_0                   (FCR_INTENSET_SERR_0_Val << FCR_INTENSET_SERR_Pos)   /* (FCR_INTENSET) Interrupt Disabled Position */
+#define FCR_INTENSET_SERR_1                   (FCR_INTENSET_SERR_1_Val << FCR_INTENSET_SERR_Pos)   /* (FCR_INTENSET) Interrupt Enabled Position */
+#define FCR_INTENSET_CRCDONE_Pos              _UINT32_(8)                                          /* (FCR_INTENSET) CRC Calculation Done Set Enable Position */
+#define FCR_INTENSET_CRCDONE_Msk              (_UINT32_(0x1) << FCR_INTENSET_CRCDONE_Pos)          /* (FCR_INTENSET) CRC Calculation Done Set Enable Mask */
+#define FCR_INTENSET_CRCDONE(value)           (FCR_INTENSET_CRCDONE_Msk & (_UINT32_(value) << FCR_INTENSET_CRCDONE_Pos)) /* Assignment of value for CRCDONE in the FCR_INTENSET register */
+#define   FCR_INTENSET_CRCDONE_0_Val          _UINT32_(0x0)                                        /* (FCR_INTENSET) Interrupt Disabled  */
+#define   FCR_INTENSET_CRCDONE_1_Val          _UINT32_(0x1)                                        /* (FCR_INTENSET) Interrupt Enabled  */
+#define FCR_INTENSET_CRCDONE_0                (FCR_INTENSET_CRCDONE_0_Val << FCR_INTENSET_CRCDONE_Pos) /* (FCR_INTENSET) Interrupt Disabled Position */
+#define FCR_INTENSET_CRCDONE_1                (FCR_INTENSET_CRCDONE_1_Val << FCR_INTENSET_CRCDONE_Pos) /* (FCR_INTENSET) Interrupt Enabled Position */
+#define FCR_INTENSET_CRCERR_Pos               _UINT32_(9)                                          /* (FCR_INTENSET) CRC Error Set Enable Position */
+#define FCR_INTENSET_CRCERR_Msk               (_UINT32_(0x1) << FCR_INTENSET_CRCERR_Pos)           /* (FCR_INTENSET) CRC Error Set Enable Mask */
+#define FCR_INTENSET_CRCERR(value)            (FCR_INTENSET_CRCERR_Msk & (_UINT32_(value) << FCR_INTENSET_CRCERR_Pos)) /* Assignment of value for CRCERR in the FCR_INTENSET register */
+#define   FCR_INTENSET_CRCERR_0_Val           _UINT32_(0x0)                                        /* (FCR_INTENSET) Interrupt Disabled  */
+#define   FCR_INTENSET_CRCERR_1_Val           _UINT32_(0x1)                                        /* (FCR_INTENSET) Interrupt Enabled  */
+#define FCR_INTENSET_CRCERR_0                 (FCR_INTENSET_CRCERR_0_Val << FCR_INTENSET_CRCERR_Pos) /* (FCR_INTENSET) Interrupt Disabled Position */
+#define FCR_INTENSET_CRCERR_1                 (FCR_INTENSET_CRCERR_1_Val << FCR_INTENSET_CRCERR_Pos) /* (FCR_INTENSET) Interrupt Enabled Position */
+#define FCR_INTENSET_FLTCAP_Pos               _UINT32_(16)                                         /* (FCR_INTENSET) ECC Fault Capture Set Enable Position */
+#define FCR_INTENSET_FLTCAP_Msk               (_UINT32_(0x1) << FCR_INTENSET_FLTCAP_Pos)           /* (FCR_INTENSET) ECC Fault Capture Set Enable Mask */
+#define FCR_INTENSET_FLTCAP(value)            (FCR_INTENSET_FLTCAP_Msk & (_UINT32_(value) << FCR_INTENSET_FLTCAP_Pos)) /* Assignment of value for FLTCAP in the FCR_INTENSET register */
+#define   FCR_INTENSET_FLTCAP_0_Val           _UINT32_(0x0)                                        /* (FCR_INTENSET) Interrupt Disabled  */
+#define   FCR_INTENSET_FLTCAP_1_Val           _UINT32_(0x1)                                        /* (FCR_INTENSET) Interrupt Enabled  */
+#define FCR_INTENSET_FLTCAP_0                 (FCR_INTENSET_FLTCAP_0_Val << FCR_INTENSET_FLTCAP_Pos) /* (FCR_INTENSET) Interrupt Disabled Position */
+#define FCR_INTENSET_FLTCAP_1                 (FCR_INTENSET_FLTCAP_1_Val << FCR_INTENSET_FLTCAP_Pos) /* (FCR_INTENSET) Interrupt Enabled Position */
+#define FCR_INTENSET_Msk                      _UINT32_(0x00010301)                                 /* (FCR_INTENSET) Register Mask  */
+
+
+/* -------- FCR_INTFLAG : (FCR Offset: 0x10) (R/W 32) Interrupt Flag REGISTER -------- */
+#define FCR_INTFLAG_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_INTFLAG) Interrupt Flag REGISTER  Reset Value */
+
+#define FCR_INTFLAG_SERR_Pos                  _UINT32_(0)                                          /* (FCR_INTFLAG) Flash SEC Interrupt Flag Position */
+#define FCR_INTFLAG_SERR_Msk                  (_UINT32_(0x1) << FCR_INTFLAG_SERR_Pos)              /* (FCR_INTFLAG) Flash SEC Interrupt Flag Mask */
+#define FCR_INTFLAG_SERR(value)               (FCR_INTFLAG_SERR_Msk & (_UINT32_(value) << FCR_INTFLAG_SERR_Pos)) /* Assignment of value for SERR in the FCR_INTFLAG register */
+#define   FCR_INTFLAG_SERR_0_Val              _UINT32_(0x0)                                        /* (FCR_INTFLAG) No Interrupt Pending  */
+#define   FCR_INTFLAG_SERR_1_Val              _UINT32_(0x1)                                        /* (FCR_INTFLAG) SECCNT Count reached  */
+#define FCR_INTFLAG_SERR_0                    (FCR_INTFLAG_SERR_0_Val << FCR_INTFLAG_SERR_Pos)     /* (FCR_INTFLAG) No Interrupt Pending Position */
+#define FCR_INTFLAG_SERR_1                    (FCR_INTFLAG_SERR_1_Val << FCR_INTFLAG_SERR_Pos)     /* (FCR_INTFLAG) SECCNT Count reached Position */
+#define FCR_INTFLAG_CRCDONE_Pos               _UINT32_(8)                                          /* (FCR_INTFLAG) CRC Calculation Done Flag Position */
+#define FCR_INTFLAG_CRCDONE_Msk               (_UINT32_(0x1) << FCR_INTFLAG_CRCDONE_Pos)           /* (FCR_INTFLAG) CRC Calculation Done Flag Mask */
+#define FCR_INTFLAG_CRCDONE(value)            (FCR_INTFLAG_CRCDONE_Msk & (_UINT32_(value) << FCR_INTFLAG_CRCDONE_Pos)) /* Assignment of value for CRCDONE in the FCR_INTFLAG register */
+#define   FCR_INTFLAG_CRCDONE_0_Val           _UINT32_(0x0)                                        /* (FCR_INTFLAG) No Interrupt Pending  */
+#define   FCR_INTFLAG_CRCDONE_1_Val           _UINT32_(0x1)                                        /* (FCR_INTFLAG) Calculation Done  */
+#define FCR_INTFLAG_CRCDONE_0                 (FCR_INTFLAG_CRCDONE_0_Val << FCR_INTFLAG_CRCDONE_Pos) /* (FCR_INTFLAG) No Interrupt Pending Position */
+#define FCR_INTFLAG_CRCDONE_1                 (FCR_INTFLAG_CRCDONE_1_Val << FCR_INTFLAG_CRCDONE_Pos) /* (FCR_INTFLAG) Calculation Done Position */
+#define FCR_INTFLAG_CRCERR_Pos                _UINT32_(9)                                          /* (FCR_INTFLAG) CRC Error Flag Position */
+#define FCR_INTFLAG_CRCERR_Msk                (_UINT32_(0x1) << FCR_INTFLAG_CRCERR_Pos)            /* (FCR_INTFLAG) CRC Error Flag Mask */
+#define FCR_INTFLAG_CRCERR(value)             (FCR_INTFLAG_CRCERR_Msk & (_UINT32_(value) << FCR_INTFLAG_CRCERR_Pos)) /* Assignment of value for CRCERR in the FCR_INTFLAG register */
+#define   FCR_INTFLAG_CRCERR_0_Val            _UINT32_(0x0)                                        /* (FCR_INTFLAG) No Interrupt Pending  */
+#define   FCR_INTFLAG_CRCERR_1_Val            _UINT32_(0x1)                                        /* (FCR_INTFLAG) CRCACC Is Not Equal to the XOR of CRCSUM and CRCFXOR  */
+#define FCR_INTFLAG_CRCERR_0                  (FCR_INTFLAG_CRCERR_0_Val << FCR_INTFLAG_CRCERR_Pos) /* (FCR_INTFLAG) No Interrupt Pending Position */
+#define FCR_INTFLAG_CRCERR_1                  (FCR_INTFLAG_CRCERR_1_Val << FCR_INTFLAG_CRCERR_Pos) /* (FCR_INTFLAG) CRCACC Is Not Equal to the XOR of CRCSUM and CRCFXOR Position */
+#define FCR_INTFLAG_FLTCAP_Pos                _UINT32_(16)                                         /* (FCR_INTFLAG) ECC Fault Capture Flag Position */
+#define FCR_INTFLAG_FLTCAP_Msk                (_UINT32_(0x1) << FCR_INTFLAG_FLTCAP_Pos)            /* (FCR_INTFLAG) ECC Fault Capture Flag Mask */
+#define FCR_INTFLAG_FLTCAP(value)             (FCR_INTFLAG_FLTCAP_Msk & (_UINT32_(value) << FCR_INTFLAG_FLTCAP_Pos)) /* Assignment of value for FLTCAP in the FCR_INTFLAG register */
+#define   FCR_INTFLAG_FLTCAP_0_Val            _UINT32_(0x0)                                        /* (FCR_INTFLAG) No Interrupt Pending  */
+#define   FCR_INTFLAG_FLTCAP_1_Val            _UINT32_(0x1)                                        /* (FCR_INTFLAG) An ECC Fault Capture, related to FLTMD[], occurred  */
+#define FCR_INTFLAG_FLTCAP_0                  (FCR_INTFLAG_FLTCAP_0_Val << FCR_INTFLAG_FLTCAP_Pos) /* (FCR_INTFLAG) No Interrupt Pending Position */
+#define FCR_INTFLAG_FLTCAP_1                  (FCR_INTFLAG_FLTCAP_1_Val << FCR_INTFLAG_FLTCAP_Pos) /* (FCR_INTFLAG) An ECC Fault Capture, related to FLTMD[], occurred Position */
+#define FCR_INTFLAG_Msk                       _UINT32_(0x00010301)                                 /* (FCR_INTFLAG) Register Mask  */
+
+
+/* -------- FCR_INTFLAGSET : (FCR Offset: 0x14) (R/W 32) Interrupt Flag Set REGISTER -------- */
+#define FCR_INTFLAGSET_RESETVALUE             _UINT32_(0x00)                                       /*  (FCR_INTFLAGSET) Interrupt Flag Set REGISTER  Reset Value */
+
+#define FCR_INTFLAGSET_SERR_Pos               _UINT32_(0)                                          /* (FCR_INTFLAGSET) Flash SEC Interrupt Flag Position */
+#define FCR_INTFLAGSET_SERR_Msk               (_UINT32_(0x1) << FCR_INTFLAGSET_SERR_Pos)           /* (FCR_INTFLAGSET) Flash SEC Interrupt Flag Mask */
+#define FCR_INTFLAGSET_SERR(value)            (FCR_INTFLAGSET_SERR_Msk & (_UINT32_(value) << FCR_INTFLAGSET_SERR_Pos)) /* Assignment of value for SERR in the FCR_INTFLAGSET register */
+#define   FCR_INTFLAGSET_SERR_0_Val           _UINT32_(0x0)                                        /* (FCR_INTFLAGSET) No Interrupt Pending  */
+#define   FCR_INTFLAGSET_SERR_1_Val           _UINT32_(0x1)                                        /* (FCR_INTFLAGSET) SECCNT Count reached  */
+#define FCR_INTFLAGSET_SERR_0                 (FCR_INTFLAGSET_SERR_0_Val << FCR_INTFLAGSET_SERR_Pos) /* (FCR_INTFLAGSET) No Interrupt Pending Position */
+#define FCR_INTFLAGSET_SERR_1                 (FCR_INTFLAGSET_SERR_1_Val << FCR_INTFLAGSET_SERR_Pos) /* (FCR_INTFLAGSET) SECCNT Count reached Position */
+#define FCR_INTFLAGSET_CRCDONE_Pos            _UINT32_(8)                                          /* (FCR_INTFLAGSET) CRC Calculation Done Flag Position */
+#define FCR_INTFLAGSET_CRCDONE_Msk            (_UINT32_(0x1) << FCR_INTFLAGSET_CRCDONE_Pos)        /* (FCR_INTFLAGSET) CRC Calculation Done Flag Mask */
+#define FCR_INTFLAGSET_CRCDONE(value)         (FCR_INTFLAGSET_CRCDONE_Msk & (_UINT32_(value) << FCR_INTFLAGSET_CRCDONE_Pos)) /* Assignment of value for CRCDONE in the FCR_INTFLAGSET register */
+#define   FCR_INTFLAGSET_CRCDONE_0_Val        _UINT32_(0x0)                                        /* (FCR_INTFLAGSET) No effect  */
+#define   FCR_INTFLAGSET_CRCDONE_1_Val        _UINT32_(0x1)                                        /* (FCR_INTFLAGSET) Set Interrupt Pending  */
+#define FCR_INTFLAGSET_CRCDONE_0              (FCR_INTFLAGSET_CRCDONE_0_Val << FCR_INTFLAGSET_CRCDONE_Pos) /* (FCR_INTFLAGSET) No effect Position */
+#define FCR_INTFLAGSET_CRCDONE_1              (FCR_INTFLAGSET_CRCDONE_1_Val << FCR_INTFLAGSET_CRCDONE_Pos) /* (FCR_INTFLAGSET) Set Interrupt Pending Position */
+#define FCR_INTFLAGSET_CRCERR_Pos             _UINT32_(9)                                          /* (FCR_INTFLAGSET) CRC Error Flag Position */
+#define FCR_INTFLAGSET_CRCERR_Msk             (_UINT32_(0x1) << FCR_INTFLAGSET_CRCERR_Pos)         /* (FCR_INTFLAGSET) CRC Error Flag Mask */
+#define FCR_INTFLAGSET_CRCERR(value)          (FCR_INTFLAGSET_CRCERR_Msk & (_UINT32_(value) << FCR_INTFLAGSET_CRCERR_Pos)) /* Assignment of value for CRCERR in the FCR_INTFLAGSET register */
+#define   FCR_INTFLAGSET_CRCERR_0_Val         _UINT32_(0x0)                                        /* (FCR_INTFLAGSET) No effect  */
+#define   FCR_INTFLAGSET_CRCERR_1_Val         _UINT32_(0x1)                                        /* (FCR_INTFLAGSET) Set Interrupt Pending  */
+#define FCR_INTFLAGSET_CRCERR_0               (FCR_INTFLAGSET_CRCERR_0_Val << FCR_INTFLAGSET_CRCERR_Pos) /* (FCR_INTFLAGSET) No effect Position */
+#define FCR_INTFLAGSET_CRCERR_1               (FCR_INTFLAGSET_CRCERR_1_Val << FCR_INTFLAGSET_CRCERR_Pos) /* (FCR_INTFLAGSET) Set Interrupt Pending Position */
+#define FCR_INTFLAGSET_FLTCAP_Pos             _UINT32_(16)                                         /* (FCR_INTFLAGSET) ECC Fault Capture Flag Position */
+#define FCR_INTFLAGSET_FLTCAP_Msk             (_UINT32_(0x1) << FCR_INTFLAGSET_FLTCAP_Pos)         /* (FCR_INTFLAGSET) ECC Fault Capture Flag Mask */
+#define FCR_INTFLAGSET_FLTCAP(value)          (FCR_INTFLAGSET_FLTCAP_Msk & (_UINT32_(value) << FCR_INTFLAGSET_FLTCAP_Pos)) /* Assignment of value for FLTCAP in the FCR_INTFLAGSET register */
+#define   FCR_INTFLAGSET_FLTCAP_0_Val         _UINT32_(0x0)                                        /* (FCR_INTFLAGSET) No effect  */
+#define   FCR_INTFLAGSET_FLTCAP_1_Val         _UINT32_(0x1)                                        /* (FCR_INTFLAGSET) Set Interrupt Pending  */
+#define FCR_INTFLAGSET_FLTCAP_0               (FCR_INTFLAGSET_FLTCAP_0_Val << FCR_INTFLAGSET_FLTCAP_Pos) /* (FCR_INTFLAGSET) No effect Position */
+#define FCR_INTFLAGSET_FLTCAP_1               (FCR_INTFLAGSET_FLTCAP_1_Val << FCR_INTFLAGSET_FLTCAP_Pos) /* (FCR_INTFLAGSET) Set Interrupt Pending Position */
+#define FCR_INTFLAGSET_Msk                    _UINT32_(0x00010301)                                 /* (FCR_INTFLAGSET) Register Mask  */
+
+
+/* -------- FCR_STATUS : (FCR Offset: 0x18) ( R/ 32) Status REGISTER -------- */
+#define FCR_STATUS_RESETVALUE                 _UINT32_(0xE0000000)                                 /*  (FCR_STATUS) Status REGISTER  Reset Value */
+
+#define FCR_STATUS_PRM_Pos                    _UINT32_(0)                                          /* (FCR_STATUS) NVM Power Reduction Mode Status Position */
+#define FCR_STATUS_PRM_Msk                    (_UINT32_(0x1) << FCR_STATUS_PRM_Pos)                /* (FCR_STATUS) NVM Power Reduction Mode Status Mask */
+#define FCR_STATUS_PRM(value)                 (FCR_STATUS_PRM_Msk & (_UINT32_(value) << FCR_STATUS_PRM_Pos)) /* Assignment of value for PRM in the FCR_STATUS register */
+#define   FCR_STATUS_PRM_0_Val                _UINT32_(0x0)                                        /* (FCR_STATUS) Flash is Ready (for read or NVMOP)  */
+#define   FCR_STATUS_PRM_1_Val                _UINT32_(0x1)                                        /* (FCR_STATUS) Flash is Powered Down and wakes on first access (read or NVMOP)  */
+#define FCR_STATUS_PRM_0                      (FCR_STATUS_PRM_0_Val << FCR_STATUS_PRM_Pos)         /* (FCR_STATUS) Flash is Ready (for read or NVMOP) Position */
+#define FCR_STATUS_PRM_1                      (FCR_STATUS_PRM_1_Val << FCR_STATUS_PRM_Pos)         /* (FCR_STATUS) Flash is Powered Down and wakes on first access (read or NVMOP) Position */
+#define FCR_STATUS_Msk                        _UINT32_(0x00000001)                                 /* (FCR_STATUS) Register Mask  */
+
+
+/* -------- FCR_DBGCTRL : (FCR Offset: 0x1C) (R/W 32) Debug Control CTRL REGISTER -------- */
+#define FCR_DBGCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_DBGCTRL) Debug Control CTRL REGISTER  Reset Value */
+
+#define FCR_DBGCTRL_CRCRUN_Pos                _UINT32_(0)                                          /* (FCR_DBGCTRL) CRC Debug Run Enable Position */
+#define FCR_DBGCTRL_CRCRUN_Msk                (_UINT32_(0x1) << FCR_DBGCTRL_CRCRUN_Pos)            /* (FCR_DBGCTRL) CRC Debug Run Enable Mask */
+#define FCR_DBGCTRL_CRCRUN(value)             (FCR_DBGCTRL_CRCRUN_Msk & (_UINT32_(value) << FCR_DBGCTRL_CRCRUN_Pos)) /* Assignment of value for CRCRUN in the FCR_DBGCTRL register */
+#define   FCR_DBGCTRL_CRCRUN_HALT_Val         _UINT32_(0x0)                                        /* (FCR_DBGCTRL) CRC Logic Halts in Debug Mode  */
+#define   FCR_DBGCTRL_CRCRUN_RUN_Val          _UINT32_(0x1)                                        /* (FCR_DBGCTRL) CRC Logic Runs in Debug Mode.  */
+#define FCR_DBGCTRL_CRCRUN_HALT               (FCR_DBGCTRL_CRCRUN_HALT_Val << FCR_DBGCTRL_CRCRUN_Pos) /* (FCR_DBGCTRL) CRC Logic Halts in Debug Mode Position */
+#define FCR_DBGCTRL_CRCRUN_RUN                (FCR_DBGCTRL_CRCRUN_RUN_Val << FCR_DBGCTRL_CRCRUN_Pos) /* (FCR_DBGCTRL) CRC Logic Runs in Debug Mode. Position */
+#define FCR_DBGCTRL_DBGECC_Pos                _UINT32_(1)                                          /* (FCR_DBGCTRL) Debug ECC ModeECC errors from debugger reads are: Position */
+#define FCR_DBGCTRL_DBGECC_Msk                (_UINT32_(0x3) << FCR_DBGCTRL_DBGECC_Pos)            /* (FCR_DBGCTRL) Debug ECC ModeECC errors from debugger reads are: Mask */
+#define FCR_DBGCTRL_DBGECC(value)             (FCR_DBGCTRL_DBGECC_Msk & (_UINT32_(value) << FCR_DBGCTRL_DBGECC_Pos)) /* Assignment of value for DBGECC in the FCR_DBGCTRL register */
+#define   FCR_DBGCTRL_DBGECC_NOERR_Val        _UINT32_(0x0)                                        /* (FCR_DBGCTRL) Corrected per ECCCTRL; No Bus ERR; INTFLAG, SEC counter, and FLT logic are not updated.  */
+#define   FCR_DBGCTRL_DBGECC_DISABLE_Val      _UINT32_(0x1)                                        /* (FCR_DBGCTRL) Not corrected; No Bus Error; INTFLAG, SEC counter, and FLT logic are not updated.  */
+#define   FCR_DBGCTRL_DBGECC_ENABLE_Val       _UINT32_(0x2)                                        /* (FCR_DBGCTRL) Corrected per ECCCTRL; Bus Error, INTFLAG, SEC counter, and FLT logic operates as setup.  */
+#define   FCR_DBGCTRL_DBGECC_RSVD11_Val       _UINT32_(0x3)                                        /* (FCR_DBGCTRL) Don't use but same as 01 (DISABLE)  */
+#define FCR_DBGCTRL_DBGECC_NOERR              (FCR_DBGCTRL_DBGECC_NOERR_Val << FCR_DBGCTRL_DBGECC_Pos) /* (FCR_DBGCTRL) Corrected per ECCCTRL; No Bus ERR; INTFLAG, SEC counter, and FLT logic are not updated. Position */
+#define FCR_DBGCTRL_DBGECC_DISABLE            (FCR_DBGCTRL_DBGECC_DISABLE_Val << FCR_DBGCTRL_DBGECC_Pos) /* (FCR_DBGCTRL) Not corrected; No Bus Error; INTFLAG, SEC counter, and FLT logic are not updated. Position */
+#define FCR_DBGCTRL_DBGECC_ENABLE             (FCR_DBGCTRL_DBGECC_ENABLE_Val << FCR_DBGCTRL_DBGECC_Pos) /* (FCR_DBGCTRL) Corrected per ECCCTRL; Bus Error, INTFLAG, SEC counter, and FLT logic operates as setup. Position */
+#define FCR_DBGCTRL_DBGECC_RSVD11             (FCR_DBGCTRL_DBGECC_RSVD11_Val << FCR_DBGCTRL_DBGECC_Pos) /* (FCR_DBGCTRL) Don't use but same as 01 (DISABLE) Position */
+#define FCR_DBGCTRL_Msk                       _UINT32_(0x00000007)                                 /* (FCR_DBGCTRL) Register Mask  */
+
+
+/* -------- FCR_ECCCTRL : (FCR Offset: 0x20) (R/W 32) ECC Control REGISTER -------- */
+#define FCR_ECCCTRL_RESETVALUE                _UINT32_(0x40)                                       /*  (FCR_ECCCTRL) ECC Control REGISTER  Reset Value */
+
+#define FCR_ECCCTRL_ECCCTL_Pos                _UINT32_(4)                                          /* (FCR_ECCCTRL) NVM ECC Mode Control - restricts one or more NVMOPs Position */
+#define FCR_ECCCTRL_ECCCTL_Msk                (_UINT32_(0x3) << FCR_ECCCTRL_ECCCTL_Pos)            /* (FCR_ECCCTRL) NVM ECC Mode Control - restricts one or more NVMOPs Mask */
+#define FCR_ECCCTRL_ECCCTL(value)             (FCR_ECCCTRL_ECCCTL_Msk & (_UINT32_(value) << FCR_ECCCTRL_ECCCTL_Pos)) /* Assignment of value for ECCCTL in the FCR_ECCCTRL register */
+#define   FCR_ECCCTRL_ECCCTL_STRICT_Val       _UINT32_(0x0)                                        /* (FCR_ECCCTRL) ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)  */
+#define   FCR_ECCCTRL_ECCCTL_DYNAMIC_Val      _UINT32_(0x1)                                        /* (FCR_ECCCTRL) Dynamic Writes with Dynamic Reads  */
+#define   FCR_ECCCTRL_ECCCTL_ECC_Val          _UINT32_(0x2)                                        /* (FCR_ECCCTRL) ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)  */
+#define   FCR_ECCCTRL_ECCCTL_DISABLE_Val      _UINT32_(0x3)                                        /* (FCR_ECCCTRL) Dynamic Writes with No Error Check Reads  */
+#define FCR_ECCCTRL_ECCCTL_STRICT             (FCR_ECCCTRL_ECCCTL_STRICT_Val << FCR_ECCCTRL_ECCCTL_Pos) /* (FCR_ECCCTRL) ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled) Position */
+#define FCR_ECCCTRL_ECCCTL_DYNAMIC            (FCR_ECCCTRL_ECCCTL_DYNAMIC_Val << FCR_ECCCTRL_ECCCTL_Pos) /* (FCR_ECCCTRL) Dynamic Writes with Dynamic Reads Position */
+#define FCR_ECCCTRL_ECCCTL_ECC                (FCR_ECCCTRL_ECCCTL_ECC_Val << FCR_ECCCTRL_ECCCTL_Pos) /* (FCR_ECCCTRL) ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled) Position */
+#define FCR_ECCCTRL_ECCCTL_DISABLE            (FCR_ECCCTRL_ECCCTL_DISABLE_Val << FCR_ECCCTRL_ECCCTL_Pos) /* (FCR_ECCCTRL) Dynamic Writes with No Error Check Reads Position */
+#define FCR_ECCCTRL_ECCUNLCK_Pos              _UINT32_(6)                                          /* (FCR_ECCCTRL) NVM ECC Mode Control Unlock Position */
+#define FCR_ECCCTRL_ECCUNLCK_Msk              (_UINT32_(0x1) << FCR_ECCCTRL_ECCUNLCK_Pos)          /* (FCR_ECCCTRL) NVM ECC Mode Control Unlock Mask */
+#define FCR_ECCCTRL_ECCUNLCK(value)           (FCR_ECCCTRL_ECCUNLCK_Msk & (_UINT32_(value) << FCR_ECCCTRL_ECCUNLCK_Pos)) /* Assignment of value for ECCUNLCK in the FCR_ECCCTRL register */
+#define   FCR_ECCCTRL_ECCUNLCK_LOCKED_Val     _UINT32_(0x0)                                        /* (FCR_ECCCTRL) ECCUNLCK and ECCCTL[1:0] cannot be written  */
+#define   FCR_ECCCTRL_ECCUNLCK_UNLOCKED_Val   _UINT32_(0x1)                                        /* (FCR_ECCCTRL) ECCUNLCK and ECCCTL[1:0] can be written  */
+#define FCR_ECCCTRL_ECCUNLCK_LOCKED           (FCR_ECCCTRL_ECCUNLCK_LOCKED_Val << FCR_ECCCTRL_ECCUNLCK_Pos) /* (FCR_ECCCTRL) ECCUNLCK and ECCCTL[1:0] cannot be written Position */
+#define FCR_ECCCTRL_ECCUNLCK_UNLOCKED         (FCR_ECCCTRL_ECCUNLCK_UNLOCKED_Val << FCR_ECCCTRL_ECCUNLCK_Pos) /* (FCR_ECCCTRL) ECCUNLCK and ECCCTL[1:0] can be written Position */
+#define FCR_ECCCTRL_SECCNT_Pos                _UINT32_(8)                                          /* (FCR_ECCCTRL) Flash SEC Count Position */
+#define FCR_ECCCTRL_SECCNT_Msk                (_UINT32_(0xFF) << FCR_ECCCTRL_SECCNT_Pos)           /* (FCR_ECCCTRL) Flash SEC Count Mask */
+#define FCR_ECCCTRL_SECCNT(value)             (FCR_ECCCTRL_SECCNT_Msk & (_UINT32_(value) << FCR_ECCCTRL_SECCNT_Pos)) /* Assignment of value for SECCNT in the FCR_ECCCTRL register */
+#define FCR_ECCCTRL_Msk                       _UINT32_(0x0000FF70)                                 /* (FCR_ECCCTRL) Register Mask  */
+
+
+/* -------- FCR_CRCCTRL : (FCR Offset: 0x24) (R/W 32) CRC Control REGISTER -------- */
+#define FCR_CRCCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_CRCCTRL) CRC Control REGISTER  Reset Value */
+
+#define FCR_CRCCTRL_CRCRST_Pos                _UINT32_(0)                                          /* (FCR_CRCCTRL) CRC Reset Position */
+#define FCR_CRCCTRL_CRCRST_Msk                (_UINT32_(0x1) << FCR_CRCCTRL_CRCRST_Pos)            /* (FCR_CRCCTRL) CRC Reset Mask */
+#define FCR_CRCCTRL_CRCRST(value)             (FCR_CRCCTRL_CRCRST_Msk & (_UINT32_(value) << FCR_CRCCTRL_CRCRST_Pos)) /* Assignment of value for CRCRST in the FCR_CRCCTRL register */
+#define   FCR_CRCCTRL_CRCRST_NONE_Val         _UINT32_(0x0)                                        /* (FCR_CRCCTRL) No Action  */
+#define   FCR_CRCCTRL_CRCRST_RESET_Val        _UINT32_(0x1)                                        /* (FCR_CRCCTRL) Resets all CRC SFR bits.  */
+#define FCR_CRCCTRL_CRCRST_NONE               (FCR_CRCCTRL_CRCRST_NONE_Val << FCR_CRCCTRL_CRCRST_Pos) /* (FCR_CRCCTRL) No Action Position */
+#define FCR_CRCCTRL_CRCRST_RESET              (FCR_CRCCTRL_CRCRST_RESET_Val << FCR_CRCCTRL_CRCRST_Pos) /* (FCR_CRCCTRL) Resets all CRC SFR bits. Position */
+#define FCR_CRCCTRL_CRCEN_Pos                 _UINT32_(1)                                          /* (FCR_CRCCTRL) Start CRC Calculation Position */
+#define FCR_CRCCTRL_CRCEN_Msk                 (_UINT32_(0x1) << FCR_CRCCTRL_CRCEN_Pos)             /* (FCR_CRCCTRL) Start CRC Calculation Mask */
+#define FCR_CRCCTRL_CRCEN(value)              (FCR_CRCCTRL_CRCEN_Msk & (_UINT32_(value) << FCR_CRCCTRL_CRCEN_Pos)) /* Assignment of value for CRCEN in the FCR_CRCCTRL register */
+#define   FCR_CRCCTRL_CRCEN_DISABLE_Val       _UINT32_(0x0)                                        /* (FCR_CRCCTRL) Stops CRC calculation.  */
+#define   FCR_CRCCTRL_CRCEN_ENABLE_Val        _UINT32_(0x1)                                        /* (FCR_CRCCTRL) CRC Calculation Enabled (w/ start on write to 1).  */
+#define FCR_CRCCTRL_CRCEN_DISABLE             (FCR_CRCCTRL_CRCEN_DISABLE_Val << FCR_CRCCTRL_CRCEN_Pos) /* (FCR_CRCCTRL) Stops CRC calculation. Position */
+#define FCR_CRCCTRL_CRCEN_ENABLE              (FCR_CRCCTRL_CRCEN_ENABLE_Val << FCR_CRCCTRL_CRCEN_Pos) /* (FCR_CRCCTRL) CRC Calculation Enabled (w/ start on write to 1). Position */
+#define FCR_CRCCTRL_RUNSTDBY_Pos              _UINT32_(5)                                          /* (FCR_CRCCTRL) CRC Run in Standby Position */
+#define FCR_CRCCTRL_RUNSTDBY_Msk              (_UINT32_(0x1) << FCR_CRCCTRL_RUNSTDBY_Pos)          /* (FCR_CRCCTRL) CRC Run in Standby Mask */
+#define FCR_CRCCTRL_RUNSTDBY(value)           (FCR_CRCCTRL_RUNSTDBY_Msk & (_UINT32_(value) << FCR_CRCCTRL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the FCR_CRCCTRL register */
+#define   FCR_CRCCTRL_RUNSTDBY_HALT_Val       _UINT32_(0x0)                                        /* (FCR_CRCCTRL) CRC Halts in Standby  */
+#define   FCR_CRCCTRL_RUNSTDBY_RUN_Val        _UINT32_(0x1)                                        /* (FCR_CRCCTRL) CRC Runs in Standby but only if STATUS.PRM=0 (i.e. Flash is in Auto Standby)  */
+#define FCR_CRCCTRL_RUNSTDBY_HALT             (FCR_CRCCTRL_RUNSTDBY_HALT_Val << FCR_CRCCTRL_RUNSTDBY_Pos) /* (FCR_CRCCTRL) CRC Halts in Standby Position */
+#define FCR_CRCCTRL_RUNSTDBY_RUN              (FCR_CRCCTRL_RUNSTDBY_RUN_Val << FCR_CRCCTRL_RUNSTDBY_Pos) /* (FCR_CRCCTRL) CRC Runs in Standby but only if STATUS.PRM=0 (i.e. Flash is in Auto Standby) Position */
+#define FCR_CRCCTRL_Msk                       _UINT32_(0x00000023)                                 /* (FCR_CRCCTRL) Register Mask  */
+
+
+/* -------- FCR_CRCMODE : (FCR Offset: 0x28) (R/W 32) CRC MODE REGISTER -------- */
+#define FCR_CRCMODE_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_CRCMODE) CRC MODE REGISTER  Reset Value */
+
+#define FCR_CRCMODE_PLEN32_Pos                _UINT32_(12)                                         /* (FCR_CRCMODE) Polynomial Length Select Position */
+#define FCR_CRCMODE_PLEN32_Msk                (_UINT32_(0x1) << FCR_CRCMODE_PLEN32_Pos)            /* (FCR_CRCMODE) Polynomial Length Select Mask */
+#define FCR_CRCMODE_PLEN32(value)             (FCR_CRCMODE_PLEN32_Msk & (_UINT32_(value) << FCR_CRCMODE_PLEN32_Pos)) /* Assignment of value for PLEN32 in the FCR_CRCMODE register */
+#define   FCR_CRCMODE_PLEN32_SIXTEEN_Val      _UINT32_(0x0)                                        /* (FCR_CRCMODE) Polynomial is 16-bits  */
+#define   FCR_CRCMODE_PLEN32_THIRTYTWO_Val    _UINT32_(0x1)                                        /* (FCR_CRCMODE) Polynomial is 32-bits  */
+#define FCR_CRCMODE_PLEN32_SIXTEEN            (FCR_CRCMODE_PLEN32_SIXTEEN_Val << FCR_CRCMODE_PLEN32_Pos) /* (FCR_CRCMODE) Polynomial is 16-bits Position */
+#define FCR_CRCMODE_PLEN32_THIRTYTWO          (FCR_CRCMODE_PLEN32_THIRTYTWO_Val << FCR_CRCMODE_PLEN32_Pos) /* (FCR_CRCMODE) Polynomial is 32-bits Position */
+#define FCR_CRCMODE_AUTOR_Pos                 _UINT32_(13)                                         /* (FCR_CRCMODE) CRC Auto Repeat Position */
+#define FCR_CRCMODE_AUTOR_Msk                 (_UINT32_(0x1) << FCR_CRCMODE_AUTOR_Pos)             /* (FCR_CRCMODE) CRC Auto Repeat Mask */
+#define FCR_CRCMODE_AUTOR(value)              (FCR_CRCMODE_AUTOR_Msk & (_UINT32_(value) << FCR_CRCMODE_AUTOR_Pos)) /* Assignment of value for AUTOR in the FCR_CRCMODE register */
+#define   FCR_CRCMODE_AUTOR_DISABLE_Val       _UINT32_(0x0)                                        /* (FCR_CRCMODE) Perform CRC calculation once then set DONE and if needed, CRCERR.  */
+#define   FCR_CRCMODE_AUTOR_ENABLE_Val        _UINT32_(0x1)                                        /* (FCR_CRCMODE) Continually Repeat CRC calculation; stop on error, set CRCDONE and CRCERR  */
+#define FCR_CRCMODE_AUTOR_DISABLE             (FCR_CRCMODE_AUTOR_DISABLE_Val << FCR_CRCMODE_AUTOR_Pos) /* (FCR_CRCMODE) Perform CRC calculation once then set DONE and if needed, CRCERR. Position */
+#define FCR_CRCMODE_AUTOR_ENABLE              (FCR_CRCMODE_AUTOR_ENABLE_Val << FCR_CRCMODE_AUTOR_Pos) /* (FCR_CRCMODE) Continually Repeat CRC calculation; stop on error, set CRCDONE and CRCERR Position */
+#define FCR_CRCMODE_ROUT_Pos                  _UINT32_(14)                                         /* (FCR_CRCMODE) CRC Reflected Output Position */
+#define FCR_CRCMODE_ROUT_Msk                  (_UINT32_(0x1) << FCR_CRCMODE_ROUT_Pos)              /* (FCR_CRCMODE) CRC Reflected Output Mask */
+#define FCR_CRCMODE_ROUT(value)               (FCR_CRCMODE_ROUT_Msk & (_UINT32_(value) << FCR_CRCMODE_ROUT_Pos)) /* Assignment of value for ROUT in the FCR_CRCMODE register */
+#define   FCR_CRCMODE_ROUT_DISABLE_Val        _UINT32_(0x0)                                        /* (FCR_CRCMODE) The CRCACC is Not Reflected  */
+#define   FCR_CRCMODE_ROUT_ENABLE_Val         _UINT32_(0x1)                                        /* (FCR_CRCMODE) The CRCACC is Reflected (before the Final XOR)  */
+#define FCR_CRCMODE_ROUT_DISABLE              (FCR_CRCMODE_ROUT_DISABLE_Val << FCR_CRCMODE_ROUT_Pos) /* (FCR_CRCMODE) The CRCACC is Not Reflected Position */
+#define FCR_CRCMODE_ROUT_ENABLE               (FCR_CRCMODE_ROUT_ENABLE_Val << FCR_CRCMODE_ROUT_Pos) /* (FCR_CRCMODE) The CRCACC is Reflected (before the Final XOR) Position */
+#define FCR_CRCMODE_RIN_Pos                   _UINT32_(15)                                         /* (FCR_CRCMODE) CRC Reflected Input Position */
+#define FCR_CRCMODE_RIN_Msk                   (_UINT32_(0x1) << FCR_CRCMODE_RIN_Pos)               /* (FCR_CRCMODE) CRC Reflected Input Mask */
+#define FCR_CRCMODE_RIN(value)                (FCR_CRCMODE_RIN_Msk & (_UINT32_(value) << FCR_CRCMODE_RIN_Pos)) /* Assignment of value for RIN in the FCR_CRCMODE register */
+#define   FCR_CRCMODE_RIN_DISABLE_Val         _UINT32_(0x0)                                        /* (FCR_CRCMODE) The LFSR CRC is calculated Most Significant Bit first (Not Reflected)  */
+#define   FCR_CRCMODE_RIN_ENABLE_Val          _UINT32_(0x1)                                        /* (FCR_CRCMODE) The LFSR CRC is calculated Least Significant Bit first (Reflected)  */
+#define FCR_CRCMODE_RIN_DISABLE               (FCR_CRCMODE_RIN_DISABLE_Val << FCR_CRCMODE_RIN_Pos) /* (FCR_CRCMODE) The LFSR CRC is calculated Most Significant Bit first (Not Reflected) Position */
+#define FCR_CRCMODE_RIN_ENABLE                (FCR_CRCMODE_RIN_ENABLE_Val << FCR_CRCMODE_RIN_Pos)  /* (FCR_CRCMODE) The LFSR CRC is calculated Least Significant Bit first (Reflected) Position */
+#define FCR_CRCMODE_PERIOD_Pos                _UINT32_(16)                                         /* (FCR_CRCMODE) Read Period in PerCLK counts Position */
+#define FCR_CRCMODE_PERIOD_Msk                (_UINT32_(0xFFF) << FCR_CRCMODE_PERIOD_Pos)          /* (FCR_CRCMODE) Read Period in PerCLK counts Mask */
+#define FCR_CRCMODE_PERIOD(value)             (FCR_CRCMODE_PERIOD_Msk & (_UINT32_(value) << FCR_CRCMODE_PERIOD_Pos)) /* Assignment of value for PERIOD in the FCR_CRCMODE register */
+#define FCR_CRCMODE_Msk                       _UINT32_(0x0FFFF000)                                 /* (FCR_CRCMODE) Register Mask  */
+
+#define FCR_CRCMODE_PLEN_Pos                  _UINT32_(12)                                         /* (FCR_CRCMODE Position) Polynomial Length Select */
+#define FCR_CRCMODE_PLEN_Msk                  (_UINT32_(0x1) << FCR_CRCMODE_PLEN_Pos)              /* (FCR_CRCMODE Mask) PLEN */
+#define FCR_CRCMODE_PLEN(value)               (FCR_CRCMODE_PLEN_Msk & (_UINT32_(value) << FCR_CRCMODE_PLEN_Pos)) 
+
+/* -------- FCR_CRCPAUSE : (FCR Offset: 0x2C) (R/W 32) CRC Pause REGISTER -------- */
+#define FCR_CRCPAUSE_RESETVALUE               _UINT32_(0x00)                                       /*  (FCR_CRCPAUSE) CRC Pause REGISTER  Reset Value */
+
+#define FCR_CRCPAUSE_PAUSE_Pos                _UINT32_(0)                                          /* (FCR_CRCPAUSE) CRC Pause Position */
+#define FCR_CRCPAUSE_PAUSE_Msk                (_UINT32_(0x1) << FCR_CRCPAUSE_PAUSE_Pos)            /* (FCR_CRCPAUSE) CRC Pause Mask */
+#define FCR_CRCPAUSE_PAUSE(value)             (FCR_CRCPAUSE_PAUSE_Msk & (_UINT32_(value) << FCR_CRCPAUSE_PAUSE_Pos)) /* Assignment of value for PAUSE in the FCR_CRCPAUSE register */
+#define   FCR_CRCPAUSE_PAUSE_DISABLE_Val      _UINT32_(0x0)                                        /* (FCR_CRCPAUSE) CRC Reads Flash as Required  */
+#define   FCR_CRCPAUSE_PAUSE_ENABLE_Val       _UINT32_(0x1)                                        /* (FCR_CRCPAUSE) Pause CRC Reads of Flash  */
+#define FCR_CRCPAUSE_PAUSE_DISABLE            (FCR_CRCPAUSE_PAUSE_DISABLE_Val << FCR_CRCPAUSE_PAUSE_Pos) /* (FCR_CRCPAUSE) CRC Reads Flash as Required Position */
+#define FCR_CRCPAUSE_PAUSE_ENABLE             (FCR_CRCPAUSE_PAUSE_ENABLE_Val << FCR_CRCPAUSE_PAUSE_Pos) /* (FCR_CRCPAUSE) Pause CRC Reads of Flash Position */
+#define FCR_CRCPAUSE_Msk                      _UINT32_(0x00000001)                                 /* (FCR_CRCPAUSE) Register Mask  */
+
+
+/* -------- FCR_CRCMADR : (FCR Offset: 0x30) (R/W 32) CRC Message Address REGISTER -------- */
+#define FCR_CRCMADR_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_CRCMADR) CRC Message Address REGISTER  Reset Value */
+
+#define FCR_CRCMADR_CRCMADR_Pos               _UINT32_(0)                                          /* (FCR_CRCMADR) Message Start Address in Flash Position */
+#define FCR_CRCMADR_CRCMADR_Msk               (_UINT32_(0xFFFFFFF) << FCR_CRCMADR_CRCMADR_Pos)     /* (FCR_CRCMADR) Message Start Address in Flash Mask */
+#define FCR_CRCMADR_CRCMADR(value)            (FCR_CRCMADR_CRCMADR_Msk & (_UINT32_(value) << FCR_CRCMADR_CRCMADR_Pos)) /* Assignment of value for CRCMADR in the FCR_CRCMADR register */
+#define FCR_CRCMADR_Msk                       _UINT32_(0x0FFFFFFF)                                 /* (FCR_CRCMADR) Register Mask  */
+
+
+/* -------- FCR_CRCMLEN : (FCR Offset: 0x34) (R/W 32) CRC Message Length REGISTER -------- */
+#define FCR_CRCMLEN_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_CRCMLEN) CRC Message Length REGISTER  Reset Value */
+
+#define FCR_CRCMLEN_CRCMLEN_Pos               _UINT32_(0)                                          /* (FCR_CRCMLEN) Message Length in Bytes Position */
+#define FCR_CRCMLEN_CRCMLEN_Msk               (_UINT32_(0xFFFFF) << FCR_CRCMLEN_CRCMLEN_Pos)       /* (FCR_CRCMLEN) Message Length in Bytes Mask */
+#define FCR_CRCMLEN_CRCMLEN(value)            (FCR_CRCMLEN_CRCMLEN_Msk & (_UINT32_(value) << FCR_CRCMLEN_CRCMLEN_Pos)) /* Assignment of value for CRCMLEN in the FCR_CRCMLEN register */
+#define FCR_CRCMLEN_Msk                       _UINT32_(0x000FFFFF)                                 /* (FCR_CRCMLEN) Register Mask  */
+
+
+/* -------- FCR_CRCIV : (FCR Offset: 0x38) (R/W 32) CRC Initial Value REGISTER -------- */
+#define FCR_CRCIV_RESETVALUE                  _UINT32_(0x00)                                       /*  (FCR_CRCIV) CRC Initial Value REGISTER  Reset Value */
+
+#define FCR_CRCIV_CRCIV_Pos                   _UINT32_(0)                                          /* (FCR_CRCIV) CRC Initial Value Position */
+#define FCR_CRCIV_CRCIV_Msk                   (_UINT32_(0xFFFFFFFF) << FCR_CRCIV_CRCIV_Pos)        /* (FCR_CRCIV) CRC Initial Value Mask */
+#define FCR_CRCIV_CRCIV(value)                (FCR_CRCIV_CRCIV_Msk & (_UINT32_(value) << FCR_CRCIV_CRCIV_Pos)) /* Assignment of value for CRCIV in the FCR_CRCIV register */
+#define FCR_CRCIV_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (FCR_CRCIV) Register Mask  */
+
+
+/* -------- FCR_CRCACC : (FCR Offset: 0x3C) ( R/ 32) CRC Accumulator REGISTER -------- */
+#define FCR_CRCACC_RESETVALUE                 _UINT32_(0x00)                                       /*  (FCR_CRCACC) CRC Accumulator REGISTER  Reset Value */
+
+#define FCR_CRCACC_CRCACC_Pos                 _UINT32_(0)                                          /* (FCR_CRCACC) CRC Accumulator Result Position */
+#define FCR_CRCACC_CRCACC_Msk                 (_UINT32_(0xFFFFFFFF) << FCR_CRCACC_CRCACC_Pos)      /* (FCR_CRCACC) CRC Accumulator Result Mask */
+#define FCR_CRCACC_CRCACC(value)              (FCR_CRCACC_CRCACC_Msk & (_UINT32_(value) << FCR_CRCACC_CRCACC_Pos)) /* Assignment of value for CRCACC in the FCR_CRCACC register */
+#define FCR_CRCACC_Msk                        _UINT32_(0xFFFFFFFF)                                 /* (FCR_CRCACC) Register Mask  */
+
+
+/* -------- FCR_CRCPOLY : (FCR Offset: 0x40) (R/W 32) CRC Polynomial REGISTER -------- */
+#define FCR_CRCPOLY_RESETVALUE                _UINT32_(0x01)                                       /*  (FCR_CRCPOLY) CRC Polynomial REGISTER  Reset Value */
+
+#define FCR_CRCPOLY_CRCPOLY_Pos               _UINT32_(0)                                          /* (FCR_CRCPOLY) CRC Polynomial Coefficients for LFSR Position */
+#define FCR_CRCPOLY_CRCPOLY_Msk               (_UINT32_(0xFFFFFFFF) << FCR_CRCPOLY_CRCPOLY_Pos)    /* (FCR_CRCPOLY) CRC Polynomial Coefficients for LFSR Mask */
+#define FCR_CRCPOLY_CRCPOLY(value)            (FCR_CRCPOLY_CRCPOLY_Msk & (_UINT32_(value) << FCR_CRCPOLY_CRCPOLY_Pos)) /* Assignment of value for CRCPOLY in the FCR_CRCPOLY register */
+#define   FCR_CRCPOLY_CRCPOLY_0_Val           _UINT32_(0x0)                                        /* (FCR_CRCPOLY) Disable the XOR input to the shift register at the associated bit position  */
+#define   FCR_CRCPOLY_CRCPOLY_1_Val           _UINT32_(0x1)                                        /* (FCR_CRCPOLY) Enable the XOR input to the shift register at the associated bit position  */
+#define FCR_CRCPOLY_CRCPOLY_0                 (FCR_CRCPOLY_CRCPOLY_0_Val << FCR_CRCPOLY_CRCPOLY_Pos) /* (FCR_CRCPOLY) Disable the XOR input to the shift register at the associated bit position Position */
+#define FCR_CRCPOLY_CRCPOLY_1                 (FCR_CRCPOLY_CRCPOLY_1_Val << FCR_CRCPOLY_CRCPOLY_Pos) /* (FCR_CRCPOLY) Enable the XOR input to the shift register at the associated bit position Position */
+#define FCR_CRCPOLY_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (FCR_CRCPOLY) Register Mask  */
+
+
+/* -------- FCR_CRCFXOR : (FCR Offset: 0x44) (R/W 32) CRC Final XOR REGISTER -------- */
+#define FCR_CRCFXOR_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_CRCFXOR) CRC Final XOR REGISTER  Reset Value */
+
+#define FCR_CRCFXOR_CRCFXOR_Pos               _UINT32_(0)                                          /* (FCR_CRCFXOR) CRC Final XOR Position */
+#define FCR_CRCFXOR_CRCFXOR_Msk               (_UINT32_(0xFFFFFFFF) << FCR_CRCFXOR_CRCFXOR_Pos)    /* (FCR_CRCFXOR) CRC Final XOR Mask */
+#define FCR_CRCFXOR_CRCFXOR(value)            (FCR_CRCFXOR_CRCFXOR_Msk & (_UINT32_(value) << FCR_CRCFXOR_CRCFXOR_Pos)) /* Assignment of value for CRCFXOR in the FCR_CRCFXOR register */
+#define   FCR_CRCFXOR_CRCFXOR_0_Val           _UINT32_(0x0)                                        /* (FCR_CRCFXOR) Disable the Final XOR at the associated bit position  */
+#define   FCR_CRCFXOR_CRCFXOR_1_Val           _UINT32_(0x1)                                        /* (FCR_CRCFXOR) Enable the Final XOR at the associated bit position  */
+#define FCR_CRCFXOR_CRCFXOR_0                 (FCR_CRCFXOR_CRCFXOR_0_Val << FCR_CRCFXOR_CRCFXOR_Pos) /* (FCR_CRCFXOR) Disable the Final XOR at the associated bit position Position */
+#define FCR_CRCFXOR_CRCFXOR_1                 (FCR_CRCFXOR_CRCFXOR_1_Val << FCR_CRCFXOR_CRCFXOR_Pos) /* (FCR_CRCFXOR) Enable the Final XOR at the associated bit position Position */
+#define FCR_CRCFXOR_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (FCR_CRCFXOR) Register Mask  */
+
+
+/* -------- FCR_CRCSUM : (FCR Offset: 0x48) (R/W 32) CRC CheckSUM REGISTER -------- */
+#define FCR_CRCSUM_RESETVALUE                 _UINT32_(0x00)                                       /*  (FCR_CRCSUM) CRC CheckSUM REGISTER  Reset Value */
+
+#define FCR_CRCSUM_CRCSUM_Pos                 _UINT32_(0)                                          /* (FCR_CRCSUM) CRC Checksum Position */
+#define FCR_CRCSUM_CRCSUM_Msk                 (_UINT32_(0xFFFFFFFF) << FCR_CRCSUM_CRCSUM_Pos)      /* (FCR_CRCSUM) CRC Checksum Mask */
+#define FCR_CRCSUM_CRCSUM(value)              (FCR_CRCSUM_CRCSUM_Msk & (_UINT32_(value) << FCR_CRCSUM_CRCSUM_Pos)) /* Assignment of value for CRCSUM in the FCR_CRCSUM register */
+#define FCR_CRCSUM_Msk                        _UINT32_(0xFFFFFFFF)                                 /* (FCR_CRCSUM) Register Mask  */
+
+
+/* -------- FCR_FFLTCTRL : (FCR Offset: 0x4C) (R/W 32) Flash ECC Fault Control REGISTER -------- */
+#define FCR_FFLTCTRL_RESETVALUE               _UINT32_(0x00)                                       /*  (FCR_FFLTCTRL) Flash ECC Fault Control REGISTER  Reset Value */
+
+#define FCR_FFLTCTRL_FLTRST_Pos               _UINT32_(0)                                          /* (FCR_FFLTCTRL) Fault Reset Position */
+#define FCR_FFLTCTRL_FLTRST_Msk               (_UINT32_(0x1) << FCR_FFLTCTRL_FLTRST_Pos)           /* (FCR_FFLTCTRL) Fault Reset Mask */
+#define FCR_FFLTCTRL_FLTRST(value)            (FCR_FFLTCTRL_FLTRST_Msk & (_UINT32_(value) << FCR_FFLTCTRL_FLTRST_Pos)) /* Assignment of value for FLTRST in the FCR_FFLTCTRL register */
+#define   FCR_FFLTCTRL_FLTRST_NONE_Val        _UINT32_(0x0)                                        /* (FCR_FFLTCTRL) No Action  */
+#define   FCR_FFLTCTRL_FLTRST_RESET_Val       _UINT32_(0x1)                                        /* (FCR_FFLTCTRL) Resets all FLT SFR bits.  */
+#define FCR_FFLTCTRL_FLTRST_NONE              (FCR_FFLTCTRL_FLTRST_NONE_Val << FCR_FFLTCTRL_FLTRST_Pos) /* (FCR_FFLTCTRL) No Action Position */
+#define FCR_FFLTCTRL_FLTRST_RESET             (FCR_FFLTCTRL_FLTRST_RESET_Val << FCR_FFLTCTRL_FLTRST_Pos) /* (FCR_FFLTCTRL) Resets all FLT SFR bits. Position */
+#define FCR_FFLTCTRL_FLTEN_Pos                _UINT32_(1)                                          /* (FCR_FFLTCTRL) ECC Fault Enable bit Position */
+#define FCR_FFLTCTRL_FLTEN_Msk                (_UINT32_(0x1) << FCR_FFLTCTRL_FLTEN_Pos)            /* (FCR_FFLTCTRL) ECC Fault Enable bit Mask */
+#define FCR_FFLTCTRL_FLTEN(value)             (FCR_FFLTCTRL_FLTEN_Msk & (_UINT32_(value) << FCR_FFLTCTRL_FLTEN_Pos)) /* Assignment of value for FLTEN in the FCR_FFLTCTRL register */
+#define   FCR_FFLTCTRL_FLTEN_DISABLE_Val      _UINT32_(0x0)                                        /* (FCR_FFLTCTRL) ECC Fault Injection Disabled  */
+#define   FCR_FFLTCTRL_FLTEN_ENABLE_Val       _UINT32_(0x1)                                        /* (FCR_FFLTCTRL) ECC Fault Injection Enabled (module performs operation selected by FFLTMODE.FLTMD)  */
+#define FCR_FFLTCTRL_FLTEN_DISABLE            (FCR_FFLTCTRL_FLTEN_DISABLE_Val << FCR_FFLTCTRL_FLTEN_Pos) /* (FCR_FFLTCTRL) ECC Fault Injection Disabled Position */
+#define FCR_FFLTCTRL_FLTEN_ENABLE             (FCR_FFLTCTRL_FLTEN_ENABLE_Val << FCR_FFLTCTRL_FLTEN_Pos) /* (FCR_FFLTCTRL) ECC Fault Injection Enabled (module performs operation selected by FFLTMODE.FLTMD) Position */
+#define FCR_FFLTCTRL_Msk                      _UINT32_(0x00000003)                                 /* (FCR_FFLTCTRL) Register Mask  */
+
+
+/* -------- FCR_FFLTMODE : (FCR Offset: 0x50) (R/W 32) Flash ECC Fault Mode REGISTER -------- */
+#define FCR_FFLTMODE_RESETVALUE               _UINT32_(0x00)                                       /*  (FCR_FFLTMODE) Flash ECC Fault Mode REGISTER  Reset Value */
+
+#define FCR_FFLTMODE_CTLFLT_Pos               _UINT32_(8)                                          /* (FCR_FFLTMODE) ECC/Parity Control Fault bits Position */
+#define FCR_FFLTMODE_CTLFLT_Msk               (_UINT32_(0x7) << FCR_FFLTMODE_CTLFLT_Pos)           /* (FCR_FFLTMODE) ECC/Parity Control Fault bits Mask */
+#define FCR_FFLTMODE_CTLFLT(value)            (FCR_FFLTMODE_CTLFLT_Msk & (_UINT32_(value) << FCR_FFLTMODE_CTLFLT_Pos)) /* Assignment of value for CTLFLT in the FCR_FFLTMODE register */
+#define   FCR_FFLTMODE_CTLFLT_0_Val           _UINT32_(0x0)                                        /* (FCR_FFLTMODE) No Fault Injected  */
+#define   FCR_FFLTMODE_CTLFLT_1_Val           _UINT32_(0x1)                                        /* (FCR_FFLTMODE) Inject a Fault on to the associated ECC/Parity Control bits (CTL[n])  */
+#define FCR_FFLTMODE_CTLFLT_0                 (FCR_FFLTMODE_CTLFLT_0_Val << FCR_FFLTMODE_CTLFLT_Pos) /* (FCR_FFLTMODE) No Fault Injected Position */
+#define FCR_FFLTMODE_CTLFLT_1                 (FCR_FFLTMODE_CTLFLT_1_Val << FCR_FFLTMODE_CTLFLT_Pos) /* (FCR_FFLTMODE) Inject a Fault on to the associated ECC/Parity Control bits (CTL[n]) Position */
+#define FCR_FFLTMODE_FLTMD_Pos                _UINT32_(12)                                         /* (FCR_FFLTMODE) Fault Mode Control Position */
+#define FCR_FFLTMODE_FLTMD_Msk                (_UINT32_(0x7) << FCR_FFLTMODE_FLTMD_Pos)            /* (FCR_FFLTMODE) Fault Mode Control Mask */
+#define FCR_FFLTMODE_FLTMD(value)             (FCR_FFLTMODE_FLTMD_Msk & (_UINT32_(value) << FCR_FFLTMODE_FLTMD_Pos)) /* Assignment of value for FLTMD in the FCR_FFLTMODE register */
+#define   FCR_FFLTMODE_FLTMD_DISABLE_Val      _UINT32_(0x0)                                        /* (FCR_FFLTMODE) Fault Injection Disabled  */
+#define   FCR_FFLTMODE_FLTMD_CAPT_Val         _UINT32_(0x2)                                        /* (FCR_FFLTMODE) Fault Capture Mode Enabled - Captures the address (in FLTADR) and Syndrome in (FLTSYN)  */
+#define   FCR_FFLTMODE_FLTMD_SINGLEREAD_Val   _UINT32_(0x4)                                        /* (FCR_FFLTMODE) Single Fault Injection (at bit selected by FLT1PTR) for Reads  */
+#define   FCR_FFLTMODE_FLTMD_DOUBLEREAD_Val   _UINT32_(0x5)                                        /* (FCR_FFLTMODE) Double Fault Injection for Reads  */
+#define   FCR_FFLTMODE_FLTMD_SINGLEWRITE_Val  _UINT32_(0x6)                                        /* (FCR_FFLTMODE) Single Fault Injection (at bit selected by FLT1PTR) for Writes  */
+#define   FCR_FFLTMODE_FLTMD_DOUBLEWRITE_Val  _UINT32_(0x7)                                        /* (FCR_FFLTMODE) Double Fault Injection for Writes  */
+#define FCR_FFLTMODE_FLTMD_DISABLE            (FCR_FFLTMODE_FLTMD_DISABLE_Val << FCR_FFLTMODE_FLTMD_Pos) /* (FCR_FFLTMODE) Fault Injection Disabled Position */
+#define FCR_FFLTMODE_FLTMD_CAPT               (FCR_FFLTMODE_FLTMD_CAPT_Val << FCR_FFLTMODE_FLTMD_Pos) /* (FCR_FFLTMODE) Fault Capture Mode Enabled - Captures the address (in FLTADR) and Syndrome in (FLTSYN) Position */
+#define FCR_FFLTMODE_FLTMD_SINGLEREAD         (FCR_FFLTMODE_FLTMD_SINGLEREAD_Val << FCR_FFLTMODE_FLTMD_Pos) /* (FCR_FFLTMODE) Single Fault Injection (at bit selected by FLT1PTR) for Reads Position */
+#define FCR_FFLTMODE_FLTMD_DOUBLEREAD         (FCR_FFLTMODE_FLTMD_DOUBLEREAD_Val << FCR_FFLTMODE_FLTMD_Pos) /* (FCR_FFLTMODE) Double Fault Injection for Reads Position */
+#define FCR_FFLTMODE_FLTMD_SINGLEWRITE        (FCR_FFLTMODE_FLTMD_SINGLEWRITE_Val << FCR_FFLTMODE_FLTMD_Pos) /* (FCR_FFLTMODE) Single Fault Injection (at bit selected by FLT1PTR) for Writes Position */
+#define FCR_FFLTMODE_FLTMD_DOUBLEWRITE        (FCR_FFLTMODE_FLTMD_DOUBLEWRITE_Val << FCR_FFLTMODE_FLTMD_Pos) /* (FCR_FFLTMODE) Double Fault Injection for Writes Position */
+#define FCR_FFLTMODE_Msk                      _UINT32_(0x00007700)                                 /* (FCR_FFLTMODE) Register Mask  */
+
+
+/* -------- FCR_FFLTPTR : (FCR Offset: 0x54) (R/W 32) Flash ECC Fault Pointer REGISTER -------- */
+#define FCR_FFLTPTR_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_FFLTPTR) Flash ECC Fault Pointer REGISTER  Reset Value */
+
+#define FCR_FFLTPTR_FLTPTR1_Pos               _UINT32_(0)                                          /* (FCR_FFLTPTR) Fault 1 Injection Pointer Position */
+#define FCR_FFLTPTR_FLTPTR1_Msk               (_UINT32_(0xFF) << FCR_FFLTPTR_FLTPTR1_Pos)          /* (FCR_FFLTPTR) Fault 1 Injection Pointer Mask */
+#define FCR_FFLTPTR_FLTPTR1(value)            (FCR_FFLTPTR_FLTPTR1_Msk & (_UINT32_(value) << FCR_FFLTPTR_FLTPTR1_Pos)) /* Assignment of value for FLTPTR1 in the FCR_FFLTPTR register */
+#define FCR_FFLTPTR_FLTPTR2_Pos               _UINT32_(16)                                         /* (FCR_FFLTPTR) Fault 2 Injection Pointer Position */
+#define FCR_FFLTPTR_FLTPTR2_Msk               (_UINT32_(0xFF) << FCR_FFLTPTR_FLTPTR2_Pos)          /* (FCR_FFLTPTR) Fault 2 Injection Pointer Mask */
+#define FCR_FFLTPTR_FLTPTR2(value)            (FCR_FFLTPTR_FLTPTR2_Msk & (_UINT32_(value) << FCR_FFLTPTR_FLTPTR2_Pos)) /* Assignment of value for FLTPTR2 in the FCR_FFLTPTR register */
+#define FCR_FFLTPTR_Msk                       _UINT32_(0x00FF00FF)                                 /* (FCR_FFLTPTR) Register Mask  */
+
+
+/* -------- FCR_FFLTADR : (FCR Offset: 0x58) (R/W 32) Flash ECC Fault Address REGISTER -------- */
+#define FCR_FFLTADR_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_FFLTADR) Flash ECC Fault Address REGISTER  Reset Value */
+
+#define FCR_FFLTADR_FLTADR_Pos                _UINT32_(0)                                          /* (FCR_FFLTADR) Fault Injection Address Position */
+#define FCR_FFLTADR_FLTADR_Msk                (_UINT32_(0xFFFFFFF) << FCR_FFLTADR_FLTADR_Pos)      /* (FCR_FFLTADR) Fault Injection Address Mask */
+#define FCR_FFLTADR_FLTADR(value)             (FCR_FFLTADR_FLTADR_Msk & (_UINT32_(value) << FCR_FFLTADR_FLTADR_Pos)) /* Assignment of value for FLTADR in the FCR_FFLTADR register */
+#define FCR_FFLTADR_Msk                       _UINT32_(0x0FFFFFFF)                                 /* (FCR_FFLTADR) Register Mask  */
+
+
+/* -------- FCR_FFLTCAP : (FCR Offset: 0x5C) ( R/ 32) Flash ECC Fault Capture Address REGISTER -------- */
+#define FCR_FFLTCAP_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_FFLTCAP) Flash ECC Fault Capture Address REGISTER  Reset Value */
+
+#define FCR_FFLTCAP_FLTADR_Pos                _UINT32_(0)                                          /* (FCR_FFLTCAP) Fault Capture Address Position */
+#define FCR_FFLTCAP_FLTADR_Msk                (_UINT32_(0xFFFFFFF) << FCR_FFLTCAP_FLTADR_Pos)      /* (FCR_FFLTCAP) Fault Capture Address Mask */
+#define FCR_FFLTCAP_FLTADR(value)             (FCR_FFLTCAP_FLTADR_Msk & (_UINT32_(value) << FCR_FFLTCAP_FLTADR_Pos)) /* Assignment of value for FLTADR in the FCR_FFLTCAP register */
+#define FCR_FFLTCAP_Msk                       _UINT32_(0x0FFFFFFF)                                 /* (FCR_FFLTCAP) Register Mask  */
+
+
+/* -------- FCR_FFLTPAR : (FCR Offset: 0x60) ( R/ 32) Flash ECC Fault Parity REGISTER -------- */
+#define FCR_FFLTPAR_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_FFLTPAR) Flash ECC Fault Parity REGISTER  Reset Value */
+
+#define FCR_FFLTPAR_SECIN_Pos                 _UINT32_(0)                                          /* (FCR_FFLTPAR) The Single Error Parity bits from Flash Position */
+#define FCR_FFLTPAR_SECIN_Msk                 (_UINT32_(0xFF) << FCR_FFLTPAR_SECIN_Pos)            /* (FCR_FFLTPAR) The Single Error Parity bits from Flash Mask */
+#define FCR_FFLTPAR_SECIN(value)              (FCR_FFLTPAR_SECIN_Msk & (_UINT32_(value) << FCR_FFLTPAR_SECIN_Pos)) /* Assignment of value for SECIN in the FCR_FFLTPAR register */
+#define FCR_FFLTPAR_DEDIN_Pos                 _UINT32_(15)                                         /* (FCR_FFLTPAR) The Overall Parity from Flash Position */
+#define FCR_FFLTPAR_DEDIN_Msk                 (_UINT32_(0x1) << FCR_FFLTPAR_DEDIN_Pos)             /* (FCR_FFLTPAR) The Overall Parity from Flash Mask */
+#define FCR_FFLTPAR_DEDIN(value)              (FCR_FFLTPAR_DEDIN_Msk & (_UINT32_(value) << FCR_FFLTPAR_DEDIN_Pos)) /* Assignment of value for DEDIN in the FCR_FFLTPAR register */
+#define FCR_FFLTPAR_SECOUT_Pos                _UINT32_(16)                                         /* (FCR_FFLTPAR) The Calculated Single Error Parity bits Position */
+#define FCR_FFLTPAR_SECOUT_Msk                (_UINT32_(0xFF) << FCR_FFLTPAR_SECOUT_Pos)           /* (FCR_FFLTPAR) The Calculated Single Error Parity bits Mask */
+#define FCR_FFLTPAR_SECOUT(value)             (FCR_FFLTPAR_SECOUT_Msk & (_UINT32_(value) << FCR_FFLTPAR_SECOUT_Pos)) /* Assignment of value for SECOUT in the FCR_FFLTPAR register */
+#define FCR_FFLTPAR_DEDOUT_Pos                _UINT32_(31)                                         /* (FCR_FFLTPAR) The Calculated Overall Parity used in Double Error Detection Position */
+#define FCR_FFLTPAR_DEDOUT_Msk                (_UINT32_(0x1) << FCR_FFLTPAR_DEDOUT_Pos)            /* (FCR_FFLTPAR) The Calculated Overall Parity used in Double Error Detection Mask */
+#define FCR_FFLTPAR_DEDOUT(value)             (FCR_FFLTPAR_DEDOUT_Msk & (_UINT32_(value) << FCR_FFLTPAR_DEDOUT_Pos)) /* Assignment of value for DEDOUT in the FCR_FFLTPAR register */
+#define FCR_FFLTPAR_Msk                       _UINT32_(0x80FF80FF)                                 /* (FCR_FFLTPAR) Register Mask  */
+
+
+/* -------- FCR_FFLTSYN : (FCR Offset: 0x64) ( R/ 32) Flash ECC Fault Syndrome REGISTER -------- */
+#define FCR_FFLTSYN_RESETVALUE                _UINT32_(0x00)                                       /*  (FCR_FFLTSYN) Flash ECC Fault Syndrome REGISTER  Reset Value */
+
+#define FCR_FFLTSYN_SECSYN_Pos                _UINT32_(0)                                          /* (FCR_FFLTSYN) Single Error Correction Syndrome Position */
+#define FCR_FFLTSYN_SECSYN_Msk                (_UINT32_(0xFF) << FCR_FFLTSYN_SECSYN_Pos)           /* (FCR_FFLTSYN) Single Error Correction Syndrome Mask */
+#define FCR_FFLTSYN_SECSYN(value)             (FCR_FFLTSYN_SECSYN_Msk & (_UINT32_(value) << FCR_FFLTSYN_SECSYN_Pos)) /* Assignment of value for SECSYN in the FCR_FFLTSYN register */
+#define FCR_FFLTSYN_DEDSYN_Pos                _UINT32_(15)                                         /* (FCR_FFLTSYN) DED Syndrome Position */
+#define FCR_FFLTSYN_DEDSYN_Msk                (_UINT32_(0x1) << FCR_FFLTSYN_DEDSYN_Pos)            /* (FCR_FFLTSYN) DED Syndrome Mask */
+#define FCR_FFLTSYN_DEDSYN(value)             (FCR_FFLTSYN_DEDSYN_Msk & (_UINT32_(value) << FCR_FFLTSYN_DEDSYN_Pos)) /* Assignment of value for DEDSYN in the FCR_FFLTSYN register */
+#define   FCR_FFLTSYN_DEDSYN_0_Val            _UINT32_(0x0)                                        /* (FCR_FFLTSYN) Calculated Overall Parity Concurs with Read Overall Parity  */
+#define   FCR_FFLTSYN_DEDSYN_1_Val            _UINT32_(0x1)                                        /* (FCR_FFLTSYN) Calculated Overall Parity Differs from Read Overall Parity  */
+#define FCR_FFLTSYN_DEDSYN_0                  (FCR_FFLTSYN_DEDSYN_0_Val << FCR_FFLTSYN_DEDSYN_Pos) /* (FCR_FFLTSYN) Calculated Overall Parity Concurs with Read Overall Parity Position */
+#define FCR_FFLTSYN_DEDSYN_1                  (FCR_FFLTSYN_DEDSYN_1_Val << FCR_FFLTSYN_DEDSYN_Pos) /* (FCR_FFLTSYN) Calculated Overall Parity Differs from Read Overall Parity Position */
+#define FCR_FFLTSYN_DSERR_Pos                 _UINT32_(16)                                         /* (FCR_FFLTSYN) Double Error Detected & Single Error Corrected Position */
+#define FCR_FFLTSYN_DSERR_Msk                 (_UINT32_(0x3) << FCR_FFLTSYN_DSERR_Pos)             /* (FCR_FFLTSYN) Double Error Detected & Single Error Corrected Mask */
+#define FCR_FFLTSYN_DSERR(value)              (FCR_FFLTSYN_DSERR_Msk & (_UINT32_(value) << FCR_FFLTSYN_DSERR_Pos)) /* Assignment of value for DSERR in the FCR_FFLTSYN register */
+#define   FCR_FFLTSYN_DSERR_NONE_Val          _UINT32_(0x0)                                        /* (FCR_FFLTSYN) No Errors  */
+#define   FCR_FFLTSYN_DSERR_SINGLE_Val        _UINT32_(0x1)                                        /* (FCR_FFLTSYN) Single Error Corrected  */
+#define   FCR_FFLTSYN_DSERR_DOUBLE_10_Val     _UINT32_(0x2)                                        /* (FCR_FFLTSYN) Double Error Detected  */
+#define   FCR_FFLTSYN_DSERR_DOUBLE_11_Val     _UINT32_(0x3)                                        /* (FCR_FFLTSYN) Double Error Detected  */
+#define FCR_FFLTSYN_DSERR_NONE                (FCR_FFLTSYN_DSERR_NONE_Val << FCR_FFLTSYN_DSERR_Pos) /* (FCR_FFLTSYN) No Errors Position */
+#define FCR_FFLTSYN_DSERR_SINGLE              (FCR_FFLTSYN_DSERR_SINGLE_Val << FCR_FFLTSYN_DSERR_Pos) /* (FCR_FFLTSYN) Single Error Corrected Position */
+#define FCR_FFLTSYN_DSERR_DOUBLE_10           (FCR_FFLTSYN_DSERR_DOUBLE_10_Val << FCR_FFLTSYN_DSERR_Pos) /* (FCR_FFLTSYN) Double Error Detected Position */
+#define FCR_FFLTSYN_DSERR_DOUBLE_11           (FCR_FFLTSYN_DSERR_DOUBLE_11_Val << FCR_FFLTSYN_DSERR_Pos) /* (FCR_FFLTSYN) Double Error Detected Position */
+#define FCR_FFLTSYN_CERR_Pos                  _UINT32_(18)                                         /* (FCR_FFLTSYN) ECC Control bit Error Position */
+#define FCR_FFLTSYN_CERR_Msk                  (_UINT32_(0x1) << FCR_FFLTSYN_CERR_Pos)              /* (FCR_FFLTSYN) ECC Control bit Error Mask */
+#define FCR_FFLTSYN_CERR(value)               (FCR_FFLTSYN_CERR_Msk & (_UINT32_(value) << FCR_FFLTSYN_CERR_Pos)) /* Assignment of value for CERR in the FCR_FFLTSYN register */
+#define   FCR_FFLTSYN_CERR_NONE_Val           _UINT32_(0x0)                                        /* (FCR_FFLTSYN) No Control bit Error (ECCSTAT either 111 or 000)  */
+#define   FCR_FFLTSYN_CERR_SINGLE_Val         _UINT32_(0x1)                                        /* (FCR_FFLTSYN) Single Control Bit Error  */
+#define FCR_FFLTSYN_CERR_NONE                 (FCR_FFLTSYN_CERR_NONE_Val << FCR_FFLTSYN_CERR_Pos)  /* (FCR_FFLTSYN) No Control bit Error (ECCSTAT either 111 or 000) Position */
+#define FCR_FFLTSYN_CERR_SINGLE               (FCR_FFLTSYN_CERR_SINGLE_Val << FCR_FFLTSYN_CERR_Pos) /* (FCR_FFLTSYN) Single Control Bit Error Position */
+#define FCR_FFLTSYN_CTLSTAT_Pos               _UINT32_(24)                                         /* (FCR_FFLTSYN) Parity vs ECC Control Status Position */
+#define FCR_FFLTSYN_CTLSTAT_Msk               (_UINT32_(0x7) << FCR_FFLTSYN_CTLSTAT_Pos)           /* (FCR_FFLTSYN) Parity vs ECC Control Status Mask */
+#define FCR_FFLTSYN_CTLSTAT(value)            (FCR_FFLTSYN_CTLSTAT_Msk & (_UINT32_(value) << FCR_FFLTSYN_CTLSTAT_Pos)) /* Assignment of value for CTLSTAT in the FCR_FFLTSYN register */
+#define   FCR_FFLTSYN_CTLSTAT_USEDECC_0_Val   _UINT32_(0x0)                                        /* (FCR_FFLTSYN) Calculation used ECC (i.e. programming used quad write)  */
+#define   FCR_FFLTSYN_CTLSTAT_USEDECC_1_Val   _UINT32_(0x1)                                        /* (FCR_FFLTSYN) Calculation used ECC (i.e. programming used quad write)  */
+#define   FCR_FFLTSYN_CTLSTAT_USEDECC_10_Val  _UINT32_(0x2)                                        /* (FCR_FFLTSYN) Calculation used ECC (i.e. programming used quad write)  */
+#define   FCR_FFLTSYN_CTLSTAT_USEDPARITY_11_Val _UINT32_(0x3)                                        /* (FCR_FFLTSYN) Calculation used Parity (i.e. programming used single write)  */
+#define   FCR_FFLTSYN_CTLSTAT_USEDECC_100_Val _UINT32_(0x4)                                        /* (FCR_FFLTSYN) Calculation used ECC (i.e. programming used quad write)  */
+#define   FCR_FFLTSYN_CTLSTAT_USEDPARITY_101_Val _UINT32_(0x5)                                        /* (FCR_FFLTSYN) Calculation used Parity (i.e. programming used single write)  */
+#define   FCR_FFLTSYN_CTLSTAT_USEDPARITY_110_Val _UINT32_(0x6)                                        /* (FCR_FFLTSYN) Calculation used Parity (i.e. programming used single write)  */
+#define   FCR_FFLTSYN_CTLSTAT_USEDPARITY_111_Val _UINT32_(0x7)                                        /* (FCR_FFLTSYN) Calculation used Parity (i.e. programming used single write)  */
+#define FCR_FFLTSYN_CTLSTAT_USEDECC_0         (FCR_FFLTSYN_CTLSTAT_USEDECC_0_Val << FCR_FFLTSYN_CTLSTAT_Pos) /* (FCR_FFLTSYN) Calculation used ECC (i.e. programming used quad write) Position */
+#define FCR_FFLTSYN_CTLSTAT_USEDECC_1         (FCR_FFLTSYN_CTLSTAT_USEDECC_1_Val << FCR_FFLTSYN_CTLSTAT_Pos) /* (FCR_FFLTSYN) Calculation used ECC (i.e. programming used quad write) Position */
+#define FCR_FFLTSYN_CTLSTAT_USEDECC_10        (FCR_FFLTSYN_CTLSTAT_USEDECC_10_Val << FCR_FFLTSYN_CTLSTAT_Pos) /* (FCR_FFLTSYN) Calculation used ECC (i.e. programming used quad write) Position */
+#define FCR_FFLTSYN_CTLSTAT_USEDPARITY_11     (FCR_FFLTSYN_CTLSTAT_USEDPARITY_11_Val << FCR_FFLTSYN_CTLSTAT_Pos) /* (FCR_FFLTSYN) Calculation used Parity (i.e. programming used single write) Position */
+#define FCR_FFLTSYN_CTLSTAT_USEDECC_100       (FCR_FFLTSYN_CTLSTAT_USEDECC_100_Val << FCR_FFLTSYN_CTLSTAT_Pos) /* (FCR_FFLTSYN) Calculation used ECC (i.e. programming used quad write) Position */
+#define FCR_FFLTSYN_CTLSTAT_USEDPARITY_101    (FCR_FFLTSYN_CTLSTAT_USEDPARITY_101_Val << FCR_FFLTSYN_CTLSTAT_Pos) /* (FCR_FFLTSYN) Calculation used Parity (i.e. programming used single write) Position */
+#define FCR_FFLTSYN_CTLSTAT_USEDPARITY_110    (FCR_FFLTSYN_CTLSTAT_USEDPARITY_110_Val << FCR_FFLTSYN_CTLSTAT_Pos) /* (FCR_FFLTSYN) Calculation used Parity (i.e. programming used single write) Position */
+#define FCR_FFLTSYN_CTLSTAT_USEDPARITY_111    (FCR_FFLTSYN_CTLSTAT_USEDPARITY_111_Val << FCR_FFLTSYN_CTLSTAT_Pos) /* (FCR_FFLTSYN) Calculation used Parity (i.e. programming used single write) Position */
+#define FCR_FFLTSYN_PERR_Pos                  _UINT32_(28)                                         /* (FCR_FFLTSYN) Per Word (n=3:0) Parity Error Status Position */
+#define FCR_FFLTSYN_PERR_Msk                  (_UINT32_(0xF) << FCR_FFLTSYN_PERR_Pos)              /* (FCR_FFLTSYN) Per Word (n=3:0) Parity Error Status Mask */
+#define FCR_FFLTSYN_PERR(value)               (FCR_FFLTSYN_PERR_Msk & (_UINT32_(value) << FCR_FFLTSYN_PERR_Pos)) /* Assignment of value for PERR in the FCR_FFLTSYN register */
+#define   FCR_FFLTSYN_PERR_NONE_Val           _UINT32_(0x0)                                        /* (FCR_FFLTSYN) No Parity Error on Word n  */
+#define   FCR_FFLTSYN_PERR_ERROR_Val          _UINT32_(0x1)                                        /* (FCR_FFLTSYN) Parity Error on Word n  */
+#define FCR_FFLTSYN_PERR_NONE                 (FCR_FFLTSYN_PERR_NONE_Val << FCR_FFLTSYN_PERR_Pos)  /* (FCR_FFLTSYN) No Parity Error on Word n Position */
+#define FCR_FFLTSYN_PERR_ERROR                (FCR_FFLTSYN_PERR_ERROR_Val << FCR_FFLTSYN_PERR_Pos) /* (FCR_FFLTSYN) Parity Error on Word n Position */
+#define FCR_FFLTSYN_Msk                       _UINT32_(0xF70780FF)                                 /* (FCR_FFLTSYN) Register Mask  */
+
+
+/* -------- FCR_CRP : (FCR Offset: 0x68) (R/W 32) CFM Page Read Protection REGISTER (CFM8) -------- */
+#define FCR_CRP_RESETVALUE                    _UINT32_(0xC20000)                                   /*  (FCR_CRP) CFM Page Read Protection REGISTER (CFM8)  Reset Value */
+
+#define FCR_CRP_BC1ARP_Pos                    _UINT32_(0)                                          /* (FCR_CRP) Panel 1 Read Protect BootCfg1A Position */
+#define FCR_CRP_BC1ARP_Msk                    (_UINT32_(0x1) << FCR_CRP_BC1ARP_Pos)                /* (FCR_CRP) Panel 1 Read Protect BootCfg1A Mask */
+#define FCR_CRP_BC1ARP(value)                 (FCR_CRP_BC1ARP_Msk & (_UINT32_(value) << FCR_CRP_BC1ARP_Pos)) /* Assignment of value for BC1ARP in the FCR_CRP register */
+#define   FCR_CRP_BC1ARP_DISABLE_Val          _UINT32_(0x0)                                        /* (FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FCR_CRP_BC1ARP_ENABLE_Val           _UINT32_(0x1)                                        /* (FCR_CRP) Read Protection for this Page is Enabled  */
+#define FCR_CRP_BC1ARP_DISABLE                (FCR_CRP_BC1ARP_DISABLE_Val << FCR_CRP_BC1ARP_Pos)   /* (FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FCR_CRP_BC1ARP_ENABLE                 (FCR_CRP_BC1ARP_ENABLE_Val << FCR_CRP_BC1ARP_Pos)    /* (FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FCR_CRP_UO1RP_Pos                     _UINT32_(1)                                          /* (FCR_CRP) Panel 1 Read Protect UserOTP1 Position */
+#define FCR_CRP_UO1RP_Msk                     (_UINT32_(0x1) << FCR_CRP_UO1RP_Pos)                 /* (FCR_CRP) Panel 1 Read Protect UserOTP1 Mask */
+#define FCR_CRP_UO1RP(value)                  (FCR_CRP_UO1RP_Msk & (_UINT32_(value) << FCR_CRP_UO1RP_Pos)) /* Assignment of value for UO1RP in the FCR_CRP register */
+#define   FCR_CRP_UO1RP_DISABLE_Val           _UINT32_(0x0)                                        /* (FCR_CRP) Read Protection for this Page is Disabled  */
+#define FCR_CRP_UO1RP_DISABLE                 (FCR_CRP_UO1RP_DISABLE_Val << FCR_CRP_UO1RP_Pos)     /* (FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FCR_CRP_BC1RP_Pos                     _UINT32_(2)                                          /* (FCR_CRP) Panel 1 Read Protect BootCfg1 Position */
+#define FCR_CRP_BC1RP_Msk                     (_UINT32_(0x1) << FCR_CRP_BC1RP_Pos)                 /* (FCR_CRP) Panel 1 Read Protect BootCfg1 Mask */
+#define FCR_CRP_BC1RP(value)                  (FCR_CRP_BC1RP_Msk & (_UINT32_(value) << FCR_CRP_BC1RP_Pos)) /* Assignment of value for BC1RP in the FCR_CRP register */
+#define   FCR_CRP_BC1RP_DISABLE_Val           _UINT32_(0x0)                                        /* (FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FCR_CRP_BC1RP_ENABLE_Val            _UINT32_(0x1)                                        /* (FCR_CRP) Read Protection for this Page is Enabled  */
+#define FCR_CRP_BC1RP_DISABLE                 (FCR_CRP_BC1RP_DISABLE_Val << FCR_CRP_BC1RP_Pos)     /* (FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FCR_CRP_BC1RP_ENABLE                  (FCR_CRP_BC1RP_ENABLE_Val << FCR_CRP_BC1RP_Pos)      /* (FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FCR_CRP_RCRP_Pos                      _UINT32_(3)                                          /* (FCR_CRP) Panel 1 Read Protect ROMCfg Position */
+#define FCR_CRP_RCRP_Msk                      (_UINT32_(0x1) << FCR_CRP_RCRP_Pos)                  /* (FCR_CRP) Panel 1 Read Protect ROMCfg Mask */
+#define FCR_CRP_RCRP(value)                   (FCR_CRP_RCRP_Msk & (_UINT32_(value) << FCR_CRP_RCRP_Pos)) /* Assignment of value for RCRP in the FCR_CRP register */
+#define   FCR_CRP_RCRP_DISABLE_Val            _UINT32_(0x0)                                        /* (FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FCR_CRP_RCRP_ENABLE_Val             _UINT32_(0x1)                                        /* (FCR_CRP) Read Protection for this Page is Enabled  */
+#define FCR_CRP_RCRP_DISABLE                  (FCR_CRP_RCRP_DISABLE_Val << FCR_CRP_RCRP_Pos)       /* (FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FCR_CRP_RCRP_ENABLE                   (FCR_CRP_RCRP_ENABLE_Val << FCR_CRP_RCRP_Pos)        /* (FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FCR_CRP_VSSRP0_Pos                    _UINT32_(4)                                          /* (FCR_CRP) Panel 1 Read Protect VSSn Position */
+#define FCR_CRP_VSSRP0_Msk                    (_UINT32_(0x1) << FCR_CRP_VSSRP0_Pos)                /* (FCR_CRP) Panel 1 Read Protect VSSn Mask */
+#define FCR_CRP_VSSRP0(value)                 (FCR_CRP_VSSRP0_Msk & (_UINT32_(value) << FCR_CRP_VSSRP0_Pos)) /* Assignment of value for VSSRP0 in the FCR_CRP register */
+#define   FCR_CRP_VSSRP0_DISABLE_Val          _UINT32_(0x0)                                        /* (FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FCR_CRP_VSSRP0_ENABLE_Val           _UINT32_(0x1)                                        /* (FCR_CRP) Read Protection for this Page is Enabled  */
+#define FCR_CRP_VSSRP0_DISABLE                (FCR_CRP_VSSRP0_DISABLE_Val << FCR_CRP_VSSRP0_Pos)   /* (FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FCR_CRP_VSSRP0_ENABLE                 (FCR_CRP_VSSRP0_ENABLE_Val << FCR_CRP_VSSRP0_Pos)    /* (FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FCR_CRP_VSSRP1_Pos                    _UINT32_(5)                                          /* (FCR_CRP) Panel 1 Read Protect VSSn Position */
+#define FCR_CRP_VSSRP1_Msk                    (_UINT32_(0x1) << FCR_CRP_VSSRP1_Pos)                /* (FCR_CRP) Panel 1 Read Protect VSSn Mask */
+#define FCR_CRP_VSSRP1(value)                 (FCR_CRP_VSSRP1_Msk & (_UINT32_(value) << FCR_CRP_VSSRP1_Pos)) /* Assignment of value for VSSRP1 in the FCR_CRP register */
+#define   FCR_CRP_VSSRP1_DISABLE_Val          _UINT32_(0x0)                                        /* (FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FCR_CRP_VSSRP1_ENABLE_Val           _UINT32_(0x1)                                        /* (FCR_CRP) Read Protection for this Page is Enabled  */
+#define FCR_CRP_VSSRP1_DISABLE                (FCR_CRP_VSSRP1_DISABLE_Val << FCR_CRP_VSSRP1_Pos)   /* (FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FCR_CRP_VSSRP1_ENABLE                 (FCR_CRP_VSSRP1_ENABLE_Val << FCR_CRP_VSSRP1_Pos)    /* (FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FCR_CRP_TRP_Pos                       _UINT32_(6)                                          /* (FCR_CRP) Panel 1 Read Protect Test Position */
+#define FCR_CRP_TRP_Msk                       (_UINT32_(0x1) << FCR_CRP_TRP_Pos)                   /* (FCR_CRP) Panel 1 Read Protect Test Mask */
+#define FCR_CRP_TRP(value)                    (FCR_CRP_TRP_Msk & (_UINT32_(value) << FCR_CRP_TRP_Pos)) /* Assignment of value for TRP in the FCR_CRP register */
+#define   FCR_CRP_TRP_DISABLE_Val             _UINT32_(0x0)                                        /* (FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FCR_CRP_TRP_ENABLE_Val              _UINT32_(0x1)                                        /* (FCR_CRP) Read Protection for this Page is Enabled  */
+#define FCR_CRP_TRP_DISABLE                   (FCR_CRP_TRP_DISABLE_Val << FCR_CRP_TRP_Pos)         /* (FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FCR_CRP_TRP_ENABLE                    (FCR_CRP_TRP_ENABLE_Val << FCR_CRP_TRP_Pos)          /* (FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FCR_CRP_CORP_Pos                      _UINT32_(7)                                          /* (FCR_CRP) Panel 1 Read Protect CalOTP Position */
+#define FCR_CRP_CORP_Msk                      (_UINT32_(0x1) << FCR_CRP_CORP_Pos)                  /* (FCR_CRP) Panel 1 Read Protect CalOTP Mask */
+#define FCR_CRP_CORP(value)                   (FCR_CRP_CORP_Msk & (_UINT32_(value) << FCR_CRP_CORP_Pos)) /* Assignment of value for CORP in the FCR_CRP register */
+#define   FCR_CRP_CORP_DISABLE_Val            _UINT32_(0x0)                                        /* (FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FCR_CRP_CORP_ENABLE_Val             _UINT32_(0x1)                                        /* (FCR_CRP) Read Protection for this Page is Enabled  */
+#define FCR_CRP_CORP_DISABLE                  (FCR_CRP_CORP_DISABLE_Val << FCR_CRP_CORP_Pos)       /* (FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FCR_CRP_CORP_ENABLE                   (FCR_CRP_CORP_ENABLE_Val << FCR_CRP_CORP_Pos)        /* (FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FCR_CRP_BC1ARPLOCK_Pos                _UINT32_(16)                                         /* (FCR_CRP) Panel 1 Lock Read Protection BootCfg1A Position */
+#define FCR_CRP_BC1ARPLOCK_Msk                (_UINT32_(0x1) << FCR_CRP_BC1ARPLOCK_Pos)            /* (FCR_CRP) Panel 1 Lock Read Protection BootCfg1A Mask */
+#define FCR_CRP_BC1ARPLOCK(value)             (FCR_CRP_BC1ARPLOCK_Msk & (_UINT32_(value) << FCR_CRP_BC1ARPLOCK_Pos)) /* Assignment of value for BC1ARPLOCK in the FCR_CRP register */
+#define   FCR_CRP_BC1ARPLOCK_UNLOCKED_Val     _UINT32_(0x0)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCR_CRP_BC1ARPLOCK_LOCKED_Val       _UINT32_(0x1)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FCR_CRP_BC1ARPLOCK_UNLOCKED           (FCR_CRP_BC1ARPLOCK_UNLOCKED_Val << FCR_CRP_BC1ARPLOCK_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCR_CRP_BC1ARPLOCK_LOCKED             (FCR_CRP_BC1ARPLOCK_LOCKED_Val << FCR_CRP_BC1ARPLOCK_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FCR_CRP_UO1RPLOCK_Pos                 _UINT32_(17)                                         /* (FCR_CRP) Panel 1 Lock Read Protection UserOTP1 Position */
+#define FCR_CRP_UO1RPLOCK_Msk                 (_UINT32_(0x1) << FCR_CRP_UO1RPLOCK_Pos)             /* (FCR_CRP) Panel 1 Lock Read Protection UserOTP1 Mask */
+#define FCR_CRP_UO1RPLOCK(value)              (FCR_CRP_UO1RPLOCK_Msk & (_UINT32_(value) << FCR_CRP_UO1RPLOCK_Pos)) /* Assignment of value for UO1RPLOCK in the FCR_CRP register */
+#define   FCR_CRP_UO1RPLOCK_LOCKED_Val        _UINT32_(0x1)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FCR_CRP_UO1RPLOCK_LOCKED              (FCR_CRP_UO1RPLOCK_LOCKED_Val << FCR_CRP_UO1RPLOCK_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FCR_CRP_BC1RPLOCK_Pos                 _UINT32_(18)                                         /* (FCR_CRP) Panel 1 Lock Read Protection BootCfg1 Position */
+#define FCR_CRP_BC1RPLOCK_Msk                 (_UINT32_(0x1) << FCR_CRP_BC1RPLOCK_Pos)             /* (FCR_CRP) Panel 1 Lock Read Protection BootCfg1 Mask */
+#define FCR_CRP_BC1RPLOCK(value)              (FCR_CRP_BC1RPLOCK_Msk & (_UINT32_(value) << FCR_CRP_BC1RPLOCK_Pos)) /* Assignment of value for BC1RPLOCK in the FCR_CRP register */
+#define   FCR_CRP_BC1RPLOCK_UNLOCKED_Val      _UINT32_(0x0)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCR_CRP_BC1RPLOCK_LOCKED_Val        _UINT32_(0x1)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FCR_CRP_BC1RPLOCK_UNLOCKED            (FCR_CRP_BC1RPLOCK_UNLOCKED_Val << FCR_CRP_BC1RPLOCK_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCR_CRP_BC1RPLOCK_LOCKED              (FCR_CRP_BC1RPLOCK_LOCKED_Val << FCR_CRP_BC1RPLOCK_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FCR_CRP_RCRPLOCK_Pos                  _UINT32_(19)                                         /* (FCR_CRP) Panel 1 Lock Read Protection ROMCfg Position */
+#define FCR_CRP_RCRPLOCK_Msk                  (_UINT32_(0x1) << FCR_CRP_RCRPLOCK_Pos)              /* (FCR_CRP) Panel 1 Lock Read Protection ROMCfg Mask */
+#define FCR_CRP_RCRPLOCK(value)               (FCR_CRP_RCRPLOCK_Msk & (_UINT32_(value) << FCR_CRP_RCRPLOCK_Pos)) /* Assignment of value for RCRPLOCK in the FCR_CRP register */
+#define   FCR_CRP_RCRPLOCK_UNLOCKED_Val       _UINT32_(0x0)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCR_CRP_RCRPLOCK_LOCKED_Val         _UINT32_(0x1)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FCR_CRP_RCRPLOCK_UNLOCKED             (FCR_CRP_RCRPLOCK_UNLOCKED_Val << FCR_CRP_RCRPLOCK_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCR_CRP_RCRPLOCK_LOCKED               (FCR_CRP_RCRPLOCK_LOCKED_Val << FCR_CRP_RCRPLOCK_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FCR_CRP_VSSRPLOCK0_Pos                _UINT32_(20)                                         /* (FCR_CRP) Panel 1 Lock Read Protection VSSn Position */
+#define FCR_CRP_VSSRPLOCK0_Msk                (_UINT32_(0x1) << FCR_CRP_VSSRPLOCK0_Pos)            /* (FCR_CRP) Panel 1 Lock Read Protection VSSn Mask */
+#define FCR_CRP_VSSRPLOCK0(value)             (FCR_CRP_VSSRPLOCK0_Msk & (_UINT32_(value) << FCR_CRP_VSSRPLOCK0_Pos)) /* Assignment of value for VSSRPLOCK0 in the FCR_CRP register */
+#define   FCR_CRP_VSSRPLOCK0_UNLOCKED_Val     _UINT32_(0x0)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCR_CRP_VSSRPLOCK0_LOCKED_Val       _UINT32_(0x1)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FCR_CRP_VSSRPLOCK0_UNLOCKED           (FCR_CRP_VSSRPLOCK0_UNLOCKED_Val << FCR_CRP_VSSRPLOCK0_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCR_CRP_VSSRPLOCK0_LOCKED             (FCR_CRP_VSSRPLOCK0_LOCKED_Val << FCR_CRP_VSSRPLOCK0_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FCR_CRP_VSSRPLOCK1_Pos                _UINT32_(21)                                         /* (FCR_CRP) Panel 1 Lock Read Protection VSSn Position */
+#define FCR_CRP_VSSRPLOCK1_Msk                (_UINT32_(0x1) << FCR_CRP_VSSRPLOCK1_Pos)            /* (FCR_CRP) Panel 1 Lock Read Protection VSSn Mask */
+#define FCR_CRP_VSSRPLOCK1(value)             (FCR_CRP_VSSRPLOCK1_Msk & (_UINT32_(value) << FCR_CRP_VSSRPLOCK1_Pos)) /* Assignment of value for VSSRPLOCK1 in the FCR_CRP register */
+#define   FCR_CRP_VSSRPLOCK1_UNLOCKED_Val     _UINT32_(0x0)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCR_CRP_VSSRPLOCK1_LOCKED_Val       _UINT32_(0x1)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FCR_CRP_VSSRPLOCK1_UNLOCKED           (FCR_CRP_VSSRPLOCK1_UNLOCKED_Val << FCR_CRP_VSSRPLOCK1_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCR_CRP_VSSRPLOCK1_LOCKED             (FCR_CRP_VSSRPLOCK1_LOCKED_Val << FCR_CRP_VSSRPLOCK1_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FCR_CRP_TRPLOCK_Pos                   _UINT32_(22)                                         /* (FCR_CRP) Panel 1 Lock Read Protection Test Position */
+#define FCR_CRP_TRPLOCK_Msk                   (_UINT32_(0x1) << FCR_CRP_TRPLOCK_Pos)               /* (FCR_CRP) Panel 1 Lock Read Protection Test Mask */
+#define FCR_CRP_TRPLOCK(value)                (FCR_CRP_TRPLOCK_Msk & (_UINT32_(value) << FCR_CRP_TRPLOCK_Pos)) /* Assignment of value for TRPLOCK in the FCR_CRP register */
+#define   FCR_CRP_TRPLOCK_LOCKED_Val          _UINT32_(0x1)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FCR_CRP_TRPLOCK_LOCKED                (FCR_CRP_TRPLOCK_LOCKED_Val << FCR_CRP_TRPLOCK_Pos)  /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FCR_CRP_CORPLOCK_Pos                  _UINT32_(23)                                         /* (FCR_CRP) Panel 1 Lock Read Protection CalOTP Position */
+#define FCR_CRP_CORPLOCK_Msk                  (_UINT32_(0x1) << FCR_CRP_CORPLOCK_Pos)              /* (FCR_CRP) Panel 1 Lock Read Protection CalOTP Mask */
+#define FCR_CRP_CORPLOCK(value)               (FCR_CRP_CORPLOCK_Msk & (_UINT32_(value) << FCR_CRP_CORPLOCK_Pos)) /* Assignment of value for CORPLOCK in the FCR_CRP register */
+#define   FCR_CRP_CORPLOCK_LOCKED_Val         _UINT32_(0x1)                                        /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FCR_CRP_CORPLOCK_LOCKED               (FCR_CRP_CORPLOCK_LOCKED_Val << FCR_CRP_CORPLOCK_Pos) /* (FCR_CRP) The Lock &amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FCR_CRP_Msk                           _UINT32_(0x00FF00FF)                                 /* (FCR_CRP) Register Mask  */
+
+#define FCR_CRP_VSSRP_Pos                     _UINT32_(4)                                          /* (FCR_CRP Position) Panel x Read Protect VSSn */
+#define FCR_CRP_VSSRP_Msk                     (_UINT32_(0x3) << FCR_CRP_VSSRP_Pos)                 /* (FCR_CRP Mask) VSSRP */
+#define FCR_CRP_VSSRP(value)                  (FCR_CRP_VSSRP_Msk & (_UINT32_(value) << FCR_CRP_VSSRP_Pos)) 
+#define FCR_CRP_VSSRPLOCK_Pos                 _UINT32_(20)                                         /* (FCR_CRP Position) Panel x Lock Read Protection VSSn */
+#define FCR_CRP_VSSRPLOCK_Msk                 (_UINT32_(0x3) << FCR_CRP_VSSRPLOCK_Pos)             /* (FCR_CRP Mask) VSSRPLOCK */
+#define FCR_CRP_VSSRPLOCK(value)              (FCR_CRP_VSSRPLOCK_Msk & (_UINT32_(value) << FCR_CRP_VSSRPLOCK_Pos)) 
+
+/* FCR register offsets definitions */
+#define FCR_CTRLA_REG_OFST             _UINT32_(0x00)      /* (FCR_CTRLA) CTRL A REGISTER Offset */
+#define FCR_CTRLB_REG_OFST             _UINT32_(0x04)      /* (FCR_CTRLB) CTRL B REGISTER Offset */
+#define FCR_INTENCLR_REG_OFST          _UINT32_(0x08)      /* (FCR_INTENCLR) Interrupt Enable Clear REGISTER Offset */
+#define FCR_INTENSET_REG_OFST          _UINT32_(0x0C)      /* (FCR_INTENSET) Interrupt Enable SET REGISTER Offset */
+#define FCR_INTFLAG_REG_OFST           _UINT32_(0x10)      /* (FCR_INTFLAG) Interrupt Flag REGISTER Offset */
+#define FCR_INTFLAGSET_REG_OFST        _UINT32_(0x14)      /* (FCR_INTFLAGSET) Interrupt Flag Set REGISTER Offset */
+#define FCR_STATUS_REG_OFST            _UINT32_(0x18)      /* (FCR_STATUS) Status REGISTER Offset */
+#define FCR_DBGCTRL_REG_OFST           _UINT32_(0x1C)      /* (FCR_DBGCTRL) Debug Control CTRL REGISTER Offset */
+#define FCR_ECCCTRL_REG_OFST           _UINT32_(0x20)      /* (FCR_ECCCTRL) ECC Control REGISTER Offset */
+#define FCR_CRCCTRL_REG_OFST           _UINT32_(0x24)      /* (FCR_CRCCTRL) CRC Control REGISTER Offset */
+#define FCR_CRCMODE_REG_OFST           _UINT32_(0x28)      /* (FCR_CRCMODE) CRC MODE REGISTER Offset */
+#define FCR_CRCPAUSE_REG_OFST          _UINT32_(0x2C)      /* (FCR_CRCPAUSE) CRC Pause REGISTER Offset */
+#define FCR_CRCMADR_REG_OFST           _UINT32_(0x30)      /* (FCR_CRCMADR) CRC Message Address REGISTER Offset */
+#define FCR_CRCMLEN_REG_OFST           _UINT32_(0x34)      /* (FCR_CRCMLEN) CRC Message Length REGISTER Offset */
+#define FCR_CRCIV_REG_OFST             _UINT32_(0x38)      /* (FCR_CRCIV) CRC Initial Value REGISTER Offset */
+#define FCR_CRCACC_REG_OFST            _UINT32_(0x3C)      /* (FCR_CRCACC) CRC Accumulator REGISTER Offset */
+#define FCR_CRCPOLY_REG_OFST           _UINT32_(0x40)      /* (FCR_CRCPOLY) CRC Polynomial REGISTER Offset */
+#define FCR_CRCFXOR_REG_OFST           _UINT32_(0x44)      /* (FCR_CRCFXOR) CRC Final XOR REGISTER Offset */
+#define FCR_CRCSUM_REG_OFST            _UINT32_(0x48)      /* (FCR_CRCSUM) CRC CheckSUM REGISTER Offset */
+#define FCR_FFLTCTRL_REG_OFST          _UINT32_(0x4C)      /* (FCR_FFLTCTRL) Flash ECC Fault Control REGISTER Offset */
+#define FCR_FFLTMODE_REG_OFST          _UINT32_(0x50)      /* (FCR_FFLTMODE) Flash ECC Fault Mode REGISTER Offset */
+#define FCR_FFLTPTR_REG_OFST           _UINT32_(0x54)      /* (FCR_FFLTPTR) Flash ECC Fault Pointer REGISTER Offset */
+#define FCR_FFLTADR_REG_OFST           _UINT32_(0x58)      /* (FCR_FFLTADR) Flash ECC Fault Address REGISTER Offset */
+#define FCR_FFLTCAP_REG_OFST           _UINT32_(0x5C)      /* (FCR_FFLTCAP) Flash ECC Fault Capture Address REGISTER Offset */
+#define FCR_FFLTPAR_REG_OFST           _UINT32_(0x60)      /* (FCR_FFLTPAR) Flash ECC Fault Parity REGISTER Offset */
+#define FCR_FFLTSYN_REG_OFST           _UINT32_(0x64)      /* (FCR_FFLTSYN) Flash ECC Fault Syndrome REGISTER Offset */
+#define FCR_CRP_REG_OFST               _UINT32_(0x68)      /* (FCR_CRP) CFM Page Read Protection REGISTER (CFM8) Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* FCR register API structure */
+typedef struct
+{  /* Polaris Flash Read Controller */
+  __IO  uint32_t                       FCR_CTRLA;          /* Offset: 0x00 (R/W  32) CTRL A REGISTER */
+  __IO  uint32_t                       FCR_CTRLB;          /* Offset: 0x04 (R/W  32) CTRL B REGISTER */
+  __IO  uint32_t                       FCR_INTENCLR;       /* Offset: 0x08 (R/W  32) Interrupt Enable Clear REGISTER */
+  __IO  uint32_t                       FCR_INTENSET;       /* Offset: 0x0C (R/W  32) Interrupt Enable SET REGISTER */
+  __IO  uint32_t                       FCR_INTFLAG;        /* Offset: 0x10 (R/W  32) Interrupt Flag REGISTER */
+  __IO  uint32_t                       FCR_INTFLAGSET;     /* Offset: 0x14 (R/W  32) Interrupt Flag Set REGISTER */
+  __I   uint32_t                       FCR_STATUS;         /* Offset: 0x18 (R/   32) Status REGISTER */
+  __IO  uint32_t                       FCR_DBGCTRL;        /* Offset: 0x1C (R/W  32) Debug Control CTRL REGISTER */
+  __IO  uint32_t                       FCR_ECCCTRL;        /* Offset: 0x20 (R/W  32) ECC Control REGISTER */
+  __IO  uint32_t                       FCR_CRCCTRL;        /* Offset: 0x24 (R/W  32) CRC Control REGISTER */
+  __IO  uint32_t                       FCR_CRCMODE;        /* Offset: 0x28 (R/W  32) CRC MODE REGISTER */
+  __IO  uint32_t                       FCR_CRCPAUSE;       /* Offset: 0x2C (R/W  32) CRC Pause REGISTER */
+  __IO  uint32_t                       FCR_CRCMADR;        /* Offset: 0x30 (R/W  32) CRC Message Address REGISTER */
+  __IO  uint32_t                       FCR_CRCMLEN;        /* Offset: 0x34 (R/W  32) CRC Message Length REGISTER */
+  __IO  uint32_t                       FCR_CRCIV;          /* Offset: 0x38 (R/W  32) CRC Initial Value REGISTER */
+  __I   uint32_t                       FCR_CRCACC;         /* Offset: 0x3C (R/   32) CRC Accumulator REGISTER */
+  __IO  uint32_t                       FCR_CRCPOLY;        /* Offset: 0x40 (R/W  32) CRC Polynomial REGISTER */
+  __IO  uint32_t                       FCR_CRCFXOR;        /* Offset: 0x44 (R/W  32) CRC Final XOR REGISTER */
+  __IO  uint32_t                       FCR_CRCSUM;         /* Offset: 0x48 (R/W  32) CRC CheckSUM REGISTER */
+  __IO  uint32_t                       FCR_FFLTCTRL;       /* Offset: 0x4C (R/W  32) Flash ECC Fault Control REGISTER */
+  __IO  uint32_t                       FCR_FFLTMODE;       /* Offset: 0x50 (R/W  32) Flash ECC Fault Mode REGISTER */
+  __IO  uint32_t                       FCR_FFLTPTR;        /* Offset: 0x54 (R/W  32) Flash ECC Fault Pointer REGISTER */
+  __IO  uint32_t                       FCR_FFLTADR;        /* Offset: 0x58 (R/W  32) Flash ECC Fault Address REGISTER */
+  __I   uint32_t                       FCR_FFLTCAP;        /* Offset: 0x5C (R/   32) Flash ECC Fault Capture Address REGISTER */
+  __I   uint32_t                       FCR_FFLTPAR;        /* Offset: 0x60 (R/   32) Flash ECC Fault Parity REGISTER */
+  __I   uint32_t                       FCR_FFLTSYN;        /* Offset: 0x64 (R/   32) Flash ECC Fault Syndrome REGISTER */
+  __IO  uint32_t                       FCR_CRP;            /* Offset: 0x68 (R/W  32) CFM Page Read Protection REGISTER (CFM8) */
+} fcr_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_FCR_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/fcw.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/fcw.h
new file mode 100644
index 00000000..6dfa3d04
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/fcw.h
@@ -0,0 +1,761 @@
+/*
+ * Component description for FCW
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_FCW_COMPONENT_H_
+#define _PIC32CMGC00_FCW_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR FCW                       */
+/* ************************************************************************** */
+
+/* -------- FCW_CTRLA : (FCW Offset: 0x00) (R/W 32) Control A REGISTER -------- */
+#define FCW_CTRLA_RESETVALUE                  _UINT32_(0x00)                                       /*  (FCW_CTRLA) Control A REGISTER  Reset Value */
+
+#define FCW_CTRLA_PRIV_Pos                    _UINT32_(2)                                          /* (FCW_CTRLA) Privileged Access Only Position */
+#define FCW_CTRLA_PRIV_Msk                    (_UINT32_(0x1) << FCW_CTRLA_PRIV_Pos)                /* (FCW_CTRLA) Privileged Access Only Mask */
+#define FCW_CTRLA_PRIV(value)                 (FCW_CTRLA_PRIV_Msk & (_UINT32_(value) << FCW_CTRLA_PRIV_Pos)) /* Assignment of value for PRIV in the FCW_CTRLA register */
+#define   FCW_CTRLA_PRIV_DISABLE_Val          _UINT32_(0x0)                                        /* (FCW_CTRLA) Macro register accessible in privileged and unprivileged accesses.  */
+#define   FCW_CTRLA_PRIV_ENABLE_Val           _UINT32_(0x1)                                        /* (FCW_CTRLA) Macro registers only accessible in privileged accesses  */
+#define FCW_CTRLA_PRIV_DISABLE                (FCW_CTRLA_PRIV_DISABLE_Val << FCW_CTRLA_PRIV_Pos)   /* (FCW_CTRLA) Macro register accessible in privileged and unprivileged accesses. Position */
+#define FCW_CTRLA_PRIV_ENABLE                 (FCW_CTRLA_PRIV_ENABLE_Val << FCW_CTRLA_PRIV_Pos)    /* (FCW_CTRLA) Macro registers only accessible in privileged accesses Position */
+#define FCW_CTRLA_Msk                         _UINT32_(0x00000004)                                 /* (FCW_CTRLA) Register Mask  */
+
+
+/* -------- FCW_CTRLOP : (FCW Offset: 0x04) (R/W 32) Control Operation REGISTER -------- */
+#define FCW_CTRLOP_RESETVALUE                 _UINT32_(0x00)                                       /*  (FCW_CTRLOP) Control Operation REGISTER  Reset Value */
+
+#define FCW_CTRLOP_NVMOP_Pos                  _UINT32_(0)                                          /* (FCW_CTRLOP) NVM Operation Position */
+#define FCW_CTRLOP_NVMOP_Msk                  (_UINT32_(0xF) << FCW_CTRLOP_NVMOP_Pos)              /* (FCW_CTRLOP) NVM Operation Mask */
+#define FCW_CTRLOP_NVMOP(value)               (FCW_CTRLOP_NVMOP_Msk & (_UINT32_(value) << FCW_CTRLOP_NVMOP_Pos)) /* Assignment of value for NVMOP in the FCW_CTRLOP register */
+#define   FCW_CTRLOP_NVMOP_NOP_Val            _UINT32_(0x0)                                        /* (FCW_CTRLOP) No Operation  */
+#define   FCW_CTRLOP_NVMOP_SINGLEWRITE_Val    _UINT32_(0x1)                                        /* (FCW_CTRLOP) Single (Word) Program Operation: Programs word selected by ADDR  */
+#define   FCW_CTRLOP_NVMOP_QUADWRITE_Val      _UINT32_(0x2)                                        /* (FCW_CTRLOP) Quad (Word) Program Operation: Programs flash word selected by ADDR  */
+#define   FCW_CTRLOP_NVMOP_ROWWRITE_Val       _UINT32_(0x3)                                        /* (FCW_CTRLOP) Row Write Operation: Programs row selected by ADDR  */
+#define   FCW_CTRLOP_NVMOP_PAGEERASE_Val      _UINT32_(0x4)                                        /* (FCW_CTRLOP) Page Erase Operation: Erases page selected by ADDR  */
+#define   FCW_CTRLOP_NVMOP_LPFMERASE_Val      _UINT32_(0x5)                                        /* (FCW_CTRLOP) Lower PFM Erase Operation: (RSVD NVMOP for Single Panel Devices)  */
+#define   FCW_CTRLOP_NVMOP_UPFMERASE_Val      _UINT32_(0x6)                                        /* (FCW_CTRLOP) Upper PFM Erase Operation: (RSVD NVMOP for Single Panel Devices)  */
+#define   FCW_CTRLOP_NVMOP_PFMERASE_Val       _UINT32_(0x7)                                        /* (FCW_CTRLOP) PFM Erase Operation: Upper &amp; Lower PFM Erase  */
+#define   FCW_CTRLOP_NVMOP_CE_Val             _UINT32_(0xE)                                        /* (FCW_CTRLOP) Chip Erase Operation: Erases PFM+SRF, BFM, CFM (except for CalOTP, Test, VSS pages if HSM is Present, UserOTP, &amp; ROMCFG).  */
+#define FCW_CTRLOP_NVMOP_NOP                  (FCW_CTRLOP_NVMOP_NOP_Val << FCW_CTRLOP_NVMOP_Pos)   /* (FCW_CTRLOP) No Operation Position */
+#define FCW_CTRLOP_NVMOP_SINGLEWRITE          (FCW_CTRLOP_NVMOP_SINGLEWRITE_Val << FCW_CTRLOP_NVMOP_Pos) /* (FCW_CTRLOP) Single (Word) Program Operation: Programs word selected by ADDR Position */
+#define FCW_CTRLOP_NVMOP_QUADWRITE            (FCW_CTRLOP_NVMOP_QUADWRITE_Val << FCW_CTRLOP_NVMOP_Pos) /* (FCW_CTRLOP) Quad (Word) Program Operation: Programs flash word selected by ADDR Position */
+#define FCW_CTRLOP_NVMOP_ROWWRITE             (FCW_CTRLOP_NVMOP_ROWWRITE_Val << FCW_CTRLOP_NVMOP_Pos) /* (FCW_CTRLOP) Row Write Operation: Programs row selected by ADDR Position */
+#define FCW_CTRLOP_NVMOP_PAGEERASE            (FCW_CTRLOP_NVMOP_PAGEERASE_Val << FCW_CTRLOP_NVMOP_Pos) /* (FCW_CTRLOP) Page Erase Operation: Erases page selected by ADDR Position */
+#define FCW_CTRLOP_NVMOP_LPFMERASE            (FCW_CTRLOP_NVMOP_LPFMERASE_Val << FCW_CTRLOP_NVMOP_Pos) /* (FCW_CTRLOP) Lower PFM Erase Operation: (RSVD NVMOP for Single Panel Devices) Position */
+#define FCW_CTRLOP_NVMOP_UPFMERASE            (FCW_CTRLOP_NVMOP_UPFMERASE_Val << FCW_CTRLOP_NVMOP_Pos) /* (FCW_CTRLOP) Upper PFM Erase Operation: (RSVD NVMOP for Single Panel Devices) Position */
+#define FCW_CTRLOP_NVMOP_PFMERASE             (FCW_CTRLOP_NVMOP_PFMERASE_Val << FCW_CTRLOP_NVMOP_Pos) /* (FCW_CTRLOP) PFM Erase Operation: Upper &amp; Lower PFM Erase Position */
+#define FCW_CTRLOP_NVMOP_CE                   (FCW_CTRLOP_NVMOP_CE_Val << FCW_CTRLOP_NVMOP_Pos)    /* (FCW_CTRLOP) Chip Erase Operation: Erases PFM+SRF, BFM, CFM (except for CalOTP, Test, VSS pages if HSM is Present, UserOTP, &amp; ROMCFG). Position */
+#define FCW_CTRLOP_PREPG_Pos                  _UINT32_(7)                                          /* (FCW_CTRLOP) NVM Pre-Program Configuration Bit Position */
+#define FCW_CTRLOP_PREPG_Msk                  (_UINT32_(0x1) << FCW_CTRLOP_PREPG_Pos)              /* (FCW_CTRLOP) NVM Pre-Program Configuration Bit Mask */
+#define FCW_CTRLOP_PREPG(value)               (FCW_CTRLOP_PREPG_Msk & (_UINT32_(value) << FCW_CTRLOP_PREPG_Pos)) /* Assignment of value for PREPG in the FCW_CTRLOP register */
+#define   FCW_CTRLOP_PREPG_DISABLE_Val        _UINT32_(0x0)                                        /* (FCW_CTRLOP) Program Operations exclude Pre-Program step  */
+#define   FCW_CTRLOP_PREPG_ENABLE_Val         _UINT32_(0x1)                                        /* (FCW_CTRLOP) Program Operations include Pre-Program step  */
+#define FCW_CTRLOP_PREPG_DISABLE              (FCW_CTRLOP_PREPG_DISABLE_Val << FCW_CTRLOP_PREPG_Pos) /* (FCW_CTRLOP) Program Operations exclude Pre-Program step Position */
+#define FCW_CTRLOP_PREPG_ENABLE               (FCW_CTRLOP_PREPG_ENABLE_Val << FCW_CTRLOP_PREPG_Pos) /* (FCW_CTRLOP) Program Operations include Pre-Program step Position */
+#define FCW_CTRLOP_Msk                        _UINT32_(0x0000008F)                                 /* (FCW_CTRLOP) Register Mask  */
+
+
+/* -------- FCW_MUTEX : (FCW Offset: 0x08) (R/W 32) MUTEX REGISTER -------- */
+#define FCW_MUTEX_RESETVALUE                  _UINT32_(0x00)                                       /*  (FCW_MUTEX) MUTEX REGISTER  Reset Value */
+
+#define FCW_MUTEX_LOCK_Pos                    _UINT32_(0)                                          /* (FCW_MUTEX) Flash Write Controller (FCW) Lock by Owner Position */
+#define FCW_MUTEX_LOCK_Msk                    (_UINT32_(0x1) << FCW_MUTEX_LOCK_Pos)                /* (FCW_MUTEX) Flash Write Controller (FCW) Lock by Owner Mask */
+#define FCW_MUTEX_LOCK(value)                 (FCW_MUTEX_LOCK_Msk & (_UINT32_(value) << FCW_MUTEX_LOCK_Pos)) /* Assignment of value for LOCK in the FCW_MUTEX register */
+#define   FCW_MUTEX_LOCK_UNLOCK_Val           _UINT32_(0x0)                                        /* (FCW_MUTEX) FCW is not locked  */
+#define   FCW_MUTEX_LOCK_LOCK_Val             _UINT32_(0x1)                                        /* (FCW_MUTEX) FCW is locked by owner  */
+#define FCW_MUTEX_LOCK_UNLOCK                 (FCW_MUTEX_LOCK_UNLOCK_Val << FCW_MUTEX_LOCK_Pos)    /* (FCW_MUTEX) FCW is not locked Position */
+#define FCW_MUTEX_LOCK_LOCK                   (FCW_MUTEX_LOCK_LOCK_Val << FCW_MUTEX_LOCK_Pos)      /* (FCW_MUTEX) FCW is locked by owner Position */
+#define FCW_MUTEX_OWNER_Pos                   _UINT32_(1)                                          /* (FCW_MUTEX) Flash Write Controller (FCW) Owner ID Position */
+#define FCW_MUTEX_OWNER_Msk                   (_UINT32_(0x3) << FCW_MUTEX_OWNER_Pos)               /* (FCW_MUTEX) Flash Write Controller (FCW) Owner ID Mask */
+#define FCW_MUTEX_OWNER(value)                (FCW_MUTEX_OWNER_Msk & (_UINT32_(value) << FCW_MUTEX_OWNER_Pos)) /* Assignment of value for OWNER in the FCW_MUTEX register */
+#define   FCW_MUTEX_OWNER_NONE_Val            _UINT32_(0x0)                                        /* (FCW_MUTEX) No Owner - always 0 if LOCK=0  */
+#define   FCW_MUTEX_OWNER_SYSTEM_Val          _UINT32_(0x1)                                        /* (FCW_MUTEX) The System owns the FCW  */
+#define FCW_MUTEX_OWNER_NONE                  (FCW_MUTEX_OWNER_NONE_Val << FCW_MUTEX_OWNER_Pos)    /* (FCW_MUTEX) No Owner - always 0 if LOCK=0 Position */
+#define FCW_MUTEX_OWNER_SYSTEM                (FCW_MUTEX_OWNER_SYSTEM_Val << FCW_MUTEX_OWNER_Pos)  /* (FCW_MUTEX) The System owns the FCW Position */
+#define FCW_MUTEX_Msk                         _UINT32_(0x00000007)                                 /* (FCW_MUTEX) Register Mask  */
+
+
+/* -------- FCW_INTENCLR : (FCW Offset: 0x0C) (R/W 32) Interrupt Enable Clear REGISTER -------- */
+#define FCW_INTENCLR_RESETVALUE               _UINT32_(0x00)                                       /*  (FCW_INTENCLR) Interrupt Enable Clear REGISTER  Reset Value */
+
+#define FCW_INTENCLR_DONE_Pos                 _UINT32_(0)                                          /* (FCW_INTENCLR) NVM Operation Done Interrupt Enable Position */
+#define FCW_INTENCLR_DONE_Msk                 (_UINT32_(0x1) << FCW_INTENCLR_DONE_Pos)             /* (FCW_INTENCLR) NVM Operation Done Interrupt Enable Mask */
+#define FCW_INTENCLR_DONE(value)              (FCW_INTENCLR_DONE_Msk & (_UINT32_(value) << FCW_INTENCLR_DONE_Pos)) /* Assignment of value for DONE in the FCW_INTENCLR register */
+#define   FCW_INTENCLR_DONE_0_Val             _UINT32_(0x0)                                        /* (FCW_INTENCLR) Interrupt Disabled  */
+#define   FCW_INTENCLR_DONE_1_Val             _UINT32_(0x1)                                        /* (FCW_INTENCLR) Interrupt Enabled  */
+#define FCW_INTENCLR_DONE_0                   (FCW_INTENCLR_DONE_0_Val << FCW_INTENCLR_DONE_Pos)   /* (FCW_INTENCLR) Interrupt Disabled Position */
+#define FCW_INTENCLR_DONE_1                   (FCW_INTENCLR_DONE_1_Val << FCW_INTENCLR_DONE_Pos)   /* (FCW_INTENCLR) Interrupt Enabled Position */
+#define FCW_INTENCLR_KEYERR_Pos               _UINT32_(1)                                          /* (FCW_INTENCLR) Key Error Interrupt Enable Position */
+#define FCW_INTENCLR_KEYERR_Msk               (_UINT32_(0x1) << FCW_INTENCLR_KEYERR_Pos)           /* (FCW_INTENCLR) Key Error Interrupt Enable Mask */
+#define FCW_INTENCLR_KEYERR(value)            (FCW_INTENCLR_KEYERR_Msk & (_UINT32_(value) << FCW_INTENCLR_KEYERR_Pos)) /* Assignment of value for KEYERR in the FCW_INTENCLR register */
+#define   FCW_INTENCLR_KEYERR_0_Val           _UINT32_(0x0)                                        /* (FCW_INTENCLR) Interrupt Disabled  */
+#define   FCW_INTENCLR_KEYERR_1_Val           _UINT32_(0x1)                                        /* (FCW_INTENCLR) Interrupt Enabled  */
+#define FCW_INTENCLR_KEYERR_0                 (FCW_INTENCLR_KEYERR_0_Val << FCW_INTENCLR_KEYERR_Pos) /* (FCW_INTENCLR) Interrupt Disabled Position */
+#define FCW_INTENCLR_KEYERR_1                 (FCW_INTENCLR_KEYERR_1_Val << FCW_INTENCLR_KEYERR_Pos) /* (FCW_INTENCLR) Interrupt Enabled Position */
+#define FCW_INTENCLR_CFGERR_Pos               _UINT32_(2)                                          /* (FCW_INTENCLR) Configuration Error Interrupt Enable Position */
+#define FCW_INTENCLR_CFGERR_Msk               (_UINT32_(0x1) << FCW_INTENCLR_CFGERR_Pos)           /* (FCW_INTENCLR) Configuration Error Interrupt Enable Mask */
+#define FCW_INTENCLR_CFGERR(value)            (FCW_INTENCLR_CFGERR_Msk & (_UINT32_(value) << FCW_INTENCLR_CFGERR_Pos)) /* Assignment of value for CFGERR in the FCW_INTENCLR register */
+#define   FCW_INTENCLR_CFGERR_0_Val           _UINT32_(0x0)                                        /* (FCW_INTENCLR) Interrupt Disabled  */
+#define   FCW_INTENCLR_CFGERR_1_Val           _UINT32_(0x1)                                        /* (FCW_INTENCLR) Interrupt Enabled  */
+#define FCW_INTENCLR_CFGERR_0                 (FCW_INTENCLR_CFGERR_0_Val << FCW_INTENCLR_CFGERR_Pos) /* (FCW_INTENCLR) Interrupt Disabled Position */
+#define FCW_INTENCLR_CFGERR_1                 (FCW_INTENCLR_CFGERR_1_Val << FCW_INTENCLR_CFGERR_Pos) /* (FCW_INTENCLR) Interrupt Enabled Position */
+#define FCW_INTENCLR_FIFOERR_Pos              _UINT32_(3)                                          /* (FCW_INTENCLR) FIFO Underrun during Row Write Interrupt Enable Position */
+#define FCW_INTENCLR_FIFOERR_Msk              (_UINT32_(0x1) << FCW_INTENCLR_FIFOERR_Pos)          /* (FCW_INTENCLR) FIFO Underrun during Row Write Interrupt Enable Mask */
+#define FCW_INTENCLR_FIFOERR(value)           (FCW_INTENCLR_FIFOERR_Msk & (_UINT32_(value) << FCW_INTENCLR_FIFOERR_Pos)) /* Assignment of value for FIFOERR in the FCW_INTENCLR register */
+#define   FCW_INTENCLR_FIFOERR_0_Val          _UINT32_(0x0)                                        /* (FCW_INTENCLR) Interrupt Disabled  */
+#define   FCW_INTENCLR_FIFOERR_1_Val          _UINT32_(0x1)                                        /* (FCW_INTENCLR) Interrupt Enabled  */
+#define FCW_INTENCLR_FIFOERR_0                (FCW_INTENCLR_FIFOERR_0_Val << FCW_INTENCLR_FIFOERR_Pos) /* (FCW_INTENCLR) Interrupt Disabled Position */
+#define FCW_INTENCLR_FIFOERR_1                (FCW_INTENCLR_FIFOERR_1_Val << FCW_INTENCLR_FIFOERR_Pos) /* (FCW_INTENCLR) Interrupt Enabled Position */
+#define FCW_INTENCLR_BUSERR_Pos               _UINT32_(4)                                          /* (FCW_INTENCLR) AHB Bus Error during Row Write Interrupt Enable Position */
+#define FCW_INTENCLR_BUSERR_Msk               (_UINT32_(0x1) << FCW_INTENCLR_BUSERR_Pos)           /* (FCW_INTENCLR) AHB Bus Error during Row Write Interrupt Enable Mask */
+#define FCW_INTENCLR_BUSERR(value)            (FCW_INTENCLR_BUSERR_Msk & (_UINT32_(value) << FCW_INTENCLR_BUSERR_Pos)) /* Assignment of value for BUSERR in the FCW_INTENCLR register */
+#define   FCW_INTENCLR_BUSERR_0_Val           _UINT32_(0x0)                                        /* (FCW_INTENCLR) Interrupt Disabled  */
+#define   FCW_INTENCLR_BUSERR_1_Val           _UINT32_(0x1)                                        /* (FCW_INTENCLR) Interrupt Enabled  */
+#define FCW_INTENCLR_BUSERR_0                 (FCW_INTENCLR_BUSERR_0_Val << FCW_INTENCLR_BUSERR_Pos) /* (FCW_INTENCLR) Interrupt Disabled Position */
+#define FCW_INTENCLR_BUSERR_1                 (FCW_INTENCLR_BUSERR_1_Val << FCW_INTENCLR_BUSERR_Pos) /* (FCW_INTENCLR) Interrupt Enabled Position */
+#define FCW_INTENCLR_WPERR_Pos                _UINT32_(5)                                          /* (FCW_INTENCLR) Write Protection Error Interrupt Enable Position */
+#define FCW_INTENCLR_WPERR_Msk                (_UINT32_(0x1) << FCW_INTENCLR_WPERR_Pos)            /* (FCW_INTENCLR) Write Protection Error Interrupt Enable Mask */
+#define FCW_INTENCLR_WPERR(value)             (FCW_INTENCLR_WPERR_Msk & (_UINT32_(value) << FCW_INTENCLR_WPERR_Pos)) /* Assignment of value for WPERR in the FCW_INTENCLR register */
+#define   FCW_INTENCLR_WPERR_0_Val            _UINT32_(0x0)                                        /* (FCW_INTENCLR) Interrupt Disabled  */
+#define   FCW_INTENCLR_WPERR_1_Val            _UINT32_(0x1)                                        /* (FCW_INTENCLR) Interrupt Enabled  */
+#define FCW_INTENCLR_WPERR_0                  (FCW_INTENCLR_WPERR_0_Val << FCW_INTENCLR_WPERR_Pos) /* (FCW_INTENCLR) Interrupt Disabled Position */
+#define FCW_INTENCLR_WPERR_1                  (FCW_INTENCLR_WPERR_1_Val << FCW_INTENCLR_WPERR_Pos) /* (FCW_INTENCLR) Interrupt Enabled Position */
+#define FCW_INTENCLR_OPERR_Pos                _UINT32_(6)                                          /* (FCW_INTENCLR) NVMOP Error Interrupt Enable Position */
+#define FCW_INTENCLR_OPERR_Msk                (_UINT32_(0x1) << FCW_INTENCLR_OPERR_Pos)            /* (FCW_INTENCLR) NVMOP Error Interrupt Enable Mask */
+#define FCW_INTENCLR_OPERR(value)             (FCW_INTENCLR_OPERR_Msk & (_UINT32_(value) << FCW_INTENCLR_OPERR_Pos)) /* Assignment of value for OPERR in the FCW_INTENCLR register */
+#define   FCW_INTENCLR_OPERR_0_Val            _UINT32_(0x0)                                        /* (FCW_INTENCLR) Interrupt Disabled  */
+#define   FCW_INTENCLR_OPERR_1_Val            _UINT32_(0x1)                                        /* (FCW_INTENCLR) Interrupt Enabled  */
+#define FCW_INTENCLR_OPERR_0                  (FCW_INTENCLR_OPERR_0_Val << FCW_INTENCLR_OPERR_Pos) /* (FCW_INTENCLR) Interrupt Disabled Position */
+#define FCW_INTENCLR_OPERR_1                  (FCW_INTENCLR_OPERR_1_Val << FCW_INTENCLR_OPERR_Pos) /* (FCW_INTENCLR) Interrupt Enabled Position */
+#define FCW_INTENCLR_HTDPGM_Pos               _UINT32_(8)                                          /* (FCW_INTENCLR) High Temperature Detect Error Interrupt Enable Position */
+#define FCW_INTENCLR_HTDPGM_Msk               (_UINT32_(0x1) << FCW_INTENCLR_HTDPGM_Pos)           /* (FCW_INTENCLR) High Temperature Detect Error Interrupt Enable Mask */
+#define FCW_INTENCLR_HTDPGM(value)            (FCW_INTENCLR_HTDPGM_Msk & (_UINT32_(value) << FCW_INTENCLR_HTDPGM_Pos)) /* Assignment of value for HTDPGM in the FCW_INTENCLR register */
+#define   FCW_INTENCLR_HTDPGM_0_Val           _UINT32_(0x0)                                        /* (FCW_INTENCLR) Interrupt Disabled  */
+#define   FCW_INTENCLR_HTDPGM_1_Val           _UINT32_(0x1)                                        /* (FCW_INTENCLR) Interrupt Enabled  */
+#define FCW_INTENCLR_HTDPGM_0                 (FCW_INTENCLR_HTDPGM_0_Val << FCW_INTENCLR_HTDPGM_Pos) /* (FCW_INTENCLR) Interrupt Disabled Position */
+#define FCW_INTENCLR_HTDPGM_1                 (FCW_INTENCLR_HTDPGM_1_Val << FCW_INTENCLR_HTDPGM_Pos) /* (FCW_INTENCLR) Interrupt Enabled Position */
+#define FCW_INTENCLR_RSTERR_Pos               _UINT32_(12)                                         /* (FCW_INTENCLR) Reset or Brown Out Detect Error Interrupt Enable Position */
+#define FCW_INTENCLR_RSTERR_Msk               (_UINT32_(0x1) << FCW_INTENCLR_RSTERR_Pos)           /* (FCW_INTENCLR) Reset or Brown Out Detect Error Interrupt Enable Mask */
+#define FCW_INTENCLR_RSTERR(value)            (FCW_INTENCLR_RSTERR_Msk & (_UINT32_(value) << FCW_INTENCLR_RSTERR_Pos)) /* Assignment of value for RSTERR in the FCW_INTENCLR register */
+#define   FCW_INTENCLR_RSTERR_0_Val           _UINT32_(0x0)                                        /* (FCW_INTENCLR) Interrupt Disabled  */
+#define   FCW_INTENCLR_RSTERR_1_Val           _UINT32_(0x1)                                        /* (FCW_INTENCLR) Interrupt Enabled  */
+#define FCW_INTENCLR_RSTERR_0                 (FCW_INTENCLR_RSTERR_0_Val << FCW_INTENCLR_RSTERR_Pos) /* (FCW_INTENCLR) Interrupt Disabled Position */
+#define FCW_INTENCLR_RSTERR_1                 (FCW_INTENCLR_RSTERR_1_Val << FCW_INTENCLR_RSTERR_Pos) /* (FCW_INTENCLR) Interrupt Enabled Position */
+#define FCW_INTENCLR_WRERR_Pos                _UINT32_(13)                                         /* (FCW_INTENCLR) Write Error Interrupt Enable Position */
+#define FCW_INTENCLR_WRERR_Msk                (_UINT32_(0x1) << FCW_INTENCLR_WRERR_Pos)            /* (FCW_INTENCLR) Write Error Interrupt Enable Mask */
+#define FCW_INTENCLR_WRERR(value)             (FCW_INTENCLR_WRERR_Msk & (_UINT32_(value) << FCW_INTENCLR_WRERR_Pos)) /* Assignment of value for WRERR in the FCW_INTENCLR register */
+#define   FCW_INTENCLR_WRERR_0_Val            _UINT32_(0x0)                                        /* (FCW_INTENCLR) Interrupt Disabled  */
+#define   FCW_INTENCLR_WRERR_1_Val            _UINT32_(0x1)                                        /* (FCW_INTENCLR) Interrupt Enabled  */
+#define FCW_INTENCLR_WRERR_0                  (FCW_INTENCLR_WRERR_0_Val << FCW_INTENCLR_WRERR_Pos) /* (FCW_INTENCLR) Interrupt Disabled Position */
+#define FCW_INTENCLR_WRERR_1                  (FCW_INTENCLR_WRERR_1_Val << FCW_INTENCLR_WRERR_Pos) /* (FCW_INTENCLR) Interrupt Enabled Position */
+#define FCW_INTENCLR_Msk                      _UINT32_(0x0000317F)                                 /* (FCW_INTENCLR) Register Mask  */
+
+
+/* -------- FCW_INTENSET : (FCW Offset: 0x10) (R/W 32) Interrupt Enable Set REGISTER -------- */
+#define FCW_INTENSET_RESETVALUE               _UINT32_(0x00)                                       /*  (FCW_INTENSET) Interrupt Enable Set REGISTER  Reset Value */
+
+#define FCW_INTENSET_DONE_Pos                 _UINT32_(0)                                          /* (FCW_INTENSET) NVM Operation Done Interrupt Set Enable Position */
+#define FCW_INTENSET_DONE_Msk                 (_UINT32_(0x1) << FCW_INTENSET_DONE_Pos)             /* (FCW_INTENSET) NVM Operation Done Interrupt Set Enable Mask */
+#define FCW_INTENSET_DONE(value)              (FCW_INTENSET_DONE_Msk & (_UINT32_(value) << FCW_INTENSET_DONE_Pos)) /* Assignment of value for DONE in the FCW_INTENSET register */
+#define   FCW_INTENSET_DONE_0_Val             _UINT32_(0x0)                                        /* (FCW_INTENSET) Interrupt Disabled  */
+#define   FCW_INTENSET_DONE_1_Val             _UINT32_(0x1)                                        /* (FCW_INTENSET) Interrupt Enabled  */
+#define FCW_INTENSET_DONE_0                   (FCW_INTENSET_DONE_0_Val << FCW_INTENSET_DONE_Pos)   /* (FCW_INTENSET) Interrupt Disabled Position */
+#define FCW_INTENSET_DONE_1                   (FCW_INTENSET_DONE_1_Val << FCW_INTENSET_DONE_Pos)   /* (FCW_INTENSET) Interrupt Enabled Position */
+#define FCW_INTENSET_KEYERR_Pos               _UINT32_(1)                                          /* (FCW_INTENSET) Key Error Interrupt Set Enable Position */
+#define FCW_INTENSET_KEYERR_Msk               (_UINT32_(0x1) << FCW_INTENSET_KEYERR_Pos)           /* (FCW_INTENSET) Key Error Interrupt Set Enable Mask */
+#define FCW_INTENSET_KEYERR(value)            (FCW_INTENSET_KEYERR_Msk & (_UINT32_(value) << FCW_INTENSET_KEYERR_Pos)) /* Assignment of value for KEYERR in the FCW_INTENSET register */
+#define   FCW_INTENSET_KEYERR_0_Val           _UINT32_(0x0)                                        /* (FCW_INTENSET) Interrupt Disabled  */
+#define   FCW_INTENSET_KEYERR_1_Val           _UINT32_(0x1)                                        /* (FCW_INTENSET) Interrupt Enabled  */
+#define FCW_INTENSET_KEYERR_0                 (FCW_INTENSET_KEYERR_0_Val << FCW_INTENSET_KEYERR_Pos) /* (FCW_INTENSET) Interrupt Disabled Position */
+#define FCW_INTENSET_KEYERR_1                 (FCW_INTENSET_KEYERR_1_Val << FCW_INTENSET_KEYERR_Pos) /* (FCW_INTENSET) Interrupt Enabled Position */
+#define FCW_INTENSET_CFGERR_Pos               _UINT32_(2)                                          /* (FCW_INTENSET) Configuration Error Interrupt Set Enable Position */
+#define FCW_INTENSET_CFGERR_Msk               (_UINT32_(0x1) << FCW_INTENSET_CFGERR_Pos)           /* (FCW_INTENSET) Configuration Error Interrupt Set Enable Mask */
+#define FCW_INTENSET_CFGERR(value)            (FCW_INTENSET_CFGERR_Msk & (_UINT32_(value) << FCW_INTENSET_CFGERR_Pos)) /* Assignment of value for CFGERR in the FCW_INTENSET register */
+#define   FCW_INTENSET_CFGERR_0_Val           _UINT32_(0x0)                                        /* (FCW_INTENSET) Interrupt Disabled  */
+#define   FCW_INTENSET_CFGERR_1_Val           _UINT32_(0x1)                                        /* (FCW_INTENSET) Interrupt Enabled  */
+#define FCW_INTENSET_CFGERR_0                 (FCW_INTENSET_CFGERR_0_Val << FCW_INTENSET_CFGERR_Pos) /* (FCW_INTENSET) Interrupt Disabled Position */
+#define FCW_INTENSET_CFGERR_1                 (FCW_INTENSET_CFGERR_1_Val << FCW_INTENSET_CFGERR_Pos) /* (FCW_INTENSET) Interrupt Enabled Position */
+#define FCW_INTENSET_FIFOERR_Pos              _UINT32_(3)                                          /* (FCW_INTENSET) FIFO Underrun during Row Write Interrupt Set Enable Position */
+#define FCW_INTENSET_FIFOERR_Msk              (_UINT32_(0x1) << FCW_INTENSET_FIFOERR_Pos)          /* (FCW_INTENSET) FIFO Underrun during Row Write Interrupt Set Enable Mask */
+#define FCW_INTENSET_FIFOERR(value)           (FCW_INTENSET_FIFOERR_Msk & (_UINT32_(value) << FCW_INTENSET_FIFOERR_Pos)) /* Assignment of value for FIFOERR in the FCW_INTENSET register */
+#define   FCW_INTENSET_FIFOERR_0_Val          _UINT32_(0x0)                                        /* (FCW_INTENSET) Interrupt Disabled  */
+#define   FCW_INTENSET_FIFOERR_1_Val          _UINT32_(0x1)                                        /* (FCW_INTENSET) Interrupt Enabled  */
+#define FCW_INTENSET_FIFOERR_0                (FCW_INTENSET_FIFOERR_0_Val << FCW_INTENSET_FIFOERR_Pos) /* (FCW_INTENSET) Interrupt Disabled Position */
+#define FCW_INTENSET_FIFOERR_1                (FCW_INTENSET_FIFOERR_1_Val << FCW_INTENSET_FIFOERR_Pos) /* (FCW_INTENSET) Interrupt Enabled Position */
+#define FCW_INTENSET_BUSERR_Pos               _UINT32_(4)                                          /* (FCW_INTENSET) AHB Bus Error during Row Write Interrupt Enable Position */
+#define FCW_INTENSET_BUSERR_Msk               (_UINT32_(0x1) << FCW_INTENSET_BUSERR_Pos)           /* (FCW_INTENSET) AHB Bus Error during Row Write Interrupt Enable Mask */
+#define FCW_INTENSET_BUSERR(value)            (FCW_INTENSET_BUSERR_Msk & (_UINT32_(value) << FCW_INTENSET_BUSERR_Pos)) /* Assignment of value for BUSERR in the FCW_INTENSET register */
+#define   FCW_INTENSET_BUSERR_0_Val           _UINT32_(0x0)                                        /* (FCW_INTENSET) Interrupt Disabled  */
+#define   FCW_INTENSET_BUSERR_1_Val           _UINT32_(0x1)                                        /* (FCW_INTENSET) Interrupt Enabled  */
+#define FCW_INTENSET_BUSERR_0                 (FCW_INTENSET_BUSERR_0_Val << FCW_INTENSET_BUSERR_Pos) /* (FCW_INTENSET) Interrupt Disabled Position */
+#define FCW_INTENSET_BUSERR_1                 (FCW_INTENSET_BUSERR_1_Val << FCW_INTENSET_BUSERR_Pos) /* (FCW_INTENSET) Interrupt Enabled Position */
+#define FCW_INTENSET_WPERR_Pos                _UINT32_(5)                                          /* (FCW_INTENSET) Write Protection Error Interrupt Enable Position */
+#define FCW_INTENSET_WPERR_Msk                (_UINT32_(0x1) << FCW_INTENSET_WPERR_Pos)            /* (FCW_INTENSET) Write Protection Error Interrupt Enable Mask */
+#define FCW_INTENSET_WPERR(value)             (FCW_INTENSET_WPERR_Msk & (_UINT32_(value) << FCW_INTENSET_WPERR_Pos)) /* Assignment of value for WPERR in the FCW_INTENSET register */
+#define   FCW_INTENSET_WPERR_0_Val            _UINT32_(0x0)                                        /* (FCW_INTENSET) Interrupt Disabled  */
+#define   FCW_INTENSET_WPERR_1_Val            _UINT32_(0x1)                                        /* (FCW_INTENSET) Interrupt Enabled  */
+#define FCW_INTENSET_WPERR_0                  (FCW_INTENSET_WPERR_0_Val << FCW_INTENSET_WPERR_Pos) /* (FCW_INTENSET) Interrupt Disabled Position */
+#define FCW_INTENSET_WPERR_1                  (FCW_INTENSET_WPERR_1_Val << FCW_INTENSET_WPERR_Pos) /* (FCW_INTENSET) Interrupt Enabled Position */
+#define FCW_INTENSET_OPERR_Pos                _UINT32_(6)                                          /* (FCW_INTENSET) NVMOP Error Interrupt Enable Position */
+#define FCW_INTENSET_OPERR_Msk                (_UINT32_(0x1) << FCW_INTENSET_OPERR_Pos)            /* (FCW_INTENSET) NVMOP Error Interrupt Enable Mask */
+#define FCW_INTENSET_OPERR(value)             (FCW_INTENSET_OPERR_Msk & (_UINT32_(value) << FCW_INTENSET_OPERR_Pos)) /* Assignment of value for OPERR in the FCW_INTENSET register */
+#define   FCW_INTENSET_OPERR_0_Val            _UINT32_(0x0)                                        /* (FCW_INTENSET) Interrupt Disabled  */
+#define   FCW_INTENSET_OPERR_1_Val            _UINT32_(0x1)                                        /* (FCW_INTENSET) Interrupt Enabled  */
+#define FCW_INTENSET_OPERR_0                  (FCW_INTENSET_OPERR_0_Val << FCW_INTENSET_OPERR_Pos) /* (FCW_INTENSET) Interrupt Disabled Position */
+#define FCW_INTENSET_OPERR_1                  (FCW_INTENSET_OPERR_1_Val << FCW_INTENSET_OPERR_Pos) /* (FCW_INTENSET) Interrupt Enabled Position */
+#define FCW_INTENSET_HTDPGM_Pos               _UINT32_(8)                                          /* (FCW_INTENSET) High Temperature Detect Error Interrupt Enable Position */
+#define FCW_INTENSET_HTDPGM_Msk               (_UINT32_(0x1) << FCW_INTENSET_HTDPGM_Pos)           /* (FCW_INTENSET) High Temperature Detect Error Interrupt Enable Mask */
+#define FCW_INTENSET_HTDPGM(value)            (FCW_INTENSET_HTDPGM_Msk & (_UINT32_(value) << FCW_INTENSET_HTDPGM_Pos)) /* Assignment of value for HTDPGM in the FCW_INTENSET register */
+#define   FCW_INTENSET_HTDPGM_0_Val           _UINT32_(0x0)                                        /* (FCW_INTENSET) Interrupt Disabled  */
+#define   FCW_INTENSET_HTDPGM_1_Val           _UINT32_(0x1)                                        /* (FCW_INTENSET) Interrupt Enabled  */
+#define FCW_INTENSET_HTDPGM_0                 (FCW_INTENSET_HTDPGM_0_Val << FCW_INTENSET_HTDPGM_Pos) /* (FCW_INTENSET) Interrupt Disabled Position */
+#define FCW_INTENSET_HTDPGM_1                 (FCW_INTENSET_HTDPGM_1_Val << FCW_INTENSET_HTDPGM_Pos) /* (FCW_INTENSET) Interrupt Enabled Position */
+#define FCW_INTENSET_RSTERR_Pos               _UINT32_(12)                                         /* (FCW_INTENSET) Reset or Brown Out Detect Error Interrupt Enable Position */
+#define FCW_INTENSET_RSTERR_Msk               (_UINT32_(0x1) << FCW_INTENSET_RSTERR_Pos)           /* (FCW_INTENSET) Reset or Brown Out Detect Error Interrupt Enable Mask */
+#define FCW_INTENSET_RSTERR(value)            (FCW_INTENSET_RSTERR_Msk & (_UINT32_(value) << FCW_INTENSET_RSTERR_Pos)) /* Assignment of value for RSTERR in the FCW_INTENSET register */
+#define   FCW_INTENSET_RSTERR_0_Val           _UINT32_(0x0)                                        /* (FCW_INTENSET) Interrupt Disabled  */
+#define   FCW_INTENSET_RSTERR_1_Val           _UINT32_(0x1)                                        /* (FCW_INTENSET) Interrupt Enabled  */
+#define FCW_INTENSET_RSTERR_0                 (FCW_INTENSET_RSTERR_0_Val << FCW_INTENSET_RSTERR_Pos) /* (FCW_INTENSET) Interrupt Disabled Position */
+#define FCW_INTENSET_RSTERR_1                 (FCW_INTENSET_RSTERR_1_Val << FCW_INTENSET_RSTERR_Pos) /* (FCW_INTENSET) Interrupt Enabled Position */
+#define FCW_INTENSET_WRERR_Pos                _UINT32_(13)                                         /* (FCW_INTENSET) Write Error Interrupt Enable Position */
+#define FCW_INTENSET_WRERR_Msk                (_UINT32_(0x1) << FCW_INTENSET_WRERR_Pos)            /* (FCW_INTENSET) Write Error Interrupt Enable Mask */
+#define FCW_INTENSET_WRERR(value)             (FCW_INTENSET_WRERR_Msk & (_UINT32_(value) << FCW_INTENSET_WRERR_Pos)) /* Assignment of value for WRERR in the FCW_INTENSET register */
+#define   FCW_INTENSET_WRERR_0_Val            _UINT32_(0x0)                                        /* (FCW_INTENSET) Interrupt Disabled  */
+#define   FCW_INTENSET_WRERR_1_Val            _UINT32_(0x1)                                        /* (FCW_INTENSET) Interrupt Enabled  */
+#define FCW_INTENSET_WRERR_0                  (FCW_INTENSET_WRERR_0_Val << FCW_INTENSET_WRERR_Pos) /* (FCW_INTENSET) Interrupt Disabled Position */
+#define FCW_INTENSET_WRERR_1                  (FCW_INTENSET_WRERR_1_Val << FCW_INTENSET_WRERR_Pos) /* (FCW_INTENSET) Interrupt Enabled Position */
+#define FCW_INTENSET_Msk                      _UINT32_(0x0000317F)                                 /* (FCW_INTENSET) Register Mask  */
+
+
+/* -------- FCW_INTFLAG : (FCW Offset: 0x14) (R/W 32) Interrupt Flag REGISTER -------- */
+#define FCW_INTFLAG_RESETVALUE                _UINT32_(0x00)                                       /*  (FCW_INTFLAG) Interrupt Flag REGISTER  Reset Value */
+
+#define FCW_INTFLAG_DONE_Pos                  _UINT32_(0)                                          /* (FCW_INTFLAG) NVM Operation Done Flag Bit Position */
+#define FCW_INTFLAG_DONE_Msk                  (_UINT32_(0x1) << FCW_INTFLAG_DONE_Pos)              /* (FCW_INTFLAG) NVM Operation Done Flag Bit Mask */
+#define FCW_INTFLAG_DONE(value)               (FCW_INTFLAG_DONE_Msk & (_UINT32_(value) << FCW_INTFLAG_DONE_Pos)) /* Assignment of value for DONE in the FCW_INTFLAG register */
+#define   FCW_INTFLAG_DONE_0_Val              _UINT32_(0x0)                                        /* (FCW_INTFLAG) NVMOP Not Done  */
+#define   FCW_INTFLAG_DONE_1_Val              _UINT32_(0x1)                                        /* (FCW_INTFLAG) NVMOP Done  */
+#define FCW_INTFLAG_DONE_0                    (FCW_INTFLAG_DONE_0_Val << FCW_INTFLAG_DONE_Pos)     /* (FCW_INTFLAG) NVMOP Not Done Position */
+#define FCW_INTFLAG_DONE_1                    (FCW_INTFLAG_DONE_1_Val << FCW_INTFLAG_DONE_Pos)     /* (FCW_INTFLAG) NVMOP Done Position */
+#define FCW_INTFLAG_KEYERR_Pos                _UINT32_(1)                                          /* (FCW_INTFLAG) Key Error Flag Bit Position */
+#define FCW_INTFLAG_KEYERR_Msk                (_UINT32_(0x1) << FCW_INTFLAG_KEYERR_Pos)            /* (FCW_INTFLAG) Key Error Flag Bit Mask */
+#define FCW_INTFLAG_KEYERR(value)             (FCW_INTFLAG_KEYERR_Msk & (_UINT32_(value) << FCW_INTFLAG_KEYERR_Pos)) /* Assignment of value for KEYERR in the FCW_INTFLAG register */
+#define   FCW_INTFLAG_KEYERR_0_Val            _UINT32_(0x0)                                        /* (FCW_INTFLAG) No Key Error  */
+#define   FCW_INTFLAG_KEYERR_1_Val            _UINT32_(0x1)                                        /* (FCW_INTFLAG) Key Error  */
+#define FCW_INTFLAG_KEYERR_0                  (FCW_INTFLAG_KEYERR_0_Val << FCW_INTFLAG_KEYERR_Pos) /* (FCW_INTFLAG) No Key Error Position */
+#define FCW_INTFLAG_KEYERR_1                  (FCW_INTFLAG_KEYERR_1_Val << FCW_INTFLAG_KEYERR_Pos) /* (FCW_INTFLAG) Key Error Position */
+#define FCW_INTFLAG_CFGERR_Pos                _UINT32_(2)                                          /* (FCW_INTFLAG) Configuration Error Flag Bit Position */
+#define FCW_INTFLAG_CFGERR_Msk                (_UINT32_(0x1) << FCW_INTFLAG_CFGERR_Pos)            /* (FCW_INTFLAG) Configuration Error Flag Bit Mask */
+#define FCW_INTFLAG_CFGERR(value)             (FCW_INTFLAG_CFGERR_Msk & (_UINT32_(value) << FCW_INTFLAG_CFGERR_Pos)) /* Assignment of value for CFGERR in the FCW_INTFLAG register */
+#define   FCW_INTFLAG_CFGERR_0_Val            _UINT32_(0x0)                                        /* (FCW_INTFLAG) No CFG Error  */
+#define   FCW_INTFLAG_CFGERR_1_Val            _UINT32_(0x1)                                        /* (FCW_INTFLAG) CFC Error  */
+#define FCW_INTFLAG_CFGERR_0                  (FCW_INTFLAG_CFGERR_0_Val << FCW_INTFLAG_CFGERR_Pos) /* (FCW_INTFLAG) No CFG Error Position */
+#define FCW_INTFLAG_CFGERR_1                  (FCW_INTFLAG_CFGERR_1_Val << FCW_INTFLAG_CFGERR_Pos) /* (FCW_INTFLAG) CFC Error Position */
+#define FCW_INTFLAG_FIFOERR_Pos               _UINT32_(3)                                          /* (FCW_INTFLAG) FIFO Underrun during Row Write Flag Bit Position */
+#define FCW_INTFLAG_FIFOERR_Msk               (_UINT32_(0x1) << FCW_INTFLAG_FIFOERR_Pos)           /* (FCW_INTFLAG) FIFO Underrun during Row Write Flag Bit Mask */
+#define FCW_INTFLAG_FIFOERR(value)            (FCW_INTFLAG_FIFOERR_Msk & (_UINT32_(value) << FCW_INTFLAG_FIFOERR_Pos)) /* Assignment of value for FIFOERR in the FCW_INTFLAG register */
+#define   FCW_INTFLAG_FIFOERR_0_Val           _UINT32_(0x0)                                        /* (FCW_INTFLAG) No FIFO Error  */
+#define   FCW_INTFLAG_FIFOERR_1_Val           _UINT32_(0x1)                                        /* (FCW_INTFLAG) FIFO Error  */
+#define FCW_INTFLAG_FIFOERR_0                 (FCW_INTFLAG_FIFOERR_0_Val << FCW_INTFLAG_FIFOERR_Pos) /* (FCW_INTFLAG) No FIFO Error Position */
+#define FCW_INTFLAG_FIFOERR_1                 (FCW_INTFLAG_FIFOERR_1_Val << FCW_INTFLAG_FIFOERR_Pos) /* (FCW_INTFLAG) FIFO Error Position */
+#define FCW_INTFLAG_BUSERR_Pos                _UINT32_(4)                                          /* (FCW_INTFLAG) AHB Bus Error during Row Write Flag Bit Position */
+#define FCW_INTFLAG_BUSERR_Msk                (_UINT32_(0x1) << FCW_INTFLAG_BUSERR_Pos)            /* (FCW_INTFLAG) AHB Bus Error during Row Write Flag Bit Mask */
+#define FCW_INTFLAG_BUSERR(value)             (FCW_INTFLAG_BUSERR_Msk & (_UINT32_(value) << FCW_INTFLAG_BUSERR_Pos)) /* Assignment of value for BUSERR in the FCW_INTFLAG register */
+#define   FCW_INTFLAG_BUSERR_0_Val            _UINT32_(0x0)                                        /* (FCW_INTFLAG) No Bus Error  */
+#define   FCW_INTFLAG_BUSERR_1_Val            _UINT32_(0x1)                                        /* (FCW_INTFLAG) Bus Error  */
+#define FCW_INTFLAG_BUSERR_0                  (FCW_INTFLAG_BUSERR_0_Val << FCW_INTFLAG_BUSERR_Pos) /* (FCW_INTFLAG) No Bus Error Position */
+#define FCW_INTFLAG_BUSERR_1                  (FCW_INTFLAG_BUSERR_1_Val << FCW_INTFLAG_BUSERR_Pos) /* (FCW_INTFLAG) Bus Error Position */
+#define FCW_INTFLAG_WPERR_Pos                 _UINT32_(5)                                          /* (FCW_INTFLAG) Write Protection Error Flag Bit Position */
+#define FCW_INTFLAG_WPERR_Msk                 (_UINT32_(0x1) << FCW_INTFLAG_WPERR_Pos)             /* (FCW_INTFLAG) Write Protection Error Flag Bit Mask */
+#define FCW_INTFLAG_WPERR(value)              (FCW_INTFLAG_WPERR_Msk & (_UINT32_(value) << FCW_INTFLAG_WPERR_Pos)) /* Assignment of value for WPERR in the FCW_INTFLAG register */
+#define   FCW_INTFLAG_WPERR_0_Val             _UINT32_(0x0)                                        /* (FCW_INTFLAG) No Write Protection Error  */
+#define   FCW_INTFLAG_WPERR_1_Val             _UINT32_(0x1)                                        /* (FCW_INTFLAG) Write Protection Error  */
+#define FCW_INTFLAG_WPERR_0                   (FCW_INTFLAG_WPERR_0_Val << FCW_INTFLAG_WPERR_Pos)   /* (FCW_INTFLAG) No Write Protection Error Position */
+#define FCW_INTFLAG_WPERR_1                   (FCW_INTFLAG_WPERR_1_Val << FCW_INTFLAG_WPERR_Pos)   /* (FCW_INTFLAG) Write Protection Error Position */
+#define FCW_INTFLAG_OPERR_Pos                 _UINT32_(6)                                          /* (FCW_INTFLAG) NVMOP Error Flag Bit Position */
+#define FCW_INTFLAG_OPERR_Msk                 (_UINT32_(0x1) << FCW_INTFLAG_OPERR_Pos)             /* (FCW_INTFLAG) NVMOP Error Flag Bit Mask */
+#define FCW_INTFLAG_OPERR(value)              (FCW_INTFLAG_OPERR_Msk & (_UINT32_(value) << FCW_INTFLAG_OPERR_Pos)) /* Assignment of value for OPERR in the FCW_INTFLAG register */
+#define   FCW_INTFLAG_OPERR_0_Val             _UINT32_(0x0)                                        /* (FCW_INTFLAG) No NVMOP Error  */
+#define   FCW_INTFLAG_OPERR_1_Val             _UINT32_(0x1)                                        /* (FCW_INTFLAG) Selected Operation is Disabled Error  */
+#define FCW_INTFLAG_OPERR_0                   (FCW_INTFLAG_OPERR_0_Val << FCW_INTFLAG_OPERR_Pos)   /* (FCW_INTFLAG) No NVMOP Error Position */
+#define FCW_INTFLAG_OPERR_1                   (FCW_INTFLAG_OPERR_1_Val << FCW_INTFLAG_OPERR_Pos)   /* (FCW_INTFLAG) Selected Operation is Disabled Error Position */
+#define FCW_INTFLAG_HTDPGM_Pos                _UINT32_(8)                                          /* (FCW_INTFLAG) High Temperature Detect Error Flag Bit Position */
+#define FCW_INTFLAG_HTDPGM_Msk                (_UINT32_(0x1) << FCW_INTFLAG_HTDPGM_Pos)            /* (FCW_INTFLAG) High Temperature Detect Error Flag Bit Mask */
+#define FCW_INTFLAG_HTDPGM(value)             (FCW_INTFLAG_HTDPGM_Msk & (_UINT32_(value) << FCW_INTFLAG_HTDPGM_Pos)) /* Assignment of value for HTDPGM in the FCW_INTFLAG register */
+#define   FCW_INTFLAG_HTDPGM_0_Val            _UINT32_(0x0)                                        /* (FCW_INTFLAG) High Temp NOT Detected  */
+#define   FCW_INTFLAG_HTDPGM_1_Val            _UINT32_(0x1)                                        /* (FCW_INTFLAG) High Temp Detected (possible data corruption, verify operation)  */
+#define FCW_INTFLAG_HTDPGM_0                  (FCW_INTFLAG_HTDPGM_0_Val << FCW_INTFLAG_HTDPGM_Pos) /* (FCW_INTFLAG) High Temp NOT Detected Position */
+#define FCW_INTFLAG_HTDPGM_1                  (FCW_INTFLAG_HTDPGM_1_Val << FCW_INTFLAG_HTDPGM_Pos) /* (FCW_INTFLAG) High Temp Detected (possible data corruption, verify operation) Position */
+#define FCW_INTFLAG_RSTERR_Pos                _UINT32_(12)                                         /* (FCW_INTFLAG) Reset or Brown Out Detect Error Flag Bit Position */
+#define FCW_INTFLAG_RSTERR_Msk                (_UINT32_(0x1) << FCW_INTFLAG_RSTERR_Pos)            /* (FCW_INTFLAG) Reset or Brown Out Detect Error Flag Bit Mask */
+#define FCW_INTFLAG_RSTERR(value)             (FCW_INTFLAG_RSTERR_Msk & (_UINT32_(value) << FCW_INTFLAG_RSTERR_Pos)) /* Assignment of value for RSTERR in the FCW_INTFLAG register */
+#define   FCW_INTFLAG_RSTERR_0_Val            _UINT32_(0x0)                                        /* (FCW_INTFLAG) No Reset and Voltage level OK during write/erase  */
+#define   FCW_INTFLAG_RSTERR_1_Val            _UINT32_(0x1)                                        /* (FCW_INTFLAG) A reset or Low Voltage Detected (possible data corruption, verify data)  */
+#define FCW_INTFLAG_RSTERR_0                  (FCW_INTFLAG_RSTERR_0_Val << FCW_INTFLAG_RSTERR_Pos) /* (FCW_INTFLAG) No Reset and Voltage level OK during write/erase Position */
+#define FCW_INTFLAG_RSTERR_1                  (FCW_INTFLAG_RSTERR_1_Val << FCW_INTFLAG_RSTERR_Pos) /* (FCW_INTFLAG) A reset or Low Voltage Detected (possible data corruption, verify data) Position */
+#define FCW_INTFLAG_WRERR_Pos                 _UINT32_(13)                                         /* (FCW_INTFLAG) Write Error Flag Bit Position */
+#define FCW_INTFLAG_WRERR_Msk                 (_UINT32_(0x1) << FCW_INTFLAG_WRERR_Pos)             /* (FCW_INTFLAG) Write Error Flag Bit Mask */
+#define FCW_INTFLAG_WRERR(value)              (FCW_INTFLAG_WRERR_Msk & (_UINT32_(value) << FCW_INTFLAG_WRERR_Pos)) /* Assignment of value for WRERR in the FCW_INTFLAG register */
+#define   FCW_INTFLAG_WRERR_0_Val             _UINT32_(0x0)                                        /* (FCW_INTFLAG) The Write/Erase sequence completed normally  */
+#define   FCW_INTFLAG_WRERR_1_Val             _UINT32_(0x1)                                        /* (FCW_INTFLAG) The Write/Erase sequence did not complete successfully  */
+#define FCW_INTFLAG_WRERR_0                   (FCW_INTFLAG_WRERR_0_Val << FCW_INTFLAG_WRERR_Pos)   /* (FCW_INTFLAG) The Write/Erase sequence completed normally Position */
+#define FCW_INTFLAG_WRERR_1                   (FCW_INTFLAG_WRERR_1_Val << FCW_INTFLAG_WRERR_Pos)   /* (FCW_INTFLAG) The Write/Erase sequence did not complete successfully Position */
+#define FCW_INTFLAG_Msk                       _UINT32_(0x0000317F)                                 /* (FCW_INTFLAG) Register Mask  */
+
+
+/* -------- FCW_INTFLAGSET : (FCW Offset: 0x18) (R/W 32) Interrupt Flag Set REGISTER -------- */
+#define FCW_INTFLAGSET_RESETVALUE             _UINT32_(0x00)                                       /*  (FCW_INTFLAGSET) Interrupt Flag Set REGISTER  Reset Value */
+
+#define FCW_INTFLAGSET_DONE_Pos               _UINT32_(0)                                          /* (FCW_INTFLAGSET) NVM Operation Done Set Flag Bit Position */
+#define FCW_INTFLAGSET_DONE_Msk               (_UINT32_(0x1) << FCW_INTFLAGSET_DONE_Pos)           /* (FCW_INTFLAGSET) NVM Operation Done Set Flag Bit Mask */
+#define FCW_INTFLAGSET_DONE(value)            (FCW_INTFLAGSET_DONE_Msk & (_UINT32_(value) << FCW_INTFLAGSET_DONE_Pos)) /* Assignment of value for DONE in the FCW_INTFLAGSET register */
+#define   FCW_INTFLAGSET_DONE_0_Val           _UINT32_(0x0)                                        /* (FCW_INTFLAGSET) No effect  */
+#define   FCW_INTFLAGSET_DONE_1_Val           _UINT32_(0x1)                                        /* (FCW_INTFLAGSET) Set Interrupt Pending  */
+#define FCW_INTFLAGSET_DONE_0                 (FCW_INTFLAGSET_DONE_0_Val << FCW_INTFLAGSET_DONE_Pos) /* (FCW_INTFLAGSET) No effect Position */
+#define FCW_INTFLAGSET_DONE_1                 (FCW_INTFLAGSET_DONE_1_Val << FCW_INTFLAGSET_DONE_Pos) /* (FCW_INTFLAGSET) Set Interrupt Pending Position */
+#define FCW_INTFLAGSET_KEYERR_Pos             _UINT32_(1)                                          /* (FCW_INTFLAGSET) Key Error Set Flag Bit Position */
+#define FCW_INTFLAGSET_KEYERR_Msk             (_UINT32_(0x1) << FCW_INTFLAGSET_KEYERR_Pos)         /* (FCW_INTFLAGSET) Key Error Set Flag Bit Mask */
+#define FCW_INTFLAGSET_KEYERR(value)          (FCW_INTFLAGSET_KEYERR_Msk & (_UINT32_(value) << FCW_INTFLAGSET_KEYERR_Pos)) /* Assignment of value for KEYERR in the FCW_INTFLAGSET register */
+#define   FCW_INTFLAGSET_KEYERR_0_Val         _UINT32_(0x0)                                        /* (FCW_INTFLAGSET) No effect  */
+#define   FCW_INTFLAGSET_KEYERR_1_Val         _UINT32_(0x1)                                        /* (FCW_INTFLAGSET) Set Interrupt Pending  */
+#define FCW_INTFLAGSET_KEYERR_0               (FCW_INTFLAGSET_KEYERR_0_Val << FCW_INTFLAGSET_KEYERR_Pos) /* (FCW_INTFLAGSET) No effect Position */
+#define FCW_INTFLAGSET_KEYERR_1               (FCW_INTFLAGSET_KEYERR_1_Val << FCW_INTFLAGSET_KEYERR_Pos) /* (FCW_INTFLAGSET) Set Interrupt Pending Position */
+#define FCW_INTFLAGSET_CFGERR_Pos             _UINT32_(2)                                          /* (FCW_INTFLAGSET) Configuration Error Set Flag Bit Position */
+#define FCW_INTFLAGSET_CFGERR_Msk             (_UINT32_(0x1) << FCW_INTFLAGSET_CFGERR_Pos)         /* (FCW_INTFLAGSET) Configuration Error Set Flag Bit Mask */
+#define FCW_INTFLAGSET_CFGERR(value)          (FCW_INTFLAGSET_CFGERR_Msk & (_UINT32_(value) << FCW_INTFLAGSET_CFGERR_Pos)) /* Assignment of value for CFGERR in the FCW_INTFLAGSET register */
+#define   FCW_INTFLAGSET_CFGERR_0_Val         _UINT32_(0x0)                                        /* (FCW_INTFLAGSET) No effect  */
+#define   FCW_INTFLAGSET_CFGERR_1_Val         _UINT32_(0x1)                                        /* (FCW_INTFLAGSET) Set Interrupt Pending  */
+#define FCW_INTFLAGSET_CFGERR_0               (FCW_INTFLAGSET_CFGERR_0_Val << FCW_INTFLAGSET_CFGERR_Pos) /* (FCW_INTFLAGSET) No effect Position */
+#define FCW_INTFLAGSET_CFGERR_1               (FCW_INTFLAGSET_CFGERR_1_Val << FCW_INTFLAGSET_CFGERR_Pos) /* (FCW_INTFLAGSET) Set Interrupt Pending Position */
+#define FCW_INTFLAGSET_FIFOERR_Pos            _UINT32_(3)                                          /* (FCW_INTFLAGSET) FIFO Underrun during Row Write Set Flag Bit Position */
+#define FCW_INTFLAGSET_FIFOERR_Msk            (_UINT32_(0x1) << FCW_INTFLAGSET_FIFOERR_Pos)        /* (FCW_INTFLAGSET) FIFO Underrun during Row Write Set Flag Bit Mask */
+#define FCW_INTFLAGSET_FIFOERR(value)         (FCW_INTFLAGSET_FIFOERR_Msk & (_UINT32_(value) << FCW_INTFLAGSET_FIFOERR_Pos)) /* Assignment of value for FIFOERR in the FCW_INTFLAGSET register */
+#define   FCW_INTFLAGSET_FIFOERR_0_Val        _UINT32_(0x0)                                        /* (FCW_INTFLAGSET) No effect  */
+#define   FCW_INTFLAGSET_FIFOERR_1_Val        _UINT32_(0x1)                                        /* (FCW_INTFLAGSET) Set Interrupt Pending  */
+#define FCW_INTFLAGSET_FIFOERR_0              (FCW_INTFLAGSET_FIFOERR_0_Val << FCW_INTFLAGSET_FIFOERR_Pos) /* (FCW_INTFLAGSET) No effect Position */
+#define FCW_INTFLAGSET_FIFOERR_1              (FCW_INTFLAGSET_FIFOERR_1_Val << FCW_INTFLAGSET_FIFOERR_Pos) /* (FCW_INTFLAGSET) Set Interrupt Pending Position */
+#define FCW_INTFLAGSET_BUSERR_Pos             _UINT32_(4)                                          /* (FCW_INTFLAGSET) AHB Bus Error during Row Write Set Flag Bit Position */
+#define FCW_INTFLAGSET_BUSERR_Msk             (_UINT32_(0x1) << FCW_INTFLAGSET_BUSERR_Pos)         /* (FCW_INTFLAGSET) AHB Bus Error during Row Write Set Flag Bit Mask */
+#define FCW_INTFLAGSET_BUSERR(value)          (FCW_INTFLAGSET_BUSERR_Msk & (_UINT32_(value) << FCW_INTFLAGSET_BUSERR_Pos)) /* Assignment of value for BUSERR in the FCW_INTFLAGSET register */
+#define   FCW_INTFLAGSET_BUSERR_0_Val         _UINT32_(0x0)                                        /* (FCW_INTFLAGSET) No effect  */
+#define   FCW_INTFLAGSET_BUSERR_1_Val         _UINT32_(0x1)                                        /* (FCW_INTFLAGSET) Set Interrupt Pending  */
+#define FCW_INTFLAGSET_BUSERR_0               (FCW_INTFLAGSET_BUSERR_0_Val << FCW_INTFLAGSET_BUSERR_Pos) /* (FCW_INTFLAGSET) No effect Position */
+#define FCW_INTFLAGSET_BUSERR_1               (FCW_INTFLAGSET_BUSERR_1_Val << FCW_INTFLAGSET_BUSERR_Pos) /* (FCW_INTFLAGSET) Set Interrupt Pending Position */
+#define FCW_INTFLAGSET_WPERR_Pos              _UINT32_(5)                                          /* (FCW_INTFLAGSET) Write Protection Error Set Flag Bit Position */
+#define FCW_INTFLAGSET_WPERR_Msk              (_UINT32_(0x1) << FCW_INTFLAGSET_WPERR_Pos)          /* (FCW_INTFLAGSET) Write Protection Error Set Flag Bit Mask */
+#define FCW_INTFLAGSET_WPERR(value)           (FCW_INTFLAGSET_WPERR_Msk & (_UINT32_(value) << FCW_INTFLAGSET_WPERR_Pos)) /* Assignment of value for WPERR in the FCW_INTFLAGSET register */
+#define   FCW_INTFLAGSET_WPERR_0_Val          _UINT32_(0x0)                                        /* (FCW_INTFLAGSET) No effect  */
+#define   FCW_INTFLAGSET_WPERR_1_Val          _UINT32_(0x1)                                        /* (FCW_INTFLAGSET) Set Interrupt Pending  */
+#define FCW_INTFLAGSET_WPERR_0                (FCW_INTFLAGSET_WPERR_0_Val << FCW_INTFLAGSET_WPERR_Pos) /* (FCW_INTFLAGSET) No effect Position */
+#define FCW_INTFLAGSET_WPERR_1                (FCW_INTFLAGSET_WPERR_1_Val << FCW_INTFLAGSET_WPERR_Pos) /* (FCW_INTFLAGSET) Set Interrupt Pending Position */
+#define FCW_INTFLAGSET_OPERR_Pos              _UINT32_(6)                                          /* (FCW_INTFLAGSET) NVMOP Error Set Flag Bit Position */
+#define FCW_INTFLAGSET_OPERR_Msk              (_UINT32_(0x1) << FCW_INTFLAGSET_OPERR_Pos)          /* (FCW_INTFLAGSET) NVMOP Error Set Flag Bit Mask */
+#define FCW_INTFLAGSET_OPERR(value)           (FCW_INTFLAGSET_OPERR_Msk & (_UINT32_(value) << FCW_INTFLAGSET_OPERR_Pos)) /* Assignment of value for OPERR in the FCW_INTFLAGSET register */
+#define   FCW_INTFLAGSET_OPERR_0_Val          _UINT32_(0x0)                                        /* (FCW_INTFLAGSET) No effect  */
+#define   FCW_INTFLAGSET_OPERR_1_Val          _UINT32_(0x1)                                        /* (FCW_INTFLAGSET) Set Interrupt Pending  */
+#define FCW_INTFLAGSET_OPERR_0                (FCW_INTFLAGSET_OPERR_0_Val << FCW_INTFLAGSET_OPERR_Pos) /* (FCW_INTFLAGSET) No effect Position */
+#define FCW_INTFLAGSET_OPERR_1                (FCW_INTFLAGSET_OPERR_1_Val << FCW_INTFLAGSET_OPERR_Pos) /* (FCW_INTFLAGSET) Set Interrupt Pending Position */
+#define FCW_INTFLAGSET_HTDPGM_Pos             _UINT32_(8)                                          /* (FCW_INTFLAGSET) High Temperature Detect Error Set Flag Bit Position */
+#define FCW_INTFLAGSET_HTDPGM_Msk             (_UINT32_(0x1) << FCW_INTFLAGSET_HTDPGM_Pos)         /* (FCW_INTFLAGSET) High Temperature Detect Error Set Flag Bit Mask */
+#define FCW_INTFLAGSET_HTDPGM(value)          (FCW_INTFLAGSET_HTDPGM_Msk & (_UINT32_(value) << FCW_INTFLAGSET_HTDPGM_Pos)) /* Assignment of value for HTDPGM in the FCW_INTFLAGSET register */
+#define   FCW_INTFLAGSET_HTDPGM_0_Val         _UINT32_(0x0)                                        /* (FCW_INTFLAGSET) No effect  */
+#define   FCW_INTFLAGSET_HTDPGM_1_Val         _UINT32_(0x1)                                        /* (FCW_INTFLAGSET) Set Interrupt Pending  */
+#define FCW_INTFLAGSET_HTDPGM_0               (FCW_INTFLAGSET_HTDPGM_0_Val << FCW_INTFLAGSET_HTDPGM_Pos) /* (FCW_INTFLAGSET) No effect Position */
+#define FCW_INTFLAGSET_HTDPGM_1               (FCW_INTFLAGSET_HTDPGM_1_Val << FCW_INTFLAGSET_HTDPGM_Pos) /* (FCW_INTFLAGSET) Set Interrupt Pending Position */
+#define FCW_INTFLAGSET_RSTERR_Pos             _UINT32_(12)                                         /* (FCW_INTFLAGSET) Reset or Brown Out Detect Error Set Flag Bit Position */
+#define FCW_INTFLAGSET_RSTERR_Msk             (_UINT32_(0x1) << FCW_INTFLAGSET_RSTERR_Pos)         /* (FCW_INTFLAGSET) Reset or Brown Out Detect Error Set Flag Bit Mask */
+#define FCW_INTFLAGSET_RSTERR(value)          (FCW_INTFLAGSET_RSTERR_Msk & (_UINT32_(value) << FCW_INTFLAGSET_RSTERR_Pos)) /* Assignment of value for RSTERR in the FCW_INTFLAGSET register */
+#define   FCW_INTFLAGSET_RSTERR_0_Val         _UINT32_(0x0)                                        /* (FCW_INTFLAGSET) No effect  */
+#define   FCW_INTFLAGSET_RSTERR_1_Val         _UINT32_(0x1)                                        /* (FCW_INTFLAGSET) Set Interrupt Pending  */
+#define FCW_INTFLAGSET_RSTERR_0               (FCW_INTFLAGSET_RSTERR_0_Val << FCW_INTFLAGSET_RSTERR_Pos) /* (FCW_INTFLAGSET) No effect Position */
+#define FCW_INTFLAGSET_RSTERR_1               (FCW_INTFLAGSET_RSTERR_1_Val << FCW_INTFLAGSET_RSTERR_Pos) /* (FCW_INTFLAGSET) Set Interrupt Pending Position */
+#define FCW_INTFLAGSET_WRERR_Pos              _UINT32_(13)                                         /* (FCW_INTFLAGSET) Write Error Set Flag Bit Position */
+#define FCW_INTFLAGSET_WRERR_Msk              (_UINT32_(0x1) << FCW_INTFLAGSET_WRERR_Pos)          /* (FCW_INTFLAGSET) Write Error Set Flag Bit Mask */
+#define FCW_INTFLAGSET_WRERR(value)           (FCW_INTFLAGSET_WRERR_Msk & (_UINT32_(value) << FCW_INTFLAGSET_WRERR_Pos)) /* Assignment of value for WRERR in the FCW_INTFLAGSET register */
+#define   FCW_INTFLAGSET_WRERR_0_Val          _UINT32_(0x0)                                        /* (FCW_INTFLAGSET) No effect  */
+#define   FCW_INTFLAGSET_WRERR_1_Val          _UINT32_(0x1)                                        /* (FCW_INTFLAGSET) Set Interrupt Pending  */
+#define FCW_INTFLAGSET_WRERR_0                (FCW_INTFLAGSET_WRERR_0_Val << FCW_INTFLAGSET_WRERR_Pos) /* (FCW_INTFLAGSET) No effect Position */
+#define FCW_INTFLAGSET_WRERR_1                (FCW_INTFLAGSET_WRERR_1_Val << FCW_INTFLAGSET_WRERR_Pos) /* (FCW_INTFLAGSET) Set Interrupt Pending Position */
+#define FCW_INTFLAGSET_Msk                    _UINT32_(0x0000317F)                                 /* (FCW_INTFLAGSET) Register Mask  */
+
+
+/* -------- FCW_STATUS : (FCW Offset: 0x1C) ( R/ 32) Status REGISTER -------- */
+#define FCW_STATUS_RESETVALUE                 _UINT32_(0x00)                                       /*  (FCW_STATUS) Status REGISTER  Reset Value */
+
+#define FCW_STATUS_BUSY_Pos                   _UINT32_(0)                                          /* (FCW_STATUS) NVM Busy Status Position */
+#define FCW_STATUS_BUSY_Msk                   (_UINT32_(0x1) << FCW_STATUS_BUSY_Pos)               /* (FCW_STATUS) NVM Busy Status Mask */
+#define FCW_STATUS_BUSY(value)                (FCW_STATUS_BUSY_Msk & (_UINT32_(value) << FCW_STATUS_BUSY_Pos)) /* Assignment of value for BUSY in the FCW_STATUS register */
+#define   FCW_STATUS_BUSY_IDLE_Val            _UINT32_(0x0)                                        /* (FCW_STATUS) NVM Not Busy  */
+#define   FCW_STATUS_BUSY_BUSY_Val            _UINT32_(0x1)                                        /* (FCW_STATUS) NVM Busy - All SFR bits are not writable  */
+#define FCW_STATUS_BUSY_IDLE                  (FCW_STATUS_BUSY_IDLE_Val << FCW_STATUS_BUSY_Pos)    /* (FCW_STATUS) NVM Not Busy Position */
+#define FCW_STATUS_BUSY_BUSY                  (FCW_STATUS_BUSY_BUSY_Val << FCW_STATUS_BUSY_Pos)    /* (FCW_STATUS) NVM Busy - All SFR bits are not writable Position */
+#define FCW_STATUS_HTDRDY_Pos                 _UINT32_(8)                                          /* (FCW_STATUS) High Temp Detect Ready Status Position */
+#define FCW_STATUS_HTDRDY_Msk                 (_UINT32_(0x1) << FCW_STATUS_HTDRDY_Pos)             /* (FCW_STATUS) High Temp Detect Ready Status Mask */
+#define FCW_STATUS_HTDRDY(value)              (FCW_STATUS_HTDRDY_Msk & (_UINT32_(value) << FCW_STATUS_HTDRDY_Pos)) /* Assignment of value for HTDRDY in the FCW_STATUS register */
+#define   FCW_STATUS_HTDRDY_NOTREADY_Val      _UINT32_(0x0)                                        /* (FCW_STATUS) HTD Not Ready  */
+#define   FCW_STATUS_HTDRDY_READY_Val         _UINT32_(0x1)                                        /* (FCW_STATUS) HTD Ready  */
+#define FCW_STATUS_HTDRDY_NOTREADY            (FCW_STATUS_HTDRDY_NOTREADY_Val << FCW_STATUS_HTDRDY_Pos) /* (FCW_STATUS) HTD Not Ready Position */
+#define FCW_STATUS_HTDRDY_READY               (FCW_STATUS_HTDRDY_READY_Val << FCW_STATUS_HTDRDY_Pos) /* (FCW_STATUS) HTD Ready Position */
+#define FCW_STATUS_Msk                        _UINT32_(0x00000101)                                 /* (FCW_STATUS) Register Mask  */
+
+
+/* -------- FCW_KEY : (FCW Offset: 0x20) (R/W 32) Feature Unlock Key REGISTER -------- */
+#define FCW_KEY_RESETVALUE                    _UINT32_(0x00)                                       /*  (FCW_KEY) Feature Unlock Key REGISTER  Reset Value */
+
+#define FCW_KEY_FEATURE_Pos                   _UINT32_(0)                                          /* (FCW_KEY) Feature Select Position */
+#define FCW_KEY_FEATURE_Msk                   (_UINT32_(0xFF) << FCW_KEY_FEATURE_Pos)              /* (FCW_KEY) Feature Select Mask */
+#define FCW_KEY_FEATURE(value)                (FCW_KEY_FEATURE_Msk & (_UINT32_(value) << FCW_KEY_FEATURE_Pos)) /* Assignment of value for FEATURE in the FCW_KEY register */
+#define   FCW_KEY_FEATURE_LOCKALL_Val         _UINT32_(0x0)                                        /* (FCW_KEY) No selection, invalid selection, or invalid Key - Locks all SFR protected by KEY register  */
+#define   FCW_KEY_FEATURE_WRKEY_Val           _UINT32_(0x1)                                        /* (FCW_KEY) WRKEY Value: Unlock SFR bits associated with Write/Erase  */
+#define   FCW_KEY_FEATURE_SWAPKEY_Val         _UINT32_(0x2)                                        /* (FCW_KEY) SWAPKEY Value: Unlock SFR bits associated with Panel Swapping  */
+#define   FCW_KEY_FEATURE_CFGKEY_Val          _UINT32_(0x4)                                        /* (FCW_KEY) CFGKEY Value: Unlock SFR bits associated with general Flash configuration  */
+#define FCW_KEY_FEATURE_LOCKALL               (FCW_KEY_FEATURE_LOCKALL_Val << FCW_KEY_FEATURE_Pos) /* (FCW_KEY) No selection, invalid selection, or invalid Key - Locks all SFR protected by KEY register Position */
+#define FCW_KEY_FEATURE_WRKEY                 (FCW_KEY_FEATURE_WRKEY_Val << FCW_KEY_FEATURE_Pos)   /* (FCW_KEY) WRKEY Value: Unlock SFR bits associated with Write/Erase Position */
+#define FCW_KEY_FEATURE_SWAPKEY               (FCW_KEY_FEATURE_SWAPKEY_Val << FCW_KEY_FEATURE_Pos) /* (FCW_KEY) SWAPKEY Value: Unlock SFR bits associated with Panel Swapping Position */
+#define FCW_KEY_FEATURE_CFGKEY                (FCW_KEY_FEATURE_CFGKEY_Val << FCW_KEY_FEATURE_Pos)  /* (FCW_KEY) CFGKEY Value: Unlock SFR bits associated with general Flash configuration Position */
+#define FCW_KEY_CODE_Pos                      _UINT32_(8)                                          /* (FCW_KEY) Unlock Code Position */
+#define FCW_KEY_CODE_Msk                      (_UINT32_(0xFFFFFF) << FCW_KEY_CODE_Pos)             /* (FCW_KEY) Unlock Code Mask */
+#define FCW_KEY_CODE(value)                   (FCW_KEY_CODE_Msk & (_UINT32_(value) << FCW_KEY_CODE_Pos)) /* Assignment of value for CODE in the FCW_KEY register */
+#define FCW_KEY_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (FCW_KEY) Register Mask  */
+
+
+/* -------- FCW_ADDR : (FCW Offset: 0x24) (R/W 32) Flash Destination Address REGISTER -------- */
+#define FCW_ADDR_RESETVALUE                   _UINT32_(0x00)                                       /*  (FCW_ADDR) Flash Destination Address REGISTER  Reset Value */
+
+#define FCW_ADDR_ADDR_Pos                     _UINT32_(0)                                          /* (FCW_ADDR) Flash Address used by NVMOP Position */
+#define FCW_ADDR_ADDR_Msk                     (_UINT32_(0xFFFFFFFF) << FCW_ADDR_ADDR_Pos)          /* (FCW_ADDR) Flash Address used by NVMOP Mask */
+#define FCW_ADDR_ADDR(value)                  (FCW_ADDR_ADDR_Msk & (_UINT32_(value) << FCW_ADDR_ADDR_Pos)) /* Assignment of value for ADDR in the FCW_ADDR register */
+#define FCW_ADDR_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (FCW_ADDR) Register Mask  */
+
+
+/* -------- FCW_SRCADDR : (FCW Offset: 0x28) (R/W 32) System Source Address REGISTER -------- */
+#define FCW_SRCADDR_RESETVALUE                _UINT32_(0x00)                                       /*  (FCW_SRCADDR) System Source Address REGISTER  Reset Value */
+
+#define FCW_SRCADDR_SRCADDR_Pos               _UINT32_(0)                                          /* (FCW_SRCADDR) Source Data (Word) Address Position */
+#define FCW_SRCADDR_SRCADDR_Msk               (_UINT32_(0xFFFFFFFF) << FCW_SRCADDR_SRCADDR_Pos)    /* (FCW_SRCADDR) Source Data (Word) Address Mask */
+#define FCW_SRCADDR_SRCADDR(value)            (FCW_SRCADDR_SRCADDR_Msk & (_UINT32_(value) << FCW_SRCADDR_SRCADDR_Pos)) /* Assignment of value for SRCADDR in the FCW_SRCADDR register */
+#define FCW_SRCADDR_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (FCW_SRCADDR) Register Mask  */
+
+
+/* -------- FCW_DATA : (FCW Offset: 0x2C) (R/W 32) Flash Write Data n REGISTER -------- */
+#define FCW_DATA_RESETVALUE                   _UINT32_(0x00)                                       /*  (FCW_DATA) Flash Write Data n REGISTER  Reset Value */
+
+#define FCW_DATA_DATA_Pos                     _UINT32_(0)                                          /* (FCW_DATA) Flash Write Data Position */
+#define FCW_DATA_DATA_Msk                     (_UINT32_(0xFFFFFFFF) << FCW_DATA_DATA_Pos)          /* (FCW_DATA) Flash Write Data Mask */
+#define FCW_DATA_DATA(value)                  (FCW_DATA_DATA_Msk & (_UINT32_(value) << FCW_DATA_DATA_Pos)) /* Assignment of value for DATA in the FCW_DATA register */
+#define FCW_DATA_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (FCW_DATA) Register Mask  */
+
+
+/* -------- FCW_SWAP : (FCW Offset: 0x4C) (R/W 32) NVM Panel Swap REGISTER -------- */
+#define FCW_SWAP_RESETVALUE                   _UINT32_(0x00)                                       /*  (FCW_SWAP) NVM Panel Swap REGISTER  Reset Value */
+
+#define FCW_SWAP_BFSWAP_Pos                   _UINT32_(0)                                          /* (FCW_SWAP) BFM Swap Status/Control Bit Position */
+#define FCW_SWAP_BFSWAP_Msk                   (_UINT32_(0x1) << FCW_SWAP_BFSWAP_Pos)               /* (FCW_SWAP) BFM Swap Status/Control Bit Mask */
+#define FCW_SWAP_BFSWAP(value)                (FCW_SWAP_BFSWAP_Msk & (_UINT32_(value) << FCW_SWAP_BFSWAP_Pos)) /* Assignment of value for BFSWAP in the FCW_SWAP register */
+#define   FCW_SWAP_BFSWAP_UNSWAP_Val          _UINT32_(0x0)                                        /* (FCW_SWAP) Upper and Lower BFM Regions are NOT Swapped  */
+#define   FCW_SWAP_BFSWAP_SWAP_Val            _UINT32_(0x1)                                        /* (FCW_SWAP) Upper and Lower BFM Regions are Swapped  */
+#define FCW_SWAP_BFSWAP_UNSWAP                (FCW_SWAP_BFSWAP_UNSWAP_Val << FCW_SWAP_BFSWAP_Pos)  /* (FCW_SWAP) Upper and Lower BFM Regions are NOT Swapped Position */
+#define FCW_SWAP_BFSWAP_SWAP                  (FCW_SWAP_BFSWAP_SWAP_Val << FCW_SWAP_BFSWAP_Pos)    /* (FCW_SWAP) Upper and Lower BFM Regions are Swapped Position */
+#define FCW_SWAP_BFSLOCK_Pos                  _UINT32_(1)                                          /* (FCW_SWAP) BFM Swap Lock Bit Position */
+#define FCW_SWAP_BFSLOCK_Msk                  (_UINT32_(0x1) << FCW_SWAP_BFSLOCK_Pos)              /* (FCW_SWAP) BFM Swap Lock Bit Mask */
+#define FCW_SWAP_BFSLOCK(value)               (FCW_SWAP_BFSLOCK_Msk & (_UINT32_(value) << FCW_SWAP_BFSLOCK_Pos)) /* Assignment of value for BFSLOCK in the FCW_SWAP register */
+#define   FCW_SWAP_BFSLOCK_UNLOCKED_Val       _UINT32_(0x0)                                        /* (FCW_SWAP) BFSLOCK and BFSWAP can be written  */
+#define   FCW_SWAP_BFSLOCK_LOCKED_Val         _UINT32_(0x1)                                        /* (FCW_SWAP) BFSLOCK and BFSWAP cannot be written  */
+#define FCW_SWAP_BFSLOCK_UNLOCKED             (FCW_SWAP_BFSLOCK_UNLOCKED_Val << FCW_SWAP_BFSLOCK_Pos) /* (FCW_SWAP) BFSLOCK and BFSWAP can be written Position */
+#define FCW_SWAP_BFSLOCK_LOCKED               (FCW_SWAP_BFSLOCK_LOCKED_Val << FCW_SWAP_BFSLOCK_Pos) /* (FCW_SWAP) BFSLOCK and BFSWAP cannot be written Position */
+#define FCW_SWAP_PFSWAP_Pos                   _UINT32_(8)                                          /* (FCW_SWAP) PFM Swap Status/Control Bit Position */
+#define FCW_SWAP_PFSWAP_Msk                   (_UINT32_(0x1) << FCW_SWAP_PFSWAP_Pos)               /* (FCW_SWAP) PFM Swap Status/Control Bit Mask */
+#define FCW_SWAP_PFSWAP(value)                (FCW_SWAP_PFSWAP_Msk & (_UINT32_(value) << FCW_SWAP_PFSWAP_Pos)) /* Assignment of value for PFSWAP in the FCW_SWAP register */
+#define   FCW_SWAP_PFSWAP_UNSWAP_Val          _UINT32_(0x0)                                        /* (FCW_SWAP) Upper and Lower PFM Regions are NOT Swapped  */
+#define   FCW_SWAP_PFSWAP_SWAP_Val            _UINT32_(0x1)                                        /* (FCW_SWAP) Upper and Lower PFM Regions are Swapped  */
+#define FCW_SWAP_PFSWAP_UNSWAP                (FCW_SWAP_PFSWAP_UNSWAP_Val << FCW_SWAP_PFSWAP_Pos)  /* (FCW_SWAP) Upper and Lower PFM Regions are NOT Swapped Position */
+#define FCW_SWAP_PFSWAP_SWAP                  (FCW_SWAP_PFSWAP_SWAP_Val << FCW_SWAP_PFSWAP_Pos)    /* (FCW_SWAP) Upper and Lower PFM Regions are Swapped Position */
+#define FCW_SWAP_PFSLOCK_Pos                  _UINT32_(9)                                          /* (FCW_SWAP) PFM Swap Lock Bit Position */
+#define FCW_SWAP_PFSLOCK_Msk                  (_UINT32_(0x1) << FCW_SWAP_PFSLOCK_Pos)              /* (FCW_SWAP) PFM Swap Lock Bit Mask */
+#define FCW_SWAP_PFSLOCK(value)               (FCW_SWAP_PFSLOCK_Msk & (_UINT32_(value) << FCW_SWAP_PFSLOCK_Pos)) /* Assignment of value for PFSLOCK in the FCW_SWAP register */
+#define   FCW_SWAP_PFSLOCK_UNLOCKED_Val       _UINT32_(0x0)                                        /* (FCW_SWAP) PFSLOCK and PFSWAP can be written  */
+#define   FCW_SWAP_PFSLOCK_LOCKED_Val         _UINT32_(0x1)                                        /* (FCW_SWAP) PFSLOCK and PFSWAP cannot be written  */
+#define FCW_SWAP_PFSLOCK_UNLOCKED             (FCW_SWAP_PFSLOCK_UNLOCKED_Val << FCW_SWAP_PFSLOCK_Pos) /* (FCW_SWAP) PFSLOCK and PFSWAP can be written Position */
+#define FCW_SWAP_PFSLOCK_LOCKED               (FCW_SWAP_PFSLOCK_LOCKED_Val << FCW_SWAP_PFSLOCK_Pos) /* (FCW_SWAP) PFSLOCK and PFSWAP cannot be written Position */
+#define FCW_SWAP_Msk                          _UINT32_(0x00000303)                                 /* (FCW_SWAP) Register Mask  */
+
+
+/* -------- FCW_PWP : (FCW Offset: 0x50) (R/W 32) PFM Write Protect Region n REGISTER -------- */
+#define FCW_PWP_RESETVALUE                    _UINT32_(0x00)                                       /*  (FCW_PWP) PFM Write Protect Region n REGISTER  Reset Value */
+
+#define FCW_PWP_PWPSIZE_Pos                   _UINT32_(0)                                          /* (FCW_PWP) PWP Size in 4KB pages Position */
+#define FCW_PWP_PWPSIZE_Msk                   (_UINT32_(0x7F) << FCW_PWP_PWPSIZE_Pos)              /* (FCW_PWP) PWP Size in 4KB pages Mask */
+#define FCW_PWP_PWPSIZE(value)                (FCW_PWP_PWPSIZE_Msk & (_UINT32_(value) << FCW_PWP_PWPSIZE_Pos)) /* Assignment of value for PWPSIZE in the FCW_PWP register */
+#define FCW_PWP_PWPMIR_Pos                    _UINT32_(13)                                         /* (FCW_PWP) Mirror PWP bit Position */
+#define FCW_PWP_PWPMIR_Msk                    (_UINT32_(0x1) << FCW_PWP_PWPMIR_Pos)                /* (FCW_PWP) Mirror PWP bit Mask */
+#define FCW_PWP_PWPMIR(value)                 (FCW_PWP_PWPMIR_Msk & (_UINT32_(value) << FCW_PWP_PWPMIR_Pos)) /* Assignment of value for PWPMIR in the FCW_PWP register */
+#define   FCW_PWP_PWPMIR_UNMIRROR_Val         _UINT32_(0x0)                                        /* (FCW_PWP) PWP settings are NOT Mirrored  */
+#define   FCW_PWP_PWPMIR_MIRROR_Val           _UINT32_(0x1)                                        /* (FCW_PWP) PWP settings are Mirrored  */
+#define FCW_PWP_PWPMIR_UNMIRROR               (FCW_PWP_PWPMIR_UNMIRROR_Val << FCW_PWP_PWPMIR_Pos)  /* (FCW_PWP) PWP settings are NOT Mirrored Position */
+#define FCW_PWP_PWPMIR_MIRROR                 (FCW_PWP_PWPMIR_MIRROR_Val << FCW_PWP_PWPMIR_Pos)    /* (FCW_PWP) PWP settings are Mirrored Position */
+#define FCW_PWP_PWPLOCK_Pos                   _UINT32_(14)                                         /* (FCW_PWP) PWP Lock Bit Position */
+#define FCW_PWP_PWPLOCK_Msk                   (_UINT32_(0x1) << FCW_PWP_PWPLOCK_Pos)               /* (FCW_PWP) PWP Lock Bit Mask */
+#define FCW_PWP_PWPLOCK(value)                (FCW_PWP_PWPLOCK_Msk & (_UINT32_(value) << FCW_PWP_PWPLOCK_Pos)) /* Assignment of value for PWPLOCK in the FCW_PWP register */
+#define   FCW_PWP_PWPLOCK_UNLOCKED_Val        _UINT32_(0x0)                                        /* (FCW_PWP) This register is Not Locked and can be modified  */
+#define   FCW_PWP_PWPLOCK_LOCKED_Val          _UINT32_(0x1)                                        /* (FCW_PWP) This register is Locked and cannot be modified  */
+#define FCW_PWP_PWPLOCK_UNLOCKED              (FCW_PWP_PWPLOCK_UNLOCKED_Val << FCW_PWP_PWPLOCK_Pos) /* (FCW_PWP) This register is Not Locked and can be modified Position */
+#define FCW_PWP_PWPLOCK_LOCKED                (FCW_PWP_PWPLOCK_LOCKED_Val << FCW_PWP_PWPLOCK_Pos)  /* (FCW_PWP) This register is Locked and cannot be modified Position */
+#define FCW_PWP_PWPEN_Pos                     _UINT32_(15)                                         /* (FCW_PWP) PWP Enable Bit Position */
+#define FCW_PWP_PWPEN_Msk                     (_UINT32_(0x1) << FCW_PWP_PWPEN_Pos)                 /* (FCW_PWP) PWP Enable Bit Mask */
+#define FCW_PWP_PWPEN(value)                  (FCW_PWP_PWPEN_Msk & (_UINT32_(value) << FCW_PWP_PWPEN_Pos)) /* Assignment of value for PWPEN in the FCW_PWP register */
+#define   FCW_PWP_PWPEN_DISABLE_Val           _UINT32_(0x0)                                        /* (FCW_PWP) PWP is Not Enabled for the defined region  */
+#define   FCW_PWP_PWPEN_ENABLE_Val            _UINT32_(0x1)                                        /* (FCW_PWP) PWP is Enabled for the defined region  */
+#define FCW_PWP_PWPEN_DISABLE                 (FCW_PWP_PWPEN_DISABLE_Val << FCW_PWP_PWPEN_Pos)     /* (FCW_PWP) PWP is Not Enabled for the defined region Position */
+#define FCW_PWP_PWPEN_ENABLE                  (FCW_PWP_PWPEN_ENABLE_Val << FCW_PWP_PWPEN_Pos)      /* (FCW_PWP) PWP is Enabled for the defined region Position */
+#define FCW_PWP_PWPBASE_Pos                   _UINT32_(16)                                         /* (FCW_PWP) PWP Base Address - 4KB Page Aligned Position */
+#define FCW_PWP_PWPBASE_Msk                   (_UINT32_(0x7F) << FCW_PWP_PWPBASE_Pos)              /* (FCW_PWP) PWP Base Address - 4KB Page Aligned Mask */
+#define FCW_PWP_PWPBASE(value)                (FCW_PWP_PWPBASE_Msk & (_UINT32_(value) << FCW_PWP_PWPBASE_Pos)) /* Assignment of value for PWPBASE in the FCW_PWP register */
+#define FCW_PWP_Msk                           _UINT32_(0x007FE07F)                                 /* (FCW_PWP) Register Mask  */
+
+
+/* -------- FCW_LBWP : (FCW Offset: 0x70) (R/W 32) Lower BFM Write Protect REGISTER -------- */
+#define FCW_LBWP_RESETVALUE                   _UINT32_(0x03)                                       /*  (FCW_LBWP) Lower BFM Write Protect REGISTER  Reset Value */
+
+#define FCW_LBWP_LBWP_Pos                     _UINT32_(0)                                          /* (FCW_LBWP) Lower Boot Pages Write Protect Bits Position */
+#define FCW_LBWP_LBWP_Msk                     (_UINT32_(0x3) << FCW_LBWP_LBWP_Pos)                 /* (FCW_LBWP) Lower Boot Pages Write Protect Bits Mask */
+#define FCW_LBWP_LBWP(value)                  (FCW_LBWP_LBWP_Msk & (_UINT32_(value) << FCW_LBWP_LBWP_Pos)) /* Assignment of value for LBWP in the FCW_LBWP register */
+#define   FCW_LBWP_LBWP_DISABLE_Val           _UINT32_(0x0)                                        /* (FCW_LBWP) Erase and Write Protection for this Lower Boot Page is Disabled  */
+#define   FCW_LBWP_LBWP_ENABLE_Val            _UINT32_(0x1)                                        /* (FCW_LBWP) Erase and Write Protection for this Lower Boot Page is Enabled  */
+#define FCW_LBWP_LBWP_DISABLE                 (FCW_LBWP_LBWP_DISABLE_Val << FCW_LBWP_LBWP_Pos)     /* (FCW_LBWP) Erase and Write Protection for this Lower Boot Page is Disabled Position */
+#define FCW_LBWP_LBWP_ENABLE                  (FCW_LBWP_LBWP_ENABLE_Val << FCW_LBWP_LBWP_Pos)      /* (FCW_LBWP) Erase and Write Protection for this Lower Boot Page is Enabled Position */
+#define FCW_LBWP_LBWPLOCK_Pos                 _UINT32_(31)                                         /* (FCW_LBWP) LBWP Lock Bit Position */
+#define FCW_LBWP_LBWPLOCK_Msk                 (_UINT32_(0x1) << FCW_LBWP_LBWPLOCK_Pos)             /* (FCW_LBWP) LBWP Lock Bit Mask */
+#define FCW_LBWP_LBWPLOCK(value)              (FCW_LBWP_LBWPLOCK_Msk & (_UINT32_(value) << FCW_LBWP_LBWPLOCK_Pos)) /* Assignment of value for LBWPLOCK in the FCW_LBWP register */
+#define   FCW_LBWP_LBWPLOCK_UNLOCKED_Val      _UINT32_(0x0)                                        /* (FCW_LBWP) This register is NOT Locked and can be modified  */
+#define   FCW_LBWP_LBWPLOCK_LOCKED_Val        _UINT32_(0x1)                                        /* (FCW_LBWP) This register is Locked and cannot be modified  */
+#define FCW_LBWP_LBWPLOCK_UNLOCKED            (FCW_LBWP_LBWPLOCK_UNLOCKED_Val << FCW_LBWP_LBWPLOCK_Pos) /* (FCW_LBWP) This register is NOT Locked and can be modified Position */
+#define FCW_LBWP_LBWPLOCK_LOCKED              (FCW_LBWP_LBWPLOCK_LOCKED_Val << FCW_LBWP_LBWPLOCK_Pos) /* (FCW_LBWP) This register is Locked and cannot be modified Position */
+#define FCW_LBWP_Msk                          _UINT32_(0x80000003)                                 /* (FCW_LBWP) Register Mask  */
+
+
+/* -------- FCW_UBWP : (FCW Offset: 0x74) (R/W 32) Upper BFM Write Protect REGISTER -------- */
+#define FCW_UBWP_RESETVALUE                   _UINT32_(0x03)                                       /*  (FCW_UBWP) Upper BFM Write Protect REGISTER  Reset Value */
+
+#define FCW_UBWP_UBWP_Pos                     _UINT32_(0)                                          /* (FCW_UBWP) Upper Boot Pages Write Protect Bits Position */
+#define FCW_UBWP_UBWP_Msk                     (_UINT32_(0x3) << FCW_UBWP_UBWP_Pos)                 /* (FCW_UBWP) Upper Boot Pages Write Protect Bits Mask */
+#define FCW_UBWP_UBWP(value)                  (FCW_UBWP_UBWP_Msk & (_UINT32_(value) << FCW_UBWP_UBWP_Pos)) /* Assignment of value for UBWP in the FCW_UBWP register */
+#define   FCW_UBWP_UBWP_DISABLE_Val           _UINT32_(0x0)                                        /* (FCW_UBWP) Erase and Write Protection for this Upper Boot Page is Disabled  */
+#define   FCW_UBWP_UBWP_ENABLE_Val            _UINT32_(0x1)                                        /* (FCW_UBWP) Erase and Write Protection for this Upper Boot Page is Enabled  */
+#define FCW_UBWP_UBWP_DISABLE                 (FCW_UBWP_UBWP_DISABLE_Val << FCW_UBWP_UBWP_Pos)     /* (FCW_UBWP) Erase and Write Protection for this Upper Boot Page is Disabled Position */
+#define FCW_UBWP_UBWP_ENABLE                  (FCW_UBWP_UBWP_ENABLE_Val << FCW_UBWP_UBWP_Pos)      /* (FCW_UBWP) Erase and Write Protection for this Upper Boot Page is Enabled Position */
+#define FCW_UBWP_UBWPLOCK_Pos                 _UINT32_(31)                                         /* (FCW_UBWP) UBWP Lock Bit Position */
+#define FCW_UBWP_UBWPLOCK_Msk                 (_UINT32_(0x1) << FCW_UBWP_UBWPLOCK_Pos)             /* (FCW_UBWP) UBWP Lock Bit Mask */
+#define FCW_UBWP_UBWPLOCK(value)              (FCW_UBWP_UBWPLOCK_Msk & (_UINT32_(value) << FCW_UBWP_UBWPLOCK_Pos)) /* Assignment of value for UBWPLOCK in the FCW_UBWP register */
+#define   FCW_UBWP_UBWPLOCK_UNLOCKED_Val      _UINT32_(0x0)                                        /* (FCW_UBWP) This register is NOT Locked and can be modified  */
+#define   FCW_UBWP_UBWPLOCK_LOCKED_Val        _UINT32_(0x1)                                        /* (FCW_UBWP) This register is Locked and cannot be modified  */
+#define FCW_UBWP_UBWPLOCK_UNLOCKED            (FCW_UBWP_UBWPLOCK_UNLOCKED_Val << FCW_UBWP_UBWPLOCK_Pos) /* (FCW_UBWP) This register is NOT Locked and can be modified Position */
+#define FCW_UBWP_UBWPLOCK_LOCKED              (FCW_UBWP_UBWPLOCK_LOCKED_Val << FCW_UBWP_UBWPLOCK_Pos) /* (FCW_UBWP) This register is Locked and cannot be modified Position */
+#define FCW_UBWP_Msk                          _UINT32_(0x80000003)                                 /* (FCW_UBWP) Register Mask  */
+
+
+/* -------- FCW_UOWP : (FCW Offset: 0x78) (R/W 32) User OTP Write protection REGISTER -------- */
+#define FCW_UOWP_RESETVALUE                   _UINT32_(0x0F)                                       /*  (FCW_UOWP) User OTP Write protection REGISTER  Reset Value */
+
+#define FCW_UOWP_UO1WPR_Pos                   _UINT32_(0)                                          /* (FCW_UOWP) User OTP Page 1 Write Protect Row Bit Position */
+#define FCW_UOWP_UO1WPR_Msk                   (_UINT32_(0xF) << FCW_UOWP_UO1WPR_Pos)               /* (FCW_UOWP) User OTP Page 1 Write Protect Row Bit Mask */
+#define FCW_UOWP_UO1WPR(value)                (FCW_UOWP_UO1WPR_Msk & (_UINT32_(value) << FCW_UOWP_UO1WPR_Pos)) /* Assignment of value for UO1WPR in the FCW_UOWP register */
+#define   FCW_UOWP_UO1WPR_DISABLE_Val         _UINT32_(0x0)                                        /* (FCW_UOWP) Write Protection for User OTP Page 1 Row "n" is Disabled  */
+#define   FCW_UOWP_UO1WPR_ENABLE_Val          _UINT32_(0x1)                                        /* (FCW_UOWP) Write Protection for User OTP Page 1 Row "n" is Enabled  */
+#define FCW_UOWP_UO1WPR_DISABLE               (FCW_UOWP_UO1WPR_DISABLE_Val << FCW_UOWP_UO1WPR_Pos) /* (FCW_UOWP) Write Protection for User OTP Page 1 Row "n" is Disabled Position */
+#define FCW_UOWP_UO1WPR_ENABLE                (FCW_UOWP_UO1WPR_ENABLE_Val << FCW_UOWP_UO1WPR_Pos)  /* (FCW_UOWP) Write Protection for User OTP Page 1 Row "n" is Enabled Position */
+#define FCW_UOWP_UO1WPRLOCK_Pos               _UINT32_(16)                                         /* (FCW_UOWP) User OTP Page 1 WP Row Lock Bit Position */
+#define FCW_UOWP_UO1WPRLOCK_Msk               (_UINT32_(0xF) << FCW_UOWP_UO1WPRLOCK_Pos)           /* (FCW_UOWP) User OTP Page 1 WP Row Lock Bit Mask */
+#define FCW_UOWP_UO1WPRLOCK(value)            (FCW_UOWP_UO1WPRLOCK_Msk & (_UINT32_(value) << FCW_UOWP_UO1WPRLOCK_Pos)) /* Assignment of value for UO1WPRLOCK in the FCW_UOWP register */
+#define   FCW_UOWP_UO1WPRLOCK_UNLOCKED_Val    _UINT32_(0x0)                                        /* (FCW_UOWP) UO1WPR[n] &amp; UO1WPRLOCK[n] bits are NOT Locked and can be modified  */
+#define   FCW_UOWP_UO1WPRLOCK_LOCKED_Val      _UINT32_(0x1)                                        /* (FCW_UOWP) UO1WPR[n] &amp; UO1WPRLOCK[n] bits are Locked and cannot be modified  */
+#define FCW_UOWP_UO1WPRLOCK_UNLOCKED          (FCW_UOWP_UO1WPRLOCK_UNLOCKED_Val << FCW_UOWP_UO1WPRLOCK_Pos) /* (FCW_UOWP) UO1WPR[n] &amp; UO1WPRLOCK[n] bits are NOT Locked and can be modified Position */
+#define FCW_UOWP_UO1WPRLOCK_LOCKED            (FCW_UOWP_UO1WPRLOCK_LOCKED_Val << FCW_UOWP_UO1WPRLOCK_Pos) /* (FCW_UOWP) UO1WPR[n] &amp; UO1WPRLOCK[n] bits are Locked and cannot be modified Position */
+#define FCW_UOWP_Msk                          _UINT32_(0x000F000F)                                 /* (FCW_UOWP) Register Mask  */
+
+
+/* -------- FCW_CWP : (FCW Offset: 0x7C) (R/W 32) CFM Page Write Protect REGISTER -------- */
+#define FCW_CWP_RESETVALUE                    _UINT32_(0x8C008FD)                                  /*  (FCW_CWP) CFM Page Write Protect REGISTER  Reset Value */
+
+#define FCW_CWP_BC1AWP_Pos                    _UINT32_(0)                                          /* (FCW_CWP) Panel 1 Write Protect BootCfg1A Position */
+#define FCW_CWP_BC1AWP_Msk                    (_UINT32_(0x1) << FCW_CWP_BC1AWP_Pos)                /* (FCW_CWP) Panel 1 Write Protect BootCfg1A Mask */
+#define FCW_CWP_BC1AWP(value)                 (FCW_CWP_BC1AWP_Msk & (_UINT32_(value) << FCW_CWP_BC1AWP_Pos)) /* Assignment of value for BC1AWP in the FCW_CWP register */
+#define   FCW_CWP_BC1AWP_DISABLE_Val          _UINT32_(0x0)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FCW_CWP_BC1AWP_ENABLE_Val           _UINT32_(0x1)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FCW_CWP_BC1AWP_DISABLE                (FCW_CWP_BC1AWP_DISABLE_Val << FCW_CWP_BC1AWP_Pos)   /* (FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FCW_CWP_BC1AWP_ENABLE                 (FCW_CWP_BC1AWP_ENABLE_Val << FCW_CWP_BC1AWP_Pos)    /* (FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FCW_CWP_BC1WP_Pos                     _UINT32_(2)                                          /* (FCW_CWP) Panel 1 Write Protect BootCfg1 Position */
+#define FCW_CWP_BC1WP_Msk                     (_UINT32_(0x1) << FCW_CWP_BC1WP_Pos)                 /* (FCW_CWP) Panel 1 Write Protect BootCfg1 Mask */
+#define FCW_CWP_BC1WP(value)                  (FCW_CWP_BC1WP_Msk & (_UINT32_(value) << FCW_CWP_BC1WP_Pos)) /* Assignment of value for BC1WP in the FCW_CWP register */
+#define   FCW_CWP_BC1WP_DISABLE_Val           _UINT32_(0x0)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FCW_CWP_BC1WP_ENABLE_Val            _UINT32_(0x1)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FCW_CWP_BC1WP_DISABLE                 (FCW_CWP_BC1WP_DISABLE_Val << FCW_CWP_BC1WP_Pos)     /* (FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FCW_CWP_BC1WP_ENABLE                  (FCW_CWP_BC1WP_ENABLE_Val << FCW_CWP_BC1WP_Pos)      /* (FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FCW_CWP_RCWP_Pos                      _UINT32_(3)                                          /* (FCW_CWP) Panel 1 Write Protect ROMCfg Position */
+#define FCW_CWP_RCWP_Msk                      (_UINT32_(0x1) << FCW_CWP_RCWP_Pos)                  /* (FCW_CWP) Panel 1 Write Protect ROMCfg Mask */
+#define FCW_CWP_RCWP(value)                   (FCW_CWP_RCWP_Msk & (_UINT32_(value) << FCW_CWP_RCWP_Pos)) /* Assignment of value for RCWP in the FCW_CWP register */
+#define   FCW_CWP_RCWP_DISABLE_Val            _UINT32_(0x0)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FCW_CWP_RCWP_ENABLE_Val             _UINT32_(0x1)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FCW_CWP_RCWP_DISABLE                  (FCW_CWP_RCWP_DISABLE_Val << FCW_CWP_RCWP_Pos)       /* (FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FCW_CWP_RCWP_ENABLE                   (FCW_CWP_RCWP_ENABLE_Val << FCW_CWP_RCWP_Pos)        /* (FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FCW_CWP_VSSWP0_Pos                    _UINT32_(4)                                          /* (FCW_CWP) Panel 1 Write Protect VSSn Position */
+#define FCW_CWP_VSSWP0_Msk                    (_UINT32_(0x1) << FCW_CWP_VSSWP0_Pos)                /* (FCW_CWP) Panel 1 Write Protect VSSn Mask */
+#define FCW_CWP_VSSWP0(value)                 (FCW_CWP_VSSWP0_Msk & (_UINT32_(value) << FCW_CWP_VSSWP0_Pos)) /* Assignment of value for VSSWP0 in the FCW_CWP register */
+#define   FCW_CWP_VSSWP0_DISABLE_Val          _UINT32_(0x0)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FCW_CWP_VSSWP0_ENABLE_Val           _UINT32_(0x1)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FCW_CWP_VSSWP0_DISABLE                (FCW_CWP_VSSWP0_DISABLE_Val << FCW_CWP_VSSWP0_Pos)   /* (FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FCW_CWP_VSSWP0_ENABLE                 (FCW_CWP_VSSWP0_ENABLE_Val << FCW_CWP_VSSWP0_Pos)    /* (FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FCW_CWP_VSSWP1_Pos                    _UINT32_(5)                                          /* (FCW_CWP) Panel 1 Write Protect VSSn Position */
+#define FCW_CWP_VSSWP1_Msk                    (_UINT32_(0x1) << FCW_CWP_VSSWP1_Pos)                /* (FCW_CWP) Panel 1 Write Protect VSSn Mask */
+#define FCW_CWP_VSSWP1(value)                 (FCW_CWP_VSSWP1_Msk & (_UINT32_(value) << FCW_CWP_VSSWP1_Pos)) /* Assignment of value for VSSWP1 in the FCW_CWP register */
+#define   FCW_CWP_VSSWP1_DISABLE_Val          _UINT32_(0x0)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FCW_CWP_VSSWP1_ENABLE_Val           _UINT32_(0x1)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FCW_CWP_VSSWP1_DISABLE                (FCW_CWP_VSSWP1_DISABLE_Val << FCW_CWP_VSSWP1_Pos)   /* (FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FCW_CWP_VSSWP1_ENABLE                 (FCW_CWP_VSSWP1_ENABLE_Val << FCW_CWP_VSSWP1_Pos)    /* (FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FCW_CWP_TWP_Pos                       _UINT32_(6)                                          /* (FCW_CWP) Panel 1 Write Protect Test Position */
+#define FCW_CWP_TWP_Msk                       (_UINT32_(0x1) << FCW_CWP_TWP_Pos)                   /* (FCW_CWP) Panel 1 Write Protect Test Mask */
+#define FCW_CWP_TWP(value)                    (FCW_CWP_TWP_Msk & (_UINT32_(value) << FCW_CWP_TWP_Pos)) /* Assignment of value for TWP in the FCW_CWP register */
+#define   FCW_CWP_TWP_DISABLE_Val             _UINT32_(0x0)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FCW_CWP_TWP_ENABLE_Val              _UINT32_(0x1)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Enable  */
+#define FCW_CWP_TWP_DISABLE                   (FCW_CWP_TWP_DISABLE_Val << FCW_CWP_TWP_Pos)         /* (FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FCW_CWP_TWP_ENABLE                    (FCW_CWP_TWP_ENABLE_Val << FCW_CWP_TWP_Pos)          /* (FCW_CWP) Erase and Write Protection for this Page is Enable Position */
+#define FCW_CWP_COWP_Pos                      _UINT32_(7)                                          /* (FCW_CWP) Panel 1 Write Protect CalOTP Position */
+#define FCW_CWP_COWP_Msk                      (_UINT32_(0x1) << FCW_CWP_COWP_Pos)                  /* (FCW_CWP) Panel 1 Write Protect CalOTP Mask */
+#define FCW_CWP_COWP(value)                   (FCW_CWP_COWP_Msk & (_UINT32_(value) << FCW_CWP_COWP_Pos)) /* Assignment of value for COWP in the FCW_CWP register */
+#define   FCW_CWP_COWP_DISABLE_Val            _UINT32_(0x0)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FCW_CWP_COWP_ENABLE_Val             _UINT32_(0x1)                                        /* (FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FCW_CWP_COWP_DISABLE                  (FCW_CWP_COWP_DISABLE_Val << FCW_CWP_COWP_Pos)       /* (FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FCW_CWP_COWP_ENABLE                   (FCW_CWP_COWP_ENABLE_Val << FCW_CWP_COWP_Pos)        /* (FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FCW_CWP_BC1AWPLOCK_Pos                _UINT32_(16)                                         /* (FCW_CWP) Panel 1 Lock Write Protection BootCfg1A Position */
+#define FCW_CWP_BC1AWPLOCK_Msk                (_UINT32_(0x1) << FCW_CWP_BC1AWPLOCK_Pos)            /* (FCW_CWP) Panel 1 Lock Write Protection BootCfg1A Mask */
+#define FCW_CWP_BC1AWPLOCK(value)             (FCW_CWP_BC1AWPLOCK_Msk & (_UINT32_(value) << FCW_CWP_BC1AWPLOCK_Pos)) /* Assignment of value for BC1AWPLOCK in the FCW_CWP register */
+#define   FCW_CWP_BC1AWPLOCK_UNLOCKED_Val     _UINT32_(0x0)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCW_CWP_BC1AWPLOCK_LOCKED_Val       _UINT32_(0x1)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FCW_CWP_BC1AWPLOCK_UNLOCKED           (FCW_CWP_BC1AWPLOCK_UNLOCKED_Val << FCW_CWP_BC1AWPLOCK_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCW_CWP_BC1AWPLOCK_LOCKED             (FCW_CWP_BC1AWPLOCK_LOCKED_Val << FCW_CWP_BC1AWPLOCK_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FCW_CWP_BC1WPLOCK_Pos                 _UINT32_(18)                                         /* (FCW_CWP) Panel 1 Lock Write Protection BootCfg1 Position */
+#define FCW_CWP_BC1WPLOCK_Msk                 (_UINT32_(0x1) << FCW_CWP_BC1WPLOCK_Pos)             /* (FCW_CWP) Panel 1 Lock Write Protection BootCfg1 Mask */
+#define FCW_CWP_BC1WPLOCK(value)              (FCW_CWP_BC1WPLOCK_Msk & (_UINT32_(value) << FCW_CWP_BC1WPLOCK_Pos)) /* Assignment of value for BC1WPLOCK in the FCW_CWP register */
+#define   FCW_CWP_BC1WPLOCK_UNLOCKED_Val      _UINT32_(0x0)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCW_CWP_BC1WPLOCK_LOCKED_Val        _UINT32_(0x1)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FCW_CWP_BC1WPLOCK_UNLOCKED            (FCW_CWP_BC1WPLOCK_UNLOCKED_Val << FCW_CWP_BC1WPLOCK_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCW_CWP_BC1WPLOCK_LOCKED              (FCW_CWP_BC1WPLOCK_LOCKED_Val << FCW_CWP_BC1WPLOCK_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FCW_CWP_RCWPLOCK_Pos                  _UINT32_(19)                                         /* (FCW_CWP) Panel 1 Lock Write Protection ROMCfg Position */
+#define FCW_CWP_RCWPLOCK_Msk                  (_UINT32_(0x1) << FCW_CWP_RCWPLOCK_Pos)              /* (FCW_CWP) Panel 1 Lock Write Protection ROMCfg Mask */
+#define FCW_CWP_RCWPLOCK(value)               (FCW_CWP_RCWPLOCK_Msk & (_UINT32_(value) << FCW_CWP_RCWPLOCK_Pos)) /* Assignment of value for RCWPLOCK in the FCW_CWP register */
+#define   FCW_CWP_RCWPLOCK_UNLOCKED_Val       _UINT32_(0x0)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCW_CWP_RCWPLOCK_LOCKED_Val         _UINT32_(0x1)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FCW_CWP_RCWPLOCK_UNLOCKED             (FCW_CWP_RCWPLOCK_UNLOCKED_Val << FCW_CWP_RCWPLOCK_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCW_CWP_RCWPLOCK_LOCKED               (FCW_CWP_RCWPLOCK_LOCKED_Val << FCW_CWP_RCWPLOCK_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FCW_CWP_VSSWPLOCK0_Pos                _UINT32_(20)                                         /* (FCW_CWP) Panel 1 Lock Write Protection VSSn Position */
+#define FCW_CWP_VSSWPLOCK0_Msk                (_UINT32_(0x1) << FCW_CWP_VSSWPLOCK0_Pos)            /* (FCW_CWP) Panel 1 Lock Write Protection VSSn Mask */
+#define FCW_CWP_VSSWPLOCK0(value)             (FCW_CWP_VSSWPLOCK0_Msk & (_UINT32_(value) << FCW_CWP_VSSWPLOCK0_Pos)) /* Assignment of value for VSSWPLOCK0 in the FCW_CWP register */
+#define   FCW_CWP_VSSWPLOCK0_UNLOCKED_Val     _UINT32_(0x0)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCW_CWP_VSSWPLOCK0_LOCKED_Val       _UINT32_(0x1)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FCW_CWP_VSSWPLOCK0_UNLOCKED           (FCW_CWP_VSSWPLOCK0_UNLOCKED_Val << FCW_CWP_VSSWPLOCK0_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCW_CWP_VSSWPLOCK0_LOCKED             (FCW_CWP_VSSWPLOCK0_LOCKED_Val << FCW_CWP_VSSWPLOCK0_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FCW_CWP_VSSWPLOCK1_Pos                _UINT32_(21)                                         /* (FCW_CWP) Panel 1 Lock Write Protection VSSn Position */
+#define FCW_CWP_VSSWPLOCK1_Msk                (_UINT32_(0x1) << FCW_CWP_VSSWPLOCK1_Pos)            /* (FCW_CWP) Panel 1 Lock Write Protection VSSn Mask */
+#define FCW_CWP_VSSWPLOCK1(value)             (FCW_CWP_VSSWPLOCK1_Msk & (_UINT32_(value) << FCW_CWP_VSSWPLOCK1_Pos)) /* Assignment of value for VSSWPLOCK1 in the FCW_CWP register */
+#define   FCW_CWP_VSSWPLOCK1_UNLOCKED_Val     _UINT32_(0x0)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCW_CWP_VSSWPLOCK1_LOCKED_Val       _UINT32_(0x1)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FCW_CWP_VSSWPLOCK1_UNLOCKED           (FCW_CWP_VSSWPLOCK1_UNLOCKED_Val << FCW_CWP_VSSWPLOCK1_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCW_CWP_VSSWPLOCK1_LOCKED             (FCW_CWP_VSSWPLOCK1_LOCKED_Val << FCW_CWP_VSSWPLOCK1_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FCW_CWP_TWPLOCK_Pos                   _UINT32_(22)                                         /* (FCW_CWP) Panel 1 Lock Write Protection Test Position */
+#define FCW_CWP_TWPLOCK_Msk                   (_UINT32_(0x1) << FCW_CWP_TWPLOCK_Pos)               /* (FCW_CWP) Panel 1 Lock Write Protection Test Mask */
+#define FCW_CWP_TWPLOCK(value)                (FCW_CWP_TWPLOCK_Msk & (_UINT32_(value) << FCW_CWP_TWPLOCK_Pos)) /* Assignment of value for TWPLOCK in the FCW_CWP register */
+#define   FCW_CWP_TWPLOCK_UNLOCKED_Val        _UINT32_(0x0)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCW_CWP_TWPLOCK_LOCKED_Val          _UINT32_(0x1)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FCW_CWP_TWPLOCK_UNLOCKED              (FCW_CWP_TWPLOCK_UNLOCKED_Val << FCW_CWP_TWPLOCK_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCW_CWP_TWPLOCK_LOCKED                (FCW_CWP_TWPLOCK_LOCKED_Val << FCW_CWP_TWPLOCK_Pos)  /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FCW_CWP_COWPLOCK_Pos                  _UINT32_(23)                                         /* (FCW_CWP) Panel 1 Lock Write Protection CalOTP Position */
+#define FCW_CWP_COWPLOCK_Msk                  (_UINT32_(0x1) << FCW_CWP_COWPLOCK_Pos)              /* (FCW_CWP) Panel 1 Lock Write Protection CalOTP Mask */
+#define FCW_CWP_COWPLOCK(value)               (FCW_CWP_COWPLOCK_Msk & (_UINT32_(value) << FCW_CWP_COWPLOCK_Pos)) /* Assignment of value for COWPLOCK in the FCW_CWP register */
+#define   FCW_CWP_COWPLOCK_UNLOCKED_Val       _UINT32_(0x0)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FCW_CWP_COWPLOCK_LOCKED_Val         _UINT32_(0x1)                                        /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FCW_CWP_COWPLOCK_UNLOCKED             (FCW_CWP_COWPLOCK_UNLOCKED_Val << FCW_CWP_COWPLOCK_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FCW_CWP_COWPLOCK_LOCKED               (FCW_CWP_COWPLOCK_LOCKED_Val << FCW_CWP_COWPLOCK_Pos) /* (FCW_CWP) The Lock &amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FCW_CWP_Msk                           _UINT32_(0x00FD00FD)                                 /* (FCW_CWP) Register Mask  */
+
+#define FCW_CWP_VSSWP_Pos                     _UINT32_(4)                                          /* (FCW_CWP Position) Panel x Write Protect VSSn */
+#define FCW_CWP_VSSWP_Msk                     (_UINT32_(0x3) << FCW_CWP_VSSWP_Pos)                 /* (FCW_CWP Mask) VSSWP */
+#define FCW_CWP_VSSWP(value)                  (FCW_CWP_VSSWP_Msk & (_UINT32_(value) << FCW_CWP_VSSWP_Pos)) 
+#define FCW_CWP_VSSWPLOCK_Pos                 _UINT32_(20)                                         /* (FCW_CWP Position) Panel x Lock Write Protection VSSn */
+#define FCW_CWP_VSSWPLOCK_Msk                 (_UINT32_(0x3) << FCW_CWP_VSSWPLOCK_Pos)             /* (FCW_CWP Mask) VSSWPLOCK */
+#define FCW_CWP_VSSWPLOCK(value)              (FCW_CWP_VSSWPLOCK_Msk & (_UINT32_(value) << FCW_CWP_VSSWPLOCK_Pos)) 
+
+/* FCW register offsets definitions */
+#define FCW_CTRLA_REG_OFST             _UINT32_(0x00)      /* (FCW_CTRLA) Control A REGISTER Offset */
+#define FCW_CTRLOP_REG_OFST            _UINT32_(0x04)      /* (FCW_CTRLOP) Control Operation REGISTER Offset */
+#define FCW_MUTEX_REG_OFST             _UINT32_(0x08)      /* (FCW_MUTEX) MUTEX REGISTER Offset */
+#define FCW_INTENCLR_REG_OFST          _UINT32_(0x0C)      /* (FCW_INTENCLR) Interrupt Enable Clear REGISTER Offset */
+#define FCW_INTENSET_REG_OFST          _UINT32_(0x10)      /* (FCW_INTENSET) Interrupt Enable Set REGISTER Offset */
+#define FCW_INTFLAG_REG_OFST           _UINT32_(0x14)      /* (FCW_INTFLAG) Interrupt Flag REGISTER Offset */
+#define FCW_INTFLAGSET_REG_OFST        _UINT32_(0x18)      /* (FCW_INTFLAGSET) Interrupt Flag Set REGISTER Offset */
+#define FCW_STATUS_REG_OFST            _UINT32_(0x1C)      /* (FCW_STATUS) Status REGISTER Offset */
+#define FCW_KEY_REG_OFST               _UINT32_(0x20)      /* (FCW_KEY) Feature Unlock Key REGISTER Offset */
+#define FCW_ADDR_REG_OFST              _UINT32_(0x24)      /* (FCW_ADDR) Flash Destination Address REGISTER Offset */
+#define FCW_SRCADDR_REG_OFST           _UINT32_(0x28)      /* (FCW_SRCADDR) System Source Address REGISTER Offset */
+#define FCW_DATA_REG_OFST              _UINT32_(0x2C)      /* (FCW_DATA) Flash Write Data n REGISTER Offset */
+#define FCW_DATA0_REG_OFST             _UINT32_(0x2C)      /* (FCW_DATA0) Flash Write Data n REGISTER Offset */
+#define FCW_DATA1_REG_OFST             _UINT32_(0x30)      /* (FCW_DATA1) Flash Write Data n REGISTER Offset */
+#define FCW_DATA2_REG_OFST             _UINT32_(0x34)      /* (FCW_DATA2) Flash Write Data n REGISTER Offset */
+#define FCW_DATA3_REG_OFST             _UINT32_(0x38)      /* (FCW_DATA3) Flash Write Data n REGISTER Offset */
+#define FCW_SWAP_REG_OFST              _UINT32_(0x4C)      /* (FCW_SWAP) NVM Panel Swap REGISTER Offset */
+#define FCW_PWP_REG_OFST               _UINT32_(0x50)      /* (FCW_PWP) PFM Write Protect Region n REGISTER Offset */
+#define FCW_PWP0_REG_OFST              _UINT32_(0x50)      /* (FCW_PWP0) PFM Write Protect Region n REGISTER Offset */
+#define FCW_PWP1_REG_OFST              _UINT32_(0x54)      /* (FCW_PWP1) PFM Write Protect Region n REGISTER Offset */
+#define FCW_PWP2_REG_OFST              _UINT32_(0x58)      /* (FCW_PWP2) PFM Write Protect Region n REGISTER Offset */
+#define FCW_PWP3_REG_OFST              _UINT32_(0x5C)      /* (FCW_PWP3) PFM Write Protect Region n REGISTER Offset */
+#define FCW_LBWP_REG_OFST              _UINT32_(0x70)      /* (FCW_LBWP) Lower BFM Write Protect REGISTER Offset */
+#define FCW_UBWP_REG_OFST              _UINT32_(0x74)      /* (FCW_UBWP) Upper BFM Write Protect REGISTER Offset */
+#define FCW_UOWP_REG_OFST              _UINT32_(0x78)      /* (FCW_UOWP) User OTP Write protection REGISTER Offset */
+#define FCW_CWP_REG_OFST               _UINT32_(0x7C)      /* (FCW_CWP) CFM Page Write Protect REGISTER Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* FCW register API structure */
+typedef struct
+{  /* Polaris Flash Write Controller */
+  __IO  uint32_t                       FCW_CTRLA;          /* Offset: 0x00 (R/W  32) Control A REGISTER */
+  __IO  uint32_t                       FCW_CTRLOP;         /* Offset: 0x04 (R/W  32) Control Operation REGISTER */
+  __IO  uint32_t                       FCW_MUTEX;          /* Offset: 0x08 (R/W  32) MUTEX REGISTER */
+  __IO  uint32_t                       FCW_INTENCLR;       /* Offset: 0x0C (R/W  32) Interrupt Enable Clear REGISTER */
+  __IO  uint32_t                       FCW_INTENSET;       /* Offset: 0x10 (R/W  32) Interrupt Enable Set REGISTER */
+  __IO  uint32_t                       FCW_INTFLAG;        /* Offset: 0x14 (R/W  32) Interrupt Flag REGISTER */
+  __IO  uint32_t                       FCW_INTFLAGSET;     /* Offset: 0x18 (R/W  32) Interrupt Flag Set REGISTER */
+  __I   uint32_t                       FCW_STATUS;         /* Offset: 0x1C (R/   32) Status REGISTER */
+  __IO  uint32_t                       FCW_KEY;            /* Offset: 0x20 (R/W  32) Feature Unlock Key REGISTER */
+  __IO  uint32_t                       FCW_ADDR;           /* Offset: 0x24 (R/W  32) Flash Destination Address REGISTER */
+  __IO  uint32_t                       FCW_SRCADDR;        /* Offset: 0x28 (R/W  32) System Source Address REGISTER */
+  __IO  uint32_t                       FCW_DATA[4];        /* Offset: 0x2C (R/W  32) Flash Write Data n REGISTER */
+  __I   uint8_t                        Reserved1[0x10];
+  __IO  uint32_t                       FCW_SWAP;           /* Offset: 0x4C (R/W  32) NVM Panel Swap REGISTER */
+  __IO  uint32_t                       FCW_PWP[4];         /* Offset: 0x50 (R/W  32) PFM Write Protect Region n REGISTER */
+  __I   uint8_t                        Reserved2[0x10];
+  __IO  uint32_t                       FCW_LBWP;           /* Offset: 0x70 (R/W  32) Lower BFM Write Protect REGISTER */
+  __IO  uint32_t                       FCW_UBWP;           /* Offset: 0x74 (R/W  32) Upper BFM Write Protect REGISTER */
+  __IO  uint32_t                       FCW_UOWP;           /* Offset: 0x78 (R/W  32) User OTP Write protection REGISTER */
+  __IO  uint32_t                       FCW_CWP;            /* Offset: 0x7C (R/W  32) CFM Page Write Protect REGISTER */
+} fcw_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_FCW_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/freqm.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/freqm.h
new file mode 100644
index 00000000..2e385b0d
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/freqm.h
@@ -0,0 +1,246 @@
+/*
+ * Component description for FREQM
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_FREQM_COMPONENT_H_
+#define _PIC32CMGC00_FREQM_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                     SOFTWARE API DEFINITION FOR FREQM                      */
+/* ************************************************************************** */
+
+/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
+#define FREQM_CTRLA_RESETVALUE                _UINT8_(0x80)                                        /*  (FREQM_CTRLA) Control A Register  Reset Value */
+
+#define FREQM_CTRLA_SWRST_Pos                 _UINT8_(0)                                           /* (FREQM_CTRLA) Software Reset Position */
+#define FREQM_CTRLA_SWRST_Msk                 (_UINT8_(0x1) << FREQM_CTRLA_SWRST_Pos)              /* (FREQM_CTRLA) Software Reset Mask */
+#define FREQM_CTRLA_SWRST(value)              (FREQM_CTRLA_SWRST_Msk & (_UINT8_(value) << FREQM_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the FREQM_CTRLA register */
+#define FREQM_CTRLA_ENABLE_Pos                _UINT8_(1)                                           /* (FREQM_CTRLA) Enable Position */
+#define FREQM_CTRLA_ENABLE_Msk                (_UINT8_(0x1) << FREQM_CTRLA_ENABLE_Pos)             /* (FREQM_CTRLA) Enable Mask */
+#define FREQM_CTRLA_ENABLE(value)             (FREQM_CTRLA_ENABLE_Msk & (_UINT8_(value) << FREQM_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the FREQM_CTRLA register */
+#define FREQM_CTRLA_FREERUN_Pos               _UINT8_(2)                                           /* (FREQM_CTRLA) Free Running Mode Position */
+#define FREQM_CTRLA_FREERUN_Msk               (_UINT8_(0x1) << FREQM_CTRLA_FREERUN_Pos)            /* (FREQM_CTRLA) Free Running Mode Mask */
+#define FREQM_CTRLA_FREERUN(value)            (FREQM_CTRLA_FREERUN_Msk & (_UINT8_(value) << FREQM_CTRLA_FREERUN_Pos)) /* Assignment of value for FREERUN in the FREQM_CTRLA register */
+#define FREQM_CTRLA_RUNSTDBY_Pos              _UINT8_(6)                                           /* (FREQM_CTRLA) Run In Standby Position */
+#define FREQM_CTRLA_RUNSTDBY_Msk              (_UINT8_(0x1) << FREQM_CTRLA_RUNSTDBY_Pos)           /* (FREQM_CTRLA) Run In Standby Mask */
+#define FREQM_CTRLA_RUNSTDBY(value)           (FREQM_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << FREQM_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the FREQM_CTRLA register */
+#define FREQM_CTRLA_ONDEMAND_Pos              _UINT8_(7)                                           /* (FREQM_CTRLA) On Demand Control Position */
+#define FREQM_CTRLA_ONDEMAND_Msk              (_UINT8_(0x1) << FREQM_CTRLA_ONDEMAND_Pos)           /* (FREQM_CTRLA) On Demand Control Mask */
+#define FREQM_CTRLA_ONDEMAND(value)           (FREQM_CTRLA_ONDEMAND_Msk & (_UINT8_(value) << FREQM_CTRLA_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the FREQM_CTRLA register */
+#define FREQM_CTRLA_Msk                       _UINT8_(0xC7)                                        /* (FREQM_CTRLA) Register Mask  */
+
+
+/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
+#define FREQM_CTRLB_RESETVALUE                _UINT8_(0x00)                                        /*  (FREQM_CTRLB) Control B Register  Reset Value */
+
+#define FREQM_CTRLB_START_Pos                 _UINT8_(0)                                           /* (FREQM_CTRLB) Start Measurement Position */
+#define FREQM_CTRLB_START_Msk                 (_UINT8_(0x1) << FREQM_CTRLB_START_Pos)              /* (FREQM_CTRLB) Start Measurement Mask */
+#define FREQM_CTRLB_START(value)              (FREQM_CTRLB_START_Msk & (_UINT8_(value) << FREQM_CTRLB_START_Pos)) /* Assignment of value for START in the FREQM_CTRLB register */
+#define FREQM_CTRLB_Msk                       _UINT8_(0x01)                                        /* (FREQM_CTRLB) Register Mask  */
+
+
+/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A Register -------- */
+#define FREQM_CFGA_RESETVALUE                 _UINT16_(0x00)                                       /*  (FREQM_CFGA) Config A Register  Reset Value */
+
+#define FREQM_CFGA_REFNUM_Pos                 _UINT16_(0)                                          /* (FREQM_CFGA) Number of Reference Clock Cycles Position */
+#define FREQM_CFGA_REFNUM_Msk                 (_UINT16_(0xFF) << FREQM_CFGA_REFNUM_Pos)            /* (FREQM_CFGA) Number of Reference Clock Cycles Mask */
+#define FREQM_CFGA_REFNUM(value)              (FREQM_CFGA_REFNUM_Msk & (_UINT16_(value) << FREQM_CFGA_REFNUM_Pos)) /* Assignment of value for REFNUM in the FREQM_CFGA register */
+#define FREQM_CFGA_MSRSEL_Pos                 _UINT16_(8)                                          /* (FREQM_CFGA) Measurement Clock Selection Position */
+#define FREQM_CFGA_MSRSEL_Msk                 (_UINT16_(0x7) << FREQM_CFGA_MSRSEL_Pos)             /* (FREQM_CFGA) Measurement Clock Selection Mask */
+#define FREQM_CFGA_MSRSEL(value)              (FREQM_CFGA_MSRSEL_Msk & (_UINT16_(value) << FREQM_CFGA_MSRSEL_Pos)) /* Assignment of value for MSRSEL in the FREQM_CFGA register */
+#define   FREQM_CFGA_MSRSEL_GCLK_Val          _UINT16_(0x0)                                        /* (FREQM_CFGA) GCLK Input Clock  */
+#define   FREQM_CFGA_MSRSEL_CPU_Val           _UINT16_(0x1)                                        /* (FREQM_CFGA) CPU Input Clock  */
+#define FREQM_CFGA_MSRSEL_GCLK                (FREQM_CFGA_MSRSEL_GCLK_Val << FREQM_CFGA_MSRSEL_Pos) /* (FREQM_CFGA) GCLK Input Clock Position */
+#define FREQM_CFGA_MSRSEL_CPU                 (FREQM_CFGA_MSRSEL_CPU_Val << FREQM_CFGA_MSRSEL_Pos) /* (FREQM_CFGA) CPU Input Clock Position */
+#define FREQM_CFGA_DIVREF_Pos                 _UINT16_(15)                                         /* (FREQM_CFGA) Divide Reference Clock Position */
+#define FREQM_CFGA_DIVREF_Msk                 (_UINT16_(0x1) << FREQM_CFGA_DIVREF_Pos)             /* (FREQM_CFGA) Divide Reference Clock Mask */
+#define FREQM_CFGA_DIVREF(value)              (FREQM_CFGA_DIVREF_Msk & (_UINT16_(value) << FREQM_CFGA_DIVREF_Pos)) /* Assignment of value for DIVREF in the FREQM_CFGA register */
+#define   FREQM_CFGA_DIVREF_DIV1_Val          _UINT16_(0x0)                                        /* (FREQM_CFGA) The reference clock is divided by 1  */
+#define   FREQM_CFGA_DIVREF_DIV8_Val          _UINT16_(0x1)                                        /* (FREQM_CFGA) The reference clock is divided by 8  */
+#define FREQM_CFGA_DIVREF_DIV1                (FREQM_CFGA_DIVREF_DIV1_Val << FREQM_CFGA_DIVREF_Pos) /* (FREQM_CFGA) The reference clock is divided by 1 Position */
+#define FREQM_CFGA_DIVREF_DIV8                (FREQM_CFGA_DIVREF_DIV8_Val << FREQM_CFGA_DIVREF_Pos) /* (FREQM_CFGA) The reference clock is divided by 8 Position */
+#define FREQM_CFGA_Msk                        _UINT16_(0x87FF)                                     /* (FREQM_CFGA) Register Mask  */
+
+
+/* -------- FREQM_CTRLC : (FREQM Offset: 0x04) (R/W 8) Control C Register -------- */
+#define FREQM_CTRLC_RESETVALUE                _UINT8_(0x00)                                        /*  (FREQM_CTRLC) Control C Register  Reset Value */
+
+#define FREQM_CTRLC_WINMODE_Pos               _UINT8_(0)                                           /* (FREQM_CTRLC) Window Monitor Mode Position */
+#define FREQM_CTRLC_WINMODE_Msk               (_UINT8_(0x7) << FREQM_CTRLC_WINMODE_Pos)            /* (FREQM_CTRLC) Window Monitor Mode Mask */
+#define FREQM_CTRLC_WINMODE(value)            (FREQM_CTRLC_WINMODE_Msk & (_UINT8_(value) << FREQM_CTRLC_WINMODE_Pos)) /* Assignment of value for WINMODE in the FREQM_CTRLC register */
+#define   FREQM_CTRLC_WINMODE_DISABLE_Val     _UINT8_(0x0)                                         /* (FREQM_CTRLC) No window mode (default)  */
+#define   FREQM_CTRLC_WINMODE_MODE1_Val       _UINT8_(0x1)                                         /* (FREQM_CTRLC) VALUE > WINLT  */
+#define   FREQM_CTRLC_WINMODE_MODE2_Val       _UINT8_(0x2)                                         /* (FREQM_CTRLC) VALUE < WINUT  */
+#define   FREQM_CTRLC_WINMODE_MODE3_Val       _UINT8_(0x3)                                         /* (FREQM_CTRLC) WINLT < VALUE < WINUT  */
+#define   FREQM_CTRLC_WINMODE_MODE4_Val       _UINT8_(0x4)                                         /* (FREQM_CTRLC) !(WINLT < VALUE < WINUT)  */
+#define FREQM_CTRLC_WINMODE_DISABLE           (FREQM_CTRLC_WINMODE_DISABLE_Val << FREQM_CTRLC_WINMODE_Pos) /* (FREQM_CTRLC) No window mode (default) Position */
+#define FREQM_CTRLC_WINMODE_MODE1             (FREQM_CTRLC_WINMODE_MODE1_Val << FREQM_CTRLC_WINMODE_Pos) /* (FREQM_CTRLC) VALUE > WINLT Position */
+#define FREQM_CTRLC_WINMODE_MODE2             (FREQM_CTRLC_WINMODE_MODE2_Val << FREQM_CTRLC_WINMODE_Pos) /* (FREQM_CTRLC) VALUE < WINUT Position */
+#define FREQM_CTRLC_WINMODE_MODE3             (FREQM_CTRLC_WINMODE_MODE3_Val << FREQM_CTRLC_WINMODE_Pos) /* (FREQM_CTRLC) WINLT < VALUE < WINUT Position */
+#define FREQM_CTRLC_WINMODE_MODE4             (FREQM_CTRLC_WINMODE_MODE4_Val << FREQM_CTRLC_WINMODE_Pos) /* (FREQM_CTRLC) !(WINLT < VALUE < WINUT) Position */
+#define FREQM_CTRLC_Msk                       _UINT8_(0x07)                                        /* (FREQM_CTRLC) Register Mask  */
+
+
+/* -------- FREQM_EVCTRL : (FREQM Offset: 0x06) (R/W 8) Event Control Register -------- */
+#define FREQM_EVCTRL_RESETVALUE               _UINT8_(0x00)                                        /*  (FREQM_EVCTRL) Event Control Register  Reset Value */
+
+#define FREQM_EVCTRL_STARTEI_Pos              _UINT8_(0)                                           /* (FREQM_EVCTRL) Start Measurement Event Input Enable Position */
+#define FREQM_EVCTRL_STARTEI_Msk              (_UINT8_(0x1) << FREQM_EVCTRL_STARTEI_Pos)           /* (FREQM_EVCTRL) Start Measurement Event Input Enable Mask */
+#define FREQM_EVCTRL_STARTEI(value)           (FREQM_EVCTRL_STARTEI_Msk & (_UINT8_(value) << FREQM_EVCTRL_STARTEI_Pos)) /* Assignment of value for STARTEI in the FREQM_EVCTRL register */
+#define FREQM_EVCTRL_STARTINV_Pos             _UINT8_(1)                                           /* (FREQM_EVCTRL) Start Measurement Event Invert Enable Position */
+#define FREQM_EVCTRL_STARTINV_Msk             (_UINT8_(0x1) << FREQM_EVCTRL_STARTINV_Pos)          /* (FREQM_EVCTRL) Start Measurement Event Invert Enable Mask */
+#define FREQM_EVCTRL_STARTINV(value)          (FREQM_EVCTRL_STARTINV_Msk & (_UINT8_(value) << FREQM_EVCTRL_STARTINV_Pos)) /* Assignment of value for STARTINV in the FREQM_EVCTRL register */
+#define FREQM_EVCTRL_DONEEO_Pos               _UINT8_(4)                                           /* (FREQM_EVCTRL) Measurement Done Event Out Position */
+#define FREQM_EVCTRL_DONEEO_Msk               (_UINT8_(0x1) << FREQM_EVCTRL_DONEEO_Pos)            /* (FREQM_EVCTRL) Measurement Done Event Out Mask */
+#define FREQM_EVCTRL_DONEEO(value)            (FREQM_EVCTRL_DONEEO_Msk & (_UINT8_(value) << FREQM_EVCTRL_DONEEO_Pos)) /* Assignment of value for DONEEO in the FREQM_EVCTRL register */
+#define FREQM_EVCTRL_WINMONEO_Pos             _UINT8_(5)                                           /* (FREQM_EVCTRL) Window Monitor Event Out Position */
+#define FREQM_EVCTRL_WINMONEO_Msk             (_UINT8_(0x1) << FREQM_EVCTRL_WINMONEO_Pos)          /* (FREQM_EVCTRL) Window Monitor Event Out Mask */
+#define FREQM_EVCTRL_WINMONEO(value)          (FREQM_EVCTRL_WINMONEO_Msk & (_UINT8_(value) << FREQM_EVCTRL_WINMONEO_Pos)) /* Assignment of value for WINMONEO in the FREQM_EVCTRL register */
+#define FREQM_EVCTRL_Msk                      _UINT8_(0x33)                                        /* (FREQM_EVCTRL) Register Mask  */
+
+
+/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
+#define FREQM_INTENCLR_RESETVALUE             _UINT8_(0x00)                                        /*  (FREQM_INTENCLR) Interrupt Enable Clear Register  Reset Value */
+
+#define FREQM_INTENCLR_DONE_Pos               _UINT8_(0)                                           /* (FREQM_INTENCLR) Measurement Done Interrupt Disable Position */
+#define FREQM_INTENCLR_DONE_Msk               (_UINT8_(0x1) << FREQM_INTENCLR_DONE_Pos)            /* (FREQM_INTENCLR) Measurement Done Interrupt Disable Mask */
+#define FREQM_INTENCLR_DONE(value)            (FREQM_INTENCLR_DONE_Msk & (_UINT8_(value) << FREQM_INTENCLR_DONE_Pos)) /* Assignment of value for DONE in the FREQM_INTENCLR register */
+#define FREQM_INTENCLR_WINMON_Pos             _UINT8_(1)                                           /* (FREQM_INTENCLR) Window Monitor Interrupt Disable Position */
+#define FREQM_INTENCLR_WINMON_Msk             (_UINT8_(0x1) << FREQM_INTENCLR_WINMON_Pos)          /* (FREQM_INTENCLR) Window Monitor Interrupt Disable Mask */
+#define FREQM_INTENCLR_WINMON(value)          (FREQM_INTENCLR_WINMON_Msk & (_UINT8_(value) << FREQM_INTENCLR_WINMON_Pos)) /* Assignment of value for WINMON in the FREQM_INTENCLR register */
+#define FREQM_INTENCLR_Msk                    _UINT8_(0x03)                                        /* (FREQM_INTENCLR) Register Mask  */
+
+
+/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
+#define FREQM_INTENSET_RESETVALUE             _UINT8_(0x00)                                        /*  (FREQM_INTENSET) Interrupt Enable Set Register  Reset Value */
+
+#define FREQM_INTENSET_DONE_Pos               _UINT8_(0)                                           /* (FREQM_INTENSET) Measurement Done Interrupt Enable Position */
+#define FREQM_INTENSET_DONE_Msk               (_UINT8_(0x1) << FREQM_INTENSET_DONE_Pos)            /* (FREQM_INTENSET) Measurement Done Interrupt Enable Mask */
+#define FREQM_INTENSET_DONE(value)            (FREQM_INTENSET_DONE_Msk & (_UINT8_(value) << FREQM_INTENSET_DONE_Pos)) /* Assignment of value for DONE in the FREQM_INTENSET register */
+#define FREQM_INTENSET_WINMON_Pos             _UINT8_(1)                                           /* (FREQM_INTENSET) Window Monitor Interrupt Enable Position */
+#define FREQM_INTENSET_WINMON_Msk             (_UINT8_(0x1) << FREQM_INTENSET_WINMON_Pos)          /* (FREQM_INTENSET) Window Monitor Interrupt Enable Mask */
+#define FREQM_INTENSET_WINMON(value)          (FREQM_INTENSET_WINMON_Msk & (_UINT8_(value) << FREQM_INTENSET_WINMON_Pos)) /* Assignment of value for WINMON in the FREQM_INTENSET register */
+#define FREQM_INTENSET_Msk                    _UINT8_(0x03)                                        /* (FREQM_INTENSET) Register Mask  */
+
+
+/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
+#define FREQM_INTFLAG_RESETVALUE              _UINT8_(0x00)                                        /*  (FREQM_INTFLAG) Interrupt Flag Register  Reset Value */
+
+#define FREQM_INTFLAG_DONE_Pos                _UINT8_(0)                                           /* (FREQM_INTFLAG) Measurement Done Position */
+#define FREQM_INTFLAG_DONE_Msk                (_UINT8_(0x1) << FREQM_INTFLAG_DONE_Pos)             /* (FREQM_INTFLAG) Measurement Done Mask */
+#define FREQM_INTFLAG_DONE(value)             (FREQM_INTFLAG_DONE_Msk & (_UINT8_(value) << FREQM_INTFLAG_DONE_Pos)) /* Assignment of value for DONE in the FREQM_INTFLAG register */
+#define FREQM_INTFLAG_WINMON_Pos              _UINT8_(1)                                           /* (FREQM_INTFLAG) Window Monitor Position */
+#define FREQM_INTFLAG_WINMON_Msk              (_UINT8_(0x1) << FREQM_INTFLAG_WINMON_Pos)           /* (FREQM_INTFLAG) Window Monitor Mask */
+#define FREQM_INTFLAG_WINMON(value)           (FREQM_INTFLAG_WINMON_Msk & (_UINT8_(value) << FREQM_INTFLAG_WINMON_Pos)) /* Assignment of value for WINMON in the FREQM_INTFLAG register */
+#define FREQM_INTFLAG_Msk                     _UINT8_(0x03)                                        /* (FREQM_INTFLAG) Register Mask  */
+
+
+/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
+#define FREQM_STATUS_RESETVALUE               _UINT8_(0x00)                                        /*  (FREQM_STATUS) Status Register  Reset Value */
+
+#define FREQM_STATUS_BUSY_Pos                 _UINT8_(0)                                           /* (FREQM_STATUS) FREQM Status Position */
+#define FREQM_STATUS_BUSY_Msk                 (_UINT8_(0x1) << FREQM_STATUS_BUSY_Pos)              /* (FREQM_STATUS) FREQM Status Mask */
+#define FREQM_STATUS_BUSY(value)              (FREQM_STATUS_BUSY_Msk & (_UINT8_(value) << FREQM_STATUS_BUSY_Pos)) /* Assignment of value for BUSY in the FREQM_STATUS register */
+#define FREQM_STATUS_OVF_Pos                  _UINT8_(1)                                           /* (FREQM_STATUS) Sticky Count Value Overflow Position */
+#define FREQM_STATUS_OVF_Msk                  (_UINT8_(0x1) << FREQM_STATUS_OVF_Pos)               /* (FREQM_STATUS) Sticky Count Value Overflow Mask */
+#define FREQM_STATUS_OVF(value)               (FREQM_STATUS_OVF_Msk & (_UINT8_(value) << FREQM_STATUS_OVF_Pos)) /* Assignment of value for OVF in the FREQM_STATUS register */
+#define FREQM_STATUS_Msk                      _UINT8_(0x03)                                        /* (FREQM_STATUS) Register Mask  */
+
+
+/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) ( R/ 32) Synchronization Busy Register -------- */
+#define FREQM_SYNCBUSY_RESETVALUE             _UINT32_(0x00)                                       /*  (FREQM_SYNCBUSY) Synchronization Busy Register  Reset Value */
+
+#define FREQM_SYNCBUSY_SWRST_Pos              _UINT32_(0)                                          /* (FREQM_SYNCBUSY) Software Reset Position */
+#define FREQM_SYNCBUSY_SWRST_Msk              (_UINT32_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)          /* (FREQM_SYNCBUSY) Software Reset Mask */
+#define FREQM_SYNCBUSY_SWRST(value)           (FREQM_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << FREQM_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the FREQM_SYNCBUSY register */
+#define FREQM_SYNCBUSY_ENABLE_Pos             _UINT32_(1)                                          /* (FREQM_SYNCBUSY) Enable Position */
+#define FREQM_SYNCBUSY_ENABLE_Msk             (_UINT32_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)         /* (FREQM_SYNCBUSY) Enable Mask */
+#define FREQM_SYNCBUSY_ENABLE(value)          (FREQM_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << FREQM_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the FREQM_SYNCBUSY register */
+#define FREQM_SYNCBUSY_Msk                    _UINT32_(0x00000003)                                 /* (FREQM_SYNCBUSY) Register Mask  */
+
+
+/* -------- FREQM_VALUE : (FREQM Offset: 0x10) ( R/ 32) Count Value Register -------- */
+#define FREQM_VALUE_RESETVALUE                _UINT32_(0x00)                                       /*  (FREQM_VALUE) Count Value Register  Reset Value */
+
+#define FREQM_VALUE_VALUE_Pos                 _UINT32_(0)                                          /* (FREQM_VALUE) Measurement Value Position */
+#define FREQM_VALUE_VALUE_Msk                 (_UINT32_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)        /* (FREQM_VALUE) Measurement Value Mask */
+#define FREQM_VALUE_VALUE(value)              (FREQM_VALUE_VALUE_Msk & (_UINT32_(value) << FREQM_VALUE_VALUE_Pos)) /* Assignment of value for VALUE in the FREQM_VALUE register */
+#define FREQM_VALUE_Msk                       _UINT32_(0x00FFFFFF)                                 /* (FREQM_VALUE) Register Mask  */
+
+
+/* -------- FREQM_WINLT : (FREQM Offset: 0x20) (R/W 32) Window Monitor Lower Threshold -------- */
+#define FREQM_WINLT_RESETVALUE                _UINT32_(0x00)                                       /*  (FREQM_WINLT) Window Monitor Lower Threshold  Reset Value */
+
+#define FREQM_WINLT_WINLT_Pos                 _UINT32_(0)                                          /* (FREQM_WINLT) Window Lower Threshold Position */
+#define FREQM_WINLT_WINLT_Msk                 (_UINT32_(0xFFFFFF) << FREQM_WINLT_WINLT_Pos)        /* (FREQM_WINLT) Window Lower Threshold Mask */
+#define FREQM_WINLT_WINLT(value)              (FREQM_WINLT_WINLT_Msk & (_UINT32_(value) << FREQM_WINLT_WINLT_Pos)) /* Assignment of value for WINLT in the FREQM_WINLT register */
+#define FREQM_WINLT_Msk                       _UINT32_(0x00FFFFFF)                                 /* (FREQM_WINLT) Register Mask  */
+
+
+/* -------- FREQM_WINUT : (FREQM Offset: 0x24) (R/W 32) Window Monitor Upper Threshold -------- */
+#define FREQM_WINUT_RESETVALUE                _UINT32_(0x00)                                       /*  (FREQM_WINUT) Window Monitor Upper Threshold  Reset Value */
+
+#define FREQM_WINUT_WINUT_Pos                 _UINT32_(0)                                          /* (FREQM_WINUT) Window Upper Threshold Position */
+#define FREQM_WINUT_WINUT_Msk                 (_UINT32_(0xFFFFFF) << FREQM_WINUT_WINUT_Pos)        /* (FREQM_WINUT) Window Upper Threshold Mask */
+#define FREQM_WINUT_WINUT(value)              (FREQM_WINUT_WINUT_Msk & (_UINT32_(value) << FREQM_WINUT_WINUT_Pos)) /* Assignment of value for WINUT in the FREQM_WINUT register */
+#define FREQM_WINUT_Msk                       _UINT32_(0x00FFFFFF)                                 /* (FREQM_WINUT) Register Mask  */
+
+
+/* FREQM register offsets definitions */
+#define FREQM_CTRLA_REG_OFST           _UINT32_(0x00)      /* (FREQM_CTRLA) Control A Register Offset */
+#define FREQM_CTRLB_REG_OFST           _UINT32_(0x01)      /* (FREQM_CTRLB) Control B Register Offset */
+#define FREQM_CFGA_REG_OFST            _UINT32_(0x02)      /* (FREQM_CFGA) Config A Register Offset */
+#define FREQM_CTRLC_REG_OFST           _UINT32_(0x04)      /* (FREQM_CTRLC) Control C Register Offset */
+#define FREQM_EVCTRL_REG_OFST          _UINT32_(0x06)      /* (FREQM_EVCTRL) Event Control Register Offset */
+#define FREQM_INTENCLR_REG_OFST        _UINT32_(0x08)      /* (FREQM_INTENCLR) Interrupt Enable Clear Register Offset */
+#define FREQM_INTENSET_REG_OFST        _UINT32_(0x09)      /* (FREQM_INTENSET) Interrupt Enable Set Register Offset */
+#define FREQM_INTFLAG_REG_OFST         _UINT32_(0x0A)      /* (FREQM_INTFLAG) Interrupt Flag Register Offset */
+#define FREQM_STATUS_REG_OFST          _UINT32_(0x0B)      /* (FREQM_STATUS) Status Register Offset */
+#define FREQM_SYNCBUSY_REG_OFST        _UINT32_(0x0C)      /* (FREQM_SYNCBUSY) Synchronization Busy Register Offset */
+#define FREQM_VALUE_REG_OFST           _UINT32_(0x10)      /* (FREQM_VALUE) Count Value Register Offset */
+#define FREQM_WINLT_REG_OFST           _UINT32_(0x20)      /* (FREQM_WINLT) Window Monitor Lower Threshold Offset */
+#define FREQM_WINUT_REG_OFST           _UINT32_(0x24)      /* (FREQM_WINUT) Window Monitor Upper Threshold Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* FREQM register API structure */
+typedef struct
+{  /* Frequency Meter */
+  __IO  uint8_t                        FREQM_CTRLA;        /* Offset: 0x00 (R/W  8) Control A Register */
+  __O   uint8_t                        FREQM_CTRLB;        /* Offset: 0x01 ( /W  8) Control B Register */
+  __IO  uint16_t                       FREQM_CFGA;         /* Offset: 0x02 (R/W  16) Config A Register */
+  __IO  uint8_t                        FREQM_CTRLC;        /* Offset: 0x04 (R/W  8) Control C Register */
+  __I   uint8_t                        Reserved1[0x01];
+  __IO  uint8_t                        FREQM_EVCTRL;       /* Offset: 0x06 (R/W  8) Event Control Register */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        FREQM_INTENCLR;     /* Offset: 0x08 (R/W  8) Interrupt Enable Clear Register */
+  __IO  uint8_t                        FREQM_INTENSET;     /* Offset: 0x09 (R/W  8) Interrupt Enable Set Register */
+  __IO  uint8_t                        FREQM_INTFLAG;      /* Offset: 0x0A (R/W  8) Interrupt Flag Register */
+  __IO  uint8_t                        FREQM_STATUS;       /* Offset: 0x0B (R/W  8) Status Register */
+  __I   uint32_t                       FREQM_SYNCBUSY;     /* Offset: 0x0C (R/   32) Synchronization Busy Register */
+  __I   uint32_t                       FREQM_VALUE;        /* Offset: 0x10 (R/   32) Count Value Register */
+  __I   uint8_t                        Reserved3[0x0C];
+  __IO  uint32_t                       FREQM_WINLT;        /* Offset: 0x20 (R/W  32) Window Monitor Lower Threshold */
+  __IO  uint32_t                       FREQM_WINUT;        /* Offset: 0x24 (R/W  32) Window Monitor Upper Threshold */
+} freqm_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_FREQM_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/fuses.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/fuses.h
new file mode 100644
index 00000000..b261c4d2
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/fuses.h
@@ -0,0 +1,3212 @@
+/*
+ * Component description for FUSES
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_FUSES_COMPONENT_H_
+#define _PIC32CMGC00_FUSES_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                     SOFTWARE API DEFINITION FOR FUSES                      */
+/* ************************************************************************** */
+
+/* -------- FUSES_DAL : (FUSES Offset: 0x00) (R/W 32) DEVICE ACCESS LEVEL Register -------- */
+#define FUSES_DAL_DAL_CPU_Pos                 _UINT32_(0)                                          /* (FUSES_DAL) CPU Device Access Level Position */
+#define FUSES_DAL_DAL_CPU_Msk                 (_UINT32_(0xFFFFFFFF) << FUSES_DAL_DAL_CPU_Pos)      /* (FUSES_DAL) CPU Device Access Level Mask */
+#define FUSES_DAL_DAL_CPU(value)              (FUSES_DAL_DAL_CPU_Msk & (_UINT32_(value) << FUSES_DAL_DAL_CPU_Pos)) /* Assignment of value for DAL_CPU in the FUSES_DAL register */
+#define FUSES_DAL_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (FUSES_DAL) Register Mask  */
+
+
+/* -------- FUSES_FRCFGBROM : (FUSES Offset: 0x400) (R/W 32) PRE-BOOT bromc user Options Register -------- */
+#define FUSES_FRCFGBROM_BCRCDIS_Pos           _UINT32_(0)                                          /* (FUSES_FRCFGBROM) Boot ROM CRC Disable Position */
+#define FUSES_FRCFGBROM_BCRCDIS_Msk           (_UINT32_(0x1) << FUSES_FRCFGBROM_BCRCDIS_Pos)       /* (FUSES_FRCFGBROM) Boot ROM CRC Disable Mask */
+#define FUSES_FRCFGBROM_BCRCDIS(value)        (FUSES_FRCFGBROM_BCRCDIS_Msk & (_UINT32_(value) << FUSES_FRCFGBROM_BCRCDIS_Pos)) /* Assignment of value for BCRCDIS in the FUSES_FRCFGBROM register */
+#define FUSES_FRCFGBROM_Msk                   _UINT32_(0x00000001)                                 /* (FUSES_FRCFGBROM) Register Mask  */
+
+
+/* -------- FUSES_FRCFGMBIST : (FUSES Offset: 0x408) (R/W 32) PRE-BOOT MBIST user Options Register -------- */
+#define FUSES_FRCFGMBIST_MOBH_Pos             _UINT32_(2)                                          /* (FUSES_FRCFGMBIST) MBIST On Boot Enable for HIBERNATE Only Retaining Memory Groups Position */
+#define FUSES_FRCFGMBIST_MOBH_Msk             (_UINT32_(0x3) << FUSES_FRCFGMBIST_MOBH_Pos)         /* (FUSES_FRCFGMBIST) MBIST On Boot Enable for HIBERNATE Only Retaining Memory Groups Mask */
+#define FUSES_FRCFGMBIST_MOBH(value)          (FUSES_FRCFGMBIST_MOBH_Msk & (_UINT32_(value) << FUSES_FRCFGMBIST_MOBH_Pos)) /* Assignment of value for MOBH in the FUSES_FRCFGMBIST register */
+#define   FUSES_FRCFGMBIST_MOBH_ENABLED_ANY_Val _UINT32_(0x1)                                        /* (FUSES_FRCFGMBIST) MOB runs after any non-BACKUP/HIBERNATE exit reset  */
+#define   FUSES_FRCFGMBIST_MOBH_ENABLED_POR_Val _UINT32_(0x2)                                        /* (FUSES_FRCFGMBIST) MOB runs only after a POR  */
+#define   FUSES_FRCFGMBIST_MOBH_DISABLED_Val  _UINT32_(0x3)                                        /* (FUSES_FRCFGMBIST) MOB Disabled  */
+#define FUSES_FRCFGMBIST_MOBH_ENABLED_ANY     (FUSES_FRCFGMBIST_MOBH_ENABLED_ANY_Val << FUSES_FRCFGMBIST_MOBH_Pos) /* (FUSES_FRCFGMBIST) MOB runs after any non-BACKUP/HIBERNATE exit reset Position */
+#define FUSES_FRCFGMBIST_MOBH_ENABLED_POR     (FUSES_FRCFGMBIST_MOBH_ENABLED_POR_Val << FUSES_FRCFGMBIST_MOBH_Pos) /* (FUSES_FRCFGMBIST) MOB runs only after a POR Position */
+#define FUSES_FRCFGMBIST_MOBH_DISABLED        (FUSES_FRCFGMBIST_MOBH_DISABLED_Val << FUSES_FRCFGMBIST_MOBH_Pos) /* (FUSES_FRCFGMBIST) MOB Disabled Position */
+#define FUSES_FRCFGMBIST_MOBB_Pos             _UINT32_(4)                                          /* (FUSES_FRCFGMBIST) MBIST On Boot Enable for BACKUP/HIBERNATE Retaining Memory Groups Position */
+#define FUSES_FRCFGMBIST_MOBB_Msk             (_UINT32_(0x3) << FUSES_FRCFGMBIST_MOBB_Pos)         /* (FUSES_FRCFGMBIST) MBIST On Boot Enable for BACKUP/HIBERNATE Retaining Memory Groups Mask */
+#define FUSES_FRCFGMBIST_MOBB(value)          (FUSES_FRCFGMBIST_MOBB_Msk & (_UINT32_(value) << FUSES_FRCFGMBIST_MOBB_Pos)) /* Assignment of value for MOBB in the FUSES_FRCFGMBIST register */
+#define   FUSES_FRCFGMBIST_MOBB_ENABLED_ANY_Val _UINT32_(0x1)                                        /* (FUSES_FRCFGMBIST) MOB runs after any non-BACKUP/HIBERNATE exit reset  */
+#define   FUSES_FRCFGMBIST_MOBB_ENABLED_POR_Val _UINT32_(0x2)                                        /* (FUSES_FRCFGMBIST) MOB runs only after a POR  */
+#define   FUSES_FRCFGMBIST_MOBB_DISABLED_Val  _UINT32_(0x3)                                        /* (FUSES_FRCFGMBIST) MOB Disabled  */
+#define FUSES_FRCFGMBIST_MOBB_ENABLED_ANY     (FUSES_FRCFGMBIST_MOBB_ENABLED_ANY_Val << FUSES_FRCFGMBIST_MOBB_Pos) /* (FUSES_FRCFGMBIST) MOB runs after any non-BACKUP/HIBERNATE exit reset Position */
+#define FUSES_FRCFGMBIST_MOBB_ENABLED_POR     (FUSES_FRCFGMBIST_MOBB_ENABLED_POR_Val << FUSES_FRCFGMBIST_MOBB_Pos) /* (FUSES_FRCFGMBIST) MOB runs only after a POR Position */
+#define FUSES_FRCFGMBIST_MOBB_DISABLED        (FUSES_FRCFGMBIST_MOBB_DISABLED_Val << FUSES_FRCFGMBIST_MOBB_Pos) /* (FUSES_FRCFGMBIST) MOB Disabled Position */
+#define FUSES_FRCFGMBIST_Msk                  _UINT32_(0x0000003C)                                 /* (FUSES_FRCFGMBIST) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_INTCHK0 : (FUSES Offset: 0x420) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_INTCHK0_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_INTCHK0) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_INTCHK0_KEYVAL_INTCHK0_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_INTCHK0)  Position */
+#define FUSES_KEYVAL_INTCHK0_KEYVAL_INTCHK0_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_INTCHK0_KEYVAL_INTCHK0_Pos) /* (FUSES_KEYVAL_INTCHK0)  Mask */
+#define FUSES_KEYVAL_INTCHK0_KEYVAL_INTCHK0(value) (FUSES_KEYVAL_INTCHK0_KEYVAL_INTCHK0_Msk & (_UINT32_(value) << FUSES_KEYVAL_INTCHK0_KEYVAL_INTCHK0_Pos)) /* Assignment of value for KEYVAL_INTCHK0 in the FUSES_KEYVAL_INTCHK0 register */
+#define FUSES_KEYVAL_INTCHK0_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_INTCHK0) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_INTCHK1 : (FUSES Offset: 0x424) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_INTCHK1_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_INTCHK1) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_INTCHK1_KEYVAL_INTCHK1_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_INTCHK1)  Position */
+#define FUSES_KEYVAL_INTCHK1_KEYVAL_INTCHK1_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_INTCHK1_KEYVAL_INTCHK1_Pos) /* (FUSES_KEYVAL_INTCHK1)  Mask */
+#define FUSES_KEYVAL_INTCHK1_KEYVAL_INTCHK1(value) (FUSES_KEYVAL_INTCHK1_KEYVAL_INTCHK1_Msk & (_UINT32_(value) << FUSES_KEYVAL_INTCHK1_KEYVAL_INTCHK1_Pos)) /* Assignment of value for KEYVAL_INTCHK1 in the FUSES_KEYVAL_INTCHK1 register */
+#define FUSES_KEYVAL_INTCHK1_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_INTCHK1) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_INTCHK2 : (FUSES Offset: 0x428) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_INTCHK2_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_INTCHK2) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_INTCHK2_KEYVAL_INTCHK2_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_INTCHK2)  Position */
+#define FUSES_KEYVAL_INTCHK2_KEYVAL_INTCHK2_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_INTCHK2_KEYVAL_INTCHK2_Pos) /* (FUSES_KEYVAL_INTCHK2)  Mask */
+#define FUSES_KEYVAL_INTCHK2_KEYVAL_INTCHK2(value) (FUSES_KEYVAL_INTCHK2_KEYVAL_INTCHK2_Msk & (_UINT32_(value) << FUSES_KEYVAL_INTCHK2_KEYVAL_INTCHK2_Pos)) /* Assignment of value for KEYVAL_INTCHK2 in the FUSES_KEYVAL_INTCHK2 register */
+#define FUSES_KEYVAL_INTCHK2_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_INTCHK2) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_INTCHK3 : (FUSES Offset: 0x42C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_INTCHK3_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_INTCHK3) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_INTCHK3_KEYVAL_INTCHK3_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_INTCHK3)  Position */
+#define FUSES_KEYVAL_INTCHK3_KEYVAL_INTCHK3_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_INTCHK3_KEYVAL_INTCHK3_Pos) /* (FUSES_KEYVAL_INTCHK3)  Mask */
+#define FUSES_KEYVAL_INTCHK3_KEYVAL_INTCHK3(value) (FUSES_KEYVAL_INTCHK3_KEYVAL_INTCHK3_Msk & (_UINT32_(value) << FUSES_KEYVAL_INTCHK3_KEYVAL_INTCHK3_Pos)) /* Assignment of value for KEYVAL_INTCHK3 in the FUSES_KEYVAL_INTCHK3 register */
+#define FUSES_KEYVAL_INTCHK3_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_INTCHK3) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_INTCHK4 : (FUSES Offset: 0x430) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_INTCHK4_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_INTCHK4) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_INTCHK4_KEYVAL_INTCHK4_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_INTCHK4)  Position */
+#define FUSES_KEYVAL_INTCHK4_KEYVAL_INTCHK4_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_INTCHK4_KEYVAL_INTCHK4_Pos) /* (FUSES_KEYVAL_INTCHK4)  Mask */
+#define FUSES_KEYVAL_INTCHK4_KEYVAL_INTCHK4(value) (FUSES_KEYVAL_INTCHK4_KEYVAL_INTCHK4_Msk & (_UINT32_(value) << FUSES_KEYVAL_INTCHK4_KEYVAL_INTCHK4_Pos)) /* Assignment of value for KEYVAL_INTCHK4 in the FUSES_KEYVAL_INTCHK4 register */
+#define FUSES_KEYVAL_INTCHK4_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_INTCHK4) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_INTCHK5 : (FUSES Offset: 0x434) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_INTCHK5_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_INTCHK5) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_INTCHK5_KEYVAL_INTCHK5_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_INTCHK5)  Position */
+#define FUSES_KEYVAL_INTCHK5_KEYVAL_INTCHK5_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_INTCHK5_KEYVAL_INTCHK5_Pos) /* (FUSES_KEYVAL_INTCHK5)  Mask */
+#define FUSES_KEYVAL_INTCHK5_KEYVAL_INTCHK5(value) (FUSES_KEYVAL_INTCHK5_KEYVAL_INTCHK5_Msk & (_UINT32_(value) << FUSES_KEYVAL_INTCHK5_KEYVAL_INTCHK5_Pos)) /* Assignment of value for KEYVAL_INTCHK5 in the FUSES_KEYVAL_INTCHK5 register */
+#define FUSES_KEYVAL_INTCHK5_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_INTCHK5) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_INTCHK6 : (FUSES Offset: 0x438) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_INTCHK6_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_INTCHK6) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_INTCHK6_KEYVAL_INTCHK6_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_INTCHK6)  Position */
+#define FUSES_KEYVAL_INTCHK6_KEYVAL_INTCHK6_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_INTCHK6_KEYVAL_INTCHK6_Pos) /* (FUSES_KEYVAL_INTCHK6)  Mask */
+#define FUSES_KEYVAL_INTCHK6_KEYVAL_INTCHK6(value) (FUSES_KEYVAL_INTCHK6_KEYVAL_INTCHK6_Msk & (_UINT32_(value) << FUSES_KEYVAL_INTCHK6_KEYVAL_INTCHK6_Pos)) /* Assignment of value for KEYVAL_INTCHK6 in the FUSES_KEYVAL_INTCHK6 register */
+#define FUSES_KEYVAL_INTCHK6_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_INTCHK6) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_INTCHK7 : (FUSES Offset: 0x43C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_INTCHK7_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_INTCHK7) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_INTCHK7_KEYVAL_INTCHK7_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_INTCHK7)  Position */
+#define FUSES_KEYVAL_INTCHK7_KEYVAL_INTCHK7_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_INTCHK7_KEYVAL_INTCHK7_Pos) /* (FUSES_KEYVAL_INTCHK7)  Mask */
+#define FUSES_KEYVAL_INTCHK7_KEYVAL_INTCHK7(value) (FUSES_KEYVAL_INTCHK7_KEYVAL_INTCHK7_Msk & (_UINT32_(value) << FUSES_KEYVAL_INTCHK7_KEYVAL_INTCHK7_Pos)) /* Assignment of value for KEYVAL_INTCHK7 in the FUSES_KEYVAL_INTCHK7 register */
+#define FUSES_KEYVAL_INTCHK7_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_INTCHK7) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_ALL0 : (FUSES Offset: 0x440) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_ALL0_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_ALL0) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_ALL0_KEYVAL_CE_ALL0_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_ALL0)  Position */
+#define FUSES_KEYVAL_CE_ALL0_KEYVAL_CE_ALL0_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_ALL0_KEYVAL_CE_ALL0_Pos) /* (FUSES_KEYVAL_CE_ALL0)  Mask */
+#define FUSES_KEYVAL_CE_ALL0_KEYVAL_CE_ALL0(value) (FUSES_KEYVAL_CE_ALL0_KEYVAL_CE_ALL0_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_ALL0_KEYVAL_CE_ALL0_Pos)) /* Assignment of value for KEYVAL_CE_ALL0 in the FUSES_KEYVAL_CE_ALL0 register */
+#define FUSES_KEYVAL_CE_ALL0_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_ALL0) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_ALL1 : (FUSES Offset: 0x444) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_ALL1_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_ALL1) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_ALL1_KEYVAL_CE_ALL1_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_ALL1)  Position */
+#define FUSES_KEYVAL_CE_ALL1_KEYVAL_CE_ALL1_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_ALL1_KEYVAL_CE_ALL1_Pos) /* (FUSES_KEYVAL_CE_ALL1)  Mask */
+#define FUSES_KEYVAL_CE_ALL1_KEYVAL_CE_ALL1(value) (FUSES_KEYVAL_CE_ALL1_KEYVAL_CE_ALL1_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_ALL1_KEYVAL_CE_ALL1_Pos)) /* Assignment of value for KEYVAL_CE_ALL1 in the FUSES_KEYVAL_CE_ALL1 register */
+#define FUSES_KEYVAL_CE_ALL1_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_ALL1) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_ALL2 : (FUSES Offset: 0x448) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_ALL2_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_ALL2) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_ALL2_KEYVAL_CE_ALL2_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_ALL2)  Position */
+#define FUSES_KEYVAL_CE_ALL2_KEYVAL_CE_ALL2_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_ALL2_KEYVAL_CE_ALL2_Pos) /* (FUSES_KEYVAL_CE_ALL2)  Mask */
+#define FUSES_KEYVAL_CE_ALL2_KEYVAL_CE_ALL2(value) (FUSES_KEYVAL_CE_ALL2_KEYVAL_CE_ALL2_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_ALL2_KEYVAL_CE_ALL2_Pos)) /* Assignment of value for KEYVAL_CE_ALL2 in the FUSES_KEYVAL_CE_ALL2 register */
+#define FUSES_KEYVAL_CE_ALL2_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_ALL2) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_ALL3 : (FUSES Offset: 0x44C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_ALL3_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_ALL3) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_ALL3_KEYVAL_CE_ALL3_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_ALL3)  Position */
+#define FUSES_KEYVAL_CE_ALL3_KEYVAL_CE_ALL3_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_ALL3_KEYVAL_CE_ALL3_Pos) /* (FUSES_KEYVAL_CE_ALL3)  Mask */
+#define FUSES_KEYVAL_CE_ALL3_KEYVAL_CE_ALL3(value) (FUSES_KEYVAL_CE_ALL3_KEYVAL_CE_ALL3_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_ALL3_KEYVAL_CE_ALL3_Pos)) /* Assignment of value for KEYVAL_CE_ALL3 in the FUSES_KEYVAL_CE_ALL3 register */
+#define FUSES_KEYVAL_CE_ALL3_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_ALL3) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_ALL4 : (FUSES Offset: 0x450) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_ALL4_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_ALL4) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_ALL4_KEYVAL_CE_ALL4_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_ALL4)  Position */
+#define FUSES_KEYVAL_CE_ALL4_KEYVAL_CE_ALL4_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_ALL4_KEYVAL_CE_ALL4_Pos) /* (FUSES_KEYVAL_CE_ALL4)  Mask */
+#define FUSES_KEYVAL_CE_ALL4_KEYVAL_CE_ALL4(value) (FUSES_KEYVAL_CE_ALL4_KEYVAL_CE_ALL4_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_ALL4_KEYVAL_CE_ALL4_Pos)) /* Assignment of value for KEYVAL_CE_ALL4 in the FUSES_KEYVAL_CE_ALL4 register */
+#define FUSES_KEYVAL_CE_ALL4_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_ALL4) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_ALL5 : (FUSES Offset: 0x454) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_ALL5_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_ALL5) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_ALL5_KEYVAL_CE_ALL5_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_ALL5)  Position */
+#define FUSES_KEYVAL_CE_ALL5_KEYVAL_CE_ALL5_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_ALL5_KEYVAL_CE_ALL5_Pos) /* (FUSES_KEYVAL_CE_ALL5)  Mask */
+#define FUSES_KEYVAL_CE_ALL5_KEYVAL_CE_ALL5(value) (FUSES_KEYVAL_CE_ALL5_KEYVAL_CE_ALL5_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_ALL5_KEYVAL_CE_ALL5_Pos)) /* Assignment of value for KEYVAL_CE_ALL5 in the FUSES_KEYVAL_CE_ALL5 register */
+#define FUSES_KEYVAL_CE_ALL5_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_ALL5) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_ALL6 : (FUSES Offset: 0x458) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_ALL6_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_ALL6) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_ALL6_KEYVAL_CE_ALL6_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_ALL6)  Position */
+#define FUSES_KEYVAL_CE_ALL6_KEYVAL_CE_ALL6_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_ALL6_KEYVAL_CE_ALL6_Pos) /* (FUSES_KEYVAL_CE_ALL6)  Mask */
+#define FUSES_KEYVAL_CE_ALL6_KEYVAL_CE_ALL6(value) (FUSES_KEYVAL_CE_ALL6_KEYVAL_CE_ALL6_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_ALL6_KEYVAL_CE_ALL6_Pos)) /* Assignment of value for KEYVAL_CE_ALL6 in the FUSES_KEYVAL_CE_ALL6 register */
+#define FUSES_KEYVAL_CE_ALL6_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_ALL6) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_ALL7 : (FUSES Offset: 0x45C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_ALL7_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_ALL7) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_ALL7_KEYVAL_CE_ALL7_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_ALL7)  Position */
+#define FUSES_KEYVAL_CE_ALL7_KEYVAL_CE_ALL7_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_ALL7_KEYVAL_CE_ALL7_Pos) /* (FUSES_KEYVAL_CE_ALL7)  Mask */
+#define FUSES_KEYVAL_CE_ALL7_KEYVAL_CE_ALL7(value) (FUSES_KEYVAL_CE_ALL7_KEYVAL_CE_ALL7_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_ALL7_KEYVAL_CE_ALL7_Pos)) /* Assignment of value for KEYVAL_CE_ALL7 in the FUSES_KEYVAL_CE_ALL7 register */
+#define FUSES_KEYVAL_CE_ALL7_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_ALL7) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S_CR0 : (FUSES Offset: 0x460) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S_CR0_RESETVALUE      _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S_CR0) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S_CR0_KEYVAL_CE_S_CR0_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S_CR0)  Position */
+#define FUSES_KEYVAL_CE_S_CR0_KEYVAL_CE_S_CR0_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S_CR0_KEYVAL_CE_S_CR0_Pos) /* (FUSES_KEYVAL_CE_S_CR0)  Mask */
+#define FUSES_KEYVAL_CE_S_CR0_KEYVAL_CE_S_CR0(value) (FUSES_KEYVAL_CE_S_CR0_KEYVAL_CE_S_CR0_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S_CR0_KEYVAL_CE_S_CR0_Pos)) /* Assignment of value for KEYVAL_CE_S_CR0 in the FUSES_KEYVAL_CE_S_CR0 register */
+#define FUSES_KEYVAL_CE_S_CR0_Msk             _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S_CR0) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S_CR1 : (FUSES Offset: 0x464) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S_CR1_RESETVALUE      _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S_CR1) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S_CR1_KEYVAL_CE_S_CR1_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S_CR1)  Position */
+#define FUSES_KEYVAL_CE_S_CR1_KEYVAL_CE_S_CR1_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S_CR1_KEYVAL_CE_S_CR1_Pos) /* (FUSES_KEYVAL_CE_S_CR1)  Mask */
+#define FUSES_KEYVAL_CE_S_CR1_KEYVAL_CE_S_CR1(value) (FUSES_KEYVAL_CE_S_CR1_KEYVAL_CE_S_CR1_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S_CR1_KEYVAL_CE_S_CR1_Pos)) /* Assignment of value for KEYVAL_CE_S_CR1 in the FUSES_KEYVAL_CE_S_CR1 register */
+#define FUSES_KEYVAL_CE_S_CR1_Msk             _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S_CR1) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S_CR2 : (FUSES Offset: 0x468) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S_CR2_RESETVALUE      _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S_CR2) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S_CR2_KEYVAL_CE_S_CR2_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S_CR2)  Position */
+#define FUSES_KEYVAL_CE_S_CR2_KEYVAL_CE_S_CR2_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S_CR2_KEYVAL_CE_S_CR2_Pos) /* (FUSES_KEYVAL_CE_S_CR2)  Mask */
+#define FUSES_KEYVAL_CE_S_CR2_KEYVAL_CE_S_CR2(value) (FUSES_KEYVAL_CE_S_CR2_KEYVAL_CE_S_CR2_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S_CR2_KEYVAL_CE_S_CR2_Pos)) /* Assignment of value for KEYVAL_CE_S_CR2 in the FUSES_KEYVAL_CE_S_CR2 register */
+#define FUSES_KEYVAL_CE_S_CR2_Msk             _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S_CR2) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S_CR3 : (FUSES Offset: 0x46C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S_CR3_RESETVALUE      _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S_CR3) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S_CR3_KEYVAL_CE_S_CR3_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S_CR3)  Position */
+#define FUSES_KEYVAL_CE_S_CR3_KEYVAL_CE_S_CR3_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S_CR3_KEYVAL_CE_S_CR3_Pos) /* (FUSES_KEYVAL_CE_S_CR3)  Mask */
+#define FUSES_KEYVAL_CE_S_CR3_KEYVAL_CE_S_CR3(value) (FUSES_KEYVAL_CE_S_CR3_KEYVAL_CE_S_CR3_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S_CR3_KEYVAL_CE_S_CR3_Pos)) /* Assignment of value for KEYVAL_CE_S_CR3 in the FUSES_KEYVAL_CE_S_CR3 register */
+#define FUSES_KEYVAL_CE_S_CR3_Msk             _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S_CR3) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S_CR4 : (FUSES Offset: 0x470) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S_CR4_RESETVALUE      _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S_CR4) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S_CR4_KEYVAL_CE_S_CR4_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S_CR4)  Position */
+#define FUSES_KEYVAL_CE_S_CR4_KEYVAL_CE_S_CR4_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S_CR4_KEYVAL_CE_S_CR4_Pos) /* (FUSES_KEYVAL_CE_S_CR4)  Mask */
+#define FUSES_KEYVAL_CE_S_CR4_KEYVAL_CE_S_CR4(value) (FUSES_KEYVAL_CE_S_CR4_KEYVAL_CE_S_CR4_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S_CR4_KEYVAL_CE_S_CR4_Pos)) /* Assignment of value for KEYVAL_CE_S_CR4 in the FUSES_KEYVAL_CE_S_CR4 register */
+#define FUSES_KEYVAL_CE_S_CR4_Msk             _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S_CR4) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S_CR5 : (FUSES Offset: 0x474) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S_CR5_RESETVALUE      _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S_CR5) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S_CR5_KEYVAL_CE_S_CR5_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S_CR5)  Position */
+#define FUSES_KEYVAL_CE_S_CR5_KEYVAL_CE_S_CR5_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S_CR5_KEYVAL_CE_S_CR5_Pos) /* (FUSES_KEYVAL_CE_S_CR5)  Mask */
+#define FUSES_KEYVAL_CE_S_CR5_KEYVAL_CE_S_CR5(value) (FUSES_KEYVAL_CE_S_CR5_KEYVAL_CE_S_CR5_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S_CR5_KEYVAL_CE_S_CR5_Pos)) /* Assignment of value for KEYVAL_CE_S_CR5 in the FUSES_KEYVAL_CE_S_CR5 register */
+#define FUSES_KEYVAL_CE_S_CR5_Msk             _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S_CR5) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S_CR6 : (FUSES Offset: 0x478) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S_CR6_RESETVALUE      _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S_CR6) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S_CR6_KEYVAL_CE_S_CR6_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S_CR6)  Position */
+#define FUSES_KEYVAL_CE_S_CR6_KEYVAL_CE_S_CR6_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S_CR6_KEYVAL_CE_S_CR6_Pos) /* (FUSES_KEYVAL_CE_S_CR6)  Mask */
+#define FUSES_KEYVAL_CE_S_CR6_KEYVAL_CE_S_CR6(value) (FUSES_KEYVAL_CE_S_CR6_KEYVAL_CE_S_CR6_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S_CR6_KEYVAL_CE_S_CR6_Pos)) /* Assignment of value for KEYVAL_CE_S_CR6 in the FUSES_KEYVAL_CE_S_CR6 register */
+#define FUSES_KEYVAL_CE_S_CR6_Msk             _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S_CR6) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S_CR7 : (FUSES Offset: 0x47C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S_CR7_RESETVALUE      _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S_CR7) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S_CR7_KEYVAL_CE_S_CR7_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S_CR7)  Position */
+#define FUSES_KEYVAL_CE_S_CR7_KEYVAL_CE_S_CR7_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S_CR7_KEYVAL_CE_S_CR7_Pos) /* (FUSES_KEYVAL_CE_S_CR7)  Mask */
+#define FUSES_KEYVAL_CE_S_CR7_KEYVAL_CE_S_CR7(value) (FUSES_KEYVAL_CE_S_CR7_KEYVAL_CE_S_CR7_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S_CR7_KEYVAL_CE_S_CR7_Pos)) /* Assignment of value for KEYVAL_CE_S_CR7 in the FUSES_KEYVAL_CE_S_CR7 register */
+#define FUSES_KEYVAL_CE_S_CR7_Msk             _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S_CR7) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S0 : (FUSES Offset: 0x480) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S0_RESETVALUE         _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S0) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S0_KEYVAL_CE_S0_Pos   _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S0)  Position */
+#define FUSES_KEYVAL_CE_S0_KEYVAL_CE_S0_Msk   (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S0_KEYVAL_CE_S0_Pos) /* (FUSES_KEYVAL_CE_S0)  Mask */
+#define FUSES_KEYVAL_CE_S0_KEYVAL_CE_S0(value) (FUSES_KEYVAL_CE_S0_KEYVAL_CE_S0_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S0_KEYVAL_CE_S0_Pos)) /* Assignment of value for KEYVAL_CE_S0 in the FUSES_KEYVAL_CE_S0 register */
+#define FUSES_KEYVAL_CE_S0_Msk                _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S0) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S1 : (FUSES Offset: 0x484) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S1_RESETVALUE         _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S1) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S1_KEYVAL_CE_S1_Pos   _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S1)  Position */
+#define FUSES_KEYVAL_CE_S1_KEYVAL_CE_S1_Msk   (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S1_KEYVAL_CE_S1_Pos) /* (FUSES_KEYVAL_CE_S1)  Mask */
+#define FUSES_KEYVAL_CE_S1_KEYVAL_CE_S1(value) (FUSES_KEYVAL_CE_S1_KEYVAL_CE_S1_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S1_KEYVAL_CE_S1_Pos)) /* Assignment of value for KEYVAL_CE_S1 in the FUSES_KEYVAL_CE_S1 register */
+#define FUSES_KEYVAL_CE_S1_Msk                _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S1) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S2 : (FUSES Offset: 0x488) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S2_RESETVALUE         _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S2) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S2_KEYVAL_CE_S2_Pos   _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S2)  Position */
+#define FUSES_KEYVAL_CE_S2_KEYVAL_CE_S2_Msk   (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S2_KEYVAL_CE_S2_Pos) /* (FUSES_KEYVAL_CE_S2)  Mask */
+#define FUSES_KEYVAL_CE_S2_KEYVAL_CE_S2(value) (FUSES_KEYVAL_CE_S2_KEYVAL_CE_S2_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S2_KEYVAL_CE_S2_Pos)) /* Assignment of value for KEYVAL_CE_S2 in the FUSES_KEYVAL_CE_S2 register */
+#define FUSES_KEYVAL_CE_S2_Msk                _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S2) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S3 : (FUSES Offset: 0x48C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S3_RESETVALUE         _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S3) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S3_KEYVAL_CE_S3_Pos   _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S3)  Position */
+#define FUSES_KEYVAL_CE_S3_KEYVAL_CE_S3_Msk   (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S3_KEYVAL_CE_S3_Pos) /* (FUSES_KEYVAL_CE_S3)  Mask */
+#define FUSES_KEYVAL_CE_S3_KEYVAL_CE_S3(value) (FUSES_KEYVAL_CE_S3_KEYVAL_CE_S3_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S3_KEYVAL_CE_S3_Pos)) /* Assignment of value for KEYVAL_CE_S3 in the FUSES_KEYVAL_CE_S3 register */
+#define FUSES_KEYVAL_CE_S3_Msk                _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S3) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S4 : (FUSES Offset: 0x490) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S4_RESETVALUE         _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S4) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S4_KEYVAL_CE_S4_Pos   _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S4)  Position */
+#define FUSES_KEYVAL_CE_S4_KEYVAL_CE_S4_Msk   (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S4_KEYVAL_CE_S4_Pos) /* (FUSES_KEYVAL_CE_S4)  Mask */
+#define FUSES_KEYVAL_CE_S4_KEYVAL_CE_S4(value) (FUSES_KEYVAL_CE_S4_KEYVAL_CE_S4_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S4_KEYVAL_CE_S4_Pos)) /* Assignment of value for KEYVAL_CE_S4 in the FUSES_KEYVAL_CE_S4 register */
+#define FUSES_KEYVAL_CE_S4_Msk                _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S4) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S5 : (FUSES Offset: 0x494) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S5_RESETVALUE         _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S5) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S5_KEYVAL_CE_S5_Pos   _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S5)  Position */
+#define FUSES_KEYVAL_CE_S5_KEYVAL_CE_S5_Msk   (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S5_KEYVAL_CE_S5_Pos) /* (FUSES_KEYVAL_CE_S5)  Mask */
+#define FUSES_KEYVAL_CE_S5_KEYVAL_CE_S5(value) (FUSES_KEYVAL_CE_S5_KEYVAL_CE_S5_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S5_KEYVAL_CE_S5_Pos)) /* Assignment of value for KEYVAL_CE_S5 in the FUSES_KEYVAL_CE_S5 register */
+#define FUSES_KEYVAL_CE_S5_Msk                _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S5) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S6 : (FUSES Offset: 0x498) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S6_RESETVALUE         _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S6) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S6_KEYVAL_CE_S6_Pos   _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S6)  Position */
+#define FUSES_KEYVAL_CE_S6_KEYVAL_CE_S6_Msk   (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S6_KEYVAL_CE_S6_Pos) /* (FUSES_KEYVAL_CE_S6)  Mask */
+#define FUSES_KEYVAL_CE_S6_KEYVAL_CE_S6(value) (FUSES_KEYVAL_CE_S6_KEYVAL_CE_S6_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S6_KEYVAL_CE_S6_Pos)) /* Assignment of value for KEYVAL_CE_S6 in the FUSES_KEYVAL_CE_S6 register */
+#define FUSES_KEYVAL_CE_S6_Msk                _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S6) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_S7 : (FUSES Offset: 0x49C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_S7_RESETVALUE         _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_S7) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_S7_KEYVAL_CE_S7_Pos   _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_S7)  Position */
+#define FUSES_KEYVAL_CE_S7_KEYVAL_CE_S7_Msk   (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_S7_KEYVAL_CE_S7_Pos) /* (FUSES_KEYVAL_CE_S7)  Mask */
+#define FUSES_KEYVAL_CE_S7_KEYVAL_CE_S7(value) (FUSES_KEYVAL_CE_S7_KEYVAL_CE_S7_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_S7_KEYVAL_CE_S7_Pos)) /* Assignment of value for KEYVAL_CE_S7 in the FUSES_KEYVAL_CE_S7 register */
+#define FUSES_KEYVAL_CE_S7_Msk                _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_S7) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS_CR0 : (FUSES Offset: 0x4A0) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS_CR0_RESETVALUE     _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS_CR0) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS_CR0_KEYVAL_CE_NS_CR0_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS_CR0)  Position */
+#define FUSES_KEYVAL_CE_NS_CR0_KEYVAL_CE_NS_CR0_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS_CR0_KEYVAL_CE_NS_CR0_Pos) /* (FUSES_KEYVAL_CE_NS_CR0)  Mask */
+#define FUSES_KEYVAL_CE_NS_CR0_KEYVAL_CE_NS_CR0(value) (FUSES_KEYVAL_CE_NS_CR0_KEYVAL_CE_NS_CR0_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS_CR0_KEYVAL_CE_NS_CR0_Pos)) /* Assignment of value for KEYVAL_CE_NS_CR0 in the FUSES_KEYVAL_CE_NS_CR0 register */
+#define FUSES_KEYVAL_CE_NS_CR0_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS_CR0) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS_CR1 : (FUSES Offset: 0x4A4) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS_CR1_RESETVALUE     _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS_CR1) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS_CR1_KEYVAL_CE_NS_CR1_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS_CR1)  Position */
+#define FUSES_KEYVAL_CE_NS_CR1_KEYVAL_CE_NS_CR1_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS_CR1_KEYVAL_CE_NS_CR1_Pos) /* (FUSES_KEYVAL_CE_NS_CR1)  Mask */
+#define FUSES_KEYVAL_CE_NS_CR1_KEYVAL_CE_NS_CR1(value) (FUSES_KEYVAL_CE_NS_CR1_KEYVAL_CE_NS_CR1_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS_CR1_KEYVAL_CE_NS_CR1_Pos)) /* Assignment of value for KEYVAL_CE_NS_CR1 in the FUSES_KEYVAL_CE_NS_CR1 register */
+#define FUSES_KEYVAL_CE_NS_CR1_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS_CR1) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS_CR2 : (FUSES Offset: 0x4A8) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS_CR2_RESETVALUE     _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS_CR2) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS_CR2_KEYVAL_CE_NS_CR2_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS_CR2)  Position */
+#define FUSES_KEYVAL_CE_NS_CR2_KEYVAL_CE_NS_CR2_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS_CR2_KEYVAL_CE_NS_CR2_Pos) /* (FUSES_KEYVAL_CE_NS_CR2)  Mask */
+#define FUSES_KEYVAL_CE_NS_CR2_KEYVAL_CE_NS_CR2(value) (FUSES_KEYVAL_CE_NS_CR2_KEYVAL_CE_NS_CR2_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS_CR2_KEYVAL_CE_NS_CR2_Pos)) /* Assignment of value for KEYVAL_CE_NS_CR2 in the FUSES_KEYVAL_CE_NS_CR2 register */
+#define FUSES_KEYVAL_CE_NS_CR2_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS_CR2) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS_CR3 : (FUSES Offset: 0x4AC) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS_CR3_RESETVALUE     _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS_CR3) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS_CR3_KEYVAL_CE_NS_CR3_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS_CR3)  Position */
+#define FUSES_KEYVAL_CE_NS_CR3_KEYVAL_CE_NS_CR3_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS_CR3_KEYVAL_CE_NS_CR3_Pos) /* (FUSES_KEYVAL_CE_NS_CR3)  Mask */
+#define FUSES_KEYVAL_CE_NS_CR3_KEYVAL_CE_NS_CR3(value) (FUSES_KEYVAL_CE_NS_CR3_KEYVAL_CE_NS_CR3_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS_CR3_KEYVAL_CE_NS_CR3_Pos)) /* Assignment of value for KEYVAL_CE_NS_CR3 in the FUSES_KEYVAL_CE_NS_CR3 register */
+#define FUSES_KEYVAL_CE_NS_CR3_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS_CR3) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS_CR4 : (FUSES Offset: 0x4B0) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS_CR4_RESETVALUE     _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS_CR4) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS_CR4_KEYVAL_CE_NS_CR4_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS_CR4)  Position */
+#define FUSES_KEYVAL_CE_NS_CR4_KEYVAL_CE_NS_CR4_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS_CR4_KEYVAL_CE_NS_CR4_Pos) /* (FUSES_KEYVAL_CE_NS_CR4)  Mask */
+#define FUSES_KEYVAL_CE_NS_CR4_KEYVAL_CE_NS_CR4(value) (FUSES_KEYVAL_CE_NS_CR4_KEYVAL_CE_NS_CR4_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS_CR4_KEYVAL_CE_NS_CR4_Pos)) /* Assignment of value for KEYVAL_CE_NS_CR4 in the FUSES_KEYVAL_CE_NS_CR4 register */
+#define FUSES_KEYVAL_CE_NS_CR4_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS_CR4) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS_CR5 : (FUSES Offset: 0x4B4) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS_CR5_RESETVALUE     _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS_CR5) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS_CR5_KEYVAL_CE_NS_CR5_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS_CR5)  Position */
+#define FUSES_KEYVAL_CE_NS_CR5_KEYVAL_CE_NS_CR5_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS_CR5_KEYVAL_CE_NS_CR5_Pos) /* (FUSES_KEYVAL_CE_NS_CR5)  Mask */
+#define FUSES_KEYVAL_CE_NS_CR5_KEYVAL_CE_NS_CR5(value) (FUSES_KEYVAL_CE_NS_CR5_KEYVAL_CE_NS_CR5_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS_CR5_KEYVAL_CE_NS_CR5_Pos)) /* Assignment of value for KEYVAL_CE_NS_CR5 in the FUSES_KEYVAL_CE_NS_CR5 register */
+#define FUSES_KEYVAL_CE_NS_CR5_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS_CR5) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS_CR6 : (FUSES Offset: 0x4B8) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS_CR6_RESETVALUE     _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS_CR6) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS_CR6_KEYVAL_CE_NS_CR6_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS_CR6)  Position */
+#define FUSES_KEYVAL_CE_NS_CR6_KEYVAL_CE_NS_CR6_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS_CR6_KEYVAL_CE_NS_CR6_Pos) /* (FUSES_KEYVAL_CE_NS_CR6)  Mask */
+#define FUSES_KEYVAL_CE_NS_CR6_KEYVAL_CE_NS_CR6(value) (FUSES_KEYVAL_CE_NS_CR6_KEYVAL_CE_NS_CR6_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS_CR6_KEYVAL_CE_NS_CR6_Pos)) /* Assignment of value for KEYVAL_CE_NS_CR6 in the FUSES_KEYVAL_CE_NS_CR6 register */
+#define FUSES_KEYVAL_CE_NS_CR6_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS_CR6) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS_CR7 : (FUSES Offset: 0x4BC) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS_CR7_RESETVALUE     _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS_CR7) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS_CR7_KEYVAL_CE_NS_CR7_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS_CR7)  Position */
+#define FUSES_KEYVAL_CE_NS_CR7_KEYVAL_CE_NS_CR7_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS_CR7_KEYVAL_CE_NS_CR7_Pos) /* (FUSES_KEYVAL_CE_NS_CR7)  Mask */
+#define FUSES_KEYVAL_CE_NS_CR7_KEYVAL_CE_NS_CR7(value) (FUSES_KEYVAL_CE_NS_CR7_KEYVAL_CE_NS_CR7_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS_CR7_KEYVAL_CE_NS_CR7_Pos)) /* Assignment of value for KEYVAL_CE_NS_CR7 in the FUSES_KEYVAL_CE_NS_CR7 register */
+#define FUSES_KEYVAL_CE_NS_CR7_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS_CR7) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS0 : (FUSES Offset: 0x4C0) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS0_RESETVALUE        _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS0) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS0_KEYVAL_CE_NS0_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS0)  Position */
+#define FUSES_KEYVAL_CE_NS0_KEYVAL_CE_NS0_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS0_KEYVAL_CE_NS0_Pos) /* (FUSES_KEYVAL_CE_NS0)  Mask */
+#define FUSES_KEYVAL_CE_NS0_KEYVAL_CE_NS0(value) (FUSES_KEYVAL_CE_NS0_KEYVAL_CE_NS0_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS0_KEYVAL_CE_NS0_Pos)) /* Assignment of value for KEYVAL_CE_NS0 in the FUSES_KEYVAL_CE_NS0 register */
+#define FUSES_KEYVAL_CE_NS0_Msk               _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS0) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS1 : (FUSES Offset: 0x4C4) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS1_RESETVALUE        _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS1) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS1_KEYVAL_CE_NS1_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS1)  Position */
+#define FUSES_KEYVAL_CE_NS1_KEYVAL_CE_NS1_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS1_KEYVAL_CE_NS1_Pos) /* (FUSES_KEYVAL_CE_NS1)  Mask */
+#define FUSES_KEYVAL_CE_NS1_KEYVAL_CE_NS1(value) (FUSES_KEYVAL_CE_NS1_KEYVAL_CE_NS1_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS1_KEYVAL_CE_NS1_Pos)) /* Assignment of value for KEYVAL_CE_NS1 in the FUSES_KEYVAL_CE_NS1 register */
+#define FUSES_KEYVAL_CE_NS1_Msk               _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS1) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS2 : (FUSES Offset: 0x4C8) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS2_RESETVALUE        _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS2) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS2_KEYVAL_CE_NS2_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS2)  Position */
+#define FUSES_KEYVAL_CE_NS2_KEYVAL_CE_NS2_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS2_KEYVAL_CE_NS2_Pos) /* (FUSES_KEYVAL_CE_NS2)  Mask */
+#define FUSES_KEYVAL_CE_NS2_KEYVAL_CE_NS2(value) (FUSES_KEYVAL_CE_NS2_KEYVAL_CE_NS2_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS2_KEYVAL_CE_NS2_Pos)) /* Assignment of value for KEYVAL_CE_NS2 in the FUSES_KEYVAL_CE_NS2 register */
+#define FUSES_KEYVAL_CE_NS2_Msk               _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS2) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS3 : (FUSES Offset: 0x4CC) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS3_RESETVALUE        _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS3) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS3_KEYVAL_CE_NS3_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS3)  Position */
+#define FUSES_KEYVAL_CE_NS3_KEYVAL_CE_NS3_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS3_KEYVAL_CE_NS3_Pos) /* (FUSES_KEYVAL_CE_NS3)  Mask */
+#define FUSES_KEYVAL_CE_NS3_KEYVAL_CE_NS3(value) (FUSES_KEYVAL_CE_NS3_KEYVAL_CE_NS3_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS3_KEYVAL_CE_NS3_Pos)) /* Assignment of value for KEYVAL_CE_NS3 in the FUSES_KEYVAL_CE_NS3 register */
+#define FUSES_KEYVAL_CE_NS3_Msk               _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS3) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS4 : (FUSES Offset: 0x4D0) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS4_RESETVALUE        _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS4) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS4_KEYVAL_CE_NS4_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS4)  Position */
+#define FUSES_KEYVAL_CE_NS4_KEYVAL_CE_NS4_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS4_KEYVAL_CE_NS4_Pos) /* (FUSES_KEYVAL_CE_NS4)  Mask */
+#define FUSES_KEYVAL_CE_NS4_KEYVAL_CE_NS4(value) (FUSES_KEYVAL_CE_NS4_KEYVAL_CE_NS4_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS4_KEYVAL_CE_NS4_Pos)) /* Assignment of value for KEYVAL_CE_NS4 in the FUSES_KEYVAL_CE_NS4 register */
+#define FUSES_KEYVAL_CE_NS4_Msk               _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS4) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS5 : (FUSES Offset: 0x4D4) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS5_RESETVALUE        _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS5) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS5_KEYVAL_CE_NS5_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS5)  Position */
+#define FUSES_KEYVAL_CE_NS5_KEYVAL_CE_NS5_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS5_KEYVAL_CE_NS5_Pos) /* (FUSES_KEYVAL_CE_NS5)  Mask */
+#define FUSES_KEYVAL_CE_NS5_KEYVAL_CE_NS5(value) (FUSES_KEYVAL_CE_NS5_KEYVAL_CE_NS5_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS5_KEYVAL_CE_NS5_Pos)) /* Assignment of value for KEYVAL_CE_NS5 in the FUSES_KEYVAL_CE_NS5 register */
+#define FUSES_KEYVAL_CE_NS5_Msk               _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS5) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS6 : (FUSES Offset: 0x4D8) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS6_RESETVALUE        _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS6) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS6_KEYVAL_CE_NS6_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS6)  Position */
+#define FUSES_KEYVAL_CE_NS6_KEYVAL_CE_NS6_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS6_KEYVAL_CE_NS6_Pos) /* (FUSES_KEYVAL_CE_NS6)  Mask */
+#define FUSES_KEYVAL_CE_NS6_KEYVAL_CE_NS6(value) (FUSES_KEYVAL_CE_NS6_KEYVAL_CE_NS6_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS6_KEYVAL_CE_NS6_Pos)) /* Assignment of value for KEYVAL_CE_NS6 in the FUSES_KEYVAL_CE_NS6 register */
+#define FUSES_KEYVAL_CE_NS6_Msk               _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS6) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_CE_NS7 : (FUSES Offset: 0x4DC) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_CE_NS7_RESETVALUE        _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_CE_NS7) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_CE_NS7_KEYVAL_CE_NS7_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_CE_NS7)  Position */
+#define FUSES_KEYVAL_CE_NS7_KEYVAL_CE_NS7_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_CE_NS7_KEYVAL_CE_NS7_Pos) /* (FUSES_KEYVAL_CE_NS7)  Mask */
+#define FUSES_KEYVAL_CE_NS7_KEYVAL_CE_NS7(value) (FUSES_KEYVAL_CE_NS7_KEYVAL_CE_NS7_Msk & (_UINT32_(value) << FUSES_KEYVAL_CE_NS7_KEYVAL_CE_NS7_Pos)) /* Assignment of value for KEYVAL_CE_NS7 in the FUSES_KEYVAL_CE_NS7 register */
+#define FUSES_KEYVAL_CE_NS7_Msk               _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_CE_NS7) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_PRG_PG0 : (FUSES Offset: 0x4E0) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_PRG_PG0_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_PRG_PG0) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_PRG_PG0_KEYVAL_PRG_PG0_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_PRG_PG0)  Position */
+#define FUSES_KEYVAL_PRG_PG0_KEYVAL_PRG_PG0_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_PRG_PG0_KEYVAL_PRG_PG0_Pos) /* (FUSES_KEYVAL_PRG_PG0)  Mask */
+#define FUSES_KEYVAL_PRG_PG0_KEYVAL_PRG_PG0(value) (FUSES_KEYVAL_PRG_PG0_KEYVAL_PRG_PG0_Msk & (_UINT32_(value) << FUSES_KEYVAL_PRG_PG0_KEYVAL_PRG_PG0_Pos)) /* Assignment of value for KEYVAL_PRG_PG0 in the FUSES_KEYVAL_PRG_PG0 register */
+#define FUSES_KEYVAL_PRG_PG0_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_PRG_PG0) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_PRG_PG1 : (FUSES Offset: 0x4E4) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_PRG_PG1_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_PRG_PG1) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_PRG_PG1_KEYVAL_PRG_PG1_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_PRG_PG1)  Position */
+#define FUSES_KEYVAL_PRG_PG1_KEYVAL_PRG_PG1_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_PRG_PG1_KEYVAL_PRG_PG1_Pos) /* (FUSES_KEYVAL_PRG_PG1)  Mask */
+#define FUSES_KEYVAL_PRG_PG1_KEYVAL_PRG_PG1(value) (FUSES_KEYVAL_PRG_PG1_KEYVAL_PRG_PG1_Msk & (_UINT32_(value) << FUSES_KEYVAL_PRG_PG1_KEYVAL_PRG_PG1_Pos)) /* Assignment of value for KEYVAL_PRG_PG1 in the FUSES_KEYVAL_PRG_PG1 register */
+#define FUSES_KEYVAL_PRG_PG1_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_PRG_PG1) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_PRG_PG2 : (FUSES Offset: 0x4E8) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_PRG_PG2_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_PRG_PG2) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_PRG_PG2_KEYVAL_PRG_PG2_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_PRG_PG2)  Position */
+#define FUSES_KEYVAL_PRG_PG2_KEYVAL_PRG_PG2_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_PRG_PG2_KEYVAL_PRG_PG2_Pos) /* (FUSES_KEYVAL_PRG_PG2)  Mask */
+#define FUSES_KEYVAL_PRG_PG2_KEYVAL_PRG_PG2(value) (FUSES_KEYVAL_PRG_PG2_KEYVAL_PRG_PG2_Msk & (_UINT32_(value) << FUSES_KEYVAL_PRG_PG2_KEYVAL_PRG_PG2_Pos)) /* Assignment of value for KEYVAL_PRG_PG2 in the FUSES_KEYVAL_PRG_PG2 register */
+#define FUSES_KEYVAL_PRG_PG2_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_PRG_PG2) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_PRG_PG3 : (FUSES Offset: 0x4EC) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_PRG_PG3_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_PRG_PG3) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_PRG_PG3_KEYVAL_PRG_PG3_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_PRG_PG3)  Position */
+#define FUSES_KEYVAL_PRG_PG3_KEYVAL_PRG_PG3_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_PRG_PG3_KEYVAL_PRG_PG3_Pos) /* (FUSES_KEYVAL_PRG_PG3)  Mask */
+#define FUSES_KEYVAL_PRG_PG3_KEYVAL_PRG_PG3(value) (FUSES_KEYVAL_PRG_PG3_KEYVAL_PRG_PG3_Msk & (_UINT32_(value) << FUSES_KEYVAL_PRG_PG3_KEYVAL_PRG_PG3_Pos)) /* Assignment of value for KEYVAL_PRG_PG3 in the FUSES_KEYVAL_PRG_PG3 register */
+#define FUSES_KEYVAL_PRG_PG3_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_PRG_PG3) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_PRG_PG4 : (FUSES Offset: 0x4F0) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_PRG_PG4_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_PRG_PG4) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_PRG_PG4_KEYVAL_PRG_PG4_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_PRG_PG4)  Position */
+#define FUSES_KEYVAL_PRG_PG4_KEYVAL_PRG_PG4_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_PRG_PG4_KEYVAL_PRG_PG4_Pos) /* (FUSES_KEYVAL_PRG_PG4)  Mask */
+#define FUSES_KEYVAL_PRG_PG4_KEYVAL_PRG_PG4(value) (FUSES_KEYVAL_PRG_PG4_KEYVAL_PRG_PG4_Msk & (_UINT32_(value) << FUSES_KEYVAL_PRG_PG4_KEYVAL_PRG_PG4_Pos)) /* Assignment of value for KEYVAL_PRG_PG4 in the FUSES_KEYVAL_PRG_PG4 register */
+#define FUSES_KEYVAL_PRG_PG4_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_PRG_PG4) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_PRG_PG5 : (FUSES Offset: 0x4F4) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_PRG_PG5_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_PRG_PG5) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_PRG_PG5_KEYVAL_PRG_PG5_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_PRG_PG5)  Position */
+#define FUSES_KEYVAL_PRG_PG5_KEYVAL_PRG_PG5_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_PRG_PG5_KEYVAL_PRG_PG5_Pos) /* (FUSES_KEYVAL_PRG_PG5)  Mask */
+#define FUSES_KEYVAL_PRG_PG5_KEYVAL_PRG_PG5(value) (FUSES_KEYVAL_PRG_PG5_KEYVAL_PRG_PG5_Msk & (_UINT32_(value) << FUSES_KEYVAL_PRG_PG5_KEYVAL_PRG_PG5_Pos)) /* Assignment of value for KEYVAL_PRG_PG5 in the FUSES_KEYVAL_PRG_PG5 register */
+#define FUSES_KEYVAL_PRG_PG5_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_PRG_PG5) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_PRG_PG6 : (FUSES Offset: 0x4F8) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_PRG_PG6_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_PRG_PG6) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_PRG_PG6_KEYVAL_PRG_PG6_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_PRG_PG6)  Position */
+#define FUSES_KEYVAL_PRG_PG6_KEYVAL_PRG_PG6_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_PRG_PG6_KEYVAL_PRG_PG6_Pos) /* (FUSES_KEYVAL_PRG_PG6)  Mask */
+#define FUSES_KEYVAL_PRG_PG6_KEYVAL_PRG_PG6(value) (FUSES_KEYVAL_PRG_PG6_KEYVAL_PRG_PG6_Msk & (_UINT32_(value) << FUSES_KEYVAL_PRG_PG6_KEYVAL_PRG_PG6_Pos)) /* Assignment of value for KEYVAL_PRG_PG6 in the FUSES_KEYVAL_PRG_PG6 register */
+#define FUSES_KEYVAL_PRG_PG6_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_PRG_PG6) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_PRG_PG7 : (FUSES Offset: 0x4FC) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_PRG_PG7_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_PRG_PG7) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_PRG_PG7_KEYVAL_PRG_PG7_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_PRG_PG7)  Position */
+#define FUSES_KEYVAL_PRG_PG7_KEYVAL_PRG_PG7_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_PRG_PG7_KEYVAL_PRG_PG7_Pos) /* (FUSES_KEYVAL_PRG_PG7)  Mask */
+#define FUSES_KEYVAL_PRG_PG7_KEYVAL_PRG_PG7(value) (FUSES_KEYVAL_PRG_PG7_KEYVAL_PRG_PG7_Msk & (_UINT32_(value) << FUSES_KEYVAL_PRG_PG7_KEYVAL_PRG_PG7_Pos)) /* Assignment of value for KEYVAL_PRG_PG7 in the FUSES_KEYVAL_PRG_PG7 register */
+#define FUSES_KEYVAL_PRG_PG7_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_PRG_PG7) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL1_0 : (FUSES Offset: 0x500) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL1_0_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL1_0) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL1_0_KEYVAL_SDAL1_0_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL1_0)  Position */
+#define FUSES_KEYVAL_SDAL1_0_KEYVAL_SDAL1_0_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL1_0_KEYVAL_SDAL1_0_Pos) /* (FUSES_KEYVAL_SDAL1_0)  Mask */
+#define FUSES_KEYVAL_SDAL1_0_KEYVAL_SDAL1_0(value) (FUSES_KEYVAL_SDAL1_0_KEYVAL_SDAL1_0_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL1_0_KEYVAL_SDAL1_0_Pos)) /* Assignment of value for KEYVAL_SDAL1_0 in the FUSES_KEYVAL_SDAL1_0 register */
+#define FUSES_KEYVAL_SDAL1_0_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL1_0) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL1_1 : (FUSES Offset: 0x504) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL1_1_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL1_1) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL1_1_KEYVAL_SDAL1_1_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL1_1)  Position */
+#define FUSES_KEYVAL_SDAL1_1_KEYVAL_SDAL1_1_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL1_1_KEYVAL_SDAL1_1_Pos) /* (FUSES_KEYVAL_SDAL1_1)  Mask */
+#define FUSES_KEYVAL_SDAL1_1_KEYVAL_SDAL1_1(value) (FUSES_KEYVAL_SDAL1_1_KEYVAL_SDAL1_1_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL1_1_KEYVAL_SDAL1_1_Pos)) /* Assignment of value for KEYVAL_SDAL1_1 in the FUSES_KEYVAL_SDAL1_1 register */
+#define FUSES_KEYVAL_SDAL1_1_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL1_1) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL1_2 : (FUSES Offset: 0x508) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL1_2_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL1_2) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL1_2_KEYVAL_SDAL1_2_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL1_2)  Position */
+#define FUSES_KEYVAL_SDAL1_2_KEYVAL_SDAL1_2_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL1_2_KEYVAL_SDAL1_2_Pos) /* (FUSES_KEYVAL_SDAL1_2)  Mask */
+#define FUSES_KEYVAL_SDAL1_2_KEYVAL_SDAL1_2(value) (FUSES_KEYVAL_SDAL1_2_KEYVAL_SDAL1_2_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL1_2_KEYVAL_SDAL1_2_Pos)) /* Assignment of value for KEYVAL_SDAL1_2 in the FUSES_KEYVAL_SDAL1_2 register */
+#define FUSES_KEYVAL_SDAL1_2_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL1_2) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL1_3 : (FUSES Offset: 0x50C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL1_3_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL1_3) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL1_3_KEYVAL_SDAL1_3_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL1_3)  Position */
+#define FUSES_KEYVAL_SDAL1_3_KEYVAL_SDAL1_3_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL1_3_KEYVAL_SDAL1_3_Pos) /* (FUSES_KEYVAL_SDAL1_3)  Mask */
+#define FUSES_KEYVAL_SDAL1_3_KEYVAL_SDAL1_3(value) (FUSES_KEYVAL_SDAL1_3_KEYVAL_SDAL1_3_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL1_3_KEYVAL_SDAL1_3_Pos)) /* Assignment of value for KEYVAL_SDAL1_3 in the FUSES_KEYVAL_SDAL1_3 register */
+#define FUSES_KEYVAL_SDAL1_3_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL1_3) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL1_4 : (FUSES Offset: 0x510) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL1_4_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL1_4) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL1_4_KEYVAL_SDAL1_4_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL1_4)  Position */
+#define FUSES_KEYVAL_SDAL1_4_KEYVAL_SDAL1_4_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL1_4_KEYVAL_SDAL1_4_Pos) /* (FUSES_KEYVAL_SDAL1_4)  Mask */
+#define FUSES_KEYVAL_SDAL1_4_KEYVAL_SDAL1_4(value) (FUSES_KEYVAL_SDAL1_4_KEYVAL_SDAL1_4_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL1_4_KEYVAL_SDAL1_4_Pos)) /* Assignment of value for KEYVAL_SDAL1_4 in the FUSES_KEYVAL_SDAL1_4 register */
+#define FUSES_KEYVAL_SDAL1_4_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL1_4) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL1_5 : (FUSES Offset: 0x514) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL1_5_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL1_5) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL1_5_KEYVAL_SDAL1_5_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL1_5)  Position */
+#define FUSES_KEYVAL_SDAL1_5_KEYVAL_SDAL1_5_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL1_5_KEYVAL_SDAL1_5_Pos) /* (FUSES_KEYVAL_SDAL1_5)  Mask */
+#define FUSES_KEYVAL_SDAL1_5_KEYVAL_SDAL1_5(value) (FUSES_KEYVAL_SDAL1_5_KEYVAL_SDAL1_5_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL1_5_KEYVAL_SDAL1_5_Pos)) /* Assignment of value for KEYVAL_SDAL1_5 in the FUSES_KEYVAL_SDAL1_5 register */
+#define FUSES_KEYVAL_SDAL1_5_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL1_5) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL1_6 : (FUSES Offset: 0x518) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL1_6_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL1_6) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL1_6_KEYVAL_SDAL1_6_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL1_6)  Position */
+#define FUSES_KEYVAL_SDAL1_6_KEYVAL_SDAL1_6_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL1_6_KEYVAL_SDAL1_6_Pos) /* (FUSES_KEYVAL_SDAL1_6)  Mask */
+#define FUSES_KEYVAL_SDAL1_6_KEYVAL_SDAL1_6(value) (FUSES_KEYVAL_SDAL1_6_KEYVAL_SDAL1_6_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL1_6_KEYVAL_SDAL1_6_Pos)) /* Assignment of value for KEYVAL_SDAL1_6 in the FUSES_KEYVAL_SDAL1_6 register */
+#define FUSES_KEYVAL_SDAL1_6_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL1_6) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL1_7 : (FUSES Offset: 0x51C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL1_7_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL1_7) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL1_7_KEYVAL_SDAL1_7_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL1_7)  Position */
+#define FUSES_KEYVAL_SDAL1_7_KEYVAL_SDAL1_7_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL1_7_KEYVAL_SDAL1_7_Pos) /* (FUSES_KEYVAL_SDAL1_7)  Mask */
+#define FUSES_KEYVAL_SDAL1_7_KEYVAL_SDAL1_7(value) (FUSES_KEYVAL_SDAL1_7_KEYVAL_SDAL1_7_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL1_7_KEYVAL_SDAL1_7_Pos)) /* Assignment of value for KEYVAL_SDAL1_7 in the FUSES_KEYVAL_SDAL1_7 register */
+#define FUSES_KEYVAL_SDAL1_7_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL1_7) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL0_0 : (FUSES Offset: 0x520) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL0_0_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL0_0) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL0_0_KEYVAL_SDAL0_0_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL0_0)  Position */
+#define FUSES_KEYVAL_SDAL0_0_KEYVAL_SDAL0_0_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL0_0_KEYVAL_SDAL0_0_Pos) /* (FUSES_KEYVAL_SDAL0_0)  Mask */
+#define FUSES_KEYVAL_SDAL0_0_KEYVAL_SDAL0_0(value) (FUSES_KEYVAL_SDAL0_0_KEYVAL_SDAL0_0_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL0_0_KEYVAL_SDAL0_0_Pos)) /* Assignment of value for KEYVAL_SDAL0_0 in the FUSES_KEYVAL_SDAL0_0 register */
+#define FUSES_KEYVAL_SDAL0_0_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL0_0) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL0_1 : (FUSES Offset: 0x524) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL0_1_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL0_1) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL0_1_KEYVAL_SDAL0_1_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL0_1)  Position */
+#define FUSES_KEYVAL_SDAL0_1_KEYVAL_SDAL0_1_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL0_1_KEYVAL_SDAL0_1_Pos) /* (FUSES_KEYVAL_SDAL0_1)  Mask */
+#define FUSES_KEYVAL_SDAL0_1_KEYVAL_SDAL0_1(value) (FUSES_KEYVAL_SDAL0_1_KEYVAL_SDAL0_1_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL0_1_KEYVAL_SDAL0_1_Pos)) /* Assignment of value for KEYVAL_SDAL0_1 in the FUSES_KEYVAL_SDAL0_1 register */
+#define FUSES_KEYVAL_SDAL0_1_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL0_1) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL0_2 : (FUSES Offset: 0x528) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL0_2_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL0_2) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL0_2_KEYVAL_SDAL0_2_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL0_2)  Position */
+#define FUSES_KEYVAL_SDAL0_2_KEYVAL_SDAL0_2_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL0_2_KEYVAL_SDAL0_2_Pos) /* (FUSES_KEYVAL_SDAL0_2)  Mask */
+#define FUSES_KEYVAL_SDAL0_2_KEYVAL_SDAL0_2(value) (FUSES_KEYVAL_SDAL0_2_KEYVAL_SDAL0_2_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL0_2_KEYVAL_SDAL0_2_Pos)) /* Assignment of value for KEYVAL_SDAL0_2 in the FUSES_KEYVAL_SDAL0_2 register */
+#define FUSES_KEYVAL_SDAL0_2_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL0_2) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL0_3 : (FUSES Offset: 0x52C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL0_3_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL0_3) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL0_3_KEYVAL_SDAL0_3_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL0_3)  Position */
+#define FUSES_KEYVAL_SDAL0_3_KEYVAL_SDAL0_3_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL0_3_KEYVAL_SDAL0_3_Pos) /* (FUSES_KEYVAL_SDAL0_3)  Mask */
+#define FUSES_KEYVAL_SDAL0_3_KEYVAL_SDAL0_3(value) (FUSES_KEYVAL_SDAL0_3_KEYVAL_SDAL0_3_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL0_3_KEYVAL_SDAL0_3_Pos)) /* Assignment of value for KEYVAL_SDAL0_3 in the FUSES_KEYVAL_SDAL0_3 register */
+#define FUSES_KEYVAL_SDAL0_3_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL0_3) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL0_4 : (FUSES Offset: 0x530) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL0_4_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL0_4) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL0_4_KEYVAL_SDAL0_4_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL0_4)  Position */
+#define FUSES_KEYVAL_SDAL0_4_KEYVAL_SDAL0_4_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL0_4_KEYVAL_SDAL0_4_Pos) /* (FUSES_KEYVAL_SDAL0_4)  Mask */
+#define FUSES_KEYVAL_SDAL0_4_KEYVAL_SDAL0_4(value) (FUSES_KEYVAL_SDAL0_4_KEYVAL_SDAL0_4_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL0_4_KEYVAL_SDAL0_4_Pos)) /* Assignment of value for KEYVAL_SDAL0_4 in the FUSES_KEYVAL_SDAL0_4 register */
+#define FUSES_KEYVAL_SDAL0_4_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL0_4) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL0_5 : (FUSES Offset: 0x534) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL0_5_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL0_5) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL0_5_KEYVAL_SDAL0_5_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL0_5)  Position */
+#define FUSES_KEYVAL_SDAL0_5_KEYVAL_SDAL0_5_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL0_5_KEYVAL_SDAL0_5_Pos) /* (FUSES_KEYVAL_SDAL0_5)  Mask */
+#define FUSES_KEYVAL_SDAL0_5_KEYVAL_SDAL0_5(value) (FUSES_KEYVAL_SDAL0_5_KEYVAL_SDAL0_5_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL0_5_KEYVAL_SDAL0_5_Pos)) /* Assignment of value for KEYVAL_SDAL0_5 in the FUSES_KEYVAL_SDAL0_5 register */
+#define FUSES_KEYVAL_SDAL0_5_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL0_5) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL0_6 : (FUSES Offset: 0x538) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL0_6_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL0_6) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL0_6_KEYVAL_SDAL0_6_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL0_6)  Position */
+#define FUSES_KEYVAL_SDAL0_6_KEYVAL_SDAL0_6_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL0_6_KEYVAL_SDAL0_6_Pos) /* (FUSES_KEYVAL_SDAL0_6)  Mask */
+#define FUSES_KEYVAL_SDAL0_6_KEYVAL_SDAL0_6(value) (FUSES_KEYVAL_SDAL0_6_KEYVAL_SDAL0_6_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL0_6_KEYVAL_SDAL0_6_Pos)) /* Assignment of value for KEYVAL_SDAL0_6 in the FUSES_KEYVAL_SDAL0_6 register */
+#define FUSES_KEYVAL_SDAL0_6_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL0_6) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_SDAL0_7 : (FUSES Offset: 0x53C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_SDAL0_7_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_SDAL0_7) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_SDAL0_7_KEYVAL_SDAL0_7_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_SDAL0_7)  Position */
+#define FUSES_KEYVAL_SDAL0_7_KEYVAL_SDAL0_7_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_SDAL0_7_KEYVAL_SDAL0_7_Pos) /* (FUSES_KEYVAL_SDAL0_7)  Mask */
+#define FUSES_KEYVAL_SDAL0_7_KEYVAL_SDAL0_7(value) (FUSES_KEYVAL_SDAL0_7_KEYVAL_SDAL0_7_Msk & (_UINT32_(value) << FUSES_KEYVAL_SDAL0_7_KEYVAL_SDAL0_7_Pos)) /* Assignment of value for KEYVAL_SDAL0_7 in the FUSES_KEYVAL_SDAL0_7 register */
+#define FUSES_KEYVAL_SDAL0_7_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_SDAL0_7) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_DAL_EL0 : (FUSES Offset: 0x540) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_DAL_EL0_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_DAL_EL0) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_DAL_EL0_KEYVAL_DAL_EL0_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_DAL_EL0)  Position */
+#define FUSES_KEYVAL_DAL_EL0_KEYVAL_DAL_EL0_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_DAL_EL0_KEYVAL_DAL_EL0_Pos) /* (FUSES_KEYVAL_DAL_EL0)  Mask */
+#define FUSES_KEYVAL_DAL_EL0_KEYVAL_DAL_EL0(value) (FUSES_KEYVAL_DAL_EL0_KEYVAL_DAL_EL0_Msk & (_UINT32_(value) << FUSES_KEYVAL_DAL_EL0_KEYVAL_DAL_EL0_Pos)) /* Assignment of value for KEYVAL_DAL_EL0 in the FUSES_KEYVAL_DAL_EL0 register */
+#define FUSES_KEYVAL_DAL_EL0_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_DAL_EL0) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_DAL_EL1 : (FUSES Offset: 0x544) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_DAL_EL1_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_DAL_EL1) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_DAL_EL1_KEYVAL_DAL_EL1_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_DAL_EL1)  Position */
+#define FUSES_KEYVAL_DAL_EL1_KEYVAL_DAL_EL1_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_DAL_EL1_KEYVAL_DAL_EL1_Pos) /* (FUSES_KEYVAL_DAL_EL1)  Mask */
+#define FUSES_KEYVAL_DAL_EL1_KEYVAL_DAL_EL1(value) (FUSES_KEYVAL_DAL_EL1_KEYVAL_DAL_EL1_Msk & (_UINT32_(value) << FUSES_KEYVAL_DAL_EL1_KEYVAL_DAL_EL1_Pos)) /* Assignment of value for KEYVAL_DAL_EL1 in the FUSES_KEYVAL_DAL_EL1 register */
+#define FUSES_KEYVAL_DAL_EL1_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_DAL_EL1) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_DAL_EL2 : (FUSES Offset: 0x548) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_DAL_EL2_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_DAL_EL2) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_DAL_EL2_KEYVAL_DAL_EL2_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_DAL_EL2)  Position */
+#define FUSES_KEYVAL_DAL_EL2_KEYVAL_DAL_EL2_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_DAL_EL2_KEYVAL_DAL_EL2_Pos) /* (FUSES_KEYVAL_DAL_EL2)  Mask */
+#define FUSES_KEYVAL_DAL_EL2_KEYVAL_DAL_EL2(value) (FUSES_KEYVAL_DAL_EL2_KEYVAL_DAL_EL2_Msk & (_UINT32_(value) << FUSES_KEYVAL_DAL_EL2_KEYVAL_DAL_EL2_Pos)) /* Assignment of value for KEYVAL_DAL_EL2 in the FUSES_KEYVAL_DAL_EL2 register */
+#define FUSES_KEYVAL_DAL_EL2_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_DAL_EL2) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_DAL_EL3 : (FUSES Offset: 0x54C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_DAL_EL3_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_DAL_EL3) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_DAL_EL3_KEYVAL_DAL_EL3_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_DAL_EL3)  Position */
+#define FUSES_KEYVAL_DAL_EL3_KEYVAL_DAL_EL3_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_DAL_EL3_KEYVAL_DAL_EL3_Pos) /* (FUSES_KEYVAL_DAL_EL3)  Mask */
+#define FUSES_KEYVAL_DAL_EL3_KEYVAL_DAL_EL3(value) (FUSES_KEYVAL_DAL_EL3_KEYVAL_DAL_EL3_Msk & (_UINT32_(value) << FUSES_KEYVAL_DAL_EL3_KEYVAL_DAL_EL3_Pos)) /* Assignment of value for KEYVAL_DAL_EL3 in the FUSES_KEYVAL_DAL_EL3 register */
+#define FUSES_KEYVAL_DAL_EL3_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_DAL_EL3) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_DAL_EL4 : (FUSES Offset: 0x550) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_DAL_EL4_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_DAL_EL4) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_DAL_EL4_KEYVAL_DAL_EL4_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_DAL_EL4)  Position */
+#define FUSES_KEYVAL_DAL_EL4_KEYVAL_DAL_EL4_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_DAL_EL4_KEYVAL_DAL_EL4_Pos) /* (FUSES_KEYVAL_DAL_EL4)  Mask */
+#define FUSES_KEYVAL_DAL_EL4_KEYVAL_DAL_EL4(value) (FUSES_KEYVAL_DAL_EL4_KEYVAL_DAL_EL4_Msk & (_UINT32_(value) << FUSES_KEYVAL_DAL_EL4_KEYVAL_DAL_EL4_Pos)) /* Assignment of value for KEYVAL_DAL_EL4 in the FUSES_KEYVAL_DAL_EL4 register */
+#define FUSES_KEYVAL_DAL_EL4_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_DAL_EL4) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_DAL_EL5 : (FUSES Offset: 0x554) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_DAL_EL5_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_DAL_EL5) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_DAL_EL5_KEYVAL_DAL_EL5_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_DAL_EL5)  Position */
+#define FUSES_KEYVAL_DAL_EL5_KEYVAL_DAL_EL5_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_DAL_EL5_KEYVAL_DAL_EL5_Pos) /* (FUSES_KEYVAL_DAL_EL5)  Mask */
+#define FUSES_KEYVAL_DAL_EL5_KEYVAL_DAL_EL5(value) (FUSES_KEYVAL_DAL_EL5_KEYVAL_DAL_EL5_Msk & (_UINT32_(value) << FUSES_KEYVAL_DAL_EL5_KEYVAL_DAL_EL5_Pos)) /* Assignment of value for KEYVAL_DAL_EL5 in the FUSES_KEYVAL_DAL_EL5 register */
+#define FUSES_KEYVAL_DAL_EL5_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_DAL_EL5) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_DAL_EL6 : (FUSES Offset: 0x558) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_DAL_EL6_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_DAL_EL6) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_DAL_EL6_KEYVAL_DAL_EL6_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_DAL_EL6)  Position */
+#define FUSES_KEYVAL_DAL_EL6_KEYVAL_DAL_EL6_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_DAL_EL6_KEYVAL_DAL_EL6_Pos) /* (FUSES_KEYVAL_DAL_EL6)  Mask */
+#define FUSES_KEYVAL_DAL_EL6_KEYVAL_DAL_EL6(value) (FUSES_KEYVAL_DAL_EL6_KEYVAL_DAL_EL6_Msk & (_UINT32_(value) << FUSES_KEYVAL_DAL_EL6_KEYVAL_DAL_EL6_Pos)) /* Assignment of value for KEYVAL_DAL_EL6 in the FUSES_KEYVAL_DAL_EL6 register */
+#define FUSES_KEYVAL_DAL_EL6_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_DAL_EL6) Register Mask  */
+
+
+/* -------- FUSES_KEYVAL_DAL_EL7 : (FUSES Offset: 0x55C) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_KEYVAL_DAL_EL7_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_KEYVAL_DAL_EL7) Mapped Fuse Register  Reset Value */
+
+#define FUSES_KEYVAL_DAL_EL7_KEYVAL_DAL_EL7_Pos _UINT32_(0)                                          /* (FUSES_KEYVAL_DAL_EL7)  Position */
+#define FUSES_KEYVAL_DAL_EL7_KEYVAL_DAL_EL7_Msk (_UINT32_(0xFFFFFFFF) << FUSES_KEYVAL_DAL_EL7_KEYVAL_DAL_EL7_Pos) /* (FUSES_KEYVAL_DAL_EL7)  Mask */
+#define FUSES_KEYVAL_DAL_EL7_KEYVAL_DAL_EL7(value) (FUSES_KEYVAL_DAL_EL7_KEYVAL_DAL_EL7_Msk & (_UINT32_(value) << FUSES_KEYVAL_DAL_EL7_KEYVAL_DAL_EL7_Pos)) /* Assignment of value for KEYVAL_DAL_EL7 in the FUSES_KEYVAL_DAL_EL7 register */
+#define FUSES_KEYVAL_DAL_EL7_Msk              _UINT32_(0xFFFFFFFF)                                 /* (FUSES_KEYVAL_DAL_EL7) Register Mask  */
+
+
+/* -------- FUSES_PUF_AC : (FUSES Offset: 0xC00) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_PUF_AC_RESETVALUE               _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_PUF_AC) Mapped Fuse Register  Reset Value */
+
+#define FUSES_PUF_AC_PUF_AC_Pos               _UINT32_(0)                                          /* (FUSES_PUF_AC)  Position */
+#define FUSES_PUF_AC_PUF_AC_Msk               (_UINT32_(0xFFFFFFFF) << FUSES_PUF_AC_PUF_AC_Pos)    /* (FUSES_PUF_AC)  Mask */
+#define FUSES_PUF_AC_PUF_AC(value)            (FUSES_PUF_AC_PUF_AC_Msk & (_UINT32_(value) << FUSES_PUF_AC_PUF_AC_Pos)) /* Assignment of value for PUF_AC in the FUSES_PUF_AC register */
+#define FUSES_PUF_AC_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (FUSES_PUF_AC) Register Mask  */
+
+
+/* -------- FUSES_DEVSIGN : (FUSES Offset: 0x0C) (R/W 32) DEVSIGN -------- */
+#define FUSES_DEVSIGN_RESETVALUE              _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_DEVSIGN) DEVSIGN  Reset Value */
+
+#define FUSES_DEVSIGN_SEQ_Pos                 _UINT32_(0)                                          /* (FUSES_DEVSIGN) Sequence number Position */
+#define FUSES_DEVSIGN_SEQ_Msk                 (_UINT32_(0xFFFF) << FUSES_DEVSIGN_SEQ_Pos)          /* (FUSES_DEVSIGN) Sequence number Mask */
+#define FUSES_DEVSIGN_SEQ(value)              (FUSES_DEVSIGN_SEQ_Msk & (_UINT32_(value) << FUSES_DEVSIGN_SEQ_Pos)) /* Assignment of value for SEQ in the FUSES_DEVSIGN register */
+#define FUSES_DEVSIGN_SEQBAR_Pos              _UINT32_(16)                                         /* (FUSES_DEVSIGN) Sequence number BAR Position */
+#define FUSES_DEVSIGN_SEQBAR_Msk              (_UINT32_(0xFFFF) << FUSES_DEVSIGN_SEQBAR_Pos)       /* (FUSES_DEVSIGN) Sequence number BAR Mask */
+#define FUSES_DEVSIGN_SEQBAR(value)           (FUSES_DEVSIGN_SEQBAR_Msk & (_UINT32_(value) << FUSES_DEVSIGN_SEQBAR_Pos)) /* Assignment of value for SEQBAR in the FUSES_DEVSIGN register */
+#define FUSES_DEVSIGN_Msk                     _UINT32_(0xFFFFFFFF)                                 /* (FUSES_DEVSIGN) Register Mask  */
+
+
+/* -------- FUSES_BOOT_FLAG : (FUSES Offset: 0x800) (R/W 32) BOOT CODE FLAGS REGISTER -------- */
+#define FUSES_BOOT_FLAG_RESETVALUE            _UINT32_(0xFFFFFFF9)                                 /*  (FUSES_BOOT_FLAG) BOOT CODE FLAGS REGISTER  Reset Value */
+
+#define FUSES_BOOT_FLAG_PUFRETRY_Pos          _UINT32_(1)                                          /* (FUSES_BOOT_FLAG) PUF Retry Position */
+#define FUSES_BOOT_FLAG_PUFRETRY_Msk          (_UINT32_(0x1) << FUSES_BOOT_FLAG_PUFRETRY_Pos)      /* (FUSES_BOOT_FLAG) PUF Retry Mask */
+#define FUSES_BOOT_FLAG_PUFRETRY(value)       (FUSES_BOOT_FLAG_PUFRETRY_Msk & (_UINT32_(value) << FUSES_BOOT_FLAG_PUFRETRY_Pos)) /* Assignment of value for PUFRETRY in the FUSES_BOOT_FLAG register */
+#define FUSES_BOOT_FLAG_PUFSTARTUP_Pos        _UINT32_(2)                                          /* (FUSES_BOOT_FLAG) PUF Start Up Mode Position */
+#define FUSES_BOOT_FLAG_PUFSTARTUP_Msk        (_UINT32_(0x1) << FUSES_BOOT_FLAG_PUFSTARTUP_Pos)    /* (FUSES_BOOT_FLAG) PUF Start Up Mode Mask */
+#define FUSES_BOOT_FLAG_PUFSTARTUP(value)     (FUSES_BOOT_FLAG_PUFSTARTUP_Msk & (_UINT32_(value) << FUSES_BOOT_FLAG_PUFSTARTUP_Pos)) /* Assignment of value for PUFSTARTUP in the FUSES_BOOT_FLAG register */
+#define FUSES_BOOT_FLAG_DICEDIS_Pos           _UINT32_(3)                                          /* (FUSES_BOOT_FLAG) Device Identifier Composition Engine Disable Position */
+#define FUSES_BOOT_FLAG_DICEDIS_Msk           (_UINT32_(0x1) << FUSES_BOOT_FLAG_DICEDIS_Pos)       /* (FUSES_BOOT_FLAG) Device Identifier Composition Engine Disable Mask */
+#define FUSES_BOOT_FLAG_DICEDIS(value)        (FUSES_BOOT_FLAG_DICEDIS_Msk & (_UINT32_(value) << FUSES_BOOT_FLAG_DICEDIS_Pos)) /* Assignment of value for DICEDIS in the FUSES_BOOT_FLAG register */
+#define FUSES_BOOT_FLAG_BOOTMODE_Pos          _UINT32_(4)                                          /* (FUSES_BOOT_FLAG) Boot Mode Position */
+#define FUSES_BOOT_FLAG_BOOTMODE_Msk          (_UINT32_(0x1) << FUSES_BOOT_FLAG_BOOTMODE_Pos)      /* (FUSES_BOOT_FLAG) Boot Mode Mask */
+#define FUSES_BOOT_FLAG_BOOTMODE(value)       (FUSES_BOOT_FLAG_BOOTMODE_Msk & (_UINT32_(value) << FUSES_BOOT_FLAG_BOOTMODE_Pos)) /* Assignment of value for BOOTMODE in the FUSES_BOOT_FLAG register */
+#define FUSES_BOOT_FLAG_RAM_INIT_ENB_Pos      _UINT32_(6)                                          /* (FUSES_BOOT_FLAG) RAM ECC Enable Position */
+#define FUSES_BOOT_FLAG_RAM_INIT_ENB_Msk      (_UINT32_(0x1) << FUSES_BOOT_FLAG_RAM_INIT_ENB_Pos)  /* (FUSES_BOOT_FLAG) RAM ECC Enable Mask */
+#define FUSES_BOOT_FLAG_RAM_INIT_ENB(value)   (FUSES_BOOT_FLAG_RAM_INIT_ENB_Msk & (_UINT32_(value) << FUSES_BOOT_FLAG_RAM_INIT_ENB_Pos)) /* Assignment of value for RAM_INIT_ENB in the FUSES_BOOT_FLAG register */
+#define FUSES_BOOT_FLAG_PUFSCORE_Pos          _UINT32_(8)                                          /* (FUSES_BOOT_FLAG) PUF Score Value Position */
+#define FUSES_BOOT_FLAG_PUFSCORE_Msk          (_UINT32_(0x7) << FUSES_BOOT_FLAG_PUFSCORE_Pos)      /* (FUSES_BOOT_FLAG) PUF Score Value Mask */
+#define FUSES_BOOT_FLAG_PUFSCORE(value)       (FUSES_BOOT_FLAG_PUFSCORE_Msk & (_UINT32_(value) << FUSES_BOOT_FLAG_PUFSCORE_Pos)) /* Assignment of value for PUFSCORE in the FUSES_BOOT_FLAG register */
+#define   FUSES_BOOT_FLAG_PUFSCORE_0_Val      _UINT32_(0x0)                                        /* (FUSES_BOOT_FLAG) 0  */
+#define   FUSES_BOOT_FLAG_PUFSCORE_1_Val      _UINT32_(0x1)                                        /* (FUSES_BOOT_FLAG) 1  */
+#define   FUSES_BOOT_FLAG_PUFSCORE_2_Val      _UINT32_(0x2)                                        /* (FUSES_BOOT_FLAG) 2  */
+#define   FUSES_BOOT_FLAG_PUFSCORE_3_Val      _UINT32_(0x3)                                        /* (FUSES_BOOT_FLAG) 3  */
+#define   FUSES_BOOT_FLAG_PUFSCORE_4_Val      _UINT32_(0x4)                                        /* (FUSES_BOOT_FLAG) 4  */
+#define   FUSES_BOOT_FLAG_PUFSCORE_5_Val      _UINT32_(0x5)                                        /* (FUSES_BOOT_FLAG) 5  */
+#define   FUSES_BOOT_FLAG_PUFSCORE_6_Val      _UINT32_(0x6)                                        /* (FUSES_BOOT_FLAG) 6  */
+#define   FUSES_BOOT_FLAG_PUFSCORE_7_Val      _UINT32_(0x7)                                        /* (FUSES_BOOT_FLAG) 7  */
+#define FUSES_BOOT_FLAG_PUFSCORE_0            (FUSES_BOOT_FLAG_PUFSCORE_0_Val << FUSES_BOOT_FLAG_PUFSCORE_Pos) /* (FUSES_BOOT_FLAG) 0 Position */
+#define FUSES_BOOT_FLAG_PUFSCORE_1            (FUSES_BOOT_FLAG_PUFSCORE_1_Val << FUSES_BOOT_FLAG_PUFSCORE_Pos) /* (FUSES_BOOT_FLAG) 1 Position */
+#define FUSES_BOOT_FLAG_PUFSCORE_2            (FUSES_BOOT_FLAG_PUFSCORE_2_Val << FUSES_BOOT_FLAG_PUFSCORE_Pos) /* (FUSES_BOOT_FLAG) 2 Position */
+#define FUSES_BOOT_FLAG_PUFSCORE_3            (FUSES_BOOT_FLAG_PUFSCORE_3_Val << FUSES_BOOT_FLAG_PUFSCORE_Pos) /* (FUSES_BOOT_FLAG) 3 Position */
+#define FUSES_BOOT_FLAG_PUFSCORE_4            (FUSES_BOOT_FLAG_PUFSCORE_4_Val << FUSES_BOOT_FLAG_PUFSCORE_Pos) /* (FUSES_BOOT_FLAG) 4 Position */
+#define FUSES_BOOT_FLAG_PUFSCORE_5            (FUSES_BOOT_FLAG_PUFSCORE_5_Val << FUSES_BOOT_FLAG_PUFSCORE_Pos) /* (FUSES_BOOT_FLAG) 5 Position */
+#define FUSES_BOOT_FLAG_PUFSCORE_6            (FUSES_BOOT_FLAG_PUFSCORE_6_Val << FUSES_BOOT_FLAG_PUFSCORE_Pos) /* (FUSES_BOOT_FLAG) 6 Position */
+#define FUSES_BOOT_FLAG_PUFSCORE_7            (FUSES_BOOT_FLAG_PUFSCORE_7_Val << FUSES_BOOT_FLAG_PUFSCORE_Pos) /* (FUSES_BOOT_FLAG) 7 Position */
+#define FUSES_BOOT_FLAG_Msk                   _UINT32_(0x0000075E)                                 /* (FUSES_BOOT_FLAG) Register Mask  */
+
+
+/* -------- FUSES_DICE_CDI_INDEX : (FUSES Offset: 0x810) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_DICE_CDI_INDEX_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_DICE_CDI_INDEX) Mapped Fuse Register  Reset Value */
+
+#define FUSES_DICE_CDI_INDEX_DICE_CDI_INDEX_Pos _UINT32_(0)                                          /* (FUSES_DICE_CDI_INDEX)  Position */
+#define FUSES_DICE_CDI_INDEX_DICE_CDI_INDEX_Msk (_UINT32_(0x7F) << FUSES_DICE_CDI_INDEX_DICE_CDI_INDEX_Pos) /* (FUSES_DICE_CDI_INDEX)  Mask */
+#define FUSES_DICE_CDI_INDEX_DICE_CDI_INDEX(value) (FUSES_DICE_CDI_INDEX_DICE_CDI_INDEX_Msk & (_UINT32_(value) << FUSES_DICE_CDI_INDEX_DICE_CDI_INDEX_Pos)) /* Assignment of value for DICE_CDI_INDEX in the FUSES_DICE_CDI_INDEX register */
+#define FUSES_DICE_CDI_INDEX_Msk              _UINT32_(0x0000007F)                                 /* (FUSES_DICE_CDI_INDEX) Register Mask  */
+
+
+/* -------- FUSES_DICE_FW_HASH_INDEX : (FUSES Offset: 0x814) (R/W 32) Mapped Fuse Register -------- */
+#define FUSES_DICE_FW_HASH_INDEX_RESETVALUE   _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_DICE_FW_HASH_INDEX) Mapped Fuse Register  Reset Value */
+
+#define FUSES_DICE_FW_HASH_INDEX_DICE_FW_HASH_INDEX_Pos _UINT32_(0)                                          /* (FUSES_DICE_FW_HASH_INDEX)  Position */
+#define FUSES_DICE_FW_HASH_INDEX_DICE_FW_HASH_INDEX_Msk (_UINT32_(0x7F) << FUSES_DICE_FW_HASH_INDEX_DICE_FW_HASH_INDEX_Pos) /* (FUSES_DICE_FW_HASH_INDEX)  Mask */
+#define FUSES_DICE_FW_HASH_INDEX_DICE_FW_HASH_INDEX(value) (FUSES_DICE_FW_HASH_INDEX_DICE_FW_HASH_INDEX_Msk & (_UINT32_(value) << FUSES_DICE_FW_HASH_INDEX_DICE_FW_HASH_INDEX_Pos)) /* Assignment of value for DICE_FW_HASH_INDEX in the FUSES_DICE_FW_HASH_INDEX register */
+#define FUSES_DICE_FW_HASH_INDEX_Msk          _UINT32_(0x0000007F)                                 /* (FUSES_DICE_FW_HASH_INDEX) Register Mask  */
+
+
+/* -------- FUSES_BOOT_GPIOSEL : (FUSES Offset: 0x818) (R/W 32) BOOT EXTERNAL NOTIFICATION IO PIN REGISTER -------- */
+#define FUSES_BOOT_GPIOSEL_RESETVALUE         _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_BOOT_GPIOSEL) BOOT EXTERNAL NOTIFICATION IO PIN REGISTER  Reset Value */
+
+#define FUSES_BOOT_GPIOSEL_GPIOPINSEL_Pos     _UINT32_(0)                                          /* (FUSES_BOOT_GPIOSEL) Selects IO Port Pin for Boot External Notification Signal Position */
+#define FUSES_BOOT_GPIOSEL_GPIOPINSEL_Msk     (_UINT32_(0x1F) << FUSES_BOOT_GPIOSEL_GPIOPINSEL_Pos) /* (FUSES_BOOT_GPIOSEL) Selects IO Port Pin for Boot External Notification Signal Mask */
+#define FUSES_BOOT_GPIOSEL_GPIOPINSEL(value)  (FUSES_BOOT_GPIOSEL_GPIOPINSEL_Msk & (_UINT32_(value) << FUSES_BOOT_GPIOSEL_GPIOPINSEL_Pos)) /* Assignment of value for GPIOPINSEL in the FUSES_BOOT_GPIOSEL register */
+#define FUSES_BOOT_GPIOSEL_GPIOPORTSEL_Pos    _UINT32_(5)                                          /* (FUSES_BOOT_GPIOSEL) Selects IO Port for Boot External Notification Signal Position */
+#define FUSES_BOOT_GPIOSEL_GPIOPORTSEL_Msk    (_UINT32_(0xF) << FUSES_BOOT_GPIOSEL_GPIOPORTSEL_Pos) /* (FUSES_BOOT_GPIOSEL) Selects IO Port for Boot External Notification Signal Mask */
+#define FUSES_BOOT_GPIOSEL_GPIOPORTSEL(value) (FUSES_BOOT_GPIOSEL_GPIOPORTSEL_Msk & (_UINT32_(value) << FUSES_BOOT_GPIOSEL_GPIOPORTSEL_Pos)) /* Assignment of value for GPIOPORTSEL in the FUSES_BOOT_GPIOSEL register */
+#define FUSES_BOOT_GPIOSEL_FLTPOL_Pos         _UINT32_(9)                                          /* (FUSES_BOOT_GPIOSEL) Selects IO Port for Boot External Notification Signal Position */
+#define FUSES_BOOT_GPIOSEL_FLTPOL_Msk         (_UINT32_(0x1) << FUSES_BOOT_GPIOSEL_FLTPOL_Pos)     /* (FUSES_BOOT_GPIOSEL) Selects IO Port for Boot External Notification Signal Mask */
+#define FUSES_BOOT_GPIOSEL_FLTPOL(value)      (FUSES_BOOT_GPIOSEL_FLTPOL_Msk & (_UINT32_(value) << FUSES_BOOT_GPIOSEL_FLTPOL_Pos)) /* Assignment of value for FLTPOL in the FUSES_BOOT_GPIOSEL register */
+#define FUSES_BOOT_GPIOSEL_FLTODRAIN_Pos      _UINT32_(11)                                         /* (FUSES_BOOT_GPIOSEL) Open Drain Control for Boot External Notification Signal Position */
+#define FUSES_BOOT_GPIOSEL_FLTODRAIN_Msk      (_UINT32_(0x1) << FUSES_BOOT_GPIOSEL_FLTODRAIN_Pos)  /* (FUSES_BOOT_GPIOSEL) Open Drain Control for Boot External Notification Signal Mask */
+#define FUSES_BOOT_GPIOSEL_FLTODRAIN(value)   (FUSES_BOOT_GPIOSEL_FLTODRAIN_Msk & (_UINT32_(value) << FUSES_BOOT_GPIOSEL_FLTODRAIN_Pos)) /* Assignment of value for FLTODRAIN in the FUSES_BOOT_GPIOSEL register */
+#define FUSES_BOOT_GPIOSEL_FLTSLEWLIM_Pos     _UINT32_(12)                                         /* (FUSES_BOOT_GPIOSEL) Selects Driver Slew Rate Selection for Boot External Notification Signal Position */
+#define FUSES_BOOT_GPIOSEL_FLTSLEWLIM_Msk     (_UINT32_(0x3) << FUSES_BOOT_GPIOSEL_FLTSLEWLIM_Pos) /* (FUSES_BOOT_GPIOSEL) Selects Driver Slew Rate Selection for Boot External Notification Signal Mask */
+#define FUSES_BOOT_GPIOSEL_FLTSLEWLIM(value)  (FUSES_BOOT_GPIOSEL_FLTSLEWLIM_Msk & (_UINT32_(value) << FUSES_BOOT_GPIOSEL_FLTSLEWLIM_Pos)) /* Assignment of value for FLTSLEWLIM in the FUSES_BOOT_GPIOSEL register */
+#define FUSES_BOOT_GPIOSEL_Msk                _UINT32_(0x00003BFF)                                 /* (FUSES_BOOT_GPIOSEL) Register Mask  */
+
+
+/* -------- FUSES_H2PB0_NONSECCLRA : (FUSES Offset: 0x81C) (R/W 32) Non-Security Clear Register A -------- */
+#define FUSES_H2PB0_NONSECCLRA_RESETVALUE     _UINT32_(0xFFFFFFFE)                                 /*  (FUSES_H2PB0_NONSECCLRA) Non-Security Clear Register A  Reset Value */
+
+#define FUSES_H2PB0_NONSECCLRA_NONSEC0_Pos    _UINT32_(0)                                          /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC0_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC0_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC0(value) (FUSES_H2PB0_NONSECCLRA_NONSEC0_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC0_Pos)) /* Assignment of value for NONSEC0 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC1_Pos    _UINT32_(1)                                          /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC1_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC1_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC1(value) (FUSES_H2PB0_NONSECCLRA_NONSEC1_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC1_Pos)) /* Assignment of value for NONSEC1 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC2_Pos    _UINT32_(2)                                          /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC2_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC2_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC2(value) (FUSES_H2PB0_NONSECCLRA_NONSEC2_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC2_Pos)) /* Assignment of value for NONSEC2 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC3_Pos    _UINT32_(3)                                          /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC3_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC3_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC3(value) (FUSES_H2PB0_NONSECCLRA_NONSEC3_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC3_Pos)) /* Assignment of value for NONSEC3 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC4_Pos    _UINT32_(4)                                          /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC4_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC4_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC4(value) (FUSES_H2PB0_NONSECCLRA_NONSEC4_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC4_Pos)) /* Assignment of value for NONSEC4 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC5_Pos    _UINT32_(5)                                          /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC5_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC5_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC5(value) (FUSES_H2PB0_NONSECCLRA_NONSEC5_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC5_Pos)) /* Assignment of value for NONSEC5 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC6_Pos    _UINT32_(6)                                          /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC6_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC6_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC6(value) (FUSES_H2PB0_NONSECCLRA_NONSEC6_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC6_Pos)) /* Assignment of value for NONSEC6 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC7_Pos    _UINT32_(7)                                          /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC7_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC7_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC7(value) (FUSES_H2PB0_NONSECCLRA_NONSEC7_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC7_Pos)) /* Assignment of value for NONSEC7 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC8_Pos    _UINT32_(8)                                          /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC8_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC8_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC8(value) (FUSES_H2PB0_NONSECCLRA_NONSEC8_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC8_Pos)) /* Assignment of value for NONSEC8 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC9_Pos    _UINT32_(9)                                          /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC9_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC9_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC9(value) (FUSES_H2PB0_NONSECCLRA_NONSEC9_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC9_Pos)) /* Assignment of value for NONSEC9 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC10_Pos   _UINT32_(10)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC10_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC10_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC10(value) (FUSES_H2PB0_NONSECCLRA_NONSEC10_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC10_Pos)) /* Assignment of value for NONSEC10 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC11_Pos   _UINT32_(11)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC11_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC11_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC11(value) (FUSES_H2PB0_NONSECCLRA_NONSEC11_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC11_Pos)) /* Assignment of value for NONSEC11 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC12_Pos   _UINT32_(12)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC12_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC12_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC12(value) (FUSES_H2PB0_NONSECCLRA_NONSEC12_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC12_Pos)) /* Assignment of value for NONSEC12 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC13_Pos   _UINT32_(13)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC13_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC13_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC13(value) (FUSES_H2PB0_NONSECCLRA_NONSEC13_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC13_Pos)) /* Assignment of value for NONSEC13 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC14_Pos   _UINT32_(14)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC14_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC14_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC14(value) (FUSES_H2PB0_NONSECCLRA_NONSEC14_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC14_Pos)) /* Assignment of value for NONSEC14 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC15_Pos   _UINT32_(15)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC15_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC15_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC15(value) (FUSES_H2PB0_NONSECCLRA_NONSEC15_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC15_Pos)) /* Assignment of value for NONSEC15 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC16_Pos   _UINT32_(16)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC16_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC16_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC16(value) (FUSES_H2PB0_NONSECCLRA_NONSEC16_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC16_Pos)) /* Assignment of value for NONSEC16 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC17_Pos   _UINT32_(17)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC17_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC17_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC17(value) (FUSES_H2PB0_NONSECCLRA_NONSEC17_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC17_Pos)) /* Assignment of value for NONSEC17 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC18_Pos   _UINT32_(18)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC18_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC18_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC18(value) (FUSES_H2PB0_NONSECCLRA_NONSEC18_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC18_Pos)) /* Assignment of value for NONSEC18 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC19_Pos   _UINT32_(19)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC19_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC19_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC19(value) (FUSES_H2PB0_NONSECCLRA_NONSEC19_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC19_Pos)) /* Assignment of value for NONSEC19 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC20_Pos   _UINT32_(20)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC20_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC20_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC20(value) (FUSES_H2PB0_NONSECCLRA_NONSEC20_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC20_Pos)) /* Assignment of value for NONSEC20 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC21_Pos   _UINT32_(21)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC21_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC21_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC21(value) (FUSES_H2PB0_NONSECCLRA_NONSEC21_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC21_Pos)) /* Assignment of value for NONSEC21 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC22_Pos   _UINT32_(22)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC22_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC22_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC22(value) (FUSES_H2PB0_NONSECCLRA_NONSEC22_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC22_Pos)) /* Assignment of value for NONSEC22 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC23_Pos   _UINT32_(23)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC23_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC23_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC23(value) (FUSES_H2PB0_NONSECCLRA_NONSEC23_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC23_Pos)) /* Assignment of value for NONSEC23 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC24_Pos   _UINT32_(24)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC24_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC24_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC24(value) (FUSES_H2PB0_NONSECCLRA_NONSEC24_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC24_Pos)) /* Assignment of value for NONSEC24 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC25_Pos   _UINT32_(25)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC25_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC25_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC25(value) (FUSES_H2PB0_NONSECCLRA_NONSEC25_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC25_Pos)) /* Assignment of value for NONSEC25 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC26_Pos   _UINT32_(26)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC26_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC26_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC26(value) (FUSES_H2PB0_NONSECCLRA_NONSEC26_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC26_Pos)) /* Assignment of value for NONSEC26 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC27_Pos   _UINT32_(27)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC27_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC27_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC27(value) (FUSES_H2PB0_NONSECCLRA_NONSEC27_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC27_Pos)) /* Assignment of value for NONSEC27 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC28_Pos   _UINT32_(28)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC28_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC28_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC28(value) (FUSES_H2PB0_NONSECCLRA_NONSEC28_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC28_Pos)) /* Assignment of value for NONSEC28 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC29_Pos   _UINT32_(29)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC29_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC29_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC29(value) (FUSES_H2PB0_NONSECCLRA_NONSEC29_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC29_Pos)) /* Assignment of value for NONSEC29 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC30_Pos   _UINT32_(30)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC30_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC30_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC30(value) (FUSES_H2PB0_NONSECCLRA_NONSEC30_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC30_Pos)) /* Assignment of value for NONSEC30 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC31_Pos   _UINT32_(31)                                         /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC31_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECCLRA_NONSEC31_Pos) /* (FUSES_H2PB0_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC31(value) (FUSES_H2PB0_NONSECCLRA_NONSEC31_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC31_Pos)) /* Assignment of value for NONSEC31 in the FUSES_H2PB0_NONSECCLRA register */
+#define FUSES_H2PB0_NONSECCLRA_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_H2PB0_NONSECCLRA) Register Mask  */
+
+#define FUSES_H2PB0_NONSECCLRA_NONSEC_Pos     _UINT32_(0)                                          /* (FUSES_H2PB0_NONSECCLRA Position) non-security bit for APB Slave k, k=x..3x */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC_Msk     (_UINT32_(0xFFFFFFFF) << FUSES_H2PB0_NONSECCLRA_NONSEC_Pos) /* (FUSES_H2PB0_NONSECCLRA Mask) NONSEC */
+#define FUSES_H2PB0_NONSECCLRA_NONSEC(value)  (FUSES_H2PB0_NONSECCLRA_NONSEC_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECCLRA_NONSEC_Pos)) 
+
+/* -------- FUSES_H2PB0_NONSECSETA : (FUSES Offset: 0x820) (R/W 32) Non-Security SET Register A -------- */
+#define FUSES_H2PB0_NONSECSETA_RESETVALUE     _UINT32_(0x01)                                       /*  (FUSES_H2PB0_NONSECSETA) Non-Security SET Register A  Reset Value */
+
+#define FUSES_H2PB0_NONSECSETA_NONSEC0_Pos    _UINT32_(0)                                          /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC0_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC0_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC0(value) (FUSES_H2PB0_NONSECSETA_NONSEC0_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC0_Pos)) /* Assignment of value for NONSEC0 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC1_Pos    _UINT32_(1)                                          /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC1_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC1_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC1(value) (FUSES_H2PB0_NONSECSETA_NONSEC1_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC1_Pos)) /* Assignment of value for NONSEC1 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC2_Pos    _UINT32_(2)                                          /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC2_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC2_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC2(value) (FUSES_H2PB0_NONSECSETA_NONSEC2_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC2_Pos)) /* Assignment of value for NONSEC2 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC3_Pos    _UINT32_(3)                                          /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC3_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC3_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC3(value) (FUSES_H2PB0_NONSECSETA_NONSEC3_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC3_Pos)) /* Assignment of value for NONSEC3 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC4_Pos    _UINT32_(4)                                          /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC4_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC4_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC4(value) (FUSES_H2PB0_NONSECSETA_NONSEC4_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC4_Pos)) /* Assignment of value for NONSEC4 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC5_Pos    _UINT32_(5)                                          /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC5_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC5_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC5(value) (FUSES_H2PB0_NONSECSETA_NONSEC5_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC5_Pos)) /* Assignment of value for NONSEC5 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC6_Pos    _UINT32_(6)                                          /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC6_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC6_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC6(value) (FUSES_H2PB0_NONSECSETA_NONSEC6_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC6_Pos)) /* Assignment of value for NONSEC6 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC7_Pos    _UINT32_(7)                                          /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC7_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC7_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC7(value) (FUSES_H2PB0_NONSECSETA_NONSEC7_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC7_Pos)) /* Assignment of value for NONSEC7 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC8_Pos    _UINT32_(8)                                          /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC8_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC8_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC8(value) (FUSES_H2PB0_NONSECSETA_NONSEC8_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC8_Pos)) /* Assignment of value for NONSEC8 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC9_Pos    _UINT32_(9)                                          /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC9_Msk    (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC9_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC9(value) (FUSES_H2PB0_NONSECSETA_NONSEC9_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC9_Pos)) /* Assignment of value for NONSEC9 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC10_Pos   _UINT32_(10)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC10_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC10_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC10(value) (FUSES_H2PB0_NONSECSETA_NONSEC10_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC10_Pos)) /* Assignment of value for NONSEC10 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC11_Pos   _UINT32_(11)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC11_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC11_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC11(value) (FUSES_H2PB0_NONSECSETA_NONSEC11_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC11_Pos)) /* Assignment of value for NONSEC11 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC12_Pos   _UINT32_(12)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC12_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC12_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC12(value) (FUSES_H2PB0_NONSECSETA_NONSEC12_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC12_Pos)) /* Assignment of value for NONSEC12 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC13_Pos   _UINT32_(13)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC13_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC13_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC13(value) (FUSES_H2PB0_NONSECSETA_NONSEC13_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC13_Pos)) /* Assignment of value for NONSEC13 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC14_Pos   _UINT32_(14)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC14_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC14_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC14(value) (FUSES_H2PB0_NONSECSETA_NONSEC14_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC14_Pos)) /* Assignment of value for NONSEC14 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC15_Pos   _UINT32_(15)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC15_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC15_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC15(value) (FUSES_H2PB0_NONSECSETA_NONSEC15_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC15_Pos)) /* Assignment of value for NONSEC15 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC16_Pos   _UINT32_(16)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC16_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC16_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC16(value) (FUSES_H2PB0_NONSECSETA_NONSEC16_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC16_Pos)) /* Assignment of value for NONSEC16 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC17_Pos   _UINT32_(17)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC17_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC17_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC17(value) (FUSES_H2PB0_NONSECSETA_NONSEC17_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC17_Pos)) /* Assignment of value for NONSEC17 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC18_Pos   _UINT32_(18)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC18_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC18_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC18(value) (FUSES_H2PB0_NONSECSETA_NONSEC18_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC18_Pos)) /* Assignment of value for NONSEC18 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC19_Pos   _UINT32_(19)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC19_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC19_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC19(value) (FUSES_H2PB0_NONSECSETA_NONSEC19_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC19_Pos)) /* Assignment of value for NONSEC19 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC20_Pos   _UINT32_(20)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC20_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC20_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC20(value) (FUSES_H2PB0_NONSECSETA_NONSEC20_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC20_Pos)) /* Assignment of value for NONSEC20 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC21_Pos   _UINT32_(21)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC21_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC21_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC21(value) (FUSES_H2PB0_NONSECSETA_NONSEC21_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC21_Pos)) /* Assignment of value for NONSEC21 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC22_Pos   _UINT32_(22)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC22_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC22_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC22(value) (FUSES_H2PB0_NONSECSETA_NONSEC22_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC22_Pos)) /* Assignment of value for NONSEC22 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC23_Pos   _UINT32_(23)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC23_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC23_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC23(value) (FUSES_H2PB0_NONSECSETA_NONSEC23_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC23_Pos)) /* Assignment of value for NONSEC23 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC24_Pos   _UINT32_(24)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC24_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC24_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC24(value) (FUSES_H2PB0_NONSECSETA_NONSEC24_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC24_Pos)) /* Assignment of value for NONSEC24 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC25_Pos   _UINT32_(25)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC25_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC25_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC25(value) (FUSES_H2PB0_NONSECSETA_NONSEC25_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC25_Pos)) /* Assignment of value for NONSEC25 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC26_Pos   _UINT32_(26)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC26_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC26_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC26(value) (FUSES_H2PB0_NONSECSETA_NONSEC26_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC26_Pos)) /* Assignment of value for NONSEC26 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC27_Pos   _UINT32_(27)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC27_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC27_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC27(value) (FUSES_H2PB0_NONSECSETA_NONSEC27_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC27_Pos)) /* Assignment of value for NONSEC27 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC28_Pos   _UINT32_(28)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC28_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC28_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC28(value) (FUSES_H2PB0_NONSECSETA_NONSEC28_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC28_Pos)) /* Assignment of value for NONSEC28 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC29_Pos   _UINT32_(29)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC29_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC29_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC29(value) (FUSES_H2PB0_NONSECSETA_NONSEC29_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC29_Pos)) /* Assignment of value for NONSEC29 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC30_Pos   _UINT32_(30)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC30_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC30_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC30(value) (FUSES_H2PB0_NONSECSETA_NONSEC30_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC30_Pos)) /* Assignment of value for NONSEC30 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_NONSEC31_Pos   _UINT32_(31)                                         /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB0_NONSECSETA_NONSEC31_Msk   (_UINT32_(0x1) << FUSES_H2PB0_NONSECSETA_NONSEC31_Pos) /* (FUSES_H2PB0_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB0_NONSECSETA_NONSEC31(value) (FUSES_H2PB0_NONSECSETA_NONSEC31_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC31_Pos)) /* Assignment of value for NONSEC31 in the FUSES_H2PB0_NONSECSETA register */
+#define FUSES_H2PB0_NONSECSETA_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_H2PB0_NONSECSETA) Register Mask  */
+
+#define FUSES_H2PB0_NONSECSETA_NONSEC_Pos     _UINT32_(0)                                          /* (FUSES_H2PB0_NONSECSETA Position) non-security bit for APB Slave k, k=x..3x */
+#define FUSES_H2PB0_NONSECSETA_NONSEC_Msk     (_UINT32_(0xFFFFFFFF) << FUSES_H2PB0_NONSECSETA_NONSEC_Pos) /* (FUSES_H2PB0_NONSECSETA Mask) NONSEC */
+#define FUSES_H2PB0_NONSECSETA_NONSEC(value)  (FUSES_H2PB0_NONSECSETA_NONSEC_Msk & (_UINT32_(value) << FUSES_H2PB0_NONSECSETA_NONSEC_Pos)) 
+
+/* -------- FUSES_PAC_WRCTRL_H2PB0 : (FUSES Offset: 0x830) (R/W 32) Write Control Register -------- */
+#define FUSES_PAC_WRCTRL_H2PB0_RESETVALUE     _UINT32_(0x13)                                       /*  (FUSES_PAC_WRCTRL_H2PB0) Write Control Register  Reset Value */
+
+#define FUSES_PAC_WRCTRL_H2PB0_PERID_Pos      _UINT32_(0)                                          /* (FUSES_PAC_WRCTRL_H2PB0) Peripheral Identifier Position */
+#define FUSES_PAC_WRCTRL_H2PB0_PERID_Msk      (_UINT32_(0xFF) << FUSES_PAC_WRCTRL_H2PB0_PERID_Pos) /* (FUSES_PAC_WRCTRL_H2PB0) Peripheral Identifier Mask */
+#define FUSES_PAC_WRCTRL_H2PB0_PERID(value)   (FUSES_PAC_WRCTRL_H2PB0_PERID_Msk & (_UINT32_(value) << FUSES_PAC_WRCTRL_H2PB0_PERID_Pos)) /* Assignment of value for PERID in the FUSES_PAC_WRCTRL_H2PB0 register */
+#define FUSES_PAC_WRCTRL_H2PB0_KEY_Pos        _UINT32_(16)                                         /* (FUSES_PAC_WRCTRL_H2PB0) Peripheral Access Control Key Position */
+#define FUSES_PAC_WRCTRL_H2PB0_KEY_Msk        (_UINT32_(0xFF) << FUSES_PAC_WRCTRL_H2PB0_KEY_Pos)   /* (FUSES_PAC_WRCTRL_H2PB0) Peripheral Access Control Key Mask */
+#define FUSES_PAC_WRCTRL_H2PB0_KEY(value)     (FUSES_PAC_WRCTRL_H2PB0_KEY_Msk & (_UINT32_(value) << FUSES_PAC_WRCTRL_H2PB0_KEY_Pos)) /* Assignment of value for KEY in the FUSES_PAC_WRCTRL_H2PB0 register */
+#define   FUSES_PAC_WRCTRL_H2PB0_KEY_OFF_Val  _UINT32_(0x0)                                        /* (FUSES_PAC_WRCTRL_H2PB0) OFF - No Action  */
+#define   FUSES_PAC_WRCTRL_H2PB0_KEY_CLEAR_Val _UINT32_(0x1)                                        /* (FUSES_PAC_WRCTRL_H2PB0) CLEAR - Clear the peripheral write protection  */
+#define   FUSES_PAC_WRCTRL_H2PB0_KEY_SET_Val  _UINT32_(0x2)                                        /* (FUSES_PAC_WRCTRL_H2PB0) SET - Set the peripheral write protection  */
+#define   FUSES_PAC_WRCTRL_H2PB0_KEY_LOCK_Val _UINT32_(0x3)                                        /* (FUSES_PAC_WRCTRL_H2PB0) LOCK - Set and Lock the write protection state of the peripheral until the next reset  */
+#define FUSES_PAC_WRCTRL_H2PB0_KEY_OFF        (FUSES_PAC_WRCTRL_H2PB0_KEY_OFF_Val << FUSES_PAC_WRCTRL_H2PB0_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB0) OFF - No Action Position */
+#define FUSES_PAC_WRCTRL_H2PB0_KEY_CLEAR      (FUSES_PAC_WRCTRL_H2PB0_KEY_CLEAR_Val << FUSES_PAC_WRCTRL_H2PB0_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB0) CLEAR - Clear the peripheral write protection Position */
+#define FUSES_PAC_WRCTRL_H2PB0_KEY_SET        (FUSES_PAC_WRCTRL_H2PB0_KEY_SET_Val << FUSES_PAC_WRCTRL_H2PB0_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB0) SET - Set the peripheral write protection Position */
+#define FUSES_PAC_WRCTRL_H2PB0_KEY_LOCK       (FUSES_PAC_WRCTRL_H2PB0_KEY_LOCK_Val << FUSES_PAC_WRCTRL_H2PB0_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB0) LOCK - Set and Lock the write protection state of the peripheral until the next reset Position */
+#define FUSES_PAC_WRCTRL_H2PB0_Msk            _UINT32_(0x00FF00FF)                                 /* (FUSES_PAC_WRCTRL_H2PB0) Register Mask  */
+
+
+/* -------- FUSES_H2PB1_NONSECCLRA : (FUSES Offset: 0x834) (R/W 32) Non-Security Clear Register A -------- */
+#define FUSES_H2PB1_NONSECCLRA_RESETVALUE     _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_H2PB1_NONSECCLRA) Non-Security Clear Register A  Reset Value */
+
+#define FUSES_H2PB1_NONSECCLRA_NONSEC0_Pos    _UINT32_(0)                                          /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC0_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC0_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC0(value) (FUSES_H2PB1_NONSECCLRA_NONSEC0_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC0_Pos)) /* Assignment of value for NONSEC0 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC1_Pos    _UINT32_(1)                                          /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC1_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC1_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC1(value) (FUSES_H2PB1_NONSECCLRA_NONSEC1_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC1_Pos)) /* Assignment of value for NONSEC1 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC2_Pos    _UINT32_(2)                                          /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC2_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC2_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC2(value) (FUSES_H2PB1_NONSECCLRA_NONSEC2_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC2_Pos)) /* Assignment of value for NONSEC2 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC3_Pos    _UINT32_(3)                                          /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC3_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC3_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC3(value) (FUSES_H2PB1_NONSECCLRA_NONSEC3_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC3_Pos)) /* Assignment of value for NONSEC3 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC4_Pos    _UINT32_(4)                                          /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC4_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC4_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC4(value) (FUSES_H2PB1_NONSECCLRA_NONSEC4_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC4_Pos)) /* Assignment of value for NONSEC4 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC5_Pos    _UINT32_(5)                                          /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC5_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC5_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC5(value) (FUSES_H2PB1_NONSECCLRA_NONSEC5_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC5_Pos)) /* Assignment of value for NONSEC5 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC6_Pos    _UINT32_(6)                                          /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC6_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC6_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC6(value) (FUSES_H2PB1_NONSECCLRA_NONSEC6_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC6_Pos)) /* Assignment of value for NONSEC6 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC7_Pos    _UINT32_(7)                                          /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC7_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC7_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC7(value) (FUSES_H2PB1_NONSECCLRA_NONSEC7_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC7_Pos)) /* Assignment of value for NONSEC7 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC8_Pos    _UINT32_(8)                                          /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC8_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC8_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC8(value) (FUSES_H2PB1_NONSECCLRA_NONSEC8_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC8_Pos)) /* Assignment of value for NONSEC8 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC9_Pos    _UINT32_(9)                                          /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC9_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC9_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC9(value) (FUSES_H2PB1_NONSECCLRA_NONSEC9_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC9_Pos)) /* Assignment of value for NONSEC9 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC10_Pos   _UINT32_(10)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC10_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC10_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC10(value) (FUSES_H2PB1_NONSECCLRA_NONSEC10_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC10_Pos)) /* Assignment of value for NONSEC10 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC11_Pos   _UINT32_(11)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC11_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC11_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC11(value) (FUSES_H2PB1_NONSECCLRA_NONSEC11_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC11_Pos)) /* Assignment of value for NONSEC11 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC12_Pos   _UINT32_(12)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC12_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC12_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC12(value) (FUSES_H2PB1_NONSECCLRA_NONSEC12_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC12_Pos)) /* Assignment of value for NONSEC12 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC13_Pos   _UINT32_(13)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC13_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC13_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC13(value) (FUSES_H2PB1_NONSECCLRA_NONSEC13_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC13_Pos)) /* Assignment of value for NONSEC13 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC14_Pos   _UINT32_(14)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC14_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC14_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC14(value) (FUSES_H2PB1_NONSECCLRA_NONSEC14_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC14_Pos)) /* Assignment of value for NONSEC14 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC15_Pos   _UINT32_(15)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC15_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC15_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC15(value) (FUSES_H2PB1_NONSECCLRA_NONSEC15_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC15_Pos)) /* Assignment of value for NONSEC15 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC16_Pos   _UINT32_(16)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC16_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC16_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC16(value) (FUSES_H2PB1_NONSECCLRA_NONSEC16_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC16_Pos)) /* Assignment of value for NONSEC16 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC17_Pos   _UINT32_(17)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC17_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC17_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC17(value) (FUSES_H2PB1_NONSECCLRA_NONSEC17_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC17_Pos)) /* Assignment of value for NONSEC17 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC18_Pos   _UINT32_(18)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC18_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC18_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC18(value) (FUSES_H2PB1_NONSECCLRA_NONSEC18_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC18_Pos)) /* Assignment of value for NONSEC18 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC19_Pos   _UINT32_(19)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC19_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC19_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC19(value) (FUSES_H2PB1_NONSECCLRA_NONSEC19_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC19_Pos)) /* Assignment of value for NONSEC19 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC20_Pos   _UINT32_(20)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC20_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC20_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC20(value) (FUSES_H2PB1_NONSECCLRA_NONSEC20_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC20_Pos)) /* Assignment of value for NONSEC20 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC21_Pos   _UINT32_(21)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC21_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC21_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC21(value) (FUSES_H2PB1_NONSECCLRA_NONSEC21_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC21_Pos)) /* Assignment of value for NONSEC21 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC22_Pos   _UINT32_(22)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC22_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC22_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC22(value) (FUSES_H2PB1_NONSECCLRA_NONSEC22_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC22_Pos)) /* Assignment of value for NONSEC22 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC23_Pos   _UINT32_(23)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC23_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC23_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC23(value) (FUSES_H2PB1_NONSECCLRA_NONSEC23_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC23_Pos)) /* Assignment of value for NONSEC23 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC24_Pos   _UINT32_(24)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC24_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC24_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC24(value) (FUSES_H2PB1_NONSECCLRA_NONSEC24_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC24_Pos)) /* Assignment of value for NONSEC24 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC25_Pos   _UINT32_(25)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC25_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC25_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC25(value) (FUSES_H2PB1_NONSECCLRA_NONSEC25_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC25_Pos)) /* Assignment of value for NONSEC25 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC26_Pos   _UINT32_(26)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC26_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC26_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC26(value) (FUSES_H2PB1_NONSECCLRA_NONSEC26_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC26_Pos)) /* Assignment of value for NONSEC26 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC27_Pos   _UINT32_(27)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC27_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC27_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC27(value) (FUSES_H2PB1_NONSECCLRA_NONSEC27_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC27_Pos)) /* Assignment of value for NONSEC27 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC28_Pos   _UINT32_(28)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC28_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC28_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC28(value) (FUSES_H2PB1_NONSECCLRA_NONSEC28_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC28_Pos)) /* Assignment of value for NONSEC28 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC29_Pos   _UINT32_(29)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC29_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC29_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC29(value) (FUSES_H2PB1_NONSECCLRA_NONSEC29_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC29_Pos)) /* Assignment of value for NONSEC29 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC30_Pos   _UINT32_(30)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC30_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC30_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC30(value) (FUSES_H2PB1_NONSECCLRA_NONSEC30_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC30_Pos)) /* Assignment of value for NONSEC30 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC31_Pos   _UINT32_(31)                                         /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC31_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECCLRA_NONSEC31_Pos) /* (FUSES_H2PB1_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC31(value) (FUSES_H2PB1_NONSECCLRA_NONSEC31_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC31_Pos)) /* Assignment of value for NONSEC31 in the FUSES_H2PB1_NONSECCLRA register */
+#define FUSES_H2PB1_NONSECCLRA_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_H2PB1_NONSECCLRA) Register Mask  */
+
+#define FUSES_H2PB1_NONSECCLRA_NONSEC_Pos     _UINT32_(0)                                          /* (FUSES_H2PB1_NONSECCLRA Position) non-security bit for APB Slave k, k=x..3x */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC_Msk     (_UINT32_(0xFFFFFFFF) << FUSES_H2PB1_NONSECCLRA_NONSEC_Pos) /* (FUSES_H2PB1_NONSECCLRA Mask) NONSEC */
+#define FUSES_H2PB1_NONSECCLRA_NONSEC(value)  (FUSES_H2PB1_NONSECCLRA_NONSEC_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECCLRA_NONSEC_Pos)) 
+
+/* -------- FUSES_H2PB1_NONSECSETA : (FUSES Offset: 0x838) (R/W 32) Non-Security SET Register A -------- */
+#define FUSES_H2PB1_NONSECSETA_RESETVALUE     _UINT32_(0x00)                                       /*  (FUSES_H2PB1_NONSECSETA) Non-Security SET Register A  Reset Value */
+
+#define FUSES_H2PB1_NONSECSETA_NONSEC0_Pos    _UINT32_(0)                                          /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC0_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC0_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC0(value) (FUSES_H2PB1_NONSECSETA_NONSEC0_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC0_Pos)) /* Assignment of value for NONSEC0 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC1_Pos    _UINT32_(1)                                          /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC1_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC1_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC1(value) (FUSES_H2PB1_NONSECSETA_NONSEC1_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC1_Pos)) /* Assignment of value for NONSEC1 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC2_Pos    _UINT32_(2)                                          /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC2_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC2_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC2(value) (FUSES_H2PB1_NONSECSETA_NONSEC2_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC2_Pos)) /* Assignment of value for NONSEC2 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC3_Pos    _UINT32_(3)                                          /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC3_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC3_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC3(value) (FUSES_H2PB1_NONSECSETA_NONSEC3_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC3_Pos)) /* Assignment of value for NONSEC3 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC4_Pos    _UINT32_(4)                                          /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC4_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC4_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC4(value) (FUSES_H2PB1_NONSECSETA_NONSEC4_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC4_Pos)) /* Assignment of value for NONSEC4 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC5_Pos    _UINT32_(5)                                          /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC5_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC5_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC5(value) (FUSES_H2PB1_NONSECSETA_NONSEC5_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC5_Pos)) /* Assignment of value for NONSEC5 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC6_Pos    _UINT32_(6)                                          /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC6_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC6_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC6(value) (FUSES_H2PB1_NONSECSETA_NONSEC6_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC6_Pos)) /* Assignment of value for NONSEC6 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC7_Pos    _UINT32_(7)                                          /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC7_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC7_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC7(value) (FUSES_H2PB1_NONSECSETA_NONSEC7_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC7_Pos)) /* Assignment of value for NONSEC7 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC8_Pos    _UINT32_(8)                                          /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC8_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC8_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC8(value) (FUSES_H2PB1_NONSECSETA_NONSEC8_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC8_Pos)) /* Assignment of value for NONSEC8 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC9_Pos    _UINT32_(9)                                          /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC9_Msk    (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC9_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC9(value) (FUSES_H2PB1_NONSECSETA_NONSEC9_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC9_Pos)) /* Assignment of value for NONSEC9 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC10_Pos   _UINT32_(10)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC10_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC10_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC10(value) (FUSES_H2PB1_NONSECSETA_NONSEC10_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC10_Pos)) /* Assignment of value for NONSEC10 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC11_Pos   _UINT32_(11)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC11_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC11_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC11(value) (FUSES_H2PB1_NONSECSETA_NONSEC11_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC11_Pos)) /* Assignment of value for NONSEC11 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC12_Pos   _UINT32_(12)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC12_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC12_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC12(value) (FUSES_H2PB1_NONSECSETA_NONSEC12_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC12_Pos)) /* Assignment of value for NONSEC12 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC13_Pos   _UINT32_(13)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC13_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC13_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC13(value) (FUSES_H2PB1_NONSECSETA_NONSEC13_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC13_Pos)) /* Assignment of value for NONSEC13 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC14_Pos   _UINT32_(14)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC14_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC14_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC14(value) (FUSES_H2PB1_NONSECSETA_NONSEC14_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC14_Pos)) /* Assignment of value for NONSEC14 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC15_Pos   _UINT32_(15)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC15_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC15_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC15(value) (FUSES_H2PB1_NONSECSETA_NONSEC15_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC15_Pos)) /* Assignment of value for NONSEC15 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC16_Pos   _UINT32_(16)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC16_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC16_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC16(value) (FUSES_H2PB1_NONSECSETA_NONSEC16_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC16_Pos)) /* Assignment of value for NONSEC16 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC17_Pos   _UINT32_(17)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC17_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC17_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC17(value) (FUSES_H2PB1_NONSECSETA_NONSEC17_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC17_Pos)) /* Assignment of value for NONSEC17 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC18_Pos   _UINT32_(18)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC18_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC18_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC18(value) (FUSES_H2PB1_NONSECSETA_NONSEC18_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC18_Pos)) /* Assignment of value for NONSEC18 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC19_Pos   _UINT32_(19)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC19_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC19_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC19(value) (FUSES_H2PB1_NONSECSETA_NONSEC19_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC19_Pos)) /* Assignment of value for NONSEC19 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC20_Pos   _UINT32_(20)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC20_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC20_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC20(value) (FUSES_H2PB1_NONSECSETA_NONSEC20_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC20_Pos)) /* Assignment of value for NONSEC20 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC21_Pos   _UINT32_(21)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC21_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC21_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC21(value) (FUSES_H2PB1_NONSECSETA_NONSEC21_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC21_Pos)) /* Assignment of value for NONSEC21 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC22_Pos   _UINT32_(22)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC22_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC22_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC22(value) (FUSES_H2PB1_NONSECSETA_NONSEC22_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC22_Pos)) /* Assignment of value for NONSEC22 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC23_Pos   _UINT32_(23)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC23_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC23_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC23(value) (FUSES_H2PB1_NONSECSETA_NONSEC23_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC23_Pos)) /* Assignment of value for NONSEC23 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC24_Pos   _UINT32_(24)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC24_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC24_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC24(value) (FUSES_H2PB1_NONSECSETA_NONSEC24_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC24_Pos)) /* Assignment of value for NONSEC24 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC25_Pos   _UINT32_(25)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC25_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC25_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC25(value) (FUSES_H2PB1_NONSECSETA_NONSEC25_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC25_Pos)) /* Assignment of value for NONSEC25 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC26_Pos   _UINT32_(26)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC26_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC26_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC26(value) (FUSES_H2PB1_NONSECSETA_NONSEC26_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC26_Pos)) /* Assignment of value for NONSEC26 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC27_Pos   _UINT32_(27)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC27_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC27_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC27(value) (FUSES_H2PB1_NONSECSETA_NONSEC27_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC27_Pos)) /* Assignment of value for NONSEC27 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC28_Pos   _UINT32_(28)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC28_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC28_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC28(value) (FUSES_H2PB1_NONSECSETA_NONSEC28_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC28_Pos)) /* Assignment of value for NONSEC28 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC29_Pos   _UINT32_(29)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC29_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC29_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC29(value) (FUSES_H2PB1_NONSECSETA_NONSEC29_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC29_Pos)) /* Assignment of value for NONSEC29 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC30_Pos   _UINT32_(30)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC30_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC30_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC30(value) (FUSES_H2PB1_NONSECSETA_NONSEC30_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC30_Pos)) /* Assignment of value for NONSEC30 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_NONSEC31_Pos   _UINT32_(31)                                         /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB1_NONSECSETA_NONSEC31_Msk   (_UINT32_(0x1) << FUSES_H2PB1_NONSECSETA_NONSEC31_Pos) /* (FUSES_H2PB1_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB1_NONSECSETA_NONSEC31(value) (FUSES_H2PB1_NONSECSETA_NONSEC31_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC31_Pos)) /* Assignment of value for NONSEC31 in the FUSES_H2PB1_NONSECSETA register */
+#define FUSES_H2PB1_NONSECSETA_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_H2PB1_NONSECSETA) Register Mask  */
+
+#define FUSES_H2PB1_NONSECSETA_NONSEC_Pos     _UINT32_(0)                                          /* (FUSES_H2PB1_NONSECSETA Position) non-security bit for APB Slave k, k=x..3x */
+#define FUSES_H2PB1_NONSECSETA_NONSEC_Msk     (_UINT32_(0xFFFFFFFF) << FUSES_H2PB1_NONSECSETA_NONSEC_Pos) /* (FUSES_H2PB1_NONSECSETA Mask) NONSEC */
+#define FUSES_H2PB1_NONSECSETA_NONSEC(value)  (FUSES_H2PB1_NONSECSETA_NONSEC_Msk & (_UINT32_(value) << FUSES_H2PB1_NONSECSETA_NONSEC_Pos)) 
+
+/* -------- FUSES_PAC_WRCTRL_H2PB1 : (FUSES Offset: 0x848) (R/W 32) Write Control Register -------- */
+#define FUSES_PAC_WRCTRL_H2PB1_RESETVALUE     _UINT32_(0x2E)                                       /*  (FUSES_PAC_WRCTRL_H2PB1) Write Control Register  Reset Value */
+
+#define FUSES_PAC_WRCTRL_H2PB1_PERID_Pos      _UINT32_(0)                                          /* (FUSES_PAC_WRCTRL_H2PB1) Peripheral Identifier Position */
+#define FUSES_PAC_WRCTRL_H2PB1_PERID_Msk      (_UINT32_(0xFF) << FUSES_PAC_WRCTRL_H2PB1_PERID_Pos) /* (FUSES_PAC_WRCTRL_H2PB1) Peripheral Identifier Mask */
+#define FUSES_PAC_WRCTRL_H2PB1_PERID(value)   (FUSES_PAC_WRCTRL_H2PB1_PERID_Msk & (_UINT32_(value) << FUSES_PAC_WRCTRL_H2PB1_PERID_Pos)) /* Assignment of value for PERID in the FUSES_PAC_WRCTRL_H2PB1 register */
+#define FUSES_PAC_WRCTRL_H2PB1_KEY_Pos        _UINT32_(16)                                         /* (FUSES_PAC_WRCTRL_H2PB1) Peripheral Access Control Key Position */
+#define FUSES_PAC_WRCTRL_H2PB1_KEY_Msk        (_UINT32_(0xFF) << FUSES_PAC_WRCTRL_H2PB1_KEY_Pos)   /* (FUSES_PAC_WRCTRL_H2PB1) Peripheral Access Control Key Mask */
+#define FUSES_PAC_WRCTRL_H2PB1_KEY(value)     (FUSES_PAC_WRCTRL_H2PB1_KEY_Msk & (_UINT32_(value) << FUSES_PAC_WRCTRL_H2PB1_KEY_Pos)) /* Assignment of value for KEY in the FUSES_PAC_WRCTRL_H2PB1 register */
+#define   FUSES_PAC_WRCTRL_H2PB1_KEY_OFF_Val  _UINT32_(0x0)                                        /* (FUSES_PAC_WRCTRL_H2PB1) OFF - No Action  */
+#define   FUSES_PAC_WRCTRL_H2PB1_KEY_CLEAR_Val _UINT32_(0x1)                                        /* (FUSES_PAC_WRCTRL_H2PB1) CLEAR - Clear the peripheral write protection  */
+#define   FUSES_PAC_WRCTRL_H2PB1_KEY_SET_Val  _UINT32_(0x2)                                        /* (FUSES_PAC_WRCTRL_H2PB1) SET - Set the peripheral write protection  */
+#define   FUSES_PAC_WRCTRL_H2PB1_KEY_LOCK_Val _UINT32_(0x3)                                        /* (FUSES_PAC_WRCTRL_H2PB1) LOCK - Set and Lock the write protection state of the peripheral until the next reset  */
+#define FUSES_PAC_WRCTRL_H2PB1_KEY_OFF        (FUSES_PAC_WRCTRL_H2PB1_KEY_OFF_Val << FUSES_PAC_WRCTRL_H2PB1_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB1) OFF - No Action Position */
+#define FUSES_PAC_WRCTRL_H2PB1_KEY_CLEAR      (FUSES_PAC_WRCTRL_H2PB1_KEY_CLEAR_Val << FUSES_PAC_WRCTRL_H2PB1_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB1) CLEAR - Clear the peripheral write protection Position */
+#define FUSES_PAC_WRCTRL_H2PB1_KEY_SET        (FUSES_PAC_WRCTRL_H2PB1_KEY_SET_Val << FUSES_PAC_WRCTRL_H2PB1_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB1) SET - Set the peripheral write protection Position */
+#define FUSES_PAC_WRCTRL_H2PB1_KEY_LOCK       (FUSES_PAC_WRCTRL_H2PB1_KEY_LOCK_Val << FUSES_PAC_WRCTRL_H2PB1_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB1) LOCK - Set and Lock the write protection state of the peripheral until the next reset Position */
+#define FUSES_PAC_WRCTRL_H2PB1_Msk            _UINT32_(0x00FF00FF)                                 /* (FUSES_PAC_WRCTRL_H2PB1) Register Mask  */
+
+
+/* -------- FUSES_H2PB2_NONSECCLRA : (FUSES Offset: 0x84C) (R/W 32) Non-Security Clear Register A -------- */
+#define FUSES_H2PB2_NONSECCLRA_RESETVALUE     _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_H2PB2_NONSECCLRA) Non-Security Clear Register A  Reset Value */
+
+#define FUSES_H2PB2_NONSECCLRA_NONSEC0_Pos    _UINT32_(0)                                          /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC0_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC0_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC0(value) (FUSES_H2PB2_NONSECCLRA_NONSEC0_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC0_Pos)) /* Assignment of value for NONSEC0 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC1_Pos    _UINT32_(1)                                          /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC1_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC1_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC1(value) (FUSES_H2PB2_NONSECCLRA_NONSEC1_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC1_Pos)) /* Assignment of value for NONSEC1 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC2_Pos    _UINT32_(2)                                          /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC2_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC2_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC2(value) (FUSES_H2PB2_NONSECCLRA_NONSEC2_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC2_Pos)) /* Assignment of value for NONSEC2 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC3_Pos    _UINT32_(3)                                          /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC3_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC3_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC3(value) (FUSES_H2PB2_NONSECCLRA_NONSEC3_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC3_Pos)) /* Assignment of value for NONSEC3 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC4_Pos    _UINT32_(4)                                          /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC4_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC4_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC4(value) (FUSES_H2PB2_NONSECCLRA_NONSEC4_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC4_Pos)) /* Assignment of value for NONSEC4 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC5_Pos    _UINT32_(5)                                          /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC5_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC5_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC5(value) (FUSES_H2PB2_NONSECCLRA_NONSEC5_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC5_Pos)) /* Assignment of value for NONSEC5 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC6_Pos    _UINT32_(6)                                          /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC6_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC6_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC6(value) (FUSES_H2PB2_NONSECCLRA_NONSEC6_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC6_Pos)) /* Assignment of value for NONSEC6 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC7_Pos    _UINT32_(7)                                          /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC7_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC7_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC7(value) (FUSES_H2PB2_NONSECCLRA_NONSEC7_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC7_Pos)) /* Assignment of value for NONSEC7 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC8_Pos    _UINT32_(8)                                          /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC8_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC8_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC8(value) (FUSES_H2PB2_NONSECCLRA_NONSEC8_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC8_Pos)) /* Assignment of value for NONSEC8 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC9_Pos    _UINT32_(9)                                          /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC9_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC9_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC9(value) (FUSES_H2PB2_NONSECCLRA_NONSEC9_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC9_Pos)) /* Assignment of value for NONSEC9 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC10_Pos   _UINT32_(10)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC10_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC10_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC10(value) (FUSES_H2PB2_NONSECCLRA_NONSEC10_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC10_Pos)) /* Assignment of value for NONSEC10 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC11_Pos   _UINT32_(11)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC11_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC11_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC11(value) (FUSES_H2PB2_NONSECCLRA_NONSEC11_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC11_Pos)) /* Assignment of value for NONSEC11 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC12_Pos   _UINT32_(12)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC12_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC12_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC12(value) (FUSES_H2PB2_NONSECCLRA_NONSEC12_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC12_Pos)) /* Assignment of value for NONSEC12 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC13_Pos   _UINT32_(13)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC13_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC13_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC13(value) (FUSES_H2PB2_NONSECCLRA_NONSEC13_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC13_Pos)) /* Assignment of value for NONSEC13 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC14_Pos   _UINT32_(14)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC14_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC14_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC14(value) (FUSES_H2PB2_NONSECCLRA_NONSEC14_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC14_Pos)) /* Assignment of value for NONSEC14 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC15_Pos   _UINT32_(15)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC15_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC15_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC15(value) (FUSES_H2PB2_NONSECCLRA_NONSEC15_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC15_Pos)) /* Assignment of value for NONSEC15 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC16_Pos   _UINT32_(16)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC16_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC16_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC16(value) (FUSES_H2PB2_NONSECCLRA_NONSEC16_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC16_Pos)) /* Assignment of value for NONSEC16 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC17_Pos   _UINT32_(17)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC17_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC17_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC17(value) (FUSES_H2PB2_NONSECCLRA_NONSEC17_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC17_Pos)) /* Assignment of value for NONSEC17 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC18_Pos   _UINT32_(18)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC18_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC18_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC18(value) (FUSES_H2PB2_NONSECCLRA_NONSEC18_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC18_Pos)) /* Assignment of value for NONSEC18 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC19_Pos   _UINT32_(19)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC19_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC19_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC19(value) (FUSES_H2PB2_NONSECCLRA_NONSEC19_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC19_Pos)) /* Assignment of value for NONSEC19 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC20_Pos   _UINT32_(20)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC20_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC20_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC20(value) (FUSES_H2PB2_NONSECCLRA_NONSEC20_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC20_Pos)) /* Assignment of value for NONSEC20 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC21_Pos   _UINT32_(21)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC21_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC21_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC21(value) (FUSES_H2PB2_NONSECCLRA_NONSEC21_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC21_Pos)) /* Assignment of value for NONSEC21 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC22_Pos   _UINT32_(22)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC22_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC22_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC22(value) (FUSES_H2PB2_NONSECCLRA_NONSEC22_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC22_Pos)) /* Assignment of value for NONSEC22 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC23_Pos   _UINT32_(23)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC23_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC23_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC23(value) (FUSES_H2PB2_NONSECCLRA_NONSEC23_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC23_Pos)) /* Assignment of value for NONSEC23 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC24_Pos   _UINT32_(24)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC24_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC24_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC24(value) (FUSES_H2PB2_NONSECCLRA_NONSEC24_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC24_Pos)) /* Assignment of value for NONSEC24 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC25_Pos   _UINT32_(25)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC25_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC25_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC25(value) (FUSES_H2PB2_NONSECCLRA_NONSEC25_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC25_Pos)) /* Assignment of value for NONSEC25 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC26_Pos   _UINT32_(26)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC26_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC26_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC26(value) (FUSES_H2PB2_NONSECCLRA_NONSEC26_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC26_Pos)) /* Assignment of value for NONSEC26 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC27_Pos   _UINT32_(27)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC27_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC27_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC27(value) (FUSES_H2PB2_NONSECCLRA_NONSEC27_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC27_Pos)) /* Assignment of value for NONSEC27 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC28_Pos   _UINT32_(28)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC28_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC28_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC28(value) (FUSES_H2PB2_NONSECCLRA_NONSEC28_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC28_Pos)) /* Assignment of value for NONSEC28 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC29_Pos   _UINT32_(29)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC29_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC29_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC29(value) (FUSES_H2PB2_NONSECCLRA_NONSEC29_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC29_Pos)) /* Assignment of value for NONSEC29 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC30_Pos   _UINT32_(30)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC30_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC30_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC30(value) (FUSES_H2PB2_NONSECCLRA_NONSEC30_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC30_Pos)) /* Assignment of value for NONSEC30 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC31_Pos   _UINT32_(31)                                         /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC31_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECCLRA_NONSEC31_Pos) /* (FUSES_H2PB2_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC31(value) (FUSES_H2PB2_NONSECCLRA_NONSEC31_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC31_Pos)) /* Assignment of value for NONSEC31 in the FUSES_H2PB2_NONSECCLRA register */
+#define FUSES_H2PB2_NONSECCLRA_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_H2PB2_NONSECCLRA) Register Mask  */
+
+#define FUSES_H2PB2_NONSECCLRA_NONSEC_Pos     _UINT32_(0)                                          /* (FUSES_H2PB2_NONSECCLRA Position) non-security bit for APB Slave k, k=x..3x */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC_Msk     (_UINT32_(0xFFFFFFFF) << FUSES_H2PB2_NONSECCLRA_NONSEC_Pos) /* (FUSES_H2PB2_NONSECCLRA Mask) NONSEC */
+#define FUSES_H2PB2_NONSECCLRA_NONSEC(value)  (FUSES_H2PB2_NONSECCLRA_NONSEC_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECCLRA_NONSEC_Pos)) 
+
+/* -------- FUSES_H2PB2_NONSECSETA : (FUSES Offset: 0x850) (R/W 32) Non-Security SET Register A -------- */
+#define FUSES_H2PB2_NONSECSETA_RESETVALUE     _UINT32_(0x00)                                       /*  (FUSES_H2PB2_NONSECSETA) Non-Security SET Register A  Reset Value */
+
+#define FUSES_H2PB2_NONSECSETA_NONSEC0_Pos    _UINT32_(0)                                          /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC0_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC0_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC0(value) (FUSES_H2PB2_NONSECSETA_NONSEC0_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC0_Pos)) /* Assignment of value for NONSEC0 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC1_Pos    _UINT32_(1)                                          /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC1_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC1_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC1(value) (FUSES_H2PB2_NONSECSETA_NONSEC1_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC1_Pos)) /* Assignment of value for NONSEC1 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC2_Pos    _UINT32_(2)                                          /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC2_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC2_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC2(value) (FUSES_H2PB2_NONSECSETA_NONSEC2_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC2_Pos)) /* Assignment of value for NONSEC2 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC3_Pos    _UINT32_(3)                                          /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC3_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC3_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC3(value) (FUSES_H2PB2_NONSECSETA_NONSEC3_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC3_Pos)) /* Assignment of value for NONSEC3 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC4_Pos    _UINT32_(4)                                          /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC4_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC4_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC4(value) (FUSES_H2PB2_NONSECSETA_NONSEC4_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC4_Pos)) /* Assignment of value for NONSEC4 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC5_Pos    _UINT32_(5)                                          /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC5_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC5_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC5(value) (FUSES_H2PB2_NONSECSETA_NONSEC5_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC5_Pos)) /* Assignment of value for NONSEC5 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC6_Pos    _UINT32_(6)                                          /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC6_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC6_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC6(value) (FUSES_H2PB2_NONSECSETA_NONSEC6_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC6_Pos)) /* Assignment of value for NONSEC6 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC7_Pos    _UINT32_(7)                                          /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC7_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC7_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC7(value) (FUSES_H2PB2_NONSECSETA_NONSEC7_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC7_Pos)) /* Assignment of value for NONSEC7 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC8_Pos    _UINT32_(8)                                          /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC8_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC8_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC8(value) (FUSES_H2PB2_NONSECSETA_NONSEC8_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC8_Pos)) /* Assignment of value for NONSEC8 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC9_Pos    _UINT32_(9)                                          /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC9_Msk    (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC9_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC9(value) (FUSES_H2PB2_NONSECSETA_NONSEC9_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC9_Pos)) /* Assignment of value for NONSEC9 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC10_Pos   _UINT32_(10)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC10_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC10_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC10(value) (FUSES_H2PB2_NONSECSETA_NONSEC10_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC10_Pos)) /* Assignment of value for NONSEC10 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC11_Pos   _UINT32_(11)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC11_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC11_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC11(value) (FUSES_H2PB2_NONSECSETA_NONSEC11_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC11_Pos)) /* Assignment of value for NONSEC11 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC12_Pos   _UINT32_(12)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC12_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC12_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC12(value) (FUSES_H2PB2_NONSECSETA_NONSEC12_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC12_Pos)) /* Assignment of value for NONSEC12 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC13_Pos   _UINT32_(13)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC13_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC13_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC13(value) (FUSES_H2PB2_NONSECSETA_NONSEC13_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC13_Pos)) /* Assignment of value for NONSEC13 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC14_Pos   _UINT32_(14)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC14_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC14_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC14(value) (FUSES_H2PB2_NONSECSETA_NONSEC14_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC14_Pos)) /* Assignment of value for NONSEC14 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC15_Pos   _UINT32_(15)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC15_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC15_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC15(value) (FUSES_H2PB2_NONSECSETA_NONSEC15_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC15_Pos)) /* Assignment of value for NONSEC15 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC16_Pos   _UINT32_(16)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC16_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC16_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC16(value) (FUSES_H2PB2_NONSECSETA_NONSEC16_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC16_Pos)) /* Assignment of value for NONSEC16 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC17_Pos   _UINT32_(17)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC17_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC17_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC17(value) (FUSES_H2PB2_NONSECSETA_NONSEC17_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC17_Pos)) /* Assignment of value for NONSEC17 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC18_Pos   _UINT32_(18)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC18_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC18_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC18(value) (FUSES_H2PB2_NONSECSETA_NONSEC18_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC18_Pos)) /* Assignment of value for NONSEC18 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC19_Pos   _UINT32_(19)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC19_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC19_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC19(value) (FUSES_H2PB2_NONSECSETA_NONSEC19_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC19_Pos)) /* Assignment of value for NONSEC19 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC20_Pos   _UINT32_(20)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC20_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC20_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC20(value) (FUSES_H2PB2_NONSECSETA_NONSEC20_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC20_Pos)) /* Assignment of value for NONSEC20 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC21_Pos   _UINT32_(21)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC21_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC21_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC21(value) (FUSES_H2PB2_NONSECSETA_NONSEC21_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC21_Pos)) /* Assignment of value for NONSEC21 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC22_Pos   _UINT32_(22)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC22_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC22_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC22(value) (FUSES_H2PB2_NONSECSETA_NONSEC22_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC22_Pos)) /* Assignment of value for NONSEC22 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC23_Pos   _UINT32_(23)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC23_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC23_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC23(value) (FUSES_H2PB2_NONSECSETA_NONSEC23_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC23_Pos)) /* Assignment of value for NONSEC23 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC24_Pos   _UINT32_(24)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC24_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC24_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC24(value) (FUSES_H2PB2_NONSECSETA_NONSEC24_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC24_Pos)) /* Assignment of value for NONSEC24 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC25_Pos   _UINT32_(25)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC25_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC25_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC25(value) (FUSES_H2PB2_NONSECSETA_NONSEC25_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC25_Pos)) /* Assignment of value for NONSEC25 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC26_Pos   _UINT32_(26)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC26_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC26_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC26(value) (FUSES_H2PB2_NONSECSETA_NONSEC26_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC26_Pos)) /* Assignment of value for NONSEC26 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC27_Pos   _UINT32_(27)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC27_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC27_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC27(value) (FUSES_H2PB2_NONSECSETA_NONSEC27_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC27_Pos)) /* Assignment of value for NONSEC27 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC28_Pos   _UINT32_(28)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC28_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC28_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC28(value) (FUSES_H2PB2_NONSECSETA_NONSEC28_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC28_Pos)) /* Assignment of value for NONSEC28 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC29_Pos   _UINT32_(29)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC29_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC29_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC29(value) (FUSES_H2PB2_NONSECSETA_NONSEC29_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC29_Pos)) /* Assignment of value for NONSEC29 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC30_Pos   _UINT32_(30)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC30_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC30_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC30(value) (FUSES_H2PB2_NONSECSETA_NONSEC30_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC30_Pos)) /* Assignment of value for NONSEC30 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_NONSEC31_Pos   _UINT32_(31)                                         /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define FUSES_H2PB2_NONSECSETA_NONSEC31_Msk   (_UINT32_(0x1) << FUSES_H2PB2_NONSECSETA_NONSEC31_Pos) /* (FUSES_H2PB2_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define FUSES_H2PB2_NONSECSETA_NONSEC31(value) (FUSES_H2PB2_NONSECSETA_NONSEC31_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC31_Pos)) /* Assignment of value for NONSEC31 in the FUSES_H2PB2_NONSECSETA register */
+#define FUSES_H2PB2_NONSECSETA_Msk            _UINT32_(0xFFFFFFFF)                                 /* (FUSES_H2PB2_NONSECSETA) Register Mask  */
+
+#define FUSES_H2PB2_NONSECSETA_NONSEC_Pos     _UINT32_(0)                                          /* (FUSES_H2PB2_NONSECSETA Position) non-security bit for APB Slave k, k=x..3x */
+#define FUSES_H2PB2_NONSECSETA_NONSEC_Msk     (_UINT32_(0xFFFFFFFF) << FUSES_H2PB2_NONSECSETA_NONSEC_Pos) /* (FUSES_H2PB2_NONSECSETA Mask) NONSEC */
+#define FUSES_H2PB2_NONSECSETA_NONSEC(value)  (FUSES_H2PB2_NONSECSETA_NONSEC_Msk & (_UINT32_(value) << FUSES_H2PB2_NONSECSETA_NONSEC_Pos)) 
+
+/* -------- FUSES_PAC_WRCTRL_H2PB2 : (FUSES Offset: 0x860) (R/W 32) Write Control Register -------- */
+#define FUSES_PAC_WRCTRL_H2PB2_RESETVALUE     _UINT32_(0x2F)                                       /*  (FUSES_PAC_WRCTRL_H2PB2) Write Control Register  Reset Value */
+
+#define FUSES_PAC_WRCTRL_H2PB2_PERID_Pos      _UINT32_(0)                                          /* (FUSES_PAC_WRCTRL_H2PB2) Peripheral Identifier Position */
+#define FUSES_PAC_WRCTRL_H2PB2_PERID_Msk      (_UINT32_(0xFF) << FUSES_PAC_WRCTRL_H2PB2_PERID_Pos) /* (FUSES_PAC_WRCTRL_H2PB2) Peripheral Identifier Mask */
+#define FUSES_PAC_WRCTRL_H2PB2_PERID(value)   (FUSES_PAC_WRCTRL_H2PB2_PERID_Msk & (_UINT32_(value) << FUSES_PAC_WRCTRL_H2PB2_PERID_Pos)) /* Assignment of value for PERID in the FUSES_PAC_WRCTRL_H2PB2 register */
+#define FUSES_PAC_WRCTRL_H2PB2_KEY_Pos        _UINT32_(16)                                         /* (FUSES_PAC_WRCTRL_H2PB2) Peripheral Access Control Key Position */
+#define FUSES_PAC_WRCTRL_H2PB2_KEY_Msk        (_UINT32_(0xFF) << FUSES_PAC_WRCTRL_H2PB2_KEY_Pos)   /* (FUSES_PAC_WRCTRL_H2PB2) Peripheral Access Control Key Mask */
+#define FUSES_PAC_WRCTRL_H2PB2_KEY(value)     (FUSES_PAC_WRCTRL_H2PB2_KEY_Msk & (_UINT32_(value) << FUSES_PAC_WRCTRL_H2PB2_KEY_Pos)) /* Assignment of value for KEY in the FUSES_PAC_WRCTRL_H2PB2 register */
+#define   FUSES_PAC_WRCTRL_H2PB2_KEY_OFF_Val  _UINT32_(0x0)                                        /* (FUSES_PAC_WRCTRL_H2PB2) OFF - No Action  */
+#define   FUSES_PAC_WRCTRL_H2PB2_KEY_CLEAR_Val _UINT32_(0x1)                                        /* (FUSES_PAC_WRCTRL_H2PB2) CLEAR - Clear the peripheral write protection  */
+#define   FUSES_PAC_WRCTRL_H2PB2_KEY_SET_Val  _UINT32_(0x2)                                        /* (FUSES_PAC_WRCTRL_H2PB2) SET - Set the peripheral write protection  */
+#define   FUSES_PAC_WRCTRL_H2PB2_KEY_LOCK_Val _UINT32_(0x3)                                        /* (FUSES_PAC_WRCTRL_H2PB2) LOCK - Set and Lock the write protection state of the peripheral until the next reset  */
+#define FUSES_PAC_WRCTRL_H2PB2_KEY_OFF        (FUSES_PAC_WRCTRL_H2PB2_KEY_OFF_Val << FUSES_PAC_WRCTRL_H2PB2_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB2) OFF - No Action Position */
+#define FUSES_PAC_WRCTRL_H2PB2_KEY_CLEAR      (FUSES_PAC_WRCTRL_H2PB2_KEY_CLEAR_Val << FUSES_PAC_WRCTRL_H2PB2_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB2) CLEAR - Clear the peripheral write protection Position */
+#define FUSES_PAC_WRCTRL_H2PB2_KEY_SET        (FUSES_PAC_WRCTRL_H2PB2_KEY_SET_Val << FUSES_PAC_WRCTRL_H2PB2_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB2) SET - Set the peripheral write protection Position */
+#define FUSES_PAC_WRCTRL_H2PB2_KEY_LOCK       (FUSES_PAC_WRCTRL_H2PB2_KEY_LOCK_Val << FUSES_PAC_WRCTRL_H2PB2_KEY_Pos) /* (FUSES_PAC_WRCTRL_H2PB2) LOCK - Set and Lock the write protection state of the peripheral until the next reset Position */
+#define FUSES_PAC_WRCTRL_H2PB2_Msk            _UINT32_(0x00FF00FF)                                 /* (FUSES_PAC_WRCTRL_H2PB2) Register Mask  */
+
+
+/* -------- FUSES_IDAU_RCTRL_BFM : (FUSES Offset: 0x864) (R/W 32) Region Control -------- */
+#define FUSES_IDAU_RCTRL_BFM_RESETVALUE       _UINT32_(0x5C000000)                                 /*  (FUSES_IDAU_RCTRL_BFM) Region Control  Reset Value */
+
+#define FUSES_IDAU_RCTRL_BFM_Msk              _UINT32_(0x00000000)                                 /* (FUSES_IDAU_RCTRL_BFM) Register Mask  */
+
+/* BLOCK mode */
+#define FUSES_IDAU_RCTRL_BFM_BLOCK_ARG_Pos    _UINT32_(0)                                          /* (FUSES_IDAU_RCTRL_BFM) IDAU Region Control BFM Command Argument (Block ID) Position */
+#define FUSES_IDAU_RCTRL_BFM_BLOCK_ARG_Msk    (_UINT32_(0x1F) << FUSES_IDAU_RCTRL_BFM_BLOCK_ARG_Pos) /* (FUSES_IDAU_RCTRL_BFM) IDAU Region Control BFM Command Argument (Block ID) Mask */
+#define FUSES_IDAU_RCTRL_BFM_BLOCK_ARG(value) (FUSES_IDAU_RCTRL_BFM_BLOCK_ARG_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_BFM_BLOCK_ARG_Pos))
+#define FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_Pos    _UINT32_(24)                                         /* (FUSES_IDAU_RCTRL_BFM) IDAU Region Control BFM Command Position */
+#define FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_Msk    (_UINT32_(0xFF) << FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_BFM) IDAU Region Control BFM Command Mask */
+#define FUSES_IDAU_RCTRL_BFM_BLOCK_CMD(value) (FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_Pos))
+#define   FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_CLRNONSEC_Val _UINT32_(0x5A)                                       /* (FUSES_IDAU_RCTRL_BFM) Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)  */
+#define   FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_SETNONSEC_Val _UINT32_(0x5B)                                       /* (FUSES_IDAU_RCTRL_BFM) Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)  */
+#define FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_CLRNONSEC (FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_CLRNONSEC_Val << FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_BFM) Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0) Position */
+#define FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_SETNONSEC (FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_SETNONSEC_Val << FUSES_IDAU_RCTRL_BFM_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_BFM) Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1) Position */
+#define FUSES_IDAU_RCTRL_BFM_BLOCK_Msk        _UINT32_(0xFF00001F)                                 /* (FUSES_IDAU_RCTRL_BFM_BLOCK) Register Mask  */
+
+/* WATERMARK mode */
+#define FUSES_IDAU_RCTRL_BFM_WATERMARK_ARG_Pos _UINT32_(0)                                          /* (FUSES_IDAU_RCTRL_BFM) IDAU Region Control BFM Command Argument (Watermark) Position */
+#define FUSES_IDAU_RCTRL_BFM_WATERMARK_ARG_Msk (_UINT32_(0xFFFFFF) << FUSES_IDAU_RCTRL_BFM_WATERMARK_ARG_Pos) /* (FUSES_IDAU_RCTRL_BFM) IDAU Region Control BFM Command Argument (Watermark) Mask */
+#define FUSES_IDAU_RCTRL_BFM_WATERMARK_ARG(value) (FUSES_IDAU_RCTRL_BFM_WATERMARK_ARG_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_BFM_WATERMARK_ARG_Pos))
+#define FUSES_IDAU_RCTRL_BFM_WATERMARK_CMD_Pos _UINT32_(24)                                         /* (FUSES_IDAU_RCTRL_BFM) IDAU Region Control BFM Command Position */
+#define FUSES_IDAU_RCTRL_BFM_WATERMARK_CMD_Msk (_UINT32_(0xFF) << FUSES_IDAU_RCTRL_BFM_WATERMARK_CMD_Pos) /* (FUSES_IDAU_RCTRL_BFM) IDAU Region Control BFM Command Mask */
+#define FUSES_IDAU_RCTRL_BFM_WATERMARK_CMD(value) (FUSES_IDAU_RCTRL_BFM_WATERMARK_CMD_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_BFM_WATERMARK_CMD_Pos))
+#define   FUSES_IDAU_RCTRL_BFM_WATERMARK_CMD_WRSZ_Val _UINT32_(0x5C)                                       /* (FUSES_IDAU_RCTRL_BFM) Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)  */
+#define FUSES_IDAU_RCTRL_BFM_WATERMARK_CMD_WRSZ (FUSES_IDAU_RCTRL_BFM_WATERMARK_CMD_WRSZ_Val << FUSES_IDAU_RCTRL_BFM_WATERMARK_CMD_Pos) /* (FUSES_IDAU_RCTRL_BFM) Write IDAU region x Size (RSTATUSB[x].SIZE=ARG) Position */
+#define FUSES_IDAU_RCTRL_BFM_WATERMARK_Msk    _UINT32_(0xFFFFFFFF)                                 /* (FUSES_IDAU_RCTRL_BFM_WATERMARK) Register Mask  */
+
+
+/* -------- FUSES_IDAU_RCTRL_PFMANS : (FUSES Offset: 0x868) (R/W 32) Region Control -------- */
+#define FUSES_IDAU_RCTRL_PFMANS_RESETVALUE    _UINT32_(0x5C000000)                                 /*  (FUSES_IDAU_RCTRL_PFMANS) Region Control  Reset Value */
+
+#define FUSES_IDAU_RCTRL_PFMANS_Msk           _UINT32_(0x00000000)                                 /* (FUSES_IDAU_RCTRL_PFMANS) Register Mask  */
+
+/* BLOCK mode */
+#define FUSES_IDAU_RCTRL_PFMANS_BLOCK_ARG_Pos _UINT32_(0)                                          /* (FUSES_IDAU_RCTRL_PFMANS) IDAU Region Control PFMANS Command Argument (Block ID) Position */
+#define FUSES_IDAU_RCTRL_PFMANS_BLOCK_ARG_Msk (_UINT32_(0x1F) << FUSES_IDAU_RCTRL_PFMANS_BLOCK_ARG_Pos) /* (FUSES_IDAU_RCTRL_PFMANS) IDAU Region Control PFMANS Command Argument (Block ID) Mask */
+#define FUSES_IDAU_RCTRL_PFMANS_BLOCK_ARG(value) (FUSES_IDAU_RCTRL_PFMANS_BLOCK_ARG_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_PFMANS_BLOCK_ARG_Pos))
+#define FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_Pos _UINT32_(24)                                         /* (FUSES_IDAU_RCTRL_PFMANS) IDAU Region Control PFMAN Command Position */
+#define FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_Msk (_UINT32_(0xFF) << FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_PFMANS) IDAU Region Control PFMAN Command Mask */
+#define FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD(value) (FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_Pos))
+#define   FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_CLRNONSEC_Val _UINT32_(0x5A)                                       /* (FUSES_IDAU_RCTRL_PFMANS) Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)  */
+#define   FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_SETNONSEC_Val _UINT32_(0x5B)                                       /* (FUSES_IDAU_RCTRL_PFMANS) Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)  */
+#define FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_CLRNONSEC (FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_CLRNONSEC_Val << FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_PFMANS) Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0) Position */
+#define FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_SETNONSEC (FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_SETNONSEC_Val << FUSES_IDAU_RCTRL_PFMANS_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_PFMANS) Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1) Position */
+#define FUSES_IDAU_RCTRL_PFMANS_BLOCK_Msk     _UINT32_(0xFF00001F)                                 /* (FUSES_IDAU_RCTRL_PFMANS_BLOCK) Register Mask  */
+
+/* WATERMARK mode */
+#define FUSES_IDAU_RCTRL_PFMANS_WATERMARK_ARG_Pos _UINT32_(0)                                          /* (FUSES_IDAU_RCTRL_PFMANS) IDAU Region Control PFMAN Command Argument (Watermark) Position */
+#define FUSES_IDAU_RCTRL_PFMANS_WATERMARK_ARG_Msk (_UINT32_(0xFFFFFF) << FUSES_IDAU_RCTRL_PFMANS_WATERMARK_ARG_Pos) /* (FUSES_IDAU_RCTRL_PFMANS) IDAU Region Control PFMAN Command Argument (Watermark) Mask */
+#define FUSES_IDAU_RCTRL_PFMANS_WATERMARK_ARG(value) (FUSES_IDAU_RCTRL_PFMANS_WATERMARK_ARG_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_PFMANS_WATERMARK_ARG_Pos))
+#define FUSES_IDAU_RCTRL_PFMANS_WATERMARK_CMD_Pos _UINT32_(24)                                         /* (FUSES_IDAU_RCTRL_PFMANS) IDAU Region Control PFMAN Command Position */
+#define FUSES_IDAU_RCTRL_PFMANS_WATERMARK_CMD_Msk (_UINT32_(0xFF) << FUSES_IDAU_RCTRL_PFMANS_WATERMARK_CMD_Pos) /* (FUSES_IDAU_RCTRL_PFMANS) IDAU Region Control PFMAN Command Mask */
+#define FUSES_IDAU_RCTRL_PFMANS_WATERMARK_CMD(value) (FUSES_IDAU_RCTRL_PFMANS_WATERMARK_CMD_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_PFMANS_WATERMARK_CMD_Pos))
+#define   FUSES_IDAU_RCTRL_PFMANS_WATERMARK_CMD_WRSZ_Val _UINT32_(0x5C)                                       /* (FUSES_IDAU_RCTRL_PFMANS) Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)  */
+#define FUSES_IDAU_RCTRL_PFMANS_WATERMARK_CMD_WRSZ (FUSES_IDAU_RCTRL_PFMANS_WATERMARK_CMD_WRSZ_Val << FUSES_IDAU_RCTRL_PFMANS_WATERMARK_CMD_Pos) /* (FUSES_IDAU_RCTRL_PFMANS) Write IDAU region x Size (RSTATUSB[x].SIZE=ARG) Position */
+#define FUSES_IDAU_RCTRL_PFMANS_WATERMARK_Msk _UINT32_(0xFFFFFFFF)                                 /* (FUSES_IDAU_RCTRL_PFMANS_WATERMARK) Register Mask  */
+
+
+/* -------- FUSES_IDAU_RCTRL_PFMANSC : (FUSES Offset: 0x86C) (R/W 32) Region Control -------- */
+#define FUSES_IDAU_RCTRL_PFMANSC_RESETVALUE   _UINT32_(0x5C000000)                                 /*  (FUSES_IDAU_RCTRL_PFMANSC) Region Control  Reset Value */
+
+#define FUSES_IDAU_RCTRL_PFMANSC_Msk          _UINT32_(0x00000000)                                 /* (FUSES_IDAU_RCTRL_PFMANSC) Register Mask  */
+
+/* BLOCK mode */
+#define FUSES_IDAU_RCTRL_PFMANSC_BLOCK_ARG_Pos _UINT32_(0)                                          /* (FUSES_IDAU_RCTRL_PFMANSC) IDAU Region Control PFMANSC Command Argument (Block ID) Position */
+#define FUSES_IDAU_RCTRL_PFMANSC_BLOCK_ARG_Msk (_UINT32_(0x1F) << FUSES_IDAU_RCTRL_PFMANSC_BLOCK_ARG_Pos) /* (FUSES_IDAU_RCTRL_PFMANSC) IDAU Region Control PFMANSC Command Argument (Block ID) Mask */
+#define FUSES_IDAU_RCTRL_PFMANSC_BLOCK_ARG(value) (FUSES_IDAU_RCTRL_PFMANSC_BLOCK_ARG_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_PFMANSC_BLOCK_ARG_Pos))
+#define FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_Pos _UINT32_(24)                                         /* (FUSES_IDAU_RCTRL_PFMANSC) IDAU Region Control PFMANSC Command Position */
+#define FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_Msk (_UINT32_(0xFF) << FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_PFMANSC) IDAU Region Control PFMANSC Command Mask */
+#define FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD(value) (FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_Pos))
+#define   FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_CLRNONSEC_Val _UINT32_(0x5A)                                       /* (FUSES_IDAU_RCTRL_PFMANSC) Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)  */
+#define   FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_SETNONSEC_Val _UINT32_(0x5B)                                       /* (FUSES_IDAU_RCTRL_PFMANSC) Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)  */
+#define FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_CLRNONSEC (FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_CLRNONSEC_Val << FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_PFMANSC) Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0) Position */
+#define FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_SETNONSEC (FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_SETNONSEC_Val << FUSES_IDAU_RCTRL_PFMANSC_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_PFMANSC) Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1) Position */
+#define FUSES_IDAU_RCTRL_PFMANSC_BLOCK_Msk    _UINT32_(0xFF00001F)                                 /* (FUSES_IDAU_RCTRL_PFMANSC_BLOCK) Register Mask  */
+
+/* WATERMARK mode */
+#define FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_ARG_Pos _UINT32_(0)                                          /* (FUSES_IDAU_RCTRL_PFMANSC) IDAU Region Control PFMANSC Command Argument (Watermark) Position */
+#define FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_ARG_Msk (_UINT32_(0xFFFFFF) << FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_ARG_Pos) /* (FUSES_IDAU_RCTRL_PFMANSC) IDAU Region Control PFMANSC Command Argument (Watermark) Mask */
+#define FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_ARG(value) (FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_ARG_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_ARG_Pos))
+#define FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_CMD_Pos _UINT32_(24)                                         /* (FUSES_IDAU_RCTRL_PFMANSC) IDAU Region Control PFMANSC Command Position */
+#define FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_CMD_Msk (_UINT32_(0xFF) << FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_CMD_Pos) /* (FUSES_IDAU_RCTRL_PFMANSC) IDAU Region Control PFMANSC Command Mask */
+#define FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_CMD(value) (FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_CMD_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_CMD_Pos))
+#define   FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_CMD_WRSZ_Val _UINT32_(0x5C)                                       /* (FUSES_IDAU_RCTRL_PFMANSC) Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)  */
+#define FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_CMD_WRSZ (FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_CMD_WRSZ_Val << FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_CMD_Pos) /* (FUSES_IDAU_RCTRL_PFMANSC) Write IDAU region x Size (RSTATUSB[x].SIZE=ARG) Position */
+#define FUSES_IDAU_RCTRL_PFMANSC_WATERMARK_Msk _UINT32_(0xFFFFFFFF)                                 /* (FUSES_IDAU_RCTRL_PFMANSC_WATERMARK) Register Mask  */
+
+
+/* -------- FUSES_IDAU_RCTRL_DRM : (FUSES Offset: 0x870) (R/W 32) Region Control -------- */
+#define FUSES_IDAU_RCTRL_DRM_RESETVALUE       _UINT32_(0x5C000000)                                 /*  (FUSES_IDAU_RCTRL_DRM) Region Control  Reset Value */
+
+#define FUSES_IDAU_RCTRL_DRM_Msk              _UINT32_(0x00000000)                                 /* (FUSES_IDAU_RCTRL_DRM) Register Mask  */
+
+/* BLOCK mode */
+#define FUSES_IDAU_RCTRL_DRM_BLOCK_ARG_Pos    _UINT32_(0)                                          /* (FUSES_IDAU_RCTRL_DRM) IDAU Region Control DRM Command Argument (Block ID) Position */
+#define FUSES_IDAU_RCTRL_DRM_BLOCK_ARG_Msk    (_UINT32_(0x1F) << FUSES_IDAU_RCTRL_DRM_BLOCK_ARG_Pos) /* (FUSES_IDAU_RCTRL_DRM) IDAU Region Control DRM Command Argument (Block ID) Mask */
+#define FUSES_IDAU_RCTRL_DRM_BLOCK_ARG(value) (FUSES_IDAU_RCTRL_DRM_BLOCK_ARG_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_DRM_BLOCK_ARG_Pos))
+#define FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_Pos    _UINT32_(24)                                         /* (FUSES_IDAU_RCTRL_DRM) IDAU Region Control DRM Command Position */
+#define FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_Msk    (_UINT32_(0xFF) << FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_DRM) IDAU Region Control DRM Command Mask */
+#define FUSES_IDAU_RCTRL_DRM_BLOCK_CMD(value) (FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_Pos))
+#define   FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_CLRNONSEC_Val _UINT32_(0x5A)                                       /* (FUSES_IDAU_RCTRL_DRM) Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0)  */
+#define   FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_SETNONSEC_Val _UINT32_(0x5B)                                       /* (FUSES_IDAU_RCTRL_DRM) Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1)  */
+#define FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_CLRNONSEC (FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_CLRNONSEC_Val << FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_DRM) Clear IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=0) Position */
+#define FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_SETNONSEC (FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_SETNONSEC_Val << FUSES_IDAU_RCTRL_DRM_BLOCK_CMD_Pos) /* (FUSES_IDAU_RCTRL_DRM) Set IDAU region x Non-Secure State of block ARG (RSTATUSB[x].NONSEC[ARG]=1) Position */
+#define FUSES_IDAU_RCTRL_DRM_BLOCK_Msk        _UINT32_(0xFF00001F)                                 /* (FUSES_IDAU_RCTRL_DRM_BLOCK) Register Mask  */
+
+/* WATERMARK mode */
+#define FUSES_IDAU_RCTRL_DRM_WATERMARK_ARG_Pos _UINT32_(0)                                          /* (FUSES_IDAU_RCTRL_DRM) IDAU Region Control DRM Command Argument (Watermark) Position */
+#define FUSES_IDAU_RCTRL_DRM_WATERMARK_ARG_Msk (_UINT32_(0xFFFFFF) << FUSES_IDAU_RCTRL_DRM_WATERMARK_ARG_Pos) /* (FUSES_IDAU_RCTRL_DRM) IDAU Region Control DRM Command Argument (Watermark) Mask */
+#define FUSES_IDAU_RCTRL_DRM_WATERMARK_ARG(value) (FUSES_IDAU_RCTRL_DRM_WATERMARK_ARG_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_DRM_WATERMARK_ARG_Pos))
+#define FUSES_IDAU_RCTRL_DRM_WATERMARK_CMD_Pos _UINT32_(24)                                         /* (FUSES_IDAU_RCTRL_DRM) IDAU Region Control DRM Command Position */
+#define FUSES_IDAU_RCTRL_DRM_WATERMARK_CMD_Msk (_UINT32_(0xFF) << FUSES_IDAU_RCTRL_DRM_WATERMARK_CMD_Pos) /* (FUSES_IDAU_RCTRL_DRM) IDAU Region Control DRM Command Mask */
+#define FUSES_IDAU_RCTRL_DRM_WATERMARK_CMD(value) (FUSES_IDAU_RCTRL_DRM_WATERMARK_CMD_Msk & (_UINT32_(value) << FUSES_IDAU_RCTRL_DRM_WATERMARK_CMD_Pos))
+#define   FUSES_IDAU_RCTRL_DRM_WATERMARK_CMD_WRSZ_Val _UINT32_(0x5C)                                       /* (FUSES_IDAU_RCTRL_DRM) Write IDAU region x Size (RSTATUSB[x].SIZE=ARG)  */
+#define FUSES_IDAU_RCTRL_DRM_WATERMARK_CMD_WRSZ (FUSES_IDAU_RCTRL_DRM_WATERMARK_CMD_WRSZ_Val << FUSES_IDAU_RCTRL_DRM_WATERMARK_CMD_Pos) /* (FUSES_IDAU_RCTRL_DRM) Write IDAU region x Size (RSTATUSB[x].SIZE=ARG) Position */
+#define FUSES_IDAU_RCTRL_DRM_WATERMARK_Msk    _UINT32_(0xFFFFFFFF)                                 /* (FUSES_IDAU_RCTRL_DRM_WATERMARK) Register Mask  */
+
+
+/* -------- FUSES_IDAU_CTRL_EN : (FUSES Offset: 0x874) (R/W 32) Control -------- */
+#define FUSES_IDAU_CTRL_EN_RESETVALUE         _UINT32_(0xA5010000)                                 /*  (FUSES_IDAU_CTRL_EN) Control  Reset Value */
+
+#define FUSES_IDAU_CTRL_EN_CMD_Pos            _UINT32_(16)                                         /* (FUSES_IDAU_CTRL_EN) IDAU Enable Command Register Position */
+#define FUSES_IDAU_CTRL_EN_CMD_Msk            (_UINT32_(0xFFFF) << FUSES_IDAU_CTRL_EN_CMD_Pos)     /* (FUSES_IDAU_CTRL_EN) IDAU Enable Command Register Mask */
+#define FUSES_IDAU_CTRL_EN_CMD(value)         (FUSES_IDAU_CTRL_EN_CMD_Msk & (_UINT32_(value) << FUSES_IDAU_CTRL_EN_CMD_Pos)) /* Assignment of value for CMD in the FUSES_IDAU_CTRL_EN register */
+#define   FUSES_IDAU_CTRL_EN_CMD_ENABLE_Val   _UINT32_(0xA501)                                     /* (FUSES_IDAU_CTRL_EN) Module Enable  */
+#define   FUSES_IDAU_CTRL_EN_CMD_DISABLE_Val  _UINT32_(0xA502)                                     /* (FUSES_IDAU_CTRL_EN) Module Disable  */
+#define FUSES_IDAU_CTRL_EN_CMD_ENABLE         (FUSES_IDAU_CTRL_EN_CMD_ENABLE_Val << FUSES_IDAU_CTRL_EN_CMD_Pos) /* (FUSES_IDAU_CTRL_EN) Module Enable Position */
+#define FUSES_IDAU_CTRL_EN_CMD_DISABLE        (FUSES_IDAU_CTRL_EN_CMD_DISABLE_Val << FUSES_IDAU_CTRL_EN_CMD_Pos) /* (FUSES_IDAU_CTRL_EN) Module Disable Position */
+#define FUSES_IDAU_CTRL_EN_Msk                _UINT32_(0xFFFF0000)                                 /* (FUSES_IDAU_CTRL_EN) Register Mask  */
+
+
+/* -------- FUSES_IDAU_CTRL_WLCK : (FUSES Offset: 0x878) (R/W 32) Control -------- */
+#define FUSES_IDAU_CTRL_WLCK_RESETVALUE       _UINT32_(0xFFFFFFFF)                                 /*  (FUSES_IDAU_CTRL_WLCK) Control  Reset Value */
+
+#define FUSES_IDAU_CTRL_WLCK_CMD_Pos          _UINT32_(16)                                         /* (FUSES_IDAU_CTRL_WLCK) IDAU Write Lock Command Register Position */
+#define FUSES_IDAU_CTRL_WLCK_CMD_Msk          (_UINT32_(0xFFFF) << FUSES_IDAU_CTRL_WLCK_CMD_Pos)   /* (FUSES_IDAU_CTRL_WLCK) IDAU Write Lock Command Register Mask */
+#define FUSES_IDAU_CTRL_WLCK_CMD(value)       (FUSES_IDAU_CTRL_WLCK_CMD_Msk & (_UINT32_(value) << FUSES_IDAU_CTRL_WLCK_CMD_Pos)) /* Assignment of value for CMD in the FUSES_IDAU_CTRL_WLCK register */
+#define   FUSES_IDAU_CTRL_WLCK_CMD_WLCK_Val   _UINT32_(0xA503)                                     /* (FUSES_IDAU_CTRL_WLCK) Write Lock  */
+#define FUSES_IDAU_CTRL_WLCK_CMD_WLCK         (FUSES_IDAU_CTRL_WLCK_CMD_WLCK_Val << FUSES_IDAU_CTRL_WLCK_CMD_Pos) /* (FUSES_IDAU_CTRL_WLCK) Write Lock Position */
+#define FUSES_IDAU_CTRL_WLCK_Msk              _UINT32_(0xFFFF0000)                                 /* (FUSES_IDAU_CTRL_WLCK) Register Mask  */
+
+
+/* -------- FUSES_FCW_CWP : (FUSES Offset: 0x87C) (R/W 32) CFM Page Write Protect REGISTER -------- */
+#define FUSES_FCW_CWP_RESETVALUE              _UINT32_(0x00)                                       /*  (FUSES_FCW_CWP) CFM Page Write Protect REGISTER  Reset Value */
+
+#define FUSES_FCW_CWP_BC1AWP_Pos              _UINT32_(0)                                          /* (FUSES_FCW_CWP) Panel 1 Write Protect BootCfg1A Position */
+#define FUSES_FCW_CWP_BC1AWP_Msk              (_UINT32_(0x1) << FUSES_FCW_CWP_BC1AWP_Pos)          /* (FUSES_FCW_CWP) Panel 1 Write Protect BootCfg1A Mask */
+#define FUSES_FCW_CWP_BC1AWP(value)           (FUSES_FCW_CWP_BC1AWP_Msk & (_UINT32_(value) << FUSES_FCW_CWP_BC1AWP_Pos)) /* Assignment of value for BC1AWP in the FUSES_FCW_CWP register */
+#define   FUSES_FCW_CWP_BC1AWP_DISABLE_Val    _UINT32_(0x0)                                        /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FUSES_FCW_CWP_BC1AWP_ENABLE_Val     _UINT32_(0x1)                                        /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FUSES_FCW_CWP_BC1AWP_DISABLE          (FUSES_FCW_CWP_BC1AWP_DISABLE_Val << FUSES_FCW_CWP_BC1AWP_Pos) /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FUSES_FCW_CWP_BC1AWP_ENABLE           (FUSES_FCW_CWP_BC1AWP_ENABLE_Val << FUSES_FCW_CWP_BC1AWP_Pos) /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FUSES_FCW_CWP_BC1WP_Pos               _UINT32_(2)                                          /* (FUSES_FCW_CWP) Panel 1 Write Protect BootCfg1 Position */
+#define FUSES_FCW_CWP_BC1WP_Msk               (_UINT32_(0x1) << FUSES_FCW_CWP_BC1WP_Pos)           /* (FUSES_FCW_CWP) Panel 1 Write Protect BootCfg1 Mask */
+#define FUSES_FCW_CWP_BC1WP(value)            (FUSES_FCW_CWP_BC1WP_Msk & (_UINT32_(value) << FUSES_FCW_CWP_BC1WP_Pos)) /* Assignment of value for BC1WP in the FUSES_FCW_CWP register */
+#define   FUSES_FCW_CWP_BC1WP_DISABLE_Val     _UINT32_(0x0)                                        /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FUSES_FCW_CWP_BC1WP_ENABLE_Val      _UINT32_(0x1)                                        /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FUSES_FCW_CWP_BC1WP_DISABLE           (FUSES_FCW_CWP_BC1WP_DISABLE_Val << FUSES_FCW_CWP_BC1WP_Pos) /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FUSES_FCW_CWP_BC1WP_ENABLE            (FUSES_FCW_CWP_BC1WP_ENABLE_Val << FUSES_FCW_CWP_BC1WP_Pos) /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FUSES_FCW_CWP_RCWP_Pos                _UINT32_(3)                                          /* (FUSES_FCW_CWP) Panel 1 Write Protect ROMCfg Position */
+#define FUSES_FCW_CWP_RCWP_Msk                (_UINT32_(0x1) << FUSES_FCW_CWP_RCWP_Pos)            /* (FUSES_FCW_CWP) Panel 1 Write Protect ROMCfg Mask */
+#define FUSES_FCW_CWP_RCWP(value)             (FUSES_FCW_CWP_RCWP_Msk & (_UINT32_(value) << FUSES_FCW_CWP_RCWP_Pos)) /* Assignment of value for RCWP in the FUSES_FCW_CWP register */
+#define   FUSES_FCW_CWP_RCWP_DISABLE_Val      _UINT32_(0x0)                                        /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FUSES_FCW_CWP_RCWP_ENABLE_Val       _UINT32_(0x1)                                        /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FUSES_FCW_CWP_RCWP_DISABLE            (FUSES_FCW_CWP_RCWP_DISABLE_Val << FUSES_FCW_CWP_RCWP_Pos) /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FUSES_FCW_CWP_RCWP_ENABLE             (FUSES_FCW_CWP_RCWP_ENABLE_Val << FUSES_FCW_CWP_RCWP_Pos) /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FUSES_FCW_CWP_VSSWP0_Pos              _UINT32_(4)                                          /* (FUSES_FCW_CWP) Panel 1 Write Protect VSSn Position */
+#define FUSES_FCW_CWP_VSSWP0_Msk              (_UINT32_(0x1) << FUSES_FCW_CWP_VSSWP0_Pos)          /* (FUSES_FCW_CWP) Panel 1 Write Protect VSSn Mask */
+#define FUSES_FCW_CWP_VSSWP0(value)           (FUSES_FCW_CWP_VSSWP0_Msk & (_UINT32_(value) << FUSES_FCW_CWP_VSSWP0_Pos)) /* Assignment of value for VSSWP0 in the FUSES_FCW_CWP register */
+#define   FUSES_FCW_CWP_VSSWP0_DISABLE_Val    _UINT32_(0x0)                                        /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FUSES_FCW_CWP_VSSWP0_ENABLE_Val     _UINT32_(0x1)                                        /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FUSES_FCW_CWP_VSSWP0_DISABLE          (FUSES_FCW_CWP_VSSWP0_DISABLE_Val << FUSES_FCW_CWP_VSSWP0_Pos) /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FUSES_FCW_CWP_VSSWP0_ENABLE           (FUSES_FCW_CWP_VSSWP0_ENABLE_Val << FUSES_FCW_CWP_VSSWP0_Pos) /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FUSES_FCW_CWP_VSSWP1_Pos              _UINT32_(5)                                          /* (FUSES_FCW_CWP) Panel 1 Write Protect VSSn Position */
+#define FUSES_FCW_CWP_VSSWP1_Msk              (_UINT32_(0x1) << FUSES_FCW_CWP_VSSWP1_Pos)          /* (FUSES_FCW_CWP) Panel 1 Write Protect VSSn Mask */
+#define FUSES_FCW_CWP_VSSWP1(value)           (FUSES_FCW_CWP_VSSWP1_Msk & (_UINT32_(value) << FUSES_FCW_CWP_VSSWP1_Pos)) /* Assignment of value for VSSWP1 in the FUSES_FCW_CWP register */
+#define   FUSES_FCW_CWP_VSSWP1_DISABLE_Val    _UINT32_(0x0)                                        /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Disabled  */
+#define   FUSES_FCW_CWP_VSSWP1_ENABLE_Val     _UINT32_(0x1)                                        /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Enabled  */
+#define FUSES_FCW_CWP_VSSWP1_DISABLE          (FUSES_FCW_CWP_VSSWP1_DISABLE_Val << FUSES_FCW_CWP_VSSWP1_Pos) /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Disabled Position */
+#define FUSES_FCW_CWP_VSSWP1_ENABLE           (FUSES_FCW_CWP_VSSWP1_ENABLE_Val << FUSES_FCW_CWP_VSSWP1_Pos) /* (FUSES_FCW_CWP) Erase and Write Protection for this Page is Enabled Position */
+#define FUSES_FCW_CWP_BC1AWPLOCK_Pos          _UINT32_(16)                                         /* (FUSES_FCW_CWP) Panel 1 Lock Write Protection BootCfg1A Position */
+#define FUSES_FCW_CWP_BC1AWPLOCK_Msk          (_UINT32_(0x1) << FUSES_FCW_CWP_BC1AWPLOCK_Pos)      /* (FUSES_FCW_CWP) Panel 1 Lock Write Protection BootCfg1A Mask */
+#define FUSES_FCW_CWP_BC1AWPLOCK(value)       (FUSES_FCW_CWP_BC1AWPLOCK_Msk & (_UINT32_(value) << FUSES_FCW_CWP_BC1AWPLOCK_Pos)) /* Assignment of value for BC1AWPLOCK in the FUSES_FCW_CWP register */
+#define   FUSES_FCW_CWP_BC1AWPLOCK_UNLOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FUSES_FCW_CWP_BC1AWPLOCK_LOCKED_Val _UINT32_(0x1)                                        /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FUSES_FCW_CWP_BC1AWPLOCK_UNLOCKED     (FUSES_FCW_CWP_BC1AWPLOCK_UNLOCKED_Val << FUSES_FCW_CWP_BC1AWPLOCK_Pos) /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FUSES_FCW_CWP_BC1AWPLOCK_LOCKED       (FUSES_FCW_CWP_BC1AWPLOCK_LOCKED_Val << FUSES_FCW_CWP_BC1AWPLOCK_Pos) /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FUSES_FCW_CWP_BC1WPLOCK_Pos           _UINT32_(18)                                         /* (FUSES_FCW_CWP) Panel 1 Lock Write Protection BootCfg1 Position */
+#define FUSES_FCW_CWP_BC1WPLOCK_Msk           (_UINT32_(0x1) << FUSES_FCW_CWP_BC1WPLOCK_Pos)       /* (FUSES_FCW_CWP) Panel 1 Lock Write Protection BootCfg1 Mask */
+#define FUSES_FCW_CWP_BC1WPLOCK(value)        (FUSES_FCW_CWP_BC1WPLOCK_Msk & (_UINT32_(value) << FUSES_FCW_CWP_BC1WPLOCK_Pos)) /* Assignment of value for BC1WPLOCK in the FUSES_FCW_CWP register */
+#define   FUSES_FCW_CWP_BC1WPLOCK_UNLOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FUSES_FCW_CWP_BC1WPLOCK_LOCKED_Val  _UINT32_(0x1)                                        /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FUSES_FCW_CWP_BC1WPLOCK_UNLOCKED      (FUSES_FCW_CWP_BC1WPLOCK_UNLOCKED_Val << FUSES_FCW_CWP_BC1WPLOCK_Pos) /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FUSES_FCW_CWP_BC1WPLOCK_LOCKED        (FUSES_FCW_CWP_BC1WPLOCK_LOCKED_Val << FUSES_FCW_CWP_BC1WPLOCK_Pos) /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FUSES_FCW_CWP_RCWPLOCK_Pos            _UINT32_(19)                                         /* (FUSES_FCW_CWP) Panel 1 Lock Write Protection ROMCfg Position */
+#define FUSES_FCW_CWP_RCWPLOCK_Msk            (_UINT32_(0x1) << FUSES_FCW_CWP_RCWPLOCK_Pos)        /* (FUSES_FCW_CWP) Panel 1 Lock Write Protection ROMCfg Mask */
+#define FUSES_FCW_CWP_RCWPLOCK(value)         (FUSES_FCW_CWP_RCWPLOCK_Msk & (_UINT32_(value) << FUSES_FCW_CWP_RCWPLOCK_Pos)) /* Assignment of value for RCWPLOCK in the FUSES_FCW_CWP register */
+#define   FUSES_FCW_CWP_RCWPLOCK_UNLOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FUSES_FCW_CWP_RCWPLOCK_LOCKED_Val   _UINT32_(0x1)                                        /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FUSES_FCW_CWP_RCWPLOCK_UNLOCKED       (FUSES_FCW_CWP_RCWPLOCK_UNLOCKED_Val << FUSES_FCW_CWP_RCWPLOCK_Pos) /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FUSES_FCW_CWP_RCWPLOCK_LOCKED         (FUSES_FCW_CWP_RCWPLOCK_LOCKED_Val << FUSES_FCW_CWP_RCWPLOCK_Pos) /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FUSES_FCW_CWP_VSSWPLOCK0_Pos          _UINT32_(20)                                         /* (FUSES_FCW_CWP) Panel 1 Lock Write Protection VSSn Position */
+#define FUSES_FCW_CWP_VSSWPLOCK0_Msk          (_UINT32_(0x1) << FUSES_FCW_CWP_VSSWPLOCK0_Pos)      /* (FUSES_FCW_CWP) Panel 1 Lock Write Protection VSSn Mask */
+#define FUSES_FCW_CWP_VSSWPLOCK0(value)       (FUSES_FCW_CWP_VSSWPLOCK0_Msk & (_UINT32_(value) << FUSES_FCW_CWP_VSSWPLOCK0_Pos)) /* Assignment of value for VSSWPLOCK0 in the FUSES_FCW_CWP register */
+#define   FUSES_FCW_CWP_VSSWPLOCK0_UNLOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FUSES_FCW_CWP_VSSWPLOCK0_LOCKED_Val _UINT32_(0x1)                                        /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FUSES_FCW_CWP_VSSWPLOCK0_UNLOCKED     (FUSES_FCW_CWP_VSSWPLOCK0_UNLOCKED_Val << FUSES_FCW_CWP_VSSWPLOCK0_Pos) /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FUSES_FCW_CWP_VSSWPLOCK0_LOCKED       (FUSES_FCW_CWP_VSSWPLOCK0_LOCKED_Val << FUSES_FCW_CWP_VSSWPLOCK0_Pos) /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FUSES_FCW_CWP_VSSWPLOCK1_Pos          _UINT32_(21)                                         /* (FUSES_FCW_CWP) Panel 1 Lock Write Protection VSSn Position */
+#define FUSES_FCW_CWP_VSSWPLOCK1_Msk          (_UINT32_(0x1) << FUSES_FCW_CWP_VSSWPLOCK1_Pos)      /* (FUSES_FCW_CWP) Panel 1 Lock Write Protection VSSn Mask */
+#define FUSES_FCW_CWP_VSSWPLOCK1(value)       (FUSES_FCW_CWP_VSSWPLOCK1_Msk & (_UINT32_(value) << FUSES_FCW_CWP_VSSWPLOCK1_Pos)) /* Assignment of value for VSSWPLOCK1 in the FUSES_FCW_CWP register */
+#define   FUSES_FCW_CWP_VSSWPLOCK1_UNLOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified  */
+#define   FUSES_FCW_CWP_VSSWPLOCK1_LOCKED_Val _UINT32_(0x1)                                        /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified  */
+#define FUSES_FCW_CWP_VSSWPLOCK1_UNLOCKED     (FUSES_FCW_CWP_VSSWPLOCK1_UNLOCKED_Val << FUSES_FCW_CWP_VSSWPLOCK1_Pos) /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are NOT Locked and can be modified Position */
+#define FUSES_FCW_CWP_VSSWPLOCK1_LOCKED       (FUSES_FCW_CWP_VSSWPLOCK1_LOCKED_Val << FUSES_FCW_CWP_VSSWPLOCK1_Pos) /* (FUSES_FCW_CWP) The Lock &amp;amp; Write Protect bits for this Page are Locked and cannot be modified Position */
+#define FUSES_FCW_CWP_Msk                     _UINT32_(0x003D003D)                                 /* (FUSES_FCW_CWP) Register Mask  */
+
+#define FUSES_FCW_CWP_VSSWP_Pos               _UINT32_(4)                                          /* (FUSES_FCW_CWP Position) Panel x Write Protect VSSn */
+#define FUSES_FCW_CWP_VSSWP_Msk               (_UINT32_(0x3) << FUSES_FCW_CWP_VSSWP_Pos)           /* (FUSES_FCW_CWP Mask) VSSWP */
+#define FUSES_FCW_CWP_VSSWP(value)            (FUSES_FCW_CWP_VSSWP_Msk & (_UINT32_(value) << FUSES_FCW_CWP_VSSWP_Pos)) 
+#define FUSES_FCW_CWP_VSSWPLOCK_Pos           _UINT32_(20)                                         /* (FUSES_FCW_CWP Position) Panel x Lock Write Protection VSSn */
+#define FUSES_FCW_CWP_VSSWPLOCK_Msk           (_UINT32_(0x3) << FUSES_FCW_CWP_VSSWPLOCK_Pos)       /* (FUSES_FCW_CWP Mask) VSSWPLOCK */
+#define FUSES_FCW_CWP_VSSWPLOCK(value)        (FUSES_FCW_CWP_VSSWPLOCK_Msk & (_UINT32_(value) << FUSES_FCW_CWP_VSSWPLOCK_Pos)) 
+
+/* -------- FUSES_FCR_CRP : (FUSES Offset: 0x880) (R/W 32) CFM Page Read Protection Register -------- */
+#define FUSES_FCR_CRP_RESETVALUE              _UINT32_(0x00)                                       /*  (FUSES_FCR_CRP) CFM Page Read Protection Register  Reset Value */
+
+#define FUSES_FCR_CRP_BC1ARP_Pos              _UINT32_(0)                                          /* (FUSES_FCR_CRP) Panel 1 Read Protect BootCfg1A Position */
+#define FUSES_FCR_CRP_BC1ARP_Msk              (_UINT32_(0x1) << FUSES_FCR_CRP_BC1ARP_Pos)          /* (FUSES_FCR_CRP) Panel 1 Read Protect BootCfg1A Mask */
+#define FUSES_FCR_CRP_BC1ARP(value)           (FUSES_FCR_CRP_BC1ARP_Msk & (_UINT32_(value) << FUSES_FCR_CRP_BC1ARP_Pos)) /* Assignment of value for BC1ARP in the FUSES_FCR_CRP register */
+#define   FUSES_FCR_CRP_BC1ARP_DISABLE_Val    _UINT32_(0x0)                                        /* (FUSES_FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FUSES_FCR_CRP_BC1ARP_ENABLE_Val     _UINT32_(0x1)                                        /* (FUSES_FCR_CRP) Read Protection for this Page is Enabled  */
+#define FUSES_FCR_CRP_BC1ARP_DISABLE          (FUSES_FCR_CRP_BC1ARP_DISABLE_Val << FUSES_FCR_CRP_BC1ARP_Pos) /* (FUSES_FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FUSES_FCR_CRP_BC1ARP_ENABLE           (FUSES_FCR_CRP_BC1ARP_ENABLE_Val << FUSES_FCR_CRP_BC1ARP_Pos) /* (FUSES_FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FUSES_FCR_CRP_BC1RP_Pos               _UINT32_(2)                                          /* (FUSES_FCR_CRP) Panel 1 Read Protect BootCfg1 Position */
+#define FUSES_FCR_CRP_BC1RP_Msk               (_UINT32_(0x1) << FUSES_FCR_CRP_BC1RP_Pos)           /* (FUSES_FCR_CRP) Panel 1 Read Protect BootCfg1 Mask */
+#define FUSES_FCR_CRP_BC1RP(value)            (FUSES_FCR_CRP_BC1RP_Msk & (_UINT32_(value) << FUSES_FCR_CRP_BC1RP_Pos)) /* Assignment of value for BC1RP in the FUSES_FCR_CRP register */
+#define   FUSES_FCR_CRP_BC1RP_DISABLE_Val     _UINT32_(0x0)                                        /* (FUSES_FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FUSES_FCR_CRP_BC1RP_ENABLE_Val      _UINT32_(0x1)                                        /* (FUSES_FCR_CRP) Read Protection for this Page is Enabled  */
+#define FUSES_FCR_CRP_BC1RP_DISABLE           (FUSES_FCR_CRP_BC1RP_DISABLE_Val << FUSES_FCR_CRP_BC1RP_Pos) /* (FUSES_FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FUSES_FCR_CRP_BC1RP_ENABLE            (FUSES_FCR_CRP_BC1RP_ENABLE_Val << FUSES_FCR_CRP_BC1RP_Pos) /* (FUSES_FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FUSES_FCR_CRP_RCRP_Pos                _UINT32_(3)                                          /* (FUSES_FCR_CRP) Panel 1 Read Protect ROMCfg Position */
+#define FUSES_FCR_CRP_RCRP_Msk                (_UINT32_(0x1) << FUSES_FCR_CRP_RCRP_Pos)            /* (FUSES_FCR_CRP) Panel 1 Read Protect ROMCfg Mask */
+#define FUSES_FCR_CRP_RCRP(value)             (FUSES_FCR_CRP_RCRP_Msk & (_UINT32_(value) << FUSES_FCR_CRP_RCRP_Pos)) /* Assignment of value for RCRP in the FUSES_FCR_CRP register */
+#define   FUSES_FCR_CRP_RCRP_DISABLE_Val      _UINT32_(0x0)                                        /* (FUSES_FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FUSES_FCR_CRP_RCRP_ENABLE_Val       _UINT32_(0x1)                                        /* (FUSES_FCR_CRP) Read Protection for this Page is Enabled  */
+#define FUSES_FCR_CRP_RCRP_DISABLE            (FUSES_FCR_CRP_RCRP_DISABLE_Val << FUSES_FCR_CRP_RCRP_Pos) /* (FUSES_FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FUSES_FCR_CRP_RCRP_ENABLE             (FUSES_FCR_CRP_RCRP_ENABLE_Val << FUSES_FCR_CRP_RCRP_Pos) /* (FUSES_FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FUSES_FCR_CRP_VSSRP0_Pos              _UINT32_(4)                                          /* (FUSES_FCR_CRP) Panel 1 Read Protect VSSn Position */
+#define FUSES_FCR_CRP_VSSRP0_Msk              (_UINT32_(0x1) << FUSES_FCR_CRP_VSSRP0_Pos)          /* (FUSES_FCR_CRP) Panel 1 Read Protect VSSn Mask */
+#define FUSES_FCR_CRP_VSSRP0(value)           (FUSES_FCR_CRP_VSSRP0_Msk & (_UINT32_(value) << FUSES_FCR_CRP_VSSRP0_Pos)) /* Assignment of value for VSSRP0 in the FUSES_FCR_CRP register */
+#define   FUSES_FCR_CRP_VSSRP0_DISABLE_Val    _UINT32_(0x0)                                        /* (FUSES_FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FUSES_FCR_CRP_VSSRP0_ENABLE_Val     _UINT32_(0x1)                                        /* (FUSES_FCR_CRP) Read Protection for this Page is Enabled  */
+#define FUSES_FCR_CRP_VSSRP0_DISABLE          (FUSES_FCR_CRP_VSSRP0_DISABLE_Val << FUSES_FCR_CRP_VSSRP0_Pos) /* (FUSES_FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FUSES_FCR_CRP_VSSRP0_ENABLE           (FUSES_FCR_CRP_VSSRP0_ENABLE_Val << FUSES_FCR_CRP_VSSRP0_Pos) /* (FUSES_FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FUSES_FCR_CRP_VSSRP1_Pos              _UINT32_(5)                                          /* (FUSES_FCR_CRP) Panel 1 Read Protect VSSn Position */
+#define FUSES_FCR_CRP_VSSRP1_Msk              (_UINT32_(0x1) << FUSES_FCR_CRP_VSSRP1_Pos)          /* (FUSES_FCR_CRP) Panel 1 Read Protect VSSn Mask */
+#define FUSES_FCR_CRP_VSSRP1(value)           (FUSES_FCR_CRP_VSSRP1_Msk & (_UINT32_(value) << FUSES_FCR_CRP_VSSRP1_Pos)) /* Assignment of value for VSSRP1 in the FUSES_FCR_CRP register */
+#define   FUSES_FCR_CRP_VSSRP1_DISABLE_Val    _UINT32_(0x0)                                        /* (FUSES_FCR_CRP) Read Protection for this Page is Disabled  */
+#define   FUSES_FCR_CRP_VSSRP1_ENABLE_Val     _UINT32_(0x1)                                        /* (FUSES_FCR_CRP) Read Protection for this Page is Enabled  */
+#define FUSES_FCR_CRP_VSSRP1_DISABLE          (FUSES_FCR_CRP_VSSRP1_DISABLE_Val << FUSES_FCR_CRP_VSSRP1_Pos) /* (FUSES_FCR_CRP) Read Protection for this Page is Disabled Position */
+#define FUSES_FCR_CRP_VSSRP1_ENABLE           (FUSES_FCR_CRP_VSSRP1_ENABLE_Val << FUSES_FCR_CRP_VSSRP1_Pos) /* (FUSES_FCR_CRP) Read Protection for this Page is Enabled Position */
+#define FUSES_FCR_CRP_BC1ARPLOCK_Pos          _UINT32_(16)                                         /* (FUSES_FCR_CRP) Panel 1 Lock Read Protection BootCfg1A Position */
+#define FUSES_FCR_CRP_BC1ARPLOCK_Msk          (_UINT32_(0x1) << FUSES_FCR_CRP_BC1ARPLOCK_Pos)      /* (FUSES_FCR_CRP) Panel 1 Lock Read Protection BootCfg1A Mask */
+#define FUSES_FCR_CRP_BC1ARPLOCK(value)       (FUSES_FCR_CRP_BC1ARPLOCK_Msk & (_UINT32_(value) << FUSES_FCR_CRP_BC1ARPLOCK_Pos)) /* Assignment of value for BC1ARPLOCK in the FUSES_FCR_CRP register */
+#define   FUSES_FCR_CRP_BC1ARPLOCK_UNLOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified  */
+#define   FUSES_FCR_CRP_BC1ARPLOCK_LOCKED_Val _UINT32_(0x1)                                        /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FUSES_FCR_CRP_BC1ARPLOCK_UNLOCKED     (FUSES_FCR_CRP_BC1ARPLOCK_UNLOCKED_Val << FUSES_FCR_CRP_BC1ARPLOCK_Pos) /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified Position */
+#define FUSES_FCR_CRP_BC1ARPLOCK_LOCKED       (FUSES_FCR_CRP_BC1ARPLOCK_LOCKED_Val << FUSES_FCR_CRP_BC1ARPLOCK_Pos) /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FUSES_FCR_CRP_BC1RPLOCK_Pos           _UINT32_(18)                                         /* (FUSES_FCR_CRP) Panel 1 Lock Read Protection BootCfg1 Position */
+#define FUSES_FCR_CRP_BC1RPLOCK_Msk           (_UINT32_(0x1) << FUSES_FCR_CRP_BC1RPLOCK_Pos)       /* (FUSES_FCR_CRP) Panel 1 Lock Read Protection BootCfg1 Mask */
+#define FUSES_FCR_CRP_BC1RPLOCK(value)        (FUSES_FCR_CRP_BC1RPLOCK_Msk & (_UINT32_(value) << FUSES_FCR_CRP_BC1RPLOCK_Pos)) /* Assignment of value for BC1RPLOCK in the FUSES_FCR_CRP register */
+#define   FUSES_FCR_CRP_BC1RPLOCK_UNLOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified  */
+#define   FUSES_FCR_CRP_BC1RPLOCK_LOCKED_Val  _UINT32_(0x1)                                        /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FUSES_FCR_CRP_BC1RPLOCK_UNLOCKED      (FUSES_FCR_CRP_BC1RPLOCK_UNLOCKED_Val << FUSES_FCR_CRP_BC1RPLOCK_Pos) /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified Position */
+#define FUSES_FCR_CRP_BC1RPLOCK_LOCKED        (FUSES_FCR_CRP_BC1RPLOCK_LOCKED_Val << FUSES_FCR_CRP_BC1RPLOCK_Pos) /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FUSES_FCR_CRP_RCRPLOCK_Pos            _UINT32_(19)                                         /* (FUSES_FCR_CRP) Panel 1 Lock Read Protection ROMCfg Position */
+#define FUSES_FCR_CRP_RCRPLOCK_Msk            (_UINT32_(0x1) << FUSES_FCR_CRP_RCRPLOCK_Pos)        /* (FUSES_FCR_CRP) Panel 1 Lock Read Protection ROMCfg Mask */
+#define FUSES_FCR_CRP_RCRPLOCK(value)         (FUSES_FCR_CRP_RCRPLOCK_Msk & (_UINT32_(value) << FUSES_FCR_CRP_RCRPLOCK_Pos)) /* Assignment of value for RCRPLOCK in the FUSES_FCR_CRP register */
+#define   FUSES_FCR_CRP_RCRPLOCK_UNLOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified  */
+#define   FUSES_FCR_CRP_RCRPLOCK_LOCKED_Val   _UINT32_(0x1)                                        /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FUSES_FCR_CRP_RCRPLOCK_UNLOCKED       (FUSES_FCR_CRP_RCRPLOCK_UNLOCKED_Val << FUSES_FCR_CRP_RCRPLOCK_Pos) /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified Position */
+#define FUSES_FCR_CRP_RCRPLOCK_LOCKED         (FUSES_FCR_CRP_RCRPLOCK_LOCKED_Val << FUSES_FCR_CRP_RCRPLOCK_Pos) /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FUSES_FCR_CRP_VSSRPLOCK0_Pos          _UINT32_(20)                                         /* (FUSES_FCR_CRP) Panel 1 Lock Read Protection VSSn Position */
+#define FUSES_FCR_CRP_VSSRPLOCK0_Msk          (_UINT32_(0x1) << FUSES_FCR_CRP_VSSRPLOCK0_Pos)      /* (FUSES_FCR_CRP) Panel 1 Lock Read Protection VSSn Mask */
+#define FUSES_FCR_CRP_VSSRPLOCK0(value)       (FUSES_FCR_CRP_VSSRPLOCK0_Msk & (_UINT32_(value) << FUSES_FCR_CRP_VSSRPLOCK0_Pos)) /* Assignment of value for VSSRPLOCK0 in the FUSES_FCR_CRP register */
+#define   FUSES_FCR_CRP_VSSRPLOCK0_UNLOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified  */
+#define   FUSES_FCR_CRP_VSSRPLOCK0_LOCKED_Val _UINT32_(0x1)                                        /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FUSES_FCR_CRP_VSSRPLOCK0_UNLOCKED     (FUSES_FCR_CRP_VSSRPLOCK0_UNLOCKED_Val << FUSES_FCR_CRP_VSSRPLOCK0_Pos) /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified Position */
+#define FUSES_FCR_CRP_VSSRPLOCK0_LOCKED       (FUSES_FCR_CRP_VSSRPLOCK0_LOCKED_Val << FUSES_FCR_CRP_VSSRPLOCK0_Pos) /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FUSES_FCR_CRP_VSSRPLOCK1_Pos          _UINT32_(21)                                         /* (FUSES_FCR_CRP) Panel 1 Lock Read Protection VSSn Position */
+#define FUSES_FCR_CRP_VSSRPLOCK1_Msk          (_UINT32_(0x1) << FUSES_FCR_CRP_VSSRPLOCK1_Pos)      /* (FUSES_FCR_CRP) Panel 1 Lock Read Protection VSSn Mask */
+#define FUSES_FCR_CRP_VSSRPLOCK1(value)       (FUSES_FCR_CRP_VSSRPLOCK1_Msk & (_UINT32_(value) << FUSES_FCR_CRP_VSSRPLOCK1_Pos)) /* Assignment of value for VSSRPLOCK1 in the FUSES_FCR_CRP register */
+#define   FUSES_FCR_CRP_VSSRPLOCK1_UNLOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified  */
+#define   FUSES_FCR_CRP_VSSRPLOCK1_LOCKED_Val _UINT32_(0x1)                                        /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified  */
+#define FUSES_FCR_CRP_VSSRPLOCK1_UNLOCKED     (FUSES_FCR_CRP_VSSRPLOCK1_UNLOCKED_Val << FUSES_FCR_CRP_VSSRPLOCK1_Pos) /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are NOT Locked and can be modified Position */
+#define FUSES_FCR_CRP_VSSRPLOCK1_LOCKED       (FUSES_FCR_CRP_VSSRPLOCK1_LOCKED_Val << FUSES_FCR_CRP_VSSRPLOCK1_Pos) /* (FUSES_FCR_CRP) The Lock &amp;amp; Read Protect bits for this Page are Locked and cannot be modified Position */
+#define FUSES_FCR_CRP_Msk                     _UINT32_(0x003D003D)                                 /* (FUSES_FCR_CRP) Register Mask  */
+
+#define FUSES_FCR_CRP_VSSRP_Pos               _UINT32_(4)                                          /* (FUSES_FCR_CRP Position) Panel x Read Protect VSSn */
+#define FUSES_FCR_CRP_VSSRP_Msk               (_UINT32_(0x3) << FUSES_FCR_CRP_VSSRP_Pos)           /* (FUSES_FCR_CRP Mask) VSSRP */
+#define FUSES_FCR_CRP_VSSRP(value)            (FUSES_FCR_CRP_VSSRP_Msk & (_UINT32_(value) << FUSES_FCR_CRP_VSSRP_Pos)) 
+#define FUSES_FCR_CRP_VSSRPLOCK_Pos           _UINT32_(20)                                         /* (FUSES_FCR_CRP Position) Panel x Lock Read Protection VSSn */
+#define FUSES_FCR_CRP_VSSRPLOCK_Msk           (_UINT32_(0x3) << FUSES_FCR_CRP_VSSRPLOCK_Pos)       /* (FUSES_FCR_CRP Mask) VSSRPLOCK */
+#define FUSES_FCR_CRP_VSSRPLOCK(value)        (FUSES_FCR_CRP_VSSRPLOCK_Msk & (_UINT32_(value) << FUSES_FCR_CRP_VSSRPLOCK_Pos)) 
+
+/* -------- FUSES_FCR_ECCCTRL : (FUSES Offset: 0x884) (R/W 32) ECC Control REGISTER -------- */
+#define FUSES_FCR_ECCCTRL_RESETVALUE          _UINT32_(0x70)                                       /*  (FUSES_FCR_ECCCTRL) ECC Control REGISTER  Reset Value */
+
+#define FUSES_FCR_ECCCTRL_ECCCTL_Pos          _UINT32_(4)                                          /* (FUSES_FCR_ECCCTRL) NVM ECC Mode Control - restricts one or more NVMOPs Position */
+#define FUSES_FCR_ECCCTRL_ECCCTL_Msk          (_UINT32_(0x3) << FUSES_FCR_ECCCTRL_ECCCTL_Pos)      /* (FUSES_FCR_ECCCTRL) NVM ECC Mode Control - restricts one or more NVMOPs Mask */
+#define FUSES_FCR_ECCCTRL_ECCCTL(value)       (FUSES_FCR_ECCCTRL_ECCCTL_Msk & (_UINT32_(value) << FUSES_FCR_ECCCTRL_ECCCTL_Pos)) /* Assignment of value for ECCCTL in the FUSES_FCR_ECCCTRL register */
+#define   FUSES_FCR_ECCCTRL_ECCCTL_STRICT_Val _UINT32_(0x0)                                        /* (FUSES_FCR_ECCCTRL) ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)  */
+#define   FUSES_FCR_ECCCTRL_ECCCTL_DYNAMIC_Val _UINT32_(0x1)                                        /* (FUSES_FCR_ECCCTRL) Dynamic Writes with Dynamic Reads  */
+#define   FUSES_FCR_ECCCTRL_ECCCTL_ECC_Val    _UINT32_(0x2)                                        /* (FUSES_FCR_ECCCTRL) ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)  */
+#define   FUSES_FCR_ECCCTRL_ECCCTL_DISABLE_Val _UINT32_(0x3)                                        /* (FUSES_FCR_ECCCTRL) Dynamic Writes with No Error Check Reads  */
+#define FUSES_FCR_ECCCTRL_ECCCTL_STRICT       (FUSES_FCR_ECCCTRL_ECCCTL_STRICT_Val << FUSES_FCR_ECCCTRL_ECCCTL_Pos) /* (FUSES_FCR_ECCCTRL) ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled) Position */
+#define FUSES_FCR_ECCCTRL_ECCCTL_DYNAMIC      (FUSES_FCR_ECCCTRL_ECCCTL_DYNAMIC_Val << FUSES_FCR_ECCCTRL_ECCCTL_Pos) /* (FUSES_FCR_ECCCTRL) Dynamic Writes with Dynamic Reads Position */
+#define FUSES_FCR_ECCCTRL_ECCCTL_ECC          (FUSES_FCR_ECCCTRL_ECCCTL_ECC_Val << FUSES_FCR_ECCCTRL_ECCCTL_Pos) /* (FUSES_FCR_ECCCTRL) ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled) Position */
+#define FUSES_FCR_ECCCTRL_ECCCTL_DISABLE      (FUSES_FCR_ECCCTRL_ECCCTL_DISABLE_Val << FUSES_FCR_ECCCTRL_ECCCTL_Pos) /* (FUSES_FCR_ECCCTRL) Dynamic Writes with No Error Check Reads Position */
+#define FUSES_FCR_ECCCTRL_ECCUNLCK_Pos        _UINT32_(6)                                          /* (FUSES_FCR_ECCCTRL) NVM ECC Mode Control Unlock Position */
+#define FUSES_FCR_ECCCTRL_ECCUNLCK_Msk        (_UINT32_(0x1) << FUSES_FCR_ECCCTRL_ECCUNLCK_Pos)    /* (FUSES_FCR_ECCCTRL) NVM ECC Mode Control Unlock Mask */
+#define FUSES_FCR_ECCCTRL_ECCUNLCK(value)     (FUSES_FCR_ECCCTRL_ECCUNLCK_Msk & (_UINT32_(value) << FUSES_FCR_ECCCTRL_ECCUNLCK_Pos)) /* Assignment of value for ECCUNLCK in the FUSES_FCR_ECCCTRL register */
+#define   FUSES_FCR_ECCCTRL_ECCUNLCK_LOCKED_Val _UINT32_(0x0)                                        /* (FUSES_FCR_ECCCTRL) ECCUNLCK and ECCCTL[1:0] cannot be written  */
+#define   FUSES_FCR_ECCCTRL_ECCUNLCK_UNLOCKED_Val _UINT32_(0x1)                                        /* (FUSES_FCR_ECCCTRL) ECCUNLCK and ECCCTL[1:0] can be written  */
+#define FUSES_FCR_ECCCTRL_ECCUNLCK_LOCKED     (FUSES_FCR_ECCCTRL_ECCUNLCK_LOCKED_Val << FUSES_FCR_ECCCTRL_ECCUNLCK_Pos) /* (FUSES_FCR_ECCCTRL) ECCUNLCK and ECCCTL[1:0] cannot be written Position */
+#define FUSES_FCR_ECCCTRL_ECCUNLCK_UNLOCKED   (FUSES_FCR_ECCCTRL_ECCUNLCK_UNLOCKED_Val << FUSES_FCR_ECCCTRL_ECCUNLCK_Pos) /* (FUSES_FCR_ECCCTRL) ECCUNLCK and ECCCTL[1:0] can be written Position */
+#define FUSES_FCR_ECCCTRL_SECCNT_Pos          _UINT32_(8)                                          /* (FUSES_FCR_ECCCTRL) Flash SEC Count Position */
+#define FUSES_FCR_ECCCTRL_SECCNT_Msk          (_UINT32_(0xFF) << FUSES_FCR_ECCCTRL_SECCNT_Pos)     /* (FUSES_FCR_ECCCTRL) Flash SEC Count Mask */
+#define FUSES_FCR_ECCCTRL_SECCNT(value)       (FUSES_FCR_ECCCTRL_SECCNT_Msk & (_UINT32_(value) << FUSES_FCR_ECCCTRL_SECCNT_Pos)) /* Assignment of value for SECCNT in the FUSES_FCR_ECCCTRL register */
+#define FUSES_FCR_ECCCTRL_Msk                 _UINT32_(0x0000FF70)                                 /* (FUSES_FCR_ECCCTRL) Register Mask  */
+
+
+/* -------- FUSES_SUPC_BRCFGUSMOR_BOR : (FUSES Offset: 0x888) (R/W 32) Boot Rom Configurable SMOR User CFG BOR register -------- */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_RESETVALUE  _UINT32_(0x00)                                       /*  (FUSES_SUPC_BRCFGUSMOR_BOR) Boot Rom Configurable SMOR User CFG BOR register  Reset Value */
+
+#define FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_Pos _UINT32_(0)                                          /* (FUSES_SUPC_BRCFGUSMOR_BOR) Refer to pwr_smor_[nn]_v2 DOS document for details. Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_Msk (_UINT32_(0x1) << FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) Refer to pwr_smor_[nn]_v2 DOS document for details. Mask */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO(value) (FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_Msk & (_UINT32_(value) << FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_Pos)) /* Assignment of value for HYST_BOR_VDDIO in the FUSES_SUPC_BRCFGUSMOR_BOR register */
+#define   FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_LOW_Val _UINT32_(0x0)                                        /* (FUSES_SUPC_BRCFGUSMOR_BOR) Low Hysteresis (default)  */
+#define   FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_HIGH_Val _UINT32_(0x1)                                        /* (FUSES_SUPC_BRCFGUSMOR_BOR) High Hysteresis  */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_LOW (FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_LOW_Val << FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) Low Hysteresis (default) Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_HIGH (FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_HIGH_Val << FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDIO_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) High Hysteresis Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_Pos _UINT32_(1)                                          /* (FUSES_SUPC_BRCFGUSMOR_BOR) Nominal BOR Trip, Refer to pwr_smor_[nn]_v2 DOS document for details. Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_Msk (_UINT32_(0x3) << FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) Nominal BOR Trip, Refer to pwr_smor_[nn]_v2 DOS document for details. Mask */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO(value) (FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_Msk & (_UINT32_(value) << FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_Pos)) /* Assignment of value for BOR_TRIP_VDDIO in the FUSES_SUPC_BRCFGUSMOR_BOR register */
+#define   FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_0_Val _UINT32_(0x0)                                        /* (FUSES_SUPC_BRCFGUSMOR_BOR) 1.68V (default)  */
+#define   FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_1_Val _UINT32_(0x1)                                        /* (FUSES_SUPC_BRCFGUSMOR_BOR) 2.2V  */
+#define   FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_2_Val _UINT32_(0x2)                                        /* (FUSES_SUPC_BRCFGUSMOR_BOR) 2.64V  */
+#define   FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_3_Val _UINT32_(0x3)                                        /* (FUSES_SUPC_BRCFGUSMOR_BOR) 2.93V  */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_0 (FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_0_Val << FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) 1.68V (default) Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_1 (FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_1_Val << FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) 2.2V Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_2 (FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_2_Val << FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) 2.64V Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_3 (FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_3_Val << FUSES_SUPC_BRCFGUSMOR_BOR_BOR_TRIP_VDDIO_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) 2.93V Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_Pos _UINT32_(10)                                         /* (FUSES_SUPC_BRCFGUSMOR_BOR) Refer to pwr_smor_[nn]_v2 DOS document for details. Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_Msk (_UINT32_(0x1) << FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) Refer to pwr_smor_[nn]_v2 DOS document for details. Mask */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG(value) (FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_Msk & (_UINT32_(value) << FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_Pos)) /* Assignment of value for HYST_BOR_VDDREG in the FUSES_SUPC_BRCFGUSMOR_BOR register */
+#define   FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_LOW_Val _UINT32_(0x0)                                        /* (FUSES_SUPC_BRCFGUSMOR_BOR) Low Hysteresis (default)  */
+#define   FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_HIGH_Val _UINT32_(0x1)                                        /* (FUSES_SUPC_BRCFGUSMOR_BOR) High Hysteresis  */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_LOW (FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_LOW_Val << FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) Low Hysteresis (default) Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_HIGH (FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_HIGH_Val << FUSES_SUPC_BRCFGUSMOR_BOR_HYST_BOR_VDDREG_Pos) /* (FUSES_SUPC_BRCFGUSMOR_BOR) High Hysteresis Position */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_Msk         _UINT32_(0x00000407)                                 /* (FUSES_SUPC_BRCFGUSMOR_BOR) Register Mask  */
+
+
+/* -------- FUSES_SUPC_BRCFGUDSSMOR : (FUSES Offset: 0x890) (R/W 32) Boot Rom Configurable DSSMOR User CFG register -------- */
+#define FUSES_SUPC_BRCFGUDSSMOR_RESETVALUE    _UINT32_(0x00)                                       /*  (FUSES_SUPC_BRCFGUDSSMOR) Boot Rom Configurable DSSMOR User CFG register  Reset Value */
+
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_Pos  _UINT32_(0)                                          /* (FUSES_SUPC_BRCFGUDSSMOR) Refer to pwr_smor_ds_[nn]_v2 DOS document for details. Position */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_Msk  (_UINT32_(0x1) << FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_Pos) /* (FUSES_SUPC_BRCFGUDSSMOR) Refer to pwr_smor_ds_[nn]_v2 DOS document for details. Mask */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST(value) (FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_Msk & (_UINT32_(value) << FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_Pos)) /* Assignment of value for BOR_HYST in the FUSES_SUPC_BRCFGUDSSMOR register */
+#define   FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_LOW_Val _UINT32_(0x0)                                        /* (FUSES_SUPC_BRCFGUDSSMOR) Low Hysteresis (default)  */
+#define   FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_HIGH_Val _UINT32_(0x1)                                        /* (FUSES_SUPC_BRCFGUDSSMOR) High Hysteresis  */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_LOW  (FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_LOW_Val << FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_Pos) /* (FUSES_SUPC_BRCFGUDSSMOR) Low Hysteresis (default) Position */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_HIGH (FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_HIGH_Val << FUSES_SUPC_BRCFGUDSSMOR_BOR_HYST_Pos) /* (FUSES_SUPC_BRCFGUDSSMOR) High Hysteresis Position */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_Pos  _UINT32_(1)                                          /* (FUSES_SUPC_BRCFGUDSSMOR) Nominal BOR Trip, Refer to pwr_smor_ds_[nn]_v2 DOS document for details. Position */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_Msk  (_UINT32_(0x3) << FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_Pos) /* (FUSES_SUPC_BRCFGUDSSMOR) Nominal BOR Trip, Refer to pwr_smor_ds_[nn]_v2 DOS document for details. Mask */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP(value) (FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_Msk & (_UINT32_(value) << FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_Pos)) /* Assignment of value for BOR_TRIP in the FUSES_SUPC_BRCFGUDSSMOR register */
+#define   FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_0_Val _UINT32_(0x0)                                        /* (FUSES_SUPC_BRCFGUDSSMOR) 1.61V (default)  */
+#define   FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_1_Val _UINT32_(0x1)                                        /* (FUSES_SUPC_BRCFGUDSSMOR) 2.12V  */
+#define   FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_2_Val _UINT32_(0x2)                                        /* (FUSES_SUPC_BRCFGUDSSMOR) 2.55V  */
+#define   FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_3_Val _UINT32_(0x3)                                        /* (FUSES_SUPC_BRCFGUDSSMOR) 2.8V  */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_0    (FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_0_Val << FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_Pos) /* (FUSES_SUPC_BRCFGUDSSMOR) 1.61V (default) Position */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_1    (FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_1_Val << FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_Pos) /* (FUSES_SUPC_BRCFGUDSSMOR) 2.12V Position */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_2    (FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_2_Val << FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_Pos) /* (FUSES_SUPC_BRCFGUDSSMOR) 2.55V Position */
+#define FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_3    (FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_3_Val << FUSES_SUPC_BRCFGUDSSMOR_BOR_TRIP_Pos) /* (FUSES_SUPC_BRCFGUDSSMOR) 2.8V Position */
+#define FUSES_SUPC_BRCFGUDSSMOR_Msk           _UINT32_(0x00000007)                                 /* (FUSES_SUPC_BRCFGUDSSMOR) Register Mask  */
+
+
+/* -------- FUSES_SUPC_BRCFGUCP0 : (FUSES Offset: 0x894) (R/W 32) Boot Rom Configurable CHARGE PUMP User CFG register -------- */
+#define FUSES_SUPC_BRCFGUCP0_RESETVALUE       _UINT32_(0x01)                                       /*  (FUSES_SUPC_BRCFGUCP0) Boot Rom Configurable CHARGE PUMP User CFG register  Reset Value */
+
+#define FUSES_SUPC_BRCFGUCP0_CP_Pos           _UINT32_(0)                                          /* (FUSES_SUPC_BRCFGUCP0) Refer to vreg_chrg_pump_v4 DOS document for details. Position */
+#define FUSES_SUPC_BRCFGUCP0_CP_Msk           (_UINT32_(0xF) << FUSES_SUPC_BRCFGUCP0_CP_Pos)       /* (FUSES_SUPC_BRCFGUCP0) Refer to vreg_chrg_pump_v4 DOS document for details. Mask */
+#define FUSES_SUPC_BRCFGUCP0_CP(value)        (FUSES_SUPC_BRCFGUCP0_CP_Msk & (_UINT32_(value) << FUSES_SUPC_BRCFGUCP0_CP_Pos)) /* Assignment of value for CP in the FUSES_SUPC_BRCFGUCP0 register */
+#define   FUSES_SUPC_BRCFGUCP0_CP_0_Val       _UINT32_(0x0)                                        /* (FUSES_SUPC_BRCFGUCP0) Clock gating trip optimized for low output threshold voltage (3.01V)  */
+#define   FUSES_SUPC_BRCFGUCP0_CP_1_Val       _UINT32_(0x1)                                        /* (FUSES_SUPC_BRCFGUCP0) Clock gating trip optimized for high output threshold voltage (3.2V) (default)  */
+#define FUSES_SUPC_BRCFGUCP0_CP_0             (FUSES_SUPC_BRCFGUCP0_CP_0_Val << FUSES_SUPC_BRCFGUCP0_CP_Pos) /* (FUSES_SUPC_BRCFGUCP0) Clock gating trip optimized for low output threshold voltage (3.01V) Position */
+#define FUSES_SUPC_BRCFGUCP0_CP_1             (FUSES_SUPC_BRCFGUCP0_CP_1_Val << FUSES_SUPC_BRCFGUCP0_CP_Pos) /* (FUSES_SUPC_BRCFGUCP0) Clock gating trip optimized for high output threshold voltage (3.2V) (default) Position */
+#define FUSES_SUPC_BRCFGUCP0_Msk              _UINT32_(0x0000000F)                                 /* (FUSES_SUPC_BRCFGUCP0) Register Mask  */
+
+
+/* -------- FUSES_WDT_SETUP : (FUSES Offset: 0x898) (R/W 32)  -------- */
+#define FUSES_WDT_SETUP_RESETVALUE            _UINT32_(0x00)                                       /*  (FUSES_WDT_SETUP)   Reset Value */
+
+#define FUSES_WDT_SETUP_ENABLE_Pos            _UINT32_(1)                                          /* (FUSES_WDT_SETUP) Enable Position */
+#define FUSES_WDT_SETUP_ENABLE_Msk            (_UINT32_(0x1) << FUSES_WDT_SETUP_ENABLE_Pos)        /* (FUSES_WDT_SETUP) Enable Mask */
+#define FUSES_WDT_SETUP_ENABLE(value)         (FUSES_WDT_SETUP_ENABLE_Msk & (_UINT32_(value) << FUSES_WDT_SETUP_ENABLE_Pos)) /* Assignment of value for ENABLE in the FUSES_WDT_SETUP register */
+#define FUSES_WDT_SETUP_WEN_Pos               _UINT32_(2)                                          /* (FUSES_WDT_SETUP) Watchdog Timer Window Mode Enable Position */
+#define FUSES_WDT_SETUP_WEN_Msk               (_UINT32_(0x1) << FUSES_WDT_SETUP_WEN_Pos)           /* (FUSES_WDT_SETUP) Watchdog Timer Window Mode Enable Mask */
+#define FUSES_WDT_SETUP_WEN(value)            (FUSES_WDT_SETUP_WEN_Msk & (_UINT32_(value) << FUSES_WDT_SETUP_WEN_Pos)) /* Assignment of value for WEN in the FUSES_WDT_SETUP register */
+#define FUSES_WDT_SETUP_RUNSTDBY_Pos          _UINT32_(6)                                          /* (FUSES_WDT_SETUP) Run During Standby Position */
+#define FUSES_WDT_SETUP_RUNSTDBY_Msk          (_UINT32_(0x1) << FUSES_WDT_SETUP_RUNSTDBY_Pos)      /* (FUSES_WDT_SETUP) Run During Standby Mask */
+#define FUSES_WDT_SETUP_RUNSTDBY(value)       (FUSES_WDT_SETUP_RUNSTDBY_Msk & (_UINT32_(value) << FUSES_WDT_SETUP_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the FUSES_WDT_SETUP register */
+#define FUSES_WDT_SETUP_ALWAYSON_Pos          _UINT32_(7)                                          /* (FUSES_WDT_SETUP) Always-On Position */
+#define FUSES_WDT_SETUP_ALWAYSON_Msk          (_UINT32_(0x1) << FUSES_WDT_SETUP_ALWAYSON_Pos)      /* (FUSES_WDT_SETUP) Always-On Mask */
+#define FUSES_WDT_SETUP_ALWAYSON(value)       (FUSES_WDT_SETUP_ALWAYSON_Msk & (_UINT32_(value) << FUSES_WDT_SETUP_ALWAYSON_Pos)) /* Assignment of value for ALWAYSON in the FUSES_WDT_SETUP register */
+#define FUSES_WDT_SETUP_PER_Pos               _UINT32_(8)                                          /* (FUSES_WDT_SETUP) Time-Out Period Position */
+#define FUSES_WDT_SETUP_PER_Msk               (_UINT32_(0xF) << FUSES_WDT_SETUP_PER_Pos)           /* (FUSES_WDT_SETUP) Time-Out Period Mask */
+#define FUSES_WDT_SETUP_PER(value)            (FUSES_WDT_SETUP_PER_Msk & (_UINT32_(value) << FUSES_WDT_SETUP_PER_Pos)) /* Assignment of value for PER in the FUSES_WDT_SETUP register */
+#define   FUSES_WDT_SETUP_PER_CYC8_Val        _UINT32_(0x0)                                        /* (FUSES_WDT_SETUP) 8 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC16_Val       _UINT32_(0x1)                                        /* (FUSES_WDT_SETUP) 16 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC32_Val       _UINT32_(0x2)                                        /* (FUSES_WDT_SETUP) 32 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC64_Val       _UINT32_(0x3)                                        /* (FUSES_WDT_SETUP) 64 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC128_Val      _UINT32_(0x4)                                        /* (FUSES_WDT_SETUP) 128 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC256_Val      _UINT32_(0x5)                                        /* (FUSES_WDT_SETUP) 256 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC512_Val      _UINT32_(0x6)                                        /* (FUSES_WDT_SETUP) 512 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC1024_Val     _UINT32_(0x7)                                        /* (FUSES_WDT_SETUP) 1024 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC2048_Val     _UINT32_(0x8)                                        /* (FUSES_WDT_SETUP) 2048 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC4096_Val     _UINT32_(0x9)                                        /* (FUSES_WDT_SETUP) 4096 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC8192_Val     _UINT32_(0xA)                                        /* (FUSES_WDT_SETUP) 8192 clock cycles  */
+#define   FUSES_WDT_SETUP_PER_CYC16384_Val    _UINT32_(0xB)                                        /* (FUSES_WDT_SETUP) 16384 clock cycles  */
+#define FUSES_WDT_SETUP_PER_CYC8              (FUSES_WDT_SETUP_PER_CYC8_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 8 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC16             (FUSES_WDT_SETUP_PER_CYC16_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 16 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC32             (FUSES_WDT_SETUP_PER_CYC32_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 32 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC64             (FUSES_WDT_SETUP_PER_CYC64_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 64 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC128            (FUSES_WDT_SETUP_PER_CYC128_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 128 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC256            (FUSES_WDT_SETUP_PER_CYC256_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 256 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC512            (FUSES_WDT_SETUP_PER_CYC512_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 512 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC1024           (FUSES_WDT_SETUP_PER_CYC1024_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 1024 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC2048           (FUSES_WDT_SETUP_PER_CYC2048_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 2048 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC4096           (FUSES_WDT_SETUP_PER_CYC4096_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 4096 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC8192           (FUSES_WDT_SETUP_PER_CYC8192_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 8192 clock cycles Position */
+#define FUSES_WDT_SETUP_PER_CYC16384          (FUSES_WDT_SETUP_PER_CYC16384_Val << FUSES_WDT_SETUP_PER_Pos) /* (FUSES_WDT_SETUP) 16384 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_Pos            _UINT32_(12)                                         /* (FUSES_WDT_SETUP) Window Mode Time-Out Period Position */
+#define FUSES_WDT_SETUP_WINDOW_Msk            (_UINT32_(0xF) << FUSES_WDT_SETUP_WINDOW_Pos)        /* (FUSES_WDT_SETUP) Window Mode Time-Out Period Mask */
+#define FUSES_WDT_SETUP_WINDOW(value)         (FUSES_WDT_SETUP_WINDOW_Msk & (_UINT32_(value) << FUSES_WDT_SETUP_WINDOW_Pos)) /* Assignment of value for WINDOW in the FUSES_WDT_SETUP register */
+#define   FUSES_WDT_SETUP_WINDOW_CYC8_Val     _UINT32_(0x0)                                        /* (FUSES_WDT_SETUP) 8 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC16_Val    _UINT32_(0x1)                                        /* (FUSES_WDT_SETUP) 16 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC32_Val    _UINT32_(0x2)                                        /* (FUSES_WDT_SETUP) 32 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC64_Val    _UINT32_(0x3)                                        /* (FUSES_WDT_SETUP) 64 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC128_Val   _UINT32_(0x4)                                        /* (FUSES_WDT_SETUP) 128 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC256_Val   _UINT32_(0x5)                                        /* (FUSES_WDT_SETUP) 256 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC512_Val   _UINT32_(0x6)                                        /* (FUSES_WDT_SETUP) 512 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC1024_Val  _UINT32_(0x7)                                        /* (FUSES_WDT_SETUP) 1024 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC2048_Val  _UINT32_(0x8)                                        /* (FUSES_WDT_SETUP) 2048 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC4096_Val  _UINT32_(0x9)                                        /* (FUSES_WDT_SETUP) 4096 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC8192_Val  _UINT32_(0xA)                                        /* (FUSES_WDT_SETUP) 8192 clock cycles  */
+#define   FUSES_WDT_SETUP_WINDOW_CYC16384_Val _UINT32_(0xB)                                        /* (FUSES_WDT_SETUP) 16384 clock cycles  */
+#define FUSES_WDT_SETUP_WINDOW_CYC8           (FUSES_WDT_SETUP_WINDOW_CYC8_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 8 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC16          (FUSES_WDT_SETUP_WINDOW_CYC16_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 16 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC32          (FUSES_WDT_SETUP_WINDOW_CYC32_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 32 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC64          (FUSES_WDT_SETUP_WINDOW_CYC64_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 64 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC128         (FUSES_WDT_SETUP_WINDOW_CYC128_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 128 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC256         (FUSES_WDT_SETUP_WINDOW_CYC256_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 256 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC512         (FUSES_WDT_SETUP_WINDOW_CYC512_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 512 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC1024        (FUSES_WDT_SETUP_WINDOW_CYC1024_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 1024 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC2048        (FUSES_WDT_SETUP_WINDOW_CYC2048_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 2048 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC4096        (FUSES_WDT_SETUP_WINDOW_CYC4096_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 4096 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC8192        (FUSES_WDT_SETUP_WINDOW_CYC8192_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 8192 clock cycles Position */
+#define FUSES_WDT_SETUP_WINDOW_CYC16384       (FUSES_WDT_SETUP_WINDOW_CYC16384_Val << FUSES_WDT_SETUP_WINDOW_Pos) /* (FUSES_WDT_SETUP) 16384 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_Pos          _UINT32_(16)                                         /* (FUSES_WDT_SETUP) Early Warning Interrupt Time Offset Position */
+#define FUSES_WDT_SETUP_EWOFFSET_Msk          (_UINT32_(0xF) << FUSES_WDT_SETUP_EWOFFSET_Pos)      /* (FUSES_WDT_SETUP) Early Warning Interrupt Time Offset Mask */
+#define FUSES_WDT_SETUP_EWOFFSET(value)       (FUSES_WDT_SETUP_EWOFFSET_Msk & (_UINT32_(value) << FUSES_WDT_SETUP_EWOFFSET_Pos)) /* Assignment of value for EWOFFSET in the FUSES_WDT_SETUP register */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC8_Val   _UINT32_(0x0)                                        /* (FUSES_WDT_SETUP) 8 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC16_Val  _UINT32_(0x1)                                        /* (FUSES_WDT_SETUP) 16 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC32_Val  _UINT32_(0x2)                                        /* (FUSES_WDT_SETUP) 32 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC64_Val  _UINT32_(0x3)                                        /* (FUSES_WDT_SETUP) 64 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC128_Val _UINT32_(0x4)                                        /* (FUSES_WDT_SETUP) 128 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC256_Val _UINT32_(0x5)                                        /* (FUSES_WDT_SETUP) 256 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC512_Val _UINT32_(0x6)                                        /* (FUSES_WDT_SETUP) 512 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC1024_Val _UINT32_(0x7)                                        /* (FUSES_WDT_SETUP) 1024 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC2048_Val _UINT32_(0x8)                                        /* (FUSES_WDT_SETUP) 2048 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC4096_Val _UINT32_(0x9)                                        /* (FUSES_WDT_SETUP) 4096 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC8192_Val _UINT32_(0xA)                                        /* (FUSES_WDT_SETUP) 8192 clock cycles  */
+#define   FUSES_WDT_SETUP_EWOFFSET_CYC16384_Val _UINT32_(0xB)                                        /* (FUSES_WDT_SETUP) 16384 clock cycles  */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC8         (FUSES_WDT_SETUP_EWOFFSET_CYC8_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 8 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC16        (FUSES_WDT_SETUP_EWOFFSET_CYC16_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 16 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC32        (FUSES_WDT_SETUP_EWOFFSET_CYC32_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 32 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC64        (FUSES_WDT_SETUP_EWOFFSET_CYC64_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 64 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC128       (FUSES_WDT_SETUP_EWOFFSET_CYC128_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 128 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC256       (FUSES_WDT_SETUP_EWOFFSET_CYC256_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 256 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC512       (FUSES_WDT_SETUP_EWOFFSET_CYC512_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 512 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC1024      (FUSES_WDT_SETUP_EWOFFSET_CYC1024_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 1024 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC2048      (FUSES_WDT_SETUP_EWOFFSET_CYC2048_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 2048 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC4096      (FUSES_WDT_SETUP_EWOFFSET_CYC4096_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 4096 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC8192      (FUSES_WDT_SETUP_EWOFFSET_CYC8192_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 8192 clock cycles Position */
+#define FUSES_WDT_SETUP_EWOFFSET_CYC16384     (FUSES_WDT_SETUP_EWOFFSET_CYC16384_Val << FUSES_WDT_SETUP_EWOFFSET_Pos) /* (FUSES_WDT_SETUP) 16384 clock cycles Position */
+#define FUSES_WDT_SETUP_Msk                   _UINT32_(0x000FFFC6)                                 /* (FUSES_WDT_SETUP) Register Mask  */
+
+
+/* -------- FUSES_F1RR : (FUSES Offset: 0x00) ( R/ 32) PANEL 0 REDUNDANCY RECORD 1-0 Register -------- */
+#define FUSES_F1RR_RR0ADDR_Pos                _UINT32_(0)                                          /* (FUSES_F1RR) Redundancy Replaced Page Address Position */
+#define FUSES_F1RR_RR0ADDR_Msk                (_UINT32_(0x7F) << FUSES_F1RR_RR0ADDR_Pos)           /* (FUSES_F1RR) Redundancy Replaced Page Address Mask */
+#define FUSES_F1RR_RR0ADDR(value)             (FUSES_F1RR_RR0ADDR_Msk & (_UINT32_(value) << FUSES_F1RR_RR0ADDR_Pos)) /* Assignment of value for RR0ADDR in the FUSES_F1RR register */
+#define FUSES_F1RR_RR0DIS_Pos                 _UINT32_(15)                                         /* (FUSES_F1RR) Redundancy Record 0 enabled Position */
+#define FUSES_F1RR_RR0DIS_Msk                 (_UINT32_(0x1) << FUSES_F1RR_RR0DIS_Pos)             /* (FUSES_F1RR) Redundancy Record 0 enabled Mask */
+#define FUSES_F1RR_RR0DIS(value)              (FUSES_F1RR_RR0DIS_Msk & (_UINT32_(value) << FUSES_F1RR_RR0DIS_Pos)) /* Assignment of value for RR0DIS in the FUSES_F1RR register */
+#define   FUSES_F1RR_RR0DIS_0_Val             _UINT32_(0x0)                                        /* (FUSES_F1RR) FCR maps the redundant page 0 into the address defined by RR0ADDR  */
+#define   FUSES_F1RR_RR0DIS_1_Val             _UINT32_(0x1)                                        /* (FUSES_F1RR) Redundant page 0 mapping is Disabled  */
+#define FUSES_F1RR_RR0DIS_0                   (FUSES_F1RR_RR0DIS_0_Val << FUSES_F1RR_RR0DIS_Pos)   /* (FUSES_F1RR) FCR maps the redundant page 0 into the address defined by RR0ADDR Position */
+#define FUSES_F1RR_RR0DIS_1                   (FUSES_F1RR_RR0DIS_1_Val << FUSES_F1RR_RR0DIS_Pos)   /* (FUSES_F1RR) Redundant page 0 mapping is Disabled Position */
+#define FUSES_F1RR_RR1ADDR_Pos                _UINT32_(16)                                         /* (FUSES_F1RR) Redundancy Replaced Page Address Position */
+#define FUSES_F1RR_RR1ADDR_Msk                (_UINT32_(0x7F) << FUSES_F1RR_RR1ADDR_Pos)           /* (FUSES_F1RR) Redundancy Replaced Page Address Mask */
+#define FUSES_F1RR_RR1ADDR(value)             (FUSES_F1RR_RR1ADDR_Msk & (_UINT32_(value) << FUSES_F1RR_RR1ADDR_Pos)) /* Assignment of value for RR1ADDR in the FUSES_F1RR register */
+#define FUSES_F1RR_RR1DIS_Pos                 _UINT32_(31)                                         /* (FUSES_F1RR) Redundancy Record 1 enabled Position */
+#define FUSES_F1RR_RR1DIS_Msk                 (_UINT32_(0x1) << FUSES_F1RR_RR1DIS_Pos)             /* (FUSES_F1RR) Redundancy Record 1 enabled Mask */
+#define FUSES_F1RR_RR1DIS(value)              (FUSES_F1RR_RR1DIS_Msk & (_UINT32_(value) << FUSES_F1RR_RR1DIS_Pos)) /* Assignment of value for RR1DIS in the FUSES_F1RR register */
+#define   FUSES_F1RR_RR1DIS_0_Val             _UINT32_(0x0)                                        /* (FUSES_F1RR) FCR maps the redundant page 1 into the address defined by RR1ADDR  */
+#define   FUSES_F1RR_RR1DIS_1_Val             _UINT32_(0x1)                                        /* (FUSES_F1RR) Redundant page 1 mapping is Disabled  */
+#define FUSES_F1RR_RR1DIS_0                   (FUSES_F1RR_RR1DIS_0_Val << FUSES_F1RR_RR1DIS_Pos)   /* (FUSES_F1RR) FCR maps the redundant page 1 into the address defined by RR1ADDR Position */
+#define FUSES_F1RR_RR1DIS_1                   (FUSES_F1RR_RR1DIS_1_Val << FUSES_F1RR_RR1DIS_Pos)   /* (FUSES_F1RR) Redundant page 1 mapping is Disabled Position */
+#define FUSES_F1RR_Msk                        _UINT32_(0x807F807F)                                 /* (FUSES_F1RR) Register Mask  */
+
+
+/* -------- FUSES_FCCFG0 : (FUSES Offset: 0x80) ( R/ 32) Calibration Configuration 0 Register -------- */
+#define FUSES_FCCFG0_CFG_SMOR0_Pos            _UINT32_(0)                                          /* (FUSES_FCCFG0) SMOR configuration bits Position */
+#define FUSES_FCCFG0_CFG_SMOR0_Msk            (_UINT32_(0xFFFFFFFF) << FUSES_FCCFG0_CFG_SMOR0_Pos) /* (FUSES_FCCFG0) SMOR configuration bits Mask */
+#define FUSES_FCCFG0_CFG_SMOR0(value)         (FUSES_FCCFG0_CFG_SMOR0_Msk & (_UINT32_(value) << FUSES_FCCFG0_CFG_SMOR0_Pos)) /* Assignment of value for CFG_SMOR0 in the FUSES_FCCFG0 register */
+#define FUSES_FCCFG0_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (FUSES_FCCFG0) Register Mask  */
+
+
+/* -------- FUSES_FCCFG1 : (FUSES Offset: 0x84) ( R/ 32) Calibration Configuration 1 Register -------- */
+#define FUSES_FCCFG1_CFG_SMOR1_Pos            _UINT32_(0)                                          /* (FUSES_FCCFG1) SMOR configuration bits Position */
+#define FUSES_FCCFG1_CFG_SMOR1_Msk            (_UINT32_(0xFFFFFFFF) << FUSES_FCCFG1_CFG_SMOR1_Pos) /* (FUSES_FCCFG1) SMOR configuration bits Mask */
+#define FUSES_FCCFG1_CFG_SMOR1(value)         (FUSES_FCCFG1_CFG_SMOR1_Msk & (_UINT32_(value) << FUSES_FCCFG1_CFG_SMOR1_Pos)) /* Assignment of value for CFG_SMOR1 in the FUSES_FCCFG1 register */
+#define FUSES_FCCFG1_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (FUSES_FCCFG1) Register Mask  */
+
+
+/* -------- FUSES_FCCFG8 : (FUSES Offset: 0xA0) ( R/ 32) Calibration Configuration 8 Register -------- */
+#define FUSES_FCCFG8_CFG_DS_SMOR_REF_Pos      _UINT32_(0)                                          /* (FUSES_FCCFG8) DSSMOR configuration bits Position */
+#define FUSES_FCCFG8_CFG_DS_SMOR_REF_Msk      (_UINT32_(0xFFFF) << FUSES_FCCFG8_CFG_DS_SMOR_REF_Pos) /* (FUSES_FCCFG8) DSSMOR configuration bits Mask */
+#define FUSES_FCCFG8_CFG_DS_SMOR_REF(value)   (FUSES_FCCFG8_CFG_DS_SMOR_REF_Msk & (_UINT32_(value) << FUSES_FCCFG8_CFG_DS_SMOR_REF_Pos)) /* Assignment of value for CFG_DS_SMOR_REF in the FUSES_FCCFG8 register */
+#define FUSES_FCCFG8_CFG_DS_SMOR_CLK_Pos      _UINT32_(16)                                         /* (FUSES_FCCFG8) DSSMOR configuration bits Position */
+#define FUSES_FCCFG8_CFG_DS_SMOR_CLK_Msk      (_UINT32_(0xFFFF) << FUSES_FCCFG8_CFG_DS_SMOR_CLK_Pos) /* (FUSES_FCCFG8) DSSMOR configuration bits Mask */
+#define FUSES_FCCFG8_CFG_DS_SMOR_CLK(value)   (FUSES_FCCFG8_CFG_DS_SMOR_CLK_Msk & (_UINT32_(value) << FUSES_FCCFG8_CFG_DS_SMOR_CLK_Pos)) /* Assignment of value for CFG_DS_SMOR_CLK in the FUSES_FCCFG8 register */
+#define FUSES_FCCFG8_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (FUSES_FCCFG8) Register Mask  */
+
+
+/* -------- FUSES_FCCFG16 : (FUSES Offset: 0xC0) ( R/ 32) Calibration Configuration 16 Register -------- */
+#define FUSES_FCCFG16_CFG_DFLL48M_Pos         _UINT32_(0)                                          /* (FUSES_FCCFG16) Comparator configuration bits Position */
+#define FUSES_FCCFG16_CFG_DFLL48M_Msk         (_UINT32_(0xFFFFFFFF) << FUSES_FCCFG16_CFG_DFLL48M_Pos) /* (FUSES_FCCFG16) Comparator configuration bits Mask */
+#define FUSES_FCCFG16_CFG_DFLL48M(value)      (FUSES_FCCFG16_CFG_DFLL48M_Msk & (_UINT32_(value) << FUSES_FCCFG16_CFG_DFLL48M_Pos)) /* Assignment of value for CFG_DFLL48M in the FUSES_FCCFG16 register */
+#define FUSES_FCCFG16_Msk                     _UINT32_(0xFFFFFFFF)                                 /* (FUSES_FCCFG16) Register Mask  */
+
+
+/* -------- FUSES_FCCFG17 : (FUSES Offset: 0xC4) ( R/ 32) Calibration Configuration 17 Register -------- */
+#define FUSES_FCCFG17_CFG_XTAL_HF_Pos         _UINT32_(0)                                          /* (FUSES_FCCFG17) Crystal Oscillator calibration configuration bits Position */
+#define FUSES_FCCFG17_CFG_XTAL_HF_Msk         (_UINT32_(0xFFFF) << FUSES_FCCFG17_CFG_XTAL_HF_Pos)  /* (FUSES_FCCFG17) Crystal Oscillator calibration configuration bits Mask */
+#define FUSES_FCCFG17_CFG_XTAL_HF(value)      (FUSES_FCCFG17_CFG_XTAL_HF_Msk & (_UINT32_(value) << FUSES_FCCFG17_CFG_XTAL_HF_Pos)) /* Assignment of value for CFG_XTAL_HF in the FUSES_FCCFG17 register */
+#define FUSES_FCCFG17_Msk                     _UINT32_(0x0000FFFF)                                 /* (FUSES_FCCFG17) Register Mask  */
+
+
+/* -------- FUSES_FCCFG24 : (FUSES Offset: 0xE0) ( R/ 32) Calibration Configuration 24 Register -------- */
+#define FUSES_FCCFG24_CFG_CALVREGSW0_Pos      _UINT32_(0)                                          /* (FUSES_FCCFG24) 99 ma VREG Calibration configuration bits Position */
+#define FUSES_FCCFG24_CFG_CALVREGSW0_Msk      (_UINT32_(0xFFFF) << FUSES_FCCFG24_CFG_CALVREGSW0_Pos) /* (FUSES_FCCFG24) 99 ma VREG Calibration configuration bits Mask */
+#define FUSES_FCCFG24_CFG_CALVREGSW0(value)   (FUSES_FCCFG24_CFG_CALVREGSW0_Msk & (_UINT32_(value) << FUSES_FCCFG24_CFG_CALVREGSW0_Pos)) /* Assignment of value for CFG_CALVREGSW0 in the FUSES_FCCFG24 register */
+#define FUSES_FCCFG24_Msk                     _UINT32_(0x0000FFFF)                                 /* (FUSES_FCCFG24) Register Mask  */
+
+
+/* -------- FUSES_FCCFG27 : (FUSES Offset: 0xEC) ( R/ 32) Calibration Configuration 27 Register -------- */
+#define FUSES_FCCFG27_CFG_CALVREGRAM_Pos      _UINT32_(16)                                         /* (FUSES_FCCFG27) 50 ma VREG Calibration configuration bits Position */
+#define FUSES_FCCFG27_CFG_CALVREGRAM_Msk      (_UINT32_(0xFFFF) << FUSES_FCCFG27_CFG_CALVREGRAM_Pos) /* (FUSES_FCCFG27) 50 ma VREG Calibration configuration bits Mask */
+#define FUSES_FCCFG27_CFG_CALVREGRAM(value)   (FUSES_FCCFG27_CFG_CALVREGRAM_Msk & (_UINT32_(value) << FUSES_FCCFG27_CFG_CALVREGRAM_Pos)) /* Assignment of value for CFG_CALVREGRAM in the FUSES_FCCFG27 register */
+#define FUSES_FCCFG27_Msk                     _UINT32_(0xFFFF0000)                                 /* (FUSES_FCCFG27) Register Mask  */
+
+
+/* -------- FUSES_FCCFG28 : (FUSES Offset: 0xF0) ( R/ 32) Calibration Configuration 28 Register -------- */
+#define FUSES_FCCFG28_CALCP_Pos               _UINT32_(0)                                          /* (FUSES_FCCFG28) Charge Pump Calibration  configuration bits for all charge pumps Position */
+#define FUSES_FCCFG28_CALCP_Msk               (_UINT32_(0xF) << FUSES_FCCFG28_CALCP_Pos)           /* (FUSES_FCCFG28) Charge Pump Calibration  configuration bits for all charge pumps Mask */
+#define FUSES_FCCFG28_CALCP(value)            (FUSES_FCCFG28_CALCP_Msk & (_UINT32_(value) << FUSES_FCCFG28_CALCP_Pos)) /* Assignment of value for CALCP in the FUSES_FCCFG28 register */
+#define FUSES_FCCFG28_CALSUPC_Pos             _UINT32_(8)                                          /* (FUSES_FCCFG28) RPMU / SUPC configuration bits Position */
+#define FUSES_FCCFG28_CALSUPC_Msk             (_UINT32_(0xFF) << FUSES_FCCFG28_CALSUPC_Pos)        /* (FUSES_FCCFG28) RPMU / SUPC configuration bits Mask */
+#define FUSES_FCCFG28_CALSUPC(value)          (FUSES_FCCFG28_CALSUPC_Msk & (_UINT32_(value) << FUSES_FCCFG28_CALSUPC_Pos)) /* Assignment of value for CALSUPC in the FUSES_FCCFG28 register */
+#define FUSES_FCCFG28_Msk                     _UINT32_(0x0000FF0F)                                 /* (FUSES_FCCFG28) Register Mask  */
+
+
+/* -------- FUSES_FCCFG29 : (FUSES Offset: 0xF4) ( R/ 32) Calibration Configuration 29 Register -------- */
+#define FUSES_FCCFG29_CALUSERLDO_Pos          _UINT32_(0)                                          /* (FUSES_FCCFG29) User LDO Calibration  configuration bits Position */
+#define FUSES_FCCFG29_CALUSERLDO_Msk          (_UINT32_(0xFF) << FUSES_FCCFG29_CALUSERLDO_Pos)     /* (FUSES_FCCFG29) User LDO Calibration  configuration bits Mask */
+#define FUSES_FCCFG29_CALUSERLDO(value)       (FUSES_FCCFG29_CALUSERLDO_Msk & (_UINT32_(value) << FUSES_FCCFG29_CALUSERLDO_Pos)) /* Assignment of value for CALUSERLDO in the FUSES_FCCFG29 register */
+#define FUSES_FCCFG29_Msk                     _UINT32_(0x000000FF)                                 /* (FUSES_FCCFG29) Register Mask  */
+
+
+/* -------- FUSES_FCCFG32 : (FUSES Offset: 0x100) ( R/ 32) DSU Device Configuration 0 Register (DEVID) -------- */
+#define FUSES_FCCFG32_PFM_SZ_Pos              _UINT32_(0)                                          /* (FUSES_FCCFG32) Program Flash Memory (PFM) Size on Device Position */
+#define FUSES_FCCFG32_PFM_SZ_Msk              (_UINT32_(0xF) << FUSES_FCCFG32_PFM_SZ_Pos)          /* (FUSES_FCCFG32) Program Flash Memory (PFM) Size on Device Mask */
+#define FUSES_FCCFG32_PFM_SZ(value)           (FUSES_FCCFG32_PFM_SZ_Msk & (_UINT32_(value) << FUSES_FCCFG32_PFM_SZ_Pos)) /* Assignment of value for PFM_SZ in the FUSES_FCCFG32 register */
+#define   FUSES_FCCFG32_PFM_SZ_6_Val          _UINT32_(0x6)                                        /* (FUSES_FCCFG32) 512KB  */
+#define FUSES_FCCFG32_PFM_SZ_6                (FUSES_FCCFG32_PFM_SZ_6_Val << FUSES_FCCFG32_PFM_SZ_Pos) /* (FUSES_FCCFG32) 512KB Position */
+#define FUSES_FCCFG32_DRM_SZ_Pos              _UINT32_(8)                                          /* (FUSES_FCCFG32) Data Ram Memory (DRM) Size on Device Position */
+#define FUSES_FCCFG32_DRM_SZ_Msk              (_UINT32_(0xFF) << FUSES_FCCFG32_DRM_SZ_Pos)         /* (FUSES_FCCFG32) Data Ram Memory (DRM) Size on Device Mask */
+#define FUSES_FCCFG32_DRM_SZ(value)           (FUSES_FCCFG32_DRM_SZ_Msk & (_UINT32_(value) << FUSES_FCCFG32_DRM_SZ_Pos)) /* Assignment of value for DRM_SZ in the FUSES_FCCFG32 register */
+#define   FUSES_FCCFG32_DRM_SZ_0_Val          _UINT32_(0x0)                                        /* (FUSES_FCCFG32) Rsvd  */
+#define   FUSES_FCCFG32_DRM_SZ_1_Val          _UINT32_(0x1)                                        /* (FUSES_FCCFG32) 128KB  */
+#define FUSES_FCCFG32_DRM_SZ_0                (FUSES_FCCFG32_DRM_SZ_0_Val << FUSES_FCCFG32_DRM_SZ_Pos) /* (FUSES_FCCFG32) Rsvd Position */
+#define FUSES_FCCFG32_DRM_SZ_1                (FUSES_FCCFG32_DRM_SZ_1_Val << FUSES_FCCFG32_DRM_SZ_Pos) /* (FUSES_FCCFG32) 128KB Position */
+#define FUSES_FCCFG32_FPACKAGE_Pos            _UINT32_(16)                                         /* (FUSES_FCCFG32) Number of Pins present on the Package Position */
+#define FUSES_FCCFG32_FPACKAGE_Msk            (_UINT32_(0xF) << FUSES_FCCFG32_FPACKAGE_Pos)        /* (FUSES_FCCFG32) Number of Pins present on the Package Mask */
+#define FUSES_FCCFG32_FPACKAGE(value)         (FUSES_FCCFG32_FPACKAGE_Msk & (_UINT32_(value) << FUSES_FCCFG32_FPACKAGE_Pos)) /* Assignment of value for FPACKAGE in the FUSES_FCCFG32 register */
+#define   FUSES_FCCFG32_FPACKAGE_5_Val        _UINT32_(0x5)                                        /* (FUSES_FCCFG32) 48 pins  */
+#define   FUSES_FCCFG32_FPACKAGE_6_Val        _UINT32_(0x6)                                        /* (FUSES_FCCFG32) 64 pins  */
+#define   FUSES_FCCFG32_FPACKAGE_7_Val        _UINT32_(0x7)                                        /* (FUSES_FCCFG32) Rsvd  */
+#define   FUSES_FCCFG32_FPACKAGE_8_Val        _UINT32_(0x8)                                        /* (FUSES_FCCFG32) 100 pins  */
+#define FUSES_FCCFG32_FPACKAGE_5              (FUSES_FCCFG32_FPACKAGE_5_Val << FUSES_FCCFG32_FPACKAGE_Pos) /* (FUSES_FCCFG32) 48 pins Position */
+#define FUSES_FCCFG32_FPACKAGE_6              (FUSES_FCCFG32_FPACKAGE_6_Val << FUSES_FCCFG32_FPACKAGE_Pos) /* (FUSES_FCCFG32) 64 pins Position */
+#define FUSES_FCCFG32_FPACKAGE_7              (FUSES_FCCFG32_FPACKAGE_7_Val << FUSES_FCCFG32_FPACKAGE_Pos) /* (FUSES_FCCFG32) Rsvd Position */
+#define FUSES_FCCFG32_FPACKAGE_8              (FUSES_FCCFG32_FPACKAGE_8_Val << FUSES_FCCFG32_FPACKAGE_Pos) /* (FUSES_FCCFG32) 100 pins Position */
+#define FUSES_FCCFG32_DEVSEL_Pos              _UINT32_(24)                                         /* (FUSES_FCCFG32) Device Variant Configuration Position */
+#define FUSES_FCCFG32_DEVSEL_Msk              (_UINT32_(0xFF) << FUSES_FCCFG32_DEVSEL_Pos)         /* (FUSES_FCCFG32) Device Variant Configuration Mask */
+#define FUSES_FCCFG32_DEVSEL(value)           (FUSES_FCCFG32_DEVSEL_Msk & (_UINT32_(value) << FUSES_FCCFG32_DEVSEL_Pos)) /* Assignment of value for DEVSEL in the FUSES_FCCFG32 register */
+#define FUSES_FCCFG32_Msk                     _UINT32_(0xFF0FFF0F)                                 /* (FUSES_FCCFG32) Register Mask  */
+
+
+/* -------- FUSES_FCCFG33 : (FUSES Offset: 0x104) ( R/ 32) DSU Device Configuration 1 Register -------- */
+#define FUSES_FCCFG33_ME_HSM_Pos              _UINT32_(7)                                          /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_HSM_Msk              (_UINT32_(0x1) << FUSES_FCCFG33_ME_HSM_Pos)          /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_HSM(value)           (FUSES_FCCFG33_ME_HSM_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_HSM_Pos)) /* Assignment of value for ME_HSM in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_HSM_0_Val          _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_HSM_1_Val          _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_HSM_0                (FUSES_FCCFG33_ME_HSM_0_Val << FUSES_FCCFG33_ME_HSM_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_HSM_1                (FUSES_FCCFG33_ME_HSM_1_Val << FUSES_FCCFG33_ME_HSM_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_TCC0_Pos             _UINT32_(8)                                          /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_TCC0_Msk             (_UINT32_(0x1) << FUSES_FCCFG33_ME_TCC0_Pos)         /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_TCC0(value)          (FUSES_FCCFG33_ME_TCC0_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_TCC0_Pos)) /* Assignment of value for ME_TCC0 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_TCC0_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_TCC0_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_TCC0_0               (FUSES_FCCFG33_ME_TCC0_0_Val << FUSES_FCCFG33_ME_TCC0_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_TCC0_1               (FUSES_FCCFG33_ME_TCC0_1_Val << FUSES_FCCFG33_ME_TCC0_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_TCC1_Pos             _UINT32_(9)                                          /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_TCC1_Msk             (_UINT32_(0x1) << FUSES_FCCFG33_ME_TCC1_Pos)         /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_TCC1(value)          (FUSES_FCCFG33_ME_TCC1_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_TCC1_Pos)) /* Assignment of value for ME_TCC1 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_TCC1_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_TCC1_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_TCC1_0               (FUSES_FCCFG33_ME_TCC1_0_Val << FUSES_FCCFG33_ME_TCC1_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_TCC1_1               (FUSES_FCCFG33_ME_TCC1_1_Val << FUSES_FCCFG33_ME_TCC1_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_TCC2_Pos             _UINT32_(10)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_TCC2_Msk             (_UINT32_(0x1) << FUSES_FCCFG33_ME_TCC2_Pos)         /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_TCC2(value)          (FUSES_FCCFG33_ME_TCC2_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_TCC2_Pos)) /* Assignment of value for ME_TCC2 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_TCC2_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_TCC2_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_TCC2_0               (FUSES_FCCFG33_ME_TCC2_0_Val << FUSES_FCCFG33_ME_TCC2_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_TCC2_1               (FUSES_FCCFG33_ME_TCC2_1_Val << FUSES_FCCFG33_ME_TCC2_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_TCC3_Pos             _UINT32_(11)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_TCC3_Msk             (_UINT32_(0x1) << FUSES_FCCFG33_ME_TCC3_Pos)         /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_TCC3(value)          (FUSES_FCCFG33_ME_TCC3_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_TCC3_Pos)) /* Assignment of value for ME_TCC3 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_TCC3_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_TCC3_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_TCC3_0               (FUSES_FCCFG33_ME_TCC3_0_Val << FUSES_FCCFG33_ME_TCC3_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_TCC3_1               (FUSES_FCCFG33_ME_TCC3_1_Val << FUSES_FCCFG33_ME_TCC3_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_TCC4_Pos             _UINT32_(12)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_TCC4_Msk             (_UINT32_(0x1) << FUSES_FCCFG33_ME_TCC4_Pos)         /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_TCC4(value)          (FUSES_FCCFG33_ME_TCC4_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_TCC4_Pos)) /* Assignment of value for ME_TCC4 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_TCC4_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_TCC4_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_TCC4_0               (FUSES_FCCFG33_ME_TCC4_0_Val << FUSES_FCCFG33_ME_TCC4_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_TCC4_1               (FUSES_FCCFG33_ME_TCC4_1_Val << FUSES_FCCFG33_ME_TCC4_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_TCC5_Pos             _UINT32_(13)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_TCC5_Msk             (_UINT32_(0x1) << FUSES_FCCFG33_ME_TCC5_Pos)         /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_TCC5(value)          (FUSES_FCCFG33_ME_TCC5_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_TCC5_Pos)) /* Assignment of value for ME_TCC5 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_TCC5_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_TCC5_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_TCC5_0               (FUSES_FCCFG33_ME_TCC5_0_Val << FUSES_FCCFG33_ME_TCC5_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_TCC5_1               (FUSES_FCCFG33_ME_TCC5_1_Val << FUSES_FCCFG33_ME_TCC5_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_TCC6_Pos             _UINT32_(14)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_TCC6_Msk             (_UINT32_(0x1) << FUSES_FCCFG33_ME_TCC6_Pos)         /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_TCC6(value)          (FUSES_FCCFG33_ME_TCC6_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_TCC6_Pos)) /* Assignment of value for ME_TCC6 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_TCC6_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_TCC6_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_TCC6_0               (FUSES_FCCFG33_ME_TCC6_0_Val << FUSES_FCCFG33_ME_TCC6_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_TCC6_1               (FUSES_FCCFG33_ME_TCC6_1_Val << FUSES_FCCFG33_ME_TCC6_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_SERCOM0_Pos          _UINT32_(18)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_SERCOM0_Msk          (_UINT32_(0x1) << FUSES_FCCFG33_ME_SERCOM0_Pos)      /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_SERCOM0(value)       (FUSES_FCCFG33_ME_SERCOM0_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_SERCOM0_Pos)) /* Assignment of value for ME_SERCOM0 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_SERCOM0_0_Val      _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_SERCOM0_1_Val      _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_SERCOM0_0            (FUSES_FCCFG33_ME_SERCOM0_0_Val << FUSES_FCCFG33_ME_SERCOM0_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_SERCOM0_1            (FUSES_FCCFG33_ME_SERCOM0_1_Val << FUSES_FCCFG33_ME_SERCOM0_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_SERCOM1_Pos          _UINT32_(19)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_SERCOM1_Msk          (_UINT32_(0x1) << FUSES_FCCFG33_ME_SERCOM1_Pos)      /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_SERCOM1(value)       (FUSES_FCCFG33_ME_SERCOM1_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_SERCOM1_Pos)) /* Assignment of value for ME_SERCOM1 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_SERCOM1_0_Val      _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_SERCOM1_1_Val      _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_SERCOM1_0            (FUSES_FCCFG33_ME_SERCOM1_0_Val << FUSES_FCCFG33_ME_SERCOM1_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_SERCOM1_1            (FUSES_FCCFG33_ME_SERCOM1_1_Val << FUSES_FCCFG33_ME_SERCOM1_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_SERCOM2_Pos          _UINT32_(20)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_SERCOM2_Msk          (_UINT32_(0x1) << FUSES_FCCFG33_ME_SERCOM2_Pos)      /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_SERCOM2(value)       (FUSES_FCCFG33_ME_SERCOM2_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_SERCOM2_Pos)) /* Assignment of value for ME_SERCOM2 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_SERCOM2_0_Val      _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_SERCOM2_1_Val      _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_SERCOM2_0            (FUSES_FCCFG33_ME_SERCOM2_0_Val << FUSES_FCCFG33_ME_SERCOM2_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_SERCOM2_1            (FUSES_FCCFG33_ME_SERCOM2_1_Val << FUSES_FCCFG33_ME_SERCOM2_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_SERCOM3_Pos          _UINT32_(21)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_SERCOM3_Msk          (_UINT32_(0x1) << FUSES_FCCFG33_ME_SERCOM3_Pos)      /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_SERCOM3(value)       (FUSES_FCCFG33_ME_SERCOM3_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_SERCOM3_Pos)) /* Assignment of value for ME_SERCOM3 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_SERCOM3_0_Val      _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_SERCOM3_1_Val      _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_SERCOM3_0            (FUSES_FCCFG33_ME_SERCOM3_0_Val << FUSES_FCCFG33_ME_SERCOM3_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_SERCOM3_1            (FUSES_FCCFG33_ME_SERCOM3_1_Val << FUSES_FCCFG33_ME_SERCOM3_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_SERCOM4_Pos          _UINT32_(22)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_SERCOM4_Msk          (_UINT32_(0x1) << FUSES_FCCFG33_ME_SERCOM4_Pos)      /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_SERCOM4(value)       (FUSES_FCCFG33_ME_SERCOM4_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_SERCOM4_Pos)) /* Assignment of value for ME_SERCOM4 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_SERCOM4_0_Val      _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_SERCOM4_1_Val      _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_SERCOM4_0            (FUSES_FCCFG33_ME_SERCOM4_0_Val << FUSES_FCCFG33_ME_SERCOM4_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_SERCOM4_1            (FUSES_FCCFG33_ME_SERCOM4_1_Val << FUSES_FCCFG33_ME_SERCOM4_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_SERCOM5_Pos          _UINT32_(23)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_SERCOM5_Msk          (_UINT32_(0x1) << FUSES_FCCFG33_ME_SERCOM5_Pos)      /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_SERCOM5(value)       (FUSES_FCCFG33_ME_SERCOM5_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_SERCOM5_Pos)) /* Assignment of value for ME_SERCOM5 in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_SERCOM5_0_Val      _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_SERCOM5_1_Val      _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_SERCOM5_0            (FUSES_FCCFG33_ME_SERCOM5_0_Val << FUSES_FCCFG33_ME_SERCOM5_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_SERCOM5_1            (FUSES_FCCFG33_ME_SERCOM5_1_Val << FUSES_FCCFG33_ME_SERCOM5_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_ME_PTC_Pos              _UINT32_(28)                                         /* (FUSES_FCCFG33) Module enables for Variant configuration Position */
+#define FUSES_FCCFG33_ME_PTC_Msk              (_UINT32_(0x1) << FUSES_FCCFG33_ME_PTC_Pos)          /* (FUSES_FCCFG33) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG33_ME_PTC(value)           (FUSES_FCCFG33_ME_PTC_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_PTC_Pos)) /* Assignment of value for ME_PTC in the FUSES_FCCFG33 register */
+#define   FUSES_FCCFG33_ME_PTC_0_Val          _UINT32_(0x0)                                        /* (FUSES_FCCFG33) Module is Disabled  */
+#define   FUSES_FCCFG33_ME_PTC_1_Val          _UINT32_(0x1)                                        /* (FUSES_FCCFG33) Module is Enabled  */
+#define FUSES_FCCFG33_ME_PTC_0                (FUSES_FCCFG33_ME_PTC_0_Val << FUSES_FCCFG33_ME_PTC_Pos) /* (FUSES_FCCFG33) Module is Disabled Position */
+#define FUSES_FCCFG33_ME_PTC_1                (FUSES_FCCFG33_ME_PTC_1_Val << FUSES_FCCFG33_ME_PTC_Pos) /* (FUSES_FCCFG33) Module is Enabled Position */
+#define FUSES_FCCFG33_Msk                     _UINT32_(0x10FC7F80)                                 /* (FUSES_FCCFG33) Register Mask  */
+
+#define FUSES_FCCFG33_ME_TCC_Pos              _UINT32_(8)                                          /* (FUSES_FCCFG33 Position) Module enables for Variant configuration */
+#define FUSES_FCCFG33_ME_TCC_Msk              (_UINT32_(0x7F) << FUSES_FCCFG33_ME_TCC_Pos)         /* (FUSES_FCCFG33 Mask) ME_TCC */
+#define FUSES_FCCFG33_ME_TCC(value)           (FUSES_FCCFG33_ME_TCC_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_TCC_Pos)) 
+#define FUSES_FCCFG33_ME_SERCOM_Pos           _UINT32_(18)                                         /* (FUSES_FCCFG33 Position) Module enables for Variant configuration */
+#define FUSES_FCCFG33_ME_SERCOM_Msk           (_UINT32_(0x3F) << FUSES_FCCFG33_ME_SERCOM_Pos)      /* (FUSES_FCCFG33 Mask) ME_SERCOM */
+#define FUSES_FCCFG33_ME_SERCOM(value)        (FUSES_FCCFG33_ME_SERCOM_Msk & (_UINT32_(value) << FUSES_FCCFG33_ME_SERCOM_Pos)) 
+
+/* -------- FUSES_FCCFG34 : (FUSES Offset: 0x108) ( R/ 32) DSU Device Configuration 2 Register -------- */
+#define FUSES_FCCFG34_ME_CAN0_Pos             _UINT32_(0)                                          /* (FUSES_FCCFG34) Module enables for Variant configuration Position */
+#define FUSES_FCCFG34_ME_CAN0_Msk             (_UINT32_(0x1) << FUSES_FCCFG34_ME_CAN0_Pos)         /* (FUSES_FCCFG34) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG34_ME_CAN0(value)          (FUSES_FCCFG34_ME_CAN0_Msk & (_UINT32_(value) << FUSES_FCCFG34_ME_CAN0_Pos)) /* Assignment of value for ME_CAN0 in the FUSES_FCCFG34 register */
+#define   FUSES_FCCFG34_ME_CAN0_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG34) Module is Disabled  */
+#define   FUSES_FCCFG34_ME_CAN0_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG34) Module is Enabled  */
+#define FUSES_FCCFG34_ME_CAN0_0               (FUSES_FCCFG34_ME_CAN0_0_Val << FUSES_FCCFG34_ME_CAN0_Pos) /* (FUSES_FCCFG34) Module is Disabled Position */
+#define FUSES_FCCFG34_ME_CAN0_1               (FUSES_FCCFG34_ME_CAN0_1_Val << FUSES_FCCFG34_ME_CAN0_Pos) /* (FUSES_FCCFG34) Module is Enabled Position */
+#define FUSES_FCCFG34_ME_CAN1_Pos             _UINT32_(1)                                          /* (FUSES_FCCFG34) Module enables for Variant configuration Position */
+#define FUSES_FCCFG34_ME_CAN1_Msk             (_UINT32_(0x1) << FUSES_FCCFG34_ME_CAN1_Pos)         /* (FUSES_FCCFG34) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG34_ME_CAN1(value)          (FUSES_FCCFG34_ME_CAN1_Msk & (_UINT32_(value) << FUSES_FCCFG34_ME_CAN1_Pos)) /* Assignment of value for ME_CAN1 in the FUSES_FCCFG34 register */
+#define   FUSES_FCCFG34_ME_CAN1_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG34) Module is Disabled  */
+#define   FUSES_FCCFG34_ME_CAN1_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG34) Module is Enabled  */
+#define FUSES_FCCFG34_ME_CAN1_0               (FUSES_FCCFG34_ME_CAN1_0_Val << FUSES_FCCFG34_ME_CAN1_Pos) /* (FUSES_FCCFG34) Module is Disabled Position */
+#define FUSES_FCCFG34_ME_CAN1_1               (FUSES_FCCFG34_ME_CAN1_1_Val << FUSES_FCCFG34_ME_CAN1_Pos) /* (FUSES_FCCFG34) Module is Enabled Position */
+#define FUSES_FCCFG34_ME_USBFS_Pos            _UINT32_(9)                                          /* (FUSES_FCCFG34) Module enables for Variant configuration Position */
+#define FUSES_FCCFG34_ME_USBFS_Msk            (_UINT32_(0x1) << FUSES_FCCFG34_ME_USBFS_Pos)        /* (FUSES_FCCFG34) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG34_ME_USBFS(value)         (FUSES_FCCFG34_ME_USBFS_Msk & (_UINT32_(value) << FUSES_FCCFG34_ME_USBFS_Pos)) /* Assignment of value for ME_USBFS in the FUSES_FCCFG34 register */
+#define   FUSES_FCCFG34_ME_USBFS_0_Val        _UINT32_(0x0)                                        /* (FUSES_FCCFG34) Module is Disabled  */
+#define   FUSES_FCCFG34_ME_USBFS_1_Val        _UINT32_(0x1)                                        /* (FUSES_FCCFG34) Module is Enabled  */
+#define FUSES_FCCFG34_ME_USBFS_0              (FUSES_FCCFG34_ME_USBFS_0_Val << FUSES_FCCFG34_ME_USBFS_Pos) /* (FUSES_FCCFG34) Module is Disabled Position */
+#define FUSES_FCCFG34_ME_USBFS_1              (FUSES_FCCFG34_ME_USBFS_1_Val << FUSES_FCCFG34_ME_USBFS_Pos) /* (FUSES_FCCFG34) Module is Enabled Position */
+#define FUSES_FCCFG34_ME_DPA_Pos              _UINT32_(23)                                         /* (FUSES_FCCFG34) Module enables for Variant configuration Position */
+#define FUSES_FCCFG34_ME_DPA_Msk              (_UINT32_(0x1) << FUSES_FCCFG34_ME_DPA_Pos)          /* (FUSES_FCCFG34) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG34_ME_DPA(value)           (FUSES_FCCFG34_ME_DPA_Msk & (_UINT32_(value) << FUSES_FCCFG34_ME_DPA_Pos)) /* Assignment of value for ME_DPA in the FUSES_FCCFG34 register */
+#define   FUSES_FCCFG34_ME_DPA_0_Val          _UINT32_(0x0)                                        /* (FUSES_FCCFG34) DPA is Disabled  */
+#define   FUSES_FCCFG34_ME_DPA_1_Val          _UINT32_(0x1)                                        /* (FUSES_FCCFG34) DPA functions in HSM is Operational  */
+#define FUSES_FCCFG34_ME_DPA_0                (FUSES_FCCFG34_ME_DPA_0_Val << FUSES_FCCFG34_ME_DPA_Pos) /* (FUSES_FCCFG34) DPA is Disabled Position */
+#define FUSES_FCCFG34_ME_DPA_1                (FUSES_FCCFG34_ME_DPA_1_Val << FUSES_FCCFG34_ME_DPA_Pos) /* (FUSES_FCCFG34) DPA functions in HSM is Operational Position */
+#define FUSES_FCCFG34_ME_TRAM_Pos             _UINT32_(30)                                         /* (FUSES_FCCFG34) Module enables for Variant configuration Position */
+#define FUSES_FCCFG34_ME_TRAM_Msk             (_UINT32_(0x1) << FUSES_FCCFG34_ME_TRAM_Pos)         /* (FUSES_FCCFG34) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG34_ME_TRAM(value)          (FUSES_FCCFG34_ME_TRAM_Msk & (_UINT32_(value) << FUSES_FCCFG34_ME_TRAM_Pos)) /* Assignment of value for ME_TRAM in the FUSES_FCCFG34 register */
+#define   FUSES_FCCFG34_ME_TRAM_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG34) Module is Disabled  */
+#define   FUSES_FCCFG34_ME_TRAM_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG34) Module is Enabled  */
+#define FUSES_FCCFG34_ME_TRAM_0               (FUSES_FCCFG34_ME_TRAM_0_Val << FUSES_FCCFG34_ME_TRAM_Pos) /* (FUSES_FCCFG34) Module is Disabled Position */
+#define FUSES_FCCFG34_ME_TRAM_1               (FUSES_FCCFG34_ME_TRAM_1_Val << FUSES_FCCFG34_ME_TRAM_Pos) /* (FUSES_FCCFG34) Module is Enabled Position */
+#define FUSES_FCCFG34_ME_PUF_Pos              _UINT32_(31)                                         /* (FUSES_FCCFG34) Module enables for Variant configuration Position */
+#define FUSES_FCCFG34_ME_PUF_Msk              (_UINT32_(0x1) << FUSES_FCCFG34_ME_PUF_Pos)          /* (FUSES_FCCFG34) Module enables for Variant configuration Mask */
+#define FUSES_FCCFG34_ME_PUF(value)           (FUSES_FCCFG34_ME_PUF_Msk & (_UINT32_(value) << FUSES_FCCFG34_ME_PUF_Pos)) /* Assignment of value for ME_PUF in the FUSES_FCCFG34 register */
+#define   FUSES_FCCFG34_ME_PUF_0_Val          _UINT32_(0x0)                                        /* (FUSES_FCCFG34) Module is Disabled  */
+#define   FUSES_FCCFG34_ME_PUF_1_Val          _UINT32_(0x1)                                        /* (FUSES_FCCFG34) Module is Enabled  */
+#define FUSES_FCCFG34_ME_PUF_0                (FUSES_FCCFG34_ME_PUF_0_Val << FUSES_FCCFG34_ME_PUF_Pos) /* (FUSES_FCCFG34) Module is Disabled Position */
+#define FUSES_FCCFG34_ME_PUF_1                (FUSES_FCCFG34_ME_PUF_1_Val << FUSES_FCCFG34_ME_PUF_Pos) /* (FUSES_FCCFG34) Module is Enabled Position */
+#define FUSES_FCCFG34_Msk                     _UINT32_(0xC0800203)                                 /* (FUSES_FCCFG34) Register Mask  */
+
+#define FUSES_FCCFG34_ME_CAN_Pos              _UINT32_(0)                                          /* (FUSES_FCCFG34 Position) Module enables for Variant configuration */
+#define FUSES_FCCFG34_ME_CAN_Msk              (_UINT32_(0x3) << FUSES_FCCFG34_ME_CAN_Pos)          /* (FUSES_FCCFG34 Mask) ME_CAN */
+#define FUSES_FCCFG34_ME_CAN(value)           (FUSES_FCCFG34_ME_CAN_Msk & (_UINT32_(value) << FUSES_FCCFG34_ME_CAN_Pos)) 
+
+/* -------- FUSES_FCCFG49 : (FUSES Offset: 0x144) ( R/ 32) Calibration Configuration 49 Register -------- */
+#define FUSES_FCCFG49_RAMC_EMAW_Pos           _UINT32_(0)                                          /* (FUSES_FCCFG49) Write Time Extra Margin Adjust Position */
+#define FUSES_FCCFG49_RAMC_EMAW_Msk           (_UINT32_(0x3) << FUSES_FCCFG49_RAMC_EMAW_Pos)       /* (FUSES_FCCFG49) Write Time Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_RAMC_EMAW(value)        (FUSES_FCCFG49_RAMC_EMAW_Msk & (_UINT32_(value) << FUSES_FCCFG49_RAMC_EMAW_Pos)) /* Assignment of value for RAMC_EMAW in the FUSES_FCCFG49 register */
+#define   FUSES_FCCFG49_RAMC_EMAW_0_Val       _UINT32_(0x0)                                        /* (FUSES_FCCFG49) Slowest Access  */
+#define   FUSES_FCCFG49_RAMC_EMAW_1_Val       _UINT32_(0x1)                                        /* (FUSES_FCCFG49)   */
+#define   FUSES_FCCFG49_RAMC_EMAW_2_Val       _UINT32_(0x2)                                        /* (FUSES_FCCFG49)   */
+#define   FUSES_FCCFG49_RAMC_EMAW_3_Val       _UINT32_(0x3)                                        /* (FUSES_FCCFG49) Fastest Access; Default (reset)  */
+#define FUSES_FCCFG49_RAMC_EMAW_0             (FUSES_FCCFG49_RAMC_EMAW_0_Val << FUSES_FCCFG49_RAMC_EMAW_Pos) /* (FUSES_FCCFG49) Slowest Access Position */
+#define FUSES_FCCFG49_RAMC_EMAW_1             (FUSES_FCCFG49_RAMC_EMAW_1_Val << FUSES_FCCFG49_RAMC_EMAW_Pos) /* (FUSES_FCCFG49)  Position */
+#define FUSES_FCCFG49_RAMC_EMAW_2             (FUSES_FCCFG49_RAMC_EMAW_2_Val << FUSES_FCCFG49_RAMC_EMAW_Pos) /* (FUSES_FCCFG49)  Position */
+#define FUSES_FCCFG49_RAMC_EMAW_3             (FUSES_FCCFG49_RAMC_EMAW_3_Val << FUSES_FCCFG49_RAMC_EMAW_Pos) /* (FUSES_FCCFG49) Fastest Access; Default (reset) Position */
+#define FUSES_FCCFG49_RAMC_EMA_Pos            _UINT32_(2)                                          /* (FUSES_FCCFG49) Cycle and Read Time Extra Margin Adjust Position */
+#define FUSES_FCCFG49_RAMC_EMA_Msk            (_UINT32_(0x7) << FUSES_FCCFG49_RAMC_EMA_Pos)        /* (FUSES_FCCFG49) Cycle and Read Time Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_RAMC_EMA(value)         (FUSES_FCCFG49_RAMC_EMA_Msk & (_UINT32_(value) << FUSES_FCCFG49_RAMC_EMA_Pos)) /* Assignment of value for RAMC_EMA in the FUSES_FCCFG49 register */
+#define   FUSES_FCCFG49_RAMC_EMA_0_Val        _UINT32_(0x0)                                        /* (FUSES_FCCFG49)   */
+#define   FUSES_FCCFG49_RAMC_EMA_1_Val        _UINT32_(0x1)                                        /* (FUSES_FCCFG49)   */
+#define   FUSES_FCCFG49_RAMC_EMA_2_Val        _UINT32_(0x2)                                        /* (FUSES_FCCFG49) Slowest Access  */
+#define   FUSES_FCCFG49_RAMC_EMA_3_Val        _UINT32_(0x3)                                        /* (FUSES_FCCFG49)   */
+#define   FUSES_FCCFG49_RAMC_EMA_4_Val        _UINT32_(0x4)                                        /* (FUSES_FCCFG49)   */
+#define   FUSES_FCCFG49_RAMC_EMA_5_Val        _UINT32_(0x5)                                        /* (FUSES_FCCFG49) Fastest Access  */
+#define   FUSES_FCCFG49_RAMC_EMA_6_Val        _UINT32_(0x6)                                        /* (FUSES_FCCFG49)   */
+#define   FUSES_FCCFG49_RAMC_EMA_7_Val        _UINT32_(0x7)                                        /* (FUSES_FCCFG49) Default (reset)  */
+#define FUSES_FCCFG49_RAMC_EMA_0              (FUSES_FCCFG49_RAMC_EMA_0_Val << FUSES_FCCFG49_RAMC_EMA_Pos) /* (FUSES_FCCFG49)  Position */
+#define FUSES_FCCFG49_RAMC_EMA_1              (FUSES_FCCFG49_RAMC_EMA_1_Val << FUSES_FCCFG49_RAMC_EMA_Pos) /* (FUSES_FCCFG49)  Position */
+#define FUSES_FCCFG49_RAMC_EMA_2              (FUSES_FCCFG49_RAMC_EMA_2_Val << FUSES_FCCFG49_RAMC_EMA_Pos) /* (FUSES_FCCFG49) Slowest Access Position */
+#define FUSES_FCCFG49_RAMC_EMA_3              (FUSES_FCCFG49_RAMC_EMA_3_Val << FUSES_FCCFG49_RAMC_EMA_Pos) /* (FUSES_FCCFG49)  Position */
+#define FUSES_FCCFG49_RAMC_EMA_4              (FUSES_FCCFG49_RAMC_EMA_4_Val << FUSES_FCCFG49_RAMC_EMA_Pos) /* (FUSES_FCCFG49)  Position */
+#define FUSES_FCCFG49_RAMC_EMA_5              (FUSES_FCCFG49_RAMC_EMA_5_Val << FUSES_FCCFG49_RAMC_EMA_Pos) /* (FUSES_FCCFG49) Fastest Access Position */
+#define FUSES_FCCFG49_RAMC_EMA_6              (FUSES_FCCFG49_RAMC_EMA_6_Val << FUSES_FCCFG49_RAMC_EMA_Pos) /* (FUSES_FCCFG49)  Position */
+#define FUSES_FCCFG49_RAMC_EMA_7              (FUSES_FCCFG49_RAMC_EMA_7_Val << FUSES_FCCFG49_RAMC_EMA_Pos) /* (FUSES_FCCFG49) Default (reset) Position */
+#define FUSES_FCCFG49_RAMAB_EMAW_Pos          _UINT32_(6)                                          /* (FUSES_FCCFG49) Write Time Extra Margin Adjust Position */
+#define FUSES_FCCFG49_RAMAB_EMAW_Msk          (_UINT32_(0x3) << FUSES_FCCFG49_RAMAB_EMAW_Pos)      /* (FUSES_FCCFG49) Write Time Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_RAMAB_EMAW(value)       (FUSES_FCCFG49_RAMAB_EMAW_Msk & (_UINT32_(value) << FUSES_FCCFG49_RAMAB_EMAW_Pos)) /* Assignment of value for RAMAB_EMAW in the FUSES_FCCFG49 register */
+#define FUSES_FCCFG49_RAMAB_EMA_Pos           _UINT32_(8)                                          /* (FUSES_FCCFG49) Cycle and Read Time Extra Margin Adjust Position */
+#define FUSES_FCCFG49_RAMAB_EMA_Msk           (_UINT32_(0x7) << FUSES_FCCFG49_RAMAB_EMA_Pos)       /* (FUSES_FCCFG49) Cycle and Read Time Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_RAMAB_EMA(value)        (FUSES_FCCFG49_RAMAB_EMA_Msk & (_UINT32_(value) << FUSES_FCCFG49_RAMAB_EMA_Pos)) /* Assignment of value for RAMAB_EMA in the FUSES_FCCFG49 register */
+#define FUSES_FCCFG49_TRAM_EMAW_Pos           _UINT32_(12)                                         /* (FUSES_FCCFG49) Write Time Extra Margin Adjust Position */
+#define FUSES_FCCFG49_TRAM_EMAW_Msk           (_UINT32_(0x3) << FUSES_FCCFG49_TRAM_EMAW_Pos)       /* (FUSES_FCCFG49) Write Time Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_TRAM_EMAW(value)        (FUSES_FCCFG49_TRAM_EMAW_Msk & (_UINT32_(value) << FUSES_FCCFG49_TRAM_EMAW_Pos)) /* Assignment of value for TRAM_EMAW in the FUSES_FCCFG49 register */
+#define FUSES_FCCFG49_TRAM_EMA_Pos            _UINT32_(14)                                         /* (FUSES_FCCFG49) Cycle and Read Time Extra Margin Adjust Position */
+#define FUSES_FCCFG49_TRAM_EMA_Msk            (_UINT32_(0x7) << FUSES_FCCFG49_TRAM_EMA_Pos)        /* (FUSES_FCCFG49) Cycle and Read Time Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_TRAM_EMA(value)         (FUSES_FCCFG49_TRAM_EMA_Msk & (_UINT32_(value) << FUSES_FCCFG49_TRAM_EMA_Pos)) /* Assignment of value for TRAM_EMA in the FUSES_FCCFG49 register */
+#define FUSES_FCCFG49_TRAM_EMAS_Pos           _UINT32_(17)                                         /* (FUSES_FCCFG49) Sense Amp Extra Margin Adjust Position */
+#define FUSES_FCCFG49_TRAM_EMAS_Msk           (_UINT32_(0x1) << FUSES_FCCFG49_TRAM_EMAS_Pos)       /* (FUSES_FCCFG49) Sense Amp Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_TRAM_EMAS(value)        (FUSES_FCCFG49_TRAM_EMAS_Msk & (_UINT32_(value) << FUSES_FCCFG49_TRAM_EMAS_Pos)) /* Assignment of value for TRAM_EMAS in the FUSES_FCCFG49 register */
+#define   FUSES_FCCFG49_TRAM_EMAS_0_Val       _UINT32_(0x0)                                        /* (FUSES_FCCFG49) Sense Amp Pulse Not Extended  */
+#define   FUSES_FCCFG49_TRAM_EMAS_1_Val       _UINT32_(0x1)                                        /* (FUSES_FCCFG49) Sense Amp Pulse Extended; Default (reset)  */
+#define FUSES_FCCFG49_TRAM_EMAS_0             (FUSES_FCCFG49_TRAM_EMAS_0_Val << FUSES_FCCFG49_TRAM_EMAS_Pos) /* (FUSES_FCCFG49) Sense Amp Pulse Not Extended Position */
+#define FUSES_FCCFG49_TRAM_EMAS_1             (FUSES_FCCFG49_TRAM_EMAS_1_Val << FUSES_FCCFG49_TRAM_EMAS_Pos) /* (FUSES_FCCFG49) Sense Amp Pulse Extended; Default (reset) Position */
+#define FUSES_FCCFG49_BROM_EMA_Pos            _UINT32_(20)                                         /* (FUSES_FCCFG49) Cycle and Read Time Extra Margin Adjust Position */
+#define FUSES_FCCFG49_BROM_EMA_Msk            (_UINT32_(0x7) << FUSES_FCCFG49_BROM_EMA_Pos)        /* (FUSES_FCCFG49) Cycle and Read Time Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_BROM_EMA(value)         (FUSES_FCCFG49_BROM_EMA_Msk & (_UINT32_(value) << FUSES_FCCFG49_BROM_EMA_Pos)) /* Assignment of value for BROM_EMA in the FUSES_FCCFG49 register */
+#define FUSES_FCCFG49_PUF_EMAW_Pos            _UINT32_(24)                                         /* (FUSES_FCCFG49) Write Time Extra Margin Adjust Position */
+#define FUSES_FCCFG49_PUF_EMAW_Msk            (_UINT32_(0x3) << FUSES_FCCFG49_PUF_EMAW_Pos)        /* (FUSES_FCCFG49) Write Time Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_PUF_EMAW(value)         (FUSES_FCCFG49_PUF_EMAW_Msk & (_UINT32_(value) << FUSES_FCCFG49_PUF_EMAW_Pos)) /* Assignment of value for PUF_EMAW in the FUSES_FCCFG49 register */
+#define FUSES_FCCFG49_PUF_EMA_Pos             _UINT32_(26)                                         /* (FUSES_FCCFG49) Cycle and Read Time Extra Margin Adjust Position */
+#define FUSES_FCCFG49_PUF_EMA_Msk             (_UINT32_(0x7) << FUSES_FCCFG49_PUF_EMA_Pos)         /* (FUSES_FCCFG49) Cycle and Read Time Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_PUF_EMA(value)          (FUSES_FCCFG49_PUF_EMA_Msk & (_UINT32_(value) << FUSES_FCCFG49_PUF_EMA_Pos)) /* Assignment of value for PUF_EMA in the FUSES_FCCFG49 register */
+#define FUSES_FCCFG49_PUF_EMAS_Pos            _UINT32_(29)                                         /* (FUSES_FCCFG49) Sense Amp Extra Margin Adjust Position */
+#define FUSES_FCCFG49_PUF_EMAS_Msk            (_UINT32_(0x1) << FUSES_FCCFG49_PUF_EMAS_Pos)        /* (FUSES_FCCFG49) Sense Amp Extra Margin Adjust Mask */
+#define FUSES_FCCFG49_PUF_EMAS(value)         (FUSES_FCCFG49_PUF_EMAS_Msk & (_UINT32_(value) << FUSES_FCCFG49_PUF_EMAS_Pos)) /* Assignment of value for PUF_EMAS in the FUSES_FCCFG49 register */
+#define   FUSES_FCCFG49_PUF_EMAS_0_Val        _UINT32_(0x0)                                        /* (FUSES_FCCFG49) Sense Amp Pulse Not Extended  */
+#define   FUSES_FCCFG49_PUF_EMAS_1_Val        _UINT32_(0x1)                                        /* (FUSES_FCCFG49) Sense Amp Pulse Extended; Default (reset)  */
+#define FUSES_FCCFG49_PUF_EMAS_0              (FUSES_FCCFG49_PUF_EMAS_0_Val << FUSES_FCCFG49_PUF_EMAS_Pos) /* (FUSES_FCCFG49) Sense Amp Pulse Not Extended Position */
+#define FUSES_FCCFG49_PUF_EMAS_1              (FUSES_FCCFG49_PUF_EMAS_1_Val << FUSES_FCCFG49_PUF_EMAS_Pos) /* (FUSES_FCCFG49) Sense Amp Pulse Extended; Default (reset) Position */
+#define FUSES_FCCFG49_Msk                     _UINT32_(0x3F73F7DF)                                 /* (FUSES_FCCFG49) Register Mask  */
+
+
+/* -------- FUSES_FCCFG56 : (FUSES Offset: 0x160) ( R/ 32) Calibration Configuration 56 Register -------- */
+#define FUSES_FCCFG56_BRINGOSC_Pos            _UINT32_(0)                                          /* (FUSES_FCCFG56) SUPC Ring-osc depth Position */
+#define FUSES_FCCFG56_BRINGOSC_Msk            (_UINT32_(0x3) << FUSES_FCCFG56_BRINGOSC_Pos)        /* (FUSES_FCCFG56) SUPC Ring-osc depth Mask */
+#define FUSES_FCCFG56_BRINGOSC(value)         (FUSES_FCCFG56_BRINGOSC_Msk & (_UINT32_(value) << FUSES_FCCFG56_BRINGOSC_Pos)) /* Assignment of value for BRINGOSC in the FUSES_FCCFG56 register */
+#define   FUSES_FCCFG56_BRINGOSC_0_Val        _UINT32_(0x0)                                        /* (FUSES_FCCFG56) Ring oscillator depth is default (DLY0)  */
+#define   FUSES_FCCFG56_BRINGOSC_1_Val        _UINT32_(0x1)                                        /* (FUSES_FCCFG56) Ring oscillator depth is default + 1 ORDLY15 (DLY1)  */
+#define   FUSES_FCCFG56_BRINGOSC_2_Val        _UINT32_(0x2)                                        /* (FUSES_FCCFG56) Ring oscillator depth is default + 2 ORDLY15 (DLY2)  */
+#define   FUSES_FCCFG56_BRINGOSC_3_Val        _UINT32_(0x3)                                        /* (FUSES_FCCFG56) Ring oscillator depth is default + 3 ORDLY15 (DLY3)  */
+#define FUSES_FCCFG56_BRINGOSC_0              (FUSES_FCCFG56_BRINGOSC_0_Val << FUSES_FCCFG56_BRINGOSC_Pos) /* (FUSES_FCCFG56) Ring oscillator depth is default (DLY0) Position */
+#define FUSES_FCCFG56_BRINGOSC_1              (FUSES_FCCFG56_BRINGOSC_1_Val << FUSES_FCCFG56_BRINGOSC_Pos) /* (FUSES_FCCFG56) Ring oscillator depth is default + 1 ORDLY15 (DLY1) Position */
+#define FUSES_FCCFG56_BRINGOSC_2              (FUSES_FCCFG56_BRINGOSC_2_Val << FUSES_FCCFG56_BRINGOSC_Pos) /* (FUSES_FCCFG56) Ring oscillator depth is default + 2 ORDLY15 (DLY2) Position */
+#define FUSES_FCCFG56_BRINGOSC_3              (FUSES_FCCFG56_BRINGOSC_3_Val << FUSES_FCCFG56_BRINGOSC_Pos) /* (FUSES_FCCFG56) Ring oscillator depth is default + 3 ORDLY15 (DLY3) Position */
+#define FUSES_FCCFG56_DIS_BOR12_RAMON_Pos     _UINT32_(4)                                          /* (FUSES_FCCFG56) Disable BOR12 (VREGRAM comparator) when RAM are turned ON when leaving sleep mode Position */
+#define FUSES_FCCFG56_DIS_BOR12_RAMON_Msk     (_UINT32_(0x1) << FUSES_FCCFG56_DIS_BOR12_RAMON_Pos) /* (FUSES_FCCFG56) Disable BOR12 (VREGRAM comparator) when RAM are turned ON when leaving sleep mode Mask */
+#define FUSES_FCCFG56_DIS_BOR12_RAMON(value)  (FUSES_FCCFG56_DIS_BOR12_RAMON_Msk & (_UINT32_(value) << FUSES_FCCFG56_DIS_BOR12_RAMON_Pos)) /* Assignment of value for DIS_BOR12_RAMON in the FUSES_FCCFG56 register */
+#define FUSES_FCCFG56_DIS_BOR12_VSCALING_Pos  _UINT32_(5)                                          /* (FUSES_FCCFG56) Disable BOR12 (VREGRAM comparator) when down voltage scaling is on going from 1.2v to 0.8v to workaround VREG undershoot issue Position */
+#define FUSES_FCCFG56_DIS_BOR12_VSCALING_Msk  (_UINT32_(0x1) << FUSES_FCCFG56_DIS_BOR12_VSCALING_Pos) /* (FUSES_FCCFG56) Disable BOR12 (VREGRAM comparator) when down voltage scaling is on going from 1.2v to 0.8v to workaround VREG undershoot issue Mask */
+#define FUSES_FCCFG56_DIS_BOR12_VSCALING(value) (FUSES_FCCFG56_DIS_BOR12_VSCALING_Msk & (_UINT32_(value) << FUSES_FCCFG56_DIS_BOR12_VSCALING_Pos)) /* Assignment of value for DIS_BOR12_VSCALING in the FUSES_FCCFG56 register */
+#define FUSES_FCCFG56_VLP2FPST_Pos            _UINT32_(16)                                         /* (FUSES_FCCFG56) Vreg Low Power to Full Power Stabilization Time Position */
+#define FUSES_FCCFG56_VLP2FPST_Msk            (_UINT32_(0x3) << FUSES_FCCFG56_VLP2FPST_Pos)        /* (FUSES_FCCFG56) Vreg Low Power to Full Power Stabilization Time Mask */
+#define FUSES_FCCFG56_VLP2FPST(value)         (FUSES_FCCFG56_VLP2FPST_Msk & (_UINT32_(value) << FUSES_FCCFG56_VLP2FPST_Pos)) /* Assignment of value for VLP2FPST in the FUSES_FCCFG56 register */
+#define   FUSES_FCCFG56_VLP2FPST_0_Val        _UINT32_(0x0)                                        /* (FUSES_FCCFG56) 5us -32 clock cycles based on 6Mhz clock (5US)  */
+#define   FUSES_FCCFG56_VLP2FPST_1_Val        _UINT32_(0x1)                                        /* (FUSES_FCCFG56) 10us -64 clock cycles based on 6Mhz clock (10US)  */
+#define   FUSES_FCCFG56_VLP2FPST_2_Val        _UINT32_(0x2)                                        /* (FUSES_FCCFG56) 21us -128 clock cycles based on 6Mhz clock (21US)  */
+#define   FUSES_FCCFG56_VLP2FPST_3_Val        _UINT32_(0x3)                                        /* (FUSES_FCCFG56) 1.3us -8 clock cycles based on 6Mhz clock (1US)  */
+#define FUSES_FCCFG56_VLP2FPST_0              (FUSES_FCCFG56_VLP2FPST_0_Val << FUSES_FCCFG56_VLP2FPST_Pos) /* (FUSES_FCCFG56) 5us -32 clock cycles based on 6Mhz clock (5US) Position */
+#define FUSES_FCCFG56_VLP2FPST_1              (FUSES_FCCFG56_VLP2FPST_1_Val << FUSES_FCCFG56_VLP2FPST_Pos) /* (FUSES_FCCFG56) 10us -64 clock cycles based on 6Mhz clock (10US) Position */
+#define FUSES_FCCFG56_VLP2FPST_2              (FUSES_FCCFG56_VLP2FPST_2_Val << FUSES_FCCFG56_VLP2FPST_Pos) /* (FUSES_FCCFG56) 21us -128 clock cycles based on 6Mhz clock (21US) Position */
+#define FUSES_FCCFG56_VLP2FPST_3              (FUSES_FCCFG56_VLP2FPST_3_Val << FUSES_FCCFG56_VLP2FPST_Pos) /* (FUSES_FCCFG56) 1.3us -8 clock cycles based on 6Mhz clock (1US) Position */
+#define FUSES_FCCFG56_VLPMST_Pos              _UINT32_(18)                                         /* (FUSES_FCCFG56) Vreg LP Mode Stabilization Time Position */
+#define FUSES_FCCFG56_VLPMST_Msk              (_UINT32_(0x3) << FUSES_FCCFG56_VLPMST_Pos)          /* (FUSES_FCCFG56) Vreg LP Mode Stabilization Time Mask */
+#define FUSES_FCCFG56_VLPMST(value)           (FUSES_FCCFG56_VLPMST_Msk & (_UINT32_(value) << FUSES_FCCFG56_VLPMST_Pos)) /* Assignment of value for VLPMST in the FUSES_FCCFG56 register */
+#define   FUSES_FCCFG56_VLPMST_0_Val          _UINT32_(0x0)                                        /* (FUSES_FCCFG56) 1.3us -8 clock cycles based on 6Mhz clock (1US)  */
+#define   FUSES_FCCFG56_VLPMST_1_Val          _UINT32_(0x1)                                        /* (FUSES_FCCFG56) 2.6us -16 clock cycles based on 6Mhz clock (2US)  */
+#define   FUSES_FCCFG56_VLPMST_2_Val          _UINT32_(0x2)                                        /* (FUSES_FCCFG56) 5us -32 clock cycles based on 6Mhz clock (5US)  */
+#define   FUSES_FCCFG56_VLPMST_3_Val          _UINT32_(0x3)                                        /* (FUSES_FCCFG56) 0.166us -1 clock cycles based on 6Mhz clock (0US)  */
+#define FUSES_FCCFG56_VLPMST_0                (FUSES_FCCFG56_VLPMST_0_Val << FUSES_FCCFG56_VLPMST_Pos) /* (FUSES_FCCFG56) 1.3us -8 clock cycles based on 6Mhz clock (1US) Position */
+#define FUSES_FCCFG56_VLPMST_1                (FUSES_FCCFG56_VLPMST_1_Val << FUSES_FCCFG56_VLPMST_Pos) /* (FUSES_FCCFG56) 2.6us -16 clock cycles based on 6Mhz clock (2US) Position */
+#define FUSES_FCCFG56_VLPMST_2                (FUSES_FCCFG56_VLPMST_2_Val << FUSES_FCCFG56_VLPMST_Pos) /* (FUSES_FCCFG56) 5us -32 clock cycles based on 6Mhz clock (5US) Position */
+#define FUSES_FCCFG56_VLPMST_3                (FUSES_FCCFG56_VLPMST_3_Val << FUSES_FCCFG56_VLPMST_Pos) /* (FUSES_FCCFG56) 0.166us -1 clock cycles based on 6Mhz clock (0US) Position */
+#define FUSES_FCCFG56_VTONST_Pos              _UINT32_(20)                                         /* (FUSES_FCCFG56) Vreg Turned On Stabilization Time Position */
+#define FUSES_FCCFG56_VTONST_Msk              (_UINT32_(0x3) << FUSES_FCCFG56_VTONST_Pos)          /* (FUSES_FCCFG56) Vreg Turned On Stabilization Time Mask */
+#define FUSES_FCCFG56_VTONST(value)           (FUSES_FCCFG56_VTONST_Msk & (_UINT32_(value) << FUSES_FCCFG56_VTONST_Pos)) /* Assignment of value for VTONST in the FUSES_FCCFG56 register */
+#define   FUSES_FCCFG56_VTONST_0_Val          _UINT32_(0x0)                                        /* (FUSES_FCCFG56) 31us -192 clock cycles based on 6Mhz clock (31US)  */
+#define   FUSES_FCCFG56_VTONST_1_Val          _UINT32_(0x1)                                        /* (FUSES_FCCFG56) 42us -256 clock cycles based on 6Mhz clock (42US)  */
+#define   FUSES_FCCFG56_VTONST_2_Val          _UINT32_(0x2)                                        /* (FUSES_FCCFG56) 84us -512 clock cycles based on 6Mhz clock (84US)  */
+#define   FUSES_FCCFG56_VTONST_3_Val          _UINT32_(0x3)                                        /* (FUSES_FCCFG56) 10.6us -64 clock cycles based on 6Mhz clock (10US)  */
+#define FUSES_FCCFG56_VTONST_0                (FUSES_FCCFG56_VTONST_0_Val << FUSES_FCCFG56_VTONST_Pos) /* (FUSES_FCCFG56) 31us -192 clock cycles based on 6Mhz clock (31US) Position */
+#define FUSES_FCCFG56_VTONST_1                (FUSES_FCCFG56_VTONST_1_Val << FUSES_FCCFG56_VTONST_Pos) /* (FUSES_FCCFG56) 42us -256 clock cycles based on 6Mhz clock (42US) Position */
+#define FUSES_FCCFG56_VTONST_2                (FUSES_FCCFG56_VTONST_2_Val << FUSES_FCCFG56_VTONST_Pos) /* (FUSES_FCCFG56) 84us -512 clock cycles based on 6Mhz clock (84US) Position */
+#define FUSES_FCCFG56_VTONST_3                (FUSES_FCCFG56_VTONST_3_Val << FUSES_FCCFG56_VTONST_Pos) /* (FUSES_FCCFG56) 10.6us -64 clock cycles based on 6Mhz clock (10US) Position */
+#define FUSES_FCCFG56_VPDDST_Pos              _UINT32_(22)                                         /* (FUSES_FCCFG56) Vreg Pull Down Disable Stabilization Time Position */
+#define FUSES_FCCFG56_VPDDST_Msk              (_UINT32_(0x3) << FUSES_FCCFG56_VPDDST_Pos)          /* (FUSES_FCCFG56) Vreg Pull Down Disable Stabilization Time Mask */
+#define FUSES_FCCFG56_VPDDST(value)           (FUSES_FCCFG56_VPDDST_Msk & (_UINT32_(value) << FUSES_FCCFG56_VPDDST_Pos)) /* Assignment of value for VPDDST in the FUSES_FCCFG56 register */
+#define   FUSES_FCCFG56_VPDDST_0_Val          _UINT32_(0x0)                                        /* (FUSES_FCCFG56) 21us -128 clock cycles based on 6Mhz clock (21US)  */
+#define   FUSES_FCCFG56_VPDDST_1_Val          _UINT32_(0x1)                                        /* (FUSES_FCCFG56) 42us -256 clock cycles based on 6Mhz clock (42US)  */
+#define   FUSES_FCCFG56_VPDDST_2_Val          _UINT32_(0x2)                                        /* (FUSES_FCCFG56) 84us -512 clock cycles based on 6Mhz clock (84US)  */
+#define   FUSES_FCCFG56_VPDDST_3_Val          _UINT32_(0x3)                                        /* (FUSES_FCCFG56) 10.6us -64 clock cycles based on 6Mhz clock (10US)  */
+#define FUSES_FCCFG56_VPDDST_0                (FUSES_FCCFG56_VPDDST_0_Val << FUSES_FCCFG56_VPDDST_Pos) /* (FUSES_FCCFG56) 21us -128 clock cycles based on 6Mhz clock (21US) Position */
+#define FUSES_FCCFG56_VPDDST_1                (FUSES_FCCFG56_VPDDST_1_Val << FUSES_FCCFG56_VPDDST_Pos) /* (FUSES_FCCFG56) 42us -256 clock cycles based on 6Mhz clock (42US) Position */
+#define FUSES_FCCFG56_VPDDST_2                (FUSES_FCCFG56_VPDDST_2_Val << FUSES_FCCFG56_VPDDST_Pos) /* (FUSES_FCCFG56) 84us -512 clock cycles based on 6Mhz clock (84US) Position */
+#define FUSES_FCCFG56_VPDDST_3                (FUSES_FCCFG56_VPDDST_3_Val << FUSES_FCCFG56_VPDDST_Pos) /* (FUSES_FCCFG56) 10.6us -64 clock cycles based on 6Mhz clock (10US) Position */
+#define FUSES_FCCFG56_VDVSST_Pos              _UINT32_(24)                                         /* (FUSES_FCCFG56) Vreg Down Voltage Scaling Stabilization Time Position */
+#define FUSES_FCCFG56_VDVSST_Msk              (_UINT32_(0x3) << FUSES_FCCFG56_VDVSST_Pos)          /* (FUSES_FCCFG56) Vreg Down Voltage Scaling Stabilization Time Mask */
+#define FUSES_FCCFG56_VDVSST(value)           (FUSES_FCCFG56_VDVSST_Msk & (_UINT32_(value) << FUSES_FCCFG56_VDVSST_Pos)) /* Assignment of value for VDVSST in the FUSES_FCCFG56 register */
+#define   FUSES_FCCFG56_VDVSST_0_Val          _UINT32_(0x0)                                        /* (FUSES_FCCFG56) 32us -192 clock cycles based on 6Mhz clock (32US)  */
+#define   FUSES_FCCFG56_VDVSST_1_Val          _UINT32_(0x1)                                        /* (FUSES_FCCFG56) 42us -256 clock cycles based on 6Mhz clock (42US)  */
+#define   FUSES_FCCFG56_VDVSST_2_Val          _UINT32_(0x2)                                        /* (FUSES_FCCFG56) 84us -512 clock cycles based on 6Mhz clock (84US)  */
+#define   FUSES_FCCFG56_VDVSST_3_Val          _UINT32_(0x3)                                        /* (FUSES_FCCFG56) 10us -64 clock cycles based on 6Mhz clock (10US)  */
+#define FUSES_FCCFG56_VDVSST_0                (FUSES_FCCFG56_VDVSST_0_Val << FUSES_FCCFG56_VDVSST_Pos) /* (FUSES_FCCFG56) 32us -192 clock cycles based on 6Mhz clock (32US) Position */
+#define FUSES_FCCFG56_VDVSST_1                (FUSES_FCCFG56_VDVSST_1_Val << FUSES_FCCFG56_VDVSST_Pos) /* (FUSES_FCCFG56) 42us -256 clock cycles based on 6Mhz clock (42US) Position */
+#define FUSES_FCCFG56_VDVSST_2                (FUSES_FCCFG56_VDVSST_2_Val << FUSES_FCCFG56_VDVSST_Pos) /* (FUSES_FCCFG56) 84us -512 clock cycles based on 6Mhz clock (84US) Position */
+#define FUSES_FCCFG56_VDVSST_3                (FUSES_FCCFG56_VDVSST_3_Val << FUSES_FCCFG56_VDVSST_Pos) /* (FUSES_FCCFG56) 10us -64 clock cycles based on 6Mhz clock (10US) Position */
+#define FUSES_FCCFG56_Msk                     _UINT32_(0x03FF0033)                                 /* (FUSES_FCCFG56) Register Mask  */
+
+
+/* -------- FUSES_FCCFG57 : (FUSES Offset: 0x164) ( R/ 32) Calibration Configuration 57 Register -------- */
+#define FUSES_FCCFG57_DLYVAL_Pos              _UINT32_(0)                                          /* (FUSES_FCCFG57) Delay Value Position */
+#define FUSES_FCCFG57_DLYVAL_Msk              (_UINT32_(0x7F) << FUSES_FCCFG57_DLYVAL_Pos)         /* (FUSES_FCCFG57) Delay Value Mask */
+#define FUSES_FCCFG57_DLYVAL(value)           (FUSES_FCCFG57_DLYVAL_Msk & (_UINT32_(value) << FUSES_FCCFG57_DLYVAL_Pos)) /* Assignment of value for DLYVAL in the FUSES_FCCFG57 register */
+#define FUSES_FCCFG57_IGNACK_Pos              _UINT32_(7)                                          /* (FUSES_FCCFG57) Ignore Acknowledge Position */
+#define FUSES_FCCFG57_IGNACK_Msk              (_UINT32_(0x1) << FUSES_FCCFG57_IGNACK_Pos)          /* (FUSES_FCCFG57) Ignore Acknowledge Mask */
+#define FUSES_FCCFG57_IGNACK(value)           (FUSES_FCCFG57_IGNACK_Msk & (_UINT32_(value) << FUSES_FCCFG57_IGNACK_Pos)) /* Assignment of value for IGNACK in the FUSES_FCCFG57 register */
+#define   FUSES_FCCFG57_IGNACK_0_Val          _UINT32_(0x0)                                        /* (FUSES_FCCFG57) Power Switch acknowledge signal is taken into account when entering/exiting retention mode. According to the DLYVAL field, a supplementary delay is also added (from 0 to 127 digital ring oscillator period)  */
+#define   FUSES_FCCFG57_IGNACK_1_Val          _UINT32_(0x1)                                        /* (FUSES_FCCFG57) Power Switch acknowledge signal is ignored when entering/exiting retention mode, and is replaced by a overflow counter signal clocked on internal digital ring oscillator. The overflow counter is programmable by using the DLYVAL field  */
+#define FUSES_FCCFG57_IGNACK_0                (FUSES_FCCFG57_IGNACK_0_Val << FUSES_FCCFG57_IGNACK_Pos) /* (FUSES_FCCFG57) Power Switch acknowledge signal is taken into account when entering/exiting retention mode. According to the DLYVAL field, a supplementary delay is also added (from 0 to 127 digital ring oscillator period) Position */
+#define FUSES_FCCFG57_IGNACK_1                (FUSES_FCCFG57_IGNACK_1_Val << FUSES_FCCFG57_IGNACK_Pos) /* (FUSES_FCCFG57) Power Switch acknowledge signal is ignored when entering/exiting retention mode, and is replaced by a overflow counter signal clocked on internal digital ring oscillator. The overflow counter is programmable by using the DLYVAL field Position */
+#define FUSES_FCCFG57_Msk                     _UINT32_(0x000000FF)                                 /* (FUSES_FCCFG57) Register Mask  */
+
+
+/* -------- FUSES_FCCFG58 : (FUSES Offset: 0x168) ( R/ 32) Calibration Configuration 58 Register -------- */
+#define FUSES_FCCFG58_BRINGOSC_Pos            _UINT32_(0)                                          /* (FUSES_FCCFG58) Backup Ring Oscillator Size Depth Position */
+#define FUSES_FCCFG58_BRINGOSC_Msk            (_UINT32_(0x3) << FUSES_FCCFG58_BRINGOSC_Pos)        /* (FUSES_FCCFG58) Backup Ring Oscillator Size Depth Mask */
+#define FUSES_FCCFG58_BRINGOSC(value)         (FUSES_FCCFG58_BRINGOSC_Msk & (_UINT32_(value) << FUSES_FCCFG58_BRINGOSC_Pos)) /* Assignment of value for BRINGOSC in the FUSES_FCCFG58 register */
+#define   FUSES_FCCFG58_BRINGOSC_0_Val        _UINT32_(0x0)                                        /* (FUSES_FCCFG58) Ring Oscillator depth is default (DLY0)  */
+#define   FUSES_FCCFG58_BRINGOSC_1_Val        _UINT32_(0x1)                                        /* (FUSES_FCCFG58) Ring Oscillator depth is default + 1 ORDLY15 (DLY1)  */
+#define   FUSES_FCCFG58_BRINGOSC_2_Val        _UINT32_(0x2)                                        /* (FUSES_FCCFG58) Ring Oscillator depth is default + 2 ORDLU15 (DLY2)  */
+#define   FUSES_FCCFG58_BRINGOSC_3_Val        _UINT32_(0x3)                                        /* (FUSES_FCCFG58) Ring Oscillator depth is default + 3 ORDLY15 (DLY3)  */
+#define FUSES_FCCFG58_BRINGOSC_0              (FUSES_FCCFG58_BRINGOSC_0_Val << FUSES_FCCFG58_BRINGOSC_Pos) /* (FUSES_FCCFG58) Ring Oscillator depth is default (DLY0) Position */
+#define FUSES_FCCFG58_BRINGOSC_1              (FUSES_FCCFG58_BRINGOSC_1_Val << FUSES_FCCFG58_BRINGOSC_Pos) /* (FUSES_FCCFG58) Ring Oscillator depth is default + 1 ORDLY15 (DLY1) Position */
+#define FUSES_FCCFG58_BRINGOSC_2              (FUSES_FCCFG58_BRINGOSC_2_Val << FUSES_FCCFG58_BRINGOSC_Pos) /* (FUSES_FCCFG58) Ring Oscillator depth is default + 2 ORDLU15 (DLY2) Position */
+#define FUSES_FCCFG58_BRINGOSC_3              (FUSES_FCCFG58_BRINGOSC_3_Val << FUSES_FCCFG58_BRINGOSC_Pos) /* (FUSES_FCCFG58) Ring Oscillator depth is default + 3 ORDLY15 (DLY3) Position */
+#define FUSES_FCCFG58_Msk                     _UINT32_(0x00000003)                                 /* (FUSES_FCCFG58) Register Mask  */
+
+
+/* -------- FUSES_FCCFG59 : (FUSES Offset: 0x16C) ( R/ 32) Calibration Configuration 59 Register -------- */
+#define FUSES_FCCFG59_IDAU_EN_Pos             _UINT32_(0)                                          /* (FUSES_FCCFG59) IDAU Enabled Position */
+#define FUSES_FCCFG59_IDAU_EN_Msk             (_UINT32_(0x1) << FUSES_FCCFG59_IDAU_EN_Pos)         /* (FUSES_FCCFG59) IDAU Enabled Mask */
+#define FUSES_FCCFG59_IDAU_EN(value)          (FUSES_FCCFG59_IDAU_EN_Msk & (_UINT32_(value) << FUSES_FCCFG59_IDAU_EN_Pos)) /* Assignment of value for IDAU_EN in the FUSES_FCCFG59 register */
+#define   FUSES_FCCFG59_IDAU_EN_0_Val         _UINT32_(0x0)                                        /* (FUSES_FCCFG59) GC device. All IDAU regions exempt. The boot code will initialize the IDAU, H2PB and PAC as described in Section 2.9.2  */
+#define   FUSES_FCCFG59_IDAU_EN_1_Val         _UINT32_(0x1)                                        /* (FUSES_FCCFG59) IDAU regions enabled. The boot code will initialize the IDAU, H2PB and PAC to the values set by customer and referred to in USERCFG as described in Section 2.9.3  */
+#define FUSES_FCCFG59_IDAU_EN_0               (FUSES_FCCFG59_IDAU_EN_0_Val << FUSES_FCCFG59_IDAU_EN_Pos) /* (FUSES_FCCFG59) GC device. All IDAU regions exempt. The boot code will initialize the IDAU, H2PB and PAC as described in Section 2.9.2 Position */
+#define FUSES_FCCFG59_IDAU_EN_1               (FUSES_FCCFG59_IDAU_EN_1_Val << FUSES_FCCFG59_IDAU_EN_Pos) /* (FUSES_FCCFG59) IDAU regions enabled. The boot code will initialize the IDAU, H2PB and PAC to the values set by customer and referred to in USERCFG as described in Section 2.9.3 Position */
+#define FUSES_FCCFG59_Msk                     _UINT32_(0x00000001)                                 /* (FUSES_FCCFG59) Register Mask  */
+
+
+/* -------- FUSES_FCCFG60 : (FUSES Offset: 0x170) ( R/ 32) Calibration Configuration 60 Register -------- */
+#define FUSES_FCCFG60_PUFRAMDNTIME_Pos        _UINT32_(0)                                          /* (FUSES_FCCFG60) PUF RAM Power Down Delay Time Position */
+#define FUSES_FCCFG60_PUFRAMDNTIME_Msk        (_UINT32_(0xFFFFFFFF) << FUSES_FCCFG60_PUFRAMDNTIME_Pos) /* (FUSES_FCCFG60) PUF RAM Power Down Delay Time Mask */
+#define FUSES_FCCFG60_PUFRAMDNTIME(value)     (FUSES_FCCFG60_PUFRAMDNTIME_Msk & (_UINT32_(value) << FUSES_FCCFG60_PUFRAMDNTIME_Pos)) /* Assignment of value for PUFRAMDNTIME in the FUSES_FCCFG60 register */
+#define FUSES_FCCFG60_Msk                     _UINT32_(0xFFFFFFFF)                                 /* (FUSES_FCCFG60) Register Mask  */
+
+
+/* -------- FUSES_FCCFG61 : (FUSES Offset: 0x174) ( R/ 32) Calibration Configuration 61 Register -------- */
+#define FUSES_FCCFG61_PUFRAMUPTIME_Pos        _UINT32_(0)                                          /* (FUSES_FCCFG61) PUF RAM Power Up Delay Time Position */
+#define FUSES_FCCFG61_PUFRAMUPTIME_Msk        (_UINT32_(0xFFFFFFFF) << FUSES_FCCFG61_PUFRAMUPTIME_Pos) /* (FUSES_FCCFG61) PUF RAM Power Up Delay Time Mask */
+#define FUSES_FCCFG61_PUFRAMUPTIME(value)     (FUSES_FCCFG61_PUFRAMUPTIME_Msk & (_UINT32_(value) << FUSES_FCCFG61_PUFRAMUPTIME_Pos)) /* Assignment of value for PUFRAMUPTIME in the FUSES_FCCFG61 register */
+#define FUSES_FCCFG61_Msk                     _UINT32_(0xFFFFFFFF)                                 /* (FUSES_FCCFG61) Register Mask  */
+
+
+/* -------- FUSES_FCCFG64 : (FUSES Offset: 0x180) ( R/ 32) Calibration Configuration 64 Register -------- */
+#define FUSES_FCCFG64_PTC_CALIB_PTC_IBIAS_TRIM_Pos _UINT32_(0)                                          /* (FUSES_FCCFG64) PTC IBIAS TRIM Position */
+#define FUSES_FCCFG64_PTC_CALIB_PTC_IBIAS_TRIM_Msk (_UINT32_(0x7) << FUSES_FCCFG64_PTC_CALIB_PTC_IBIAS_TRIM_Pos) /* (FUSES_FCCFG64) PTC IBIAS TRIM Mask */
+#define FUSES_FCCFG64_PTC_CALIB_PTC_IBIAS_TRIM(value) (FUSES_FCCFG64_PTC_CALIB_PTC_IBIAS_TRIM_Msk & (_UINT32_(value) << FUSES_FCCFG64_PTC_CALIB_PTC_IBIAS_TRIM_Pos)) /* Assignment of value for PTC_CALIB_PTC_IBIAS_TRIM in the FUSES_FCCFG64 register */
+#define FUSES_FCCFG64_PTC_CALIB_PTAT_EN_Pos   _UINT32_(3)                                          /* (FUSES_FCCFG64) Enable PTAT current Position */
+#define FUSES_FCCFG64_PTC_CALIB_PTAT_EN_Msk   (_UINT32_(0x1) << FUSES_FCCFG64_PTC_CALIB_PTAT_EN_Pos) /* (FUSES_FCCFG64) Enable PTAT current Mask */
+#define FUSES_FCCFG64_PTC_CALIB_PTAT_EN(value) (FUSES_FCCFG64_PTC_CALIB_PTAT_EN_Msk & (_UINT32_(value) << FUSES_FCCFG64_PTC_CALIB_PTAT_EN_Pos)) /* Assignment of value for PTC_CALIB_PTAT_EN in the FUSES_FCCFG64 register */
+#define FUSES_FCCFG64_PTC_CALIB_EXT_IBIAS_EN_Pos _UINT32_(4)                                          /* (FUSES_FCCFG64) Enable External Bias Position */
+#define FUSES_FCCFG64_PTC_CALIB_EXT_IBIAS_EN_Msk (_UINT32_(0x1) << FUSES_FCCFG64_PTC_CALIB_EXT_IBIAS_EN_Pos) /* (FUSES_FCCFG64) Enable External Bias Mask */
+#define FUSES_FCCFG64_PTC_CALIB_EXT_IBIAS_EN(value) (FUSES_FCCFG64_PTC_CALIB_EXT_IBIAS_EN_Msk & (_UINT32_(value) << FUSES_FCCFG64_PTC_CALIB_EXT_IBIAS_EN_Pos)) /* Assignment of value for PTC_CALIB_EXT_IBIAS_EN in the FUSES_FCCFG64 register */
+#define FUSES_FCCFG64_Msk                     _UINT32_(0x0000001F)                                 /* (FUSES_FCCFG64) Register Mask  */
+
+
+/* -------- FUSES_FCCFG65 : (FUSES Offset: 0x184) ( R/ 32) Calibration Configuration 65 Register -------- */
+#define FUSES_FCCFG65_EN_CMBF_Pos             _UINT32_(0)                                          /* (FUSES_FCCFG65) Enable Common Mode Power Cycling Position */
+#define FUSES_FCCFG65_EN_CMBF_Msk             (_UINT32_(0x1) << FUSES_FCCFG65_EN_CMBF_Pos)         /* (FUSES_FCCFG65) Enable Common Mode Power Cycling Mask */
+#define FUSES_FCCFG65_EN_CMBF(value)          (FUSES_FCCFG65_EN_CMBF_Msk & (_UINT32_(value) << FUSES_FCCFG65_EN_CMBF_Pos)) /* Assignment of value for EN_CMBF in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_EN_DITHER_Pos           _UINT32_(2)                                          /* (FUSES_FCCFG65) Enable Dithering Position */
+#define FUSES_FCCFG65_EN_DITHER_Msk           (_UINT32_(0x1) << FUSES_FCCFG65_EN_DITHER_Pos)       /* (FUSES_FCCFG65) Enable Dithering Mask */
+#define FUSES_FCCFG65_EN_DITHER(value)        (FUSES_FCCFG65_EN_DITHER_Msk & (_UINT32_(value) << FUSES_FCCFG65_EN_DITHER_Pos)) /* Assignment of value for EN_DITHER in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_DIS_FAZ_Pos             _UINT32_(3)                                          /* (FUSES_FCCFG65) First Auto Zeroing Position */
+#define FUSES_FCCFG65_DIS_FAZ_Msk             (_UINT32_(0x1) << FUSES_FCCFG65_DIS_FAZ_Pos)         /* (FUSES_FCCFG65) First Auto Zeroing Mask */
+#define FUSES_FCCFG65_DIS_FAZ(value)          (FUSES_FCCFG65_DIS_FAZ_Msk & (_UINT32_(value) << FUSES_FCCFG65_DIS_FAZ_Pos)) /* Assignment of value for DIS_FAZ in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_DIS_SAZ_Pos             _UINT32_(4)                                          /* (FUSES_FCCFG65) Second Auto Zeroing Position */
+#define FUSES_FCCFG65_DIS_SAZ_Msk             (_UINT32_(0x1) << FUSES_FCCFG65_DIS_SAZ_Pos)         /* (FUSES_FCCFG65) Second Auto Zeroing Mask */
+#define FUSES_FCCFG65_DIS_SAZ(value)          (FUSES_FCCFG65_DIS_SAZ_Msk & (_UINT32_(value) << FUSES_FCCFG65_DIS_SAZ_Pos)) /* Assignment of value for DIS_SAZ in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_DIS_LAZ_Pos             _UINT32_(5)                                          /* (FUSES_FCCFG65) Current Auto Zeroing Position */
+#define FUSES_FCCFG65_DIS_LAZ_Msk             (_UINT32_(0x1) << FUSES_FCCFG65_DIS_LAZ_Pos)         /* (FUSES_FCCFG65) Current Auto Zeroing Mask */
+#define FUSES_FCCFG65_DIS_LAZ(value)          (FUSES_FCCFG65_DIS_LAZ_Msk & (_UINT32_(value) << FUSES_FCCFG65_DIS_LAZ_Pos)) /* Assignment of value for DIS_LAZ in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_EN_RDAC_Pos             _UINT32_(6)                                          /* (FUSES_FCCFG65) RDAC Duty Cycle Position */
+#define FUSES_FCCFG65_EN_RDAC_Msk             (_UINT32_(0x1) << FUSES_FCCFG65_EN_RDAC_Pos)         /* (FUSES_FCCFG65) RDAC Duty Cycle Mask */
+#define FUSES_FCCFG65_EN_RDAC(value)          (FUSES_FCCFG65_EN_RDAC_Msk & (_UINT32_(value) << FUSES_FCCFG65_EN_RDAC_Pos)) /* Assignment of value for EN_RDAC in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_DBG_SEL_Pos             _UINT32_(7)                                          /* (FUSES_FCCFG65) Enable Test Output Position */
+#define FUSES_FCCFG65_DBG_SEL_Msk             (_UINT32_(0x1) << FUSES_FCCFG65_DBG_SEL_Pos)         /* (FUSES_FCCFG65) Enable Test Output Mask */
+#define FUSES_FCCFG65_DBG_SEL(value)          (FUSES_FCCFG65_DBG_SEL_Msk & (_UINT32_(value) << FUSES_FCCFG65_DBG_SEL_Pos)) /* Assignment of value for DBG_SEL in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_SEL_DEL_Pos             _UINT32_(8)                                          /* (FUSES_FCCFG65) Select Value to comp_out Position */
+#define FUSES_FCCFG65_SEL_DEL_Msk             (_UINT32_(0x1) << FUSES_FCCFG65_SEL_DEL_Pos)         /* (FUSES_FCCFG65) Select Value to comp_out Mask */
+#define FUSES_FCCFG65_SEL_DEL(value)          (FUSES_FCCFG65_SEL_DEL_Msk & (_UINT32_(value) << FUSES_FCCFG65_SEL_DEL_Pos)) /* Assignment of value for SEL_DEL in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_T1_DELAY_Pos            _UINT32_(9)                                          /* (FUSES_FCCFG65) Programmable delay, selects the delay between regen and latch Position */
+#define FUSES_FCCFG65_T1_DELAY_Msk            (_UINT32_(0x3) << FUSES_FCCFG65_T1_DELAY_Pos)        /* (FUSES_FCCFG65) Programmable delay, selects the delay between regen and latch Mask */
+#define FUSES_FCCFG65_T1_DELAY(value)         (FUSES_FCCFG65_T1_DELAY_Msk & (_UINT32_(value) << FUSES_FCCFG65_T1_DELAY_Pos)) /* Assignment of value for T1_DELAY in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_TCLK_DIV_Pos            _UINT32_(11)                                         /* (FUSES_FCCFG65) Programmable divider for adc_clk_div. The division ratio is 256, 128, 64,32, and 16 going from MSB to LSB. Position */
+#define FUSES_FCCFG65_TCLK_DIV_Msk            (_UINT32_(0x1F) << FUSES_FCCFG65_TCLK_DIV_Pos)       /* (FUSES_FCCFG65) Programmable divider for adc_clk_div. The division ratio is 256, 128, 64,32, and 16 going from MSB to LSB. Mask */
+#define FUSES_FCCFG65_TCLK_DIV(value)         (FUSES_FCCFG65_TCLK_DIV_Msk & (_UINT32_(value) << FUSES_FCCFG65_TCLK_DIV_Pos)) /* Assignment of value for TCLK_DIV in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_IADC_1_Pos              _UINT32_(20)                                         /* (FUSES_FCCFG65) Controls the current consumption for of the whole ADC Position */
+#define FUSES_FCCFG65_IADC_1_Msk              (_UINT32_(0x3) << FUSES_FCCFG65_IADC_1_Pos)          /* (FUSES_FCCFG65) Controls the current consumption for of the whole ADC Mask */
+#define FUSES_FCCFG65_IADC_1(value)           (FUSES_FCCFG65_IADC_1_Msk & (_UINT32_(value) << FUSES_FCCFG65_IADC_1_Pos)) /* Assignment of value for IADC_1 in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_IADC_2_Pos              _UINT32_(22)                                         /* (FUSES_FCCFG65) Controls the current consumption for of the whole ADC. Position */
+#define FUSES_FCCFG65_IADC_2_Msk              (_UINT32_(0x3) << FUSES_FCCFG65_IADC_2_Pos)          /* (FUSES_FCCFG65) Controls the current consumption for of the whole ADC. Mask */
+#define FUSES_FCCFG65_IADC_2(value)           (FUSES_FCCFG65_IADC_2_Msk & (_UINT32_(value) << FUSES_FCCFG65_IADC_2_Pos)) /* Assignment of value for IADC_2 in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_ICMP_1_Pos              _UINT32_(24)                                         /* (FUSES_FCCFG65) Controls the bias current for 1 stage of the comparator. This will control the resolution needed by comparator. More current means less time but at expense of gain. Position */
+#define FUSES_FCCFG65_ICMP_1_Msk              (_UINT32_(0x3) << FUSES_FCCFG65_ICMP_1_Pos)          /* (FUSES_FCCFG65) Controls the bias current for 1 stage of the comparator. This will control the resolution needed by comparator. More current means less time but at expense of gain. Mask */
+#define FUSES_FCCFG65_ICMP_1(value)           (FUSES_FCCFG65_ICMP_1_Msk & (_UINT32_(value) << FUSES_FCCFG65_ICMP_1_Pos)) /* Assignment of value for ICMP_1 in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_ICMP_2_Pos              _UINT32_(26)                                         /* (FUSES_FCCFG65) Controls the bias current for 2 stage of the comparator. This will control the resolution needed by comparator. More current means less time but at expense of gain. Position */
+#define FUSES_FCCFG65_ICMP_2_Msk              (_UINT32_(0x3) << FUSES_FCCFG65_ICMP_2_Pos)          /* (FUSES_FCCFG65) Controls the bias current for 2 stage of the comparator. This will control the resolution needed by comparator. More current means less time but at expense of gain. Mask */
+#define FUSES_FCCFG65_ICMP_2(value)           (FUSES_FCCFG65_ICMP_2_Msk & (_UINT32_(value) << FUSES_FCCFG65_ICMP_2_Pos)) /* Assignment of value for ICMP_2 in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_ICMBF_Pos               _UINT32_(28)                                         /* (FUSES_FCCFG65) Controls the bias current for Common mode buffer amplifier (CMBF) Position */
+#define FUSES_FCCFG65_ICMBF_Msk               (_UINT32_(0x3) << FUSES_FCCFG65_ICMBF_Pos)           /* (FUSES_FCCFG65) Controls the bias current for Common mode buffer amplifier (CMBF) Mask */
+#define FUSES_FCCFG65_ICMBF(value)            (FUSES_FCCFG65_ICMBF_Msk & (_UINT32_(value) << FUSES_FCCFG65_ICMBF_Pos)) /* Assignment of value for ICMBF in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_EN_ATEST_Pos            _UINT32_(30)                                         /* (FUSES_FCCFG65) Enable analog test signals Position */
+#define FUSES_FCCFG65_EN_ATEST_Msk            (_UINT32_(0x1) << FUSES_FCCFG65_EN_ATEST_Pos)        /* (FUSES_FCCFG65) Enable analog test signals Mask */
+#define FUSES_FCCFG65_EN_ATEST(value)         (FUSES_FCCFG65_EN_ATEST_Msk & (_UINT32_(value) << FUSES_FCCFG65_EN_ATEST_Pos)) /* Assignment of value for EN_ATEST in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_EN_EXT_BIAS_Pos         _UINT32_(31)                                         /* (FUSES_FCCFG65) Internal switched capacitor bias current allows to make the bias current proportional to conversion frequency. Position */
+#define FUSES_FCCFG65_EN_EXT_BIAS_Msk         (_UINT32_(0x1) << FUSES_FCCFG65_EN_EXT_BIAS_Pos)     /* (FUSES_FCCFG65) Internal switched capacitor bias current allows to make the bias current proportional to conversion frequency. Mask */
+#define FUSES_FCCFG65_EN_EXT_BIAS(value)      (FUSES_FCCFG65_EN_EXT_BIAS_Msk & (_UINT32_(value) << FUSES_FCCFG65_EN_EXT_BIAS_Pos)) /* Assignment of value for EN_EXT_BIAS in the FUSES_FCCFG65 register */
+#define FUSES_FCCFG65_Msk                     _UINT32_(0xFFF0FFFD)                                 /* (FUSES_FCCFG65) Register Mask  */
+
+
+/* -------- FUSES_FCCFG66 : (FUSES Offset: 0x188) ( R/ 32) Calibration Configuration 66 Register -------- */
+#define FUSES_FCCFG66_AC_CONFIG_Pos           _UINT32_(0)                                          /* (FUSES_FCCFG66) Comparator 0 Calibration Configuration bits.' Position */
+#define FUSES_FCCFG66_AC_CONFIG_Msk           (_UINT32_(0xF) << FUSES_FCCFG66_AC_CONFIG_Pos)       /* (FUSES_FCCFG66) Comparator 0 Calibration Configuration bits.' Mask */
+#define FUSES_FCCFG66_AC_CONFIG(value)        (FUSES_FCCFG66_AC_CONFIG_Msk & (_UINT32_(value) << FUSES_FCCFG66_AC_CONFIG_Pos)) /* Assignment of value for AC_CONFIG in the FUSES_FCCFG66 register */
+#define FUSES_FCCFG66_Msk                     _UINT32_(0x0000000F)                                 /* (FUSES_FCCFG66) Register Mask  */
+
+
+/* -------- FUSES_FCCFG68 : (FUSES Offset: 0x190) ( R/ 32) Calibration Configuration 68 Register -------- */
+#define FUSES_FCCFG68_TRANSP_Pos              _UINT32_(0)                                          /* (FUSES_FCCFG68) USB PAD P Driver Configuration bits.' Position */
+#define FUSES_FCCFG68_TRANSP_Msk              (_UINT32_(0x1F) << FUSES_FCCFG68_TRANSP_Pos)         /* (FUSES_FCCFG68) USB PAD P Driver Configuration bits.' Mask */
+#define FUSES_FCCFG68_TRANSP(value)           (FUSES_FCCFG68_TRANSP_Msk & (_UINT32_(value) << FUSES_FCCFG68_TRANSP_Pos)) /* Assignment of value for TRANSP in the FUSES_FCCFG68 register */
+#define FUSES_FCCFG68_TRANSN_Pos              _UINT32_(6)                                          /* (FUSES_FCCFG68) USB PAD N Driver Configuration bits.' Position */
+#define FUSES_FCCFG68_TRANSN_Msk              (_UINT32_(0x1F) << FUSES_FCCFG68_TRANSN_Pos)         /* (FUSES_FCCFG68) USB PAD N Driver Configuration bits.' Mask */
+#define FUSES_FCCFG68_TRANSN(value)           (FUSES_FCCFG68_TRANSN_Msk & (_UINT32_(value) << FUSES_FCCFG68_TRANSN_Pos)) /* Assignment of value for TRANSN in the FUSES_FCCFG68 register */
+#define FUSES_FCCFG68_TRIM_Pos                _UINT32_(12)                                         /* (FUSES_FCCFG68) USB PAD Rise/Fall Configuration bits.' Position */
+#define FUSES_FCCFG68_TRIM_Msk                (_UINT32_(0x7) << FUSES_FCCFG68_TRIM_Pos)            /* (FUSES_FCCFG68) USB PAD Rise/Fall Configuration bits.' Mask */
+#define FUSES_FCCFG68_TRIM(value)             (FUSES_FCCFG68_TRIM_Msk & (_UINT32_(value) << FUSES_FCCFG68_TRIM_Pos)) /* Assignment of value for TRIM in the FUSES_FCCFG68 register */
+#define FUSES_FCCFG68_Msk                     _UINT32_(0x000077DF)                                 /* (FUSES_FCCFG68) Register Mask  */
+
+
+/* FUSES register offsets definitions */
+#define FUSES_DAL_REG_OFST             _UINT32_(0x00)      /* (FUSES_DAL) DEVICE ACCESS LEVEL Register Offset */
+#define FUSES_FRCFGBROM_REG_OFST       _UINT32_(0x400)     /* (FUSES_FRCFGBROM) PRE-BOOT bromc user Options Register Offset */
+#define FUSES_FRCFGMBIST_REG_OFST      _UINT32_(0x408)     /* (FUSES_FRCFGMBIST) PRE-BOOT MBIST user Options Register Offset */
+#define FUSES_KEYVAL_INTCHK0_REG_OFST  _UINT32_(0x420)     /* (FUSES_KEYVAL_INTCHK0) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_INTCHK1_REG_OFST  _UINT32_(0x424)     /* (FUSES_KEYVAL_INTCHK1) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_INTCHK2_REG_OFST  _UINT32_(0x428)     /* (FUSES_KEYVAL_INTCHK2) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_INTCHK3_REG_OFST  _UINT32_(0x42C)     /* (FUSES_KEYVAL_INTCHK3) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_INTCHK4_REG_OFST  _UINT32_(0x430)     /* (FUSES_KEYVAL_INTCHK4) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_INTCHK5_REG_OFST  _UINT32_(0x434)     /* (FUSES_KEYVAL_INTCHK5) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_INTCHK6_REG_OFST  _UINT32_(0x438)     /* (FUSES_KEYVAL_INTCHK6) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_INTCHK7_REG_OFST  _UINT32_(0x43C)     /* (FUSES_KEYVAL_INTCHK7) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_ALL0_REG_OFST  _UINT32_(0x440)     /* (FUSES_KEYVAL_CE_ALL0) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_ALL1_REG_OFST  _UINT32_(0x444)     /* (FUSES_KEYVAL_CE_ALL1) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_ALL2_REG_OFST  _UINT32_(0x448)     /* (FUSES_KEYVAL_CE_ALL2) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_ALL3_REG_OFST  _UINT32_(0x44C)     /* (FUSES_KEYVAL_CE_ALL3) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_ALL4_REG_OFST  _UINT32_(0x450)     /* (FUSES_KEYVAL_CE_ALL4) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_ALL5_REG_OFST  _UINT32_(0x454)     /* (FUSES_KEYVAL_CE_ALL5) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_ALL6_REG_OFST  _UINT32_(0x458)     /* (FUSES_KEYVAL_CE_ALL6) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_ALL7_REG_OFST  _UINT32_(0x45C)     /* (FUSES_KEYVAL_CE_ALL7) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S_CR0_REG_OFST _UINT32_(0x460)     /* (FUSES_KEYVAL_CE_S_CR0) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S_CR1_REG_OFST _UINT32_(0x464)     /* (FUSES_KEYVAL_CE_S_CR1) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S_CR2_REG_OFST _UINT32_(0x468)     /* (FUSES_KEYVAL_CE_S_CR2) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S_CR3_REG_OFST _UINT32_(0x46C)     /* (FUSES_KEYVAL_CE_S_CR3) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S_CR4_REG_OFST _UINT32_(0x470)     /* (FUSES_KEYVAL_CE_S_CR4) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S_CR5_REG_OFST _UINT32_(0x474)     /* (FUSES_KEYVAL_CE_S_CR5) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S_CR6_REG_OFST _UINT32_(0x478)     /* (FUSES_KEYVAL_CE_S_CR6) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S_CR7_REG_OFST _UINT32_(0x47C)     /* (FUSES_KEYVAL_CE_S_CR7) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S0_REG_OFST    _UINT32_(0x480)     /* (FUSES_KEYVAL_CE_S0) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S1_REG_OFST    _UINT32_(0x484)     /* (FUSES_KEYVAL_CE_S1) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S2_REG_OFST    _UINT32_(0x488)     /* (FUSES_KEYVAL_CE_S2) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S3_REG_OFST    _UINT32_(0x48C)     /* (FUSES_KEYVAL_CE_S3) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S4_REG_OFST    _UINT32_(0x490)     /* (FUSES_KEYVAL_CE_S4) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S5_REG_OFST    _UINT32_(0x494)     /* (FUSES_KEYVAL_CE_S5) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S6_REG_OFST    _UINT32_(0x498)     /* (FUSES_KEYVAL_CE_S6) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_S7_REG_OFST    _UINT32_(0x49C)     /* (FUSES_KEYVAL_CE_S7) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS_CR0_REG_OFST _UINT32_(0x4A0)     /* (FUSES_KEYVAL_CE_NS_CR0) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS_CR1_REG_OFST _UINT32_(0x4A4)     /* (FUSES_KEYVAL_CE_NS_CR1) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS_CR2_REG_OFST _UINT32_(0x4A8)     /* (FUSES_KEYVAL_CE_NS_CR2) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS_CR3_REG_OFST _UINT32_(0x4AC)     /* (FUSES_KEYVAL_CE_NS_CR3) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS_CR4_REG_OFST _UINT32_(0x4B0)     /* (FUSES_KEYVAL_CE_NS_CR4) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS_CR5_REG_OFST _UINT32_(0x4B4)     /* (FUSES_KEYVAL_CE_NS_CR5) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS_CR6_REG_OFST _UINT32_(0x4B8)     /* (FUSES_KEYVAL_CE_NS_CR6) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS_CR7_REG_OFST _UINT32_(0x4BC)     /* (FUSES_KEYVAL_CE_NS_CR7) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS0_REG_OFST   _UINT32_(0x4C0)     /* (FUSES_KEYVAL_CE_NS0) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS1_REG_OFST   _UINT32_(0x4C4)     /* (FUSES_KEYVAL_CE_NS1) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS2_REG_OFST   _UINT32_(0x4C8)     /* (FUSES_KEYVAL_CE_NS2) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS3_REG_OFST   _UINT32_(0x4CC)     /* (FUSES_KEYVAL_CE_NS3) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS4_REG_OFST   _UINT32_(0x4D0)     /* (FUSES_KEYVAL_CE_NS4) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS5_REG_OFST   _UINT32_(0x4D4)     /* (FUSES_KEYVAL_CE_NS5) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS6_REG_OFST   _UINT32_(0x4D8)     /* (FUSES_KEYVAL_CE_NS6) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_CE_NS7_REG_OFST   _UINT32_(0x4DC)     /* (FUSES_KEYVAL_CE_NS7) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_PRG_PG0_REG_OFST  _UINT32_(0x4E0)     /* (FUSES_KEYVAL_PRG_PG0) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_PRG_PG1_REG_OFST  _UINT32_(0x4E4)     /* (FUSES_KEYVAL_PRG_PG1) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_PRG_PG2_REG_OFST  _UINT32_(0x4E8)     /* (FUSES_KEYVAL_PRG_PG2) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_PRG_PG3_REG_OFST  _UINT32_(0x4EC)     /* (FUSES_KEYVAL_PRG_PG3) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_PRG_PG4_REG_OFST  _UINT32_(0x4F0)     /* (FUSES_KEYVAL_PRG_PG4) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_PRG_PG5_REG_OFST  _UINT32_(0x4F4)     /* (FUSES_KEYVAL_PRG_PG5) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_PRG_PG6_REG_OFST  _UINT32_(0x4F8)     /* (FUSES_KEYVAL_PRG_PG6) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_PRG_PG7_REG_OFST  _UINT32_(0x4FC)     /* (FUSES_KEYVAL_PRG_PG7) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL1_0_REG_OFST  _UINT32_(0x500)     /* (FUSES_KEYVAL_SDAL1_0) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL1_1_REG_OFST  _UINT32_(0x504)     /* (FUSES_KEYVAL_SDAL1_1) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL1_2_REG_OFST  _UINT32_(0x508)     /* (FUSES_KEYVAL_SDAL1_2) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL1_3_REG_OFST  _UINT32_(0x50C)     /* (FUSES_KEYVAL_SDAL1_3) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL1_4_REG_OFST  _UINT32_(0x510)     /* (FUSES_KEYVAL_SDAL1_4) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL1_5_REG_OFST  _UINT32_(0x514)     /* (FUSES_KEYVAL_SDAL1_5) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL1_6_REG_OFST  _UINT32_(0x518)     /* (FUSES_KEYVAL_SDAL1_6) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL1_7_REG_OFST  _UINT32_(0x51C)     /* (FUSES_KEYVAL_SDAL1_7) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL0_0_REG_OFST  _UINT32_(0x520)     /* (FUSES_KEYVAL_SDAL0_0) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL0_1_REG_OFST  _UINT32_(0x524)     /* (FUSES_KEYVAL_SDAL0_1) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL0_2_REG_OFST  _UINT32_(0x528)     /* (FUSES_KEYVAL_SDAL0_2) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL0_3_REG_OFST  _UINT32_(0x52C)     /* (FUSES_KEYVAL_SDAL0_3) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL0_4_REG_OFST  _UINT32_(0x530)     /* (FUSES_KEYVAL_SDAL0_4) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL0_5_REG_OFST  _UINT32_(0x534)     /* (FUSES_KEYVAL_SDAL0_5) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL0_6_REG_OFST  _UINT32_(0x538)     /* (FUSES_KEYVAL_SDAL0_6) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_SDAL0_7_REG_OFST  _UINT32_(0x53C)     /* (FUSES_KEYVAL_SDAL0_7) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_DAL_EL0_REG_OFST  _UINT32_(0x540)     /* (FUSES_KEYVAL_DAL_EL0) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_DAL_EL1_REG_OFST  _UINT32_(0x544)     /* (FUSES_KEYVAL_DAL_EL1) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_DAL_EL2_REG_OFST  _UINT32_(0x548)     /* (FUSES_KEYVAL_DAL_EL2) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_DAL_EL3_REG_OFST  _UINT32_(0x54C)     /* (FUSES_KEYVAL_DAL_EL3) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_DAL_EL4_REG_OFST  _UINT32_(0x550)     /* (FUSES_KEYVAL_DAL_EL4) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_DAL_EL5_REG_OFST  _UINT32_(0x554)     /* (FUSES_KEYVAL_DAL_EL5) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_DAL_EL6_REG_OFST  _UINT32_(0x558)     /* (FUSES_KEYVAL_DAL_EL6) Mapped Fuse Register Offset */
+#define FUSES_KEYVAL_DAL_EL7_REG_OFST  _UINT32_(0x55C)     /* (FUSES_KEYVAL_DAL_EL7) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC_REG_OFST          _UINT32_(0xC00)     /* (FUSES_PUF_AC) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC0_REG_OFST         _UINT32_(0xC00)     /* (FUSES_PUF_AC0) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC1_REG_OFST         _UINT32_(0xC04)     /* (FUSES_PUF_AC1) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC2_REG_OFST         _UINT32_(0xC08)     /* (FUSES_PUF_AC2) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC3_REG_OFST         _UINT32_(0xC0C)     /* (FUSES_PUF_AC3) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC4_REG_OFST         _UINT32_(0xC10)     /* (FUSES_PUF_AC4) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC5_REG_OFST         _UINT32_(0xC14)     /* (FUSES_PUF_AC5) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC6_REG_OFST         _UINT32_(0xC18)     /* (FUSES_PUF_AC6) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC7_REG_OFST         _UINT32_(0xC1C)     /* (FUSES_PUF_AC7) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC8_REG_OFST         _UINT32_(0xC20)     /* (FUSES_PUF_AC8) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC9_REG_OFST         _UINT32_(0xC24)     /* (FUSES_PUF_AC9) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC10_REG_OFST        _UINT32_(0xC28)     /* (FUSES_PUF_AC10) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC11_REG_OFST        _UINT32_(0xC2C)     /* (FUSES_PUF_AC11) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC12_REG_OFST        _UINT32_(0xC30)     /* (FUSES_PUF_AC12) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC13_REG_OFST        _UINT32_(0xC34)     /* (FUSES_PUF_AC13) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC14_REG_OFST        _UINT32_(0xC38)     /* (FUSES_PUF_AC14) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC15_REG_OFST        _UINT32_(0xC3C)     /* (FUSES_PUF_AC15) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC16_REG_OFST        _UINT32_(0xC40)     /* (FUSES_PUF_AC16) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC17_REG_OFST        _UINT32_(0xC44)     /* (FUSES_PUF_AC17) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC18_REG_OFST        _UINT32_(0xC48)     /* (FUSES_PUF_AC18) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC19_REG_OFST        _UINT32_(0xC4C)     /* (FUSES_PUF_AC19) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC20_REG_OFST        _UINT32_(0xC50)     /* (FUSES_PUF_AC20) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC21_REG_OFST        _UINT32_(0xC54)     /* (FUSES_PUF_AC21) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC22_REG_OFST        _UINT32_(0xC58)     /* (FUSES_PUF_AC22) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC23_REG_OFST        _UINT32_(0xC5C)     /* (FUSES_PUF_AC23) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC24_REG_OFST        _UINT32_(0xC60)     /* (FUSES_PUF_AC24) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC25_REG_OFST        _UINT32_(0xC64)     /* (FUSES_PUF_AC25) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC26_REG_OFST        _UINT32_(0xC68)     /* (FUSES_PUF_AC26) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC27_REG_OFST        _UINT32_(0xC6C)     /* (FUSES_PUF_AC27) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC28_REG_OFST        _UINT32_(0xC70)     /* (FUSES_PUF_AC28) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC29_REG_OFST        _UINT32_(0xC74)     /* (FUSES_PUF_AC29) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC30_REG_OFST        _UINT32_(0xC78)     /* (FUSES_PUF_AC30) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC31_REG_OFST        _UINT32_(0xC7C)     /* (FUSES_PUF_AC31) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC32_REG_OFST        _UINT32_(0xC80)     /* (FUSES_PUF_AC32) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC33_REG_OFST        _UINT32_(0xC84)     /* (FUSES_PUF_AC33) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC34_REG_OFST        _UINT32_(0xC88)     /* (FUSES_PUF_AC34) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC35_REG_OFST        _UINT32_(0xC8C)     /* (FUSES_PUF_AC35) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC36_REG_OFST        _UINT32_(0xC90)     /* (FUSES_PUF_AC36) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC37_REG_OFST        _UINT32_(0xC94)     /* (FUSES_PUF_AC37) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC38_REG_OFST        _UINT32_(0xC98)     /* (FUSES_PUF_AC38) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC39_REG_OFST        _UINT32_(0xC9C)     /* (FUSES_PUF_AC39) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC40_REG_OFST        _UINT32_(0xCA0)     /* (FUSES_PUF_AC40) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC41_REG_OFST        _UINT32_(0xCA4)     /* (FUSES_PUF_AC41) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC42_REG_OFST        _UINT32_(0xCA8)     /* (FUSES_PUF_AC42) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC43_REG_OFST        _UINT32_(0xCAC)     /* (FUSES_PUF_AC43) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC44_REG_OFST        _UINT32_(0xCB0)     /* (FUSES_PUF_AC44) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC45_REG_OFST        _UINT32_(0xCB4)     /* (FUSES_PUF_AC45) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC46_REG_OFST        _UINT32_(0xCB8)     /* (FUSES_PUF_AC46) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC47_REG_OFST        _UINT32_(0xCBC)     /* (FUSES_PUF_AC47) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC48_REG_OFST        _UINT32_(0xCC0)     /* (FUSES_PUF_AC48) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC49_REG_OFST        _UINT32_(0xCC4)     /* (FUSES_PUF_AC49) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC50_REG_OFST        _UINT32_(0xCC8)     /* (FUSES_PUF_AC50) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC51_REG_OFST        _UINT32_(0xCCC)     /* (FUSES_PUF_AC51) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC52_REG_OFST        _UINT32_(0xCD0)     /* (FUSES_PUF_AC52) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC53_REG_OFST        _UINT32_(0xCD4)     /* (FUSES_PUF_AC53) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC54_REG_OFST        _UINT32_(0xCD8)     /* (FUSES_PUF_AC54) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC55_REG_OFST        _UINT32_(0xCDC)     /* (FUSES_PUF_AC55) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC56_REG_OFST        _UINT32_(0xCE0)     /* (FUSES_PUF_AC56) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC57_REG_OFST        _UINT32_(0xCE4)     /* (FUSES_PUF_AC57) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC58_REG_OFST        _UINT32_(0xCE8)     /* (FUSES_PUF_AC58) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC59_REG_OFST        _UINT32_(0xCEC)     /* (FUSES_PUF_AC59) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC60_REG_OFST        _UINT32_(0xCF0)     /* (FUSES_PUF_AC60) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC61_REG_OFST        _UINT32_(0xCF4)     /* (FUSES_PUF_AC61) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC62_REG_OFST        _UINT32_(0xCF8)     /* (FUSES_PUF_AC62) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC63_REG_OFST        _UINT32_(0xCFC)     /* (FUSES_PUF_AC63) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC64_REG_OFST        _UINT32_(0xD00)     /* (FUSES_PUF_AC64) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC65_REG_OFST        _UINT32_(0xD04)     /* (FUSES_PUF_AC65) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC66_REG_OFST        _UINT32_(0xD08)     /* (FUSES_PUF_AC66) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC67_REG_OFST        _UINT32_(0xD0C)     /* (FUSES_PUF_AC67) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC68_REG_OFST        _UINT32_(0xD10)     /* (FUSES_PUF_AC68) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC69_REG_OFST        _UINT32_(0xD14)     /* (FUSES_PUF_AC69) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC70_REG_OFST        _UINT32_(0xD18)     /* (FUSES_PUF_AC70) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC71_REG_OFST        _UINT32_(0xD1C)     /* (FUSES_PUF_AC71) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC72_REG_OFST        _UINT32_(0xD20)     /* (FUSES_PUF_AC72) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC73_REG_OFST        _UINT32_(0xD24)     /* (FUSES_PUF_AC73) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC74_REG_OFST        _UINT32_(0xD28)     /* (FUSES_PUF_AC74) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC75_REG_OFST        _UINT32_(0xD2C)     /* (FUSES_PUF_AC75) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC76_REG_OFST        _UINT32_(0xD30)     /* (FUSES_PUF_AC76) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC77_REG_OFST        _UINT32_(0xD34)     /* (FUSES_PUF_AC77) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC78_REG_OFST        _UINT32_(0xD38)     /* (FUSES_PUF_AC78) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC79_REG_OFST        _UINT32_(0xD3C)     /* (FUSES_PUF_AC79) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC80_REG_OFST        _UINT32_(0xD40)     /* (FUSES_PUF_AC80) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC81_REG_OFST        _UINT32_(0xD44)     /* (FUSES_PUF_AC81) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC82_REG_OFST        _UINT32_(0xD48)     /* (FUSES_PUF_AC82) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC83_REG_OFST        _UINT32_(0xD4C)     /* (FUSES_PUF_AC83) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC84_REG_OFST        _UINT32_(0xD50)     /* (FUSES_PUF_AC84) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC85_REG_OFST        _UINT32_(0xD54)     /* (FUSES_PUF_AC85) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC86_REG_OFST        _UINT32_(0xD58)     /* (FUSES_PUF_AC86) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC87_REG_OFST        _UINT32_(0xD5C)     /* (FUSES_PUF_AC87) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC88_REG_OFST        _UINT32_(0xD60)     /* (FUSES_PUF_AC88) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC89_REG_OFST        _UINT32_(0xD64)     /* (FUSES_PUF_AC89) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC90_REG_OFST        _UINT32_(0xD68)     /* (FUSES_PUF_AC90) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC91_REG_OFST        _UINT32_(0xD6C)     /* (FUSES_PUF_AC91) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC92_REG_OFST        _UINT32_(0xD70)     /* (FUSES_PUF_AC92) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC93_REG_OFST        _UINT32_(0xD74)     /* (FUSES_PUF_AC93) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC94_REG_OFST        _UINT32_(0xD78)     /* (FUSES_PUF_AC94) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC95_REG_OFST        _UINT32_(0xD7C)     /* (FUSES_PUF_AC95) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC96_REG_OFST        _UINT32_(0xD80)     /* (FUSES_PUF_AC96) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC97_REG_OFST        _UINT32_(0xD84)     /* (FUSES_PUF_AC97) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC98_REG_OFST        _UINT32_(0xD88)     /* (FUSES_PUF_AC98) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC99_REG_OFST        _UINT32_(0xD8C)     /* (FUSES_PUF_AC99) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC100_REG_OFST       _UINT32_(0xD90)     /* (FUSES_PUF_AC100) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC101_REG_OFST       _UINT32_(0xD94)     /* (FUSES_PUF_AC101) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC102_REG_OFST       _UINT32_(0xD98)     /* (FUSES_PUF_AC102) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC103_REG_OFST       _UINT32_(0xD9C)     /* (FUSES_PUF_AC103) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC104_REG_OFST       _UINT32_(0xDA0)     /* (FUSES_PUF_AC104) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC105_REG_OFST       _UINT32_(0xDA4)     /* (FUSES_PUF_AC105) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC106_REG_OFST       _UINT32_(0xDA8)     /* (FUSES_PUF_AC106) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC107_REG_OFST       _UINT32_(0xDAC)     /* (FUSES_PUF_AC107) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC108_REG_OFST       _UINT32_(0xDB0)     /* (FUSES_PUF_AC108) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC109_REG_OFST       _UINT32_(0xDB4)     /* (FUSES_PUF_AC109) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC110_REG_OFST       _UINT32_(0xDB8)     /* (FUSES_PUF_AC110) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC111_REG_OFST       _UINT32_(0xDBC)     /* (FUSES_PUF_AC111) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC112_REG_OFST       _UINT32_(0xDC0)     /* (FUSES_PUF_AC112) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC113_REG_OFST       _UINT32_(0xDC4)     /* (FUSES_PUF_AC113) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC114_REG_OFST       _UINT32_(0xDC8)     /* (FUSES_PUF_AC114) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC115_REG_OFST       _UINT32_(0xDCC)     /* (FUSES_PUF_AC115) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC116_REG_OFST       _UINT32_(0xDD0)     /* (FUSES_PUF_AC116) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC117_REG_OFST       _UINT32_(0xDD4)     /* (FUSES_PUF_AC117) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC118_REG_OFST       _UINT32_(0xDD8)     /* (FUSES_PUF_AC118) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC119_REG_OFST       _UINT32_(0xDDC)     /* (FUSES_PUF_AC119) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC120_REG_OFST       _UINT32_(0xDE0)     /* (FUSES_PUF_AC120) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC121_REG_OFST       _UINT32_(0xDE4)     /* (FUSES_PUF_AC121) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC122_REG_OFST       _UINT32_(0xDE8)     /* (FUSES_PUF_AC122) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC123_REG_OFST       _UINT32_(0xDEC)     /* (FUSES_PUF_AC123) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC124_REG_OFST       _UINT32_(0xDF0)     /* (FUSES_PUF_AC124) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC125_REG_OFST       _UINT32_(0xDF4)     /* (FUSES_PUF_AC125) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC126_REG_OFST       _UINT32_(0xDF8)     /* (FUSES_PUF_AC126) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC127_REG_OFST       _UINT32_(0xDFC)     /* (FUSES_PUF_AC127) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC128_REG_OFST       _UINT32_(0xE00)     /* (FUSES_PUF_AC128) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC129_REG_OFST       _UINT32_(0xE04)     /* (FUSES_PUF_AC129) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC130_REG_OFST       _UINT32_(0xE08)     /* (FUSES_PUF_AC130) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC131_REG_OFST       _UINT32_(0xE0C)     /* (FUSES_PUF_AC131) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC132_REG_OFST       _UINT32_(0xE10)     /* (FUSES_PUF_AC132) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC133_REG_OFST       _UINT32_(0xE14)     /* (FUSES_PUF_AC133) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC134_REG_OFST       _UINT32_(0xE18)     /* (FUSES_PUF_AC134) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC135_REG_OFST       _UINT32_(0xE1C)     /* (FUSES_PUF_AC135) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC136_REG_OFST       _UINT32_(0xE20)     /* (FUSES_PUF_AC136) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC137_REG_OFST       _UINT32_(0xE24)     /* (FUSES_PUF_AC137) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC138_REG_OFST       _UINT32_(0xE28)     /* (FUSES_PUF_AC138) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC139_REG_OFST       _UINT32_(0xE2C)     /* (FUSES_PUF_AC139) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC140_REG_OFST       _UINT32_(0xE30)     /* (FUSES_PUF_AC140) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC141_REG_OFST       _UINT32_(0xE34)     /* (FUSES_PUF_AC141) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC142_REG_OFST       _UINT32_(0xE38)     /* (FUSES_PUF_AC142) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC143_REG_OFST       _UINT32_(0xE3C)     /* (FUSES_PUF_AC143) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC144_REG_OFST       _UINT32_(0xE40)     /* (FUSES_PUF_AC144) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC145_REG_OFST       _UINT32_(0xE44)     /* (FUSES_PUF_AC145) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC146_REG_OFST       _UINT32_(0xE48)     /* (FUSES_PUF_AC146) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC147_REG_OFST       _UINT32_(0xE4C)     /* (FUSES_PUF_AC147) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC148_REG_OFST       _UINT32_(0xE50)     /* (FUSES_PUF_AC148) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC149_REG_OFST       _UINT32_(0xE54)     /* (FUSES_PUF_AC149) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC150_REG_OFST       _UINT32_(0xE58)     /* (FUSES_PUF_AC150) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC151_REG_OFST       _UINT32_(0xE5C)     /* (FUSES_PUF_AC151) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC152_REG_OFST       _UINT32_(0xE60)     /* (FUSES_PUF_AC152) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC153_REG_OFST       _UINT32_(0xE64)     /* (FUSES_PUF_AC153) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC154_REG_OFST       _UINT32_(0xE68)     /* (FUSES_PUF_AC154) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC155_REG_OFST       _UINT32_(0xE6C)     /* (FUSES_PUF_AC155) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC156_REG_OFST       _UINT32_(0xE70)     /* (FUSES_PUF_AC156) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC157_REG_OFST       _UINT32_(0xE74)     /* (FUSES_PUF_AC157) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC158_REG_OFST       _UINT32_(0xE78)     /* (FUSES_PUF_AC158) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC159_REG_OFST       _UINT32_(0xE7C)     /* (FUSES_PUF_AC159) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC160_REG_OFST       _UINT32_(0xE80)     /* (FUSES_PUF_AC160) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC161_REG_OFST       _UINT32_(0xE84)     /* (FUSES_PUF_AC161) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC162_REG_OFST       _UINT32_(0xE88)     /* (FUSES_PUF_AC162) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC163_REG_OFST       _UINT32_(0xE8C)     /* (FUSES_PUF_AC163) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC164_REG_OFST       _UINT32_(0xE90)     /* (FUSES_PUF_AC164) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC165_REG_OFST       _UINT32_(0xE94)     /* (FUSES_PUF_AC165) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC166_REG_OFST       _UINT32_(0xE98)     /* (FUSES_PUF_AC166) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC167_REG_OFST       _UINT32_(0xE9C)     /* (FUSES_PUF_AC167) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC168_REG_OFST       _UINT32_(0xEA0)     /* (FUSES_PUF_AC168) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC169_REG_OFST       _UINT32_(0xEA4)     /* (FUSES_PUF_AC169) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC170_REG_OFST       _UINT32_(0xEA8)     /* (FUSES_PUF_AC170) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC171_REG_OFST       _UINT32_(0xEAC)     /* (FUSES_PUF_AC171) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC172_REG_OFST       _UINT32_(0xEB0)     /* (FUSES_PUF_AC172) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC173_REG_OFST       _UINT32_(0xEB4)     /* (FUSES_PUF_AC173) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC174_REG_OFST       _UINT32_(0xEB8)     /* (FUSES_PUF_AC174) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC175_REG_OFST       _UINT32_(0xEBC)     /* (FUSES_PUF_AC175) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC176_REG_OFST       _UINT32_(0xEC0)     /* (FUSES_PUF_AC176) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC177_REG_OFST       _UINT32_(0xEC4)     /* (FUSES_PUF_AC177) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC178_REG_OFST       _UINT32_(0xEC8)     /* (FUSES_PUF_AC178) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC179_REG_OFST       _UINT32_(0xECC)     /* (FUSES_PUF_AC179) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC180_REG_OFST       _UINT32_(0xED0)     /* (FUSES_PUF_AC180) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC181_REG_OFST       _UINT32_(0xED4)     /* (FUSES_PUF_AC181) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC182_REG_OFST       _UINT32_(0xED8)     /* (FUSES_PUF_AC182) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC183_REG_OFST       _UINT32_(0xEDC)     /* (FUSES_PUF_AC183) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC184_REG_OFST       _UINT32_(0xEE0)     /* (FUSES_PUF_AC184) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC185_REG_OFST       _UINT32_(0xEE4)     /* (FUSES_PUF_AC185) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC186_REG_OFST       _UINT32_(0xEE8)     /* (FUSES_PUF_AC186) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC187_REG_OFST       _UINT32_(0xEEC)     /* (FUSES_PUF_AC187) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC188_REG_OFST       _UINT32_(0xEF0)     /* (FUSES_PUF_AC188) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC189_REG_OFST       _UINT32_(0xEF4)     /* (FUSES_PUF_AC189) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC190_REG_OFST       _UINT32_(0xEF8)     /* (FUSES_PUF_AC190) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC191_REG_OFST       _UINT32_(0xEFC)     /* (FUSES_PUF_AC191) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC192_REG_OFST       _UINT32_(0xF00)     /* (FUSES_PUF_AC192) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC193_REG_OFST       _UINT32_(0xF04)     /* (FUSES_PUF_AC193) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC194_REG_OFST       _UINT32_(0xF08)     /* (FUSES_PUF_AC194) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC195_REG_OFST       _UINT32_(0xF0C)     /* (FUSES_PUF_AC195) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC196_REG_OFST       _UINT32_(0xF10)     /* (FUSES_PUF_AC196) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC197_REG_OFST       _UINT32_(0xF14)     /* (FUSES_PUF_AC197) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC198_REG_OFST       _UINT32_(0xF18)     /* (FUSES_PUF_AC198) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC199_REG_OFST       _UINT32_(0xF1C)     /* (FUSES_PUF_AC199) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC200_REG_OFST       _UINT32_(0xF20)     /* (FUSES_PUF_AC200) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC201_REG_OFST       _UINT32_(0xF24)     /* (FUSES_PUF_AC201) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC202_REG_OFST       _UINT32_(0xF28)     /* (FUSES_PUF_AC202) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC203_REG_OFST       _UINT32_(0xF2C)     /* (FUSES_PUF_AC203) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC204_REG_OFST       _UINT32_(0xF30)     /* (FUSES_PUF_AC204) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC205_REG_OFST       _UINT32_(0xF34)     /* (FUSES_PUF_AC205) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC206_REG_OFST       _UINT32_(0xF38)     /* (FUSES_PUF_AC206) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC207_REG_OFST       _UINT32_(0xF3C)     /* (FUSES_PUF_AC207) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC208_REG_OFST       _UINT32_(0xF40)     /* (FUSES_PUF_AC208) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC209_REG_OFST       _UINT32_(0xF44)     /* (FUSES_PUF_AC209) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC210_REG_OFST       _UINT32_(0xF48)     /* (FUSES_PUF_AC210) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC211_REG_OFST       _UINT32_(0xF4C)     /* (FUSES_PUF_AC211) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC212_REG_OFST       _UINT32_(0xF50)     /* (FUSES_PUF_AC212) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC213_REG_OFST       _UINT32_(0xF54)     /* (FUSES_PUF_AC213) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC214_REG_OFST       _UINT32_(0xF58)     /* (FUSES_PUF_AC214) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC215_REG_OFST       _UINT32_(0xF5C)     /* (FUSES_PUF_AC215) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC216_REG_OFST       _UINT32_(0xF60)     /* (FUSES_PUF_AC216) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC217_REG_OFST       _UINT32_(0xF64)     /* (FUSES_PUF_AC217) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC218_REG_OFST       _UINT32_(0xF68)     /* (FUSES_PUF_AC218) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC219_REG_OFST       _UINT32_(0xF6C)     /* (FUSES_PUF_AC219) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC220_REG_OFST       _UINT32_(0xF70)     /* (FUSES_PUF_AC220) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC221_REG_OFST       _UINT32_(0xF74)     /* (FUSES_PUF_AC221) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC222_REG_OFST       _UINT32_(0xF78)     /* (FUSES_PUF_AC222) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC223_REG_OFST       _UINT32_(0xF7C)     /* (FUSES_PUF_AC223) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC224_REG_OFST       _UINT32_(0xF80)     /* (FUSES_PUF_AC224) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC225_REG_OFST       _UINT32_(0xF84)     /* (FUSES_PUF_AC225) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC226_REG_OFST       _UINT32_(0xF88)     /* (FUSES_PUF_AC226) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC227_REG_OFST       _UINT32_(0xF8C)     /* (FUSES_PUF_AC227) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC228_REG_OFST       _UINT32_(0xF90)     /* (FUSES_PUF_AC228) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC229_REG_OFST       _UINT32_(0xF94)     /* (FUSES_PUF_AC229) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC230_REG_OFST       _UINT32_(0xF98)     /* (FUSES_PUF_AC230) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC231_REG_OFST       _UINT32_(0xF9C)     /* (FUSES_PUF_AC231) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC232_REG_OFST       _UINT32_(0xFA0)     /* (FUSES_PUF_AC232) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC233_REG_OFST       _UINT32_(0xFA4)     /* (FUSES_PUF_AC233) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC234_REG_OFST       _UINT32_(0xFA8)     /* (FUSES_PUF_AC234) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC235_REG_OFST       _UINT32_(0xFAC)     /* (FUSES_PUF_AC235) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC236_REG_OFST       _UINT32_(0xFB0)     /* (FUSES_PUF_AC236) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC237_REG_OFST       _UINT32_(0xFB4)     /* (FUSES_PUF_AC237) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC238_REG_OFST       _UINT32_(0xFB8)     /* (FUSES_PUF_AC238) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC239_REG_OFST       _UINT32_(0xFBC)     /* (FUSES_PUF_AC239) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC240_REG_OFST       _UINT32_(0xFC0)     /* (FUSES_PUF_AC240) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC241_REG_OFST       _UINT32_(0xFC4)     /* (FUSES_PUF_AC241) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC242_REG_OFST       _UINT32_(0xFC8)     /* (FUSES_PUF_AC242) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC243_REG_OFST       _UINT32_(0xFCC)     /* (FUSES_PUF_AC243) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC244_REG_OFST       _UINT32_(0xFD0)     /* (FUSES_PUF_AC244) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC245_REG_OFST       _UINT32_(0xFD4)     /* (FUSES_PUF_AC245) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC246_REG_OFST       _UINT32_(0xFD8)     /* (FUSES_PUF_AC246) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC247_REG_OFST       _UINT32_(0xFDC)     /* (FUSES_PUF_AC247) Mapped Fuse Register Offset */
+#define FUSES_PUF_AC248_REG_OFST       _UINT32_(0xFE0)     /* (FUSES_PUF_AC248) Mapped Fuse Register Offset */
+#define FUSES_DEVSIGN_REG_OFST         _UINT32_(0x0C)      /* (FUSES_DEVSIGN) DEVSIGN Offset */
+#define FUSES_BOOT_FLAG_REG_OFST       _UINT32_(0x800)     /* (FUSES_BOOT_FLAG) BOOT CODE FLAGS REGISTER Offset */
+#define FUSES_DICE_CDI_INDEX_REG_OFST  _UINT32_(0x810)     /* (FUSES_DICE_CDI_INDEX) Mapped Fuse Register Offset */
+#define FUSES_DICE_FW_HASH_INDEX_REG_OFST _UINT32_(0x814)     /* (FUSES_DICE_FW_HASH_INDEX) Mapped Fuse Register Offset */
+#define FUSES_BOOT_GPIOSEL_REG_OFST    _UINT32_(0x818)     /* (FUSES_BOOT_GPIOSEL) BOOT EXTERNAL NOTIFICATION IO PIN REGISTER Offset */
+#define FUSES_H2PB0_NONSECCLRA_REG_OFST _UINT32_(0x81C)     /* (FUSES_H2PB0_NONSECCLRA) Non-Security Clear Register A Offset */
+#define FUSES_H2PB0_NONSECSETA_REG_OFST _UINT32_(0x820)     /* (FUSES_H2PB0_NONSECSETA) Non-Security SET Register A Offset */
+#define FUSES_PAC_WRCTRL_H2PB0_REG_OFST _UINT32_(0x830)     /* (FUSES_PAC_WRCTRL_H2PB0) Write Control Register Offset */
+#define FUSES_H2PB1_NONSECCLRA_REG_OFST _UINT32_(0x834)     /* (FUSES_H2PB1_NONSECCLRA) Non-Security Clear Register A Offset */
+#define FUSES_H2PB1_NONSECSETA_REG_OFST _UINT32_(0x838)     /* (FUSES_H2PB1_NONSECSETA) Non-Security SET Register A Offset */
+#define FUSES_PAC_WRCTRL_H2PB1_REG_OFST _UINT32_(0x848)     /* (FUSES_PAC_WRCTRL_H2PB1) Write Control Register Offset */
+#define FUSES_H2PB2_NONSECCLRA_REG_OFST _UINT32_(0x84C)     /* (FUSES_H2PB2_NONSECCLRA) Non-Security Clear Register A Offset */
+#define FUSES_H2PB2_NONSECSETA_REG_OFST _UINT32_(0x850)     /* (FUSES_H2PB2_NONSECSETA) Non-Security SET Register A Offset */
+#define FUSES_PAC_WRCTRL_H2PB2_REG_OFST _UINT32_(0x860)     /* (FUSES_PAC_WRCTRL_H2PB2) Write Control Register Offset */
+#define FUSES_IDAU_RCTRL_BFM_REG_OFST  _UINT32_(0x864)     /* (FUSES_IDAU_RCTRL_BFM) Region Control Offset */
+#define FUSES_IDAU_RCTRL_PFMANS_REG_OFST _UINT32_(0x868)     /* (FUSES_IDAU_RCTRL_PFMANS) Region Control Offset */
+#define FUSES_IDAU_RCTRL_PFMANSC_REG_OFST _UINT32_(0x86C)     /* (FUSES_IDAU_RCTRL_PFMANSC) Region Control Offset */
+#define FUSES_IDAU_RCTRL_DRM_REG_OFST  _UINT32_(0x870)     /* (FUSES_IDAU_RCTRL_DRM) Region Control Offset */
+#define FUSES_IDAU_CTRL_EN_REG_OFST    _UINT32_(0x874)     /* (FUSES_IDAU_CTRL_EN) Control Offset */
+#define FUSES_IDAU_CTRL_WLCK_REG_OFST  _UINT32_(0x878)     /* (FUSES_IDAU_CTRL_WLCK) Control Offset */
+#define FUSES_FCW_CWP_REG_OFST         _UINT32_(0x87C)     /* (FUSES_FCW_CWP) CFM Page Write Protect REGISTER Offset */
+#define FUSES_FCR_CRP_REG_OFST         _UINT32_(0x880)     /* (FUSES_FCR_CRP) CFM Page Read Protection Register Offset */
+#define FUSES_FCR_ECCCTRL_REG_OFST     _UINT32_(0x884)     /* (FUSES_FCR_ECCCTRL) ECC Control REGISTER Offset */
+#define FUSES_SUPC_BRCFGUSMOR_BOR_REG_OFST _UINT32_(0x888)     /* (FUSES_SUPC_BRCFGUSMOR_BOR) Boot Rom Configurable SMOR User CFG BOR register Offset */
+#define FUSES_SUPC_BRCFGUDSSMOR_REG_OFST _UINT32_(0x890)     /* (FUSES_SUPC_BRCFGUDSSMOR) Boot Rom Configurable DSSMOR User CFG register Offset */
+#define FUSES_SUPC_BRCFGUCP0_REG_OFST  _UINT32_(0x894)     /* (FUSES_SUPC_BRCFGUCP0) Boot Rom Configurable CHARGE PUMP User CFG register Offset */
+#define FUSES_WDT_SETUP_REG_OFST       _UINT32_(0x898)     /* (FUSES_WDT_SETUP)  Offset */
+#define FUSES_F1RR_REG_OFST            _UINT32_(0x00)      /* (FUSES_F1RR) PANEL 0 REDUNDANCY RECORD 1-0 Register Offset */
+#define FUSES_FCCFG0_REG_OFST          _UINT32_(0x80)      /* (FUSES_FCCFG0) Calibration Configuration 0 Register Offset */
+#define FUSES_FCCFG1_REG_OFST          _UINT32_(0x84)      /* (FUSES_FCCFG1) Calibration Configuration 1 Register Offset */
+#define FUSES_FCCFG8_REG_OFST          _UINT32_(0xA0)      /* (FUSES_FCCFG8) Calibration Configuration 8 Register Offset */
+#define FUSES_FCCFG16_REG_OFST         _UINT32_(0xC0)      /* (FUSES_FCCFG16) Calibration Configuration 16 Register Offset */
+#define FUSES_FCCFG17_REG_OFST         _UINT32_(0xC4)      /* (FUSES_FCCFG17) Calibration Configuration 17 Register Offset */
+#define FUSES_FCCFG24_REG_OFST         _UINT32_(0xE0)      /* (FUSES_FCCFG24) Calibration Configuration 24 Register Offset */
+#define FUSES_FCCFG27_REG_OFST         _UINT32_(0xEC)      /* (FUSES_FCCFG27) Calibration Configuration 27 Register Offset */
+#define FUSES_FCCFG28_REG_OFST         _UINT32_(0xF0)      /* (FUSES_FCCFG28) Calibration Configuration 28 Register Offset */
+#define FUSES_FCCFG29_REG_OFST         _UINT32_(0xF4)      /* (FUSES_FCCFG29) Calibration Configuration 29 Register Offset */
+#define FUSES_FCCFG32_REG_OFST         _UINT32_(0x100)     /* (FUSES_FCCFG32) DSU Device Configuration 0 Register (DEVID) Offset */
+#define FUSES_FCCFG33_REG_OFST         _UINT32_(0x104)     /* (FUSES_FCCFG33) DSU Device Configuration 1 Register Offset */
+#define FUSES_FCCFG34_REG_OFST         _UINT32_(0x108)     /* (FUSES_FCCFG34) DSU Device Configuration 2 Register Offset */
+#define FUSES_FCCFG49_REG_OFST         _UINT32_(0x144)     /* (FUSES_FCCFG49) Calibration Configuration 49 Register Offset */
+#define FUSES_FCCFG56_REG_OFST         _UINT32_(0x160)     /* (FUSES_FCCFG56) Calibration Configuration 56 Register Offset */
+#define FUSES_FCCFG57_REG_OFST         _UINT32_(0x164)     /* (FUSES_FCCFG57) Calibration Configuration 57 Register Offset */
+#define FUSES_FCCFG58_REG_OFST         _UINT32_(0x168)     /* (FUSES_FCCFG58) Calibration Configuration 58 Register Offset */
+#define FUSES_FCCFG59_REG_OFST         _UINT32_(0x16C)     /* (FUSES_FCCFG59) Calibration Configuration 59 Register Offset */
+#define FUSES_FCCFG60_REG_OFST         _UINT32_(0x170)     /* (FUSES_FCCFG60) Calibration Configuration 60 Register Offset */
+#define FUSES_FCCFG61_REG_OFST         _UINT32_(0x174)     /* (FUSES_FCCFG61) Calibration Configuration 61 Register Offset */
+#define FUSES_FCCFG64_REG_OFST         _UINT32_(0x180)     /* (FUSES_FCCFG64) Calibration Configuration 64 Register Offset */
+#define FUSES_FCCFG65_REG_OFST         _UINT32_(0x184)     /* (FUSES_FCCFG65) Calibration Configuration 65 Register Offset */
+#define FUSES_FCCFG66_REG_OFST         _UINT32_(0x188)     /* (FUSES_FCCFG66) Calibration Configuration 66 Register Offset */
+#define FUSES_FCCFG68_REG_OFST         _UINT32_(0x190)     /* (FUSES_FCCFG68) Calibration Configuration 68 Register Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* FUSES_ROMCFG register API structure */
+typedef struct
+{  /* Defines FUSES module data */
+  __IO  uint32_t                       FUSES_DAL;          /* Offset: 0x00 (R/W  32) DEVICE ACCESS LEVEL Register */
+  __I   uint8_t                        Reserved1[0x3FC];
+  __IO  uint32_t                       FUSES_FRCFGBROM;    /* Offset: 0x400 (R/W  32) PRE-BOOT bromc user Options Register */
+  __I   uint8_t                        Reserved2[0x04];
+  __IO  uint32_t                       FUSES_FRCFGMBIST;   /* Offset: 0x408 (R/W  32) PRE-BOOT MBIST user Options Register */
+  __I   uint8_t                        Reserved3[0x14];
+  __IO  uint32_t                       FUSES_KEYVAL_INTCHK0; /* Offset: 0x420 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_INTCHK1; /* Offset: 0x424 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_INTCHK2; /* Offset: 0x428 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_INTCHK3; /* Offset: 0x42C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_INTCHK4; /* Offset: 0x430 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_INTCHK5; /* Offset: 0x434 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_INTCHK6; /* Offset: 0x438 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_INTCHK7; /* Offset: 0x43C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_ALL0; /* Offset: 0x440 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_ALL1; /* Offset: 0x444 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_ALL2; /* Offset: 0x448 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_ALL3; /* Offset: 0x44C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_ALL4; /* Offset: 0x450 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_ALL5; /* Offset: 0x454 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_ALL6; /* Offset: 0x458 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_ALL7; /* Offset: 0x45C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S_CR0; /* Offset: 0x460 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S_CR1; /* Offset: 0x464 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S_CR2; /* Offset: 0x468 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S_CR3; /* Offset: 0x46C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S_CR4; /* Offset: 0x470 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S_CR5; /* Offset: 0x474 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S_CR6; /* Offset: 0x478 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S_CR7; /* Offset: 0x47C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S0; /* Offset: 0x480 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S1; /* Offset: 0x484 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S2; /* Offset: 0x488 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S3; /* Offset: 0x48C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S4; /* Offset: 0x490 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S5; /* Offset: 0x494 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S6; /* Offset: 0x498 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_S7; /* Offset: 0x49C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS_CR0; /* Offset: 0x4A0 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS_CR1; /* Offset: 0x4A4 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS_CR2; /* Offset: 0x4A8 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS_CR3; /* Offset: 0x4AC (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS_CR4; /* Offset: 0x4B0 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS_CR5; /* Offset: 0x4B4 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS_CR6; /* Offset: 0x4B8 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS_CR7; /* Offset: 0x4BC (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS0; /* Offset: 0x4C0 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS1; /* Offset: 0x4C4 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS2; /* Offset: 0x4C8 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS3; /* Offset: 0x4CC (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS4; /* Offset: 0x4D0 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS5; /* Offset: 0x4D4 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS6; /* Offset: 0x4D8 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_CE_NS7; /* Offset: 0x4DC (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_PRG_PG0; /* Offset: 0x4E0 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_PRG_PG1; /* Offset: 0x4E4 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_PRG_PG2; /* Offset: 0x4E8 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_PRG_PG3; /* Offset: 0x4EC (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_PRG_PG4; /* Offset: 0x4F0 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_PRG_PG5; /* Offset: 0x4F4 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_PRG_PG6; /* Offset: 0x4F8 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_PRG_PG7; /* Offset: 0x4FC (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL1_0; /* Offset: 0x500 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL1_1; /* Offset: 0x504 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL1_2; /* Offset: 0x508 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL1_3; /* Offset: 0x50C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL1_4; /* Offset: 0x510 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL1_5; /* Offset: 0x514 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL1_6; /* Offset: 0x518 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL1_7; /* Offset: 0x51C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL0_0; /* Offset: 0x520 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL0_1; /* Offset: 0x524 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL0_2; /* Offset: 0x528 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL0_3; /* Offset: 0x52C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL0_4; /* Offset: 0x530 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL0_5; /* Offset: 0x534 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL0_6; /* Offset: 0x538 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_SDAL0_7; /* Offset: 0x53C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_DAL_EL0; /* Offset: 0x540 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_DAL_EL1; /* Offset: 0x544 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_DAL_EL2; /* Offset: 0x548 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_DAL_EL3; /* Offset: 0x54C (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_DAL_EL4; /* Offset: 0x550 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_DAL_EL5; /* Offset: 0x554 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_DAL_EL6; /* Offset: 0x558 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_KEYVAL_DAL_EL7; /* Offset: 0x55C (R/W  32) Mapped Fuse Register */
+  __I   uint8_t                        Reserved4[0x6A0];
+  __IO  uint32_t                       FUSES_PUF_AC[249];  /* Offset: 0xC00 (R/W  32) Mapped Fuse Register */
+} fuses_romcfg_registers_t;
+
+/* FUSES_BOOTCFG1 register API structure */
+typedef struct
+{  /* Defines FUSES module data */
+  __I   uint8_t                        Reserved1[0x0C];
+  __IO  uint32_t                       FUSES_DEVSIGN;      /* Offset: 0x0C (R/W  32) DEVSIGN */
+  __I   uint8_t                        Reserved2[0x7F0];
+  __IO  uint32_t                       FUSES_BOOT_FLAG;    /* Offset: 0x800 (R/W  32) BOOT CODE FLAGS REGISTER */
+  __I   uint8_t                        Reserved3[0x0C];
+  __IO  uint32_t                       FUSES_DICE_CDI_INDEX; /* Offset: 0x810 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_DICE_FW_HASH_INDEX; /* Offset: 0x814 (R/W  32) Mapped Fuse Register */
+  __IO  uint32_t                       FUSES_BOOT_GPIOSEL; /* Offset: 0x818 (R/W  32) BOOT EXTERNAL NOTIFICATION IO PIN REGISTER */
+  __IO  uint32_t                       FUSES_H2PB0_NONSECCLRA; /* Offset: 0x81C (R/W  32) Non-Security Clear Register A */
+  __IO  uint32_t                       FUSES_H2PB0_NONSECSETA; /* Offset: 0x820 (R/W  32) Non-Security SET Register A */
+  __I   uint8_t                        Reserved4[0x0C];
+  __IO  uint32_t                       FUSES_PAC_WRCTRL_H2PB0; /* Offset: 0x830 (R/W  32) Write Control Register */
+  __IO  uint32_t                       FUSES_H2PB1_NONSECCLRA; /* Offset: 0x834 (R/W  32) Non-Security Clear Register A */
+  __IO  uint32_t                       FUSES_H2PB1_NONSECSETA; /* Offset: 0x838 (R/W  32) Non-Security SET Register A */
+  __I   uint8_t                        Reserved5[0x0C];
+  __IO  uint32_t                       FUSES_PAC_WRCTRL_H2PB1; /* Offset: 0x848 (R/W  32) Write Control Register */
+  __IO  uint32_t                       FUSES_H2PB2_NONSECCLRA; /* Offset: 0x84C (R/W  32) Non-Security Clear Register A */
+  __IO  uint32_t                       FUSES_H2PB2_NONSECSETA; /* Offset: 0x850 (R/W  32) Non-Security SET Register A */
+  __I   uint8_t                        Reserved6[0x0C];
+  __IO  uint32_t                       FUSES_PAC_WRCTRL_H2PB2; /* Offset: 0x860 (R/W  32) Write Control Register */
+  __IO  uint32_t                       FUSES_IDAU_RCTRL_BFM; /* Offset: 0x864 (R/W  32) Region Control */
+  __IO  uint32_t                       FUSES_IDAU_RCTRL_PFMANS; /* Offset: 0x868 (R/W  32) Region Control */
+  __IO  uint32_t                       FUSES_IDAU_RCTRL_PFMANSC; /* Offset: 0x86C (R/W  32) Region Control */
+  __IO  uint32_t                       FUSES_IDAU_RCTRL_DRM; /* Offset: 0x870 (R/W  32) Region Control */
+  __IO  uint32_t                       FUSES_IDAU_CTRL_EN; /* Offset: 0x874 (R/W  32) Control */
+  __IO  uint32_t                       FUSES_IDAU_CTRL_WLCK; /* Offset: 0x878 (R/W  32) Control */
+  __IO  uint32_t                       FUSES_FCW_CWP;      /* Offset: 0x87C (R/W  32) CFM Page Write Protect REGISTER */
+  __IO  uint32_t                       FUSES_FCR_CRP;      /* Offset: 0x880 (R/W  32) CFM Page Read Protection Register */
+  __IO  uint32_t                       FUSES_FCR_ECCCTRL;  /* Offset: 0x884 (R/W  32) ECC Control REGISTER */
+  __IO  uint32_t                       FUSES_SUPC_BRCFGUSMOR_BOR; /* Offset: 0x888 (R/W  32) Boot Rom Configurable SMOR User CFG BOR register */
+  __I   uint8_t                        Reserved7[0x04];
+  __IO  uint32_t                       FUSES_SUPC_BRCFGUDSSMOR; /* Offset: 0x890 (R/W  32) Boot Rom Configurable DSSMOR User CFG register */
+  __IO  uint32_t                       FUSES_SUPC_BRCFGUCP0; /* Offset: 0x894 (R/W  32) Boot Rom Configurable CHARGE PUMP User CFG register */
+  __IO  uint32_t                       FUSES_WDT_SETUP;    /* Offset: 0x898 (R/W  32)  */
+} fuses_bootcfg1_registers_t;
+
+/* FUSES_CALOTP register API structure */
+typedef struct
+{  /* Defines FUSES module data */
+  __I   uint32_t                       FUSES_F1RR;         /* Offset: 0x00 (R/   32) PANEL 0 REDUNDANCY RECORD 1-0 Register */
+  __I   uint8_t                        Reserved1[0x7C];
+  __I   uint32_t                       FUSES_FCCFG0;       /* Offset: 0x80 (R/   32) Calibration Configuration 0 Register */
+  __I   uint32_t                       FUSES_FCCFG1;       /* Offset: 0x84 (R/   32) Calibration Configuration 1 Register */
+  __I   uint8_t                        Reserved2[0x18];
+  __I   uint32_t                       FUSES_FCCFG8;       /* Offset: 0xA0 (R/   32) Calibration Configuration 8 Register */
+  __I   uint8_t                        Reserved3[0x1C];
+  __I   uint32_t                       FUSES_FCCFG16;      /* Offset: 0xC0 (R/   32) Calibration Configuration 16 Register */
+  __I   uint32_t                       FUSES_FCCFG17;      /* Offset: 0xC4 (R/   32) Calibration Configuration 17 Register */
+  __I   uint8_t                        Reserved4[0x18];
+  __I   uint32_t                       FUSES_FCCFG24;      /* Offset: 0xE0 (R/   32) Calibration Configuration 24 Register */
+  __I   uint8_t                        Reserved5[0x08];
+  __I   uint32_t                       FUSES_FCCFG27;      /* Offset: 0xEC (R/   32) Calibration Configuration 27 Register */
+  __I   uint32_t                       FUSES_FCCFG28;      /* Offset: 0xF0 (R/   32) Calibration Configuration 28 Register */
+  __I   uint32_t                       FUSES_FCCFG29;      /* Offset: 0xF4 (R/   32) Calibration Configuration 29 Register */
+  __I   uint8_t                        Reserved6[0x08];
+  __I   uint32_t                       FUSES_FCCFG32;      /* Offset: 0x100 (R/   32) DSU Device Configuration 0 Register (DEVID) */
+  __I   uint32_t                       FUSES_FCCFG33;      /* Offset: 0x104 (R/   32) DSU Device Configuration 1 Register */
+  __I   uint32_t                       FUSES_FCCFG34;      /* Offset: 0x108 (R/   32) DSU Device Configuration 2 Register */
+  __I   uint8_t                        Reserved7[0x38];
+  __I   uint32_t                       FUSES_FCCFG49;      /* Offset: 0x144 (R/   32) Calibration Configuration 49 Register */
+  __I   uint8_t                        Reserved8[0x18];
+  __I   uint32_t                       FUSES_FCCFG56;      /* Offset: 0x160 (R/   32) Calibration Configuration 56 Register */
+  __I   uint32_t                       FUSES_FCCFG57;      /* Offset: 0x164 (R/   32) Calibration Configuration 57 Register */
+  __I   uint32_t                       FUSES_FCCFG58;      /* Offset: 0x168 (R/   32) Calibration Configuration 58 Register */
+  __I   uint32_t                       FUSES_FCCFG59;      /* Offset: 0x16C (R/   32) Calibration Configuration 59 Register */
+  __I   uint32_t                       FUSES_FCCFG60;      /* Offset: 0x170 (R/   32) Calibration Configuration 60 Register */
+  __I   uint32_t                       FUSES_FCCFG61;      /* Offset: 0x174 (R/   32) Calibration Configuration 61 Register */
+  __I   uint8_t                        Reserved9[0x08];
+  __I   uint32_t                       FUSES_FCCFG64;      /* Offset: 0x180 (R/   32) Calibration Configuration 64 Register */
+  __I   uint32_t                       FUSES_FCCFG65;      /* Offset: 0x184 (R/   32) Calibration Configuration 65 Register */
+  __I   uint32_t                       FUSES_FCCFG66;      /* Offset: 0x188 (R/   32) Calibration Configuration 66 Register */
+  __I   uint8_t                        Reserved10[0x04];
+  __I   uint32_t                       FUSES_FCCFG68;      /* Offset: 0x190 (R/   32) Calibration Configuration 68 Register */
+} fuses_calotp_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_FUSES_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/gclk.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/gclk.h
new file mode 100644
index 00000000..c544778d
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/gclk.h
@@ -0,0 +1,254 @@
+/*
+ * Component description for GCLK
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_GCLK_COMPONENT_H_
+#define _PIC32CMGC00_GCLK_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR GCLK                      */
+/* ************************************************************************** */
+
+/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
+#define GCLK_CTRLA_RESETVALUE                 _UINT8_(0x00)                                        /*  (GCLK_CTRLA) Control  Reset Value */
+
+#define GCLK_CTRLA_SWRST_Pos                  _UINT8_(0)                                           /* (GCLK_CTRLA) Software Reset Position */
+#define GCLK_CTRLA_SWRST_Msk                  (_UINT8_(0x1) << GCLK_CTRLA_SWRST_Pos)               /* (GCLK_CTRLA) Software Reset Mask */
+#define GCLK_CTRLA_SWRST(value)               (GCLK_CTRLA_SWRST_Msk & (_UINT8_(value) << GCLK_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the GCLK_CTRLA register */
+#define GCLK_CTRLA_Msk                        _UINT8_(0x01)                                        /* (GCLK_CTRLA) Register Mask  */
+
+
+/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) ( R/ 32) Synchronization Busy -------- */
+#define GCLK_SYNCBUSY_RESETVALUE              _UINT32_(0x00)                                       /*  (GCLK_SYNCBUSY) Synchronization Busy  Reset Value */
+
+#define GCLK_SYNCBUSY_SWRST_Pos               _UINT32_(0)                                          /* (GCLK_SYNCBUSY) Software Reset Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_SWRST_Msk               (_UINT32_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)           /* (GCLK_SYNCBUSY) Software Reset Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_SWRST(value)            (GCLK_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL0_Pos            _UINT32_(2)                                          /* (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL0_Msk            (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL0_Pos)        /* (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL0(value)         (GCLK_SYNCBUSY_GENCTRL0_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL0_Pos)) /* Assignment of value for GENCTRL0 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL1_Pos            _UINT32_(3)                                          /* (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL1_Msk            (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL1_Pos)        /* (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL1(value)         (GCLK_SYNCBUSY_GENCTRL1_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL1_Pos)) /* Assignment of value for GENCTRL1 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL2_Pos            _UINT32_(4)                                          /* (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL2_Msk            (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL2_Pos)        /* (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL2(value)         (GCLK_SYNCBUSY_GENCTRL2_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL2_Pos)) /* Assignment of value for GENCTRL2 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL3_Pos            _UINT32_(5)                                          /* (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL3_Msk            (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL3_Pos)        /* (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL3(value)         (GCLK_SYNCBUSY_GENCTRL3_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL3_Pos)) /* Assignment of value for GENCTRL3 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL4_Pos            _UINT32_(6)                                          /* (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL4_Msk            (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL4_Pos)        /* (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL4(value)         (GCLK_SYNCBUSY_GENCTRL4_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL4_Pos)) /* Assignment of value for GENCTRL4 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL5_Pos            _UINT32_(7)                                          /* (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL5_Msk            (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL5_Pos)        /* (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL5(value)         (GCLK_SYNCBUSY_GENCTRL5_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL5_Pos)) /* Assignment of value for GENCTRL5 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL6_Pos            _UINT32_(8)                                          /* (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL6_Msk            (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL6_Pos)        /* (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL6(value)         (GCLK_SYNCBUSY_GENCTRL6_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL6_Pos)) /* Assignment of value for GENCTRL6 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL7_Pos            _UINT32_(9)                                          /* (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL7_Msk            (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL7_Pos)        /* (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL7(value)         (GCLK_SYNCBUSY_GENCTRL7_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL7_Pos)) /* Assignment of value for GENCTRL7 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL8_Pos            _UINT32_(10)                                         /* (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL8_Msk            (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL8_Pos)        /* (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL8(value)         (GCLK_SYNCBUSY_GENCTRL8_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL8_Pos)) /* Assignment of value for GENCTRL8 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL9_Pos            _UINT32_(11)                                         /* (GCLK_SYNCBUSY) Generic Clock Generator Control 9 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL9_Msk            (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL9_Pos)        /* (GCLK_SYNCBUSY) Generic Clock Generator Control 9 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL9(value)         (GCLK_SYNCBUSY_GENCTRL9_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL9_Pos)) /* Assignment of value for GENCTRL9 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL10_Pos           _UINT32_(12)                                         /* (GCLK_SYNCBUSY) Generic Clock Generator Control 10 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL10_Msk           (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL10_Pos)       /* (GCLK_SYNCBUSY) Generic Clock Generator Control 10 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL10(value)        (GCLK_SYNCBUSY_GENCTRL10_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL10_Pos)) /* Assignment of value for GENCTRL10 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_GENCTRL11_Pos           _UINT32_(13)                                         /* (GCLK_SYNCBUSY) Generic Clock Generator Control 11 Synchronization Busy bit Position */
+#define GCLK_SYNCBUSY_GENCTRL11_Msk           (_UINT32_(0x1) << GCLK_SYNCBUSY_GENCTRL11_Pos)       /* (GCLK_SYNCBUSY) Generic Clock Generator Control 11 Synchronization Busy bit Mask */
+#define GCLK_SYNCBUSY_GENCTRL11(value)        (GCLK_SYNCBUSY_GENCTRL11_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL11_Pos)) /* Assignment of value for GENCTRL11 in the GCLK_SYNCBUSY register */
+#define GCLK_SYNCBUSY_Msk                     _UINT32_(0x00003FFD)                                 /* (GCLK_SYNCBUSY) Register Mask  */
+
+#define GCLK_SYNCBUSY_GENCTRL_Pos             _UINT32_(2)                                          /* (GCLK_SYNCBUSY Position) Generic Clock Generator Control xx Synchronization Busy bit */
+#define GCLK_SYNCBUSY_GENCTRL_Msk             (_UINT32_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)       /* (GCLK_SYNCBUSY Mask) GENCTRL */
+#define GCLK_SYNCBUSY_GENCTRL(value)          (GCLK_SYNCBUSY_GENCTRL_Msk & (_UINT32_(value) << GCLK_SYNCBUSY_GENCTRL_Pos)) 
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
+#define GCLK_GENCTRL_RESETVALUE               _UINT32_(0x00)                                       /*  (GCLK_GENCTRL) Generic Clock Generator Control  Reset Value */
+
+#define GCLK_GENCTRL_SRC_Pos                  _UINT32_(0)                                          /* (GCLK_GENCTRL) Source Select Position */
+#define GCLK_GENCTRL_SRC_Msk                  (_UINT32_(0xF) << GCLK_GENCTRL_SRC_Pos)              /* (GCLK_GENCTRL) Source Select Mask */
+#define GCLK_GENCTRL_SRC(value)               (GCLK_GENCTRL_SRC_Msk & (_UINT32_(value) << GCLK_GENCTRL_SRC_Pos)) /* Assignment of value for SRC in the GCLK_GENCTRL register */
+#define   GCLK_GENCTRL_SRC_XOSC_Val           _UINT32_(0x0)                                        /* (GCLK_GENCTRL) XOSC oscillator output  */
+#define   GCLK_GENCTRL_SRC_GCLK_IN_Val        _UINT32_(0x1)                                        /* (GCLK_GENCTRL) Generator input pad (GCLK_IO)  */
+#define   GCLK_GENCTRL_SRC_GCLK_GEN1_Val      _UINT32_(0x2)                                        /* (GCLK_GENCTRL) Generic clock generator 1 output  */
+#define   GCLK_GENCTRL_SRC_OSCULP32K_Val      _UINT32_(0x3)                                        /* (GCLK_GENCTRL) OSCULP32K oscillator output  */
+#define   GCLK_GENCTRL_SRC_XOSC32K_Val        _UINT32_(0x4)                                        /* (GCLK_GENCTRL) XOSC32K oscillator output  */
+#define   GCLK_GENCTRL_SRC_DFLL48M_Val        _UINT32_(0x5)                                        /* (GCLK_GENCTRL) DFLL oscillator output  */
+#define   GCLK_GENCTRL_SRC_PLL0_CLKOUT1_Val   _UINT32_(0x6)                                        /* (GCLK_GENCTRL) PLL 0 port CLKOUT1  */
+#define   GCLK_GENCTRL_SRC_PLL0_CLKOUT2_Val   _UINT32_(0x7)                                        /* (GCLK_GENCTRL) PLL 0 port CLKOUT2  */
+#define   GCLK_GENCTRL_SRC_PLL0_CLKOUT3_Val   _UINT32_(0x8)                                        /* (GCLK_GENCTRL) PLL 0 port CLKOUT3  */
+#define   GCLK_GENCTRL_SRC_PLL0_CLKOUT4_Val   _UINT32_(0x9)                                        /* (GCLK_GENCTRL) PLL 0 port CLKOUT4  */
+#define   GCLK_GENCTRL_SRC_PLL0_CLKOUT5_Val   _UINT32_(0xA)                                        /* (GCLK_GENCTRL) PLL 0 port CLKOUT5  */
+#define GCLK_GENCTRL_SRC_XOSC                 (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)  /* (GCLK_GENCTRL) XOSC oscillator output Position */
+#define GCLK_GENCTRL_SRC_GCLK_IN              (GCLK_GENCTRL_SRC_GCLK_IN_Val << GCLK_GENCTRL_SRC_Pos) /* (GCLK_GENCTRL) Generator input pad (GCLK_IO) Position */
+#define GCLK_GENCTRL_SRC_GCLK_GEN1            (GCLK_GENCTRL_SRC_GCLK_GEN1_Val << GCLK_GENCTRL_SRC_Pos) /* (GCLK_GENCTRL) Generic clock generator 1 output Position */
+#define GCLK_GENCTRL_SRC_OSCULP32K            (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) /* (GCLK_GENCTRL) OSCULP32K oscillator output Position */
+#define GCLK_GENCTRL_SRC_XOSC32K              (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) /* (GCLK_GENCTRL) XOSC32K oscillator output Position */
+#define GCLK_GENCTRL_SRC_DFLL48M              (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos) /* (GCLK_GENCTRL) DFLL oscillator output Position */
+#define GCLK_GENCTRL_SRC_PLL0_CLKOUT1         (GCLK_GENCTRL_SRC_PLL0_CLKOUT1_Val << GCLK_GENCTRL_SRC_Pos) /* (GCLK_GENCTRL) PLL 0 port CLKOUT1 Position */
+#define GCLK_GENCTRL_SRC_PLL0_CLKOUT2         (GCLK_GENCTRL_SRC_PLL0_CLKOUT2_Val << GCLK_GENCTRL_SRC_Pos) /* (GCLK_GENCTRL) PLL 0 port CLKOUT2 Position */
+#define GCLK_GENCTRL_SRC_PLL0_CLKOUT3         (GCLK_GENCTRL_SRC_PLL0_CLKOUT3_Val << GCLK_GENCTRL_SRC_Pos) /* (GCLK_GENCTRL) PLL 0 port CLKOUT3 Position */
+#define GCLK_GENCTRL_SRC_PLL0_CLKOUT4         (GCLK_GENCTRL_SRC_PLL0_CLKOUT4_Val << GCLK_GENCTRL_SRC_Pos) /* (GCLK_GENCTRL) PLL 0 port CLKOUT4 Position */
+#define GCLK_GENCTRL_SRC_PLL0_CLKOUT5         (GCLK_GENCTRL_SRC_PLL0_CLKOUT5_Val << GCLK_GENCTRL_SRC_Pos) /* (GCLK_GENCTRL) PLL 0 port CLKOUT5 Position */
+#define GCLK_GENCTRL_GENEN_Pos                _UINT32_(8)                                          /* (GCLK_GENCTRL) Generic Clock Generator Enable Position */
+#define GCLK_GENCTRL_GENEN_Msk                (_UINT32_(0x1) << GCLK_GENCTRL_GENEN_Pos)            /* (GCLK_GENCTRL) Generic Clock Generator Enable Mask */
+#define GCLK_GENCTRL_GENEN(value)             (GCLK_GENCTRL_GENEN_Msk & (_UINT32_(value) << GCLK_GENCTRL_GENEN_Pos)) /* Assignment of value for GENEN in the GCLK_GENCTRL register */
+#define GCLK_GENCTRL_IDC_Pos                  _UINT32_(9)                                          /* (GCLK_GENCTRL) Improve Duty Cycle Position */
+#define GCLK_GENCTRL_IDC_Msk                  (_UINT32_(0x1) << GCLK_GENCTRL_IDC_Pos)              /* (GCLK_GENCTRL) Improve Duty Cycle Mask */
+#define GCLK_GENCTRL_IDC(value)               (GCLK_GENCTRL_IDC_Msk & (_UINT32_(value) << GCLK_GENCTRL_IDC_Pos)) /* Assignment of value for IDC in the GCLK_GENCTRL register */
+#define GCLK_GENCTRL_OOV_Pos                  _UINT32_(10)                                         /* (GCLK_GENCTRL) Output Off Value Position */
+#define GCLK_GENCTRL_OOV_Msk                  (_UINT32_(0x1) << GCLK_GENCTRL_OOV_Pos)              /* (GCLK_GENCTRL) Output Off Value Mask */
+#define GCLK_GENCTRL_OOV(value)               (GCLK_GENCTRL_OOV_Msk & (_UINT32_(value) << GCLK_GENCTRL_OOV_Pos)) /* Assignment of value for OOV in the GCLK_GENCTRL register */
+#define GCLK_GENCTRL_OE_Pos                   _UINT32_(11)                                         /* (GCLK_GENCTRL) Output Enable Position */
+#define GCLK_GENCTRL_OE_Msk                   (_UINT32_(0x1) << GCLK_GENCTRL_OE_Pos)               /* (GCLK_GENCTRL) Output Enable Mask */
+#define GCLK_GENCTRL_OE(value)                (GCLK_GENCTRL_OE_Msk & (_UINT32_(value) << GCLK_GENCTRL_OE_Pos)) /* Assignment of value for OE in the GCLK_GENCTRL register */
+#define GCLK_GENCTRL_DIVSEL_Pos               _UINT32_(12)                                         /* (GCLK_GENCTRL) Divide Selection Position */
+#define GCLK_GENCTRL_DIVSEL_Msk               (_UINT32_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)           /* (GCLK_GENCTRL) Divide Selection Mask */
+#define GCLK_GENCTRL_DIVSEL(value)            (GCLK_GENCTRL_DIVSEL_Msk & (_UINT32_(value) << GCLK_GENCTRL_DIVSEL_Pos)) /* Assignment of value for DIVSEL in the GCLK_GENCTRL register */
+#define   GCLK_GENCTRL_DIVSEL_DIV1_Val        _UINT32_(0x0)                                        /* (GCLK_GENCTRL) Divide input directly by divider factor  */
+#define   GCLK_GENCTRL_DIVSEL_DIV2_Val        _UINT32_(0x1)                                        /* (GCLK_GENCTRL) Divide input by 2^(divider factor+ 1)  */
+#define GCLK_GENCTRL_DIVSEL_DIV1              (GCLK_GENCTRL_DIVSEL_DIV1_Val << GCLK_GENCTRL_DIVSEL_Pos) /* (GCLK_GENCTRL) Divide input directly by divider factor Position */
+#define GCLK_GENCTRL_DIVSEL_DIV2              (GCLK_GENCTRL_DIVSEL_DIV2_Val << GCLK_GENCTRL_DIVSEL_Pos) /* (GCLK_GENCTRL) Divide input by 2^(divider factor+ 1) Position */
+#define GCLK_GENCTRL_RUNSTDBY_Pos             _UINT32_(13)                                         /* (GCLK_GENCTRL) Run in Standby Position */
+#define GCLK_GENCTRL_RUNSTDBY_Msk             (_UINT32_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)         /* (GCLK_GENCTRL) Run in Standby Mask */
+#define GCLK_GENCTRL_RUNSTDBY(value)          (GCLK_GENCTRL_RUNSTDBY_Msk & (_UINT32_(value) << GCLK_GENCTRL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the GCLK_GENCTRL register */
+#define GCLK_GENCTRL_DIV_Pos                  _UINT32_(16)                                         /* (GCLK_GENCTRL) Division Factor Position */
+#define GCLK_GENCTRL_DIV_Msk                  (_UINT32_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)           /* (GCLK_GENCTRL) Division Factor Mask */
+#define GCLK_GENCTRL_DIV(value)               (GCLK_GENCTRL_DIV_Msk & (_UINT32_(value) << GCLK_GENCTRL_DIV_Pos)) /* Assignment of value for DIV in the GCLK_GENCTRL register */
+#define GCLK_GENCTRL_Msk                      _UINT32_(0xFFFF3F0F)                                 /* (GCLK_GENCTRL) Register Mask  */
+
+
+/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
+#define GCLK_PCHCTRL_RESETVALUE               _UINT32_(0x00)                                       /*  (GCLK_PCHCTRL) Peripheral Clock Control  Reset Value */
+
+#define GCLK_PCHCTRL_GEN_Pos                  _UINT32_(0)                                          /* (GCLK_PCHCTRL) Generic Clock Generator Position */
+#define GCLK_PCHCTRL_GEN_Msk                  (_UINT32_(0xF) << GCLK_PCHCTRL_GEN_Pos)              /* (GCLK_PCHCTRL) Generic Clock Generator Mask */
+#define GCLK_PCHCTRL_GEN(value)               (GCLK_PCHCTRL_GEN_Msk & (_UINT32_(value) << GCLK_PCHCTRL_GEN_Pos)) /* Assignment of value for GEN in the GCLK_PCHCTRL register */
+#define   GCLK_PCHCTRL_GEN_GCLK0_Val          _UINT32_(0x0)                                        /* (GCLK_PCHCTRL) Generic clock generator 0  */
+#define   GCLK_PCHCTRL_GEN_GCLK1_Val          _UINT32_(0x1)                                        /* (GCLK_PCHCTRL) Generic clock generator 1  */
+#define   GCLK_PCHCTRL_GEN_GCLK2_Val          _UINT32_(0x2)                                        /* (GCLK_PCHCTRL) Generic clock generator 2  */
+#define   GCLK_PCHCTRL_GEN_GCLK3_Val          _UINT32_(0x3)                                        /* (GCLK_PCHCTRL) Generic clock generator 3  */
+#define   GCLK_PCHCTRL_GEN_GCLK4_Val          _UINT32_(0x4)                                        /* (GCLK_PCHCTRL) Generic clock generator 4  */
+#define   GCLK_PCHCTRL_GEN_GCLK5_Val          _UINT32_(0x5)                                        /* (GCLK_PCHCTRL) Generic clock generator 5  */
+#define   GCLK_PCHCTRL_GEN_GCLK6_Val          _UINT32_(0x6)                                        /* (GCLK_PCHCTRL) Generic clock generator 6  */
+#define   GCLK_PCHCTRL_GEN_GCLK7_Val          _UINT32_(0x7)                                        /* (GCLK_PCHCTRL) Generic clock generator 7  */
+#define   GCLK_PCHCTRL_GEN_GCLK8_Val          _UINT32_(0x8)                                        /* (GCLK_PCHCTRL) Generic clock generator 8  */
+#define   GCLK_PCHCTRL_GEN_GCLK9_Val          _UINT32_(0x9)                                        /* (GCLK_PCHCTRL) Generic clock generator 9  */
+#define   GCLK_PCHCTRL_GEN_GCLK10_Val         _UINT32_(0xA)                                        /* (GCLK_PCHCTRL) Generic clock generator 10  */
+#define   GCLK_PCHCTRL_GEN_GCLK11_Val         _UINT32_(0xB)                                        /* (GCLK_PCHCTRL) Generic clock generator 11  */
+#define GCLK_PCHCTRL_GEN_GCLK0                (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 0 Position */
+#define GCLK_PCHCTRL_GEN_GCLK1                (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 1 Position */
+#define GCLK_PCHCTRL_GEN_GCLK2                (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 2 Position */
+#define GCLK_PCHCTRL_GEN_GCLK3                (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 3 Position */
+#define GCLK_PCHCTRL_GEN_GCLK4                (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 4 Position */
+#define GCLK_PCHCTRL_GEN_GCLK5                (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 5 Position */
+#define GCLK_PCHCTRL_GEN_GCLK6                (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 6 Position */
+#define GCLK_PCHCTRL_GEN_GCLK7                (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 7 Position */
+#define GCLK_PCHCTRL_GEN_GCLK8                (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 8 Position */
+#define GCLK_PCHCTRL_GEN_GCLK9                (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 9 Position */
+#define GCLK_PCHCTRL_GEN_GCLK10               (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 10 Position */
+#define GCLK_PCHCTRL_GEN_GCLK11               (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos) /* (GCLK_PCHCTRL) Generic clock generator 11 Position */
+#define GCLK_PCHCTRL_CHEN_Pos                 _UINT32_(6)                                          /* (GCLK_PCHCTRL) Channel Enable Position */
+#define GCLK_PCHCTRL_CHEN_Msk                 (_UINT32_(0x1) << GCLK_PCHCTRL_CHEN_Pos)             /* (GCLK_PCHCTRL) Channel Enable Mask */
+#define GCLK_PCHCTRL_CHEN(value)              (GCLK_PCHCTRL_CHEN_Msk & (_UINT32_(value) << GCLK_PCHCTRL_CHEN_Pos)) /* Assignment of value for CHEN in the GCLK_PCHCTRL register */
+#define GCLK_PCHCTRL_WRTLOCK_Pos              _UINT32_(7)                                          /* (GCLK_PCHCTRL) Write Lock Position */
+#define GCLK_PCHCTRL_WRTLOCK_Msk              (_UINT32_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)          /* (GCLK_PCHCTRL) Write Lock Mask */
+#define GCLK_PCHCTRL_WRTLOCK(value)           (GCLK_PCHCTRL_WRTLOCK_Msk & (_UINT32_(value) << GCLK_PCHCTRL_WRTLOCK_Pos)) /* Assignment of value for WRTLOCK in the GCLK_PCHCTRL register */
+#define GCLK_PCHCTRL_Msk                      _UINT32_(0x000000CF)                                 /* (GCLK_PCHCTRL) Register Mask  */
+
+
+/* GCLK register offsets definitions */
+#define GCLK_CTRLA_REG_OFST            _UINT32_(0x00)      /* (GCLK_CTRLA) Control Offset */
+#define GCLK_SYNCBUSY_REG_OFST         _UINT32_(0x04)      /* (GCLK_SYNCBUSY) Synchronization Busy Offset */
+#define GCLK_GENCTRL_REG_OFST          _UINT32_(0x20)      /* (GCLK_GENCTRL) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL0_REG_OFST         _UINT32_(0x20)      /* (GCLK_GENCTRL0) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL1_REG_OFST         _UINT32_(0x24)      /* (GCLK_GENCTRL1) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL2_REG_OFST         _UINT32_(0x28)      /* (GCLK_GENCTRL2) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL3_REG_OFST         _UINT32_(0x2C)      /* (GCLK_GENCTRL3) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL4_REG_OFST         _UINT32_(0x30)      /* (GCLK_GENCTRL4) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL5_REG_OFST         _UINT32_(0x34)      /* (GCLK_GENCTRL5) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL6_REG_OFST         _UINT32_(0x38)      /* (GCLK_GENCTRL6) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL7_REG_OFST         _UINT32_(0x3C)      /* (GCLK_GENCTRL7) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL8_REG_OFST         _UINT32_(0x40)      /* (GCLK_GENCTRL8) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL9_REG_OFST         _UINT32_(0x44)      /* (GCLK_GENCTRL9) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL10_REG_OFST        _UINT32_(0x48)      /* (GCLK_GENCTRL10) Generic Clock Generator Control Offset */
+#define GCLK_GENCTRL11_REG_OFST        _UINT32_(0x4C)      /* (GCLK_GENCTRL11) Generic Clock Generator Control Offset */
+#define GCLK_PCHCTRL_REG_OFST          _UINT32_(0x80)      /* (GCLK_PCHCTRL) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL0_REG_OFST         _UINT32_(0x80)      /* (GCLK_PCHCTRL0) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL1_REG_OFST         _UINT32_(0x84)      /* (GCLK_PCHCTRL1) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL2_REG_OFST         _UINT32_(0x88)      /* (GCLK_PCHCTRL2) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL3_REG_OFST         _UINT32_(0x8C)      /* (GCLK_PCHCTRL3) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL4_REG_OFST         _UINT32_(0x90)      /* (GCLK_PCHCTRL4) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL5_REG_OFST         _UINT32_(0x94)      /* (GCLK_PCHCTRL5) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL6_REG_OFST         _UINT32_(0x98)      /* (GCLK_PCHCTRL6) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL7_REG_OFST         _UINT32_(0x9C)      /* (GCLK_PCHCTRL7) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL8_REG_OFST         _UINT32_(0xA0)      /* (GCLK_PCHCTRL8) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL9_REG_OFST         _UINT32_(0xA4)      /* (GCLK_PCHCTRL9) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL10_REG_OFST        _UINT32_(0xA8)      /* (GCLK_PCHCTRL10) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL11_REG_OFST        _UINT32_(0xAC)      /* (GCLK_PCHCTRL11) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL12_REG_OFST        _UINT32_(0xB0)      /* (GCLK_PCHCTRL12) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL13_REG_OFST        _UINT32_(0xB4)      /* (GCLK_PCHCTRL13) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL14_REG_OFST        _UINT32_(0xB8)      /* (GCLK_PCHCTRL14) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL15_REG_OFST        _UINT32_(0xBC)      /* (GCLK_PCHCTRL15) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL16_REG_OFST        _UINT32_(0xC0)      /* (GCLK_PCHCTRL16) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL17_REG_OFST        _UINT32_(0xC4)      /* (GCLK_PCHCTRL17) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL18_REG_OFST        _UINT32_(0xC8)      /* (GCLK_PCHCTRL18) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL19_REG_OFST        _UINT32_(0xCC)      /* (GCLK_PCHCTRL19) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL20_REG_OFST        _UINT32_(0xD0)      /* (GCLK_PCHCTRL20) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL21_REG_OFST        _UINT32_(0xD4)      /* (GCLK_PCHCTRL21) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL22_REG_OFST        _UINT32_(0xD8)      /* (GCLK_PCHCTRL22) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL23_REG_OFST        _UINT32_(0xDC)      /* (GCLK_PCHCTRL23) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL24_REG_OFST        _UINT32_(0xE0)      /* (GCLK_PCHCTRL24) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL25_REG_OFST        _UINT32_(0xE4)      /* (GCLK_PCHCTRL25) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL26_REG_OFST        _UINT32_(0xE8)      /* (GCLK_PCHCTRL26) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL27_REG_OFST        _UINT32_(0xEC)      /* (GCLK_PCHCTRL27) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL28_REG_OFST        _UINT32_(0xF0)      /* (GCLK_PCHCTRL28) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL29_REG_OFST        _UINT32_(0xF4)      /* (GCLK_PCHCTRL29) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL30_REG_OFST        _UINT32_(0xF8)      /* (GCLK_PCHCTRL30) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL31_REG_OFST        _UINT32_(0xFC)      /* (GCLK_PCHCTRL31) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL32_REG_OFST        _UINT32_(0x100)     /* (GCLK_PCHCTRL32) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL33_REG_OFST        _UINT32_(0x104)     /* (GCLK_PCHCTRL33) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL34_REG_OFST        _UINT32_(0x108)     /* (GCLK_PCHCTRL34) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL35_REG_OFST        _UINT32_(0x10C)     /* (GCLK_PCHCTRL35) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL36_REG_OFST        _UINT32_(0x110)     /* (GCLK_PCHCTRL36) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL37_REG_OFST        _UINT32_(0x114)     /* (GCLK_PCHCTRL37) Peripheral Clock Control Offset */
+#define GCLK_PCHCTRL38_REG_OFST        _UINT32_(0x118)     /* (GCLK_PCHCTRL38) Peripheral Clock Control Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* GCLK register API structure */
+typedef struct
+{  /* Generic Clock Generator */
+  __IO  uint8_t                        GCLK_CTRLA;         /* Offset: 0x00 (R/W  8) Control */
+  __I   uint8_t                        Reserved1[0x03];
+  __I   uint32_t                       GCLK_SYNCBUSY;      /* Offset: 0x04 (R/   32) Synchronization Busy */
+  __I   uint8_t                        Reserved2[0x18];
+  __IO  uint32_t                       GCLK_GENCTRL[12];   /* Offset: 0x20 (R/W  32) Generic Clock Generator Control */
+  __I   uint8_t                        Reserved3[0x30];
+  __IO  uint32_t                       GCLK_PCHCTRL[39];   /* Offset: 0x80 (R/W  32) Peripheral Clock Control */
+} gclk_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_GCLK_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/h2pb.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/h2pb.h
new file mode 100644
index 00000000..94899853
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/h2pb.h
@@ -0,0 +1,269 @@
+/*
+ * Component description for H2PB
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_H2PB_COMPONENT_H_
+#define _PIC32CMGC00_H2PB_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR H2PB                      */
+/* ************************************************************************** */
+
+/* -------- H2PB_CTRLA : (H2PB Offset: 0x00) (R/W 32) H2PB CONTROL Register -------- */
+#define H2PB_CTRLA_RESETVALUE                 _UINT32_(0x00)                                       /*  (H2PB_CTRLA) H2PB CONTROL Register  Reset Value */
+
+#define H2PB_CTRLA_PRIV_Pos                   _UINT32_(2)                                          /* (H2PB_CTRLA) PRIV privileged access protection bit Position */
+#define H2PB_CTRLA_PRIV_Msk                   (_UINT32_(0x1) << H2PB_CTRLA_PRIV_Pos)               /* (H2PB_CTRLA) PRIV privileged access protection bit Mask */
+#define H2PB_CTRLA_PRIV(value)                (H2PB_CTRLA_PRIV_Msk & (_UINT32_(value) << H2PB_CTRLA_PRIV_Pos)) /* Assignment of value for PRIV in the H2PB_CTRLA register */
+#define H2PB_CTRLA_SECEN_Pos                  _UINT32_(3)                                          /* (H2PB_CTRLA) SECEN security enable bit Position */
+#define H2PB_CTRLA_SECEN_Msk                  (_UINT32_(0x1) << H2PB_CTRLA_SECEN_Pos)              /* (H2PB_CTRLA) SECEN security enable bit Mask */
+#define H2PB_CTRLA_SECEN(value)               (H2PB_CTRLA_SECEN_Msk & (_UINT32_(value) << H2PB_CTRLA_SECEN_Pos)) /* Assignment of value for SECEN in the H2PB_CTRLA register */
+#define H2PB_CTRLA_Msk                        _UINT32_(0x0000000C)                                 /* (H2PB_CTRLA) Register Mask  */
+
+
+/* -------- H2PB_NONSECCLRA : (H2PB Offset: 0x08) (R/W 32) Non-Security Clear Register A -------- */
+#define H2PB_NONSECCLRA_RESETVALUE            _UINT32_(0x00)                                       /*  (H2PB_NONSECCLRA) Non-Security Clear Register A  Reset Value */
+
+#define H2PB_NONSECCLRA_NONSEC0_Pos           _UINT32_(0)                                          /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC0_Msk           (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC0_Pos)       /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC0(value)        (H2PB_NONSECCLRA_NONSEC0_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC0_Pos)) /* Assignment of value for NONSEC0 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC1_Pos           _UINT32_(1)                                          /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC1_Msk           (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC1_Pos)       /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC1(value)        (H2PB_NONSECCLRA_NONSEC1_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC1_Pos)) /* Assignment of value for NONSEC1 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC2_Pos           _UINT32_(2)                                          /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC2_Msk           (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC2_Pos)       /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC2(value)        (H2PB_NONSECCLRA_NONSEC2_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC2_Pos)) /* Assignment of value for NONSEC2 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC3_Pos           _UINT32_(3)                                          /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC3_Msk           (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC3_Pos)       /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC3(value)        (H2PB_NONSECCLRA_NONSEC3_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC3_Pos)) /* Assignment of value for NONSEC3 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC4_Pos           _UINT32_(4)                                          /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC4_Msk           (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC4_Pos)       /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC4(value)        (H2PB_NONSECCLRA_NONSEC4_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC4_Pos)) /* Assignment of value for NONSEC4 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC5_Pos           _UINT32_(5)                                          /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC5_Msk           (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC5_Pos)       /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC5(value)        (H2PB_NONSECCLRA_NONSEC5_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC5_Pos)) /* Assignment of value for NONSEC5 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC6_Pos           _UINT32_(6)                                          /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC6_Msk           (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC6_Pos)       /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC6(value)        (H2PB_NONSECCLRA_NONSEC6_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC6_Pos)) /* Assignment of value for NONSEC6 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC7_Pos           _UINT32_(7)                                          /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC7_Msk           (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC7_Pos)       /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC7(value)        (H2PB_NONSECCLRA_NONSEC7_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC7_Pos)) /* Assignment of value for NONSEC7 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC8_Pos           _UINT32_(8)                                          /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC8_Msk           (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC8_Pos)       /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC8(value)        (H2PB_NONSECCLRA_NONSEC8_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC8_Pos)) /* Assignment of value for NONSEC8 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC9_Pos           _UINT32_(9)                                          /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC9_Msk           (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC9_Pos)       /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC9(value)        (H2PB_NONSECCLRA_NONSEC9_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC9_Pos)) /* Assignment of value for NONSEC9 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC10_Pos          _UINT32_(10)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC10_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC10_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC10(value)       (H2PB_NONSECCLRA_NONSEC10_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC10_Pos)) /* Assignment of value for NONSEC10 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC11_Pos          _UINT32_(11)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC11_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC11_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC11(value)       (H2PB_NONSECCLRA_NONSEC11_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC11_Pos)) /* Assignment of value for NONSEC11 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC12_Pos          _UINT32_(12)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC12_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC12_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC12(value)       (H2PB_NONSECCLRA_NONSEC12_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC12_Pos)) /* Assignment of value for NONSEC12 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC13_Pos          _UINT32_(13)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC13_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC13_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC13(value)       (H2PB_NONSECCLRA_NONSEC13_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC13_Pos)) /* Assignment of value for NONSEC13 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC14_Pos          _UINT32_(14)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC14_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC14_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC14(value)       (H2PB_NONSECCLRA_NONSEC14_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC14_Pos)) /* Assignment of value for NONSEC14 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC15_Pos          _UINT32_(15)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC15_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC15_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC15(value)       (H2PB_NONSECCLRA_NONSEC15_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC15_Pos)) /* Assignment of value for NONSEC15 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC16_Pos          _UINT32_(16)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC16_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC16_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC16(value)       (H2PB_NONSECCLRA_NONSEC16_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC16_Pos)) /* Assignment of value for NONSEC16 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC17_Pos          _UINT32_(17)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC17_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC17_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC17(value)       (H2PB_NONSECCLRA_NONSEC17_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC17_Pos)) /* Assignment of value for NONSEC17 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC18_Pos          _UINT32_(18)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC18_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC18_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC18(value)       (H2PB_NONSECCLRA_NONSEC18_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC18_Pos)) /* Assignment of value for NONSEC18 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC19_Pos          _UINT32_(19)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC19_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC19_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC19(value)       (H2PB_NONSECCLRA_NONSEC19_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC19_Pos)) /* Assignment of value for NONSEC19 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC20_Pos          _UINT32_(20)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC20_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC20_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC20(value)       (H2PB_NONSECCLRA_NONSEC20_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC20_Pos)) /* Assignment of value for NONSEC20 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC21_Pos          _UINT32_(21)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC21_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC21_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC21(value)       (H2PB_NONSECCLRA_NONSEC21_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC21_Pos)) /* Assignment of value for NONSEC21 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC22_Pos          _UINT32_(22)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC22_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC22_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC22(value)       (H2PB_NONSECCLRA_NONSEC22_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC22_Pos)) /* Assignment of value for NONSEC22 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC23_Pos          _UINT32_(23)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC23_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC23_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC23(value)       (H2PB_NONSECCLRA_NONSEC23_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC23_Pos)) /* Assignment of value for NONSEC23 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC24_Pos          _UINT32_(24)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC24_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC24_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC24(value)       (H2PB_NONSECCLRA_NONSEC24_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC24_Pos)) /* Assignment of value for NONSEC24 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC25_Pos          _UINT32_(25)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC25_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC25_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC25(value)       (H2PB_NONSECCLRA_NONSEC25_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC25_Pos)) /* Assignment of value for NONSEC25 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC26_Pos          _UINT32_(26)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC26_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC26_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC26(value)       (H2PB_NONSECCLRA_NONSEC26_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC26_Pos)) /* Assignment of value for NONSEC26 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC27_Pos          _UINT32_(27)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC27_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC27_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC27(value)       (H2PB_NONSECCLRA_NONSEC27_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC27_Pos)) /* Assignment of value for NONSEC27 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC28_Pos          _UINT32_(28)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC28_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC28_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC28(value)       (H2PB_NONSECCLRA_NONSEC28_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC28_Pos)) /* Assignment of value for NONSEC28 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC29_Pos          _UINT32_(29)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC29_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC29_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC29(value)       (H2PB_NONSECCLRA_NONSEC29_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC29_Pos)) /* Assignment of value for NONSEC29 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC30_Pos          _UINT32_(30)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC30_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC30_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC30(value)       (H2PB_NONSECCLRA_NONSEC30_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC30_Pos)) /* Assignment of value for NONSEC30 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_NONSEC31_Pos          _UINT32_(31)                                         /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECCLRA_NONSEC31_Msk          (_UINT32_(0x1) << H2PB_NONSECCLRA_NONSEC31_Pos)      /* (H2PB_NONSECCLRA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECCLRA_NONSEC31(value)       (H2PB_NONSECCLRA_NONSEC31_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC31_Pos)) /* Assignment of value for NONSEC31 in the H2PB_NONSECCLRA register */
+#define H2PB_NONSECCLRA_Msk                   _UINT32_(0xFFFFFFFF)                                 /* (H2PB_NONSECCLRA) Register Mask  */
+
+#define H2PB_NONSECCLRA_NONSEC_Pos            _UINT32_(0)                                          /* (H2PB_NONSECCLRA Position) non-security bit for APB Slave k, k=x..3x */
+#define H2PB_NONSECCLRA_NONSEC_Msk            (_UINT32_(0xFFFFFFFF) << H2PB_NONSECCLRA_NONSEC_Pos) /* (H2PB_NONSECCLRA Mask) NONSEC */
+#define H2PB_NONSECCLRA_NONSEC(value)         (H2PB_NONSECCLRA_NONSEC_Msk & (_UINT32_(value) << H2PB_NONSECCLRA_NONSEC_Pos)) 
+
+/* -------- H2PB_NONSECSETA : (H2PB Offset: 0x0C) (R/W 32) Non-Security SET Register A -------- */
+#define H2PB_NONSECSETA_RESETVALUE            _UINT32_(0x00)                                       /*  (H2PB_NONSECSETA) Non-Security SET Register A  Reset Value */
+
+#define H2PB_NONSECSETA_NONSEC0_Pos           _UINT32_(0)                                          /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC0_Msk           (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC0_Pos)       /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC0(value)        (H2PB_NONSECSETA_NONSEC0_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC0_Pos)) /* Assignment of value for NONSEC0 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC1_Pos           _UINT32_(1)                                          /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC1_Msk           (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC1_Pos)       /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC1(value)        (H2PB_NONSECSETA_NONSEC1_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC1_Pos)) /* Assignment of value for NONSEC1 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC2_Pos           _UINT32_(2)                                          /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC2_Msk           (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC2_Pos)       /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC2(value)        (H2PB_NONSECSETA_NONSEC2_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC2_Pos)) /* Assignment of value for NONSEC2 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC3_Pos           _UINT32_(3)                                          /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC3_Msk           (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC3_Pos)       /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC3(value)        (H2PB_NONSECSETA_NONSEC3_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC3_Pos)) /* Assignment of value for NONSEC3 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC4_Pos           _UINT32_(4)                                          /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC4_Msk           (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC4_Pos)       /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC4(value)        (H2PB_NONSECSETA_NONSEC4_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC4_Pos)) /* Assignment of value for NONSEC4 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC5_Pos           _UINT32_(5)                                          /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC5_Msk           (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC5_Pos)       /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC5(value)        (H2PB_NONSECSETA_NONSEC5_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC5_Pos)) /* Assignment of value for NONSEC5 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC6_Pos           _UINT32_(6)                                          /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC6_Msk           (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC6_Pos)       /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC6(value)        (H2PB_NONSECSETA_NONSEC6_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC6_Pos)) /* Assignment of value for NONSEC6 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC7_Pos           _UINT32_(7)                                          /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC7_Msk           (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC7_Pos)       /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC7(value)        (H2PB_NONSECSETA_NONSEC7_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC7_Pos)) /* Assignment of value for NONSEC7 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC8_Pos           _UINT32_(8)                                          /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC8_Msk           (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC8_Pos)       /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC8(value)        (H2PB_NONSECSETA_NONSEC8_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC8_Pos)) /* Assignment of value for NONSEC8 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC9_Pos           _UINT32_(9)                                          /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC9_Msk           (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC9_Pos)       /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC9(value)        (H2PB_NONSECSETA_NONSEC9_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC9_Pos)) /* Assignment of value for NONSEC9 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC10_Pos          _UINT32_(10)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC10_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC10_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC10(value)       (H2PB_NONSECSETA_NONSEC10_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC10_Pos)) /* Assignment of value for NONSEC10 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC11_Pos          _UINT32_(11)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC11_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC11_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC11(value)       (H2PB_NONSECSETA_NONSEC11_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC11_Pos)) /* Assignment of value for NONSEC11 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC12_Pos          _UINT32_(12)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC12_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC12_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC12(value)       (H2PB_NONSECSETA_NONSEC12_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC12_Pos)) /* Assignment of value for NONSEC12 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC13_Pos          _UINT32_(13)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC13_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC13_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC13(value)       (H2PB_NONSECSETA_NONSEC13_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC13_Pos)) /* Assignment of value for NONSEC13 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC14_Pos          _UINT32_(14)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC14_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC14_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC14(value)       (H2PB_NONSECSETA_NONSEC14_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC14_Pos)) /* Assignment of value for NONSEC14 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC15_Pos          _UINT32_(15)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC15_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC15_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC15(value)       (H2PB_NONSECSETA_NONSEC15_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC15_Pos)) /* Assignment of value for NONSEC15 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC16_Pos          _UINT32_(16)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC16_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC16_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC16(value)       (H2PB_NONSECSETA_NONSEC16_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC16_Pos)) /* Assignment of value for NONSEC16 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC17_Pos          _UINT32_(17)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC17_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC17_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC17(value)       (H2PB_NONSECSETA_NONSEC17_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC17_Pos)) /* Assignment of value for NONSEC17 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC18_Pos          _UINT32_(18)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC18_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC18_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC18(value)       (H2PB_NONSECSETA_NONSEC18_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC18_Pos)) /* Assignment of value for NONSEC18 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC19_Pos          _UINT32_(19)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC19_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC19_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC19(value)       (H2PB_NONSECSETA_NONSEC19_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC19_Pos)) /* Assignment of value for NONSEC19 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC20_Pos          _UINT32_(20)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC20_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC20_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC20(value)       (H2PB_NONSECSETA_NONSEC20_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC20_Pos)) /* Assignment of value for NONSEC20 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC21_Pos          _UINT32_(21)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC21_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC21_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC21(value)       (H2PB_NONSECSETA_NONSEC21_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC21_Pos)) /* Assignment of value for NONSEC21 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC22_Pos          _UINT32_(22)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC22_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC22_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC22(value)       (H2PB_NONSECSETA_NONSEC22_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC22_Pos)) /* Assignment of value for NONSEC22 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC23_Pos          _UINT32_(23)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC23_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC23_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC23(value)       (H2PB_NONSECSETA_NONSEC23_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC23_Pos)) /* Assignment of value for NONSEC23 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC24_Pos          _UINT32_(24)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC24_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC24_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC24(value)       (H2PB_NONSECSETA_NONSEC24_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC24_Pos)) /* Assignment of value for NONSEC24 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC25_Pos          _UINT32_(25)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC25_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC25_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC25(value)       (H2PB_NONSECSETA_NONSEC25_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC25_Pos)) /* Assignment of value for NONSEC25 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC26_Pos          _UINT32_(26)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC26_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC26_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC26(value)       (H2PB_NONSECSETA_NONSEC26_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC26_Pos)) /* Assignment of value for NONSEC26 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC27_Pos          _UINT32_(27)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC27_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC27_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC27(value)       (H2PB_NONSECSETA_NONSEC27_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC27_Pos)) /* Assignment of value for NONSEC27 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC28_Pos          _UINT32_(28)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC28_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC28_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC28(value)       (H2PB_NONSECSETA_NONSEC28_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC28_Pos)) /* Assignment of value for NONSEC28 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC29_Pos          _UINT32_(29)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC29_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC29_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC29(value)       (H2PB_NONSECSETA_NONSEC29_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC29_Pos)) /* Assignment of value for NONSEC29 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC30_Pos          _UINT32_(30)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC30_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC30_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC30(value)       (H2PB_NONSECSETA_NONSEC30_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC30_Pos)) /* Assignment of value for NONSEC30 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_NONSEC31_Pos          _UINT32_(31)                                         /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Position */
+#define H2PB_NONSECSETA_NONSEC31_Msk          (_UINT32_(0x1) << H2PB_NONSECSETA_NONSEC31_Pos)      /* (H2PB_NONSECSETA) non-security bit for APB Slave k, k=0..31 Mask */
+#define H2PB_NONSECSETA_NONSEC31(value)       (H2PB_NONSECSETA_NONSEC31_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC31_Pos)) /* Assignment of value for NONSEC31 in the H2PB_NONSECSETA register */
+#define H2PB_NONSECSETA_Msk                   _UINT32_(0xFFFFFFFF)                                 /* (H2PB_NONSECSETA) Register Mask  */
+
+#define H2PB_NONSECSETA_NONSEC_Pos            _UINT32_(0)                                          /* (H2PB_NONSECSETA Position) non-security bit for APB Slave k, k=x..3x */
+#define H2PB_NONSECSETA_NONSEC_Msk            (_UINT32_(0xFFFFFFFF) << H2PB_NONSECSETA_NONSEC_Pos) /* (H2PB_NONSECSETA Mask) NONSEC */
+#define H2PB_NONSECSETA_NONSEC(value)         (H2PB_NONSECSETA_NONSEC_Msk & (_UINT32_(value) << H2PB_NONSECSETA_NONSEC_Pos)) 
+
+/* H2PB register offsets definitions */
+#define H2PB_CTRLA_REG_OFST            _UINT32_(0x00)      /* (H2PB_CTRLA) H2PB CONTROL Register Offset */
+#define H2PB_NONSECCLRA_REG_OFST       _UINT32_(0x08)      /* (H2PB_NONSECCLRA) Non-Security Clear Register A Offset */
+#define H2PB_NONSECSETA_REG_OFST       _UINT32_(0x0C)      /* (H2PB_NONSECSETA) Non-Security SET Register A Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* H2PB register API structure */
+typedef struct
+{  /* AHB To APB Bridge */
+  __IO  uint32_t                       H2PB_CTRLA;         /* Offset: 0x00 (R/W  32) H2PB CONTROL Register */
+  __I   uint8_t                        Reserved1[0x04];
+  __IO  uint32_t                       H2PB_NONSECCLRA;    /* Offset: 0x08 (R/W  32) Non-Security Clear Register A */
+  __IO  uint32_t                       H2PB_NONSECSETA;    /* Offset: 0x0C (R/W  32) Non-Security SET Register A */
+} h2pb_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_H2PB_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/hmatrix2.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/hmatrix2.h
new file mode 100644
index 00000000..a52add20
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/hmatrix2.h
@@ -0,0 +1,350 @@
+/*
+ * Component description for HMATRIX2
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_HMATRIX2_COMPONENT_H_
+#define _PIC32CMGC00_HMATRIX2_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                    SOFTWARE API DEFINITION FOR HMATRIX2                    */
+/* ************************************************************************** */
+
+/* -------- HMATRIX2_PRAS : (HMATRIX2 Offset: 0x00) (R/W 32) Priority A for Slave -------- */
+#define HMATRIX2_PRAS_RESETVALUE              _UINT32_(0x00)                                       /*  (HMATRIX2_PRAS) Priority A for Slave  Reset Value */
+
+#define HMATRIX2_PRAS_M0PR_Pos                _UINT32_(0)                                          /* (HMATRIX2_PRAS) Master 0 Priority Position */
+#define HMATRIX2_PRAS_M0PR_Msk                (_UINT32_(0x3) << HMATRIX2_PRAS_M0PR_Pos)            /* (HMATRIX2_PRAS) Master 0 Priority Mask */
+#define HMATRIX2_PRAS_M0PR(value)             (HMATRIX2_PRAS_M0PR_Msk & (_UINT32_(value) << HMATRIX2_PRAS_M0PR_Pos)) /* Assignment of value for M0PR in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_LQOSEN0_Pos             _UINT32_(2)                                          /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 0 Position */
+#define HMATRIX2_PRAS_LQOSEN0_Msk             (_UINT32_(0x1) << HMATRIX2_PRAS_LQOSEN0_Pos)         /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 0 Mask */
+#define HMATRIX2_PRAS_LQOSEN0(value)          (HMATRIX2_PRAS_LQOSEN0_Msk & (_UINT32_(value) << HMATRIX2_PRAS_LQOSEN0_Pos)) /* Assignment of value for LQOSEN0 in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_M1PR_Pos                _UINT32_(4)                                          /* (HMATRIX2_PRAS) Master 1 Priority Position */
+#define HMATRIX2_PRAS_M1PR_Msk                (_UINT32_(0x3) << HMATRIX2_PRAS_M1PR_Pos)            /* (HMATRIX2_PRAS) Master 1 Priority Mask */
+#define HMATRIX2_PRAS_M1PR(value)             (HMATRIX2_PRAS_M1PR_Msk & (_UINT32_(value) << HMATRIX2_PRAS_M1PR_Pos)) /* Assignment of value for M1PR in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_LQOSEN1_Pos             _UINT32_(6)                                          /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 1 Position */
+#define HMATRIX2_PRAS_LQOSEN1_Msk             (_UINT32_(0x1) << HMATRIX2_PRAS_LQOSEN1_Pos)         /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 1 Mask */
+#define HMATRIX2_PRAS_LQOSEN1(value)          (HMATRIX2_PRAS_LQOSEN1_Msk & (_UINT32_(value) << HMATRIX2_PRAS_LQOSEN1_Pos)) /* Assignment of value for LQOSEN1 in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_M2PR_Pos                _UINT32_(8)                                          /* (HMATRIX2_PRAS) Master 2 Priority Position */
+#define HMATRIX2_PRAS_M2PR_Msk                (_UINT32_(0x3) << HMATRIX2_PRAS_M2PR_Pos)            /* (HMATRIX2_PRAS) Master 2 Priority Mask */
+#define HMATRIX2_PRAS_M2PR(value)             (HMATRIX2_PRAS_M2PR_Msk & (_UINT32_(value) << HMATRIX2_PRAS_M2PR_Pos)) /* Assignment of value for M2PR in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_LQOSEN2_Pos             _UINT32_(10)                                         /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 2 Position */
+#define HMATRIX2_PRAS_LQOSEN2_Msk             (_UINT32_(0x1) << HMATRIX2_PRAS_LQOSEN2_Pos)         /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 2 Mask */
+#define HMATRIX2_PRAS_LQOSEN2(value)          (HMATRIX2_PRAS_LQOSEN2_Msk & (_UINT32_(value) << HMATRIX2_PRAS_LQOSEN2_Pos)) /* Assignment of value for LQOSEN2 in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_M3PR_Pos                _UINT32_(12)                                         /* (HMATRIX2_PRAS) Master 3 Priority Position */
+#define HMATRIX2_PRAS_M3PR_Msk                (_UINT32_(0x3) << HMATRIX2_PRAS_M3PR_Pos)            /* (HMATRIX2_PRAS) Master 3 Priority Mask */
+#define HMATRIX2_PRAS_M3PR(value)             (HMATRIX2_PRAS_M3PR_Msk & (_UINT32_(value) << HMATRIX2_PRAS_M3PR_Pos)) /* Assignment of value for M3PR in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_LQOSEN3_Pos             _UINT32_(14)                                         /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 3 Position */
+#define HMATRIX2_PRAS_LQOSEN3_Msk             (_UINT32_(0x1) << HMATRIX2_PRAS_LQOSEN3_Pos)         /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 3 Mask */
+#define HMATRIX2_PRAS_LQOSEN3(value)          (HMATRIX2_PRAS_LQOSEN3_Msk & (_UINT32_(value) << HMATRIX2_PRAS_LQOSEN3_Pos)) /* Assignment of value for LQOSEN3 in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_M4PR_Pos                _UINT32_(16)                                         /* (HMATRIX2_PRAS) Master 4 Priority Position */
+#define HMATRIX2_PRAS_M4PR_Msk                (_UINT32_(0x3) << HMATRIX2_PRAS_M4PR_Pos)            /* (HMATRIX2_PRAS) Master 4 Priority Mask */
+#define HMATRIX2_PRAS_M4PR(value)             (HMATRIX2_PRAS_M4PR_Msk & (_UINT32_(value) << HMATRIX2_PRAS_M4PR_Pos)) /* Assignment of value for M4PR in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_LQOSEN4_Pos             _UINT32_(18)                                         /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 4 Position */
+#define HMATRIX2_PRAS_LQOSEN4_Msk             (_UINT32_(0x1) << HMATRIX2_PRAS_LQOSEN4_Pos)         /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 4 Mask */
+#define HMATRIX2_PRAS_LQOSEN4(value)          (HMATRIX2_PRAS_LQOSEN4_Msk & (_UINT32_(value) << HMATRIX2_PRAS_LQOSEN4_Pos)) /* Assignment of value for LQOSEN4 in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_M5PR_Pos                _UINT32_(20)                                         /* (HMATRIX2_PRAS) Master 5 Priority Position */
+#define HMATRIX2_PRAS_M5PR_Msk                (_UINT32_(0x3) << HMATRIX2_PRAS_M5PR_Pos)            /* (HMATRIX2_PRAS) Master 5 Priority Mask */
+#define HMATRIX2_PRAS_M5PR(value)             (HMATRIX2_PRAS_M5PR_Msk & (_UINT32_(value) << HMATRIX2_PRAS_M5PR_Pos)) /* Assignment of value for M5PR in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_LQOSEN5_Pos             _UINT32_(22)                                         /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 5 Position */
+#define HMATRIX2_PRAS_LQOSEN5_Msk             (_UINT32_(0x1) << HMATRIX2_PRAS_LQOSEN5_Pos)         /* (HMATRIX2_PRAS) Latency Quality Of Service Enable for Master 5 Mask */
+#define HMATRIX2_PRAS_LQOSEN5(value)          (HMATRIX2_PRAS_LQOSEN5_Msk & (_UINT32_(value) << HMATRIX2_PRAS_LQOSEN5_Pos)) /* Assignment of value for LQOSEN5 in the HMATRIX2_PRAS register */
+#define HMATRIX2_PRAS_Msk                     _UINT32_(0x00777777)                                 /* (HMATRIX2_PRAS) Register Mask  */
+
+
+/* -------- HMATRIX2_MCFG : (HMATRIX2 Offset: 0x00) (R/W 32) Master Configuration -------- */
+#define HMATRIX2_MCFG_RESETVALUE              _UINT32_(0x02)                                       /*  (HMATRIX2_MCFG) Master Configuration  Reset Value */
+
+#define HMATRIX2_MCFG_ULBT_Pos                _UINT32_(0)                                          /* (HMATRIX2_MCFG) Undefined Length Burst Type Position */
+#define HMATRIX2_MCFG_ULBT_Msk                (_UINT32_(0x7) << HMATRIX2_MCFG_ULBT_Pos)            /* (HMATRIX2_MCFG) Undefined Length Burst Type Mask */
+#define HMATRIX2_MCFG_ULBT(value)             (HMATRIX2_MCFG_ULBT_Msk & (_UINT32_(value) << HMATRIX2_MCFG_ULBT_Pos)) /* Assignment of value for ULBT in the HMATRIX2_MCFG register */
+#define   HMATRIX2_MCFG_ULBT_INFINITE_Val     _UINT32_(0x0)                                        /* (HMATRIX2_MCFG) Infinite Length  */
+#define   HMATRIX2_MCFG_ULBT_SINGLE_Val       _UINT32_(0x1)                                        /* (HMATRIX2_MCFG) Single Access  */
+#define   HMATRIX2_MCFG_ULBT_FOUR_BEAT_Val    _UINT32_(0x2)                                        /* (HMATRIX2_MCFG) Four Beat Burst  */
+#define   HMATRIX2_MCFG_ULBT_EIGHT_BEAT_Val   _UINT32_(0x3)                                        /* (HMATRIX2_MCFG) Eight Beat Burst  */
+#define   HMATRIX2_MCFG_ULBT_SIXTEEN_BEAT_Val _UINT32_(0x4)                                        /* (HMATRIX2_MCFG) Sixteen Beat Burst  */
+#define HMATRIX2_MCFG_ULBT_INFINITE           (HMATRIX2_MCFG_ULBT_INFINITE_Val << HMATRIX2_MCFG_ULBT_Pos) /* (HMATRIX2_MCFG) Infinite Length Position */
+#define HMATRIX2_MCFG_ULBT_SINGLE             (HMATRIX2_MCFG_ULBT_SINGLE_Val << HMATRIX2_MCFG_ULBT_Pos) /* (HMATRIX2_MCFG) Single Access Position */
+#define HMATRIX2_MCFG_ULBT_FOUR_BEAT          (HMATRIX2_MCFG_ULBT_FOUR_BEAT_Val << HMATRIX2_MCFG_ULBT_Pos) /* (HMATRIX2_MCFG) Four Beat Burst Position */
+#define HMATRIX2_MCFG_ULBT_EIGHT_BEAT         (HMATRIX2_MCFG_ULBT_EIGHT_BEAT_Val << HMATRIX2_MCFG_ULBT_Pos) /* (HMATRIX2_MCFG) Eight Beat Burst Position */
+#define HMATRIX2_MCFG_ULBT_SIXTEEN_BEAT       (HMATRIX2_MCFG_ULBT_SIXTEEN_BEAT_Val << HMATRIX2_MCFG_ULBT_Pos) /* (HMATRIX2_MCFG) Sixteen Beat Burst Position */
+#define HMATRIX2_MCFG_Msk                     _UINT32_(0x00000007)                                 /* (HMATRIX2_MCFG) Register Mask  */
+
+
+/* -------- HMATRIX2_SCFG : (HMATRIX2 Offset: 0x40) (R/W 32) Slave Configuration -------- */
+#define HMATRIX2_SCFG_RESETVALUE              _UINT32_(0x10)                                       /*  (HMATRIX2_SCFG) Slave Configuration  Reset Value */
+
+#define HMATRIX2_SCFG_SLOT_CYCLE_Pos          _UINT32_(0)                                          /* (HMATRIX2_SCFG) Maximum Number of Allowed Cycles for a Burst Position */
+#define HMATRIX2_SCFG_SLOT_CYCLE_Msk          (_UINT32_(0x1FF) << HMATRIX2_SCFG_SLOT_CYCLE_Pos)    /* (HMATRIX2_SCFG) Maximum Number of Allowed Cycles for a Burst Mask */
+#define HMATRIX2_SCFG_SLOT_CYCLE(value)       (HMATRIX2_SCFG_SLOT_CYCLE_Msk & (_UINT32_(value) << HMATRIX2_SCFG_SLOT_CYCLE_Pos)) /* Assignment of value for SLOT_CYCLE in the HMATRIX2_SCFG register */
+#define HMATRIX2_SCFG_DEFMSTR_TYPE_Pos        _UINT32_(16)                                         /* (HMATRIX2_SCFG) Default Master Type Position */
+#define HMATRIX2_SCFG_DEFMSTR_TYPE_Msk        (_UINT32_(0x3) << HMATRIX2_SCFG_DEFMSTR_TYPE_Pos)    /* (HMATRIX2_SCFG) Default Master Type Mask */
+#define HMATRIX2_SCFG_DEFMSTR_TYPE(value)     (HMATRIX2_SCFG_DEFMSTR_TYPE_Msk & (_UINT32_(value) << HMATRIX2_SCFG_DEFMSTR_TYPE_Pos)) /* Assignment of value for DEFMSTR_TYPE in the HMATRIX2_SCFG register */
+#define   HMATRIX2_SCFG_DEFMSTR_TYPE_NO_DEFAULT_Val _UINT32_(0x0)                                        /* (HMATRIX2_SCFG) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.  */
+#define   HMATRIX2_SCFG_DEFMSTR_TYPE_LAST_DEFAULT_Val _UINT32_(0x1)                                        /* (HMATRIX2_SCFG) Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.  */
+#define   HMATRIX2_SCFG_DEFMSTR_TYPE_FIXED_DEFAULT_Val _UINT32_(0x2)                                        /* (HMATRIX2_SCFG) Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.  */
+#define HMATRIX2_SCFG_DEFMSTR_TYPE_NO_DEFAULT (HMATRIX2_SCFG_DEFMSTR_TYPE_NO_DEFAULT_Val << HMATRIX2_SCFG_DEFMSTR_TYPE_Pos) /* (HMATRIX2_SCFG) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. Position */
+#define HMATRIX2_SCFG_DEFMSTR_TYPE_LAST_DEFAULT (HMATRIX2_SCFG_DEFMSTR_TYPE_LAST_DEFAULT_Val << HMATRIX2_SCFG_DEFMSTR_TYPE_Pos) /* (HMATRIX2_SCFG) Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. Position */
+#define HMATRIX2_SCFG_DEFMSTR_TYPE_FIXED_DEFAULT (HMATRIX2_SCFG_DEFMSTR_TYPE_FIXED_DEFAULT_Val << HMATRIX2_SCFG_DEFMSTR_TYPE_Pos) /* (HMATRIX2_SCFG) Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. Position */
+#define HMATRIX2_SCFG_FIXED_DEFMSTR_Pos       _UINT32_(18)                                         /* (HMATRIX2_SCFG) Fixed Index of Default Master Position */
+#define HMATRIX2_SCFG_FIXED_DEFMSTR_Msk       (_UINT32_(0xF) << HMATRIX2_SCFG_FIXED_DEFMSTR_Pos)   /* (HMATRIX2_SCFG) Fixed Index of Default Master Mask */
+#define HMATRIX2_SCFG_FIXED_DEFMSTR(value)    (HMATRIX2_SCFG_FIXED_DEFMSTR_Msk & (_UINT32_(value) << HMATRIX2_SCFG_FIXED_DEFMSTR_Pos)) /* Assignment of value for FIXED_DEFMSTR in the HMATRIX2_SCFG register */
+#define HMATRIX2_SCFG_Msk                     _UINT32_(0x003F01FF)                                 /* (HMATRIX2_SCFG) Register Mask  */
+
+
+/* -------- HMATRIX2_MRCR : (HMATRIX2 Offset: 0x100) (R/W 32) Master Remap Control -------- */
+#define HMATRIX2_MRCR_RESETVALUE              _UINT32_(0x00)                                       /*  (HMATRIX2_MRCR) Master Remap Control  Reset Value */
+
+#define HMATRIX2_MRCR_RCB0_Pos                _UINT32_(0)                                          /* (HMATRIX2_MRCR) Remap Command Bit for Master 0 Position */
+#define HMATRIX2_MRCR_RCB0_Msk                (_UINT32_(0x1) << HMATRIX2_MRCR_RCB0_Pos)            /* (HMATRIX2_MRCR) Remap Command Bit for Master 0 Mask */
+#define HMATRIX2_MRCR_RCB0(value)             (HMATRIX2_MRCR_RCB0_Msk & (_UINT32_(value) << HMATRIX2_MRCR_RCB0_Pos)) /* Assignment of value for RCB0 in the HMATRIX2_MRCR register */
+#define   HMATRIX2_MRCR_RCB0_DIS_Val          _UINT32_(0x0)                                        /* (HMATRIX2_MRCR) Disable remapped address decoding for master  */
+#define   HMATRIX2_MRCR_RCB0_ENA_Val          _UINT32_(0x1)                                        /* (HMATRIX2_MRCR) Enable remapped address decoding for master  */
+#define HMATRIX2_MRCR_RCB0_DIS                (HMATRIX2_MRCR_RCB0_DIS_Val << HMATRIX2_MRCR_RCB0_Pos) /* (HMATRIX2_MRCR) Disable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB0_ENA                (HMATRIX2_MRCR_RCB0_ENA_Val << HMATRIX2_MRCR_RCB0_Pos) /* (HMATRIX2_MRCR) Enable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB1_Pos                _UINT32_(1)                                          /* (HMATRIX2_MRCR) Remap Command Bit for Master 1 Position */
+#define HMATRIX2_MRCR_RCB1_Msk                (_UINT32_(0x1) << HMATRIX2_MRCR_RCB1_Pos)            /* (HMATRIX2_MRCR) Remap Command Bit for Master 1 Mask */
+#define HMATRIX2_MRCR_RCB1(value)             (HMATRIX2_MRCR_RCB1_Msk & (_UINT32_(value) << HMATRIX2_MRCR_RCB1_Pos)) /* Assignment of value for RCB1 in the HMATRIX2_MRCR register */
+#define   HMATRIX2_MRCR_RCB1_DIS_Val          _UINT32_(0x0)                                        /* (HMATRIX2_MRCR) Disable remapped address decoding for master  */
+#define   HMATRIX2_MRCR_RCB1_ENA_Val          _UINT32_(0x1)                                        /* (HMATRIX2_MRCR) Enable remapped address decoding for master  */
+#define HMATRIX2_MRCR_RCB1_DIS                (HMATRIX2_MRCR_RCB1_DIS_Val << HMATRIX2_MRCR_RCB1_Pos) /* (HMATRIX2_MRCR) Disable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB1_ENA                (HMATRIX2_MRCR_RCB1_ENA_Val << HMATRIX2_MRCR_RCB1_Pos) /* (HMATRIX2_MRCR) Enable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB2_Pos                _UINT32_(2)                                          /* (HMATRIX2_MRCR) Remap Command Bit for Master 2 Position */
+#define HMATRIX2_MRCR_RCB2_Msk                (_UINT32_(0x1) << HMATRIX2_MRCR_RCB2_Pos)            /* (HMATRIX2_MRCR) Remap Command Bit for Master 2 Mask */
+#define HMATRIX2_MRCR_RCB2(value)             (HMATRIX2_MRCR_RCB2_Msk & (_UINT32_(value) << HMATRIX2_MRCR_RCB2_Pos)) /* Assignment of value for RCB2 in the HMATRIX2_MRCR register */
+#define   HMATRIX2_MRCR_RCB2_DIS_Val          _UINT32_(0x0)                                        /* (HMATRIX2_MRCR) Disable remapped address decoding for master  */
+#define   HMATRIX2_MRCR_RCB2_ENA_Val          _UINT32_(0x1)                                        /* (HMATRIX2_MRCR) Enable remapped address decoding for master  */
+#define HMATRIX2_MRCR_RCB2_DIS                (HMATRIX2_MRCR_RCB2_DIS_Val << HMATRIX2_MRCR_RCB2_Pos) /* (HMATRIX2_MRCR) Disable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB2_ENA                (HMATRIX2_MRCR_RCB2_ENA_Val << HMATRIX2_MRCR_RCB2_Pos) /* (HMATRIX2_MRCR) Enable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB3_Pos                _UINT32_(3)                                          /* (HMATRIX2_MRCR) Remap Command Bit for Master 3 Position */
+#define HMATRIX2_MRCR_RCB3_Msk                (_UINT32_(0x1) << HMATRIX2_MRCR_RCB3_Pos)            /* (HMATRIX2_MRCR) Remap Command Bit for Master 3 Mask */
+#define HMATRIX2_MRCR_RCB3(value)             (HMATRIX2_MRCR_RCB3_Msk & (_UINT32_(value) << HMATRIX2_MRCR_RCB3_Pos)) /* Assignment of value for RCB3 in the HMATRIX2_MRCR register */
+#define   HMATRIX2_MRCR_RCB3_DIS_Val          _UINT32_(0x0)                                        /* (HMATRIX2_MRCR) Disable remapped address decoding for master  */
+#define   HMATRIX2_MRCR_RCB3_ENA_Val          _UINT32_(0x1)                                        /* (HMATRIX2_MRCR) Enable remapped address decoding for master  */
+#define HMATRIX2_MRCR_RCB3_DIS                (HMATRIX2_MRCR_RCB3_DIS_Val << HMATRIX2_MRCR_RCB3_Pos) /* (HMATRIX2_MRCR) Disable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB3_ENA                (HMATRIX2_MRCR_RCB3_ENA_Val << HMATRIX2_MRCR_RCB3_Pos) /* (HMATRIX2_MRCR) Enable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB4_Pos                _UINT32_(4)                                          /* (HMATRIX2_MRCR) Remap Command Bit for Master 4 Position */
+#define HMATRIX2_MRCR_RCB4_Msk                (_UINT32_(0x1) << HMATRIX2_MRCR_RCB4_Pos)            /* (HMATRIX2_MRCR) Remap Command Bit for Master 4 Mask */
+#define HMATRIX2_MRCR_RCB4(value)             (HMATRIX2_MRCR_RCB4_Msk & (_UINT32_(value) << HMATRIX2_MRCR_RCB4_Pos)) /* Assignment of value for RCB4 in the HMATRIX2_MRCR register */
+#define   HMATRIX2_MRCR_RCB4_DIS_Val          _UINT32_(0x0)                                        /* (HMATRIX2_MRCR) Disable remapped address decoding for master  */
+#define   HMATRIX2_MRCR_RCB4_ENA_Val          _UINT32_(0x1)                                        /* (HMATRIX2_MRCR) Enable remapped address decoding for master  */
+#define HMATRIX2_MRCR_RCB4_DIS                (HMATRIX2_MRCR_RCB4_DIS_Val << HMATRIX2_MRCR_RCB4_Pos) /* (HMATRIX2_MRCR) Disable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB4_ENA                (HMATRIX2_MRCR_RCB4_ENA_Val << HMATRIX2_MRCR_RCB4_Pos) /* (HMATRIX2_MRCR) Enable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB5_Pos                _UINT32_(5)                                          /* (HMATRIX2_MRCR) Remap Command Bit for Master 5 Position */
+#define HMATRIX2_MRCR_RCB5_Msk                (_UINT32_(0x1) << HMATRIX2_MRCR_RCB5_Pos)            /* (HMATRIX2_MRCR) Remap Command Bit for Master 5 Mask */
+#define HMATRIX2_MRCR_RCB5(value)             (HMATRIX2_MRCR_RCB5_Msk & (_UINT32_(value) << HMATRIX2_MRCR_RCB5_Pos)) /* Assignment of value for RCB5 in the HMATRIX2_MRCR register */
+#define   HMATRIX2_MRCR_RCB5_DIS_Val          _UINT32_(0x0)                                        /* (HMATRIX2_MRCR) Disable remapped address decoding for master  */
+#define   HMATRIX2_MRCR_RCB5_ENA_Val          _UINT32_(0x1)                                        /* (HMATRIX2_MRCR) Enable remapped address decoding for master  */
+#define HMATRIX2_MRCR_RCB5_DIS                (HMATRIX2_MRCR_RCB5_DIS_Val << HMATRIX2_MRCR_RCB5_Pos) /* (HMATRIX2_MRCR) Disable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_RCB5_ENA                (HMATRIX2_MRCR_RCB5_ENA_Val << HMATRIX2_MRCR_RCB5_Pos) /* (HMATRIX2_MRCR) Enable remapped address decoding for master Position */
+#define HMATRIX2_MRCR_Msk                     _UINT32_(0x0000003F)                                 /* (HMATRIX2_MRCR) Register Mask  */
+
+#define HMATRIX2_MRCR_RCB_Pos                 _UINT32_(0)                                          /* (HMATRIX2_MRCR Position) Remap Command Bit for Master 5 */
+#define HMATRIX2_MRCR_RCB_Msk                 (_UINT32_(0x3F) << HMATRIX2_MRCR_RCB_Pos)            /* (HMATRIX2_MRCR Mask) RCB */
+#define HMATRIX2_MRCR_RCB(value)              (HMATRIX2_MRCR_RCB_Msk & (_UINT32_(value) << HMATRIX2_MRCR_RCB_Pos)) 
+
+/* -------- HMATRIX2_SFR : (HMATRIX2 Offset: 0x110) (R/W 32) Special Function -------- */
+#define HMATRIX2_SFR_RESETVALUE               _UINT32_(0x00)                                       /*  (HMATRIX2_SFR) Special Function  Reset Value */
+
+#define HMATRIX2_SFR_SFR_Pos                  _UINT32_(0)                                          /* (HMATRIX2_SFR) Special Function Register Position */
+#define HMATRIX2_SFR_SFR_Msk                  (_UINT32_(0xFFFFFFFF) << HMATRIX2_SFR_SFR_Pos)       /* (HMATRIX2_SFR) Special Function Register Mask */
+#define HMATRIX2_SFR_SFR(value)               (HMATRIX2_SFR_SFR_Msk & (_UINT32_(value) << HMATRIX2_SFR_SFR_Pos)) /* Assignment of value for SFR in the HMATRIX2_SFR register */
+#define HMATRIX2_SFR_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (HMATRIX2_SFR) Register Mask  */
+
+
+/* -------- HMATRIX2_MEIER : (HMATRIX2 Offset: 0x150) ( /W 32) Master Error Interrupt Enable -------- */
+#define HMATRIX2_MEIER_MERR0_Pos              _UINT32_(0)                                          /* (HMATRIX2_MEIER) Master 0 Access Error Position */
+#define HMATRIX2_MEIER_MERR0_Msk              (_UINT32_(0x1) << HMATRIX2_MEIER_MERR0_Pos)          /* (HMATRIX2_MEIER) Master 0 Access Error Mask */
+#define HMATRIX2_MEIER_MERR0(value)           (HMATRIX2_MEIER_MERR0_Msk & (_UINT32_(value) << HMATRIX2_MEIER_MERR0_Pos)) /* Assignment of value for MERR0 in the HMATRIX2_MEIER register */
+#define HMATRIX2_MEIER_MERR1_Pos              _UINT32_(1)                                          /* (HMATRIX2_MEIER) Master 1 Access Error Position */
+#define HMATRIX2_MEIER_MERR1_Msk              (_UINT32_(0x1) << HMATRIX2_MEIER_MERR1_Pos)          /* (HMATRIX2_MEIER) Master 1 Access Error Mask */
+#define HMATRIX2_MEIER_MERR1(value)           (HMATRIX2_MEIER_MERR1_Msk & (_UINT32_(value) << HMATRIX2_MEIER_MERR1_Pos)) /* Assignment of value for MERR1 in the HMATRIX2_MEIER register */
+#define HMATRIX2_MEIER_MERR2_Pos              _UINT32_(2)                                          /* (HMATRIX2_MEIER) Master 2 Access Error Position */
+#define HMATRIX2_MEIER_MERR2_Msk              (_UINT32_(0x1) << HMATRIX2_MEIER_MERR2_Pos)          /* (HMATRIX2_MEIER) Master 2 Access Error Mask */
+#define HMATRIX2_MEIER_MERR2(value)           (HMATRIX2_MEIER_MERR2_Msk & (_UINT32_(value) << HMATRIX2_MEIER_MERR2_Pos)) /* Assignment of value for MERR2 in the HMATRIX2_MEIER register */
+#define HMATRIX2_MEIER_MERR3_Pos              _UINT32_(3)                                          /* (HMATRIX2_MEIER) Master 3 Access Error Position */
+#define HMATRIX2_MEIER_MERR3_Msk              (_UINT32_(0x1) << HMATRIX2_MEIER_MERR3_Pos)          /* (HMATRIX2_MEIER) Master 3 Access Error Mask */
+#define HMATRIX2_MEIER_MERR3(value)           (HMATRIX2_MEIER_MERR3_Msk & (_UINT32_(value) << HMATRIX2_MEIER_MERR3_Pos)) /* Assignment of value for MERR3 in the HMATRIX2_MEIER register */
+#define HMATRIX2_MEIER_MERR4_Pos              _UINT32_(4)                                          /* (HMATRIX2_MEIER) Master 4 Access Error Position */
+#define HMATRIX2_MEIER_MERR4_Msk              (_UINT32_(0x1) << HMATRIX2_MEIER_MERR4_Pos)          /* (HMATRIX2_MEIER) Master 4 Access Error Mask */
+#define HMATRIX2_MEIER_MERR4(value)           (HMATRIX2_MEIER_MERR4_Msk & (_UINT32_(value) << HMATRIX2_MEIER_MERR4_Pos)) /* Assignment of value for MERR4 in the HMATRIX2_MEIER register */
+#define HMATRIX2_MEIER_MERR5_Pos              _UINT32_(5)                                          /* (HMATRIX2_MEIER) Master 5 Access Error Position */
+#define HMATRIX2_MEIER_MERR5_Msk              (_UINT32_(0x1) << HMATRIX2_MEIER_MERR5_Pos)          /* (HMATRIX2_MEIER) Master 5 Access Error Mask */
+#define HMATRIX2_MEIER_MERR5(value)           (HMATRIX2_MEIER_MERR5_Msk & (_UINT32_(value) << HMATRIX2_MEIER_MERR5_Pos)) /* Assignment of value for MERR5 in the HMATRIX2_MEIER register */
+#define HMATRIX2_MEIER_Msk                    _UINT32_(0x0000003F)                                 /* (HMATRIX2_MEIER) Register Mask  */
+
+#define HMATRIX2_MEIER_MERR_Pos               _UINT32_(0)                                          /* (HMATRIX2_MEIER Position) Master 5 Access Error */
+#define HMATRIX2_MEIER_MERR_Msk               (_UINT32_(0x3F) << HMATRIX2_MEIER_MERR_Pos)          /* (HMATRIX2_MEIER Mask) MERR */
+#define HMATRIX2_MEIER_MERR(value)            (HMATRIX2_MEIER_MERR_Msk & (_UINT32_(value) << HMATRIX2_MEIER_MERR_Pos)) 
+
+/* -------- HMATRIX2_MEIDR : (HMATRIX2 Offset: 0x154) ( /W 32) Master Error Interrupt Disable -------- */
+#define HMATRIX2_MEIDR_MERR0_Pos              _UINT32_(0)                                          /* (HMATRIX2_MEIDR) Master 0 Access Error Position */
+#define HMATRIX2_MEIDR_MERR0_Msk              (_UINT32_(0x1) << HMATRIX2_MEIDR_MERR0_Pos)          /* (HMATRIX2_MEIDR) Master 0 Access Error Mask */
+#define HMATRIX2_MEIDR_MERR0(value)           (HMATRIX2_MEIDR_MERR0_Msk & (_UINT32_(value) << HMATRIX2_MEIDR_MERR0_Pos)) /* Assignment of value for MERR0 in the HMATRIX2_MEIDR register */
+#define HMATRIX2_MEIDR_MERR1_Pos              _UINT32_(1)                                          /* (HMATRIX2_MEIDR) Master 1 Access Error Position */
+#define HMATRIX2_MEIDR_MERR1_Msk              (_UINT32_(0x1) << HMATRIX2_MEIDR_MERR1_Pos)          /* (HMATRIX2_MEIDR) Master 1 Access Error Mask */
+#define HMATRIX2_MEIDR_MERR1(value)           (HMATRIX2_MEIDR_MERR1_Msk & (_UINT32_(value) << HMATRIX2_MEIDR_MERR1_Pos)) /* Assignment of value for MERR1 in the HMATRIX2_MEIDR register */
+#define HMATRIX2_MEIDR_MERR2_Pos              _UINT32_(2)                                          /* (HMATRIX2_MEIDR) Master 2 Access Error Position */
+#define HMATRIX2_MEIDR_MERR2_Msk              (_UINT32_(0x1) << HMATRIX2_MEIDR_MERR2_Pos)          /* (HMATRIX2_MEIDR) Master 2 Access Error Mask */
+#define HMATRIX2_MEIDR_MERR2(value)           (HMATRIX2_MEIDR_MERR2_Msk & (_UINT32_(value) << HMATRIX2_MEIDR_MERR2_Pos)) /* Assignment of value for MERR2 in the HMATRIX2_MEIDR register */
+#define HMATRIX2_MEIDR_MERR3_Pos              _UINT32_(3)                                          /* (HMATRIX2_MEIDR) Master 3 Access Error Position */
+#define HMATRIX2_MEIDR_MERR3_Msk              (_UINT32_(0x1) << HMATRIX2_MEIDR_MERR3_Pos)          /* (HMATRIX2_MEIDR) Master 3 Access Error Mask */
+#define HMATRIX2_MEIDR_MERR3(value)           (HMATRIX2_MEIDR_MERR3_Msk & (_UINT32_(value) << HMATRIX2_MEIDR_MERR3_Pos)) /* Assignment of value for MERR3 in the HMATRIX2_MEIDR register */
+#define HMATRIX2_MEIDR_MERR4_Pos              _UINT32_(4)                                          /* (HMATRIX2_MEIDR) Master 4 Access Error Position */
+#define HMATRIX2_MEIDR_MERR4_Msk              (_UINT32_(0x1) << HMATRIX2_MEIDR_MERR4_Pos)          /* (HMATRIX2_MEIDR) Master 4 Access Error Mask */
+#define HMATRIX2_MEIDR_MERR4(value)           (HMATRIX2_MEIDR_MERR4_Msk & (_UINT32_(value) << HMATRIX2_MEIDR_MERR4_Pos)) /* Assignment of value for MERR4 in the HMATRIX2_MEIDR register */
+#define HMATRIX2_MEIDR_MERR5_Pos              _UINT32_(5)                                          /* (HMATRIX2_MEIDR) Master 5 Access Error Position */
+#define HMATRIX2_MEIDR_MERR5_Msk              (_UINT32_(0x1) << HMATRIX2_MEIDR_MERR5_Pos)          /* (HMATRIX2_MEIDR) Master 5 Access Error Mask */
+#define HMATRIX2_MEIDR_MERR5(value)           (HMATRIX2_MEIDR_MERR5_Msk & (_UINT32_(value) << HMATRIX2_MEIDR_MERR5_Pos)) /* Assignment of value for MERR5 in the HMATRIX2_MEIDR register */
+#define HMATRIX2_MEIDR_Msk                    _UINT32_(0x0000003F)                                 /* (HMATRIX2_MEIDR) Register Mask  */
+
+#define HMATRIX2_MEIDR_MERR_Pos               _UINT32_(0)                                          /* (HMATRIX2_MEIDR Position) Master 5 Access Error */
+#define HMATRIX2_MEIDR_MERR_Msk               (_UINT32_(0x3F) << HMATRIX2_MEIDR_MERR_Pos)          /* (HMATRIX2_MEIDR Mask) MERR */
+#define HMATRIX2_MEIDR_MERR(value)            (HMATRIX2_MEIDR_MERR_Msk & (_UINT32_(value) << HMATRIX2_MEIDR_MERR_Pos)) 
+
+/* -------- HMATRIX2_MEIMR : (HMATRIX2 Offset: 0x158) ( R/ 32) Master Error Interrupt Mask -------- */
+#define HMATRIX2_MEIMR_MERR0_Pos              _UINT32_(0)                                          /* (HMATRIX2_MEIMR) Master 0 Access Error Position */
+#define HMATRIX2_MEIMR_MERR0_Msk              (_UINT32_(0x1) << HMATRIX2_MEIMR_MERR0_Pos)          /* (HMATRIX2_MEIMR) Master 0 Access Error Mask */
+#define HMATRIX2_MEIMR_MERR0(value)           (HMATRIX2_MEIMR_MERR0_Msk & (_UINT32_(value) << HMATRIX2_MEIMR_MERR0_Pos)) /* Assignment of value for MERR0 in the HMATRIX2_MEIMR register */
+#define HMATRIX2_MEIMR_MERR1_Pos              _UINT32_(1)                                          /* (HMATRIX2_MEIMR) Master 1 Access Error Position */
+#define HMATRIX2_MEIMR_MERR1_Msk              (_UINT32_(0x1) << HMATRIX2_MEIMR_MERR1_Pos)          /* (HMATRIX2_MEIMR) Master 1 Access Error Mask */
+#define HMATRIX2_MEIMR_MERR1(value)           (HMATRIX2_MEIMR_MERR1_Msk & (_UINT32_(value) << HMATRIX2_MEIMR_MERR1_Pos)) /* Assignment of value for MERR1 in the HMATRIX2_MEIMR register */
+#define HMATRIX2_MEIMR_MERR2_Pos              _UINT32_(2)                                          /* (HMATRIX2_MEIMR) Master 2 Access Error Position */
+#define HMATRIX2_MEIMR_MERR2_Msk              (_UINT32_(0x1) << HMATRIX2_MEIMR_MERR2_Pos)          /* (HMATRIX2_MEIMR) Master 2 Access Error Mask */
+#define HMATRIX2_MEIMR_MERR2(value)           (HMATRIX2_MEIMR_MERR2_Msk & (_UINT32_(value) << HMATRIX2_MEIMR_MERR2_Pos)) /* Assignment of value for MERR2 in the HMATRIX2_MEIMR register */
+#define HMATRIX2_MEIMR_MERR3_Pos              _UINT32_(3)                                          /* (HMATRIX2_MEIMR) Master 3 Access Error Position */
+#define HMATRIX2_MEIMR_MERR3_Msk              (_UINT32_(0x1) << HMATRIX2_MEIMR_MERR3_Pos)          /* (HMATRIX2_MEIMR) Master 3 Access Error Mask */
+#define HMATRIX2_MEIMR_MERR3(value)           (HMATRIX2_MEIMR_MERR3_Msk & (_UINT32_(value) << HMATRIX2_MEIMR_MERR3_Pos)) /* Assignment of value for MERR3 in the HMATRIX2_MEIMR register */
+#define HMATRIX2_MEIMR_MERR4_Pos              _UINT32_(4)                                          /* (HMATRIX2_MEIMR) Master 4 Access Error Position */
+#define HMATRIX2_MEIMR_MERR4_Msk              (_UINT32_(0x1) << HMATRIX2_MEIMR_MERR4_Pos)          /* (HMATRIX2_MEIMR) Master 4 Access Error Mask */
+#define HMATRIX2_MEIMR_MERR4(value)           (HMATRIX2_MEIMR_MERR4_Msk & (_UINT32_(value) << HMATRIX2_MEIMR_MERR4_Pos)) /* Assignment of value for MERR4 in the HMATRIX2_MEIMR register */
+#define HMATRIX2_MEIMR_MERR5_Pos              _UINT32_(5)                                          /* (HMATRIX2_MEIMR) Master 5 Access Error Position */
+#define HMATRIX2_MEIMR_MERR5_Msk              (_UINT32_(0x1) << HMATRIX2_MEIMR_MERR5_Pos)          /* (HMATRIX2_MEIMR) Master 5 Access Error Mask */
+#define HMATRIX2_MEIMR_MERR5(value)           (HMATRIX2_MEIMR_MERR5_Msk & (_UINT32_(value) << HMATRIX2_MEIMR_MERR5_Pos)) /* Assignment of value for MERR5 in the HMATRIX2_MEIMR register */
+#define HMATRIX2_MEIMR_Msk                    _UINT32_(0x0000003F)                                 /* (HMATRIX2_MEIMR) Register Mask  */
+
+#define HMATRIX2_MEIMR_MERR_Pos               _UINT32_(0)                                          /* (HMATRIX2_MEIMR Position) Master 5 Access Error */
+#define HMATRIX2_MEIMR_MERR_Msk               (_UINT32_(0x3F) << HMATRIX2_MEIMR_MERR_Pos)          /* (HMATRIX2_MEIMR Mask) MERR */
+#define HMATRIX2_MEIMR_MERR(value)            (HMATRIX2_MEIMR_MERR_Msk & (_UINT32_(value) << HMATRIX2_MEIMR_MERR_Pos)) 
+
+/* -------- HMATRIX2_MESR : (HMATRIX2 Offset: 0x15C) ( R/ 32) Master Error Status -------- */
+#define HMATRIX2_MESR_MERR0_Pos               _UINT32_(0)                                          /* (HMATRIX2_MESR) Master 0 Access Error Position */
+#define HMATRIX2_MESR_MERR0_Msk               (_UINT32_(0x1) << HMATRIX2_MESR_MERR0_Pos)           /* (HMATRIX2_MESR) Master 0 Access Error Mask */
+#define HMATRIX2_MESR_MERR0(value)            (HMATRIX2_MESR_MERR0_Msk & (_UINT32_(value) << HMATRIX2_MESR_MERR0_Pos)) /* Assignment of value for MERR0 in the HMATRIX2_MESR register */
+#define HMATRIX2_MESR_MERR1_Pos               _UINT32_(1)                                          /* (HMATRIX2_MESR) Master 1 Access Error Position */
+#define HMATRIX2_MESR_MERR1_Msk               (_UINT32_(0x1) << HMATRIX2_MESR_MERR1_Pos)           /* (HMATRIX2_MESR) Master 1 Access Error Mask */
+#define HMATRIX2_MESR_MERR1(value)            (HMATRIX2_MESR_MERR1_Msk & (_UINT32_(value) << HMATRIX2_MESR_MERR1_Pos)) /* Assignment of value for MERR1 in the HMATRIX2_MESR register */
+#define HMATRIX2_MESR_MERR2_Pos               _UINT32_(2)                                          /* (HMATRIX2_MESR) Master 2 Access Error Position */
+#define HMATRIX2_MESR_MERR2_Msk               (_UINT32_(0x1) << HMATRIX2_MESR_MERR2_Pos)           /* (HMATRIX2_MESR) Master 2 Access Error Mask */
+#define HMATRIX2_MESR_MERR2(value)            (HMATRIX2_MESR_MERR2_Msk & (_UINT32_(value) << HMATRIX2_MESR_MERR2_Pos)) /* Assignment of value for MERR2 in the HMATRIX2_MESR register */
+#define HMATRIX2_MESR_MERR3_Pos               _UINT32_(3)                                          /* (HMATRIX2_MESR) Master 3 Access Error Position */
+#define HMATRIX2_MESR_MERR3_Msk               (_UINT32_(0x1) << HMATRIX2_MESR_MERR3_Pos)           /* (HMATRIX2_MESR) Master 3 Access Error Mask */
+#define HMATRIX2_MESR_MERR3(value)            (HMATRIX2_MESR_MERR3_Msk & (_UINT32_(value) << HMATRIX2_MESR_MERR3_Pos)) /* Assignment of value for MERR3 in the HMATRIX2_MESR register */
+#define HMATRIX2_MESR_MERR4_Pos               _UINT32_(4)                                          /* (HMATRIX2_MESR) Master 4 Access Error Position */
+#define HMATRIX2_MESR_MERR4_Msk               (_UINT32_(0x1) << HMATRIX2_MESR_MERR4_Pos)           /* (HMATRIX2_MESR) Master 4 Access Error Mask */
+#define HMATRIX2_MESR_MERR4(value)            (HMATRIX2_MESR_MERR4_Msk & (_UINT32_(value) << HMATRIX2_MESR_MERR4_Pos)) /* Assignment of value for MERR4 in the HMATRIX2_MESR register */
+#define HMATRIX2_MESR_MERR5_Pos               _UINT32_(5)                                          /* (HMATRIX2_MESR) Master 5 Access Error Position */
+#define HMATRIX2_MESR_MERR5_Msk               (_UINT32_(0x1) << HMATRIX2_MESR_MERR5_Pos)           /* (HMATRIX2_MESR) Master 5 Access Error Mask */
+#define HMATRIX2_MESR_MERR5(value)            (HMATRIX2_MESR_MERR5_Msk & (_UINT32_(value) << HMATRIX2_MESR_MERR5_Pos)) /* Assignment of value for MERR5 in the HMATRIX2_MESR register */
+#define HMATRIX2_MESR_Msk                     _UINT32_(0x0000003F)                                 /* (HMATRIX2_MESR) Register Mask  */
+
+#define HMATRIX2_MESR_MERR_Pos                _UINT32_(0)                                          /* (HMATRIX2_MESR Position) Master 5 Access Error */
+#define HMATRIX2_MESR_MERR_Msk                (_UINT32_(0x3F) << HMATRIX2_MESR_MERR_Pos)           /* (HMATRIX2_MESR Mask) MERR */
+#define HMATRIX2_MESR_MERR(value)             (HMATRIX2_MESR_MERR_Msk & (_UINT32_(value) << HMATRIX2_MESR_MERR_Pos)) 
+
+/* -------- HMATRIX2_MEAR : (HMATRIX2 Offset: 0x160) ( R/ 32) Master Error Address -------- */
+#define HMATRIX2_MEAR_Msk                     _UINT32_(0x00000000)                                 /* (HMATRIX2_MEAR) Register Mask  */
+
+
+/* HMATRIX2 register offsets definitions */
+#define HMATRIX2_PRAS_REG_OFST         _UINT32_(0x00)      /* (HMATRIX2_PRAS) Priority A for Slave Offset */
+#define HMATRIX2_MCFG_REG_OFST         _UINT32_(0x00)      /* (HMATRIX2_MCFG) Master Configuration Offset */
+#define HMATRIX2_MCFG0_REG_OFST        _UINT32_(0x00)      /* (HMATRIX2_MCFG0) Master Configuration Offset */
+#define HMATRIX2_MCFG1_REG_OFST        _UINT32_(0x04)      /* (HMATRIX2_MCFG1) Master Configuration Offset */
+#define HMATRIX2_MCFG2_REG_OFST        _UINT32_(0x08)      /* (HMATRIX2_MCFG2) Master Configuration Offset */
+#define HMATRIX2_MCFG3_REG_OFST        _UINT32_(0x0C)      /* (HMATRIX2_MCFG3) Master Configuration Offset */
+#define HMATRIX2_MCFG4_REG_OFST        _UINT32_(0x10)      /* (HMATRIX2_MCFG4) Master Configuration Offset */
+#define HMATRIX2_MCFG5_REG_OFST        _UINT32_(0x14)      /* (HMATRIX2_MCFG5) Master Configuration Offset */
+#define HMATRIX2_SCFG_REG_OFST         _UINT32_(0x40)      /* (HMATRIX2_SCFG) Slave Configuration Offset */
+#define HMATRIX2_SCFG0_REG_OFST        _UINT32_(0x40)      /* (HMATRIX2_SCFG0) Slave Configuration Offset */
+#define HMATRIX2_SCFG1_REG_OFST        _UINT32_(0x44)      /* (HMATRIX2_SCFG1) Slave Configuration Offset */
+#define HMATRIX2_SCFG2_REG_OFST        _UINT32_(0x48)      /* (HMATRIX2_SCFG2) Slave Configuration Offset */
+#define HMATRIX2_SCFG3_REG_OFST        _UINT32_(0x4C)      /* (HMATRIX2_SCFG3) Slave Configuration Offset */
+#define HMATRIX2_SCFG4_REG_OFST        _UINT32_(0x50)      /* (HMATRIX2_SCFG4) Slave Configuration Offset */
+#define HMATRIX2_SCFG5_REG_OFST        _UINT32_(0x54)      /* (HMATRIX2_SCFG5) Slave Configuration Offset */
+#define HMATRIX2_SCFG6_REG_OFST        _UINT32_(0x58)      /* (HMATRIX2_SCFG6) Slave Configuration Offset */
+#define HMATRIX2_SCFG7_REG_OFST        _UINT32_(0x5C)      /* (HMATRIX2_SCFG7) Slave Configuration Offset */
+#define HMATRIX2_SCFG8_REG_OFST        _UINT32_(0x60)      /* (HMATRIX2_SCFG8) Slave Configuration Offset */
+#define HMATRIX2_MRCR_REG_OFST         _UINT32_(0x100)     /* (HMATRIX2_MRCR) Master Remap Control Offset */
+#define HMATRIX2_SFR_REG_OFST          _UINT32_(0x110)     /* (HMATRIX2_SFR) Special Function Offset */
+#define HMATRIX2_SFR0_REG_OFST         _UINT32_(0x110)     /* (HMATRIX2_SFR0) Special Function Offset */
+#define HMATRIX2_SFR1_REG_OFST         _UINT32_(0x114)     /* (HMATRIX2_SFR1) Special Function Offset */
+#define HMATRIX2_SFR2_REG_OFST         _UINT32_(0x118)     /* (HMATRIX2_SFR2) Special Function Offset */
+#define HMATRIX2_SFR3_REG_OFST         _UINT32_(0x11C)     /* (HMATRIX2_SFR3) Special Function Offset */
+#define HMATRIX2_SFR4_REG_OFST         _UINT32_(0x120)     /* (HMATRIX2_SFR4) Special Function Offset */
+#define HMATRIX2_SFR5_REG_OFST         _UINT32_(0x124)     /* (HMATRIX2_SFR5) Special Function Offset */
+#define HMATRIX2_SFR6_REG_OFST         _UINT32_(0x128)     /* (HMATRIX2_SFR6) Special Function Offset */
+#define HMATRIX2_SFR7_REG_OFST         _UINT32_(0x12C)     /* (HMATRIX2_SFR7) Special Function Offset */
+#define HMATRIX2_SFR8_REG_OFST         _UINT32_(0x130)     /* (HMATRIX2_SFR8) Special Function Offset */
+#define HMATRIX2_MEIER_REG_OFST        _UINT32_(0x150)     /* (HMATRIX2_MEIER) Master Error Interrupt Enable Offset */
+#define HMATRIX2_MEIDR_REG_OFST        _UINT32_(0x154)     /* (HMATRIX2_MEIDR) Master Error Interrupt Disable Offset */
+#define HMATRIX2_MEIMR_REG_OFST        _UINT32_(0x158)     /* (HMATRIX2_MEIMR) Master Error Interrupt Mask Offset */
+#define HMATRIX2_MESR_REG_OFST         _UINT32_(0x15C)     /* (HMATRIX2_MESR) Master Error Status Offset */
+#define HMATRIX2_MEAR_REG_OFST         _UINT32_(0x160)     /* (HMATRIX2_MEAR) Master Error Address Offset */
+#define HMATRIX2_MEAR0_REG_OFST        _UINT32_(0x160)     /* (HMATRIX2_MEAR0) Master Error Address Offset */
+#define HMATRIX2_MEAR1_REG_OFST        _UINT32_(0x164)     /* (HMATRIX2_MEAR1) Master Error Address Offset */
+#define HMATRIX2_MEAR2_REG_OFST        _UINT32_(0x168)     /* (HMATRIX2_MEAR2) Master Error Address Offset */
+#define HMATRIX2_MEAR3_REG_OFST        _UINT32_(0x16C)     /* (HMATRIX2_MEAR3) Master Error Address Offset */
+#define HMATRIX2_MEAR4_REG_OFST        _UINT32_(0x170)     /* (HMATRIX2_MEAR4) Master Error Address Offset */
+#define HMATRIX2_MEAR5_REG_OFST        _UINT32_(0x174)     /* (HMATRIX2_MEAR5) Master Error Address Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* PRS register API structure */
+typedef struct
+{
+  __IO  uint32_t                       HMATRIX2_PRAS;      /* Offset: 0x00 (R/W  32) Priority A for Slave */
+  __I   uint8_t                        Reserved1[0x04];
+} hmatrix2_prs_registers_t;
+
+#define HMATRIX2_PRS_NUMBER 9
+
+/* HMATRIX2 register API structure */
+typedef struct
+{  /* HSB Matrix */
+  __IO  uint32_t                       HMATRIX2_MCFG[6];   /* Offset: 0x00 (R/W  32) Master Configuration */
+  __I   uint8_t                        Reserved1[0x28];
+  __IO  uint32_t                       HMATRIX2_SCFG[9];   /* Offset: 0x40 (R/W  32) Slave Configuration */
+  __I   uint8_t                        Reserved2[0x1C];
+        hmatrix2_prs_registers_t       PRS[HMATRIX2_PRS_NUMBER]; /* Offset: 0x80  */
+  __I   uint8_t                        Reserved3[0x38];
+  __IO  uint32_t                       HMATRIX2_MRCR;      /* Offset: 0x100 (R/W  32) Master Remap Control */
+  __I   uint8_t                        Reserved4[0x0C];
+  __IO  uint32_t                       HMATRIX2_SFR[9];    /* Offset: 0x110 (R/W  32) Special Function */
+  __I   uint8_t                        Reserved5[0x1C];
+  __O   uint32_t                       HMATRIX2_MEIER;     /* Offset: 0x150 ( /W  32) Master Error Interrupt Enable */
+  __O   uint32_t                       HMATRIX2_MEIDR;     /* Offset: 0x154 ( /W  32) Master Error Interrupt Disable */
+  __I   uint32_t                       HMATRIX2_MEIMR;     /* Offset: 0x158 (R/   32) Master Error Interrupt Mask */
+  __I   uint32_t                       HMATRIX2_MESR;      /* Offset: 0x15C (R/   32) Master Error Status */
+  __I   uint32_t                       HMATRIX2_MEAR[6];   /* Offset: 0x160 (R/   32) Master Error Address */
+} hmatrix2_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_HMATRIX2_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/mclk.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/mclk.h
new file mode 100644
index 00000000..ee3792cd
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/mclk.h
@@ -0,0 +1,356 @@
+/*
+ * Component description for MCLK
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_MCLK_COMPONENT_H_
+#define _PIC32CMGC00_MCLK_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR MCLK                      */
+/* ************************************************************************** */
+
+/* -------- MCLK_INTENCLR : (MCLK Offset: 0x00) (R/W 32) Interrupt Enable Clear Register -------- */
+#define MCLK_INTENCLR_RESETVALUE              _UINT32_(0x00)                                       /*  (MCLK_INTENCLR) Interrupt Enable Clear Register  Reset Value */
+
+#define MCLK_INTENCLR_CKRDY_Pos               _UINT32_(0)                                          /* (MCLK_INTENCLR) Clock Ready Interrupt Enable Clear Position */
+#define MCLK_INTENCLR_CKRDY_Msk               (_UINT32_(0x1) << MCLK_INTENCLR_CKRDY_Pos)           /* (MCLK_INTENCLR) Clock Ready Interrupt Enable Clear Mask */
+#define MCLK_INTENCLR_CKRDY(value)            (MCLK_INTENCLR_CKRDY_Msk & (_UINT32_(value) << MCLK_INTENCLR_CKRDY_Pos)) /* Assignment of value for CKRDY in the MCLK_INTENCLR register */
+#define   MCLK_INTENCLR_CKRDY_0_Val           _UINT32_(0x0)                                        /* (MCLK_INTENCLR) The Clock Ready interrupt is disabled  */
+#define   MCLK_INTENCLR_CKRDY_1_Val           _UINT32_(0x1)                                        /* (MCLK_INTENCLR) The Clock Ready interrupt is enabled.  */
+#define MCLK_INTENCLR_CKRDY_0                 (MCLK_INTENCLR_CKRDY_0_Val << MCLK_INTENCLR_CKRDY_Pos) /* (MCLK_INTENCLR) The Clock Ready interrupt is disabled Position */
+#define MCLK_INTENCLR_CKRDY_1                 (MCLK_INTENCLR_CKRDY_1_Val << MCLK_INTENCLR_CKRDY_Pos) /* (MCLK_INTENCLR) The Clock Ready interrupt is enabled. Position */
+#define MCLK_INTENCLR_Msk                     _UINT32_(0x00000001)                                 /* (MCLK_INTENCLR) Register Mask  */
+
+
+/* -------- MCLK_INTENSET : (MCLK Offset: 0x04) (R/W 32) Interrupt Enable Set Register -------- */
+#define MCLK_INTENSET_RESETVALUE              _UINT32_(0x00)                                       /*  (MCLK_INTENSET) Interrupt Enable Set Register  Reset Value */
+
+#define MCLK_INTENSET_CKRDY_Pos               _UINT32_(0)                                          /* (MCLK_INTENSET) Clock Ready Interrupt Enable Set Position */
+#define MCLK_INTENSET_CKRDY_Msk               (_UINT32_(0x1) << MCLK_INTENSET_CKRDY_Pos)           /* (MCLK_INTENSET) Clock Ready Interrupt Enable Set Mask */
+#define MCLK_INTENSET_CKRDY(value)            (MCLK_INTENSET_CKRDY_Msk & (_UINT32_(value) << MCLK_INTENSET_CKRDY_Pos)) /* Assignment of value for CKRDY in the MCLK_INTENSET register */
+#define   MCLK_INTENSET_CKRDY_0_Val           _UINT32_(0x0)                                        /* (MCLK_INTENSET) The Clock Ready interrupt is disabled.  */
+#define   MCLK_INTENSET_CKRDY_1_Val           _UINT32_(0x1)                                        /* (MCLK_INTENSET) The Clock Ready interrupt is enabled.  */
+#define MCLK_INTENSET_CKRDY_0                 (MCLK_INTENSET_CKRDY_0_Val << MCLK_INTENSET_CKRDY_Pos) /* (MCLK_INTENSET) The Clock Ready interrupt is disabled. Position */
+#define MCLK_INTENSET_CKRDY_1                 (MCLK_INTENSET_CKRDY_1_Val << MCLK_INTENSET_CKRDY_Pos) /* (MCLK_INTENSET) The Clock Ready interrupt is enabled. Position */
+#define MCLK_INTENSET_Msk                     _UINT32_(0x00000001)                                 /* (MCLK_INTENSET) Register Mask  */
+
+
+/* -------- MCLK_INTFLAG : (MCLK Offset: 0x08) ( /W 32) Interrupt Flag Status Register -------- */
+#define MCLK_INTFLAG_RESETVALUE               _UINT32_(0x01)                                       /*  (MCLK_INTFLAG) Interrupt Flag Status Register  Reset Value */
+
+#define MCLK_INTFLAG_CKRDY_Pos                _UINT32_(0)                                          /* (MCLK_INTFLAG) Clock Ready Interrupt Flag Position */
+#define MCLK_INTFLAG_CKRDY_Msk                (_UINT32_(0x1) << MCLK_INTFLAG_CKRDY_Pos)            /* (MCLK_INTFLAG) Clock Ready Interrupt Flag Mask */
+#define MCLK_INTFLAG_CKRDY(value)             (MCLK_INTFLAG_CKRDY_Msk & (_UINT32_(value) << MCLK_INTFLAG_CKRDY_Pos)) /* Assignment of value for CKRDY in the MCLK_INTFLAG register */
+#define MCLK_INTFLAG_Msk                      _UINT32_(0x00000001)                                 /* (MCLK_INTFLAG) Register Mask  */
+
+
+/* -------- MCLK_CLKDIV : (MCLK Offset: 0x0C) (R/W 32) Clock Divider Control n Register -------- */
+#define MCLK_CLKDIV_RESETVALUE                _UINT32_(0x00)                                       /*  (MCLK_CLKDIV) Clock Divider Control n Register  Reset Value */
+
+#define MCLK_CLKDIV_DIV_Pos                   _UINT32_(0)                                          /* (MCLK_CLKDIV) Clock Domain n Division Factor Position */
+#define MCLK_CLKDIV_DIV_Msk                   (_UINT32_(0xFF) << MCLK_CLKDIV_DIV_Pos)              /* (MCLK_CLKDIV) Clock Domain n Division Factor Mask */
+#define MCLK_CLKDIV_DIV(value)                (MCLK_CLKDIV_DIV_Msk & (_UINT32_(value) << MCLK_CLKDIV_DIV_Pos)) /* Assignment of value for DIV in the MCLK_CLKDIV register */
+#define   MCLK_CLKDIV_DIV_DIV1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKDIV) Divide by 1  */
+#define   MCLK_CLKDIV_DIV_DIV2_Val            _UINT32_(0x2)                                        /* (MCLK_CLKDIV) Divide by 2  */
+#define   MCLK_CLKDIV_DIV_DIV4_Val            _UINT32_(0x4)                                        /* (MCLK_CLKDIV) Divide by 4  */
+#define   MCLK_CLKDIV_DIV_DIV8_Val            _UINT32_(0x8)                                        /* (MCLK_CLKDIV) Divide by 8  */
+#define   MCLK_CLKDIV_DIV_DIV16_Val           _UINT32_(0x10)                                       /* (MCLK_CLKDIV) Divide by 16  */
+#define   MCLK_CLKDIV_DIV_DIV32_Val           _UINT32_(0x20)                                       /* (MCLK_CLKDIV) Divide by 32  */
+#define   MCLK_CLKDIV_DIV_DIV64_Val           _UINT32_(0x40)                                       /* (MCLK_CLKDIV) Divide by 64  */
+#define   MCLK_CLKDIV_DIV_DIV128_Val          _UINT32_(0x80)                                       /* (MCLK_CLKDIV) Divide by 128  */
+#define MCLK_CLKDIV_DIV_DIV1                  (MCLK_CLKDIV_DIV_DIV1_Val << MCLK_CLKDIV_DIV_Pos)    /* (MCLK_CLKDIV) Divide by 1 Position */
+#define MCLK_CLKDIV_DIV_DIV2                  (MCLK_CLKDIV_DIV_DIV2_Val << MCLK_CLKDIV_DIV_Pos)    /* (MCLK_CLKDIV) Divide by 2 Position */
+#define MCLK_CLKDIV_DIV_DIV4                  (MCLK_CLKDIV_DIV_DIV4_Val << MCLK_CLKDIV_DIV_Pos)    /* (MCLK_CLKDIV) Divide by 4 Position */
+#define MCLK_CLKDIV_DIV_DIV8                  (MCLK_CLKDIV_DIV_DIV8_Val << MCLK_CLKDIV_DIV_Pos)    /* (MCLK_CLKDIV) Divide by 8 Position */
+#define MCLK_CLKDIV_DIV_DIV16                 (MCLK_CLKDIV_DIV_DIV16_Val << MCLK_CLKDIV_DIV_Pos)   /* (MCLK_CLKDIV) Divide by 16 Position */
+#define MCLK_CLKDIV_DIV_DIV32                 (MCLK_CLKDIV_DIV_DIV32_Val << MCLK_CLKDIV_DIV_Pos)   /* (MCLK_CLKDIV) Divide by 32 Position */
+#define MCLK_CLKDIV_DIV_DIV64                 (MCLK_CLKDIV_DIV_DIV64_Val << MCLK_CLKDIV_DIV_Pos)   /* (MCLK_CLKDIV) Divide by 64 Position */
+#define MCLK_CLKDIV_DIV_DIV128                (MCLK_CLKDIV_DIV_DIV128_Val << MCLK_CLKDIV_DIV_Pos)  /* (MCLK_CLKDIV) Divide by 128 Position */
+#define MCLK_CLKDIV_Msk                       _UINT32_(0x000000FF)                                 /* (MCLK_CLKDIV) Register Mask  */
+
+
+/* -------- MCLK_CLKMSK : (MCLK Offset: 0x3C) (R/W 32) Peripheral Clock Enable Mask n Register -------- */
+#define MCLK_CLKMSK_RESETVALUE                _UINT32_(0x00)                                       /*  (MCLK_CLKMSK) Peripheral Clock Enable Mask n Register  Reset Value */
+
+#define MCLK_CLKMSK_MASK0_Pos                 _UINT32_(0)                                          /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK0_Msk                 (_UINT32_(0x1) << MCLK_CLKMSK_MASK0_Pos)             /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK0(value)              (MCLK_CLKMSK_MASK0_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK0_Pos)) /* Assignment of value for MASK0 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK0_0_Val             _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK0_1_Val             _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK0_0                   (MCLK_CLKMSK_MASK0_0_Val << MCLK_CLKMSK_MASK0_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK0_1                   (MCLK_CLKMSK_MASK0_1_Val << MCLK_CLKMSK_MASK0_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK1_Pos                 _UINT32_(1)                                          /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK1_Msk                 (_UINT32_(0x1) << MCLK_CLKMSK_MASK1_Pos)             /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK1(value)              (MCLK_CLKMSK_MASK1_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK1_Pos)) /* Assignment of value for MASK1 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK1_0_Val             _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK1_1_Val             _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK1_0                   (MCLK_CLKMSK_MASK1_0_Val << MCLK_CLKMSK_MASK1_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK1_1                   (MCLK_CLKMSK_MASK1_1_Val << MCLK_CLKMSK_MASK1_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK2_Pos                 _UINT32_(2)                                          /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK2_Msk                 (_UINT32_(0x1) << MCLK_CLKMSK_MASK2_Pos)             /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK2(value)              (MCLK_CLKMSK_MASK2_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK2_Pos)) /* Assignment of value for MASK2 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK2_0_Val             _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK2_1_Val             _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK2_0                   (MCLK_CLKMSK_MASK2_0_Val << MCLK_CLKMSK_MASK2_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK2_1                   (MCLK_CLKMSK_MASK2_1_Val << MCLK_CLKMSK_MASK2_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK3_Pos                 _UINT32_(3)                                          /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK3_Msk                 (_UINT32_(0x1) << MCLK_CLKMSK_MASK3_Pos)             /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK3(value)              (MCLK_CLKMSK_MASK3_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK3_Pos)) /* Assignment of value for MASK3 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK3_0_Val             _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK3_1_Val             _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK3_0                   (MCLK_CLKMSK_MASK3_0_Val << MCLK_CLKMSK_MASK3_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK3_1                   (MCLK_CLKMSK_MASK3_1_Val << MCLK_CLKMSK_MASK3_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK4_Pos                 _UINT32_(4)                                          /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK4_Msk                 (_UINT32_(0x1) << MCLK_CLKMSK_MASK4_Pos)             /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK4(value)              (MCLK_CLKMSK_MASK4_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK4_Pos)) /* Assignment of value for MASK4 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK4_0_Val             _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK4_1_Val             _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK4_0                   (MCLK_CLKMSK_MASK4_0_Val << MCLK_CLKMSK_MASK4_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK4_1                   (MCLK_CLKMSK_MASK4_1_Val << MCLK_CLKMSK_MASK4_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK5_Pos                 _UINT32_(5)                                          /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK5_Msk                 (_UINT32_(0x1) << MCLK_CLKMSK_MASK5_Pos)             /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK5(value)              (MCLK_CLKMSK_MASK5_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK5_Pos)) /* Assignment of value for MASK5 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK5_0_Val             _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK5_1_Val             _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK5_0                   (MCLK_CLKMSK_MASK5_0_Val << MCLK_CLKMSK_MASK5_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK5_1                   (MCLK_CLKMSK_MASK5_1_Val << MCLK_CLKMSK_MASK5_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK6_Pos                 _UINT32_(6)                                          /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK6_Msk                 (_UINT32_(0x1) << MCLK_CLKMSK_MASK6_Pos)             /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK6(value)              (MCLK_CLKMSK_MASK6_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK6_Pos)) /* Assignment of value for MASK6 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK6_0_Val             _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK6_1_Val             _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK6_0                   (MCLK_CLKMSK_MASK6_0_Val << MCLK_CLKMSK_MASK6_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK6_1                   (MCLK_CLKMSK_MASK6_1_Val << MCLK_CLKMSK_MASK6_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK7_Pos                 _UINT32_(7)                                          /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK7_Msk                 (_UINT32_(0x1) << MCLK_CLKMSK_MASK7_Pos)             /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK7(value)              (MCLK_CLKMSK_MASK7_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK7_Pos)) /* Assignment of value for MASK7 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK7_0_Val             _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK7_1_Val             _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK7_0                   (MCLK_CLKMSK_MASK7_0_Val << MCLK_CLKMSK_MASK7_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK7_1                   (MCLK_CLKMSK_MASK7_1_Val << MCLK_CLKMSK_MASK7_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK8_Pos                 _UINT32_(8)                                          /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK8_Msk                 (_UINT32_(0x1) << MCLK_CLKMSK_MASK8_Pos)             /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK8(value)              (MCLK_CLKMSK_MASK8_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK8_Pos)) /* Assignment of value for MASK8 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK8_0_Val             _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK8_1_Val             _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK8_0                   (MCLK_CLKMSK_MASK8_0_Val << MCLK_CLKMSK_MASK8_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK8_1                   (MCLK_CLKMSK_MASK8_1_Val << MCLK_CLKMSK_MASK8_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK9_Pos                 _UINT32_(9)                                          /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK9_Msk                 (_UINT32_(0x1) << MCLK_CLKMSK_MASK9_Pos)             /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK9(value)              (MCLK_CLKMSK_MASK9_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK9_Pos)) /* Assignment of value for MASK9 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK9_0_Val             _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK9_1_Val             _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK9_0                   (MCLK_CLKMSK_MASK9_0_Val << MCLK_CLKMSK_MASK9_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK9_1                   (MCLK_CLKMSK_MASK9_1_Val << MCLK_CLKMSK_MASK9_Pos)   /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK10_Pos                _UINT32_(10)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK10_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK10_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK10(value)             (MCLK_CLKMSK_MASK10_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK10_Pos)) /* Assignment of value for MASK10 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK10_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK10_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK10_0                  (MCLK_CLKMSK_MASK10_0_Val << MCLK_CLKMSK_MASK10_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK10_1                  (MCLK_CLKMSK_MASK10_1_Val << MCLK_CLKMSK_MASK10_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK11_Pos                _UINT32_(11)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK11_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK11_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK11(value)             (MCLK_CLKMSK_MASK11_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK11_Pos)) /* Assignment of value for MASK11 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK11_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK11_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK11_0                  (MCLK_CLKMSK_MASK11_0_Val << MCLK_CLKMSK_MASK11_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK11_1                  (MCLK_CLKMSK_MASK11_1_Val << MCLK_CLKMSK_MASK11_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK12_Pos                _UINT32_(12)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK12_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK12_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK12(value)             (MCLK_CLKMSK_MASK12_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK12_Pos)) /* Assignment of value for MASK12 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK12_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK12_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK12_0                  (MCLK_CLKMSK_MASK12_0_Val << MCLK_CLKMSK_MASK12_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK12_1                  (MCLK_CLKMSK_MASK12_1_Val << MCLK_CLKMSK_MASK12_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK13_Pos                _UINT32_(13)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK13_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK13_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK13(value)             (MCLK_CLKMSK_MASK13_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK13_Pos)) /* Assignment of value for MASK13 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK13_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK13_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK13_0                  (MCLK_CLKMSK_MASK13_0_Val << MCLK_CLKMSK_MASK13_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK13_1                  (MCLK_CLKMSK_MASK13_1_Val << MCLK_CLKMSK_MASK13_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK14_Pos                _UINT32_(14)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK14_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK14_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK14(value)             (MCLK_CLKMSK_MASK14_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK14_Pos)) /* Assignment of value for MASK14 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK14_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK14_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK14_0                  (MCLK_CLKMSK_MASK14_0_Val << MCLK_CLKMSK_MASK14_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK14_1                  (MCLK_CLKMSK_MASK14_1_Val << MCLK_CLKMSK_MASK14_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK15_Pos                _UINT32_(15)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK15_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK15_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK15(value)             (MCLK_CLKMSK_MASK15_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK15_Pos)) /* Assignment of value for MASK15 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK15_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK15_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK15_0                  (MCLK_CLKMSK_MASK15_0_Val << MCLK_CLKMSK_MASK15_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK15_1                  (MCLK_CLKMSK_MASK15_1_Val << MCLK_CLKMSK_MASK15_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK16_Pos                _UINT32_(16)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK16_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK16_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK16(value)             (MCLK_CLKMSK_MASK16_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK16_Pos)) /* Assignment of value for MASK16 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK16_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK16_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK16_0                  (MCLK_CLKMSK_MASK16_0_Val << MCLK_CLKMSK_MASK16_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK16_1                  (MCLK_CLKMSK_MASK16_1_Val << MCLK_CLKMSK_MASK16_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK17_Pos                _UINT32_(17)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK17_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK17_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK17(value)             (MCLK_CLKMSK_MASK17_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK17_Pos)) /* Assignment of value for MASK17 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK17_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK17_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK17_0                  (MCLK_CLKMSK_MASK17_0_Val << MCLK_CLKMSK_MASK17_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK17_1                  (MCLK_CLKMSK_MASK17_1_Val << MCLK_CLKMSK_MASK17_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK18_Pos                _UINT32_(18)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK18_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK18_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK18(value)             (MCLK_CLKMSK_MASK18_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK18_Pos)) /* Assignment of value for MASK18 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK18_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK18_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK18_0                  (MCLK_CLKMSK_MASK18_0_Val << MCLK_CLKMSK_MASK18_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK18_1                  (MCLK_CLKMSK_MASK18_1_Val << MCLK_CLKMSK_MASK18_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK19_Pos                _UINT32_(19)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK19_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK19_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK19(value)             (MCLK_CLKMSK_MASK19_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK19_Pos)) /* Assignment of value for MASK19 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK19_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK19_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK19_0                  (MCLK_CLKMSK_MASK19_0_Val << MCLK_CLKMSK_MASK19_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK19_1                  (MCLK_CLKMSK_MASK19_1_Val << MCLK_CLKMSK_MASK19_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK20_Pos                _UINT32_(20)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK20_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK20_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK20(value)             (MCLK_CLKMSK_MASK20_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK20_Pos)) /* Assignment of value for MASK20 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK20_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK20_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK20_0                  (MCLK_CLKMSK_MASK20_0_Val << MCLK_CLKMSK_MASK20_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK20_1                  (MCLK_CLKMSK_MASK20_1_Val << MCLK_CLKMSK_MASK20_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK21_Pos                _UINT32_(21)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK21_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK21_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK21(value)             (MCLK_CLKMSK_MASK21_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK21_Pos)) /* Assignment of value for MASK21 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK21_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK21_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK21_0                  (MCLK_CLKMSK_MASK21_0_Val << MCLK_CLKMSK_MASK21_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK21_1                  (MCLK_CLKMSK_MASK21_1_Val << MCLK_CLKMSK_MASK21_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK22_Pos                _UINT32_(22)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK22_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK22_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK22(value)             (MCLK_CLKMSK_MASK22_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK22_Pos)) /* Assignment of value for MASK22 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK22_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK22_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK22_0                  (MCLK_CLKMSK_MASK22_0_Val << MCLK_CLKMSK_MASK22_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK22_1                  (MCLK_CLKMSK_MASK22_1_Val << MCLK_CLKMSK_MASK22_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK23_Pos                _UINT32_(23)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK23_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK23_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK23(value)             (MCLK_CLKMSK_MASK23_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK23_Pos)) /* Assignment of value for MASK23 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK23_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK23_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK23_0                  (MCLK_CLKMSK_MASK23_0_Val << MCLK_CLKMSK_MASK23_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK23_1                  (MCLK_CLKMSK_MASK23_1_Val << MCLK_CLKMSK_MASK23_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK24_Pos                _UINT32_(24)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK24_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK24_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK24(value)             (MCLK_CLKMSK_MASK24_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK24_Pos)) /* Assignment of value for MASK24 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK24_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK24_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK24_0                  (MCLK_CLKMSK_MASK24_0_Val << MCLK_CLKMSK_MASK24_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK24_1                  (MCLK_CLKMSK_MASK24_1_Val << MCLK_CLKMSK_MASK24_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK25_Pos                _UINT32_(25)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK25_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK25_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK25(value)             (MCLK_CLKMSK_MASK25_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK25_Pos)) /* Assignment of value for MASK25 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK25_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK25_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK25_0                  (MCLK_CLKMSK_MASK25_0_Val << MCLK_CLKMSK_MASK25_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK25_1                  (MCLK_CLKMSK_MASK25_1_Val << MCLK_CLKMSK_MASK25_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK26_Pos                _UINT32_(26)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK26_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK26_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK26(value)             (MCLK_CLKMSK_MASK26_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK26_Pos)) /* Assignment of value for MASK26 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK26_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK26_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK26_0                  (MCLK_CLKMSK_MASK26_0_Val << MCLK_CLKMSK_MASK26_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK26_1                  (MCLK_CLKMSK_MASK26_1_Val << MCLK_CLKMSK_MASK26_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK27_Pos                _UINT32_(27)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK27_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK27_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK27(value)             (MCLK_CLKMSK_MASK27_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK27_Pos)) /* Assignment of value for MASK27 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK27_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK27_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK27_0                  (MCLK_CLKMSK_MASK27_0_Val << MCLK_CLKMSK_MASK27_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK27_1                  (MCLK_CLKMSK_MASK27_1_Val << MCLK_CLKMSK_MASK27_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK28_Pos                _UINT32_(28)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK28_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK28_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK28(value)             (MCLK_CLKMSK_MASK28_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK28_Pos)) /* Assignment of value for MASK28 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK28_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK28_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK28_0                  (MCLK_CLKMSK_MASK28_0_Val << MCLK_CLKMSK_MASK28_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK28_1                  (MCLK_CLKMSK_MASK28_1_Val << MCLK_CLKMSK_MASK28_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK29_Pos                _UINT32_(29)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK29_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK29_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK29(value)             (MCLK_CLKMSK_MASK29_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK29_Pos)) /* Assignment of value for MASK29 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK29_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK29_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK29_0                  (MCLK_CLKMSK_MASK29_0_Val << MCLK_CLKMSK_MASK29_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK29_1                  (MCLK_CLKMSK_MASK29_1_Val << MCLK_CLKMSK_MASK29_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK30_Pos                _UINT32_(30)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK30_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK30_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK30(value)             (MCLK_CLKMSK_MASK30_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK30_Pos)) /* Assignment of value for MASK30 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK30_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK30_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK30_0                  (MCLK_CLKMSK_MASK30_0_Val << MCLK_CLKMSK_MASK30_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK30_1                  (MCLK_CLKMSK_MASK30_1_Val << MCLK_CLKMSK_MASK30_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_MASK31_Pos                _UINT32_(31)                                         /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Position */
+#define MCLK_CLKMSK_MASK31_Msk                (_UINT32_(0x1) << MCLK_CLKMSK_MASK31_Pos)            /* (MCLK_CLKMSK) Peripheral Clock Enable Mask Mask */
+#define MCLK_CLKMSK_MASK31(value)             (MCLK_CLKMSK_MASK31_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK31_Pos)) /* Assignment of value for MASK31 in the MCLK_CLKMSK register */
+#define   MCLK_CLKMSK_MASK31_0_Val            _UINT32_(0x0)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped  */
+#define   MCLK_CLKMSK_MASK31_1_Val            _UINT32_(0x1)                                        /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled  */
+#define MCLK_CLKMSK_MASK31_0                  (MCLK_CLKMSK_MASK31_0_Val << MCLK_CLKMSK_MASK31_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] stopped Position */
+#define MCLK_CLKMSK_MASK31_1                  (MCLK_CLKMSK_MASK31_1_Val << MCLK_CLKMSK_MASK31_Pos) /* (MCLK_CLKMSK) Peripheral clock mclk_clk_periph[n*32+x] enabled Position */
+#define MCLK_CLKMSK_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (MCLK_CLKMSK) Register Mask  */
+
+#define MCLK_CLKMSK_MASK_Pos                  _UINT32_(0)                                          /* (MCLK_CLKMSK Position) Peripheral Clock Enable Mask */
+#define MCLK_CLKMSK_MASK_Msk                  (_UINT32_(0xFFFFFFFF) << MCLK_CLKMSK_MASK_Pos)       /* (MCLK_CLKMSK Mask) MASK */
+#define MCLK_CLKMSK_MASK(value)               (MCLK_CLKMSK_MASK_Msk & (_UINT32_(value) << MCLK_CLKMSK_MASK_Pos)) 
+
+/* MCLK register offsets definitions */
+#define MCLK_INTENCLR_REG_OFST         _UINT32_(0x00)      /* (MCLK_INTENCLR) Interrupt Enable Clear Register Offset */
+#define MCLK_INTENSET_REG_OFST         _UINT32_(0x04)      /* (MCLK_INTENSET) Interrupt Enable Set Register Offset */
+#define MCLK_INTFLAG_REG_OFST          _UINT32_(0x08)      /* (MCLK_INTFLAG) Interrupt Flag Status Register Offset */
+#define MCLK_CLKDIV_REG_OFST           _UINT32_(0x0C)      /* (MCLK_CLKDIV) Clock Divider Control n Register Offset */
+#define MCLK_CLKDIV0_REG_OFST          _UINT32_(0x0C)      /* (MCLK_CLKDIV0) Clock Divider Control n Register Offset */
+#define MCLK_CLKDIV1_REG_OFST          _UINT32_(0x10)      /* (MCLK_CLKDIV1) Clock Divider Control n Register Offset */
+#define MCLK_CLKDIV2_REG_OFST          _UINT32_(0x14)      /* (MCLK_CLKDIV2) Clock Divider Control n Register Offset */
+#define MCLK_CLKMSK_REG_OFST           _UINT32_(0x3C)      /* (MCLK_CLKMSK) Peripheral Clock Enable Mask n Register Offset */
+#define MCLK_CLKMSK0_REG_OFST          _UINT32_(0x3C)      /* (MCLK_CLKMSK0) Peripheral Clock Enable Mask n Register Offset */
+#define MCLK_CLKMSK1_REG_OFST          _UINT32_(0x40)      /* (MCLK_CLKMSK1) Peripheral Clock Enable Mask n Register Offset */
+#define MCLK_CLKMSK2_REG_OFST          _UINT32_(0x44)      /* (MCLK_CLKMSK2) Peripheral Clock Enable Mask n Register Offset */
+#define MCLK_CLKMSK3_REG_OFST          _UINT32_(0x48)      /* (MCLK_CLKMSK3) Peripheral Clock Enable Mask n Register Offset */
+#define MCLK_CLKMSK4_REG_OFST          _UINT32_(0x4C)      /* (MCLK_CLKMSK4) Peripheral Clock Enable Mask n Register Offset */
+#define MCLK_CLKMSK5_REG_OFST          _UINT32_(0x50)      /* (MCLK_CLKMSK5) Peripheral Clock Enable Mask n Register Offset */
+#define MCLK_CLKMSK6_REG_OFST          _UINT32_(0x54)      /* (MCLK_CLKMSK6) Peripheral Clock Enable Mask n Register Offset */
+#define MCLK_CLKMSK7_REG_OFST          _UINT32_(0x58)      /* (MCLK_CLKMSK7) Peripheral Clock Enable Mask n Register Offset */
+#define MCLK_CLKMSK8_REG_OFST          _UINT32_(0x5C)      /* (MCLK_CLKMSK8) Peripheral Clock Enable Mask n Register Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* MCLK register API structure */
+typedef struct
+{  /* Polaris Main Clock Controller */
+  __IO  uint32_t                       MCLK_INTENCLR;      /* Offset: 0x00 (R/W  32) Interrupt Enable Clear Register */
+  __IO  uint32_t                       MCLK_INTENSET;      /* Offset: 0x04 (R/W  32) Interrupt Enable Set Register */
+  __O   uint32_t                       MCLK_INTFLAG;       /* Offset: 0x08 ( /W  32) Interrupt Flag Status Register */
+  __IO  uint32_t                       MCLK_CLKDIV[3];     /* Offset: 0x0C (R/W  32) Clock Divider Control n Register */
+  __I   uint8_t                        Reserved1[0x24];
+  __IO  uint32_t                       MCLK_CLKMSK[9];     /* Offset: 0x3C (R/W  32) Peripheral Clock Enable Mask n Register */
+} mclk_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_MCLK_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/mcramc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/mcramc.h
new file mode 100644
index 00000000..cd296ddc
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/mcramc.h
@@ -0,0 +1,219 @@
+/*
+ * Component description for MCRAMC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_MCRAMC_COMPONENT_H_
+#define _PIC32CMGC00_MCRAMC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                     SOFTWARE API DEFINITION FOR MCRAMC                     */
+/* ************************************************************************** */
+
+/* -------- MCRAMC_CTRLA : (MCRAMC Offset: 0x00) (R/W 32) Control Enable A Register -------- */
+#define MCRAMC_CTRLA_RESETVALUE               _UINT32_(0x02)                                       /*  (MCRAMC_CTRLA) Control Enable A Register  Reset Value */
+
+#define MCRAMC_CTRLA_SWRST_Pos                _UINT32_(0)                                          /* (MCRAMC_CTRLA) Software Reset Position */
+#define MCRAMC_CTRLA_SWRST_Msk                (_UINT32_(0x1) << MCRAMC_CTRLA_SWRST_Pos)            /* (MCRAMC_CTRLA) Software Reset Mask */
+#define MCRAMC_CTRLA_SWRST(value)             (MCRAMC_CTRLA_SWRST_Msk & (_UINT32_(value) << MCRAMC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the MCRAMC_CTRLA register */
+#define   MCRAMC_CTRLA_SWRST_0_Val            _UINT32_(0x0)                                        /* (MCRAMC_CTRLA) No effect.  */
+#define   MCRAMC_CTRLA_SWRST_1_Val            _UINT32_(0x1)                                        /* (MCRAMC_CTRLA) Reset the MCRAMC. A software-triggered hardware reset of the MCRAMC user interface is performed.  */
+#define MCRAMC_CTRLA_SWRST_0                  (MCRAMC_CTRLA_SWRST_0_Val << MCRAMC_CTRLA_SWRST_Pos) /* (MCRAMC_CTRLA) No effect. Position */
+#define MCRAMC_CTRLA_SWRST_1                  (MCRAMC_CTRLA_SWRST_1_Val << MCRAMC_CTRLA_SWRST_Pos) /* (MCRAMC_CTRLA) Reset the MCRAMC. A software-triggered hardware reset of the MCRAMC user interface is performed. Position */
+#define MCRAMC_CTRLA_ENABLE_Pos               _UINT32_(1)                                          /* (MCRAMC_CTRLA) ECC Decoder Enable Position */
+#define MCRAMC_CTRLA_ENABLE_Msk               (_UINT32_(0x1) << MCRAMC_CTRLA_ENABLE_Pos)           /* (MCRAMC_CTRLA) ECC Decoder Enable Mask */
+#define MCRAMC_CTRLA_ENABLE(value)            (MCRAMC_CTRLA_ENABLE_Msk & (_UINT32_(value) << MCRAMC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the MCRAMC_CTRLA register */
+#define   MCRAMC_CTRLA_ENABLE_0_Val           _UINT32_(0x0)                                        /* (MCRAMC_CTRLA) ECC decoding is disabled.  */
+#define   MCRAMC_CTRLA_ENABLE_1_Val           _UINT32_(0x1)                                        /* (MCRAMC_CTRLA) ECC decoding is enabled.  */
+#define MCRAMC_CTRLA_ENABLE_0                 (MCRAMC_CTRLA_ENABLE_0_Val << MCRAMC_CTRLA_ENABLE_Pos) /* (MCRAMC_CTRLA) ECC decoding is disabled. Position */
+#define MCRAMC_CTRLA_ENABLE_1                 (MCRAMC_CTRLA_ENABLE_1_Val << MCRAMC_CTRLA_ENABLE_Pos) /* (MCRAMC_CTRLA) ECC decoding is enabled. Position */
+#define MCRAMC_CTRLA_PRIV_Pos                 _UINT32_(2)                                          /* (MCRAMC_CTRLA) Priviledged Access Enable Position */
+#define MCRAMC_CTRLA_PRIV_Msk                 (_UINT32_(0x1) << MCRAMC_CTRLA_PRIV_Pos)             /* (MCRAMC_CTRLA) Priviledged Access Enable Mask */
+#define MCRAMC_CTRLA_PRIV(value)              (MCRAMC_CTRLA_PRIV_Msk & (_UINT32_(value) << MCRAMC_CTRLA_PRIV_Pos)) /* Assignment of value for PRIV in the MCRAMC_CTRLA register */
+#define MCRAMC_CTRLA_WS_Pos                   _UINT32_(8)                                          /* (MCRAMC_CTRLA) Wait State Enable Position */
+#define MCRAMC_CTRLA_WS_Msk                   (_UINT32_(0x1) << MCRAMC_CTRLA_WS_Pos)               /* (MCRAMC_CTRLA) Wait State Enable Mask */
+#define MCRAMC_CTRLA_WS(value)                (MCRAMC_CTRLA_WS_Msk & (_UINT32_(value) << MCRAMC_CTRLA_WS_Pos)) /* Assignment of value for WS in the MCRAMC_CTRLA register */
+#define MCRAMC_CTRLA_Msk                      _UINT32_(0x00000107)                                 /* (MCRAMC_CTRLA) Register Mask  */
+
+
+/* -------- MCRAMC_INTENCLR : (MCRAMC Offset: 0x08) (R/W 32) Interrupt Enable Clear Register -------- */
+#define MCRAMC_INTENCLR_RESETVALUE            _UINT32_(0x00)                                       /*  (MCRAMC_INTENCLR) Interrupt Enable Clear Register  Reset Value */
+
+#define MCRAMC_INTENCLR_SERREN_Pos            _UINT32_(0)                                          /* (MCRAMC_INTENCLR) Single Bit Error Interrupt Enable, Clear Position */
+#define MCRAMC_INTENCLR_SERREN_Msk            (_UINT32_(0x1) << MCRAMC_INTENCLR_SERREN_Pos)        /* (MCRAMC_INTENCLR) Single Bit Error Interrupt Enable, Clear Mask */
+#define MCRAMC_INTENCLR_SERREN(value)         (MCRAMC_INTENCLR_SERREN_Msk & (_UINT32_(value) << MCRAMC_INTENCLR_SERREN_Pos)) /* Assignment of value for SERREN in the MCRAMC_INTENCLR register */
+#define MCRAMC_INTENCLR_DERREN_Pos            _UINT32_(1)                                          /* (MCRAMC_INTENCLR) Double Bit Error Interrupt Enable, Clear Position */
+#define MCRAMC_INTENCLR_DERREN_Msk            (_UINT32_(0x1) << MCRAMC_INTENCLR_DERREN_Pos)        /* (MCRAMC_INTENCLR) Double Bit Error Interrupt Enable, Clear Mask */
+#define MCRAMC_INTENCLR_DERREN(value)         (MCRAMC_INTENCLR_DERREN_Msk & (_UINT32_(value) << MCRAMC_INTENCLR_DERREN_Pos)) /* Assignment of value for DERREN in the MCRAMC_INTENCLR register */
+#define MCRAMC_INTENCLR_Msk                   _UINT32_(0x00000003)                                 /* (MCRAMC_INTENCLR) Register Mask  */
+
+
+/* -------- MCRAMC_INTENSET : (MCRAMC Offset: 0x0C) (R/W 32) Interrupt Enable Set Register -------- */
+#define MCRAMC_INTENSET_RESETVALUE            _UINT32_(0x00)                                       /*  (MCRAMC_INTENSET) Interrupt Enable Set Register  Reset Value */
+
+#define MCRAMC_INTENSET_SERREN_Pos            _UINT32_(0)                                          /* (MCRAMC_INTENSET) Single Bit Error Interrupt Enable, Set Position */
+#define MCRAMC_INTENSET_SERREN_Msk            (_UINT32_(0x1) << MCRAMC_INTENSET_SERREN_Pos)        /* (MCRAMC_INTENSET) Single Bit Error Interrupt Enable, Set Mask */
+#define MCRAMC_INTENSET_SERREN(value)         (MCRAMC_INTENSET_SERREN_Msk & (_UINT32_(value) << MCRAMC_INTENSET_SERREN_Pos)) /* Assignment of value for SERREN in the MCRAMC_INTENSET register */
+#define MCRAMC_INTENSET_DERREN_Pos            _UINT32_(1)                                          /* (MCRAMC_INTENSET) Double Bit Error Interrupt Enable, Set Position */
+#define MCRAMC_INTENSET_DERREN_Msk            (_UINT32_(0x1) << MCRAMC_INTENSET_DERREN_Pos)        /* (MCRAMC_INTENSET) Double Bit Error Interrupt Enable, Set Mask */
+#define MCRAMC_INTENSET_DERREN(value)         (MCRAMC_INTENSET_DERREN_Msk & (_UINT32_(value) << MCRAMC_INTENSET_DERREN_Pos)) /* Assignment of value for DERREN in the MCRAMC_INTENSET register */
+#define MCRAMC_INTENSET_Msk                   _UINT32_(0x00000003)                                 /* (MCRAMC_INTENSET) Register Mask  */
+
+
+/* -------- MCRAMC_INTSTA : (MCRAMC Offset: 0x10) (R/W 32) Interrupt Status Register -------- */
+#define MCRAMC_INTSTA_RESETVALUE              _UINT32_(0x00)                                       /*  (MCRAMC_INTSTA) Interrupt Status Register  Reset Value */
+
+#define MCRAMC_INTSTA_SERR_Pos                _UINT32_(0)                                          /* (MCRAMC_INTSTA) Single Bit Error Position */
+#define MCRAMC_INTSTA_SERR_Msk                (_UINT32_(0x1) << MCRAMC_INTSTA_SERR_Pos)            /* (MCRAMC_INTSTA) Single Bit Error Mask */
+#define MCRAMC_INTSTA_SERR(value)             (MCRAMC_INTSTA_SERR_Msk & (_UINT32_(value) << MCRAMC_INTSTA_SERR_Pos)) /* Assignment of value for SERR in the MCRAMC_INTSTA register */
+#define MCRAMC_INTSTA_DERR_Pos                _UINT32_(1)                                          /* (MCRAMC_INTSTA) Double Bit Error Position */
+#define MCRAMC_INTSTA_DERR_Msk                (_UINT32_(0x1) << MCRAMC_INTSTA_DERR_Pos)            /* (MCRAMC_INTSTA) Double Bit Error Mask */
+#define MCRAMC_INTSTA_DERR(value)             (MCRAMC_INTSTA_DERR_Msk & (_UINT32_(value) << MCRAMC_INTSTA_DERR_Pos)) /* Assignment of value for DERR in the MCRAMC_INTSTA register */
+#define MCRAMC_INTSTA_Msk                     _UINT32_(0x00000003)                                 /* (MCRAMC_INTSTA) Register Mask  */
+
+
+/* -------- MCRAMC_FLTCTRL : (MCRAMC Offset: 0x14) (R/W 32) Fault Injection Control Register -------- */
+#define MCRAMC_FLTCTRL_RESETVALUE             _UINT32_(0x00)                                       /*  (MCRAMC_FLTCTRL) Fault Injection Control Register  Reset Value */
+
+#define MCRAMC_FLTCTRL_FLTEN_Pos              _UINT32_(1)                                          /* (MCRAMC_FLTCTRL) Fault Injection Enabled Position */
+#define MCRAMC_FLTCTRL_FLTEN_Msk              (_UINT32_(0x1) << MCRAMC_FLTCTRL_FLTEN_Pos)          /* (MCRAMC_FLTCTRL) Fault Injection Enabled Mask */
+#define MCRAMC_FLTCTRL_FLTEN(value)           (MCRAMC_FLTCTRL_FLTEN_Msk & (_UINT32_(value) << MCRAMC_FLTCTRL_FLTEN_Pos)) /* Assignment of value for FLTEN in the MCRAMC_FLTCTRL register */
+#define   MCRAMC_FLTCTRL_FLTEN_0_Val          _UINT32_(0x0)                                        /* (MCRAMC_FLTCTRL) Disables fault injection.  */
+#define   MCRAMC_FLTCTRL_FLTEN_1_Val          _UINT32_(0x1)                                        /* (MCRAMC_FLTCTRL) Enables fault injection at FLTADR address offset as selected by FLTMD and FLTxPTR.  */
+#define MCRAMC_FLTCTRL_FLTEN_0                (MCRAMC_FLTCTRL_FLTEN_0_Val << MCRAMC_FLTCTRL_FLTEN_Pos) /* (MCRAMC_FLTCTRL) Disables fault injection. Position */
+#define MCRAMC_FLTCTRL_FLTEN_1                (MCRAMC_FLTCTRL_FLTEN_1_Val << MCRAMC_FLTCTRL_FLTEN_Pos) /* (MCRAMC_FLTCTRL) Enables fault injection at FLTADR address offset as selected by FLTMD and FLTxPTR. Position */
+#define MCRAMC_FLTCTRL_FLTMD_Pos              _UINT32_(12)                                         /* (MCRAMC_FLTCTRL) Fault Injection Mode Position */
+#define MCRAMC_FLTCTRL_FLTMD_Msk              (_UINT32_(0x3) << MCRAMC_FLTCTRL_FLTMD_Pos)          /* (MCRAMC_FLTCTRL) Fault Injection Mode Mask */
+#define MCRAMC_FLTCTRL_FLTMD(value)           (MCRAMC_FLTCTRL_FLTMD_Msk & (_UINT32_(value) << MCRAMC_FLTCTRL_FLTMD_Pos)) /* Assignment of value for FLTMD in the MCRAMC_FLTCTRL register */
+#define MCRAMC_FLTCTRL_Msk                    _UINT32_(0x00003002)                                 /* (MCRAMC_FLTCTRL) Register Mask  */
+
+
+/* -------- MCRAMC_FLTPTR : (MCRAMC Offset: 0x18) (R/W 32) Fault Injection Pointer Register -------- */
+#define MCRAMC_FLTPTR_RESETVALUE              _UINT32_(0x00)                                       /*  (MCRAMC_FLTPTR) Fault Injection Pointer Register  Reset Value */
+
+#define MCRAMC_FLTPTR_FLT1PTR_Pos             _UINT32_(0)                                          /* (MCRAMC_FLTPTR) Single Fault Injection Bit Pointer Position */
+#define MCRAMC_FLTPTR_FLT1PTR_Msk             (_UINT32_(0xFF) << MCRAMC_FLTPTR_FLT1PTR_Pos)        /* (MCRAMC_FLTPTR) Single Fault Injection Bit Pointer Mask */
+#define MCRAMC_FLTPTR_FLT1PTR(value)          (MCRAMC_FLTPTR_FLT1PTR_Msk & (_UINT32_(value) << MCRAMC_FLTPTR_FLT1PTR_Pos)) /* Assignment of value for FLT1PTR in the MCRAMC_FLTPTR register */
+#define MCRAMC_FLTPTR_FLT2PTR_Pos             _UINT32_(16)                                         /* (MCRAMC_FLTPTR) Double Fault Injection Bit Pointer Position */
+#define MCRAMC_FLTPTR_FLT2PTR_Msk             (_UINT32_(0xFF) << MCRAMC_FLTPTR_FLT2PTR_Pos)        /* (MCRAMC_FLTPTR) Double Fault Injection Bit Pointer Mask */
+#define MCRAMC_FLTPTR_FLT2PTR(value)          (MCRAMC_FLTPTR_FLT2PTR_Msk & (_UINT32_(value) << MCRAMC_FLTPTR_FLT2PTR_Pos)) /* Assignment of value for FLT2PTR in the MCRAMC_FLTPTR register */
+#define MCRAMC_FLTPTR_Msk                     _UINT32_(0x00FF00FF)                                 /* (MCRAMC_FLTPTR) Register Mask  */
+
+
+/* -------- MCRAMC_FLTADR : (MCRAMC Offset: 0x1C) (R/W 32) Fault Injection Address Register -------- */
+#define MCRAMC_FLTADR_RESETVALUE              _UINT32_(0x00)                                       /*  (MCRAMC_FLTADR) Fault Injection Address Register  Reset Value */
+
+#define MCRAMC_FLTADR_FLTADR_Pos              _UINT32_(0)                                          /* (MCRAMC_FLTADR) Fault Address Offset Position */
+#define MCRAMC_FLTADR_FLTADR_Msk              (_UINT32_(0xFFFFFF) << MCRAMC_FLTADR_FLTADR_Pos)     /* (MCRAMC_FLTADR) Fault Address Offset Mask */
+#define MCRAMC_FLTADR_FLTADR(value)           (MCRAMC_FLTADR_FLTADR_Msk & (_UINT32_(value) << MCRAMC_FLTADR_FLTADR_Pos)) /* Assignment of value for FLTADR in the MCRAMC_FLTADR register */
+#define MCRAMC_FLTADR_Msk                     _UINT32_(0x00FFFFFF)                                 /* (MCRAMC_FLTADR) Register Mask  */
+
+
+/* -------- MCRAMC_ERRCADR : (MCRAMC Offset: 0x20) ( R/ 32) Error Capture Address Register -------- */
+#define MCRAMC_ERRCADR_RESETVALUE             _UINT32_(0x00)                                       /*  (MCRAMC_ERRCADR) Error Capture Address Register  Reset Value */
+
+#define MCRAMC_ERRCADR_ERCADR_Pos             _UINT32_(0)                                          /* (MCRAMC_ERRCADR) ECC SECDED Error Capture Address Position */
+#define MCRAMC_ERRCADR_ERCADR_Msk             (_UINT32_(0xFFFFFF) << MCRAMC_ERRCADR_ERCADR_Pos)    /* (MCRAMC_ERRCADR) ECC SECDED Error Capture Address Mask */
+#define MCRAMC_ERRCADR_ERCADR(value)          (MCRAMC_ERRCADR_ERCADR_Msk & (_UINT32_(value) << MCRAMC_ERRCADR_ERCADR_Pos)) /* Assignment of value for ERCADR in the MCRAMC_ERRCADR register */
+#define MCRAMC_ERRCADR_Msk                    _UINT32_(0x00FFFFFF)                                 /* (MCRAMC_ERRCADR) Register Mask  */
+
+
+/* -------- MCRAMC_ERRCPAR : (MCRAMC Offset: 0x24) ( R/ 32) Error Capture Parity Register -------- */
+#define MCRAMC_ERRCPAR_RESETVALUE             _UINT32_(0x00)                                       /*  (MCRAMC_ERRCPAR) Error Capture Parity Register  Reset Value */
+
+#define MCRAMC_ERRCPAR_ERCPAR_Pos             _UINT32_(0)                                          /* (MCRAMC_ERRCPAR) ECC SECDED Error Capture Parity Position */
+#define MCRAMC_ERRCPAR_ERCPAR_Msk             (_UINT32_(0xFF) << MCRAMC_ERRCPAR_ERCPAR_Pos)        /* (MCRAMC_ERRCPAR) ECC SECDED Error Capture Parity Mask */
+#define MCRAMC_ERRCPAR_ERCPAR(value)          (MCRAMC_ERRCPAR_ERCPAR_Msk & (_UINT32_(value) << MCRAMC_ERRCPAR_ERCPAR_Pos)) /* Assignment of value for ERCPAR in the MCRAMC_ERRCPAR register */
+#define MCRAMC_ERRCPAR_Msk                    _UINT32_(0x000000FF)                                 /* (MCRAMC_ERRCPAR) Register Mask  */
+
+
+/* -------- MCRAMC_ERRCSYN : (MCRAMC Offset: 0x28) ( R/ 32) Error Capture Syndrome Register -------- */
+#define MCRAMC_ERRCSYN_RESETVALUE             _UINT32_(0x00)                                       /*  (MCRAMC_ERRCSYN) Error Capture Syndrome Register  Reset Value */
+
+#define MCRAMC_ERRCSYN_ERCSYN_Pos             _UINT32_(0)                                          /* (MCRAMC_ERRCSYN) ECC SECDED Error Capture Syndrome Position */
+#define MCRAMC_ERRCSYN_ERCSYN_Msk             (_UINT32_(0xFF) << MCRAMC_ERRCSYN_ERCSYN_Pos)        /* (MCRAMC_ERRCSYN) ECC SECDED Error Capture Syndrome Mask */
+#define MCRAMC_ERRCSYN_ERCSYN(value)          (MCRAMC_ERRCSYN_ERCSYN_Msk & (_UINT32_(value) << MCRAMC_ERRCSYN_ERCSYN_Pos)) /* Assignment of value for ERCSYN in the MCRAMC_ERRCSYN register */
+#define   MCRAMC_ERRCSYN_ERCSYN_0_Val         _UINT32_(0x0)                                        /* (MCRAMC_ERRCSYN) Not a Single bit error.  */
+#define   MCRAMC_ERRCSYN_ERCSYN_1_Val         _UINT32_(0x1)                                        /* (MCRAMC_ERRCSYN) Single bit error.  */
+#define MCRAMC_ERRCSYN_ERCSYN_0               (MCRAMC_ERRCSYN_ERCSYN_0_Val << MCRAMC_ERRCSYN_ERCSYN_Pos) /* (MCRAMC_ERRCSYN) Not a Single bit error. Position */
+#define MCRAMC_ERRCSYN_ERCSYN_1               (MCRAMC_ERRCSYN_ERCSYN_1_Val << MCRAMC_ERRCSYN_ERCSYN_Pos) /* (MCRAMC_ERRCSYN) Single bit error. Position */
+#define MCRAMC_ERRCSYN_ERR1_Pos               _UINT32_(14)                                         /* (MCRAMC_ERRCSYN) ECC Single Bit Error Position */
+#define MCRAMC_ERRCSYN_ERR1_Msk               (_UINT32_(0x1) << MCRAMC_ERRCSYN_ERR1_Pos)           /* (MCRAMC_ERRCSYN) ECC Single Bit Error Mask */
+#define MCRAMC_ERRCSYN_ERR1(value)            (MCRAMC_ERRCSYN_ERR1_Msk & (_UINT32_(value) << MCRAMC_ERRCSYN_ERR1_Pos)) /* Assignment of value for ERR1 in the MCRAMC_ERRCSYN register */
+#define MCRAMC_ERRCSYN_ERR2_Pos               _UINT32_(15)                                         /* (MCRAMC_ERRCSYN) ECC Double Bit Error Position */
+#define MCRAMC_ERRCSYN_ERR2_Msk               (_UINT32_(0x1) << MCRAMC_ERRCSYN_ERR2_Pos)           /* (MCRAMC_ERRCSYN) ECC Double Bit Error Mask */
+#define MCRAMC_ERRCSYN_ERR2(value)            (MCRAMC_ERRCSYN_ERR2_Msk & (_UINT32_(value) << MCRAMC_ERRCSYN_ERR2_Pos)) /* Assignment of value for ERR2 in the MCRAMC_ERRCSYN register */
+#define   MCRAMC_ERRCSYN_ERR2_0_Val           _UINT32_(0x0)                                        /* (MCRAMC_ERRCSYN) Not a Double bit error.  */
+#define   MCRAMC_ERRCSYN_ERR2_1_Val           _UINT32_(0x1)                                        /* (MCRAMC_ERRCSYN) Double bit error.  */
+#define MCRAMC_ERRCSYN_ERR2_0                 (MCRAMC_ERRCSYN_ERR2_0_Val << MCRAMC_ERRCSYN_ERR2_Pos) /* (MCRAMC_ERRCSYN) Not a Double bit error. Position */
+#define MCRAMC_ERRCSYN_ERR2_1                 (MCRAMC_ERRCSYN_ERR2_1_Val << MCRAMC_ERRCSYN_ERR2_Pos) /* (MCRAMC_ERRCSYN) Double bit error. Position */
+#define MCRAMC_ERRCSYN_Msk                    _UINT32_(0x0000C0FF)                                 /* (MCRAMC_ERRCSYN) Register Mask  */
+
+#define MCRAMC_ERRCSYN_ERR_Pos                _UINT32_(14)                                         /* (MCRAMC_ERRCSYN Position) ECC Double Bit Error */
+#define MCRAMC_ERRCSYN_ERR_Msk                (_UINT32_(0x3) << MCRAMC_ERRCSYN_ERR_Pos)            /* (MCRAMC_ERRCSYN Mask) ERR */
+#define MCRAMC_ERRCSYN_ERR(value)             (MCRAMC_ERRCSYN_ERR_Msk & (_UINT32_(value) << MCRAMC_ERRCSYN_ERR_Pos)) 
+
+/* -------- MCRAMC_VERSION : (MCRAMC Offset: 0xFC) ( R/ 32) Version Register -------- */
+#define MCRAMC_VERSION_RESETVALUE             _UINT32_(0x510)                                      /*  (MCRAMC_VERSION) Version Register  Reset Value */
+
+#define MCRAMC_VERSION_VERSION_Pos            _UINT32_(0)                                          /* (MCRAMC_VERSION) MCRAMC Version Position */
+#define MCRAMC_VERSION_VERSION_Msk            (_UINT32_(0xFFF) << MCRAMC_VERSION_VERSION_Pos)      /* (MCRAMC_VERSION) MCRAMC Version Mask */
+#define MCRAMC_VERSION_VERSION(value)         (MCRAMC_VERSION_VERSION_Msk & (_UINT32_(value) << MCRAMC_VERSION_VERSION_Pos)) /* Assignment of value for VERSION in the MCRAMC_VERSION register */
+#define MCRAMC_VERSION_MFN_Pos                _UINT32_(16)                                         /* (MCRAMC_VERSION) Metal Fix Number Position */
+#define MCRAMC_VERSION_MFN_Msk                (_UINT32_(0x7) << MCRAMC_VERSION_MFN_Pos)            /* (MCRAMC_VERSION) Metal Fix Number Mask */
+#define MCRAMC_VERSION_MFN(value)             (MCRAMC_VERSION_MFN_Msk & (_UINT32_(value) << MCRAMC_VERSION_MFN_Pos)) /* Assignment of value for MFN in the MCRAMC_VERSION register */
+#define MCRAMC_VERSION_Msk                    _UINT32_(0x00070FFF)                                 /* (MCRAMC_VERSION) Register Mask  */
+
+
+/* MCRAMC register offsets definitions */
+#define MCRAMC_CTRLA_REG_OFST          _UINT32_(0x00)      /* (MCRAMC_CTRLA) Control Enable A Register Offset */
+#define MCRAMC_INTENCLR_REG_OFST       _UINT32_(0x08)      /* (MCRAMC_INTENCLR) Interrupt Enable Clear Register Offset */
+#define MCRAMC_INTENSET_REG_OFST       _UINT32_(0x0C)      /* (MCRAMC_INTENSET) Interrupt Enable Set Register Offset */
+#define MCRAMC_INTSTA_REG_OFST         _UINT32_(0x10)      /* (MCRAMC_INTSTA) Interrupt Status Register Offset */
+#define MCRAMC_FLTCTRL_REG_OFST        _UINT32_(0x14)      /* (MCRAMC_FLTCTRL) Fault Injection Control Register Offset */
+#define MCRAMC_FLTPTR_REG_OFST         _UINT32_(0x18)      /* (MCRAMC_FLTPTR) Fault Injection Pointer Register Offset */
+#define MCRAMC_FLTADR_REG_OFST         _UINT32_(0x1C)      /* (MCRAMC_FLTADR) Fault Injection Address Register Offset */
+#define MCRAMC_ERRCADR_REG_OFST        _UINT32_(0x20)      /* (MCRAMC_ERRCADR) Error Capture Address Register Offset */
+#define MCRAMC_ERRCPAR_REG_OFST        _UINT32_(0x24)      /* (MCRAMC_ERRCPAR) Error Capture Parity Register Offset */
+#define MCRAMC_ERRCSYN_REG_OFST        _UINT32_(0x28)      /* (MCRAMC_ERRCSYN) Error Capture Syndrome Register Offset */
+#define MCRAMC_VERSION_REG_OFST        _UINT32_(0xFC)      /* (MCRAMC_VERSION) Version Register Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* MCRAMC register API structure */
+typedef struct
+{  /* Multi-Channel RAM Controller */
+  __IO  uint32_t                       MCRAMC_CTRLA;       /* Offset: 0x00 (R/W  32) Control Enable A Register */
+  __I   uint8_t                        Reserved1[0x04];
+  __IO  uint32_t                       MCRAMC_INTENCLR;    /* Offset: 0x08 (R/W  32) Interrupt Enable Clear Register */
+  __IO  uint32_t                       MCRAMC_INTENSET;    /* Offset: 0x0C (R/W  32) Interrupt Enable Set Register */
+  __IO  uint32_t                       MCRAMC_INTSTA;      /* Offset: 0x10 (R/W  32) Interrupt Status Register */
+  __IO  uint32_t                       MCRAMC_FLTCTRL;     /* Offset: 0x14 (R/W  32) Fault Injection Control Register */
+  __IO  uint32_t                       MCRAMC_FLTPTR;      /* Offset: 0x18 (R/W  32) Fault Injection Pointer Register */
+  __IO  uint32_t                       MCRAMC_FLTADR;      /* Offset: 0x1C (R/W  32) Fault Injection Address Register */
+  __I   uint32_t                       MCRAMC_ERRCADR;     /* Offset: 0x20 (R/   32) Error Capture Address Register */
+  __I   uint32_t                       MCRAMC_ERRCPAR;     /* Offset: 0x24 (R/   32) Error Capture Parity Register */
+  __I   uint32_t                       MCRAMC_ERRCSYN;     /* Offset: 0x28 (R/   32) Error Capture Syndrome Register */
+  __I   uint8_t                        Reserved2[0xD0];
+  __I   uint32_t                       MCRAMC_VERSION;     /* Offset: 0xFC (R/   32) Version Register */
+} mcramc_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_MCRAMC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/osc32kctrl.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/osc32kctrl.h
new file mode 100644
index 00000000..49f6ba1c
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/osc32kctrl.h
@@ -0,0 +1,239 @@
+/*
+ * Component description for OSC32KCTRL
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_OSC32KCTRL_COMPONENT_H_
+#define _PIC32CMGC00_OSC32KCTRL_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                   SOFTWARE API DEFINITION FOR OSC32KCTRL                   */
+/* ************************************************************************** */
+
+/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#define OSC32KCTRL_INTENCLR_RESETVALUE        _UINT32_(0x00)                                       /*  (OSC32KCTRL_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos    _UINT32_(0)                                          /* (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Position */
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk    (_UINT32_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) /* (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Mask */
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY(value) (OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk & (_UINT32_(value) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)) /* Assignment of value for XOSC32KRDY in the OSC32KCTRL_INTENCLR register */
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos   _UINT32_(2)                                          /* (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Position */
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk   (_UINT32_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos) /* (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Mask */
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL(value) (OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk & (_UINT32_(value) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)) /* Assignment of value for XOSC32KFAIL in the OSC32KCTRL_INTENCLR register */
+#define OSC32KCTRL_INTENCLR_Msk               _UINT32_(0x00000005)                                 /* (OSC32KCTRL_INTENCLR) Register Mask  */
+
+
+/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#define OSC32KCTRL_INTENSET_RESETVALUE        _UINT32_(0x00)                                       /*  (OSC32KCTRL_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos    _UINT32_(0)                                          /* (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Position */
+#define OSC32KCTRL_INTENSET_XOSC32KRDY_Msk    (_UINT32_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) /* (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Mask */
+#define OSC32KCTRL_INTENSET_XOSC32KRDY(value) (OSC32KCTRL_INTENSET_XOSC32KRDY_Msk & (_UINT32_(value) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)) /* Assignment of value for XOSC32KRDY in the OSC32KCTRL_INTENSET register */
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos   _UINT32_(2)                                          /* (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Position */
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk   (_UINT32_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos) /* (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Mask */
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL(value) (OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk & (_UINT32_(value) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)) /* Assignment of value for XOSC32KFAIL in the OSC32KCTRL_INTENSET register */
+#define OSC32KCTRL_INTENSET_Msk               _UINT32_(0x00000005)                                 /* (OSC32KCTRL_INTENSET) Register Mask  */
+
+
+/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#define OSC32KCTRL_INTFLAG_RESETVALUE         _UINT32_(0x00)                                       /*  (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos     _UINT32_(0)                                          /* (OSC32KCTRL_INTFLAG) XOSC32K Ready Position */
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk     (_UINT32_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) /* (OSC32KCTRL_INTFLAG) XOSC32K Ready Mask */
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY(value)  (OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk & (_UINT32_(value) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)) /* Assignment of value for XOSC32KRDY in the OSC32KCTRL_INTFLAG register */
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos    _UINT32_(2)                                          /* (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Position */
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk    (_UINT32_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos) /* (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Mask */
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL(value) (OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk & (_UINT32_(value) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)) /* Assignment of value for XOSC32KFAIL in the OSC32KCTRL_INTFLAG register */
+#define OSC32KCTRL_INTFLAG_Msk                _UINT32_(0x00000005)                                 /* (OSC32KCTRL_INTFLAG) Register Mask  */
+
+
+/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) ( R/ 32) Power and Clocks Status -------- */
+#define OSC32KCTRL_STATUS_RESETVALUE          _UINT32_(0x00)                                       /*  (OSC32KCTRL_STATUS) Power and Clocks Status  Reset Value */
+
+#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos      _UINT32_(0)                                          /* (OSC32KCTRL_STATUS) XOSC32K Ready Position */
+#define OSC32KCTRL_STATUS_XOSC32KRDY_Msk      (_UINT32_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)  /* (OSC32KCTRL_STATUS) XOSC32K Ready Mask */
+#define OSC32KCTRL_STATUS_XOSC32KRDY(value)   (OSC32KCTRL_STATUS_XOSC32KRDY_Msk & (_UINT32_(value) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)) /* Assignment of value for XOSC32KRDY in the OSC32KCTRL_STATUS register */
+#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos     _UINT32_(2)                                          /* (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Position */
+#define OSC32KCTRL_STATUS_XOSC32KFAIL_Msk     (_UINT32_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos) /* (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Mask */
+#define OSC32KCTRL_STATUS_XOSC32KFAIL(value)  (OSC32KCTRL_STATUS_XOSC32KFAIL_Msk & (_UINT32_(value) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)) /* Assignment of value for XOSC32KFAIL in the OSC32KCTRL_STATUS register */
+#define OSC32KCTRL_STATUS_XOSC32KSW_Pos       _UINT32_(3)                                          /* (OSC32KCTRL_STATUS) XOSC32K Clock switch Position */
+#define OSC32KCTRL_STATUS_XOSC32KSW_Msk       (_UINT32_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)   /* (OSC32KCTRL_STATUS) XOSC32K Clock switch Mask */
+#define OSC32KCTRL_STATUS_XOSC32KSW(value)    (OSC32KCTRL_STATUS_XOSC32KSW_Msk & (_UINT32_(value) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)) /* Assignment of value for XOSC32KSW in the OSC32KCTRL_STATUS register */
+#define OSC32KCTRL_STATUS_Msk                 _UINT32_(0x0000000D)                                 /* (OSC32KCTRL_STATUS) Register Mask  */
+
+
+/* -------- OSC32KCTRL_CLKSELCTRL : (OSC32KCTRL Offset: 0x10) (R/W 32) Clock Selection Control -------- */
+#define OSC32KCTRL_CLKSELCTRL_RESETVALUE      _UINT32_(0x00)                                       /*  (OSC32KCTRL_CLKSELCTRL) Clock Selection Control  Reset Value */
+
+#define OSC32KCTRL_CLKSELCTRL_RTCSEL_Pos      _UINT32_(0)                                          /* (OSC32KCTRL_CLKSELCTRL) RTC Clock Selection Position */
+#define OSC32KCTRL_CLKSELCTRL_RTCSEL_Msk      (_UINT32_(0x3) << OSC32KCTRL_CLKSELCTRL_RTCSEL_Pos)  /* (OSC32KCTRL_CLKSELCTRL) RTC Clock Selection Mask */
+#define OSC32KCTRL_CLKSELCTRL_RTCSEL(value)   (OSC32KCTRL_CLKSELCTRL_RTCSEL_Msk & (_UINT32_(value) << OSC32KCTRL_CLKSELCTRL_RTCSEL_Pos)) /* Assignment of value for RTCSEL in the OSC32KCTRL_CLKSELCTRL register */
+#define   OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP32K_Val _UINT32_(0x0)                                        /* (OSC32KCTRL_CLKSELCTRL) 32.768kHz from 32kHz internal ULP oscillator  */
+#define   OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP1K_Val _UINT32_(0x1)                                        /* (OSC32KCTRL_CLKSELCTRL) 1.024kHz from 32kHz internal ULP oscillator  */
+#define   OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC32K_Val _UINT32_(0x2)                                        /* (OSC32KCTRL_CLKSELCTRL) 32.768kHz from 32.768kHz external crystal oscillator  */
+#define   OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC1K_Val _UINT32_(0x3)                                        /* (OSC32KCTRL_CLKSELCTRL) 1.024kHz from 32.768kHz internal oscillator  */
+#define OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP32K   (OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_CLKSELCTRL_RTCSEL_Pos) /* (OSC32KCTRL_CLKSELCTRL) 32.768kHz from 32kHz internal ULP oscillator Position */
+#define OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP1K    (OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_CLKSELCTRL_RTCSEL_Pos) /* (OSC32KCTRL_CLKSELCTRL) 1.024kHz from 32kHz internal ULP oscillator Position */
+#define OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC32K  (OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_CLKSELCTRL_RTCSEL_Pos) /* (OSC32KCTRL_CLKSELCTRL) 32.768kHz from 32.768kHz external crystal oscillator Position */
+#define OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC1K   (OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_CLKSELCTRL_RTCSEL_Pos) /* (OSC32KCTRL_CLKSELCTRL) 1.024kHz from 32.768kHz internal oscillator Position */
+#define OSC32KCTRL_CLKSELCTRL_HSMSEL_Pos      _UINT32_(4)                                          /* (OSC32KCTRL_CLKSELCTRL) HSM Clock Selection Position */
+#define OSC32KCTRL_CLKSELCTRL_HSMSEL_Msk      (_UINT32_(0x3) << OSC32KCTRL_CLKSELCTRL_HSMSEL_Pos)  /* (OSC32KCTRL_CLKSELCTRL) HSM Clock Selection Mask */
+#define OSC32KCTRL_CLKSELCTRL_HSMSEL(value)   (OSC32KCTRL_CLKSELCTRL_HSMSEL_Msk & (_UINT32_(value) << OSC32KCTRL_CLKSELCTRL_HSMSEL_Pos)) /* Assignment of value for HSMSEL in the OSC32KCTRL_CLKSELCTRL register */
+#define   OSC32KCTRL_CLKSELCTRL_HSMSEL_ULP32K_Val _UINT32_(0x0)                                        /* (OSC32KCTRL_CLKSELCTRL) 32.768kHz from 32kHz internal ULP oscillator  */
+#define   OSC32KCTRL_CLKSELCTRL_HSMSEL_XOSC32K_Val _UINT32_(0x2)                                        /* (OSC32KCTRL_CLKSELCTRL) 32.768kHz from 32.768kHz external crystal oscillator  */
+#define OSC32KCTRL_CLKSELCTRL_HSMSEL_ULP32K   (OSC32KCTRL_CLKSELCTRL_HSMSEL_ULP32K_Val << OSC32KCTRL_CLKSELCTRL_HSMSEL_Pos) /* (OSC32KCTRL_CLKSELCTRL) 32.768kHz from 32kHz internal ULP oscillator Position */
+#define OSC32KCTRL_CLKSELCTRL_HSMSEL_XOSC32K  (OSC32KCTRL_CLKSELCTRL_HSMSEL_XOSC32K_Val << OSC32KCTRL_CLKSELCTRL_HSMSEL_Pos) /* (OSC32KCTRL_CLKSELCTRL) 32.768kHz from 32.768kHz external crystal oscillator Position */
+#define OSC32KCTRL_CLKSELCTRL_Msk             _UINT32_(0x00000033)                                 /* (OSC32KCTRL_CLKSELCTRL) Register Mask  */
+
+
+/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x14) (R/W 32) Clock Failure Detector Control -------- */
+#define OSC32KCTRL_CFDCTRL_RESETVALUE         _UINT32_(0x00)                                       /*  (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control  Reset Value */
+
+#define OSC32KCTRL_CFDCTRL_CFDEN_Pos          _UINT32_(0)                                          /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Position */
+#define OSC32KCTRL_CFDCTRL_CFDEN_Msk          (_UINT32_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)      /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Mask */
+#define OSC32KCTRL_CFDCTRL_CFDEN(value)       (OSC32KCTRL_CFDCTRL_CFDEN_Msk & (_UINT32_(value) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)) /* Assignment of value for CFDEN in the OSC32KCTRL_CFDCTRL register */
+#define OSC32KCTRL_CFDCTRL_SWBACK_Pos         _UINT32_(1)                                          /* (OSC32KCTRL_CFDCTRL) Clock Switch Back Position */
+#define OSC32KCTRL_CFDCTRL_SWBACK_Msk         (_UINT32_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)     /* (OSC32KCTRL_CFDCTRL) Clock Switch Back Mask */
+#define OSC32KCTRL_CFDCTRL_SWBACK(value)      (OSC32KCTRL_CFDCTRL_SWBACK_Msk & (_UINT32_(value) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)) /* Assignment of value for SWBACK in the OSC32KCTRL_CFDCTRL register */
+#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos       _UINT32_(2)                                          /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Position */
+#define OSC32KCTRL_CFDCTRL_CFDPRESC_Msk       (_UINT32_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)   /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Mask */
+#define OSC32KCTRL_CFDCTRL_CFDPRESC(value)    (OSC32KCTRL_CFDCTRL_CFDPRESC_Msk & (_UINT32_(value) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)) /* Assignment of value for CFDPRESC in the OSC32KCTRL_CFDCTRL register */
+#define OSC32KCTRL_CFDCTRL_Msk                _UINT32_(0x00000007)                                 /* (OSC32KCTRL_CFDCTRL) Register Mask  */
+
+
+/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x18) (R/W 32) Event Control -------- */
+#define OSC32KCTRL_EVCTRL_RESETVALUE          _UINT32_(0x00)                                       /*  (OSC32KCTRL_EVCTRL) Event Control  Reset Value */
+
+#define OSC32KCTRL_EVCTRL_CFDEO_Pos           _UINT32_(0)                                          /* (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Position */
+#define OSC32KCTRL_EVCTRL_CFDEO_Msk           (_UINT32_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)       /* (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Mask */
+#define OSC32KCTRL_EVCTRL_CFDEO(value)        (OSC32KCTRL_EVCTRL_CFDEO_Msk & (_UINT32_(value) << OSC32KCTRL_EVCTRL_CFDEO_Pos)) /* Assignment of value for CFDEO in the OSC32KCTRL_EVCTRL register */
+#define OSC32KCTRL_EVCTRL_Msk                 _UINT32_(0x00000001)                                 /* (OSC32KCTRL_EVCTRL) Register Mask  */
+
+
+/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#define OSC32KCTRL_XOSC32K_RESETVALUE         _UINT32_(0x200080)                                   /*  (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control  Reset Value */
+
+#define OSC32KCTRL_XOSC32K_ENABLE_Pos         _UINT32_(1)                                          /* (OSC32KCTRL_XOSC32K) Oscillator Enable Position */
+#define OSC32KCTRL_XOSC32K_ENABLE_Msk         (_UINT32_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)     /* (OSC32KCTRL_XOSC32K) Oscillator Enable Mask */
+#define OSC32KCTRL_XOSC32K_ENABLE(value)      (OSC32KCTRL_XOSC32K_ENABLE_Msk & (_UINT32_(value) << OSC32KCTRL_XOSC32K_ENABLE_Pos)) /* Assignment of value for ENABLE in the OSC32KCTRL_XOSC32K register */
+#define OSC32KCTRL_XOSC32K_XTALEN_Pos         _UINT32_(2)                                          /* (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Position */
+#define OSC32KCTRL_XOSC32K_XTALEN_Msk         (_UINT32_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)     /* (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Mask */
+#define OSC32KCTRL_XOSC32K_XTALEN(value)      (OSC32KCTRL_XOSC32K_XTALEN_Msk & (_UINT32_(value) << OSC32KCTRL_XOSC32K_XTALEN_Pos)) /* Assignment of value for XTALEN in the OSC32KCTRL_XOSC32K register */
+#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos       _UINT32_(7)                                          /* (OSC32KCTRL_XOSC32K) On Demand Mode Position */
+#define OSC32KCTRL_XOSC32K_ONDEMAND_Msk       (_UINT32_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)   /* (OSC32KCTRL_XOSC32K) On Demand Mode Mask */
+#define OSC32KCTRL_XOSC32K_ONDEMAND(value)    (OSC32KCTRL_XOSC32K_ONDEMAND_Msk & (_UINT32_(value) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the OSC32KCTRL_XOSC32K register */
+#define OSC32KCTRL_XOSC32K_STARTUP_Pos        _UINT32_(8)                                          /* (OSC32KCTRL_XOSC32K) Startup Mode Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_Msk        (_UINT32_(0xF) << OSC32KCTRL_XOSC32K_STARTUP_Pos)    /* (OSC32KCTRL_XOSC32K) Startup Mode Mask */
+#define OSC32KCTRL_XOSC32K_STARTUP(value)     (OSC32KCTRL_XOSC32K_STARTUP_Msk & (_UINT32_(value) << OSC32KCTRL_XOSC32K_STARTUP_Pos)) /* Assignment of value for STARTUP in the OSC32KCTRL_XOSC32K register */
+#define   OSC32KCTRL_XOSC32K_STARTUP_1CYCLE_Val _UINT32_(0x0)                                        /* (OSC32KCTRL_XOSC32K) 1 ULP clock cycle  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_16CYCLES_Val _UINT32_(0x1)                                        /* (OSC32KCTRL_XOSC32K) 16 ULP clock cycles  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_32CYCLES_Val _UINT32_(0x2)                                        /* (OSC32KCTRL_XOSC32K) 32 ULP clock cycles  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_2048CYCLES_Val _UINT32_(0x3)                                        /* (OSC32KCTRL_XOSC32K) 2048 ULP clock cycles  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_4096CYCLES_Val _UINT32_(0x4)                                        /* (OSC32KCTRL_XOSC32K) 4096 ULP clock cycles  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_8192CYCLES_Val _UINT32_(0x5)                                        /* (OSC32KCTRL_XOSC32K) 8192 ULP clock cycles  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_16384CYCLES_Val _UINT32_(0x6)                                        /* (OSC32KCTRL_XOSC32K) 16384 ULP clock cycles  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_32768CYCLES_Val _UINT32_(0x7)                                        /* (OSC32KCTRL_XOSC32K) 32768 ULP clock cycles  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_65536CYCLES_Val _UINT32_(0x8)                                        /* (OSC32KCTRL_XOSC32K) 65536 ULP clock cycles  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_131072CYCLES_Val _UINT32_(0x9)                                        /* (OSC32KCTRL_XOSC32K) 131072 ULP clock cycles  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_262144CYCLES_Val _UINT32_(0xA)                                        /* (OSC32KCTRL_XOSC32K) 262144 ULP clock cycles  */
+#define OSC32KCTRL_XOSC32K_STARTUP_1CYCLE     (OSC32KCTRL_XOSC32K_STARTUP_1CYCLE_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 1 ULP clock cycle Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_16CYCLES   (OSC32KCTRL_XOSC32K_STARTUP_16CYCLES_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 16 ULP clock cycles Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_32CYCLES   (OSC32KCTRL_XOSC32K_STARTUP_32CYCLES_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 32 ULP clock cycles Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_2048CYCLES (OSC32KCTRL_XOSC32K_STARTUP_2048CYCLES_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 2048 ULP clock cycles Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_4096CYCLES (OSC32KCTRL_XOSC32K_STARTUP_4096CYCLES_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 4096 ULP clock cycles Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_8192CYCLES (OSC32KCTRL_XOSC32K_STARTUP_8192CYCLES_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 8192 ULP clock cycles Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_16384CYCLES (OSC32KCTRL_XOSC32K_STARTUP_16384CYCLES_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 16384 ULP clock cycles Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_32768CYCLES (OSC32KCTRL_XOSC32K_STARTUP_32768CYCLES_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 32768 ULP clock cycles Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_65536CYCLES (OSC32KCTRL_XOSC32K_STARTUP_65536CYCLES_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 65536 ULP clock cycles Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_131072CYCLES (OSC32KCTRL_XOSC32K_STARTUP_131072CYCLES_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 131072 ULP clock cycles Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_262144CYCLES (OSC32KCTRL_XOSC32K_STARTUP_262144CYCLES_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 262144 ULP clock cycles Position */
+#define OSC32KCTRL_XOSC32K_ENSL_Pos           _UINT32_(16)                                         /* (OSC32KCTRL_XOSC32K) Enable Servo Loop Position */
+#define OSC32KCTRL_XOSC32K_ENSL_Msk           (_UINT32_(0x1) << OSC32KCTRL_XOSC32K_ENSL_Pos)       /* (OSC32KCTRL_XOSC32K) Enable Servo Loop Mask */
+#define OSC32KCTRL_XOSC32K_ENSL(value)        (OSC32KCTRL_XOSC32K_ENSL_Msk & (_UINT32_(value) << OSC32KCTRL_XOSC32K_ENSL_Pos)) /* Assignment of value for ENSL in the OSC32KCTRL_XOSC32K register */
+#define OSC32KCTRL_XOSC32K_BOOST_Pos          _UINT32_(17)                                         /* (OSC32KCTRL_XOSC32K) Gain Boost Position */
+#define OSC32KCTRL_XOSC32K_BOOST_Msk          (_UINT32_(0x1) << OSC32KCTRL_XOSC32K_BOOST_Pos)      /* (OSC32KCTRL_XOSC32K) Gain Boost Mask */
+#define OSC32KCTRL_XOSC32K_BOOST(value)       (OSC32KCTRL_XOSC32K_BOOST_Msk & (_UINT32_(value) << OSC32KCTRL_XOSC32K_BOOST_Pos)) /* Assignment of value for BOOST in the OSC32KCTRL_XOSC32K register */
+#define OSC32KCTRL_XOSC32K_CGM_Pos            _UINT32_(18)                                         /* (OSC32KCTRL_XOSC32K) Control Gain Mode Position */
+#define OSC32KCTRL_XOSC32K_CGM_Msk            (_UINT32_(0xF) << OSC32KCTRL_XOSC32K_CGM_Pos)        /* (OSC32KCTRL_XOSC32K) Control Gain Mode Mask */
+#define OSC32KCTRL_XOSC32K_CGM(value)         (OSC32KCTRL_XOSC32K_CGM_Msk & (_UINT32_(value) << OSC32KCTRL_XOSC32K_CGM_Pos)) /* Assignment of value for CGM in the OSC32KCTRL_XOSC32K register */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM0_Val     _UINT32_(0x0)                                        /* (OSC32KCTRL_XOSC32K) The lower Control Gain Mode value  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM1_Val     _UINT32_(0x1)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM0  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM2_Val     _UINT32_(0x2)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM1  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM3_Val     _UINT32_(0x3)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM2  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM4_Val     _UINT32_(0x4)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM3  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM5_Val     _UINT32_(0x5)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM4  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM6_Val     _UINT32_(0x6)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM5  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM7_Val     _UINT32_(0x7)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM6  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM8_Val     _UINT32_(0x8)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM7  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM9_Val     _UINT32_(0x9)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM8  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM10_Val    _UINT32_(0xA)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM9  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM11_Val    _UINT32_(0xB)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM10  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM12_Val    _UINT32_(0xC)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM11  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM13_Val    _UINT32_(0xD)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM12  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM14_Val    _UINT32_(0xE)                                        /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM13  */
+#define   OSC32KCTRL_XOSC32K_CGM_CGM15_Val    _UINT32_(0xF)                                        /* (OSC32KCTRL_XOSC32K) The highest Control Gain Mode value  */
+#define OSC32KCTRL_XOSC32K_CGM_CGM0           (OSC32KCTRL_XOSC32K_CGM_CGM0_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) The lower Control Gain Mode value Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM1           (OSC32KCTRL_XOSC32K_CGM_CGM1_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM0 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM2           (OSC32KCTRL_XOSC32K_CGM_CGM2_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM1 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM3           (OSC32KCTRL_XOSC32K_CGM_CGM3_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM2 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM4           (OSC32KCTRL_XOSC32K_CGM_CGM4_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM3 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM5           (OSC32KCTRL_XOSC32K_CGM_CGM5_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM4 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM6           (OSC32KCTRL_XOSC32K_CGM_CGM6_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM5 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM7           (OSC32KCTRL_XOSC32K_CGM_CGM7_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM6 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM8           (OSC32KCTRL_XOSC32K_CGM_CGM8_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM7 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM9           (OSC32KCTRL_XOSC32K_CGM_CGM9_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM8 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM10          (OSC32KCTRL_XOSC32K_CGM_CGM10_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM9 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM11          (OSC32KCTRL_XOSC32K_CGM_CGM11_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM10 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM12          (OSC32KCTRL_XOSC32K_CGM_CGM12_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM11 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM13          (OSC32KCTRL_XOSC32K_CGM_CGM13_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM12 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM14          (OSC32KCTRL_XOSC32K_CGM_CGM14_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) A higher Control Gain Mode value than CGM13 Position */
+#define OSC32KCTRL_XOSC32K_CGM_CGM15          (OSC32KCTRL_XOSC32K_CGM_CGM15_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) The highest Control Gain Mode value Position */
+#define OSC32KCTRL_XOSC32K_CTRLX_Pos          _UINT32_(24)                                         /* (OSC32KCTRL_XOSC32K) Extended Control Position */
+#define OSC32KCTRL_XOSC32K_CTRLX_Msk          (_UINT32_(0xF) << OSC32KCTRL_XOSC32K_CTRLX_Pos)      /* (OSC32KCTRL_XOSC32K) Extended Control Mask */
+#define OSC32KCTRL_XOSC32K_CTRLX(value)       (OSC32KCTRL_XOSC32K_CTRLX_Msk & (_UINT32_(value) << OSC32KCTRL_XOSC32K_CTRLX_Pos)) /* Assignment of value for CTRLX in the OSC32KCTRL_XOSC32K register */
+#define OSC32KCTRL_XOSC32K_Msk                _UINT32_(0x0F3F0F86)                                 /* (OSC32KCTRL_XOSC32K) Register Mask  */
+
+
+/* OSC32KCTRL register offsets definitions */
+#define OSC32KCTRL_INTENCLR_REG_OFST   _UINT32_(0x00)      /* (OSC32KCTRL_INTENCLR) Interrupt Enable Clear Offset */
+#define OSC32KCTRL_INTENSET_REG_OFST   _UINT32_(0x04)      /* (OSC32KCTRL_INTENSET) Interrupt Enable Set Offset */
+#define OSC32KCTRL_INTFLAG_REG_OFST    _UINT32_(0x08)      /* (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define OSC32KCTRL_STATUS_REG_OFST     _UINT32_(0x0C)      /* (OSC32KCTRL_STATUS) Power and Clocks Status Offset */
+#define OSC32KCTRL_CLKSELCTRL_REG_OFST _UINT32_(0x10)      /* (OSC32KCTRL_CLKSELCTRL) Clock Selection Control Offset */
+#define OSC32KCTRL_CFDCTRL_REG_OFST    _UINT32_(0x14)      /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control Offset */
+#define OSC32KCTRL_EVCTRL_REG_OFST     _UINT32_(0x18)      /* (OSC32KCTRL_EVCTRL) Event Control Offset */
+#define OSC32KCTRL_XOSC32K_REG_OFST    _UINT32_(0x1C)      /* (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* OSC32KCTRL register API structure */
+typedef struct
+{  /* 32kHz Oscillators Control */
+  __IO  uint32_t                       OSC32KCTRL_INTENCLR; /* Offset: 0x00 (R/W  32) Interrupt Enable Clear */
+  __IO  uint32_t                       OSC32KCTRL_INTENSET; /* Offset: 0x04 (R/W  32) Interrupt Enable Set */
+  __IO  uint32_t                       OSC32KCTRL_INTFLAG; /* Offset: 0x08 (R/W  32) Interrupt Flag Status and Clear */
+  __I   uint32_t                       OSC32KCTRL_STATUS;  /* Offset: 0x0C (R/   32) Power and Clocks Status */
+  __IO  uint32_t                       OSC32KCTRL_CLKSELCTRL; /* Offset: 0x10 (R/W  32) Clock Selection Control */
+  __IO  uint32_t                       OSC32KCTRL_CFDCTRL; /* Offset: 0x14 (R/W  32) Clock Failure Detector Control */
+  __IO  uint32_t                       OSC32KCTRL_EVCTRL;  /* Offset: 0x18 (R/W  32) Event Control */
+  __IO  uint32_t                       OSC32KCTRL_XOSC32K; /* Offset: 0x1C (R/W  32) 32kHz External Crystal Oscillator (XOSC32K) Control */
+} osc32kctrl_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_OSC32KCTRL_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/oscctrl.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/oscctrl.h
new file mode 100644
index 00000000..1e8d689b
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/oscctrl.h
@@ -0,0 +1,652 @@
+/*
+ * Component description for OSCCTRL
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_OSCCTRL_COMPONENT_H_
+#define _PIC32CMGC00_OSCCTRL_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                    SOFTWARE API DEFINITION FOR OSCCTRL                     */
+/* ************************************************************************** */
+
+/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 32) Event Control -------- */
+#define OSCCTRL_EVCTRL_RESETVALUE             _UINT32_(0x00)                                       /*  (OSCCTRL_EVCTRL) Event Control  Reset Value */
+
+#define OSCCTRL_EVCTRL_CFDEO_Pos              _UINT32_(0)                                          /* (OSCCTRL_EVCTRL) Clock Failure Detector Event Output Enable Position */
+#define OSCCTRL_EVCTRL_CFDEO_Msk              (_UINT32_(0x1) << OSCCTRL_EVCTRL_CFDEO_Pos)          /* (OSCCTRL_EVCTRL) Clock Failure Detector Event Output Enable Mask */
+#define OSCCTRL_EVCTRL_CFDEO(value)           (OSCCTRL_EVCTRL_CFDEO_Msk & (_UINT32_(value) << OSCCTRL_EVCTRL_CFDEO_Pos)) /* Assignment of value for CFDEO in the OSCCTRL_EVCTRL register */
+#define OSCCTRL_EVCTRL_Msk                    _UINT32_(0x00000001)                                 /* (OSCCTRL_EVCTRL) Register Mask  */
+
+
+/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
+#define OSCCTRL_INTENCLR_RESETVALUE           _UINT32_(0x00)                                       /*  (OSCCTRL_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define OSCCTRL_INTENCLR_XOSCRDY_Pos          _UINT32_(0)                                          /* (OSCCTRL_INTENCLR) XOSC Ready Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_XOSCRDY_Msk          (_UINT32_(0x1) << OSCCTRL_INTENCLR_XOSCRDY_Pos)      /* (OSCCTRL_INTENCLR) XOSC Ready Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_XOSCRDY(value)       (OSCCTRL_INTENCLR_XOSCRDY_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_XOSCRDY_Pos)) /* Assignment of value for XOSCRDY in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_XOSCFAIL_Pos         _UINT32_(1)                                          /* (OSCCTRL_INTENCLR) XOSC Startup Failure Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_XOSCFAIL_Msk         (_UINT32_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)     /* (OSCCTRL_INTENCLR) XOSC Startup Failure Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_XOSCFAIL(value)      (OSCCTRL_INTENCLR_XOSCFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)) /* Assignment of value for XOSCFAIL in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_CLKFAIL_Pos          _UINT32_(2)                                          /* (OSCCTRL_INTENCLR) XOSC Clock Failure Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_CLKFAIL_Msk          (_UINT32_(0x1) << OSCCTRL_INTENCLR_CLKFAIL_Pos)      /* (OSCCTRL_INTENCLR) XOSC Clock Failure Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_CLKFAIL(value)       (OSCCTRL_INTENCLR_CLKFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_CLKFAIL_Pos)) /* Assignment of value for CLKFAIL in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_DFLLRDY_Pos          _UINT32_(8)                                          /* (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLRDY_Msk          (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)      /* (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLRDY(value)       (OSCCTRL_INTENCLR_DFLLRDY_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLRDY_Pos)) /* Assignment of value for DFLLRDY in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_DFLLLOCK_Pos         _UINT32_(9)                                          /* (OSCCTRL_INTENCLR) DFLL Lock Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLLOCK_Msk         (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLLOCK_Pos)     /* (OSCCTRL_INTENCLR) DFLL Lock Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLLOCK(value)      (OSCCTRL_INTENCLR_DFLLLOCK_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLLOCK_Pos)) /* Assignment of value for DFLLLOCK in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_DFLLOVF_Pos          _UINT32_(10)                                         /* (OSCCTRL_INTENCLR) DFLL Tuner Overflow Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLOVF_Msk          (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLOVF_Pos)      /* (OSCCTRL_INTENCLR) DFLL Tuner Overflow Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLOVF(value)       (OSCCTRL_INTENCLR_DFLLOVF_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLOVF_Pos)) /* Assignment of value for DFLLOVF in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_DFLLUNF_Pos          _UINT32_(11)                                         /* (OSCCTRL_INTENCLR) DFLL Tuner Underflow Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLUNF_Msk          (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLUNF_Pos)      /* (OSCCTRL_INTENCLR) DFLL Tuner Underflow Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLUNF(value)       (OSCCTRL_INTENCLR_DFLLUNF_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLUNF_Pos)) /* Assignment of value for DFLLUNF in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_DFLLRCS_Pos          _UINT32_(12)                                         /* (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLRCS_Msk          (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)      /* (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLRCS(value)       (OSCCTRL_INTENCLR_DFLLRCS_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLRCS_Pos)) /* Assignment of value for DFLLRCS in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_DFLLFAIL_Pos         _UINT32_(13)                                         /* (OSCCTRL_INTENCLR) DFLL Startup Failure Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLFAIL_Msk         (_UINT32_(0x1) << OSCCTRL_INTENCLR_DFLLFAIL_Pos)     /* (OSCCTRL_INTENCLR) DFLL Startup Failure Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLFAIL(value)      (OSCCTRL_INTENCLR_DFLLFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_DFLLFAIL_Pos)) /* Assignment of value for DFLLFAIL in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_PLL0LOCKR_Pos        _UINT32_(24)                                         /* (OSCCTRL_INTENCLR) PLL 0 Lock Rise Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_PLL0LOCKR_Msk        (_UINT32_(0x1) << OSCCTRL_INTENCLR_PLL0LOCKR_Pos)    /* (OSCCTRL_INTENCLR) PLL 0 Lock Rise Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_PLL0LOCKR(value)     (OSCCTRL_INTENCLR_PLL0LOCKR_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_PLL0LOCKR_Pos)) /* Assignment of value for PLL0LOCKR in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_PLL0LOCKF_Pos        _UINT32_(25)                                         /* (OSCCTRL_INTENCLR) PLL 0 Lock Fall Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_PLL0LOCKF_Msk        (_UINT32_(0x1) << OSCCTRL_INTENCLR_PLL0LOCKF_Pos)    /* (OSCCTRL_INTENCLR) PLL 0 Lock Fall Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_PLL0LOCKF(value)     (OSCCTRL_INTENCLR_PLL0LOCKF_Msk & (_UINT32_(value) << OSCCTRL_INTENCLR_PLL0LOCKF_Pos)) /* Assignment of value for PLL0LOCKF in the OSCCTRL_INTENCLR register */
+#define OSCCTRL_INTENCLR_Msk                  _UINT32_(0x03003F07)                                 /* (OSCCTRL_INTENCLR) Register Mask  */
+
+
+/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
+#define OSCCTRL_INTENSET_RESETVALUE           _UINT32_(0x00)                                       /*  (OSCCTRL_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define OSCCTRL_INTENSET_XOSCRDY_Pos          _UINT32_(0)                                          /* (OSCCTRL_INTENSET) XOSC Ready Interrupt Enable Position */
+#define OSCCTRL_INTENSET_XOSCRDY_Msk          (_UINT32_(0x1) << OSCCTRL_INTENSET_XOSCRDY_Pos)      /* (OSCCTRL_INTENSET) XOSC Ready Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_XOSCRDY(value)       (OSCCTRL_INTENSET_XOSCRDY_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_XOSCRDY_Pos)) /* Assignment of value for XOSCRDY in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_XOSCFAIL_Pos         _UINT32_(1)                                          /* (OSCCTRL_INTENSET) XOSC Startup Failure Interrupt Enable Position */
+#define OSCCTRL_INTENSET_XOSCFAIL_Msk         (_UINT32_(0x1) << OSCCTRL_INTENSET_XOSCFAIL_Pos)     /* (OSCCTRL_INTENSET) XOSC Startup Failure Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_XOSCFAIL(value)      (OSCCTRL_INTENSET_XOSCFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_XOSCFAIL_Pos)) /* Assignment of value for XOSCFAIL in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_CLKFAIL_Pos          _UINT32_(2)                                          /* (OSCCTRL_INTENSET) XOSC Clock Failure Interrupt Enable Position */
+#define OSCCTRL_INTENSET_CLKFAIL_Msk          (_UINT32_(0x1) << OSCCTRL_INTENSET_CLKFAIL_Pos)      /* (OSCCTRL_INTENSET) XOSC Clock Failure Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_CLKFAIL(value)       (OSCCTRL_INTENSET_CLKFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_CLKFAIL_Pos)) /* Assignment of value for CLKFAIL in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_DFLLRDY_Pos          _UINT32_(8)                                          /* (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLRDY_Msk          (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)      /* (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLRDY(value)       (OSCCTRL_INTENSET_DFLLRDY_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLRDY_Pos)) /* Assignment of value for DFLLRDY in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_DFLLLOCK_Pos         _UINT32_(9)                                          /* (OSCCTRL_INTENSET) DFLL Lock Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLLOCK_Msk         (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLLOCK_Pos)     /* (OSCCTRL_INTENSET) DFLL Lock Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLLOCK(value)      (OSCCTRL_INTENSET_DFLLLOCK_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLLOCK_Pos)) /* Assignment of value for DFLLLOCK in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_DFLLOVF_Pos          _UINT32_(10)                                         /* (OSCCTRL_INTENSET) DFLL Tuner Overflow Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLOVF_Msk          (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLOVF_Pos)      /* (OSCCTRL_INTENSET) DFLL Tuner Overflow Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLOVF(value)       (OSCCTRL_INTENSET_DFLLOVF_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLOVF_Pos)) /* Assignment of value for DFLLOVF in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_DFLLUNF_Pos          _UINT32_(11)                                         /* (OSCCTRL_INTENSET) DFLL Tuner Underflow Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLUNF_Msk          (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLUNF_Pos)      /* (OSCCTRL_INTENSET) DFLL Tuner Underflow Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLUNF(value)       (OSCCTRL_INTENSET_DFLLUNF_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLUNF_Pos)) /* Assignment of value for DFLLUNF in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_DFLLRCS_Pos          _UINT32_(12)                                         /* (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLRCS_Msk          (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)      /* (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLRCS(value)       (OSCCTRL_INTENSET_DFLLRCS_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLRCS_Pos)) /* Assignment of value for DFLLRCS in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_DFLLFAIL_Pos         _UINT32_(13)                                         /* (OSCCTRL_INTENSET) DFLL Startup Failure Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLFAIL_Msk         (_UINT32_(0x1) << OSCCTRL_INTENSET_DFLLFAIL_Pos)     /* (OSCCTRL_INTENSET) DFLL Startup Failure Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLFAIL(value)      (OSCCTRL_INTENSET_DFLLFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_DFLLFAIL_Pos)) /* Assignment of value for DFLLFAIL in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_PLL0LOCKR_Pos        _UINT32_(24)                                         /* (OSCCTRL_INTENSET) PLL 0 Lock Rise Interrupt Enable Position */
+#define OSCCTRL_INTENSET_PLL0LOCKR_Msk        (_UINT32_(0x1) << OSCCTRL_INTENSET_PLL0LOCKR_Pos)    /* (OSCCTRL_INTENSET) PLL 0 Lock Rise Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_PLL0LOCKR(value)     (OSCCTRL_INTENSET_PLL0LOCKR_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_PLL0LOCKR_Pos)) /* Assignment of value for PLL0LOCKR in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_PLL0LOCKF_Pos        _UINT32_(25)                                         /* (OSCCTRL_INTENSET) PLL 0 Lock Fall Interrupt Enable Position */
+#define OSCCTRL_INTENSET_PLL0LOCKF_Msk        (_UINT32_(0x1) << OSCCTRL_INTENSET_PLL0LOCKF_Pos)    /* (OSCCTRL_INTENSET) PLL 0 Lock Fall Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_PLL0LOCKF(value)     (OSCCTRL_INTENSET_PLL0LOCKF_Msk & (_UINT32_(value) << OSCCTRL_INTENSET_PLL0LOCKF_Pos)) /* Assignment of value for PLL0LOCKF in the OSCCTRL_INTENSET register */
+#define OSCCTRL_INTENSET_Msk                  _UINT32_(0x03003F07)                                 /* (OSCCTRL_INTENSET) Register Mask  */
+
+
+/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#define OSCCTRL_INTFLAG_RESETVALUE            _UINT32_(0x00)                                       /*  (OSCCTRL_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define OSCCTRL_INTFLAG_XOSCRDY_Pos           _UINT32_(0)                                          /* (OSCCTRL_INTFLAG) XOSC Ready Position */
+#define OSCCTRL_INTFLAG_XOSCRDY_Msk           (_UINT32_(0x1) << OSCCTRL_INTFLAG_XOSCRDY_Pos)       /* (OSCCTRL_INTFLAG) XOSC Ready Mask */
+#define OSCCTRL_INTFLAG_XOSCRDY(value)        (OSCCTRL_INTFLAG_XOSCRDY_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_XOSCRDY_Pos)) /* Assignment of value for XOSCRDY in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_XOSCFAIL_Pos          _UINT32_(1)                                          /* (OSCCTRL_INTFLAG) XOSC Startup Failure Position */
+#define OSCCTRL_INTFLAG_XOSCFAIL_Msk          (_UINT32_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)      /* (OSCCTRL_INTFLAG) XOSC Startup Failure Mask */
+#define OSCCTRL_INTFLAG_XOSCFAIL(value)       (OSCCTRL_INTFLAG_XOSCFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)) /* Assignment of value for XOSCFAIL in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_CLKFAIL_Pos           _UINT32_(2)                                          /* (OSCCTRL_INTFLAG) XOSC Clock Failure Position */
+#define OSCCTRL_INTFLAG_CLKFAIL_Msk           (_UINT32_(0x1) << OSCCTRL_INTFLAG_CLKFAIL_Pos)       /* (OSCCTRL_INTFLAG) XOSC Clock Failure Mask */
+#define OSCCTRL_INTFLAG_CLKFAIL(value)        (OSCCTRL_INTFLAG_CLKFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_CLKFAIL_Pos)) /* Assignment of value for CLKFAIL in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_DFLLRDY_Pos           _UINT32_(8)                                          /* (OSCCTRL_INTFLAG) DFLL Ready Position */
+#define OSCCTRL_INTFLAG_DFLLRDY_Msk           (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)       /* (OSCCTRL_INTFLAG) DFLL Ready Mask */
+#define OSCCTRL_INTFLAG_DFLLRDY(value)        (OSCCTRL_INTFLAG_DFLLRDY_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLRDY_Pos)) /* Assignment of value for DFLLRDY in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_DFLLLOCK_Pos          _UINT32_(9)                                          /* (OSCCTRL_INTFLAG) DFLL Lock Position */
+#define OSCCTRL_INTFLAG_DFLLLOCK_Msk          (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLLOCK_Pos)      /* (OSCCTRL_INTFLAG) DFLL Lock Mask */
+#define OSCCTRL_INTFLAG_DFLLLOCK(value)       (OSCCTRL_INTFLAG_DFLLLOCK_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLLOCK_Pos)) /* Assignment of value for DFLLLOCK in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_DFLLOVF_Pos           _UINT32_(10)                                         /* (OSCCTRL_INTFLAG) DFLL Tuner Overflow Position */
+#define OSCCTRL_INTFLAG_DFLLOVF_Msk           (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLOVF_Pos)       /* (OSCCTRL_INTFLAG) DFLL Tuner Overflow Mask */
+#define OSCCTRL_INTFLAG_DFLLOVF(value)        (OSCCTRL_INTFLAG_DFLLOVF_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLOVF_Pos)) /* Assignment of value for DFLLOVF in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_DFLLUNF_Pos           _UINT32_(11)                                         /* (OSCCTRL_INTFLAG) DFLL Tuner Underflow Position */
+#define OSCCTRL_INTFLAG_DFLLUNF_Msk           (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLUNF_Pos)       /* (OSCCTRL_INTFLAG) DFLL Tuner Underflow Mask */
+#define OSCCTRL_INTFLAG_DFLLUNF(value)        (OSCCTRL_INTFLAG_DFLLUNF_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLUNF_Pos)) /* Assignment of value for DFLLUNF in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_DFLLRCS_Pos           _UINT32_(12)                                         /* (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped Position */
+#define OSCCTRL_INTFLAG_DFLLRCS_Msk           (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)       /* (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped Mask */
+#define OSCCTRL_INTFLAG_DFLLRCS(value)        (OSCCTRL_INTFLAG_DFLLRCS_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLRCS_Pos)) /* Assignment of value for DFLLRCS in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_DFLLFAIL_Pos          _UINT32_(13)                                         /* (OSCCTRL_INTFLAG) DFLL Startup Failure Position */
+#define OSCCTRL_INTFLAG_DFLLFAIL_Msk          (_UINT32_(0x1) << OSCCTRL_INTFLAG_DFLLFAIL_Pos)      /* (OSCCTRL_INTFLAG) DFLL Startup Failure Mask */
+#define OSCCTRL_INTFLAG_DFLLFAIL(value)       (OSCCTRL_INTFLAG_DFLLFAIL_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_DFLLFAIL_Pos)) /* Assignment of value for DFLLFAIL in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_PLL0LOCKR_Pos         _UINT32_(24)                                         /* (OSCCTRL_INTFLAG) PLL 0 Lock Rise Position */
+#define OSCCTRL_INTFLAG_PLL0LOCKR_Msk         (_UINT32_(0x1) << OSCCTRL_INTFLAG_PLL0LOCKR_Pos)     /* (OSCCTRL_INTFLAG) PLL 0 Lock Rise Mask */
+#define OSCCTRL_INTFLAG_PLL0LOCKR(value)      (OSCCTRL_INTFLAG_PLL0LOCKR_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_PLL0LOCKR_Pos)) /* Assignment of value for PLL0LOCKR in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_PLL0LOCKF_Pos         _UINT32_(25)                                         /* (OSCCTRL_INTFLAG) PLL 0 Lock Fall Position */
+#define OSCCTRL_INTFLAG_PLL0LOCKF_Msk         (_UINT32_(0x1) << OSCCTRL_INTFLAG_PLL0LOCKF_Pos)     /* (OSCCTRL_INTFLAG) PLL 0 Lock Fall Mask */
+#define OSCCTRL_INTFLAG_PLL0LOCKF(value)      (OSCCTRL_INTFLAG_PLL0LOCKF_Msk & (_UINT32_(value) << OSCCTRL_INTFLAG_PLL0LOCKF_Pos)) /* Assignment of value for PLL0LOCKF in the OSCCTRL_INTFLAG register */
+#define OSCCTRL_INTFLAG_Msk                   _UINT32_(0x03003F07)                                 /* (OSCCTRL_INTFLAG) Register Mask  */
+
+
+/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) ( R/ 32) Status -------- */
+#define OSCCTRL_STATUS_RESETVALUE             _UINT32_(0x00)                                       /*  (OSCCTRL_STATUS) Status  Reset Value */
+
+#define OSCCTRL_STATUS_XOSCRDY_Pos            _UINT32_(0)                                          /* (OSCCTRL_STATUS) XOSC Ready Position */
+#define OSCCTRL_STATUS_XOSCRDY_Msk            (_UINT32_(0x1) << OSCCTRL_STATUS_XOSCRDY_Pos)        /* (OSCCTRL_STATUS) XOSC Ready Mask */
+#define OSCCTRL_STATUS_XOSCRDY(value)         (OSCCTRL_STATUS_XOSCRDY_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCRDY_Pos)) /* Assignment of value for XOSCRDY in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_XOSCFAIL_Pos           _UINT32_(1)                                          /* (OSCCTRL_STATUS) XOSC Startup Failure Position */
+#define OSCCTRL_STATUS_XOSCFAIL_Msk           (_UINT32_(0x1) << OSCCTRL_STATUS_XOSCFAIL_Pos)       /* (OSCCTRL_STATUS) XOSC Startup Failure Mask */
+#define OSCCTRL_STATUS_XOSCFAIL(value)        (OSCCTRL_STATUS_XOSCFAIL_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCFAIL_Pos)) /* Assignment of value for XOSCFAIL in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_CLKFAIL_Pos            _UINT32_(2)                                          /* (OSCCTRL_STATUS) XOSC Clock Failure Position */
+#define OSCCTRL_STATUS_CLKFAIL_Msk            (_UINT32_(0x1) << OSCCTRL_STATUS_CLKFAIL_Pos)        /* (OSCCTRL_STATUS) XOSC Clock Failure Mask */
+#define OSCCTRL_STATUS_CLKFAIL(value)         (OSCCTRL_STATUS_CLKFAIL_Msk & (_UINT32_(value) << OSCCTRL_STATUS_CLKFAIL_Pos)) /* Assignment of value for CLKFAIL in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_XOSCCKSW_Pos           _UINT32_(3)                                          /* (OSCCTRL_STATUS) XOSC Clock Switch Position */
+#define OSCCTRL_STATUS_XOSCCKSW_Msk           (_UINT32_(0x1) << OSCCTRL_STATUS_XOSCCKSW_Pos)       /* (OSCCTRL_STATUS) XOSC Clock Switch Mask */
+#define OSCCTRL_STATUS_XOSCCKSW(value)        (OSCCTRL_STATUS_XOSCCKSW_Msk & (_UINT32_(value) << OSCCTRL_STATUS_XOSCCKSW_Pos)) /* Assignment of value for XOSCCKSW in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_DFLLRDY_Pos            _UINT32_(8)                                          /* (OSCCTRL_STATUS) DFLL Ready Position */
+#define OSCCTRL_STATUS_DFLLRDY_Msk            (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)        /* (OSCCTRL_STATUS) DFLL Ready Mask */
+#define OSCCTRL_STATUS_DFLLRDY(value)         (OSCCTRL_STATUS_DFLLRDY_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLRDY_Pos)) /* Assignment of value for DFLLRDY in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_DFLLLOCK_Pos           _UINT32_(9)                                          /* (OSCCTRL_STATUS) DFLL Lock Position */
+#define OSCCTRL_STATUS_DFLLLOCK_Msk           (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLLOCK_Pos)       /* (OSCCTRL_STATUS) DFLL Lock Mask */
+#define OSCCTRL_STATUS_DFLLLOCK(value)        (OSCCTRL_STATUS_DFLLLOCK_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLLOCK_Pos)) /* Assignment of value for DFLLLOCK in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_DFLLOVF_Pos            _UINT32_(10)                                         /* (OSCCTRL_STATUS) DFLL Tuner Overflow Position */
+#define OSCCTRL_STATUS_DFLLOVF_Msk            (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLOVF_Pos)        /* (OSCCTRL_STATUS) DFLL Tuner Overflow Mask */
+#define OSCCTRL_STATUS_DFLLOVF(value)         (OSCCTRL_STATUS_DFLLOVF_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLOVF_Pos)) /* Assignment of value for DFLLOVF in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_DFLLUNF_Pos            _UINT32_(11)                                         /* (OSCCTRL_STATUS) DFLL Tuner Underflow Position */
+#define OSCCTRL_STATUS_DFLLUNF_Msk            (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLUNF_Pos)        /* (OSCCTRL_STATUS) DFLL Tuner Underflow Mask */
+#define OSCCTRL_STATUS_DFLLUNF(value)         (OSCCTRL_STATUS_DFLLUNF_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLUNF_Pos)) /* Assignment of value for DFLLUNF in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_DFLLRCS_Pos            _UINT32_(12)                                         /* (OSCCTRL_STATUS) DFLL Reference Clock Stopped Position */
+#define OSCCTRL_STATUS_DFLLRCS_Msk            (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)        /* (OSCCTRL_STATUS) DFLL Reference Clock Stopped Mask */
+#define OSCCTRL_STATUS_DFLLRCS(value)         (OSCCTRL_STATUS_DFLLRCS_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLRCS_Pos)) /* Assignment of value for DFLLRCS in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_DFLLFAIL_Pos           _UINT32_(13)                                         /* (OSCCTRL_STATUS) DFLL Startup Failure Position */
+#define OSCCTRL_STATUS_DFLLFAIL_Msk           (_UINT32_(0x1) << OSCCTRL_STATUS_DFLLFAIL_Pos)       /* (OSCCTRL_STATUS) DFLL Startup Failure Mask */
+#define OSCCTRL_STATUS_DFLLFAIL(value)        (OSCCTRL_STATUS_DFLLFAIL_Msk & (_UINT32_(value) << OSCCTRL_STATUS_DFLLFAIL_Pos)) /* Assignment of value for DFLLFAIL in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_PLL0LOCK_Pos           _UINT32_(24)                                         /* (OSCCTRL_STATUS) PLL 0 Lock Position */
+#define OSCCTRL_STATUS_PLL0LOCK_Msk           (_UINT32_(0x1) << OSCCTRL_STATUS_PLL0LOCK_Pos)       /* (OSCCTRL_STATUS) PLL 0 Lock Mask */
+#define OSCCTRL_STATUS_PLL0LOCK(value)        (OSCCTRL_STATUS_PLL0LOCK_Msk & (_UINT32_(value) << OSCCTRL_STATUS_PLL0LOCK_Pos)) /* Assignment of value for PLL0LOCK in the OSCCTRL_STATUS register */
+#define OSCCTRL_STATUS_Msk                    _UINT32_(0x01003F0F)                                 /* (OSCCTRL_STATUS) Register Mask  */
+
+
+/* -------- OSCCTRL_XOSCCTRLA : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control A -------- */
+#define OSCCTRL_XOSCCTRLA_RESETVALUE          _UINT32_(0xD00)                                      /*  (OSCCTRL_XOSCCTRLA) External Multipurpose Crystal Oscillator Control A  Reset Value */
+
+#define OSCCTRL_XOSCCTRLA_ENABLE_Pos          _UINT32_(1)                                          /* (OSCCTRL_XOSCCTRLA) Oscillator Enable Position */
+#define OSCCTRL_XOSCCTRLA_ENABLE_Msk          (_UINT32_(0x1) << OSCCTRL_XOSCCTRLA_ENABLE_Pos)      /* (OSCCTRL_XOSCCTRLA) Oscillator Enable Mask */
+#define OSCCTRL_XOSCCTRLA_ENABLE(value)       (OSCCTRL_XOSCCTRLA_ENABLE_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the OSCCTRL_XOSCCTRLA register */
+#define OSCCTRL_XOSCCTRLA_AGC_Pos             _UINT32_(2)                                          /* (OSCCTRL_XOSCCTRLA) Auto Gain Control Loop Enable Position */
+#define OSCCTRL_XOSCCTRLA_AGC_Msk             (_UINT32_(0x1) << OSCCTRL_XOSCCTRLA_AGC_Pos)         /* (OSCCTRL_XOSCCTRLA) Auto Gain Control Loop Enable Mask */
+#define OSCCTRL_XOSCCTRLA_AGC(value)          (OSCCTRL_XOSCCTRLA_AGC_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLA_AGC_Pos)) /* Assignment of value for AGC in the OSCCTRL_XOSCCTRLA register */
+#define OSCCTRL_XOSCCTRLA_XTALEN_Pos          _UINT32_(3)                                          /* (OSCCTRL_XOSCCTRLA) Crystal Oscillator Enable Position */
+#define OSCCTRL_XOSCCTRLA_XTALEN_Msk          (_UINT32_(0x1) << OSCCTRL_XOSCCTRLA_XTALEN_Pos)      /* (OSCCTRL_XOSCCTRLA) Crystal Oscillator Enable Mask */
+#define OSCCTRL_XOSCCTRLA_XTALEN(value)       (OSCCTRL_XOSCCTRLA_XTALEN_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLA_XTALEN_Pos)) /* Assignment of value for XTALEN in the OSCCTRL_XOSCCTRLA register */
+#define OSCCTRL_XOSCCTRLA_CFDEN_Pos           _UINT32_(4)                                          /* (OSCCTRL_XOSCCTRLA) Clock Failure Detector Enable Position */
+#define OSCCTRL_XOSCCTRLA_CFDEN_Msk           (_UINT32_(0x1) << OSCCTRL_XOSCCTRLA_CFDEN_Pos)       /* (OSCCTRL_XOSCCTRLA) Clock Failure Detector Enable Mask */
+#define OSCCTRL_XOSCCTRLA_CFDEN(value)        (OSCCTRL_XOSCCTRLA_CFDEN_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLA_CFDEN_Pos)) /* Assignment of value for CFDEN in the OSCCTRL_XOSCCTRLA register */
+#define OSCCTRL_XOSCCTRLA_SWBEN_Pos           _UINT32_(5)                                          /* (OSCCTRL_XOSCCTRLA) Xosc Clock Switch Back Enable Position */
+#define OSCCTRL_XOSCCTRLA_SWBEN_Msk           (_UINT32_(0x1) << OSCCTRL_XOSCCTRLA_SWBEN_Pos)       /* (OSCCTRL_XOSCCTRLA) Xosc Clock Switch Back Enable Mask */
+#define OSCCTRL_XOSCCTRLA_SWBEN(value)        (OSCCTRL_XOSCCTRLA_SWBEN_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLA_SWBEN_Pos)) /* Assignment of value for SWBEN in the OSCCTRL_XOSCCTRLA register */
+#define OSCCTRL_XOSCCTRLA_ONDEMAND_Pos        _UINT32_(7)                                          /* (OSCCTRL_XOSCCTRLA) On Demand Control Position */
+#define OSCCTRL_XOSCCTRLA_ONDEMAND_Msk        (_UINT32_(0x1) << OSCCTRL_XOSCCTRLA_ONDEMAND_Pos)    /* (OSCCTRL_XOSCCTRLA) On Demand Control Mask */
+#define OSCCTRL_XOSCCTRLA_ONDEMAND(value)     (OSCCTRL_XOSCCTRLA_ONDEMAND_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLA_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the OSCCTRL_XOSCCTRLA register */
+#define OSCCTRL_XOSCCTRLA_STARTUP_Pos         _UINT32_(8)                                          /* (OSCCTRL_XOSCCTRLA) Start-Up Time Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_Msk         (_UINT32_(0xF) << OSCCTRL_XOSCCTRLA_STARTUP_Pos)     /* (OSCCTRL_XOSCCTRLA) Start-Up Time Mask */
+#define OSCCTRL_XOSCCTRLA_STARTUP(value)      (OSCCTRL_XOSCCTRLA_STARTUP_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLA_STARTUP_Pos)) /* Assignment of value for STARTUP in the OSCCTRL_XOSCCTRLA register */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE1_Val _UINT32_(0x0)                                        /* (OSCCTRL_XOSCCTRLA) 31 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE2_Val _UINT32_(0x1)                                        /* (OSCCTRL_XOSCCTRLA) 61 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE4_Val _UINT32_(0x2)                                        /* (OSCCTRL_XOSCCTRLA) 122 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE8_Val _UINT32_(0x3)                                        /* (OSCCTRL_XOSCCTRLA) 244 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE16_Val _UINT32_(0x4)                                        /* (OSCCTRL_XOSCCTRLA) 488 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE32_Val _UINT32_(0x5)                                        /* (OSCCTRL_XOSCCTRLA) 977 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE64_Val _UINT32_(0x6)                                        /* (OSCCTRL_XOSCCTRLA) 1953 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE128_Val _UINT32_(0x7)                                        /* (OSCCTRL_XOSCCTRLA) 3906 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE256_Val _UINT32_(0x8)                                        /* (OSCCTRL_XOSCCTRLA) 7813 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE512_Val _UINT32_(0x9)                                        /* (OSCCTRL_XOSCCTRLA) 15625 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE1024_Val _UINT32_(0xA)                                        /* (OSCCTRL_XOSCCTRLA) 31250 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE2048_Val _UINT32_(0xB)                                        /* (OSCCTRL_XOSCCTRLA) 62500 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE4096_Val _UINT32_(0xC)                                        /* (OSCCTRL_XOSCCTRLA) 125000 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE8192_Val _UINT32_(0xD)                                        /* (OSCCTRL_XOSCCTRLA) 250000 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE16384_Val _UINT32_(0xE)                                        /* (OSCCTRL_XOSCCTRLA) 500000 us  */
+#define   OSCCTRL_XOSCCTRLA_STARTUP_CYCLE32768_Val _UINT32_(0xF)                                        /* (OSCCTRL_XOSCCTRLA) 1000000 us  */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE1      (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE1_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 31 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE2      (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE2_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 61 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE4      (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE4_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 122 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE8      (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE8_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 244 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE16     (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE16_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 488 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE32     (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE32_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 977 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE64     (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE64_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 1953 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE128    (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE128_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 3906 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE256    (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE256_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 7813 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE512    (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE512_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 15625 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE1024   (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE1024_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 31250 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE2048   (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE2048_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 62500 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE4096   (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE4096_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 125000 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE8192   (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE8192_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 250000 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE16384  (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE16384_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 500000 us Position */
+#define OSCCTRL_XOSCCTRLA_STARTUP_CYCLE32768  (OSCCTRL_XOSCCTRLA_STARTUP_CYCLE32768_Val << OSCCTRL_XOSCCTRLA_STARTUP_Pos) /* (OSCCTRL_XOSCCTRLA) 1000000 us Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_Pos        _UINT32_(16)                                         /* (OSCCTRL_XOSCCTRLA) Clock Failure Detector Prescaler Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_Msk        (_UINT32_(0xF) << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos)    /* (OSCCTRL_XOSCCTRLA) Clock Failure Detector Prescaler Mask */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC(value)     (OSCCTRL_XOSCCTRLA_CFDPRESC_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos)) /* Assignment of value for CFDPRESC in the OSCCTRL_XOSCCTRLA register */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV1_Val _UINT32_(0x0)                                        /* (OSCCTRL_XOSCCTRLA) 48 MHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV2_Val _UINT32_(0x1)                                        /* (OSCCTRL_XOSCCTRLA) 24 MHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV4_Val _UINT32_(0x2)                                        /* (OSCCTRL_XOSCCTRLA) 12 MHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV8_Val _UINT32_(0x3)                                        /* (OSCCTRL_XOSCCTRLA) 6 MHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV16_Val _UINT32_(0x4)                                        /* (OSCCTRL_XOSCCTRLA) 3 MHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV32_Val _UINT32_(0x5)                                        /* (OSCCTRL_XOSCCTRLA) 1.5 MHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV64_Val _UINT32_(0x6)                                        /* (OSCCTRL_XOSCCTRLA) 0.75 MHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV128_Val _UINT32_(0x7)                                        /* (OSCCTRL_XOSCCTRLA) 0.375 MHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV256_Val _UINT32_(0x8)                                        /* (OSCCTRL_XOSCCTRLA) 187.5 KHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV512_Val _UINT32_(0x9)                                        /* (OSCCTRL_XOSCCTRLA) 93.75 KHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV1024_Val _UINT32_(0xA)                                        /* (OSCCTRL_XOSCCTRLA) 46.875 KHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV2048_Val _UINT32_(0xB)                                        /* (OSCCTRL_XOSCCTRLA) 23.437 KHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV4096_Val _UINT32_(0xC)                                        /* (OSCCTRL_XOSCCTRLA) 11.718 KHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV8192_Val _UINT32_(0xD)                                        /* (OSCCTRL_XOSCCTRLA) 5.85 KHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV16384_Val _UINT32_(0xE)                                        /* (OSCCTRL_XOSCCTRLA) 2.92 KHz  */
+#define   OSCCTRL_XOSCCTRLA_CFDPRESC_DIV32768_Val _UINT32_(0xF)                                        /* (OSCCTRL_XOSCCTRLA) 1.46 KHz  */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV1       (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV1_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 48 MHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV2       (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV2_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 24 MHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV4       (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV4_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 12 MHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV8       (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV8_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 6 MHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV16      (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV16_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 3 MHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV32      (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV32_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 1.5 MHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV64      (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV64_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 0.75 MHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV128     (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV128_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 0.375 MHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV256     (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV256_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 187.5 KHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV512     (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV512_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 93.75 KHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV1024    (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV1024_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 46.875 KHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV2048    (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV2048_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 23.437 KHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV4096    (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV4096_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 11.718 KHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV8192    (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV8192_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 5.85 KHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV16384   (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV16384_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 2.92 KHz Position */
+#define OSCCTRL_XOSCCTRLA_CFDPRESC_DIV32768   (OSCCTRL_XOSCCTRLA_CFDPRESC_DIV32768_Val << OSCCTRL_XOSCCTRLA_CFDPRESC_Pos) /* (OSCCTRL_XOSCCTRLA) 1.46 KHz Position */
+#define OSCCTRL_XOSCCTRLA_USBHSDIV_Pos        _UINT32_(24)                                         /* (OSCCTRL_XOSCCTRLA) USBHS Referrence Clock Division Position */
+#define OSCCTRL_XOSCCTRLA_USBHSDIV_Msk        (_UINT32_(0x3) << OSCCTRL_XOSCCTRLA_USBHSDIV_Pos)    /* (OSCCTRL_XOSCCTRLA) USBHS Referrence Clock Division Mask */
+#define OSCCTRL_XOSCCTRLA_USBHSDIV(value)     (OSCCTRL_XOSCCTRLA_USBHSDIV_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLA_USBHSDIV_Pos)) /* Assignment of value for USBHSDIV in the OSCCTRL_XOSCCTRLA register */
+#define   OSCCTRL_XOSCCTRLA_USBHSDIV_DIS_Val  _UINT32_(0x0)                                        /* (OSCCTRL_XOSCCTRLA) USBHS PLL reference XOSC clock is disabled  */
+#define   OSCCTRL_XOSCCTRLA_USBHSDIV_DIV1_Val _UINT32_(0x1)                                        /* (OSCCTRL_XOSCCTRLA) USBHS PLL reference XOSC clock is divided by 1  */
+#define   OSCCTRL_XOSCCTRLA_USBHSDIV_DIV2_Val _UINT32_(0x2)                                        /* (OSCCTRL_XOSCCTRLA) USBHS PLL reference XOSC clock is divided by 2  */
+#define   OSCCTRL_XOSCCTRLA_USBHSDIV_DIV4_Val _UINT32_(0x3)                                        /* (OSCCTRL_XOSCCTRLA) USBHS PLL reference XOSC clock is divided by 4  */
+#define OSCCTRL_XOSCCTRLA_USBHSDIV_DIS        (OSCCTRL_XOSCCTRLA_USBHSDIV_DIS_Val << OSCCTRL_XOSCCTRLA_USBHSDIV_Pos) /* (OSCCTRL_XOSCCTRLA) USBHS PLL reference XOSC clock is disabled Position */
+#define OSCCTRL_XOSCCTRLA_USBHSDIV_DIV1       (OSCCTRL_XOSCCTRLA_USBHSDIV_DIV1_Val << OSCCTRL_XOSCCTRLA_USBHSDIV_Pos) /* (OSCCTRL_XOSCCTRLA) USBHS PLL reference XOSC clock is divided by 1 Position */
+#define OSCCTRL_XOSCCTRLA_USBHSDIV_DIV2       (OSCCTRL_XOSCCTRLA_USBHSDIV_DIV2_Val << OSCCTRL_XOSCCTRLA_USBHSDIV_Pos) /* (OSCCTRL_XOSCCTRLA) USBHS PLL reference XOSC clock is divided by 2 Position */
+#define OSCCTRL_XOSCCTRLA_USBHSDIV_DIV4       (OSCCTRL_XOSCCTRLA_USBHSDIV_DIV4_Val << OSCCTRL_XOSCCTRLA_USBHSDIV_Pos) /* (OSCCTRL_XOSCCTRLA) USBHS PLL reference XOSC clock is divided by 4 Position */
+#define OSCCTRL_XOSCCTRLA_WRTLOCK_Pos         _UINT32_(31)                                         /* (OSCCTRL_XOSCCTRLA) Write Lock for CTRLA register Position */
+#define OSCCTRL_XOSCCTRLA_WRTLOCK_Msk         (_UINT32_(0x1) << OSCCTRL_XOSCCTRLA_WRTLOCK_Pos)     /* (OSCCTRL_XOSCCTRLA) Write Lock for CTRLA register Mask */
+#define OSCCTRL_XOSCCTRLA_WRTLOCK(value)      (OSCCTRL_XOSCCTRLA_WRTLOCK_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLA_WRTLOCK_Pos)) /* Assignment of value for WRTLOCK in the OSCCTRL_XOSCCTRLA register */
+#define OSCCTRL_XOSCCTRLA_Msk                 _UINT32_(0x830F0FBE)                                 /* (OSCCTRL_XOSCCTRLA) Register Mask  */
+
+
+/* -------- OSCCTRL_XOSCCTRLB : (OSCCTRL Offset: 0x18) (R/W 32) External Multipurpose Crystal Oscillator Control B -------- */
+#define OSCCTRL_XOSCCTRLB_RESETVALUE          _UINT32_(0x00)                                       /*  (OSCCTRL_XOSCCTRLB) External Multipurpose Crystal Oscillator Control B  Reset Value */
+
+#define OSCCTRL_XOSCCTRLB_USRCFG_Pos          _UINT32_(0)                                          /* (OSCCTRL_XOSCCTRLB) User Configuration Control Bits Position */
+#define OSCCTRL_XOSCCTRLB_USRCFG_Msk          (_UINT32_(0xFF) << OSCCTRL_XOSCCTRLB_USRCFG_Pos)     /* (OSCCTRL_XOSCCTRLB) User Configuration Control Bits Mask */
+#define OSCCTRL_XOSCCTRLB_USRCFG(value)       (OSCCTRL_XOSCCTRLB_USRCFG_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLB_USRCFG_Pos)) /* Assignment of value for USRCFG in the OSCCTRL_XOSCCTRLB register */
+#define OSCCTRL_XOSCCTRLB_WRTLOCK_Pos         _UINT32_(31)                                         /* (OSCCTRL_XOSCCTRLB) Write Lock for CTRLB register Position */
+#define OSCCTRL_XOSCCTRLB_WRTLOCK_Msk         (_UINT32_(0x1) << OSCCTRL_XOSCCTRLB_WRTLOCK_Pos)     /* (OSCCTRL_XOSCCTRLB) Write Lock for CTRLB register Mask */
+#define OSCCTRL_XOSCCTRLB_WRTLOCK(value)      (OSCCTRL_XOSCCTRLB_WRTLOCK_Msk & (_UINT32_(value) << OSCCTRL_XOSCCTRLB_WRTLOCK_Pos)) /* Assignment of value for WRTLOCK in the OSCCTRL_XOSCCTRLB register */
+#define OSCCTRL_XOSCCTRLB_Msk                 _UINT32_(0x800000FF)                                 /* (OSCCTRL_XOSCCTRLB) Register Mask  */
+
+
+/* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x2C) (R/W 32) DFLL48M Control A -------- */
+#define OSCCTRL_DFLLCTRLA_RESETVALUE          _UINT32_(0x82)                                       /*  (OSCCTRL_DFLLCTRLA) DFLL48M Control A  Reset Value */
+
+#define OSCCTRL_DFLLCTRLA_ENABLE_Pos          _UINT32_(1)                                          /* (OSCCTRL_DFLLCTRLA) DFLL Enable Position */
+#define OSCCTRL_DFLLCTRLA_ENABLE_Msk          (_UINT32_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)      /* (OSCCTRL_DFLLCTRLA) DFLL Enable Mask */
+#define OSCCTRL_DFLLCTRLA_ENABLE(value)       (OSCCTRL_DFLLCTRLA_ENABLE_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the OSCCTRL_DFLLCTRLA register */
+#define OSCCTRL_DFLLCTRLA_WRTLOCK_Pos         _UINT32_(2)                                          /* (OSCCTRL_DFLLCTRLA) Write Lock Position */
+#define OSCCTRL_DFLLCTRLA_WRTLOCK_Msk         (_UINT32_(0x1) << OSCCTRL_DFLLCTRLA_WRTLOCK_Pos)     /* (OSCCTRL_DFLLCTRLA) Write Lock Mask */
+#define OSCCTRL_DFLLCTRLA_WRTLOCK(value)      (OSCCTRL_DFLLCTRLA_WRTLOCK_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLA_WRTLOCK_Pos)) /* Assignment of value for WRTLOCK in the OSCCTRL_DFLLCTRLA register */
+#define OSCCTRL_DFLLCTRLA_LOWFREQ_Pos         _UINT32_(3)                                          /* (OSCCTRL_DFLLCTRLA) Low Frequency Mode Position */
+#define OSCCTRL_DFLLCTRLA_LOWFREQ_Msk         (_UINT32_(0x1) << OSCCTRL_DFLLCTRLA_LOWFREQ_Pos)     /* (OSCCTRL_DFLLCTRLA) Low Frequency Mode Mask */
+#define OSCCTRL_DFLLCTRLA_LOWFREQ(value)      (OSCCTRL_DFLLCTRLA_LOWFREQ_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLA_LOWFREQ_Pos)) /* Assignment of value for LOWFREQ in the OSCCTRL_DFLLCTRLA register */
+#define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos        _UINT32_(7)                                          /* (OSCCTRL_DFLLCTRLA) On Demand Control Position */
+#define OSCCTRL_DFLLCTRLA_ONDEMAND_Msk        (_UINT32_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)    /* (OSCCTRL_DFLLCTRLA) On Demand Control Mask */
+#define OSCCTRL_DFLLCTRLA_ONDEMAND(value)     (OSCCTRL_DFLLCTRLA_ONDEMAND_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the OSCCTRL_DFLLCTRLA register */
+#define OSCCTRL_DFLLCTRLA_Msk                 _UINT32_(0x0000008E)                                 /* (OSCCTRL_DFLLCTRLA) Register Mask  */
+
+
+/* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x30) (R/W 32) DFLL48M Control B -------- */
+#define OSCCTRL_DFLLCTRLB_RESETVALUE          _UINT32_(0x00)                                       /*  (OSCCTRL_DFLLCTRLB) DFLL48M Control B  Reset Value */
+
+#define OSCCTRL_DFLLCTRLB_LOOPEN_Pos          _UINT32_(0)                                          /* (OSCCTRL_DFLLCTRLB) Operating Mode Selection Position */
+#define OSCCTRL_DFLLCTRLB_LOOPEN_Msk          (_UINT32_(0x1) << OSCCTRL_DFLLCTRLB_LOOPEN_Pos)      /* (OSCCTRL_DFLLCTRLB) Operating Mode Selection Mask */
+#define OSCCTRL_DFLLCTRLB_LOOPEN(value)       (OSCCTRL_DFLLCTRLB_LOOPEN_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLB_LOOPEN_Pos)) /* Assignment of value for LOOPEN in the OSCCTRL_DFLLCTRLB register */
+#define OSCCTRL_DFLLCTRLB_STABLE_Pos          _UINT32_(1)                                          /* (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency Position */
+#define OSCCTRL_DFLLCTRLB_STABLE_Msk          (_UINT32_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos)      /* (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency Mask */
+#define OSCCTRL_DFLLCTRLB_STABLE(value)       (OSCCTRL_DFLLCTRLB_STABLE_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLB_STABLE_Pos)) /* Assignment of value for STABLE in the OSCCTRL_DFLLCTRLB register */
+#define OSCCTRL_DFLLCTRLB_LLAW_Pos            _UINT32_(2)                                          /* (OSCCTRL_DFLLCTRLB) Lose Lock After Wake Position */
+#define OSCCTRL_DFLLCTRLB_LLAW_Msk            (_UINT32_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos)        /* (OSCCTRL_DFLLCTRLB) Lose Lock After Wake Mask */
+#define OSCCTRL_DFLLCTRLB_LLAW(value)         (OSCCTRL_DFLLCTRLB_LLAW_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLB_LLAW_Pos)) /* Assignment of value for LLAW in the OSCCTRL_DFLLCTRLB register */
+#define OSCCTRL_DFLLCTRLB_USBCRM_Pos          _UINT32_(3)                                          /* (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode Position */
+#define OSCCTRL_DFLLCTRLB_USBCRM_Msk          (_UINT32_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)      /* (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode Mask */
+#define OSCCTRL_DFLLCTRLB_USBCRM(value)       (OSCCTRL_DFLLCTRLB_USBCRM_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)) /* Assignment of value for USBCRM in the OSCCTRL_DFLLCTRLB register */
+#define OSCCTRL_DFLLCTRLB_CCDIS_Pos           _UINT32_(4)                                          /* (OSCCTRL_DFLLCTRLB) Chill Cycle Disable Position */
+#define OSCCTRL_DFLLCTRLB_CCDIS_Msk           (_UINT32_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)       /* (OSCCTRL_DFLLCTRLB) Chill Cycle Disable Mask */
+#define OSCCTRL_DFLLCTRLB_CCDIS(value)        (OSCCTRL_DFLLCTRLB_CCDIS_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)) /* Assignment of value for CCDIS in the OSCCTRL_DFLLCTRLB register */
+#define OSCCTRL_DFLLCTRLB_QLDIS_Pos           _UINT32_(5)                                          /* (OSCCTRL_DFLLCTRLB) Quick Lock Disable Position */
+#define OSCCTRL_DFLLCTRLB_QLDIS_Msk           (_UINT32_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)       /* (OSCCTRL_DFLLCTRLB) Quick Lock Disable Mask */
+#define OSCCTRL_DFLLCTRLB_QLDIS(value)        (OSCCTRL_DFLLCTRLB_QLDIS_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)) /* Assignment of value for QLDIS in the OSCCTRL_DFLLCTRLB register */
+#define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos        _UINT32_(7)                                          /* (OSCCTRL_DFLLCTRLB) Wait Lock Position */
+#define OSCCTRL_DFLLCTRLB_WAITLOCK_Msk        (_UINT32_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)    /* (OSCCTRL_DFLLCTRLB) Wait Lock Mask */
+#define OSCCTRL_DFLLCTRLB_WAITLOCK(value)     (OSCCTRL_DFLLCTRLB_WAITLOCK_Msk & (_UINT32_(value) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)) /* Assignment of value for WAITLOCK in the OSCCTRL_DFLLCTRLB register */
+#define OSCCTRL_DFLLCTRLB_Msk                 _UINT32_(0x000000BF)                                 /* (OSCCTRL_DFLLCTRLB) Register Mask  */
+
+
+/* -------- OSCCTRL_DFLLTUNE : (OSCCTRL Offset: 0x34) (R/W 32) DFLL48M Tune -------- */
+#define OSCCTRL_DFLLTUNE_RESETVALUE           _UINT32_(0x00)                                       /*  (OSCCTRL_DFLLTUNE) DFLL48M Tune  Reset Value */
+
+#define OSCCTRL_DFLLTUNE_TUNE_Pos             _UINT32_(0)                                          /* (OSCCTRL_DFLLTUNE) Tune Value Position */
+#define OSCCTRL_DFLLTUNE_TUNE_Msk             (_UINT32_(0x7F) << OSCCTRL_DFLLTUNE_TUNE_Pos)        /* (OSCCTRL_DFLLTUNE) Tune Value Mask */
+#define OSCCTRL_DFLLTUNE_TUNE(value)          (OSCCTRL_DFLLTUNE_TUNE_Msk & (_UINT32_(value) << OSCCTRL_DFLLTUNE_TUNE_Pos)) /* Assignment of value for TUNE in the OSCCTRL_DFLLTUNE register */
+#define OSCCTRL_DFLLTUNE_Msk                  _UINT32_(0x0000007F)                                 /* (OSCCTRL_DFLLTUNE) Register Mask  */
+
+
+/* -------- OSCCTRL_DFLLDIFF : (OSCCTRL Offset: 0x38) ( R/ 32) DFLL48M Diff -------- */
+#define OSCCTRL_DFLLDIFF_RESETVALUE           _UINT32_(0x00)                                       /*  (OSCCTRL_DFLLDIFF) DFLL48M Diff  Reset Value */
+
+#define OSCCTRL_DFLLDIFF_DIFF_Pos             _UINT32_(0)                                          /* (OSCCTRL_DFLLDIFF) Multiplication Ratio Difference Position */
+#define OSCCTRL_DFLLDIFF_DIFF_Msk             (_UINT32_(0xFFFF) << OSCCTRL_DFLLDIFF_DIFF_Pos)      /* (OSCCTRL_DFLLDIFF) Multiplication Ratio Difference Mask */
+#define OSCCTRL_DFLLDIFF_DIFF(value)          (OSCCTRL_DFLLDIFF_DIFF_Msk & (_UINT32_(value) << OSCCTRL_DFLLDIFF_DIFF_Pos)) /* Assignment of value for DIFF in the OSCCTRL_DFLLDIFF register */
+#define OSCCTRL_DFLLDIFF_Msk                  _UINT32_(0x0000FFFF)                                 /* (OSCCTRL_DFLLDIFF) Register Mask  */
+
+
+/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x3C) (R/W 32) DFLL48M Multiplier -------- */
+#define OSCCTRL_DFLLMUL_RESETVALUE            _UINT32_(0x00)                                       /*  (OSCCTRL_DFLLMUL) DFLL48M Multiplier  Reset Value */
+
+#define OSCCTRL_DFLLMUL_MUL_Pos               _UINT32_(0)                                          /* (OSCCTRL_DFLLMUL) DFLL Multiply Factor Position */
+#define OSCCTRL_DFLLMUL_MUL_Msk               (_UINT32_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)        /* (OSCCTRL_DFLLMUL) DFLL Multiply Factor Mask */
+#define OSCCTRL_DFLLMUL_MUL(value)            (OSCCTRL_DFLLMUL_MUL_Msk & (_UINT32_(value) << OSCCTRL_DFLLMUL_MUL_Pos)) /* Assignment of value for MUL in the OSCCTRL_DFLLMUL register */
+#define OSCCTRL_DFLLMUL_STEP_Pos              _UINT32_(16)                                         /* (OSCCTRL_DFLLMUL) Tune Maximum Step Position */
+#define OSCCTRL_DFLLMUL_STEP_Msk              (_UINT32_(0x7F) << OSCCTRL_DFLLMUL_STEP_Pos)         /* (OSCCTRL_DFLLMUL) Tune Maximum Step Mask */
+#define OSCCTRL_DFLLMUL_STEP(value)           (OSCCTRL_DFLLMUL_STEP_Msk & (_UINT32_(value) << OSCCTRL_DFLLMUL_STEP_Pos)) /* Assignment of value for STEP in the OSCCTRL_DFLLMUL register */
+#define OSCCTRL_DFLLMUL_Msk                   _UINT32_(0x007FFFFF)                                 /* (OSCCTRL_DFLLMUL) Register Mask  */
+
+
+/* -------- OSCCTRL_PLL0CTRL : (OSCCTRL Offset: 0x40) (R/W 32) PLL Control -------- */
+#define OSCCTRL_PLL0CTRL_RESETVALUE           _UINT32_(0x00)                                       /*  (OSCCTRL_PLL0CTRL) PLL Control  Reset Value */
+
+#define OSCCTRL_PLL0CTRL_ENABLE_Pos           _UINT32_(1)                                          /* (OSCCTRL_PLL0CTRL) PLL Enable Position */
+#define OSCCTRL_PLL0CTRL_ENABLE_Msk           (_UINT32_(0x1) << OSCCTRL_PLL0CTRL_ENABLE_Pos)       /* (OSCCTRL_PLL0CTRL) PLL Enable Mask */
+#define OSCCTRL_PLL0CTRL_ENABLE(value)        (OSCCTRL_PLL0CTRL_ENABLE_Msk & (_UINT32_(value) << OSCCTRL_PLL0CTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the OSCCTRL_PLL0CTRL register */
+#define OSCCTRL_PLL0CTRL_WRTLOCK_Pos          _UINT32_(2)                                          /* (OSCCTRL_PLL0CTRL) Write Lock Position */
+#define OSCCTRL_PLL0CTRL_WRTLOCK_Msk          (_UINT32_(0x1) << OSCCTRL_PLL0CTRL_WRTLOCK_Pos)      /* (OSCCTRL_PLL0CTRL) Write Lock Mask */
+#define OSCCTRL_PLL0CTRL_WRTLOCK(value)       (OSCCTRL_PLL0CTRL_WRTLOCK_Msk & (_UINT32_(value) << OSCCTRL_PLL0CTRL_WRTLOCK_Pos)) /* Assignment of value for WRTLOCK in the OSCCTRL_PLL0CTRL register */
+#define OSCCTRL_PLL0CTRL_ONDEMAND_Pos         _UINT32_(7)                                          /* (OSCCTRL_PLL0CTRL) On Demand Control Position */
+#define OSCCTRL_PLL0CTRL_ONDEMAND_Msk         (_UINT32_(0x1) << OSCCTRL_PLL0CTRL_ONDEMAND_Pos)     /* (OSCCTRL_PLL0CTRL) On Demand Control Mask */
+#define OSCCTRL_PLL0CTRL_ONDEMAND(value)      (OSCCTRL_PLL0CTRL_ONDEMAND_Msk & (_UINT32_(value) << OSCCTRL_PLL0CTRL_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the OSCCTRL_PLL0CTRL register */
+#define OSCCTRL_PLL0CTRL_REFSEL_Pos           _UINT32_(8)                                          /* (OSCCTRL_PLL0CTRL) Reference selection Position */
+#define OSCCTRL_PLL0CTRL_REFSEL_Msk           (_UINT32_(0x7) << OSCCTRL_PLL0CTRL_REFSEL_Pos)       /* (OSCCTRL_PLL0CTRL) Reference selection Mask */
+#define OSCCTRL_PLL0CTRL_REFSEL(value)        (OSCCTRL_PLL0CTRL_REFSEL_Msk & (_UINT32_(value) << OSCCTRL_PLL0CTRL_REFSEL_Pos)) /* Assignment of value for REFSEL in the OSCCTRL_PLL0CTRL register */
+#define   OSCCTRL_PLL0CTRL_REFSEL_GCLK_Val    _UINT32_(0x0)                                        /* (OSCCTRL_PLL0CTRL) Dedicated GCLK clock reference  */
+#define   OSCCTRL_PLL0CTRL_REFSEL_XOSC_Val    _UINT32_(0x1)                                        /* (OSCCTRL_PLL0CTRL) XOSC clock reference  */
+#define   OSCCTRL_PLL0CTRL_REFSEL_DFLL48M_Val _UINT32_(0x2)                                        /* (OSCCTRL_PLL0CTRL) DFLL48M clock reference  */
+#define OSCCTRL_PLL0CTRL_REFSEL_GCLK          (OSCCTRL_PLL0CTRL_REFSEL_GCLK_Val << OSCCTRL_PLL0CTRL_REFSEL_Pos) /* (OSCCTRL_PLL0CTRL) Dedicated GCLK clock reference Position */
+#define OSCCTRL_PLL0CTRL_REFSEL_XOSC          (OSCCTRL_PLL0CTRL_REFSEL_XOSC_Val << OSCCTRL_PLL0CTRL_REFSEL_Pos) /* (OSCCTRL_PLL0CTRL) XOSC clock reference Position */
+#define OSCCTRL_PLL0CTRL_REFSEL_DFLL48M       (OSCCTRL_PLL0CTRL_REFSEL_DFLL48M_Val << OSCCTRL_PLL0CTRL_REFSEL_Pos) /* (OSCCTRL_PLL0CTRL) DFLL48M clock reference Position */
+#define OSCCTRL_PLL0CTRL_BWSEL_Pos            _UINT32_(11)                                         /* (OSCCTRL_PLL0CTRL) Bandwidth selection Position */
+#define OSCCTRL_PLL0CTRL_BWSEL_Msk            (_UINT32_(0x7) << OSCCTRL_PLL0CTRL_BWSEL_Pos)        /* (OSCCTRL_PLL0CTRL) Bandwidth selection Mask */
+#define OSCCTRL_PLL0CTRL_BWSEL(value)         (OSCCTRL_PLL0CTRL_BWSEL_Msk & (_UINT32_(value) << OSCCTRL_PLL0CTRL_BWSEL_Pos)) /* Assignment of value for BWSEL in the OSCCTRL_PLL0CTRL register */
+#define   OSCCTRL_PLL0CTRL_BWSEL_BWSEL0_Val   _UINT32_(0x0)                                        /* (OSCCTRL_PLL0CTRL) TBD  */
+#define   OSCCTRL_PLL0CTRL_BWSEL_BWSEL1_Val   _UINT32_(0x1)                                        /* (OSCCTRL_PLL0CTRL) TBD  */
+#define   OSCCTRL_PLL0CTRL_BWSEL_BWSEL2_Val   _UINT32_(0x2)                                        /* (OSCCTRL_PLL0CTRL) TBD  */
+#define   OSCCTRL_PLL0CTRL_BWSEL_BWSEL3_Val   _UINT32_(0x3)                                        /* (OSCCTRL_PLL0CTRL) TBD  */
+#define   OSCCTRL_PLL0CTRL_BWSEL_BWSEL4_Val   _UINT32_(0x4)                                        /* (OSCCTRL_PLL0CTRL) TBD  */
+#define   OSCCTRL_PLL0CTRL_BWSEL_BWSEL5_Val   _UINT32_(0x5)                                        /* (OSCCTRL_PLL0CTRL) TBD  */
+#define   OSCCTRL_PLL0CTRL_BWSEL_BWSEL6_Val   _UINT32_(0x6)                                        /* (OSCCTRL_PLL0CTRL) TBD  */
+#define   OSCCTRL_PLL0CTRL_BWSEL_BWSEL7_Val   _UINT32_(0x7)                                        /* (OSCCTRL_PLL0CTRL) TBD  */
+#define OSCCTRL_PLL0CTRL_BWSEL_BWSEL0         (OSCCTRL_PLL0CTRL_BWSEL_BWSEL0_Val << OSCCTRL_PLL0CTRL_BWSEL_Pos) /* (OSCCTRL_PLL0CTRL) TBD Position */
+#define OSCCTRL_PLL0CTRL_BWSEL_BWSEL1         (OSCCTRL_PLL0CTRL_BWSEL_BWSEL1_Val << OSCCTRL_PLL0CTRL_BWSEL_Pos) /* (OSCCTRL_PLL0CTRL) TBD Position */
+#define OSCCTRL_PLL0CTRL_BWSEL_BWSEL2         (OSCCTRL_PLL0CTRL_BWSEL_BWSEL2_Val << OSCCTRL_PLL0CTRL_BWSEL_Pos) /* (OSCCTRL_PLL0CTRL) TBD Position */
+#define OSCCTRL_PLL0CTRL_BWSEL_BWSEL3         (OSCCTRL_PLL0CTRL_BWSEL_BWSEL3_Val << OSCCTRL_PLL0CTRL_BWSEL_Pos) /* (OSCCTRL_PLL0CTRL) TBD Position */
+#define OSCCTRL_PLL0CTRL_BWSEL_BWSEL4         (OSCCTRL_PLL0CTRL_BWSEL_BWSEL4_Val << OSCCTRL_PLL0CTRL_BWSEL_Pos) /* (OSCCTRL_PLL0CTRL) TBD Position */
+#define OSCCTRL_PLL0CTRL_BWSEL_BWSEL5         (OSCCTRL_PLL0CTRL_BWSEL_BWSEL5_Val << OSCCTRL_PLL0CTRL_BWSEL_Pos) /* (OSCCTRL_PLL0CTRL) TBD Position */
+#define OSCCTRL_PLL0CTRL_BWSEL_BWSEL6         (OSCCTRL_PLL0CTRL_BWSEL_BWSEL6_Val << OSCCTRL_PLL0CTRL_BWSEL_Pos) /* (OSCCTRL_PLL0CTRL) TBD Position */
+#define OSCCTRL_PLL0CTRL_BWSEL_BWSEL7         (OSCCTRL_PLL0CTRL_BWSEL_BWSEL7_Val << OSCCTRL_PLL0CTRL_BWSEL_Pos) /* (OSCCTRL_PLL0CTRL) TBD Position */
+#define OSCCTRL_PLL0CTRL_Msk                  _UINT32_(0x00003F86)                                 /* (OSCCTRL_PLL0CTRL) Register Mask  */
+
+
+/* -------- OSCCTRL_PLL0FBDIV : (OSCCTRL Offset: 0x44) (R/W 32) PLL Feed-Back Divider -------- */
+#define OSCCTRL_PLL0FBDIV_RESETVALUE          _UINT32_(0x00)                                       /*  (OSCCTRL_PLL0FBDIV) PLL Feed-Back Divider  Reset Value */
+
+#define OSCCTRL_PLL0FBDIV_FBDIV_Pos           _UINT32_(0)                                          /* (OSCCTRL_PLL0FBDIV) PLL Feed-Back Divider Factor Position */
+#define OSCCTRL_PLL0FBDIV_FBDIV_Msk           (_UINT32_(0x3FF) << OSCCTRL_PLL0FBDIV_FBDIV_Pos)     /* (OSCCTRL_PLL0FBDIV) PLL Feed-Back Divider Factor Mask */
+#define OSCCTRL_PLL0FBDIV_FBDIV(value)        (OSCCTRL_PLL0FBDIV_FBDIV_Msk & (_UINT32_(value) << OSCCTRL_PLL0FBDIV_FBDIV_Pos)) /* Assignment of value for FBDIV in the OSCCTRL_PLL0FBDIV register */
+#define OSCCTRL_PLL0FBDIV_Msk                 _UINT32_(0x000003FF)                                 /* (OSCCTRL_PLL0FBDIV) Register Mask  */
+
+
+/* -------- OSCCTRL_PLL0REFDIV : (OSCCTRL Offset: 0x48) (R/W 32) PLL reference divider -------- */
+#define OSCCTRL_PLL0REFDIV_RESETVALUE         _UINT32_(0x00)                                       /*  (OSCCTRL_PLL0REFDIV) PLL reference divider  Reset Value */
+
+#define OSCCTRL_PLL0REFDIV_REFDIV_Pos         _UINT32_(0)                                          /* (OSCCTRL_PLL0REFDIV) PLL reference division factor Position */
+#define OSCCTRL_PLL0REFDIV_REFDIV_Msk         (_UINT32_(0x3F) << OSCCTRL_PLL0REFDIV_REFDIV_Pos)    /* (OSCCTRL_PLL0REFDIV) PLL reference division factor Mask */
+#define OSCCTRL_PLL0REFDIV_REFDIV(value)      (OSCCTRL_PLL0REFDIV_REFDIV_Msk & (_UINT32_(value) << OSCCTRL_PLL0REFDIV_REFDIV_Pos)) /* Assignment of value for REFDIV in the OSCCTRL_PLL0REFDIV register */
+#define OSCCTRL_PLL0REFDIV_Msk                _UINT32_(0x0000003F)                                 /* (OSCCTRL_PLL0REFDIV) Register Mask  */
+
+
+/* -------- OSCCTRL_PLL0POSTDIVA : (OSCCTRL Offset: 0x4C) (R/W 32) PLL output clock divider A -------- */
+#define OSCCTRL_PLL0POSTDIVA_RESETVALUE       _UINT32_(0x20202020)                                 /*  (OSCCTRL_PLL0POSTDIVA) PLL output clock divider A  Reset Value */
+
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV0_Pos     _UINT32_(0)                                          /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 clock division factor Position */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV0_Msk     (_UINT32_(0x3F) << OSCCTRL_PLL0POSTDIVA_POSTDIV0_Pos) /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 clock division factor Mask */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV0(value)  (OSCCTRL_PLL0POSTDIVA_POSTDIV0_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVA_POSTDIV0_Pos)) /* Assignment of value for POSTDIV0 in the OSCCTRL_PLL0POSTDIVA register */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN0_Pos       _UINT32_(7)                                          /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 enable Position */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN0_Msk       (_UINT32_(0x1) << OSCCTRL_PLL0POSTDIVA_OUTEN0_Pos)   /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 enable Mask */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN0(value)    (OSCCTRL_PLL0POSTDIVA_OUTEN0_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVA_OUTEN0_Pos)) /* Assignment of value for OUTEN0 in the OSCCTRL_PLL0POSTDIVA register */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV1_Pos     _UINT32_(8)                                          /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 clock division factor Position */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV1_Msk     (_UINT32_(0x3F) << OSCCTRL_PLL0POSTDIVA_POSTDIV1_Pos) /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 clock division factor Mask */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV1(value)  (OSCCTRL_PLL0POSTDIVA_POSTDIV1_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVA_POSTDIV1_Pos)) /* Assignment of value for POSTDIV1 in the OSCCTRL_PLL0POSTDIVA register */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN1_Pos       _UINT32_(15)                                         /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 enable Position */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN1_Msk       (_UINT32_(0x1) << OSCCTRL_PLL0POSTDIVA_OUTEN1_Pos)   /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 enable Mask */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN1(value)    (OSCCTRL_PLL0POSTDIVA_OUTEN1_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVA_OUTEN1_Pos)) /* Assignment of value for OUTEN1 in the OSCCTRL_PLL0POSTDIVA register */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV2_Pos     _UINT32_(16)                                         /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 clock division factor Position */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV2_Msk     (_UINT32_(0x3F) << OSCCTRL_PLL0POSTDIVA_POSTDIV2_Pos) /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 clock division factor Mask */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV2(value)  (OSCCTRL_PLL0POSTDIVA_POSTDIV2_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVA_POSTDIV2_Pos)) /* Assignment of value for POSTDIV2 in the OSCCTRL_PLL0POSTDIVA register */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN2_Pos       _UINT32_(23)                                         /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 enable Position */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN2_Msk       (_UINT32_(0x1) << OSCCTRL_PLL0POSTDIVA_OUTEN2_Pos)   /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 enable Mask */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN2(value)    (OSCCTRL_PLL0POSTDIVA_OUTEN2_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVA_OUTEN2_Pos)) /* Assignment of value for OUTEN2 in the OSCCTRL_PLL0POSTDIVA register */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV3_Pos     _UINT32_(24)                                         /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 clock division factor Position */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV3_Msk     (_UINT32_(0x3F) << OSCCTRL_PLL0POSTDIVA_POSTDIV3_Pos) /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 clock division factor Mask */
+#define OSCCTRL_PLL0POSTDIVA_POSTDIV3(value)  (OSCCTRL_PLL0POSTDIVA_POSTDIV3_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVA_POSTDIV3_Pos)) /* Assignment of value for POSTDIV3 in the OSCCTRL_PLL0POSTDIVA register */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN3_Pos       _UINT32_(31)                                         /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 enable Position */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN3_Msk       (_UINT32_(0x1) << OSCCTRL_PLL0POSTDIVA_OUTEN3_Pos)   /* (OSCCTRL_PLL0POSTDIVA) PLL output 0 enable Mask */
+#define OSCCTRL_PLL0POSTDIVA_OUTEN3(value)    (OSCCTRL_PLL0POSTDIVA_OUTEN3_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVA_OUTEN3_Pos)) /* Assignment of value for OUTEN3 in the OSCCTRL_PLL0POSTDIVA register */
+#define OSCCTRL_PLL0POSTDIVA_Msk              _UINT32_(0xBFBFBFBF)                                 /* (OSCCTRL_PLL0POSTDIVA) Register Mask  */
+
+
+/* -------- OSCCTRL_PLL0POSTDIVB : (OSCCTRL Offset: 0x50) (R/W 32) PLL output clock divider B -------- */
+#define OSCCTRL_PLL0POSTDIVB_RESETVALUE       _UINT32_(0x20)                                       /*  (OSCCTRL_PLL0POSTDIVB) PLL output clock divider B  Reset Value */
+
+#define OSCCTRL_PLL0POSTDIVB_POSTDIV4_Pos     _UINT32_(0)                                          /* (OSCCTRL_PLL0POSTDIVB) PLL output 4 clock division factor Position */
+#define OSCCTRL_PLL0POSTDIVB_POSTDIV4_Msk     (_UINT32_(0x3F) << OSCCTRL_PLL0POSTDIVB_POSTDIV4_Pos) /* (OSCCTRL_PLL0POSTDIVB) PLL output 4 clock division factor Mask */
+#define OSCCTRL_PLL0POSTDIVB_POSTDIV4(value)  (OSCCTRL_PLL0POSTDIVB_POSTDIV4_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVB_POSTDIV4_Pos)) /* Assignment of value for POSTDIV4 in the OSCCTRL_PLL0POSTDIVB register */
+#define OSCCTRL_PLL0POSTDIVB_OUTEN4_Pos       _UINT32_(7)                                          /* (OSCCTRL_PLL0POSTDIVB) PLL output 4 enable Position */
+#define OSCCTRL_PLL0POSTDIVB_OUTEN4_Msk       (_UINT32_(0x1) << OSCCTRL_PLL0POSTDIVB_OUTEN4_Pos)   /* (OSCCTRL_PLL0POSTDIVB) PLL output 4 enable Mask */
+#define OSCCTRL_PLL0POSTDIVB_OUTEN4(value)    (OSCCTRL_PLL0POSTDIVB_OUTEN4_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVB_OUTEN4_Pos)) /* Assignment of value for OUTEN4 in the OSCCTRL_PLL0POSTDIVB register */
+#define OSCCTRL_PLL0POSTDIVB_Msk              _UINT32_(0x000000BF)                                 /* (OSCCTRL_PLL0POSTDIVB) Register Mask  */
+
+#define OSCCTRL_PLL0POSTDIVB_OUTEN_Pos        _UINT32_(7)                                          /* (OSCCTRL_PLL0POSTDIVB Position) PLL output 4 enable */
+#define OSCCTRL_PLL0POSTDIVB_OUTEN_Msk        (_UINT32_(0x1) << OSCCTRL_PLL0POSTDIVB_OUTEN_Pos)    /* (OSCCTRL_PLL0POSTDIVB Mask) OUTEN */
+#define OSCCTRL_PLL0POSTDIVB_OUTEN(value)     (OSCCTRL_PLL0POSTDIVB_OUTEN_Msk & (_UINT32_(value) << OSCCTRL_PLL0POSTDIVB_OUTEN_Pos)) 
+
+/* -------- OSCCTRL_SYNCBUSY : (OSCCTRL Offset: 0x78) ( R/ 32) Synchronization Busy -------- */
+#define OSCCTRL_SYNCBUSY_RESETVALUE           _UINT32_(0x00)                                       /*  (OSCCTRL_SYNCBUSY) Synchronization Busy  Reset Value */
+
+#define OSCCTRL_SYNCBUSY_DFLLENABLE_Pos       _UINT32_(1)                                          /* (OSCCTRL_SYNCBUSY) DFLL48M ENABLE Synchronization Busy Position */
+#define OSCCTRL_SYNCBUSY_DFLLENABLE_Msk       (_UINT32_(0x1) << OSCCTRL_SYNCBUSY_DFLLENABLE_Pos)   /* (OSCCTRL_SYNCBUSY) DFLL48M ENABLE Synchronization Busy Mask */
+#define OSCCTRL_SYNCBUSY_DFLLENABLE(value)    (OSCCTRL_SYNCBUSY_DFLLENABLE_Msk & (_UINT32_(value) << OSCCTRL_SYNCBUSY_DFLLENABLE_Pos)) /* Assignment of value for DFLLENABLE in the OSCCTRL_SYNCBUSY register */
+#define OSCCTRL_SYNCBUSY_DFLLCTRLB_Pos        _UINT32_(2)                                          /* (OSCCTRL_SYNCBUSY) DFLLCTRLB Synchronization Busy Position */
+#define OSCCTRL_SYNCBUSY_DFLLCTRLB_Msk        (_UINT32_(0x1) << OSCCTRL_SYNCBUSY_DFLLCTRLB_Pos)    /* (OSCCTRL_SYNCBUSY) DFLLCTRLB Synchronization Busy Mask */
+#define OSCCTRL_SYNCBUSY_DFLLCTRLB(value)     (OSCCTRL_SYNCBUSY_DFLLCTRLB_Msk & (_UINT32_(value) << OSCCTRL_SYNCBUSY_DFLLCTRLB_Pos)) /* Assignment of value for DFLLCTRLB in the OSCCTRL_SYNCBUSY register */
+#define OSCCTRL_SYNCBUSY_DFLLTUNE_Pos         _UINT32_(3)                                          /* (OSCCTRL_SYNCBUSY) DFLLTUNE Synchronization Busy Position */
+#define OSCCTRL_SYNCBUSY_DFLLTUNE_Msk         (_UINT32_(0x1) << OSCCTRL_SYNCBUSY_DFLLTUNE_Pos)     /* (OSCCTRL_SYNCBUSY) DFLLTUNE Synchronization Busy Mask */
+#define OSCCTRL_SYNCBUSY_DFLLTUNE(value)      (OSCCTRL_SYNCBUSY_DFLLTUNE_Msk & (_UINT32_(value) << OSCCTRL_SYNCBUSY_DFLLTUNE_Pos)) /* Assignment of value for DFLLTUNE in the OSCCTRL_SYNCBUSY register */
+#define OSCCTRL_SYNCBUSY_DFLLDIFF_Pos         _UINT32_(4)                                          /* (OSCCTRL_SYNCBUSY) DFLLDIFF Synchronization Busy Position */
+#define OSCCTRL_SYNCBUSY_DFLLDIFF_Msk         (_UINT32_(0x1) << OSCCTRL_SYNCBUSY_DFLLDIFF_Pos)     /* (OSCCTRL_SYNCBUSY) DFLLDIFF Synchronization Busy Mask */
+#define OSCCTRL_SYNCBUSY_DFLLDIFF(value)      (OSCCTRL_SYNCBUSY_DFLLDIFF_Msk & (_UINT32_(value) << OSCCTRL_SYNCBUSY_DFLLDIFF_Pos)) /* Assignment of value for DFLLDIFF in the OSCCTRL_SYNCBUSY register */
+#define OSCCTRL_SYNCBUSY_DFLLMUL_Pos          _UINT32_(5)                                          /* (OSCCTRL_SYNCBUSY) DFLLMUL Synchronization Busy Position */
+#define OSCCTRL_SYNCBUSY_DFLLMUL_Msk          (_UINT32_(0x1) << OSCCTRL_SYNCBUSY_DFLLMUL_Pos)      /* (OSCCTRL_SYNCBUSY) DFLLMUL Synchronization Busy Mask */
+#define OSCCTRL_SYNCBUSY_DFLLMUL(value)       (OSCCTRL_SYNCBUSY_DFLLMUL_Msk & (_UINT32_(value) << OSCCTRL_SYNCBUSY_DFLLMUL_Pos)) /* Assignment of value for DFLLMUL in the OSCCTRL_SYNCBUSY register */
+#define OSCCTRL_SYNCBUSY_FRACDIV0_Pos         _UINT32_(6)                                          /* (OSCCTRL_SYNCBUSY) FRACDIV0 Synchronization Busy Position */
+#define OSCCTRL_SYNCBUSY_FRACDIV0_Msk         (_UINT32_(0x1) << OSCCTRL_SYNCBUSY_FRACDIV0_Pos)     /* (OSCCTRL_SYNCBUSY) FRACDIV0 Synchronization Busy Mask */
+#define OSCCTRL_SYNCBUSY_FRACDIV0(value)      (OSCCTRL_SYNCBUSY_FRACDIV0_Msk & (_UINT32_(value) << OSCCTRL_SYNCBUSY_FRACDIV0_Pos)) /* Assignment of value for FRACDIV0 in the OSCCTRL_SYNCBUSY register */
+#define OSCCTRL_SYNCBUSY_FRACDIV1_Pos         _UINT32_(7)                                          /* (OSCCTRL_SYNCBUSY) FRACDIV1 Synchronization Busy Position */
+#define OSCCTRL_SYNCBUSY_FRACDIV1_Msk         (_UINT32_(0x1) << OSCCTRL_SYNCBUSY_FRACDIV1_Pos)     /* (OSCCTRL_SYNCBUSY) FRACDIV1 Synchronization Busy Mask */
+#define OSCCTRL_SYNCBUSY_FRACDIV1(value)      (OSCCTRL_SYNCBUSY_FRACDIV1_Msk & (_UINT32_(value) << OSCCTRL_SYNCBUSY_FRACDIV1_Pos)) /* Assignment of value for FRACDIV1 in the OSCCTRL_SYNCBUSY register */
+#define OSCCTRL_SYNCBUSY_Msk                  _UINT32_(0x000000FE)                                 /* (OSCCTRL_SYNCBUSY) Register Mask  */
+
+#define OSCCTRL_SYNCBUSY_FRACDIV_Pos          _UINT32_(6)                                          /* (OSCCTRL_SYNCBUSY Position) FRACDIVx Synchronization Busy */
+#define OSCCTRL_SYNCBUSY_FRACDIV_Msk          (_UINT32_(0x3) << OSCCTRL_SYNCBUSY_FRACDIV_Pos)      /* (OSCCTRL_SYNCBUSY Mask) FRACDIV */
+#define OSCCTRL_SYNCBUSY_FRACDIV(value)       (OSCCTRL_SYNCBUSY_FRACDIV_Msk & (_UINT32_(value) << OSCCTRL_SYNCBUSY_FRACDIV_Pos)) 
+
+/* -------- OSCCTRL_XOSCCAL : (OSCCTRL Offset: 0x80) (R/W 32) XOSC Calibration Register -------- */
+#define OSCCTRL_XOSCCAL_RESETVALUE            _UINT32_(0x00)                                       /*  (OSCCTRL_XOSCCAL) XOSC Calibration Register  Reset Value */
+
+#define OSCCTRL_XOSCCAL_CAL_Pos               _UINT32_(0)                                          /* (OSCCTRL_XOSCCAL) XOSC Calibration Position */
+#define OSCCTRL_XOSCCAL_CAL_Msk               (_UINT32_(0xFFFF) << OSCCTRL_XOSCCAL_CAL_Pos)        /* (OSCCTRL_XOSCCAL) XOSC Calibration Mask */
+#define OSCCTRL_XOSCCAL_CAL(value)            (OSCCTRL_XOSCCAL_CAL_Msk & (_UINT32_(value) << OSCCTRL_XOSCCAL_CAL_Pos)) /* Assignment of value for CAL in the OSCCTRL_XOSCCAL register */
+#define OSCCTRL_XOSCCAL_Msk                   _UINT32_(0x0000FFFF)                                 /* (OSCCTRL_XOSCCAL) Register Mask  */
+
+/* FUSES_OSC_XTAL_HF_AGC_V2 mode */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FTRANS_Pos _UINT32_(0)                                          /* (OSCCTRL_XOSCCAL) Fine Transconductance programmability for Oscillator Position */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FTRANS_Msk (_UINT32_(0x3) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FTRANS_Pos) /* (OSCCTRL_XOSCCAL) Fine Transconductance programmability for Oscillator Mask */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FTRANS(value) (OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FTRANS_Msk & (_UINT32_(value) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FTRANS_Pos))
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_KICKEREN_Pos _UINT32_(2)                                          /* (OSCCTRL_XOSCCAL) Kicker enable Position */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_KICKEREN_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_KICKEREN_Pos) /* (OSCCTRL_XOSCCAL) Kicker enable Mask */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_KICKEREN(value) (OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_KICKEREN_Msk & (_UINT32_(value) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_KICKEREN_Pos))
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_ENVAMP_Pos _UINT32_(3)                                          /* (OSCCTRL_XOSCCAL) envelope amplitude at osci Position */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_ENVAMP_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_ENVAMP_Pos) /* (OSCCTRL_XOSCCAL) envelope amplitude at osci Mask */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_ENVAMP(value) (OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_ENVAMP_Msk & (_UINT32_(value) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_ENVAMP_Pos))
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_HYST_Pos _UINT32_(4)                                          /* (OSCCTRL_XOSCCAL) loop hysteresis control Position */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_HYST_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_HYST_Pos) /* (OSCCTRL_XOSCCAL) loop hysteresis control Mask */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_HYST(value) (OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_HYST_Msk & (_UINT32_(value) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_HYST_Pos))
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_CMSEL_Pos _UINT32_(5)                                          /* (OSCCTRL_XOSCCAL) clock buffer common mode selection Position */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_CMSEL_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_CMSEL_Pos) /* (OSCCTRL_XOSCCAL) clock buffer common mode selection Mask */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_CMSEL(value) (OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_CMSEL_Msk & (_UINT32_(value) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_CMSEL_Pos))
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FLIPPOL_Pos _UINT32_(6)                                          /* (OSCCTRL_XOSCCAL) flip output clock polarity Position */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FLIPPOL_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FLIPPOL_Pos) /* (OSCCTRL_XOSCCAL) flip output clock polarity Mask */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FLIPPOL(value) (OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FLIPPOL_Msk & (_UINT32_(value) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_FLIPPOL_Pos))
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDGAIN_Pos _UINT32_(8)                                          /* (OSCCTRL_XOSCCAL) reduce gain control timer Position */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDGAIN_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDGAIN_Pos) /* (OSCCTRL_XOSCCAL) reduce gain control timer Mask */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDGAIN(value) (OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDGAIN_Msk & (_UINT32_(value) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDGAIN_Pos))
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDOSC_Pos _UINT32_(9)                                          /* (OSCCTRL_XOSCCAL) reduce oscillation debug counter Position */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDOSC_Msk (_UINT32_(0x1) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDOSC_Pos) /* (OSCCTRL_XOSCCAL) reduce oscillation debug counter Mask */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDOSC(value) (OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDOSC_Msk & (_UINT32_(value) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_REDOSC_Pos))
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_SPARES_Pos _UINT32_(10)                                         /* (OSCCTRL_XOSCCAL) Spare bits Position */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_SPARES_Msk (_UINT32_(0x3F) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_SPARES_Pos) /* (OSCCTRL_XOSCCAL) Spare bits Mask */
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_SPARES(value) (OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_SPARES_Msk & (_UINT32_(value) << OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_SPARES_Pos))
+#define OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_Msk _UINT32_(0x0000FF7F)                                 /* (OSCCTRL_XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2) Register Mask  */
+
+
+/* -------- OSCCTRL_RC48MCAL0 : (OSCCTRL Offset: 0x88) (R/W 32) RC48M Calibration 0 -------- */
+#define OSCCTRL_RC48MCAL0_RESETVALUE          _UINT32_(0x00)                                       /*  (OSCCTRL_RC48MCAL0) RC48M Calibration 0  Reset Value */
+
+#define OSCCTRL_RC48MCAL0_CAL_Pos             _UINT32_(0)                                          /* (OSCCTRL_RC48MCAL0) RC48M Calibration Position */
+#define OSCCTRL_RC48MCAL0_CAL_Msk             (_UINT32_(0xFFFFFFFF) << OSCCTRL_RC48MCAL0_CAL_Pos)  /* (OSCCTRL_RC48MCAL0) RC48M Calibration Mask */
+#define OSCCTRL_RC48MCAL0_CAL(value)          (OSCCTRL_RC48MCAL0_CAL_Msk & (_UINT32_(value) << OSCCTRL_RC48MCAL0_CAL_Pos)) /* Assignment of value for CAL in the OSCCTRL_RC48MCAL0 register */
+#define OSCCTRL_RC48MCAL0_Msk                 _UINT32_(0xFFFFFFFF)                                 /* (OSCCTRL_RC48MCAL0) Register Mask  */
+
+/* FUSES_OSC_RC48MHZ_V1 mode */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_temp_trim_mv_Pos _UINT32_(0)                                          /* (OSCCTRL_RC48MCAL0) Temp trim value Position */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_temp_trim_mv_Msk (_UINT32_(0x3F) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_temp_trim_mv_Pos) /* (OSCCTRL_RC48MCAL0) Temp trim value Mask */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_temp_trim_mv(value) (OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_temp_trim_mv_Msk & (_UINT32_(value) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_temp_trim_mv_Pos))
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_proc_trim_mv_Pos _UINT32_(6)                                          /* (OSCCTRL_RC48MCAL0) Proc trim value Position */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_proc_trim_mv_Msk (_UINT32_(0xFF) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_proc_trim_mv_Pos) /* (OSCCTRL_RC48MCAL0) Proc trim value Mask */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_proc_trim_mv(value) (OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_proc_trim_mv_Msk & (_UINT32_(value) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_proc_trim_mv_Pos))
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_iosc_boost_Pos _UINT32_(16)                                         /* (OSCCTRL_RC48MCAL0) IOSC boost Position */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_iosc_boost_Msk (_UINT32_(0x1) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_iosc_boost_Pos) /* (OSCCTRL_RC48MCAL0) IOSC boost Mask */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_iosc_boost(value) (OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_iosc_boost_Msk & (_UINT32_(value) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_iosc_boost_Pos))
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_out_buf_sel_Pos _UINT32_(17)                                         /* (OSCCTRL_RC48MCAL0) Output buffer select Position */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_out_buf_sel_Msk (_UINT32_(0x1) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_out_buf_sel_Pos) /* (OSCCTRL_RC48MCAL0) Output buffer select Mask */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_out_buf_sel(value) (OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_out_buf_sel_Msk & (_UINT32_(value) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_out_buf_sel_Pos))
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_ldo_vout_boost_Pos _UINT32_(18)                                         /* (OSCCTRL_RC48MCAL0) LDO VOUT boost Position */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_ldo_vout_boost_Msk (_UINT32_(0x1) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_ldo_vout_boost_Pos) /* (OSCCTRL_RC48MCAL0) LDO VOUT boost Mask */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_ldo_vout_boost(value) (OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_ldo_vout_boost_Msk & (_UINT32_(value) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_ldo_vout_boost_Pos))
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_8m_lp_Pos _UINT32_(19)                                         /* (OSCCTRL_RC48MCAL0) Comparator 8MHz low-power Position */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_8m_lp_Msk (_UINT32_(0x1) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_8m_lp_Pos) /* (OSCCTRL_RC48MCAL0) Comparator 8MHz low-power Mask */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_8m_lp(value) (OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_8m_lp_Msk & (_UINT32_(value) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_8m_lp_Pos))
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_pwr_ctrl_Pos _UINT32_(20)                                         /* (OSCCTRL_RC48MCAL0) Comparator power control Position */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_pwr_ctrl_Msk (_UINT32_(0x7) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_pwr_ctrl_Pos) /* (OSCCTRL_RC48MCAL0) Comparator power control Mask */
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_pwr_ctrl(value) (OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_pwr_ctrl_Msk & (_UINT32_(value) << OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_cmp_pwr_ctrl_Pos))
+#define OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1_Msk _UINT32_(0x007F3FFF)                                 /* (OSCCTRL_RC48MCAL0_FUSES_OSC_RC48MHZ_V1) Register Mask  */
+
+
+/* OSCCTRL register offsets definitions */
+#define OSCCTRL_EVCTRL_REG_OFST        _UINT32_(0x00)      /* (OSCCTRL_EVCTRL) Event Control Offset */
+#define OSCCTRL_INTENCLR_REG_OFST      _UINT32_(0x04)      /* (OSCCTRL_INTENCLR) Interrupt Enable Clear Offset */
+#define OSCCTRL_INTENSET_REG_OFST      _UINT32_(0x08)      /* (OSCCTRL_INTENSET) Interrupt Enable Set Offset */
+#define OSCCTRL_INTFLAG_REG_OFST       _UINT32_(0x0C)      /* (OSCCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define OSCCTRL_STATUS_REG_OFST        _UINT32_(0x10)      /* (OSCCTRL_STATUS) Status Offset */
+#define OSCCTRL_XOSCCTRLA_REG_OFST     _UINT32_(0x14)      /* (OSCCTRL_XOSCCTRLA) External Multipurpose Crystal Oscillator Control A Offset */
+#define OSCCTRL_XOSCCTRLB_REG_OFST     _UINT32_(0x18)      /* (OSCCTRL_XOSCCTRLB) External Multipurpose Crystal Oscillator Control B Offset */
+#define OSCCTRL_DFLLCTRLA_REG_OFST     _UINT32_(0x2C)      /* (OSCCTRL_DFLLCTRLA) DFLL48M Control A Offset */
+#define OSCCTRL_DFLLCTRLB_REG_OFST     _UINT32_(0x30)      /* (OSCCTRL_DFLLCTRLB) DFLL48M Control B Offset */
+#define OSCCTRL_DFLLTUNE_REG_OFST      _UINT32_(0x34)      /* (OSCCTRL_DFLLTUNE) DFLL48M Tune Offset */
+#define OSCCTRL_DFLLDIFF_REG_OFST      _UINT32_(0x38)      /* (OSCCTRL_DFLLDIFF) DFLL48M Diff Offset */
+#define OSCCTRL_DFLLMUL_REG_OFST       _UINT32_(0x3C)      /* (OSCCTRL_DFLLMUL) DFLL48M Multiplier Offset */
+#define OSCCTRL_PLL0CTRL_REG_OFST      _UINT32_(0x40)      /* (OSCCTRL_PLL0CTRL) PLL Control Offset */
+#define OSCCTRL_PLL0FBDIV_REG_OFST     _UINT32_(0x44)      /* (OSCCTRL_PLL0FBDIV) PLL Feed-Back Divider Offset */
+#define OSCCTRL_PLL0REFDIV_REG_OFST    _UINT32_(0x48)      /* (OSCCTRL_PLL0REFDIV) PLL reference divider Offset */
+#define OSCCTRL_PLL0POSTDIVA_REG_OFST  _UINT32_(0x4C)      /* (OSCCTRL_PLL0POSTDIVA) PLL output clock divider A Offset */
+#define OSCCTRL_PLL0POSTDIVB_REG_OFST  _UINT32_(0x50)      /* (OSCCTRL_PLL0POSTDIVB) PLL output clock divider B Offset */
+#define OSCCTRL_SYNCBUSY_REG_OFST      _UINT32_(0x78)      /* (OSCCTRL_SYNCBUSY) Synchronization Busy Offset */
+#define OSCCTRL_XOSCCAL_REG_OFST       _UINT32_(0x80)      /* (OSCCTRL_XOSCCAL) XOSC Calibration Register Offset */
+#define OSCCTRL_RC48MCAL0_REG_OFST     _UINT32_(0x88)      /* (OSCCTRL_RC48MCAL0) RC48M Calibration 0 Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* OSCCTRL register API structure */
+typedef struct
+{  /* Oscillators Control */
+  __IO  uint32_t                       OSCCTRL_EVCTRL;     /* Offset: 0x00 (R/W  32) Event Control */
+  __IO  uint32_t                       OSCCTRL_INTENCLR;   /* Offset: 0x04 (R/W  32) Interrupt Enable Clear */
+  __IO  uint32_t                       OSCCTRL_INTENSET;   /* Offset: 0x08 (R/W  32) Interrupt Enable Set */
+  __IO  uint32_t                       OSCCTRL_INTFLAG;    /* Offset: 0x0C (R/W  32) Interrupt Flag Status and Clear */
+  __I   uint32_t                       OSCCTRL_STATUS;     /* Offset: 0x10 (R/   32) Status */
+  __IO  uint32_t                       OSCCTRL_XOSCCTRLA;  /* Offset: 0x14 (R/W  32) External Multipurpose Crystal Oscillator Control A */
+  __IO  uint32_t                       OSCCTRL_XOSCCTRLB;  /* Offset: 0x18 (R/W  32) External Multipurpose Crystal Oscillator Control B */
+  __I   uint8_t                        Reserved1[0x10];
+  __IO  uint32_t                       OSCCTRL_DFLLCTRLA;  /* Offset: 0x2C (R/W  32) DFLL48M Control A */
+  __IO  uint32_t                       OSCCTRL_DFLLCTRLB;  /* Offset: 0x30 (R/W  32) DFLL48M Control B */
+  __IO  uint32_t                       OSCCTRL_DFLLTUNE;   /* Offset: 0x34 (R/W  32) DFLL48M Tune */
+  __I   uint32_t                       OSCCTRL_DFLLDIFF;   /* Offset: 0x38 (R/   32) DFLL48M Diff */
+  __IO  uint32_t                       OSCCTRL_DFLLMUL;    /* Offset: 0x3C (R/W  32) DFLL48M Multiplier */
+  __IO  uint32_t                       OSCCTRL_PLL0CTRL;   /* Offset: 0x40 (R/W  32) PLL Control */
+  __IO  uint32_t                       OSCCTRL_PLL0FBDIV;  /* Offset: 0x44 (R/W  32) PLL Feed-Back Divider */
+  __IO  uint32_t                       OSCCTRL_PLL0REFDIV; /* Offset: 0x48 (R/W  32) PLL reference divider */
+  __IO  uint32_t                       OSCCTRL_PLL0POSTDIVA; /* Offset: 0x4C (R/W  32) PLL output clock divider A */
+  __IO  uint32_t                       OSCCTRL_PLL0POSTDIVB; /* Offset: 0x50 (R/W  32) PLL output clock divider B */
+  __I   uint8_t                        Reserved2[0x24];
+  __I   uint32_t                       OSCCTRL_SYNCBUSY;   /* Offset: 0x78 (R/   32) Synchronization Busy */
+  __I   uint8_t                        Reserved3[0x04];
+  __IO  uint32_t                       OSCCTRL_XOSCCAL;    /* Offset: 0x80 (R/W  32) XOSC Calibration Register */
+  __I   uint8_t                        Reserved4[0x04];
+  __IO  uint32_t                       OSCCTRL_RC48MCAL0;  /* Offset: 0x88 (R/W  32) RC48M Calibration 0 */
+} oscctrl_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_OSCCTRL_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/pac.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/pac.h
new file mode 100644
index 00000000..09dde6c7
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/pac.h
@@ -0,0 +1,556 @@
+/*
+ * Component description for PAC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_PAC_COMPONENT_H_
+#define _PIC32CMGC00_PAC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR PAC                       */
+/* ************************************************************************** */
+
+/* -------- PAC_CTRLA : (PAC Offset: 0x00) (R/W 32) Control A Register -------- */
+#define PAC_CTRLA_RESETVALUE                  _UINT32_(0x00)                                       /*  (PAC_CTRLA) Control A Register  Reset Value */
+
+#define PAC_CTRLA_PRIV_Pos                    _UINT32_(2)                                          /* (PAC_CTRLA) Privileged Access Only Position */
+#define PAC_CTRLA_PRIV_Msk                    (_UINT32_(0x1) << PAC_CTRLA_PRIV_Pos)                /* (PAC_CTRLA) Privileged Access Only Mask */
+#define PAC_CTRLA_PRIV(value)                 (PAC_CTRLA_PRIV_Msk & (_UINT32_(value) << PAC_CTRLA_PRIV_Pos)) /* Assignment of value for PRIV in the PAC_CTRLA register */
+#define   PAC_CTRLA_PRIV_DISABLE_Val          _UINT32_(0x0)                                        /* (PAC_CTRLA) Macro register accessible in privileged and unprivileged accesses.  */
+#define   PAC_CTRLA_PRIV_ENABLE_Val           _UINT32_(0x1)                                        /* (PAC_CTRLA) Macro registers only accessible in privileged accesses  */
+#define PAC_CTRLA_PRIV_DISABLE                (PAC_CTRLA_PRIV_DISABLE_Val << PAC_CTRLA_PRIV_Pos)   /* (PAC_CTRLA) Macro register accessible in privileged and unprivileged accesses. Position */
+#define PAC_CTRLA_PRIV_ENABLE                 (PAC_CTRLA_PRIV_ENABLE_Val << PAC_CTRLA_PRIV_Pos)    /* (PAC_CTRLA) Macro registers only accessible in privileged accesses Position */
+#define PAC_CTRLA_Msk                         _UINT32_(0x00000004)                                 /* (PAC_CTRLA) Register Mask  */
+
+
+/* -------- PAC_WRCTRL : (PAC Offset: 0x04) ( /W 32) Write Control Register -------- */
+#define PAC_WRCTRL_RESETVALUE                 _UINT32_(0x00)                                       /*  (PAC_WRCTRL) Write Control Register  Reset Value */
+
+#define PAC_WRCTRL_PERID_Pos                  _UINT32_(0)                                          /* (PAC_WRCTRL) Peripheral Identifier Position */
+#define PAC_WRCTRL_PERID_Msk                  (_UINT32_(0xFF) << PAC_WRCTRL_PERID_Pos)             /* (PAC_WRCTRL) Peripheral Identifier Mask */
+#define PAC_WRCTRL_PERID(value)               (PAC_WRCTRL_PERID_Msk & (_UINT32_(value) << PAC_WRCTRL_PERID_Pos)) /* Assignment of value for PERID in the PAC_WRCTRL register */
+#define PAC_WRCTRL_KEY_Pos                    _UINT32_(16)                                         /* (PAC_WRCTRL) Peripheral Access Control Key Position */
+#define PAC_WRCTRL_KEY_Msk                    (_UINT32_(0xFF) << PAC_WRCTRL_KEY_Pos)               /* (PAC_WRCTRL) Peripheral Access Control Key Mask */
+#define PAC_WRCTRL_KEY(value)                 (PAC_WRCTRL_KEY_Msk & (_UINT32_(value) << PAC_WRCTRL_KEY_Pos)) /* Assignment of value for KEY in the PAC_WRCTRL register */
+#define   PAC_WRCTRL_KEY_OFF_Val              _UINT32_(0x0)                                        /* (PAC_WRCTRL) OFF - No Action  */
+#define   PAC_WRCTRL_KEY_CLEAR_Val            _UINT32_(0x1)                                        /* (PAC_WRCTRL) CLEAR - Clear the peripheral write protection  */
+#define   PAC_WRCTRL_KEY_SET_Val              _UINT32_(0x2)                                        /* (PAC_WRCTRL) SET - Set the peripheral write protection  */
+#define   PAC_WRCTRL_KEY_LOCK_Val             _UINT32_(0x3)                                        /* (PAC_WRCTRL) LOCK - Set and Lock the write protection state of the peripheral until the next reset  */
+#define PAC_WRCTRL_KEY_OFF                    (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos)       /* (PAC_WRCTRL) OFF - No Action Position */
+#define PAC_WRCTRL_KEY_CLEAR                  (PAC_WRCTRL_KEY_CLEAR_Val << PAC_WRCTRL_KEY_Pos)     /* (PAC_WRCTRL) CLEAR - Clear the peripheral write protection Position */
+#define PAC_WRCTRL_KEY_SET                    (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos)       /* (PAC_WRCTRL) SET - Set the peripheral write protection Position */
+#define PAC_WRCTRL_KEY_LOCK                   (PAC_WRCTRL_KEY_LOCK_Val << PAC_WRCTRL_KEY_Pos)      /* (PAC_WRCTRL) LOCK - Set and Lock the write protection state of the peripheral until the next reset Position */
+#define PAC_WRCTRL_Msk                        _UINT32_(0x00FF00FF)                                 /* (PAC_WRCTRL) Register Mask  */
+
+
+/* -------- PAC_STATUS : (PAC Offset: 0x40) ( R/ 32) Peripheral Status n Register -------- */
+#define PAC_STATUS_RESETVALUE                 _UINT32_(0x00)                                       /*  (PAC_STATUS) Peripheral Status n Register  Reset Value */
+
+#define PAC_STATUS_PERID0_Pos                 _UINT32_(0)                                          /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID0_Msk                 (_UINT32_(0x1) << PAC_STATUS_PERID0_Pos)             /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID0(value)              (PAC_STATUS_PERID0_Msk & (_UINT32_(value) << PAC_STATUS_PERID0_Pos)) /* Assignment of value for PERID0 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID0_0_Val             _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID0_1_Val             _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID0_0                   (PAC_STATUS_PERID0_0_Val << PAC_STATUS_PERID0_Pos)   /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID0_1                   (PAC_STATUS_PERID0_1_Val << PAC_STATUS_PERID0_Pos)   /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID1_Pos                 _UINT32_(1)                                          /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID1_Msk                 (_UINT32_(0x1) << PAC_STATUS_PERID1_Pos)             /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID1(value)              (PAC_STATUS_PERID1_Msk & (_UINT32_(value) << PAC_STATUS_PERID1_Pos)) /* Assignment of value for PERID1 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID1_0_Val             _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID1_1_Val             _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID1_0                   (PAC_STATUS_PERID1_0_Val << PAC_STATUS_PERID1_Pos)   /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID1_1                   (PAC_STATUS_PERID1_1_Val << PAC_STATUS_PERID1_Pos)   /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID2_Pos                 _UINT32_(2)                                          /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID2_Msk                 (_UINT32_(0x1) << PAC_STATUS_PERID2_Pos)             /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID2(value)              (PAC_STATUS_PERID2_Msk & (_UINT32_(value) << PAC_STATUS_PERID2_Pos)) /* Assignment of value for PERID2 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID2_0_Val             _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID2_1_Val             _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID2_0                   (PAC_STATUS_PERID2_0_Val << PAC_STATUS_PERID2_Pos)   /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID2_1                   (PAC_STATUS_PERID2_1_Val << PAC_STATUS_PERID2_Pos)   /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID3_Pos                 _UINT32_(3)                                          /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID3_Msk                 (_UINT32_(0x1) << PAC_STATUS_PERID3_Pos)             /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID3(value)              (PAC_STATUS_PERID3_Msk & (_UINT32_(value) << PAC_STATUS_PERID3_Pos)) /* Assignment of value for PERID3 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID3_0_Val             _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID3_1_Val             _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID3_0                   (PAC_STATUS_PERID3_0_Val << PAC_STATUS_PERID3_Pos)   /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID3_1                   (PAC_STATUS_PERID3_1_Val << PAC_STATUS_PERID3_Pos)   /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID4_Pos                 _UINT32_(4)                                          /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID4_Msk                 (_UINT32_(0x1) << PAC_STATUS_PERID4_Pos)             /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID4(value)              (PAC_STATUS_PERID4_Msk & (_UINT32_(value) << PAC_STATUS_PERID4_Pos)) /* Assignment of value for PERID4 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID4_0_Val             _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID4_1_Val             _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID4_0                   (PAC_STATUS_PERID4_0_Val << PAC_STATUS_PERID4_Pos)   /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID4_1                   (PAC_STATUS_PERID4_1_Val << PAC_STATUS_PERID4_Pos)   /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID5_Pos                 _UINT32_(5)                                          /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID5_Msk                 (_UINT32_(0x1) << PAC_STATUS_PERID5_Pos)             /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID5(value)              (PAC_STATUS_PERID5_Msk & (_UINT32_(value) << PAC_STATUS_PERID5_Pos)) /* Assignment of value for PERID5 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID5_0_Val             _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID5_1_Val             _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID5_0                   (PAC_STATUS_PERID5_0_Val << PAC_STATUS_PERID5_Pos)   /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID5_1                   (PAC_STATUS_PERID5_1_Val << PAC_STATUS_PERID5_Pos)   /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID6_Pos                 _UINT32_(6)                                          /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID6_Msk                 (_UINT32_(0x1) << PAC_STATUS_PERID6_Pos)             /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID6(value)              (PAC_STATUS_PERID6_Msk & (_UINT32_(value) << PAC_STATUS_PERID6_Pos)) /* Assignment of value for PERID6 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID6_0_Val             _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID6_1_Val             _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID6_0                   (PAC_STATUS_PERID6_0_Val << PAC_STATUS_PERID6_Pos)   /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID6_1                   (PAC_STATUS_PERID6_1_Val << PAC_STATUS_PERID6_Pos)   /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID7_Pos                 _UINT32_(7)                                          /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID7_Msk                 (_UINT32_(0x1) << PAC_STATUS_PERID7_Pos)             /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID7(value)              (PAC_STATUS_PERID7_Msk & (_UINT32_(value) << PAC_STATUS_PERID7_Pos)) /* Assignment of value for PERID7 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID7_0_Val             _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID7_1_Val             _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID7_0                   (PAC_STATUS_PERID7_0_Val << PAC_STATUS_PERID7_Pos)   /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID7_1                   (PAC_STATUS_PERID7_1_Val << PAC_STATUS_PERID7_Pos)   /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID8_Pos                 _UINT32_(8)                                          /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID8_Msk                 (_UINT32_(0x1) << PAC_STATUS_PERID8_Pos)             /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID8(value)              (PAC_STATUS_PERID8_Msk & (_UINT32_(value) << PAC_STATUS_PERID8_Pos)) /* Assignment of value for PERID8 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID8_0_Val             _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID8_1_Val             _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID8_0                   (PAC_STATUS_PERID8_0_Val << PAC_STATUS_PERID8_Pos)   /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID8_1                   (PAC_STATUS_PERID8_1_Val << PAC_STATUS_PERID8_Pos)   /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID9_Pos                 _UINT32_(9)                                          /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID9_Msk                 (_UINT32_(0x1) << PAC_STATUS_PERID9_Pos)             /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID9(value)              (PAC_STATUS_PERID9_Msk & (_UINT32_(value) << PAC_STATUS_PERID9_Pos)) /* Assignment of value for PERID9 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID9_0_Val             _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID9_1_Val             _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID9_0                   (PAC_STATUS_PERID9_0_Val << PAC_STATUS_PERID9_Pos)   /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID9_1                   (PAC_STATUS_PERID9_1_Val << PAC_STATUS_PERID9_Pos)   /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID10_Pos                _UINT32_(10)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID10_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID10_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID10(value)             (PAC_STATUS_PERID10_Msk & (_UINT32_(value) << PAC_STATUS_PERID10_Pos)) /* Assignment of value for PERID10 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID10_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID10_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID10_0                  (PAC_STATUS_PERID10_0_Val << PAC_STATUS_PERID10_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID10_1                  (PAC_STATUS_PERID10_1_Val << PAC_STATUS_PERID10_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID11_Pos                _UINT32_(11)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID11_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID11_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID11(value)             (PAC_STATUS_PERID11_Msk & (_UINT32_(value) << PAC_STATUS_PERID11_Pos)) /* Assignment of value for PERID11 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID11_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID11_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID11_0                  (PAC_STATUS_PERID11_0_Val << PAC_STATUS_PERID11_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID11_1                  (PAC_STATUS_PERID11_1_Val << PAC_STATUS_PERID11_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID12_Pos                _UINT32_(12)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID12_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID12_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID12(value)             (PAC_STATUS_PERID12_Msk & (_UINT32_(value) << PAC_STATUS_PERID12_Pos)) /* Assignment of value for PERID12 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID12_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID12_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID12_0                  (PAC_STATUS_PERID12_0_Val << PAC_STATUS_PERID12_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID12_1                  (PAC_STATUS_PERID12_1_Val << PAC_STATUS_PERID12_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID13_Pos                _UINT32_(13)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID13_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID13_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID13(value)             (PAC_STATUS_PERID13_Msk & (_UINT32_(value) << PAC_STATUS_PERID13_Pos)) /* Assignment of value for PERID13 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID13_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID13_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID13_0                  (PAC_STATUS_PERID13_0_Val << PAC_STATUS_PERID13_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID13_1                  (PAC_STATUS_PERID13_1_Val << PAC_STATUS_PERID13_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID14_Pos                _UINT32_(14)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID14_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID14_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID14(value)             (PAC_STATUS_PERID14_Msk & (_UINT32_(value) << PAC_STATUS_PERID14_Pos)) /* Assignment of value for PERID14 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID14_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID14_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID14_0                  (PAC_STATUS_PERID14_0_Val << PAC_STATUS_PERID14_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID14_1                  (PAC_STATUS_PERID14_1_Val << PAC_STATUS_PERID14_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID15_Pos                _UINT32_(15)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID15_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID15_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID15(value)             (PAC_STATUS_PERID15_Msk & (_UINT32_(value) << PAC_STATUS_PERID15_Pos)) /* Assignment of value for PERID15 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID15_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID15_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID15_0                  (PAC_STATUS_PERID15_0_Val << PAC_STATUS_PERID15_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID15_1                  (PAC_STATUS_PERID15_1_Val << PAC_STATUS_PERID15_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID16_Pos                _UINT32_(16)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID16_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID16_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID16(value)             (PAC_STATUS_PERID16_Msk & (_UINT32_(value) << PAC_STATUS_PERID16_Pos)) /* Assignment of value for PERID16 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID16_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID16_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID16_0                  (PAC_STATUS_PERID16_0_Val << PAC_STATUS_PERID16_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID16_1                  (PAC_STATUS_PERID16_1_Val << PAC_STATUS_PERID16_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID17_Pos                _UINT32_(17)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID17_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID17_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID17(value)             (PAC_STATUS_PERID17_Msk & (_UINT32_(value) << PAC_STATUS_PERID17_Pos)) /* Assignment of value for PERID17 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID17_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID17_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID17_0                  (PAC_STATUS_PERID17_0_Val << PAC_STATUS_PERID17_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID17_1                  (PAC_STATUS_PERID17_1_Val << PAC_STATUS_PERID17_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID18_Pos                _UINT32_(18)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID18_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID18_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID18(value)             (PAC_STATUS_PERID18_Msk & (_UINT32_(value) << PAC_STATUS_PERID18_Pos)) /* Assignment of value for PERID18 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID18_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID18_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID18_0                  (PAC_STATUS_PERID18_0_Val << PAC_STATUS_PERID18_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID18_1                  (PAC_STATUS_PERID18_1_Val << PAC_STATUS_PERID18_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID19_Pos                _UINT32_(19)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID19_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID19_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID19(value)             (PAC_STATUS_PERID19_Msk & (_UINT32_(value) << PAC_STATUS_PERID19_Pos)) /* Assignment of value for PERID19 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID19_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID19_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID19_0                  (PAC_STATUS_PERID19_0_Val << PAC_STATUS_PERID19_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID19_1                  (PAC_STATUS_PERID19_1_Val << PAC_STATUS_PERID19_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID20_Pos                _UINT32_(20)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID20_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID20_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID20(value)             (PAC_STATUS_PERID20_Msk & (_UINT32_(value) << PAC_STATUS_PERID20_Pos)) /* Assignment of value for PERID20 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID20_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID20_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID20_0                  (PAC_STATUS_PERID20_0_Val << PAC_STATUS_PERID20_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID20_1                  (PAC_STATUS_PERID20_1_Val << PAC_STATUS_PERID20_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID21_Pos                _UINT32_(21)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID21_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID21_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID21(value)             (PAC_STATUS_PERID21_Msk & (_UINT32_(value) << PAC_STATUS_PERID21_Pos)) /* Assignment of value for PERID21 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID21_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID21_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID21_0                  (PAC_STATUS_PERID21_0_Val << PAC_STATUS_PERID21_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID21_1                  (PAC_STATUS_PERID21_1_Val << PAC_STATUS_PERID21_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID22_Pos                _UINT32_(22)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID22_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID22_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID22(value)             (PAC_STATUS_PERID22_Msk & (_UINT32_(value) << PAC_STATUS_PERID22_Pos)) /* Assignment of value for PERID22 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID22_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID22_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID22_0                  (PAC_STATUS_PERID22_0_Val << PAC_STATUS_PERID22_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID22_1                  (PAC_STATUS_PERID22_1_Val << PAC_STATUS_PERID22_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID23_Pos                _UINT32_(23)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID23_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID23_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID23(value)             (PAC_STATUS_PERID23_Msk & (_UINT32_(value) << PAC_STATUS_PERID23_Pos)) /* Assignment of value for PERID23 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID23_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID23_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID23_0                  (PAC_STATUS_PERID23_0_Val << PAC_STATUS_PERID23_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID23_1                  (PAC_STATUS_PERID23_1_Val << PAC_STATUS_PERID23_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID24_Pos                _UINT32_(24)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID24_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID24_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID24(value)             (PAC_STATUS_PERID24_Msk & (_UINT32_(value) << PAC_STATUS_PERID24_Pos)) /* Assignment of value for PERID24 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID24_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID24_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID24_0                  (PAC_STATUS_PERID24_0_Val << PAC_STATUS_PERID24_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID24_1                  (PAC_STATUS_PERID24_1_Val << PAC_STATUS_PERID24_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID25_Pos                _UINT32_(25)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID25_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID25_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID25(value)             (PAC_STATUS_PERID25_Msk & (_UINT32_(value) << PAC_STATUS_PERID25_Pos)) /* Assignment of value for PERID25 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID25_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID25_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID25_0                  (PAC_STATUS_PERID25_0_Val << PAC_STATUS_PERID25_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID25_1                  (PAC_STATUS_PERID25_1_Val << PAC_STATUS_PERID25_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID26_Pos                _UINT32_(26)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID26_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID26_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID26(value)             (PAC_STATUS_PERID26_Msk & (_UINT32_(value) << PAC_STATUS_PERID26_Pos)) /* Assignment of value for PERID26 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID26_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID26_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID26_0                  (PAC_STATUS_PERID26_0_Val << PAC_STATUS_PERID26_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID26_1                  (PAC_STATUS_PERID26_1_Val << PAC_STATUS_PERID26_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID27_Pos                _UINT32_(27)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID27_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID27_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID27(value)             (PAC_STATUS_PERID27_Msk & (_UINT32_(value) << PAC_STATUS_PERID27_Pos)) /* Assignment of value for PERID27 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID27_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID27_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID27_0                  (PAC_STATUS_PERID27_0_Val << PAC_STATUS_PERID27_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID27_1                  (PAC_STATUS_PERID27_1_Val << PAC_STATUS_PERID27_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID28_Pos                _UINT32_(28)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID28_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID28_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID28(value)             (PAC_STATUS_PERID28_Msk & (_UINT32_(value) << PAC_STATUS_PERID28_Pos)) /* Assignment of value for PERID28 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID28_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID28_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID28_0                  (PAC_STATUS_PERID28_0_Val << PAC_STATUS_PERID28_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID28_1                  (PAC_STATUS_PERID28_1_Val << PAC_STATUS_PERID28_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID29_Pos                _UINT32_(29)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID29_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID29_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID29(value)             (PAC_STATUS_PERID29_Msk & (_UINT32_(value) << PAC_STATUS_PERID29_Pos)) /* Assignment of value for PERID29 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID29_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID29_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID29_0                  (PAC_STATUS_PERID29_0_Val << PAC_STATUS_PERID29_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID29_1                  (PAC_STATUS_PERID29_1_Val << PAC_STATUS_PERID29_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID30_Pos                _UINT32_(30)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID30_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID30_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID30(value)             (PAC_STATUS_PERID30_Msk & (_UINT32_(value) << PAC_STATUS_PERID30_Pos)) /* Assignment of value for PERID30 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID30_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID30_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID30_0                  (PAC_STATUS_PERID30_0_Val << PAC_STATUS_PERID30_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID30_1                  (PAC_STATUS_PERID30_1_Val << PAC_STATUS_PERID30_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_PERID31_Pos                _UINT32_(31)                                         /* (PAC_STATUS) PERID Write Protection Status Position */
+#define PAC_STATUS_PERID31_Msk                (_UINT32_(0x1) << PAC_STATUS_PERID31_Pos)            /* (PAC_STATUS) PERID Write Protection Status Mask */
+#define PAC_STATUS_PERID31(value)             (PAC_STATUS_PERID31_Msk & (_UINT32_(value) << PAC_STATUS_PERID31_Pos)) /* Assignment of value for PERID31 in the PAC_STATUS register */
+#define   PAC_STATUS_PERID31_0_Val            _UINT32_(0x0)                                        /* (PAC_STATUS) Write Protection disabled  */
+#define   PAC_STATUS_PERID31_1_Val            _UINT32_(0x1)                                        /* (PAC_STATUS) Write Protection enabled  */
+#define PAC_STATUS_PERID31_0                  (PAC_STATUS_PERID31_0_Val << PAC_STATUS_PERID31_Pos) /* (PAC_STATUS) Write Protection disabled Position */
+#define PAC_STATUS_PERID31_1                  (PAC_STATUS_PERID31_1_Val << PAC_STATUS_PERID31_Pos) /* (PAC_STATUS) Write Protection enabled Position */
+#define PAC_STATUS_Msk                        _UINT32_(0xFFFFFFFF)                                 /* (PAC_STATUS) Register Mask  */
+
+#define PAC_STATUS_PERID_Pos                  _UINT32_(0)                                          /* (PAC_STATUS Position) PERID Write Protection Status */
+#define PAC_STATUS_PERID_Msk                  (_UINT32_(0xFFFFFFFF) << PAC_STATUS_PERID_Pos)       /* (PAC_STATUS Mask) PERID */
+#define PAC_STATUS_PERID(value)               (PAC_STATUS_PERID_Msk & (_UINT32_(value) << PAC_STATUS_PERID_Pos)) 
+
+/* -------- PAC_LOCK : (PAC Offset: 0x50) ( R/ 32) Peripheral Lock n Register -------- */
+#define PAC_LOCK_RESETVALUE                   _UINT32_(0x00)                                       /*  (PAC_LOCK) Peripheral Lock n Register  Reset Value */
+
+#define PAC_LOCK_PERID0_Pos                   _UINT32_(0)                                          /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID0_Msk                   (_UINT32_(0x1) << PAC_LOCK_PERID0_Pos)               /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID0(value)                (PAC_LOCK_PERID0_Msk & (_UINT32_(value) << PAC_LOCK_PERID0_Pos)) /* Assignment of value for PERID0 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID0_0_Val               _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID0_1_Val               _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID0_0                     (PAC_LOCK_PERID0_0_Val << PAC_LOCK_PERID0_Pos)       /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID0_1                     (PAC_LOCK_PERID0_1_Val << PAC_LOCK_PERID0_Pos)       /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID1_Pos                   _UINT32_(1)                                          /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID1_Msk                   (_UINT32_(0x1) << PAC_LOCK_PERID1_Pos)               /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID1(value)                (PAC_LOCK_PERID1_Msk & (_UINT32_(value) << PAC_LOCK_PERID1_Pos)) /* Assignment of value for PERID1 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID1_0_Val               _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID1_1_Val               _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID1_0                     (PAC_LOCK_PERID1_0_Val << PAC_LOCK_PERID1_Pos)       /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID1_1                     (PAC_LOCK_PERID1_1_Val << PAC_LOCK_PERID1_Pos)       /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID2_Pos                   _UINT32_(2)                                          /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID2_Msk                   (_UINT32_(0x1) << PAC_LOCK_PERID2_Pos)               /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID2(value)                (PAC_LOCK_PERID2_Msk & (_UINT32_(value) << PAC_LOCK_PERID2_Pos)) /* Assignment of value for PERID2 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID2_0_Val               _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID2_1_Val               _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID2_0                     (PAC_LOCK_PERID2_0_Val << PAC_LOCK_PERID2_Pos)       /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID2_1                     (PAC_LOCK_PERID2_1_Val << PAC_LOCK_PERID2_Pos)       /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID3_Pos                   _UINT32_(3)                                          /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID3_Msk                   (_UINT32_(0x1) << PAC_LOCK_PERID3_Pos)               /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID3(value)                (PAC_LOCK_PERID3_Msk & (_UINT32_(value) << PAC_LOCK_PERID3_Pos)) /* Assignment of value for PERID3 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID3_0_Val               _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID3_1_Val               _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID3_0                     (PAC_LOCK_PERID3_0_Val << PAC_LOCK_PERID3_Pos)       /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID3_1                     (PAC_LOCK_PERID3_1_Val << PAC_LOCK_PERID3_Pos)       /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID4_Pos                   _UINT32_(4)                                          /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID4_Msk                   (_UINT32_(0x1) << PAC_LOCK_PERID4_Pos)               /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID4(value)                (PAC_LOCK_PERID4_Msk & (_UINT32_(value) << PAC_LOCK_PERID4_Pos)) /* Assignment of value for PERID4 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID4_0_Val               _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID4_1_Val               _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID4_0                     (PAC_LOCK_PERID4_0_Val << PAC_LOCK_PERID4_Pos)       /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID4_1                     (PAC_LOCK_PERID4_1_Val << PAC_LOCK_PERID4_Pos)       /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID5_Pos                   _UINT32_(5)                                          /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID5_Msk                   (_UINT32_(0x1) << PAC_LOCK_PERID5_Pos)               /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID5(value)                (PAC_LOCK_PERID5_Msk & (_UINT32_(value) << PAC_LOCK_PERID5_Pos)) /* Assignment of value for PERID5 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID5_0_Val               _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID5_1_Val               _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID5_0                     (PAC_LOCK_PERID5_0_Val << PAC_LOCK_PERID5_Pos)       /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID5_1                     (PAC_LOCK_PERID5_1_Val << PAC_LOCK_PERID5_Pos)       /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID6_Pos                   _UINT32_(6)                                          /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID6_Msk                   (_UINT32_(0x1) << PAC_LOCK_PERID6_Pos)               /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID6(value)                (PAC_LOCK_PERID6_Msk & (_UINT32_(value) << PAC_LOCK_PERID6_Pos)) /* Assignment of value for PERID6 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID6_0_Val               _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID6_1_Val               _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID6_0                     (PAC_LOCK_PERID6_0_Val << PAC_LOCK_PERID6_Pos)       /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID6_1                     (PAC_LOCK_PERID6_1_Val << PAC_LOCK_PERID6_Pos)       /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID7_Pos                   _UINT32_(7)                                          /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID7_Msk                   (_UINT32_(0x1) << PAC_LOCK_PERID7_Pos)               /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID7(value)                (PAC_LOCK_PERID7_Msk & (_UINT32_(value) << PAC_LOCK_PERID7_Pos)) /* Assignment of value for PERID7 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID7_0_Val               _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID7_1_Val               _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID7_0                     (PAC_LOCK_PERID7_0_Val << PAC_LOCK_PERID7_Pos)       /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID7_1                     (PAC_LOCK_PERID7_1_Val << PAC_LOCK_PERID7_Pos)       /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID8_Pos                   _UINT32_(8)                                          /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID8_Msk                   (_UINT32_(0x1) << PAC_LOCK_PERID8_Pos)               /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID8(value)                (PAC_LOCK_PERID8_Msk & (_UINT32_(value) << PAC_LOCK_PERID8_Pos)) /* Assignment of value for PERID8 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID8_0_Val               _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID8_1_Val               _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID8_0                     (PAC_LOCK_PERID8_0_Val << PAC_LOCK_PERID8_Pos)       /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID8_1                     (PAC_LOCK_PERID8_1_Val << PAC_LOCK_PERID8_Pos)       /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID9_Pos                   _UINT32_(9)                                          /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID9_Msk                   (_UINT32_(0x1) << PAC_LOCK_PERID9_Pos)               /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID9(value)                (PAC_LOCK_PERID9_Msk & (_UINT32_(value) << PAC_LOCK_PERID9_Pos)) /* Assignment of value for PERID9 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID9_0_Val               _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID9_1_Val               _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID9_0                     (PAC_LOCK_PERID9_0_Val << PAC_LOCK_PERID9_Pos)       /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID9_1                     (PAC_LOCK_PERID9_1_Val << PAC_LOCK_PERID9_Pos)       /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID10_Pos                  _UINT32_(10)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID10_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID10_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID10(value)               (PAC_LOCK_PERID10_Msk & (_UINT32_(value) << PAC_LOCK_PERID10_Pos)) /* Assignment of value for PERID10 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID10_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID10_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID10_0                    (PAC_LOCK_PERID10_0_Val << PAC_LOCK_PERID10_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID10_1                    (PAC_LOCK_PERID10_1_Val << PAC_LOCK_PERID10_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID11_Pos                  _UINT32_(11)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID11_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID11_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID11(value)               (PAC_LOCK_PERID11_Msk & (_UINT32_(value) << PAC_LOCK_PERID11_Pos)) /* Assignment of value for PERID11 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID11_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID11_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID11_0                    (PAC_LOCK_PERID11_0_Val << PAC_LOCK_PERID11_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID11_1                    (PAC_LOCK_PERID11_1_Val << PAC_LOCK_PERID11_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID12_Pos                  _UINT32_(12)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID12_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID12_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID12(value)               (PAC_LOCK_PERID12_Msk & (_UINT32_(value) << PAC_LOCK_PERID12_Pos)) /* Assignment of value for PERID12 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID12_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID12_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID12_0                    (PAC_LOCK_PERID12_0_Val << PAC_LOCK_PERID12_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID12_1                    (PAC_LOCK_PERID12_1_Val << PAC_LOCK_PERID12_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID13_Pos                  _UINT32_(13)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID13_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID13_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID13(value)               (PAC_LOCK_PERID13_Msk & (_UINT32_(value) << PAC_LOCK_PERID13_Pos)) /* Assignment of value for PERID13 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID13_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID13_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID13_0                    (PAC_LOCK_PERID13_0_Val << PAC_LOCK_PERID13_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID13_1                    (PAC_LOCK_PERID13_1_Val << PAC_LOCK_PERID13_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID14_Pos                  _UINT32_(14)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID14_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID14_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID14(value)               (PAC_LOCK_PERID14_Msk & (_UINT32_(value) << PAC_LOCK_PERID14_Pos)) /* Assignment of value for PERID14 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID14_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID14_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID14_0                    (PAC_LOCK_PERID14_0_Val << PAC_LOCK_PERID14_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID14_1                    (PAC_LOCK_PERID14_1_Val << PAC_LOCK_PERID14_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID15_Pos                  _UINT32_(15)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID15_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID15_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID15(value)               (PAC_LOCK_PERID15_Msk & (_UINT32_(value) << PAC_LOCK_PERID15_Pos)) /* Assignment of value for PERID15 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID15_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID15_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID15_0                    (PAC_LOCK_PERID15_0_Val << PAC_LOCK_PERID15_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID15_1                    (PAC_LOCK_PERID15_1_Val << PAC_LOCK_PERID15_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID16_Pos                  _UINT32_(16)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID16_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID16_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID16(value)               (PAC_LOCK_PERID16_Msk & (_UINT32_(value) << PAC_LOCK_PERID16_Pos)) /* Assignment of value for PERID16 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID16_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID16_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID16_0                    (PAC_LOCK_PERID16_0_Val << PAC_LOCK_PERID16_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID16_1                    (PAC_LOCK_PERID16_1_Val << PAC_LOCK_PERID16_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID17_Pos                  _UINT32_(17)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID17_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID17_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID17(value)               (PAC_LOCK_PERID17_Msk & (_UINT32_(value) << PAC_LOCK_PERID17_Pos)) /* Assignment of value for PERID17 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID17_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID17_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID17_0                    (PAC_LOCK_PERID17_0_Val << PAC_LOCK_PERID17_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID17_1                    (PAC_LOCK_PERID17_1_Val << PAC_LOCK_PERID17_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID18_Pos                  _UINT32_(18)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID18_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID18_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID18(value)               (PAC_LOCK_PERID18_Msk & (_UINT32_(value) << PAC_LOCK_PERID18_Pos)) /* Assignment of value for PERID18 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID18_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID18_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID18_0                    (PAC_LOCK_PERID18_0_Val << PAC_LOCK_PERID18_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID18_1                    (PAC_LOCK_PERID18_1_Val << PAC_LOCK_PERID18_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID19_Pos                  _UINT32_(19)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID19_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID19_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID19(value)               (PAC_LOCK_PERID19_Msk & (_UINT32_(value) << PAC_LOCK_PERID19_Pos)) /* Assignment of value for PERID19 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID19_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID19_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID19_0                    (PAC_LOCK_PERID19_0_Val << PAC_LOCK_PERID19_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID19_1                    (PAC_LOCK_PERID19_1_Val << PAC_LOCK_PERID19_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID20_Pos                  _UINT32_(20)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID20_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID20_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID20(value)               (PAC_LOCK_PERID20_Msk & (_UINT32_(value) << PAC_LOCK_PERID20_Pos)) /* Assignment of value for PERID20 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID20_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID20_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID20_0                    (PAC_LOCK_PERID20_0_Val << PAC_LOCK_PERID20_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID20_1                    (PAC_LOCK_PERID20_1_Val << PAC_LOCK_PERID20_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID21_Pos                  _UINT32_(21)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID21_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID21_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID21(value)               (PAC_LOCK_PERID21_Msk & (_UINT32_(value) << PAC_LOCK_PERID21_Pos)) /* Assignment of value for PERID21 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID21_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID21_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID21_0                    (PAC_LOCK_PERID21_0_Val << PAC_LOCK_PERID21_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID21_1                    (PAC_LOCK_PERID21_1_Val << PAC_LOCK_PERID21_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID22_Pos                  _UINT32_(22)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID22_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID22_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID22(value)               (PAC_LOCK_PERID22_Msk & (_UINT32_(value) << PAC_LOCK_PERID22_Pos)) /* Assignment of value for PERID22 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID22_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID22_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID22_0                    (PAC_LOCK_PERID22_0_Val << PAC_LOCK_PERID22_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID22_1                    (PAC_LOCK_PERID22_1_Val << PAC_LOCK_PERID22_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID23_Pos                  _UINT32_(23)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID23_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID23_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID23(value)               (PAC_LOCK_PERID23_Msk & (_UINT32_(value) << PAC_LOCK_PERID23_Pos)) /* Assignment of value for PERID23 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID23_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID23_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID23_0                    (PAC_LOCK_PERID23_0_Val << PAC_LOCK_PERID23_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID23_1                    (PAC_LOCK_PERID23_1_Val << PAC_LOCK_PERID23_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID24_Pos                  _UINT32_(24)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID24_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID24_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID24(value)               (PAC_LOCK_PERID24_Msk & (_UINT32_(value) << PAC_LOCK_PERID24_Pos)) /* Assignment of value for PERID24 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID24_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID24_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID24_0                    (PAC_LOCK_PERID24_0_Val << PAC_LOCK_PERID24_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID24_1                    (PAC_LOCK_PERID24_1_Val << PAC_LOCK_PERID24_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID25_Pos                  _UINT32_(25)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID25_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID25_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID25(value)               (PAC_LOCK_PERID25_Msk & (_UINT32_(value) << PAC_LOCK_PERID25_Pos)) /* Assignment of value for PERID25 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID25_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID25_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID25_0                    (PAC_LOCK_PERID25_0_Val << PAC_LOCK_PERID25_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID25_1                    (PAC_LOCK_PERID25_1_Val << PAC_LOCK_PERID25_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID26_Pos                  _UINT32_(26)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID26_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID26_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID26(value)               (PAC_LOCK_PERID26_Msk & (_UINT32_(value) << PAC_LOCK_PERID26_Pos)) /* Assignment of value for PERID26 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID26_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID26_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID26_0                    (PAC_LOCK_PERID26_0_Val << PAC_LOCK_PERID26_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID26_1                    (PAC_LOCK_PERID26_1_Val << PAC_LOCK_PERID26_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID27_Pos                  _UINT32_(27)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID27_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID27_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID27(value)               (PAC_LOCK_PERID27_Msk & (_UINT32_(value) << PAC_LOCK_PERID27_Pos)) /* Assignment of value for PERID27 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID27_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID27_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID27_0                    (PAC_LOCK_PERID27_0_Val << PAC_LOCK_PERID27_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID27_1                    (PAC_LOCK_PERID27_1_Val << PAC_LOCK_PERID27_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID28_Pos                  _UINT32_(28)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID28_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID28_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID28(value)               (PAC_LOCK_PERID28_Msk & (_UINT32_(value) << PAC_LOCK_PERID28_Pos)) /* Assignment of value for PERID28 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID28_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID28_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID28_0                    (PAC_LOCK_PERID28_0_Val << PAC_LOCK_PERID28_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID28_1                    (PAC_LOCK_PERID28_1_Val << PAC_LOCK_PERID28_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID29_Pos                  _UINT32_(29)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID29_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID29_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID29(value)               (PAC_LOCK_PERID29_Msk & (_UINT32_(value) << PAC_LOCK_PERID29_Pos)) /* Assignment of value for PERID29 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID29_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID29_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID29_0                    (PAC_LOCK_PERID29_0_Val << PAC_LOCK_PERID29_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID29_1                    (PAC_LOCK_PERID29_1_Val << PAC_LOCK_PERID29_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID30_Pos                  _UINT32_(30)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID30_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID30_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID30(value)               (PAC_LOCK_PERID30_Msk & (_UINT32_(value) << PAC_LOCK_PERID30_Pos)) /* Assignment of value for PERID30 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID30_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID30_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID30_0                    (PAC_LOCK_PERID30_0_Val << PAC_LOCK_PERID30_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID30_1                    (PAC_LOCK_PERID30_1_Val << PAC_LOCK_PERID30_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_PERID31_Pos                  _UINT32_(31)                                         /* (PAC_LOCK) PERID Write Protection Lock Status Position */
+#define PAC_LOCK_PERID31_Msk                  (_UINT32_(0x1) << PAC_LOCK_PERID31_Pos)              /* (PAC_LOCK) PERID Write Protection Lock Status Mask */
+#define PAC_LOCK_PERID31(value)               (PAC_LOCK_PERID31_Msk & (_UINT32_(value) << PAC_LOCK_PERID31_Pos)) /* Assignment of value for PERID31 in the PAC_LOCK register */
+#define   PAC_LOCK_PERID31_0_Val              _UINT32_(0x0)                                        /* (PAC_LOCK) Write Protection Unlocked  */
+#define   PAC_LOCK_PERID31_1_Val              _UINT32_(0x1)                                        /* (PAC_LOCK) Write Protection Locked  */
+#define PAC_LOCK_PERID31_0                    (PAC_LOCK_PERID31_0_Val << PAC_LOCK_PERID31_Pos)     /* (PAC_LOCK) Write Protection Unlocked Position */
+#define PAC_LOCK_PERID31_1                    (PAC_LOCK_PERID31_1_Val << PAC_LOCK_PERID31_Pos)     /* (PAC_LOCK) Write Protection Locked Position */
+#define PAC_LOCK_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (PAC_LOCK) Register Mask  */
+
+#define PAC_LOCK_PERID_Pos                    _UINT32_(0)                                          /* (PAC_LOCK Position) PERID Write Protection Lock Status */
+#define PAC_LOCK_PERID_Msk                    (_UINT32_(0xFFFFFFFF) << PAC_LOCK_PERID_Pos)         /* (PAC_LOCK Mask) PERID */
+#define PAC_LOCK_PERID(value)                 (PAC_LOCK_PERID_Msk & (_UINT32_(value) << PAC_LOCK_PERID_Pos)) 
+
+/* PAC register offsets definitions */
+#define PAC_CTRLA_REG_OFST             _UINT32_(0x00)      /* (PAC_CTRLA) Control A Register Offset */
+#define PAC_WRCTRL_REG_OFST            _UINT32_(0x04)      /* (PAC_WRCTRL) Write Control Register Offset */
+#define PAC_STATUS_REG_OFST            _UINT32_(0x40)      /* (PAC_STATUS) Peripheral Status n Register Offset */
+#define PAC_STATUS0_REG_OFST           _UINT32_(0x40)      /* (PAC_STATUS0) Peripheral Status n Register Offset */
+#define PAC_STATUS1_REG_OFST           _UINT32_(0x44)      /* (PAC_STATUS1) Peripheral Status n Register Offset */
+#define PAC_STATUS2_REG_OFST           _UINT32_(0x48)      /* (PAC_STATUS2) Peripheral Status n Register Offset */
+#define PAC_STATUS3_REG_OFST           _UINT32_(0x4C)      /* (PAC_STATUS3) Peripheral Status n Register Offset */
+#define PAC_LOCK_REG_OFST              _UINT32_(0x50)      /* (PAC_LOCK) Peripheral Lock n Register Offset */
+#define PAC_LOCK0_REG_OFST             _UINT32_(0x50)      /* (PAC_LOCK0) Peripheral Lock n Register Offset */
+#define PAC_LOCK1_REG_OFST             _UINT32_(0x54)      /* (PAC_LOCK1) Peripheral Lock n Register Offset */
+#define PAC_LOCK2_REG_OFST             _UINT32_(0x58)      /* (PAC_LOCK2) Peripheral Lock n Register Offset */
+#define PAC_LOCK3_REG_OFST             _UINT32_(0x5C)      /* (PAC_LOCK3) Peripheral Lock n Register Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* PAC register API structure */
+typedef struct
+{  /* Peripheral Access Controller */
+  __IO  uint32_t                       PAC_CTRLA;          /* Offset: 0x00 (R/W  32) Control A Register */
+  __O   uint32_t                       PAC_WRCTRL;         /* Offset: 0x04 ( /W  32) Write Control Register */
+  __I   uint8_t                        Reserved1[0x38];
+  __I   uint32_t                       PAC_STATUS[4];      /* Offset: 0x40 (R/   32) Peripheral Status n Register */
+  __I   uint32_t                       PAC_LOCK[4];        /* Offset: 0x50 (R/   32) Peripheral Lock n Register */
+} pac_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_PAC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/pm.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/pm.h
new file mode 100644
index 00000000..e9921eba
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/pm.h
@@ -0,0 +1,147 @@
+/*
+ * Component description for PM
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_PM_COMPONENT_H_
+#define _PIC32CMGC00_PM_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                       SOFTWARE API DEFINITION FOR PM                       */
+/* ************************************************************************** */
+
+/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */
+#define PM_CTRLA_RESETVALUE                   _UINT8_(0x00)                                        /*  (PM_CTRLA) Control A  Reset Value */
+
+#define PM_CTRLA_IORET_Pos                    _UINT8_(2)                                           /* (PM_CTRLA) I/O Retention Position */
+#define PM_CTRLA_IORET_Msk                    (_UINT8_(0x1) << PM_CTRLA_IORET_Pos)                 /* (PM_CTRLA) I/O Retention Mask */
+#define PM_CTRLA_IORET(value)                 (PM_CTRLA_IORET_Msk & (_UINT8_(value) << PM_CTRLA_IORET_Pos)) /* Assignment of value for IORET in the PM_CTRLA register */
+#define   PM_CTRLA_IORET_NOIORET_Val          _UINT8_(0x0)                                         /* (PM_CTRLA) When  the  device  exits  the  HIBERNATE or BACKUP  mode,  the  I/O  line  configuration are released.  */
+#define   PM_CTRLA_IORET_IORET_Val            _UINT8_(0x1)                                         /* (PM_CTRLA) When  the  device  exits  the  HIBERNATE or BACKUP  mode,  the  I/O  line  configuration are stretched.  */
+#define PM_CTRLA_IORET_NOIORET                (PM_CTRLA_IORET_NOIORET_Val << PM_CTRLA_IORET_Pos)   /* (PM_CTRLA) When  the  device  exits  the  HIBERNATE or BACKUP  mode,  the  I/O  line  configuration are released. Position */
+#define PM_CTRLA_IORET_IORET                  (PM_CTRLA_IORET_IORET_Val << PM_CTRLA_IORET_Pos)     /* (PM_CTRLA) When  the  device  exits  the  HIBERNATE or BACKUP  mode,  the  I/O  line  configuration are stretched. Position */
+#define PM_CTRLA_Msk                          _UINT8_(0x04)                                        /* (PM_CTRLA) Register Mask  */
+
+
+/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
+#define PM_SLEEPCFG_RESETVALUE                _UINT8_(0x02)                                        /*  (PM_SLEEPCFG) Sleep Configuration  Reset Value */
+
+#define PM_SLEEPCFG_SLEEPMODE_Pos             _UINT8_(0)                                           /* (PM_SLEEPCFG) Sleep Mode Position */
+#define PM_SLEEPCFG_SLEEPMODE_Msk             (_UINT8_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)          /* (PM_SLEEPCFG) Sleep Mode Mask */
+#define PM_SLEEPCFG_SLEEPMODE(value)          (PM_SLEEPCFG_SLEEPMODE_Msk & (_UINT8_(value) << PM_SLEEPCFG_SLEEPMODE_Pos)) /* Assignment of value for SLEEPMODE in the PM_SLEEPCFG register */
+#define   PM_SLEEPCFG_SLEEPMODE_IDLE_Val      _UINT8_(0x2)                                         /* (PM_SLEEPCFG) CPU, AHB and APB clocks are OFF  */
+#define   PM_SLEEPCFG_SLEEPMODE_STANDBY_Val   _UINT8_(0x4)                                         /* (PM_SLEEPCFG) All Clocks are OFF  */
+#define   PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _UINT8_(0x5)                                         /* (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs  */
+#define   PM_SLEEPCFG_SLEEPMODE_BACKUP_Val    _UINT8_(0x6)                                         /* (PM_SLEEPCFG) Only Backup domain is powered ON  */
+#define   PM_SLEEPCFG_SLEEPMODE_OFF_Val       _UINT8_(0x7)                                         /* (PM_SLEEPCFG) All power domains are powered OFF  */
+#define PM_SLEEPCFG_SLEEPMODE_IDLE            (PM_SLEEPCFG_SLEEPMODE_IDLE_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) CPU, AHB and APB clocks are OFF Position */
+#define PM_SLEEPCFG_SLEEPMODE_STANDBY         (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) All Clocks are OFF Position */
+#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE       (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs Position */
+#define PM_SLEEPCFG_SLEEPMODE_BACKUP          (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) Only Backup domain is powered ON Position */
+#define PM_SLEEPCFG_SLEEPMODE_OFF             (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /* (PM_SLEEPCFG) All power domains are powered OFF Position */
+#define PM_SLEEPCFG_Msk                       _UINT8_(0x07)                                        /* (PM_SLEEPCFG) Register Mask  */
+
+
+/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#define PM_INTENCLR_RESETVALUE                _UINT8_(0x00)                                        /*  (PM_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define PM_INTENCLR_SLEEPRDY_Pos              _UINT8_(0)                                           /* (PM_INTENCLR) Backup Sleep Mode Entry Ready Enable Position */
+#define PM_INTENCLR_SLEEPRDY_Msk              (_UINT8_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)           /* (PM_INTENCLR) Backup Sleep Mode Entry Ready Enable Mask */
+#define PM_INTENCLR_SLEEPRDY(value)           (PM_INTENCLR_SLEEPRDY_Msk & (_UINT8_(value) << PM_INTENCLR_SLEEPRDY_Pos)) /* Assignment of value for SLEEPRDY in the PM_INTENCLR register */
+#define PM_INTENCLR_Msk                       _UINT8_(0x01)                                        /* (PM_INTENCLR) Register Mask  */
+
+
+/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#define PM_INTENSET_RESETVALUE                _UINT8_(0x00)                                        /*  (PM_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define PM_INTENSET_SLEEPRDY_Pos              _UINT8_(0)                                           /* (PM_INTENSET) Backup Sleep Mode Entry Ready Enable Position */
+#define PM_INTENSET_SLEEPRDY_Msk              (_UINT8_(0x1) << PM_INTENSET_SLEEPRDY_Pos)           /* (PM_INTENSET) Backup Sleep Mode Entry Ready Enable Mask */
+#define PM_INTENSET_SLEEPRDY(value)           (PM_INTENSET_SLEEPRDY_Msk & (_UINT8_(value) << PM_INTENSET_SLEEPRDY_Pos)) /* Assignment of value for SLEEPRDY in the PM_INTENSET register */
+#define PM_INTENSET_Msk                       _UINT8_(0x01)                                        /* (PM_INTENSET) Register Mask  */
+
+
+/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#define PM_INTFLAG_RESETVALUE                 _UINT8_(0x00)                                        /*  (PM_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define PM_INTFLAG_SLEEPRDY_Pos               _UINT8_(0)                                           /* (PM_INTFLAG) Backup Sleep Mode Entry Ready Position */
+#define PM_INTFLAG_SLEEPRDY_Msk               (_UINT8_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)            /* (PM_INTFLAG) Backup Sleep Mode Entry Ready Mask */
+#define PM_INTFLAG_SLEEPRDY(value)            (PM_INTFLAG_SLEEPRDY_Msk & (_UINT8_(value) << PM_INTFLAG_SLEEPRDY_Pos)) /* Assignment of value for SLEEPRDY in the PM_INTFLAG register */
+#define PM_INTFLAG_Msk                        _UINT8_(0x01)                                        /* (PM_INTFLAG) Register Mask  */
+
+
+/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */
+#define PM_STDBYCFG_RESETVALUE                _UINT8_(0x04)                                        /*  (PM_STDBYCFG) Standby Configuration  Reset Value */
+
+#define PM_STDBYCFG_RAMCFG_Pos                _UINT8_(0)                                           /* (PM_STDBYCFG) Ram Configuration Position */
+#define PM_STDBYCFG_RAMCFG_Msk                (_UINT8_(0x1) << PM_STDBYCFG_RAMCFG_Pos)             /* (PM_STDBYCFG) Ram Configuration Mask */
+#define PM_STDBYCFG_RAMCFG(value)             (PM_STDBYCFG_RAMCFG_Msk & (_UINT8_(value) << PM_STDBYCFG_RAMCFG_Pos)) /* Assignment of value for RAMCFG in the PM_STDBYCFG register */
+#define   PM_STDBYCFG_RAMCFG_RET_Val          _UINT8_(0x0)                                         /* (PM_STDBYCFG) All the RAMs are retained  */
+#define   PM_STDBYCFG_RAMCFG_OFF_Val          _UINT8_(0x1)                                         /* (PM_STDBYCFG) Only the first 32K bytes are retained  */
+#define PM_STDBYCFG_RAMCFG_RET                (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos) /* (PM_STDBYCFG) All the RAMs are retained Position */
+#define PM_STDBYCFG_RAMCFG_OFF                (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos) /* (PM_STDBYCFG) Only the first 32K bytes are retained Position */
+#define PM_STDBYCFG_LPRAM_Pos                 _UINT8_(2)                                           /* (PM_STDBYCFG) Low Power RAM Enable Position */
+#define PM_STDBYCFG_LPRAM_Msk                 (_UINT8_(0x1) << PM_STDBYCFG_LPRAM_Pos)              /* (PM_STDBYCFG) Low Power RAM Enable Mask */
+#define PM_STDBYCFG_LPRAM(value)              (PM_STDBYCFG_LPRAM_Msk & (_UINT8_(value) << PM_STDBYCFG_LPRAM_Pos)) /* Assignment of value for LPRAM in the PM_STDBYCFG register */
+#define PM_STDBYCFG_Msk                       _UINT8_(0x05)                                        /* (PM_STDBYCFG) Register Mask  */
+
+
+/* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */
+#define PM_HIBCFG_RESETVALUE                  _UINT8_(0x04)                                        /*  (PM_HIBCFG) Hibernate Configuration  Reset Value */
+
+#define PM_HIBCFG_RAMCFG_Pos                  _UINT8_(0)                                           /* (PM_HIBCFG) Ram Configuration Position */
+#define PM_HIBCFG_RAMCFG_Msk                  (_UINT8_(0x1) << PM_HIBCFG_RAMCFG_Pos)               /* (PM_HIBCFG) Ram Configuration Mask */
+#define PM_HIBCFG_RAMCFG(value)               (PM_HIBCFG_RAMCFG_Msk & (_UINT8_(value) << PM_HIBCFG_RAMCFG_Pos)) /* Assignment of value for RAMCFG in the PM_HIBCFG register */
+#define   PM_HIBCFG_RAMCFG_RET_Val            _UINT8_(0x0)                                         /* (PM_HIBCFG) All the RAMs are retained  */
+#define   PM_HIBCFG_RAMCFG_OFF_Val            _UINT8_(0x1)                                         /* (PM_HIBCFG) Only the first 32K bytes are retained  */
+#define PM_HIBCFG_RAMCFG_RET                  (PM_HIBCFG_RAMCFG_RET_Val << PM_HIBCFG_RAMCFG_Pos)   /* (PM_HIBCFG) All the RAMs are retained Position */
+#define PM_HIBCFG_RAMCFG_OFF                  (PM_HIBCFG_RAMCFG_OFF_Val << PM_HIBCFG_RAMCFG_Pos)   /* (PM_HIBCFG) Only the first 32K bytes are retained Position */
+#define PM_HIBCFG_LPRAM_Pos                   _UINT8_(2)                                           /* (PM_HIBCFG) Low Power RAM Enable Position */
+#define PM_HIBCFG_LPRAM_Msk                   (_UINT8_(0x1) << PM_HIBCFG_LPRAM_Pos)                /* (PM_HIBCFG) Low Power RAM Enable Mask */
+#define PM_HIBCFG_LPRAM(value)                (PM_HIBCFG_LPRAM_Msk & (_UINT8_(value) << PM_HIBCFG_LPRAM_Pos)) /* Assignment of value for LPRAM in the PM_HIBCFG register */
+#define PM_HIBCFG_Msk                         _UINT8_(0x05)                                        /* (PM_HIBCFG) Register Mask  */
+
+
+/* PM register offsets definitions */
+#define PM_CTRLA_REG_OFST              _UINT32_(0x00)      /* (PM_CTRLA) Control A Offset */
+#define PM_SLEEPCFG_REG_OFST           _UINT32_(0x01)      /* (PM_SLEEPCFG) Sleep Configuration Offset */
+#define PM_INTENCLR_REG_OFST           _UINT32_(0x04)      /* (PM_INTENCLR) Interrupt Enable Clear Offset */
+#define PM_INTENSET_REG_OFST           _UINT32_(0x05)      /* (PM_INTENSET) Interrupt Enable Set Offset */
+#define PM_INTFLAG_REG_OFST            _UINT32_(0x06)      /* (PM_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define PM_STDBYCFG_REG_OFST           _UINT32_(0x08)      /* (PM_STDBYCFG) Standby Configuration Offset */
+#define PM_HIBCFG_REG_OFST             _UINT32_(0x09)      /* (PM_HIBCFG) Hibernate Configuration Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* PM register API structure */
+typedef struct
+{  /* Power Manager */
+  __IO  uint8_t                        PM_CTRLA;           /* Offset: 0x00 (R/W  8) Control A */
+  __IO  uint8_t                        PM_SLEEPCFG;        /* Offset: 0x01 (R/W  8) Sleep Configuration */
+  __I   uint8_t                        Reserved1[0x02];
+  __IO  uint8_t                        PM_INTENCLR;        /* Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO  uint8_t                        PM_INTENSET;        /* Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO  uint8_t                        PM_INTFLAG;         /* Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        PM_STDBYCFG;        /* Offset: 0x08 (R/W  8) Standby Configuration */
+  __IO  uint8_t                        PM_HIBCFG;          /* Offset: 0x09 (R/W  8) Hibernate Configuration */
+} pm_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_PM_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/port.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/port.h
new file mode 100644
index 00000000..2694b9dc
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/port.h
@@ -0,0 +1,429 @@
+/*
+ * Component description for PORT
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_PORT_COMPONENT_H_
+#define _PIC32CMGC00_PORT_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR PORT                      */
+/* ************************************************************************** */
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) Data Direction -------- */
+#define PORT_DIR_RESETVALUE                   _UINT32_(0x00)                                       /*  (PORT_DIR) Data Direction  Reset Value */
+
+#define PORT_DIR_DIR_Pos                      _UINT32_(0)                                          /* (PORT_DIR) Port Data Direction Position */
+#define PORT_DIR_DIR_Msk                      (_UINT32_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)           /* (PORT_DIR) Port Data Direction Mask */
+#define PORT_DIR_DIR(value)                   (PORT_DIR_DIR_Msk & (_UINT32_(value) << PORT_DIR_DIR_Pos)) /* Assignment of value for DIR in the PORT_DIR register */
+#define PORT_DIR_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (PORT_DIR) Register Mask  */
+
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) Data Direction Clear -------- */
+#define PORT_DIRCLR_RESETVALUE                _UINT32_(0x00)                                       /*  (PORT_DIRCLR) Data Direction Clear  Reset Value */
+
+#define PORT_DIRCLR_DIRCLR_Pos                _UINT32_(0)                                          /* (PORT_DIRCLR) Port Data Direction Clear Position */
+#define PORT_DIRCLR_DIRCLR_Msk                (_UINT32_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)     /* (PORT_DIRCLR) Port Data Direction Clear Mask */
+#define PORT_DIRCLR_DIRCLR(value)             (PORT_DIRCLR_DIRCLR_Msk & (_UINT32_(value) << PORT_DIRCLR_DIRCLR_Pos)) /* Assignment of value for DIRCLR in the PORT_DIRCLR register */
+#define PORT_DIRCLR_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (PORT_DIRCLR) Register Mask  */
+
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) Data Direction Set -------- */
+#define PORT_DIRSET_RESETVALUE                _UINT32_(0x00)                                       /*  (PORT_DIRSET) Data Direction Set  Reset Value */
+
+#define PORT_DIRSET_DIRSET_Pos                _UINT32_(0)                                          /* (PORT_DIRSET) Port Data Direction Set Position */
+#define PORT_DIRSET_DIRSET_Msk                (_UINT32_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)     /* (PORT_DIRSET) Port Data Direction Set Mask */
+#define PORT_DIRSET_DIRSET(value)             (PORT_DIRSET_DIRSET_Msk & (_UINT32_(value) << PORT_DIRSET_DIRSET_Pos)) /* Assignment of value for DIRSET in the PORT_DIRSET register */
+#define PORT_DIRSET_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (PORT_DIRSET) Register Mask  */
+
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) Data Direction Toggle -------- */
+#define PORT_DIRTGL_RESETVALUE                _UINT32_(0x00)                                       /*  (PORT_DIRTGL) Data Direction Toggle  Reset Value */
+
+#define PORT_DIRTGL_DIRTGL_Pos                _UINT32_(0)                                          /* (PORT_DIRTGL) Port Data Direction Toggle Position */
+#define PORT_DIRTGL_DIRTGL_Msk                (_UINT32_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)     /* (PORT_DIRTGL) Port Data Direction Toggle Mask */
+#define PORT_DIRTGL_DIRTGL(value)             (PORT_DIRTGL_DIRTGL_Msk & (_UINT32_(value) << PORT_DIRTGL_DIRTGL_Pos)) /* Assignment of value for DIRTGL in the PORT_DIRTGL register */
+#define PORT_DIRTGL_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (PORT_DIRTGL) Register Mask  */
+
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) Data Output Value -------- */
+#define PORT_OUT_RESETVALUE                   _UINT32_(0x00)                                       /*  (PORT_OUT) Data Output Value  Reset Value */
+
+#define PORT_OUT_OUT_Pos                      _UINT32_(0)                                          /* (PORT_OUT) PORT Data Output Value Position */
+#define PORT_OUT_OUT_Msk                      (_UINT32_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)           /* (PORT_OUT) PORT Data Output Value Mask */
+#define PORT_OUT_OUT(value)                   (PORT_OUT_OUT_Msk & (_UINT32_(value) << PORT_OUT_OUT_Pos)) /* Assignment of value for OUT in the PORT_OUT register */
+#define PORT_OUT_Msk                          _UINT32_(0xFFFFFFFF)                                 /* (PORT_OUT) Register Mask  */
+
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) Data Output Value Clear -------- */
+#define PORT_OUTCLR_RESETVALUE                _UINT32_(0x00)                                       /*  (PORT_OUTCLR) Data Output Value Clear  Reset Value */
+
+#define PORT_OUTCLR_OUTCLR_Pos                _UINT32_(0)                                          /* (PORT_OUTCLR) PORT Data Output Value Clear Position */
+#define PORT_OUTCLR_OUTCLR_Msk                (_UINT32_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)     /* (PORT_OUTCLR) PORT Data Output Value Clear Mask */
+#define PORT_OUTCLR_OUTCLR(value)             (PORT_OUTCLR_OUTCLR_Msk & (_UINT32_(value) << PORT_OUTCLR_OUTCLR_Pos)) /* Assignment of value for OUTCLR in the PORT_OUTCLR register */
+#define PORT_OUTCLR_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (PORT_OUTCLR) Register Mask  */
+
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) Data Output Value Set -------- */
+#define PORT_OUTSET_RESETVALUE                _UINT32_(0x00)                                       /*  (PORT_OUTSET) Data Output Value Set  Reset Value */
+
+#define PORT_OUTSET_OUTSET_Pos                _UINT32_(0)                                          /* (PORT_OUTSET) PORT Data Output Value Set Position */
+#define PORT_OUTSET_OUTSET_Msk                (_UINT32_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)     /* (PORT_OUTSET) PORT Data Output Value Set Mask */
+#define PORT_OUTSET_OUTSET(value)             (PORT_OUTSET_OUTSET_Msk & (_UINT32_(value) << PORT_OUTSET_OUTSET_Pos)) /* Assignment of value for OUTSET in the PORT_OUTSET register */
+#define PORT_OUTSET_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (PORT_OUTSET) Register Mask  */
+
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) Data Output Value Toggle -------- */
+#define PORT_OUTTGL_RESETVALUE                _UINT32_(0x00)                                       /*  (PORT_OUTTGL) Data Output Value Toggle  Reset Value */
+
+#define PORT_OUTTGL_OUTTGL_Pos                _UINT32_(0)                                          /* (PORT_OUTTGL) PORT Data Output Value Toggle Position */
+#define PORT_OUTTGL_OUTTGL_Msk                (_UINT32_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)     /* (PORT_OUTTGL) PORT Data Output Value Toggle Mask */
+#define PORT_OUTTGL_OUTTGL(value)             (PORT_OUTTGL_OUTTGL_Msk & (_UINT32_(value) << PORT_OUTTGL_OUTTGL_Pos)) /* Assignment of value for OUTTGL in the PORT_OUTTGL register */
+#define PORT_OUTTGL_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (PORT_OUTTGL) Register Mask  */
+
+
+/* -------- PORT_IN : (PORT Offset: 0x20) ( R/ 32) Data Input Value -------- */
+#define PORT_IN_RESETVALUE                    _UINT32_(0x00)                                       /*  (PORT_IN) Data Input Value  Reset Value */
+
+#define PORT_IN_IN_Pos                        _UINT32_(0)                                          /* (PORT_IN) PORT Data Input Value Position */
+#define PORT_IN_IN_Msk                        (_UINT32_(0xFFFFFFFF) << PORT_IN_IN_Pos)             /* (PORT_IN) PORT Data Input Value Mask */
+#define PORT_IN_IN(value)                     (PORT_IN_IN_Msk & (_UINT32_(value) << PORT_IN_IN_Pos)) /* Assignment of value for IN in the PORT_IN register */
+#define PORT_IN_Msk                           _UINT32_(0xFFFFFFFF)                                 /* (PORT_IN) Register Mask  */
+
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) Control -------- */
+#define PORT_CTRL_RESETVALUE                  _UINT32_(0x00)                                       /*  (PORT_CTRL) Control  Reset Value */
+
+#define PORT_CTRL_SAMPLING_Pos                _UINT32_(0)                                          /* (PORT_CTRL) Input Sampling Mode Position */
+#define PORT_CTRL_SAMPLING_Msk                (_UINT32_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)     /* (PORT_CTRL) Input Sampling Mode Mask */
+#define PORT_CTRL_SAMPLING(value)             (PORT_CTRL_SAMPLING_Msk & (_UINT32_(value) << PORT_CTRL_SAMPLING_Pos)) /* Assignment of value for SAMPLING in the PORT_CTRL register */
+#define PORT_CTRL_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (PORT_CTRL) Register Mask  */
+
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) Write Configuration -------- */
+#define PORT_WRCONFIG_RESETVALUE              _UINT32_(0x00)                                       /*  (PORT_WRCONFIG) Write Configuration  Reset Value */
+
+#define PORT_WRCONFIG_PINMASK_Pos             _UINT32_(0)                                          /* (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Position */
+#define PORT_WRCONFIG_PINMASK_Msk             (_UINT32_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)      /* (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Mask */
+#define PORT_WRCONFIG_PINMASK(value)          (PORT_WRCONFIG_PINMASK_Msk & (_UINT32_(value) << PORT_WRCONFIG_PINMASK_Pos)) /* Assignment of value for PINMASK in the PORT_WRCONFIG register */
+#define PORT_WRCONFIG_PMUXEN_Pos              _UINT32_(16)                                         /* (PORT_WRCONFIG) Peripheral Multiplexer Enable Position */
+#define PORT_WRCONFIG_PMUXEN_Msk              (_UINT32_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)          /* (PORT_WRCONFIG) Peripheral Multiplexer Enable Mask */
+#define PORT_WRCONFIG_PMUXEN(value)           (PORT_WRCONFIG_PMUXEN_Msk & (_UINT32_(value) << PORT_WRCONFIG_PMUXEN_Pos)) /* Assignment of value for PMUXEN in the PORT_WRCONFIG register */
+#define PORT_WRCONFIG_INEN_Pos                _UINT32_(17)                                         /* (PORT_WRCONFIG) Input Enable Position */
+#define PORT_WRCONFIG_INEN_Msk                (_UINT32_(0x1) << PORT_WRCONFIG_INEN_Pos)            /* (PORT_WRCONFIG) Input Enable Mask */
+#define PORT_WRCONFIG_INEN(value)             (PORT_WRCONFIG_INEN_Msk & (_UINT32_(value) << PORT_WRCONFIG_INEN_Pos)) /* Assignment of value for INEN in the PORT_WRCONFIG register */
+#define PORT_WRCONFIG_PULLEN_Pos              _UINT32_(18)                                         /* (PORT_WRCONFIG) Pull Enable Position */
+#define PORT_WRCONFIG_PULLEN_Msk              (_UINT32_(0x1) << PORT_WRCONFIG_PULLEN_Pos)          /* (PORT_WRCONFIG) Pull Enable Mask */
+#define PORT_WRCONFIG_PULLEN(value)           (PORT_WRCONFIG_PULLEN_Msk & (_UINT32_(value) << PORT_WRCONFIG_PULLEN_Pos)) /* Assignment of value for PULLEN in the PORT_WRCONFIG register */
+#define PORT_WRCONFIG_ODRAIN_Pos              _UINT32_(19)                                         /* (PORT_WRCONFIG) Open Drain Output Position */
+#define PORT_WRCONFIG_ODRAIN_Msk              (_UINT32_(0x1) << PORT_WRCONFIG_ODRAIN_Pos)          /* (PORT_WRCONFIG) Open Drain Output Mask */
+#define PORT_WRCONFIG_ODRAIN(value)           (PORT_WRCONFIG_ODRAIN_Msk & (_UINT32_(value) << PORT_WRCONFIG_ODRAIN_Pos)) /* Assignment of value for ODRAIN in the PORT_WRCONFIG register */
+#define PORT_WRCONFIG_SLEWLIM_Pos             _UINT32_(20)                                         /* (PORT_WRCONFIG) Output Driver Slew Rate Selection Position */
+#define PORT_WRCONFIG_SLEWLIM_Msk             (_UINT32_(0x3) << PORT_WRCONFIG_SLEWLIM_Pos)         /* (PORT_WRCONFIG) Output Driver Slew Rate Selection Mask */
+#define PORT_WRCONFIG_SLEWLIM(value)          (PORT_WRCONFIG_SLEWLIM_Msk & (_UINT32_(value) << PORT_WRCONFIG_SLEWLIM_Pos)) /* Assignment of value for SLEWLIM in the PORT_WRCONFIG register */
+#define PORT_WRCONFIG_PMUX_Pos                _UINT32_(24)                                         /* (PORT_WRCONFIG) Peripheral Multiplexing Position */
+#define PORT_WRCONFIG_PMUX_Msk                (_UINT32_(0xF) << PORT_WRCONFIG_PMUX_Pos)            /* (PORT_WRCONFIG) Peripheral Multiplexing Mask */
+#define PORT_WRCONFIG_PMUX(value)             (PORT_WRCONFIG_PMUX_Msk & (_UINT32_(value) << PORT_WRCONFIG_PMUX_Pos)) /* Assignment of value for PMUX in the PORT_WRCONFIG register */
+#define PORT_WRCONFIG_WRPMUX_Pos              _UINT32_(28)                                         /* (PORT_WRCONFIG) Write PMUX Position */
+#define PORT_WRCONFIG_WRPMUX_Msk              (_UINT32_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)          /* (PORT_WRCONFIG) Write PMUX Mask */
+#define PORT_WRCONFIG_WRPMUX(value)           (PORT_WRCONFIG_WRPMUX_Msk & (_UINT32_(value) << PORT_WRCONFIG_WRPMUX_Pos)) /* Assignment of value for WRPMUX in the PORT_WRCONFIG register */
+#define PORT_WRCONFIG_WRPINCFG_Pos            _UINT32_(30)                                         /* (PORT_WRCONFIG) Write PINCFG Position */
+#define PORT_WRCONFIG_WRPINCFG_Msk            (_UINT32_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)        /* (PORT_WRCONFIG) Write PINCFG Mask */
+#define PORT_WRCONFIG_WRPINCFG(value)         (PORT_WRCONFIG_WRPINCFG_Msk & (_UINT32_(value) << PORT_WRCONFIG_WRPINCFG_Pos)) /* Assignment of value for WRPINCFG in the PORT_WRCONFIG register */
+#define PORT_WRCONFIG_HWSEL_Pos               _UINT32_(31)                                         /* (PORT_WRCONFIG) Half-Word Select Position */
+#define PORT_WRCONFIG_HWSEL_Msk               (_UINT32_(0x1) << PORT_WRCONFIG_HWSEL_Pos)           /* (PORT_WRCONFIG) Half-Word Select Mask */
+#define PORT_WRCONFIG_HWSEL(value)            (PORT_WRCONFIG_HWSEL_Msk & (_UINT32_(value) << PORT_WRCONFIG_HWSEL_Pos)) /* Assignment of value for HWSEL in the PORT_WRCONFIG register */
+#define PORT_WRCONFIG_Msk                     _UINT32_(0xDF3FFFFF)                                 /* (PORT_WRCONFIG) Register Mask  */
+
+
+/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) Event Input Control -------- */
+#define PORT_EVCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (PORT_EVCTRL) Event Input Control  Reset Value */
+
+#define PORT_EVCTRL_PID0_Pos                  _UINT32_(0)                                          /* (PORT_EVCTRL) PORT Event Pin Identifier 0 Position */
+#define PORT_EVCTRL_PID0_Msk                  (_UINT32_(0x1F) << PORT_EVCTRL_PID0_Pos)             /* (PORT_EVCTRL) PORT Event Pin Identifier 0 Mask */
+#define PORT_EVCTRL_PID0(value)               (PORT_EVCTRL_PID0_Msk & (_UINT32_(value) << PORT_EVCTRL_PID0_Pos)) /* Assignment of value for PID0 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_EVACT0_Pos                _UINT32_(5)                                          /* (PORT_EVCTRL) PORT Event Action 0 Position */
+#define PORT_EVCTRL_EVACT0_Msk                (_UINT32_(0x3) << PORT_EVCTRL_EVACT0_Pos)            /* (PORT_EVCTRL) PORT Event Action 0 Mask */
+#define PORT_EVCTRL_EVACT0(value)             (PORT_EVCTRL_EVACT0_Msk & (_UINT32_(value) << PORT_EVCTRL_EVACT0_Pos)) /* Assignment of value for EVACT0 in the PORT_EVCTRL register */
+#define   PORT_EVCTRL_EVACT0_OUT_Val          _UINT32_(0x0)                                        /* (PORT_EVCTRL) Event output to pin  */
+#define   PORT_EVCTRL_EVACT0_SET_Val          _UINT32_(0x1)                                        /* (PORT_EVCTRL) Set output register of pin on event  */
+#define   PORT_EVCTRL_EVACT0_CLR_Val          _UINT32_(0x2)                                        /* (PORT_EVCTRL) Clear output register of pin on event  */
+#define   PORT_EVCTRL_EVACT0_TGL_Val          _UINT32_(0x3)                                        /* (PORT_EVCTRL) Toggle output register of pin on event  */
+#define PORT_EVCTRL_EVACT0_OUT                (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos) /* (PORT_EVCTRL) Event output to pin Position */
+#define PORT_EVCTRL_EVACT0_SET                (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos) /* (PORT_EVCTRL) Set output register of pin on event Position */
+#define PORT_EVCTRL_EVACT0_CLR                (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos) /* (PORT_EVCTRL) Clear output register of pin on event Position */
+#define PORT_EVCTRL_EVACT0_TGL                (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos) /* (PORT_EVCTRL) Toggle output register of pin on event Position */
+#define PORT_EVCTRL_PORTEI0_Pos               _UINT32_(7)                                          /* (PORT_EVCTRL) PORT Event Input Enable 0 Position */
+#define PORT_EVCTRL_PORTEI0_Msk               (_UINT32_(0x1) << PORT_EVCTRL_PORTEI0_Pos)           /* (PORT_EVCTRL) PORT Event Input Enable 0 Mask */
+#define PORT_EVCTRL_PORTEI0(value)            (PORT_EVCTRL_PORTEI0_Msk & (_UINT32_(value) << PORT_EVCTRL_PORTEI0_Pos)) /* Assignment of value for PORTEI0 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_PID1_Pos                  _UINT32_(8)                                          /* (PORT_EVCTRL) PORT Event Pin Identifier 1 Position */
+#define PORT_EVCTRL_PID1_Msk                  (_UINT32_(0x1F) << PORT_EVCTRL_PID1_Pos)             /* (PORT_EVCTRL) PORT Event Pin Identifier 1 Mask */
+#define PORT_EVCTRL_PID1(value)               (PORT_EVCTRL_PID1_Msk & (_UINT32_(value) << PORT_EVCTRL_PID1_Pos)) /* Assignment of value for PID1 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_EVACT1_Pos                _UINT32_(13)                                         /* (PORT_EVCTRL) PORT Event Action 1 Position */
+#define PORT_EVCTRL_EVACT1_Msk                (_UINT32_(0x3) << PORT_EVCTRL_EVACT1_Pos)            /* (PORT_EVCTRL) PORT Event Action 1 Mask */
+#define PORT_EVCTRL_EVACT1(value)             (PORT_EVCTRL_EVACT1_Msk & (_UINT32_(value) << PORT_EVCTRL_EVACT1_Pos)) /* Assignment of value for EVACT1 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_PORTEI1_Pos               _UINT32_(15)                                         /* (PORT_EVCTRL) PORT Event Input Enable 1 Position */
+#define PORT_EVCTRL_PORTEI1_Msk               (_UINT32_(0x1) << PORT_EVCTRL_PORTEI1_Pos)           /* (PORT_EVCTRL) PORT Event Input Enable 1 Mask */
+#define PORT_EVCTRL_PORTEI1(value)            (PORT_EVCTRL_PORTEI1_Msk & (_UINT32_(value) << PORT_EVCTRL_PORTEI1_Pos)) /* Assignment of value for PORTEI1 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_PID2_Pos                  _UINT32_(16)                                         /* (PORT_EVCTRL) PORT Event Pin Identifier 2 Position */
+#define PORT_EVCTRL_PID2_Msk                  (_UINT32_(0x1F) << PORT_EVCTRL_PID2_Pos)             /* (PORT_EVCTRL) PORT Event Pin Identifier 2 Mask */
+#define PORT_EVCTRL_PID2(value)               (PORT_EVCTRL_PID2_Msk & (_UINT32_(value) << PORT_EVCTRL_PID2_Pos)) /* Assignment of value for PID2 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_EVACT2_Pos                _UINT32_(21)                                         /* (PORT_EVCTRL) PORT Event Action 2 Position */
+#define PORT_EVCTRL_EVACT2_Msk                (_UINT32_(0x3) << PORT_EVCTRL_EVACT2_Pos)            /* (PORT_EVCTRL) PORT Event Action 2 Mask */
+#define PORT_EVCTRL_EVACT2(value)             (PORT_EVCTRL_EVACT2_Msk & (_UINT32_(value) << PORT_EVCTRL_EVACT2_Pos)) /* Assignment of value for EVACT2 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_PORTEI2_Pos               _UINT32_(23)                                         /* (PORT_EVCTRL) PORT Event Input Enable 2 Position */
+#define PORT_EVCTRL_PORTEI2_Msk               (_UINT32_(0x1) << PORT_EVCTRL_PORTEI2_Pos)           /* (PORT_EVCTRL) PORT Event Input Enable 2 Mask */
+#define PORT_EVCTRL_PORTEI2(value)            (PORT_EVCTRL_PORTEI2_Msk & (_UINT32_(value) << PORT_EVCTRL_PORTEI2_Pos)) /* Assignment of value for PORTEI2 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_PID3_Pos                  _UINT32_(24)                                         /* (PORT_EVCTRL) PORT Event Pin Identifier 3 Position */
+#define PORT_EVCTRL_PID3_Msk                  (_UINT32_(0x1F) << PORT_EVCTRL_PID3_Pos)             /* (PORT_EVCTRL) PORT Event Pin Identifier 3 Mask */
+#define PORT_EVCTRL_PID3(value)               (PORT_EVCTRL_PID3_Msk & (_UINT32_(value) << PORT_EVCTRL_PID3_Pos)) /* Assignment of value for PID3 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_EVACT3_Pos                _UINT32_(29)                                         /* (PORT_EVCTRL) PORT Event Action 3 Position */
+#define PORT_EVCTRL_EVACT3_Msk                (_UINT32_(0x3) << PORT_EVCTRL_EVACT3_Pos)            /* (PORT_EVCTRL) PORT Event Action 3 Mask */
+#define PORT_EVCTRL_EVACT3(value)             (PORT_EVCTRL_EVACT3_Msk & (_UINT32_(value) << PORT_EVCTRL_EVACT3_Pos)) /* Assignment of value for EVACT3 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_PORTEI3_Pos               _UINT32_(31)                                         /* (PORT_EVCTRL) PORT Event Input Enable 3 Position */
+#define PORT_EVCTRL_PORTEI3_Msk               (_UINT32_(0x1) << PORT_EVCTRL_PORTEI3_Pos)           /* (PORT_EVCTRL) PORT Event Input Enable 3 Mask */
+#define PORT_EVCTRL_PORTEI3(value)            (PORT_EVCTRL_PORTEI3_Msk & (_UINT32_(value) << PORT_EVCTRL_PORTEI3_Pos)) /* Assignment of value for PORTEI3 in the PORT_EVCTRL register */
+#define PORT_EVCTRL_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (PORT_EVCTRL) Register Mask  */
+
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) Peripheral Multiplexing -------- */
+#define PORT_PMUX_RESETVALUE                  _UINT8_(0x00)                                        /*  (PORT_PMUX) Peripheral Multiplexing  Reset Value */
+
+#define PORT_PMUX_PMUXE_Pos                   _UINT8_(0)                                           /* (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Position */
+#define PORT_PMUX_PMUXE_Msk                   (_UINT8_(0xF) << PORT_PMUX_PMUXE_Pos)                /* (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Mask */
+#define PORT_PMUX_PMUXE(value)                (PORT_PMUX_PMUXE_Msk & (_UINT8_(value) << PORT_PMUX_PMUXE_Pos)) /* Assignment of value for PMUXE in the PORT_PMUX register */
+#define   PORT_PMUX_PMUXE_A_Val               _UINT8_(0x0)                                         /* (PORT_PMUX) Peripheral function A selected  */
+#define   PORT_PMUX_PMUXE_B_Val               _UINT8_(0x1)                                         /* (PORT_PMUX) Peripheral function B selected  */
+#define   PORT_PMUX_PMUXE_D_Val               _UINT8_(0x3)                                         /* (PORT_PMUX) Peripheral function D selected  */
+#define   PORT_PMUX_PMUXE_F_Val               _UINT8_(0x5)                                         /* (PORT_PMUX) Peripheral function F selected  */
+#define   PORT_PMUX_PMUXE_H_Val               _UINT8_(0x7)                                         /* (PORT_PMUX) Peripheral function H selected  */
+#define   PORT_PMUX_PMUXE_I_Val               _UINT8_(0x8)                                         /* (PORT_PMUX) Peripheral function I selected  */
+#define   PORT_PMUX_PMUXE_K_Val               _UINT8_(0xA)                                         /* (PORT_PMUX) Peripheral function K selected  */
+#define   PORT_PMUX_PMUXE_P_Val               _UINT8_(0xF)                                         /* (PORT_PMUX) Peripheral function P selected  */
+#define PORT_PMUX_PMUXE_A                     (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)       /* (PORT_PMUX) Peripheral function A selected Position */
+#define PORT_PMUX_PMUXE_B                     (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)       /* (PORT_PMUX) Peripheral function B selected Position */
+#define PORT_PMUX_PMUXE_D                     (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)       /* (PORT_PMUX) Peripheral function D selected Position */
+#define PORT_PMUX_PMUXE_F                     (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)       /* (PORT_PMUX) Peripheral function F selected Position */
+#define PORT_PMUX_PMUXE_H                     (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)       /* (PORT_PMUX) Peripheral function H selected Position */
+#define PORT_PMUX_PMUXE_I                     (PORT_PMUX_PMUXE_I_Val << PORT_PMUX_PMUXE_Pos)       /* (PORT_PMUX) Peripheral function I selected Position */
+#define PORT_PMUX_PMUXE_K                     (PORT_PMUX_PMUXE_K_Val << PORT_PMUX_PMUXE_Pos)       /* (PORT_PMUX) Peripheral function K selected Position */
+#define PORT_PMUX_PMUXE_P                     (PORT_PMUX_PMUXE_P_Val << PORT_PMUX_PMUXE_Pos)       /* (PORT_PMUX) Peripheral function P selected Position */
+#define PORT_PMUX_PMUXO_Pos                   _UINT8_(4)                                           /* (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Position */
+#define PORT_PMUX_PMUXO_Msk                   (_UINT8_(0xF) << PORT_PMUX_PMUXO_Pos)                /* (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Mask */
+#define PORT_PMUX_PMUXO(value)                (PORT_PMUX_PMUXO_Msk & (_UINT8_(value) << PORT_PMUX_PMUXO_Pos)) /* Assignment of value for PMUXO in the PORT_PMUX register */
+#define   PORT_PMUX_PMUXO_A_Val               _UINT8_(0x0)                                         /* (PORT_PMUX) Peripheral function A selected  */
+#define   PORT_PMUX_PMUXO_B_Val               _UINT8_(0x1)                                         /* (PORT_PMUX) Peripheral function B selected  */
+#define   PORT_PMUX_PMUXO_D_Val               _UINT8_(0x3)                                         /* (PORT_PMUX) Peripheral function D selected  */
+#define   PORT_PMUX_PMUXO_F_Val               _UINT8_(0x5)                                         /* (PORT_PMUX) Peripheral function F selected  */
+#define   PORT_PMUX_PMUXO_H_Val               _UINT8_(0x7)                                         /* (PORT_PMUX) Peripheral function H selected  */
+#define   PORT_PMUX_PMUXO_I_Val               _UINT8_(0x8)                                         /* (PORT_PMUX) Peripheral function I selected  */
+#define   PORT_PMUX_PMUXO_K_Val               _UINT8_(0xA)                                         /* (PORT_PMUX) Peripheral function K selected  */
+#define   PORT_PMUX_PMUXO_P_Val               _UINT8_(0xF)                                         /* (PORT_PMUX) Peripheral function P selected  */
+#define PORT_PMUX_PMUXO_A                     (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)       /* (PORT_PMUX) Peripheral function A selected Position */
+#define PORT_PMUX_PMUXO_B                     (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)       /* (PORT_PMUX) Peripheral function B selected Position */
+#define PORT_PMUX_PMUXO_D                     (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)       /* (PORT_PMUX) Peripheral function D selected Position */
+#define PORT_PMUX_PMUXO_F                     (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)       /* (PORT_PMUX) Peripheral function F selected Position */
+#define PORT_PMUX_PMUXO_H                     (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)       /* (PORT_PMUX) Peripheral function H selected Position */
+#define PORT_PMUX_PMUXO_I                     (PORT_PMUX_PMUXO_I_Val << PORT_PMUX_PMUXO_Pos)       /* (PORT_PMUX) Peripheral function I selected Position */
+#define PORT_PMUX_PMUXO_K                     (PORT_PMUX_PMUXO_K_Val << PORT_PMUX_PMUXO_Pos)       /* (PORT_PMUX) Peripheral function K selected Position */
+#define PORT_PMUX_PMUXO_P                     (PORT_PMUX_PMUXO_P_Val << PORT_PMUX_PMUXO_Pos)       /* (PORT_PMUX) Peripheral function P selected Position */
+#define PORT_PMUX_Msk                         _UINT8_(0xFF)                                        /* (PORT_PMUX) Register Mask  */
+
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) Pin Configuration -------- */
+#define PORT_PINCFG_RESETVALUE                _UINT8_(0x00)                                        /*  (PORT_PINCFG) Pin Configuration  Reset Value */
+
+#define PORT_PINCFG_PMUXEN_Pos                _UINT8_(0)                                           /* (PORT_PINCFG) Peripheral Multiplexer Enable Position */
+#define PORT_PINCFG_PMUXEN_Msk                (_UINT8_(0x1) << PORT_PINCFG_PMUXEN_Pos)             /* (PORT_PINCFG) Peripheral Multiplexer Enable Mask */
+#define PORT_PINCFG_PMUXEN(value)             (PORT_PINCFG_PMUXEN_Msk & (_UINT8_(value) << PORT_PINCFG_PMUXEN_Pos)) /* Assignment of value for PMUXEN in the PORT_PINCFG register */
+#define PORT_PINCFG_INEN_Pos                  _UINT8_(1)                                           /* (PORT_PINCFG) Input Enable Position */
+#define PORT_PINCFG_INEN_Msk                  (_UINT8_(0x1) << PORT_PINCFG_INEN_Pos)               /* (PORT_PINCFG) Input Enable Mask */
+#define PORT_PINCFG_INEN(value)               (PORT_PINCFG_INEN_Msk & (_UINT8_(value) << PORT_PINCFG_INEN_Pos)) /* Assignment of value for INEN in the PORT_PINCFG register */
+#define PORT_PINCFG_PULLEN_Pos                _UINT8_(2)                                           /* (PORT_PINCFG) Pull Enable Position */
+#define PORT_PINCFG_PULLEN_Msk                (_UINT8_(0x1) << PORT_PINCFG_PULLEN_Pos)             /* (PORT_PINCFG) Pull Enable Mask */
+#define PORT_PINCFG_PULLEN(value)             (PORT_PINCFG_PULLEN_Msk & (_UINT8_(value) << PORT_PINCFG_PULLEN_Pos)) /* Assignment of value for PULLEN in the PORT_PINCFG register */
+#define PORT_PINCFG_ODRAIN_Pos                _UINT8_(3)                                           /* (PORT_PINCFG) Open Drain Output Position */
+#define PORT_PINCFG_ODRAIN_Msk                (_UINT8_(0x1) << PORT_PINCFG_ODRAIN_Pos)             /* (PORT_PINCFG) Open Drain Output Mask */
+#define PORT_PINCFG_ODRAIN(value)             (PORT_PINCFG_ODRAIN_Msk & (_UINT8_(value) << PORT_PINCFG_ODRAIN_Pos)) /* Assignment of value for ODRAIN in the PORT_PINCFG register */
+#define PORT_PINCFG_SLEWLIM_Pos               _UINT8_(4)                                           /* (PORT_PINCFG) Output Driver Slew Rate Selection Position */
+#define PORT_PINCFG_SLEWLIM_Msk               (_UINT8_(0x3) << PORT_PINCFG_SLEWLIM_Pos)            /* (PORT_PINCFG) Output Driver Slew Rate Selection Mask */
+#define PORT_PINCFG_SLEWLIM(value)            (PORT_PINCFG_SLEWLIM_Msk & (_UINT8_(value) << PORT_PINCFG_SLEWLIM_Pos)) /* Assignment of value for SLEWLIM in the PORT_PINCFG register */
+#define   PORT_PINCFG_SLEWLIM_FAST_Val        _UINT8_(0x0)                                         /* (PORT_PINCFG) Slew rate control disabled (fast rise/fall time operation)  */
+#define   PORT_PINCFG_SLEWLIM_SLOW4_Val       _UINT8_(0x1)                                         /* (PORT_PINCFG) Slew rate control enabled (4x slower)  */
+#define   PORT_PINCFG_SLEWLIM_SLOW8_Val       _UINT8_(0x2)                                         /* (PORT_PINCFG) Slew rate control enabled (8x slower)  */
+#define   PORT_PINCFG_SLEWLIM_SLOW12_Val      _UINT8_(0x3)                                         /* (PORT_PINCFG) Slew rate control enabled (12x slower)  */
+#define PORT_PINCFG_SLEWLIM_FAST              (PORT_PINCFG_SLEWLIM_FAST_Val << PORT_PINCFG_SLEWLIM_Pos) /* (PORT_PINCFG) Slew rate control disabled (fast rise/fall time operation) Position */
+#define PORT_PINCFG_SLEWLIM_SLOW4             (PORT_PINCFG_SLEWLIM_SLOW4_Val << PORT_PINCFG_SLEWLIM_Pos) /* (PORT_PINCFG) Slew rate control enabled (4x slower) Position */
+#define PORT_PINCFG_SLEWLIM_SLOW8             (PORT_PINCFG_SLEWLIM_SLOW8_Val << PORT_PINCFG_SLEWLIM_Pos) /* (PORT_PINCFG) Slew rate control enabled (8x slower) Position */
+#define PORT_PINCFG_SLEWLIM_SLOW12            (PORT_PINCFG_SLEWLIM_SLOW12_Val << PORT_PINCFG_SLEWLIM_Pos) /* (PORT_PINCFG) Slew rate control enabled (12x slower) Position */
+#define PORT_PINCFG_Msk                       _UINT8_(0x3F)                                        /* (PORT_PINCFG) Register Mask  */
+
+
+/* -------- PORT_INTENCLR : (PORT Offset: 0x60) (R/W 32) Interrupt Enable Clear -------- */
+#define PORT_INTENCLR_RESETVALUE              _UINT32_(0x00)                                       /*  (PORT_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define PORT_INTENCLR_NSCHK_Pos               _UINT32_(0)                                          /* (PORT_INTENCLR) Non-Secure Check Interrupt Enable Position */
+#define PORT_INTENCLR_NSCHK_Msk               (_UINT32_(0x1) << PORT_INTENCLR_NSCHK_Pos)           /* (PORT_INTENCLR) Non-Secure Check Interrupt Enable Mask */
+#define PORT_INTENCLR_NSCHK(value)            (PORT_INTENCLR_NSCHK_Msk & (_UINT32_(value) << PORT_INTENCLR_NSCHK_Pos)) /* Assignment of value for NSCHK in the PORT_INTENCLR register */
+#define PORT_INTENCLR_Msk                     _UINT32_(0x00000001)                                 /* (PORT_INTENCLR) Register Mask  */
+
+
+/* -------- PORT_INTENSET : (PORT Offset: 0x64) (R/W 32) Interrupt Enable Set -------- */
+#define PORT_INTENSET_RESETVALUE              _UINT32_(0x00)                                       /*  (PORT_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define PORT_INTENSET_NSCHK_Pos               _UINT32_(0)                                          /* (PORT_INTENSET) Non-Secure Check Interrupt Enable Position */
+#define PORT_INTENSET_NSCHK_Msk               (_UINT32_(0x1) << PORT_INTENSET_NSCHK_Pos)           /* (PORT_INTENSET) Non-Secure Check Interrupt Enable Mask */
+#define PORT_INTENSET_NSCHK(value)            (PORT_INTENSET_NSCHK_Msk & (_UINT32_(value) << PORT_INTENSET_NSCHK_Pos)) /* Assignment of value for NSCHK in the PORT_INTENSET register */
+#define PORT_INTENSET_Msk                     _UINT32_(0x00000001)                                 /* (PORT_INTENSET) Register Mask  */
+
+
+/* -------- PORT_INTFLAG : (PORT Offset: 0x68) (R/W 32) Interrupt Flag Status and Clear -------- */
+#define PORT_INTFLAG_RESETVALUE               _UINT32_(0x00)                                       /*  (PORT_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define PORT_INTFLAG_NSCHK_Pos                _UINT32_(0)                                          /* (PORT_INTFLAG) Non-Secure Check Position */
+#define PORT_INTFLAG_NSCHK_Msk                (_UINT32_(0x1) << PORT_INTFLAG_NSCHK_Pos)            /* (PORT_INTFLAG) Non-Secure Check Mask */
+#define PORT_INTFLAG_NSCHK(value)             (PORT_INTFLAG_NSCHK_Msk & (_UINT32_(value) << PORT_INTFLAG_NSCHK_Pos)) /* Assignment of value for NSCHK in the PORT_INTFLAG register */
+#define PORT_INTFLAG_Msk                      _UINT32_(0x00000001)                                 /* (PORT_INTFLAG) Register Mask  */
+
+
+/* -------- PORT_NONSEC : (PORT Offset: 0x6C) (R/W 32) Security Attribution -------- */
+#define PORT_NONSEC_RESETVALUE                _UINT32_(0x00)                                       /*  (PORT_NONSEC) Security Attribution  Reset Value */
+
+#define PORT_NONSEC_NONSEC_Pos                _UINT32_(0)                                          /* (PORT_NONSEC) Port Security Attribution Position */
+#define PORT_NONSEC_NONSEC_Msk                (_UINT32_(0xFFFFFFFF) << PORT_NONSEC_NONSEC_Pos)     /* (PORT_NONSEC) Port Security Attribution Mask */
+#define PORT_NONSEC_NONSEC(value)             (PORT_NONSEC_NONSEC_Msk & (_UINT32_(value) << PORT_NONSEC_NONSEC_Pos)) /* Assignment of value for NONSEC in the PORT_NONSEC register */
+#define PORT_NONSEC_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (PORT_NONSEC) Register Mask  */
+
+
+/* -------- PORT_NSCHK : (PORT Offset: 0x70) (R/W 32) Security Attribution Check -------- */
+#define PORT_NSCHK_RESETVALUE                 _UINT32_(0x00)                                       /*  (PORT_NSCHK) Security Attribution Check  Reset Value */
+
+#define PORT_NSCHK_NSCHK_Pos                  _UINT32_(0)                                          /* (PORT_NSCHK) Port Security Attribution Check Position */
+#define PORT_NSCHK_NSCHK_Msk                  (_UINT32_(0xFFFFFFFF) << PORT_NSCHK_NSCHK_Pos)       /* (PORT_NSCHK) Port Security Attribution Check Mask */
+#define PORT_NSCHK_NSCHK(value)               (PORT_NSCHK_NSCHK_Msk & (_UINT32_(value) << PORT_NSCHK_NSCHK_Pos)) /* Assignment of value for NSCHK in the PORT_NSCHK register */
+#define PORT_NSCHK_Msk                        _UINT32_(0xFFFFFFFF)                                 /* (PORT_NSCHK) Register Mask  */
+
+
+/* PORT register offsets definitions */
+#define PORT_DIR_REG_OFST              _UINT32_(0x00)      /* (PORT_DIR) Data Direction Offset */
+#define PORT_DIRCLR_REG_OFST           _UINT32_(0x04)      /* (PORT_DIRCLR) Data Direction Clear Offset */
+#define PORT_DIRSET_REG_OFST           _UINT32_(0x08)      /* (PORT_DIRSET) Data Direction Set Offset */
+#define PORT_DIRTGL_REG_OFST           _UINT32_(0x0C)      /* (PORT_DIRTGL) Data Direction Toggle Offset */
+#define PORT_OUT_REG_OFST              _UINT32_(0x10)      /* (PORT_OUT) Data Output Value Offset */
+#define PORT_OUTCLR_REG_OFST           _UINT32_(0x14)      /* (PORT_OUTCLR) Data Output Value Clear Offset */
+#define PORT_OUTSET_REG_OFST           _UINT32_(0x18)      /* (PORT_OUTSET) Data Output Value Set Offset */
+#define PORT_OUTTGL_REG_OFST           _UINT32_(0x1C)      /* (PORT_OUTTGL) Data Output Value Toggle Offset */
+#define PORT_IN_REG_OFST               _UINT32_(0x20)      /* (PORT_IN) Data Input Value Offset */
+#define PORT_CTRL_REG_OFST             _UINT32_(0x24)      /* (PORT_CTRL) Control Offset */
+#define PORT_WRCONFIG_REG_OFST         _UINT32_(0x28)      /* (PORT_WRCONFIG) Write Configuration Offset */
+#define PORT_EVCTRL_REG_OFST           _UINT32_(0x2C)      /* (PORT_EVCTRL) Event Input Control Offset */
+#define PORT_PMUX_REG_OFST             _UINT32_(0x30)      /* (PORT_PMUX) Peripheral Multiplexing Offset */
+#define PORT_PMUX0_REG_OFST            _UINT32_(0x30)      /* (PORT_PMUX0) Peripheral Multiplexing Offset */
+#define PORT_PMUX1_REG_OFST            _UINT32_(0x31)      /* (PORT_PMUX1) Peripheral Multiplexing Offset */
+#define PORT_PMUX2_REG_OFST            _UINT32_(0x32)      /* (PORT_PMUX2) Peripheral Multiplexing Offset */
+#define PORT_PMUX3_REG_OFST            _UINT32_(0x33)      /* (PORT_PMUX3) Peripheral Multiplexing Offset */
+#define PORT_PMUX4_REG_OFST            _UINT32_(0x34)      /* (PORT_PMUX4) Peripheral Multiplexing Offset */
+#define PORT_PMUX5_REG_OFST            _UINT32_(0x35)      /* (PORT_PMUX5) Peripheral Multiplexing Offset */
+#define PORT_PMUX6_REG_OFST            _UINT32_(0x36)      /* (PORT_PMUX6) Peripheral Multiplexing Offset */
+#define PORT_PMUX7_REG_OFST            _UINT32_(0x37)      /* (PORT_PMUX7) Peripheral Multiplexing Offset */
+#define PORT_PMUX8_REG_OFST            _UINT32_(0x38)      /* (PORT_PMUX8) Peripheral Multiplexing Offset */
+#define PORT_PMUX9_REG_OFST            _UINT32_(0x39)      /* (PORT_PMUX9) Peripheral Multiplexing Offset */
+#define PORT_PMUX10_REG_OFST           _UINT32_(0x3A)      /* (PORT_PMUX10) Peripheral Multiplexing Offset */
+#define PORT_PMUX11_REG_OFST           _UINT32_(0x3B)      /* (PORT_PMUX11) Peripheral Multiplexing Offset */
+#define PORT_PMUX12_REG_OFST           _UINT32_(0x3C)      /* (PORT_PMUX12) Peripheral Multiplexing Offset */
+#define PORT_PMUX13_REG_OFST           _UINT32_(0x3D)      /* (PORT_PMUX13) Peripheral Multiplexing Offset */
+#define PORT_PMUX14_REG_OFST           _UINT32_(0x3E)      /* (PORT_PMUX14) Peripheral Multiplexing Offset */
+#define PORT_PMUX15_REG_OFST           _UINT32_(0x3F)      /* (PORT_PMUX15) Peripheral Multiplexing Offset */
+#define PORT_PINCFG_REG_OFST           _UINT32_(0x40)      /* (PORT_PINCFG) Pin Configuration Offset */
+#define PORT_PINCFG0_REG_OFST          _UINT32_(0x40)      /* (PORT_PINCFG0) Pin Configuration Offset */
+#define PORT_PINCFG1_REG_OFST          _UINT32_(0x41)      /* (PORT_PINCFG1) Pin Configuration Offset */
+#define PORT_PINCFG2_REG_OFST          _UINT32_(0x42)      /* (PORT_PINCFG2) Pin Configuration Offset */
+#define PORT_PINCFG3_REG_OFST          _UINT32_(0x43)      /* (PORT_PINCFG3) Pin Configuration Offset */
+#define PORT_PINCFG4_REG_OFST          _UINT32_(0x44)      /* (PORT_PINCFG4) Pin Configuration Offset */
+#define PORT_PINCFG5_REG_OFST          _UINT32_(0x45)      /* (PORT_PINCFG5) Pin Configuration Offset */
+#define PORT_PINCFG6_REG_OFST          _UINT32_(0x46)      /* (PORT_PINCFG6) Pin Configuration Offset */
+#define PORT_PINCFG7_REG_OFST          _UINT32_(0x47)      /* (PORT_PINCFG7) Pin Configuration Offset */
+#define PORT_PINCFG8_REG_OFST          _UINT32_(0x48)      /* (PORT_PINCFG8) Pin Configuration Offset */
+#define PORT_PINCFG9_REG_OFST          _UINT32_(0x49)      /* (PORT_PINCFG9) Pin Configuration Offset */
+#define PORT_PINCFG10_REG_OFST         _UINT32_(0x4A)      /* (PORT_PINCFG10) Pin Configuration Offset */
+#define PORT_PINCFG11_REG_OFST         _UINT32_(0x4B)      /* (PORT_PINCFG11) Pin Configuration Offset */
+#define PORT_PINCFG12_REG_OFST         _UINT32_(0x4C)      /* (PORT_PINCFG12) Pin Configuration Offset */
+#define PORT_PINCFG13_REG_OFST         _UINT32_(0x4D)      /* (PORT_PINCFG13) Pin Configuration Offset */
+#define PORT_PINCFG14_REG_OFST         _UINT32_(0x4E)      /* (PORT_PINCFG14) Pin Configuration Offset */
+#define PORT_PINCFG15_REG_OFST         _UINT32_(0x4F)      /* (PORT_PINCFG15) Pin Configuration Offset */
+#define PORT_PINCFG16_REG_OFST         _UINT32_(0x50)      /* (PORT_PINCFG16) Pin Configuration Offset */
+#define PORT_PINCFG17_REG_OFST         _UINT32_(0x51)      /* (PORT_PINCFG17) Pin Configuration Offset */
+#define PORT_PINCFG18_REG_OFST         _UINT32_(0x52)      /* (PORT_PINCFG18) Pin Configuration Offset */
+#define PORT_PINCFG19_REG_OFST         _UINT32_(0x53)      /* (PORT_PINCFG19) Pin Configuration Offset */
+#define PORT_PINCFG20_REG_OFST         _UINT32_(0x54)      /* (PORT_PINCFG20) Pin Configuration Offset */
+#define PORT_PINCFG21_REG_OFST         _UINT32_(0x55)      /* (PORT_PINCFG21) Pin Configuration Offset */
+#define PORT_PINCFG22_REG_OFST         _UINT32_(0x56)      /* (PORT_PINCFG22) Pin Configuration Offset */
+#define PORT_PINCFG23_REG_OFST         _UINT32_(0x57)      /* (PORT_PINCFG23) Pin Configuration Offset */
+#define PORT_PINCFG24_REG_OFST         _UINT32_(0x58)      /* (PORT_PINCFG24) Pin Configuration Offset */
+#define PORT_PINCFG25_REG_OFST         _UINT32_(0x59)      /* (PORT_PINCFG25) Pin Configuration Offset */
+#define PORT_PINCFG26_REG_OFST         _UINT32_(0x5A)      /* (PORT_PINCFG26) Pin Configuration Offset */
+#define PORT_PINCFG27_REG_OFST         _UINT32_(0x5B)      /* (PORT_PINCFG27) Pin Configuration Offset */
+#define PORT_PINCFG28_REG_OFST         _UINT32_(0x5C)      /* (PORT_PINCFG28) Pin Configuration Offset */
+#define PORT_PINCFG29_REG_OFST         _UINT32_(0x5D)      /* (PORT_PINCFG29) Pin Configuration Offset */
+#define PORT_PINCFG30_REG_OFST         _UINT32_(0x5E)      /* (PORT_PINCFG30) Pin Configuration Offset */
+#define PORT_PINCFG31_REG_OFST         _UINT32_(0x5F)      /* (PORT_PINCFG31) Pin Configuration Offset */
+#define PORT_INTENCLR_REG_OFST         _UINT32_(0x60)      /* (PORT_INTENCLR) Interrupt Enable Clear Offset */
+#define PORT_INTENSET_REG_OFST         _UINT32_(0x64)      /* (PORT_INTENSET) Interrupt Enable Set Offset */
+#define PORT_INTFLAG_REG_OFST          _UINT32_(0x68)      /* (PORT_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define PORT_NONSEC_REG_OFST           _UINT32_(0x6C)      /* (PORT_NONSEC) Security Attribution Offset */
+#define PORT_NSCHK_REG_OFST            _UINT32_(0x70)      /* (PORT_NSCHK) Security Attribution Check Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* GROUP register API structure */
+typedef struct
+{
+  __IO  uint32_t                       PORT_DIR;           /* Offset: 0x00 (R/W  32) Data Direction */
+  __IO  uint32_t                       PORT_DIRCLR;        /* Offset: 0x04 (R/W  32) Data Direction Clear */
+  __IO  uint32_t                       PORT_DIRSET;        /* Offset: 0x08 (R/W  32) Data Direction Set */
+  __IO  uint32_t                       PORT_DIRTGL;        /* Offset: 0x0C (R/W  32) Data Direction Toggle */
+  __IO  uint32_t                       PORT_OUT;           /* Offset: 0x10 (R/W  32) Data Output Value */
+  __IO  uint32_t                       PORT_OUTCLR;        /* Offset: 0x14 (R/W  32) Data Output Value Clear */
+  __IO  uint32_t                       PORT_OUTSET;        /* Offset: 0x18 (R/W  32) Data Output Value Set */
+  __IO  uint32_t                       PORT_OUTTGL;        /* Offset: 0x1C (R/W  32) Data Output Value Toggle */
+  __I   uint32_t                       PORT_IN;            /* Offset: 0x20 (R/   32) Data Input Value */
+  __IO  uint32_t                       PORT_CTRL;          /* Offset: 0x24 (R/W  32) Control */
+  __O   uint32_t                       PORT_WRCONFIG;      /* Offset: 0x28 ( /W  32) Write Configuration */
+  __IO  uint32_t                       PORT_EVCTRL;        /* Offset: 0x2C (R/W  32) Event Input Control */
+  __IO  uint8_t                        PORT_PMUX[16];      /* Offset: 0x30 (R/W  8) Peripheral Multiplexing */
+  __IO  uint8_t                        PORT_PINCFG[32];    /* Offset: 0x40 (R/W  8) Pin Configuration */
+  __IO  uint32_t                       PORT_INTENCLR;      /* Offset: 0x60 (R/W  32) Interrupt Enable Clear */
+  __IO  uint32_t                       PORT_INTENSET;      /* Offset: 0x64 (R/W  32) Interrupt Enable Set */
+  __IO  uint32_t                       PORT_INTFLAG;       /* Offset: 0x68 (R/W  32) Interrupt Flag Status and Clear */
+  __IO  uint32_t                       PORT_NONSEC;        /* Offset: 0x6C (R/W  32) Security Attribution */
+  __IO  uint32_t                       PORT_NSCHK;         /* Offset: 0x70 (R/W  32) Security Attribution Check */
+  __I   uint8_t                        Reserved1[0x0C];
+} port_group_registers_t;
+
+#define PORT_GROUP_NUMBER 4
+
+/* PORT register API structure */
+typedef struct
+{  /* Port Module */
+        port_group_registers_t         GROUP[PORT_GROUP_NUMBER]; /* Offset: 0x00  */
+} port_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_PORT_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/ptc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/ptc.h
new file mode 100644
index 00000000..11ca048a
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/ptc.h
@@ -0,0 +1,569 @@
+/*
+ * Component description for PTC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_PTC_COMPONENT_H_
+#define _PIC32CMGC00_PTC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR PTC                       */
+/* ************************************************************************** */
+
+/* -------- PTC_CTRLA : (PTC Offset: 0x00) (R/W 32) CONTROL ENABLE REGISTER -------- */
+#define PTC_CTRLA_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_CTRLA) CONTROL ENABLE REGISTER  Reset Value */
+
+#define PTC_CTRLA_SWRST_Pos                   _UINT32_(0)                                          /* (PTC_CTRLA) Software Reset for this macro. Position */
+#define PTC_CTRLA_SWRST_Msk                   (_UINT32_(0x1) << PTC_CTRLA_SWRST_Pos)               /* (PTC_CTRLA) Software Reset for this macro. Mask */
+#define PTC_CTRLA_SWRST(value)                (PTC_CTRLA_SWRST_Msk & (_UINT32_(value) << PTC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the PTC_CTRLA register */
+#define   PTC_CTRLA_SWRST_0_Val               _UINT32_(0x0)                                        /* (PTC_CTRLA) There is no reset operation ongoing  */
+#define   PTC_CTRLA_SWRST_1_Val               _UINT32_(0x1)                                        /* (PTC_CTRLA) The reset operation is ongoing  */
+#define PTC_CTRLA_SWRST_0                     (PTC_CTRLA_SWRST_0_Val << PTC_CTRLA_SWRST_Pos)       /* (PTC_CTRLA) There is no reset operation ongoing Position */
+#define PTC_CTRLA_SWRST_1                     (PTC_CTRLA_SWRST_1_Val << PTC_CTRLA_SWRST_Pos)       /* (PTC_CTRLA) The reset operation is ongoing Position */
+#define PTC_CTRLA_ENABLE_Pos                  _UINT32_(1)                                          /* (PTC_CTRLA) PTC -- Enable Position */
+#define PTC_CTRLA_ENABLE_Msk                  (_UINT32_(0x1) << PTC_CTRLA_ENABLE_Pos)              /* (PTC_CTRLA) PTC -- Enable Mask */
+#define PTC_CTRLA_ENABLE(value)               (PTC_CTRLA_ENABLE_Msk & (_UINT32_(value) << PTC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the PTC_CTRLA register */
+#define   PTC_CTRLA_ENABLE_0_Val              _UINT32_(0x0)                                        /* (PTC_CTRLA) Disable module. System clock is only requested for bus transactions. GCLK is never requested.  */
+#define   PTC_CTRLA_ENABLE_1_Val              _UINT32_(0x1)                                        /* (PTC_CTRLA) Enable module by allowing both the generic clock and system clock requests based on the incoming clock requests from the SIB.  */
+#define PTC_CTRLA_ENABLE_0                    (PTC_CTRLA_ENABLE_0_Val << PTC_CTRLA_ENABLE_Pos)     /* (PTC_CTRLA) Disable module. System clock is only requested for bus transactions. GCLK is never requested. Position */
+#define PTC_CTRLA_ENABLE_1                    (PTC_CTRLA_ENABLE_1_Val << PTC_CTRLA_ENABLE_Pos)     /* (PTC_CTRLA) Enable module by allowing both the generic clock and system clock requests based on the incoming clock requests from the SIB. Position */
+#define PTC_CTRLA_PRIV_Pos                    _UINT32_(2)                                          /* (PTC_CTRLA) Privileged Access Only -- provides filtering of privilege/non-privilege bus accesses to SFR registers Position */
+#define PTC_CTRLA_PRIV_Msk                    (_UINT32_(0x1) << PTC_CTRLA_PRIV_Pos)                /* (PTC_CTRLA) Privileged Access Only -- provides filtering of privilege/non-privilege bus accesses to SFR registers Mask */
+#define PTC_CTRLA_PRIV(value)                 (PTC_CTRLA_PRIV_Msk & (_UINT32_(value) << PTC_CTRLA_PRIV_Pos)) /* Assignment of value for PRIV in the PTC_CTRLA register */
+#define PTC_CTRLA_RUNSTDBY_Pos                _UINT32_(6)                                          /* (PTC_CTRLA) Run In Standby Position */
+#define PTC_CTRLA_RUNSTDBY_Msk                (_UINT32_(0x1) << PTC_CTRLA_RUNSTDBY_Pos)            /* (PTC_CTRLA) Run In Standby Mask */
+#define PTC_CTRLA_RUNSTDBY(value)             (PTC_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << PTC_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the PTC_CTRLA register */
+#define PTC_CTRLA_ONDEMAND_Pos                _UINT32_(7)                                          /* (PTC_CTRLA) On Demand Control Position */
+#define PTC_CTRLA_ONDEMAND_Msk                (_UINT32_(0x1) << PTC_CTRLA_ONDEMAND_Pos)            /* (PTC_CTRLA) On Demand Control Mask */
+#define PTC_CTRLA_ONDEMAND(value)             (PTC_CTRLA_ONDEMAND_Msk & (_UINT32_(value) << PTC_CTRLA_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the PTC_CTRLA register */
+#define PTC_CTRLA_Msk                         _UINT32_(0x000000C7)                                 /* (PTC_CTRLA) Register Mask  */
+
+
+/* -------- PTC_EVCTRL : (PTC Offset: 0x04) (R/W 32) EVENT CONTROL REGISTER -------- */
+#define PTC_EVCTRL_RESETVALUE                 _UINT32_(0x00)                                       /*  (PTC_EVCTRL) EVENT CONTROL REGISTER  Reset Value */
+
+#define PTC_EVCTRL_STCONVEI_Pos               _UINT32_(0)                                          /* (PTC_EVCTRL) Start Conversion Event Input Enable Position */
+#define PTC_EVCTRL_STCONVEI_Msk               (_UINT32_(0x1) << PTC_EVCTRL_STCONVEI_Pos)           /* (PTC_EVCTRL) Start Conversion Event Input Enable Mask */
+#define PTC_EVCTRL_STCONVEI(value)            (PTC_EVCTRL_STCONVEI_Msk & (_UINT32_(value) << PTC_EVCTRL_STCONVEI_Pos)) /* Assignment of value for STCONVEI in the PTC_EVCTRL register */
+#define PTC_EVCTRL_DSEQREI_Pos                _UINT32_(1)                                          /* (PTC_EVCTRL) DMA Sequencing Restart Event Input Enable Position */
+#define PTC_EVCTRL_DSEQREI_Msk                (_UINT32_(0x1) << PTC_EVCTRL_DSEQREI_Pos)            /* (PTC_EVCTRL) DMA Sequencing Restart Event Input Enable Mask */
+#define PTC_EVCTRL_DSEQREI(value)             (PTC_EVCTRL_DSEQREI_Msk & (_UINT32_(value) << PTC_EVCTRL_DSEQREI_Pos)) /* Assignment of value for DSEQREI in the PTC_EVCTRL register */
+#define PTC_EVCTRL_STCONVINV_Pos              _UINT32_(2)                                          /* (PTC_EVCTRL) Start Conversion Event Invert Enable Position */
+#define PTC_EVCTRL_STCONVINV_Msk              (_UINT32_(0x1) << PTC_EVCTRL_STCONVINV_Pos)          /* (PTC_EVCTRL) Start Conversion Event Invert Enable Mask */
+#define PTC_EVCTRL_STCONVINV(value)           (PTC_EVCTRL_STCONVINV_Msk & (_UINT32_(value) << PTC_EVCTRL_STCONVINV_Pos)) /* Assignment of value for STCONVINV in the PTC_EVCTRL register */
+#define PTC_EVCTRL_DSEQRINV_Pos               _UINT32_(3)                                          /* (PTC_EVCTRL) DMA Sequencing Restart Event Invert Enable Position */
+#define PTC_EVCTRL_DSEQRINV_Msk               (_UINT32_(0x1) << PTC_EVCTRL_DSEQRINV_Pos)           /* (PTC_EVCTRL) DMA Sequencing Restart Event Invert Enable Mask */
+#define PTC_EVCTRL_DSEQRINV(value)            (PTC_EVCTRL_DSEQRINV_Msk & (_UINT32_(value) << PTC_EVCTRL_DSEQRINV_Pos)) /* Assignment of value for DSEQRINV in the PTC_EVCTRL register */
+#define PTC_EVCTRL_EOCEO_Pos                  _UINT32_(4)                                          /* (PTC_EVCTRL) End of Conversion Event Output Enable Position */
+#define PTC_EVCTRL_EOCEO_Msk                  (_UINT32_(0x1) << PTC_EVCTRL_EOCEO_Pos)              /* (PTC_EVCTRL) End of Conversion Event Output Enable Mask */
+#define PTC_EVCTRL_EOCEO(value)               (PTC_EVCTRL_EOCEO_Msk & (_UINT32_(value) << PTC_EVCTRL_EOCEO_Pos)) /* Assignment of value for EOCEO in the PTC_EVCTRL register */
+#define PTC_EVCTRL_WCOMPEO_Pos                _UINT32_(5)                                          /* (PTC_EVCTRL) Window Comparator Event Output Enable Position */
+#define PTC_EVCTRL_WCOMPEO_Msk                (_UINT32_(0x1) << PTC_EVCTRL_WCOMPEO_Pos)            /* (PTC_EVCTRL) Window Comparator Event Output Enable Mask */
+#define PTC_EVCTRL_WCOMPEO(value)             (PTC_EVCTRL_WCOMPEO_Msk & (_UINT32_(value) << PTC_EVCTRL_WCOMPEO_Pos)) /* Assignment of value for WCOMPEO in the PTC_EVCTRL register */
+#define PTC_EVCTRL_Msk                        _UINT32_(0x0000003F)                                 /* (PTC_EVCTRL) Register Mask  */
+
+
+/* -------- PTC_DBGCTRL : (PTC Offset: 0x08) (R/W 32) DEBUG CONTROL Register -------- */
+#define PTC_DBGCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (PTC_DBGCTRL) DEBUG CONTROL Register  Reset Value */
+
+#define PTC_DBGCTRL_DBGRUN_Pos                _UINT32_(0)                                          /* (PTC_DBGCTRL) Debug Run Position */
+#define PTC_DBGCTRL_DBGRUN_Msk                (_UINT32_(0x1) << PTC_DBGCTRL_DBGRUN_Pos)            /* (PTC_DBGCTRL) Debug Run Mask */
+#define PTC_DBGCTRL_DBGRUN(value)             (PTC_DBGCTRL_DBGRUN_Msk & (_UINT32_(value) << PTC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the PTC_DBGCTRL register */
+#define PTC_DBGCTRL_Msk                       _UINT32_(0x00000001)                                 /* (PTC_DBGCTRL) Register Mask  */
+
+
+/* -------- PTC_CTRLB : (PTC Offset: 0x0C) (R/W 32) CONTROL B Register -------- */
+#define PTC_CTRLB_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_CTRLB) CONTROL B Register  Reset Value */
+
+#define PTC_CTRLB_CTSM_Pos                    _UINT32_(0)                                          /* (PTC_CTRLB) Capacitive Touch Sensing Mode Position */
+#define PTC_CTRLB_CTSM_Msk                    (_UINT32_(0x7) << PTC_CTRLB_CTSM_Pos)                /* (PTC_CTRLB) Capacitive Touch Sensing Mode Mask */
+#define PTC_CTRLB_CTSM(value)                 (PTC_CTRLB_CTSM_Msk & (_UINT32_(value) << PTC_CTRLB_CTSM_Pos)) /* Assignment of value for CTSM in the PTC_CTRLB register */
+#define PTC_CTRLB_INTSEL_Pos                  _UINT32_(4)                                          /* (PTC_CTRLB) Interrupt Selection Position */
+#define PTC_CTRLB_INTSEL_Msk                  (_UINT32_(0x1) << PTC_CTRLB_INTSEL_Pos)              /* (PTC_CTRLB) Interrupt Selection Mask */
+#define PTC_CTRLB_INTSEL(value)               (PTC_CTRLB_INTSEL_Msk & (_UINT32_(value) << PTC_CTRLB_INTSEL_Pos)) /* Assignment of value for INTSEL in the PTC_CTRLB register */
+#define PTC_CTRLB_SDS_Pos                     _UINT32_(8)                                          /* (PTC_CTRLB) Sampling Delay Selection. Position */
+#define PTC_CTRLB_SDS_Msk                     (_UINT32_(0xF) << PTC_CTRLB_SDS_Pos)                 /* (PTC_CTRLB) Sampling Delay Selection. Mask */
+#define PTC_CTRLB_SDS(value)                  (PTC_CTRLB_SDS_Msk & (_UINT32_(value) << PTC_CTRLB_SDS_Pos)) /* Assignment of value for SDS in the PTC_CTRLB register */
+#define PTC_CTRLB_ASDV_Pos                    _UINT32_(12)                                         /* (PTC_CTRLB) Automatic Sampling Delay Variation. Position */
+#define PTC_CTRLB_ASDV_Msk                    (_UINT32_(0x1) << PTC_CTRLB_ASDV_Pos)                /* (PTC_CTRLB) Automatic Sampling Delay Variation. Mask */
+#define PTC_CTRLB_ASDV(value)                 (PTC_CTRLB_ASDV_Msk & (_UINT32_(value) << PTC_CTRLB_ASDV_Pos)) /* Assignment of value for ASDV in the PTC_CTRLB register */
+#define PTC_CTRLB_CCDS_Pos                    _UINT32_(13)                                         /* (PTC_CTRLB) Channel Change Delay Selection Position */
+#define PTC_CTRLB_CCDS_Msk                    (_UINT32_(0x3) << PTC_CTRLB_CCDS_Pos)                /* (PTC_CTRLB) Channel Change Delay Selection Mask */
+#define PTC_CTRLB_CCDS(value)                 (PTC_CTRLB_CCDS_Msk & (_UINT32_(value) << PTC_CTRLB_CCDS_Pos)) /* Assignment of value for CCDS in the PTC_CTRLB register */
+#define PTC_CTRLB_RSEL_Pos                    _UINT32_(20)                                         /* (PTC_CTRLB) Resistor Selection Position */
+#define PTC_CTRLB_RSEL_Msk                    (_UINT32_(0x7) << PTC_CTRLB_RSEL_Pos)                /* (PTC_CTRLB) Resistor Selection Mask */
+#define PTC_CTRLB_RSEL(value)                 (PTC_CTRLB_RSEL_Msk & (_UINT32_(value) << PTC_CTRLB_RSEL_Pos)) /* Assignment of value for RSEL in the PTC_CTRLB register */
+#define PTC_CTRLB_Msk                         _UINT32_(0x00707F17)                                 /* (PTC_CTRLB) Register Mask  */
+
+
+/* -------- PTC_CTRLC : (PTC Offset: 0x10) (R/W 32) CONTROL C Register -------- */
+#define PTC_CTRLC_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_CTRLC) CONTROL C Register  Reset Value */
+
+#define PTC_CTRLC_CCF_Pos                     _UINT32_(0)                                          /* (PTC_CTRLC) Compensation Capacitor Fine Value Position */
+#define PTC_CTRLC_CCF_Msk                     (_UINT32_(0x1F) << PTC_CTRLC_CCF_Pos)                /* (PTC_CTRLC) Compensation Capacitor Fine Value Mask */
+#define PTC_CTRLC_CCF(value)                  (PTC_CTRLC_CCF_Msk & (_UINT32_(value) << PTC_CTRLC_CCF_Pos)) /* Assignment of value for CCF in the PTC_CTRLC register */
+#define PTC_CTRLC_CCC_Pos                     _UINT32_(8)                                          /* (PTC_CTRLC) Compensation Capacitor Coarse Value Position */
+#define PTC_CTRLC_CCC_Msk                     (_UINT32_(0x1F) << PTC_CTRLC_CCC_Pos)                /* (PTC_CTRLC) Compensation Capacitor Coarse Value Mask */
+#define PTC_CTRLC_CCC(value)                  (PTC_CTRLC_CCC_Msk & (_UINT32_(value) << PTC_CTRLC_CCC_Pos)) /* Assignment of value for CCC in the PTC_CTRLC register */
+#define PTC_CTRLC_CI_Pos                      _UINT32_(16)                                         /* (PTC_CTRLC) Integration Capacitor Value Position */
+#define PTC_CTRLC_CI_Msk                      (_UINT32_(0x1F) << PTC_CTRLC_CI_Pos)                 /* (PTC_CTRLC) Integration Capacitor Value Mask */
+#define PTC_CTRLC_CI(value)                   (PTC_CTRLC_CI_Msk & (_UINT32_(value) << PTC_CTRLC_CI_Pos)) /* Assignment of value for CI in the PTC_CTRLC register */
+#define PTC_CTRLC_CSD_Pos                     _UINT32_(24)                                         /* (PTC_CTRLC) Charge Share Delay Value Position */
+#define PTC_CTRLC_CSD_Msk                     (_UINT32_(0xFF) << PTC_CTRLC_CSD_Pos)                /* (PTC_CTRLC) Charge Share Delay Value Mask */
+#define PTC_CTRLC_CSD(value)                  (PTC_CTRLC_CSD_Msk & (_UINT32_(value) << PTC_CTRLC_CSD_Pos)) /* Assignment of value for CSD in the PTC_CTRLC register */
+#define PTC_CTRLC_Msk                         _UINT32_(0xFF1F1F1F)                                 /* (PTC_CTRLC) Register Mask  */
+
+
+/* -------- PTC_CTRLD : (PTC Offset: 0x14) (R/W 32) CONTROL D Register -------- */
+#define PTC_CTRLD_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_CTRLD) CONTROL D Register  Reset Value */
+
+#define PTC_CTRLD_DAN_Pos                     _UINT32_(0)                                          /* (PTC_CTRLD) Digital Accumulation Number Position */
+#define PTC_CTRLD_DAN_Msk                     (_UINT32_(0x7) << PTC_CTRLD_DAN_Pos)                 /* (PTC_CTRLD) Digital Accumulation Number Mask */
+#define PTC_CTRLD_DAN(value)                  (PTC_CTRLD_DAN_Msk & (_UINT32_(value) << PTC_CTRLD_DAN_Pos)) /* Assignment of value for DAN in the PTC_CTRLD register */
+#define PTC_CTRLD_AAN_Pos                     _UINT32_(8)                                          /* (PTC_CTRLD) Analog Accumulation Number Position */
+#define PTC_CTRLD_AAN_Msk                     (_UINT32_(0xF) << PTC_CTRLD_AAN_Pos)                 /* (PTC_CTRLD) Analog Accumulation Number Mask */
+#define PTC_CTRLD_AAN(value)                  (PTC_CTRLD_AAN_Msk & (_UINT32_(value) << PTC_CTRLD_AAN_Pos)) /* Assignment of value for AAN in the PTC_CTRLD register */
+#define PTC_CTRLD_WINCM_Pos                   _UINT32_(16)                                         /* (PTC_CTRLD) Window Comparator Mode Position */
+#define PTC_CTRLD_WINCM_Msk                   (_UINT32_(0x7) << PTC_CTRLD_WINCM_Pos)               /* (PTC_CTRLD) Window Comparator Mode Mask */
+#define PTC_CTRLD_WINCM(value)                (PTC_CTRLD_WINCM_Msk & (_UINT32_(value) << PTC_CTRLD_WINCM_Pos)) /* Assignment of value for WINCM in the PTC_CTRLD register */
+#define PTC_CTRLD_WINSS_Pos                   _UINT32_(19)                                         /* (PTC_CTRLD) Window Single Sample Position */
+#define PTC_CTRLD_WINSS_Msk                   (_UINT32_(0x1) << PTC_CTRLD_WINSS_Pos)               /* (PTC_CTRLD) Window Single Sample Mask */
+#define PTC_CTRLD_WINSS(value)                (PTC_CTRLD_WINSS_Msk & (_UINT32_(value) << PTC_CTRLD_WINSS_Pos)) /* Assignment of value for WINSS in the PTC_CTRLD register */
+#define PTC_CTRLD_EXTCIEN_Pos                 _UINT32_(20)                                         /* (PTC_CTRLD) External Integration Capacitor Enable Position */
+#define PTC_CTRLD_EXTCIEN_Msk                 (_UINT32_(0x3) << PTC_CTRLD_EXTCIEN_Pos)             /* (PTC_CTRLD) External Integration Capacitor Enable Mask */
+#define PTC_CTRLD_EXTCIEN(value)              (PTC_CTRLD_EXTCIEN_Msk & (_UINT32_(value) << PTC_CTRLD_EXTCIEN_Pos)) /* Assignment of value for EXTCIEN in the PTC_CTRLD register */
+#define PTC_CTRLD_POLICC_Pos                  _UINT32_(23)                                         /* (PTC_CTRLD) Polarity of Internal Compensation Capacitor Position */
+#define PTC_CTRLD_POLICC_Msk                  (_UINT32_(0x1) << PTC_CTRLD_POLICC_Pos)              /* (PTC_CTRLD) Polarity of Internal Compensation Capacitor Mask */
+#define PTC_CTRLD_POLICC(value)               (PTC_CTRLD_POLICC_Msk & (_UINT32_(value) << PTC_CTRLD_POLICC_Pos)) /* Assignment of value for POLICC in the PTC_CTRLD register */
+#define PTC_CTRLD_DSEN_Pos                    _UINT32_(24)                                         /* (PTC_CTRLD) DSEN Driven Shield Enable. Position */
+#define PTC_CTRLD_DSEN_Msk                    (_UINT32_(0x1) << PTC_CTRLD_DSEN_Pos)                /* (PTC_CTRLD) DSEN Driven Shield Enable. Mask */
+#define PTC_CTRLD_DSEN(value)                 (PTC_CTRLD_DSEN_Msk & (_UINT32_(value) << PTC_CTRLD_DSEN_Pos)) /* Assignment of value for DSEN in the PTC_CTRLD register */
+#define PTC_CTRLD_DSEQSTOP_Pos                _UINT32_(31)                                         /* (PTC_CTRLD) Stop DMA Sequence Position */
+#define PTC_CTRLD_DSEQSTOP_Msk                (_UINT32_(0x1) << PTC_CTRLD_DSEQSTOP_Pos)            /* (PTC_CTRLD) Stop DMA Sequence Mask */
+#define PTC_CTRLD_DSEQSTOP(value)             (PTC_CTRLD_DSEQSTOP_Msk & (_UINT32_(value) << PTC_CTRLD_DSEQSTOP_Pos)) /* Assignment of value for DSEQSTOP in the PTC_CTRLD register */
+#define PTC_CTRLD_Msk                         _UINT32_(0x81BF0F07)                                 /* (PTC_CTRLD) Register Mask  */
+
+
+/* -------- PTC_CTRLE : (PTC Offset: 0x18) (R/W 32) CONTROL E REGISTER -------- */
+#define PTC_CTRLE_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_CTRLE) CONTROL E REGISTER  Reset Value */
+
+#define PTC_CTRLE_AIPMPEN_Pos                 _UINT32_(4)                                          /* (PTC_CTRLE) Analog Input Charge Pump Enable Position */
+#define PTC_CTRLE_AIPMPEN_Msk                 (_UINT32_(0x1) << PTC_CTRLE_AIPMPEN_Pos)             /* (PTC_CTRLE) Analog Input Charge Pump Enable Mask */
+#define PTC_CTRLE_AIPMPEN(value)              (PTC_CTRLE_AIPMPEN_Msk & (_UINT32_(value) << PTC_CTRLE_AIPMPEN_Pos)) /* Assignment of value for AIPMPEN in the PTC_CTRLE register */
+#define PTC_CTRLE_PRSC_Pos                    _UINT32_(8)                                          /* (PTC_CTRLE) This field defines the PTC clock relative to the peripheral clock according to the table below. Position */
+#define PTC_CTRLE_PRSC_Msk                    (_UINT32_(0x7) << PTC_CTRLE_PRSC_Pos)                /* (PTC_CTRLE) This field defines the PTC clock relative to the peripheral clock according to the table below. Mask */
+#define PTC_CTRLE_PRSC(value)                 (PTC_CTRLE_PRSC_Msk & (_UINT32_(value) << PTC_CTRLE_PRSC_Pos)) /* Assignment of value for PRSC in the PTC_CTRLE register */
+#define PTC_CTRLE_WKUPEXP_Pos                 _UINT32_(12)                                         /* (PTC_CTRLE) Wake-Up Exponent Position */
+#define PTC_CTRLE_WKUPEXP_Msk                 (_UINT32_(0xF) << PTC_CTRLE_WKUPEXP_Pos)             /* (PTC_CTRLE) Wake-Up Exponent Mask */
+#define PTC_CTRLE_WKUPEXP(value)              (PTC_CTRLE_WKUPEXP_Msk & (_UINT32_(value) << PTC_CTRLE_WKUPEXP_Pos)) /* Assignment of value for WKUPEXP in the PTC_CTRLE register */
+#define PTC_CTRLE_Msk                         _UINT32_(0x0000F710)                                 /* (PTC_CTRLE) Register Mask  */
+
+
+/* -------- PTC_SWTRIG : (PTC Offset: 0x1C) (R/W 32) Software Trigger Register -------- */
+#define PTC_SWTRIG_RESETVALUE                 _UINT32_(0x00)                                       /*  (PTC_SWTRIG) Software Trigger Register  Reset Value */
+
+#define PTC_SWTRIG_STCONV_Pos                 _UINT32_(0)                                          /* (PTC_SWTRIG) Start Conversion Position */
+#define PTC_SWTRIG_STCONV_Msk                 (_UINT32_(0x1) << PTC_SWTRIG_STCONV_Pos)             /* (PTC_SWTRIG) Start Conversion Mask */
+#define PTC_SWTRIG_STCONV(value)              (PTC_SWTRIG_STCONV_Msk & (_UINT32_(value) << PTC_SWTRIG_STCONV_Pos)) /* Assignment of value for STCONV in the PTC_SWTRIG register */
+#define PTC_SWTRIG_Msk                        _UINT32_(0x00000001)                                 /* (PTC_SWTRIG) Register Mask  */
+
+
+/* -------- PTC_WINLT : (PTC Offset: 0x20) (R/W 32) Window Comparator Low Threshold Register -------- */
+#define PTC_WINLT_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_WINLT) Window Comparator Low Threshold Register  Reset Value */
+
+#define PTC_WINLT_WCLT_Pos                    _UINT32_(0)                                          /* (PTC_WINLT) Window Comparator Low Threshold Position */
+#define PTC_WINLT_WCLT_Msk                    (_UINT32_(0xFFFF) << PTC_WINLT_WCLT_Pos)             /* (PTC_WINLT) Window Comparator Low Threshold Mask */
+#define PTC_WINLT_WCLT(value)                 (PTC_WINLT_WCLT_Msk & (_UINT32_(value) << PTC_WINLT_WCLT_Pos)) /* Assignment of value for WCLT in the PTC_WINLT register */
+#define PTC_WINLT_Msk                         _UINT32_(0x0000FFFF)                                 /* (PTC_WINLT) Register Mask  */
+
+
+/* -------- PTC_WINHT : (PTC Offset: 0x24) (R/W 32) Window Comparator High Threshold Register -------- */
+#define PTC_WINHT_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_WINHT) Window Comparator High Threshold Register  Reset Value */
+
+#define PTC_WINHT_WCHT_Pos                    _UINT32_(0)                                          /* (PTC_WINHT) Window Comparator High Threshold Position */
+#define PTC_WINHT_WCHT_Msk                    (_UINT32_(0xFFFF) << PTC_WINHT_WCHT_Pos)             /* (PTC_WINHT) Window Comparator High Threshold Mask */
+#define PTC_WINHT_WCHT(value)                 (PTC_WINHT_WCHT_Msk & (_UINT32_(value) << PTC_WINHT_WCHT_Pos)) /* Assignment of value for WCHT in the PTC_WINHT register */
+#define PTC_WINHT_Msk                         _UINT32_(0x0000FFFF)                                 /* (PTC_WINHT) Register Mask  */
+
+
+/* -------- PTC_PINEN1 : (PTC Offset: 0x28) (R/W 32) PTC Line Enable 1 Register -------- */
+#define PTC_PINEN1_RESETVALUE                 _UINT32_(0x00)                                       /*  (PTC_PINEN1) PTC Line Enable 1 Register  Reset Value */
+
+#define PTC_PINEN1_PINEN_Pos                  _UINT32_(0)                                          /* (PTC_PINEN1) PTC-Line 31-0 Enable Position */
+#define PTC_PINEN1_PINEN_Msk                  (_UINT32_(0xFFFFFFFF) << PTC_PINEN1_PINEN_Pos)       /* (PTC_PINEN1) PTC-Line 31-0 Enable Mask */
+#define PTC_PINEN1_PINEN(value)               (PTC_PINEN1_PINEN_Msk & (_UINT32_(value) << PTC_PINEN1_PINEN_Pos)) /* Assignment of value for PINEN in the PTC_PINEN1 register */
+#define PTC_PINEN1_Msk                        _UINT32_(0xFFFFFFFF)                                 /* (PTC_PINEN1) Register Mask  */
+
+
+/* -------- PTC_PINEN2 : (PTC Offset: 0x2C) (R/W 32) PTC Line Enable 2 Register -------- */
+#define PTC_PINEN2_RESETVALUE                 _UINT32_(0x00)                                       /*  (PTC_PINEN2) PTC Line Enable 2 Register  Reset Value */
+
+#define PTC_PINEN2_PINEN_Pos                  _UINT32_(0)                                          /* (PTC_PINEN2) PTC-Line 63-32 Enable Position */
+#define PTC_PINEN2_PINEN_Msk                  (_UINT32_(0xF) << PTC_PINEN2_PINEN_Pos)              /* (PTC_PINEN2) PTC-Line 63-32 Enable Mask */
+#define PTC_PINEN2_PINEN(value)               (PTC_PINEN2_PINEN_Msk & (_UINT32_(value) << PTC_PINEN2_PINEN_Pos)) /* Assignment of value for PINEN in the PTC_PINEN2 register */
+#define PTC_PINEN2_Msk                        _UINT32_(0x0000000F)                                 /* (PTC_PINEN2) Register Mask  */
+
+
+/* -------- PTC_XSEL1 : (PTC Offset: 0x30) (R/W 32) X Line Selection 1 Register -------- */
+#define PTC_XSEL1_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_XSEL1) X Line Selection 1 Register  Reset Value */
+
+#define PTC_XSEL1_XSEL_Pos                    _UINT32_(0)                                          /* (PTC_XSEL1) X-Line Selection [31:0] Position */
+#define PTC_XSEL1_XSEL_Msk                    (_UINT32_(0xFFFFFFFF) << PTC_XSEL1_XSEL_Pos)         /* (PTC_XSEL1) X-Line Selection [31:0] Mask */
+#define PTC_XSEL1_XSEL(value)                 (PTC_XSEL1_XSEL_Msk & (_UINT32_(value) << PTC_XSEL1_XSEL_Pos)) /* Assignment of value for XSEL in the PTC_XSEL1 register */
+#define PTC_XSEL1_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (PTC_XSEL1) Register Mask  */
+
+
+/* -------- PTC_XSEL2 : (PTC Offset: 0x34) (R/W 32) X Line Selection 2 Register -------- */
+#define PTC_XSEL2_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_XSEL2) X Line Selection 2 Register  Reset Value */
+
+#define PTC_XSEL2_XSEL_Pos                    _UINT32_(0)                                          /* (PTC_XSEL2) X-Line Selection [63:32] Position */
+#define PTC_XSEL2_XSEL_Msk                    (_UINT32_(0xF) << PTC_XSEL2_XSEL_Pos)                /* (PTC_XSEL2) X-Line Selection [63:32] Mask */
+#define PTC_XSEL2_XSEL(value)                 (PTC_XSEL2_XSEL_Msk & (_UINT32_(value) << PTC_XSEL2_XSEL_Pos)) /* Assignment of value for XSEL in the PTC_XSEL2 register */
+#define PTC_XSEL2_Msk                         _UINT32_(0x0000000F)                                 /* (PTC_XSEL2) Register Mask  */
+
+
+/* -------- PTC_YSEL1 : (PTC Offset: 0x38) (R/W 32) Y Line Selection 1 Register -------- */
+#define PTC_YSEL1_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_YSEL1) Y Line Selection 1 Register  Reset Value */
+
+#define PTC_YSEL1_YSEL_Pos                    _UINT32_(0)                                          /* (PTC_YSEL1) Y-Line Selection [31:0] Position */
+#define PTC_YSEL1_YSEL_Msk                    (_UINT32_(0xFFFFFFFF) << PTC_YSEL1_YSEL_Pos)         /* (PTC_YSEL1) Y-Line Selection [31:0] Mask */
+#define PTC_YSEL1_YSEL(value)                 (PTC_YSEL1_YSEL_Msk & (_UINT32_(value) << PTC_YSEL1_YSEL_Pos)) /* Assignment of value for YSEL in the PTC_YSEL1 register */
+#define PTC_YSEL1_Msk                         _UINT32_(0xFFFFFFFF)                                 /* (PTC_YSEL1) Register Mask  */
+
+
+/* -------- PTC_YSEL2 : (PTC Offset: 0x3C) (R/W 32) Y Line Selection 2 Register -------- */
+#define PTC_YSEL2_RESETVALUE                  _UINT32_(0x00)                                       /*  (PTC_YSEL2) Y Line Selection 2 Register  Reset Value */
+
+#define PTC_YSEL2_YSEL_Pos                    _UINT32_(0)                                          /* (PTC_YSEL2) Y-Line Selection [63:32] Position */
+#define PTC_YSEL2_YSEL_Msk                    (_UINT32_(0xF) << PTC_YSEL2_YSEL_Pos)                /* (PTC_YSEL2) Y-Line Selection [63:32] Mask */
+#define PTC_YSEL2_YSEL(value)                 (PTC_YSEL2_YSEL_Msk & (_UINT32_(value) << PTC_YSEL2_YSEL_Pos)) /* Assignment of value for YSEL in the PTC_YSEL2 register */
+#define PTC_YSEL2_Msk                         _UINT32_(0x0000000F)                                 /* (PTC_YSEL2) Register Mask  */
+
+
+/* -------- PTC_POLCTRL1 : (PTC Offset: 0x40) (R/W 32) Polarity Control 1 Register -------- */
+#define PTC_POLCTRL1_RESETVALUE               _UINT32_(0x00)                                       /*  (PTC_POLCTRL1) Polarity Control 1 Register  Reset Value */
+
+#define PTC_POLCTRL1_POLARITY_Pos             _UINT32_(0)                                          /* (PTC_POLCTRL1) Choose X/Y lines Polarity [31:0] Position */
+#define PTC_POLCTRL1_POLARITY_Msk             (_UINT32_(0xFFFFFFFF) << PTC_POLCTRL1_POLARITY_Pos)  /* (PTC_POLCTRL1) Choose X/Y lines Polarity [31:0] Mask */
+#define PTC_POLCTRL1_POLARITY(value)          (PTC_POLCTRL1_POLARITY_Msk & (_UINT32_(value) << PTC_POLCTRL1_POLARITY_Pos)) /* Assignment of value for POLARITY in the PTC_POLCTRL1 register */
+#define PTC_POLCTRL1_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (PTC_POLCTRL1) Register Mask  */
+
+
+/* -------- PTC_POLCTRL2 : (PTC Offset: 0x44) (R/W 32) Polarity Control 2 Register -------- */
+#define PTC_POLCTRL2_RESETVALUE               _UINT32_(0x00)                                       /*  (PTC_POLCTRL2) Polarity Control 2 Register  Reset Value */
+
+#define PTC_POLCTRL2_POLARITY_Pos             _UINT32_(0)                                          /* (PTC_POLCTRL2) Choose X/Y lines Polarity [63:32] Position */
+#define PTC_POLCTRL2_POLARITY_Msk             (_UINT32_(0xF) << PTC_POLCTRL2_POLARITY_Pos)         /* (PTC_POLCTRL2) Choose X/Y lines Polarity [63:32] Mask */
+#define PTC_POLCTRL2_POLARITY(value)          (PTC_POLCTRL2_POLARITY_Msk & (_UINT32_(value) << PTC_POLCTRL2_POLARITY_Pos)) /* Assignment of value for POLARITY in the PTC_POLCTRL2 register */
+#define PTC_POLCTRL2_Msk                      _UINT32_(0x0000000F)                                 /* (PTC_POLCTRL2) Register Mask  */
+
+
+/* -------- PTC_INTENCLR : (PTC Offset: 0x48) (R/W 32) INTERRUPT ENABLE CLEAR Register -------- */
+#define PTC_INTENCLR_RESETVALUE               _UINT32_(0x00)                                       /*  (PTC_INTENCLR) INTERRUPT ENABLE CLEAR Register  Reset Value */
+
+#define PTC_INTENCLR_EOC_Pos                  _UINT32_(0)                                          /* (PTC_INTENCLR) End of Conversion Enable Clear. Position */
+#define PTC_INTENCLR_EOC_Msk                  (_UINT32_(0x1) << PTC_INTENCLR_EOC_Pos)              /* (PTC_INTENCLR) End of Conversion Enable Clear. Mask */
+#define PTC_INTENCLR_EOC(value)               (PTC_INTENCLR_EOC_Msk & (_UINT32_(value) << PTC_INTENCLR_EOC_Pos)) /* Assignment of value for EOC in the PTC_INTENCLR register */
+#define PTC_INTENCLR_WCOMP_Pos                _UINT32_(1)                                          /* (PTC_INTENCLR) Window Comparator Enable Clear. Position */
+#define PTC_INTENCLR_WCOMP_Msk                (_UINT32_(0x1) << PTC_INTENCLR_WCOMP_Pos)            /* (PTC_INTENCLR) Window Comparator Enable Clear. Mask */
+#define PTC_INTENCLR_WCOMP(value)             (PTC_INTENCLR_WCOMP_Msk & (_UINT32_(value) << PTC_INTENCLR_WCOMP_Pos)) /* Assignment of value for WCOMP in the PTC_INTENCLR register */
+#define PTC_INTENCLR_ACRRDY_Pos               _UINT32_(7)                                          /* (PTC_INTENCLR) Analog Core Ready Enable Clear. Position */
+#define PTC_INTENCLR_ACRRDY_Msk               (_UINT32_(0x1) << PTC_INTENCLR_ACRRDY_Pos)           /* (PTC_INTENCLR) Analog Core Ready Enable Clear. Mask */
+#define PTC_INTENCLR_ACRRDY(value)            (PTC_INTENCLR_ACRRDY_Msk & (_UINT32_(value) << PTC_INTENCLR_ACRRDY_Pos)) /* Assignment of value for ACRRDY in the PTC_INTENCLR register */
+#define PTC_INTENCLR_Msk                      _UINT32_(0x00000083)                                 /* (PTC_INTENCLR) Register Mask  */
+
+
+/* -------- PTC_INTENSET : (PTC Offset: 0x4C) (R/W 32) INTERRUPT ENABLE SET Register -------- */
+#define PTC_INTENSET_RESETVALUE               _UINT32_(0x00)                                       /*  (PTC_INTENSET) INTERRUPT ENABLE SET Register  Reset Value */
+
+#define PTC_INTENSET_EOC_Pos                  _UINT32_(0)                                          /* (PTC_INTENSET) End of Conversion Enable Set. Position */
+#define PTC_INTENSET_EOC_Msk                  (_UINT32_(0x1) << PTC_INTENSET_EOC_Pos)              /* (PTC_INTENSET) End of Conversion Enable Set. Mask */
+#define PTC_INTENSET_EOC(value)               (PTC_INTENSET_EOC_Msk & (_UINT32_(value) << PTC_INTENSET_EOC_Pos)) /* Assignment of value for EOC in the PTC_INTENSET register */
+#define PTC_INTENSET_WCOMP_Pos                _UINT32_(1)                                          /* (PTC_INTENSET) Window Comparator Enable Set. Position */
+#define PTC_INTENSET_WCOMP_Msk                (_UINT32_(0x1) << PTC_INTENSET_WCOMP_Pos)            /* (PTC_INTENSET) Window Comparator Enable Set. Mask */
+#define PTC_INTENSET_WCOMP(value)             (PTC_INTENSET_WCOMP_Msk & (_UINT32_(value) << PTC_INTENSET_WCOMP_Pos)) /* Assignment of value for WCOMP in the PTC_INTENSET register */
+#define PTC_INTENSET_ACRRDY_Pos               _UINT32_(7)                                          /* (PTC_INTENSET) Analog Core Ready Enable Set. Position */
+#define PTC_INTENSET_ACRRDY_Msk               (_UINT32_(0x1) << PTC_INTENSET_ACRRDY_Pos)           /* (PTC_INTENSET) Analog Core Ready Enable Set. Mask */
+#define PTC_INTENSET_ACRRDY(value)            (PTC_INTENSET_ACRRDY_Msk & (_UINT32_(value) << PTC_INTENSET_ACRRDY_Pos)) /* Assignment of value for ACRRDY in the PTC_INTENSET register */
+#define PTC_INTENSET_Msk                      _UINT32_(0x00000083)                                 /* (PTC_INTENSET) Register Mask  */
+
+
+/* -------- PTC_INTFLAGSET : (PTC Offset: 0x50) (R/W 32) INTERRUPT FLAG SET Register -------- */
+#define PTC_INTFLAGSET_RESETVALUE             _UINT32_(0x00)                                       /*  (PTC_INTFLAGSET) INTERRUPT FLAG SET Register  Reset Value */
+
+#define PTC_INTFLAGSET_EOC_Pos                _UINT32_(0)                                          /* (PTC_INTFLAGSET) End of Conversion Enable Set. Position */
+#define PTC_INTFLAGSET_EOC_Msk                (_UINT32_(0x1) << PTC_INTFLAGSET_EOC_Pos)            /* (PTC_INTFLAGSET) End of Conversion Enable Set. Mask */
+#define PTC_INTFLAGSET_EOC(value)             (PTC_INTFLAGSET_EOC_Msk & (_UINT32_(value) << PTC_INTFLAGSET_EOC_Pos)) /* Assignment of value for EOC in the PTC_INTFLAGSET register */
+#define PTC_INTFLAGSET_WCOMP_Pos              _UINT32_(1)                                          /* (PTC_INTFLAGSET) Window Comparator Enable Set. Position */
+#define PTC_INTFLAGSET_WCOMP_Msk              (_UINT32_(0x1) << PTC_INTFLAGSET_WCOMP_Pos)          /* (PTC_INTFLAGSET) Window Comparator Enable Set. Mask */
+#define PTC_INTFLAGSET_WCOMP(value)           (PTC_INTFLAGSET_WCOMP_Msk & (_UINT32_(value) << PTC_INTFLAGSET_WCOMP_Pos)) /* Assignment of value for WCOMP in the PTC_INTFLAGSET register */
+#define PTC_INTFLAGSET_ACRRDY_Pos             _UINT32_(7)                                          /* (PTC_INTFLAGSET) Analog Core Ready Enable Set. Position */
+#define PTC_INTFLAGSET_ACRRDY_Msk             (_UINT32_(0x1) << PTC_INTFLAGSET_ACRRDY_Pos)         /* (PTC_INTFLAGSET) Analog Core Ready Enable Set. Mask */
+#define PTC_INTFLAGSET_ACRRDY(value)          (PTC_INTFLAGSET_ACRRDY_Msk & (_UINT32_(value) << PTC_INTFLAGSET_ACRRDY_Pos)) /* Assignment of value for ACRRDY in the PTC_INTFLAGSET register */
+#define PTC_INTFLAGSET_Msk                    _UINT32_(0x00000083)                                 /* (PTC_INTFLAGSET) Register Mask  */
+
+
+/* -------- PTC_INTFLAG : (PTC Offset: 0x54) (R/W 32) INTERRUPT FLAG STATUS and CLEAR Register -------- */
+#define PTC_INTFLAG_RESETVALUE                _UINT32_(0x00)                                       /*  (PTC_INTFLAG) INTERRUPT FLAG STATUS and CLEAR Register  Reset Value */
+
+#define PTC_INTFLAG_EOC_Pos                   _UINT32_(0)                                          /* (PTC_INTFLAG) End of Conversion Flag Position */
+#define PTC_INTFLAG_EOC_Msk                   (_UINT32_(0x1) << PTC_INTFLAG_EOC_Pos)               /* (PTC_INTFLAG) End of Conversion Flag Mask */
+#define PTC_INTFLAG_EOC(value)                (PTC_INTFLAG_EOC_Msk & (_UINT32_(value) << PTC_INTFLAG_EOC_Pos)) /* Assignment of value for EOC in the PTC_INTFLAG register */
+#define PTC_INTFLAG_WCOMP_Pos                 _UINT32_(1)                                          /* (PTC_INTFLAG) Window Comparator Flag Position */
+#define PTC_INTFLAG_WCOMP_Msk                 (_UINT32_(0x1) << PTC_INTFLAG_WCOMP_Pos)             /* (PTC_INTFLAG) Window Comparator Flag Mask */
+#define PTC_INTFLAG_WCOMP(value)              (PTC_INTFLAG_WCOMP_Msk & (_UINT32_(value) << PTC_INTFLAG_WCOMP_Pos)) /* Assignment of value for WCOMP in the PTC_INTFLAG register */
+#define PTC_INTFLAG_ACRRDY_Pos                _UINT32_(7)                                          /* (PTC_INTFLAG) Analog Core Ready Flag Position */
+#define PTC_INTFLAG_ACRRDY_Msk                (_UINT32_(0x1) << PTC_INTFLAG_ACRRDY_Pos)            /* (PTC_INTFLAG) Analog Core Ready Flag Mask */
+#define PTC_INTFLAG_ACRRDY(value)             (PTC_INTFLAG_ACRRDY_Msk & (_UINT32_(value) << PTC_INTFLAG_ACRRDY_Pos)) /* Assignment of value for ACRRDY in the PTC_INTFLAG register */
+#define PTC_INTFLAG_Msk                       _UINT32_(0x00000083)                                 /* (PTC_INTFLAG) Register Mask  */
+
+
+/* -------- PTC_STATUS : (PTC Offset: 0x58) ( R/ 32) STATUS Register -------- */
+#define PTC_STATUS_RESETVALUE                 _UINT32_(0x00)                                       /*  (PTC_STATUS) STATUS Register  Reset Value */
+
+#define PTC_STATUS_PTCBUSY_Pos                _UINT32_(0)                                          /* (PTC_STATUS) PTC Busy Status Position */
+#define PTC_STATUS_PTCBUSY_Msk                (_UINT32_(0x1) << PTC_STATUS_PTCBUSY_Pos)            /* (PTC_STATUS) PTC Busy Status Mask */
+#define PTC_STATUS_PTCBUSY(value)             (PTC_STATUS_PTCBUSY_Msk & (_UINT32_(value) << PTC_STATUS_PTCBUSY_Pos)) /* Assignment of value for PTCBUSY in the PTC_STATUS register */
+#define PTC_STATUS_DAD_Pos                    _UINT32_(7)                                          /* (PTC_STATUS) Digital Accumulation Done Position */
+#define PTC_STATUS_DAD_Msk                    (_UINT32_(0x1) << PTC_STATUS_DAD_Pos)                /* (PTC_STATUS) Digital Accumulation Done Mask */
+#define PTC_STATUS_DAD(value)                 (PTC_STATUS_DAD_Msk & (_UINT32_(value) << PTC_STATUS_DAD_Pos)) /* Assignment of value for DAD in the PTC_STATUS register */
+#define PTC_STATUS_WCC_Pos                    _UINT32_(8)                                          /* (PTC_STATUS) Window Comparator Counter Position */
+#define PTC_STATUS_WCC_Msk                    (_UINT32_(0x7F) << PTC_STATUS_WCC_Pos)               /* (PTC_STATUS) Window Comparator Counter Mask */
+#define PTC_STATUS_WCC(value)                 (PTC_STATUS_WCC_Msk & (_UINT32_(value) << PTC_STATUS_WCC_Pos)) /* Assignment of value for WCC in the PTC_STATUS register */
+#define PTC_STATUS_Msk                        _UINT32_(0x00007F81)                                 /* (PTC_STATUS) Register Mask  */
+
+
+/* -------- PTC_SYNCBUSY : (PTC Offset: 0x5C) ( R/ 32) Synchronization Register -------- */
+#define PTC_SYNCBUSY_RESETVALUE               _UINT32_(0x00)                                       /*  (PTC_SYNCBUSY) Synchronization Register  Reset Value */
+
+#define PTC_SYNCBUSY_SWRST_Pos                _UINT32_(0)                                          /* (PTC_SYNCBUSY) SWRST Synchronization Busy --- Synchronizing Busy bit for swrst Position */
+#define PTC_SYNCBUSY_SWRST_Msk                (_UINT32_(0x1) << PTC_SYNCBUSY_SWRST_Pos)            /* (PTC_SYNCBUSY) SWRST Synchronization Busy --- Synchronizing Busy bit for swrst Mask */
+#define PTC_SYNCBUSY_SWRST(value)             (PTC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << PTC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_ENABLE_Pos               _UINT32_(1)                                          /* (PTC_SYNCBUSY) ENABLE Synchronization Busy Position */
+#define PTC_SYNCBUSY_ENABLE_Msk               (_UINT32_(0x1) << PTC_SYNCBUSY_ENABLE_Pos)           /* (PTC_SYNCBUSY) ENABLE Synchronization Busy Mask */
+#define PTC_SYNCBUSY_ENABLE(value)            (PTC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << PTC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_CTRLB_Pos                _UINT32_(2)                                          /* (PTC_SYNCBUSY) Control B Synchronization Busy Position */
+#define PTC_SYNCBUSY_CTRLB_Msk                (_UINT32_(0x1) << PTC_SYNCBUSY_CTRLB_Pos)            /* (PTC_SYNCBUSY) Control B Synchronization Busy Mask */
+#define PTC_SYNCBUSY_CTRLB(value)             (PTC_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << PTC_SYNCBUSY_CTRLB_Pos)) /* Assignment of value for CTRLB in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_CTRLC_Pos                _UINT32_(3)                                          /* (PTC_SYNCBUSY) Control C Synchronization Busy Position */
+#define PTC_SYNCBUSY_CTRLC_Msk                (_UINT32_(0x1) << PTC_SYNCBUSY_CTRLC_Pos)            /* (PTC_SYNCBUSY) Control C Synchronization Busy Mask */
+#define PTC_SYNCBUSY_CTRLC(value)             (PTC_SYNCBUSY_CTRLC_Msk & (_UINT32_(value) << PTC_SYNCBUSY_CTRLC_Pos)) /* Assignment of value for CTRLC in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_CTRLD_Pos                _UINT32_(4)                                          /* (PTC_SYNCBUSY) Control D Synchronization Busy Position */
+#define PTC_SYNCBUSY_CTRLD_Msk                (_UINT32_(0x1) << PTC_SYNCBUSY_CTRLD_Pos)            /* (PTC_SYNCBUSY) Control D Synchronization Busy Mask */
+#define PTC_SYNCBUSY_CTRLD(value)             (PTC_SYNCBUSY_CTRLD_Msk & (_UINT32_(value) << PTC_SYNCBUSY_CTRLD_Pos)) /* Assignment of value for CTRLD in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_SWTRIG_Pos               _UINT32_(5)                                          /* (PTC_SYNCBUSY) Software Trigger Synchronization Busy Position */
+#define PTC_SYNCBUSY_SWTRIG_Msk               (_UINT32_(0x1) << PTC_SYNCBUSY_SWTRIG_Pos)           /* (PTC_SYNCBUSY) Software Trigger Synchronization Busy Mask */
+#define PTC_SYNCBUSY_SWTRIG(value)            (PTC_SYNCBUSY_SWTRIG_Msk & (_UINT32_(value) << PTC_SYNCBUSY_SWTRIG_Pos)) /* Assignment of value for SWTRIG in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_WINLT_Pos                _UINT32_(6)                                          /* (PTC_SYNCBUSY) Window Comparator Low Threshold Synchronization Busy Position */
+#define PTC_SYNCBUSY_WINLT_Msk                (_UINT32_(0x1) << PTC_SYNCBUSY_WINLT_Pos)            /* (PTC_SYNCBUSY) Window Comparator Low Threshold Synchronization Busy Mask */
+#define PTC_SYNCBUSY_WINLT(value)             (PTC_SYNCBUSY_WINLT_Msk & (_UINT32_(value) << PTC_SYNCBUSY_WINLT_Pos)) /* Assignment of value for WINLT in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_WINHT_Pos                _UINT32_(7)                                          /* (PTC_SYNCBUSY) Window Comparator High Threshold Synchronization Busy Position */
+#define PTC_SYNCBUSY_WINHT_Msk                (_UINT32_(0x1) << PTC_SYNCBUSY_WINHT_Pos)            /* (PTC_SYNCBUSY) Window Comparator High Threshold Synchronization Busy Mask */
+#define PTC_SYNCBUSY_WINHT(value)             (PTC_SYNCBUSY_WINHT_Msk & (_UINT32_(value) << PTC_SYNCBUSY_WINHT_Pos)) /* Assignment of value for WINHT in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_XSEL1_Pos                _UINT32_(8)                                          /* (PTC_SYNCBUSY) X-lines Selection 1 Synchronization Busy Position */
+#define PTC_SYNCBUSY_XSEL1_Msk                (_UINT32_(0x1) << PTC_SYNCBUSY_XSEL1_Pos)            /* (PTC_SYNCBUSY) X-lines Selection 1 Synchronization Busy Mask */
+#define PTC_SYNCBUSY_XSEL1(value)             (PTC_SYNCBUSY_XSEL1_Msk & (_UINT32_(value) << PTC_SYNCBUSY_XSEL1_Pos)) /* Assignment of value for XSEL1 in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_XSEL2_Pos                _UINT32_(9)                                          /* (PTC_SYNCBUSY) X-lines Selection 2 Synchronization Busy Position */
+#define PTC_SYNCBUSY_XSEL2_Msk                (_UINT32_(0x1) << PTC_SYNCBUSY_XSEL2_Pos)            /* (PTC_SYNCBUSY) X-lines Selection 2 Synchronization Busy Mask */
+#define PTC_SYNCBUSY_XSEL2(value)             (PTC_SYNCBUSY_XSEL2_Msk & (_UINT32_(value) << PTC_SYNCBUSY_XSEL2_Pos)) /* Assignment of value for XSEL2 in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_YSEL1_Pos                _UINT32_(10)                                         /* (PTC_SYNCBUSY) Y-lines Selection 1 Synchronization Busy Position */
+#define PTC_SYNCBUSY_YSEL1_Msk                (_UINT32_(0x1) << PTC_SYNCBUSY_YSEL1_Pos)            /* (PTC_SYNCBUSY) Y-lines Selection 1 Synchronization Busy Mask */
+#define PTC_SYNCBUSY_YSEL1(value)             (PTC_SYNCBUSY_YSEL1_Msk & (_UINT32_(value) << PTC_SYNCBUSY_YSEL1_Pos)) /* Assignment of value for YSEL1 in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_YSEL2_Pos                _UINT32_(11)                                         /* (PTC_SYNCBUSY) Y-lines Selection 2 Synchronization Busy Position */
+#define PTC_SYNCBUSY_YSEL2_Msk                (_UINT32_(0x1) << PTC_SYNCBUSY_YSEL2_Pos)            /* (PTC_SYNCBUSY) Y-lines Selection 2 Synchronization Busy Mask */
+#define PTC_SYNCBUSY_YSEL2(value)             (PTC_SYNCBUSY_YSEL2_Msk & (_UINT32_(value) << PTC_SYNCBUSY_YSEL2_Pos)) /* Assignment of value for YSEL2 in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_POLCTRL1_Pos             _UINT32_(12)                                         /* (PTC_SYNCBUSY) Polarity Control 1 Synchronization Busy Position */
+#define PTC_SYNCBUSY_POLCTRL1_Msk             (_UINT32_(0x1) << PTC_SYNCBUSY_POLCTRL1_Pos)         /* (PTC_SYNCBUSY) Polarity Control 1 Synchronization Busy Mask */
+#define PTC_SYNCBUSY_POLCTRL1(value)          (PTC_SYNCBUSY_POLCTRL1_Msk & (_UINT32_(value) << PTC_SYNCBUSY_POLCTRL1_Pos)) /* Assignment of value for POLCTRL1 in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_POLCTRL2_Pos             _UINT32_(13)                                         /* (PTC_SYNCBUSY) Polarity Control 2 Synchronization Busy Position */
+#define PTC_SYNCBUSY_POLCTRL2_Msk             (_UINT32_(0x1) << PTC_SYNCBUSY_POLCTRL2_Pos)         /* (PTC_SYNCBUSY) Polarity Control 2 Synchronization Busy Mask */
+#define PTC_SYNCBUSY_POLCTRL2(value)          (PTC_SYNCBUSY_POLCTRL2_Msk & (_UINT32_(value) << PTC_SYNCBUSY_POLCTRL2_Pos)) /* Assignment of value for POLCTRL2 in the PTC_SYNCBUSY register */
+#define PTC_SYNCBUSY_Msk                      _UINT32_(0x00003FFF)                                 /* (PTC_SYNCBUSY) Register Mask  */
+
+#define PTC_SYNCBUSY_XSEL_Pos                 _UINT32_(8)                                          /* (PTC_SYNCBUSY Position) X-lines Selection x Synchronization Busy */
+#define PTC_SYNCBUSY_XSEL_Msk                 (_UINT32_(0x3) << PTC_SYNCBUSY_XSEL_Pos)             /* (PTC_SYNCBUSY Mask) XSEL */
+#define PTC_SYNCBUSY_XSEL(value)              (PTC_SYNCBUSY_XSEL_Msk & (_UINT32_(value) << PTC_SYNCBUSY_XSEL_Pos)) 
+#define PTC_SYNCBUSY_YSEL_Pos                 _UINT32_(10)                                         /* (PTC_SYNCBUSY Position) Y-lines Selection x Synchronization Busy */
+#define PTC_SYNCBUSY_YSEL_Msk                 (_UINT32_(0x3) << PTC_SYNCBUSY_YSEL_Pos)             /* (PTC_SYNCBUSY Mask) YSEL */
+#define PTC_SYNCBUSY_YSEL(value)              (PTC_SYNCBUSY_YSEL_Msk & (_UINT32_(value) << PTC_SYNCBUSY_YSEL_Pos)) 
+#define PTC_SYNCBUSY_POLCTRL_Pos              _UINT32_(12)                                         /* (PTC_SYNCBUSY Position) Polarity Control 2 Synchronization Busy */
+#define PTC_SYNCBUSY_POLCTRL_Msk              (_UINT32_(0x3) << PTC_SYNCBUSY_POLCTRL_Pos)          /* (PTC_SYNCBUSY Mask) POLCTRL */
+#define PTC_SYNCBUSY_POLCTRL(value)           (PTC_SYNCBUSY_POLCTRL_Msk & (_UINT32_(value) << PTC_SYNCBUSY_POLCTRL_Pos)) 
+
+/* -------- PTC_DSEQCTRL : (PTC Offset: 0x60) (R/W 32) DMA SEQUENCE CTRL Register -------- */
+#define PTC_DSEQCTRL_RESETVALUE               _UINT32_(0x00)                                       /*  (PTC_DSEQCTRL) DMA SEQUENCE CTRL Register  Reset Value */
+
+#define PTC_DSEQCTRL_CTRLD_Pos                _UINT32_(0)                                          /* (PTC_DSEQCTRL) Control D. Position */
+#define PTC_DSEQCTRL_CTRLD_Msk                (_UINT32_(0x1) << PTC_DSEQCTRL_CTRLD_Pos)            /* (PTC_DSEQCTRL) Control D. Mask */
+#define PTC_DSEQCTRL_CTRLD(value)             (PTC_DSEQCTRL_CTRLD_Msk & (_UINT32_(value) << PTC_DSEQCTRL_CTRLD_Pos)) /* Assignment of value for CTRLD in the PTC_DSEQCTRL register */
+#define PTC_DSEQCTRL_WINLT_Pos                _UINT32_(1)                                          /* (PTC_DSEQCTRL) Window Comparator Low Threshold Position */
+#define PTC_DSEQCTRL_WINLT_Msk                (_UINT32_(0x1) << PTC_DSEQCTRL_WINLT_Pos)            /* (PTC_DSEQCTRL) Window Comparator Low Threshold Mask */
+#define PTC_DSEQCTRL_WINLT(value)             (PTC_DSEQCTRL_WINLT_Msk & (_UINT32_(value) << PTC_DSEQCTRL_WINLT_Pos)) /* Assignment of value for WINLT in the PTC_DSEQCTRL register */
+#define PTC_DSEQCTRL_WINHT_Pos                _UINT32_(2)                                          /* (PTC_DSEQCTRL) Window Comparator High Threshold Position */
+#define PTC_DSEQCTRL_WINHT_Msk                (_UINT32_(0x1) << PTC_DSEQCTRL_WINHT_Pos)            /* (PTC_DSEQCTRL) Window Comparator High Threshold Mask */
+#define PTC_DSEQCTRL_WINHT(value)             (PTC_DSEQCTRL_WINHT_Msk & (_UINT32_(value) << PTC_DSEQCTRL_WINHT_Pos)) /* Assignment of value for WINHT in the PTC_DSEQCTRL register */
+#define PTC_DSEQCTRL_XSEL_Pos                 _UINT32_(3)                                          /* (PTC_DSEQCTRL) X-line n Selection lower/upper half word Position */
+#define PTC_DSEQCTRL_XSEL_Msk                 (_UINT32_(0xF) << PTC_DSEQCTRL_XSEL_Pos)             /* (PTC_DSEQCTRL) X-line n Selection lower/upper half word Mask */
+#define PTC_DSEQCTRL_XSEL(value)              (PTC_DSEQCTRL_XSEL_Msk & (_UINT32_(value) << PTC_DSEQCTRL_XSEL_Pos)) /* Assignment of value for XSEL in the PTC_DSEQCTRL register */
+#define PTC_DSEQCTRL_YSEL_Pos                 _UINT32_(7)                                          /* (PTC_DSEQCTRL) Y-line n Selection lower/uper half word Position */
+#define PTC_DSEQCTRL_YSEL_Msk                 (_UINT32_(0xF) << PTC_DSEQCTRL_YSEL_Pos)             /* (PTC_DSEQCTRL) Y-line n Selection lower/uper half word Mask */
+#define PTC_DSEQCTRL_YSEL(value)              (PTC_DSEQCTRL_YSEL_Msk & (_UINT32_(value) << PTC_DSEQCTRL_YSEL_Pos)) /* Assignment of value for YSEL in the PTC_DSEQCTRL register */
+#define PTC_DSEQCTRL_POL_Pos                  _UINT32_(11)                                         /* (PTC_DSEQCTRL) Polarity n lower/upper half word Position */
+#define PTC_DSEQCTRL_POL_Msk                  (_UINT32_(0xF) << PTC_DSEQCTRL_POL_Pos)              /* (PTC_DSEQCTRL) Polarity n lower/upper half word Mask */
+#define PTC_DSEQCTRL_POL(value)               (PTC_DSEQCTRL_POL_Msk & (_UINT32_(value) << PTC_DSEQCTRL_POL_Pos)) /* Assignment of value for POL in the PTC_DSEQCTRL register */
+#define PTC_DSEQCTRL_CC_Pos                   _UINT32_(15)                                         /* (PTC_DSEQCTRL) Compensation Capacitor Position */
+#define PTC_DSEQCTRL_CC_Msk                   (_UINT32_(0x1) << PTC_DSEQCTRL_CC_Pos)               /* (PTC_DSEQCTRL) Compensation Capacitor Mask */
+#define PTC_DSEQCTRL_CC(value)                (PTC_DSEQCTRL_CC_Msk & (_UINT32_(value) << PTC_DSEQCTRL_CC_Pos)) /* Assignment of value for CC in the PTC_DSEQCTRL register */
+#define PTC_DSEQCTRL_CI_Pos                   _UINT32_(16)                                         /* (PTC_DSEQCTRL) Integration Capacitor Position */
+#define PTC_DSEQCTRL_CI_Msk                   (_UINT32_(0x1) << PTC_DSEQCTRL_CI_Pos)               /* (PTC_DSEQCTRL) Integration Capacitor Mask */
+#define PTC_DSEQCTRL_CI(value)                (PTC_DSEQCTRL_CI_Msk & (_UINT32_(value) << PTC_DSEQCTRL_CI_Pos)) /* Assignment of value for CI in the PTC_DSEQCTRL register */
+#define PTC_DSEQCTRL_CSD_Pos                  _UINT32_(17)                                         /* (PTC_DSEQCTRL) Charge Share Delay Position */
+#define PTC_DSEQCTRL_CSD_Msk                  (_UINT32_(0x1) << PTC_DSEQCTRL_CSD_Pos)              /* (PTC_DSEQCTRL) Charge Share Delay Mask */
+#define PTC_DSEQCTRL_CSD(value)               (PTC_DSEQCTRL_CSD_Msk & (_UINT32_(value) << PTC_DSEQCTRL_CSD_Pos)) /* Assignment of value for CSD in the PTC_DSEQCTRL register */
+#define PTC_DSEQCTRL_AUTOSTART_Pos            _UINT32_(31)                                         /* (PTC_DSEQCTRL) PTC Auto-Start Conversion. Position */
+#define PTC_DSEQCTRL_AUTOSTART_Msk            (_UINT32_(0x1) << PTC_DSEQCTRL_AUTOSTART_Pos)        /* (PTC_DSEQCTRL) PTC Auto-Start Conversion. Mask */
+#define PTC_DSEQCTRL_AUTOSTART(value)         (PTC_DSEQCTRL_AUTOSTART_Msk & (_UINT32_(value) << PTC_DSEQCTRL_AUTOSTART_Pos)) /* Assignment of value for AUTOSTART in the PTC_DSEQCTRL register */
+#define PTC_DSEQCTRL_Msk                      _UINT32_(0x8003FFFF)                                 /* (PTC_DSEQCTRL) Register Mask  */
+
+
+/* -------- PTC_DSEQSTAT : (PTC Offset: 0x64) ( R/ 32) DMA SEQUENCE STATUS - Register -------- */
+#define PTC_DSEQSTAT_RESETVALUE               _UINT32_(0x00)                                       /*  (PTC_DSEQSTAT) DMA SEQUENCE STATUS - Register  Reset Value */
+
+#define PTC_DSEQSTAT_CTRLD_Pos                _UINT32_(0)                                          /* (PTC_DSEQSTAT) Control D. Position */
+#define PTC_DSEQSTAT_CTRLD_Msk                (_UINT32_(0x1) << PTC_DSEQSTAT_CTRLD_Pos)            /* (PTC_DSEQSTAT) Control D. Mask */
+#define PTC_DSEQSTAT_CTRLD(value)             (PTC_DSEQSTAT_CTRLD_Msk & (_UINT32_(value) << PTC_DSEQSTAT_CTRLD_Pos)) /* Assignment of value for CTRLD in the PTC_DSEQSTAT register */
+#define PTC_DSEQSTAT_WINLT_Pos                _UINT32_(1)                                          /* (PTC_DSEQSTAT) Window Comparator Low Threshold Position */
+#define PTC_DSEQSTAT_WINLT_Msk                (_UINT32_(0x1) << PTC_DSEQSTAT_WINLT_Pos)            /* (PTC_DSEQSTAT) Window Comparator Low Threshold Mask */
+#define PTC_DSEQSTAT_WINLT(value)             (PTC_DSEQSTAT_WINLT_Msk & (_UINT32_(value) << PTC_DSEQSTAT_WINLT_Pos)) /* Assignment of value for WINLT in the PTC_DSEQSTAT register */
+#define PTC_DSEQSTAT_WINHT_Pos                _UINT32_(2)                                          /* (PTC_DSEQSTAT) Window Comparator High Threshold Position */
+#define PTC_DSEQSTAT_WINHT_Msk                (_UINT32_(0x1) << PTC_DSEQSTAT_WINHT_Pos)            /* (PTC_DSEQSTAT) Window Comparator High Threshold Mask */
+#define PTC_DSEQSTAT_WINHT(value)             (PTC_DSEQSTAT_WINHT_Msk & (_UINT32_(value) << PTC_DSEQSTAT_WINHT_Pos)) /* Assignment of value for WINHT in the PTC_DSEQSTAT register */
+#define PTC_DSEQSTAT_XSEL_Pos                 _UINT32_(3)                                          /* (PTC_DSEQSTAT) X-line n  Selection lower/upper half word Position */
+#define PTC_DSEQSTAT_XSEL_Msk                 (_UINT32_(0xF) << PTC_DSEQSTAT_XSEL_Pos)             /* (PTC_DSEQSTAT) X-line n  Selection lower/upper half word Mask */
+#define PTC_DSEQSTAT_XSEL(value)              (PTC_DSEQSTAT_XSEL_Msk & (_UINT32_(value) << PTC_DSEQSTAT_XSEL_Pos)) /* Assignment of value for XSEL in the PTC_DSEQSTAT register */
+#define PTC_DSEQSTAT_YSEL_Pos                 _UINT32_(7)                                          /* (PTC_DSEQSTAT) Y-line n Selection lower/upper half word Position */
+#define PTC_DSEQSTAT_YSEL_Msk                 (_UINT32_(0xF) << PTC_DSEQSTAT_YSEL_Pos)             /* (PTC_DSEQSTAT) Y-line n Selection lower/upper half word Mask */
+#define PTC_DSEQSTAT_YSEL(value)              (PTC_DSEQSTAT_YSEL_Msk & (_UINT32_(value) << PTC_DSEQSTAT_YSEL_Pos)) /* Assignment of value for YSEL in the PTC_DSEQSTAT register */
+#define PTC_DSEQSTAT_POL_Pos                  _UINT32_(11)                                         /* (PTC_DSEQSTAT) Polarity n lower/upper half word Position */
+#define PTC_DSEQSTAT_POL_Msk                  (_UINT32_(0xF) << PTC_DSEQSTAT_POL_Pos)              /* (PTC_DSEQSTAT) Polarity n lower/upper half word Mask */
+#define PTC_DSEQSTAT_POL(value)               (PTC_DSEQSTAT_POL_Msk & (_UINT32_(value) << PTC_DSEQSTAT_POL_Pos)) /* Assignment of value for POL in the PTC_DSEQSTAT register */
+#define PTC_DSEQSTAT_CC_Pos                   _UINT32_(15)                                         /* (PTC_DSEQSTAT) Compensation Capacitor Position */
+#define PTC_DSEQSTAT_CC_Msk                   (_UINT32_(0x1) << PTC_DSEQSTAT_CC_Pos)               /* (PTC_DSEQSTAT) Compensation Capacitor Mask */
+#define PTC_DSEQSTAT_CC(value)                (PTC_DSEQSTAT_CC_Msk & (_UINT32_(value) << PTC_DSEQSTAT_CC_Pos)) /* Assignment of value for CC in the PTC_DSEQSTAT register */
+#define PTC_DSEQSTAT_CI_Pos                   _UINT32_(16)                                         /* (PTC_DSEQSTAT) Integration Capacitor Position */
+#define PTC_DSEQSTAT_CI_Msk                   (_UINT32_(0x1) << PTC_DSEQSTAT_CI_Pos)               /* (PTC_DSEQSTAT) Integration Capacitor Mask */
+#define PTC_DSEQSTAT_CI(value)                (PTC_DSEQSTAT_CI_Msk & (_UINT32_(value) << PTC_DSEQSTAT_CI_Pos)) /* Assignment of value for CI in the PTC_DSEQSTAT register */
+#define PTC_DSEQSTAT_CSD_Pos                  _UINT32_(17)                                         /* (PTC_DSEQSTAT) Charge Share Delay Position */
+#define PTC_DSEQSTAT_CSD_Msk                  (_UINT32_(0x1) << PTC_DSEQSTAT_CSD_Pos)              /* (PTC_DSEQSTAT) Charge Share Delay Mask */
+#define PTC_DSEQSTAT_CSD(value)               (PTC_DSEQSTAT_CSD_Msk & (_UINT32_(value) << PTC_DSEQSTAT_CSD_Pos)) /* Assignment of value for CSD in the PTC_DSEQSTAT register */
+#define PTC_DSEQSTAT_BUSY_Pos                 _UINT32_(31)                                         /* (PTC_DSEQSTAT) Sequencing Busy Position */
+#define PTC_DSEQSTAT_BUSY_Msk                 (_UINT32_(0x1) << PTC_DSEQSTAT_BUSY_Pos)             /* (PTC_DSEQSTAT) Sequencing Busy Mask */
+#define PTC_DSEQSTAT_BUSY(value)              (PTC_DSEQSTAT_BUSY_Msk & (_UINT32_(value) << PTC_DSEQSTAT_BUSY_Pos)) /* Assignment of value for BUSY in the PTC_DSEQSTAT register */
+#define PTC_DSEQSTAT_Msk                      _UINT32_(0x8003FFFF)                                 /* (PTC_DSEQSTAT) Register Mask  */
+
+
+/* -------- PTC_DSEQDATA : (PTC Offset: 0x68) ( /W 32) DMA SEQUENCE DATA - Register -------- */
+#define PTC_DSEQDATA_RESETVALUE               _UINT32_(0x00)                                       /*  (PTC_DSEQDATA) DMA SEQUENCE DATA - Register  Reset Value */
+
+#define PTC_DSEQDATA_DATA_Pos                 _UINT32_(0)                                          /* (PTC_DSEQDATA) DMA Sequential Data. Position */
+#define PTC_DSEQDATA_DATA_Msk                 (_UINT32_(0xFFFFFFFF) << PTC_DSEQDATA_DATA_Pos)      /* (PTC_DSEQDATA) DMA Sequential Data. Mask */
+#define PTC_DSEQDATA_DATA(value)              (PTC_DSEQDATA_DATA_Msk & (_UINT32_(value) << PTC_DSEQDATA_DATA_Pos)) /* Assignment of value for DATA in the PTC_DSEQDATA register */
+#define PTC_DSEQDATA_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (PTC_DSEQDATA) Register Mask  */
+
+
+/* -------- PTC_RESULT : (PTC Offset: 0x6C) ( R/ 32) Register -------- */
+#define PTC_RESULT_RESETVALUE                 _UINT32_(0x00)                                       /*  (PTC_RESULT) Register  Reset Value */
+
+#define PTC_RESULT_RES_Pos                    _UINT32_(0)                                          /* (PTC_RESULT) Result Conversion Value. Position */
+#define PTC_RESULT_RES_Msk                    (_UINT32_(0xFFF) << PTC_RESULT_RES_Pos)              /* (PTC_RESULT) Result Conversion Value. Mask */
+#define PTC_RESULT_RES(value)                 (PTC_RESULT_RES_Msk & (_UINT32_(value) << PTC_RESULT_RES_Pos)) /* Assignment of value for RES in the PTC_RESULT register */
+#define PTC_RESULT_ACCRES_Pos                 _UINT32_(16)                                         /* (PTC_RESULT) Accumulated Result Conversion Value. Position */
+#define PTC_RESULT_ACCRES_Msk                 (_UINT32_(0xFFFF) << PTC_RESULT_ACCRES_Pos)          /* (PTC_RESULT) Accumulated Result Conversion Value. Mask */
+#define PTC_RESULT_ACCRES(value)              (PTC_RESULT_ACCRES_Msk & (_UINT32_(value) << PTC_RESULT_ACCRES_Pos)) /* Assignment of value for ACCRES in the PTC_RESULT register */
+#define PTC_RESULT_Msk                        _UINT32_(0xFFFF0FFF)                                 /* (PTC_RESULT) Register Mask  */
+
+
+/* PTC register offsets definitions */
+#define PTC_CTRLA_REG_OFST             _UINT32_(0x00)      /* (PTC_CTRLA) CONTROL ENABLE REGISTER Offset */
+#define PTC_EVCTRL_REG_OFST            _UINT32_(0x04)      /* (PTC_EVCTRL) EVENT CONTROL REGISTER Offset */
+#define PTC_DBGCTRL_REG_OFST           _UINT32_(0x08)      /* (PTC_DBGCTRL) DEBUG CONTROL Register Offset */
+#define PTC_CTRLB_REG_OFST             _UINT32_(0x0C)      /* (PTC_CTRLB) CONTROL B Register Offset */
+#define PTC_CTRLC_REG_OFST             _UINT32_(0x10)      /* (PTC_CTRLC) CONTROL C Register Offset */
+#define PTC_CTRLD_REG_OFST             _UINT32_(0x14)      /* (PTC_CTRLD) CONTROL D Register Offset */
+#define PTC_CTRLE_REG_OFST             _UINT32_(0x18)      /* (PTC_CTRLE) CONTROL E REGISTER Offset */
+#define PTC_SWTRIG_REG_OFST            _UINT32_(0x1C)      /* (PTC_SWTRIG) Software Trigger Register Offset */
+#define PTC_WINLT_REG_OFST             _UINT32_(0x20)      /* (PTC_WINLT) Window Comparator Low Threshold Register Offset */
+#define PTC_WINHT_REG_OFST             _UINT32_(0x24)      /* (PTC_WINHT) Window Comparator High Threshold Register Offset */
+#define PTC_PINEN1_REG_OFST            _UINT32_(0x28)      /* (PTC_PINEN1) PTC Line Enable 1 Register Offset */
+#define PTC_PINEN2_REG_OFST            _UINT32_(0x2C)      /* (PTC_PINEN2) PTC Line Enable 2 Register Offset */
+#define PTC_XSEL1_REG_OFST             _UINT32_(0x30)      /* (PTC_XSEL1) X Line Selection 1 Register Offset */
+#define PTC_XSEL2_REG_OFST             _UINT32_(0x34)      /* (PTC_XSEL2) X Line Selection 2 Register Offset */
+#define PTC_YSEL1_REG_OFST             _UINT32_(0x38)      /* (PTC_YSEL1) Y Line Selection 1 Register Offset */
+#define PTC_YSEL2_REG_OFST             _UINT32_(0x3C)      /* (PTC_YSEL2) Y Line Selection 2 Register Offset */
+#define PTC_POLCTRL1_REG_OFST          _UINT32_(0x40)      /* (PTC_POLCTRL1) Polarity Control 1 Register Offset */
+#define PTC_POLCTRL2_REG_OFST          _UINT32_(0x44)      /* (PTC_POLCTRL2) Polarity Control 2 Register Offset */
+#define PTC_INTENCLR_REG_OFST          _UINT32_(0x48)      /* (PTC_INTENCLR) INTERRUPT ENABLE CLEAR Register Offset */
+#define PTC_INTENSET_REG_OFST          _UINT32_(0x4C)      /* (PTC_INTENSET) INTERRUPT ENABLE SET Register Offset */
+#define PTC_INTFLAGSET_REG_OFST        _UINT32_(0x50)      /* (PTC_INTFLAGSET) INTERRUPT FLAG SET Register Offset */
+#define PTC_INTFLAG_REG_OFST           _UINT32_(0x54)      /* (PTC_INTFLAG) INTERRUPT FLAG STATUS and CLEAR Register Offset */
+#define PTC_STATUS_REG_OFST            _UINT32_(0x58)      /* (PTC_STATUS) STATUS Register Offset */
+#define PTC_SYNCBUSY_REG_OFST          _UINT32_(0x5C)      /* (PTC_SYNCBUSY) Synchronization Register Offset */
+#define PTC_DSEQCTRL_REG_OFST          _UINT32_(0x60)      /* (PTC_DSEQCTRL) DMA SEQUENCE CTRL Register Offset */
+#define PTC_DSEQSTAT_REG_OFST          _UINT32_(0x64)      /* (PTC_DSEQSTAT) DMA SEQUENCE STATUS - Register Offset */
+#define PTC_DSEQDATA_REG_OFST          _UINT32_(0x68)      /* (PTC_DSEQDATA) DMA SEQUENCE DATA - Register Offset */
+#define PTC_RESULT_REG_OFST            _UINT32_(0x6C)      /* (PTC_RESULT) Register Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* PTC register API structure */
+typedef struct
+{  /* Polaris Peripheral Touch Controller */
+  __IO  uint32_t                       PTC_CTRLA;          /* Offset: 0x00 (R/W  32) CONTROL ENABLE REGISTER */
+  __IO  uint32_t                       PTC_EVCTRL;         /* Offset: 0x04 (R/W  32) EVENT CONTROL REGISTER */
+  __IO  uint32_t                       PTC_DBGCTRL;        /* Offset: 0x08 (R/W  32) DEBUG CONTROL Register */
+  __IO  uint32_t                       PTC_CTRLB;          /* Offset: 0x0C (R/W  32) CONTROL B Register */
+  __IO  uint32_t                       PTC_CTRLC;          /* Offset: 0x10 (R/W  32) CONTROL C Register */
+  __IO  uint32_t                       PTC_CTRLD;          /* Offset: 0x14 (R/W  32) CONTROL D Register */
+  __IO  uint32_t                       PTC_CTRLE;          /* Offset: 0x18 (R/W  32) CONTROL E REGISTER */
+  __IO  uint32_t                       PTC_SWTRIG;         /* Offset: 0x1C (R/W  32) Software Trigger Register */
+  __IO  uint32_t                       PTC_WINLT;          /* Offset: 0x20 (R/W  32) Window Comparator Low Threshold Register */
+  __IO  uint32_t                       PTC_WINHT;          /* Offset: 0x24 (R/W  32) Window Comparator High Threshold Register */
+  __IO  uint32_t                       PTC_PINEN1;         /* Offset: 0x28 (R/W  32) PTC Line Enable 1 Register */
+  __IO  uint32_t                       PTC_PINEN2;         /* Offset: 0x2C (R/W  32) PTC Line Enable 2 Register */
+  __IO  uint32_t                       PTC_XSEL1;          /* Offset: 0x30 (R/W  32) X Line Selection 1 Register */
+  __IO  uint32_t                       PTC_XSEL2;          /* Offset: 0x34 (R/W  32) X Line Selection 2 Register */
+  __IO  uint32_t                       PTC_YSEL1;          /* Offset: 0x38 (R/W  32) Y Line Selection 1 Register */
+  __IO  uint32_t                       PTC_YSEL2;          /* Offset: 0x3C (R/W  32) Y Line Selection 2 Register */
+  __IO  uint32_t                       PTC_POLCTRL1;       /* Offset: 0x40 (R/W  32) Polarity Control 1 Register */
+  __IO  uint32_t                       PTC_POLCTRL2;       /* Offset: 0x44 (R/W  32) Polarity Control 2 Register */
+  __IO  uint32_t                       PTC_INTENCLR;       /* Offset: 0x48 (R/W  32) INTERRUPT ENABLE CLEAR Register */
+  __IO  uint32_t                       PTC_INTENSET;       /* Offset: 0x4C (R/W  32) INTERRUPT ENABLE SET Register */
+  __IO  uint32_t                       PTC_INTFLAGSET;     /* Offset: 0x50 (R/W  32) INTERRUPT FLAG SET Register */
+  __IO  uint32_t                       PTC_INTFLAG;        /* Offset: 0x54 (R/W  32) INTERRUPT FLAG STATUS and CLEAR Register */
+  __I   uint32_t                       PTC_STATUS;         /* Offset: 0x58 (R/   32) STATUS Register */
+  __I   uint32_t                       PTC_SYNCBUSY;       /* Offset: 0x5C (R/   32) Synchronization Register */
+  __IO  uint32_t                       PTC_DSEQCTRL;       /* Offset: 0x60 (R/W  32) DMA SEQUENCE CTRL Register */
+  __I   uint32_t                       PTC_DSEQSTAT;       /* Offset: 0x64 (R/   32) DMA SEQUENCE STATUS - Register */
+  __O   uint32_t                       PTC_DSEQDATA;       /* Offset: 0x68 ( /W  32) DMA SEQUENCE DATA - Register */
+  __I   uint32_t                       PTC_RESULT;         /* Offset: 0x6C (R/   32) Register */
+} ptc_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_PTC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/rstc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/rstc.h
new file mode 100644
index 00000000..25828bd8
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/rstc.h
@@ -0,0 +1,105 @@
+/*
+ * Component description for RSTC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_RSTC_COMPONENT_H_
+#define _PIC32CMGC00_RSTC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR RSTC                      */
+/* ************************************************************************** */
+
+/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) ( R/ 16) Reset Cause -------- */
+#define RSTC_RCAUSE_POR_Pos                   _UINT16_(0)                                          /* (RSTC_RCAUSE) Power On Reset Position */
+#define RSTC_RCAUSE_POR_Msk                   (_UINT16_(0x1) << RSTC_RCAUSE_POR_Pos)               /* (RSTC_RCAUSE) Power On Reset Mask */
+#define RSTC_RCAUSE_POR(value)                (RSTC_RCAUSE_POR_Msk & (_UINT16_(value) << RSTC_RCAUSE_POR_Pos)) /* Assignment of value for POR in the RSTC_RCAUSE register */
+#define RSTC_RCAUSE_PORCORE_Pos               _UINT16_(1)                                          /* (RSTC_RCAUSE) Brown Out CORE Detector Reset Position */
+#define RSTC_RCAUSE_PORCORE_Msk               (_UINT16_(0x1) << RSTC_RCAUSE_PORCORE_Pos)           /* (RSTC_RCAUSE) Brown Out CORE Detector Reset Mask */
+#define RSTC_RCAUSE_PORCORE(value)            (RSTC_RCAUSE_PORCORE_Msk & (_UINT16_(value) << RSTC_RCAUSE_PORCORE_Pos)) /* Assignment of value for PORCORE in the RSTC_RCAUSE register */
+#define RSTC_RCAUSE_BORVDDREG_Pos             _UINT16_(2)                                          /* (RSTC_RCAUSE) Brown Out VDDREG Detector Reset Position */
+#define RSTC_RCAUSE_BORVDDREG_Msk             (_UINT16_(0x1) << RSTC_RCAUSE_BORVDDREG_Pos)         /* (RSTC_RCAUSE) Brown Out VDDREG Detector Reset Mask */
+#define RSTC_RCAUSE_BORVDDREG(value)          (RSTC_RCAUSE_BORVDDREG_Msk & (_UINT16_(value) << RSTC_RCAUSE_BORVDDREG_Pos)) /* Assignment of value for BORVDDREG in the RSTC_RCAUSE register */
+#define RSTC_RCAUSE_BORVDDA_Pos               _UINT16_(3)                                          /* (RSTC_RCAUSE) Brown Out VDDA Detector Reset Position */
+#define RSTC_RCAUSE_BORVDDA_Msk               (_UINT16_(0x1) << RSTC_RCAUSE_BORVDDA_Pos)           /* (RSTC_RCAUSE) Brown Out VDDA Detector Reset Mask */
+#define RSTC_RCAUSE_BORVDDA(value)            (RSTC_RCAUSE_BORVDDA_Msk & (_UINT16_(value) << RSTC_RCAUSE_BORVDDA_Pos)) /* Assignment of value for BORVDDA in the RSTC_RCAUSE register */
+#define RSTC_RCAUSE_BORVDDIO_Pos              _UINT16_(4)                                          /* (RSTC_RCAUSE) Brown Out VDDIO Detector Reset Position */
+#define RSTC_RCAUSE_BORVDDIO_Msk              (_UINT16_(0x1) << RSTC_RCAUSE_BORVDDIO_Pos)          /* (RSTC_RCAUSE) Brown Out VDDIO Detector Reset Mask */
+#define RSTC_RCAUSE_BORVDDIO(value)           (RSTC_RCAUSE_BORVDDIO_Msk & (_UINT16_(value) << RSTC_RCAUSE_BORVDDIO_Pos)) /* Assignment of value for BORVDDIO in the RSTC_RCAUSE register */
+#define RSTC_RCAUSE_EXT_Pos                   _UINT16_(5)                                          /* (RSTC_RCAUSE) External Reset Position */
+#define RSTC_RCAUSE_EXT_Msk                   (_UINT16_(0x1) << RSTC_RCAUSE_EXT_Pos)               /* (RSTC_RCAUSE) External Reset Mask */
+#define RSTC_RCAUSE_EXT(value)                (RSTC_RCAUSE_EXT_Msk & (_UINT16_(value) << RSTC_RCAUSE_EXT_Pos)) /* Assignment of value for EXT in the RSTC_RCAUSE register */
+#define RSTC_RCAUSE_WDT_Pos                   _UINT16_(6)                                          /* (RSTC_RCAUSE) Watchdog Reset Position */
+#define RSTC_RCAUSE_WDT_Msk                   (_UINT16_(0x1) << RSTC_RCAUSE_WDT_Pos)               /* (RSTC_RCAUSE) Watchdog Reset Mask */
+#define RSTC_RCAUSE_WDT(value)                (RSTC_RCAUSE_WDT_Msk & (_UINT16_(value) << RSTC_RCAUSE_WDT_Pos)) /* Assignment of value for WDT in the RSTC_RCAUSE register */
+#define RSTC_RCAUSE_SYST_Pos                  _UINT16_(7)                                          /* (RSTC_RCAUSE) System Reset Request Position */
+#define RSTC_RCAUSE_SYST_Msk                  (_UINT16_(0x1) << RSTC_RCAUSE_SYST_Pos)              /* (RSTC_RCAUSE) System Reset Request Mask */
+#define RSTC_RCAUSE_SYST(value)               (RSTC_RCAUSE_SYST_Msk & (_UINT16_(value) << RSTC_RCAUSE_SYST_Pos)) /* Assignment of value for SYST in the RSTC_RCAUSE register */
+#define RSTC_RCAUSE_BACKUP_Pos                _UINT16_(8)                                          /* (RSTC_RCAUSE) Backup Reset Position */
+#define RSTC_RCAUSE_BACKUP_Msk                (_UINT16_(0x1) << RSTC_RCAUSE_BACKUP_Pos)            /* (RSTC_RCAUSE) Backup Reset Mask */
+#define RSTC_RCAUSE_BACKUP(value)             (RSTC_RCAUSE_BACKUP_Msk & (_UINT16_(value) << RSTC_RCAUSE_BACKUP_Pos)) /* Assignment of value for BACKUP in the RSTC_RCAUSE register */
+#define RSTC_RCAUSE_LOCKUP_Pos                _UINT16_(9)                                          /* (RSTC_RCAUSE) Lockup Reset Position */
+#define RSTC_RCAUSE_LOCKUP_Msk                (_UINT16_(0x1) << RSTC_RCAUSE_LOCKUP_Pos)            /* (RSTC_RCAUSE) Lockup Reset Mask */
+#define RSTC_RCAUSE_LOCKUP(value)             (RSTC_RCAUSE_LOCKUP_Msk & (_UINT16_(value) << RSTC_RCAUSE_LOCKUP_Pos)) /* Assignment of value for LOCKUP in the RSTC_RCAUSE register */
+#define RSTC_RCAUSE_Msk                       _UINT16_(0x03FF)                                     /* (RSTC_RCAUSE) Register Mask  */
+
+
+/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) ( R/ 8) Backup Exit Source. Implemented only if RSTC_BACKUP_IMPLEMENTED=1 -------- */
+#define RSTC_BKUPEXIT_RESETVALUE              _UINT8_(0x00)                                        /*  (RSTC_BKUPEXIT) Backup Exit Source. Implemented only if RSTC_BACKUP_IMPLEMENTED=1  Reset Value */
+
+#define RSTC_BKUPEXIT_RTC_Pos                 _UINT8_(1)                                           /* (RSTC_BKUPEXIT) Real Timer Counter Interrupt Position */
+#define RSTC_BKUPEXIT_RTC_Msk                 (_UINT8_(0x1) << RSTC_BKUPEXIT_RTC_Pos)              /* (RSTC_BKUPEXIT) Real Timer Counter Interrupt Mask */
+#define RSTC_BKUPEXIT_RTC(value)              (RSTC_BKUPEXIT_RTC_Msk & (_UINT8_(value) << RSTC_BKUPEXIT_RTC_Pos)) /* Assignment of value for RTC in the RSTC_BKUPEXIT register */
+#define RSTC_BKUPEXIT_HIB0_Pos                _UINT8_(7)                                           /* (RSTC_BKUPEXIT) Hibernate Position */
+#define RSTC_BKUPEXIT_HIB0_Msk                (_UINT8_(0x1) << RSTC_BKUPEXIT_HIB0_Pos)             /* (RSTC_BKUPEXIT) Hibernate Mask */
+#define RSTC_BKUPEXIT_HIB0(value)             (RSTC_BKUPEXIT_HIB0_Msk & (_UINT8_(value) << RSTC_BKUPEXIT_HIB0_Pos)) /* Assignment of value for HIB0 in the RSTC_BKUPEXIT register */
+#define RSTC_BKUPEXIT_Msk                     _UINT8_(0x82)                                        /* (RSTC_BKUPEXIT) Register Mask  */
+
+#define RSTC_BKUPEXIT_HIB_Pos                 _UINT8_(7)                                           /* (RSTC_BKUPEXIT Position) Hibernate */
+#define RSTC_BKUPEXIT_HIB_Msk                 (_UINT8_(0x1) << RSTC_BKUPEXIT_HIB_Pos)              /* (RSTC_BKUPEXIT Mask) HIB */
+#define RSTC_BKUPEXIT_HIB(value)              (RSTC_BKUPEXIT_HIB_Msk & (_UINT8_(value) << RSTC_BKUPEXIT_HIB_Pos)) 
+
+/* -------- RSTC_DBGCTRL : (RSTC Offset: 0x04) (R/W 32) Debug Control -------- */
+#define RSTC_DBGCTRL_RESETVALUE               _UINT32_(0x00)                                       /*  (RSTC_DBGCTRL) Debug Control  Reset Value */
+
+#define RSTC_DBGCTRL_LCKUPDIS_Pos             _UINT32_(0)                                          /* (RSTC_DBGCTRL) Lockup Disable Position */
+#define RSTC_DBGCTRL_LCKUPDIS_Msk             (_UINT32_(0x1) << RSTC_DBGCTRL_LCKUPDIS_Pos)         /* (RSTC_DBGCTRL) Lockup Disable Mask */
+#define RSTC_DBGCTRL_LCKUPDIS(value)          (RSTC_DBGCTRL_LCKUPDIS_Msk & (_UINT32_(value) << RSTC_DBGCTRL_LCKUPDIS_Pos)) /* Assignment of value for LCKUPDIS in the RSTC_DBGCTRL register */
+#define RSTC_DBGCTRL_Msk                      _UINT32_(0x00000001)                                 /* (RSTC_DBGCTRL) Register Mask  */
+
+
+/* RSTC register offsets definitions */
+#define RSTC_RCAUSE_REG_OFST           _UINT32_(0x00)      /* (RSTC_RCAUSE) Reset Cause Offset */
+#define RSTC_BKUPEXIT_REG_OFST         _UINT32_(0x02)      /* (RSTC_BKUPEXIT) Backup Exit Source. Implemented only if RSTC_BACKUP_IMPLEMENTED=1 Offset */
+#define RSTC_DBGCTRL_REG_OFST          _UINT32_(0x04)      /* (RSTC_DBGCTRL) Debug Control Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* RSTC register API structure */
+typedef struct
+{  /* Reset Controller */
+  __I   uint16_t                       RSTC_RCAUSE;        /* Offset: 0x00 (R/   16) Reset Cause */
+  __I   uint8_t                        RSTC_BKUPEXIT;      /* Offset: 0x02 (R/   8) Backup Exit Source. Implemented only if RSTC_BACKUP_IMPLEMENTED=1 */
+  __I   uint8_t                        Reserved1[0x01];
+  __IO  uint32_t                       RSTC_DBGCTRL;       /* Offset: 0x04 (R/W  32) Debug Control */
+} rstc_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_RSTC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/rtc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/rtc.h
new file mode 100644
index 00000000..da44243b
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/rtc.h
@@ -0,0 +1,1727 @@
+/*
+ * Component description for RTC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_RTC_COMPONENT_H_
+#define _PIC32CMGC00_RTC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR RTC                       */
+/* ************************************************************************** */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x00) (R/W 32) MODE2_ALARM Alarm n Value -------- */
+#define RTC_MODE2_ALARM_RESETVALUE            _UINT32_(0x00)                                       /*  (RTC_MODE2_ALARM) MODE2_ALARM Alarm n Value  Reset Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos            _UINT32_(0)                                          /* (RTC_MODE2_ALARM) Second Position */
+#define RTC_MODE2_ALARM_SECOND_Msk            (_UINT32_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)       /* (RTC_MODE2_ALARM) Second Mask */
+#define RTC_MODE2_ALARM_SECOND(value)         (RTC_MODE2_ALARM_SECOND_Msk & (_UINT32_(value) << RTC_MODE2_ALARM_SECOND_Pos)) /* Assignment of value for SECOND in the RTC_MODE2_ALARM register */
+#define RTC_MODE2_ALARM_MINUTE_Pos            _UINT32_(6)                                          /* (RTC_MODE2_ALARM) Minute Position */
+#define RTC_MODE2_ALARM_MINUTE_Msk            (_UINT32_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)       /* (RTC_MODE2_ALARM) Minute Mask */
+#define RTC_MODE2_ALARM_MINUTE(value)         (RTC_MODE2_ALARM_MINUTE_Msk & (_UINT32_(value) << RTC_MODE2_ALARM_MINUTE_Pos)) /* Assignment of value for MINUTE in the RTC_MODE2_ALARM register */
+#define RTC_MODE2_ALARM_HOUR_Pos              _UINT32_(12)                                         /* (RTC_MODE2_ALARM) Hour Position */
+#define RTC_MODE2_ALARM_HOUR_Msk              (_UINT32_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)         /* (RTC_MODE2_ALARM) Hour Mask */
+#define RTC_MODE2_ALARM_HOUR(value)           (RTC_MODE2_ALARM_HOUR_Msk & (_UINT32_(value) << RTC_MODE2_ALARM_HOUR_Pos)) /* Assignment of value for HOUR in the RTC_MODE2_ALARM register */
+#define   RTC_MODE2_ALARM_HOUR_AM_Val         _UINT32_(0x0)                                        /* (RTC_MODE2_ALARM) Morning hour  */
+#define   RTC_MODE2_ALARM_HOUR_PM_Val         _UINT32_(0x10)                                       /* (RTC_MODE2_ALARM) Afternoon hour  */
+#define RTC_MODE2_ALARM_HOUR_AM               (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos) /* (RTC_MODE2_ALARM) Morning hour Position */
+#define RTC_MODE2_ALARM_HOUR_PM               (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos) /* (RTC_MODE2_ALARM) Afternoon hour Position */
+#define RTC_MODE2_ALARM_DAY_Pos               _UINT32_(17)                                         /* (RTC_MODE2_ALARM) Day Position */
+#define RTC_MODE2_ALARM_DAY_Msk               (_UINT32_(0x1F) << RTC_MODE2_ALARM_DAY_Pos)          /* (RTC_MODE2_ALARM) Day Mask */
+#define RTC_MODE2_ALARM_DAY(value)            (RTC_MODE2_ALARM_DAY_Msk & (_UINT32_(value) << RTC_MODE2_ALARM_DAY_Pos)) /* Assignment of value for DAY in the RTC_MODE2_ALARM register */
+#define RTC_MODE2_ALARM_MONTH_Pos             _UINT32_(22)                                         /* (RTC_MODE2_ALARM) Month Position */
+#define RTC_MODE2_ALARM_MONTH_Msk             (_UINT32_(0xF) << RTC_MODE2_ALARM_MONTH_Pos)         /* (RTC_MODE2_ALARM) Month Mask */
+#define RTC_MODE2_ALARM_MONTH(value)          (RTC_MODE2_ALARM_MONTH_Msk & (_UINT32_(value) << RTC_MODE2_ALARM_MONTH_Pos)) /* Assignment of value for MONTH in the RTC_MODE2_ALARM register */
+#define RTC_MODE2_ALARM_YEAR_Pos              _UINT32_(26)                                         /* (RTC_MODE2_ALARM) Year Position */
+#define RTC_MODE2_ALARM_YEAR_Msk              (_UINT32_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)         /* (RTC_MODE2_ALARM) Year Mask */
+#define RTC_MODE2_ALARM_YEAR(value)           (RTC_MODE2_ALARM_YEAR_Msk & (_UINT32_(value) << RTC_MODE2_ALARM_YEAR_Pos)) /* Assignment of value for YEAR in the RTC_MODE2_ALARM register */
+#define RTC_MODE2_ALARM_Msk                   _UINT32_(0xFFFFFFFF)                                 /* (RTC_MODE2_ALARM) Register Mask  */
+
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x04) (R/W 8) MODE2_ALARM Alarm n Mask -------- */
+#define RTC_MODE2_MASK_RESETVALUE             _UINT8_(0x00)                                        /*  (RTC_MODE2_MASK) MODE2_ALARM Alarm n Mask  Reset Value */
+
+#define RTC_MODE2_MASK_SEL_Pos                _UINT8_(0)                                           /* (RTC_MODE2_MASK) Alarm Mask Selection Position */
+#define RTC_MODE2_MASK_SEL_Msk                (_UINT8_(0x7) << RTC_MODE2_MASK_SEL_Pos)             /* (RTC_MODE2_MASK) Alarm Mask Selection Mask */
+#define RTC_MODE2_MASK_SEL(value)             (RTC_MODE2_MASK_SEL_Msk & (_UINT8_(value) << RTC_MODE2_MASK_SEL_Pos)) /* Assignment of value for SEL in the RTC_MODE2_MASK register */
+#define   RTC_MODE2_MASK_SEL_OFF_Val          _UINT8_(0x0)                                         /* (RTC_MODE2_MASK) Alarm Disabled  */
+#define   RTC_MODE2_MASK_SEL_SS_Val           _UINT8_(0x1)                                         /* (RTC_MODE2_MASK) Match seconds only  */
+#define   RTC_MODE2_MASK_SEL_MMSS_Val         _UINT8_(0x2)                                         /* (RTC_MODE2_MASK) Match seconds and minutes only  */
+#define   RTC_MODE2_MASK_SEL_HHMMSS_Val       _UINT8_(0x3)                                         /* (RTC_MODE2_MASK) Match seconds, minutes, and hours only  */
+#define   RTC_MODE2_MASK_SEL_DDHHMMSS_Val     _UINT8_(0x4)                                         /* (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only  */
+#define   RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val   _UINT8_(0x5)                                         /* (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only  */
+#define   RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _UINT8_(0x6)                                         /* (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years  */
+#define RTC_MODE2_MASK_SEL_OFF                (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos) /* (RTC_MODE2_MASK) Alarm Disabled Position */
+#define RTC_MODE2_MASK_SEL_SS                 (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos) /* (RTC_MODE2_MASK) Match seconds only Position */
+#define RTC_MODE2_MASK_SEL_MMSS               (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos) /* (RTC_MODE2_MASK) Match seconds and minutes only Position */
+#define RTC_MODE2_MASK_SEL_HHMMSS             (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) /* (RTC_MODE2_MASK) Match seconds, minutes, and hours only Position */
+#define RTC_MODE2_MASK_SEL_DDHHMMSS           (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) /* (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only Position */
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS         (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) /* (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only Position */
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS       (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) /* (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years Position */
+#define RTC_MODE2_MASK_Msk                    _UINT8_(0x07)                                        /* (RTC_MODE2_MASK) Register Mask  */
+
+
+/* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 Control A -------- */
+#define RTC_MODE0_CTRLA_RESETVALUE            _UINT16_(0x00)                                       /*  (RTC_MODE0_CTRLA) MODE0 Control A  Reset Value */
+
+#define RTC_MODE0_CTRLA_SWRST_Pos             _UINT16_(0)                                          /* (RTC_MODE0_CTRLA) Software Reset Position */
+#define RTC_MODE0_CTRLA_SWRST_Msk             (_UINT16_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)         /* (RTC_MODE0_CTRLA) Software Reset Mask */
+#define RTC_MODE0_CTRLA_SWRST(value)          (RTC_MODE0_CTRLA_SWRST_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE0_CTRLA register */
+#define RTC_MODE0_CTRLA_ENABLE_Pos            _UINT16_(1)                                          /* (RTC_MODE0_CTRLA) Enable Position */
+#define RTC_MODE0_CTRLA_ENABLE_Msk            (_UINT16_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)        /* (RTC_MODE0_CTRLA) Enable Mask */
+#define RTC_MODE0_CTRLA_ENABLE(value)         (RTC_MODE0_CTRLA_ENABLE_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE0_CTRLA register */
+#define RTC_MODE0_CTRLA_MODE_Pos              _UINT16_(2)                                          /* (RTC_MODE0_CTRLA) Operating Mode Position */
+#define RTC_MODE0_CTRLA_MODE_Msk              (_UINT16_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)          /* (RTC_MODE0_CTRLA) Operating Mode Mask */
+#define RTC_MODE0_CTRLA_MODE(value)           (RTC_MODE0_CTRLA_MODE_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the RTC_MODE0_CTRLA register */
+#define   RTC_MODE0_CTRLA_MODE_COUNT32_Val    _UINT16_(0x0)                                        /* (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter  */
+#define   RTC_MODE0_CTRLA_MODE_COUNT16_Val    _UINT16_(0x1)                                        /* (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter  */
+#define   RTC_MODE0_CTRLA_MODE_CLOCK_Val      _UINT16_(0x2)                                        /* (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar  */
+#define RTC_MODE0_CTRLA_MODE_COUNT32          (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos) /* (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter Position */
+#define RTC_MODE0_CTRLA_MODE_COUNT16          (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos) /* (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter Position */
+#define RTC_MODE0_CTRLA_MODE_CLOCK            (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos) /* (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar Position */
+#define RTC_MODE0_CTRLA_MATCHCLR_Pos          _UINT16_(7)                                          /* (RTC_MODE0_CTRLA) Clear on Match Position */
+#define RTC_MODE0_CTRLA_MATCHCLR_Msk          (_UINT16_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)      /* (RTC_MODE0_CTRLA) Clear on Match Mask */
+#define RTC_MODE0_CTRLA_MATCHCLR(value)       (RTC_MODE0_CTRLA_MATCHCLR_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_MATCHCLR_Pos)) /* Assignment of value for MATCHCLR in the RTC_MODE0_CTRLA register */
+#define RTC_MODE0_CTRLA_PRESCALER_Pos         _UINT16_(8)                                          /* (RTC_MODE0_CTRLA) Prescaler Position */
+#define RTC_MODE0_CTRLA_PRESCALER_Msk         (_UINT16_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)     /* (RTC_MODE0_CTRLA) Prescaler Mask */
+#define RTC_MODE0_CTRLA_PRESCALER(value)      (RTC_MODE0_CTRLA_PRESCALER_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the RTC_MODE0_CTRLA register */
+#define   RTC_MODE0_CTRLA_PRESCALER_OFF_Val   _UINT16_(0x0)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV1_Val  _UINT16_(0x1)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV2_Val  _UINT16_(0x2)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV4_Val  _UINT16_(0x3)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV8_Val  _UINT16_(0x4)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _UINT16_(0x5)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _UINT16_(0x6)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _UINT16_(0x7)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _UINT16_(0x8)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _UINT16_(0x9)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _UINT16_(0xA)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512  */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _UINT16_(0xB)                                        /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024  */
+#define RTC_MODE0_CTRLA_PRESCALER_OFF         (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1        (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV2        (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV4        (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV8        (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV16       (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV32       (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV64       (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV128      (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV256      (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV512      (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 Position */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1024     (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) /* (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 Position */
+#define RTC_MODE0_CTRLA_GPTRST_Pos            _UINT16_(14)                                         /* (RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable Position */
+#define RTC_MODE0_CTRLA_GPTRST_Msk            (_UINT16_(0x1) << RTC_MODE0_CTRLA_GPTRST_Pos)        /* (RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable Mask */
+#define RTC_MODE0_CTRLA_GPTRST(value)         (RTC_MODE0_CTRLA_GPTRST_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_GPTRST_Pos)) /* Assignment of value for GPTRST in the RTC_MODE0_CTRLA register */
+#define RTC_MODE0_CTRLA_COUNTSYNC_Pos         _UINT16_(15)                                         /* (RTC_MODE0_CTRLA) Count Read Synchronization Enable Position */
+#define RTC_MODE0_CTRLA_COUNTSYNC_Msk         (_UINT16_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)     /* (RTC_MODE0_CTRLA) Count Read Synchronization Enable Mask */
+#define RTC_MODE0_CTRLA_COUNTSYNC(value)      (RTC_MODE0_CTRLA_COUNTSYNC_Msk & (_UINT16_(value) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)) /* Assignment of value for COUNTSYNC in the RTC_MODE0_CTRLA register */
+#define RTC_MODE0_CTRLA_Msk                   _UINT16_(0xCF8F)                                     /* (RTC_MODE0_CTRLA) Register Mask  */
+
+
+/* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 Control A -------- */
+#define RTC_MODE1_CTRLA_RESETVALUE            _UINT16_(0x00)                                       /*  (RTC_MODE1_CTRLA) MODE1 Control A  Reset Value */
+
+#define RTC_MODE1_CTRLA_SWRST_Pos             _UINT16_(0)                                          /* (RTC_MODE1_CTRLA) Software Reset Position */
+#define RTC_MODE1_CTRLA_SWRST_Msk             (_UINT16_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos)         /* (RTC_MODE1_CTRLA) Software Reset Mask */
+#define RTC_MODE1_CTRLA_SWRST(value)          (RTC_MODE1_CTRLA_SWRST_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE1_CTRLA register */
+#define RTC_MODE1_CTRLA_ENABLE_Pos            _UINT16_(1)                                          /* (RTC_MODE1_CTRLA) Enable Position */
+#define RTC_MODE1_CTRLA_ENABLE_Msk            (_UINT16_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos)        /* (RTC_MODE1_CTRLA) Enable Mask */
+#define RTC_MODE1_CTRLA_ENABLE(value)         (RTC_MODE1_CTRLA_ENABLE_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE1_CTRLA register */
+#define RTC_MODE1_CTRLA_MODE_Pos              _UINT16_(2)                                          /* (RTC_MODE1_CTRLA) Operating Mode Position */
+#define RTC_MODE1_CTRLA_MODE_Msk              (_UINT16_(0x3) << RTC_MODE1_CTRLA_MODE_Pos)          /* (RTC_MODE1_CTRLA) Operating Mode Mask */
+#define RTC_MODE1_CTRLA_MODE(value)           (RTC_MODE1_CTRLA_MODE_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the RTC_MODE1_CTRLA register */
+#define   RTC_MODE1_CTRLA_MODE_COUNT32_Val    _UINT16_(0x0)                                        /* (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter  */
+#define   RTC_MODE1_CTRLA_MODE_COUNT16_Val    _UINT16_(0x1)                                        /* (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter  */
+#define   RTC_MODE1_CTRLA_MODE_CLOCK_Val      _UINT16_(0x2)                                        /* (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar  */
+#define RTC_MODE1_CTRLA_MODE_COUNT32          (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos) /* (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter Position */
+#define RTC_MODE1_CTRLA_MODE_COUNT16          (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos) /* (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter Position */
+#define RTC_MODE1_CTRLA_MODE_CLOCK            (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos) /* (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar Position */
+#define RTC_MODE1_CTRLA_PRESCALER_Pos         _UINT16_(8)                                          /* (RTC_MODE1_CTRLA) Prescaler Position */
+#define RTC_MODE1_CTRLA_PRESCALER_Msk         (_UINT16_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos)     /* (RTC_MODE1_CTRLA) Prescaler Mask */
+#define RTC_MODE1_CTRLA_PRESCALER(value)      (RTC_MODE1_CTRLA_PRESCALER_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the RTC_MODE1_CTRLA register */
+#define   RTC_MODE1_CTRLA_PRESCALER_OFF_Val   _UINT16_(0x0)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV1_Val  _UINT16_(0x1)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV2_Val  _UINT16_(0x2)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV4_Val  _UINT16_(0x3)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV8_Val  _UINT16_(0x4)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _UINT16_(0x5)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _UINT16_(0x6)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _UINT16_(0x7)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _UINT16_(0x8)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _UINT16_(0x9)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _UINT16_(0xA)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512  */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _UINT16_(0xB)                                        /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024  */
+#define RTC_MODE1_CTRLA_PRESCALER_OFF         (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1        (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV2        (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV4        (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV8        (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV16       (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV32       (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV64       (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV128      (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV256      (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV512      (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 Position */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1024     (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) /* (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 Position */
+#define RTC_MODE1_CTRLA_GPTRST_Pos            _UINT16_(14)                                         /* (RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable Position */
+#define RTC_MODE1_CTRLA_GPTRST_Msk            (_UINT16_(0x1) << RTC_MODE1_CTRLA_GPTRST_Pos)        /* (RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable Mask */
+#define RTC_MODE1_CTRLA_GPTRST(value)         (RTC_MODE1_CTRLA_GPTRST_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_GPTRST_Pos)) /* Assignment of value for GPTRST in the RTC_MODE1_CTRLA register */
+#define RTC_MODE1_CTRLA_COUNTSYNC_Pos         _UINT16_(15)                                         /* (RTC_MODE1_CTRLA) Count Read Synchronization Enable Position */
+#define RTC_MODE1_CTRLA_COUNTSYNC_Msk         (_UINT16_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)     /* (RTC_MODE1_CTRLA) Count Read Synchronization Enable Mask */
+#define RTC_MODE1_CTRLA_COUNTSYNC(value)      (RTC_MODE1_CTRLA_COUNTSYNC_Msk & (_UINT16_(value) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)) /* Assignment of value for COUNTSYNC in the RTC_MODE1_CTRLA register */
+#define RTC_MODE1_CTRLA_Msk                   _UINT16_(0xCF0F)                                     /* (RTC_MODE1_CTRLA) Register Mask  */
+
+
+/* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 Control A -------- */
+#define RTC_MODE2_CTRLA_RESETVALUE            _UINT16_(0x00)                                       /*  (RTC_MODE2_CTRLA) MODE2 Control A  Reset Value */
+
+#define RTC_MODE2_CTRLA_SWRST_Pos             _UINT16_(0)                                          /* (RTC_MODE2_CTRLA) Software Reset Position */
+#define RTC_MODE2_CTRLA_SWRST_Msk             (_UINT16_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos)         /* (RTC_MODE2_CTRLA) Software Reset Mask */
+#define RTC_MODE2_CTRLA_SWRST(value)          (RTC_MODE2_CTRLA_SWRST_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE2_CTRLA register */
+#define RTC_MODE2_CTRLA_ENABLE_Pos            _UINT16_(1)                                          /* (RTC_MODE2_CTRLA) Enable Position */
+#define RTC_MODE2_CTRLA_ENABLE_Msk            (_UINT16_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos)        /* (RTC_MODE2_CTRLA) Enable Mask */
+#define RTC_MODE2_CTRLA_ENABLE(value)         (RTC_MODE2_CTRLA_ENABLE_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE2_CTRLA register */
+#define RTC_MODE2_CTRLA_MODE_Pos              _UINT16_(2)                                          /* (RTC_MODE2_CTRLA) Operating Mode Position */
+#define RTC_MODE2_CTRLA_MODE_Msk              (_UINT16_(0x3) << RTC_MODE2_CTRLA_MODE_Pos)          /* (RTC_MODE2_CTRLA) Operating Mode Mask */
+#define RTC_MODE2_CTRLA_MODE(value)           (RTC_MODE2_CTRLA_MODE_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the RTC_MODE2_CTRLA register */
+#define   RTC_MODE2_CTRLA_MODE_COUNT32_Val    _UINT16_(0x0)                                        /* (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter  */
+#define   RTC_MODE2_CTRLA_MODE_COUNT16_Val    _UINT16_(0x1)                                        /* (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter  */
+#define   RTC_MODE2_CTRLA_MODE_CLOCK_Val      _UINT16_(0x2)                                        /* (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar  */
+#define RTC_MODE2_CTRLA_MODE_COUNT32          (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos) /* (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter Position */
+#define RTC_MODE2_CTRLA_MODE_COUNT16          (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos) /* (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter Position */
+#define RTC_MODE2_CTRLA_MODE_CLOCK            (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos) /* (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar Position */
+#define RTC_MODE2_CTRLA_CLKREP_Pos            _UINT16_(6)                                          /* (RTC_MODE2_CTRLA) Clock Representation Position */
+#define RTC_MODE2_CTRLA_CLKREP_Msk            (_UINT16_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos)        /* (RTC_MODE2_CTRLA) Clock Representation Mask */
+#define RTC_MODE2_CTRLA_CLKREP(value)         (RTC_MODE2_CTRLA_CLKREP_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_CLKREP_Pos)) /* Assignment of value for CLKREP in the RTC_MODE2_CTRLA register */
+#define RTC_MODE2_CTRLA_MATCHCLR_Pos          _UINT16_(7)                                          /* (RTC_MODE2_CTRLA) Clear on Match Position */
+#define RTC_MODE2_CTRLA_MATCHCLR_Msk          (_UINT16_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos)      /* (RTC_MODE2_CTRLA) Clear on Match Mask */
+#define RTC_MODE2_CTRLA_MATCHCLR(value)       (RTC_MODE2_CTRLA_MATCHCLR_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_MATCHCLR_Pos)) /* Assignment of value for MATCHCLR in the RTC_MODE2_CTRLA register */
+#define RTC_MODE2_CTRLA_PRESCALER_Pos         _UINT16_(8)                                          /* (RTC_MODE2_CTRLA) Prescaler Position */
+#define RTC_MODE2_CTRLA_PRESCALER_Msk         (_UINT16_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos)     /* (RTC_MODE2_CTRLA) Prescaler Mask */
+#define RTC_MODE2_CTRLA_PRESCALER(value)      (RTC_MODE2_CTRLA_PRESCALER_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the RTC_MODE2_CTRLA register */
+#define   RTC_MODE2_CTRLA_PRESCALER_OFF_Val   _UINT16_(0x0)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV1_Val  _UINT16_(0x1)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV2_Val  _UINT16_(0x2)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV4_Val  _UINT16_(0x3)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV8_Val  _UINT16_(0x4)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _UINT16_(0x5)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _UINT16_(0x6)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _UINT16_(0x7)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _UINT16_(0x8)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _UINT16_(0x9)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _UINT16_(0xA)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512  */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _UINT16_(0xB)                                        /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024  */
+#define RTC_MODE2_CTRLA_PRESCALER_OFF         (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1        (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV2        (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV4        (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV8        (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV16       (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV32       (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV64       (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV128      (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV256      (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV512      (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 Position */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1024     (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) /* (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 Position */
+#define RTC_MODE2_CTRLA_GPTRST_Pos            _UINT16_(14)                                         /* (RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable Position */
+#define RTC_MODE2_CTRLA_GPTRST_Msk            (_UINT16_(0x1) << RTC_MODE2_CTRLA_GPTRST_Pos)        /* (RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable Mask */
+#define RTC_MODE2_CTRLA_GPTRST(value)         (RTC_MODE2_CTRLA_GPTRST_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_GPTRST_Pos)) /* Assignment of value for GPTRST in the RTC_MODE2_CTRLA register */
+#define RTC_MODE2_CTRLA_CLOCKSYNC_Pos         _UINT16_(15)                                         /* (RTC_MODE2_CTRLA) Clock Read Synchronization Enable Position */
+#define RTC_MODE2_CTRLA_CLOCKSYNC_Msk         (_UINT16_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)     /* (RTC_MODE2_CTRLA) Clock Read Synchronization Enable Mask */
+#define RTC_MODE2_CTRLA_CLOCKSYNC(value)      (RTC_MODE2_CTRLA_CLOCKSYNC_Msk & (_UINT16_(value) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)) /* Assignment of value for CLOCKSYNC in the RTC_MODE2_CTRLA register */
+#define RTC_MODE2_CTRLA_Msk                   _UINT16_(0xCFCF)                                     /* (RTC_MODE2_CTRLA) Register Mask  */
+
+
+/* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 Control B -------- */
+#define RTC_MODE0_CTRLB_RESETVALUE            _UINT16_(0x00)                                       /*  (RTC_MODE0_CTRLB) MODE0 Control B  Reset Value */
+
+#define RTC_MODE0_CTRLB_GP0EN_Pos             _UINT16_(0)                                          /* (RTC_MODE0_CTRLB) General Purpose 0 Enable Position */
+#define RTC_MODE0_CTRLB_GP0EN_Msk             (_UINT16_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos)         /* (RTC_MODE0_CTRLB) General Purpose 0 Enable Mask */
+#define RTC_MODE0_CTRLB_GP0EN(value)          (RTC_MODE0_CTRLB_GP0EN_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_GP0EN_Pos)) /* Assignment of value for GP0EN in the RTC_MODE0_CTRLB register */
+#define RTC_MODE0_CTRLB_GP2EN_Pos             _UINT16_(1)                                          /* (RTC_MODE0_CTRLB) General Purpose 2 Enable Position */
+#define RTC_MODE0_CTRLB_GP2EN_Msk             (_UINT16_(0x1) << RTC_MODE0_CTRLB_GP2EN_Pos)         /* (RTC_MODE0_CTRLB) General Purpose 2 Enable Mask */
+#define RTC_MODE0_CTRLB_GP2EN(value)          (RTC_MODE0_CTRLB_GP2EN_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_GP2EN_Pos)) /* Assignment of value for GP2EN in the RTC_MODE0_CTRLB register */
+#define RTC_MODE0_CTRLB_DEBMAJ_Pos            _UINT16_(4)                                          /* (RTC_MODE0_CTRLB) Debouncer Majority Enable Position */
+#define RTC_MODE0_CTRLB_DEBMAJ_Msk            (_UINT16_(0x1) << RTC_MODE0_CTRLB_DEBMAJ_Pos)        /* (RTC_MODE0_CTRLB) Debouncer Majority Enable Mask */
+#define RTC_MODE0_CTRLB_DEBMAJ(value)         (RTC_MODE0_CTRLB_DEBMAJ_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_DEBMAJ_Pos)) /* Assignment of value for DEBMAJ in the RTC_MODE0_CTRLB register */
+#define RTC_MODE0_CTRLB_DEBASYNC_Pos          _UINT16_(5)                                          /* (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable Position */
+#define RTC_MODE0_CTRLB_DEBASYNC_Msk          (_UINT16_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos)      /* (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable Mask */
+#define RTC_MODE0_CTRLB_DEBASYNC(value)       (RTC_MODE0_CTRLB_DEBASYNC_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_DEBASYNC_Pos)) /* Assignment of value for DEBASYNC in the RTC_MODE0_CTRLB register */
+#define RTC_MODE0_CTRLB_RTCOUT_Pos            _UINT16_(6)                                          /* (RTC_MODE0_CTRLB) RTC Output Enable Position */
+#define RTC_MODE0_CTRLB_RTCOUT_Msk            (_UINT16_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos)        /* (RTC_MODE0_CTRLB) RTC Output Enable Mask */
+#define RTC_MODE0_CTRLB_RTCOUT(value)         (RTC_MODE0_CTRLB_RTCOUT_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_RTCOUT_Pos)) /* Assignment of value for RTCOUT in the RTC_MODE0_CTRLB register */
+#define RTC_MODE0_CTRLB_DMAEN_Pos             _UINT16_(7)                                          /* (RTC_MODE0_CTRLB) DMA Enable Position */
+#define RTC_MODE0_CTRLB_DMAEN_Msk             (_UINT16_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos)         /* (RTC_MODE0_CTRLB) DMA Enable Mask */
+#define RTC_MODE0_CTRLB_DMAEN(value)          (RTC_MODE0_CTRLB_DMAEN_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_DMAEN_Pos)) /* Assignment of value for DMAEN in the RTC_MODE0_CTRLB register */
+#define RTC_MODE0_CTRLB_DEBF_Pos              _UINT16_(8)                                          /* (RTC_MODE0_CTRLB) Debounce Frequency Position */
+#define RTC_MODE0_CTRLB_DEBF_Msk              (_UINT16_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos)          /* (RTC_MODE0_CTRLB) Debounce Frequency Mask */
+#define RTC_MODE0_CTRLB_DEBF(value)           (RTC_MODE0_CTRLB_DEBF_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_DEBF_Pos)) /* Assignment of value for DEBF in the RTC_MODE0_CTRLB register */
+#define   RTC_MODE0_CTRLB_DEBF_DIV2_Val       _UINT16_(0x0)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2  */
+#define   RTC_MODE0_CTRLB_DEBF_DIV4_Val       _UINT16_(0x1)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4  */
+#define   RTC_MODE0_CTRLB_DEBF_DIV8_Val       _UINT16_(0x2)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8  */
+#define   RTC_MODE0_CTRLB_DEBF_DIV16_Val      _UINT16_(0x3)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16  */
+#define   RTC_MODE0_CTRLB_DEBF_DIV32_Val      _UINT16_(0x4)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32  */
+#define   RTC_MODE0_CTRLB_DEBF_DIV64_Val      _UINT16_(0x5)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64  */
+#define   RTC_MODE0_CTRLB_DEBF_DIV128_Val     _UINT16_(0x6)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128  */
+#define   RTC_MODE0_CTRLB_DEBF_DIV256_Val     _UINT16_(0x7)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256  */
+#define RTC_MODE0_CTRLB_DEBF_DIV2             (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2 Position */
+#define RTC_MODE0_CTRLB_DEBF_DIV4             (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4 Position */
+#define RTC_MODE0_CTRLB_DEBF_DIV8             (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8 Position */
+#define RTC_MODE0_CTRLB_DEBF_DIV16            (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16 Position */
+#define RTC_MODE0_CTRLB_DEBF_DIV32            (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32 Position */
+#define RTC_MODE0_CTRLB_DEBF_DIV64            (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64 Position */
+#define RTC_MODE0_CTRLB_DEBF_DIV128           (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128 Position */
+#define RTC_MODE0_CTRLB_DEBF_DIV256           (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256 Position */
+#define RTC_MODE0_CTRLB_ACTF_Pos              _UINT16_(12)                                         /* (RTC_MODE0_CTRLB) Active Layer Frequency Position */
+#define RTC_MODE0_CTRLB_ACTF_Msk              (_UINT16_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos)          /* (RTC_MODE0_CTRLB) Active Layer Frequency Mask */
+#define RTC_MODE0_CTRLB_ACTF(value)           (RTC_MODE0_CTRLB_ACTF_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_ACTF_Pos)) /* Assignment of value for ACTF in the RTC_MODE0_CTRLB register */
+#define   RTC_MODE0_CTRLB_ACTF_DIV2_Val       _UINT16_(0x0)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2  */
+#define   RTC_MODE0_CTRLB_ACTF_DIV4_Val       _UINT16_(0x1)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4  */
+#define   RTC_MODE0_CTRLB_ACTF_DIV8_Val       _UINT16_(0x2)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8  */
+#define   RTC_MODE0_CTRLB_ACTF_DIV16_Val      _UINT16_(0x3)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16  */
+#define   RTC_MODE0_CTRLB_ACTF_DIV32_Val      _UINT16_(0x4)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32  */
+#define   RTC_MODE0_CTRLB_ACTF_DIV64_Val      _UINT16_(0x5)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64  */
+#define   RTC_MODE0_CTRLB_ACTF_DIV128_Val     _UINT16_(0x6)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128  */
+#define   RTC_MODE0_CTRLB_ACTF_DIV256_Val     _UINT16_(0x7)                                        /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256  */
+#define RTC_MODE0_CTRLB_ACTF_DIV2             (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2 Position */
+#define RTC_MODE0_CTRLB_ACTF_DIV4             (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4 Position */
+#define RTC_MODE0_CTRLB_ACTF_DIV8             (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8 Position */
+#define RTC_MODE0_CTRLB_ACTF_DIV16            (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16 Position */
+#define RTC_MODE0_CTRLB_ACTF_DIV32            (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32 Position */
+#define RTC_MODE0_CTRLB_ACTF_DIV64            (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64 Position */
+#define RTC_MODE0_CTRLB_ACTF_DIV128           (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128 Position */
+#define RTC_MODE0_CTRLB_ACTF_DIV256           (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos) /* (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256 Position */
+#define RTC_MODE0_CTRLB_SEPTO_Pos             _UINT16_(15)                                         /* (RTC_MODE0_CTRLB) Separate Tamper Outputs Position */
+#define RTC_MODE0_CTRLB_SEPTO_Msk             (_UINT16_(0x1) << RTC_MODE0_CTRLB_SEPTO_Pos)         /* (RTC_MODE0_CTRLB) Separate Tamper Outputs Mask */
+#define RTC_MODE0_CTRLB_SEPTO(value)          (RTC_MODE0_CTRLB_SEPTO_Msk & (_UINT16_(value) << RTC_MODE0_CTRLB_SEPTO_Pos)) /* Assignment of value for SEPTO in the RTC_MODE0_CTRLB register */
+#define RTC_MODE0_CTRLB_Msk                   _UINT16_(0xF7F3)                                     /* (RTC_MODE0_CTRLB) Register Mask  */
+
+
+/* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 Control B -------- */
+#define RTC_MODE1_CTRLB_RESETVALUE            _UINT16_(0x00)                                       /*  (RTC_MODE1_CTRLB) MODE1 Control B  Reset Value */
+
+#define RTC_MODE1_CTRLB_GP0EN_Pos             _UINT16_(0)                                          /* (RTC_MODE1_CTRLB) General Purpose 0 Enable Position */
+#define RTC_MODE1_CTRLB_GP0EN_Msk             (_UINT16_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos)         /* (RTC_MODE1_CTRLB) General Purpose 0 Enable Mask */
+#define RTC_MODE1_CTRLB_GP0EN(value)          (RTC_MODE1_CTRLB_GP0EN_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_GP0EN_Pos)) /* Assignment of value for GP0EN in the RTC_MODE1_CTRLB register */
+#define RTC_MODE1_CTRLB_GP2EN_Pos             _UINT16_(1)                                          /* (RTC_MODE1_CTRLB) General Purpose 2 Enable Position */
+#define RTC_MODE1_CTRLB_GP2EN_Msk             (_UINT16_(0x1) << RTC_MODE1_CTRLB_GP2EN_Pos)         /* (RTC_MODE1_CTRLB) General Purpose 2 Enable Mask */
+#define RTC_MODE1_CTRLB_GP2EN(value)          (RTC_MODE1_CTRLB_GP2EN_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_GP2EN_Pos)) /* Assignment of value for GP2EN in the RTC_MODE1_CTRLB register */
+#define RTC_MODE1_CTRLB_DEBMAJ_Pos            _UINT16_(4)                                          /* (RTC_MODE1_CTRLB) Debouncer Majority Enable Position */
+#define RTC_MODE1_CTRLB_DEBMAJ_Msk            (_UINT16_(0x1) << RTC_MODE1_CTRLB_DEBMAJ_Pos)        /* (RTC_MODE1_CTRLB) Debouncer Majority Enable Mask */
+#define RTC_MODE1_CTRLB_DEBMAJ(value)         (RTC_MODE1_CTRLB_DEBMAJ_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_DEBMAJ_Pos)) /* Assignment of value for DEBMAJ in the RTC_MODE1_CTRLB register */
+#define RTC_MODE1_CTRLB_DEBASYNC_Pos          _UINT16_(5)                                          /* (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable Position */
+#define RTC_MODE1_CTRLB_DEBASYNC_Msk          (_UINT16_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos)      /* (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable Mask */
+#define RTC_MODE1_CTRLB_DEBASYNC(value)       (RTC_MODE1_CTRLB_DEBASYNC_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_DEBASYNC_Pos)) /* Assignment of value for DEBASYNC in the RTC_MODE1_CTRLB register */
+#define RTC_MODE1_CTRLB_RTCOUT_Pos            _UINT16_(6)                                          /* (RTC_MODE1_CTRLB) RTC Output Enable Position */
+#define RTC_MODE1_CTRLB_RTCOUT_Msk            (_UINT16_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos)        /* (RTC_MODE1_CTRLB) RTC Output Enable Mask */
+#define RTC_MODE1_CTRLB_RTCOUT(value)         (RTC_MODE1_CTRLB_RTCOUT_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_RTCOUT_Pos)) /* Assignment of value for RTCOUT in the RTC_MODE1_CTRLB register */
+#define RTC_MODE1_CTRLB_DMAEN_Pos             _UINT16_(7)                                          /* (RTC_MODE1_CTRLB) DMA Enable Position */
+#define RTC_MODE1_CTRLB_DMAEN_Msk             (_UINT16_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos)         /* (RTC_MODE1_CTRLB) DMA Enable Mask */
+#define RTC_MODE1_CTRLB_DMAEN(value)          (RTC_MODE1_CTRLB_DMAEN_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_DMAEN_Pos)) /* Assignment of value for DMAEN in the RTC_MODE1_CTRLB register */
+#define RTC_MODE1_CTRLB_DEBF_Pos              _UINT16_(8)                                          /* (RTC_MODE1_CTRLB) Debounce Frequency Position */
+#define RTC_MODE1_CTRLB_DEBF_Msk              (_UINT16_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos)          /* (RTC_MODE1_CTRLB) Debounce Frequency Mask */
+#define RTC_MODE1_CTRLB_DEBF(value)           (RTC_MODE1_CTRLB_DEBF_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_DEBF_Pos)) /* Assignment of value for DEBF in the RTC_MODE1_CTRLB register */
+#define   RTC_MODE1_CTRLB_DEBF_DIV2_Val       _UINT16_(0x0)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2  */
+#define   RTC_MODE1_CTRLB_DEBF_DIV4_Val       _UINT16_(0x1)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4  */
+#define   RTC_MODE1_CTRLB_DEBF_DIV8_Val       _UINT16_(0x2)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8  */
+#define   RTC_MODE1_CTRLB_DEBF_DIV16_Val      _UINT16_(0x3)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16  */
+#define   RTC_MODE1_CTRLB_DEBF_DIV32_Val      _UINT16_(0x4)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32  */
+#define   RTC_MODE1_CTRLB_DEBF_DIV64_Val      _UINT16_(0x5)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64  */
+#define   RTC_MODE1_CTRLB_DEBF_DIV128_Val     _UINT16_(0x6)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128  */
+#define   RTC_MODE1_CTRLB_DEBF_DIV256_Val     _UINT16_(0x7)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256  */
+#define RTC_MODE1_CTRLB_DEBF_DIV2             (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2 Position */
+#define RTC_MODE1_CTRLB_DEBF_DIV4             (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4 Position */
+#define RTC_MODE1_CTRLB_DEBF_DIV8             (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8 Position */
+#define RTC_MODE1_CTRLB_DEBF_DIV16            (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16 Position */
+#define RTC_MODE1_CTRLB_DEBF_DIV32            (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32 Position */
+#define RTC_MODE1_CTRLB_DEBF_DIV64            (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64 Position */
+#define RTC_MODE1_CTRLB_DEBF_DIV128           (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128 Position */
+#define RTC_MODE1_CTRLB_DEBF_DIV256           (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256 Position */
+#define RTC_MODE1_CTRLB_ACTF_Pos              _UINT16_(12)                                         /* (RTC_MODE1_CTRLB) Active Layer Frequency Position */
+#define RTC_MODE1_CTRLB_ACTF_Msk              (_UINT16_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos)          /* (RTC_MODE1_CTRLB) Active Layer Frequency Mask */
+#define RTC_MODE1_CTRLB_ACTF(value)           (RTC_MODE1_CTRLB_ACTF_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_ACTF_Pos)) /* Assignment of value for ACTF in the RTC_MODE1_CTRLB register */
+#define   RTC_MODE1_CTRLB_ACTF_DIV2_Val       _UINT16_(0x0)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2  */
+#define   RTC_MODE1_CTRLB_ACTF_DIV4_Val       _UINT16_(0x1)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4  */
+#define   RTC_MODE1_CTRLB_ACTF_DIV8_Val       _UINT16_(0x2)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8  */
+#define   RTC_MODE1_CTRLB_ACTF_DIV16_Val      _UINT16_(0x3)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16  */
+#define   RTC_MODE1_CTRLB_ACTF_DIV32_Val      _UINT16_(0x4)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32  */
+#define   RTC_MODE1_CTRLB_ACTF_DIV64_Val      _UINT16_(0x5)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64  */
+#define   RTC_MODE1_CTRLB_ACTF_DIV128_Val     _UINT16_(0x6)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128  */
+#define   RTC_MODE1_CTRLB_ACTF_DIV256_Val     _UINT16_(0x7)                                        /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256  */
+#define RTC_MODE1_CTRLB_ACTF_DIV2             (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2 Position */
+#define RTC_MODE1_CTRLB_ACTF_DIV4             (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4 Position */
+#define RTC_MODE1_CTRLB_ACTF_DIV8             (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8 Position */
+#define RTC_MODE1_CTRLB_ACTF_DIV16            (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16 Position */
+#define RTC_MODE1_CTRLB_ACTF_DIV32            (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32 Position */
+#define RTC_MODE1_CTRLB_ACTF_DIV64            (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64 Position */
+#define RTC_MODE1_CTRLB_ACTF_DIV128           (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128 Position */
+#define RTC_MODE1_CTRLB_ACTF_DIV256           (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos) /* (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256 Position */
+#define RTC_MODE1_CTRLB_SEPTO_Pos             _UINT16_(15)                                         /* (RTC_MODE1_CTRLB) Separate Tamper Outputs Position */
+#define RTC_MODE1_CTRLB_SEPTO_Msk             (_UINT16_(0x1) << RTC_MODE1_CTRLB_SEPTO_Pos)         /* (RTC_MODE1_CTRLB) Separate Tamper Outputs Mask */
+#define RTC_MODE1_CTRLB_SEPTO(value)          (RTC_MODE1_CTRLB_SEPTO_Msk & (_UINT16_(value) << RTC_MODE1_CTRLB_SEPTO_Pos)) /* Assignment of value for SEPTO in the RTC_MODE1_CTRLB register */
+#define RTC_MODE1_CTRLB_Msk                   _UINT16_(0xF7F3)                                     /* (RTC_MODE1_CTRLB) Register Mask  */
+
+
+/* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 Control B -------- */
+#define RTC_MODE2_CTRLB_RESETVALUE            _UINT16_(0x00)                                       /*  (RTC_MODE2_CTRLB) MODE2 Control B  Reset Value */
+
+#define RTC_MODE2_CTRLB_GP0EN_Pos             _UINT16_(0)                                          /* (RTC_MODE2_CTRLB) General Purpose 0 Enable Position */
+#define RTC_MODE2_CTRLB_GP0EN_Msk             (_UINT16_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos)         /* (RTC_MODE2_CTRLB) General Purpose 0 Enable Mask */
+#define RTC_MODE2_CTRLB_GP0EN(value)          (RTC_MODE2_CTRLB_GP0EN_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_GP0EN_Pos)) /* Assignment of value for GP0EN in the RTC_MODE2_CTRLB register */
+#define RTC_MODE2_CTRLB_GP2EN_Pos             _UINT16_(1)                                          /* (RTC_MODE2_CTRLB) General Purpose 2 Enable Position */
+#define RTC_MODE2_CTRLB_GP2EN_Msk             (_UINT16_(0x1) << RTC_MODE2_CTRLB_GP2EN_Pos)         /* (RTC_MODE2_CTRLB) General Purpose 2 Enable Mask */
+#define RTC_MODE2_CTRLB_GP2EN(value)          (RTC_MODE2_CTRLB_GP2EN_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_GP2EN_Pos)) /* Assignment of value for GP2EN in the RTC_MODE2_CTRLB register */
+#define RTC_MODE2_CTRLB_DEBMAJ_Pos            _UINT16_(4)                                          /* (RTC_MODE2_CTRLB) Debouncer Majority Enable Position */
+#define RTC_MODE2_CTRLB_DEBMAJ_Msk            (_UINT16_(0x1) << RTC_MODE2_CTRLB_DEBMAJ_Pos)        /* (RTC_MODE2_CTRLB) Debouncer Majority Enable Mask */
+#define RTC_MODE2_CTRLB_DEBMAJ(value)         (RTC_MODE2_CTRLB_DEBMAJ_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_DEBMAJ_Pos)) /* Assignment of value for DEBMAJ in the RTC_MODE2_CTRLB register */
+#define RTC_MODE2_CTRLB_DEBASYNC_Pos          _UINT16_(5)                                          /* (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable Position */
+#define RTC_MODE2_CTRLB_DEBASYNC_Msk          (_UINT16_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos)      /* (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable Mask */
+#define RTC_MODE2_CTRLB_DEBASYNC(value)       (RTC_MODE2_CTRLB_DEBASYNC_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_DEBASYNC_Pos)) /* Assignment of value for DEBASYNC in the RTC_MODE2_CTRLB register */
+#define RTC_MODE2_CTRLB_RTCOUT_Pos            _UINT16_(6)                                          /* (RTC_MODE2_CTRLB) RTC Output Enable Position */
+#define RTC_MODE2_CTRLB_RTCOUT_Msk            (_UINT16_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos)        /* (RTC_MODE2_CTRLB) RTC Output Enable Mask */
+#define RTC_MODE2_CTRLB_RTCOUT(value)         (RTC_MODE2_CTRLB_RTCOUT_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_RTCOUT_Pos)) /* Assignment of value for RTCOUT in the RTC_MODE2_CTRLB register */
+#define RTC_MODE2_CTRLB_DMAEN_Pos             _UINT16_(7)                                          /* (RTC_MODE2_CTRLB) DMA Enable Position */
+#define RTC_MODE2_CTRLB_DMAEN_Msk             (_UINT16_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos)         /* (RTC_MODE2_CTRLB) DMA Enable Mask */
+#define RTC_MODE2_CTRLB_DMAEN(value)          (RTC_MODE2_CTRLB_DMAEN_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_DMAEN_Pos)) /* Assignment of value for DMAEN in the RTC_MODE2_CTRLB register */
+#define RTC_MODE2_CTRLB_DEBF_Pos              _UINT16_(8)                                          /* (RTC_MODE2_CTRLB) Debounce Frequency Position */
+#define RTC_MODE2_CTRLB_DEBF_Msk              (_UINT16_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos)          /* (RTC_MODE2_CTRLB) Debounce Frequency Mask */
+#define RTC_MODE2_CTRLB_DEBF(value)           (RTC_MODE2_CTRLB_DEBF_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_DEBF_Pos)) /* Assignment of value for DEBF in the RTC_MODE2_CTRLB register */
+#define   RTC_MODE2_CTRLB_DEBF_DIV2_Val       _UINT16_(0x0)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2  */
+#define   RTC_MODE2_CTRLB_DEBF_DIV4_Val       _UINT16_(0x1)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4  */
+#define   RTC_MODE2_CTRLB_DEBF_DIV8_Val       _UINT16_(0x2)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8  */
+#define   RTC_MODE2_CTRLB_DEBF_DIV16_Val      _UINT16_(0x3)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16  */
+#define   RTC_MODE2_CTRLB_DEBF_DIV32_Val      _UINT16_(0x4)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32  */
+#define   RTC_MODE2_CTRLB_DEBF_DIV64_Val      _UINT16_(0x5)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64  */
+#define   RTC_MODE2_CTRLB_DEBF_DIV128_Val     _UINT16_(0x6)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128  */
+#define   RTC_MODE2_CTRLB_DEBF_DIV256_Val     _UINT16_(0x7)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256  */
+#define RTC_MODE2_CTRLB_DEBF_DIV2             (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2 Position */
+#define RTC_MODE2_CTRLB_DEBF_DIV4             (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4 Position */
+#define RTC_MODE2_CTRLB_DEBF_DIV8             (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8 Position */
+#define RTC_MODE2_CTRLB_DEBF_DIV16            (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16 Position */
+#define RTC_MODE2_CTRLB_DEBF_DIV32            (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32 Position */
+#define RTC_MODE2_CTRLB_DEBF_DIV64            (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64 Position */
+#define RTC_MODE2_CTRLB_DEBF_DIV128           (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128 Position */
+#define RTC_MODE2_CTRLB_DEBF_DIV256           (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256 Position */
+#define RTC_MODE2_CTRLB_ACTF_Pos              _UINT16_(12)                                         /* (RTC_MODE2_CTRLB) Active Layer Frequency Position */
+#define RTC_MODE2_CTRLB_ACTF_Msk              (_UINT16_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos)          /* (RTC_MODE2_CTRLB) Active Layer Frequency Mask */
+#define RTC_MODE2_CTRLB_ACTF(value)           (RTC_MODE2_CTRLB_ACTF_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_ACTF_Pos)) /* Assignment of value for ACTF in the RTC_MODE2_CTRLB register */
+#define   RTC_MODE2_CTRLB_ACTF_DIV2_Val       _UINT16_(0x0)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2  */
+#define   RTC_MODE2_CTRLB_ACTF_DIV4_Val       _UINT16_(0x1)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4  */
+#define   RTC_MODE2_CTRLB_ACTF_DIV8_Val       _UINT16_(0x2)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8  */
+#define   RTC_MODE2_CTRLB_ACTF_DIV16_Val      _UINT16_(0x3)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16  */
+#define   RTC_MODE2_CTRLB_ACTF_DIV32_Val      _UINT16_(0x4)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32  */
+#define   RTC_MODE2_CTRLB_ACTF_DIV64_Val      _UINT16_(0x5)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64  */
+#define   RTC_MODE2_CTRLB_ACTF_DIV128_Val     _UINT16_(0x6)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128  */
+#define   RTC_MODE2_CTRLB_ACTF_DIV256_Val     _UINT16_(0x7)                                        /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256  */
+#define RTC_MODE2_CTRLB_ACTF_DIV2             (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2 Position */
+#define RTC_MODE2_CTRLB_ACTF_DIV4             (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4 Position */
+#define RTC_MODE2_CTRLB_ACTF_DIV8             (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8 Position */
+#define RTC_MODE2_CTRLB_ACTF_DIV16            (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16 Position */
+#define RTC_MODE2_CTRLB_ACTF_DIV32            (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32 Position */
+#define RTC_MODE2_CTRLB_ACTF_DIV64            (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64 Position */
+#define RTC_MODE2_CTRLB_ACTF_DIV128           (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128 Position */
+#define RTC_MODE2_CTRLB_ACTF_DIV256           (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos) /* (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256 Position */
+#define RTC_MODE2_CTRLB_SEPTO_Pos             _UINT16_(15)                                         /* (RTC_MODE2_CTRLB) Separate Tamper Outputs Position */
+#define RTC_MODE2_CTRLB_SEPTO_Msk             (_UINT16_(0x1) << RTC_MODE2_CTRLB_SEPTO_Pos)         /* (RTC_MODE2_CTRLB) Separate Tamper Outputs Mask */
+#define RTC_MODE2_CTRLB_SEPTO(value)          (RTC_MODE2_CTRLB_SEPTO_Msk & (_UINT16_(value) << RTC_MODE2_CTRLB_SEPTO_Pos)) /* Assignment of value for SEPTO in the RTC_MODE2_CTRLB register */
+#define RTC_MODE2_CTRLB_Msk                   _UINT16_(0xF7F3)                                     /* (RTC_MODE2_CTRLB) Register Mask  */
+
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 Event Control -------- */
+#define RTC_MODE0_EVCTRL_RESETVALUE           _UINT32_(0x00)                                       /*  (RTC_MODE0_EVCTRL) MODE0 Event Control  Reset Value */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos           _UINT32_(0)                                          /* (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_PEREO0_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO0_Pos)       /* (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_PEREO0(value)        (RTC_MODE0_EVCTRL_PEREO0_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO0_Pos)) /* Assignment of value for PEREO0 in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_PEREO1_Pos           _UINT32_(1)                                          /* (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_PEREO1_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO1_Pos)       /* (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_PEREO1(value)        (RTC_MODE0_EVCTRL_PEREO1_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO1_Pos)) /* Assignment of value for PEREO1 in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_PEREO2_Pos           _UINT32_(2)                                          /* (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_PEREO2_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO2_Pos)       /* (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_PEREO2(value)        (RTC_MODE0_EVCTRL_PEREO2_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO2_Pos)) /* Assignment of value for PEREO2 in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_PEREO3_Pos           _UINT32_(3)                                          /* (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_PEREO3_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO3_Pos)       /* (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_PEREO3(value)        (RTC_MODE0_EVCTRL_PEREO3_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO3_Pos)) /* Assignment of value for PEREO3 in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_PEREO4_Pos           _UINT32_(4)                                          /* (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_PEREO4_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO4_Pos)       /* (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_PEREO4(value)        (RTC_MODE0_EVCTRL_PEREO4_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO4_Pos)) /* Assignment of value for PEREO4 in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_PEREO5_Pos           _UINT32_(5)                                          /* (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_PEREO5_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO5_Pos)       /* (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_PEREO5(value)        (RTC_MODE0_EVCTRL_PEREO5_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO5_Pos)) /* Assignment of value for PEREO5 in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_PEREO6_Pos           _UINT32_(6)                                          /* (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_PEREO6_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO6_Pos)       /* (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_PEREO6(value)        (RTC_MODE0_EVCTRL_PEREO6_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO6_Pos)) /* Assignment of value for PEREO6 in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_PEREO7_Pos           _UINT32_(7)                                          /* (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_PEREO7_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PEREO7_Pos)       /* (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_PEREO7(value)        (RTC_MODE0_EVCTRL_PEREO7_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO7_Pos)) /* Assignment of value for PEREO7 in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos           _UINT32_(8)                                          /* (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_CMPEO0_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_CMPEO0_Pos)       /* (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_CMPEO0(value)        (RTC_MODE0_EVCTRL_CMPEO0_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_CMPEO0_Pos)) /* Assignment of value for CMPEO0 in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_CMPEO1_Pos           _UINT32_(9)                                          /* (RTC_MODE0_EVCTRL) Compare 1 Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_CMPEO1_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_CMPEO1_Pos)       /* (RTC_MODE0_EVCTRL) Compare 1 Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_CMPEO1(value)        (RTC_MODE0_EVCTRL_CMPEO1_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_CMPEO1_Pos)) /* Assignment of value for CMPEO1 in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_TAMPEREO_Pos         _UINT32_(14)                                         /* (RTC_MODE0_EVCTRL) Tamper Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_TAMPEREO_Msk         (_UINT32_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)     /* (RTC_MODE0_EVCTRL) Tamper Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_TAMPEREO(value)      (RTC_MODE0_EVCTRL_TAMPEREO_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)) /* Assignment of value for TAMPEREO in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_OVFEO_Pos            _UINT32_(15)                                         /* (RTC_MODE0_EVCTRL) Overflow Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_OVFEO_Msk            (_UINT32_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)        /* (RTC_MODE0_EVCTRL) Overflow Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_OVFEO(value)         (RTC_MODE0_EVCTRL_OVFEO_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_OVFEO_Pos)) /* Assignment of value for OVFEO in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_TAMPEVEI_Pos         _UINT32_(16)                                         /* (RTC_MODE0_EVCTRL) Tamper Event Input Enable Position */
+#define RTC_MODE0_EVCTRL_TAMPEVEI_Msk         (_UINT32_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)     /* (RTC_MODE0_EVCTRL) Tamper Event Input Enable Mask */
+#define RTC_MODE0_EVCTRL_TAMPEVEI(value)      (RTC_MODE0_EVCTRL_TAMPEVEI_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)) /* Assignment of value for TAMPEVEI in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_PERDEO_Pos           _UINT32_(24)                                         /* (RTC_MODE0_EVCTRL) Periodic Interval Daily Event Output Enable Position */
+#define RTC_MODE0_EVCTRL_PERDEO_Msk           (_UINT32_(0x1) << RTC_MODE0_EVCTRL_PERDEO_Pos)       /* (RTC_MODE0_EVCTRL) Periodic Interval Daily Event Output Enable Mask */
+#define RTC_MODE0_EVCTRL_PERDEO(value)        (RTC_MODE0_EVCTRL_PERDEO_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PERDEO_Pos)) /* Assignment of value for PERDEO in the RTC_MODE0_EVCTRL register */
+#define RTC_MODE0_EVCTRL_Msk                  _UINT32_(0x0101C3FF)                                 /* (RTC_MODE0_EVCTRL) Register Mask  */
+
+#define RTC_MODE0_EVCTRL_PEREO_Pos            _UINT32_(0)                                          /* (RTC_MODE0_EVCTRL Position) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk            (_UINT32_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)       /* (RTC_MODE0_EVCTRL Mask) PEREO */
+#define RTC_MODE0_EVCTRL_PEREO(value)         (RTC_MODE0_EVCTRL_PEREO_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_PEREO_Pos)) 
+#define RTC_MODE0_EVCTRL_CMPEO_Pos            _UINT32_(8)                                          /* (RTC_MODE0_EVCTRL Position) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk            (_UINT32_(0x3) << RTC_MODE0_EVCTRL_CMPEO_Pos)        /* (RTC_MODE0_EVCTRL Mask) CMPEO */
+#define RTC_MODE0_EVCTRL_CMPEO(value)         (RTC_MODE0_EVCTRL_CMPEO_Msk & (_UINT32_(value) << RTC_MODE0_EVCTRL_CMPEO_Pos)) 
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 Event Control -------- */
+#define RTC_MODE1_EVCTRL_RESETVALUE           _UINT32_(0x00)                                       /*  (RTC_MODE1_EVCTRL) MODE1 Event Control  Reset Value */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos           _UINT32_(0)                                          /* (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_PEREO0_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO0_Pos)       /* (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_PEREO0(value)        (RTC_MODE1_EVCTRL_PEREO0_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO0_Pos)) /* Assignment of value for PEREO0 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_PEREO1_Pos           _UINT32_(1)                                          /* (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_PEREO1_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO1_Pos)       /* (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_PEREO1(value)        (RTC_MODE1_EVCTRL_PEREO1_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO1_Pos)) /* Assignment of value for PEREO1 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_PEREO2_Pos           _UINT32_(2)                                          /* (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_PEREO2_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO2_Pos)       /* (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_PEREO2(value)        (RTC_MODE1_EVCTRL_PEREO2_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO2_Pos)) /* Assignment of value for PEREO2 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_PEREO3_Pos           _UINT32_(3)                                          /* (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_PEREO3_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO3_Pos)       /* (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_PEREO3(value)        (RTC_MODE1_EVCTRL_PEREO3_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO3_Pos)) /* Assignment of value for PEREO3 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_PEREO4_Pos           _UINT32_(4)                                          /* (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_PEREO4_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO4_Pos)       /* (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_PEREO4(value)        (RTC_MODE1_EVCTRL_PEREO4_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO4_Pos)) /* Assignment of value for PEREO4 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_PEREO5_Pos           _UINT32_(5)                                          /* (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_PEREO5_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO5_Pos)       /* (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_PEREO5(value)        (RTC_MODE1_EVCTRL_PEREO5_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO5_Pos)) /* Assignment of value for PEREO5 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_PEREO6_Pos           _UINT32_(6)                                          /* (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_PEREO6_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO6_Pos)       /* (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_PEREO6(value)        (RTC_MODE1_EVCTRL_PEREO6_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO6_Pos)) /* Assignment of value for PEREO6 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_PEREO7_Pos           _UINT32_(7)                                          /* (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_PEREO7_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PEREO7_Pos)       /* (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_PEREO7(value)        (RTC_MODE1_EVCTRL_PEREO7_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO7_Pos)) /* Assignment of value for PEREO7 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos           _UINT32_(8)                                          /* (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_CMPEO0_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_CMPEO0_Pos)       /* (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_CMPEO0(value)        (RTC_MODE1_EVCTRL_CMPEO0_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_CMPEO0_Pos)) /* Assignment of value for CMPEO0 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos           _UINT32_(9)                                          /* (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_CMPEO1_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_CMPEO1_Pos)       /* (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_CMPEO1(value)        (RTC_MODE1_EVCTRL_CMPEO1_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_CMPEO1_Pos)) /* Assignment of value for CMPEO1 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_CMPEO2_Pos           _UINT32_(10)                                         /* (RTC_MODE1_EVCTRL) Compare 2 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_CMPEO2_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_CMPEO2_Pos)       /* (RTC_MODE1_EVCTRL) Compare 2 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_CMPEO2(value)        (RTC_MODE1_EVCTRL_CMPEO2_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_CMPEO2_Pos)) /* Assignment of value for CMPEO2 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_CMPEO3_Pos           _UINT32_(11)                                         /* (RTC_MODE1_EVCTRL) Compare 3 Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_CMPEO3_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_CMPEO3_Pos)       /* (RTC_MODE1_EVCTRL) Compare 3 Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_CMPEO3(value)        (RTC_MODE1_EVCTRL_CMPEO3_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_CMPEO3_Pos)) /* Assignment of value for CMPEO3 in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_TAMPEREO_Pos         _UINT32_(14)                                         /* (RTC_MODE1_EVCTRL) Tamper Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_TAMPEREO_Msk         (_UINT32_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)     /* (RTC_MODE1_EVCTRL) Tamper Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_TAMPEREO(value)      (RTC_MODE1_EVCTRL_TAMPEREO_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)) /* Assignment of value for TAMPEREO in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_OVFEO_Pos            _UINT32_(15)                                         /* (RTC_MODE1_EVCTRL) Overflow Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_OVFEO_Msk            (_UINT32_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)        /* (RTC_MODE1_EVCTRL) Overflow Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_OVFEO(value)         (RTC_MODE1_EVCTRL_OVFEO_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_OVFEO_Pos)) /* Assignment of value for OVFEO in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_TAMPEVEI_Pos         _UINT32_(16)                                         /* (RTC_MODE1_EVCTRL) Tamper Event Input Enable Position */
+#define RTC_MODE1_EVCTRL_TAMPEVEI_Msk         (_UINT32_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)     /* (RTC_MODE1_EVCTRL) Tamper Event Input Enable Mask */
+#define RTC_MODE1_EVCTRL_TAMPEVEI(value)      (RTC_MODE1_EVCTRL_TAMPEVEI_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)) /* Assignment of value for TAMPEVEI in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_PERDEO_Pos           _UINT32_(24)                                         /* (RTC_MODE1_EVCTRL) Periodic Interval Daily Event Output Enable Position */
+#define RTC_MODE1_EVCTRL_PERDEO_Msk           (_UINT32_(0x1) << RTC_MODE1_EVCTRL_PERDEO_Pos)       /* (RTC_MODE1_EVCTRL) Periodic Interval Daily Event Output Enable Mask */
+#define RTC_MODE1_EVCTRL_PERDEO(value)        (RTC_MODE1_EVCTRL_PERDEO_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PERDEO_Pos)) /* Assignment of value for PERDEO in the RTC_MODE1_EVCTRL register */
+#define RTC_MODE1_EVCTRL_Msk                  _UINT32_(0x0101CFFF)                                 /* (RTC_MODE1_EVCTRL) Register Mask  */
+
+#define RTC_MODE1_EVCTRL_PEREO_Pos            _UINT32_(0)                                          /* (RTC_MODE1_EVCTRL Position) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk            (_UINT32_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)       /* (RTC_MODE1_EVCTRL Mask) PEREO */
+#define RTC_MODE1_EVCTRL_PEREO(value)         (RTC_MODE1_EVCTRL_PEREO_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_PEREO_Pos)) 
+#define RTC_MODE1_EVCTRL_CMPEO_Pos            _UINT32_(8)                                          /* (RTC_MODE1_EVCTRL Position) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk            (_UINT32_(0xF) << RTC_MODE1_EVCTRL_CMPEO_Pos)        /* (RTC_MODE1_EVCTRL Mask) CMPEO */
+#define RTC_MODE1_EVCTRL_CMPEO(value)         (RTC_MODE1_EVCTRL_CMPEO_Msk & (_UINT32_(value) << RTC_MODE1_EVCTRL_CMPEO_Pos)) 
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 Event Control -------- */
+#define RTC_MODE2_EVCTRL_RESETVALUE           _UINT32_(0x00)                                       /*  (RTC_MODE2_EVCTRL) MODE2 Event Control  Reset Value */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos           _UINT32_(0)                                          /* (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_PEREO0_Msk           (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO0_Pos)       /* (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_PEREO0(value)        (RTC_MODE2_EVCTRL_PEREO0_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO0_Pos)) /* Assignment of value for PEREO0 in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_PEREO1_Pos           _UINT32_(1)                                          /* (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_PEREO1_Msk           (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO1_Pos)       /* (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_PEREO1(value)        (RTC_MODE2_EVCTRL_PEREO1_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO1_Pos)) /* Assignment of value for PEREO1 in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_PEREO2_Pos           _UINT32_(2)                                          /* (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_PEREO2_Msk           (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO2_Pos)       /* (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_PEREO2(value)        (RTC_MODE2_EVCTRL_PEREO2_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO2_Pos)) /* Assignment of value for PEREO2 in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_PEREO3_Pos           _UINT32_(3)                                          /* (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_PEREO3_Msk           (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO3_Pos)       /* (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_PEREO3(value)        (RTC_MODE2_EVCTRL_PEREO3_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO3_Pos)) /* Assignment of value for PEREO3 in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_PEREO4_Pos           _UINT32_(4)                                          /* (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_PEREO4_Msk           (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO4_Pos)       /* (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_PEREO4(value)        (RTC_MODE2_EVCTRL_PEREO4_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO4_Pos)) /* Assignment of value for PEREO4 in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_PEREO5_Pos           _UINT32_(5)                                          /* (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_PEREO5_Msk           (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO5_Pos)       /* (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_PEREO5(value)        (RTC_MODE2_EVCTRL_PEREO5_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO5_Pos)) /* Assignment of value for PEREO5 in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_PEREO6_Pos           _UINT32_(6)                                          /* (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_PEREO6_Msk           (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO6_Pos)       /* (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_PEREO6(value)        (RTC_MODE2_EVCTRL_PEREO6_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO6_Pos)) /* Assignment of value for PEREO6 in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_PEREO7_Pos           _UINT32_(7)                                          /* (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_PEREO7_Msk           (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PEREO7_Pos)       /* (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_PEREO7(value)        (RTC_MODE2_EVCTRL_PEREO7_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO7_Pos)) /* Assignment of value for PEREO7 in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos         _UINT32_(8)                                          /* (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_ALARMEO0_Msk         (_UINT32_(0x1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)     /* (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_ALARMEO0(value)      (RTC_MODE2_EVCTRL_ALARMEO0_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)) /* Assignment of value for ALARMEO0 in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_ALARMEO1_Pos         _UINT32_(9)                                          /* (RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_ALARMEO1_Msk         (_UINT32_(0x1) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)     /* (RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_ALARMEO1(value)      (RTC_MODE2_EVCTRL_ALARMEO1_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)) /* Assignment of value for ALARMEO1 in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_TAMPEREO_Pos         _UINT32_(14)                                         /* (RTC_MODE2_EVCTRL) Tamper Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_TAMPEREO_Msk         (_UINT32_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)     /* (RTC_MODE2_EVCTRL) Tamper Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_TAMPEREO(value)      (RTC_MODE2_EVCTRL_TAMPEREO_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)) /* Assignment of value for TAMPEREO in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_OVFEO_Pos            _UINT32_(15)                                         /* (RTC_MODE2_EVCTRL) Overflow Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_OVFEO_Msk            (_UINT32_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)        /* (RTC_MODE2_EVCTRL) Overflow Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_OVFEO(value)         (RTC_MODE2_EVCTRL_OVFEO_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_OVFEO_Pos)) /* Assignment of value for OVFEO in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_TAMPEVEI_Pos         _UINT32_(16)                                         /* (RTC_MODE2_EVCTRL) Tamper Event Input Enable Position */
+#define RTC_MODE2_EVCTRL_TAMPEVEI_Msk         (_UINT32_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)     /* (RTC_MODE2_EVCTRL) Tamper Event Input Enable Mask */
+#define RTC_MODE2_EVCTRL_TAMPEVEI(value)      (RTC_MODE2_EVCTRL_TAMPEVEI_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)) /* Assignment of value for TAMPEVEI in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_PERDEO_Pos           _UINT32_(24)                                         /* (RTC_MODE2_EVCTRL) Periodic Interval Daily Event Output Enable Position */
+#define RTC_MODE2_EVCTRL_PERDEO_Msk           (_UINT32_(0x1) << RTC_MODE2_EVCTRL_PERDEO_Pos)       /* (RTC_MODE2_EVCTRL) Periodic Interval Daily Event Output Enable Mask */
+#define RTC_MODE2_EVCTRL_PERDEO(value)        (RTC_MODE2_EVCTRL_PERDEO_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PERDEO_Pos)) /* Assignment of value for PERDEO in the RTC_MODE2_EVCTRL register */
+#define RTC_MODE2_EVCTRL_Msk                  _UINT32_(0x0101C3FF)                                 /* (RTC_MODE2_EVCTRL) Register Mask  */
+
+#define RTC_MODE2_EVCTRL_PEREO_Pos            _UINT32_(0)                                          /* (RTC_MODE2_EVCTRL Position) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk            (_UINT32_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)       /* (RTC_MODE2_EVCTRL Mask) PEREO */
+#define RTC_MODE2_EVCTRL_PEREO(value)         (RTC_MODE2_EVCTRL_PEREO_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_PEREO_Pos)) 
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos          _UINT32_(8)                                          /* (RTC_MODE2_EVCTRL Position) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk          (_UINT32_(0x3) << RTC_MODE2_EVCTRL_ALARMEO_Pos)      /* (RTC_MODE2_EVCTRL Mask) ALARMEO */
+#define RTC_MODE2_EVCTRL_ALARMEO(value)       (RTC_MODE2_EVCTRL_ALARMEO_Msk & (_UINT32_(value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)) 
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 Interrupt Enable Clear -------- */
+#define RTC_MODE0_INTENCLR_RESETVALUE         _UINT16_(0x00)                                       /*  (RTC_MODE0_INTENCLR) MODE0 Interrupt Enable Clear  Reset Value */
+
+#define RTC_MODE0_INTENCLR_PER0_Pos           _UINT16_(0)                                          /* (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_PER0_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER0_Pos)       /* (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_PER0(value)        (RTC_MODE0_INTENCLR_PER0_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_PER1_Pos           _UINT16_(1)                                          /* (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_PER1_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER1_Pos)       /* (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_PER1(value)        (RTC_MODE0_INTENCLR_PER1_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_PER2_Pos           _UINT16_(2)                                          /* (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_PER2_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER2_Pos)       /* (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_PER2(value)        (RTC_MODE0_INTENCLR_PER2_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_PER3_Pos           _UINT16_(3)                                          /* (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_PER3_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER3_Pos)       /* (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_PER3(value)        (RTC_MODE0_INTENCLR_PER3_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_PER4_Pos           _UINT16_(4)                                          /* (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_PER4_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER4_Pos)       /* (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_PER4(value)        (RTC_MODE0_INTENCLR_PER4_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_PER5_Pos           _UINT16_(5)                                          /* (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_PER5_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER5_Pos)       /* (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_PER5(value)        (RTC_MODE0_INTENCLR_PER5_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_PER6_Pos           _UINT16_(6)                                          /* (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_PER6_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER6_Pos)       /* (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_PER6(value)        (RTC_MODE0_INTENCLR_PER6_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_PER7_Pos           _UINT16_(7)                                          /* (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_PER7_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENCLR_PER7_Pos)       /* (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_PER7(value)        (RTC_MODE0_INTENCLR_PER7_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_CMP0_Pos           _UINT16_(8)                                          /* (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_CMP0_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENCLR_CMP0_Pos)       /* (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_CMP0(value)        (RTC_MODE0_INTENCLR_CMP0_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_CMP1_Pos           _UINT16_(9)                                          /* (RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_CMP1_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENCLR_CMP1_Pos)       /* (RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_CMP1(value)        (RTC_MODE0_INTENCLR_CMP1_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_TAMPER_Pos         _UINT16_(14)                                         /* (RTC_MODE0_INTENCLR) Tamper Enable Position */
+#define RTC_MODE0_INTENCLR_TAMPER_Msk         (_UINT16_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos)     /* (RTC_MODE0_INTENCLR) Tamper Enable Mask */
+#define RTC_MODE0_INTENCLR_TAMPER(value)      (RTC_MODE0_INTENCLR_TAMPER_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_OVF_Pos            _UINT16_(15)                                         /* (RTC_MODE0_INTENCLR) Overflow Interrupt Enable Position */
+#define RTC_MODE0_INTENCLR_OVF_Msk            (_UINT16_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)        /* (RTC_MODE0_INTENCLR) Overflow Interrupt Enable Mask */
+#define RTC_MODE0_INTENCLR_OVF(value)         (RTC_MODE0_INTENCLR_OVF_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE0_INTENCLR register */
+#define RTC_MODE0_INTENCLR_Msk                _UINT16_(0xC3FF)                                     /* (RTC_MODE0_INTENCLR) Register Mask  */
+
+#define RTC_MODE0_INTENCLR_PER_Pos            _UINT16_(0)                                          /* (RTC_MODE0_INTENCLR Position) Periodic Interval x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER_Msk            (_UINT16_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos)       /* (RTC_MODE0_INTENCLR Mask) PER */
+#define RTC_MODE0_INTENCLR_PER(value)         (RTC_MODE0_INTENCLR_PER_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_PER_Pos)) 
+#define RTC_MODE0_INTENCLR_CMP_Pos            _UINT16_(8)                                          /* (RTC_MODE0_INTENCLR Position) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk            (_UINT16_(0x3) << RTC_MODE0_INTENCLR_CMP_Pos)        /* (RTC_MODE0_INTENCLR Mask) CMP */
+#define RTC_MODE0_INTENCLR_CMP(value)         (RTC_MODE0_INTENCLR_CMP_Msk & (_UINT16_(value) << RTC_MODE0_INTENCLR_CMP_Pos)) 
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 Interrupt Enable Clear -------- */
+#define RTC_MODE1_INTENCLR_RESETVALUE         _UINT16_(0x00)                                       /*  (RTC_MODE1_INTENCLR) MODE1 Interrupt Enable Clear  Reset Value */
+
+#define RTC_MODE1_INTENCLR_PER0_Pos           _UINT16_(0)                                          /* (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_PER0_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER0_Pos)       /* (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_PER0(value)        (RTC_MODE1_INTENCLR_PER0_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_PER1_Pos           _UINT16_(1)                                          /* (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_PER1_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER1_Pos)       /* (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_PER1(value)        (RTC_MODE1_INTENCLR_PER1_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_PER2_Pos           _UINT16_(2)                                          /* (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_PER2_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER2_Pos)       /* (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_PER2(value)        (RTC_MODE1_INTENCLR_PER2_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_PER3_Pos           _UINT16_(3)                                          /* (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_PER3_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER3_Pos)       /* (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_PER3(value)        (RTC_MODE1_INTENCLR_PER3_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_PER4_Pos           _UINT16_(4)                                          /* (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_PER4_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER4_Pos)       /* (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_PER4(value)        (RTC_MODE1_INTENCLR_PER4_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_PER5_Pos           _UINT16_(5)                                          /* (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_PER5_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER5_Pos)       /* (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_PER5(value)        (RTC_MODE1_INTENCLR_PER5_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_PER6_Pos           _UINT16_(6)                                          /* (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_PER6_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER6_Pos)       /* (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_PER6(value)        (RTC_MODE1_INTENCLR_PER6_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_PER7_Pos           _UINT16_(7)                                          /* (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_PER7_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_PER7_Pos)       /* (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_PER7(value)        (RTC_MODE1_INTENCLR_PER7_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_CMP0_Pos           _UINT16_(8)                                          /* (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_CMP0_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_CMP0_Pos)       /* (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_CMP0(value)        (RTC_MODE1_INTENCLR_CMP0_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_CMP1_Pos           _UINT16_(9)                                          /* (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_CMP1_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_CMP1_Pos)       /* (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_CMP1(value)        (RTC_MODE1_INTENCLR_CMP1_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_CMP2_Pos           _UINT16_(10)                                         /* (RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_CMP2_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_CMP2_Pos)       /* (RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_CMP2(value)        (RTC_MODE1_INTENCLR_CMP2_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_CMP2_Pos)) /* Assignment of value for CMP2 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_CMP3_Pos           _UINT16_(11)                                         /* (RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_CMP3_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENCLR_CMP3_Pos)       /* (RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_CMP3(value)        (RTC_MODE1_INTENCLR_CMP3_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_CMP3_Pos)) /* Assignment of value for CMP3 in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_TAMPER_Pos         _UINT16_(14)                                         /* (RTC_MODE1_INTENCLR) Tamper Enable Position */
+#define RTC_MODE1_INTENCLR_TAMPER_Msk         (_UINT16_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos)     /* (RTC_MODE1_INTENCLR) Tamper Enable Mask */
+#define RTC_MODE1_INTENCLR_TAMPER(value)      (RTC_MODE1_INTENCLR_TAMPER_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_OVF_Pos            _UINT16_(15)                                         /* (RTC_MODE1_INTENCLR) Overflow Interrupt Enable Position */
+#define RTC_MODE1_INTENCLR_OVF_Msk            (_UINT16_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)        /* (RTC_MODE1_INTENCLR) Overflow Interrupt Enable Mask */
+#define RTC_MODE1_INTENCLR_OVF(value)         (RTC_MODE1_INTENCLR_OVF_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE1_INTENCLR register */
+#define RTC_MODE1_INTENCLR_Msk                _UINT16_(0xCFFF)                                     /* (RTC_MODE1_INTENCLR) Register Mask  */
+
+#define RTC_MODE1_INTENCLR_PER_Pos            _UINT16_(0)                                          /* (RTC_MODE1_INTENCLR Position) Periodic Interval x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER_Msk            (_UINT16_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos)       /* (RTC_MODE1_INTENCLR Mask) PER */
+#define RTC_MODE1_INTENCLR_PER(value)         (RTC_MODE1_INTENCLR_PER_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_PER_Pos)) 
+#define RTC_MODE1_INTENCLR_CMP_Pos            _UINT16_(8)                                          /* (RTC_MODE1_INTENCLR Position) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk            (_UINT16_(0xF) << RTC_MODE1_INTENCLR_CMP_Pos)        /* (RTC_MODE1_INTENCLR Mask) CMP */
+#define RTC_MODE1_INTENCLR_CMP(value)         (RTC_MODE1_INTENCLR_CMP_Msk & (_UINT16_(value) << RTC_MODE1_INTENCLR_CMP_Pos)) 
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 Interrupt Enable Clear -------- */
+#define RTC_MODE2_INTENCLR_RESETVALUE         _UINT16_(0x00)                                       /*  (RTC_MODE2_INTENCLR) MODE2 Interrupt Enable Clear  Reset Value */
+
+#define RTC_MODE2_INTENCLR_PER0_Pos           _UINT16_(0)                                          /* (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_PER0_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER0_Pos)       /* (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_PER0(value)        (RTC_MODE2_INTENCLR_PER0_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_PER1_Pos           _UINT16_(1)                                          /* (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_PER1_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER1_Pos)       /* (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_PER1(value)        (RTC_MODE2_INTENCLR_PER1_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_PER2_Pos           _UINT16_(2)                                          /* (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_PER2_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER2_Pos)       /* (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_PER2(value)        (RTC_MODE2_INTENCLR_PER2_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_PER3_Pos           _UINT16_(3)                                          /* (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_PER3_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER3_Pos)       /* (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_PER3(value)        (RTC_MODE2_INTENCLR_PER3_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_PER4_Pos           _UINT16_(4)                                          /* (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_PER4_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER4_Pos)       /* (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_PER4(value)        (RTC_MODE2_INTENCLR_PER4_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_PER5_Pos           _UINT16_(5)                                          /* (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_PER5_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER5_Pos)       /* (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_PER5(value)        (RTC_MODE2_INTENCLR_PER5_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_PER6_Pos           _UINT16_(6)                                          /* (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_PER6_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER6_Pos)       /* (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_PER6(value)        (RTC_MODE2_INTENCLR_PER6_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_PER7_Pos           _UINT16_(7)                                          /* (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_PER7_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENCLR_PER7_Pos)       /* (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_PER7(value)        (RTC_MODE2_INTENCLR_PER7_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_ALARM0_Pos         _UINT16_(8)                                          /* (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_ALARM0_Msk         (_UINT16_(0x1) << RTC_MODE2_INTENCLR_ALARM0_Pos)     /* (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_ALARM0(value)      (RTC_MODE2_INTENCLR_ALARM0_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_ALARM0_Pos)) /* Assignment of value for ALARM0 in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_ALARM1_Pos         _UINT16_(9)                                          /* (RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_ALARM1_Msk         (_UINT16_(0x1) << RTC_MODE2_INTENCLR_ALARM1_Pos)     /* (RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_ALARM1(value)      (RTC_MODE2_INTENCLR_ALARM1_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_ALARM1_Pos)) /* Assignment of value for ALARM1 in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_TAMPER_Pos         _UINT16_(14)                                         /* (RTC_MODE2_INTENCLR) Tamper Enable Position */
+#define RTC_MODE2_INTENCLR_TAMPER_Msk         (_UINT16_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos)     /* (RTC_MODE2_INTENCLR) Tamper Enable Mask */
+#define RTC_MODE2_INTENCLR_TAMPER(value)      (RTC_MODE2_INTENCLR_TAMPER_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_OVF_Pos            _UINT16_(15)                                         /* (RTC_MODE2_INTENCLR) Overflow Interrupt Enable Position */
+#define RTC_MODE2_INTENCLR_OVF_Msk            (_UINT16_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)        /* (RTC_MODE2_INTENCLR) Overflow Interrupt Enable Mask */
+#define RTC_MODE2_INTENCLR_OVF(value)         (RTC_MODE2_INTENCLR_OVF_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE2_INTENCLR register */
+#define RTC_MODE2_INTENCLR_Msk                _UINT16_(0xC3FF)                                     /* (RTC_MODE2_INTENCLR) Register Mask  */
+
+#define RTC_MODE2_INTENCLR_PER_Pos            _UINT16_(0)                                          /* (RTC_MODE2_INTENCLR Position) Periodic Interval x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER_Msk            (_UINT16_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos)       /* (RTC_MODE2_INTENCLR Mask) PER */
+#define RTC_MODE2_INTENCLR_PER(value)         (RTC_MODE2_INTENCLR_PER_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_PER_Pos)) 
+#define RTC_MODE2_INTENCLR_ALARM_Pos          _UINT16_(8)                                          /* (RTC_MODE2_INTENCLR Position) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk          (_UINT16_(0x3) << RTC_MODE2_INTENCLR_ALARM_Pos)      /* (RTC_MODE2_INTENCLR Mask) ALARM */
+#define RTC_MODE2_INTENCLR_ALARM(value)       (RTC_MODE2_INTENCLR_ALARM_Msk & (_UINT16_(value) << RTC_MODE2_INTENCLR_ALARM_Pos)) 
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 Interrupt Enable Set -------- */
+#define RTC_MODE0_INTENSET_RESETVALUE         _UINT16_(0x00)                                       /*  (RTC_MODE0_INTENSET) MODE0 Interrupt Enable Set  Reset Value */
+
+#define RTC_MODE0_INTENSET_PER0_Pos           _UINT16_(0)                                          /* (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_PER0_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER0_Pos)       /* (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_PER0(value)        (RTC_MODE0_INTENSET_PER0_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_PER1_Pos           _UINT16_(1)                                          /* (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_PER1_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER1_Pos)       /* (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_PER1(value)        (RTC_MODE0_INTENSET_PER1_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_PER2_Pos           _UINT16_(2)                                          /* (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_PER2_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER2_Pos)       /* (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_PER2(value)        (RTC_MODE0_INTENSET_PER2_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_PER3_Pos           _UINT16_(3)                                          /* (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_PER3_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER3_Pos)       /* (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_PER3(value)        (RTC_MODE0_INTENSET_PER3_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_PER4_Pos           _UINT16_(4)                                          /* (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_PER4_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER4_Pos)       /* (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_PER4(value)        (RTC_MODE0_INTENSET_PER4_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_PER5_Pos           _UINT16_(5)                                          /* (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_PER5_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER5_Pos)       /* (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_PER5(value)        (RTC_MODE0_INTENSET_PER5_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_PER6_Pos           _UINT16_(6)                                          /* (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_PER6_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER6_Pos)       /* (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_PER6(value)        (RTC_MODE0_INTENSET_PER6_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_PER7_Pos           _UINT16_(7)                                          /* (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_PER7_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENSET_PER7_Pos)       /* (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_PER7(value)        (RTC_MODE0_INTENSET_PER7_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_CMP0_Pos           _UINT16_(8)                                          /* (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_CMP0_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENSET_CMP0_Pos)       /* (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_CMP0(value)        (RTC_MODE0_INTENSET_CMP0_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_CMP1_Pos           _UINT16_(9)                                          /* (RTC_MODE0_INTENSET) Compare 1 Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_CMP1_Msk           (_UINT16_(0x1) << RTC_MODE0_INTENSET_CMP1_Pos)       /* (RTC_MODE0_INTENSET) Compare 1 Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_CMP1(value)        (RTC_MODE0_INTENSET_CMP1_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_TAMPER_Pos         _UINT16_(14)                                         /* (RTC_MODE0_INTENSET) Tamper Enable Position */
+#define RTC_MODE0_INTENSET_TAMPER_Msk         (_UINT16_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos)     /* (RTC_MODE0_INTENSET) Tamper Enable Mask */
+#define RTC_MODE0_INTENSET_TAMPER(value)      (RTC_MODE0_INTENSET_TAMPER_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_OVF_Pos            _UINT16_(15)                                         /* (RTC_MODE0_INTENSET) Overflow Interrupt Enable Position */
+#define RTC_MODE0_INTENSET_OVF_Msk            (_UINT16_(0x1) << RTC_MODE0_INTENSET_OVF_Pos)        /* (RTC_MODE0_INTENSET) Overflow Interrupt Enable Mask */
+#define RTC_MODE0_INTENSET_OVF(value)         (RTC_MODE0_INTENSET_OVF_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE0_INTENSET register */
+#define RTC_MODE0_INTENSET_Msk                _UINT16_(0xC3FF)                                     /* (RTC_MODE0_INTENSET) Register Mask  */
+
+#define RTC_MODE0_INTENSET_PER_Pos            _UINT16_(0)                                          /* (RTC_MODE0_INTENSET Position) Periodic Interval x Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER_Msk            (_UINT16_(0xFF) << RTC_MODE0_INTENSET_PER_Pos)       /* (RTC_MODE0_INTENSET Mask) PER */
+#define RTC_MODE0_INTENSET_PER(value)         (RTC_MODE0_INTENSET_PER_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_PER_Pos)) 
+#define RTC_MODE0_INTENSET_CMP_Pos            _UINT16_(8)                                          /* (RTC_MODE0_INTENSET Position) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk            (_UINT16_(0x3) << RTC_MODE0_INTENSET_CMP_Pos)        /* (RTC_MODE0_INTENSET Mask) CMP */
+#define RTC_MODE0_INTENSET_CMP(value)         (RTC_MODE0_INTENSET_CMP_Msk & (_UINT16_(value) << RTC_MODE0_INTENSET_CMP_Pos)) 
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 Interrupt Enable Set -------- */
+#define RTC_MODE1_INTENSET_RESETVALUE         _UINT16_(0x00)                                       /*  (RTC_MODE1_INTENSET) MODE1 Interrupt Enable Set  Reset Value */
+
+#define RTC_MODE1_INTENSET_PER0_Pos           _UINT16_(0)                                          /* (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_PER0_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER0_Pos)       /* (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_PER0(value)        (RTC_MODE1_INTENSET_PER0_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_PER1_Pos           _UINT16_(1)                                          /* (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_PER1_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER1_Pos)       /* (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_PER1(value)        (RTC_MODE1_INTENSET_PER1_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_PER2_Pos           _UINT16_(2)                                          /* (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_PER2_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER2_Pos)       /* (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_PER2(value)        (RTC_MODE1_INTENSET_PER2_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_PER3_Pos           _UINT16_(3)                                          /* (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_PER3_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER3_Pos)       /* (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_PER3(value)        (RTC_MODE1_INTENSET_PER3_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_PER4_Pos           _UINT16_(4)                                          /* (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_PER4_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER4_Pos)       /* (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_PER4(value)        (RTC_MODE1_INTENSET_PER4_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_PER5_Pos           _UINT16_(5)                                          /* (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_PER5_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER5_Pos)       /* (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_PER5(value)        (RTC_MODE1_INTENSET_PER5_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_PER6_Pos           _UINT16_(6)                                          /* (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_PER6_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER6_Pos)       /* (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_PER6(value)        (RTC_MODE1_INTENSET_PER6_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_PER7_Pos           _UINT16_(7)                                          /* (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_PER7_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_PER7_Pos)       /* (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_PER7(value)        (RTC_MODE1_INTENSET_PER7_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_CMP0_Pos           _UINT16_(8)                                          /* (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_CMP0_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_CMP0_Pos)       /* (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_CMP0(value)        (RTC_MODE1_INTENSET_CMP0_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_CMP1_Pos           _UINT16_(9)                                          /* (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_CMP1_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_CMP1_Pos)       /* (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_CMP1(value)        (RTC_MODE1_INTENSET_CMP1_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_CMP2_Pos           _UINT16_(10)                                         /* (RTC_MODE1_INTENSET) Compare 2 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_CMP2_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_CMP2_Pos)       /* (RTC_MODE1_INTENSET) Compare 2 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_CMP2(value)        (RTC_MODE1_INTENSET_CMP2_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_CMP2_Pos)) /* Assignment of value for CMP2 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_CMP3_Pos           _UINT16_(11)                                         /* (RTC_MODE1_INTENSET) Compare 3 Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_CMP3_Msk           (_UINT16_(0x1) << RTC_MODE1_INTENSET_CMP3_Pos)       /* (RTC_MODE1_INTENSET) Compare 3 Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_CMP3(value)        (RTC_MODE1_INTENSET_CMP3_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_CMP3_Pos)) /* Assignment of value for CMP3 in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_TAMPER_Pos         _UINT16_(14)                                         /* (RTC_MODE1_INTENSET) Tamper Enable Position */
+#define RTC_MODE1_INTENSET_TAMPER_Msk         (_UINT16_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos)     /* (RTC_MODE1_INTENSET) Tamper Enable Mask */
+#define RTC_MODE1_INTENSET_TAMPER(value)      (RTC_MODE1_INTENSET_TAMPER_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_OVF_Pos            _UINT16_(15)                                         /* (RTC_MODE1_INTENSET) Overflow Interrupt Enable Position */
+#define RTC_MODE1_INTENSET_OVF_Msk            (_UINT16_(0x1) << RTC_MODE1_INTENSET_OVF_Pos)        /* (RTC_MODE1_INTENSET) Overflow Interrupt Enable Mask */
+#define RTC_MODE1_INTENSET_OVF(value)         (RTC_MODE1_INTENSET_OVF_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE1_INTENSET register */
+#define RTC_MODE1_INTENSET_Msk                _UINT16_(0xCFFF)                                     /* (RTC_MODE1_INTENSET) Register Mask  */
+
+#define RTC_MODE1_INTENSET_PER_Pos            _UINT16_(0)                                          /* (RTC_MODE1_INTENSET Position) Periodic Interval x Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER_Msk            (_UINT16_(0xFF) << RTC_MODE1_INTENSET_PER_Pos)       /* (RTC_MODE1_INTENSET Mask) PER */
+#define RTC_MODE1_INTENSET_PER(value)         (RTC_MODE1_INTENSET_PER_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_PER_Pos)) 
+#define RTC_MODE1_INTENSET_CMP_Pos            _UINT16_(8)                                          /* (RTC_MODE1_INTENSET Position) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk            (_UINT16_(0xF) << RTC_MODE1_INTENSET_CMP_Pos)        /* (RTC_MODE1_INTENSET Mask) CMP */
+#define RTC_MODE1_INTENSET_CMP(value)         (RTC_MODE1_INTENSET_CMP_Msk & (_UINT16_(value) << RTC_MODE1_INTENSET_CMP_Pos)) 
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 Interrupt Enable Set -------- */
+#define RTC_MODE2_INTENSET_RESETVALUE         _UINT16_(0x00)                                       /*  (RTC_MODE2_INTENSET) MODE2 Interrupt Enable Set  Reset Value */
+
+#define RTC_MODE2_INTENSET_PER0_Pos           _UINT16_(0)                                          /* (RTC_MODE2_INTENSET) Periodic Interval 0 Enable Position */
+#define RTC_MODE2_INTENSET_PER0_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER0_Pos)       /* (RTC_MODE2_INTENSET) Periodic Interval 0 Enable Mask */
+#define RTC_MODE2_INTENSET_PER0(value)        (RTC_MODE2_INTENSET_PER0_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_PER1_Pos           _UINT16_(1)                                          /* (RTC_MODE2_INTENSET) Periodic Interval 1 Enable Position */
+#define RTC_MODE2_INTENSET_PER1_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER1_Pos)       /* (RTC_MODE2_INTENSET) Periodic Interval 1 Enable Mask */
+#define RTC_MODE2_INTENSET_PER1(value)        (RTC_MODE2_INTENSET_PER1_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_PER2_Pos           _UINT16_(2)                                          /* (RTC_MODE2_INTENSET) Periodic Interval 2 Enable Position */
+#define RTC_MODE2_INTENSET_PER2_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER2_Pos)       /* (RTC_MODE2_INTENSET) Periodic Interval 2 Enable Mask */
+#define RTC_MODE2_INTENSET_PER2(value)        (RTC_MODE2_INTENSET_PER2_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_PER3_Pos           _UINT16_(3)                                          /* (RTC_MODE2_INTENSET) Periodic Interval 3 Enable Position */
+#define RTC_MODE2_INTENSET_PER3_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER3_Pos)       /* (RTC_MODE2_INTENSET) Periodic Interval 3 Enable Mask */
+#define RTC_MODE2_INTENSET_PER3(value)        (RTC_MODE2_INTENSET_PER3_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_PER4_Pos           _UINT16_(4)                                          /* (RTC_MODE2_INTENSET) Periodic Interval 4 Enable Position */
+#define RTC_MODE2_INTENSET_PER4_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER4_Pos)       /* (RTC_MODE2_INTENSET) Periodic Interval 4 Enable Mask */
+#define RTC_MODE2_INTENSET_PER4(value)        (RTC_MODE2_INTENSET_PER4_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_PER5_Pos           _UINT16_(5)                                          /* (RTC_MODE2_INTENSET) Periodic Interval 5 Enable Position */
+#define RTC_MODE2_INTENSET_PER5_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER5_Pos)       /* (RTC_MODE2_INTENSET) Periodic Interval 5 Enable Mask */
+#define RTC_MODE2_INTENSET_PER5(value)        (RTC_MODE2_INTENSET_PER5_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_PER6_Pos           _UINT16_(6)                                          /* (RTC_MODE2_INTENSET) Periodic Interval 6 Enable Position */
+#define RTC_MODE2_INTENSET_PER6_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER6_Pos)       /* (RTC_MODE2_INTENSET) Periodic Interval 6 Enable Mask */
+#define RTC_MODE2_INTENSET_PER6(value)        (RTC_MODE2_INTENSET_PER6_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_PER7_Pos           _UINT16_(7)                                          /* (RTC_MODE2_INTENSET) Periodic Interval 7 Enable Position */
+#define RTC_MODE2_INTENSET_PER7_Msk           (_UINT16_(0x1) << RTC_MODE2_INTENSET_PER7_Pos)       /* (RTC_MODE2_INTENSET) Periodic Interval 7 Enable Mask */
+#define RTC_MODE2_INTENSET_PER7(value)        (RTC_MODE2_INTENSET_PER7_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_ALARM0_Pos         _UINT16_(8)                                          /* (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable Position */
+#define RTC_MODE2_INTENSET_ALARM0_Msk         (_UINT16_(0x1) << RTC_MODE2_INTENSET_ALARM0_Pos)     /* (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable Mask */
+#define RTC_MODE2_INTENSET_ALARM0(value)      (RTC_MODE2_INTENSET_ALARM0_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_ALARM0_Pos)) /* Assignment of value for ALARM0 in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_ALARM1_Pos         _UINT16_(9)                                          /* (RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable Position */
+#define RTC_MODE2_INTENSET_ALARM1_Msk         (_UINT16_(0x1) << RTC_MODE2_INTENSET_ALARM1_Pos)     /* (RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable Mask */
+#define RTC_MODE2_INTENSET_ALARM1(value)      (RTC_MODE2_INTENSET_ALARM1_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_ALARM1_Pos)) /* Assignment of value for ALARM1 in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_TAMPER_Pos         _UINT16_(14)                                         /* (RTC_MODE2_INTENSET) Tamper Enable Position */
+#define RTC_MODE2_INTENSET_TAMPER_Msk         (_UINT16_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos)     /* (RTC_MODE2_INTENSET) Tamper Enable Mask */
+#define RTC_MODE2_INTENSET_TAMPER(value)      (RTC_MODE2_INTENSET_TAMPER_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_OVF_Pos            _UINT16_(15)                                         /* (RTC_MODE2_INTENSET) Overflow Interrupt Enable Position */
+#define RTC_MODE2_INTENSET_OVF_Msk            (_UINT16_(0x1) << RTC_MODE2_INTENSET_OVF_Pos)        /* (RTC_MODE2_INTENSET) Overflow Interrupt Enable Mask */
+#define RTC_MODE2_INTENSET_OVF(value)         (RTC_MODE2_INTENSET_OVF_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE2_INTENSET register */
+#define RTC_MODE2_INTENSET_Msk                _UINT16_(0xC3FF)                                     /* (RTC_MODE2_INTENSET) Register Mask  */
+
+#define RTC_MODE2_INTENSET_PER_Pos            _UINT16_(0)                                          /* (RTC_MODE2_INTENSET Position) Periodic Interval x Enable */
+#define RTC_MODE2_INTENSET_PER_Msk            (_UINT16_(0xFF) << RTC_MODE2_INTENSET_PER_Pos)       /* (RTC_MODE2_INTENSET Mask) PER */
+#define RTC_MODE2_INTENSET_PER(value)         (RTC_MODE2_INTENSET_PER_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_PER_Pos)) 
+#define RTC_MODE2_INTENSET_ALARM_Pos          _UINT16_(8)                                          /* (RTC_MODE2_INTENSET Position) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk          (_UINT16_(0x3) << RTC_MODE2_INTENSET_ALARM_Pos)      /* (RTC_MODE2_INTENSET Mask) ALARM */
+#define RTC_MODE2_INTENSET_ALARM(value)       (RTC_MODE2_INTENSET_ALARM_Msk & (_UINT16_(value) << RTC_MODE2_INTENSET_ALARM_Pos)) 
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 Interrupt Flag Status and Clear -------- */
+#define RTC_MODE0_INTFLAG_RESETVALUE          _UINT16_(0x00)                                       /*  (RTC_MODE0_INTFLAG) MODE0 Interrupt Flag Status and Clear  Reset Value */
+
+#define RTC_MODE0_INTFLAG_PER0_Pos            _UINT16_(0)                                          /* (RTC_MODE0_INTFLAG) Periodic Interval 0 Position */
+#define RTC_MODE0_INTFLAG_PER0_Msk            (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER0_Pos)        /* (RTC_MODE0_INTFLAG) Periodic Interval 0 Mask */
+#define RTC_MODE0_INTFLAG_PER0(value)         (RTC_MODE0_INTFLAG_PER0_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_PER1_Pos            _UINT16_(1)                                          /* (RTC_MODE0_INTFLAG) Periodic Interval 1 Position */
+#define RTC_MODE0_INTFLAG_PER1_Msk            (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER1_Pos)        /* (RTC_MODE0_INTFLAG) Periodic Interval 1 Mask */
+#define RTC_MODE0_INTFLAG_PER1(value)         (RTC_MODE0_INTFLAG_PER1_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_PER2_Pos            _UINT16_(2)                                          /* (RTC_MODE0_INTFLAG) Periodic Interval 2 Position */
+#define RTC_MODE0_INTFLAG_PER2_Msk            (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER2_Pos)        /* (RTC_MODE0_INTFLAG) Periodic Interval 2 Mask */
+#define RTC_MODE0_INTFLAG_PER2(value)         (RTC_MODE0_INTFLAG_PER2_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_PER3_Pos            _UINT16_(3)                                          /* (RTC_MODE0_INTFLAG) Periodic Interval 3 Position */
+#define RTC_MODE0_INTFLAG_PER3_Msk            (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER3_Pos)        /* (RTC_MODE0_INTFLAG) Periodic Interval 3 Mask */
+#define RTC_MODE0_INTFLAG_PER3(value)         (RTC_MODE0_INTFLAG_PER3_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_PER4_Pos            _UINT16_(4)                                          /* (RTC_MODE0_INTFLAG) Periodic Interval 4 Position */
+#define RTC_MODE0_INTFLAG_PER4_Msk            (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER4_Pos)        /* (RTC_MODE0_INTFLAG) Periodic Interval 4 Mask */
+#define RTC_MODE0_INTFLAG_PER4(value)         (RTC_MODE0_INTFLAG_PER4_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_PER5_Pos            _UINT16_(5)                                          /* (RTC_MODE0_INTFLAG) Periodic Interval 5 Position */
+#define RTC_MODE0_INTFLAG_PER5_Msk            (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER5_Pos)        /* (RTC_MODE0_INTFLAG) Periodic Interval 5 Mask */
+#define RTC_MODE0_INTFLAG_PER5(value)         (RTC_MODE0_INTFLAG_PER5_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_PER6_Pos            _UINT16_(6)                                          /* (RTC_MODE0_INTFLAG) Periodic Interval 6 Position */
+#define RTC_MODE0_INTFLAG_PER6_Msk            (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER6_Pos)        /* (RTC_MODE0_INTFLAG) Periodic Interval 6 Mask */
+#define RTC_MODE0_INTFLAG_PER6(value)         (RTC_MODE0_INTFLAG_PER6_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_PER7_Pos            _UINT16_(7)                                          /* (RTC_MODE0_INTFLAG) Periodic Interval 7 Position */
+#define RTC_MODE0_INTFLAG_PER7_Msk            (_UINT16_(0x1) << RTC_MODE0_INTFLAG_PER7_Pos)        /* (RTC_MODE0_INTFLAG) Periodic Interval 7 Mask */
+#define RTC_MODE0_INTFLAG_PER7(value)         (RTC_MODE0_INTFLAG_PER7_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_CMP0_Pos            _UINT16_(8)                                          /* (RTC_MODE0_INTFLAG) Compare 0 Position */
+#define RTC_MODE0_INTFLAG_CMP0_Msk            (_UINT16_(0x1) << RTC_MODE0_INTFLAG_CMP0_Pos)        /* (RTC_MODE0_INTFLAG) Compare 0 Mask */
+#define RTC_MODE0_INTFLAG_CMP0(value)         (RTC_MODE0_INTFLAG_CMP0_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_CMP1_Pos            _UINT16_(9)                                          /* (RTC_MODE0_INTFLAG) Compare 1 Position */
+#define RTC_MODE0_INTFLAG_CMP1_Msk            (_UINT16_(0x1) << RTC_MODE0_INTFLAG_CMP1_Pos)        /* (RTC_MODE0_INTFLAG) Compare 1 Mask */
+#define RTC_MODE0_INTFLAG_CMP1(value)         (RTC_MODE0_INTFLAG_CMP1_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_TAMPER_Pos          _UINT16_(14)                                         /* (RTC_MODE0_INTFLAG) Tamper Position */
+#define RTC_MODE0_INTFLAG_TAMPER_Msk          (_UINT16_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos)      /* (RTC_MODE0_INTFLAG) Tamper Mask */
+#define RTC_MODE0_INTFLAG_TAMPER(value)       (RTC_MODE0_INTFLAG_TAMPER_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_OVF_Pos             _UINT16_(15)                                         /* (RTC_MODE0_INTFLAG) Overflow Position */
+#define RTC_MODE0_INTFLAG_OVF_Msk             (_UINT16_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)         /* (RTC_MODE0_INTFLAG) Overflow Mask */
+#define RTC_MODE0_INTFLAG_OVF(value)          (RTC_MODE0_INTFLAG_OVF_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE0_INTFLAG register */
+#define RTC_MODE0_INTFLAG_Msk                 _UINT16_(0xC3FF)                                     /* (RTC_MODE0_INTFLAG) Register Mask  */
+
+#define RTC_MODE0_INTFLAG_PER_Pos             _UINT16_(0)                                          /* (RTC_MODE0_INTFLAG Position) Periodic Interval x */
+#define RTC_MODE0_INTFLAG_PER_Msk             (_UINT16_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos)        /* (RTC_MODE0_INTFLAG Mask) PER */
+#define RTC_MODE0_INTFLAG_PER(value)          (RTC_MODE0_INTFLAG_PER_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_PER_Pos)) 
+#define RTC_MODE0_INTFLAG_CMP_Pos             _UINT16_(8)                                          /* (RTC_MODE0_INTFLAG Position) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk             (_UINT16_(0x3) << RTC_MODE0_INTFLAG_CMP_Pos)         /* (RTC_MODE0_INTFLAG Mask) CMP */
+#define RTC_MODE0_INTFLAG_CMP(value)          (RTC_MODE0_INTFLAG_CMP_Msk & (_UINT16_(value) << RTC_MODE0_INTFLAG_CMP_Pos)) 
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 Interrupt Flag Status and Clear -------- */
+#define RTC_MODE1_INTFLAG_RESETVALUE          _UINT16_(0x00)                                       /*  (RTC_MODE1_INTFLAG) MODE1 Interrupt Flag Status and Clear  Reset Value */
+
+#define RTC_MODE1_INTFLAG_PER0_Pos            _UINT16_(0)                                          /* (RTC_MODE1_INTFLAG) Periodic Interval 0 Position */
+#define RTC_MODE1_INTFLAG_PER0_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER0_Pos)        /* (RTC_MODE1_INTFLAG) Periodic Interval 0 Mask */
+#define RTC_MODE1_INTFLAG_PER0(value)         (RTC_MODE1_INTFLAG_PER0_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_PER1_Pos            _UINT16_(1)                                          /* (RTC_MODE1_INTFLAG) Periodic Interval 1 Position */
+#define RTC_MODE1_INTFLAG_PER1_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER1_Pos)        /* (RTC_MODE1_INTFLAG) Periodic Interval 1 Mask */
+#define RTC_MODE1_INTFLAG_PER1(value)         (RTC_MODE1_INTFLAG_PER1_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_PER2_Pos            _UINT16_(2)                                          /* (RTC_MODE1_INTFLAG) Periodic Interval 2 Position */
+#define RTC_MODE1_INTFLAG_PER2_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER2_Pos)        /* (RTC_MODE1_INTFLAG) Periodic Interval 2 Mask */
+#define RTC_MODE1_INTFLAG_PER2(value)         (RTC_MODE1_INTFLAG_PER2_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_PER3_Pos            _UINT16_(3)                                          /* (RTC_MODE1_INTFLAG) Periodic Interval 3 Position */
+#define RTC_MODE1_INTFLAG_PER3_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER3_Pos)        /* (RTC_MODE1_INTFLAG) Periodic Interval 3 Mask */
+#define RTC_MODE1_INTFLAG_PER3(value)         (RTC_MODE1_INTFLAG_PER3_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_PER4_Pos            _UINT16_(4)                                          /* (RTC_MODE1_INTFLAG) Periodic Interval 4 Position */
+#define RTC_MODE1_INTFLAG_PER4_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER4_Pos)        /* (RTC_MODE1_INTFLAG) Periodic Interval 4 Mask */
+#define RTC_MODE1_INTFLAG_PER4(value)         (RTC_MODE1_INTFLAG_PER4_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_PER5_Pos            _UINT16_(5)                                          /* (RTC_MODE1_INTFLAG) Periodic Interval 5 Position */
+#define RTC_MODE1_INTFLAG_PER5_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER5_Pos)        /* (RTC_MODE1_INTFLAG) Periodic Interval 5 Mask */
+#define RTC_MODE1_INTFLAG_PER5(value)         (RTC_MODE1_INTFLAG_PER5_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_PER6_Pos            _UINT16_(6)                                          /* (RTC_MODE1_INTFLAG) Periodic Interval 6 Position */
+#define RTC_MODE1_INTFLAG_PER6_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER6_Pos)        /* (RTC_MODE1_INTFLAG) Periodic Interval 6 Mask */
+#define RTC_MODE1_INTFLAG_PER6(value)         (RTC_MODE1_INTFLAG_PER6_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_PER7_Pos            _UINT16_(7)                                          /* (RTC_MODE1_INTFLAG) Periodic Interval 7 Position */
+#define RTC_MODE1_INTFLAG_PER7_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_PER7_Pos)        /* (RTC_MODE1_INTFLAG) Periodic Interval 7 Mask */
+#define RTC_MODE1_INTFLAG_PER7(value)         (RTC_MODE1_INTFLAG_PER7_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_CMP0_Pos            _UINT16_(8)                                          /* (RTC_MODE1_INTFLAG) Compare 0 Position */
+#define RTC_MODE1_INTFLAG_CMP0_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_CMP0_Pos)        /* (RTC_MODE1_INTFLAG) Compare 0 Mask */
+#define RTC_MODE1_INTFLAG_CMP0(value)         (RTC_MODE1_INTFLAG_CMP0_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_CMP0_Pos)) /* Assignment of value for CMP0 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_CMP1_Pos            _UINT16_(9)                                          /* (RTC_MODE1_INTFLAG) Compare 1 Position */
+#define RTC_MODE1_INTFLAG_CMP1_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_CMP1_Pos)        /* (RTC_MODE1_INTFLAG) Compare 1 Mask */
+#define RTC_MODE1_INTFLAG_CMP1(value)         (RTC_MODE1_INTFLAG_CMP1_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_CMP1_Pos)) /* Assignment of value for CMP1 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_CMP2_Pos            _UINT16_(10)                                         /* (RTC_MODE1_INTFLAG) Compare 2 Position */
+#define RTC_MODE1_INTFLAG_CMP2_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_CMP2_Pos)        /* (RTC_MODE1_INTFLAG) Compare 2 Mask */
+#define RTC_MODE1_INTFLAG_CMP2(value)         (RTC_MODE1_INTFLAG_CMP2_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_CMP2_Pos)) /* Assignment of value for CMP2 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_CMP3_Pos            _UINT16_(11)                                         /* (RTC_MODE1_INTFLAG) Compare 3 Position */
+#define RTC_MODE1_INTFLAG_CMP3_Msk            (_UINT16_(0x1) << RTC_MODE1_INTFLAG_CMP3_Pos)        /* (RTC_MODE1_INTFLAG) Compare 3 Mask */
+#define RTC_MODE1_INTFLAG_CMP3(value)         (RTC_MODE1_INTFLAG_CMP3_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_CMP3_Pos)) /* Assignment of value for CMP3 in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_TAMPER_Pos          _UINT16_(14)                                         /* (RTC_MODE1_INTFLAG) Tamper Position */
+#define RTC_MODE1_INTFLAG_TAMPER_Msk          (_UINT16_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos)      /* (RTC_MODE1_INTFLAG) Tamper Mask */
+#define RTC_MODE1_INTFLAG_TAMPER(value)       (RTC_MODE1_INTFLAG_TAMPER_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_OVF_Pos             _UINT16_(15)                                         /* (RTC_MODE1_INTFLAG) Overflow Position */
+#define RTC_MODE1_INTFLAG_OVF_Msk             (_UINT16_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)         /* (RTC_MODE1_INTFLAG) Overflow Mask */
+#define RTC_MODE1_INTFLAG_OVF(value)          (RTC_MODE1_INTFLAG_OVF_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE1_INTFLAG register */
+#define RTC_MODE1_INTFLAG_Msk                 _UINT16_(0xCFFF)                                     /* (RTC_MODE1_INTFLAG) Register Mask  */
+
+#define RTC_MODE1_INTFLAG_PER_Pos             _UINT16_(0)                                          /* (RTC_MODE1_INTFLAG Position) Periodic Interval x */
+#define RTC_MODE1_INTFLAG_PER_Msk             (_UINT16_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos)        /* (RTC_MODE1_INTFLAG Mask) PER */
+#define RTC_MODE1_INTFLAG_PER(value)          (RTC_MODE1_INTFLAG_PER_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_PER_Pos)) 
+#define RTC_MODE1_INTFLAG_CMP_Pos             _UINT16_(8)                                          /* (RTC_MODE1_INTFLAG Position) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk             (_UINT16_(0xF) << RTC_MODE1_INTFLAG_CMP_Pos)         /* (RTC_MODE1_INTFLAG Mask) CMP */
+#define RTC_MODE1_INTFLAG_CMP(value)          (RTC_MODE1_INTFLAG_CMP_Msk & (_UINT16_(value) << RTC_MODE1_INTFLAG_CMP_Pos)) 
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 Interrupt Flag Status and Clear -------- */
+#define RTC_MODE2_INTFLAG_RESETVALUE          _UINT16_(0x00)                                       /*  (RTC_MODE2_INTFLAG) MODE2 Interrupt Flag Status and Clear  Reset Value */
+
+#define RTC_MODE2_INTFLAG_PER0_Pos            _UINT16_(0)                                          /* (RTC_MODE2_INTFLAG) Periodic Interval 0 Position */
+#define RTC_MODE2_INTFLAG_PER0_Msk            (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER0_Pos)        /* (RTC_MODE2_INTFLAG) Periodic Interval 0 Mask */
+#define RTC_MODE2_INTFLAG_PER0(value)         (RTC_MODE2_INTFLAG_PER0_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER0_Pos)) /* Assignment of value for PER0 in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_PER1_Pos            _UINT16_(1)                                          /* (RTC_MODE2_INTFLAG) Periodic Interval 1 Position */
+#define RTC_MODE2_INTFLAG_PER1_Msk            (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER1_Pos)        /* (RTC_MODE2_INTFLAG) Periodic Interval 1 Mask */
+#define RTC_MODE2_INTFLAG_PER1(value)         (RTC_MODE2_INTFLAG_PER1_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER1_Pos)) /* Assignment of value for PER1 in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_PER2_Pos            _UINT16_(2)                                          /* (RTC_MODE2_INTFLAG) Periodic Interval 2 Position */
+#define RTC_MODE2_INTFLAG_PER2_Msk            (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER2_Pos)        /* (RTC_MODE2_INTFLAG) Periodic Interval 2 Mask */
+#define RTC_MODE2_INTFLAG_PER2(value)         (RTC_MODE2_INTFLAG_PER2_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER2_Pos)) /* Assignment of value for PER2 in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_PER3_Pos            _UINT16_(3)                                          /* (RTC_MODE2_INTFLAG) Periodic Interval 3 Position */
+#define RTC_MODE2_INTFLAG_PER3_Msk            (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER3_Pos)        /* (RTC_MODE2_INTFLAG) Periodic Interval 3 Mask */
+#define RTC_MODE2_INTFLAG_PER3(value)         (RTC_MODE2_INTFLAG_PER3_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER3_Pos)) /* Assignment of value for PER3 in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_PER4_Pos            _UINT16_(4)                                          /* (RTC_MODE2_INTFLAG) Periodic Interval 4 Position */
+#define RTC_MODE2_INTFLAG_PER4_Msk            (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER4_Pos)        /* (RTC_MODE2_INTFLAG) Periodic Interval 4 Mask */
+#define RTC_MODE2_INTFLAG_PER4(value)         (RTC_MODE2_INTFLAG_PER4_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER4_Pos)) /* Assignment of value for PER4 in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_PER5_Pos            _UINT16_(5)                                          /* (RTC_MODE2_INTFLAG) Periodic Interval 5 Position */
+#define RTC_MODE2_INTFLAG_PER5_Msk            (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER5_Pos)        /* (RTC_MODE2_INTFLAG) Periodic Interval 5 Mask */
+#define RTC_MODE2_INTFLAG_PER5(value)         (RTC_MODE2_INTFLAG_PER5_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER5_Pos)) /* Assignment of value for PER5 in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_PER6_Pos            _UINT16_(6)                                          /* (RTC_MODE2_INTFLAG) Periodic Interval 6 Position */
+#define RTC_MODE2_INTFLAG_PER6_Msk            (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER6_Pos)        /* (RTC_MODE2_INTFLAG) Periodic Interval 6 Mask */
+#define RTC_MODE2_INTFLAG_PER6(value)         (RTC_MODE2_INTFLAG_PER6_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER6_Pos)) /* Assignment of value for PER6 in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_PER7_Pos            _UINT16_(7)                                          /* (RTC_MODE2_INTFLAG) Periodic Interval 7 Position */
+#define RTC_MODE2_INTFLAG_PER7_Msk            (_UINT16_(0x1) << RTC_MODE2_INTFLAG_PER7_Pos)        /* (RTC_MODE2_INTFLAG) Periodic Interval 7 Mask */
+#define RTC_MODE2_INTFLAG_PER7(value)         (RTC_MODE2_INTFLAG_PER7_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER7_Pos)) /* Assignment of value for PER7 in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_ALARM0_Pos          _UINT16_(8)                                          /* (RTC_MODE2_INTFLAG) Alarm 0 Position */
+#define RTC_MODE2_INTFLAG_ALARM0_Msk          (_UINT16_(0x1) << RTC_MODE2_INTFLAG_ALARM0_Pos)      /* (RTC_MODE2_INTFLAG) Alarm 0 Mask */
+#define RTC_MODE2_INTFLAG_ALARM0(value)       (RTC_MODE2_INTFLAG_ALARM0_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_ALARM0_Pos)) /* Assignment of value for ALARM0 in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_ALARM1_Pos          _UINT16_(9)                                          /* (RTC_MODE2_INTFLAG) Alarm 1 Position */
+#define RTC_MODE2_INTFLAG_ALARM1_Msk          (_UINT16_(0x1) << RTC_MODE2_INTFLAG_ALARM1_Pos)      /* (RTC_MODE2_INTFLAG) Alarm 1 Mask */
+#define RTC_MODE2_INTFLAG_ALARM1(value)       (RTC_MODE2_INTFLAG_ALARM1_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_ALARM1_Pos)) /* Assignment of value for ALARM1 in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_TAMPER_Pos          _UINT16_(14)                                         /* (RTC_MODE2_INTFLAG) Tamper Position */
+#define RTC_MODE2_INTFLAG_TAMPER_Msk          (_UINT16_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos)      /* (RTC_MODE2_INTFLAG) Tamper Mask */
+#define RTC_MODE2_INTFLAG_TAMPER(value)       (RTC_MODE2_INTFLAG_TAMPER_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_TAMPER_Pos)) /* Assignment of value for TAMPER in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_OVF_Pos             _UINT16_(15)                                         /* (RTC_MODE2_INTFLAG) Overflow Position */
+#define RTC_MODE2_INTFLAG_OVF_Msk             (_UINT16_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)         /* (RTC_MODE2_INTFLAG) Overflow Mask */
+#define RTC_MODE2_INTFLAG_OVF(value)          (RTC_MODE2_INTFLAG_OVF_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_OVF_Pos)) /* Assignment of value for OVF in the RTC_MODE2_INTFLAG register */
+#define RTC_MODE2_INTFLAG_Msk                 _UINT16_(0xC3FF)                                     /* (RTC_MODE2_INTFLAG) Register Mask  */
+
+#define RTC_MODE2_INTFLAG_PER_Pos             _UINT16_(0)                                          /* (RTC_MODE2_INTFLAG Position) Periodic Interval x */
+#define RTC_MODE2_INTFLAG_PER_Msk             (_UINT16_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos)        /* (RTC_MODE2_INTFLAG Mask) PER */
+#define RTC_MODE2_INTFLAG_PER(value)          (RTC_MODE2_INTFLAG_PER_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_PER_Pos)) 
+#define RTC_MODE2_INTFLAG_ALARM_Pos           _UINT16_(8)                                          /* (RTC_MODE2_INTFLAG Position) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk           (_UINT16_(0x3) << RTC_MODE2_INTFLAG_ALARM_Pos)       /* (RTC_MODE2_INTFLAG Mask) ALARM */
+#define RTC_MODE2_INTFLAG_ALARM(value)        (RTC_MODE2_INTFLAG_ALARM_Msk & (_UINT16_(value) << RTC_MODE2_INTFLAG_ALARM_Pos)) 
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W 8) Debug Control -------- */
+#define RTC_DBGCTRL_RESETVALUE                _UINT8_(0x00)                                        /*  (RTC_DBGCTRL) Debug Control  Reset Value */
+
+#define RTC_DBGCTRL_DBGRUN_Pos                _UINT8_(0)                                           /* (RTC_DBGCTRL) Run During Debug Position */
+#define RTC_DBGCTRL_DBGRUN_Msk                (_UINT8_(0x1) << RTC_DBGCTRL_DBGRUN_Pos)             /* (RTC_DBGCTRL) Run During Debug Mask */
+#define RTC_DBGCTRL_DBGRUN(value)             (RTC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << RTC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the RTC_DBGCTRL register */
+#define RTC_DBGCTRL_Msk                       _UINT8_(0x01)                                        /* (RTC_DBGCTRL) Register Mask  */
+
+
+/* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) ( R/ 32) MODE0 Synchronization Busy Status -------- */
+#define RTC_MODE0_SYNCBUSY_RESETVALUE         _UINT32_(0x00)                                       /*  (RTC_MODE0_SYNCBUSY) MODE0 Synchronization Busy Status  Reset Value */
+
+#define RTC_MODE0_SYNCBUSY_SWRST_Pos          _UINT32_(0)                                          /* (RTC_MODE0_SYNCBUSY) Software Reset Busy Position */
+#define RTC_MODE0_SYNCBUSY_SWRST_Msk          (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos)      /* (RTC_MODE0_SYNCBUSY) Software Reset Busy Mask */
+#define RTC_MODE0_SYNCBUSY_SWRST(value)       (RTC_MODE0_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_ENABLE_Pos         _UINT32_(1)                                          /* (RTC_MODE0_SYNCBUSY) Enable Bit Busy Position */
+#define RTC_MODE0_SYNCBUSY_ENABLE_Msk         (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)     /* (RTC_MODE0_SYNCBUSY) Enable Bit Busy Mask */
+#define RTC_MODE0_SYNCBUSY_ENABLE(value)      (RTC_MODE0_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_FREQCORR_Pos       _UINT32_(2)                                          /* (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy Position */
+#define RTC_MODE0_SYNCBUSY_FREQCORR_Msk       (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)   /* (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy Mask */
+#define RTC_MODE0_SYNCBUSY_FREQCORR(value)    (RTC_MODE0_SYNCBUSY_FREQCORR_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)) /* Assignment of value for FREQCORR in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_COUNT_Pos          _UINT32_(3)                                          /* (RTC_MODE0_SYNCBUSY) COUNT Register Busy Position */
+#define RTC_MODE0_SYNCBUSY_COUNT_Msk          (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos)      /* (RTC_MODE0_SYNCBUSY) COUNT Register Busy Mask */
+#define RTC_MODE0_SYNCBUSY_COUNT(value)       (RTC_MODE0_SYNCBUSY_COUNT_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_COMP0_Pos          _UINT32_(5)                                          /* (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy Position */
+#define RTC_MODE0_SYNCBUSY_COMP0_Msk          (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_COMP0_Pos)      /* (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy Mask */
+#define RTC_MODE0_SYNCBUSY_COMP0(value)       (RTC_MODE0_SYNCBUSY_COMP0_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_COMP0_Pos)) /* Assignment of value for COMP0 in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_COMP1_Pos          _UINT32_(6)                                          /* (RTC_MODE0_SYNCBUSY) COMP 1 Register Busy Position */
+#define RTC_MODE0_SYNCBUSY_COMP1_Msk          (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_COMP1_Pos)      /* (RTC_MODE0_SYNCBUSY) COMP 1 Register Busy Mask */
+#define RTC_MODE0_SYNCBUSY_COMP1(value)       (RTC_MODE0_SYNCBUSY_COMP1_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_COMP1_Pos)) /* Assignment of value for COMP1 in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos      _UINT32_(15)                                         /* (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy Position */
+#define RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk      (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)  /* (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy Mask */
+#define RTC_MODE0_SYNCBUSY_COUNTSYNC(value)   (RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)) /* Assignment of value for COUNTSYNC in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_GP0_Pos            _UINT32_(16)                                         /* (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy Position */
+#define RTC_MODE0_SYNCBUSY_GP0_Msk            (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_GP0_Pos)        /* (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy Mask */
+#define RTC_MODE0_SYNCBUSY_GP0(value)         (RTC_MODE0_SYNCBUSY_GP0_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_GP0_Pos)) /* Assignment of value for GP0 in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_GP1_Pos            _UINT32_(17)                                         /* (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy Position */
+#define RTC_MODE0_SYNCBUSY_GP1_Msk            (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_GP1_Pos)        /* (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy Mask */
+#define RTC_MODE0_SYNCBUSY_GP1(value)         (RTC_MODE0_SYNCBUSY_GP1_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_GP1_Pos)) /* Assignment of value for GP1 in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_GP2_Pos            _UINT32_(18)                                         /* (RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy Position */
+#define RTC_MODE0_SYNCBUSY_GP2_Msk            (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_GP2_Pos)        /* (RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy Mask */
+#define RTC_MODE0_SYNCBUSY_GP2(value)         (RTC_MODE0_SYNCBUSY_GP2_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_GP2_Pos)) /* Assignment of value for GP2 in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_GP3_Pos            _UINT32_(19)                                         /* (RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy Position */
+#define RTC_MODE0_SYNCBUSY_GP3_Msk            (_UINT32_(0x1) << RTC_MODE0_SYNCBUSY_GP3_Pos)        /* (RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy Mask */
+#define RTC_MODE0_SYNCBUSY_GP3(value)         (RTC_MODE0_SYNCBUSY_GP3_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_GP3_Pos)) /* Assignment of value for GP3 in the RTC_MODE0_SYNCBUSY register */
+#define RTC_MODE0_SYNCBUSY_Msk                _UINT32_(0x000F806F)                                 /* (RTC_MODE0_SYNCBUSY) Register Mask  */
+
+#define RTC_MODE0_SYNCBUSY_COMP_Pos           _UINT32_(5)                                          /* (RTC_MODE0_SYNCBUSY Position) COMP x Register Busy */
+#define RTC_MODE0_SYNCBUSY_COMP_Msk           (_UINT32_(0x3) << RTC_MODE0_SYNCBUSY_COMP_Pos)       /* (RTC_MODE0_SYNCBUSY Mask) COMP */
+#define RTC_MODE0_SYNCBUSY_COMP(value)        (RTC_MODE0_SYNCBUSY_COMP_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_COMP_Pos)) 
+#define RTC_MODE0_SYNCBUSY_GP_Pos             _UINT32_(16)                                         /* (RTC_MODE0_SYNCBUSY Position) General Purpose 3 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP_Msk             (_UINT32_(0xF) << RTC_MODE0_SYNCBUSY_GP_Pos)         /* (RTC_MODE0_SYNCBUSY Mask) GP */
+#define RTC_MODE0_SYNCBUSY_GP(value)          (RTC_MODE0_SYNCBUSY_GP_Msk & (_UINT32_(value) << RTC_MODE0_SYNCBUSY_GP_Pos)) 
+
+/* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) ( R/ 32) MODE1 Synchronization Busy Status -------- */
+#define RTC_MODE1_SYNCBUSY_RESETVALUE         _UINT32_(0x00)                                       /*  (RTC_MODE1_SYNCBUSY) MODE1 Synchronization Busy Status  Reset Value */
+
+#define RTC_MODE1_SYNCBUSY_SWRST_Pos          _UINT32_(0)                                          /* (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy Position */
+#define RTC_MODE1_SYNCBUSY_SWRST_Msk          (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos)      /* (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy Mask */
+#define RTC_MODE1_SYNCBUSY_SWRST(value)       (RTC_MODE1_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_ENABLE_Pos         _UINT32_(1)                                          /* (RTC_MODE1_SYNCBUSY) Enable Bit Busy Position */
+#define RTC_MODE1_SYNCBUSY_ENABLE_Msk         (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)     /* (RTC_MODE1_SYNCBUSY) Enable Bit Busy Mask */
+#define RTC_MODE1_SYNCBUSY_ENABLE(value)      (RTC_MODE1_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_FREQCORR_Pos       _UINT32_(2)                                          /* (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_FREQCORR_Msk       (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)   /* (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_FREQCORR(value)    (RTC_MODE1_SYNCBUSY_FREQCORR_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)) /* Assignment of value for FREQCORR in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_COUNT_Pos          _UINT32_(3)                                          /* (RTC_MODE1_SYNCBUSY) COUNT Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_COUNT_Msk          (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos)      /* (RTC_MODE1_SYNCBUSY) COUNT Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_COUNT(value)       (RTC_MODE1_SYNCBUSY_COUNT_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_PER_Pos            _UINT32_(4)                                          /* (RTC_MODE1_SYNCBUSY) PER Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_PER_Msk            (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos)        /* (RTC_MODE1_SYNCBUSY) PER Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_PER(value)         (RTC_MODE1_SYNCBUSY_PER_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_PER_Pos)) /* Assignment of value for PER in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_COMP0_Pos          _UINT32_(5)                                          /* (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_COMP0_Msk          (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COMP0_Pos)      /* (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_COMP0(value)       (RTC_MODE1_SYNCBUSY_COMP0_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COMP0_Pos)) /* Assignment of value for COMP0 in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_COMP1_Pos          _UINT32_(6)                                          /* (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_COMP1_Msk          (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COMP1_Pos)      /* (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_COMP1(value)       (RTC_MODE1_SYNCBUSY_COMP1_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COMP1_Pos)) /* Assignment of value for COMP1 in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_COMP2_Pos          _UINT32_(7)                                          /* (RTC_MODE1_SYNCBUSY) COMP 2 Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_COMP2_Msk          (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COMP2_Pos)      /* (RTC_MODE1_SYNCBUSY) COMP 2 Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_COMP2(value)       (RTC_MODE1_SYNCBUSY_COMP2_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COMP2_Pos)) /* Assignment of value for COMP2 in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_COMP3_Pos          _UINT32_(8)                                          /* (RTC_MODE1_SYNCBUSY) COMP 3 Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_COMP3_Msk          (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COMP3_Pos)      /* (RTC_MODE1_SYNCBUSY) COMP 3 Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_COMP3(value)       (RTC_MODE1_SYNCBUSY_COMP3_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COMP3_Pos)) /* Assignment of value for COMP3 in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos      _UINT32_(15)                                         /* (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy Position */
+#define RTC_MODE1_SYNCBUSY_COUNTSYNC_Msk      (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)  /* (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy Mask */
+#define RTC_MODE1_SYNCBUSY_COUNTSYNC(value)   (RTC_MODE1_SYNCBUSY_COUNTSYNC_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)) /* Assignment of value for COUNTSYNC in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_GP0_Pos            _UINT32_(16)                                         /* (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_GP0_Msk            (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_GP0_Pos)        /* (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_GP0(value)         (RTC_MODE1_SYNCBUSY_GP0_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_GP0_Pos)) /* Assignment of value for GP0 in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_GP1_Pos            _UINT32_(17)                                         /* (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_GP1_Msk            (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_GP1_Pos)        /* (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_GP1(value)         (RTC_MODE1_SYNCBUSY_GP1_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_GP1_Pos)) /* Assignment of value for GP1 in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_GP2_Pos            _UINT32_(18)                                         /* (RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_GP2_Msk            (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_GP2_Pos)        /* (RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_GP2(value)         (RTC_MODE1_SYNCBUSY_GP2_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_GP2_Pos)) /* Assignment of value for GP2 in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_GP3_Pos            _UINT32_(19)                                         /* (RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy Position */
+#define RTC_MODE1_SYNCBUSY_GP3_Msk            (_UINT32_(0x1) << RTC_MODE1_SYNCBUSY_GP3_Pos)        /* (RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy Mask */
+#define RTC_MODE1_SYNCBUSY_GP3(value)         (RTC_MODE1_SYNCBUSY_GP3_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_GP3_Pos)) /* Assignment of value for GP3 in the RTC_MODE1_SYNCBUSY register */
+#define RTC_MODE1_SYNCBUSY_Msk                _UINT32_(0x000F81FF)                                 /* (RTC_MODE1_SYNCBUSY) Register Mask  */
+
+#define RTC_MODE1_SYNCBUSY_COMP_Pos           _UINT32_(5)                                          /* (RTC_MODE1_SYNCBUSY Position) COMP x Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP_Msk           (_UINT32_(0xF) << RTC_MODE1_SYNCBUSY_COMP_Pos)       /* (RTC_MODE1_SYNCBUSY Mask) COMP */
+#define RTC_MODE1_SYNCBUSY_COMP(value)        (RTC_MODE1_SYNCBUSY_COMP_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_COMP_Pos)) 
+#define RTC_MODE1_SYNCBUSY_GP_Pos             _UINT32_(16)                                         /* (RTC_MODE1_SYNCBUSY Position) General Purpose 3 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP_Msk             (_UINT32_(0xF) << RTC_MODE1_SYNCBUSY_GP_Pos)         /* (RTC_MODE1_SYNCBUSY Mask) GP */
+#define RTC_MODE1_SYNCBUSY_GP(value)          (RTC_MODE1_SYNCBUSY_GP_Msk & (_UINT32_(value) << RTC_MODE1_SYNCBUSY_GP_Pos)) 
+
+/* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) ( R/ 32) MODE2 Synchronization Busy Status -------- */
+#define RTC_MODE2_SYNCBUSY_RESETVALUE         _UINT32_(0x00)                                       /*  (RTC_MODE2_SYNCBUSY) MODE2 Synchronization Busy Status  Reset Value */
+
+#define RTC_MODE2_SYNCBUSY_SWRST_Pos          _UINT32_(0)                                          /* (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy Position */
+#define RTC_MODE2_SYNCBUSY_SWRST_Msk          (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos)      /* (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy Mask */
+#define RTC_MODE2_SYNCBUSY_SWRST(value)       (RTC_MODE2_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_ENABLE_Pos         _UINT32_(1)                                          /* (RTC_MODE2_SYNCBUSY) Enable Bit Busy Position */
+#define RTC_MODE2_SYNCBUSY_ENABLE_Msk         (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)     /* (RTC_MODE2_SYNCBUSY) Enable Bit Busy Mask */
+#define RTC_MODE2_SYNCBUSY_ENABLE(value)      (RTC_MODE2_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_FREQCORR_Pos       _UINT32_(2)                                          /* (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy Position */
+#define RTC_MODE2_SYNCBUSY_FREQCORR_Msk       (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)   /* (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy Mask */
+#define RTC_MODE2_SYNCBUSY_FREQCORR(value)    (RTC_MODE2_SYNCBUSY_FREQCORR_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)) /* Assignment of value for FREQCORR in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_CLOCK_Pos          _UINT32_(3)                                          /* (RTC_MODE2_SYNCBUSY) CLOCK Register Busy Position */
+#define RTC_MODE2_SYNCBUSY_CLOCK_Msk          (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)      /* (RTC_MODE2_SYNCBUSY) CLOCK Register Busy Mask */
+#define RTC_MODE2_SYNCBUSY_CLOCK(value)       (RTC_MODE2_SYNCBUSY_CLOCK_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)) /* Assignment of value for CLOCK in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_ALARM0_Pos         _UINT32_(5)                                          /* (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy Position */
+#define RTC_MODE2_SYNCBUSY_ALARM0_Msk         (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)     /* (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy Mask */
+#define RTC_MODE2_SYNCBUSY_ALARM0(value)      (RTC_MODE2_SYNCBUSY_ALARM0_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)) /* Assignment of value for ALARM0 in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_ALARM1_Pos         _UINT32_(6)                                          /* (RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy Position */
+#define RTC_MODE2_SYNCBUSY_ALARM1_Msk         (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)     /* (RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy Mask */
+#define RTC_MODE2_SYNCBUSY_ALARM1(value)      (RTC_MODE2_SYNCBUSY_ALARM1_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)) /* Assignment of value for ALARM1 in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_MASK0_Pos          _UINT32_(11)                                         /* (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy Position */
+#define RTC_MODE2_SYNCBUSY_MASK0_Msk          (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_MASK0_Pos)      /* (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy Mask */
+#define RTC_MODE2_SYNCBUSY_MASK0(value)       (RTC_MODE2_SYNCBUSY_MASK0_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_MASK0_Pos)) /* Assignment of value for MASK0 in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_MASK1_Pos          _UINT32_(12)                                         /* (RTC_MODE2_SYNCBUSY) MASK 1 Register Busy Position */
+#define RTC_MODE2_SYNCBUSY_MASK1_Msk          (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_MASK1_Pos)      /* (RTC_MODE2_SYNCBUSY) MASK 1 Register Busy Mask */
+#define RTC_MODE2_SYNCBUSY_MASK1(value)       (RTC_MODE2_SYNCBUSY_MASK1_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_MASK1_Pos)) /* Assignment of value for MASK1 in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos      _UINT32_(15)                                         /* (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy Position */
+#define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Msk      (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)  /* (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy Mask */
+#define RTC_MODE2_SYNCBUSY_CLOCKSYNC(value)   (RTC_MODE2_SYNCBUSY_CLOCKSYNC_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)) /* Assignment of value for CLOCKSYNC in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_GP0_Pos            _UINT32_(16)                                         /* (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy Position */
+#define RTC_MODE2_SYNCBUSY_GP0_Msk            (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_GP0_Pos)        /* (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy Mask */
+#define RTC_MODE2_SYNCBUSY_GP0(value)         (RTC_MODE2_SYNCBUSY_GP0_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_GP0_Pos)) /* Assignment of value for GP0 in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_GP1_Pos            _UINT32_(17)                                         /* (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy Position */
+#define RTC_MODE2_SYNCBUSY_GP1_Msk            (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_GP1_Pos)        /* (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy Mask */
+#define RTC_MODE2_SYNCBUSY_GP1(value)         (RTC_MODE2_SYNCBUSY_GP1_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_GP1_Pos)) /* Assignment of value for GP1 in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_GP2_Pos            _UINT32_(18)                                         /* (RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy Position */
+#define RTC_MODE2_SYNCBUSY_GP2_Msk            (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_GP2_Pos)        /* (RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy Mask */
+#define RTC_MODE2_SYNCBUSY_GP2(value)         (RTC_MODE2_SYNCBUSY_GP2_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_GP2_Pos)) /* Assignment of value for GP2 in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_GP3_Pos            _UINT32_(19)                                         /* (RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy Position */
+#define RTC_MODE2_SYNCBUSY_GP3_Msk            (_UINT32_(0x1) << RTC_MODE2_SYNCBUSY_GP3_Pos)        /* (RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy Mask */
+#define RTC_MODE2_SYNCBUSY_GP3(value)         (RTC_MODE2_SYNCBUSY_GP3_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_GP3_Pos)) /* Assignment of value for GP3 in the RTC_MODE2_SYNCBUSY register */
+#define RTC_MODE2_SYNCBUSY_Msk                _UINT32_(0x000F986F)                                 /* (RTC_MODE2_SYNCBUSY) Register Mask  */
+
+#define RTC_MODE2_SYNCBUSY_ALARM_Pos          _UINT32_(5)                                          /* (RTC_MODE2_SYNCBUSY Position) ALARM x Register Busy */
+#define RTC_MODE2_SYNCBUSY_ALARM_Msk          (_UINT32_(0x3) << RTC_MODE2_SYNCBUSY_ALARM_Pos)      /* (RTC_MODE2_SYNCBUSY Mask) ALARM */
+#define RTC_MODE2_SYNCBUSY_ALARM(value)       (RTC_MODE2_SYNCBUSY_ALARM_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_ALARM_Pos)) 
+#define RTC_MODE2_SYNCBUSY_MASK_Pos           _UINT32_(11)                                         /* (RTC_MODE2_SYNCBUSY Position) MASK x Register Busy */
+#define RTC_MODE2_SYNCBUSY_MASK_Msk           (_UINT32_(0x3) << RTC_MODE2_SYNCBUSY_MASK_Pos)       /* (RTC_MODE2_SYNCBUSY Mask) MASK */
+#define RTC_MODE2_SYNCBUSY_MASK(value)        (RTC_MODE2_SYNCBUSY_MASK_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_MASK_Pos)) 
+#define RTC_MODE2_SYNCBUSY_GP_Pos             _UINT32_(16)                                         /* (RTC_MODE2_SYNCBUSY Position) General Purpose 3 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP_Msk             (_UINT32_(0xF) << RTC_MODE2_SYNCBUSY_GP_Pos)         /* (RTC_MODE2_SYNCBUSY Mask) GP */
+#define RTC_MODE2_SYNCBUSY_GP(value)          (RTC_MODE2_SYNCBUSY_GP_Msk & (_UINT32_(value) << RTC_MODE2_SYNCBUSY_GP_Pos)) 
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */
+#define RTC_FREQCORR_RESETVALUE               _UINT8_(0x00)                                        /*  (RTC_FREQCORR) Frequency Correction  Reset Value */
+
+#define RTC_FREQCORR_VALUE_Pos                _UINT8_(0)                                           /* (RTC_FREQCORR) Correction Value Position */
+#define RTC_FREQCORR_VALUE_Msk                (_UINT8_(0x7F) << RTC_FREQCORR_VALUE_Pos)            /* (RTC_FREQCORR) Correction Value Mask */
+#define RTC_FREQCORR_VALUE(value)             (RTC_FREQCORR_VALUE_Msk & (_UINT8_(value) << RTC_FREQCORR_VALUE_Pos)) /* Assignment of value for VALUE in the RTC_FREQCORR register */
+#define RTC_FREQCORR_SIGN_Pos                 _UINT8_(7)                                           /* (RTC_FREQCORR) Correction Sign Position */
+#define RTC_FREQCORR_SIGN_Msk                 (_UINT8_(0x1) << RTC_FREQCORR_SIGN_Pos)              /* (RTC_FREQCORR) Correction Sign Mask */
+#define RTC_FREQCORR_SIGN(value)              (RTC_FREQCORR_SIGN_Msk & (_UINT8_(value) << RTC_FREQCORR_SIGN_Pos)) /* Assignment of value for SIGN in the RTC_FREQCORR register */
+#define RTC_FREQCORR_Msk                      _UINT8_(0xFF)                                        /* (RTC_FREQCORR) Register Mask  */
+
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 Counter Value -------- */
+#define RTC_MODE0_COUNT_RESETVALUE            _UINT32_(0x00)                                       /*  (RTC_MODE0_COUNT) MODE0 Counter Value  Reset Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos             _UINT32_(0)                                          /* (RTC_MODE0_COUNT) Counter Value Position */
+#define RTC_MODE0_COUNT_COUNT_Msk             (_UINT32_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)  /* (RTC_MODE0_COUNT) Counter Value Mask */
+#define RTC_MODE0_COUNT_COUNT(value)          (RTC_MODE0_COUNT_COUNT_Msk & (_UINT32_(value) << RTC_MODE0_COUNT_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE0_COUNT register */
+#define RTC_MODE0_COUNT_Msk                   _UINT32_(0xFFFFFFFF)                                 /* (RTC_MODE0_COUNT) Register Mask  */
+
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 Counter Value -------- */
+#define RTC_MODE1_COUNT_RESETVALUE            _UINT16_(0x00)                                       /*  (RTC_MODE1_COUNT) MODE1 Counter Value  Reset Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos             _UINT16_(0)                                          /* (RTC_MODE1_COUNT) Counter Value Position */
+#define RTC_MODE1_COUNT_COUNT_Msk             (_UINT16_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)      /* (RTC_MODE1_COUNT) Counter Value Mask */
+#define RTC_MODE1_COUNT_COUNT(value)          (RTC_MODE1_COUNT_COUNT_Msk & (_UINT16_(value) << RTC_MODE1_COUNT_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE1_COUNT register */
+#define RTC_MODE1_COUNT_Msk                   _UINT16_(0xFFFF)                                     /* (RTC_MODE1_COUNT) Register Mask  */
+
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 Clock Value -------- */
+#define RTC_MODE2_CLOCK_RESETVALUE            _UINT32_(0x00)                                       /*  (RTC_MODE2_CLOCK) MODE2 Clock Value  Reset Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos            _UINT32_(0)                                          /* (RTC_MODE2_CLOCK) Second Position */
+#define RTC_MODE2_CLOCK_SECOND_Msk            (_UINT32_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)       /* (RTC_MODE2_CLOCK) Second Mask */
+#define RTC_MODE2_CLOCK_SECOND(value)         (RTC_MODE2_CLOCK_SECOND_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_SECOND_Pos)) /* Assignment of value for SECOND in the RTC_MODE2_CLOCK register */
+#define RTC_MODE2_CLOCK_MINUTE_Pos            _UINT32_(6)                                          /* (RTC_MODE2_CLOCK) Minute Position */
+#define RTC_MODE2_CLOCK_MINUTE_Msk            (_UINT32_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)       /* (RTC_MODE2_CLOCK) Minute Mask */
+#define RTC_MODE2_CLOCK_MINUTE(value)         (RTC_MODE2_CLOCK_MINUTE_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_MINUTE_Pos)) /* Assignment of value for MINUTE in the RTC_MODE2_CLOCK register */
+#define RTC_MODE2_CLOCK_HOUR_Pos              _UINT32_(12)                                         /* (RTC_MODE2_CLOCK) Hour Position */
+#define RTC_MODE2_CLOCK_HOUR_Msk              (_UINT32_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)         /* (RTC_MODE2_CLOCK) Hour Mask */
+#define RTC_MODE2_CLOCK_HOUR(value)           (RTC_MODE2_CLOCK_HOUR_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_HOUR_Pos)) /* Assignment of value for HOUR in the RTC_MODE2_CLOCK register */
+#define RTC_MODE2_CLOCK_DAY_Pos               _UINT32_(17)                                         /* (RTC_MODE2_CLOCK) Day Position */
+#define RTC_MODE2_CLOCK_DAY_Msk               (_UINT32_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)          /* (RTC_MODE2_CLOCK) Day Mask */
+#define RTC_MODE2_CLOCK_DAY(value)            (RTC_MODE2_CLOCK_DAY_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_DAY_Pos)) /* Assignment of value for DAY in the RTC_MODE2_CLOCK register */
+#define RTC_MODE2_CLOCK_MONTH_Pos             _UINT32_(22)                                         /* (RTC_MODE2_CLOCK) Month Position */
+#define RTC_MODE2_CLOCK_MONTH_Msk             (_UINT32_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)         /* (RTC_MODE2_CLOCK) Month Mask */
+#define RTC_MODE2_CLOCK_MONTH(value)          (RTC_MODE2_CLOCK_MONTH_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_MONTH_Pos)) /* Assignment of value for MONTH in the RTC_MODE2_CLOCK register */
+#define RTC_MODE2_CLOCK_YEAR_Pos              _UINT32_(26)                                         /* (RTC_MODE2_CLOCK) Year Position */
+#define RTC_MODE2_CLOCK_YEAR_Msk              (_UINT32_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)         /* (RTC_MODE2_CLOCK) Year Mask */
+#define RTC_MODE2_CLOCK_YEAR(value)           (RTC_MODE2_CLOCK_YEAR_Msk & (_UINT32_(value) << RTC_MODE2_CLOCK_YEAR_Pos)) /* Assignment of value for YEAR in the RTC_MODE2_CLOCK register */
+#define RTC_MODE2_CLOCK_Msk                   _UINT32_(0xFFFFFFFF)                                 /* (RTC_MODE2_CLOCK) Register Mask  */
+
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 Counter Period -------- */
+#define RTC_MODE1_PER_RESETVALUE              _UINT16_(0x00)                                       /*  (RTC_MODE1_PER) MODE1 Counter Period  Reset Value */
+
+#define RTC_MODE1_PER_PER_Pos                 _UINT16_(0)                                          /* (RTC_MODE1_PER) Counter Period Position */
+#define RTC_MODE1_PER_PER_Msk                 (_UINT16_(0xFFFF) << RTC_MODE1_PER_PER_Pos)          /* (RTC_MODE1_PER) Counter Period Mask */
+#define RTC_MODE1_PER_PER(value)              (RTC_MODE1_PER_PER_Msk & (_UINT16_(value) << RTC_MODE1_PER_PER_Pos)) /* Assignment of value for PER in the RTC_MODE1_PER register */
+#define RTC_MODE1_PER_Msk                     _UINT16_(0xFFFF)                                     /* (RTC_MODE1_PER) Register Mask  */
+
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 Compare n Value -------- */
+#define RTC_MODE0_COMP_RESETVALUE             _UINT32_(0x00)                                       /*  (RTC_MODE0_COMP) MODE0 Compare n Value  Reset Value */
+
+#define RTC_MODE0_COMP_COMP_Pos               _UINT32_(0)                                          /* (RTC_MODE0_COMP) Compare Value Position */
+#define RTC_MODE0_COMP_COMP_Msk               (_UINT32_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)    /* (RTC_MODE0_COMP) Compare Value Mask */
+#define RTC_MODE0_COMP_COMP(value)            (RTC_MODE0_COMP_COMP_Msk & (_UINT32_(value) << RTC_MODE0_COMP_COMP_Pos)) /* Assignment of value for COMP in the RTC_MODE0_COMP register */
+#define RTC_MODE0_COMP_Msk                    _UINT32_(0xFFFFFFFF)                                 /* (RTC_MODE0_COMP) Register Mask  */
+
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 Compare n Value -------- */
+#define RTC_MODE1_COMP_RESETVALUE             _UINT16_(0x00)                                       /*  (RTC_MODE1_COMP) MODE1 Compare n Value  Reset Value */
+
+#define RTC_MODE1_COMP_COMP_Pos               _UINT16_(0)                                          /* (RTC_MODE1_COMP) Compare Value Position */
+#define RTC_MODE1_COMP_COMP_Msk               (_UINT16_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)        /* (RTC_MODE1_COMP) Compare Value Mask */
+#define RTC_MODE1_COMP_COMP(value)            (RTC_MODE1_COMP_COMP_Msk & (_UINT16_(value) << RTC_MODE1_COMP_COMP_Pos)) /* Assignment of value for COMP in the RTC_MODE1_COMP register */
+#define RTC_MODE1_COMP_Msk                    _UINT16_(0xFFFF)                                     /* (RTC_MODE1_COMP) Register Mask  */
+
+
+/* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */
+#define RTC_GP_RESETVALUE                     _UINT32_(0x00)                                       /*  (RTC_GP) General Purpose  Reset Value */
+
+#define RTC_GP_GP_Pos                         _UINT32_(0)                                          /* (RTC_GP) General Purpose Position */
+#define RTC_GP_GP_Msk                         (_UINT32_(0xFFFFFFFF) << RTC_GP_GP_Pos)              /* (RTC_GP) General Purpose Mask */
+#define RTC_GP_GP(value)                      (RTC_GP_GP_Msk & (_UINT32_(value) << RTC_GP_GP_Pos)) /* Assignment of value for GP in the RTC_GP register */
+#define RTC_GP_Msk                            _UINT32_(0xFFFFFFFF)                                 /* (RTC_GP) Register Mask  */
+
+
+/* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */
+#define RTC_TAMPCTRL_RESETVALUE               _UINT32_(0x00)                                       /*  (RTC_TAMPCTRL) Tamper Control  Reset Value */
+
+#define RTC_TAMPCTRL_IN0ACT_Pos               _UINT32_(0)                                          /* (RTC_TAMPCTRL) Tamper Input 0 Action Position */
+#define RTC_TAMPCTRL_IN0ACT_Msk               (_UINT32_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos)           /* (RTC_TAMPCTRL) Tamper Input 0 Action Mask */
+#define RTC_TAMPCTRL_IN0ACT(value)            (RTC_TAMPCTRL_IN0ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN0ACT_Pos)) /* Assignment of value for IN0ACT in the RTC_TAMPCTRL register */
+#define   RTC_TAMPCTRL_IN0ACT_OFF_Val         _UINT32_(0x0)                                        /* (RTC_TAMPCTRL) Off (Disabled)  */
+#define   RTC_TAMPCTRL_IN0ACT_WAKE_Val        _UINT32_(0x1)                                        /* (RTC_TAMPCTRL) Wake and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN0ACT_CAPTURE_Val     _UINT32_(0x2)                                        /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN0ACT_ACTL_Val        _UINT32_(0x3)                                        /* (RTC_TAMPCTRL) Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
+#define RTC_TAMPCTRL_IN0ACT_OFF               (RTC_TAMPCTRL_IN0ACT_OFF_Val << RTC_TAMPCTRL_IN0ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */
+#define RTC_TAMPCTRL_IN0ACT_WAKE              (RTC_TAMPCTRL_IN0ACT_WAKE_Val << RTC_TAMPCTRL_IN0ACT_Pos) /* (RTC_TAMPCTRL) Wake and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN0ACT_CAPTURE           (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN0ACT_ACTL              (RTC_TAMPCTRL_IN0ACT_ACTL_Val << RTC_TAMPCTRL_IN0ACT_Pos) /* (RTC_TAMPCTRL) Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN1ACT_Pos               _UINT32_(2)                                          /* (RTC_TAMPCTRL) Tamper Input 1 Action Position */
+#define RTC_TAMPCTRL_IN1ACT_Msk               (_UINT32_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos)           /* (RTC_TAMPCTRL) Tamper Input 1 Action Mask */
+#define RTC_TAMPCTRL_IN1ACT(value)            (RTC_TAMPCTRL_IN1ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN1ACT_Pos)) /* Assignment of value for IN1ACT in the RTC_TAMPCTRL register */
+#define   RTC_TAMPCTRL_IN1ACT_OFF_Val         _UINT32_(0x0)                                        /* (RTC_TAMPCTRL) Off (Disabled)  */
+#define   RTC_TAMPCTRL_IN1ACT_WAKE_Val        _UINT32_(0x1)                                        /* (RTC_TAMPCTRL) Wake and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN1ACT_CAPTURE_Val     _UINT32_(0x2)                                        /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN1ACT_ACTL_Val        _UINT32_(0x3)                                        /* (RTC_TAMPCTRL) Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
+#define RTC_TAMPCTRL_IN1ACT_OFF               (RTC_TAMPCTRL_IN1ACT_OFF_Val << RTC_TAMPCTRL_IN1ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */
+#define RTC_TAMPCTRL_IN1ACT_WAKE              (RTC_TAMPCTRL_IN1ACT_WAKE_Val << RTC_TAMPCTRL_IN1ACT_Pos) /* (RTC_TAMPCTRL) Wake and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN1ACT_CAPTURE           (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN1ACT_ACTL              (RTC_TAMPCTRL_IN1ACT_ACTL_Val << RTC_TAMPCTRL_IN1ACT_Pos) /* (RTC_TAMPCTRL) Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN2ACT_Pos               _UINT32_(4)                                          /* (RTC_TAMPCTRL) Tamper Input 2 Action Position */
+#define RTC_TAMPCTRL_IN2ACT_Msk               (_UINT32_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos)           /* (RTC_TAMPCTRL) Tamper Input 2 Action Mask */
+#define RTC_TAMPCTRL_IN2ACT(value)            (RTC_TAMPCTRL_IN2ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN2ACT_Pos)) /* Assignment of value for IN2ACT in the RTC_TAMPCTRL register */
+#define   RTC_TAMPCTRL_IN2ACT_OFF_Val         _UINT32_(0x0)                                        /* (RTC_TAMPCTRL) Off (Disabled)  */
+#define   RTC_TAMPCTRL_IN2ACT_WAKE_Val        _UINT32_(0x1)                                        /* (RTC_TAMPCTRL) Wake and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN2ACT_CAPTURE_Val     _UINT32_(0x2)                                        /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN2ACT_ACTL_Val        _UINT32_(0x3)                                        /* (RTC_TAMPCTRL) Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
+#define RTC_TAMPCTRL_IN2ACT_OFF               (RTC_TAMPCTRL_IN2ACT_OFF_Val << RTC_TAMPCTRL_IN2ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */
+#define RTC_TAMPCTRL_IN2ACT_WAKE              (RTC_TAMPCTRL_IN2ACT_WAKE_Val << RTC_TAMPCTRL_IN2ACT_Pos) /* (RTC_TAMPCTRL) Wake and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN2ACT_CAPTURE           (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN2ACT_ACTL              (RTC_TAMPCTRL_IN2ACT_ACTL_Val << RTC_TAMPCTRL_IN2ACT_Pos) /* (RTC_TAMPCTRL) Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN3ACT_Pos               _UINT32_(6)                                          /* (RTC_TAMPCTRL) Tamper Input 3 Action Position */
+#define RTC_TAMPCTRL_IN3ACT_Msk               (_UINT32_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos)           /* (RTC_TAMPCTRL) Tamper Input 3 Action Mask */
+#define RTC_TAMPCTRL_IN3ACT(value)            (RTC_TAMPCTRL_IN3ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN3ACT_Pos)) /* Assignment of value for IN3ACT in the RTC_TAMPCTRL register */
+#define   RTC_TAMPCTRL_IN3ACT_OFF_Val         _UINT32_(0x0)                                        /* (RTC_TAMPCTRL) Off (Disabled)  */
+#define   RTC_TAMPCTRL_IN3ACT_WAKE_Val        _UINT32_(0x1)                                        /* (RTC_TAMPCTRL) Wake and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN3ACT_CAPTURE_Val     _UINT32_(0x2)                                        /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN3ACT_ACTL_Val        _UINT32_(0x3)                                        /* (RTC_TAMPCTRL) Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
+#define RTC_TAMPCTRL_IN3ACT_OFF               (RTC_TAMPCTRL_IN3ACT_OFF_Val << RTC_TAMPCTRL_IN3ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */
+#define RTC_TAMPCTRL_IN3ACT_WAKE              (RTC_TAMPCTRL_IN3ACT_WAKE_Val << RTC_TAMPCTRL_IN3ACT_Pos) /* (RTC_TAMPCTRL) Wake and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN3ACT_CAPTURE           (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN3ACT_ACTL              (RTC_TAMPCTRL_IN3ACT_ACTL_Val << RTC_TAMPCTRL_IN3ACT_Pos) /* (RTC_TAMPCTRL) Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN4ACT_Pos               _UINT32_(8)                                          /* (RTC_TAMPCTRL) Tamper Input 4 Action Position */
+#define RTC_TAMPCTRL_IN4ACT_Msk               (_UINT32_(0x3) << RTC_TAMPCTRL_IN4ACT_Pos)           /* (RTC_TAMPCTRL) Tamper Input 4 Action Mask */
+#define RTC_TAMPCTRL_IN4ACT(value)            (RTC_TAMPCTRL_IN4ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN4ACT_Pos)) /* Assignment of value for IN4ACT in the RTC_TAMPCTRL register */
+#define   RTC_TAMPCTRL_IN4ACT_OFF_Val         _UINT32_(0x0)                                        /* (RTC_TAMPCTRL) Off (Disabled)  */
+#define   RTC_TAMPCTRL_IN4ACT_WAKE_Val        _UINT32_(0x1)                                        /* (RTC_TAMPCTRL) Wake and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN4ACT_CAPTURE_Val     _UINT32_(0x2)                                        /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN4ACT_ACTL_Val        _UINT32_(0x3)                                        /* (RTC_TAMPCTRL) Compare IN4 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
+#define RTC_TAMPCTRL_IN4ACT_OFF               (RTC_TAMPCTRL_IN4ACT_OFF_Val << RTC_TAMPCTRL_IN4ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */
+#define RTC_TAMPCTRL_IN4ACT_WAKE              (RTC_TAMPCTRL_IN4ACT_WAKE_Val << RTC_TAMPCTRL_IN4ACT_Pos) /* (RTC_TAMPCTRL) Wake and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN4ACT_CAPTURE           (RTC_TAMPCTRL_IN4ACT_CAPTURE_Val << RTC_TAMPCTRL_IN4ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN4ACT_ACTL              (RTC_TAMPCTRL_IN4ACT_ACTL_Val << RTC_TAMPCTRL_IN4ACT_Pos) /* (RTC_TAMPCTRL) Compare IN4 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN5ACT_Pos               _UINT32_(10)                                         /* (RTC_TAMPCTRL) Tamper Input 5 Action Position */
+#define RTC_TAMPCTRL_IN5ACT_Msk               (_UINT32_(0x3) << RTC_TAMPCTRL_IN5ACT_Pos)           /* (RTC_TAMPCTRL) Tamper Input 5 Action Mask */
+#define RTC_TAMPCTRL_IN5ACT(value)            (RTC_TAMPCTRL_IN5ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN5ACT_Pos)) /* Assignment of value for IN5ACT in the RTC_TAMPCTRL register */
+#define   RTC_TAMPCTRL_IN5ACT_OFF_Val         _UINT32_(0x0)                                        /* (RTC_TAMPCTRL) Off (Disabled)  */
+#define   RTC_TAMPCTRL_IN5ACT_WAKE_Val        _UINT32_(0x1)                                        /* (RTC_TAMPCTRL) Wake and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN5ACT_CAPTURE_Val     _UINT32_(0x2)                                        /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN5ACT_ACTL_Val        _UINT32_(0x3)                                        /* (RTC_TAMPCTRL) Compare IN5 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
+#define RTC_TAMPCTRL_IN5ACT_OFF               (RTC_TAMPCTRL_IN5ACT_OFF_Val << RTC_TAMPCTRL_IN5ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */
+#define RTC_TAMPCTRL_IN5ACT_WAKE              (RTC_TAMPCTRL_IN5ACT_WAKE_Val << RTC_TAMPCTRL_IN5ACT_Pos) /* (RTC_TAMPCTRL) Wake and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN5ACT_CAPTURE           (RTC_TAMPCTRL_IN5ACT_CAPTURE_Val << RTC_TAMPCTRL_IN5ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN5ACT_ACTL              (RTC_TAMPCTRL_IN5ACT_ACTL_Val << RTC_TAMPCTRL_IN5ACT_Pos) /* (RTC_TAMPCTRL) Compare IN5 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN6ACT_Pos               _UINT32_(12)                                         /* (RTC_TAMPCTRL) Tamper Input 6 Action Position */
+#define RTC_TAMPCTRL_IN6ACT_Msk               (_UINT32_(0x3) << RTC_TAMPCTRL_IN6ACT_Pos)           /* (RTC_TAMPCTRL) Tamper Input 6 Action Mask */
+#define RTC_TAMPCTRL_IN6ACT(value)            (RTC_TAMPCTRL_IN6ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN6ACT_Pos)) /* Assignment of value for IN6ACT in the RTC_TAMPCTRL register */
+#define   RTC_TAMPCTRL_IN6ACT_OFF_Val         _UINT32_(0x0)                                        /* (RTC_TAMPCTRL) Off (Disabled)  */
+#define   RTC_TAMPCTRL_IN6ACT_WAKE_Val        _UINT32_(0x1)                                        /* (RTC_TAMPCTRL) Wake and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN6ACT_CAPTURE_Val     _UINT32_(0x2)                                        /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN6ACT_ACTL_Val        _UINT32_(0x3)                                        /* (RTC_TAMPCTRL) Compare IN6 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
+#define RTC_TAMPCTRL_IN6ACT_OFF               (RTC_TAMPCTRL_IN6ACT_OFF_Val << RTC_TAMPCTRL_IN6ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */
+#define RTC_TAMPCTRL_IN6ACT_WAKE              (RTC_TAMPCTRL_IN6ACT_WAKE_Val << RTC_TAMPCTRL_IN6ACT_Pos) /* (RTC_TAMPCTRL) Wake and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN6ACT_CAPTURE           (RTC_TAMPCTRL_IN6ACT_CAPTURE_Val << RTC_TAMPCTRL_IN6ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN6ACT_ACTL              (RTC_TAMPCTRL_IN6ACT_ACTL_Val << RTC_TAMPCTRL_IN6ACT_Pos) /* (RTC_TAMPCTRL) Compare IN6 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN7ACT_Pos               _UINT32_(14)                                         /* (RTC_TAMPCTRL) Tamper Input 7 Action Position */
+#define RTC_TAMPCTRL_IN7ACT_Msk               (_UINT32_(0x3) << RTC_TAMPCTRL_IN7ACT_Pos)           /* (RTC_TAMPCTRL) Tamper Input 7 Action Mask */
+#define RTC_TAMPCTRL_IN7ACT(value)            (RTC_TAMPCTRL_IN7ACT_Msk & (_UINT32_(value) << RTC_TAMPCTRL_IN7ACT_Pos)) /* Assignment of value for IN7ACT in the RTC_TAMPCTRL register */
+#define   RTC_TAMPCTRL_IN7ACT_OFF_Val         _UINT32_(0x0)                                        /* (RTC_TAMPCTRL) Off (Disabled)  */
+#define   RTC_TAMPCTRL_IN7ACT_WAKE_Val        _UINT32_(0x1)                                        /* (RTC_TAMPCTRL) Wake and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN7ACT_CAPTURE_Val     _UINT32_(0x2)                                        /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
+#define   RTC_TAMPCTRL_IN7ACT_ACTL_Val        _UINT32_(0x3)                                        /* (RTC_TAMPCTRL) Compare IN7 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
+#define RTC_TAMPCTRL_IN7ACT_OFF               (RTC_TAMPCTRL_IN7ACT_OFF_Val << RTC_TAMPCTRL_IN7ACT_Pos) /* (RTC_TAMPCTRL) Off (Disabled) Position */
+#define RTC_TAMPCTRL_IN7ACT_WAKE              (RTC_TAMPCTRL_IN7ACT_WAKE_Val << RTC_TAMPCTRL_IN7ACT_Pos) /* (RTC_TAMPCTRL) Wake and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN7ACT_CAPTURE           (RTC_TAMPCTRL_IN7ACT_CAPTURE_Val << RTC_TAMPCTRL_IN7ACT_Pos) /* (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_IN7ACT_ACTL              (RTC_TAMPCTRL_IN7ACT_ACTL_Val << RTC_TAMPCTRL_IN7ACT_Pos) /* (RTC_TAMPCTRL) Compare IN7 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position */
+#define RTC_TAMPCTRL_TAMLVL0_Pos              _UINT32_(16)                                         /* (RTC_TAMPCTRL) Tamper Level Select 0 Position */
+#define RTC_TAMPCTRL_TAMLVL0_Msk              (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL0_Pos)          /* (RTC_TAMPCTRL) Tamper Level Select 0 Mask */
+#define RTC_TAMPCTRL_TAMLVL0(value)           (RTC_TAMPCTRL_TAMLVL0_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL0_Pos)) /* Assignment of value for TAMLVL0 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_TAMLVL1_Pos              _UINT32_(17)                                         /* (RTC_TAMPCTRL) Tamper Level Select 1 Position */
+#define RTC_TAMPCTRL_TAMLVL1_Msk              (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL1_Pos)          /* (RTC_TAMPCTRL) Tamper Level Select 1 Mask */
+#define RTC_TAMPCTRL_TAMLVL1(value)           (RTC_TAMPCTRL_TAMLVL1_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL1_Pos)) /* Assignment of value for TAMLVL1 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_TAMLVL2_Pos              _UINT32_(18)                                         /* (RTC_TAMPCTRL) Tamper Level Select 2 Position */
+#define RTC_TAMPCTRL_TAMLVL2_Msk              (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL2_Pos)          /* (RTC_TAMPCTRL) Tamper Level Select 2 Mask */
+#define RTC_TAMPCTRL_TAMLVL2(value)           (RTC_TAMPCTRL_TAMLVL2_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL2_Pos)) /* Assignment of value for TAMLVL2 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_TAMLVL3_Pos              _UINT32_(19)                                         /* (RTC_TAMPCTRL) Tamper Level Select 3 Position */
+#define RTC_TAMPCTRL_TAMLVL3_Msk              (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL3_Pos)          /* (RTC_TAMPCTRL) Tamper Level Select 3 Mask */
+#define RTC_TAMPCTRL_TAMLVL3(value)           (RTC_TAMPCTRL_TAMLVL3_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL3_Pos)) /* Assignment of value for TAMLVL3 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_TAMLVL4_Pos              _UINT32_(20)                                         /* (RTC_TAMPCTRL) Tamper Level Select 4 Position */
+#define RTC_TAMPCTRL_TAMLVL4_Msk              (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL4_Pos)          /* (RTC_TAMPCTRL) Tamper Level Select 4 Mask */
+#define RTC_TAMPCTRL_TAMLVL4(value)           (RTC_TAMPCTRL_TAMLVL4_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL4_Pos)) /* Assignment of value for TAMLVL4 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_TAMLVL5_Pos              _UINT32_(21)                                         /* (RTC_TAMPCTRL) Tamper Level Select 5 Position */
+#define RTC_TAMPCTRL_TAMLVL5_Msk              (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL5_Pos)          /* (RTC_TAMPCTRL) Tamper Level Select 5 Mask */
+#define RTC_TAMPCTRL_TAMLVL5(value)           (RTC_TAMPCTRL_TAMLVL5_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL5_Pos)) /* Assignment of value for TAMLVL5 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_TAMLVL6_Pos              _UINT32_(22)                                         /* (RTC_TAMPCTRL) Tamper Level Select 6 Position */
+#define RTC_TAMPCTRL_TAMLVL6_Msk              (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL6_Pos)          /* (RTC_TAMPCTRL) Tamper Level Select 6 Mask */
+#define RTC_TAMPCTRL_TAMLVL6(value)           (RTC_TAMPCTRL_TAMLVL6_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL6_Pos)) /* Assignment of value for TAMLVL6 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_TAMLVL7_Pos              _UINT32_(23)                                         /* (RTC_TAMPCTRL) Tamper Level Select 7 Position */
+#define RTC_TAMPCTRL_TAMLVL7_Msk              (_UINT32_(0x1) << RTC_TAMPCTRL_TAMLVL7_Pos)          /* (RTC_TAMPCTRL) Tamper Level Select 7 Mask */
+#define RTC_TAMPCTRL_TAMLVL7(value)           (RTC_TAMPCTRL_TAMLVL7_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL7_Pos)) /* Assignment of value for TAMLVL7 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_DEBNC0_Pos               _UINT32_(24)                                         /* (RTC_TAMPCTRL) Debouncer Enable 0 Position */
+#define RTC_TAMPCTRL_DEBNC0_Msk               (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC0_Pos)           /* (RTC_TAMPCTRL) Debouncer Enable 0 Mask */
+#define RTC_TAMPCTRL_DEBNC0(value)            (RTC_TAMPCTRL_DEBNC0_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC0_Pos)) /* Assignment of value for DEBNC0 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_DEBNC1_Pos               _UINT32_(25)                                         /* (RTC_TAMPCTRL) Debouncer Enable 1 Position */
+#define RTC_TAMPCTRL_DEBNC1_Msk               (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC1_Pos)           /* (RTC_TAMPCTRL) Debouncer Enable 1 Mask */
+#define RTC_TAMPCTRL_DEBNC1(value)            (RTC_TAMPCTRL_DEBNC1_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC1_Pos)) /* Assignment of value for DEBNC1 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_DEBNC2_Pos               _UINT32_(26)                                         /* (RTC_TAMPCTRL) Debouncer Enable 2 Position */
+#define RTC_TAMPCTRL_DEBNC2_Msk               (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC2_Pos)           /* (RTC_TAMPCTRL) Debouncer Enable 2 Mask */
+#define RTC_TAMPCTRL_DEBNC2(value)            (RTC_TAMPCTRL_DEBNC2_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC2_Pos)) /* Assignment of value for DEBNC2 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_DEBNC3_Pos               _UINT32_(27)                                         /* (RTC_TAMPCTRL) Debouncer Enable 3 Position */
+#define RTC_TAMPCTRL_DEBNC3_Msk               (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC3_Pos)           /* (RTC_TAMPCTRL) Debouncer Enable 3 Mask */
+#define RTC_TAMPCTRL_DEBNC3(value)            (RTC_TAMPCTRL_DEBNC3_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC3_Pos)) /* Assignment of value for DEBNC3 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_DEBNC4_Pos               _UINT32_(28)                                         /* (RTC_TAMPCTRL) Debouncer Enable 4 Position */
+#define RTC_TAMPCTRL_DEBNC4_Msk               (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC4_Pos)           /* (RTC_TAMPCTRL) Debouncer Enable 4 Mask */
+#define RTC_TAMPCTRL_DEBNC4(value)            (RTC_TAMPCTRL_DEBNC4_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC4_Pos)) /* Assignment of value for DEBNC4 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_DEBNC5_Pos               _UINT32_(29)                                         /* (RTC_TAMPCTRL) Debouncer Enable 5 Position */
+#define RTC_TAMPCTRL_DEBNC5_Msk               (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC5_Pos)           /* (RTC_TAMPCTRL) Debouncer Enable 5 Mask */
+#define RTC_TAMPCTRL_DEBNC5(value)            (RTC_TAMPCTRL_DEBNC5_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC5_Pos)) /* Assignment of value for DEBNC5 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_DEBNC6_Pos               _UINT32_(30)                                         /* (RTC_TAMPCTRL) Debouncer Enable 6 Position */
+#define RTC_TAMPCTRL_DEBNC6_Msk               (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC6_Pos)           /* (RTC_TAMPCTRL) Debouncer Enable 6 Mask */
+#define RTC_TAMPCTRL_DEBNC6(value)            (RTC_TAMPCTRL_DEBNC6_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC6_Pos)) /* Assignment of value for DEBNC6 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_DEBNC7_Pos               _UINT32_(31)                                         /* (RTC_TAMPCTRL) Debouncer Enable 7 Position */
+#define RTC_TAMPCTRL_DEBNC7_Msk               (_UINT32_(0x1) << RTC_TAMPCTRL_DEBNC7_Pos)           /* (RTC_TAMPCTRL) Debouncer Enable 7 Mask */
+#define RTC_TAMPCTRL_DEBNC7(value)            (RTC_TAMPCTRL_DEBNC7_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC7_Pos)) /* Assignment of value for DEBNC7 in the RTC_TAMPCTRL register */
+#define RTC_TAMPCTRL_Msk                      _UINT32_(0xFFFFFFFF)                                 /* (RTC_TAMPCTRL) Register Mask  */
+
+#define RTC_TAMPCTRL_TAMLVL_Pos               _UINT32_(16)                                         /* (RTC_TAMPCTRL Position) Tamper Level Select x */
+#define RTC_TAMPCTRL_TAMLVL_Msk               (_UINT32_(0xFF) << RTC_TAMPCTRL_TAMLVL_Pos)          /* (RTC_TAMPCTRL Mask) TAMLVL */
+#define RTC_TAMPCTRL_TAMLVL(value)            (RTC_TAMPCTRL_TAMLVL_Msk & (_UINT32_(value) << RTC_TAMPCTRL_TAMLVL_Pos)) 
+#define RTC_TAMPCTRL_DEBNC_Pos                _UINT32_(24)                                         /* (RTC_TAMPCTRL Position) Debouncer Enable 7 */
+#define RTC_TAMPCTRL_DEBNC_Msk                (_UINT32_(0xFF) << RTC_TAMPCTRL_DEBNC_Pos)           /* (RTC_TAMPCTRL Mask) DEBNC */
+#define RTC_TAMPCTRL_DEBNC(value)             (RTC_TAMPCTRL_DEBNC_Msk & (_UINT32_(value) << RTC_TAMPCTRL_DEBNC_Pos)) 
+
+/* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) ( R/ 32) MODE0 Timestamp -------- */
+#define RTC_MODE0_TIMESTAMP_RESETVALUE        _UINT32_(0x00)                                       /*  (RTC_MODE0_TIMESTAMP) MODE0 Timestamp  Reset Value */
+
+#define RTC_MODE0_TIMESTAMP_COUNT_Pos         _UINT32_(0)                                          /* (RTC_MODE0_TIMESTAMP) Count Timestamp Value Position */
+#define RTC_MODE0_TIMESTAMP_COUNT_Msk         (_UINT32_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos) /* (RTC_MODE0_TIMESTAMP) Count Timestamp Value Mask */
+#define RTC_MODE0_TIMESTAMP_COUNT(value)      (RTC_MODE0_TIMESTAMP_COUNT_Msk & (_UINT32_(value) << RTC_MODE0_TIMESTAMP_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE0_TIMESTAMP register */
+#define RTC_MODE0_TIMESTAMP_Msk               _UINT32_(0xFFFFFFFF)                                 /* (RTC_MODE0_TIMESTAMP) Register Mask  */
+
+
+/* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) ( R/ 32) MODE1 Timestamp -------- */
+#define RTC_MODE1_TIMESTAMP_RESETVALUE        _UINT32_(0x00)                                       /*  (RTC_MODE1_TIMESTAMP) MODE1 Timestamp  Reset Value */
+
+#define RTC_MODE1_TIMESTAMP_COUNT_Pos         _UINT32_(0)                                          /* (RTC_MODE1_TIMESTAMP) Count Timestamp Value Position */
+#define RTC_MODE1_TIMESTAMP_COUNT_Msk         (_UINT32_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos)  /* (RTC_MODE1_TIMESTAMP) Count Timestamp Value Mask */
+#define RTC_MODE1_TIMESTAMP_COUNT(value)      (RTC_MODE1_TIMESTAMP_COUNT_Msk & (_UINT32_(value) << RTC_MODE1_TIMESTAMP_COUNT_Pos)) /* Assignment of value for COUNT in the RTC_MODE1_TIMESTAMP register */
+#define RTC_MODE1_TIMESTAMP_Msk               _UINT32_(0x0000FFFF)                                 /* (RTC_MODE1_TIMESTAMP) Register Mask  */
+
+
+/* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) ( R/ 32) MODE2 Timestamp -------- */
+#define RTC_MODE2_TIMESTAMP_RESETVALUE        _UINT32_(0x00)                                       /*  (RTC_MODE2_TIMESTAMP) MODE2 Timestamp  Reset Value */
+
+#define RTC_MODE2_TIMESTAMP_SECOND_Pos        _UINT32_(0)                                          /* (RTC_MODE2_TIMESTAMP) Second Timestamp Value Position */
+#define RTC_MODE2_TIMESTAMP_SECOND_Msk        (_UINT32_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos)   /* (RTC_MODE2_TIMESTAMP) Second Timestamp Value Mask */
+#define RTC_MODE2_TIMESTAMP_SECOND(value)     (RTC_MODE2_TIMESTAMP_SECOND_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_SECOND_Pos)) /* Assignment of value for SECOND in the RTC_MODE2_TIMESTAMP register */
+#define RTC_MODE2_TIMESTAMP_MINUTE_Pos        _UINT32_(6)                                          /* (RTC_MODE2_TIMESTAMP) Minute Timestamp Value Position */
+#define RTC_MODE2_TIMESTAMP_MINUTE_Msk        (_UINT32_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)   /* (RTC_MODE2_TIMESTAMP) Minute Timestamp Value Mask */
+#define RTC_MODE2_TIMESTAMP_MINUTE(value)     (RTC_MODE2_TIMESTAMP_MINUTE_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)) /* Assignment of value for MINUTE in the RTC_MODE2_TIMESTAMP register */
+#define RTC_MODE2_TIMESTAMP_HOUR_Pos          _UINT32_(12)                                         /* (RTC_MODE2_TIMESTAMP) Hour Timestamp Value Position */
+#define RTC_MODE2_TIMESTAMP_HOUR_Msk          (_UINT32_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos)     /* (RTC_MODE2_TIMESTAMP) Hour Timestamp Value Mask */
+#define RTC_MODE2_TIMESTAMP_HOUR(value)       (RTC_MODE2_TIMESTAMP_HOUR_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_HOUR_Pos)) /* Assignment of value for HOUR in the RTC_MODE2_TIMESTAMP register */
+#define RTC_MODE2_TIMESTAMP_DAY_Pos           _UINT32_(17)                                         /* (RTC_MODE2_TIMESTAMP) Day Timestamp Value Position */
+#define RTC_MODE2_TIMESTAMP_DAY_Msk           (_UINT32_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos)      /* (RTC_MODE2_TIMESTAMP) Day Timestamp Value Mask */
+#define RTC_MODE2_TIMESTAMP_DAY(value)        (RTC_MODE2_TIMESTAMP_DAY_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_DAY_Pos)) /* Assignment of value for DAY in the RTC_MODE2_TIMESTAMP register */
+#define RTC_MODE2_TIMESTAMP_MONTH_Pos         _UINT32_(22)                                         /* (RTC_MODE2_TIMESTAMP) Month Timestamp Value Position */
+#define RTC_MODE2_TIMESTAMP_MONTH_Msk         (_UINT32_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos)     /* (RTC_MODE2_TIMESTAMP) Month Timestamp Value Mask */
+#define RTC_MODE2_TIMESTAMP_MONTH(value)      (RTC_MODE2_TIMESTAMP_MONTH_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_MONTH_Pos)) /* Assignment of value for MONTH in the RTC_MODE2_TIMESTAMP register */
+#define RTC_MODE2_TIMESTAMP_YEAR_Pos          _UINT32_(26)                                         /* (RTC_MODE2_TIMESTAMP) Year Timestamp Value Position */
+#define RTC_MODE2_TIMESTAMP_YEAR_Msk          (_UINT32_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos)     /* (RTC_MODE2_TIMESTAMP) Year Timestamp Value Mask */
+#define RTC_MODE2_TIMESTAMP_YEAR(value)       (RTC_MODE2_TIMESTAMP_YEAR_Msk & (_UINT32_(value) << RTC_MODE2_TIMESTAMP_YEAR_Pos)) /* Assignment of value for YEAR in the RTC_MODE2_TIMESTAMP register */
+#define RTC_MODE2_TIMESTAMP_Msk               _UINT32_(0xFFFFFFFF)                                 /* (RTC_MODE2_TIMESTAMP) Register Mask  */
+
+
+/* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */
+#define RTC_TAMPID_RESETVALUE                 _UINT32_(0x00)                                       /*  (RTC_TAMPID) Tamper ID  Reset Value */
+
+#define RTC_TAMPID_TAMPID0_Pos                _UINT32_(0)                                          /* (RTC_TAMPID) Tamper Input 0 Detected Position */
+#define RTC_TAMPID_TAMPID0_Msk                (_UINT32_(0x1) << RTC_TAMPID_TAMPID0_Pos)            /* (RTC_TAMPID) Tamper Input 0 Detected Mask */
+#define RTC_TAMPID_TAMPID0(value)             (RTC_TAMPID_TAMPID0_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID0_Pos)) /* Assignment of value for TAMPID0 in the RTC_TAMPID register */
+#define RTC_TAMPID_TAMPID1_Pos                _UINT32_(1)                                          /* (RTC_TAMPID) Tamper Input 1 Detected Position */
+#define RTC_TAMPID_TAMPID1_Msk                (_UINT32_(0x1) << RTC_TAMPID_TAMPID1_Pos)            /* (RTC_TAMPID) Tamper Input 1 Detected Mask */
+#define RTC_TAMPID_TAMPID1(value)             (RTC_TAMPID_TAMPID1_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID1_Pos)) /* Assignment of value for TAMPID1 in the RTC_TAMPID register */
+#define RTC_TAMPID_TAMPID2_Pos                _UINT32_(2)                                          /* (RTC_TAMPID) Tamper Input 2 Detected Position */
+#define RTC_TAMPID_TAMPID2_Msk                (_UINT32_(0x1) << RTC_TAMPID_TAMPID2_Pos)            /* (RTC_TAMPID) Tamper Input 2 Detected Mask */
+#define RTC_TAMPID_TAMPID2(value)             (RTC_TAMPID_TAMPID2_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID2_Pos)) /* Assignment of value for TAMPID2 in the RTC_TAMPID register */
+#define RTC_TAMPID_TAMPID3_Pos                _UINT32_(3)                                          /* (RTC_TAMPID) Tamper Input 3 Detected Position */
+#define RTC_TAMPID_TAMPID3_Msk                (_UINT32_(0x1) << RTC_TAMPID_TAMPID3_Pos)            /* (RTC_TAMPID) Tamper Input 3 Detected Mask */
+#define RTC_TAMPID_TAMPID3(value)             (RTC_TAMPID_TAMPID3_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID3_Pos)) /* Assignment of value for TAMPID3 in the RTC_TAMPID register */
+#define RTC_TAMPID_TAMPID4_Pos                _UINT32_(4)                                          /* (RTC_TAMPID) Tamper Input 4 Detected Position */
+#define RTC_TAMPID_TAMPID4_Msk                (_UINT32_(0x1) << RTC_TAMPID_TAMPID4_Pos)            /* (RTC_TAMPID) Tamper Input 4 Detected Mask */
+#define RTC_TAMPID_TAMPID4(value)             (RTC_TAMPID_TAMPID4_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID4_Pos)) /* Assignment of value for TAMPID4 in the RTC_TAMPID register */
+#define RTC_TAMPID_TAMPID5_Pos                _UINT32_(5)                                          /* (RTC_TAMPID) Tamper Input 5 Detected Position */
+#define RTC_TAMPID_TAMPID5_Msk                (_UINT32_(0x1) << RTC_TAMPID_TAMPID5_Pos)            /* (RTC_TAMPID) Tamper Input 5 Detected Mask */
+#define RTC_TAMPID_TAMPID5(value)             (RTC_TAMPID_TAMPID5_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID5_Pos)) /* Assignment of value for TAMPID5 in the RTC_TAMPID register */
+#define RTC_TAMPID_TAMPID6_Pos                _UINT32_(6)                                          /* (RTC_TAMPID) Tamper Input 6 Detected Position */
+#define RTC_TAMPID_TAMPID6_Msk                (_UINT32_(0x1) << RTC_TAMPID_TAMPID6_Pos)            /* (RTC_TAMPID) Tamper Input 6 Detected Mask */
+#define RTC_TAMPID_TAMPID6(value)             (RTC_TAMPID_TAMPID6_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID6_Pos)) /* Assignment of value for TAMPID6 in the RTC_TAMPID register */
+#define RTC_TAMPID_TAMPID7_Pos                _UINT32_(7)                                          /* (RTC_TAMPID) Tamper Input 7 Detected Position */
+#define RTC_TAMPID_TAMPID7_Msk                (_UINT32_(0x1) << RTC_TAMPID_TAMPID7_Pos)            /* (RTC_TAMPID) Tamper Input 7 Detected Mask */
+#define RTC_TAMPID_TAMPID7(value)             (RTC_TAMPID_TAMPID7_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID7_Pos)) /* Assignment of value for TAMPID7 in the RTC_TAMPID register */
+#define RTC_TAMPID_TAMPEVT_Pos                _UINT32_(31)                                         /* (RTC_TAMPID) Tamper Event Detected Position */
+#define RTC_TAMPID_TAMPEVT_Msk                (_UINT32_(0x1) << RTC_TAMPID_TAMPEVT_Pos)            /* (RTC_TAMPID) Tamper Event Detected Mask */
+#define RTC_TAMPID_TAMPEVT(value)             (RTC_TAMPID_TAMPEVT_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPEVT_Pos)) /* Assignment of value for TAMPEVT in the RTC_TAMPID register */
+#define RTC_TAMPID_Msk                        _UINT32_(0x800000FF)                                 /* (RTC_TAMPID) Register Mask  */
+
+#define RTC_TAMPID_TAMPID_Pos                 _UINT32_(0)                                          /* (RTC_TAMPID Position) Tamper Input x Detected */
+#define RTC_TAMPID_TAMPID_Msk                 (_UINT32_(0xFF) << RTC_TAMPID_TAMPID_Pos)            /* (RTC_TAMPID Mask) TAMPID */
+#define RTC_TAMPID_TAMPID(value)              (RTC_TAMPID_TAMPID_Msk & (_UINT32_(value) << RTC_TAMPID_TAMPID_Pos)) 
+
+/* -------- RTC_TAMPCTRLB : (RTC Offset: 0x6C) (R/W 32) Tamper Control B -------- */
+#define RTC_TAMPCTRLB_RESETVALUE              _UINT32_(0x00)                                       /*  (RTC_TAMPCTRLB) Tamper Control B  Reset Value */
+
+#define RTC_TAMPCTRLB_ALSI0_Pos               _UINT32_(0)                                          /* (RTC_TAMPCTRLB) Active Layer Select Internal 0 Position */
+#define RTC_TAMPCTRLB_ALSI0_Msk               (_UINT32_(0x1) << RTC_TAMPCTRLB_ALSI0_Pos)           /* (RTC_TAMPCTRLB) Active Layer Select Internal 0 Mask */
+#define RTC_TAMPCTRLB_ALSI0(value)            (RTC_TAMPCTRLB_ALSI0_Msk & (_UINT32_(value) << RTC_TAMPCTRLB_ALSI0_Pos)) /* Assignment of value for ALSI0 in the RTC_TAMPCTRLB register */
+#define RTC_TAMPCTRLB_ALSI1_Pos               _UINT32_(1)                                          /* (RTC_TAMPCTRLB) Active Layer Select Internal 1 Position */
+#define RTC_TAMPCTRLB_ALSI1_Msk               (_UINT32_(0x1) << RTC_TAMPCTRLB_ALSI1_Pos)           /* (RTC_TAMPCTRLB) Active Layer Select Internal 1 Mask */
+#define RTC_TAMPCTRLB_ALSI1(value)            (RTC_TAMPCTRLB_ALSI1_Msk & (_UINT32_(value) << RTC_TAMPCTRLB_ALSI1_Pos)) /* Assignment of value for ALSI1 in the RTC_TAMPCTRLB register */
+#define RTC_TAMPCTRLB_ALSI2_Pos               _UINT32_(2)                                          /* (RTC_TAMPCTRLB) Active Layer Select Internal 2 Position */
+#define RTC_TAMPCTRLB_ALSI2_Msk               (_UINT32_(0x1) << RTC_TAMPCTRLB_ALSI2_Pos)           /* (RTC_TAMPCTRLB) Active Layer Select Internal 2 Mask */
+#define RTC_TAMPCTRLB_ALSI2(value)            (RTC_TAMPCTRLB_ALSI2_Msk & (_UINT32_(value) << RTC_TAMPCTRLB_ALSI2_Pos)) /* Assignment of value for ALSI2 in the RTC_TAMPCTRLB register */
+#define RTC_TAMPCTRLB_ALSI3_Pos               _UINT32_(3)                                          /* (RTC_TAMPCTRLB) Active Layer Select Internal 3 Position */
+#define RTC_TAMPCTRLB_ALSI3_Msk               (_UINT32_(0x1) << RTC_TAMPCTRLB_ALSI3_Pos)           /* (RTC_TAMPCTRLB) Active Layer Select Internal 3 Mask */
+#define RTC_TAMPCTRLB_ALSI3(value)            (RTC_TAMPCTRLB_ALSI3_Msk & (_UINT32_(value) << RTC_TAMPCTRLB_ALSI3_Pos)) /* Assignment of value for ALSI3 in the RTC_TAMPCTRLB register */
+#define RTC_TAMPCTRLB_ALSI4_Pos               _UINT32_(4)                                          /* (RTC_TAMPCTRLB) Active Layer Select Internal 4 Position */
+#define RTC_TAMPCTRLB_ALSI4_Msk               (_UINT32_(0x1) << RTC_TAMPCTRLB_ALSI4_Pos)           /* (RTC_TAMPCTRLB) Active Layer Select Internal 4 Mask */
+#define RTC_TAMPCTRLB_ALSI4(value)            (RTC_TAMPCTRLB_ALSI4_Msk & (_UINT32_(value) << RTC_TAMPCTRLB_ALSI4_Pos)) /* Assignment of value for ALSI4 in the RTC_TAMPCTRLB register */
+#define RTC_TAMPCTRLB_ALSI5_Pos               _UINT32_(5)                                          /* (RTC_TAMPCTRLB) Active Layer Select Internal 5 Position */
+#define RTC_TAMPCTRLB_ALSI5_Msk               (_UINT32_(0x1) << RTC_TAMPCTRLB_ALSI5_Pos)           /* (RTC_TAMPCTRLB) Active Layer Select Internal 5 Mask */
+#define RTC_TAMPCTRLB_ALSI5(value)            (RTC_TAMPCTRLB_ALSI5_Msk & (_UINT32_(value) << RTC_TAMPCTRLB_ALSI5_Pos)) /* Assignment of value for ALSI5 in the RTC_TAMPCTRLB register */
+#define RTC_TAMPCTRLB_ALSI6_Pos               _UINT32_(6)                                          /* (RTC_TAMPCTRLB) Active Layer Select Internal 6 Position */
+#define RTC_TAMPCTRLB_ALSI6_Msk               (_UINT32_(0x1) << RTC_TAMPCTRLB_ALSI6_Pos)           /* (RTC_TAMPCTRLB) Active Layer Select Internal 6 Mask */
+#define RTC_TAMPCTRLB_ALSI6(value)            (RTC_TAMPCTRLB_ALSI6_Msk & (_UINT32_(value) << RTC_TAMPCTRLB_ALSI6_Pos)) /* Assignment of value for ALSI6 in the RTC_TAMPCTRLB register */
+#define RTC_TAMPCTRLB_ALSI7_Pos               _UINT32_(7)                                          /* (RTC_TAMPCTRLB) Active Layer Select Internal 7 Position */
+#define RTC_TAMPCTRLB_ALSI7_Msk               (_UINT32_(0x1) << RTC_TAMPCTRLB_ALSI7_Pos)           /* (RTC_TAMPCTRLB) Active Layer Select Internal 7 Mask */
+#define RTC_TAMPCTRLB_ALSI7(value)            (RTC_TAMPCTRLB_ALSI7_Msk & (_UINT32_(value) << RTC_TAMPCTRLB_ALSI7_Pos)) /* Assignment of value for ALSI7 in the RTC_TAMPCTRLB register */
+#define RTC_TAMPCTRLB_Msk                     _UINT32_(0x000000FF)                                 /* (RTC_TAMPCTRLB) Register Mask  */
+
+#define RTC_TAMPCTRLB_ALSI_Pos                _UINT32_(0)                                          /* (RTC_TAMPCTRLB Position) Active Layer Select Internal 7 */
+#define RTC_TAMPCTRLB_ALSI_Msk                (_UINT32_(0xFF) << RTC_TAMPCTRLB_ALSI_Pos)           /* (RTC_TAMPCTRLB Mask) ALSI */
+#define RTC_TAMPCTRLB_ALSI(value)             (RTC_TAMPCTRLB_ALSI_Msk & (_UINT32_(value) << RTC_TAMPCTRLB_ALSI_Pos)) 
+
+/* RTC register offsets definitions */
+#define RTC_MODE2_ALARM_REG_OFST       _UINT32_(0x00)      /* (RTC_MODE2_ALARM) MODE2_ALARM Alarm n Value Offset */
+#define RTC_MODE2_MASK_REG_OFST        _UINT32_(0x04)      /* (RTC_MODE2_MASK) MODE2_ALARM Alarm n Mask Offset */
+#define RTC_MODE0_CTRLA_REG_OFST       _UINT32_(0x00)      /* (RTC_MODE0_CTRLA) MODE0 Control A Offset */
+#define RTC_MODE1_CTRLA_REG_OFST       _UINT32_(0x00)      /* (RTC_MODE1_CTRLA) MODE1 Control A Offset */
+#define RTC_MODE2_CTRLA_REG_OFST       _UINT32_(0x00)      /* (RTC_MODE2_CTRLA) MODE2 Control A Offset */
+#define RTC_MODE0_CTRLB_REG_OFST       _UINT32_(0x02)      /* (RTC_MODE0_CTRLB) MODE0 Control B Offset */
+#define RTC_MODE1_CTRLB_REG_OFST       _UINT32_(0x02)      /* (RTC_MODE1_CTRLB) MODE1 Control B Offset */
+#define RTC_MODE2_CTRLB_REG_OFST       _UINT32_(0x02)      /* (RTC_MODE2_CTRLB) MODE2 Control B Offset */
+#define RTC_MODE0_EVCTRL_REG_OFST      _UINT32_(0x04)      /* (RTC_MODE0_EVCTRL) MODE0 Event Control Offset */
+#define RTC_MODE1_EVCTRL_REG_OFST      _UINT32_(0x04)      /* (RTC_MODE1_EVCTRL) MODE1 Event Control Offset */
+#define RTC_MODE2_EVCTRL_REG_OFST      _UINT32_(0x04)      /* (RTC_MODE2_EVCTRL) MODE2 Event Control Offset */
+#define RTC_MODE0_INTENCLR_REG_OFST    _UINT32_(0x08)      /* (RTC_MODE0_INTENCLR) MODE0 Interrupt Enable Clear Offset */
+#define RTC_MODE1_INTENCLR_REG_OFST    _UINT32_(0x08)      /* (RTC_MODE1_INTENCLR) MODE1 Interrupt Enable Clear Offset */
+#define RTC_MODE2_INTENCLR_REG_OFST    _UINT32_(0x08)      /* (RTC_MODE2_INTENCLR) MODE2 Interrupt Enable Clear Offset */
+#define RTC_MODE0_INTENSET_REG_OFST    _UINT32_(0x0A)      /* (RTC_MODE0_INTENSET) MODE0 Interrupt Enable Set Offset */
+#define RTC_MODE1_INTENSET_REG_OFST    _UINT32_(0x0A)      /* (RTC_MODE1_INTENSET) MODE1 Interrupt Enable Set Offset */
+#define RTC_MODE2_INTENSET_REG_OFST    _UINT32_(0x0A)      /* (RTC_MODE2_INTENSET) MODE2 Interrupt Enable Set Offset */
+#define RTC_MODE0_INTFLAG_REG_OFST     _UINT32_(0x0C)      /* (RTC_MODE0_INTFLAG) MODE0 Interrupt Flag Status and Clear Offset */
+#define RTC_MODE1_INTFLAG_REG_OFST     _UINT32_(0x0C)      /* (RTC_MODE1_INTFLAG) MODE1 Interrupt Flag Status and Clear Offset */
+#define RTC_MODE2_INTFLAG_REG_OFST     _UINT32_(0x0C)      /* (RTC_MODE2_INTFLAG) MODE2 Interrupt Flag Status and Clear Offset */
+#define RTC_DBGCTRL_REG_OFST           _UINT32_(0x0E)      /* (RTC_DBGCTRL) Debug Control Offset */
+#define RTC_MODE0_SYNCBUSY_REG_OFST    _UINT32_(0x10)      /* (RTC_MODE0_SYNCBUSY) MODE0 Synchronization Busy Status Offset */
+#define RTC_MODE1_SYNCBUSY_REG_OFST    _UINT32_(0x10)      /* (RTC_MODE1_SYNCBUSY) MODE1 Synchronization Busy Status Offset */
+#define RTC_MODE2_SYNCBUSY_REG_OFST    _UINT32_(0x10)      /* (RTC_MODE2_SYNCBUSY) MODE2 Synchronization Busy Status Offset */
+#define RTC_FREQCORR_REG_OFST          _UINT32_(0x14)      /* (RTC_FREQCORR) Frequency Correction Offset */
+#define RTC_MODE0_COUNT_REG_OFST       _UINT32_(0x18)      /* (RTC_MODE0_COUNT) MODE0 Counter Value Offset */
+#define RTC_MODE1_COUNT_REG_OFST       _UINT32_(0x18)      /* (RTC_MODE1_COUNT) MODE1 Counter Value Offset */
+#define RTC_MODE2_CLOCK_REG_OFST       _UINT32_(0x18)      /* (RTC_MODE2_CLOCK) MODE2 Clock Value Offset */
+#define RTC_MODE1_PER_REG_OFST         _UINT32_(0x1C)      /* (RTC_MODE1_PER) MODE1 Counter Period Offset */
+#define RTC_MODE0_COMP_REG_OFST        _UINT32_(0x20)      /* (RTC_MODE0_COMP) MODE0 Compare n Value Offset */
+#define RTC_MODE0_COMP0_REG_OFST       _UINT32_(0x20)      /* (RTC_MODE0_COMP0) MODE0 Compare n Value Offset */
+#define RTC_MODE0_COMP1_REG_OFST       _UINT32_(0x24)      /* (RTC_MODE0_COMP1) MODE0 Compare n Value Offset */
+#define RTC_MODE1_COMP_REG_OFST        _UINT32_(0x20)      /* (RTC_MODE1_COMP) MODE1 Compare n Value Offset */
+#define RTC_MODE1_COMP0_REG_OFST       _UINT32_(0x20)      /* (RTC_MODE1_COMP0) MODE1 Compare n Value Offset */
+#define RTC_MODE1_COMP1_REG_OFST       _UINT32_(0x22)      /* (RTC_MODE1_COMP1) MODE1 Compare n Value Offset */
+#define RTC_MODE1_COMP2_REG_OFST       _UINT32_(0x24)      /* (RTC_MODE1_COMP2) MODE1 Compare n Value Offset */
+#define RTC_MODE1_COMP3_REG_OFST       _UINT32_(0x26)      /* (RTC_MODE1_COMP3) MODE1 Compare n Value Offset */
+#define RTC_GP_REG_OFST                _UINT32_(0x40)      /* (RTC_GP) General Purpose Offset */
+#define RTC_GP0_REG_OFST               _UINT32_(0x40)      /* (RTC_GP0) General Purpose Offset */
+#define RTC_GP1_REG_OFST               _UINT32_(0x44)      /* (RTC_GP1) General Purpose Offset */
+#define RTC_GP2_REG_OFST               _UINT32_(0x48)      /* (RTC_GP2) General Purpose Offset */
+#define RTC_GP3_REG_OFST               _UINT32_(0x4C)      /* (RTC_GP3) General Purpose Offset */
+#define RTC_TAMPCTRL_REG_OFST          _UINT32_(0x60)      /* (RTC_TAMPCTRL) Tamper Control Offset */
+#define RTC_MODE0_TIMESTAMP_REG_OFST   _UINT32_(0x64)      /* (RTC_MODE0_TIMESTAMP) MODE0 Timestamp Offset */
+#define RTC_MODE1_TIMESTAMP_REG_OFST   _UINT32_(0x64)      /* (RTC_MODE1_TIMESTAMP) MODE1 Timestamp Offset */
+#define RTC_MODE2_TIMESTAMP_REG_OFST   _UINT32_(0x64)      /* (RTC_MODE2_TIMESTAMP) MODE2 Timestamp Offset */
+#define RTC_TAMPID_REG_OFST            _UINT32_(0x68)      /* (RTC_TAMPID) Tamper ID Offset */
+#define RTC_TAMPCTRLB_REG_OFST         _UINT32_(0x6C)      /* (RTC_TAMPCTRLB) Tamper Control B Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* MODE2_ALARM register API structure */
+typedef struct
+{
+  __IO  uint32_t                       RTC_ALARM;          /* Offset: 0x00 (R/W  32) MODE2_ALARM Alarm n Value */
+  __IO  uint8_t                        RTC_MASK;           /* Offset: 0x04 (R/W  8) MODE2_ALARM Alarm n Mask */
+  __I   uint8_t                        Reserved1[0x03];
+} rtc_mode2_alarm_registers_t;
+
+/* RTC register API structure */
+typedef struct
+{  /* Real-Time Counter */
+  __IO  uint16_t                       RTC_CTRLA;          /* Offset: 0x00 (R/W  16) MODE0 Control A */
+  __IO  uint16_t                       RTC_CTRLB;          /* Offset: 0x02 (R/W  16) MODE0 Control B */
+  __IO  uint32_t                       RTC_EVCTRL;         /* Offset: 0x04 (R/W  32) MODE0 Event Control */
+  __IO  uint16_t                       RTC_INTENCLR;       /* Offset: 0x08 (R/W  16) MODE0 Interrupt Enable Clear */
+  __IO  uint16_t                       RTC_INTENSET;       /* Offset: 0x0A (R/W  16) MODE0 Interrupt Enable Set */
+  __IO  uint16_t                       RTC_INTFLAG;        /* Offset: 0x0C (R/W  16) MODE0 Interrupt Flag Status and Clear */
+  __IO  uint8_t                        RTC_DBGCTRL;        /* Offset: 0x0E (R/W  8) Debug Control */
+  __I   uint8_t                        Reserved1[0x01];
+  __I   uint32_t                       RTC_SYNCBUSY;       /* Offset: 0x10 (R/   32) MODE0 Synchronization Busy Status */
+  __IO  uint8_t                        RTC_FREQCORR;       /* Offset: 0x14 (R/W  8) Frequency Correction */
+  __I   uint8_t                        Reserved2[0x03];
+  __IO  uint32_t                       RTC_COUNT;          /* Offset: 0x18 (R/W  32) MODE0 Counter Value */
+  __I   uint8_t                        Reserved3[0x04];
+  __IO  uint32_t                       RTC_COMP[2];        /* Offset: 0x20 (R/W  32) MODE0 Compare n Value */
+  __I   uint8_t                        Reserved4[0x18];
+  __IO  uint32_t                       RTC_GP[4];          /* Offset: 0x40 (R/W  32) General Purpose */
+  __I   uint8_t                        Reserved5[0x10];
+  __IO  uint32_t                       RTC_TAMPCTRL;       /* Offset: 0x60 (R/W  32) Tamper Control */
+  __I   uint32_t                       RTC_TIMESTAMP;      /* Offset: 0x64 (R/   32) MODE0 Timestamp */
+  __IO  uint32_t                       RTC_TAMPID;         /* Offset: 0x68 (R/W  32) Tamper ID */
+  __IO  uint32_t                       RTC_TAMPCTRLB;      /* Offset: 0x6C (R/W  32) Tamper Control B */
+} rtc_mode0_registers_t;
+
+/* RTC register API structure */
+typedef struct
+{  /* Real-Time Counter */
+  __IO  uint16_t                       RTC_CTRLA;          /* Offset: 0x00 (R/W  16) MODE1 Control A */
+  __IO  uint16_t                       RTC_CTRLB;          /* Offset: 0x02 (R/W  16) MODE1 Control B */
+  __IO  uint32_t                       RTC_EVCTRL;         /* Offset: 0x04 (R/W  32) MODE1 Event Control */
+  __IO  uint16_t                       RTC_INTENCLR;       /* Offset: 0x08 (R/W  16) MODE1 Interrupt Enable Clear */
+  __IO  uint16_t                       RTC_INTENSET;       /* Offset: 0x0A (R/W  16) MODE1 Interrupt Enable Set */
+  __IO  uint16_t                       RTC_INTFLAG;        /* Offset: 0x0C (R/W  16) MODE1 Interrupt Flag Status and Clear */
+  __IO  uint8_t                        RTC_DBGCTRL;        /* Offset: 0x0E (R/W  8) Debug Control */
+  __I   uint8_t                        Reserved1[0x01];
+  __I   uint32_t                       RTC_SYNCBUSY;       /* Offset: 0x10 (R/   32) MODE1 Synchronization Busy Status */
+  __IO  uint8_t                        RTC_FREQCORR;       /* Offset: 0x14 (R/W  8) Frequency Correction */
+  __I   uint8_t                        Reserved2[0x03];
+  __IO  uint16_t                       RTC_COUNT;          /* Offset: 0x18 (R/W  16) MODE1 Counter Value */
+  __I   uint8_t                        Reserved3[0x02];
+  __IO  uint16_t                       RTC_PER;            /* Offset: 0x1C (R/W  16) MODE1 Counter Period */
+  __I   uint8_t                        Reserved4[0x02];
+  __IO  uint16_t                       RTC_COMP[4];        /* Offset: 0x20 (R/W  16) MODE1 Compare n Value */
+  __I   uint8_t                        Reserved5[0x18];
+  __IO  uint32_t                       RTC_GP[4];          /* Offset: 0x40 (R/W  32) General Purpose */
+  __I   uint8_t                        Reserved6[0x10];
+  __IO  uint32_t                       RTC_TAMPCTRL;       /* Offset: 0x60 (R/W  32) Tamper Control */
+  __I   uint32_t                       RTC_TIMESTAMP;      /* Offset: 0x64 (R/   32) MODE1 Timestamp */
+  __IO  uint32_t                       RTC_TAMPID;         /* Offset: 0x68 (R/W  32) Tamper ID */
+  __IO  uint32_t                       RTC_TAMPCTRLB;      /* Offset: 0x6C (R/W  32) Tamper Control B */
+} rtc_mode1_registers_t;
+
+#define RTC_MODE2_ALARM_NUMBER 2
+
+/* RTC register API structure */
+typedef struct
+{  /* Real-Time Counter */
+  __IO  uint16_t                       RTC_CTRLA;          /* Offset: 0x00 (R/W  16) MODE2 Control A */
+  __IO  uint16_t                       RTC_CTRLB;          /* Offset: 0x02 (R/W  16) MODE2 Control B */
+  __IO  uint32_t                       RTC_EVCTRL;         /* Offset: 0x04 (R/W  32) MODE2 Event Control */
+  __IO  uint16_t                       RTC_INTENCLR;       /* Offset: 0x08 (R/W  16) MODE2 Interrupt Enable Clear */
+  __IO  uint16_t                       RTC_INTENSET;       /* Offset: 0x0A (R/W  16) MODE2 Interrupt Enable Set */
+  __IO  uint16_t                       RTC_INTFLAG;        /* Offset: 0x0C (R/W  16) MODE2 Interrupt Flag Status and Clear */
+  __IO  uint8_t                        RTC_DBGCTRL;        /* Offset: 0x0E (R/W  8) Debug Control */
+  __I   uint8_t                        Reserved1[0x01];
+  __I   uint32_t                       RTC_SYNCBUSY;       /* Offset: 0x10 (R/   32) MODE2 Synchronization Busy Status */
+  __IO  uint8_t                        RTC_FREQCORR;       /* Offset: 0x14 (R/W  8) Frequency Correction */
+  __I   uint8_t                        Reserved2[0x03];
+  __IO  uint32_t                       RTC_CLOCK;          /* Offset: 0x18 (R/W  32) MODE2 Clock Value */
+  __I   uint8_t                        Reserved3[0x04];
+        rtc_mode2_alarm_registers_t    MODE2_ALARM[RTC_MODE2_ALARM_NUMBER]; /* Offset: 0x20  */
+  __I   uint8_t                        Reserved4[0x10];
+  __IO  uint32_t                       RTC_GP[4];          /* Offset: 0x40 (R/W  32) General Purpose */
+  __I   uint8_t                        Reserved5[0x10];
+  __IO  uint32_t                       RTC_TAMPCTRL;       /* Offset: 0x60 (R/W  32) Tamper Control */
+  __I   uint32_t                       RTC_TIMESTAMP;      /* Offset: 0x64 (R/   32) MODE2 Timestamp */
+  __IO  uint32_t                       RTC_TAMPID;         /* Offset: 0x68 (R/W  32) Tamper ID */
+  __IO  uint32_t                       RTC_TAMPCTRLB;      /* Offset: 0x6C (R/W  32) Tamper Control B */
+} rtc_mode2_registers_t;
+
+/* RTC hardware registers */
+typedef union
+{  /* Real-Time Counter */
+       rtc_mode0_registers_t          MODE0;          /* 32-bit Counter with Single 32-bit Compare */
+       rtc_mode1_registers_t          MODE1;          /* 16-bit Counter with Two 16-bit Compares */
+       rtc_mode2_registers_t          MODE2;          /* Clock/Calendar with Alarm */
+} rtc_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_RTC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/sercom.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/sercom.h
new file mode 100644
index 00000000..58b3a3ae
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/sercom.h
@@ -0,0 +1,1722 @@
+/*
+ * Component description for SERCOM
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_SERCOM_COMPONENT_H_
+#define _PIC32CMGC00_SERCOM_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                     SOFTWARE API DEFINITION FOR SERCOM                     */
+/* ************************************************************************** */
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM Control A -------- */
+#define SERCOM_I2CM_CTRLA_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CM_CTRLA) I2CM Control A  Reset Value */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos           _UINT32_(0)                                          /* (SERCOM_I2CM_CTRLA) Software Reset Position */
+#define SERCOM_I2CM_CTRLA_SWRST_Msk           (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)       /* (SERCOM_I2CM_CTRLA) Software Reset Mask */
+#define SERCOM_I2CM_CTRLA_SWRST(value)        (SERCOM_I2CM_CTRLA_SWRST_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the SERCOM_I2CM_CTRLA register */
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos          _UINT32_(1)                                          /* (SERCOM_I2CM_CTRLA) Enable Position */
+#define SERCOM_I2CM_CTRLA_ENABLE_Msk          (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)      /* (SERCOM_I2CM_CTRLA) Enable Mask */
+#define SERCOM_I2CM_CTRLA_ENABLE(value)       (SERCOM_I2CM_CTRLA_ENABLE_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the SERCOM_I2CM_CTRLA register */
+#define SERCOM_I2CM_CTRLA_MODE_Pos            _UINT32_(2)                                          /* (SERCOM_I2CM_CTRLA) Operating Mode Position */
+#define SERCOM_I2CM_CTRLA_MODE_Msk            (_UINT32_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)        /* (SERCOM_I2CM_CTRLA) Operating Mode Mask */
+#define SERCOM_I2CM_CTRLA_MODE(value)         (SERCOM_I2CM_CTRLA_MODE_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the SERCOM_I2CM_CTRLA register */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val _UINT32_(0x5)                                        /* (SERCOM_I2CM_CTRLA) I2C host mode operation  */
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER     (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /* (SERCOM_I2CM_CTRLA) I2C host mode operation Position */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos        _UINT32_(7)                                          /* (SERCOM_I2CM_CTRLA) Run in Standby Position */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Msk        (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)    /* (SERCOM_I2CM_CTRLA) Run in Standby Mask */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY(value)     (SERCOM_I2CM_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the SERCOM_I2CM_CTRLA register */
+#define SERCOM_I2CM_CTRLA_FILTSEL_Pos         _UINT32_(8)                                          /* (SERCOM_I2CM_CTRLA) Input Filter Selection Position */
+#define SERCOM_I2CM_CTRLA_FILTSEL_Msk         (_UINT32_(0x3) << SERCOM_I2CM_CTRLA_FILTSEL_Pos)     /* (SERCOM_I2CM_CTRLA) Input Filter Selection Mask */
+#define SERCOM_I2CM_CTRLA_FILTSEL(value)      (SERCOM_I2CM_CTRLA_FILTSEL_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_FILTSEL_Pos)) /* Assignment of value for FILTSEL in the SERCOM_I2CM_CTRLA register */
+#define   SERCOM_I2CM_CTRLA_FILTSEL_DIS_Val   _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLA) Disable  */
+#define   SERCOM_I2CM_CTRLA_FILTSEL_50NS_Val  _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLA) Minimum 50ns filter  */
+#define   SERCOM_I2CM_CTRLA_FILTSEL_10NS_Val  _UINT32_(0x3)                                        /* (SERCOM_I2CM_CTRLA) Minimum 10ns filter  */
+#define SERCOM_I2CM_CTRLA_FILTSEL_DIS         (SERCOM_I2CM_CTRLA_FILTSEL_DIS_Val << SERCOM_I2CM_CTRLA_FILTSEL_Pos) /* (SERCOM_I2CM_CTRLA) Disable Position */
+#define SERCOM_I2CM_CTRLA_FILTSEL_50NS        (SERCOM_I2CM_CTRLA_FILTSEL_50NS_Val << SERCOM_I2CM_CTRLA_FILTSEL_Pos) /* (SERCOM_I2CM_CTRLA) Minimum 50ns filter Position */
+#define SERCOM_I2CM_CTRLA_FILTSEL_10NS        (SERCOM_I2CM_CTRLA_FILTSEL_10NS_Val << SERCOM_I2CM_CTRLA_FILTSEL_Pos) /* (SERCOM_I2CM_CTRLA) Minimum 10ns filter Position */
+#define SERCOM_I2CM_CTRLA_SLEWRATE_Pos        _UINT32_(10)                                         /* (SERCOM_I2CM_CTRLA) Slew Rate Selection Position */
+#define SERCOM_I2CM_CTRLA_SLEWRATE_Msk        (_UINT32_(0x3) << SERCOM_I2CM_CTRLA_SLEWRATE_Pos)    /* (SERCOM_I2CM_CTRLA) Slew Rate Selection Mask */
+#define SERCOM_I2CM_CTRLA_SLEWRATE(value)     (SERCOM_I2CM_CTRLA_SLEWRATE_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SLEWRATE_Pos)) /* Assignment of value for SLEWRATE in the SERCOM_I2CM_CTRLA register */
+#define   SERCOM_I2CM_CTRLA_SLEWRATE_SMM_Val  _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLA) Standard mode  */
+#define   SERCOM_I2CM_CTRLA_SLEWRATE_FM_Val   _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLA) Fast mode  */
+#define   SERCOM_I2CM_CTRLA_SLEWRATE_FMP_Val  _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLA) Fast mode plus  */
+#define   SERCOM_I2CM_CTRLA_SLEWRATE_HS_Val   _UINT32_(0x3)                                        /* (SERCOM_I2CM_CTRLA) High-speed mode  */
+#define SERCOM_I2CM_CTRLA_SLEWRATE_SMM        (SERCOM_I2CM_CTRLA_SLEWRATE_SMM_Val << SERCOM_I2CM_CTRLA_SLEWRATE_Pos) /* (SERCOM_I2CM_CTRLA) Standard mode Position */
+#define SERCOM_I2CM_CTRLA_SLEWRATE_FM         (SERCOM_I2CM_CTRLA_SLEWRATE_FM_Val << SERCOM_I2CM_CTRLA_SLEWRATE_Pos) /* (SERCOM_I2CM_CTRLA) Fast mode Position */
+#define SERCOM_I2CM_CTRLA_SLEWRATE_FMP        (SERCOM_I2CM_CTRLA_SLEWRATE_FMP_Val << SERCOM_I2CM_CTRLA_SLEWRATE_Pos) /* (SERCOM_I2CM_CTRLA) Fast mode plus Position */
+#define SERCOM_I2CM_CTRLA_SLEWRATE_HS         (SERCOM_I2CM_CTRLA_SLEWRATE_HS_Val << SERCOM_I2CM_CTRLA_SLEWRATE_Pos) /* (SERCOM_I2CM_CTRLA) High-speed mode Position */
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos          _UINT32_(16)                                         /* (SERCOM_I2CM_CTRLA) Pin Usage Position */
+#define SERCOM_I2CM_CTRLA_PINOUT_Msk          (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)      /* (SERCOM_I2CM_CTRLA) Pin Usage Mask */
+#define SERCOM_I2CM_CTRLA_PINOUT(value)       (SERCOM_I2CM_CTRLA_PINOUT_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_PINOUT_Pos)) /* Assignment of value for PINOUT in the SERCOM_I2CM_CTRLA register */
+#define SERCOM_I2CM_CTRLA_SMBUSEN_Pos         _UINT32_(17)                                         /* (SERCOM_I2CM_CTRLA) SMBUS Input Buffer Enable Position */
+#define SERCOM_I2CM_CTRLA_SMBUSEN_Msk         (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_SMBUSEN_Pos)     /* (SERCOM_I2CM_CTRLA) SMBUS Input Buffer Enable Mask */
+#define SERCOM_I2CM_CTRLA_SMBUSEN(value)      (SERCOM_I2CM_CTRLA_SMBUSEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SMBUSEN_Pos)) /* Assignment of value for SMBUSEN in the SERCOM_I2CM_CTRLA register */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos         _UINT32_(20)                                         /* (SERCOM_I2CM_CTRLA) SDA Hold Time Position */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk         (_UINT32_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)     /* (SERCOM_I2CM_CTRLA) SDA Hold Time Mask */
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value)      (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)) /* Assignment of value for SDAHOLD in the SERCOM_I2CM_CTRLA register */
+#define   SERCOM_I2CM_CTRLA_SDAHOLD_DIS_Val   _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLA) Disable  */
+#define   SERCOM_I2CM_CTRLA_SDAHOLD_75NS_Val  _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLA) 50ns - 100ns hold time  */
+#define   SERCOM_I2CM_CTRLA_SDAHOLD_450NS_Val _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLA) 300ns - 600ns hold time  */
+#define   SERCOM_I2CM_CTRLA_SDAHOLD_600NS_Val _UINT32_(0x3)                                        /* (SERCOM_I2CM_CTRLA) 400ns - 800ns hold time  */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_DIS         (SERCOM_I2CM_CTRLA_SDAHOLD_DIS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CM_CTRLA) Disable Position */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_75NS        (SERCOM_I2CM_CTRLA_SDAHOLD_75NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CM_CTRLA) 50ns - 100ns hold time Position */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_450NS       (SERCOM_I2CM_CTRLA_SDAHOLD_450NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CM_CTRLA) 300ns - 600ns hold time Position */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_600NS       (SERCOM_I2CM_CTRLA_SDAHOLD_600NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CM_CTRLA) 400ns - 800ns hold time Position */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos        _UINT32_(22)                                         /* (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout Position */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Msk        (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)    /* (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout Mask */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN(value)     (SERCOM_I2CM_CTRLA_MEXTTOEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)) /* Assignment of value for MEXTTOEN in the SERCOM_I2CM_CTRLA register */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos        _UINT32_(23)                                         /* (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout Position */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Msk        (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)    /* (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout Mask */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN(value)     (SERCOM_I2CM_CTRLA_SEXTTOEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)) /* Assignment of value for SEXTTOEN in the SERCOM_I2CM_CTRLA register */
+#define SERCOM_I2CM_CTRLA_SPEED_Pos           _UINT32_(24)                                         /* (SERCOM_I2CM_CTRLA) Transfer Speed Position */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk           (_UINT32_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)       /* (SERCOM_I2CM_CTRLA) Transfer Speed Mask */
+#define SERCOM_I2CM_CTRLA_SPEED(value)        (SERCOM_I2CM_CTRLA_SPEED_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SPEED_Pos)) /* Assignment of value for SPEED in the SERCOM_I2CM_CTRLA register */
+#define   SERCOM_I2CM_CTRLA_SPEED_SM_Val      _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLA) Standard-Mode (SM) and Fast-Mode (FM)  */
+#define   SERCOM_I2CM_CTRLA_SPEED_FMP_Val     _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLA) Fast-Mode Plus (FM+)  */
+#define   SERCOM_I2CM_CTRLA_SPEED_HS_Val      _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLA) High-Speed Mode  */
+#define SERCOM_I2CM_CTRLA_SPEED_SM            (SERCOM_I2CM_CTRLA_SPEED_SM_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /* (SERCOM_I2CM_CTRLA) Standard-Mode (SM) and Fast-Mode (FM) Position */
+#define SERCOM_I2CM_CTRLA_SPEED_FMP           (SERCOM_I2CM_CTRLA_SPEED_FMP_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /* (SERCOM_I2CM_CTRLA) Fast-Mode Plus (FM+) Position */
+#define SERCOM_I2CM_CTRLA_SPEED_HS            (SERCOM_I2CM_CTRLA_SPEED_HS_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /* (SERCOM_I2CM_CTRLA) High-Speed Mode Position */
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos           _UINT32_(27)                                         /* (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode Position */
+#define SERCOM_I2CM_CTRLA_SCLSM_Msk           (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)       /* (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode Mask */
+#define SERCOM_I2CM_CTRLA_SCLSM(value)        (SERCOM_I2CM_CTRLA_SCLSM_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_SCLSM_Pos)) /* Assignment of value for SCLSM in the SERCOM_I2CM_CTRLA register */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos        _UINT32_(28)                                         /* (SERCOM_I2CM_CTRLA) Inactive Time-Out Position */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk        (_UINT32_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)    /* (SERCOM_I2CM_CTRLA) Inactive Time-Out Mask */
+#define SERCOM_I2CM_CTRLA_INACTOUT(value)     (SERCOM_I2CM_CTRLA_INACTOUT_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)) /* Assignment of value for INACTOUT in the SERCOM_I2CM_CTRLA register */
+#define   SERCOM_I2CM_CTRLA_INACTOUT_DIS_Val  _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLA) Disable  */
+#define   SERCOM_I2CM_CTRLA_INACTOUT_55US_Val _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLA) 5-6 SCL cycle time-out  */
+#define   SERCOM_I2CM_CTRLA_INACTOUT_105US_Val _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLA) 10-11 SCL cycle time-out  */
+#define   SERCOM_I2CM_CTRLA_INACTOUT_205US_Val _UINT32_(0x3)                                        /* (SERCOM_I2CM_CTRLA) 20-21-6 SCL cycle time-out  */
+#define SERCOM_I2CM_CTRLA_INACTOUT_DIS        (SERCOM_I2CM_CTRLA_INACTOUT_DIS_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /* (SERCOM_I2CM_CTRLA) Disable Position */
+#define SERCOM_I2CM_CTRLA_INACTOUT_55US       (SERCOM_I2CM_CTRLA_INACTOUT_55US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /* (SERCOM_I2CM_CTRLA) 5-6 SCL cycle time-out Position */
+#define SERCOM_I2CM_CTRLA_INACTOUT_105US      (SERCOM_I2CM_CTRLA_INACTOUT_105US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /* (SERCOM_I2CM_CTRLA) 10-11 SCL cycle time-out Position */
+#define SERCOM_I2CM_CTRLA_INACTOUT_205US      (SERCOM_I2CM_CTRLA_INACTOUT_205US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /* (SERCOM_I2CM_CTRLA) 20-21-6 SCL cycle time-out Position */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos       _UINT32_(30)                                         /* (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable Position */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Msk       (_UINT32_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)   /* (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable Mask */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN(value)    (SERCOM_I2CM_CTRLA_LOWTOUTEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)) /* Assignment of value for LOWTOUTEN in the SERCOM_I2CM_CTRLA register */
+#define SERCOM_I2CM_CTRLA_Msk                 _UINT32_(0x7BF30F9F)                                 /* (SERCOM_I2CM_CTRLA) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS Control A -------- */
+#define SERCOM_I2CS_CTRLA_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CS_CTRLA) I2CS Control A  Reset Value */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos           _UINT32_(0)                                          /* (SERCOM_I2CS_CTRLA) Software Reset Position */
+#define SERCOM_I2CS_CTRLA_SWRST_Msk           (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)       /* (SERCOM_I2CS_CTRLA) Software Reset Mask */
+#define SERCOM_I2CS_CTRLA_SWRST(value)        (SERCOM_I2CS_CTRLA_SWRST_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the SERCOM_I2CS_CTRLA register */
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos          _UINT32_(1)                                          /* (SERCOM_I2CS_CTRLA) Enable Position */
+#define SERCOM_I2CS_CTRLA_ENABLE_Msk          (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)      /* (SERCOM_I2CS_CTRLA) Enable Mask */
+#define SERCOM_I2CS_CTRLA_ENABLE(value)       (SERCOM_I2CS_CTRLA_ENABLE_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the SERCOM_I2CS_CTRLA register */
+#define SERCOM_I2CS_CTRLA_MODE_Pos            _UINT32_(2)                                          /* (SERCOM_I2CS_CTRLA) Operating Mode Position */
+#define SERCOM_I2CS_CTRLA_MODE_Msk            (_UINT32_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)        /* (SERCOM_I2CS_CTRLA) Operating Mode Mask */
+#define SERCOM_I2CS_CTRLA_MODE(value)         (SERCOM_I2CS_CTRLA_MODE_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the SERCOM_I2CS_CTRLA register */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val _UINT32_(0x4)                                        /* (SERCOM_I2CS_CTRLA) I2C client mode operation  */
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE      (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /* (SERCOM_I2CS_CTRLA) I2C client mode operation Position */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos        _UINT32_(7)                                          /* (SERCOM_I2CS_CTRLA) Run during Standby Position */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Msk        (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)    /* (SERCOM_I2CS_CTRLA) Run during Standby Mask */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY(value)     (SERCOM_I2CS_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the SERCOM_I2CS_CTRLA register */
+#define SERCOM_I2CS_CTRLA_FILTSEL_Pos         _UINT32_(8)                                          /* (SERCOM_I2CS_CTRLA) Input Filter Selection Position */
+#define SERCOM_I2CS_CTRLA_FILTSEL_Msk         (_UINT32_(0x3) << SERCOM_I2CS_CTRLA_FILTSEL_Pos)     /* (SERCOM_I2CS_CTRLA) Input Filter Selection Mask */
+#define SERCOM_I2CS_CTRLA_FILTSEL(value)      (SERCOM_I2CS_CTRLA_FILTSEL_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_FILTSEL_Pos)) /* Assignment of value for FILTSEL in the SERCOM_I2CS_CTRLA register */
+#define SERCOM_I2CS_CTRLA_SLEWRATE_Pos        _UINT32_(10)                                         /* (SERCOM_I2CS_CTRLA) Slew Rate Selection Position */
+#define SERCOM_I2CS_CTRLA_SLEWRATE_Msk        (_UINT32_(0x3) << SERCOM_I2CS_CTRLA_SLEWRATE_Pos)    /* (SERCOM_I2CS_CTRLA) Slew Rate Selection Mask */
+#define SERCOM_I2CS_CTRLA_SLEWRATE(value)     (SERCOM_I2CS_CTRLA_SLEWRATE_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SLEWRATE_Pos)) /* Assignment of value for SLEWRATE in the SERCOM_I2CS_CTRLA register */
+#define   SERCOM_I2CS_CTRLA_SLEWRATE_SM_Val   _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLA) Standard mode  */
+#define   SERCOM_I2CS_CTRLA_SLEWRATE_FM_Val   _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLA) Fast mode  */
+#define   SERCOM_I2CS_CTRLA_SLEWRATE_FMP_Val  _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLA) Fast mode plus  */
+#define   SERCOM_I2CS_CTRLA_SLEWRATE_HS_Val   _UINT32_(0x3)                                        /* (SERCOM_I2CS_CTRLA) High-speed mode  */
+#define SERCOM_I2CS_CTRLA_SLEWRATE_SM         (SERCOM_I2CS_CTRLA_SLEWRATE_SM_Val << SERCOM_I2CS_CTRLA_SLEWRATE_Pos) /* (SERCOM_I2CS_CTRLA) Standard mode Position */
+#define SERCOM_I2CS_CTRLA_SLEWRATE_FM         (SERCOM_I2CS_CTRLA_SLEWRATE_FM_Val << SERCOM_I2CS_CTRLA_SLEWRATE_Pos) /* (SERCOM_I2CS_CTRLA) Fast mode Position */
+#define SERCOM_I2CS_CTRLA_SLEWRATE_FMP        (SERCOM_I2CS_CTRLA_SLEWRATE_FMP_Val << SERCOM_I2CS_CTRLA_SLEWRATE_Pos) /* (SERCOM_I2CS_CTRLA) Fast mode plus Position */
+#define SERCOM_I2CS_CTRLA_SLEWRATE_HS         (SERCOM_I2CS_CTRLA_SLEWRATE_HS_Val << SERCOM_I2CS_CTRLA_SLEWRATE_Pos) /* (SERCOM_I2CS_CTRLA) High-speed mode Position */
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos          _UINT32_(16)                                         /* (SERCOM_I2CS_CTRLA) Pin Usage Position */
+#define SERCOM_I2CS_CTRLA_PINOUT_Msk          (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)      /* (SERCOM_I2CS_CTRLA) Pin Usage Mask */
+#define SERCOM_I2CS_CTRLA_PINOUT(value)       (SERCOM_I2CS_CTRLA_PINOUT_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_PINOUT_Pos)) /* Assignment of value for PINOUT in the SERCOM_I2CS_CTRLA register */
+#define SERCOM_I2CS_CTRLA_SMBUSEN_Pos         _UINT32_(17)                                         /* (SERCOM_I2CS_CTRLA) SMBUS Input Buffer Enable Position */
+#define SERCOM_I2CS_CTRLA_SMBUSEN_Msk         (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_SMBUSEN_Pos)     /* (SERCOM_I2CS_CTRLA) SMBUS Input Buffer Enable Mask */
+#define SERCOM_I2CS_CTRLA_SMBUSEN(value)      (SERCOM_I2CS_CTRLA_SMBUSEN_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SMBUSEN_Pos)) /* Assignment of value for SMBUSEN in the SERCOM_I2CS_CTRLA register */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos         _UINT32_(20)                                         /* (SERCOM_I2CS_CTRLA) SDA Hold Time Position */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk         (_UINT32_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)     /* (SERCOM_I2CS_CTRLA) SDA Hold Time Mask */
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value)      (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)) /* Assignment of value for SDAHOLD in the SERCOM_I2CS_CTRLA register */
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_DIS_Val   _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLA) Disable  */
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_75NS_Val  _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLA) 50ns - 100ns hold time  */
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_450NS_Val _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLA) 300ns - 600ns hold time  */
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_600NS_Val _UINT32_(0x3)                                        /* (SERCOM_I2CS_CTRLA) 400ns - 800ns hold time  */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_DIS         (SERCOM_I2CS_CTRLA_SDAHOLD_DIS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CS_CTRLA) Disable Position */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_75NS        (SERCOM_I2CS_CTRLA_SDAHOLD_75NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CS_CTRLA) 50ns - 100ns hold time Position */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_450NS       (SERCOM_I2CS_CTRLA_SDAHOLD_450NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CS_CTRLA) 300ns - 600ns hold time Position */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_600NS       (SERCOM_I2CS_CTRLA_SDAHOLD_600NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /* (SERCOM_I2CS_CTRLA) 400ns - 800ns hold time Position */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos        _UINT32_(23)                                         /* (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout Position */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Msk        (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)    /* (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout Mask */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN(value)     (SERCOM_I2CS_CTRLA_SEXTTOEN_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)) /* Assignment of value for SEXTTOEN in the SERCOM_I2CS_CTRLA register */
+#define SERCOM_I2CS_CTRLA_SPEED_Pos           _UINT32_(24)                                         /* (SERCOM_I2CS_CTRLA) Transfer Speed Position */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk           (_UINT32_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)       /* (SERCOM_I2CS_CTRLA) Transfer Speed Mask */
+#define SERCOM_I2CS_CTRLA_SPEED(value)        (SERCOM_I2CS_CTRLA_SPEED_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SPEED_Pos)) /* Assignment of value for SPEED in the SERCOM_I2CS_CTRLA register */
+#define   SERCOM_I2CS_CTRLA_SPEED_SM_Val      _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLA) Standard-Mode (SM) and Fast-Mode (FM)  */
+#define   SERCOM_I2CS_CTRLA_SPEED_FMP_Val     _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLA) Fast-Mode Plus (FM+)  */
+#define   SERCOM_I2CS_CTRLA_SPEED_HS_Val      _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLA) High-Speed Mode  */
+#define SERCOM_I2CS_CTRLA_SPEED_SM            (SERCOM_I2CS_CTRLA_SPEED_SM_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /* (SERCOM_I2CS_CTRLA) Standard-Mode (SM) and Fast-Mode (FM) Position */
+#define SERCOM_I2CS_CTRLA_SPEED_FMP           (SERCOM_I2CS_CTRLA_SPEED_FMP_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /* (SERCOM_I2CS_CTRLA) Fast-Mode Plus (FM+) Position */
+#define SERCOM_I2CS_CTRLA_SPEED_HS            (SERCOM_I2CS_CTRLA_SPEED_HS_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /* (SERCOM_I2CS_CTRLA) High-Speed Mode Position */
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos           _UINT32_(27)                                         /* (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode Position */
+#define SERCOM_I2CS_CTRLA_SCLSM_Msk           (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)       /* (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode Mask */
+#define SERCOM_I2CS_CTRLA_SCLSM(value)        (SERCOM_I2CS_CTRLA_SCLSM_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_SCLSM_Pos)) /* Assignment of value for SCLSM in the SERCOM_I2CS_CTRLA register */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos       _UINT32_(30)                                         /* (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable Position */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Msk       (_UINT32_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)   /* (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable Mask */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN(value)    (SERCOM_I2CS_CTRLA_LOWTOUTEN_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)) /* Assignment of value for LOWTOUTEN in the SERCOM_I2CS_CTRLA register */
+#define SERCOM_I2CS_CTRLA_Msk                 _UINT32_(0x4BB30F9F)                                 /* (SERCOM_I2CS_CTRLA) Register Mask  */
+
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI Control A -------- */
+#define SERCOM_SPI_CTRLA_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_SPI_CTRLA) SPI Control A  Reset Value */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos            _UINT32_(0)                                          /* (SERCOM_SPI_CTRLA) Software Reset Position */
+#define SERCOM_SPI_CTRLA_SWRST_Msk            (_UINT32_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos)        /* (SERCOM_SPI_CTRLA) Software Reset Mask */
+#define SERCOM_SPI_CTRLA_SWRST(value)         (SERCOM_SPI_CTRLA_SWRST_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the SERCOM_SPI_CTRLA register */
+#define SERCOM_SPI_CTRLA_ENABLE_Pos           _UINT32_(1)                                          /* (SERCOM_SPI_CTRLA) Enable Position */
+#define SERCOM_SPI_CTRLA_ENABLE_Msk           (_UINT32_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos)       /* (SERCOM_SPI_CTRLA) Enable Mask */
+#define SERCOM_SPI_CTRLA_ENABLE(value)        (SERCOM_SPI_CTRLA_ENABLE_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the SERCOM_SPI_CTRLA register */
+#define SERCOM_SPI_CTRLA_MODE_Pos             _UINT32_(2)                                          /* (SERCOM_SPI_CTRLA) Operating Mode Position */
+#define SERCOM_SPI_CTRLA_MODE_Msk             (_UINT32_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos)         /* (SERCOM_SPI_CTRLA) Operating Mode Mask */
+#define SERCOM_SPI_CTRLA_MODE(value)          (SERCOM_SPI_CTRLA_MODE_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the SERCOM_SPI_CTRLA register */
+#define   SERCOM_SPI_CTRLA_MODE_SLAVE_Val     _UINT32_(0x2)                                        /* (SERCOM_SPI_CTRLA) SPI slave operation  */
+#define   SERCOM_SPI_CTRLA_MODE_MASTER_Val    _UINT32_(0x3)                                        /* (SERCOM_SPI_CTRLA) SPI master operation  */
+#define SERCOM_SPI_CTRLA_MODE_SLAVE           (SERCOM_SPI_CTRLA_MODE_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) /* (SERCOM_SPI_CTRLA) SPI slave operation Position */
+#define SERCOM_SPI_CTRLA_MODE_MASTER          (SERCOM_SPI_CTRLA_MODE_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) /* (SERCOM_SPI_CTRLA) SPI master operation Position */
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos         _UINT32_(7)                                          /* (SERCOM_SPI_CTRLA) Run during Standby Position */
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Msk         (_UINT32_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)     /* (SERCOM_SPI_CTRLA) Run during Standby Mask */
+#define SERCOM_SPI_CTRLA_RUNSTDBY(value)      (SERCOM_SPI_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the SERCOM_SPI_CTRLA register */
+#define SERCOM_SPI_CTRLA_IBON_Pos             _UINT32_(8)                                          /* (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification Position */
+#define SERCOM_SPI_CTRLA_IBON_Msk             (_UINT32_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos)         /* (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification Mask */
+#define SERCOM_SPI_CTRLA_IBON(value)          (SERCOM_SPI_CTRLA_IBON_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_IBON_Pos)) /* Assignment of value for IBON in the SERCOM_SPI_CTRLA register */
+#define SERCOM_SPI_CTRLA_DOPO_Pos             _UINT32_(16)                                         /* (SERCOM_SPI_CTRLA) Data Out Pinout Position */
+#define SERCOM_SPI_CTRLA_DOPO_Msk             (_UINT32_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos)         /* (SERCOM_SPI_CTRLA) Data Out Pinout Mask */
+#define SERCOM_SPI_CTRLA_DOPO(value)          (SERCOM_SPI_CTRLA_DOPO_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_DOPO_Pos)) /* Assignment of value for DOPO in the SERCOM_SPI_CTRLA register */
+#define   SERCOM_SPI_CTRLA_DOPO_PAD0_Val      _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2]  */
+#define   SERCOM_SPI_CTRLA_DOPO_PAD3_Val      _UINT32_(0x2)                                        /* (SERCOM_SPI_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2]  */
+#define SERCOM_SPI_CTRLA_DOPO_PAD0            (SERCOM_SPI_CTRLA_DOPO_PAD0_Val << SERCOM_SPI_CTRLA_DOPO_Pos) /* (SERCOM_SPI_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2] Position */
+#define SERCOM_SPI_CTRLA_DOPO_PAD3            (SERCOM_SPI_CTRLA_DOPO_PAD3_Val << SERCOM_SPI_CTRLA_DOPO_Pos) /* (SERCOM_SPI_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2] Position */
+#define SERCOM_SPI_CTRLA_DIPO_Pos             _UINT32_(20)                                         /* (SERCOM_SPI_CTRLA) Data In Pinout Position */
+#define SERCOM_SPI_CTRLA_DIPO_Msk             (_UINT32_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos)         /* (SERCOM_SPI_CTRLA) Data In Pinout Mask */
+#define SERCOM_SPI_CTRLA_DIPO(value)          (SERCOM_SPI_CTRLA_DIPO_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_DIPO_Pos)) /* Assignment of value for DIPO in the SERCOM_SPI_CTRLA register */
+#define   SERCOM_SPI_CTRLA_DIPO_PAD0_Val      _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLA) SERCOM PAD0 is used as data input  */
+#define   SERCOM_SPI_CTRLA_DIPO_PAD1_Val      _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLA) SERCOM PAD1 is used as data input  */
+#define   SERCOM_SPI_CTRLA_DIPO_PAD2_Val      _UINT32_(0x2)                                        /* (SERCOM_SPI_CTRLA) SERCOM PAD2 is used as data input  */
+#define   SERCOM_SPI_CTRLA_DIPO_PAD3_Val      _UINT32_(0x3)                                        /* (SERCOM_SPI_CTRLA) SERCOM PAD3 is used as data input  */
+#define SERCOM_SPI_CTRLA_DIPO_PAD0            (SERCOM_SPI_CTRLA_DIPO_PAD0_Val << SERCOM_SPI_CTRLA_DIPO_Pos) /* (SERCOM_SPI_CTRLA) SERCOM PAD0 is used as data input Position */
+#define SERCOM_SPI_CTRLA_DIPO_PAD1            (SERCOM_SPI_CTRLA_DIPO_PAD1_Val << SERCOM_SPI_CTRLA_DIPO_Pos) /* (SERCOM_SPI_CTRLA) SERCOM PAD1 is used as data input Position */
+#define SERCOM_SPI_CTRLA_DIPO_PAD2            (SERCOM_SPI_CTRLA_DIPO_PAD2_Val << SERCOM_SPI_CTRLA_DIPO_Pos) /* (SERCOM_SPI_CTRLA) SERCOM PAD2 is used as data input Position */
+#define SERCOM_SPI_CTRLA_DIPO_PAD3            (SERCOM_SPI_CTRLA_DIPO_PAD3_Val << SERCOM_SPI_CTRLA_DIPO_Pos) /* (SERCOM_SPI_CTRLA) SERCOM PAD3 is used as data input Position */
+#define SERCOM_SPI_CTRLA_FORM_Pos             _UINT32_(24)                                         /* (SERCOM_SPI_CTRLA) Frame Format Position */
+#define SERCOM_SPI_CTRLA_FORM_Msk             (_UINT32_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos)         /* (SERCOM_SPI_CTRLA) Frame Format Mask */
+#define SERCOM_SPI_CTRLA_FORM(value)          (SERCOM_SPI_CTRLA_FORM_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_FORM_Pos)) /* Assignment of value for FORM in the SERCOM_SPI_CTRLA register */
+#define   SERCOM_SPI_CTRLA_FORM_SPI_Val       _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLA) SPI frame  */
+#define   SERCOM_SPI_CTRLA_FORM_ADDR_Val      _UINT32_(0x2)                                        /* (SERCOM_SPI_CTRLA) SPI frame with address  */
+#define SERCOM_SPI_CTRLA_FORM_SPI             (SERCOM_SPI_CTRLA_FORM_SPI_Val << SERCOM_SPI_CTRLA_FORM_Pos) /* (SERCOM_SPI_CTRLA) SPI frame Position */
+#define SERCOM_SPI_CTRLA_FORM_ADDR            (SERCOM_SPI_CTRLA_FORM_ADDR_Val << SERCOM_SPI_CTRLA_FORM_Pos) /* (SERCOM_SPI_CTRLA) SPI frame with address Position */
+#define SERCOM_SPI_CTRLA_CPHA_Pos             _UINT32_(28)                                         /* (SERCOM_SPI_CTRLA) Clock Phase Position */
+#define SERCOM_SPI_CTRLA_CPHA_Msk             (_UINT32_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos)         /* (SERCOM_SPI_CTRLA) Clock Phase Mask */
+#define SERCOM_SPI_CTRLA_CPHA(value)          (SERCOM_SPI_CTRLA_CPHA_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_CPHA_Pos)) /* Assignment of value for CPHA in the SERCOM_SPI_CTRLA register */
+#define   SERCOM_SPI_CTRLA_CPHA_LEADING_EDGE_Val _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge  */
+#define   SERCOM_SPI_CTRLA_CPHA_TRAILING_EDGE_Val _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge  */
+#define SERCOM_SPI_CTRLA_CPHA_LEADING_EDGE    (SERCOM_SPI_CTRLA_CPHA_LEADING_EDGE_Val << SERCOM_SPI_CTRLA_CPHA_Pos) /* (SERCOM_SPI_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge Position */
+#define SERCOM_SPI_CTRLA_CPHA_TRAILING_EDGE   (SERCOM_SPI_CTRLA_CPHA_TRAILING_EDGE_Val << SERCOM_SPI_CTRLA_CPHA_Pos) /* (SERCOM_SPI_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge Position */
+#define SERCOM_SPI_CTRLA_CPOL_Pos             _UINT32_(29)                                         /* (SERCOM_SPI_CTRLA) Clock Polarity Position */
+#define SERCOM_SPI_CTRLA_CPOL_Msk             (_UINT32_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos)         /* (SERCOM_SPI_CTRLA) Clock Polarity Mask */
+#define SERCOM_SPI_CTRLA_CPOL(value)          (SERCOM_SPI_CTRLA_CPOL_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_CPOL_Pos)) /* Assignment of value for CPOL in the SERCOM_SPI_CTRLA register */
+#define   SERCOM_SPI_CTRLA_CPOL_LOW_Val       _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLA) SCK is low when idle  */
+#define   SERCOM_SPI_CTRLA_CPOL_HIGH_Val      _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLA) SCK is high when idle  */
+#define SERCOM_SPI_CTRLA_CPOL_LOW             (SERCOM_SPI_CTRLA_CPOL_LOW_Val << SERCOM_SPI_CTRLA_CPOL_Pos) /* (SERCOM_SPI_CTRLA) SCK is low when idle Position */
+#define SERCOM_SPI_CTRLA_CPOL_HIGH            (SERCOM_SPI_CTRLA_CPOL_HIGH_Val << SERCOM_SPI_CTRLA_CPOL_Pos) /* (SERCOM_SPI_CTRLA) SCK is high when idle Position */
+#define SERCOM_SPI_CTRLA_DORD_Pos             _UINT32_(30)                                         /* (SERCOM_SPI_CTRLA) Data Order Position */
+#define SERCOM_SPI_CTRLA_DORD_Msk             (_UINT32_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos)         /* (SERCOM_SPI_CTRLA) Data Order Mask */
+#define SERCOM_SPI_CTRLA_DORD(value)          (SERCOM_SPI_CTRLA_DORD_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLA_DORD_Pos)) /* Assignment of value for DORD in the SERCOM_SPI_CTRLA register */
+#define   SERCOM_SPI_CTRLA_DORD_MSB_Val       _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLA) MSB is transmitted first  */
+#define   SERCOM_SPI_CTRLA_DORD_LSB_Val       _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLA) LSB is transmitted first  */
+#define SERCOM_SPI_CTRLA_DORD_MSB             (SERCOM_SPI_CTRLA_DORD_MSB_Val << SERCOM_SPI_CTRLA_DORD_Pos) /* (SERCOM_SPI_CTRLA) MSB is transmitted first Position */
+#define SERCOM_SPI_CTRLA_DORD_LSB             (SERCOM_SPI_CTRLA_DORD_LSB_Val << SERCOM_SPI_CTRLA_DORD_Pos) /* (SERCOM_SPI_CTRLA) LSB is transmitted first Position */
+#define SERCOM_SPI_CTRLA_Msk                  _UINT32_(0x7F33019F)                                 /* (SERCOM_SPI_CTRLA) Register Mask  */
+
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART Control A -------- */
+#define SERCOM_USART_CTRLA_RESETVALUE         _UINT32_(0x00)                                       /*  (SERCOM_USART_CTRLA) USART Control A  Reset Value */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos          _UINT32_(0)                                          /* (SERCOM_USART_CTRLA) Software Reset Position */
+#define SERCOM_USART_CTRLA_SWRST_Msk          (_UINT32_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos)      /* (SERCOM_USART_CTRLA) Software Reset Mask */
+#define SERCOM_USART_CTRLA_SWRST(value)       (SERCOM_USART_CTRLA_SWRST_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the SERCOM_USART_CTRLA register */
+#define SERCOM_USART_CTRLA_ENABLE_Pos         _UINT32_(1)                                          /* (SERCOM_USART_CTRLA) Enable Position */
+#define SERCOM_USART_CTRLA_ENABLE_Msk         (_UINT32_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos)     /* (SERCOM_USART_CTRLA) Enable Mask */
+#define SERCOM_USART_CTRLA_ENABLE(value)      (SERCOM_USART_CTRLA_ENABLE_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the SERCOM_USART_CTRLA register */
+#define SERCOM_USART_CTRLA_MODE_Pos           _UINT32_(2)                                          /* (SERCOM_USART_CTRLA) Operating Mode Position */
+#define SERCOM_USART_CTRLA_MODE_Msk           (_UINT32_(0x7) << SERCOM_USART_CTRLA_MODE_Pos)       /* (SERCOM_USART_CTRLA) Operating Mode Mask */
+#define SERCOM_USART_CTRLA_MODE(value)        (SERCOM_USART_CTRLA_MODE_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the SERCOM_USART_CTRLA register */
+#define   SERCOM_USART_CTRLA_MODE_EXTCLK_Val  _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLA) USART with external clock  */
+#define   SERCOM_USART_CTRLA_MODE_INTCLK_Val  _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLA) Usart with internal clock  */
+#define SERCOM_USART_CTRLA_MODE_EXTCLK        (SERCOM_USART_CTRLA_MODE_EXTCLK_Val << SERCOM_USART_CTRLA_MODE_Pos) /* (SERCOM_USART_CTRLA) USART with external clock Position */
+#define SERCOM_USART_CTRLA_MODE_INTCLK        (SERCOM_USART_CTRLA_MODE_INTCLK_Val << SERCOM_USART_CTRLA_MODE_Pos) /* (SERCOM_USART_CTRLA) Usart with internal clock Position */
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos       _UINT32_(7)                                          /* (SERCOM_USART_CTRLA) Run during Standby Position */
+#define SERCOM_USART_CTRLA_RUNSTDBY_Msk       (_UINT32_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos)   /* (SERCOM_USART_CTRLA) Run during Standby Mask */
+#define SERCOM_USART_CTRLA_RUNSTDBY(value)    (SERCOM_USART_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the SERCOM_USART_CTRLA register */
+#define SERCOM_USART_CTRLA_IBON_Pos           _UINT32_(8)                                          /* (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification Position */
+#define SERCOM_USART_CTRLA_IBON_Msk           (_UINT32_(0x1) << SERCOM_USART_CTRLA_IBON_Pos)       /* (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification Mask */
+#define SERCOM_USART_CTRLA_IBON(value)        (SERCOM_USART_CTRLA_IBON_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_IBON_Pos)) /* Assignment of value for IBON in the SERCOM_USART_CTRLA register */
+#define SERCOM_USART_CTRLA_TXINV_Pos          _UINT32_(9)                                          /* (SERCOM_USART_CTRLA) Transmit Data Invert Position */
+#define SERCOM_USART_CTRLA_TXINV_Msk          (_UINT32_(0x1) << SERCOM_USART_CTRLA_TXINV_Pos)      /* (SERCOM_USART_CTRLA) Transmit Data Invert Mask */
+#define SERCOM_USART_CTRLA_TXINV(value)       (SERCOM_USART_CTRLA_TXINV_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_TXINV_Pos)) /* Assignment of value for TXINV in the SERCOM_USART_CTRLA register */
+#define   SERCOM_USART_CTRLA_TXINV_DISABLE_Val _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLA) TxD is not inverted  */
+#define   SERCOM_USART_CTRLA_TXINV_INV_Val    _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLA) TxD is inverted  */
+#define SERCOM_USART_CTRLA_TXINV_DISABLE      (SERCOM_USART_CTRLA_TXINV_DISABLE_Val << SERCOM_USART_CTRLA_TXINV_Pos) /* (SERCOM_USART_CTRLA) TxD is not inverted Position */
+#define SERCOM_USART_CTRLA_TXINV_INV          (SERCOM_USART_CTRLA_TXINV_INV_Val << SERCOM_USART_CTRLA_TXINV_Pos) /* (SERCOM_USART_CTRLA) TxD is inverted Position */
+#define SERCOM_USART_CTRLA_RXINV_Pos          _UINT32_(10)                                         /* (SERCOM_USART_CTRLA) Receive Data Invert Position */
+#define SERCOM_USART_CTRLA_RXINV_Msk          (_UINT32_(0x1) << SERCOM_USART_CTRLA_RXINV_Pos)      /* (SERCOM_USART_CTRLA) Receive Data Invert Mask */
+#define SERCOM_USART_CTRLA_RXINV(value)       (SERCOM_USART_CTRLA_RXINV_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_RXINV_Pos)) /* Assignment of value for RXINV in the SERCOM_USART_CTRLA register */
+#define   SERCOM_USART_CTRLA_RXINV_DISABLE_Val _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLA) RxD is not inverted  */
+#define   SERCOM_USART_CTRLA_RXINV_INV_Val    _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLA) RxD is inverted  */
+#define SERCOM_USART_CTRLA_RXINV_DISABLE      (SERCOM_USART_CTRLA_RXINV_DISABLE_Val << SERCOM_USART_CTRLA_RXINV_Pos) /* (SERCOM_USART_CTRLA) RxD is not inverted Position */
+#define SERCOM_USART_CTRLA_RXINV_INV          (SERCOM_USART_CTRLA_RXINV_INV_Val << SERCOM_USART_CTRLA_RXINV_Pos) /* (SERCOM_USART_CTRLA) RxD is inverted Position */
+#define SERCOM_USART_CTRLA_SAMPR_Pos          _UINT32_(13)                                         /* (SERCOM_USART_CTRLA) Sample Position */
+#define SERCOM_USART_CTRLA_SAMPR_Msk          (_UINT32_(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos)      /* (SERCOM_USART_CTRLA) Sample Mask */
+#define SERCOM_USART_CTRLA_SAMPR(value)       (SERCOM_USART_CTRLA_SAMPR_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_SAMPR_Pos)) /* Assignment of value for SAMPR in the SERCOM_USART_CTRLA register */
+#define   SERCOM_USART_CTRLA_SAMPR_ARITHM16X_Val _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLA) 16x oversampling using arithmetic baud rate generation  */
+#define   SERCOM_USART_CTRLA_SAMPR_FRAC16X_Val _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLA) 16x oversampling using fractional baud rate generation  */
+#define   SERCOM_USART_CTRLA_SAMPR_ARITHM8X_Val _UINT32_(0x2)                                        /* (SERCOM_USART_CTRLA) 8x oversampling using arithmetic baud rate generation  */
+#define   SERCOM_USART_CTRLA_SAMPR_FRAC8X_Val _UINT32_(0x3)                                        /* (SERCOM_USART_CTRLA) 8x oversampling using fractional baud rate generation  */
+#define   SERCOM_USART_CTRLA_SAMPR_ARITHM3X_Val _UINT32_(0x4)                                        /* (SERCOM_USART_CTRLA) 3x oversampling using arithmetic baud rate generation  */
+#define SERCOM_USART_CTRLA_SAMPR_ARITHM16X    (SERCOM_USART_CTRLA_SAMPR_ARITHM16X_Val << SERCOM_USART_CTRLA_SAMPR_Pos) /* (SERCOM_USART_CTRLA) 16x oversampling using arithmetic baud rate generation Position */
+#define SERCOM_USART_CTRLA_SAMPR_FRAC16X      (SERCOM_USART_CTRLA_SAMPR_FRAC16X_Val << SERCOM_USART_CTRLA_SAMPR_Pos) /* (SERCOM_USART_CTRLA) 16x oversampling using fractional baud rate generation Position */
+#define SERCOM_USART_CTRLA_SAMPR_ARITHM8X     (SERCOM_USART_CTRLA_SAMPR_ARITHM8X_Val << SERCOM_USART_CTRLA_SAMPR_Pos) /* (SERCOM_USART_CTRLA) 8x oversampling using arithmetic baud rate generation Position */
+#define SERCOM_USART_CTRLA_SAMPR_FRAC8X       (SERCOM_USART_CTRLA_SAMPR_FRAC8X_Val << SERCOM_USART_CTRLA_SAMPR_Pos) /* (SERCOM_USART_CTRLA) 8x oversampling using fractional baud rate generation Position */
+#define SERCOM_USART_CTRLA_SAMPR_ARITHM3X     (SERCOM_USART_CTRLA_SAMPR_ARITHM3X_Val << SERCOM_USART_CTRLA_SAMPR_Pos) /* (SERCOM_USART_CTRLA) 3x oversampling using arithmetic baud rate generation Position */
+#define SERCOM_USART_CTRLA_TXPO_Pos           _UINT32_(16)                                         /* (SERCOM_USART_CTRLA) Transmit Data Pinout Position */
+#define SERCOM_USART_CTRLA_TXPO_Msk           (_UINT32_(0x3) << SERCOM_USART_CTRLA_TXPO_Pos)       /* (SERCOM_USART_CTRLA) Transmit Data Pinout Mask */
+#define SERCOM_USART_CTRLA_TXPO(value)        (SERCOM_USART_CTRLA_TXPO_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_TXPO_Pos)) /* Assignment of value for TXPO in the SERCOM_USART_CTRLA register */
+#define   SERCOM_USART_CTRLA_TXPO_PAD0_Val    _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLA) PAD[0] = TxD; PAD[1] = XCK  */
+#define   SERCOM_USART_CTRLA_TXPO_PAD2_Val    _UINT32_(0x2)                                        /* (SERCOM_USART_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS  */
+#define   SERCOM_USART_CTRLA_TXPO_PAD3_Val    _UINT32_(0x3)                                        /* (SERCOM_USART_CTRLA) PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE  */
+#define SERCOM_USART_CTRLA_TXPO_PAD0          (SERCOM_USART_CTRLA_TXPO_PAD0_Val << SERCOM_USART_CTRLA_TXPO_Pos) /* (SERCOM_USART_CTRLA) PAD[0] = TxD; PAD[1] = XCK Position */
+#define SERCOM_USART_CTRLA_TXPO_PAD2          (SERCOM_USART_CTRLA_TXPO_PAD2_Val << SERCOM_USART_CTRLA_TXPO_Pos) /* (SERCOM_USART_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS Position */
+#define SERCOM_USART_CTRLA_TXPO_PAD3          (SERCOM_USART_CTRLA_TXPO_PAD3_Val << SERCOM_USART_CTRLA_TXPO_Pos) /* (SERCOM_USART_CTRLA) PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE Position */
+#define SERCOM_USART_CTRLA_RXPO_Pos           _UINT32_(20)                                         /* (SERCOM_USART_CTRLA) Receive Data Pinout Position */
+#define SERCOM_USART_CTRLA_RXPO_Msk           (_UINT32_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos)       /* (SERCOM_USART_CTRLA) Receive Data Pinout Mask */
+#define SERCOM_USART_CTRLA_RXPO(value)        (SERCOM_USART_CTRLA_RXPO_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_RXPO_Pos)) /* Assignment of value for RXPO in the SERCOM_USART_CTRLA register */
+#define   SERCOM_USART_CTRLA_RXPO_PAD0_Val    _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLA) SERCOM PAD0 is used for data reception  */
+#define   SERCOM_USART_CTRLA_RXPO_PAD1_Val    _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLA) SERCOM PAD1 is used for data reception  */
+#define   SERCOM_USART_CTRLA_RXPO_PAD2_Val    _UINT32_(0x2)                                        /* (SERCOM_USART_CTRLA) SERCOM PAD2 is used for data reception  */
+#define   SERCOM_USART_CTRLA_RXPO_PAD3_Val    _UINT32_(0x3)                                        /* (SERCOM_USART_CTRLA) SERCOM PAD3 is used for data reception  */
+#define SERCOM_USART_CTRLA_RXPO_PAD0          (SERCOM_USART_CTRLA_RXPO_PAD0_Val << SERCOM_USART_CTRLA_RXPO_Pos) /* (SERCOM_USART_CTRLA) SERCOM PAD0 is used for data reception Position */
+#define SERCOM_USART_CTRLA_RXPO_PAD1          (SERCOM_USART_CTRLA_RXPO_PAD1_Val << SERCOM_USART_CTRLA_RXPO_Pos) /* (SERCOM_USART_CTRLA) SERCOM PAD1 is used for data reception Position */
+#define SERCOM_USART_CTRLA_RXPO_PAD2          (SERCOM_USART_CTRLA_RXPO_PAD2_Val << SERCOM_USART_CTRLA_RXPO_Pos) /* (SERCOM_USART_CTRLA) SERCOM PAD2 is used for data reception Position */
+#define SERCOM_USART_CTRLA_RXPO_PAD3          (SERCOM_USART_CTRLA_RXPO_PAD3_Val << SERCOM_USART_CTRLA_RXPO_Pos) /* (SERCOM_USART_CTRLA) SERCOM PAD3 is used for data reception Position */
+#define SERCOM_USART_CTRLA_SAMPA_Pos          _UINT32_(22)                                         /* (SERCOM_USART_CTRLA) Sample Adjustment Position */
+#define SERCOM_USART_CTRLA_SAMPA_Msk          (_UINT32_(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos)      /* (SERCOM_USART_CTRLA) Sample Adjustment Mask */
+#define SERCOM_USART_CTRLA_SAMPA(value)       (SERCOM_USART_CTRLA_SAMPA_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_SAMPA_Pos)) /* Assignment of value for SAMPA in the SERCOM_USART_CTRLA register */
+#define SERCOM_USART_CTRLA_FORM_Pos           _UINT32_(24)                                         /* (SERCOM_USART_CTRLA) Frame Format Position */
+#define SERCOM_USART_CTRLA_FORM_Msk           (_UINT32_(0xF) << SERCOM_USART_CTRLA_FORM_Pos)       /* (SERCOM_USART_CTRLA) Frame Format Mask */
+#define SERCOM_USART_CTRLA_FORM(value)        (SERCOM_USART_CTRLA_FORM_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_FORM_Pos)) /* Assignment of value for FORM in the SERCOM_USART_CTRLA register */
+#define   SERCOM_USART_CTRLA_FORM_USART_Val   _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLA) USART frame  */
+#define   SERCOM_USART_CTRLA_FORM_USARTP_Val  _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLA) USART frame with parity  */
+#define   SERCOM_USART_CTRLA_FORM_LINBRKGEN_Val _UINT32_(0x2)                                        /* (SERCOM_USART_CTRLA) LIN Master Break and Synck generation  */
+#define   SERCOM_USART_CTRLA_FORM_LINBRKDET_Val _UINT32_(0x4)                                        /* (SERCOM_USART_CTRLA) LIN Slave break detection and auto-baud  */
+#define   SERCOM_USART_CTRLA_FORM_BRKDET_Val  _UINT32_(0x5)                                        /* (SERCOM_USART_CTRLA) Break detection and auto-baud with parity  */
+#define SERCOM_USART_CTRLA_FORM_USART         (SERCOM_USART_CTRLA_FORM_USART_Val << SERCOM_USART_CTRLA_FORM_Pos) /* (SERCOM_USART_CTRLA) USART frame Position */
+#define SERCOM_USART_CTRLA_FORM_USARTP        (SERCOM_USART_CTRLA_FORM_USARTP_Val << SERCOM_USART_CTRLA_FORM_Pos) /* (SERCOM_USART_CTRLA) USART frame with parity Position */
+#define SERCOM_USART_CTRLA_FORM_LINBRKGEN     (SERCOM_USART_CTRLA_FORM_LINBRKGEN_Val << SERCOM_USART_CTRLA_FORM_Pos) /* (SERCOM_USART_CTRLA) LIN Master Break and Synck generation Position */
+#define SERCOM_USART_CTRLA_FORM_LINBRKDET     (SERCOM_USART_CTRLA_FORM_LINBRKDET_Val << SERCOM_USART_CTRLA_FORM_Pos) /* (SERCOM_USART_CTRLA) LIN Slave break detection and auto-baud Position */
+#define SERCOM_USART_CTRLA_FORM_BRKDET        (SERCOM_USART_CTRLA_FORM_BRKDET_Val << SERCOM_USART_CTRLA_FORM_Pos) /* (SERCOM_USART_CTRLA) Break detection and auto-baud with parity Position */
+#define SERCOM_USART_CTRLA_CMODE_Pos          _UINT32_(28)                                         /* (SERCOM_USART_CTRLA) Communication Mode Position */
+#define SERCOM_USART_CTRLA_CMODE_Msk          (_UINT32_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos)      /* (SERCOM_USART_CTRLA) Communication Mode Mask */
+#define SERCOM_USART_CTRLA_CMODE(value)       (SERCOM_USART_CTRLA_CMODE_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_CMODE_Pos)) /* Assignment of value for CMODE in the SERCOM_USART_CTRLA register */
+#define   SERCOM_USART_CTRLA_CMODE_ASYNC_Val  _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLA) Asynchronous communication.  */
+#define   SERCOM_USART_CTRLA_CMODE_SYNC_Val   _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLA) Synchronous communication.  */
+#define SERCOM_USART_CTRLA_CMODE_ASYNC        (SERCOM_USART_CTRLA_CMODE_ASYNC_Val << SERCOM_USART_CTRLA_CMODE_Pos) /* (SERCOM_USART_CTRLA) Asynchronous communication. Position */
+#define SERCOM_USART_CTRLA_CMODE_SYNC         (SERCOM_USART_CTRLA_CMODE_SYNC_Val << SERCOM_USART_CTRLA_CMODE_Pos) /* (SERCOM_USART_CTRLA) Synchronous communication. Position */
+#define SERCOM_USART_CTRLA_CPOL_Pos           _UINT32_(29)                                         /* (SERCOM_USART_CTRLA) Clock Polarity Position */
+#define SERCOM_USART_CTRLA_CPOL_Msk           (_UINT32_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos)       /* (SERCOM_USART_CTRLA) Clock Polarity Mask */
+#define SERCOM_USART_CTRLA_CPOL(value)        (SERCOM_USART_CTRLA_CPOL_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_CPOL_Pos)) /* Assignment of value for CPOL in the SERCOM_USART_CTRLA register */
+#define SERCOM_USART_CTRLA_DORD_Pos           _UINT32_(30)                                         /* (SERCOM_USART_CTRLA) Data Order Position */
+#define SERCOM_USART_CTRLA_DORD_Msk           (_UINT32_(0x1) << SERCOM_USART_CTRLA_DORD_Pos)       /* (SERCOM_USART_CTRLA) Data Order Mask */
+#define SERCOM_USART_CTRLA_DORD(value)        (SERCOM_USART_CTRLA_DORD_Msk & (_UINT32_(value) << SERCOM_USART_CTRLA_DORD_Pos)) /* Assignment of value for DORD in the SERCOM_USART_CTRLA register */
+#define   SERCOM_USART_CTRLA_DORD_MSB_Val     _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLA) MSB is transmitted first.  */
+#define   SERCOM_USART_CTRLA_DORD_LSB_Val     _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLA) LSB is transmitted first.  */
+#define SERCOM_USART_CTRLA_DORD_MSB           (SERCOM_USART_CTRLA_DORD_MSB_Val << SERCOM_USART_CTRLA_DORD_Pos) /* (SERCOM_USART_CTRLA) MSB is transmitted first. Position */
+#define SERCOM_USART_CTRLA_DORD_LSB           (SERCOM_USART_CTRLA_DORD_LSB_Val << SERCOM_USART_CTRLA_DORD_Pos) /* (SERCOM_USART_CTRLA) LSB is transmitted first. Position */
+#define SERCOM_USART_CTRLA_Msk                _UINT32_(0x7FF3E79F)                                 /* (SERCOM_USART_CTRLA) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM Control B -------- */
+#define SERCOM_I2CM_CTRLB_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CM_CTRLB) I2CM Control B  Reset Value */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos            _UINT32_(8)                                          /* (SERCOM_I2CM_CTRLB) Smart Mode Enable Position */
+#define SERCOM_I2CM_CTRLB_SMEN_Msk            (_UINT32_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)        /* (SERCOM_I2CM_CTRLB) Smart Mode Enable Mask */
+#define SERCOM_I2CM_CTRLB_SMEN(value)         (SERCOM_I2CM_CTRLB_SMEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLB_SMEN_Pos)) /* Assignment of value for SMEN in the SERCOM_I2CM_CTRLB register */
+#define SERCOM_I2CM_CTRLB_QCEN_Pos            _UINT32_(9)                                          /* (SERCOM_I2CM_CTRLB) Quick Command Enable Position */
+#define SERCOM_I2CM_CTRLB_QCEN_Msk            (_UINT32_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)        /* (SERCOM_I2CM_CTRLB) Quick Command Enable Mask */
+#define SERCOM_I2CM_CTRLB_QCEN(value)         (SERCOM_I2CM_CTRLB_QCEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLB_QCEN_Pos)) /* Assignment of value for QCEN in the SERCOM_I2CM_CTRLB register */
+#define SERCOM_I2CM_CTRLB_CMD_Pos             _UINT32_(16)                                         /* (SERCOM_I2CM_CTRLB) Command Position */
+#define SERCOM_I2CM_CTRLB_CMD_Msk             (_UINT32_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)         /* (SERCOM_I2CM_CTRLB) Command Mask */
+#define SERCOM_I2CM_CTRLB_CMD(value)          (SERCOM_I2CM_CTRLB_CMD_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLB_CMD_Pos)) /* Assignment of value for CMD in the SERCOM_I2CM_CTRLB register */
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos          _UINT32_(18)                                         /* (SERCOM_I2CM_CTRLB) Acknowledge Action Position */
+#define SERCOM_I2CM_CTRLB_ACKACT_Msk          (_UINT32_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)      /* (SERCOM_I2CM_CTRLB) Acknowledge Action Mask */
+#define SERCOM_I2CM_CTRLB_ACKACT(value)       (SERCOM_I2CM_CTRLB_ACKACT_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLB_ACKACT_Pos)) /* Assignment of value for ACKACT in the SERCOM_I2CM_CTRLB register */
+#define SERCOM_I2CM_CTRLB_FIFOCLR_Pos         _UINT32_(22)                                         /* (SERCOM_I2CM_CTRLB) FIFO Clear Position */
+#define SERCOM_I2CM_CTRLB_FIFOCLR_Msk         (_UINT32_(0x3) << SERCOM_I2CM_CTRLB_FIFOCLR_Pos)     /* (SERCOM_I2CM_CTRLB) FIFO Clear Mask */
+#define SERCOM_I2CM_CTRLB_FIFOCLR(value)      (SERCOM_I2CM_CTRLB_FIFOCLR_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLB_FIFOCLR_Pos)) /* Assignment of value for FIFOCLR in the SERCOM_I2CM_CTRLB register */
+#define   SERCOM_I2CM_CTRLB_FIFOCLR_NONE_Val  _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLB) No action  */
+#define   SERCOM_I2CM_CTRLB_FIFOCLR_TXFIFO_Val _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLB) Clear TX FIFO  */
+#define   SERCOM_I2CM_CTRLB_FIFOCLR_RXFIFO_Val _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLB) Clear RX FIFO  */
+#define   SERCOM_I2CM_CTRLB_FIFOCLR_BOTH_Val  _UINT32_(0x3)                                        /* (SERCOM_I2CM_CTRLB) Clear both TX and RF FIFOs  */
+#define SERCOM_I2CM_CTRLB_FIFOCLR_NONE        (SERCOM_I2CM_CTRLB_FIFOCLR_NONE_Val << SERCOM_I2CM_CTRLB_FIFOCLR_Pos) /* (SERCOM_I2CM_CTRLB) No action Position */
+#define SERCOM_I2CM_CTRLB_FIFOCLR_TXFIFO      (SERCOM_I2CM_CTRLB_FIFOCLR_TXFIFO_Val << SERCOM_I2CM_CTRLB_FIFOCLR_Pos) /* (SERCOM_I2CM_CTRLB) Clear TX FIFO Position */
+#define SERCOM_I2CM_CTRLB_FIFOCLR_RXFIFO      (SERCOM_I2CM_CTRLB_FIFOCLR_RXFIFO_Val << SERCOM_I2CM_CTRLB_FIFOCLR_Pos) /* (SERCOM_I2CM_CTRLB) Clear RX FIFO Position */
+#define SERCOM_I2CM_CTRLB_FIFOCLR_BOTH        (SERCOM_I2CM_CTRLB_FIFOCLR_BOTH_Val << SERCOM_I2CM_CTRLB_FIFOCLR_Pos) /* (SERCOM_I2CM_CTRLB) Clear both TX and RF FIFOs Position */
+#define SERCOM_I2CM_CTRLB_Msk                 _UINT32_(0x00C70300)                                 /* (SERCOM_I2CM_CTRLB) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS Control B -------- */
+#define SERCOM_I2CS_CTRLB_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CS_CTRLB) I2CS Control B  Reset Value */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos            _UINT32_(8)                                          /* (SERCOM_I2CS_CTRLB) Smart Mode Enable Position */
+#define SERCOM_I2CS_CTRLB_SMEN_Msk            (_UINT32_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)        /* (SERCOM_I2CS_CTRLB) Smart Mode Enable Mask */
+#define SERCOM_I2CS_CTRLB_SMEN(value)         (SERCOM_I2CS_CTRLB_SMEN_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_SMEN_Pos)) /* Assignment of value for SMEN in the SERCOM_I2CS_CTRLB register */
+#define SERCOM_I2CS_CTRLB_GCMD_Pos            _UINT32_(9)                                          /* (SERCOM_I2CS_CTRLB) PMBus Group Command Position */
+#define SERCOM_I2CS_CTRLB_GCMD_Msk            (_UINT32_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)        /* (SERCOM_I2CS_CTRLB) PMBus Group Command Mask */
+#define SERCOM_I2CS_CTRLB_GCMD(value)         (SERCOM_I2CS_CTRLB_GCMD_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_GCMD_Pos)) /* Assignment of value for GCMD in the SERCOM_I2CS_CTRLB register */
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos          _UINT32_(10)                                         /* (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge Position */
+#define SERCOM_I2CS_CTRLB_AACKEN_Msk          (_UINT32_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos)      /* (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge Mask */
+#define SERCOM_I2CS_CTRLB_AACKEN(value)       (SERCOM_I2CS_CTRLB_AACKEN_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_AACKEN_Pos)) /* Assignment of value for AACKEN in the SERCOM_I2CS_CTRLB register */
+#define SERCOM_I2CS_CTRLB_AMODE_Pos           _UINT32_(14)                                         /* (SERCOM_I2CS_CTRLB) Address Mode Position */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk           (_UINT32_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)       /* (SERCOM_I2CS_CTRLB) Address Mode Mask */
+#define SERCOM_I2CS_CTRLB_AMODE(value)        (SERCOM_I2CS_CTRLB_AMODE_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_AMODE_Pos)) /* Assignment of value for AMODE in the SERCOM_I2CS_CTRLB register */
+#define   SERCOM_I2CS_CTRLB_AMODE_MASK_Val    _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLB) The slave responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK  */
+#define   SERCOM_I2CS_CTRLB_AMODE_2ADDRS_Val  _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLB) The slave responds to the two unique addresses in ADDR and ADDRMASK  */
+#define   SERCOM_I2CS_CTRLB_AMODE_RANGE_Val   _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLB) The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit  */
+#define SERCOM_I2CS_CTRLB_AMODE_MASK          (SERCOM_I2CS_CTRLB_AMODE_MASK_Val << SERCOM_I2CS_CTRLB_AMODE_Pos) /* (SERCOM_I2CS_CTRLB) The slave responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK Position */
+#define SERCOM_I2CS_CTRLB_AMODE_2ADDRS        (SERCOM_I2CS_CTRLB_AMODE_2ADDRS_Val << SERCOM_I2CS_CTRLB_AMODE_Pos) /* (SERCOM_I2CS_CTRLB) The slave responds to the two unique addresses in ADDR and ADDRMASK Position */
+#define SERCOM_I2CS_CTRLB_AMODE_RANGE         (SERCOM_I2CS_CTRLB_AMODE_RANGE_Val << SERCOM_I2CS_CTRLB_AMODE_Pos) /* (SERCOM_I2CS_CTRLB) The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit Position */
+#define SERCOM_I2CS_CTRLB_CMD_Pos             _UINT32_(16)                                         /* (SERCOM_I2CS_CTRLB) Command Position */
+#define SERCOM_I2CS_CTRLB_CMD_Msk             (_UINT32_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)         /* (SERCOM_I2CS_CTRLB) Command Mask */
+#define SERCOM_I2CS_CTRLB_CMD(value)          (SERCOM_I2CS_CTRLB_CMD_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_CMD_Pos)) /* Assignment of value for CMD in the SERCOM_I2CS_CTRLB register */
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos          _UINT32_(18)                                         /* (SERCOM_I2CS_CTRLB) Acknowledge Action Position */
+#define SERCOM_I2CS_CTRLB_ACKACT_Msk          (_UINT32_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)      /* (SERCOM_I2CS_CTRLB) Acknowledge Action Mask */
+#define SERCOM_I2CS_CTRLB_ACKACT(value)       (SERCOM_I2CS_CTRLB_ACKACT_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_ACKACT_Pos)) /* Assignment of value for ACKACT in the SERCOM_I2CS_CTRLB register */
+#define SERCOM_I2CS_CTRLB_FIFOCLR_Pos         _UINT32_(22)                                         /* (SERCOM_I2CS_CTRLB) FIFO Clear Position */
+#define SERCOM_I2CS_CTRLB_FIFOCLR_Msk         (_UINT32_(0x3) << SERCOM_I2CS_CTRLB_FIFOCLR_Pos)     /* (SERCOM_I2CS_CTRLB) FIFO Clear Mask */
+#define SERCOM_I2CS_CTRLB_FIFOCLR(value)      (SERCOM_I2CS_CTRLB_FIFOCLR_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLB_FIFOCLR_Pos)) /* Assignment of value for FIFOCLR in the SERCOM_I2CS_CTRLB register */
+#define   SERCOM_I2CS_CTRLB_FIFOCLR_NONE_Val  _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLB) No action  */
+#define   SERCOM_I2CS_CTRLB_FIFOCLR_TXFIFO_Val _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLB) Clear TX FIFO  */
+#define   SERCOM_I2CS_CTRLB_FIFOCLR_RXFIFO_Val _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLB) Clear RX FIFO  */
+#define   SERCOM_I2CS_CTRLB_FIFOCLR_BOTH_Val  _UINT32_(0x3)                                        /* (SERCOM_I2CS_CTRLB) Clear both TX and RF FIFOs  */
+#define SERCOM_I2CS_CTRLB_FIFOCLR_NONE        (SERCOM_I2CS_CTRLB_FIFOCLR_NONE_Val << SERCOM_I2CS_CTRLB_FIFOCLR_Pos) /* (SERCOM_I2CS_CTRLB) No action Position */
+#define SERCOM_I2CS_CTRLB_FIFOCLR_TXFIFO      (SERCOM_I2CS_CTRLB_FIFOCLR_TXFIFO_Val << SERCOM_I2CS_CTRLB_FIFOCLR_Pos) /* (SERCOM_I2CS_CTRLB) Clear TX FIFO Position */
+#define SERCOM_I2CS_CTRLB_FIFOCLR_RXFIFO      (SERCOM_I2CS_CTRLB_FIFOCLR_RXFIFO_Val << SERCOM_I2CS_CTRLB_FIFOCLR_Pos) /* (SERCOM_I2CS_CTRLB) Clear RX FIFO Position */
+#define SERCOM_I2CS_CTRLB_FIFOCLR_BOTH        (SERCOM_I2CS_CTRLB_FIFOCLR_BOTH_Val << SERCOM_I2CS_CTRLB_FIFOCLR_Pos) /* (SERCOM_I2CS_CTRLB) Clear both TX and RF FIFOs Position */
+#define SERCOM_I2CS_CTRLB_Msk                 _UINT32_(0x00C7C700)                                 /* (SERCOM_I2CS_CTRLB) Register Mask  */
+
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI Control B -------- */
+#define SERCOM_SPI_CTRLB_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_SPI_CTRLB) SPI Control B  Reset Value */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos           _UINT32_(0)                                          /* (SERCOM_SPI_CTRLB) Character Size Position */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk           (_UINT32_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos)       /* (SERCOM_SPI_CTRLB) Character Size Mask */
+#define SERCOM_SPI_CTRLB_CHSIZE(value)        (SERCOM_SPI_CTRLB_CHSIZE_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)) /* Assignment of value for CHSIZE in the SERCOM_SPI_CTRLB register */
+#define   SERCOM_SPI_CTRLB_CHSIZE_8BITS_Val   _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLB) 8-bits character  */
+#define   SERCOM_SPI_CTRLB_CHSIZE_9BITS_Val   _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLB) 9-bits character  */
+#define SERCOM_SPI_CTRLB_CHSIZE_8BITS         (SERCOM_SPI_CTRLB_CHSIZE_8BITS_Val << SERCOM_SPI_CTRLB_CHSIZE_Pos) /* (SERCOM_SPI_CTRLB) 8-bits character Position */
+#define SERCOM_SPI_CTRLB_CHSIZE_9BITS         (SERCOM_SPI_CTRLB_CHSIZE_9BITS_Val << SERCOM_SPI_CTRLB_CHSIZE_Pos) /* (SERCOM_SPI_CTRLB) 9-bits character Position */
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos          _UINT32_(6)                                          /* (SERCOM_SPI_CTRLB) Data Preload Enable Position */
+#define SERCOM_SPI_CTRLB_PLOADEN_Msk          (_UINT32_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos)      /* (SERCOM_SPI_CTRLB) Data Preload Enable Mask */
+#define SERCOM_SPI_CTRLB_PLOADEN(value)       (SERCOM_SPI_CTRLB_PLOADEN_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLB_PLOADEN_Pos)) /* Assignment of value for PLOADEN in the SERCOM_SPI_CTRLB register */
+#define SERCOM_SPI_CTRLB_SSDE_Pos             _UINT32_(9)                                          /* (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable Position */
+#define SERCOM_SPI_CTRLB_SSDE_Msk             (_UINT32_(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos)         /* (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable Mask */
+#define SERCOM_SPI_CTRLB_SSDE(value)          (SERCOM_SPI_CTRLB_SSDE_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLB_SSDE_Pos)) /* Assignment of value for SSDE in the SERCOM_SPI_CTRLB register */
+#define   SERCOM_SPI_CTRLB_SSDE_DISABLE_Val   _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLB) SS low detector is disabled  */
+#define   SERCOM_SPI_CTRLB_SSDE_ENABLE_Val    _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLB) SS low detector is enabled  */
+#define SERCOM_SPI_CTRLB_SSDE_DISABLE         (SERCOM_SPI_CTRLB_SSDE_DISABLE_Val << SERCOM_SPI_CTRLB_SSDE_Pos) /* (SERCOM_SPI_CTRLB) SS low detector is disabled Position */
+#define SERCOM_SPI_CTRLB_SSDE_ENABLE          (SERCOM_SPI_CTRLB_SSDE_ENABLE_Val << SERCOM_SPI_CTRLB_SSDE_Pos) /* (SERCOM_SPI_CTRLB) SS low detector is enabled Position */
+#define SERCOM_SPI_CTRLB_MSSEN_Pos            _UINT32_(13)                                         /* (SERCOM_SPI_CTRLB) Master Slave Select Enable Position */
+#define SERCOM_SPI_CTRLB_MSSEN_Msk            (_UINT32_(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos)        /* (SERCOM_SPI_CTRLB) Master Slave Select Enable Mask */
+#define SERCOM_SPI_CTRLB_MSSEN(value)         (SERCOM_SPI_CTRLB_MSSEN_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLB_MSSEN_Pos)) /* Assignment of value for MSSEN in the SERCOM_SPI_CTRLB register */
+#define   SERCOM_SPI_CTRLB_MSSEN_DISABLE_Val  _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLB) Hardware SS control is disabled  */
+#define   SERCOM_SPI_CTRLB_MSSEN_ENABLE_Val   _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLB) Hardware SS control is enabled  */
+#define SERCOM_SPI_CTRLB_MSSEN_DISABLE        (SERCOM_SPI_CTRLB_MSSEN_DISABLE_Val << SERCOM_SPI_CTRLB_MSSEN_Pos) /* (SERCOM_SPI_CTRLB) Hardware SS control is disabled Position */
+#define SERCOM_SPI_CTRLB_MSSEN_ENABLE         (SERCOM_SPI_CTRLB_MSSEN_ENABLE_Val << SERCOM_SPI_CTRLB_MSSEN_Pos) /* (SERCOM_SPI_CTRLB) Hardware SS control is enabled Position */
+#define SERCOM_SPI_CTRLB_AMODE_Pos            _UINT32_(14)                                         /* (SERCOM_SPI_CTRLB) Address Mode Position */
+#define SERCOM_SPI_CTRLB_AMODE_Msk            (_UINT32_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos)        /* (SERCOM_SPI_CTRLB) Address Mode Mask */
+#define SERCOM_SPI_CTRLB_AMODE(value)         (SERCOM_SPI_CTRLB_AMODE_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLB_AMODE_Pos)) /* Assignment of value for AMODE in the SERCOM_SPI_CTRLB register */
+#define   SERCOM_SPI_CTRLB_AMODE_MASK_Val     _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLB) ADDRMASK is used as a mask to the AADR register  */
+#define   SERCOM_SPI_CTRLB_AMODE_2ADDRS_Val   _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLB) The slave responds to the two unique addresses in ADDR and ADDRMASK  */
+#define   SERCOM_SPI_CTRLB_AMODE_RANGE_Val    _UINT32_(0x2)                                        /* (SERCOM_SPI_CTRLB) The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit  */
+#define SERCOM_SPI_CTRLB_AMODE_MASK           (SERCOM_SPI_CTRLB_AMODE_MASK_Val << SERCOM_SPI_CTRLB_AMODE_Pos) /* (SERCOM_SPI_CTRLB) ADDRMASK is used as a mask to the AADR register Position */
+#define SERCOM_SPI_CTRLB_AMODE_2ADDRS         (SERCOM_SPI_CTRLB_AMODE_2ADDRS_Val << SERCOM_SPI_CTRLB_AMODE_Pos) /* (SERCOM_SPI_CTRLB) The slave responds to the two unique addresses in ADDR and ADDRMASK Position */
+#define SERCOM_SPI_CTRLB_AMODE_RANGE          (SERCOM_SPI_CTRLB_AMODE_RANGE_Val << SERCOM_SPI_CTRLB_AMODE_Pos) /* (SERCOM_SPI_CTRLB) The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit Position */
+#define SERCOM_SPI_CTRLB_RXEN_Pos             _UINT32_(17)                                         /* (SERCOM_SPI_CTRLB) Receiver Enable Position */
+#define SERCOM_SPI_CTRLB_RXEN_Msk             (_UINT32_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos)         /* (SERCOM_SPI_CTRLB) Receiver Enable Mask */
+#define SERCOM_SPI_CTRLB_RXEN(value)          (SERCOM_SPI_CTRLB_RXEN_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLB_RXEN_Pos)) /* Assignment of value for RXEN in the SERCOM_SPI_CTRLB register */
+#define SERCOM_SPI_CTRLB_FIFOCLR_Pos          _UINT32_(22)                                         /* (SERCOM_SPI_CTRLB) FIFO Clear Position */
+#define SERCOM_SPI_CTRLB_FIFOCLR_Msk          (_UINT32_(0x3) << SERCOM_SPI_CTRLB_FIFOCLR_Pos)      /* (SERCOM_SPI_CTRLB) FIFO Clear Mask */
+#define SERCOM_SPI_CTRLB_FIFOCLR(value)       (SERCOM_SPI_CTRLB_FIFOCLR_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLB_FIFOCLR_Pos)) /* Assignment of value for FIFOCLR in the SERCOM_SPI_CTRLB register */
+#define   SERCOM_SPI_CTRLB_FIFOCLR_NONE_Val   _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLB) No action  */
+#define   SERCOM_SPI_CTRLB_FIFOCLR_TXFIFO_Val _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLB) Clear TX FIFO  */
+#define   SERCOM_SPI_CTRLB_FIFOCLR_RXFIFO_Val _UINT32_(0x2)                                        /* (SERCOM_SPI_CTRLB) Clear RX FIFO  */
+#define   SERCOM_SPI_CTRLB_FIFOCLR_BOTH_Val   _UINT32_(0x3)                                        /* (SERCOM_SPI_CTRLB) Clear both TX and RF FIFOs  */
+#define SERCOM_SPI_CTRLB_FIFOCLR_NONE         (SERCOM_SPI_CTRLB_FIFOCLR_NONE_Val << SERCOM_SPI_CTRLB_FIFOCLR_Pos) /* (SERCOM_SPI_CTRLB) No action Position */
+#define SERCOM_SPI_CTRLB_FIFOCLR_TXFIFO       (SERCOM_SPI_CTRLB_FIFOCLR_TXFIFO_Val << SERCOM_SPI_CTRLB_FIFOCLR_Pos) /* (SERCOM_SPI_CTRLB) Clear TX FIFO Position */
+#define SERCOM_SPI_CTRLB_FIFOCLR_RXFIFO       (SERCOM_SPI_CTRLB_FIFOCLR_RXFIFO_Val << SERCOM_SPI_CTRLB_FIFOCLR_Pos) /* (SERCOM_SPI_CTRLB) Clear RX FIFO Position */
+#define SERCOM_SPI_CTRLB_FIFOCLR_BOTH         (SERCOM_SPI_CTRLB_FIFOCLR_BOTH_Val << SERCOM_SPI_CTRLB_FIFOCLR_Pos) /* (SERCOM_SPI_CTRLB) Clear both TX and RF FIFOs Position */
+#define SERCOM_SPI_CTRLB_Msk                  _UINT32_(0x00C2E247)                                 /* (SERCOM_SPI_CTRLB) Register Mask  */
+
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART Control B -------- */
+#define SERCOM_USART_CTRLB_RESETVALUE         _UINT32_(0x00)                                       /*  (SERCOM_USART_CTRLB) USART Control B  Reset Value */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos         _UINT32_(0)                                          /* (SERCOM_USART_CTRLB) Character Size Position */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk         (_UINT32_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos)     /* (SERCOM_USART_CTRLB) Character Size Mask */
+#define SERCOM_USART_CTRLB_CHSIZE(value)      (SERCOM_USART_CTRLB_CHSIZE_Msk & (_UINT32_(value) << SERCOM_USART_CTRLB_CHSIZE_Pos)) /* Assignment of value for CHSIZE in the SERCOM_USART_CTRLB register */
+#define   SERCOM_USART_CTRLB_CHSIZE_8BITS_Val _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLB) 8-bits character  */
+#define   SERCOM_USART_CTRLB_CHSIZE_9BITS_Val _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLB) 9-bits character  */
+#define   SERCOM_USART_CTRLB_CHSIZE_5BITS_Val _UINT32_(0x5)                                        /* (SERCOM_USART_CTRLB) 5-bits character  */
+#define   SERCOM_USART_CTRLB_CHSIZE_6BITS_Val _UINT32_(0x6)                                        /* (SERCOM_USART_CTRLB) 6-bits character  */
+#define   SERCOM_USART_CTRLB_CHSIZE_7BITS_Val _UINT32_(0x7)                                        /* (SERCOM_USART_CTRLB) 7-bits character  */
+#define SERCOM_USART_CTRLB_CHSIZE_8BITS       (SERCOM_USART_CTRLB_CHSIZE_8BITS_Val << SERCOM_USART_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_CTRLB) 8-bits character Position */
+#define SERCOM_USART_CTRLB_CHSIZE_9BITS       (SERCOM_USART_CTRLB_CHSIZE_9BITS_Val << SERCOM_USART_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_CTRLB) 9-bits character Position */
+#define SERCOM_USART_CTRLB_CHSIZE_5BITS       (SERCOM_USART_CTRLB_CHSIZE_5BITS_Val << SERCOM_USART_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_CTRLB) 5-bits character Position */
+#define SERCOM_USART_CTRLB_CHSIZE_6BITS       (SERCOM_USART_CTRLB_CHSIZE_6BITS_Val << SERCOM_USART_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_CTRLB) 6-bits character Position */
+#define SERCOM_USART_CTRLB_CHSIZE_7BITS       (SERCOM_USART_CTRLB_CHSIZE_7BITS_Val << SERCOM_USART_CTRLB_CHSIZE_Pos) /* (SERCOM_USART_CTRLB) 7-bits character Position */
+#define SERCOM_USART_CTRLB_SBMODE_Pos         _UINT32_(6)                                          /* (SERCOM_USART_CTRLB) Stop Bit Mode Position */
+#define SERCOM_USART_CTRLB_SBMODE_Msk         (_UINT32_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos)     /* (SERCOM_USART_CTRLB) Stop Bit Mode Mask */
+#define SERCOM_USART_CTRLB_SBMODE(value)      (SERCOM_USART_CTRLB_SBMODE_Msk & (_UINT32_(value) << SERCOM_USART_CTRLB_SBMODE_Pos)) /* Assignment of value for SBMODE in the SERCOM_USART_CTRLB register */
+#define   SERCOM_USART_CTRLB_SBMODE_ONE_Val   _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLB) One stop bit  */
+#define   SERCOM_USART_CTRLB_SBMODE_TWO_Val   _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLB) Two stop bits  */
+#define SERCOM_USART_CTRLB_SBMODE_ONE         (SERCOM_USART_CTRLB_SBMODE_ONE_Val << SERCOM_USART_CTRLB_SBMODE_Pos) /* (SERCOM_USART_CTRLB) One stop bit Position */
+#define SERCOM_USART_CTRLB_SBMODE_TWO         (SERCOM_USART_CTRLB_SBMODE_TWO_Val << SERCOM_USART_CTRLB_SBMODE_Pos) /* (SERCOM_USART_CTRLB) Two stop bits Position */
+#define SERCOM_USART_CTRLB_COLDEN_Pos         _UINT32_(8)                                          /* (SERCOM_USART_CTRLB) Collision Detection Enable Position */
+#define SERCOM_USART_CTRLB_COLDEN_Msk         (_UINT32_(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos)     /* (SERCOM_USART_CTRLB) Collision Detection Enable Mask */
+#define SERCOM_USART_CTRLB_COLDEN(value)      (SERCOM_USART_CTRLB_COLDEN_Msk & (_UINT32_(value) << SERCOM_USART_CTRLB_COLDEN_Pos)) /* Assignment of value for COLDEN in the SERCOM_USART_CTRLB register */
+#define SERCOM_USART_CTRLB_SFDE_Pos           _UINT32_(9)                                          /* (SERCOM_USART_CTRLB) Start of Frame Detection Enable Position */
+#define SERCOM_USART_CTRLB_SFDE_Msk           (_UINT32_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos)       /* (SERCOM_USART_CTRLB) Start of Frame Detection Enable Mask */
+#define SERCOM_USART_CTRLB_SFDE(value)        (SERCOM_USART_CTRLB_SFDE_Msk & (_UINT32_(value) << SERCOM_USART_CTRLB_SFDE_Pos)) /* Assignment of value for SFDE in the SERCOM_USART_CTRLB register */
+#define SERCOM_USART_CTRLB_ENC_Pos            _UINT32_(10)                                         /* (SERCOM_USART_CTRLB) Encoding Format Position */
+#define SERCOM_USART_CTRLB_ENC_Msk            (_UINT32_(0x1) << SERCOM_USART_CTRLB_ENC_Pos)        /* (SERCOM_USART_CTRLB) Encoding Format Mask */
+#define SERCOM_USART_CTRLB_ENC(value)         (SERCOM_USART_CTRLB_ENC_Msk & (_UINT32_(value) << SERCOM_USART_CTRLB_ENC_Pos)) /* Assignment of value for ENC in the SERCOM_USART_CTRLB register */
+#define   SERCOM_USART_CTRLB_ENC_DISABLE_Val  _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLB) Data is not encoded  */
+#define   SERCOM_USART_CTRLB_ENC_IRDA_Val     _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLB) Data is IrDA encoded  */
+#define SERCOM_USART_CTRLB_ENC_DISABLE        (SERCOM_USART_CTRLB_ENC_DISABLE_Val << SERCOM_USART_CTRLB_ENC_Pos) /* (SERCOM_USART_CTRLB) Data is not encoded Position */
+#define SERCOM_USART_CTRLB_ENC_IRDA           (SERCOM_USART_CTRLB_ENC_IRDA_Val << SERCOM_USART_CTRLB_ENC_Pos) /* (SERCOM_USART_CTRLB) Data is IrDA encoded Position */
+#define SERCOM_USART_CTRLB_PMODE_Pos          _UINT32_(13)                                         /* (SERCOM_USART_CTRLB) Parity Mode Position */
+#define SERCOM_USART_CTRLB_PMODE_Msk          (_UINT32_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos)      /* (SERCOM_USART_CTRLB) Parity Mode Mask */
+#define SERCOM_USART_CTRLB_PMODE(value)       (SERCOM_USART_CTRLB_PMODE_Msk & (_UINT32_(value) << SERCOM_USART_CTRLB_PMODE_Pos)) /* Assignment of value for PMODE in the SERCOM_USART_CTRLB register */
+#define   SERCOM_USART_CTRLB_PMODE_EVEN_Val   _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLB) Even parity  */
+#define   SERCOM_USART_CTRLB_PMODE_ODD_Val    _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLB) Odd parity  */
+#define SERCOM_USART_CTRLB_PMODE_EVEN         (SERCOM_USART_CTRLB_PMODE_EVEN_Val << SERCOM_USART_CTRLB_PMODE_Pos) /* (SERCOM_USART_CTRLB) Even parity Position */
+#define SERCOM_USART_CTRLB_PMODE_ODD          (SERCOM_USART_CTRLB_PMODE_ODD_Val << SERCOM_USART_CTRLB_PMODE_Pos) /* (SERCOM_USART_CTRLB) Odd parity Position */
+#define SERCOM_USART_CTRLB_TXEN_Pos           _UINT32_(16)                                         /* (SERCOM_USART_CTRLB) Transmitter Enable Position */
+#define SERCOM_USART_CTRLB_TXEN_Msk           (_UINT32_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos)       /* (SERCOM_USART_CTRLB) Transmitter Enable Mask */
+#define SERCOM_USART_CTRLB_TXEN(value)        (SERCOM_USART_CTRLB_TXEN_Msk & (_UINT32_(value) << SERCOM_USART_CTRLB_TXEN_Pos)) /* Assignment of value for TXEN in the SERCOM_USART_CTRLB register */
+#define SERCOM_USART_CTRLB_RXEN_Pos           _UINT32_(17)                                         /* (SERCOM_USART_CTRLB) Receiver Enable Position */
+#define SERCOM_USART_CTRLB_RXEN_Msk           (_UINT32_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos)       /* (SERCOM_USART_CTRLB) Receiver Enable Mask */
+#define SERCOM_USART_CTRLB_RXEN(value)        (SERCOM_USART_CTRLB_RXEN_Msk & (_UINT32_(value) << SERCOM_USART_CTRLB_RXEN_Pos)) /* Assignment of value for RXEN in the SERCOM_USART_CTRLB register */
+#define SERCOM_USART_CTRLB_FIFOCLR_Pos        _UINT32_(22)                                         /* (SERCOM_USART_CTRLB) FIFO Clear Position */
+#define SERCOM_USART_CTRLB_FIFOCLR_Msk        (_UINT32_(0x3) << SERCOM_USART_CTRLB_FIFOCLR_Pos)    /* (SERCOM_USART_CTRLB) FIFO Clear Mask */
+#define SERCOM_USART_CTRLB_FIFOCLR(value)     (SERCOM_USART_CTRLB_FIFOCLR_Msk & (_UINT32_(value) << SERCOM_USART_CTRLB_FIFOCLR_Pos)) /* Assignment of value for FIFOCLR in the SERCOM_USART_CTRLB register */
+#define   SERCOM_USART_CTRLB_FIFOCLR_NONE_Val _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLB) No action  */
+#define   SERCOM_USART_CTRLB_FIFOCLR_TXFIFO_Val _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLB) Clear TX FIFO  */
+#define   SERCOM_USART_CTRLB_FIFOCLR_RXFIFO_Val _UINT32_(0x2)                                        /* (SERCOM_USART_CTRLB) Clear RX FIFO  */
+#define   SERCOM_USART_CTRLB_FIFOCLR_BOTH_Val _UINT32_(0x3)                                        /* (SERCOM_USART_CTRLB) Clear both TX and RF FIFOs  */
+#define SERCOM_USART_CTRLB_FIFOCLR_NONE       (SERCOM_USART_CTRLB_FIFOCLR_NONE_Val << SERCOM_USART_CTRLB_FIFOCLR_Pos) /* (SERCOM_USART_CTRLB) No action Position */
+#define SERCOM_USART_CTRLB_FIFOCLR_TXFIFO     (SERCOM_USART_CTRLB_FIFOCLR_TXFIFO_Val << SERCOM_USART_CTRLB_FIFOCLR_Pos) /* (SERCOM_USART_CTRLB) Clear TX FIFO Position */
+#define SERCOM_USART_CTRLB_FIFOCLR_RXFIFO     (SERCOM_USART_CTRLB_FIFOCLR_RXFIFO_Val << SERCOM_USART_CTRLB_FIFOCLR_Pos) /* (SERCOM_USART_CTRLB) Clear RX FIFO Position */
+#define SERCOM_USART_CTRLB_FIFOCLR_BOTH       (SERCOM_USART_CTRLB_FIFOCLR_BOTH_Val << SERCOM_USART_CTRLB_FIFOCLR_Pos) /* (SERCOM_USART_CTRLB) Clear both TX and RF FIFOs Position */
+#define SERCOM_USART_CTRLB_LINCMD_Pos         _UINT32_(24)                                         /* (SERCOM_USART_CTRLB) LIN Command Position */
+#define SERCOM_USART_CTRLB_LINCMD_Msk         (_UINT32_(0x3) << SERCOM_USART_CTRLB_LINCMD_Pos)     /* (SERCOM_USART_CTRLB) LIN Command Mask */
+#define SERCOM_USART_CTRLB_LINCMD(value)      (SERCOM_USART_CTRLB_LINCMD_Msk & (_UINT32_(value) << SERCOM_USART_CTRLB_LINCMD_Pos)) /* Assignment of value for LINCMD in the SERCOM_USART_CTRLB register */
+#define   SERCOM_USART_CTRLB_LINCMD_NONE_Val  _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLB) Normal USART transmission  */
+#define   SERCOM_USART_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD_Val _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLB) Break field is transmitted when DATA is written  */
+#define   SERCOM_USART_CTRLB_LINCMD_AUTO_TRANSMIT_CMD_Val _UINT32_(0x2)                                        /* (SERCOM_USART_CTRLB) Break, synch and identifier are automaticcaly transmitted when DATA is written with the identifier  */
+#define SERCOM_USART_CTRLB_LINCMD_NONE        (SERCOM_USART_CTRLB_LINCMD_NONE_Val << SERCOM_USART_CTRLB_LINCMD_Pos) /* (SERCOM_USART_CTRLB) Normal USART transmission Position */
+#define SERCOM_USART_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD (SERCOM_USART_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD_Val << SERCOM_USART_CTRLB_LINCMD_Pos) /* (SERCOM_USART_CTRLB) Break field is transmitted when DATA is written Position */
+#define SERCOM_USART_CTRLB_LINCMD_AUTO_TRANSMIT_CMD (SERCOM_USART_CTRLB_LINCMD_AUTO_TRANSMIT_CMD_Val << SERCOM_USART_CTRLB_LINCMD_Pos) /* (SERCOM_USART_CTRLB) Break, synch and identifier are automaticcaly transmitted when DATA is written with the identifier Position */
+#define SERCOM_USART_CTRLB_Msk                _UINT32_(0x03C32747)                                 /* (SERCOM_USART_CTRLB) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CM Control C -------- */
+#define SERCOM_I2CM_CTRLC_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CM_CTRLC) I2CM Control C  Reset Value */
+
+#define SERCOM_I2CM_CTRLC_DATA32B_Pos         _UINT32_(24)                                         /* (SERCOM_I2CM_CTRLC) Data 32 Bit Position */
+#define SERCOM_I2CM_CTRLC_DATA32B_Msk         (_UINT32_(0x1) << SERCOM_I2CM_CTRLC_DATA32B_Pos)     /* (SERCOM_I2CM_CTRLC) Data 32 Bit Mask */
+#define SERCOM_I2CM_CTRLC_DATA32B(value)      (SERCOM_I2CM_CTRLC_DATA32B_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLC_DATA32B_Pos)) /* Assignment of value for DATA32B in the SERCOM_I2CM_CTRLC register */
+#define SERCOM_I2CM_CTRLC_FIFOEN_Pos          _UINT32_(27)                                         /* (SERCOM_I2CM_CTRLC) FIFO Enable Position */
+#define SERCOM_I2CM_CTRLC_FIFOEN_Msk          (_UINT32_(0x1) << SERCOM_I2CM_CTRLC_FIFOEN_Pos)      /* (SERCOM_I2CM_CTRLC) FIFO Enable Mask */
+#define SERCOM_I2CM_CTRLC_FIFOEN(value)       (SERCOM_I2CM_CTRLC_FIFOEN_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLC_FIFOEN_Pos)) /* Assignment of value for FIFOEN in the SERCOM_I2CM_CTRLC register */
+#define SERCOM_I2CM_CTRLC_RXTRHOLD_Pos        _UINT32_(28)                                         /* (SERCOM_I2CM_CTRLC) Receive FIFO Threshold Position */
+#define SERCOM_I2CM_CTRLC_RXTRHOLD_Msk        (_UINT32_(0x3) << SERCOM_I2CM_CTRLC_RXTRHOLD_Pos)    /* (SERCOM_I2CM_CTRLC) Receive FIFO Threshold Mask */
+#define SERCOM_I2CM_CTRLC_RXTRHOLD(value)     (SERCOM_I2CM_CTRLC_RXTRHOLD_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLC_RXTRHOLD_Pos)) /* Assignment of value for RXTRHOLD in the SERCOM_I2CM_CTRLC register */
+#define   SERCOM_I2CM_CTRLC_RXTRHOLD_DEFAULT_Val _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated when DATA is present in the FIFO  */
+#define   SERCOM_I2CM_CTRLC_RXTRHOLD_HALF_Val _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated when FIFO is half-full  */
+#define   SERCOM_I2CM_CTRLC_RXTRHOLD_FULL_Val _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated when FIFO is full  */
+#define SERCOM_I2CM_CTRLC_RXTRHOLD_DEFAULT    (SERCOM_I2CM_CTRLC_RXTRHOLD_DEFAULT_Val << SERCOM_I2CM_CTRLC_RXTRHOLD_Pos) /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated when DATA is present in the FIFO Position */
+#define SERCOM_I2CM_CTRLC_RXTRHOLD_HALF       (SERCOM_I2CM_CTRLC_RXTRHOLD_HALF_Val << SERCOM_I2CM_CTRLC_RXTRHOLD_Pos) /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated when FIFO is half-full Position */
+#define SERCOM_I2CM_CTRLC_RXTRHOLD_FULL       (SERCOM_I2CM_CTRLC_RXTRHOLD_FULL_Val << SERCOM_I2CM_CTRLC_RXTRHOLD_Pos) /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated when FIFO is full Position */
+#define SERCOM_I2CM_CTRLC_TXTRHOLD_Pos        _UINT32_(30)                                         /* (SERCOM_I2CM_CTRLC) Transmit FIFO Threshold Position */
+#define SERCOM_I2CM_CTRLC_TXTRHOLD_Msk        (_UINT32_(0x3) << SERCOM_I2CM_CTRLC_TXTRHOLD_Pos)    /* (SERCOM_I2CM_CTRLC) Transmit FIFO Threshold Mask */
+#define SERCOM_I2CM_CTRLC_TXTRHOLD(value)     (SERCOM_I2CM_CTRLC_TXTRHOLD_Msk & (_UINT32_(value) << SERCOM_I2CM_CTRLC_TXTRHOLD_Pos)) /* Assignment of value for TXTRHOLD in the SERCOM_I2CM_CTRLC register */
+#define   SERCOM_I2CM_CTRLC_TXTRHOLD_DEFAULT_Val _UINT32_(0x0)                                        /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full  */
+#define   SERCOM_I2CM_CTRLC_TXTRHOLD_HALF_Val _UINT32_(0x1)                                        /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated when half FIFO space is free  */
+#define   SERCOM_I2CM_CTRLC_TXTRHOLD_EMPTY_Val _UINT32_(0x2)                                        /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full  */
+#define SERCOM_I2CM_CTRLC_TXTRHOLD_DEFAULT    (SERCOM_I2CM_CTRLC_TXTRHOLD_DEFAULT_Val << SERCOM_I2CM_CTRLC_TXTRHOLD_Pos) /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full Position */
+#define SERCOM_I2CM_CTRLC_TXTRHOLD_HALF       (SERCOM_I2CM_CTRLC_TXTRHOLD_HALF_Val << SERCOM_I2CM_CTRLC_TXTRHOLD_Pos) /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated when half FIFO space is free Position */
+#define SERCOM_I2CM_CTRLC_TXTRHOLD_EMPTY      (SERCOM_I2CM_CTRLC_TXTRHOLD_EMPTY_Val << SERCOM_I2CM_CTRLC_TXTRHOLD_Pos) /* (SERCOM_I2CM_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full Position */
+#define SERCOM_I2CM_CTRLC_Msk                 _UINT32_(0xF9000000)                                 /* (SERCOM_I2CM_CTRLC) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CS Control C -------- */
+#define SERCOM_I2CS_CTRLC_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_I2CS_CTRLC) I2CS Control C  Reset Value */
+
+#define SERCOM_I2CS_CTRLC_SDASETUP_Pos        _UINT32_(0)                                          /* (SERCOM_I2CS_CTRLC) SDA Setup Time Position */
+#define SERCOM_I2CS_CTRLC_SDASETUP_Msk        (_UINT32_(0xF) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)    /* (SERCOM_I2CS_CTRLC) SDA Setup Time Mask */
+#define SERCOM_I2CS_CTRLC_SDASETUP(value)     (SERCOM_I2CS_CTRLC_SDASETUP_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)) /* Assignment of value for SDASETUP in the SERCOM_I2CS_CTRLC register */
+#define SERCOM_I2CS_CTRLC_DATA32B_Pos         _UINT32_(24)                                         /* (SERCOM_I2CS_CTRLC) Data 32 Bit Position */
+#define SERCOM_I2CS_CTRLC_DATA32B_Msk         (_UINT32_(0x1) << SERCOM_I2CS_CTRLC_DATA32B_Pos)     /* (SERCOM_I2CS_CTRLC) Data 32 Bit Mask */
+#define SERCOM_I2CS_CTRLC_DATA32B(value)      (SERCOM_I2CS_CTRLC_DATA32B_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLC_DATA32B_Pos)) /* Assignment of value for DATA32B in the SERCOM_I2CS_CTRLC register */
+#define SERCOM_I2CS_CTRLC_FIFOEN_Pos          _UINT32_(27)                                         /* (SERCOM_I2CS_CTRLC) FIFO Enable Position */
+#define SERCOM_I2CS_CTRLC_FIFOEN_Msk          (_UINT32_(0x1) << SERCOM_I2CS_CTRLC_FIFOEN_Pos)      /* (SERCOM_I2CS_CTRLC) FIFO Enable Mask */
+#define SERCOM_I2CS_CTRLC_FIFOEN(value)       (SERCOM_I2CS_CTRLC_FIFOEN_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLC_FIFOEN_Pos)) /* Assignment of value for FIFOEN in the SERCOM_I2CS_CTRLC register */
+#define SERCOM_I2CS_CTRLC_RXTRHOLD_Pos        _UINT32_(28)                                         /* (SERCOM_I2CS_CTRLC) Receive FIFO Threshold Position */
+#define SERCOM_I2CS_CTRLC_RXTRHOLD_Msk        (_UINT32_(0x3) << SERCOM_I2CS_CTRLC_RXTRHOLD_Pos)    /* (SERCOM_I2CS_CTRLC) Receive FIFO Threshold Mask */
+#define SERCOM_I2CS_CTRLC_RXTRHOLD(value)     (SERCOM_I2CS_CTRLC_RXTRHOLD_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLC_RXTRHOLD_Pos)) /* Assignment of value for RXTRHOLD in the SERCOM_I2CS_CTRLC register */
+#define   SERCOM_I2CS_CTRLC_RXTRHOLD_DEFAULT_Val _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated when DATA is present in the FIFO  */
+#define   SERCOM_I2CS_CTRLC_RXTRHOLD_HALF_Val _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated when FIFO is half-full  */
+#define   SERCOM_I2CS_CTRLC_RXTRHOLD_FULL_Val _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated when FIFO is full  */
+#define SERCOM_I2CS_CTRLC_RXTRHOLD_DEFAULT    (SERCOM_I2CS_CTRLC_RXTRHOLD_DEFAULT_Val << SERCOM_I2CS_CTRLC_RXTRHOLD_Pos) /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated when DATA is present in the FIFO Position */
+#define SERCOM_I2CS_CTRLC_RXTRHOLD_HALF       (SERCOM_I2CS_CTRLC_RXTRHOLD_HALF_Val << SERCOM_I2CS_CTRLC_RXTRHOLD_Pos) /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated when FIFO is half-full Position */
+#define SERCOM_I2CS_CTRLC_RXTRHOLD_FULL       (SERCOM_I2CS_CTRLC_RXTRHOLD_FULL_Val << SERCOM_I2CS_CTRLC_RXTRHOLD_Pos) /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated when FIFO is full Position */
+#define SERCOM_I2CS_CTRLC_TXTRHOLD_Pos        _UINT32_(30)                                         /* (SERCOM_I2CS_CTRLC) Transmit FIFO Threshold Position */
+#define SERCOM_I2CS_CTRLC_TXTRHOLD_Msk        (_UINT32_(0x3) << SERCOM_I2CS_CTRLC_TXTRHOLD_Pos)    /* (SERCOM_I2CS_CTRLC) Transmit FIFO Threshold Mask */
+#define SERCOM_I2CS_CTRLC_TXTRHOLD(value)     (SERCOM_I2CS_CTRLC_TXTRHOLD_Msk & (_UINT32_(value) << SERCOM_I2CS_CTRLC_TXTRHOLD_Pos)) /* Assignment of value for TXTRHOLD in the SERCOM_I2CS_CTRLC register */
+#define   SERCOM_I2CS_CTRLC_TXTRHOLD_DEFAULT_Val _UINT32_(0x0)                                        /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full  */
+#define   SERCOM_I2CS_CTRLC_TXTRHOLD_HALF_Val _UINT32_(0x1)                                        /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated when half FIFO space is free  */
+#define   SERCOM_I2CS_CTRLC_TXTRHOLD_EMPTY_Val _UINT32_(0x2)                                        /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full  */
+#define SERCOM_I2CS_CTRLC_TXTRHOLD_DEFAULT    (SERCOM_I2CS_CTRLC_TXTRHOLD_DEFAULT_Val << SERCOM_I2CS_CTRLC_TXTRHOLD_Pos) /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full Position */
+#define SERCOM_I2CS_CTRLC_TXTRHOLD_HALF       (SERCOM_I2CS_CTRLC_TXTRHOLD_HALF_Val << SERCOM_I2CS_CTRLC_TXTRHOLD_Pos) /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated when half FIFO space is free Position */
+#define SERCOM_I2CS_CTRLC_TXTRHOLD_EMPTY      (SERCOM_I2CS_CTRLC_TXTRHOLD_EMPTY_Val << SERCOM_I2CS_CTRLC_TXTRHOLD_Pos) /* (SERCOM_I2CS_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full Position */
+#define SERCOM_I2CS_CTRLC_Msk                 _UINT32_(0xF900000F)                                 /* (SERCOM_I2CS_CTRLC) Register Mask  */
+
+
+/* -------- SERCOM_SPI_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPI Control C -------- */
+#define SERCOM_SPI_CTRLC_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_SPI_CTRLC) SPI Control C  Reset Value */
+
+#define SERCOM_SPI_CTRLC_ICSPACE_Pos          _UINT32_(0)                                          /* (SERCOM_SPI_CTRLC) Inter-Character Spacing Position */
+#define SERCOM_SPI_CTRLC_ICSPACE_Msk          (_UINT32_(0x3F) << SERCOM_SPI_CTRLC_ICSPACE_Pos)     /* (SERCOM_SPI_CTRLC) Inter-Character Spacing Mask */
+#define SERCOM_SPI_CTRLC_ICSPACE(value)       (SERCOM_SPI_CTRLC_ICSPACE_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_ICSPACE_Pos)) /* Assignment of value for ICSPACE in the SERCOM_SPI_CTRLC register */
+#define SERCOM_SPI_CTRLC_FSES_Pos             _UINT32_(8)                                          /* (SERCOM_SPI_CTRLC) Frame Synch Edge Select Position */
+#define SERCOM_SPI_CTRLC_FSES_Msk             (_UINT32_(0x1) << SERCOM_SPI_CTRLC_FSES_Pos)         /* (SERCOM_SPI_CTRLC) Frame Synch Edge Select Mask */
+#define SERCOM_SPI_CTRLC_FSES(value)          (SERCOM_SPI_CTRLC_FSES_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_FSES_Pos)) /* Assignment of value for FSES in the SERCOM_SPI_CTRLC register */
+#define SERCOM_SPI_CTRLC_FSLEN_Pos            _UINT32_(9)                                          /* (SERCOM_SPI_CTRLC) Frame Synch Length Position */
+#define SERCOM_SPI_CTRLC_FSLEN_Msk            (_UINT32_(0x1) << SERCOM_SPI_CTRLC_FSLEN_Pos)        /* (SERCOM_SPI_CTRLC) Frame Synch Length Mask */
+#define SERCOM_SPI_CTRLC_FSLEN(value)         (SERCOM_SPI_CTRLC_FSLEN_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_FSLEN_Pos)) /* Assignment of value for FSLEN in the SERCOM_SPI_CTRLC register */
+#define   SERCOM_SPI_CTRLC_FSLEN_STROBE_Val   _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLC) One SCK pulse  */
+#define   SERCOM_SPI_CTRLC_FSLEN_LEVEL_Val    _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLC) One frame duration  */
+#define SERCOM_SPI_CTRLC_FSLEN_STROBE         (SERCOM_SPI_CTRLC_FSLEN_STROBE_Val << SERCOM_SPI_CTRLC_FSLEN_Pos) /* (SERCOM_SPI_CTRLC) One SCK pulse Position */
+#define SERCOM_SPI_CTRLC_FSLEN_LEVEL          (SERCOM_SPI_CTRLC_FSLEN_LEVEL_Val << SERCOM_SPI_CTRLC_FSLEN_Pos) /* (SERCOM_SPI_CTRLC) One frame duration Position */
+#define SERCOM_SPI_CTRLC_FSPOL_Pos            _UINT32_(10)                                         /* (SERCOM_SPI_CTRLC) Frame Synch Polarity Position */
+#define SERCOM_SPI_CTRLC_FSPOL_Msk            (_UINT32_(0x1) << SERCOM_SPI_CTRLC_FSPOL_Pos)        /* (SERCOM_SPI_CTRLC) Frame Synch Polarity Mask */
+#define SERCOM_SPI_CTRLC_FSPOL(value)         (SERCOM_SPI_CTRLC_FSPOL_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_FSPOL_Pos)) /* Assignment of value for FSPOL in the SERCOM_SPI_CTRLC register */
+#define   SERCOM_SPI_CTRLC_FSPOL_HIGH_Val     _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLC) VCC-level valid polarity  */
+#define   SERCOM_SPI_CTRLC_FSPOL_LOW_Val      _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLC) GND-level valid polarity  */
+#define SERCOM_SPI_CTRLC_FSPOL_HIGH           (SERCOM_SPI_CTRLC_FSPOL_HIGH_Val << SERCOM_SPI_CTRLC_FSPOL_Pos) /* (SERCOM_SPI_CTRLC) VCC-level valid polarity Position */
+#define SERCOM_SPI_CTRLC_FSPOL_LOW            (SERCOM_SPI_CTRLC_FSPOL_LOW_Val << SERCOM_SPI_CTRLC_FSPOL_Pos) /* (SERCOM_SPI_CTRLC) GND-level valid polarity Position */
+#define SERCOM_SPI_CTRLC_IGNTUR_Pos           _UINT32_(11)                                         /* (SERCOM_SPI_CTRLC) Ignore Transmit Underrun Position */
+#define SERCOM_SPI_CTRLC_IGNTUR_Msk           (_UINT32_(0x1) << SERCOM_SPI_CTRLC_IGNTUR_Pos)       /* (SERCOM_SPI_CTRLC) Ignore Transmit Underrun Mask */
+#define SERCOM_SPI_CTRLC_IGNTUR(value)        (SERCOM_SPI_CTRLC_IGNTUR_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_IGNTUR_Pos)) /* Assignment of value for IGNTUR in the SERCOM_SPI_CTRLC register */
+#define SERCOM_SPI_CTRLC_FRMEN_Pos            _UINT32_(16)                                         /* (SERCOM_SPI_CTRLC) Frame mode enable Position */
+#define SERCOM_SPI_CTRLC_FRMEN_Msk            (_UINT32_(0x1) << SERCOM_SPI_CTRLC_FRMEN_Pos)        /* (SERCOM_SPI_CTRLC) Frame mode enable Mask */
+#define SERCOM_SPI_CTRLC_FRMEN(value)         (SERCOM_SPI_CTRLC_FRMEN_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_FRMEN_Pos)) /* Assignment of value for FRMEN in the SERCOM_SPI_CTRLC register */
+#define SERCOM_SPI_CTRLC_FMODE_Pos            _UINT32_(17)                                         /* (SERCOM_SPI_CTRLC) Frame mode Position */
+#define SERCOM_SPI_CTRLC_FMODE_Msk            (_UINT32_(0x1) << SERCOM_SPI_CTRLC_FMODE_Pos)        /* (SERCOM_SPI_CTRLC) Frame mode Mask */
+#define SERCOM_SPI_CTRLC_FMODE(value)         (SERCOM_SPI_CTRLC_FMODE_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_FMODE_Pos)) /* Assignment of value for FMODE in the SERCOM_SPI_CTRLC register */
+#define   SERCOM_SPI_CTRLC_FMODE_MASTER_Val   _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLC) Frame Master  */
+#define   SERCOM_SPI_CTRLC_FMODE_SLAVE_Val    _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLC) Frame Slave  */
+#define SERCOM_SPI_CTRLC_FMODE_MASTER         (SERCOM_SPI_CTRLC_FMODE_MASTER_Val << SERCOM_SPI_CTRLC_FMODE_Pos) /* (SERCOM_SPI_CTRLC) Frame Master Position */
+#define SERCOM_SPI_CTRLC_FMODE_SLAVE          (SERCOM_SPI_CTRLC_FMODE_SLAVE_Val << SERCOM_SPI_CTRLC_FMODE_Pos) /* (SERCOM_SPI_CTRLC) Frame Slave Position */
+#define SERCOM_SPI_CTRLC_DATA32B_Pos          _UINT32_(24)                                         /* (SERCOM_SPI_CTRLC) Data 32 Bit Position */
+#define SERCOM_SPI_CTRLC_DATA32B_Msk          (_UINT32_(0x1) << SERCOM_SPI_CTRLC_DATA32B_Pos)      /* (SERCOM_SPI_CTRLC) Data 32 Bit Mask */
+#define SERCOM_SPI_CTRLC_DATA32B(value)       (SERCOM_SPI_CTRLC_DATA32B_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_DATA32B_Pos)) /* Assignment of value for DATA32B in the SERCOM_SPI_CTRLC register */
+#define SERCOM_SPI_CTRLC_FIFOEN_Pos           _UINT32_(27)                                         /* (SERCOM_SPI_CTRLC) FIFO Enable Position */
+#define SERCOM_SPI_CTRLC_FIFOEN_Msk           (_UINT32_(0x1) << SERCOM_SPI_CTRLC_FIFOEN_Pos)       /* (SERCOM_SPI_CTRLC) FIFO Enable Mask */
+#define SERCOM_SPI_CTRLC_FIFOEN(value)        (SERCOM_SPI_CTRLC_FIFOEN_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_FIFOEN_Pos)) /* Assignment of value for FIFOEN in the SERCOM_SPI_CTRLC register */
+#define SERCOM_SPI_CTRLC_RXTRHOLD_Pos         _UINT32_(28)                                         /* (SERCOM_SPI_CTRLC) Receive FIFO Threshold Position */
+#define SERCOM_SPI_CTRLC_RXTRHOLD_Msk         (_UINT32_(0x3) << SERCOM_SPI_CTRLC_RXTRHOLD_Pos)     /* (SERCOM_SPI_CTRLC) Receive FIFO Threshold Mask */
+#define SERCOM_SPI_CTRLC_RXTRHOLD(value)      (SERCOM_SPI_CTRLC_RXTRHOLD_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_RXTRHOLD_Pos)) /* Assignment of value for RXTRHOLD in the SERCOM_SPI_CTRLC register */
+#define   SERCOM_SPI_CTRLC_RXTRHOLD_DEFAULT_Val _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated when DATA is present in the FIFO  */
+#define   SERCOM_SPI_CTRLC_RXTRHOLD_HALF_Val  _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated when FIFO is half-full  */
+#define   SERCOM_SPI_CTRLC_RXTRHOLD_FULL_Val  _UINT32_(0x2)                                        /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated when FIFO is full  */
+#define SERCOM_SPI_CTRLC_RXTRHOLD_DEFAULT     (SERCOM_SPI_CTRLC_RXTRHOLD_DEFAULT_Val << SERCOM_SPI_CTRLC_RXTRHOLD_Pos) /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated when DATA is present in the FIFO Position */
+#define SERCOM_SPI_CTRLC_RXTRHOLD_HALF        (SERCOM_SPI_CTRLC_RXTRHOLD_HALF_Val << SERCOM_SPI_CTRLC_RXTRHOLD_Pos) /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated when FIFO is half-full Position */
+#define SERCOM_SPI_CTRLC_RXTRHOLD_FULL        (SERCOM_SPI_CTRLC_RXTRHOLD_FULL_Val << SERCOM_SPI_CTRLC_RXTRHOLD_Pos) /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated when FIFO is full Position */
+#define SERCOM_SPI_CTRLC_TXTRHOLD_Pos         _UINT32_(30)                                         /* (SERCOM_SPI_CTRLC) Transmit FIFO Threshold Position */
+#define SERCOM_SPI_CTRLC_TXTRHOLD_Msk         (_UINT32_(0x3) << SERCOM_SPI_CTRLC_TXTRHOLD_Pos)     /* (SERCOM_SPI_CTRLC) Transmit FIFO Threshold Mask */
+#define SERCOM_SPI_CTRLC_TXTRHOLD(value)      (SERCOM_SPI_CTRLC_TXTRHOLD_Msk & (_UINT32_(value) << SERCOM_SPI_CTRLC_TXTRHOLD_Pos)) /* Assignment of value for TXTRHOLD in the SERCOM_SPI_CTRLC register */
+#define   SERCOM_SPI_CTRLC_TXTRHOLD_DEFAULT_Val _UINT32_(0x0)                                        /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full  */
+#define   SERCOM_SPI_CTRLC_TXTRHOLD_HALF_Val  _UINT32_(0x1)                                        /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated when half FIFO space is free  */
+#define   SERCOM_SPI_CTRLC_TXTRHOLD_EMPTY_Val _UINT32_(0x2)                                        /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is empty  */
+#define SERCOM_SPI_CTRLC_TXTRHOLD_DEFAULT     (SERCOM_SPI_CTRLC_TXTRHOLD_DEFAULT_Val << SERCOM_SPI_CTRLC_TXTRHOLD_Pos) /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full Position */
+#define SERCOM_SPI_CTRLC_TXTRHOLD_HALF        (SERCOM_SPI_CTRLC_TXTRHOLD_HALF_Val << SERCOM_SPI_CTRLC_TXTRHOLD_Pos) /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated when half FIFO space is free Position */
+#define SERCOM_SPI_CTRLC_TXTRHOLD_EMPTY       (SERCOM_SPI_CTRLC_TXTRHOLD_EMPTY_Val << SERCOM_SPI_CTRLC_TXTRHOLD_Pos) /* (SERCOM_SPI_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is empty Position */
+#define SERCOM_SPI_CTRLC_Msk                  _UINT32_(0xF9030F3F)                                 /* (SERCOM_SPI_CTRLC) Register Mask  */
+
+
+/* -------- SERCOM_USART_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART Control C -------- */
+#define SERCOM_USART_CTRLC_RESETVALUE         _UINT32_(0x00)                                       /*  (SERCOM_USART_CTRLC) USART Control C  Reset Value */
+
+#define SERCOM_USART_CTRLC_GTIME_Pos          _UINT32_(0)                                          /* (SERCOM_USART_CTRLC) Guard Time Position */
+#define SERCOM_USART_CTRLC_GTIME_Msk          (_UINT32_(0x7) << SERCOM_USART_CTRLC_GTIME_Pos)      /* (SERCOM_USART_CTRLC) Guard Time Mask */
+#define SERCOM_USART_CTRLC_GTIME(value)       (SERCOM_USART_CTRLC_GTIME_Msk & (_UINT32_(value) << SERCOM_USART_CTRLC_GTIME_Pos)) /* Assignment of value for GTIME in the SERCOM_USART_CTRLC register */
+#define SERCOM_USART_CTRLC_BRKLEN_Pos         _UINT32_(8)                                          /* (SERCOM_USART_CTRLC) LIN Master Break Length Position */
+#define SERCOM_USART_CTRLC_BRKLEN_Msk         (_UINT32_(0x3) << SERCOM_USART_CTRLC_BRKLEN_Pos)     /* (SERCOM_USART_CTRLC) LIN Master Break Length Mask */
+#define SERCOM_USART_CTRLC_BRKLEN(value)      (SERCOM_USART_CTRLC_BRKLEN_Msk & (_UINT32_(value) << SERCOM_USART_CTRLC_BRKLEN_Pos)) /* Assignment of value for BRKLEN in the SERCOM_USART_CTRLC register */
+#define   SERCOM_USART_CTRLC_BRKLEN_13BITS_Val _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLC) Break field transmission is 13 bit times  */
+#define   SERCOM_USART_CTRLC_BRKLEN_17BITS_Val _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLC) Break field transmission is 17 bit times  */
+#define   SERCOM_USART_CTRLC_BRKLEN_21BITS_Val _UINT32_(0x2)                                        /* (SERCOM_USART_CTRLC) Break field transmission is 21 bit times  */
+#define   SERCOM_USART_CTRLC_BRKLEN_26BITS_Val _UINT32_(0x3)                                        /* (SERCOM_USART_CTRLC) Break field transmission is 26 bit times  */
+#define SERCOM_USART_CTRLC_BRKLEN_13BITS      (SERCOM_USART_CTRLC_BRKLEN_13BITS_Val << SERCOM_USART_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_CTRLC) Break field transmission is 13 bit times Position */
+#define SERCOM_USART_CTRLC_BRKLEN_17BITS      (SERCOM_USART_CTRLC_BRKLEN_17BITS_Val << SERCOM_USART_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_CTRLC) Break field transmission is 17 bit times Position */
+#define SERCOM_USART_CTRLC_BRKLEN_21BITS      (SERCOM_USART_CTRLC_BRKLEN_21BITS_Val << SERCOM_USART_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_CTRLC) Break field transmission is 21 bit times Position */
+#define SERCOM_USART_CTRLC_BRKLEN_26BITS      (SERCOM_USART_CTRLC_BRKLEN_26BITS_Val << SERCOM_USART_CTRLC_BRKLEN_Pos) /* (SERCOM_USART_CTRLC) Break field transmission is 26 bit times Position */
+#define SERCOM_USART_CTRLC_HDRDLY_Pos         _UINT32_(10)                                         /* (SERCOM_USART_CTRLC) LIN Master Header Delay Position */
+#define SERCOM_USART_CTRLC_HDRDLY_Msk         (_UINT32_(0x3) << SERCOM_USART_CTRLC_HDRDLY_Pos)     /* (SERCOM_USART_CTRLC) LIN Master Header Delay Mask */
+#define SERCOM_USART_CTRLC_HDRDLY(value)      (SERCOM_USART_CTRLC_HDRDLY_Msk & (_UINT32_(value) << SERCOM_USART_CTRLC_HDRDLY_Pos)) /* Assignment of value for HDRDLY in the SERCOM_USART_CTRLC register */
+#define   SERCOM_USART_CTRLC_HDRDLY_1BIT_Val  _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLC) Delay between break and sync transmission is 1-bit time  */
+#define   SERCOM_USART_CTRLC_HDRDLY_4BITS_Val _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLC) Delay between break and sync transmission is 4-bit time  */
+#define   SERCOM_USART_CTRLC_HDRDLY_8BITS_Val _UINT32_(0x2)                                        /* (SERCOM_USART_CTRLC) Delay between break and sync transmission is 8-bit time  */
+#define   SERCOM_USART_CTRLC_HDRDLY_14BITS_Val _UINT32_(0x3)                                        /* (SERCOM_USART_CTRLC) Delay between break and sync transmission is 14-bit time  */
+#define SERCOM_USART_CTRLC_HDRDLY_1BIT        (SERCOM_USART_CTRLC_HDRDLY_1BIT_Val << SERCOM_USART_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_CTRLC) Delay between break and sync transmission is 1-bit time Position */
+#define SERCOM_USART_CTRLC_HDRDLY_4BITS       (SERCOM_USART_CTRLC_HDRDLY_4BITS_Val << SERCOM_USART_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_CTRLC) Delay between break and sync transmission is 4-bit time Position */
+#define SERCOM_USART_CTRLC_HDRDLY_8BITS       (SERCOM_USART_CTRLC_HDRDLY_8BITS_Val << SERCOM_USART_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_CTRLC) Delay between break and sync transmission is 8-bit time Position */
+#define SERCOM_USART_CTRLC_HDRDLY_14BITS      (SERCOM_USART_CTRLC_HDRDLY_14BITS_Val << SERCOM_USART_CTRLC_HDRDLY_Pos) /* (SERCOM_USART_CTRLC) Delay between break and sync transmission is 14-bit time Position */
+#define SERCOM_USART_CTRLC_INACK_Pos          _UINT32_(16)                                         /* (SERCOM_USART_CTRLC) Inhibit Not Acknowledge Position */
+#define SERCOM_USART_CTRLC_INACK_Msk          (_UINT32_(0x1) << SERCOM_USART_CTRLC_INACK_Pos)      /* (SERCOM_USART_CTRLC) Inhibit Not Acknowledge Mask */
+#define SERCOM_USART_CTRLC_INACK(value)       (SERCOM_USART_CTRLC_INACK_Msk & (_UINT32_(value) << SERCOM_USART_CTRLC_INACK_Pos)) /* Assignment of value for INACK in the SERCOM_USART_CTRLC register */
+#define SERCOM_USART_CTRLC_DSNACK_Pos         _UINT32_(17)                                         /* (SERCOM_USART_CTRLC) Disable Successive NACK Position */
+#define SERCOM_USART_CTRLC_DSNACK_Msk         (_UINT32_(0x1) << SERCOM_USART_CTRLC_DSNACK_Pos)     /* (SERCOM_USART_CTRLC) Disable Successive NACK Mask */
+#define SERCOM_USART_CTRLC_DSNACK(value)      (SERCOM_USART_CTRLC_DSNACK_Msk & (_UINT32_(value) << SERCOM_USART_CTRLC_DSNACK_Pos)) /* Assignment of value for DSNACK in the SERCOM_USART_CTRLC register */
+#define SERCOM_USART_CTRLC_MAXITER_Pos        _UINT32_(20)                                         /* (SERCOM_USART_CTRLC) Maximum Iterations Position */
+#define SERCOM_USART_CTRLC_MAXITER_Msk        (_UINT32_(0x7) << SERCOM_USART_CTRLC_MAXITER_Pos)    /* (SERCOM_USART_CTRLC) Maximum Iterations Mask */
+#define SERCOM_USART_CTRLC_MAXITER(value)     (SERCOM_USART_CTRLC_MAXITER_Msk & (_UINT32_(value) << SERCOM_USART_CTRLC_MAXITER_Pos)) /* Assignment of value for MAXITER in the SERCOM_USART_CTRLC register */
+#define SERCOM_USART_CTRLC_DATA32B_Pos        _UINT32_(24)                                         /* (SERCOM_USART_CTRLC) Data 32 Bit Position */
+#define SERCOM_USART_CTRLC_DATA32B_Msk        (_UINT32_(0x3) << SERCOM_USART_CTRLC_DATA32B_Pos)    /* (SERCOM_USART_CTRLC) Data 32 Bit Mask */
+#define SERCOM_USART_CTRLC_DATA32B(value)     (SERCOM_USART_CTRLC_DATA32B_Msk & (_UINT32_(value) << SERCOM_USART_CTRLC_DATA32B_Pos)) /* Assignment of value for DATA32B in the SERCOM_USART_CTRLC register */
+#define SERCOM_USART_CTRLC_FIFOEN_Pos         _UINT32_(27)                                         /* (SERCOM_USART_CTRLC) FIFO Enable Position */
+#define SERCOM_USART_CTRLC_FIFOEN_Msk         (_UINT32_(0x1) << SERCOM_USART_CTRLC_FIFOEN_Pos)     /* (SERCOM_USART_CTRLC) FIFO Enable Mask */
+#define SERCOM_USART_CTRLC_FIFOEN(value)      (SERCOM_USART_CTRLC_FIFOEN_Msk & (_UINT32_(value) << SERCOM_USART_CTRLC_FIFOEN_Pos)) /* Assignment of value for FIFOEN in the SERCOM_USART_CTRLC register */
+#define SERCOM_USART_CTRLC_RXTRHOLD_Pos       _UINT32_(28)                                         /* (SERCOM_USART_CTRLC) Receive FIFO Threshold Position */
+#define SERCOM_USART_CTRLC_RXTRHOLD_Msk       (_UINT32_(0x3) << SERCOM_USART_CTRLC_RXTRHOLD_Pos)   /* (SERCOM_USART_CTRLC) Receive FIFO Threshold Mask */
+#define SERCOM_USART_CTRLC_RXTRHOLD(value)    (SERCOM_USART_CTRLC_RXTRHOLD_Msk & (_UINT32_(value) << SERCOM_USART_CTRLC_RXTRHOLD_Pos)) /* Assignment of value for RXTRHOLD in the SERCOM_USART_CTRLC register */
+#define   SERCOM_USART_CTRLC_RXTRHOLD_DEFAULT_Val _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated when DATA is present in the FIFO  */
+#define   SERCOM_USART_CTRLC_RXTRHOLD_HALF_Val _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated when FIFO is half-full  */
+#define   SERCOM_USART_CTRLC_RXTRHOLD_FULL_Val _UINT32_(0x2)                                        /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated when FIFO is full  */
+#define SERCOM_USART_CTRLC_RXTRHOLD_DEFAULT   (SERCOM_USART_CTRLC_RXTRHOLD_DEFAULT_Val << SERCOM_USART_CTRLC_RXTRHOLD_Pos) /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated when DATA is present in the FIFO Position */
+#define SERCOM_USART_CTRLC_RXTRHOLD_HALF      (SERCOM_USART_CTRLC_RXTRHOLD_HALF_Val << SERCOM_USART_CTRLC_RXTRHOLD_Pos) /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated when FIFO is half-full Position */
+#define SERCOM_USART_CTRLC_RXTRHOLD_FULL      (SERCOM_USART_CTRLC_RXTRHOLD_FULL_Val << SERCOM_USART_CTRLC_RXTRHOLD_Pos) /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated when FIFO is full Position */
+#define SERCOM_USART_CTRLC_TXTRHOLD_Pos       _UINT32_(30)                                         /* (SERCOM_USART_CTRLC) Transmit FIFO Threshold Position */
+#define SERCOM_USART_CTRLC_TXTRHOLD_Msk       (_UINT32_(0x3) << SERCOM_USART_CTRLC_TXTRHOLD_Pos)   /* (SERCOM_USART_CTRLC) Transmit FIFO Threshold Mask */
+#define SERCOM_USART_CTRLC_TXTRHOLD(value)    (SERCOM_USART_CTRLC_TXTRHOLD_Msk & (_UINT32_(value) << SERCOM_USART_CTRLC_TXTRHOLD_Pos)) /* Assignment of value for TXTRHOLD in the SERCOM_USART_CTRLC register */
+#define   SERCOM_USART_CTRLC_TXTRHOLD_DEFAULT_Val _UINT32_(0x0)                                        /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full  */
+#define   SERCOM_USART_CTRLC_TXTRHOLD_HALF_Val _UINT32_(0x1)                                        /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated when half FIFO space is free  */
+#define   SERCOM_USART_CTRLC_TXTRHOLD_EMPTY_Val _UINT32_(0x2)                                        /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated when the FIFO is empty  */
+#define SERCOM_USART_CTRLC_TXTRHOLD_DEFAULT   (SERCOM_USART_CTRLC_TXTRHOLD_DEFAULT_Val << SERCOM_USART_CTRLC_TXTRHOLD_Pos) /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated as long as the FIFO is not full Position */
+#define SERCOM_USART_CTRLC_TXTRHOLD_HALF      (SERCOM_USART_CTRLC_TXTRHOLD_HALF_Val << SERCOM_USART_CTRLC_TXTRHOLD_Pos) /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated when half FIFO space is free Position */
+#define SERCOM_USART_CTRLC_TXTRHOLD_EMPTY     (SERCOM_USART_CTRLC_TXTRHOLD_EMPTY_Val << SERCOM_USART_CTRLC_TXTRHOLD_Pos) /* (SERCOM_USART_CTRLC) Interrupt and DMA triggers are generated when the FIFO is empty Position */
+#define SERCOM_USART_CTRLC_Msk                _UINT32_(0xFB730F07)                                 /* (SERCOM_USART_CTRLC) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM Baud Rate -------- */
+#define SERCOM_I2CM_BAUD_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_I2CM_BAUD) I2CM Baud Rate  Reset Value */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos             _UINT32_(0)                                          /* (SERCOM_I2CM_BAUD) Baud Rate Value Position */
+#define SERCOM_I2CM_BAUD_BAUD_Msk             (_UINT32_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)        /* (SERCOM_I2CM_BAUD) Baud Rate Value Mask */
+#define SERCOM_I2CM_BAUD_BAUD(value)          (SERCOM_I2CM_BAUD_BAUD_Msk & (_UINT32_(value) << SERCOM_I2CM_BAUD_BAUD_Pos)) /* Assignment of value for BAUD in the SERCOM_I2CM_BAUD register */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos          _UINT32_(8)                                          /* (SERCOM_I2CM_BAUD) Baud Rate Value Low Position */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk          (_UINT32_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)     /* (SERCOM_I2CM_BAUD) Baud Rate Value Low Mask */
+#define SERCOM_I2CM_BAUD_BAUDLOW(value)       (SERCOM_I2CM_BAUD_BAUDLOW_Msk & (_UINT32_(value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)) /* Assignment of value for BAUDLOW in the SERCOM_I2CM_BAUD register */
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos           _UINT32_(16)                                         /* (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Position */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk           (_UINT32_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)      /* (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Mask */
+#define SERCOM_I2CM_BAUD_HSBAUD(value)        (SERCOM_I2CM_BAUD_HSBAUD_Msk & (_UINT32_(value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)) /* Assignment of value for HSBAUD in the SERCOM_I2CM_BAUD register */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos        _UINT32_(24)                                         /* (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low Position */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk        (_UINT32_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)   /* (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low Mask */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value)     (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & (_UINT32_(value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)) /* Assignment of value for HSBAUDLOW in the SERCOM_I2CM_BAUD register */
+#define SERCOM_I2CM_BAUD_Msk                  _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_I2CM_BAUD) Register Mask  */
+
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI Baud Rate -------- */
+#define SERCOM_SPI_BAUD_RESETVALUE            _UINT8_(0x00)                                        /*  (SERCOM_SPI_BAUD) SPI Baud Rate  Reset Value */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos              _UINT8_(0)                                           /* (SERCOM_SPI_BAUD) Baud Rate Value Position */
+#define SERCOM_SPI_BAUD_BAUD_Msk              (_UINT8_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos)          /* (SERCOM_SPI_BAUD) Baud Rate Value Mask */
+#define SERCOM_SPI_BAUD_BAUD(value)           (SERCOM_SPI_BAUD_BAUD_Msk & (_UINT8_(value) << SERCOM_SPI_BAUD_BAUD_Pos)) /* Assignment of value for BAUD in the SERCOM_SPI_BAUD register */
+#define SERCOM_SPI_BAUD_Msk                   _UINT8_(0xFF)                                        /* (SERCOM_SPI_BAUD) Register Mask  */
+
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART Baud Rate -------- */
+#define SERCOM_USART_BAUD_RESETVALUE          _UINT16_(0x00)                                       /*  (SERCOM_USART_BAUD) USART Baud Rate  Reset Value */
+
+#define SERCOM_USART_BAUD_BAUD_Pos            _UINT16_(0)                                          /* (SERCOM_USART_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_BAUD_BAUD_Msk            (_UINT16_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos)     /* (SERCOM_USART_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_BAUD_BAUD(value)         (SERCOM_USART_BAUD_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_BAUD_BAUD_Pos)) /* Assignment of value for BAUD in the SERCOM_USART_BAUD register */
+#define SERCOM_USART_BAUD_Msk                 _UINT16_(0xFFFF)                                     /* (SERCOM_USART_BAUD) Register Mask  */
+
+/* FRAC mode */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Pos       _UINT16_(0)                                          /* (SERCOM_USART_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Msk       (_UINT16_(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos) /* (SERCOM_USART_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_BAUD_FRAC_BAUD(value)    (SERCOM_USART_BAUD_FRAC_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRAC_FP_Pos         _UINT16_(13)                                         /* (SERCOM_USART_BAUD) Fractional Part Position */
+#define SERCOM_USART_BAUD_FRAC_FP_Msk         (_UINT16_(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos)     /* (SERCOM_USART_BAUD) Fractional Part Mask */
+#define SERCOM_USART_BAUD_FRAC_FP(value)      (SERCOM_USART_BAUD_FRAC_FP_Msk & (_UINT16_(value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
+#define SERCOM_USART_BAUD_FRAC_Msk            _UINT16_(0xFFFF)                                     /* (SERCOM_USART_BAUD_FRAC) Register Mask  */
+
+/* FRACFP mode */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos     _UINT16_(0)                                          /* (SERCOM_USART_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk     (_UINT16_(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos) /* (SERCOM_USART_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_BAUD_FRACFP_BAUD(value)  (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRACFP_FP_Pos       _UINT16_(13)                                         /* (SERCOM_USART_BAUD) Fractional Part Position */
+#define SERCOM_USART_BAUD_FRACFP_FP_Msk       (_UINT16_(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos)   /* (SERCOM_USART_BAUD) Fractional Part Mask */
+#define SERCOM_USART_BAUD_FRACFP_FP(value)    (SERCOM_USART_BAUD_FRACFP_FP_Msk & (_UINT16_(value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
+#define SERCOM_USART_BAUD_FRACFP_Msk          _UINT16_(0xFFFF)                                     /* (SERCOM_USART_BAUD_FRACFP) Register Mask  */
+
+/* USARTFP mode */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos    _UINT16_(0)                                          /* (SERCOM_USART_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk    (_UINT16_(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos) /* (SERCOM_USART_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & (_UINT16_(value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_USARTFP_Msk         _UINT16_(0xFFFF)                                     /* (SERCOM_USART_BAUD_USARTFP) Register Mask  */
+
+
+/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART Receive Pulse Length -------- */
+#define SERCOM_USART_RXPL_RESETVALUE          _UINT8_(0x00)                                        /*  (SERCOM_USART_RXPL) USART Receive Pulse Length  Reset Value */
+
+#define SERCOM_USART_RXPL_RXPL_Pos            _UINT8_(0)                                           /* (SERCOM_USART_RXPL) Receive Pulse Length Position */
+#define SERCOM_USART_RXPL_RXPL_Msk            (_UINT8_(0xFF) << SERCOM_USART_RXPL_RXPL_Pos)        /* (SERCOM_USART_RXPL) Receive Pulse Length Mask */
+#define SERCOM_USART_RXPL_RXPL(value)         (SERCOM_USART_RXPL_RXPL_Msk & (_UINT8_(value) << SERCOM_USART_RXPL_RXPL_Pos)) /* Assignment of value for RXPL in the SERCOM_USART_RXPL register */
+#define SERCOM_USART_RXPL_Msk                 _UINT8_(0xFF)                                        /* (SERCOM_USART_RXPL) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM Interrupt Enable Clear -------- */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_I2CM_INTENCLR) I2CM Interrupt Enable Clear  Reset Value */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos           _UINT8_(0)                                           /* (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable Position */
+#define SERCOM_I2CM_INTENCLR_MB_Msk           (_UINT8_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)        /* (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable Mask */
+#define SERCOM_I2CM_INTENCLR_MB(value)        (SERCOM_I2CM_INTENCLR_MB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENCLR_MB_Pos)) /* Assignment of value for MB in the SERCOM_I2CM_INTENCLR register */
+#define SERCOM_I2CM_INTENCLR_SB_Pos           _UINT8_(1)                                           /* (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable Position */
+#define SERCOM_I2CM_INTENCLR_SB_Msk           (_UINT8_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)        /* (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable Mask */
+#define SERCOM_I2CM_INTENCLR_SB(value)        (SERCOM_I2CM_INTENCLR_SB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENCLR_SB_Pos)) /* Assignment of value for SB in the SERCOM_I2CM_INTENCLR register */
+#define SERCOM_I2CM_INTENCLR_TXFE_Pos         _UINT8_(3)                                           /* (SERCOM_I2CM_INTENCLR) Tx FIFO Empty Interrupt Disable Position */
+#define SERCOM_I2CM_INTENCLR_TXFE_Msk         (_UINT8_(0x1) << SERCOM_I2CM_INTENCLR_TXFE_Pos)      /* (SERCOM_I2CM_INTENCLR) Tx FIFO Empty Interrupt Disable Mask */
+#define SERCOM_I2CM_INTENCLR_TXFE(value)      (SERCOM_I2CM_INTENCLR_TXFE_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENCLR_TXFE_Pos)) /* Assignment of value for TXFE in the SERCOM_I2CM_INTENCLR register */
+#define SERCOM_I2CM_INTENCLR_RXFF_Pos         _UINT8_(4)                                           /* (SERCOM_I2CM_INTENCLR) Rx FIFO Full Interrupt Disable Position */
+#define SERCOM_I2CM_INTENCLR_RXFF_Msk         (_UINT8_(0x1) << SERCOM_I2CM_INTENCLR_RXFF_Pos)      /* (SERCOM_I2CM_INTENCLR) Rx FIFO Full Interrupt Disable Mask */
+#define SERCOM_I2CM_INTENCLR_RXFF(value)      (SERCOM_I2CM_INTENCLR_RXFF_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENCLR_RXFF_Pos)) /* Assignment of value for RXFF in the SERCOM_I2CM_INTENCLR register */
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable Position */
+#define SERCOM_I2CM_INTENCLR_ERROR_Msk        (_UINT8_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)     /* (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable Mask */
+#define SERCOM_I2CM_INTENCLR_ERROR(value)     (SERCOM_I2CM_INTENCLR_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENCLR_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_I2CM_INTENCLR register */
+#define SERCOM_I2CM_INTENCLR_Msk              _UINT8_(0x9B)                                        /* (SERCOM_I2CM_INTENCLR) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS Interrupt Enable Clear -------- */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_I2CS_INTENCLR) I2CS Interrupt Enable Clear  Reset Value */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos         _UINT8_(0)                                           /* (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable Position */
+#define SERCOM_I2CS_INTENCLR_PREC_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)      /* (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable Mask */
+#define SERCOM_I2CS_INTENCLR_PREC(value)      (SERCOM_I2CS_INTENCLR_PREC_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENCLR_PREC_Pos)) /* Assignment of value for PREC in the SERCOM_I2CS_INTENCLR register */
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos       _UINT8_(1)                                           /* (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable Position */
+#define SERCOM_I2CS_INTENCLR_AMATCH_Msk       (_UINT8_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)    /* (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable Mask */
+#define SERCOM_I2CS_INTENCLR_AMATCH(value)    (SERCOM_I2CS_INTENCLR_AMATCH_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)) /* Assignment of value for AMATCH in the SERCOM_I2CS_INTENCLR register */
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos         _UINT8_(2)                                           /* (SERCOM_I2CS_INTENCLR) Data Interrupt Disable Position */
+#define SERCOM_I2CS_INTENCLR_DRDY_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)      /* (SERCOM_I2CS_INTENCLR) Data Interrupt Disable Mask */
+#define SERCOM_I2CS_INTENCLR_DRDY(value)      (SERCOM_I2CS_INTENCLR_DRDY_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENCLR_DRDY_Pos)) /* Assignment of value for DRDY in the SERCOM_I2CS_INTENCLR register */
+#define SERCOM_I2CS_INTENCLR_TXFE_Pos         _UINT8_(3)                                           /* (SERCOM_I2CS_INTENCLR) Tx FIFO Empty Interrupt Disable Position */
+#define SERCOM_I2CS_INTENCLR_TXFE_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENCLR_TXFE_Pos)      /* (SERCOM_I2CS_INTENCLR) Tx FIFO Empty Interrupt Disable Mask */
+#define SERCOM_I2CS_INTENCLR_TXFE(value)      (SERCOM_I2CS_INTENCLR_TXFE_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENCLR_TXFE_Pos)) /* Assignment of value for TXFE in the SERCOM_I2CS_INTENCLR register */
+#define SERCOM_I2CS_INTENCLR_RXFF_Pos         _UINT8_(4)                                           /* (SERCOM_I2CS_INTENCLR) Rx FIFO Full Interrupt Disable Position */
+#define SERCOM_I2CS_INTENCLR_RXFF_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENCLR_RXFF_Pos)      /* (SERCOM_I2CS_INTENCLR) Rx FIFO Full Interrupt Disable Mask */
+#define SERCOM_I2CS_INTENCLR_RXFF(value)      (SERCOM_I2CS_INTENCLR_RXFF_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENCLR_RXFF_Pos)) /* Assignment of value for RXFF in the SERCOM_I2CS_INTENCLR register */
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable Position */
+#define SERCOM_I2CS_INTENCLR_ERROR_Msk        (_UINT8_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)     /* (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable Mask */
+#define SERCOM_I2CS_INTENCLR_ERROR(value)     (SERCOM_I2CS_INTENCLR_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENCLR_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_I2CS_INTENCLR register */
+#define SERCOM_I2CS_INTENCLR_Msk              _UINT8_(0x9F)                                        /* (SERCOM_I2CS_INTENCLR) Register Mask  */
+
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI Interrupt Enable Clear -------- */
+#define SERCOM_SPI_INTENCLR_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_SPI_INTENCLR) SPI Interrupt Enable Clear  Reset Value */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos           _UINT8_(0)                                           /* (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable Position */
+#define SERCOM_SPI_INTENCLR_DRE_Msk           (_UINT8_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos)        /* (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable Mask */
+#define SERCOM_SPI_INTENCLR_DRE(value)        (SERCOM_SPI_INTENCLR_DRE_Msk & (_UINT8_(value) << SERCOM_SPI_INTENCLR_DRE_Pos)) /* Assignment of value for DRE in the SERCOM_SPI_INTENCLR register */
+#define SERCOM_SPI_INTENCLR_TXC_Pos           _UINT8_(1)                                           /* (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable Position */
+#define SERCOM_SPI_INTENCLR_TXC_Msk           (_UINT8_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos)        /* (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable Mask */
+#define SERCOM_SPI_INTENCLR_TXC(value)        (SERCOM_SPI_INTENCLR_TXC_Msk & (_UINT8_(value) << SERCOM_SPI_INTENCLR_TXC_Pos)) /* Assignment of value for TXC in the SERCOM_SPI_INTENCLR register */
+#define SERCOM_SPI_INTENCLR_RXC_Pos           _UINT8_(2)                                           /* (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable Position */
+#define SERCOM_SPI_INTENCLR_RXC_Msk           (_UINT8_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos)        /* (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable Mask */
+#define SERCOM_SPI_INTENCLR_RXC(value)        (SERCOM_SPI_INTENCLR_RXC_Msk & (_UINT8_(value) << SERCOM_SPI_INTENCLR_RXC_Pos)) /* Assignment of value for RXC in the SERCOM_SPI_INTENCLR register */
+#define SERCOM_SPI_INTENCLR_SSL_Pos           _UINT8_(3)                                           /* (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable Position */
+#define SERCOM_SPI_INTENCLR_SSL_Msk           (_UINT8_(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos)        /* (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable Mask */
+#define SERCOM_SPI_INTENCLR_SSL(value)        (SERCOM_SPI_INTENCLR_SSL_Msk & (_UINT8_(value) << SERCOM_SPI_INTENCLR_SSL_Pos)) /* Assignment of value for SSL in the SERCOM_SPI_INTENCLR register */
+#define SERCOM_SPI_INTENCLR_ERROR_Pos         _UINT8_(7)                                           /* (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable Position */
+#define SERCOM_SPI_INTENCLR_ERROR_Msk         (_UINT8_(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos)      /* (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable Mask */
+#define SERCOM_SPI_INTENCLR_ERROR(value)      (SERCOM_SPI_INTENCLR_ERROR_Msk & (_UINT8_(value) << SERCOM_SPI_INTENCLR_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_SPI_INTENCLR register */
+#define SERCOM_SPI_INTENCLR_Msk               _UINT8_(0x8F)                                        /* (SERCOM_SPI_INTENCLR) Register Mask  */
+
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART Interrupt Enable Clear -------- */
+#define SERCOM_USART_INTENCLR_RESETVALUE      _UINT8_(0x00)                                        /*  (SERCOM_USART_INTENCLR) USART Interrupt Enable Clear  Reset Value */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos         _UINT8_(0)                                           /* (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable Position */
+#define SERCOM_USART_INTENCLR_DRE_Msk         (_UINT8_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos)      /* (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable Mask */
+#define SERCOM_USART_INTENCLR_DRE(value)      (SERCOM_USART_INTENCLR_DRE_Msk & (_UINT8_(value) << SERCOM_USART_INTENCLR_DRE_Pos)) /* Assignment of value for DRE in the SERCOM_USART_INTENCLR register */
+#define SERCOM_USART_INTENCLR_TXC_Pos         _UINT8_(1)                                           /* (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable Position */
+#define SERCOM_USART_INTENCLR_TXC_Msk         (_UINT8_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos)      /* (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable Mask */
+#define SERCOM_USART_INTENCLR_TXC(value)      (SERCOM_USART_INTENCLR_TXC_Msk & (_UINT8_(value) << SERCOM_USART_INTENCLR_TXC_Pos)) /* Assignment of value for TXC in the SERCOM_USART_INTENCLR register */
+#define SERCOM_USART_INTENCLR_RXC_Pos         _UINT8_(2)                                           /* (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable Position */
+#define SERCOM_USART_INTENCLR_RXC_Msk         (_UINT8_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos)      /* (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable Mask */
+#define SERCOM_USART_INTENCLR_RXC(value)      (SERCOM_USART_INTENCLR_RXC_Msk & (_UINT8_(value) << SERCOM_USART_INTENCLR_RXC_Pos)) /* Assignment of value for RXC in the SERCOM_USART_INTENCLR register */
+#define SERCOM_USART_INTENCLR_RXS_Pos         _UINT8_(3)                                           /* (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable Position */
+#define SERCOM_USART_INTENCLR_RXS_Msk         (_UINT8_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos)      /* (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable Mask */
+#define SERCOM_USART_INTENCLR_RXS(value)      (SERCOM_USART_INTENCLR_RXS_Msk & (_UINT8_(value) << SERCOM_USART_INTENCLR_RXS_Pos)) /* Assignment of value for RXS in the SERCOM_USART_INTENCLR register */
+#define SERCOM_USART_INTENCLR_CTSIC_Pos       _UINT8_(4)                                           /* (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable Position */
+#define SERCOM_USART_INTENCLR_CTSIC_Msk       (_UINT8_(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos)    /* (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable Mask */
+#define SERCOM_USART_INTENCLR_CTSIC(value)    (SERCOM_USART_INTENCLR_CTSIC_Msk & (_UINT8_(value) << SERCOM_USART_INTENCLR_CTSIC_Pos)) /* Assignment of value for CTSIC in the SERCOM_USART_INTENCLR register */
+#define SERCOM_USART_INTENCLR_RXBRK_Pos       _UINT8_(5)                                           /* (SERCOM_USART_INTENCLR) Break Received Interrupt Disable Position */
+#define SERCOM_USART_INTENCLR_RXBRK_Msk       (_UINT8_(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos)    /* (SERCOM_USART_INTENCLR) Break Received Interrupt Disable Mask */
+#define SERCOM_USART_INTENCLR_RXBRK(value)    (SERCOM_USART_INTENCLR_RXBRK_Msk & (_UINT8_(value) << SERCOM_USART_INTENCLR_RXBRK_Pos)) /* Assignment of value for RXBRK in the SERCOM_USART_INTENCLR register */
+#define SERCOM_USART_INTENCLR_ERROR_Pos       _UINT8_(7)                                           /* (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable Position */
+#define SERCOM_USART_INTENCLR_ERROR_Msk       (_UINT8_(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos)    /* (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable Mask */
+#define SERCOM_USART_INTENCLR_ERROR(value)    (SERCOM_USART_INTENCLR_ERROR_Msk & (_UINT8_(value) << SERCOM_USART_INTENCLR_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_USART_INTENCLR register */
+#define SERCOM_USART_INTENCLR_Msk             _UINT8_(0xBF)                                        /* (SERCOM_USART_INTENCLR) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM Interrupt Enable Set -------- */
+#define SERCOM_I2CM_INTENSET_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_I2CM_INTENSET) I2CM Interrupt Enable Set  Reset Value */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos           _UINT8_(0)                                           /* (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable Position */
+#define SERCOM_I2CM_INTENSET_MB_Msk           (_UINT8_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)        /* (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable Mask */
+#define SERCOM_I2CM_INTENSET_MB(value)        (SERCOM_I2CM_INTENSET_MB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENSET_MB_Pos)) /* Assignment of value for MB in the SERCOM_I2CM_INTENSET register */
+#define SERCOM_I2CM_INTENSET_SB_Pos           _UINT8_(1)                                           /* (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable Position */
+#define SERCOM_I2CM_INTENSET_SB_Msk           (_UINT8_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)        /* (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable Mask */
+#define SERCOM_I2CM_INTENSET_SB(value)        (SERCOM_I2CM_INTENSET_SB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENSET_SB_Pos)) /* Assignment of value for SB in the SERCOM_I2CM_INTENSET register */
+#define SERCOM_I2CM_INTENSET_TXFE_Pos         _UINT8_(3)                                           /* (SERCOM_I2CM_INTENSET) Tx FIFO Empty Interrupt Enable Position */
+#define SERCOM_I2CM_INTENSET_TXFE_Msk         (_UINT8_(0x1) << SERCOM_I2CM_INTENSET_TXFE_Pos)      /* (SERCOM_I2CM_INTENSET) Tx FIFO Empty Interrupt Enable Mask */
+#define SERCOM_I2CM_INTENSET_TXFE(value)      (SERCOM_I2CM_INTENSET_TXFE_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENSET_TXFE_Pos)) /* Assignment of value for TXFE in the SERCOM_I2CM_INTENSET register */
+#define SERCOM_I2CM_INTENSET_RXFF_Pos         _UINT8_(4)                                           /* (SERCOM_I2CM_INTENSET) Rx FIFO Full Interrupt Enable Position */
+#define SERCOM_I2CM_INTENSET_RXFF_Msk         (_UINT8_(0x1) << SERCOM_I2CM_INTENSET_RXFF_Pos)      /* (SERCOM_I2CM_INTENSET) Rx FIFO Full Interrupt Enable Mask */
+#define SERCOM_I2CM_INTENSET_RXFF(value)      (SERCOM_I2CM_INTENSET_RXFF_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENSET_RXFF_Pos)) /* Assignment of value for RXFF in the SERCOM_I2CM_INTENSET register */
+#define SERCOM_I2CM_INTENSET_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable Position */
+#define SERCOM_I2CM_INTENSET_ERROR_Msk        (_UINT8_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)     /* (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable Mask */
+#define SERCOM_I2CM_INTENSET_ERROR(value)     (SERCOM_I2CM_INTENSET_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CM_INTENSET_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_I2CM_INTENSET register */
+#define SERCOM_I2CM_INTENSET_Msk              _UINT8_(0x9B)                                        /* (SERCOM_I2CM_INTENSET) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS Interrupt Enable Set -------- */
+#define SERCOM_I2CS_INTENSET_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_I2CS_INTENSET) I2CS Interrupt Enable Set  Reset Value */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos         _UINT8_(0)                                           /* (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable Position */
+#define SERCOM_I2CS_INTENSET_PREC_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)      /* (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable Mask */
+#define SERCOM_I2CS_INTENSET_PREC(value)      (SERCOM_I2CS_INTENSET_PREC_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENSET_PREC_Pos)) /* Assignment of value for PREC in the SERCOM_I2CS_INTENSET register */
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos       _UINT8_(1)                                           /* (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable Position */
+#define SERCOM_I2CS_INTENSET_AMATCH_Msk       (_UINT8_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)    /* (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable Mask */
+#define SERCOM_I2CS_INTENSET_AMATCH(value)    (SERCOM_I2CS_INTENSET_AMATCH_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENSET_AMATCH_Pos)) /* Assignment of value for AMATCH in the SERCOM_I2CS_INTENSET register */
+#define SERCOM_I2CS_INTENSET_DRDY_Pos         _UINT8_(2)                                           /* (SERCOM_I2CS_INTENSET) Data Interrupt Enable Position */
+#define SERCOM_I2CS_INTENSET_DRDY_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)      /* (SERCOM_I2CS_INTENSET) Data Interrupt Enable Mask */
+#define SERCOM_I2CS_INTENSET_DRDY(value)      (SERCOM_I2CS_INTENSET_DRDY_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENSET_DRDY_Pos)) /* Assignment of value for DRDY in the SERCOM_I2CS_INTENSET register */
+#define SERCOM_I2CS_INTENSET_TXFE_Pos         _UINT8_(3)                                           /* (SERCOM_I2CS_INTENSET) Tx FIFO Empty Interrupt Enable Position */
+#define SERCOM_I2CS_INTENSET_TXFE_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENSET_TXFE_Pos)      /* (SERCOM_I2CS_INTENSET) Tx FIFO Empty Interrupt Enable Mask */
+#define SERCOM_I2CS_INTENSET_TXFE(value)      (SERCOM_I2CS_INTENSET_TXFE_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENSET_TXFE_Pos)) /* Assignment of value for TXFE in the SERCOM_I2CS_INTENSET register */
+#define SERCOM_I2CS_INTENSET_RXFF_Pos         _UINT8_(4)                                           /* (SERCOM_I2CS_INTENSET) Rx FIFO Full Interrupt Enable Position */
+#define SERCOM_I2CS_INTENSET_RXFF_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTENSET_RXFF_Pos)      /* (SERCOM_I2CS_INTENSET) Rx FIFO Full Interrupt Enable Mask */
+#define SERCOM_I2CS_INTENSET_RXFF(value)      (SERCOM_I2CS_INTENSET_RXFF_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENSET_RXFF_Pos)) /* Assignment of value for RXFF in the SERCOM_I2CS_INTENSET register */
+#define SERCOM_I2CS_INTENSET_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable Position */
+#define SERCOM_I2CS_INTENSET_ERROR_Msk        (_UINT8_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)     /* (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable Mask */
+#define SERCOM_I2CS_INTENSET_ERROR(value)     (SERCOM_I2CS_INTENSET_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CS_INTENSET_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_I2CS_INTENSET register */
+#define SERCOM_I2CS_INTENSET_Msk              _UINT8_(0x9F)                                        /* (SERCOM_I2CS_INTENSET) Register Mask  */
+
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI Interrupt Enable Set -------- */
+#define SERCOM_SPI_INTENSET_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_SPI_INTENSET) SPI Interrupt Enable Set  Reset Value */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos           _UINT8_(0)                                           /* (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable Position */
+#define SERCOM_SPI_INTENSET_DRE_Msk           (_UINT8_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos)        /* (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable Mask */
+#define SERCOM_SPI_INTENSET_DRE(value)        (SERCOM_SPI_INTENSET_DRE_Msk & (_UINT8_(value) << SERCOM_SPI_INTENSET_DRE_Pos)) /* Assignment of value for DRE in the SERCOM_SPI_INTENSET register */
+#define SERCOM_SPI_INTENSET_TXC_Pos           _UINT8_(1)                                           /* (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable Position */
+#define SERCOM_SPI_INTENSET_TXC_Msk           (_UINT8_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos)        /* (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable Mask */
+#define SERCOM_SPI_INTENSET_TXC(value)        (SERCOM_SPI_INTENSET_TXC_Msk & (_UINT8_(value) << SERCOM_SPI_INTENSET_TXC_Pos)) /* Assignment of value for TXC in the SERCOM_SPI_INTENSET register */
+#define SERCOM_SPI_INTENSET_RXC_Pos           _UINT8_(2)                                           /* (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable Position */
+#define SERCOM_SPI_INTENSET_RXC_Msk           (_UINT8_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos)        /* (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable Mask */
+#define SERCOM_SPI_INTENSET_RXC(value)        (SERCOM_SPI_INTENSET_RXC_Msk & (_UINT8_(value) << SERCOM_SPI_INTENSET_RXC_Pos)) /* Assignment of value for RXC in the SERCOM_SPI_INTENSET register */
+#define SERCOM_SPI_INTENSET_SSL_Pos           _UINT8_(3)                                           /* (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable Position */
+#define SERCOM_SPI_INTENSET_SSL_Msk           (_UINT8_(0x1) << SERCOM_SPI_INTENSET_SSL_Pos)        /* (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable Mask */
+#define SERCOM_SPI_INTENSET_SSL(value)        (SERCOM_SPI_INTENSET_SSL_Msk & (_UINT8_(value) << SERCOM_SPI_INTENSET_SSL_Pos)) /* Assignment of value for SSL in the SERCOM_SPI_INTENSET register */
+#define SERCOM_SPI_INTENSET_ERROR_Pos         _UINT8_(7)                                           /* (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable Position */
+#define SERCOM_SPI_INTENSET_ERROR_Msk         (_UINT8_(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos)      /* (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable Mask */
+#define SERCOM_SPI_INTENSET_ERROR(value)      (SERCOM_SPI_INTENSET_ERROR_Msk & (_UINT8_(value) << SERCOM_SPI_INTENSET_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_SPI_INTENSET register */
+#define SERCOM_SPI_INTENSET_Msk               _UINT8_(0x8F)                                        /* (SERCOM_SPI_INTENSET) Register Mask  */
+
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART Interrupt Enable Set -------- */
+#define SERCOM_USART_INTENSET_RESETVALUE      _UINT8_(0x00)                                        /*  (SERCOM_USART_INTENSET) USART Interrupt Enable Set  Reset Value */
+
+#define SERCOM_USART_INTENSET_DRE_Pos         _UINT8_(0)                                           /* (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable Position */
+#define SERCOM_USART_INTENSET_DRE_Msk         (_UINT8_(0x1) << SERCOM_USART_INTENSET_DRE_Pos)      /* (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable Mask */
+#define SERCOM_USART_INTENSET_DRE(value)      (SERCOM_USART_INTENSET_DRE_Msk & (_UINT8_(value) << SERCOM_USART_INTENSET_DRE_Pos)) /* Assignment of value for DRE in the SERCOM_USART_INTENSET register */
+#define SERCOM_USART_INTENSET_TXC_Pos         _UINT8_(1)                                           /* (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable Position */
+#define SERCOM_USART_INTENSET_TXC_Msk         (_UINT8_(0x1) << SERCOM_USART_INTENSET_TXC_Pos)      /* (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable Mask */
+#define SERCOM_USART_INTENSET_TXC(value)      (SERCOM_USART_INTENSET_TXC_Msk & (_UINT8_(value) << SERCOM_USART_INTENSET_TXC_Pos)) /* Assignment of value for TXC in the SERCOM_USART_INTENSET register */
+#define SERCOM_USART_INTENSET_RXC_Pos         _UINT8_(2)                                           /* (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable Position */
+#define SERCOM_USART_INTENSET_RXC_Msk         (_UINT8_(0x1) << SERCOM_USART_INTENSET_RXC_Pos)      /* (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable Mask */
+#define SERCOM_USART_INTENSET_RXC(value)      (SERCOM_USART_INTENSET_RXC_Msk & (_UINT8_(value) << SERCOM_USART_INTENSET_RXC_Pos)) /* Assignment of value for RXC in the SERCOM_USART_INTENSET register */
+#define SERCOM_USART_INTENSET_RXS_Pos         _UINT8_(3)                                           /* (SERCOM_USART_INTENSET) Receive Start Interrupt Enable Position */
+#define SERCOM_USART_INTENSET_RXS_Msk         (_UINT8_(0x1) << SERCOM_USART_INTENSET_RXS_Pos)      /* (SERCOM_USART_INTENSET) Receive Start Interrupt Enable Mask */
+#define SERCOM_USART_INTENSET_RXS(value)      (SERCOM_USART_INTENSET_RXS_Msk & (_UINT8_(value) << SERCOM_USART_INTENSET_RXS_Pos)) /* Assignment of value for RXS in the SERCOM_USART_INTENSET register */
+#define SERCOM_USART_INTENSET_CTSIC_Pos       _UINT8_(4)                                           /* (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable Position */
+#define SERCOM_USART_INTENSET_CTSIC_Msk       (_UINT8_(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos)    /* (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable Mask */
+#define SERCOM_USART_INTENSET_CTSIC(value)    (SERCOM_USART_INTENSET_CTSIC_Msk & (_UINT8_(value) << SERCOM_USART_INTENSET_CTSIC_Pos)) /* Assignment of value for CTSIC in the SERCOM_USART_INTENSET register */
+#define SERCOM_USART_INTENSET_RXBRK_Pos       _UINT8_(5)                                           /* (SERCOM_USART_INTENSET) Break Received Interrupt Enable Position */
+#define SERCOM_USART_INTENSET_RXBRK_Msk       (_UINT8_(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos)    /* (SERCOM_USART_INTENSET) Break Received Interrupt Enable Mask */
+#define SERCOM_USART_INTENSET_RXBRK(value)    (SERCOM_USART_INTENSET_RXBRK_Msk & (_UINT8_(value) << SERCOM_USART_INTENSET_RXBRK_Pos)) /* Assignment of value for RXBRK in the SERCOM_USART_INTENSET register */
+#define SERCOM_USART_INTENSET_ERROR_Pos       _UINT8_(7)                                           /* (SERCOM_USART_INTENSET) Combined Error Interrupt Enable Position */
+#define SERCOM_USART_INTENSET_ERROR_Msk       (_UINT8_(0x1) << SERCOM_USART_INTENSET_ERROR_Pos)    /* (SERCOM_USART_INTENSET) Combined Error Interrupt Enable Mask */
+#define SERCOM_USART_INTENSET_ERROR(value)    (SERCOM_USART_INTENSET_ERROR_Msk & (_UINT8_(value) << SERCOM_USART_INTENSET_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_USART_INTENSET register */
+#define SERCOM_USART_INTENSET_Msk             _UINT8_(0xBF)                                        /* (SERCOM_USART_INTENSET) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM Interrupt Flag Status and Clear -------- */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_I2CM_INTFLAG) I2CM Interrupt Flag Status and Clear  Reset Value */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos            _UINT8_(0)                                           /* (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt Position */
+#define SERCOM_I2CM_INTFLAG_MB_Msk            (_UINT8_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)         /* (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt Mask */
+#define SERCOM_I2CM_INTFLAG_MB(value)         (SERCOM_I2CM_INTFLAG_MB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTFLAG_MB_Pos)) /* Assignment of value for MB in the SERCOM_I2CM_INTFLAG register */
+#define SERCOM_I2CM_INTFLAG_SB_Pos            _UINT8_(1)                                           /* (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt Position */
+#define SERCOM_I2CM_INTFLAG_SB_Msk            (_UINT8_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)         /* (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt Mask */
+#define SERCOM_I2CM_INTFLAG_SB(value)         (SERCOM_I2CM_INTFLAG_SB_Msk & (_UINT8_(value) << SERCOM_I2CM_INTFLAG_SB_Pos)) /* Assignment of value for SB in the SERCOM_I2CM_INTFLAG register */
+#define SERCOM_I2CM_INTFLAG_TXFE_Pos          _UINT8_(3)                                           /* (SERCOM_I2CM_INTFLAG) Tx FIFO Empty Interrupt Position */
+#define SERCOM_I2CM_INTFLAG_TXFE_Msk          (_UINT8_(0x1) << SERCOM_I2CM_INTFLAG_TXFE_Pos)       /* (SERCOM_I2CM_INTFLAG) Tx FIFO Empty Interrupt Mask */
+#define SERCOM_I2CM_INTFLAG_TXFE(value)       (SERCOM_I2CM_INTFLAG_TXFE_Msk & (_UINT8_(value) << SERCOM_I2CM_INTFLAG_TXFE_Pos)) /* Assignment of value for TXFE in the SERCOM_I2CM_INTFLAG register */
+#define SERCOM_I2CM_INTFLAG_RXFF_Pos          _UINT8_(4)                                           /* (SERCOM_I2CM_INTFLAG) Rx FIFO Full Interrupt Position */
+#define SERCOM_I2CM_INTFLAG_RXFF_Msk          (_UINT8_(0x1) << SERCOM_I2CM_INTFLAG_RXFF_Pos)       /* (SERCOM_I2CM_INTFLAG) Rx FIFO Full Interrupt Mask */
+#define SERCOM_I2CM_INTFLAG_RXFF(value)       (SERCOM_I2CM_INTFLAG_RXFF_Msk & (_UINT8_(value) << SERCOM_I2CM_INTFLAG_RXFF_Pos)) /* Assignment of value for RXFF in the SERCOM_I2CM_INTFLAG register */
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos         _UINT8_(7)                                           /* (SERCOM_I2CM_INTFLAG) Combined Error Interrupt Position */
+#define SERCOM_I2CM_INTFLAG_ERROR_Msk         (_UINT8_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)      /* (SERCOM_I2CM_INTFLAG) Combined Error Interrupt Mask */
+#define SERCOM_I2CM_INTFLAG_ERROR(value)      (SERCOM_I2CM_INTFLAG_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CM_INTFLAG_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_I2CM_INTFLAG register */
+#define SERCOM_I2CM_INTFLAG_Msk               _UINT8_(0x9B)                                        /* (SERCOM_I2CM_INTFLAG) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS Interrupt Flag Status and Clear -------- */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_I2CS_INTFLAG) I2CS Interrupt Flag Status and Clear  Reset Value */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos          _UINT8_(0)                                           /* (SERCOM_I2CS_INTFLAG) Stop Received Interrupt Position */
+#define SERCOM_I2CS_INTFLAG_PREC_Msk          (_UINT8_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)       /* (SERCOM_I2CS_INTFLAG) Stop Received Interrupt Mask */
+#define SERCOM_I2CS_INTFLAG_PREC(value)       (SERCOM_I2CS_INTFLAG_PREC_Msk & (_UINT8_(value) << SERCOM_I2CS_INTFLAG_PREC_Pos)) /* Assignment of value for PREC in the SERCOM_I2CS_INTFLAG register */
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos        _UINT8_(1)                                           /* (SERCOM_I2CS_INTFLAG) Address Match Interrupt Position */
+#define SERCOM_I2CS_INTFLAG_AMATCH_Msk        (_UINT8_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)     /* (SERCOM_I2CS_INTFLAG) Address Match Interrupt Mask */
+#define SERCOM_I2CS_INTFLAG_AMATCH(value)     (SERCOM_I2CS_INTFLAG_AMATCH_Msk & (_UINT8_(value) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)) /* Assignment of value for AMATCH in the SERCOM_I2CS_INTFLAG register */
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos          _UINT8_(2)                                           /* (SERCOM_I2CS_INTFLAG) Data Interrupt Position */
+#define SERCOM_I2CS_INTFLAG_DRDY_Msk          (_UINT8_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)       /* (SERCOM_I2CS_INTFLAG) Data Interrupt Mask */
+#define SERCOM_I2CS_INTFLAG_DRDY(value)       (SERCOM_I2CS_INTFLAG_DRDY_Msk & (_UINT8_(value) << SERCOM_I2CS_INTFLAG_DRDY_Pos)) /* Assignment of value for DRDY in the SERCOM_I2CS_INTFLAG register */
+#define SERCOM_I2CS_INTFLAG_TXFE_Pos          _UINT8_(3)                                           /* (SERCOM_I2CS_INTFLAG) Tx FIFO Empty Interrupt Position */
+#define SERCOM_I2CS_INTFLAG_TXFE_Msk          (_UINT8_(0x1) << SERCOM_I2CS_INTFLAG_TXFE_Pos)       /* (SERCOM_I2CS_INTFLAG) Tx FIFO Empty Interrupt Mask */
+#define SERCOM_I2CS_INTFLAG_TXFE(value)       (SERCOM_I2CS_INTFLAG_TXFE_Msk & (_UINT8_(value) << SERCOM_I2CS_INTFLAG_TXFE_Pos)) /* Assignment of value for TXFE in the SERCOM_I2CS_INTFLAG register */
+#define SERCOM_I2CS_INTFLAG_RXFF_Pos          _UINT8_(4)                                           /* (SERCOM_I2CS_INTFLAG) Rx FIFO Full Interrupt Position */
+#define SERCOM_I2CS_INTFLAG_RXFF_Msk          (_UINT8_(0x1) << SERCOM_I2CS_INTFLAG_RXFF_Pos)       /* (SERCOM_I2CS_INTFLAG) Rx FIFO Full Interrupt Mask */
+#define SERCOM_I2CS_INTFLAG_RXFF(value)       (SERCOM_I2CS_INTFLAG_RXFF_Msk & (_UINT8_(value) << SERCOM_I2CS_INTFLAG_RXFF_Pos)) /* Assignment of value for RXFF in the SERCOM_I2CS_INTFLAG register */
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos         _UINT8_(7)                                           /* (SERCOM_I2CS_INTFLAG) Combined Error Interrupt Position */
+#define SERCOM_I2CS_INTFLAG_ERROR_Msk         (_UINT8_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)      /* (SERCOM_I2CS_INTFLAG) Combined Error Interrupt Mask */
+#define SERCOM_I2CS_INTFLAG_ERROR(value)      (SERCOM_I2CS_INTFLAG_ERROR_Msk & (_UINT8_(value) << SERCOM_I2CS_INTFLAG_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_I2CS_INTFLAG register */
+#define SERCOM_I2CS_INTFLAG_Msk               _UINT8_(0x9F)                                        /* (SERCOM_I2CS_INTFLAG) Register Mask  */
+
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI Interrupt Flag Status and Clear -------- */
+#define SERCOM_SPI_INTFLAG_RESETVALUE         _UINT8_(0x00)                                        /*  (SERCOM_SPI_INTFLAG) SPI Interrupt Flag Status and Clear  Reset Value */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos            _UINT8_(0)                                           /* (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt Position */
+#define SERCOM_SPI_INTFLAG_DRE_Msk            (_UINT8_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos)         /* (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt Mask */
+#define SERCOM_SPI_INTFLAG_DRE(value)         (SERCOM_SPI_INTFLAG_DRE_Msk & (_UINT8_(value) << SERCOM_SPI_INTFLAG_DRE_Pos)) /* Assignment of value for DRE in the SERCOM_SPI_INTFLAG register */
+#define SERCOM_SPI_INTFLAG_TXC_Pos            _UINT8_(1)                                           /* (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt Position */
+#define SERCOM_SPI_INTFLAG_TXC_Msk            (_UINT8_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos)         /* (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt Mask */
+#define SERCOM_SPI_INTFLAG_TXC(value)         (SERCOM_SPI_INTFLAG_TXC_Msk & (_UINT8_(value) << SERCOM_SPI_INTFLAG_TXC_Pos)) /* Assignment of value for TXC in the SERCOM_SPI_INTFLAG register */
+#define SERCOM_SPI_INTFLAG_RXC_Pos            _UINT8_(2)                                           /* (SERCOM_SPI_INTFLAG) Receive Complete Interrupt Position */
+#define SERCOM_SPI_INTFLAG_RXC_Msk            (_UINT8_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos)         /* (SERCOM_SPI_INTFLAG) Receive Complete Interrupt Mask */
+#define SERCOM_SPI_INTFLAG_RXC(value)         (SERCOM_SPI_INTFLAG_RXC_Msk & (_UINT8_(value) << SERCOM_SPI_INTFLAG_RXC_Pos)) /* Assignment of value for RXC in the SERCOM_SPI_INTFLAG register */
+#define SERCOM_SPI_INTFLAG_SSL_Pos            _UINT8_(3)                                           /* (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag Position */
+#define SERCOM_SPI_INTFLAG_SSL_Msk            (_UINT8_(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos)         /* (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag Mask */
+#define SERCOM_SPI_INTFLAG_SSL(value)         (SERCOM_SPI_INTFLAG_SSL_Msk & (_UINT8_(value) << SERCOM_SPI_INTFLAG_SSL_Pos)) /* Assignment of value for SSL in the SERCOM_SPI_INTFLAG register */
+#define SERCOM_SPI_INTFLAG_ERROR_Pos          _UINT8_(7)                                           /* (SERCOM_SPI_INTFLAG) Combined Error Interrupt Position */
+#define SERCOM_SPI_INTFLAG_ERROR_Msk          (_UINT8_(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos)       /* (SERCOM_SPI_INTFLAG) Combined Error Interrupt Mask */
+#define SERCOM_SPI_INTFLAG_ERROR(value)       (SERCOM_SPI_INTFLAG_ERROR_Msk & (_UINT8_(value) << SERCOM_SPI_INTFLAG_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_SPI_INTFLAG register */
+#define SERCOM_SPI_INTFLAG_Msk                _UINT8_(0x8F)                                        /* (SERCOM_SPI_INTFLAG) Register Mask  */
+
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART Interrupt Flag Status and Clear -------- */
+#define SERCOM_USART_INTFLAG_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_USART_INTFLAG) USART Interrupt Flag Status and Clear  Reset Value */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos          _UINT8_(0)                                           /* (SERCOM_USART_INTFLAG) Data Register Empty Interrupt Position */
+#define SERCOM_USART_INTFLAG_DRE_Msk          (_UINT8_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos)       /* (SERCOM_USART_INTFLAG) Data Register Empty Interrupt Mask */
+#define SERCOM_USART_INTFLAG_DRE(value)       (SERCOM_USART_INTFLAG_DRE_Msk & (_UINT8_(value) << SERCOM_USART_INTFLAG_DRE_Pos)) /* Assignment of value for DRE in the SERCOM_USART_INTFLAG register */
+#define SERCOM_USART_INTFLAG_TXC_Pos          _UINT8_(1)                                           /* (SERCOM_USART_INTFLAG) Transmit Complete Interrupt Position */
+#define SERCOM_USART_INTFLAG_TXC_Msk          (_UINT8_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos)       /* (SERCOM_USART_INTFLAG) Transmit Complete Interrupt Mask */
+#define SERCOM_USART_INTFLAG_TXC(value)       (SERCOM_USART_INTFLAG_TXC_Msk & (_UINT8_(value) << SERCOM_USART_INTFLAG_TXC_Pos)) /* Assignment of value for TXC in the SERCOM_USART_INTFLAG register */
+#define SERCOM_USART_INTFLAG_RXC_Pos          _UINT8_(2)                                           /* (SERCOM_USART_INTFLAG) Receive Complete Interrupt Position */
+#define SERCOM_USART_INTFLAG_RXC_Msk          (_UINT8_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos)       /* (SERCOM_USART_INTFLAG) Receive Complete Interrupt Mask */
+#define SERCOM_USART_INTFLAG_RXC(value)       (SERCOM_USART_INTFLAG_RXC_Msk & (_UINT8_(value) << SERCOM_USART_INTFLAG_RXC_Pos)) /* Assignment of value for RXC in the SERCOM_USART_INTFLAG register */
+#define SERCOM_USART_INTFLAG_RXS_Pos          _UINT8_(3)                                           /* (SERCOM_USART_INTFLAG) Receive Start Interrupt Position */
+#define SERCOM_USART_INTFLAG_RXS_Msk          (_UINT8_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos)       /* (SERCOM_USART_INTFLAG) Receive Start Interrupt Mask */
+#define SERCOM_USART_INTFLAG_RXS(value)       (SERCOM_USART_INTFLAG_RXS_Msk & (_UINT8_(value) << SERCOM_USART_INTFLAG_RXS_Pos)) /* Assignment of value for RXS in the SERCOM_USART_INTFLAG register */
+#define SERCOM_USART_INTFLAG_CTSIC_Pos        _UINT8_(4)                                           /* (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt Position */
+#define SERCOM_USART_INTFLAG_CTSIC_Msk        (_UINT8_(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos)     /* (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt Mask */
+#define SERCOM_USART_INTFLAG_CTSIC(value)     (SERCOM_USART_INTFLAG_CTSIC_Msk & (_UINT8_(value) << SERCOM_USART_INTFLAG_CTSIC_Pos)) /* Assignment of value for CTSIC in the SERCOM_USART_INTFLAG register */
+#define SERCOM_USART_INTFLAG_RXBRK_Pos        _UINT8_(5)                                           /* (SERCOM_USART_INTFLAG) Break Received Interrupt Position */
+#define SERCOM_USART_INTFLAG_RXBRK_Msk        (_UINT8_(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos)     /* (SERCOM_USART_INTFLAG) Break Received Interrupt Mask */
+#define SERCOM_USART_INTFLAG_RXBRK(value)     (SERCOM_USART_INTFLAG_RXBRK_Msk & (_UINT8_(value) << SERCOM_USART_INTFLAG_RXBRK_Pos)) /* Assignment of value for RXBRK in the SERCOM_USART_INTFLAG register */
+#define SERCOM_USART_INTFLAG_ERROR_Pos        _UINT8_(7)                                           /* (SERCOM_USART_INTFLAG) Combined Error Interrupt Position */
+#define SERCOM_USART_INTFLAG_ERROR_Msk        (_UINT8_(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos)     /* (SERCOM_USART_INTFLAG) Combined Error Interrupt Mask */
+#define SERCOM_USART_INTFLAG_ERROR(value)     (SERCOM_USART_INTFLAG_ERROR_Msk & (_UINT8_(value) << SERCOM_USART_INTFLAG_ERROR_Pos)) /* Assignment of value for ERROR in the SERCOM_USART_INTFLAG register */
+#define SERCOM_USART_INTFLAG_Msk              _UINT8_(0xBF)                                        /* (SERCOM_USART_INTFLAG) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM Status -------- */
+#define SERCOM_I2CM_STATUS_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_I2CM_STATUS) I2CM Status  Reset Value */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos         _UINT16_(0)                                          /* (SERCOM_I2CM_STATUS) Bus Error Position */
+#define SERCOM_I2CM_STATUS_BUSERR_Msk         (_UINT16_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)     /* (SERCOM_I2CM_STATUS) Bus Error Mask */
+#define SERCOM_I2CM_STATUS_BUSERR(value)      (SERCOM_I2CM_STATUS_BUSERR_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_BUSERR_Pos)) /* Assignment of value for BUSERR in the SERCOM_I2CM_STATUS register */
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos        _UINT16_(1)                                          /* (SERCOM_I2CM_STATUS) Arbitration Lost Position */
+#define SERCOM_I2CM_STATUS_ARBLOST_Msk        (_UINT16_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)    /* (SERCOM_I2CM_STATUS) Arbitration Lost Mask */
+#define SERCOM_I2CM_STATUS_ARBLOST(value)     (SERCOM_I2CM_STATUS_ARBLOST_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_ARBLOST_Pos)) /* Assignment of value for ARBLOST in the SERCOM_I2CM_STATUS register */
+#define SERCOM_I2CM_STATUS_RXNACK_Pos         _UINT16_(2)                                          /* (SERCOM_I2CM_STATUS) Received Not Acknowledge Position */
+#define SERCOM_I2CM_STATUS_RXNACK_Msk         (_UINT16_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)     /* (SERCOM_I2CM_STATUS) Received Not Acknowledge Mask */
+#define SERCOM_I2CM_STATUS_RXNACK(value)      (SERCOM_I2CM_STATUS_RXNACK_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_RXNACK_Pos)) /* Assignment of value for RXNACK in the SERCOM_I2CM_STATUS register */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos       _UINT16_(4)                                          /* (SERCOM_I2CM_STATUS) Bus State Position */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk       (_UINT16_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)   /* (SERCOM_I2CM_STATUS) Bus State Mask */
+#define SERCOM_I2CM_STATUS_BUSSTATE(value)    (SERCOM_I2CM_STATUS_BUSSTATE_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)) /* Assignment of value for BUSSTATE in the SERCOM_I2CM_STATUS register */
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos        _UINT16_(6)                                          /* (SERCOM_I2CM_STATUS) SCL Low Timeout Position */
+#define SERCOM_I2CM_STATUS_LOWTOUT_Msk        (_UINT16_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)    /* (SERCOM_I2CM_STATUS) SCL Low Timeout Mask */
+#define SERCOM_I2CM_STATUS_LOWTOUT(value)     (SERCOM_I2CM_STATUS_LOWTOUT_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)) /* Assignment of value for LOWTOUT in the SERCOM_I2CM_STATUS register */
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos        _UINT16_(7)                                          /* (SERCOM_I2CM_STATUS) Clock Hold Position */
+#define SERCOM_I2CM_STATUS_CLKHOLD_Msk        (_UINT16_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)    /* (SERCOM_I2CM_STATUS) Clock Hold Mask */
+#define SERCOM_I2CM_STATUS_CLKHOLD(value)     (SERCOM_I2CM_STATUS_CLKHOLD_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)) /* Assignment of value for CLKHOLD in the SERCOM_I2CM_STATUS register */
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos       _UINT16_(8)                                          /* (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout Position */
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Msk       (_UINT16_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)   /* (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout Mask */
+#define SERCOM_I2CM_STATUS_MEXTTOUT(value)    (SERCOM_I2CM_STATUS_MEXTTOUT_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)) /* Assignment of value for MEXTTOUT in the SERCOM_I2CM_STATUS register */
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos       _UINT16_(9)                                          /* (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout Position */
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Msk       (_UINT16_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)   /* (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout Mask */
+#define SERCOM_I2CM_STATUS_SEXTTOUT(value)    (SERCOM_I2CM_STATUS_SEXTTOUT_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)) /* Assignment of value for SEXTTOUT in the SERCOM_I2CM_STATUS register */
+#define SERCOM_I2CM_STATUS_LENERR_Pos         _UINT16_(10)                                         /* (SERCOM_I2CM_STATUS) Length Error Position */
+#define SERCOM_I2CM_STATUS_LENERR_Msk         (_UINT16_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)     /* (SERCOM_I2CM_STATUS) Length Error Mask */
+#define SERCOM_I2CM_STATUS_LENERR(value)      (SERCOM_I2CM_STATUS_LENERR_Msk & (_UINT16_(value) << SERCOM_I2CM_STATUS_LENERR_Pos)) /* Assignment of value for LENERR in the SERCOM_I2CM_STATUS register */
+#define SERCOM_I2CM_STATUS_Msk                _UINT16_(0x07F7)                                     /* (SERCOM_I2CM_STATUS) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS Status -------- */
+#define SERCOM_I2CS_STATUS_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_I2CS_STATUS) I2CS Status  Reset Value */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos         _UINT16_(0)                                          /* (SERCOM_I2CS_STATUS) Bus Error Position */
+#define SERCOM_I2CS_STATUS_BUSERR_Msk         (_UINT16_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)     /* (SERCOM_I2CS_STATUS) Bus Error Mask */
+#define SERCOM_I2CS_STATUS_BUSERR(value)      (SERCOM_I2CS_STATUS_BUSERR_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_BUSERR_Pos)) /* Assignment of value for BUSERR in the SERCOM_I2CS_STATUS register */
+#define SERCOM_I2CS_STATUS_COLL_Pos           _UINT16_(1)                                          /* (SERCOM_I2CS_STATUS) Transmit Collision Position */
+#define SERCOM_I2CS_STATUS_COLL_Msk           (_UINT16_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)       /* (SERCOM_I2CS_STATUS) Transmit Collision Mask */
+#define SERCOM_I2CS_STATUS_COLL(value)        (SERCOM_I2CS_STATUS_COLL_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_COLL_Pos)) /* Assignment of value for COLL in the SERCOM_I2CS_STATUS register */
+#define SERCOM_I2CS_STATUS_RXNACK_Pos         _UINT16_(2)                                          /* (SERCOM_I2CS_STATUS) Received Not Acknowledge Position */
+#define SERCOM_I2CS_STATUS_RXNACK_Msk         (_UINT16_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)     /* (SERCOM_I2CS_STATUS) Received Not Acknowledge Mask */
+#define SERCOM_I2CS_STATUS_RXNACK(value)      (SERCOM_I2CS_STATUS_RXNACK_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_RXNACK_Pos)) /* Assignment of value for RXNACK in the SERCOM_I2CS_STATUS register */
+#define SERCOM_I2CS_STATUS_DIR_Pos            _UINT16_(3)                                          /* (SERCOM_I2CS_STATUS) Read/Write Direction Position */
+#define SERCOM_I2CS_STATUS_DIR_Msk            (_UINT16_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)        /* (SERCOM_I2CS_STATUS) Read/Write Direction Mask */
+#define SERCOM_I2CS_STATUS_DIR(value)         (SERCOM_I2CS_STATUS_DIR_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_DIR_Pos)) /* Assignment of value for DIR in the SERCOM_I2CS_STATUS register */
+#define SERCOM_I2CS_STATUS_SR_Pos             _UINT16_(4)                                          /* (SERCOM_I2CS_STATUS) Repeated Start Position */
+#define SERCOM_I2CS_STATUS_SR_Msk             (_UINT16_(0x1) << SERCOM_I2CS_STATUS_SR_Pos)         /* (SERCOM_I2CS_STATUS) Repeated Start Mask */
+#define SERCOM_I2CS_STATUS_SR(value)          (SERCOM_I2CS_STATUS_SR_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_SR_Pos)) /* Assignment of value for SR in the SERCOM_I2CS_STATUS register */
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos        _UINT16_(6)                                          /* (SERCOM_I2CS_STATUS) SCL Low Timeout Position */
+#define SERCOM_I2CS_STATUS_LOWTOUT_Msk        (_UINT16_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)    /* (SERCOM_I2CS_STATUS) SCL Low Timeout Mask */
+#define SERCOM_I2CS_STATUS_LOWTOUT(value)     (SERCOM_I2CS_STATUS_LOWTOUT_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)) /* Assignment of value for LOWTOUT in the SERCOM_I2CS_STATUS register */
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos        _UINT16_(7)                                          /* (SERCOM_I2CS_STATUS) Clock Hold Position */
+#define SERCOM_I2CS_STATUS_CLKHOLD_Msk        (_UINT16_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)    /* (SERCOM_I2CS_STATUS) Clock Hold Mask */
+#define SERCOM_I2CS_STATUS_CLKHOLD(value)     (SERCOM_I2CS_STATUS_CLKHOLD_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)) /* Assignment of value for CLKHOLD in the SERCOM_I2CS_STATUS register */
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos       _UINT16_(9)                                          /* (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout Position */
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Msk       (_UINT16_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)   /* (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout Mask */
+#define SERCOM_I2CS_STATUS_SEXTTOUT(value)    (SERCOM_I2CS_STATUS_SEXTTOUT_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)) /* Assignment of value for SEXTTOUT in the SERCOM_I2CS_STATUS register */
+#define SERCOM_I2CS_STATUS_HS_Pos             _UINT16_(10)                                         /* (SERCOM_I2CS_STATUS) High Speed Position */
+#define SERCOM_I2CS_STATUS_HS_Msk             (_UINT16_(0x1) << SERCOM_I2CS_STATUS_HS_Pos)         /* (SERCOM_I2CS_STATUS) High Speed Mask */
+#define SERCOM_I2CS_STATUS_HS(value)          (SERCOM_I2CS_STATUS_HS_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_HS_Pos)) /* Assignment of value for HS in the SERCOM_I2CS_STATUS register */
+#define SERCOM_I2CS_STATUS_LENERR_Pos         _UINT16_(11)                                         /* (SERCOM_I2CS_STATUS) Transaction Length Error Position */
+#define SERCOM_I2CS_STATUS_LENERR_Msk         (_UINT16_(0x1) << SERCOM_I2CS_STATUS_LENERR_Pos)     /* (SERCOM_I2CS_STATUS) Transaction Length Error Mask */
+#define SERCOM_I2CS_STATUS_LENERR(value)      (SERCOM_I2CS_STATUS_LENERR_Msk & (_UINT16_(value) << SERCOM_I2CS_STATUS_LENERR_Pos)) /* Assignment of value for LENERR in the SERCOM_I2CS_STATUS register */
+#define SERCOM_I2CS_STATUS_Msk                _UINT16_(0x0EDF)                                     /* (SERCOM_I2CS_STATUS) Register Mask  */
+
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI Status -------- */
+#define SERCOM_SPI_STATUS_RESETVALUE          _UINT16_(0x00)                                       /*  (SERCOM_SPI_STATUS) SPI Status  Reset Value */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos          _UINT16_(2)                                          /* (SERCOM_SPI_STATUS) Buffer Overflow Position */
+#define SERCOM_SPI_STATUS_BUFOVF_Msk          (_UINT16_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos)      /* (SERCOM_SPI_STATUS) Buffer Overflow Mask */
+#define SERCOM_SPI_STATUS_BUFOVF(value)       (SERCOM_SPI_STATUS_BUFOVF_Msk & (_UINT16_(value) << SERCOM_SPI_STATUS_BUFOVF_Pos)) /* Assignment of value for BUFOVF in the SERCOM_SPI_STATUS register */
+#define SERCOM_SPI_STATUS_TUR_Pos             _UINT16_(3)                                          /* (SERCOM_SPI_STATUS) Frame Transmit Underrun Position */
+#define SERCOM_SPI_STATUS_TUR_Msk             (_UINT16_(0x1) << SERCOM_SPI_STATUS_TUR_Pos)         /* (SERCOM_SPI_STATUS) Frame Transmit Underrun Mask */
+#define SERCOM_SPI_STATUS_TUR(value)          (SERCOM_SPI_STATUS_TUR_Msk & (_UINT16_(value) << SERCOM_SPI_STATUS_TUR_Pos)) /* Assignment of value for TUR in the SERCOM_SPI_STATUS register */
+#define SERCOM_SPI_STATUS_LENERR_Pos          _UINT16_(11)                                         /* (SERCOM_SPI_STATUS) Transaction Length Error Position */
+#define SERCOM_SPI_STATUS_LENERR_Msk          (_UINT16_(0x1) << SERCOM_SPI_STATUS_LENERR_Pos)      /* (SERCOM_SPI_STATUS) Transaction Length Error Mask */
+#define SERCOM_SPI_STATUS_LENERR(value)       (SERCOM_SPI_STATUS_LENERR_Msk & (_UINT16_(value) << SERCOM_SPI_STATUS_LENERR_Pos)) /* Assignment of value for LENERR in the SERCOM_SPI_STATUS register */
+#define SERCOM_SPI_STATUS_Msk                 _UINT16_(0x080C)                                     /* (SERCOM_SPI_STATUS) Register Mask  */
+
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART Status -------- */
+#define SERCOM_USART_STATUS_RESETVALUE        _UINT16_(0x00)                                       /*  (SERCOM_USART_STATUS) USART Status  Reset Value */
+
+#define SERCOM_USART_STATUS_PERR_Pos          _UINT16_(0)                                          /* (SERCOM_USART_STATUS) Parity Error Position */
+#define SERCOM_USART_STATUS_PERR_Msk          (_UINT16_(0x1) << SERCOM_USART_STATUS_PERR_Pos)      /* (SERCOM_USART_STATUS) Parity Error Mask */
+#define SERCOM_USART_STATUS_PERR(value)       (SERCOM_USART_STATUS_PERR_Msk & (_UINT16_(value) << SERCOM_USART_STATUS_PERR_Pos)) /* Assignment of value for PERR in the SERCOM_USART_STATUS register */
+#define SERCOM_USART_STATUS_FERR_Pos          _UINT16_(1)                                          /* (SERCOM_USART_STATUS) Frame Error Position */
+#define SERCOM_USART_STATUS_FERR_Msk          (_UINT16_(0x1) << SERCOM_USART_STATUS_FERR_Pos)      /* (SERCOM_USART_STATUS) Frame Error Mask */
+#define SERCOM_USART_STATUS_FERR(value)       (SERCOM_USART_STATUS_FERR_Msk & (_UINT16_(value) << SERCOM_USART_STATUS_FERR_Pos)) /* Assignment of value for FERR in the SERCOM_USART_STATUS register */
+#define SERCOM_USART_STATUS_BUFOVF_Pos        _UINT16_(2)                                          /* (SERCOM_USART_STATUS) Buffer Overflow Position */
+#define SERCOM_USART_STATUS_BUFOVF_Msk        (_UINT16_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos)    /* (SERCOM_USART_STATUS) Buffer Overflow Mask */
+#define SERCOM_USART_STATUS_BUFOVF(value)     (SERCOM_USART_STATUS_BUFOVF_Msk & (_UINT16_(value) << SERCOM_USART_STATUS_BUFOVF_Pos)) /* Assignment of value for BUFOVF in the SERCOM_USART_STATUS register */
+#define SERCOM_USART_STATUS_CTS_Pos           _UINT16_(3)                                          /* (SERCOM_USART_STATUS) Clear To Send Position */
+#define SERCOM_USART_STATUS_CTS_Msk           (_UINT16_(0x1) << SERCOM_USART_STATUS_CTS_Pos)       /* (SERCOM_USART_STATUS) Clear To Send Mask */
+#define SERCOM_USART_STATUS_CTS(value)        (SERCOM_USART_STATUS_CTS_Msk & (_UINT16_(value) << SERCOM_USART_STATUS_CTS_Pos)) /* Assignment of value for CTS in the SERCOM_USART_STATUS register */
+#define SERCOM_USART_STATUS_ISF_Pos           _UINT16_(4)                                          /* (SERCOM_USART_STATUS) Inconsistent Sync Field Position */
+#define SERCOM_USART_STATUS_ISF_Msk           (_UINT16_(0x1) << SERCOM_USART_STATUS_ISF_Pos)       /* (SERCOM_USART_STATUS) Inconsistent Sync Field Mask */
+#define SERCOM_USART_STATUS_ISF(value)        (SERCOM_USART_STATUS_ISF_Msk & (_UINT16_(value) << SERCOM_USART_STATUS_ISF_Pos)) /* Assignment of value for ISF in the SERCOM_USART_STATUS register */
+#define SERCOM_USART_STATUS_COLL_Pos          _UINT16_(5)                                          /* (SERCOM_USART_STATUS) Collision Detected Position */
+#define SERCOM_USART_STATUS_COLL_Msk          (_UINT16_(0x1) << SERCOM_USART_STATUS_COLL_Pos)      /* (SERCOM_USART_STATUS) Collision Detected Mask */
+#define SERCOM_USART_STATUS_COLL(value)       (SERCOM_USART_STATUS_COLL_Msk & (_UINT16_(value) << SERCOM_USART_STATUS_COLL_Pos)) /* Assignment of value for COLL in the SERCOM_USART_STATUS register */
+#define SERCOM_USART_STATUS_TXE_Pos           _UINT16_(6)                                          /* (SERCOM_USART_STATUS) Transmitter Empty Position */
+#define SERCOM_USART_STATUS_TXE_Msk           (_UINT16_(0x1) << SERCOM_USART_STATUS_TXE_Pos)       /* (SERCOM_USART_STATUS) Transmitter Empty Mask */
+#define SERCOM_USART_STATUS_TXE(value)        (SERCOM_USART_STATUS_TXE_Msk & (_UINT16_(value) << SERCOM_USART_STATUS_TXE_Pos)) /* Assignment of value for TXE in the SERCOM_USART_STATUS register */
+#define SERCOM_USART_STATUS_ITER_Pos          _UINT16_(7)                                          /* (SERCOM_USART_STATUS) Maximum Number of Repetitions Reached Position */
+#define SERCOM_USART_STATUS_ITER_Msk          (_UINT16_(0x1) << SERCOM_USART_STATUS_ITER_Pos)      /* (SERCOM_USART_STATUS) Maximum Number of Repetitions Reached Mask */
+#define SERCOM_USART_STATUS_ITER(value)       (SERCOM_USART_STATUS_ITER_Msk & (_UINT16_(value) << SERCOM_USART_STATUS_ITER_Pos)) /* Assignment of value for ITER in the SERCOM_USART_STATUS register */
+#define SERCOM_USART_STATUS_Msk               _UINT16_(0x00FF)                                     /* (SERCOM_USART_STATUS) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) I2CM Synchronization Busy -------- */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE       _UINT32_(0x00)                                       /*  (SERCOM_I2CM_SYNCBUSY) I2CM Synchronization Busy  Reset Value */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos        _UINT32_(0)                                          /* (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Msk        (_UINT32_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)    /* (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define SERCOM_I2CM_SYNCBUSY_SWRST(value)     (SERCOM_I2CM_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the SERCOM_I2CM_SYNCBUSY register */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos       _UINT32_(1)                                          /* (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Msk       (_UINT32_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)   /* (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE(value)    (SERCOM_I2CM_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the SERCOM_I2CM_SYNCBUSY register */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos        _UINT32_(2)                                          /* (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy Position */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Msk        (_UINT32_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)    /* (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy Mask */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP(value)     (SERCOM_I2CM_SYNCBUSY_SYSOP_Msk & (_UINT32_(value) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)) /* Assignment of value for SYSOP in the SERCOM_I2CM_SYNCBUSY register */
+#define SERCOM_I2CM_SYNCBUSY_LENGTH_Pos       _UINT32_(4)                                          /* (SERCOM_I2CM_SYNCBUSY) Length Synchronization Busy Position */
+#define SERCOM_I2CM_SYNCBUSY_LENGTH_Msk       (_UINT32_(0x1) << SERCOM_I2CM_SYNCBUSY_LENGTH_Pos)   /* (SERCOM_I2CM_SYNCBUSY) Length Synchronization Busy Mask */
+#define SERCOM_I2CM_SYNCBUSY_LENGTH(value)    (SERCOM_I2CM_SYNCBUSY_LENGTH_Msk & (_UINT32_(value) << SERCOM_I2CM_SYNCBUSY_LENGTH_Pos)) /* Assignment of value for LENGTH in the SERCOM_I2CM_SYNCBUSY register */
+#define SERCOM_I2CM_SYNCBUSY_Msk              _UINT32_(0x00000017)                                 /* (SERCOM_I2CM_SYNCBUSY) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) I2CS Synchronization Busy -------- */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE       _UINT32_(0x00)                                       /*  (SERCOM_I2CS_SYNCBUSY) I2CS Synchronization Busy  Reset Value */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos        _UINT32_(0)                                          /* (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Msk        (_UINT32_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)    /* (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define SERCOM_I2CS_SYNCBUSY_SWRST(value)     (SERCOM_I2CS_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the SERCOM_I2CS_SYNCBUSY register */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos       _UINT32_(1)                                          /* (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Msk       (_UINT32_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)   /* (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE(value)    (SERCOM_I2CS_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the SERCOM_I2CS_SYNCBUSY register */
+#define SERCOM_I2CS_SYNCBUSY_SYSOP_Pos        _UINT32_(2)                                          /* (SERCOM_I2CS_SYNCBUSY) System Operation Synchronization Busy Position */
+#define SERCOM_I2CS_SYNCBUSY_SYSOP_Msk        (_UINT32_(0x1) << SERCOM_I2CS_SYNCBUSY_SYSOP_Pos)    /* (SERCOM_I2CS_SYNCBUSY) System Operation Synchronization Busy Mask */
+#define SERCOM_I2CS_SYNCBUSY_SYSOP(value)     (SERCOM_I2CS_SYNCBUSY_SYSOP_Msk & (_UINT32_(value) << SERCOM_I2CS_SYNCBUSY_SYSOP_Pos)) /* Assignment of value for SYSOP in the SERCOM_I2CS_SYNCBUSY register */
+#define SERCOM_I2CS_SYNCBUSY_LENGTH_Pos       _UINT32_(4)                                          /* (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy Position */
+#define SERCOM_I2CS_SYNCBUSY_LENGTH_Msk       (_UINT32_(0x1) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)   /* (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy Mask */
+#define SERCOM_I2CS_SYNCBUSY_LENGTH(value)    (SERCOM_I2CS_SYNCBUSY_LENGTH_Msk & (_UINT32_(value) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)) /* Assignment of value for LENGTH in the SERCOM_I2CS_SYNCBUSY register */
+#define SERCOM_I2CS_SYNCBUSY_Msk              _UINT32_(0x00000017)                                 /* (SERCOM_I2CS_SYNCBUSY) Register Mask  */
+
+
+/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) SPI Synchronization Busy -------- */
+#define SERCOM_SPI_SYNCBUSY_RESETVALUE        _UINT32_(0x00)                                       /*  (SERCOM_SPI_SYNCBUSY) SPI Synchronization Busy  Reset Value */
+
+#define SERCOM_SPI_SYNCBUSY_SWRST_Pos         _UINT32_(0)                                          /* (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define SERCOM_SPI_SYNCBUSY_SWRST_Msk         (_UINT32_(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos)     /* (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define SERCOM_SPI_SYNCBUSY_SWRST(value)      (SERCOM_SPI_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << SERCOM_SPI_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the SERCOM_SPI_SYNCBUSY register */
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos        _UINT32_(1)                                          /* (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Msk        (_UINT32_(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)    /* (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
+#define SERCOM_SPI_SYNCBUSY_ENABLE(value)     (SERCOM_SPI_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the SERCOM_SPI_SYNCBUSY register */
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos         _UINT32_(2)                                          /* (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy Position */
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Msk         (_UINT32_(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)     /* (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy Mask */
+#define SERCOM_SPI_SYNCBUSY_CTRLB(value)      (SERCOM_SPI_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)) /* Assignment of value for CTRLB in the SERCOM_SPI_SYNCBUSY register */
+#define SERCOM_SPI_SYNCBUSY_LENGTH_Pos        _UINT32_(4)                                          /* (SERCOM_SPI_SYNCBUSY) LENGTH Synchronization Busy Position */
+#define SERCOM_SPI_SYNCBUSY_LENGTH_Msk        (_UINT32_(0x1) << SERCOM_SPI_SYNCBUSY_LENGTH_Pos)    /* (SERCOM_SPI_SYNCBUSY) LENGTH Synchronization Busy Mask */
+#define SERCOM_SPI_SYNCBUSY_LENGTH(value)     (SERCOM_SPI_SYNCBUSY_LENGTH_Msk & (_UINT32_(value) << SERCOM_SPI_SYNCBUSY_LENGTH_Pos)) /* Assignment of value for LENGTH in the SERCOM_SPI_SYNCBUSY register */
+#define SERCOM_SPI_SYNCBUSY_Msk               _UINT32_(0x00000017)                                 /* (SERCOM_SPI_SYNCBUSY) Register Mask  */
+
+
+/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) USART Synchronization Busy -------- */
+#define SERCOM_USART_SYNCBUSY_RESETVALUE      _UINT32_(0x00)                                       /*  (SERCOM_USART_SYNCBUSY) USART Synchronization Busy  Reset Value */
+
+#define SERCOM_USART_SYNCBUSY_SWRST_Pos       _UINT32_(0)                                          /* (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define SERCOM_USART_SYNCBUSY_SWRST_Msk       (_UINT32_(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos)   /* (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define SERCOM_USART_SYNCBUSY_SWRST(value)    (SERCOM_USART_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << SERCOM_USART_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the SERCOM_USART_SYNCBUSY register */
+#define SERCOM_USART_SYNCBUSY_ENABLE_Pos      _UINT32_(1)                                          /* (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
+#define SERCOM_USART_SYNCBUSY_ENABLE_Msk      (_UINT32_(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos)  /* (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
+#define SERCOM_USART_SYNCBUSY_ENABLE(value)   (SERCOM_USART_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << SERCOM_USART_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the SERCOM_USART_SYNCBUSY register */
+#define SERCOM_USART_SYNCBUSY_CTRLB_Pos       _UINT32_(2)                                          /* (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy Position */
+#define SERCOM_USART_SYNCBUSY_CTRLB_Msk       (_UINT32_(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos)   /* (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy Mask */
+#define SERCOM_USART_SYNCBUSY_CTRLB(value)    (SERCOM_USART_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << SERCOM_USART_SYNCBUSY_CTRLB_Pos)) /* Assignment of value for CTRLB in the SERCOM_USART_SYNCBUSY register */
+#define SERCOM_USART_SYNCBUSY_RXERRCNT_Pos    _UINT32_(3)                                          /* (SERCOM_USART_SYNCBUSY) RXERRCNT Synchronization Busy Position */
+#define SERCOM_USART_SYNCBUSY_RXERRCNT_Msk    (_UINT32_(0x1) << SERCOM_USART_SYNCBUSY_RXERRCNT_Pos) /* (SERCOM_USART_SYNCBUSY) RXERRCNT Synchronization Busy Mask */
+#define SERCOM_USART_SYNCBUSY_RXERRCNT(value) (SERCOM_USART_SYNCBUSY_RXERRCNT_Msk & (_UINT32_(value) << SERCOM_USART_SYNCBUSY_RXERRCNT_Pos)) /* Assignment of value for RXERRCNT in the SERCOM_USART_SYNCBUSY register */
+#define SERCOM_USART_SYNCBUSY_LENGTH_Pos      _UINT32_(4)                                          /* (SERCOM_USART_SYNCBUSY) LENGTH Synchronization Busy Position */
+#define SERCOM_USART_SYNCBUSY_LENGTH_Msk      (_UINT32_(0x1) << SERCOM_USART_SYNCBUSY_LENGTH_Pos)  /* (SERCOM_USART_SYNCBUSY) LENGTH Synchronization Busy Mask */
+#define SERCOM_USART_SYNCBUSY_LENGTH(value)   (SERCOM_USART_SYNCBUSY_LENGTH_Msk & (_UINT32_(value) << SERCOM_USART_SYNCBUSY_LENGTH_Pos)) /* Assignment of value for LENGTH in the SERCOM_USART_SYNCBUSY register */
+#define SERCOM_USART_SYNCBUSY_Msk             _UINT32_(0x0000001F)                                 /* (SERCOM_USART_SYNCBUSY) Register Mask  */
+
+
+/* -------- SERCOM_USART_RXERRCNT : (SERCOM Offset: 0x20) ( R/ 8) USART Receive Error Count -------- */
+#define SERCOM_USART_RXERRCNT_RESETVALUE      _UINT8_(0x00)                                        /*  (SERCOM_USART_RXERRCNT) USART Receive Error Count  Reset Value */
+
+#define SERCOM_USART_RXERRCNT_Msk             _UINT8_(0x00)                                        /* (SERCOM_USART_RXERRCNT) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) I2CS Length -------- */
+#define SERCOM_I2CS_LENGTH_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_I2CS_LENGTH) I2CS Length  Reset Value */
+
+#define SERCOM_I2CS_LENGTH_LEN_Pos            _UINT16_(0)                                          /* (SERCOM_I2CS_LENGTH) Data Length Position */
+#define SERCOM_I2CS_LENGTH_LEN_Msk            (_UINT16_(0xFF) << SERCOM_I2CS_LENGTH_LEN_Pos)       /* (SERCOM_I2CS_LENGTH) Data Length Mask */
+#define SERCOM_I2CS_LENGTH_LEN(value)         (SERCOM_I2CS_LENGTH_LEN_Msk & (_UINT16_(value) << SERCOM_I2CS_LENGTH_LEN_Pos)) /* Assignment of value for LEN in the SERCOM_I2CS_LENGTH register */
+#define SERCOM_I2CS_LENGTH_LENEN_Pos          _UINT16_(8)                                          /* (SERCOM_I2CS_LENGTH) Data Length Enable Position */
+#define SERCOM_I2CS_LENGTH_LENEN_Msk          (_UINT16_(0x1) << SERCOM_I2CS_LENGTH_LENEN_Pos)      /* (SERCOM_I2CS_LENGTH) Data Length Enable Mask */
+#define SERCOM_I2CS_LENGTH_LENEN(value)       (SERCOM_I2CS_LENGTH_LENEN_Msk & (_UINT16_(value) << SERCOM_I2CS_LENGTH_LENEN_Pos)) /* Assignment of value for LENEN in the SERCOM_I2CS_LENGTH register */
+#define SERCOM_I2CS_LENGTH_Msk                _UINT16_(0x01FF)                                     /* (SERCOM_I2CS_LENGTH) Register Mask  */
+
+
+/* -------- SERCOM_SPI_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPI Length -------- */
+#define SERCOM_SPI_LENGTH_RESETVALUE          _UINT16_(0x00)                                       /*  (SERCOM_SPI_LENGTH) SPI Length  Reset Value */
+
+#define SERCOM_SPI_LENGTH_LEN_Pos             _UINT16_(0)                                          /* (SERCOM_SPI_LENGTH) Data Length Position */
+#define SERCOM_SPI_LENGTH_LEN_Msk             (_UINT16_(0xFF) << SERCOM_SPI_LENGTH_LEN_Pos)        /* (SERCOM_SPI_LENGTH) Data Length Mask */
+#define SERCOM_SPI_LENGTH_LEN(value)          (SERCOM_SPI_LENGTH_LEN_Msk & (_UINT16_(value) << SERCOM_SPI_LENGTH_LEN_Pos)) /* Assignment of value for LEN in the SERCOM_SPI_LENGTH register */
+#define SERCOM_SPI_LENGTH_LENEN_Pos           _UINT16_(8)                                          /* (SERCOM_SPI_LENGTH) Data Length Enable Position */
+#define SERCOM_SPI_LENGTH_LENEN_Msk           (_UINT16_(0x1) << SERCOM_SPI_LENGTH_LENEN_Pos)       /* (SERCOM_SPI_LENGTH) Data Length Enable Mask */
+#define SERCOM_SPI_LENGTH_LENEN(value)        (SERCOM_SPI_LENGTH_LENEN_Msk & (_UINT16_(value) << SERCOM_SPI_LENGTH_LENEN_Pos)) /* Assignment of value for LENEN in the SERCOM_SPI_LENGTH register */
+#define SERCOM_SPI_LENGTH_Msk                 _UINT16_(0x01FF)                                     /* (SERCOM_SPI_LENGTH) Register Mask  */
+
+
+/* -------- SERCOM_USART_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART Length -------- */
+#define SERCOM_USART_LENGTH_RESETVALUE        _UINT16_(0x00)                                       /*  (SERCOM_USART_LENGTH) USART Length  Reset Value */
+
+#define SERCOM_USART_LENGTH_LEN_Pos           _UINT16_(0)                                          /* (SERCOM_USART_LENGTH) Data Length Position */
+#define SERCOM_USART_LENGTH_LEN_Msk           (_UINT16_(0xFF) << SERCOM_USART_LENGTH_LEN_Pos)      /* (SERCOM_USART_LENGTH) Data Length Mask */
+#define SERCOM_USART_LENGTH_LEN(value)        (SERCOM_USART_LENGTH_LEN_Msk & (_UINT16_(value) << SERCOM_USART_LENGTH_LEN_Pos)) /* Assignment of value for LEN in the SERCOM_USART_LENGTH register */
+#define SERCOM_USART_LENGTH_LENEN_Pos         _UINT16_(8)                                          /* (SERCOM_USART_LENGTH) Data Length Enable Position */
+#define SERCOM_USART_LENGTH_LENEN_Msk         (_UINT16_(0x3) << SERCOM_USART_LENGTH_LENEN_Pos)     /* (SERCOM_USART_LENGTH) Data Length Enable Mask */
+#define SERCOM_USART_LENGTH_LENEN(value)      (SERCOM_USART_LENGTH_LENEN_Msk & (_UINT16_(value) << SERCOM_USART_LENGTH_LENEN_Pos)) /* Assignment of value for LENEN in the SERCOM_USART_LENGTH register */
+#define   SERCOM_USART_LENGTH_LENEN_DISABLE_Val _UINT16_(0x0)                                        /* (SERCOM_USART_LENGTH) Length counter is disabled  */
+#define   SERCOM_USART_LENGTH_LENEN_TX_Val    _UINT16_(0x1)                                        /* (SERCOM_USART_LENGTH) Length counter is enabled for transmit  */
+#define   SERCOM_USART_LENGTH_LENEN_RX_Val    _UINT16_(0x2)                                        /* (SERCOM_USART_LENGTH) Length counter is enabled for receive  */
+#define SERCOM_USART_LENGTH_LENEN_DISABLE     (SERCOM_USART_LENGTH_LENEN_DISABLE_Val << SERCOM_USART_LENGTH_LENEN_Pos) /* (SERCOM_USART_LENGTH) Length counter is disabled Position */
+#define SERCOM_USART_LENGTH_LENEN_TX          (SERCOM_USART_LENGTH_LENEN_TX_Val << SERCOM_USART_LENGTH_LENEN_Pos) /* (SERCOM_USART_LENGTH) Length counter is enabled for transmit Position */
+#define SERCOM_USART_LENGTH_LENEN_RX          (SERCOM_USART_LENGTH_LENEN_RX_Val << SERCOM_USART_LENGTH_LENEN_Pos) /* (SERCOM_USART_LENGTH) Length counter is enabled for receive Position */
+#define SERCOM_USART_LENGTH_Msk               _UINT16_(0x03FF)                                     /* (SERCOM_USART_LENGTH) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM Address -------- */
+#define SERCOM_I2CM_ADDR_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_I2CM_ADDR) I2CM Address  Reset Value */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos             _UINT32_(0)                                          /* (SERCOM_I2CM_ADDR) Address Value Position */
+#define SERCOM_I2CM_ADDR_ADDR_Msk             (_UINT32_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)       /* (SERCOM_I2CM_ADDR) Address Value Mask */
+#define SERCOM_I2CM_ADDR_ADDR(value)          (SERCOM_I2CM_ADDR_ADDR_Msk & (_UINT32_(value) << SERCOM_I2CM_ADDR_ADDR_Pos)) /* Assignment of value for ADDR in the SERCOM_I2CM_ADDR register */
+#define SERCOM_I2CM_ADDR_LENEN_Pos            _UINT32_(13)                                         /* (SERCOM_I2CM_ADDR) Length Enable Position */
+#define SERCOM_I2CM_ADDR_LENEN_Msk            (_UINT32_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)        /* (SERCOM_I2CM_ADDR) Length Enable Mask */
+#define SERCOM_I2CM_ADDR_LENEN(value)         (SERCOM_I2CM_ADDR_LENEN_Msk & (_UINT32_(value) << SERCOM_I2CM_ADDR_LENEN_Pos)) /* Assignment of value for LENEN in the SERCOM_I2CM_ADDR register */
+#define SERCOM_I2CM_ADDR_HS_Pos               _UINT32_(14)                                         /* (SERCOM_I2CM_ADDR) High Speed Mode Position */
+#define SERCOM_I2CM_ADDR_HS_Msk               (_UINT32_(0x1) << SERCOM_I2CM_ADDR_HS_Pos)           /* (SERCOM_I2CM_ADDR) High Speed Mode Mask */
+#define SERCOM_I2CM_ADDR_HS(value)            (SERCOM_I2CM_ADDR_HS_Msk & (_UINT32_(value) << SERCOM_I2CM_ADDR_HS_Pos)) /* Assignment of value for HS in the SERCOM_I2CM_ADDR register */
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos         _UINT32_(15)                                         /* (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable Position */
+#define SERCOM_I2CM_ADDR_TENBITEN_Msk         (_UINT32_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)     /* (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable Mask */
+#define SERCOM_I2CM_ADDR_TENBITEN(value)      (SERCOM_I2CM_ADDR_TENBITEN_Msk & (_UINT32_(value) << SERCOM_I2CM_ADDR_TENBITEN_Pos)) /* Assignment of value for TENBITEN in the SERCOM_I2CM_ADDR register */
+#define SERCOM_I2CM_ADDR_LEN_Pos              _UINT32_(16)                                         /* (SERCOM_I2CM_ADDR) Length Position */
+#define SERCOM_I2CM_ADDR_LEN_Msk              (_UINT32_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)         /* (SERCOM_I2CM_ADDR) Length Mask */
+#define SERCOM_I2CM_ADDR_LEN(value)           (SERCOM_I2CM_ADDR_LEN_Msk & (_UINT32_(value) << SERCOM_I2CM_ADDR_LEN_Pos)) /* Assignment of value for LEN in the SERCOM_I2CM_ADDR register */
+#define SERCOM_I2CM_ADDR_Msk                  _UINT32_(0x00FFE7FF)                                 /* (SERCOM_I2CM_ADDR) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS Address -------- */
+#define SERCOM_I2CS_ADDR_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_I2CS_ADDR) I2CS Address  Reset Value */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos           _UINT32_(0)                                          /* (SERCOM_I2CS_ADDR) General Call Address Enable Position */
+#define SERCOM_I2CS_ADDR_GENCEN_Msk           (_UINT32_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)       /* (SERCOM_I2CS_ADDR) General Call Address Enable Mask */
+#define SERCOM_I2CS_ADDR_GENCEN(value)        (SERCOM_I2CS_ADDR_GENCEN_Msk & (_UINT32_(value) << SERCOM_I2CS_ADDR_GENCEN_Pos)) /* Assignment of value for GENCEN in the SERCOM_I2CS_ADDR register */
+#define SERCOM_I2CS_ADDR_ADDR_Pos             _UINT32_(1)                                          /* (SERCOM_I2CS_ADDR) Address Value Position */
+#define SERCOM_I2CS_ADDR_ADDR_Msk             (_UINT32_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)       /* (SERCOM_I2CS_ADDR) Address Value Mask */
+#define SERCOM_I2CS_ADDR_ADDR(value)          (SERCOM_I2CS_ADDR_ADDR_Msk & (_UINT32_(value) << SERCOM_I2CS_ADDR_ADDR_Pos)) /* Assignment of value for ADDR in the SERCOM_I2CS_ADDR register */
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos         _UINT32_(15)                                         /* (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable Position */
+#define SERCOM_I2CS_ADDR_TENBITEN_Msk         (_UINT32_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)     /* (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable Mask */
+#define SERCOM_I2CS_ADDR_TENBITEN(value)      (SERCOM_I2CS_ADDR_TENBITEN_Msk & (_UINT32_(value) << SERCOM_I2CS_ADDR_TENBITEN_Pos)) /* Assignment of value for TENBITEN in the SERCOM_I2CS_ADDR register */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos         _UINT32_(17)                                         /* (SERCOM_I2CS_ADDR) Address Mask Position */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk         (_UINT32_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)   /* (SERCOM_I2CS_ADDR) Address Mask Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK(value)      (SERCOM_I2CS_ADDR_ADDRMASK_Msk & (_UINT32_(value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)) /* Assignment of value for ADDRMASK in the SERCOM_I2CS_ADDR register */
+#define SERCOM_I2CS_ADDR_Msk                  _UINT32_(0x07FE87FF)                                 /* (SERCOM_I2CS_ADDR) Register Mask  */
+
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI Address -------- */
+#define SERCOM_SPI_ADDR_RESETVALUE            _UINT32_(0x00)                                       /*  (SERCOM_SPI_ADDR) SPI Address  Reset Value */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos              _UINT32_(0)                                          /* (SERCOM_SPI_ADDR) Address Value Position */
+#define SERCOM_SPI_ADDR_ADDR_Msk              (_UINT32_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos)         /* (SERCOM_SPI_ADDR) Address Value Mask */
+#define SERCOM_SPI_ADDR_ADDR(value)           (SERCOM_SPI_ADDR_ADDR_Msk & (_UINT32_(value) << SERCOM_SPI_ADDR_ADDR_Pos)) /* Assignment of value for ADDR in the SERCOM_SPI_ADDR register */
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos          _UINT32_(16)                                         /* (SERCOM_SPI_ADDR) Address Mask Position */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk          (_UINT32_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos)     /* (SERCOM_SPI_ADDR) Address Mask Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK(value)       (SERCOM_SPI_ADDR_ADDRMASK_Msk & (_UINT32_(value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)) /* Assignment of value for ADDRMASK in the SERCOM_SPI_ADDR register */
+#define SERCOM_SPI_ADDR_Msk                   _UINT32_(0x00FF00FF)                                 /* (SERCOM_SPI_ADDR) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CM Data -------- */
+#define SERCOM_I2CM_DATA_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_I2CM_DATA) I2CM Data  Reset Value */
+
+#define SERCOM_I2CM_DATA_DATA_Pos             _UINT32_(0)                                          /* (SERCOM_I2CM_DATA) Data Value Position */
+#define SERCOM_I2CM_DATA_DATA_Msk             (_UINT32_(0xFFFFFFFF) << SERCOM_I2CM_DATA_DATA_Pos)  /* (SERCOM_I2CM_DATA) Data Value Mask */
+#define SERCOM_I2CM_DATA_DATA(value)          (SERCOM_I2CM_DATA_DATA_Msk & (_UINT32_(value) << SERCOM_I2CM_DATA_DATA_Pos)) /* Assignment of value for DATA in the SERCOM_I2CM_DATA register */
+#define SERCOM_I2CM_DATA_Msk                  _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_I2CM_DATA) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CS Data -------- */
+#define SERCOM_I2CS_DATA_RESETVALUE           _UINT32_(0x00)                                       /*  (SERCOM_I2CS_DATA) I2CS Data  Reset Value */
+
+#define SERCOM_I2CS_DATA_DATA_Pos             _UINT32_(0)                                          /* (SERCOM_I2CS_DATA) Data Value Position */
+#define SERCOM_I2CS_DATA_DATA_Msk             (_UINT32_(0xFFFFFFFF) << SERCOM_I2CS_DATA_DATA_Pos)  /* (SERCOM_I2CS_DATA) Data Value Mask */
+#define SERCOM_I2CS_DATA_DATA(value)          (SERCOM_I2CS_DATA_DATA_Msk & (_UINT32_(value) << SERCOM_I2CS_DATA_DATA_Pos)) /* Assignment of value for DATA in the SERCOM_I2CS_DATA register */
+#define SERCOM_I2CS_DATA_Msk                  _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_I2CS_DATA) Register Mask  */
+
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI Data -------- */
+#define SERCOM_SPI_DATA_RESETVALUE            _UINT32_(0x00)                                       /*  (SERCOM_SPI_DATA) SPI Data  Reset Value */
+
+#define SERCOM_SPI_DATA_DATA_Pos              _UINT32_(0)                                          /* (SERCOM_SPI_DATA) Data Value Position */
+#define SERCOM_SPI_DATA_DATA_Msk              (_UINT32_(0xFFFFFFFF) << SERCOM_SPI_DATA_DATA_Pos)   /* (SERCOM_SPI_DATA) Data Value Mask */
+#define SERCOM_SPI_DATA_DATA(value)           (SERCOM_SPI_DATA_DATA_Msk & (_UINT32_(value) << SERCOM_SPI_DATA_DATA_Pos)) /* Assignment of value for DATA in the SERCOM_SPI_DATA register */
+#define SERCOM_SPI_DATA_Msk                   _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_SPI_DATA) Register Mask  */
+
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 32) USART Data -------- */
+#define SERCOM_USART_DATA_RESETVALUE          _UINT32_(0x00)                                       /*  (SERCOM_USART_DATA) USART Data  Reset Value */
+
+#define SERCOM_USART_DATA_DATA_Pos            _UINT32_(0)                                          /* (SERCOM_USART_DATA) Data Value Position */
+#define SERCOM_USART_DATA_DATA_Msk            (_UINT32_(0xFFFFFFFF) << SERCOM_USART_DATA_DATA_Pos) /* (SERCOM_USART_DATA) Data Value Mask */
+#define SERCOM_USART_DATA_DATA(value)         (SERCOM_USART_DATA_DATA_Msk & (_UINT32_(value) << SERCOM_USART_DATA_DATA_Pos)) /* Assignment of value for DATA in the SERCOM_USART_DATA register */
+#define SERCOM_USART_DATA_Msk                 _UINT32_(0xFFFFFFFF)                                 /* (SERCOM_USART_DATA) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM Debug Control -------- */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE        _UINT8_(0x00)                                        /*  (SERCOM_I2CM_DBGCTRL) I2CM Debug Control  Reset Value */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos       _UINT8_(0)                                           /* (SERCOM_I2CM_DBGCTRL) Debug Mode Position */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Msk       (_UINT8_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)    /* (SERCOM_I2CM_DBGCTRL) Debug Mode Mask */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP(value)    (SERCOM_I2CM_DBGCTRL_DBGSTOP_Msk & (_UINT8_(value) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)) /* Assignment of value for DBGSTOP in the SERCOM_I2CM_DBGCTRL register */
+#define SERCOM_I2CM_DBGCTRL_Msk               _UINT8_(0x01)                                        /* (SERCOM_I2CM_DBGCTRL) Register Mask  */
+
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI Debug Control -------- */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE         _UINT8_(0x00)                                        /*  (SERCOM_SPI_DBGCTRL) SPI Debug Control  Reset Value */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos        _UINT8_(0)                                           /* (SERCOM_SPI_DBGCTRL) Debug Mode Position */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Msk        (_UINT8_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)     /* (SERCOM_SPI_DBGCTRL) Debug Mode Mask */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP(value)     (SERCOM_SPI_DBGCTRL_DBGSTOP_Msk & (_UINT8_(value) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)) /* Assignment of value for DBGSTOP in the SERCOM_SPI_DBGCTRL register */
+#define SERCOM_SPI_DBGCTRL_Msk                _UINT8_(0x01)                                        /* (SERCOM_SPI_DBGCTRL) Register Mask  */
+
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART Debug Control -------- */
+#define SERCOM_USART_DBGCTRL_RESETVALUE       _UINT8_(0x00)                                        /*  (SERCOM_USART_DBGCTRL) USART Debug Control  Reset Value */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos      _UINT8_(0)                                           /* (SERCOM_USART_DBGCTRL) Debug Mode Position */
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Msk      (_UINT8_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)   /* (SERCOM_USART_DBGCTRL) Debug Mode Mask */
+#define SERCOM_USART_DBGCTRL_DBGSTOP(value)   (SERCOM_USART_DBGCTRL_DBGSTOP_Msk & (_UINT8_(value) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)) /* Assignment of value for DBGSTOP in the SERCOM_USART_DBGCTRL register */
+#define SERCOM_USART_DBGCTRL_Msk              _UINT8_(0x01)                                        /* (SERCOM_USART_DBGCTRL) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_FIFOSPACE : (SERCOM Offset: 0x34) ( R/ 16) I2CM FIFO Space -------- */
+#define SERCOM_I2CM_FIFOSPACE_RESETVALUE      _UINT16_(0x00)                                       /*  (SERCOM_I2CM_FIFOSPACE) I2CM FIFO Space  Reset Value */
+
+#define SERCOM_I2CM_FIFOSPACE_TXSPACE_Pos     _UINT16_(0)                                          /* (SERCOM_I2CM_FIFOSPACE) Tx FIFO Empty Space Position */
+#define SERCOM_I2CM_FIFOSPACE_TXSPACE_Msk     (_UINT16_(0x1F) << SERCOM_I2CM_FIFOSPACE_TXSPACE_Pos) /* (SERCOM_I2CM_FIFOSPACE) Tx FIFO Empty Space Mask */
+#define SERCOM_I2CM_FIFOSPACE_TXSPACE(value)  (SERCOM_I2CM_FIFOSPACE_TXSPACE_Msk & (_UINT16_(value) << SERCOM_I2CM_FIFOSPACE_TXSPACE_Pos)) /* Assignment of value for TXSPACE in the SERCOM_I2CM_FIFOSPACE register */
+#define SERCOM_I2CM_FIFOSPACE_RXSPACE_Pos     _UINT16_(8)                                          /* (SERCOM_I2CM_FIFOSPACE) Rx FIFO Filled Space Position */
+#define SERCOM_I2CM_FIFOSPACE_RXSPACE_Msk     (_UINT16_(0x1F) << SERCOM_I2CM_FIFOSPACE_RXSPACE_Pos) /* (SERCOM_I2CM_FIFOSPACE) Rx FIFO Filled Space Mask */
+#define SERCOM_I2CM_FIFOSPACE_RXSPACE(value)  (SERCOM_I2CM_FIFOSPACE_RXSPACE_Msk & (_UINT16_(value) << SERCOM_I2CM_FIFOSPACE_RXSPACE_Pos)) /* Assignment of value for RXSPACE in the SERCOM_I2CM_FIFOSPACE register */
+#define SERCOM_I2CM_FIFOSPACE_Msk             _UINT16_(0x1F1F)                                     /* (SERCOM_I2CM_FIFOSPACE) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_FIFOSPACE : (SERCOM Offset: 0x34) ( R/ 16) I2CS FIFO Space -------- */
+#define SERCOM_I2CS_FIFOSPACE_RESETVALUE      _UINT16_(0x00)                                       /*  (SERCOM_I2CS_FIFOSPACE) I2CS FIFO Space  Reset Value */
+
+#define SERCOM_I2CS_FIFOSPACE_TXSPACE_Pos     _UINT16_(0)                                          /* (SERCOM_I2CS_FIFOSPACE) Tx FIFO Empty Space Position */
+#define SERCOM_I2CS_FIFOSPACE_TXSPACE_Msk     (_UINT16_(0x1F) << SERCOM_I2CS_FIFOSPACE_TXSPACE_Pos) /* (SERCOM_I2CS_FIFOSPACE) Tx FIFO Empty Space Mask */
+#define SERCOM_I2CS_FIFOSPACE_TXSPACE(value)  (SERCOM_I2CS_FIFOSPACE_TXSPACE_Msk & (_UINT16_(value) << SERCOM_I2CS_FIFOSPACE_TXSPACE_Pos)) /* Assignment of value for TXSPACE in the SERCOM_I2CS_FIFOSPACE register */
+#define SERCOM_I2CS_FIFOSPACE_RXSPACE_Pos     _UINT16_(8)                                          /* (SERCOM_I2CS_FIFOSPACE) Rx FIFO Filled Space Position */
+#define SERCOM_I2CS_FIFOSPACE_RXSPACE_Msk     (_UINT16_(0x1F) << SERCOM_I2CS_FIFOSPACE_RXSPACE_Pos) /* (SERCOM_I2CS_FIFOSPACE) Rx FIFO Filled Space Mask */
+#define SERCOM_I2CS_FIFOSPACE_RXSPACE(value)  (SERCOM_I2CS_FIFOSPACE_RXSPACE_Msk & (_UINT16_(value) << SERCOM_I2CS_FIFOSPACE_RXSPACE_Pos)) /* Assignment of value for RXSPACE in the SERCOM_I2CS_FIFOSPACE register */
+#define SERCOM_I2CS_FIFOSPACE_Msk             _UINT16_(0x1F1F)                                     /* (SERCOM_I2CS_FIFOSPACE) Register Mask  */
+
+
+/* -------- SERCOM_SPI_FIFOSPACE : (SERCOM Offset: 0x34) ( R/ 16) SPI FIFO Space -------- */
+#define SERCOM_SPI_FIFOSPACE_RESETVALUE       _UINT16_(0x00)                                       /*  (SERCOM_SPI_FIFOSPACE) SPI FIFO Space  Reset Value */
+
+#define SERCOM_SPI_FIFOSPACE_TXSPACE_Pos      _UINT16_(0)                                          /* (SERCOM_SPI_FIFOSPACE) Tx FIFO Empty Space Position */
+#define SERCOM_SPI_FIFOSPACE_TXSPACE_Msk      (_UINT16_(0x1F) << SERCOM_SPI_FIFOSPACE_TXSPACE_Pos) /* (SERCOM_SPI_FIFOSPACE) Tx FIFO Empty Space Mask */
+#define SERCOM_SPI_FIFOSPACE_TXSPACE(value)   (SERCOM_SPI_FIFOSPACE_TXSPACE_Msk & (_UINT16_(value) << SERCOM_SPI_FIFOSPACE_TXSPACE_Pos)) /* Assignment of value for TXSPACE in the SERCOM_SPI_FIFOSPACE register */
+#define SERCOM_SPI_FIFOSPACE_RXSPACE_Pos      _UINT16_(8)                                          /* (SERCOM_SPI_FIFOSPACE) Rx FIFO Filled Space Position */
+#define SERCOM_SPI_FIFOSPACE_RXSPACE_Msk      (_UINT16_(0x1F) << SERCOM_SPI_FIFOSPACE_RXSPACE_Pos) /* (SERCOM_SPI_FIFOSPACE) Rx FIFO Filled Space Mask */
+#define SERCOM_SPI_FIFOSPACE_RXSPACE(value)   (SERCOM_SPI_FIFOSPACE_RXSPACE_Msk & (_UINT16_(value) << SERCOM_SPI_FIFOSPACE_RXSPACE_Pos)) /* Assignment of value for RXSPACE in the SERCOM_SPI_FIFOSPACE register */
+#define SERCOM_SPI_FIFOSPACE_Msk              _UINT16_(0x1F1F)                                     /* (SERCOM_SPI_FIFOSPACE) Register Mask  */
+
+
+/* -------- SERCOM_USART_FIFOSPACE : (SERCOM Offset: 0x34) ( R/ 16) USART FIFO Space -------- */
+#define SERCOM_USART_FIFOSPACE_RESETVALUE     _UINT16_(0x00)                                       /*  (SERCOM_USART_FIFOSPACE) USART FIFO Space  Reset Value */
+
+#define SERCOM_USART_FIFOSPACE_TXSPACE_Pos    _UINT16_(0)                                          /* (SERCOM_USART_FIFOSPACE) Tx FIFO Empty Space Position */
+#define SERCOM_USART_FIFOSPACE_TXSPACE_Msk    (_UINT16_(0x1F) << SERCOM_USART_FIFOSPACE_TXSPACE_Pos) /* (SERCOM_USART_FIFOSPACE) Tx FIFO Empty Space Mask */
+#define SERCOM_USART_FIFOSPACE_TXSPACE(value) (SERCOM_USART_FIFOSPACE_TXSPACE_Msk & (_UINT16_(value) << SERCOM_USART_FIFOSPACE_TXSPACE_Pos)) /* Assignment of value for TXSPACE in the SERCOM_USART_FIFOSPACE register */
+#define SERCOM_USART_FIFOSPACE_RXSPACE_Pos    _UINT16_(8)                                          /* (SERCOM_USART_FIFOSPACE) Rx FIFO Filled Space Position */
+#define SERCOM_USART_FIFOSPACE_RXSPACE_Msk    (_UINT16_(0x1F) << SERCOM_USART_FIFOSPACE_RXSPACE_Pos) /* (SERCOM_USART_FIFOSPACE) Rx FIFO Filled Space Mask */
+#define SERCOM_USART_FIFOSPACE_RXSPACE(value) (SERCOM_USART_FIFOSPACE_RXSPACE_Msk & (_UINT16_(value) << SERCOM_USART_FIFOSPACE_RXSPACE_Pos)) /* Assignment of value for RXSPACE in the SERCOM_USART_FIFOSPACE register */
+#define SERCOM_USART_FIFOSPACE_Msk            _UINT16_(0x1F1F)                                     /* (SERCOM_USART_FIFOSPACE) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_FIFOPTR : (SERCOM Offset: 0x36) (R/W 16) I2CM FIFO CPU Pointers -------- */
+#define SERCOM_I2CM_FIFOPTR_RESETVALUE        _UINT16_(0x00)                                       /*  (SERCOM_I2CM_FIFOPTR) I2CM FIFO CPU Pointers  Reset Value */
+
+#define SERCOM_I2CM_FIFOPTR_CPUWRPTR_Pos      _UINT16_(0)                                          /* (SERCOM_I2CM_FIFOPTR) CPU FIFO Write Pointer Position */
+#define SERCOM_I2CM_FIFOPTR_CPUWRPTR_Msk      (_UINT16_(0xF) << SERCOM_I2CM_FIFOPTR_CPUWRPTR_Pos)  /* (SERCOM_I2CM_FIFOPTR) CPU FIFO Write Pointer Mask */
+#define SERCOM_I2CM_FIFOPTR_CPUWRPTR(value)   (SERCOM_I2CM_FIFOPTR_CPUWRPTR_Msk & (_UINT16_(value) << SERCOM_I2CM_FIFOPTR_CPUWRPTR_Pos)) /* Assignment of value for CPUWRPTR in the SERCOM_I2CM_FIFOPTR register */
+#define SERCOM_I2CM_FIFOPTR_CPURDPTR_Pos      _UINT16_(8)                                          /* (SERCOM_I2CM_FIFOPTR) CPU FIFO Read Pointer Position */
+#define SERCOM_I2CM_FIFOPTR_CPURDPTR_Msk      (_UINT16_(0xF) << SERCOM_I2CM_FIFOPTR_CPURDPTR_Pos)  /* (SERCOM_I2CM_FIFOPTR) CPU FIFO Read Pointer Mask */
+#define SERCOM_I2CM_FIFOPTR_CPURDPTR(value)   (SERCOM_I2CM_FIFOPTR_CPURDPTR_Msk & (_UINT16_(value) << SERCOM_I2CM_FIFOPTR_CPURDPTR_Pos)) /* Assignment of value for CPURDPTR in the SERCOM_I2CM_FIFOPTR register */
+#define SERCOM_I2CM_FIFOPTR_Msk               _UINT16_(0x0F0F)                                     /* (SERCOM_I2CM_FIFOPTR) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_FIFOPTR : (SERCOM Offset: 0x36) (R/W 16) I2CS FIFO CPU Pointers -------- */
+#define SERCOM_I2CS_FIFOPTR_RESETVALUE        _UINT16_(0x00)                                       /*  (SERCOM_I2CS_FIFOPTR) I2CS FIFO CPU Pointers  Reset Value */
+
+#define SERCOM_I2CS_FIFOPTR_CPUWRPTR_Pos      _UINT16_(0)                                          /* (SERCOM_I2CS_FIFOPTR) CPU FIFO Write Pointer Position */
+#define SERCOM_I2CS_FIFOPTR_CPUWRPTR_Msk      (_UINT16_(0xF) << SERCOM_I2CS_FIFOPTR_CPUWRPTR_Pos)  /* (SERCOM_I2CS_FIFOPTR) CPU FIFO Write Pointer Mask */
+#define SERCOM_I2CS_FIFOPTR_CPUWRPTR(value)   (SERCOM_I2CS_FIFOPTR_CPUWRPTR_Msk & (_UINT16_(value) << SERCOM_I2CS_FIFOPTR_CPUWRPTR_Pos)) /* Assignment of value for CPUWRPTR in the SERCOM_I2CS_FIFOPTR register */
+#define SERCOM_I2CS_FIFOPTR_CPURDPTR_Pos      _UINT16_(8)                                          /* (SERCOM_I2CS_FIFOPTR) CPU FIFO Read Pointer Position */
+#define SERCOM_I2CS_FIFOPTR_CPURDPTR_Msk      (_UINT16_(0xF) << SERCOM_I2CS_FIFOPTR_CPURDPTR_Pos)  /* (SERCOM_I2CS_FIFOPTR) CPU FIFO Read Pointer Mask */
+#define SERCOM_I2CS_FIFOPTR_CPURDPTR(value)   (SERCOM_I2CS_FIFOPTR_CPURDPTR_Msk & (_UINT16_(value) << SERCOM_I2CS_FIFOPTR_CPURDPTR_Pos)) /* Assignment of value for CPURDPTR in the SERCOM_I2CS_FIFOPTR register */
+#define SERCOM_I2CS_FIFOPTR_Msk               _UINT16_(0x0F0F)                                     /* (SERCOM_I2CS_FIFOPTR) Register Mask  */
+
+
+/* -------- SERCOM_SPI_FIFOPTR : (SERCOM Offset: 0x36) (R/W 16) SPI FIFO CPU Pointers -------- */
+#define SERCOM_SPI_FIFOPTR_RESETVALUE         _UINT16_(0x00)                                       /*  (SERCOM_SPI_FIFOPTR) SPI FIFO CPU Pointers  Reset Value */
+
+#define SERCOM_SPI_FIFOPTR_CPUWRPTR_Pos       _UINT16_(0)                                          /* (SERCOM_SPI_FIFOPTR) CPU FIFO Write Pointer Position */
+#define SERCOM_SPI_FIFOPTR_CPUWRPTR_Msk       (_UINT16_(0xF) << SERCOM_SPI_FIFOPTR_CPUWRPTR_Pos)   /* (SERCOM_SPI_FIFOPTR) CPU FIFO Write Pointer Mask */
+#define SERCOM_SPI_FIFOPTR_CPUWRPTR(value)    (SERCOM_SPI_FIFOPTR_CPUWRPTR_Msk & (_UINT16_(value) << SERCOM_SPI_FIFOPTR_CPUWRPTR_Pos)) /* Assignment of value for CPUWRPTR in the SERCOM_SPI_FIFOPTR register */
+#define SERCOM_SPI_FIFOPTR_CPURDPTR_Pos       _UINT16_(8)                                          /* (SERCOM_SPI_FIFOPTR) CPU FIFO Read Pointer Position */
+#define SERCOM_SPI_FIFOPTR_CPURDPTR_Msk       (_UINT16_(0xF) << SERCOM_SPI_FIFOPTR_CPURDPTR_Pos)   /* (SERCOM_SPI_FIFOPTR) CPU FIFO Read Pointer Mask */
+#define SERCOM_SPI_FIFOPTR_CPURDPTR(value)    (SERCOM_SPI_FIFOPTR_CPURDPTR_Msk & (_UINT16_(value) << SERCOM_SPI_FIFOPTR_CPURDPTR_Pos)) /* Assignment of value for CPURDPTR in the SERCOM_SPI_FIFOPTR register */
+#define SERCOM_SPI_FIFOPTR_Msk                _UINT16_(0x0F0F)                                     /* (SERCOM_SPI_FIFOPTR) Register Mask  */
+
+
+/* -------- SERCOM_USART_FIFOPTR : (SERCOM Offset: 0x36) (R/W 16) USART FIFO CPU Pointers -------- */
+#define SERCOM_USART_FIFOPTR_RESETVALUE       _UINT16_(0x00)                                       /*  (SERCOM_USART_FIFOPTR) USART FIFO CPU Pointers  Reset Value */
+
+#define SERCOM_USART_FIFOPTR_CPUWRPTR_Pos     _UINT16_(0)                                          /* (SERCOM_USART_FIFOPTR) CPU FIFO Write Pointer Position */
+#define SERCOM_USART_FIFOPTR_CPUWRPTR_Msk     (_UINT16_(0xF) << SERCOM_USART_FIFOPTR_CPUWRPTR_Pos) /* (SERCOM_USART_FIFOPTR) CPU FIFO Write Pointer Mask */
+#define SERCOM_USART_FIFOPTR_CPUWRPTR(value)  (SERCOM_USART_FIFOPTR_CPUWRPTR_Msk & (_UINT16_(value) << SERCOM_USART_FIFOPTR_CPUWRPTR_Pos)) /* Assignment of value for CPUWRPTR in the SERCOM_USART_FIFOPTR register */
+#define SERCOM_USART_FIFOPTR_CPURDPTR_Pos     _UINT16_(8)                                          /* (SERCOM_USART_FIFOPTR) CPU FIFO Read Pointer Position */
+#define SERCOM_USART_FIFOPTR_CPURDPTR_Msk     (_UINT16_(0xF) << SERCOM_USART_FIFOPTR_CPURDPTR_Pos) /* (SERCOM_USART_FIFOPTR) CPU FIFO Read Pointer Mask */
+#define SERCOM_USART_FIFOPTR_CPURDPTR(value)  (SERCOM_USART_FIFOPTR_CPURDPTR_Msk & (_UINT16_(value) << SERCOM_USART_FIFOPTR_CPURDPTR_Pos)) /* Assignment of value for CPURDPTR in the SERCOM_USART_FIFOPTR register */
+#define SERCOM_USART_FIFOPTR_Msk              _UINT16_(0x0F0F)                                     /* (SERCOM_USART_FIFOPTR) Register Mask  */
+
+
+/* SERCOM register offsets definitions */
+#define SERCOM_I2CM_CTRLA_REG_OFST     _UINT32_(0x00)      /* (SERCOM_I2CM_CTRLA) I2CM Control A Offset */
+#define SERCOM_I2CS_CTRLA_REG_OFST     _UINT32_(0x00)      /* (SERCOM_I2CS_CTRLA) I2CS Control A Offset */
+#define SERCOM_SPI_CTRLA_REG_OFST      _UINT32_(0x00)      /* (SERCOM_SPI_CTRLA) SPI Control A Offset */
+#define SERCOM_USART_CTRLA_REG_OFST    _UINT32_(0x00)      /* (SERCOM_USART_CTRLA) USART Control A Offset */
+#define SERCOM_I2CM_CTRLB_REG_OFST     _UINT32_(0x04)      /* (SERCOM_I2CM_CTRLB) I2CM Control B Offset */
+#define SERCOM_I2CS_CTRLB_REG_OFST     _UINT32_(0x04)      /* (SERCOM_I2CS_CTRLB) I2CS Control B Offset */
+#define SERCOM_SPI_CTRLB_REG_OFST      _UINT32_(0x04)      /* (SERCOM_SPI_CTRLB) SPI Control B Offset */
+#define SERCOM_USART_CTRLB_REG_OFST    _UINT32_(0x04)      /* (SERCOM_USART_CTRLB) USART Control B Offset */
+#define SERCOM_I2CM_CTRLC_REG_OFST     _UINT32_(0x08)      /* (SERCOM_I2CM_CTRLC) I2CM Control C Offset */
+#define SERCOM_I2CS_CTRLC_REG_OFST     _UINT32_(0x08)      /* (SERCOM_I2CS_CTRLC) I2CS Control C Offset */
+#define SERCOM_SPI_CTRLC_REG_OFST      _UINT32_(0x08)      /* (SERCOM_SPI_CTRLC) SPI Control C Offset */
+#define SERCOM_USART_CTRLC_REG_OFST    _UINT32_(0x08)      /* (SERCOM_USART_CTRLC) USART Control C Offset */
+#define SERCOM_I2CM_BAUD_REG_OFST      _UINT32_(0x0C)      /* (SERCOM_I2CM_BAUD) I2CM Baud Rate Offset */
+#define SERCOM_SPI_BAUD_REG_OFST       _UINT32_(0x0C)      /* (SERCOM_SPI_BAUD) SPI Baud Rate Offset */
+#define SERCOM_USART_BAUD_REG_OFST     _UINT32_(0x0C)      /* (SERCOM_USART_BAUD) USART Baud Rate Offset */
+#define SERCOM_USART_RXPL_REG_OFST     _UINT32_(0x0E)      /* (SERCOM_USART_RXPL) USART Receive Pulse Length Offset */
+#define SERCOM_I2CM_INTENCLR_REG_OFST  _UINT32_(0x14)      /* (SERCOM_I2CM_INTENCLR) I2CM Interrupt Enable Clear Offset */
+#define SERCOM_I2CS_INTENCLR_REG_OFST  _UINT32_(0x14)      /* (SERCOM_I2CS_INTENCLR) I2CS Interrupt Enable Clear Offset */
+#define SERCOM_SPI_INTENCLR_REG_OFST   _UINT32_(0x14)      /* (SERCOM_SPI_INTENCLR) SPI Interrupt Enable Clear Offset */
+#define SERCOM_USART_INTENCLR_REG_OFST _UINT32_(0x14)      /* (SERCOM_USART_INTENCLR) USART Interrupt Enable Clear Offset */
+#define SERCOM_I2CM_INTENSET_REG_OFST  _UINT32_(0x16)      /* (SERCOM_I2CM_INTENSET) I2CM Interrupt Enable Set Offset */
+#define SERCOM_I2CS_INTENSET_REG_OFST  _UINT32_(0x16)      /* (SERCOM_I2CS_INTENSET) I2CS Interrupt Enable Set Offset */
+#define SERCOM_SPI_INTENSET_REG_OFST   _UINT32_(0x16)      /* (SERCOM_SPI_INTENSET) SPI Interrupt Enable Set Offset */
+#define SERCOM_USART_INTENSET_REG_OFST _UINT32_(0x16)      /* (SERCOM_USART_INTENSET) USART Interrupt Enable Set Offset */
+#define SERCOM_I2CM_INTFLAG_REG_OFST   _UINT32_(0x18)      /* (SERCOM_I2CM_INTFLAG) I2CM Interrupt Flag Status and Clear Offset */
+#define SERCOM_I2CS_INTFLAG_REG_OFST   _UINT32_(0x18)      /* (SERCOM_I2CS_INTFLAG) I2CS Interrupt Flag Status and Clear Offset */
+#define SERCOM_SPI_INTFLAG_REG_OFST    _UINT32_(0x18)      /* (SERCOM_SPI_INTFLAG) SPI Interrupt Flag Status and Clear Offset */
+#define SERCOM_USART_INTFLAG_REG_OFST  _UINT32_(0x18)      /* (SERCOM_USART_INTFLAG) USART Interrupt Flag Status and Clear Offset */
+#define SERCOM_I2CM_STATUS_REG_OFST    _UINT32_(0x1A)      /* (SERCOM_I2CM_STATUS) I2CM Status Offset */
+#define SERCOM_I2CS_STATUS_REG_OFST    _UINT32_(0x1A)      /* (SERCOM_I2CS_STATUS) I2CS Status Offset */
+#define SERCOM_SPI_STATUS_REG_OFST     _UINT32_(0x1A)      /* (SERCOM_SPI_STATUS) SPI Status Offset */
+#define SERCOM_USART_STATUS_REG_OFST   _UINT32_(0x1A)      /* (SERCOM_USART_STATUS) USART Status Offset */
+#define SERCOM_I2CM_SYNCBUSY_REG_OFST  _UINT32_(0x1C)      /* (SERCOM_I2CM_SYNCBUSY) I2CM Synchronization Busy Offset */
+#define SERCOM_I2CS_SYNCBUSY_REG_OFST  _UINT32_(0x1C)      /* (SERCOM_I2CS_SYNCBUSY) I2CS Synchronization Busy Offset */
+#define SERCOM_SPI_SYNCBUSY_REG_OFST   _UINT32_(0x1C)      /* (SERCOM_SPI_SYNCBUSY) SPI Synchronization Busy Offset */
+#define SERCOM_USART_SYNCBUSY_REG_OFST _UINT32_(0x1C)      /* (SERCOM_USART_SYNCBUSY) USART Synchronization Busy Offset */
+#define SERCOM_USART_RXERRCNT_REG_OFST _UINT32_(0x20)      /* (SERCOM_USART_RXERRCNT) USART Receive Error Count Offset */
+#define SERCOM_I2CS_LENGTH_REG_OFST    _UINT32_(0x22)      /* (SERCOM_I2CS_LENGTH) I2CS Length Offset */
+#define SERCOM_SPI_LENGTH_REG_OFST     _UINT32_(0x22)      /* (SERCOM_SPI_LENGTH) SPI Length Offset */
+#define SERCOM_USART_LENGTH_REG_OFST   _UINT32_(0x22)      /* (SERCOM_USART_LENGTH) USART Length Offset */
+#define SERCOM_I2CM_ADDR_REG_OFST      _UINT32_(0x24)      /* (SERCOM_I2CM_ADDR) I2CM Address Offset */
+#define SERCOM_I2CS_ADDR_REG_OFST      _UINT32_(0x24)      /* (SERCOM_I2CS_ADDR) I2CS Address Offset */
+#define SERCOM_SPI_ADDR_REG_OFST       _UINT32_(0x24)      /* (SERCOM_SPI_ADDR) SPI Address Offset */
+#define SERCOM_I2CM_DATA_REG_OFST      _UINT32_(0x28)      /* (SERCOM_I2CM_DATA) I2CM Data Offset */
+#define SERCOM_I2CS_DATA_REG_OFST      _UINT32_(0x28)      /* (SERCOM_I2CS_DATA) I2CS Data Offset */
+#define SERCOM_SPI_DATA_REG_OFST       _UINT32_(0x28)      /* (SERCOM_SPI_DATA) SPI Data Offset */
+#define SERCOM_USART_DATA_REG_OFST     _UINT32_(0x28)      /* (SERCOM_USART_DATA) USART Data Offset */
+#define SERCOM_I2CM_DBGCTRL_REG_OFST   _UINT32_(0x30)      /* (SERCOM_I2CM_DBGCTRL) I2CM Debug Control Offset */
+#define SERCOM_SPI_DBGCTRL_REG_OFST    _UINT32_(0x30)      /* (SERCOM_SPI_DBGCTRL) SPI Debug Control Offset */
+#define SERCOM_USART_DBGCTRL_REG_OFST  _UINT32_(0x30)      /* (SERCOM_USART_DBGCTRL) USART Debug Control Offset */
+#define SERCOM_I2CM_FIFOSPACE_REG_OFST _UINT32_(0x34)      /* (SERCOM_I2CM_FIFOSPACE) I2CM FIFO Space Offset */
+#define SERCOM_I2CS_FIFOSPACE_REG_OFST _UINT32_(0x34)      /* (SERCOM_I2CS_FIFOSPACE) I2CS FIFO Space Offset */
+#define SERCOM_SPI_FIFOSPACE_REG_OFST  _UINT32_(0x34)      /* (SERCOM_SPI_FIFOSPACE) SPI FIFO Space Offset */
+#define SERCOM_USART_FIFOSPACE_REG_OFST _UINT32_(0x34)      /* (SERCOM_USART_FIFOSPACE) USART FIFO Space Offset */
+#define SERCOM_I2CM_FIFOPTR_REG_OFST   _UINT32_(0x36)      /* (SERCOM_I2CM_FIFOPTR) I2CM FIFO CPU Pointers Offset */
+#define SERCOM_I2CS_FIFOPTR_REG_OFST   _UINT32_(0x36)      /* (SERCOM_I2CS_FIFOPTR) I2CS FIFO CPU Pointers Offset */
+#define SERCOM_SPI_FIFOPTR_REG_OFST    _UINT32_(0x36)      /* (SERCOM_SPI_FIFOPTR) SPI FIFO CPU Pointers Offset */
+#define SERCOM_USART_FIFOPTR_REG_OFST  _UINT32_(0x36)      /* (SERCOM_USART_FIFOPTR) USART FIFO CPU Pointers Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* SERCOM register API structure */
+typedef struct
+{  /* Serial Communication Interface */
+  __IO  uint32_t                       SERCOM_CTRLA;       /* Offset: 0x00 (R/W  32) I2CM Control A */
+  __IO  uint32_t                       SERCOM_CTRLB;       /* Offset: 0x04 (R/W  32) I2CM Control B */
+  __IO  uint32_t                       SERCOM_CTRLC;       /* Offset: 0x08 (R/W  32) I2CM Control C */
+  __IO  uint32_t                       SERCOM_BAUD;        /* Offset: 0x0C (R/W  32) I2CM Baud Rate */
+  __I   uint8_t                        Reserved1[0x04];
+  __IO  uint8_t                        SERCOM_INTENCLR;    /* Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        SERCOM_INTENSET;    /* Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        SERCOM_INTFLAG;     /* Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint16_t                       SERCOM_STATUS;      /* Offset: 0x1A (R/W  16) I2CM Status */
+  __I   uint32_t                       SERCOM_SYNCBUSY;    /* Offset: 0x1C (R/   32) I2CM Synchronization Busy */
+  __I   uint8_t                        Reserved5[0x04];
+  __IO  uint32_t                       SERCOM_ADDR;        /* Offset: 0x24 (R/W  32) I2CM Address */
+  __IO  uint32_t                       SERCOM_DATA;        /* Offset: 0x28 (R/W  32) I2CM Data */
+  __I   uint8_t                        Reserved6[0x04];
+  __IO  uint8_t                        SERCOM_DBGCTRL;     /* Offset: 0x30 (R/W  8) I2CM Debug Control */
+  __I   uint8_t                        Reserved7[0x03];
+  __I   uint16_t                       SERCOM_FIFOSPACE;   /* Offset: 0x34 (R/   16) I2CM FIFO Space */
+  __IO  uint16_t                       SERCOM_FIFOPTR;     /* Offset: 0x36 (R/W  16) I2CM FIFO CPU Pointers */
+} sercom_i2cm_registers_t;
+
+/* SERCOM register API structure */
+typedef struct
+{  /* Serial Communication Interface */
+  __IO  uint32_t                       SERCOM_CTRLA;       /* Offset: 0x00 (R/W  32) I2CS Control A */
+  __IO  uint32_t                       SERCOM_CTRLB;       /* Offset: 0x04 (R/W  32) I2CS Control B */
+  __IO  uint32_t                       SERCOM_CTRLC;       /* Offset: 0x08 (R/W  32) I2CS Control C */
+  __I   uint8_t                        Reserved1[0x08];
+  __IO  uint8_t                        SERCOM_INTENCLR;    /* Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        SERCOM_INTENSET;    /* Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        SERCOM_INTFLAG;     /* Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint16_t                       SERCOM_STATUS;      /* Offset: 0x1A (R/W  16) I2CS Status */
+  __I   uint32_t                       SERCOM_SYNCBUSY;    /* Offset: 0x1C (R/   32) I2CS Synchronization Busy */
+  __I   uint8_t                        Reserved5[0x02];
+  __IO  uint16_t                       SERCOM_LENGTH;      /* Offset: 0x22 (R/W  16) I2CS Length */
+  __IO  uint32_t                       SERCOM_ADDR;        /* Offset: 0x24 (R/W  32) I2CS Address */
+  __IO  uint32_t                       SERCOM_DATA;        /* Offset: 0x28 (R/W  32) I2CS Data */
+  __I   uint8_t                        Reserved6[0x08];
+  __I   uint16_t                       SERCOM_FIFOSPACE;   /* Offset: 0x34 (R/   16) I2CS FIFO Space */
+  __IO  uint16_t                       SERCOM_FIFOPTR;     /* Offset: 0x36 (R/W  16) I2CS FIFO CPU Pointers */
+} sercom_i2cs_registers_t;
+
+/* SERCOM register API structure */
+typedef struct
+{  /* Serial Communication Interface */
+  __IO  uint32_t                       SERCOM_CTRLA;       /* Offset: 0x00 (R/W  32) SPI Control A */
+  __IO  uint32_t                       SERCOM_CTRLB;       /* Offset: 0x04 (R/W  32) SPI Control B */
+  __IO  uint32_t                       SERCOM_CTRLC;       /* Offset: 0x08 (R/W  32) SPI Control C */
+  __IO  uint8_t                        SERCOM_BAUD;        /* Offset: 0x0C (R/W  8) SPI Baud Rate */
+  __I   uint8_t                        Reserved1[0x07];
+  __IO  uint8_t                        SERCOM_INTENCLR;    /* Offset: 0x14 (R/W  8) SPI Interrupt Enable Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        SERCOM_INTENSET;    /* Offset: 0x16 (R/W  8) SPI Interrupt Enable Set */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        SERCOM_INTFLAG;     /* Offset: 0x18 (R/W  8) SPI Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint16_t                       SERCOM_STATUS;      /* Offset: 0x1A (R/W  16) SPI Status */
+  __I   uint32_t                       SERCOM_SYNCBUSY;    /* Offset: 0x1C (R/   32) SPI Synchronization Busy */
+  __I   uint8_t                        Reserved5[0x02];
+  __IO  uint16_t                       SERCOM_LENGTH;      /* Offset: 0x22 (R/W  16) SPI Length */
+  __IO  uint32_t                       SERCOM_ADDR;        /* Offset: 0x24 (R/W  32) SPI Address */
+  __IO  uint32_t                       SERCOM_DATA;        /* Offset: 0x28 (R/W  32) SPI Data */
+  __I   uint8_t                        Reserved6[0x04];
+  __IO  uint8_t                        SERCOM_DBGCTRL;     /* Offset: 0x30 (R/W  8) SPI Debug Control */
+  __I   uint8_t                        Reserved7[0x03];
+  __I   uint16_t                       SERCOM_FIFOSPACE;   /* Offset: 0x34 (R/   16) SPI FIFO Space */
+  __IO  uint16_t                       SERCOM_FIFOPTR;     /* Offset: 0x36 (R/W  16) SPI FIFO CPU Pointers */
+} sercom_spi_registers_t;
+
+/* SERCOM register API structure */
+typedef struct
+{  /* Serial Communication Interface */
+  __IO  uint32_t                       SERCOM_CTRLA;       /* Offset: 0x00 (R/W  32) USART Control A */
+  __IO  uint32_t                       SERCOM_CTRLB;       /* Offset: 0x04 (R/W  32) USART Control B */
+  __IO  uint32_t                       SERCOM_CTRLC;       /* Offset: 0x08 (R/W  32) USART Control C */
+  __IO  uint16_t                       SERCOM_BAUD;        /* Offset: 0x0C (R/W  16) USART Baud Rate */
+  __IO  uint8_t                        SERCOM_RXPL;        /* Offset: 0x0E (R/W  8) USART Receive Pulse Length */
+  __I   uint8_t                        Reserved1[0x05];
+  __IO  uint8_t                        SERCOM_INTENCLR;    /* Offset: 0x14 (R/W  8) USART Interrupt Enable Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        SERCOM_INTENSET;    /* Offset: 0x16 (R/W  8) USART Interrupt Enable Set */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        SERCOM_INTFLAG;     /* Offset: 0x18 (R/W  8) USART Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint16_t                       SERCOM_STATUS;      /* Offset: 0x1A (R/W  16) USART Status */
+  __I   uint32_t                       SERCOM_SYNCBUSY;    /* Offset: 0x1C (R/   32) USART Synchronization Busy */
+  __I   uint8_t                        SERCOM_RXERRCNT;    /* Offset: 0x20 (R/   8) USART Receive Error Count */
+  __I   uint8_t                        Reserved5[0x01];
+  __IO  uint16_t                       SERCOM_LENGTH;      /* Offset: 0x22 (R/W  16) USART Length */
+  __I   uint8_t                        Reserved6[0x04];
+  __IO  uint32_t                       SERCOM_DATA;        /* Offset: 0x28 (R/W  32) USART Data */
+  __I   uint8_t                        Reserved7[0x04];
+  __IO  uint8_t                        SERCOM_DBGCTRL;     /* Offset: 0x30 (R/W  8) USART Debug Control */
+  __I   uint8_t                        Reserved8[0x03];
+  __I   uint16_t                       SERCOM_FIFOSPACE;   /* Offset: 0x34 (R/   16) USART FIFO Space */
+  __IO  uint16_t                       SERCOM_FIFOPTR;     /* Offset: 0x36 (R/W  16) USART FIFO CPU Pointers */
+} sercom_usart_registers_t;
+
+/* SERCOM hardware registers */
+typedef union
+{  /* Serial Communication Interface */
+       sercom_i2cm_registers_t        I2CM;           /* I2C Master Mode */
+       sercom_i2cs_registers_t        I2CS;           /* I2C Slave Mode */
+       sercom_spi_registers_t         SPI;            /* SPI Mode */
+       sercom_usart_registers_t       USART;          /* USART Mode */
+} sercom_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_SERCOM_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/supc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/supc.h
new file mode 100644
index 00000000..1e26cc63
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/supc.h
@@ -0,0 +1,400 @@
+/*
+ * Component description for SUPC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_SUPC_COMPONENT_H_
+#define _PIC32CMGC00_SUPC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR SUPC                      */
+/* ************************************************************************** */
+
+/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#define SUPC_INTENCLR_RESETVALUE              _UINT32_(0x00)                                       /*  (SUPC_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define SUPC_INTENCLR_LVDET_Pos               _UINT32_(0)                                          /* (SUPC_INTENCLR) Low Voltage Detector Interrupt Enable Position */
+#define SUPC_INTENCLR_LVDET_Msk               (_UINT32_(0x1) << SUPC_INTENCLR_LVDET_Pos)           /* (SUPC_INTENCLR) Low Voltage Detector Interrupt Enable Mask */
+#define SUPC_INTENCLR_LVDET(value)            (SUPC_INTENCLR_LVDET_Msk & (_UINT32_(value) << SUPC_INTENCLR_LVDET_Pos)) /* Assignment of value for LVDET in the SUPC_INTENCLR register */
+#define SUPC_INTENCLR_LVDRDY_Pos              _UINT32_(1)                                          /* (SUPC_INTENCLR) Low Voltage Detector Ready Interrupt Enable Position */
+#define SUPC_INTENCLR_LVDRDY_Msk              (_UINT32_(0x1) << SUPC_INTENCLR_LVDRDY_Pos)          /* (SUPC_INTENCLR) Low Voltage Detector Ready Interrupt Enable Mask */
+#define SUPC_INTENCLR_LVDRDY(value)           (SUPC_INTENCLR_LVDRDY_Msk & (_UINT32_(value) << SUPC_INTENCLR_LVDRDY_Pos)) /* Assignment of value for LVDRDY in the SUPC_INTENCLR register */
+#define SUPC_INTENCLR_ULDORDY_Pos             _UINT32_(2)                                          /* (SUPC_INTENCLR) User LDO Regulator Ready Interrupt Enable Position */
+#define SUPC_INTENCLR_ULDORDY_Msk             (_UINT32_(0x1) << SUPC_INTENCLR_ULDORDY_Pos)         /* (SUPC_INTENCLR) User LDO Regulator Ready Interrupt Enable Mask */
+#define SUPC_INTENCLR_ULDORDY(value)          (SUPC_INTENCLR_ULDORDY_Msk & (_UINT32_(value) << SUPC_INTENCLR_ULDORDY_Pos)) /* Assignment of value for ULDORDY in the SUPC_INTENCLR register */
+#define SUPC_INTENCLR_ULDOOVHEAT_Pos          _UINT32_(3)                                          /* (SUPC_INTENCLR) User LDO Regulator OverHeat Interrupt Enable Position */
+#define SUPC_INTENCLR_ULDOOVHEAT_Msk          (_UINT32_(0x1) << SUPC_INTENCLR_ULDOOVHEAT_Pos)      /* (SUPC_INTENCLR) User LDO Regulator OverHeat Interrupt Enable Mask */
+#define SUPC_INTENCLR_ULDOOVHEAT(value)       (SUPC_INTENCLR_ULDOOVHEAT_Msk & (_UINT32_(value) << SUPC_INTENCLR_ULDOOVHEAT_Pos)) /* Assignment of value for ULDOOVHEAT in the SUPC_INTENCLR register */
+#define SUPC_INTENCLR_BORVDDUSB_Pos           _UINT32_(5)                                          /* (SUPC_INTENCLR) BORVDDUSB Interrupt Enable Position */
+#define SUPC_INTENCLR_BORVDDUSB_Msk           (_UINT32_(0x1) << SUPC_INTENCLR_BORVDDUSB_Pos)       /* (SUPC_INTENCLR) BORVDDUSB Interrupt Enable Mask */
+#define SUPC_INTENCLR_BORVDDUSB(value)        (SUPC_INTENCLR_BORVDDUSB_Msk & (_UINT32_(value) << SUPC_INTENCLR_BORVDDUSB_Pos)) /* Assignment of value for BORVDDUSB in the SUPC_INTENCLR register */
+#define SUPC_INTENCLR_ADDVREGRDY0_Pos         _UINT32_(8)                                          /* (SUPC_INTENCLR) Additional Regulator ready 0 Interrupt Enable Position */
+#define SUPC_INTENCLR_ADDVREGRDY0_Msk         (_UINT32_(0x1) << SUPC_INTENCLR_ADDVREGRDY0_Pos)     /* (SUPC_INTENCLR) Additional Regulator ready 0 Interrupt Enable Mask */
+#define SUPC_INTENCLR_ADDVREGRDY0(value)      (SUPC_INTENCLR_ADDVREGRDY0_Msk & (_UINT32_(value) << SUPC_INTENCLR_ADDVREGRDY0_Pos)) /* Assignment of value for ADDVREGRDY0 in the SUPC_INTENCLR register */
+#define SUPC_INTENCLR_Msk                     _UINT32_(0x0000012F)                                 /* (SUPC_INTENCLR) Register Mask  */
+
+#define SUPC_INTENCLR_ADDVREGRDY_Pos          _UINT32_(8)                                          /* (SUPC_INTENCLR Position) Additional Regulator ready x Interrupt Enable */
+#define SUPC_INTENCLR_ADDVREGRDY_Msk          (_UINT32_(0x1) << SUPC_INTENCLR_ADDVREGRDY_Pos)      /* (SUPC_INTENCLR Mask) ADDVREGRDY */
+#define SUPC_INTENCLR_ADDVREGRDY(value)       (SUPC_INTENCLR_ADDVREGRDY_Msk & (_UINT32_(value) << SUPC_INTENCLR_ADDVREGRDY_Pos)) 
+
+/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#define SUPC_INTENSET_RESETVALUE              _UINT32_(0x00)                                       /*  (SUPC_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define SUPC_INTENSET_LVDET_Pos               _UINT32_(0)                                          /* (SUPC_INTENSET) Low Voltage Detector Interrupt Enable Position */
+#define SUPC_INTENSET_LVDET_Msk               (_UINT32_(0x1) << SUPC_INTENSET_LVDET_Pos)           /* (SUPC_INTENSET) Low Voltage Detector Interrupt Enable Mask */
+#define SUPC_INTENSET_LVDET(value)            (SUPC_INTENSET_LVDET_Msk & (_UINT32_(value) << SUPC_INTENSET_LVDET_Pos)) /* Assignment of value for LVDET in the SUPC_INTENSET register */
+#define SUPC_INTENSET_LVDRDY_Pos              _UINT32_(1)                                          /* (SUPC_INTENSET) Low Voltage Detector Ready Interrupt Enable Position */
+#define SUPC_INTENSET_LVDRDY_Msk              (_UINT32_(0x1) << SUPC_INTENSET_LVDRDY_Pos)          /* (SUPC_INTENSET) Low Voltage Detector Ready Interrupt Enable Mask */
+#define SUPC_INTENSET_LVDRDY(value)           (SUPC_INTENSET_LVDRDY_Msk & (_UINT32_(value) << SUPC_INTENSET_LVDRDY_Pos)) /* Assignment of value for LVDRDY in the SUPC_INTENSET register */
+#define SUPC_INTENSET_ULDORDY_Pos             _UINT32_(2)                                          /* (SUPC_INTENSET) User LDO Regulator Ready Interrupt Enable Position */
+#define SUPC_INTENSET_ULDORDY_Msk             (_UINT32_(0x1) << SUPC_INTENSET_ULDORDY_Pos)         /* (SUPC_INTENSET) User LDO Regulator Ready Interrupt Enable Mask */
+#define SUPC_INTENSET_ULDORDY(value)          (SUPC_INTENSET_ULDORDY_Msk & (_UINT32_(value) << SUPC_INTENSET_ULDORDY_Pos)) /* Assignment of value for ULDORDY in the SUPC_INTENSET register */
+#define SUPC_INTENSET_ULDOOVHEAT_Pos          _UINT32_(3)                                          /* (SUPC_INTENSET) User LDO Regulator OverHeat Interrupt Enable Position */
+#define SUPC_INTENSET_ULDOOVHEAT_Msk          (_UINT32_(0x1) << SUPC_INTENSET_ULDOOVHEAT_Pos)      /* (SUPC_INTENSET) User LDO Regulator OverHeat Interrupt Enable Mask */
+#define SUPC_INTENSET_ULDOOVHEAT(value)       (SUPC_INTENSET_ULDOOVHEAT_Msk & (_UINT32_(value) << SUPC_INTENSET_ULDOOVHEAT_Pos)) /* Assignment of value for ULDOOVHEAT in the SUPC_INTENSET register */
+#define SUPC_INTENSET_BORVDDUSB_Pos           _UINT32_(5)                                          /* (SUPC_INTENSET) BORVDDUSB Interrupt Enable Position */
+#define SUPC_INTENSET_BORVDDUSB_Msk           (_UINT32_(0x1) << SUPC_INTENSET_BORVDDUSB_Pos)       /* (SUPC_INTENSET) BORVDDUSB Interrupt Enable Mask */
+#define SUPC_INTENSET_BORVDDUSB(value)        (SUPC_INTENSET_BORVDDUSB_Msk & (_UINT32_(value) << SUPC_INTENSET_BORVDDUSB_Pos)) /* Assignment of value for BORVDDUSB in the SUPC_INTENSET register */
+#define SUPC_INTENSET_ADDVREGRDY0_Pos         _UINT32_(8)                                          /* (SUPC_INTENSET) Additional Regulator ready 0 Interrupt Enable Position */
+#define SUPC_INTENSET_ADDVREGRDY0_Msk         (_UINT32_(0x1) << SUPC_INTENSET_ADDVREGRDY0_Pos)     /* (SUPC_INTENSET) Additional Regulator ready 0 Interrupt Enable Mask */
+#define SUPC_INTENSET_ADDVREGRDY0(value)      (SUPC_INTENSET_ADDVREGRDY0_Msk & (_UINT32_(value) << SUPC_INTENSET_ADDVREGRDY0_Pos)) /* Assignment of value for ADDVREGRDY0 in the SUPC_INTENSET register */
+#define SUPC_INTENSET_Msk                     _UINT32_(0x0000012F)                                 /* (SUPC_INTENSET) Register Mask  */
+
+#define SUPC_INTENSET_ADDVREGRDY_Pos          _UINT32_(8)                                          /* (SUPC_INTENSET Position) Additional Regulator ready x Interrupt Enable */
+#define SUPC_INTENSET_ADDVREGRDY_Msk          (_UINT32_(0x1) << SUPC_INTENSET_ADDVREGRDY_Pos)      /* (SUPC_INTENSET Mask) ADDVREGRDY */
+#define SUPC_INTENSET_ADDVREGRDY(value)       (SUPC_INTENSET_ADDVREGRDY_Msk & (_UINT32_(value) << SUPC_INTENSET_ADDVREGRDY_Pos)) 
+
+/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#define SUPC_INTFLAG_RESETVALUE               _UINT32_(0x00)                                       /*  (SUPC_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define SUPC_INTFLAG_LVDET_Pos                _UINT32_(0)                                          /* (SUPC_INTFLAG) Low Voltage Detector Interrupt. Set to one if VDDIO crosses the treshold voltage in the good direction according to LVD.DIR. Position */
+#define SUPC_INTFLAG_LVDET_Msk                (_UINT32_(0x1) << SUPC_INTFLAG_LVDET_Pos)            /* (SUPC_INTFLAG) Low Voltage Detector Interrupt. Set to one if VDDIO crosses the treshold voltage in the good direction according to LVD.DIR. Mask */
+#define SUPC_INTFLAG_LVDET(value)             (SUPC_INTFLAG_LVDET_Msk & (_UINT32_(value) << SUPC_INTFLAG_LVDET_Pos)) /* Assignment of value for LVDET in the SUPC_INTFLAG register */
+#define SUPC_INTFLAG_LVDRDY_Pos               _UINT32_(1)                                          /* (SUPC_INTFLAG) Low Voltage Detector Ready Interrupt. Set to one if LVD is ready to operate. Position */
+#define SUPC_INTFLAG_LVDRDY_Msk               (_UINT32_(0x1) << SUPC_INTFLAG_LVDRDY_Pos)           /* (SUPC_INTFLAG) Low Voltage Detector Ready Interrupt. Set to one if LVD is ready to operate. Mask */
+#define SUPC_INTFLAG_LVDRDY(value)            (SUPC_INTFLAG_LVDRDY_Msk & (_UINT32_(value) << SUPC_INTFLAG_LVDRDY_Pos)) /* Assignment of value for LVDRDY in the SUPC_INTFLAG register */
+#define SUPC_INTFLAG_ULDORDY_Pos              _UINT32_(2)                                          /* (SUPC_INTFLAG) User LDO Regulator Ready Interrupt. Set to one if ULDO is ready meaning that output voltage is correct. Position */
+#define SUPC_INTFLAG_ULDORDY_Msk              (_UINT32_(0x1) << SUPC_INTFLAG_ULDORDY_Pos)          /* (SUPC_INTFLAG) User LDO Regulator Ready Interrupt. Set to one if ULDO is ready meaning that output voltage is correct. Mask */
+#define SUPC_INTFLAG_ULDORDY(value)           (SUPC_INTFLAG_ULDORDY_Msk & (_UINT32_(value) << SUPC_INTFLAG_ULDORDY_Pos)) /* Assignment of value for ULDORDY in the SUPC_INTFLAG register */
+#define SUPC_INTFLAG_ULDOOVHEAT_Pos           _UINT32_(3)                                          /* (SUPC_INTFLAG) User LDO Regulator OverHeat Interrupt. Is set to one if overheat condition is detected. Position */
+#define SUPC_INTFLAG_ULDOOVHEAT_Msk           (_UINT32_(0x1) << SUPC_INTFLAG_ULDOOVHEAT_Pos)       /* (SUPC_INTFLAG) User LDO Regulator OverHeat Interrupt. Is set to one if overheat condition is detected. Mask */
+#define SUPC_INTFLAG_ULDOOVHEAT(value)        (SUPC_INTFLAG_ULDOOVHEAT_Msk & (_UINT32_(value) << SUPC_INTFLAG_ULDOOVHEAT_Pos)) /* Assignment of value for ULDOOVHEAT in the SUPC_INTFLAG register */
+#define SUPC_INTFLAG_BORVDDUSB_Pos            _UINT32_(5)                                          /* (SUPC_INTFLAG) BORVDDUSB Interrupt. Set to one if VDDUSB issue is detected. Position */
+#define SUPC_INTFLAG_BORVDDUSB_Msk            (_UINT32_(0x1) << SUPC_INTFLAG_BORVDDUSB_Pos)        /* (SUPC_INTFLAG) BORVDDUSB Interrupt. Set to one if VDDUSB issue is detected. Mask */
+#define SUPC_INTFLAG_BORVDDUSB(value)         (SUPC_INTFLAG_BORVDDUSB_Msk & (_UINT32_(value) << SUPC_INTFLAG_BORVDDUSB_Pos)) /* Assignment of value for BORVDDUSB in the SUPC_INTFLAG register */
+#define SUPC_INTFLAG_ADDVREGRDY0_Pos          _UINT32_(8)                                          /* (SUPC_INTFLAG) Additional Regulator ready 0 Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct. Position */
+#define SUPC_INTFLAG_ADDVREGRDY0_Msk          (_UINT32_(0x1) << SUPC_INTFLAG_ADDVREGRDY0_Pos)      /* (SUPC_INTFLAG) Additional Regulator ready 0 Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct. Mask */
+#define SUPC_INTFLAG_ADDVREGRDY0(value)       (SUPC_INTFLAG_ADDVREGRDY0_Msk & (_UINT32_(value) << SUPC_INTFLAG_ADDVREGRDY0_Pos)) /* Assignment of value for ADDVREGRDY0 in the SUPC_INTFLAG register */
+#define SUPC_INTFLAG_Msk                      _UINT32_(0x0000012F)                                 /* (SUPC_INTFLAG) Register Mask  */
+
+#define SUPC_INTFLAG_ADDVREGRDY_Pos           _UINT32_(8)                                          /* (SUPC_INTFLAG Position) Additional Regulator ready x Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct. */
+#define SUPC_INTFLAG_ADDVREGRDY_Msk           (_UINT32_(0x1) << SUPC_INTFLAG_ADDVREGRDY_Pos)       /* (SUPC_INTFLAG Mask) ADDVREGRDY */
+#define SUPC_INTFLAG_ADDVREGRDY(value)        (SUPC_INTFLAG_ADDVREGRDY_Msk & (_UINT32_(value) << SUPC_INTFLAG_ADDVREGRDY_Pos)) 
+
+/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) ( R/ 32) Flag status -------- */
+#define SUPC_STATUS_RESETVALUE                _UINT32_(0x00)                                       /*  (SUPC_STATUS) Flag status  Reset Value */
+
+#define SUPC_STATUS_LVDET_Pos                 _UINT32_(0)                                          /* (SUPC_STATUS) Low Voltage Detector Status. Position */
+#define SUPC_STATUS_LVDET_Msk                 (_UINT32_(0x1) << SUPC_STATUS_LVDET_Pos)             /* (SUPC_STATUS) Low Voltage Detector Status. Mask */
+#define SUPC_STATUS_LVDET(value)              (SUPC_STATUS_LVDET_Msk & (_UINT32_(value) << SUPC_STATUS_LVDET_Pos)) /* Assignment of value for LVDET in the SUPC_STATUS register */
+#define SUPC_STATUS_LVDRDY_Pos                _UINT32_(1)                                          /* (SUPC_STATUS) Low Voltage Detector Ready Status Position */
+#define SUPC_STATUS_LVDRDY_Msk                (_UINT32_(0x1) << SUPC_STATUS_LVDRDY_Pos)            /* (SUPC_STATUS) Low Voltage Detector Ready Status Mask */
+#define SUPC_STATUS_LVDRDY(value)             (SUPC_STATUS_LVDRDY_Msk & (_UINT32_(value) << SUPC_STATUS_LVDRDY_Pos)) /* Assignment of value for LVDRDY in the SUPC_STATUS register */
+#define SUPC_STATUS_ULDORDY_Pos               _UINT32_(2)                                          /* (SUPC_STATUS) User LDO regulator Status. It corresponds to vreg_ready_mv signal from ULDO. Position */
+#define SUPC_STATUS_ULDORDY_Msk               (_UINT32_(0x1) << SUPC_STATUS_ULDORDY_Pos)           /* (SUPC_STATUS) User LDO regulator Status. It corresponds to vreg_ready_mv signal from ULDO. Mask */
+#define SUPC_STATUS_ULDORDY(value)            (SUPC_STATUS_ULDORDY_Msk & (_UINT32_(value) << SUPC_STATUS_ULDORDY_Pos)) /* Assignment of value for ULDORDY in the SUPC_STATUS register */
+#define SUPC_STATUS_ULDOOVHEAT_Pos            _UINT32_(3)                                          /* (SUPC_STATUS) User LDO Regulator OverHeat Status. It corresponds to vreg_overheat_event_mv signal from ULDO. Position */
+#define SUPC_STATUS_ULDOOVHEAT_Msk            (_UINT32_(0x1) << SUPC_STATUS_ULDOOVHEAT_Pos)        /* (SUPC_STATUS) User LDO Regulator OverHeat Status. It corresponds to vreg_overheat_event_mv signal from ULDO. Mask */
+#define SUPC_STATUS_ULDOOVHEAT(value)         (SUPC_STATUS_ULDOOVHEAT_Msk & (_UINT32_(value) << SUPC_STATUS_ULDOOVHEAT_Pos)) /* Assignment of value for ULDOOVHEAT in the SUPC_STATUS register */
+#define SUPC_STATUS_BORVDDUSB_Pos             _UINT32_(5)                                          /* (SUPC_STATUS) BORVDDUSB Status. One if VDDUSB is OK. It corresponds to bor_vddusb_n_mv signal of SMOR. Position */
+#define SUPC_STATUS_BORVDDUSB_Msk             (_UINT32_(0x1) << SUPC_STATUS_BORVDDUSB_Pos)         /* (SUPC_STATUS) BORVDDUSB Status. One if VDDUSB is OK. It corresponds to bor_vddusb_n_mv signal of SMOR. Mask */
+#define SUPC_STATUS_BORVDDUSB(value)          (SUPC_STATUS_BORVDDUSB_Msk & (_UINT32_(value) << SUPC_STATUS_BORVDDUSB_Pos)) /* Assignment of value for BORVDDUSB in the SUPC_STATUS register */
+#define SUPC_STATUS_ADDVREGRDY0_Pos           _UINT32_(8)                                          /* (SUPC_STATUS) Additional Regulator ready 0 Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator. Position */
+#define SUPC_STATUS_ADDVREGRDY0_Msk           (_UINT32_(0x1) << SUPC_STATUS_ADDVREGRDY0_Pos)       /* (SUPC_STATUS) Additional Regulator ready 0 Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator. Mask */
+#define SUPC_STATUS_ADDVREGRDY0(value)        (SUPC_STATUS_ADDVREGRDY0_Msk & (_UINT32_(value) << SUPC_STATUS_ADDVREGRDY0_Pos)) /* Assignment of value for ADDVREGRDY0 in the SUPC_STATUS register */
+#define SUPC_STATUS_Msk                       _UINT32_(0x0000012F)                                 /* (SUPC_STATUS) Register Mask  */
+
+#define SUPC_STATUS_ADDVREGRDY_Pos            _UINT32_(8)                                          /* (SUPC_STATUS Position) Additional Regulator ready x Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator. */
+#define SUPC_STATUS_ADDVREGRDY_Msk            (_UINT32_(0x1) << SUPC_STATUS_ADDVREGRDY_Pos)        /* (SUPC_STATUS Mask) ADDVREGRDY */
+#define SUPC_STATUS_ADDVREGRDY(value)         (SUPC_STATUS_ADDVREGRDY_Msk & (_UINT32_(value) << SUPC_STATUS_ADDVREGRDY_Pos)) 
+
+/* -------- SUPC_SYNCBUSY : (SUPC Offset: 0x10) ( R/ 32) Synchronisation Busy -------- */
+#define SUPC_SYNCBUSY_RESETVALUE              _UINT32_(0x00)                                       /*  (SUPC_SYNCBUSY) Synchronisation Busy  Reset Value */
+
+#define SUPC_SYNCBUSY_BOR_Pos                 _UINT32_(0)                                          /* (SUPC_SYNCBUSY) BOR Synchronization Busy Position */
+#define SUPC_SYNCBUSY_BOR_Msk                 (_UINT32_(0x1) << SUPC_SYNCBUSY_BOR_Pos)             /* (SUPC_SYNCBUSY) BOR Synchronization Busy Mask */
+#define SUPC_SYNCBUSY_BOR(value)              (SUPC_SYNCBUSY_BOR_Msk & (_UINT32_(value) << SUPC_SYNCBUSY_BOR_Pos)) /* Assignment of value for BOR in the SUPC_SYNCBUSY register */
+#define SUPC_SYNCBUSY_Msk                     _UINT32_(0x00000001)                                 /* (SUPC_SYNCBUSY) Register Mask  */
+
+
+/* -------- SUPC_BOR : (SUPC Offset: 0x14) (R/W 32) BOR Control -------- */
+#define SUPC_BOR_RESETVALUE                   _UINT32_(0x00)                                       /*  (SUPC_BOR) BOR Control  Reset Value */
+
+#define SUPC_BOR_DCBORPSEL_Pos                _UINT32_(4)                                          /* (SUPC_BOR) Duty Cycle BOR Prescaler Select Position */
+#define SUPC_BOR_DCBORPSEL_Msk                (_UINT32_(0x7) << SUPC_BOR_DCBORPSEL_Pos)            /* (SUPC_BOR) Duty Cycle BOR Prescaler Select Mask */
+#define SUPC_BOR_DCBORPSEL(value)             (SUPC_BOR_DCBORPSEL_Msk & (_UINT32_(value) << SUPC_BOR_DCBORPSEL_Pos)) /* Assignment of value for DCBORPSEL in the SUPC_BOR register */
+#define   SUPC_BOR_DCBORPSEL_NODIV_Val        _UINT32_(0x0)                                        /* (SUPC_BOR) Not Divided  */
+#define   SUPC_BOR_DCBORPSEL_DIV2_Val         _UINT32_(0x1)                                        /* (SUPC_BOR) Divide clock by 2  */
+#define   SUPC_BOR_DCBORPSEL_DIV4_Val         _UINT32_(0x2)                                        /* (SUPC_BOR) Divide clock by 4  */
+#define   SUPC_BOR_DCBORPSEL_DIV8_Val         _UINT32_(0x3)                                        /* (SUPC_BOR) Divide clock by 8  */
+#define   SUPC_BOR_DCBORPSEL_DIV16_Val        _UINT32_(0x4)                                        /* (SUPC_BOR) Divide clock by 16  */
+#define   SUPC_BOR_DCBORPSEL_DIV32_Val        _UINT32_(0x5)                                        /* (SUPC_BOR) Divide clock by 32  */
+#define   SUPC_BOR_DCBORPSEL_DIV64_Val        _UINT32_(0x6)                                        /* (SUPC_BOR) Divide clock by 64  */
+#define   SUPC_BOR_DCBORPSEL_DIV128_Val       _UINT32_(0x7)                                        /* (SUPC_BOR) Divide clock by 128  */
+#define SUPC_BOR_DCBORPSEL_NODIV              (SUPC_BOR_DCBORPSEL_NODIV_Val << SUPC_BOR_DCBORPSEL_Pos) /* (SUPC_BOR) Not Divided Position */
+#define SUPC_BOR_DCBORPSEL_DIV2               (SUPC_BOR_DCBORPSEL_DIV2_Val << SUPC_BOR_DCBORPSEL_Pos) /* (SUPC_BOR) Divide clock by 2 Position */
+#define SUPC_BOR_DCBORPSEL_DIV4               (SUPC_BOR_DCBORPSEL_DIV4_Val << SUPC_BOR_DCBORPSEL_Pos) /* (SUPC_BOR) Divide clock by 4 Position */
+#define SUPC_BOR_DCBORPSEL_DIV8               (SUPC_BOR_DCBORPSEL_DIV8_Val << SUPC_BOR_DCBORPSEL_Pos) /* (SUPC_BOR) Divide clock by 8 Position */
+#define SUPC_BOR_DCBORPSEL_DIV16              (SUPC_BOR_DCBORPSEL_DIV16_Val << SUPC_BOR_DCBORPSEL_Pos) /* (SUPC_BOR) Divide clock by 16 Position */
+#define SUPC_BOR_DCBORPSEL_DIV32              (SUPC_BOR_DCBORPSEL_DIV32_Val << SUPC_BOR_DCBORPSEL_Pos) /* (SUPC_BOR) Divide clock by 32 Position */
+#define SUPC_BOR_DCBORPSEL_DIV64              (SUPC_BOR_DCBORPSEL_DIV64_Val << SUPC_BOR_DCBORPSEL_Pos) /* (SUPC_BOR) Divide clock by 64 Position */
+#define SUPC_BOR_DCBORPSEL_DIV128             (SUPC_BOR_DCBORPSEL_DIV128_Val << SUPC_BOR_DCBORPSEL_Pos) /* (SUPC_BOR) Divide clock by 128 Position */
+#define SUPC_BOR_BORFILT_Pos                  _UINT32_(8)                                          /* (SUPC_BOR) BOR filtering Position */
+#define SUPC_BOR_BORFILT_Msk                  (_UINT32_(0x3) << SUPC_BOR_BORFILT_Pos)              /* (SUPC_BOR) BOR filtering Mask */
+#define SUPC_BOR_BORFILT(value)               (SUPC_BOR_BORFILT_Msk & (_UINT32_(value) << SUPC_BOR_BORFILT_Pos)) /* Assignment of value for BORFILT in the SUPC_BOR register */
+#define   SUPC_BOR_BORFILT_NOFILT_Val         _UINT32_(0x0)                                        /* (SUPC_BOR) No digital filtering  */
+#define   SUPC_BOR_BORFILT_FILT32US_Val       _UINT32_(0x1)                                        /* (SUPC_BOR) 32us filtering  */
+#define   SUPC_BOR_BORFILT_FILT125US_Val      _UINT32_(0x2)                                        /* (SUPC_BOR) 125us filtering  */
+#define   SUPC_BOR_BORFILT_FILT250US_Val      _UINT32_(0x3)                                        /* (SUPC_BOR) 250us filtering  */
+#define SUPC_BOR_BORFILT_NOFILT               (SUPC_BOR_BORFILT_NOFILT_Val << SUPC_BOR_BORFILT_Pos) /* (SUPC_BOR) No digital filtering Position */
+#define SUPC_BOR_BORFILT_FILT32US             (SUPC_BOR_BORFILT_FILT32US_Val << SUPC_BOR_BORFILT_Pos) /* (SUPC_BOR) 32us filtering Position */
+#define SUPC_BOR_BORFILT_FILT125US            (SUPC_BOR_BORFILT_FILT125US_Val << SUPC_BOR_BORFILT_Pos) /* (SUPC_BOR) 125us filtering Position */
+#define SUPC_BOR_BORFILT_FILT250US            (SUPC_BOR_BORFILT_FILT250US_Val << SUPC_BOR_BORFILT_Pos) /* (SUPC_BOR) 250us filtering Position */
+#define SUPC_BOR_Msk                          _UINT32_(0x00000370)                                 /* (SUPC_BOR) Register Mask  */
+
+
+/* -------- SUPC_LVD : (SUPC Offset: 0x18) (R/W 32) LVD Control -------- */
+#define SUPC_LVD_RESETVALUE                   _UINT32_(0x00)                                       /*  (SUPC_LVD) LVD Control  Reset Value */
+
+#define SUPC_LVD_ENABLE_Pos                   _UINT32_(1)                                          /* (SUPC_LVD) Enable Position */
+#define SUPC_LVD_ENABLE_Msk                   (_UINT32_(0x1) << SUPC_LVD_ENABLE_Pos)               /* (SUPC_LVD) Enable Mask */
+#define SUPC_LVD_ENABLE(value)                (SUPC_LVD_ENABLE_Msk & (_UINT32_(value) << SUPC_LVD_ENABLE_Pos)) /* Assignment of value for ENABLE in the SUPC_LVD register */
+#define SUPC_LVD_DIR_Pos                      _UINT32_(2)                                          /* (SUPC_LVD) Direction Position */
+#define SUPC_LVD_DIR_Msk                      (_UINT32_(0x1) << SUPC_LVD_DIR_Pos)                  /* (SUPC_LVD) Direction Mask */
+#define SUPC_LVD_DIR(value)                   (SUPC_LVD_DIR_Msk & (_UINT32_(value) << SUPC_LVD_DIR_Pos)) /* Assignment of value for DIR in the SUPC_LVD register */
+#define   SUPC_LVD_DIR_rising_Val             _UINT32_(0x0)                                        /* (SUPC_LVD) Rising detection  */
+#define   SUPC_LVD_DIR_falling_Val            _UINT32_(0x1)                                        /* (SUPC_LVD) Falling detection  */
+#define SUPC_LVD_DIR_rising                   (SUPC_LVD_DIR_rising_Val << SUPC_LVD_DIR_Pos)        /* (SUPC_LVD) Rising detection Position */
+#define SUPC_LVD_DIR_falling                  (SUPC_LVD_DIR_falling_Val << SUPC_LVD_DIR_Pos)       /* (SUPC_LVD) Falling detection Position */
+#define SUPC_LVD_OEVEN_Pos                    _UINT32_(3)                                          /* (SUPC_LVD) Output Event Enable Position */
+#define SUPC_LVD_OEVEN_Msk                    (_UINT32_(0x1) << SUPC_LVD_OEVEN_Pos)                /* (SUPC_LVD) Output Event Enable Mask */
+#define SUPC_LVD_OEVEN(value)                 (SUPC_LVD_OEVEN_Msk & (_UINT32_(value) << SUPC_LVD_OEVEN_Pos)) /* Assignment of value for OEVEN in the SUPC_LVD register */
+#define SUPC_LVD_RUNSTDBY_Pos                 _UINT32_(4)                                          /* (SUPC_LVD) Run during Standby Position */
+#define SUPC_LVD_RUNSTDBY_Msk                 (_UINT32_(0x1) << SUPC_LVD_RUNSTDBY_Pos)             /* (SUPC_LVD) Run during Standby Mask */
+#define SUPC_LVD_RUNSTDBY(value)              (SUPC_LVD_RUNSTDBY_Msk & (_UINT32_(value) << SUPC_LVD_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the SUPC_LVD register */
+#define SUPC_LVD_LEVEL_Pos                    _UINT32_(16)                                         /* (SUPC_LVD) Threshold Level. See "pwr_smor_[nn]_v1 DOS" - level section to get details. Position */
+#define SUPC_LVD_LEVEL_Msk                    (_UINT32_(0xF) << SUPC_LVD_LEVEL_Pos)                /* (SUPC_LVD) Threshold Level. See "pwr_smor_[nn]_v1 DOS" - level section to get details. Mask */
+#define SUPC_LVD_LEVEL(value)                 (SUPC_LVD_LEVEL_Msk & (_UINT32_(value) << SUPC_LVD_LEVEL_Pos)) /* Assignment of value for LEVEL in the SUPC_LVD register */
+#define SUPC_LVD_Msk                          _UINT32_(0x000F001E)                                 /* (SUPC_LVD) Register Mask  */
+
+
+/* -------- SUPC_VREGCTRL : (SUPC Offset: 0x1C) (R/W 32) VREG Control -------- */
+#define SUPC_VREGCTRL_RESETVALUE              _UINT32_(0x04)                                       /*  (SUPC_VREGCTRL) VREG Control  Reset Value */
+
+#define SUPC_VREGCTRL_VREGOUT_Pos             _UINT32_(0)                                          /* (SUPC_VREGCTRL) VREG Output Control in RUN mode only. Enable by production fuse by CALSUPC.VREGOUTEN Position */
+#define SUPC_VREGCTRL_VREGOUT_Msk             (_UINT32_(0x3) << SUPC_VREGCTRL_VREGOUT_Pos)         /* (SUPC_VREGCTRL) VREG Output Control in RUN mode only. Enable by production fuse by CALSUPC.VREGOUTEN Mask */
+#define SUPC_VREGCTRL_VREGOUT(value)          (SUPC_VREGCTRL_VREGOUT_Msk & (_UINT32_(value) << SUPC_VREGCTRL_VREGOUT_Pos)) /* Assignment of value for VREGOUT in the SUPC_VREGCTRL register */
+#define   SUPC_VREGCTRL_VREGOUT_1p2v_Val      _UINT32_(0x0)                                        /* (SUPC_VREGCTRL) In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.2v.  */
+#define   SUPC_VREGCTRL_VREGOUT_1p0v_Val      _UINT32_(0x1)                                        /* (SUPC_VREGCTRL) In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.0v.  */
+#define   SUPC_VREGCTRL_VREGOUT_0p8v_Val      _UINT32_(0x2)                                        /* (SUPC_VREGCTRL) In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 0.8v.  */
+#define SUPC_VREGCTRL_VREGOUT_1p2v            (SUPC_VREGCTRL_VREGOUT_1p2v_Val << SUPC_VREGCTRL_VREGOUT_Pos) /* (SUPC_VREGCTRL) In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.2v. Position */
+#define SUPC_VREGCTRL_VREGOUT_1p0v            (SUPC_VREGCTRL_VREGOUT_1p0v_Val << SUPC_VREGCTRL_VREGOUT_Pos) /* (SUPC_VREGCTRL) In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.0v. Position */
+#define SUPC_VREGCTRL_VREGOUT_0p8v            (SUPC_VREGCTRL_VREGOUT_0p8v_Val << SUPC_VREGCTRL_VREGOUT_Pos) /* (SUPC_VREGCTRL) In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 0.8v. Position */
+#define SUPC_VREGCTRL_OFFSTDBY_Pos            _UINT32_(2)                                          /* (SUPC_VREGCTRL) Off in Standby Control for VREGSW[N-1]. Useful for Riverside only. Position */
+#define SUPC_VREGCTRL_OFFSTDBY_Msk            (_UINT32_(0x1) << SUPC_VREGCTRL_OFFSTDBY_Pos)        /* (SUPC_VREGCTRL) Off in Standby Control for VREGSW[N-1]. Useful for Riverside only. Mask */
+#define SUPC_VREGCTRL_OFFSTDBY(value)         (SUPC_VREGCTRL_OFFSTDBY_Msk & (_UINT32_(value) << SUPC_VREGCTRL_OFFSTDBY_Pos)) /* Assignment of value for OFFSTDBY in the SUPC_VREGCTRL register */
+#define   SUPC_VREGCTRL_OFFSTDBY_OFF_Val      _UINT32_(0x0)                                        /* (SUPC_VREGCTRL) In standby mode, VREGSW1,2,3 are OFF  */
+#define   SUPC_VREGCTRL_OFFSTDBY_ON_Val       _UINT32_(0x1)                                        /* (SUPC_VREGCTRL) In standby mode, VREGSW1,2,3 are ON  */
+#define SUPC_VREGCTRL_OFFSTDBY_OFF            (SUPC_VREGCTRL_OFFSTDBY_OFF_Val << SUPC_VREGCTRL_OFFSTDBY_Pos) /* (SUPC_VREGCTRL) In standby mode, VREGSW1,2,3 are OFF Position */
+#define SUPC_VREGCTRL_OFFSTDBY_ON             (SUPC_VREGCTRL_OFFSTDBY_ON_Val << SUPC_VREGCTRL_OFFSTDBY_Pos) /* (SUPC_VREGCTRL) In standby mode, VREGSW1,2,3 are ON Position */
+#define SUPC_VREGCTRL_LVSTDBY_Pos             _UINT32_(4)                                          /* (SUPC_VREGCTRL) Low Voltage Standby Enable Position */
+#define SUPC_VREGCTRL_LVSTDBY_Msk             (_UINT32_(0x1) << SUPC_VREGCTRL_LVSTDBY_Pos)         /* (SUPC_VREGCTRL) Low Voltage Standby Enable Mask */
+#define SUPC_VREGCTRL_LVSTDBY(value)          (SUPC_VREGCTRL_LVSTDBY_Msk & (_UINT32_(value) << SUPC_VREGCTRL_LVSTDBY_Pos)) /* Assignment of value for LVSTDBY in the SUPC_VREGCTRL register */
+#define   SUPC_VREGCTRL_LVSTDBY_1p2v_Val      _UINT32_(0x0)                                        /* (SUPC_VREGCTRL) In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 1.2v.  */
+#define   SUPC_VREGCTRL_LVSTDBY_0p8v_Val      _UINT32_(0x1)                                        /* (SUPC_VREGCTRL) In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 0.8v.  */
+#define SUPC_VREGCTRL_LVSTDBY_1p2v            (SUPC_VREGCTRL_LVSTDBY_1p2v_Val << SUPC_VREGCTRL_LVSTDBY_Pos) /* (SUPC_VREGCTRL) In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 1.2v. Position */
+#define SUPC_VREGCTRL_LVSTDBY_0p8v            (SUPC_VREGCTRL_LVSTDBY_0p8v_Val << SUPC_VREGCTRL_LVSTDBY_Pos) /* (SUPC_VREGCTRL) In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 0.8v. Position */
+#define SUPC_VREGCTRL_LVHIB_Pos               _UINT32_(5)                                          /* (SUPC_VREGCTRL) Low Voltage Hibernate Enable Position */
+#define SUPC_VREGCTRL_LVHIB_Msk               (_UINT32_(0x1) << SUPC_VREGCTRL_LVHIB_Pos)           /* (SUPC_VREGCTRL) Low Voltage Hibernate Enable Mask */
+#define SUPC_VREGCTRL_LVHIB(value)            (SUPC_VREGCTRL_LVHIB_Msk & (_UINT32_(value) << SUPC_VREGCTRL_LVHIB_Pos)) /* Assignment of value for LVHIB in the SUPC_VREGCTRL register */
+#define   SUPC_VREGCTRL_LVHIB_1p2v_Val        _UINT32_(0x0)                                        /* (SUPC_VREGCTRL) In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 1.2v.  */
+#define   SUPC_VREGCTRL_LVHIB_0p8v_Val        _UINT32_(0x1)                                        /* (SUPC_VREGCTRL) In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 0.8v  */
+#define SUPC_VREGCTRL_LVHIB_1p2v              (SUPC_VREGCTRL_LVHIB_1p2v_Val << SUPC_VREGCTRL_LVHIB_Pos) /* (SUPC_VREGCTRL) In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 1.2v. Position */
+#define SUPC_VREGCTRL_LVHIB_0p8v              (SUPC_VREGCTRL_LVHIB_0p8v_Val << SUPC_VREGCTRL_LVHIB_Pos) /* (SUPC_VREGCTRL) In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 0.8v Position */
+#define SUPC_VREGCTRL_CPEN_Pos                _UINT32_(8)                                          /* (SUPC_VREGCTRL) Charge Pump Enable and Auto-enable. Position */
+#define SUPC_VREGCTRL_CPEN_Msk                (_UINT32_(0x3) << SUPC_VREGCTRL_CPEN_Pos)            /* (SUPC_VREGCTRL) Charge Pump Enable and Auto-enable. Mask */
+#define SUPC_VREGCTRL_CPEN(value)             (SUPC_VREGCTRL_CPEN_Msk & (_UINT32_(value) << SUPC_VREGCTRL_CPEN_Pos)) /* Assignment of value for CPEN in the SUPC_VREGCTRL register */
+#define SUPC_VREGCTRL_ULDOEN_Pos              _UINT32_(12)                                         /* (SUPC_VREGCTRL) User LDO Voltage Regulator Enable Position */
+#define SUPC_VREGCTRL_ULDOEN_Msk              (_UINT32_(0x1) << SUPC_VREGCTRL_ULDOEN_Pos)          /* (SUPC_VREGCTRL) User LDO Voltage Regulator Enable Mask */
+#define SUPC_VREGCTRL_ULDOEN(value)           (SUPC_VREGCTRL_ULDOEN_Msk & (_UINT32_(value) << SUPC_VREGCTRL_ULDOEN_Pos)) /* Assignment of value for ULDOEN in the SUPC_VREGCTRL register */
+#define SUPC_VREGCTRL_ULDOSTDBY_Pos           _UINT32_(13)                                         /* (SUPC_VREGCTRL) User LDO Voltage Regulator Configuration Position */
+#define SUPC_VREGCTRL_ULDOSTDBY_Msk           (_UINT32_(0x1) << SUPC_VREGCTRL_ULDOSTDBY_Pos)       /* (SUPC_VREGCTRL) User LDO Voltage Regulator Configuration Mask */
+#define SUPC_VREGCTRL_ULDOSTDBY(value)        (SUPC_VREGCTRL_ULDOSTDBY_Msk & (_UINT32_(value) << SUPC_VREGCTRL_ULDOSTDBY_Pos)) /* Assignment of value for ULDOSTDBY in the SUPC_VREGCTRL register */
+#define   SUPC_VREGCTRL_ULDOSTDBY_OFFINSTDBY_Val _UINT32_(0x0)                                        /* (SUPC_VREGCTRL) Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well.  */
+#define   SUPC_VREGCTRL_ULDOSTDBY_ONINSTDBY_Val _UINT32_(0x1)                                        /* (SUPC_VREGCTRL) Regulator is ON in Standby mode. is OFF from Hibernate mode. It is OFF in backup mode as well.  */
+#define SUPC_VREGCTRL_ULDOSTDBY_OFFINSTDBY    (SUPC_VREGCTRL_ULDOSTDBY_OFFINSTDBY_Val << SUPC_VREGCTRL_ULDOSTDBY_Pos) /* (SUPC_VREGCTRL) Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well. Position */
+#define SUPC_VREGCTRL_ULDOSTDBY_ONINSTDBY     (SUPC_VREGCTRL_ULDOSTDBY_ONINSTDBY_Val << SUPC_VREGCTRL_ULDOSTDBY_Pos) /* (SUPC_VREGCTRL) Regulator is ON in Standby mode. is OFF from Hibernate mode. It is OFF in backup mode as well. Position */
+#define SUPC_VREGCTRL_ULDOLEVEL_Pos           _UINT32_(14)                                         /* (SUPC_VREGCTRL) User LDO Voltage Level Selection Position */
+#define SUPC_VREGCTRL_ULDOLEVEL_Msk           (_UINT32_(0x3) << SUPC_VREGCTRL_ULDOLEVEL_Pos)       /* (SUPC_VREGCTRL) User LDO Voltage Level Selection Mask */
+#define SUPC_VREGCTRL_ULDOLEVEL(value)        (SUPC_VREGCTRL_ULDOLEVEL_Msk & (_UINT32_(value) << SUPC_VREGCTRL_ULDOLEVEL_Pos)) /* Assignment of value for ULDOLEVEL in the SUPC_VREGCTRL register */
+#define   SUPC_VREGCTRL_ULDOLEVEL_1p2v_Val    _UINT32_(0x0)                                        /* (SUPC_VREGCTRL) Vout = 1.2v  */
+#define   SUPC_VREGCTRL_ULDOLEVEL_1p5v_Val    _UINT32_(0x1)                                        /* (SUPC_VREGCTRL) Vout = 1.5v  */
+#define   SUPC_VREGCTRL_ULDOLEVEL_1p8v_Val    _UINT32_(0x2)                                        /* (SUPC_VREGCTRL) Vout = 1.8v  */
+#define   SUPC_VREGCTRL_ULDOLEVEL_2p5v_Val    _UINT32_(0x3)                                        /* (SUPC_VREGCTRL) Vout = 2.5v  */
+#define SUPC_VREGCTRL_ULDOLEVEL_1p2v          (SUPC_VREGCTRL_ULDOLEVEL_1p2v_Val << SUPC_VREGCTRL_ULDOLEVEL_Pos) /* (SUPC_VREGCTRL) Vout = 1.2v Position */
+#define SUPC_VREGCTRL_ULDOLEVEL_1p5v          (SUPC_VREGCTRL_ULDOLEVEL_1p5v_Val << SUPC_VREGCTRL_ULDOLEVEL_Pos) /* (SUPC_VREGCTRL) Vout = 1.5v Position */
+#define SUPC_VREGCTRL_ULDOLEVEL_1p8v          (SUPC_VREGCTRL_ULDOLEVEL_1p8v_Val << SUPC_VREGCTRL_ULDOLEVEL_Pos) /* (SUPC_VREGCTRL) Vout = 1.8v Position */
+#define SUPC_VREGCTRL_ULDOLEVEL_2p5v          (SUPC_VREGCTRL_ULDOLEVEL_2p5v_Val << SUPC_VREGCTRL_ULDOLEVEL_Pos) /* (SUPC_VREGCTRL) Vout = 2.5v Position */
+#define SUPC_VREGCTRL_AVREGEN_Pos             _UINT32_(16)                                         /* (SUPC_VREGCTRL) Additional Voltage Regulator Enable Position */
+#define SUPC_VREGCTRL_AVREGEN_Msk             (_UINT32_(0x1) << SUPC_VREGCTRL_AVREGEN_Pos)         /* (SUPC_VREGCTRL) Additional Voltage Regulator Enable Mask */
+#define SUPC_VREGCTRL_AVREGEN(value)          (SUPC_VREGCTRL_AVREGEN_Msk & (_UINT32_(value) << SUPC_VREGCTRL_AVREGEN_Pos)) /* Assignment of value for AVREGEN in the SUPC_VREGCTRL register */
+#define SUPC_VREGCTRL_AVREGSTDBY_Pos          _UINT32_(24)                                         /* (SUPC_VREGCTRL) Additional Voltage Regulator Configuration Position */
+#define SUPC_VREGCTRL_AVREGSTDBY_Msk          (_UINT32_(0x1) << SUPC_VREGCTRL_AVREGSTDBY_Pos)      /* (SUPC_VREGCTRL) Additional Voltage Regulator Configuration Mask */
+#define SUPC_VREGCTRL_AVREGSTDBY(value)       (SUPC_VREGCTRL_AVREGSTDBY_Msk & (_UINT32_(value) << SUPC_VREGCTRL_AVREGSTDBY_Pos)) /* Assignment of value for AVREGSTDBY in the SUPC_VREGCTRL register */
+#define   SUPC_VREGCTRL_AVREGSTDBY_OFFINSTDBY_Val _UINT32_(0x0)                                        /* (SUPC_VREGCTRL) Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well.  */
+#define   SUPC_VREGCTRL_AVREGSTDBY_ONINSTDBY_Val _UINT32_(0x1)                                        /* (SUPC_VREGCTRL) Regulator is ON in Standby mode if AVREGEN bit is set. is OFF from Hibernate mode. It is OFF in backup mode as well.  */
+#define SUPC_VREGCTRL_AVREGSTDBY_OFFINSTDBY   (SUPC_VREGCTRL_AVREGSTDBY_OFFINSTDBY_Val << SUPC_VREGCTRL_AVREGSTDBY_Pos) /* (SUPC_VREGCTRL) Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well. Position */
+#define SUPC_VREGCTRL_AVREGSTDBY_ONINSTDBY    (SUPC_VREGCTRL_AVREGSTDBY_ONINSTDBY_Val << SUPC_VREGCTRL_AVREGSTDBY_Pos) /* (SUPC_VREGCTRL) Regulator is ON in Standby mode if AVREGEN bit is set. is OFF from Hibernate mode. It is OFF in backup mode as well. Position */
+#define SUPC_VREGCTRL_SRAM_VLD_Pos            _UINT32_(30)                                         /* (SUPC_VREGCTRL) SRAM VALID Status Bit Position */
+#define SUPC_VREGCTRL_SRAM_VLD_Msk            (_UINT32_(0x1) << SUPC_VREGCTRL_SRAM_VLD_Pos)        /* (SUPC_VREGCTRL) SRAM VALID Status Bit Mask */
+#define SUPC_VREGCTRL_SRAM_VLD(value)         (SUPC_VREGCTRL_SRAM_VLD_Msk & (_UINT32_(value) << SUPC_VREGCTRL_SRAM_VLD_Pos)) /* Assignment of value for SRAM_VLD in the SUPC_VREGCTRL register */
+#define SUPC_VREGCTRL_BKUP_VLD_Pos            _UINT32_(31)                                         /* (SUPC_VREGCTRL) Backup Domain Valid Status Bit Position */
+#define SUPC_VREGCTRL_BKUP_VLD_Msk            (_UINT32_(0x1) << SUPC_VREGCTRL_BKUP_VLD_Pos)        /* (SUPC_VREGCTRL) Backup Domain Valid Status Bit Mask */
+#define SUPC_VREGCTRL_BKUP_VLD(value)         (SUPC_VREGCTRL_BKUP_VLD_Msk & (_UINT32_(value) << SUPC_VREGCTRL_BKUP_VLD_Pos)) /* Assignment of value for BKUP_VLD in the SUPC_VREGCTRL register */
+#define SUPC_VREGCTRL_Msk                     _UINT32_(0xC101F337)                                 /* (SUPC_VREGCTRL) Register Mask  */
+
+
+/* -------- SUPC_VREFCTRL : (SUPC Offset: 0x20) (R/W 32) VREF Control -------- */
+#define SUPC_VREFCTRL_RESETVALUE              _UINT32_(0x02)                                       /*  (SUPC_VREFCTRL) VREF Control  Reset Value */
+
+#define SUPC_VREFCTRL_LPSTDBY_Pos             _UINT32_(0)                                          /* (SUPC_VREFCTRL) Bandgap and Regulators Low Power Standby Enable Position */
+#define SUPC_VREFCTRL_LPSTDBY_Msk             (_UINT32_(0x1) << SUPC_VREFCTRL_LPSTDBY_Pos)         /* (SUPC_VREFCTRL) Bandgap and Regulators Low Power Standby Enable Mask */
+#define SUPC_VREFCTRL_LPSTDBY(value)          (SUPC_VREFCTRL_LPSTDBY_Msk & (_UINT32_(value) << SUPC_VREFCTRL_LPSTDBY_Pos)) /* Assignment of value for LPSTDBY in the SUPC_VREFCTRL register */
+#define   SUPC_VREFCTRL_LPSTDBY_FullPower_Val _UINT32_(0x0)                                        /* (SUPC_VREFCTRL) In standby mode, bandgap and enabled regulator(s) are set to nominal power mode.  */
+#define   SUPC_VREFCTRL_LPSTDBY_LowPower_Val  _UINT32_(0x1)                                        /* (SUPC_VREFCTRL) In standby mode, bandgap and enabled regulator(s) are set to low power mode.  */
+#define SUPC_VREFCTRL_LPSTDBY_FullPower       (SUPC_VREFCTRL_LPSTDBY_FullPower_Val << SUPC_VREFCTRL_LPSTDBY_Pos) /* (SUPC_VREFCTRL) In standby mode, bandgap and enabled regulator(s) are set to nominal power mode. Position */
+#define SUPC_VREFCTRL_LPSTDBY_LowPower        (SUPC_VREFCTRL_LPSTDBY_LowPower_Val << SUPC_VREFCTRL_LPSTDBY_Pos) /* (SUPC_VREFCTRL) In standby mode, bandgap and enabled regulator(s) are set to low power mode. Position */
+#define SUPC_VREFCTRL_LPHIB_Pos               _UINT32_(1)                                          /* (SUPC_VREFCTRL) Bandgap and Regulators Low Power Hibernate Enable Position */
+#define SUPC_VREFCTRL_LPHIB_Msk               (_UINT32_(0x1) << SUPC_VREFCTRL_LPHIB_Pos)           /* (SUPC_VREFCTRL) Bandgap and Regulators Low Power Hibernate Enable Mask */
+#define SUPC_VREFCTRL_LPHIB(value)            (SUPC_VREFCTRL_LPHIB_Msk & (_UINT32_(value) << SUPC_VREFCTRL_LPHIB_Pos)) /* Assignment of value for LPHIB in the SUPC_VREFCTRL register */
+#define   SUPC_VREFCTRL_LPHIB_FullPower_Val   _UINT32_(0x0)                                        /* (SUPC_VREFCTRL) In hibernate mode, bandgap is set to nominal power mode. As a consequence, enabled regulator(s) are set to nominal power mode.  */
+#define   SUPC_VREFCTRL_LPHIB_LowPower_Val    _UINT32_(0x1)                                        /* (SUPC_VREFCTRL) In hibernate mode, bandgap is set to low power mode. As a consequence, enabled regulator(s) are set to low power mode.  */
+#define SUPC_VREFCTRL_LPHIB_FullPower         (SUPC_VREFCTRL_LPHIB_FullPower_Val << SUPC_VREFCTRL_LPHIB_Pos) /* (SUPC_VREFCTRL) In hibernate mode, bandgap is set to nominal power mode. As a consequence, enabled regulator(s) are set to nominal power mode. Position */
+#define SUPC_VREFCTRL_LPHIB_LowPower          (SUPC_VREFCTRL_LPHIB_LowPower_Val << SUPC_VREFCTRL_LPHIB_Pos) /* (SUPC_VREFCTRL) In hibernate mode, bandgap is set to low power mode. As a consequence, enabled regulator(s) are set to low power mode. Position */
+#define SUPC_VREFCTRL_TSEN_Pos                _UINT32_(4)                                          /* (SUPC_VREFCTRL) Temperature Sensor Output Enable Position */
+#define SUPC_VREFCTRL_TSEN_Msk                (_UINT32_(0x1) << SUPC_VREFCTRL_TSEN_Pos)            /* (SUPC_VREFCTRL) Temperature Sensor Output Enable Mask */
+#define SUPC_VREFCTRL_TSEN(value)             (SUPC_VREFCTRL_TSEN_Msk & (_UINT32_(value) << SUPC_VREFCTRL_TSEN_Pos)) /* Assignment of value for TSEN in the SUPC_VREFCTRL register */
+#define SUPC_VREFCTRL_Msk                     _UINT32_(0x00000013)                                 /* (SUPC_VREFCTRL) Register Mask  */
+
+
+/* -------- SUPC_BKOUT : (SUPC Offset: 0x28) (R/W 32) Backup Output Control -------- */
+#define SUPC_BKOUT_RESETVALUE                 _UINT32_(0x00)                                       /*  (SUPC_BKOUT) Backup Output Control  Reset Value */
+
+#define SUPC_BKOUT_EN0_Pos                    _UINT32_(0)                                          /* (SUPC_BKOUT) Enable Output Position */
+#define SUPC_BKOUT_EN0_Msk                    (_UINT32_(0x1) << SUPC_BKOUT_EN0_Pos)                /* (SUPC_BKOUT) Enable Output Mask */
+#define SUPC_BKOUT_EN0(value)                 (SUPC_BKOUT_EN0_Msk & (_UINT32_(value) << SUPC_BKOUT_EN0_Pos)) /* Assignment of value for EN0 in the SUPC_BKOUT register */
+#define SUPC_BKOUT_EN1_Pos                    _UINT32_(2)                                          /* (SUPC_BKOUT) Enable Output Position */
+#define SUPC_BKOUT_EN1_Msk                    (_UINT32_(0x1) << SUPC_BKOUT_EN1_Pos)                /* (SUPC_BKOUT) Enable Output Mask */
+#define SUPC_BKOUT_EN1(value)                 (SUPC_BKOUT_EN1_Msk & (_UINT32_(value) << SUPC_BKOUT_EN1_Pos)) /* Assignment of value for EN1 in the SUPC_BKOUT register */
+#define SUPC_BKOUT_CLR0_Pos                   _UINT32_(8)                                          /* (SUPC_BKOUT) Clear Output Position */
+#define SUPC_BKOUT_CLR0_Msk                   (_UINT32_(0x1) << SUPC_BKOUT_CLR0_Pos)               /* (SUPC_BKOUT) Clear Output Mask */
+#define SUPC_BKOUT_CLR0(value)                (SUPC_BKOUT_CLR0_Msk & (_UINT32_(value) << SUPC_BKOUT_CLR0_Pos)) /* Assignment of value for CLR0 in the SUPC_BKOUT register */
+#define SUPC_BKOUT_CLR1_Pos                   _UINT32_(10)                                         /* (SUPC_BKOUT) Clear Output Position */
+#define SUPC_BKOUT_CLR1_Msk                   (_UINT32_(0x1) << SUPC_BKOUT_CLR1_Pos)               /* (SUPC_BKOUT) Clear Output Mask */
+#define SUPC_BKOUT_CLR1(value)                (SUPC_BKOUT_CLR1_Msk & (_UINT32_(value) << SUPC_BKOUT_CLR1_Pos)) /* Assignment of value for CLR1 in the SUPC_BKOUT register */
+#define SUPC_BKOUT_SET0_Pos                   _UINT32_(16)                                         /* (SUPC_BKOUT) Set Output Position */
+#define SUPC_BKOUT_SET0_Msk                   (_UINT32_(0x1) << SUPC_BKOUT_SET0_Pos)               /* (SUPC_BKOUT) Set Output Mask */
+#define SUPC_BKOUT_SET0(value)                (SUPC_BKOUT_SET0_Msk & (_UINT32_(value) << SUPC_BKOUT_SET0_Pos)) /* Assignment of value for SET0 in the SUPC_BKOUT register */
+#define SUPC_BKOUT_SET1_Pos                   _UINT32_(18)                                         /* (SUPC_BKOUT) Set Output Position */
+#define SUPC_BKOUT_SET1_Msk                   (_UINT32_(0x1) << SUPC_BKOUT_SET1_Pos)               /* (SUPC_BKOUT) Set Output Mask */
+#define SUPC_BKOUT_SET1(value)                (SUPC_BKOUT_SET1_Msk & (_UINT32_(value) << SUPC_BKOUT_SET1_Pos)) /* Assignment of value for SET1 in the SUPC_BKOUT register */
+#define SUPC_BKOUT_TGLOM0_Pos                 _UINT32_(24)                                         /* (SUPC_BKOUT) Toggle Output Mode Position */
+#define SUPC_BKOUT_TGLOM0_Msk                 (_UINT32_(0x3) << SUPC_BKOUT_TGLOM0_Pos)             /* (SUPC_BKOUT) Toggle Output Mode Mask */
+#define SUPC_BKOUT_TGLOM0(value)              (SUPC_BKOUT_TGLOM0_Msk & (_UINT32_(value) << SUPC_BKOUT_TGLOM0_Pos)) /* Assignment of value for TGLOM0 in the SUPC_BKOUT register */
+#define   SUPC_BKOUT_TGLOM0_DISABLE_Val       _UINT32_(0x0)                                        /* (SUPC_BKOUT) The output does not toggle.  */
+#define   SUPC_BKOUT_TGLOM0_RTCTGL_Val        _UINT32_(0x1)                                        /* (SUPC_BKOUT) The output toggles on RTC event.  */
+#define   SUPC_BKOUT_TGLOM0_BKUPTGL_Val       _UINT32_(0x2)                                        /* (SUPC_BKOUT) The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software.  */
+#define SUPC_BKOUT_TGLOM0_DISABLE             (SUPC_BKOUT_TGLOM0_DISABLE_Val << SUPC_BKOUT_TGLOM0_Pos) /* (SUPC_BKOUT) The output does not toggle. Position */
+#define SUPC_BKOUT_TGLOM0_RTCTGL              (SUPC_BKOUT_TGLOM0_RTCTGL_Val << SUPC_BKOUT_TGLOM0_Pos) /* (SUPC_BKOUT) The output toggles on RTC event. Position */
+#define SUPC_BKOUT_TGLOM0_BKUPTGL             (SUPC_BKOUT_TGLOM0_BKUPTGL_Val << SUPC_BKOUT_TGLOM0_Pos) /* (SUPC_BKOUT) The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software. Position */
+#define SUPC_BKOUT_TGLOM1_Pos                 _UINT32_(26)                                         /* (SUPC_BKOUT) Toggle Output Mode Position */
+#define SUPC_BKOUT_TGLOM1_Msk                 (_UINT32_(0x3) << SUPC_BKOUT_TGLOM1_Pos)             /* (SUPC_BKOUT) Toggle Output Mode Mask */
+#define SUPC_BKOUT_TGLOM1(value)              (SUPC_BKOUT_TGLOM1_Msk & (_UINT32_(value) << SUPC_BKOUT_TGLOM1_Pos)) /* Assignment of value for TGLOM1 in the SUPC_BKOUT register */
+#define   SUPC_BKOUT_TGLOM1_DISABLE_Val       _UINT32_(0x0)                                        /* (SUPC_BKOUT) The output does not toggle.  */
+#define   SUPC_BKOUT_TGLOM1_RTCTGL_Val        _UINT32_(0x1)                                        /* (SUPC_BKOUT) The output toggles on RTC event.  */
+#define   SUPC_BKOUT_TGLOM1_BKUPTGL_Val       _UINT32_(0x2)                                        /* (SUPC_BKOUT) The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software.  */
+#define SUPC_BKOUT_TGLOM1_DISABLE             (SUPC_BKOUT_TGLOM1_DISABLE_Val << SUPC_BKOUT_TGLOM1_Pos) /* (SUPC_BKOUT) The output does not toggle. Position */
+#define SUPC_BKOUT_TGLOM1_RTCTGL              (SUPC_BKOUT_TGLOM1_RTCTGL_Val << SUPC_BKOUT_TGLOM1_Pos) /* (SUPC_BKOUT) The output toggles on RTC event. Position */
+#define SUPC_BKOUT_TGLOM1_BKUPTGL             (SUPC_BKOUT_TGLOM1_BKUPTGL_Val << SUPC_BKOUT_TGLOM1_Pos) /* (SUPC_BKOUT) The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software. Position */
+#define SUPC_BKOUT_Msk                        _UINT32_(0x0F050505)                                 /* (SUPC_BKOUT) Register Mask  */
+
+#define SUPC_BKOUT_EN_Pos                     _UINT32_(0)                                          /* (SUPC_BKOUT Position) Enable Output */
+#define SUPC_BKOUT_EN_Msk                     (_UINT32_(0x3) << SUPC_BKOUT_EN_Pos)                 /* (SUPC_BKOUT Mask) EN */
+#define SUPC_BKOUT_EN(value)                  (SUPC_BKOUT_EN_Msk & (_UINT32_(value) << SUPC_BKOUT_EN_Pos)) 
+#define SUPC_BKOUT_CLR_Pos                    _UINT32_(8)                                          /* (SUPC_BKOUT Position) Clear Output */
+#define SUPC_BKOUT_CLR_Msk                    (_UINT32_(0x3) << SUPC_BKOUT_CLR_Pos)                /* (SUPC_BKOUT Mask) CLR */
+#define SUPC_BKOUT_CLR(value)                 (SUPC_BKOUT_CLR_Msk & (_UINT32_(value) << SUPC_BKOUT_CLR_Pos)) 
+#define SUPC_BKOUT_SET_Pos                    _UINT32_(16)                                         /* (SUPC_BKOUT Position) Set Output */
+#define SUPC_BKOUT_SET_Msk                    (_UINT32_(0x3) << SUPC_BKOUT_SET_Pos)                /* (SUPC_BKOUT Mask) SET */
+#define SUPC_BKOUT_SET(value)                 (SUPC_BKOUT_SET_Msk & (_UINT32_(value) << SUPC_BKOUT_SET_Pos)) 
+
+/* -------- SUPC_BKIN : (SUPC Offset: 0x2C) ( R/ 32) Backup Input Control -------- */
+#define SUPC_BKIN_RESETVALUE                  _UINT32_(0x00)                                       /*  (SUPC_BKIN) Backup Input Control  Reset Value */
+
+#define SUPC_BKIN_BKIN_Pos                    _UINT32_(0)                                          /* (SUPC_BKIN) Backup Input Value Position */
+#define SUPC_BKIN_BKIN_Msk                    (_UINT32_(0x3) << SUPC_BKIN_BKIN_Pos)                /* (SUPC_BKIN) Backup Input Value Mask */
+#define SUPC_BKIN_BKIN(value)                 (SUPC_BKIN_BKIN_Msk & (_UINT32_(value) << SUPC_BKIN_BKIN_Pos)) /* Assignment of value for BKIN in the SUPC_BKIN register */
+#define SUPC_BKIN_Msk                         _UINT32_(0x00000003)                                 /* (SUPC_BKIN) Register Mask  */
+
+
+/* SUPC register offsets definitions */
+#define SUPC_INTENCLR_REG_OFST         _UINT32_(0x00)      /* (SUPC_INTENCLR) Interrupt Enable Clear Offset */
+#define SUPC_INTENSET_REG_OFST         _UINT32_(0x04)      /* (SUPC_INTENSET) Interrupt Enable Set Offset */
+#define SUPC_INTFLAG_REG_OFST          _UINT32_(0x08)      /* (SUPC_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define SUPC_STATUS_REG_OFST           _UINT32_(0x0C)      /* (SUPC_STATUS) Flag status Offset */
+#define SUPC_SYNCBUSY_REG_OFST         _UINT32_(0x10)      /* (SUPC_SYNCBUSY) Synchronisation Busy Offset */
+#define SUPC_BOR_REG_OFST              _UINT32_(0x14)      /* (SUPC_BOR) BOR Control Offset */
+#define SUPC_LVD_REG_OFST              _UINT32_(0x18)      /* (SUPC_LVD) LVD Control Offset */
+#define SUPC_VREGCTRL_REG_OFST         _UINT32_(0x1C)      /* (SUPC_VREGCTRL) VREG Control Offset */
+#define SUPC_VREFCTRL_REG_OFST         _UINT32_(0x20)      /* (SUPC_VREFCTRL) VREF Control Offset */
+#define SUPC_BKOUT_REG_OFST            _UINT32_(0x28)      /* (SUPC_BKOUT) Backup Output Control Offset */
+#define SUPC_BKIN_REG_OFST             _UINT32_(0x2C)      /* (SUPC_BKIN) Backup Input Control Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* SUPC register API structure */
+typedef struct
+{  /* Supply Controller */
+  __IO  uint32_t                       SUPC_INTENCLR;      /* Offset: 0x00 (R/W  32) Interrupt Enable Clear */
+  __IO  uint32_t                       SUPC_INTENSET;      /* Offset: 0x04 (R/W  32) Interrupt Enable Set */
+  __IO  uint32_t                       SUPC_INTFLAG;       /* Offset: 0x08 (R/W  32) Interrupt Flag Status and Clear */
+  __I   uint32_t                       SUPC_STATUS;        /* Offset: 0x0C (R/   32) Flag status */
+  __I   uint32_t                       SUPC_SYNCBUSY;      /* Offset: 0x10 (R/   32) Synchronisation Busy */
+  __IO  uint32_t                       SUPC_BOR;           /* Offset: 0x14 (R/W  32) BOR Control */
+  __IO  uint32_t                       SUPC_LVD;           /* Offset: 0x18 (R/W  32) LVD Control */
+  __IO  uint32_t                       SUPC_VREGCTRL;      /* Offset: 0x1C (R/W  32) VREG Control */
+  __IO  uint32_t                       SUPC_VREFCTRL;      /* Offset: 0x20 (R/W  32) VREF Control */
+  __I   uint8_t                        Reserved1[0x04];
+  __IO  uint32_t                       SUPC_BKOUT;         /* Offset: 0x28 (R/W  32) Backup Output Control */
+  __I   uint32_t                       SUPC_BKIN;          /* Offset: 0x2C (R/   32) Backup Input Control */
+} supc_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_SUPC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/tcc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/tcc.h
new file mode 100644
index 00000000..bb938592
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/tcc.h
@@ -0,0 +1,1051 @@
+/*
+ * Component description for TCC
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_TCC_COMPONENT_H_
+#define _PIC32CMGC00_TCC_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR TCC                       */
+/* ************************************************************************** */
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#define TCC_CTRLA_RESETVALUE                  _UINT32_(0x00)                                       /*  (TCC_CTRLA) Control A  Reset Value */
+
+#define TCC_CTRLA_SWRST_Pos                   _UINT32_(0)                                          /* (TCC_CTRLA) Software Reset Position */
+#define TCC_CTRLA_SWRST_Msk                   (_UINT32_(0x1) << TCC_CTRLA_SWRST_Pos)               /* (TCC_CTRLA) Software Reset Mask */
+#define TCC_CTRLA_SWRST(value)                (TCC_CTRLA_SWRST_Msk & (_UINT32_(value) << TCC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the TCC_CTRLA register */
+#define TCC_CTRLA_ENABLE_Pos                  _UINT32_(1)                                          /* (TCC_CTRLA) Enable Position */
+#define TCC_CTRLA_ENABLE_Msk                  (_UINT32_(0x1) << TCC_CTRLA_ENABLE_Pos)              /* (TCC_CTRLA) Enable Mask */
+#define TCC_CTRLA_ENABLE(value)               (TCC_CTRLA_ENABLE_Msk & (_UINT32_(value) << TCC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the TCC_CTRLA register */
+#define TCC_CTRLA_RESOLUTION_Pos              _UINT32_(5)                                          /* (TCC_CTRLA) Enhanced Resolution Position */
+#define TCC_CTRLA_RESOLUTION_Msk              (_UINT32_(0x3) << TCC_CTRLA_RESOLUTION_Pos)          /* (TCC_CTRLA) Enhanced Resolution Mask */
+#define TCC_CTRLA_RESOLUTION(value)           (TCC_CTRLA_RESOLUTION_Msk & (_UINT32_(value) << TCC_CTRLA_RESOLUTION_Pos)) /* Assignment of value for RESOLUTION in the TCC_CTRLA register */
+#define   TCC_CTRLA_RESOLUTION_NONE_Val       _UINT32_(0x0)                                        /* (TCC_CTRLA) Dithering is disabled  */
+#define   TCC_CTRLA_RESOLUTION_DITH4_Val      _UINT32_(0x1)                                        /* (TCC_CTRLA) Dithering is done every 16 PWM frames  */
+#define   TCC_CTRLA_RESOLUTION_DITH5_Val      _UINT32_(0x2)                                        /* (TCC_CTRLA) Dithering is done every 32 PWM frames  */
+#define   TCC_CTRLA_RESOLUTION_DITH6_Val      _UINT32_(0x3)                                        /* (TCC_CTRLA) Dithering is done every 64 PWM frames  */
+#define TCC_CTRLA_RESOLUTION_NONE             (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) /* (TCC_CTRLA) Dithering is disabled Position */
+#define TCC_CTRLA_RESOLUTION_DITH4            (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) /* (TCC_CTRLA) Dithering is done every 16 PWM frames Position */
+#define TCC_CTRLA_RESOLUTION_DITH5            (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) /* (TCC_CTRLA) Dithering is done every 32 PWM frames Position */
+#define TCC_CTRLA_RESOLUTION_DITH6            (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) /* (TCC_CTRLA) Dithering is done every 64 PWM frames Position */
+#define TCC_CTRLA_PRESCALER_Pos               _UINT32_(8)                                          /* (TCC_CTRLA) Prescaler Position */
+#define TCC_CTRLA_PRESCALER_Msk               (_UINT32_(0x7) << TCC_CTRLA_PRESCALER_Pos)           /* (TCC_CTRLA) Prescaler Mask */
+#define TCC_CTRLA_PRESCALER(value)            (TCC_CTRLA_PRESCALER_Msk & (_UINT32_(value) << TCC_CTRLA_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the TCC_CTRLA register */
+#define   TCC_CTRLA_PRESCALER_DIV1_Val        _UINT32_(0x0)                                        /* (TCC_CTRLA) No division  */
+#define   TCC_CTRLA_PRESCALER_DIV2_Val        _UINT32_(0x1)                                        /* (TCC_CTRLA) Divide by 2  */
+#define   TCC_CTRLA_PRESCALER_DIV4_Val        _UINT32_(0x2)                                        /* (TCC_CTRLA) Divide by 4  */
+#define   TCC_CTRLA_PRESCALER_DIV8_Val        _UINT32_(0x3)                                        /* (TCC_CTRLA) Divide by 8  */
+#define   TCC_CTRLA_PRESCALER_DIV16_Val       _UINT32_(0x4)                                        /* (TCC_CTRLA) Divide by 16  */
+#define   TCC_CTRLA_PRESCALER_DIV64_Val       _UINT32_(0x5)                                        /* (TCC_CTRLA) Divide by 64  */
+#define   TCC_CTRLA_PRESCALER_DIV256_Val      _UINT32_(0x6)                                        /* (TCC_CTRLA) Divide by 256  */
+#define   TCC_CTRLA_PRESCALER_DIV1024_Val     _UINT32_(0x7)                                        /* (TCC_CTRLA) Divide by 1024  */
+#define TCC_CTRLA_PRESCALER_DIV1              (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) No division Position */
+#define TCC_CTRLA_PRESCALER_DIV2              (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 2 Position */
+#define TCC_CTRLA_PRESCALER_DIV4              (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 4 Position */
+#define TCC_CTRLA_PRESCALER_DIV8              (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 8 Position */
+#define TCC_CTRLA_PRESCALER_DIV16             (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 16 Position */
+#define TCC_CTRLA_PRESCALER_DIV64             (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 64 Position */
+#define TCC_CTRLA_PRESCALER_DIV256            (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 256 Position */
+#define TCC_CTRLA_PRESCALER_DIV1024           (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) /* (TCC_CTRLA) Divide by 1024 Position */
+#define TCC_CTRLA_RUNSTDBY_Pos                _UINT32_(11)                                         /* (TCC_CTRLA) Run in Standby Position */
+#define TCC_CTRLA_RUNSTDBY_Msk                (_UINT32_(0x1) << TCC_CTRLA_RUNSTDBY_Pos)            /* (TCC_CTRLA) Run in Standby Mask */
+#define TCC_CTRLA_RUNSTDBY(value)             (TCC_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << TCC_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the TCC_CTRLA register */
+#define TCC_CTRLA_PRESCSYNC_Pos               _UINT32_(12)                                         /* (TCC_CTRLA) Prescaler and Counter Synchronization Selection Position */
+#define TCC_CTRLA_PRESCSYNC_Msk               (_UINT32_(0x3) << TCC_CTRLA_PRESCSYNC_Pos)           /* (TCC_CTRLA) Prescaler and Counter Synchronization Selection Mask */
+#define TCC_CTRLA_PRESCSYNC(value)            (TCC_CTRLA_PRESCSYNC_Msk & (_UINT32_(value) << TCC_CTRLA_PRESCSYNC_Pos)) /* Assignment of value for PRESCSYNC in the TCC_CTRLA register */
+#define   TCC_CTRLA_PRESCSYNC_GCLK_Val        _UINT32_(0x0)                                        /* (TCC_CTRLA) Reload or reset counter on next GCLK  */
+#define   TCC_CTRLA_PRESCSYNC_PRESC_Val       _UINT32_(0x1)                                        /* (TCC_CTRLA) Reload or reset counter on next prescaler clock  */
+#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val      _UINT32_(0x2)                                        /* (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter  */
+#define TCC_CTRLA_PRESCSYNC_GCLK              (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) /* (TCC_CTRLA) Reload or reset counter on next GCLK Position */
+#define TCC_CTRLA_PRESCSYNC_PRESC             (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) /* (TCC_CTRLA) Reload or reset counter on next prescaler clock Position */
+#define TCC_CTRLA_PRESCSYNC_RESYNC            (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) /* (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter Position */
+#define TCC_CTRLA_ALOCK_Pos                   _UINT32_(14)                                         /* (TCC_CTRLA) Auto Lock Position */
+#define TCC_CTRLA_ALOCK_Msk                   (_UINT32_(0x1) << TCC_CTRLA_ALOCK_Pos)               /* (TCC_CTRLA) Auto Lock Mask */
+#define TCC_CTRLA_ALOCK(value)                (TCC_CTRLA_ALOCK_Msk & (_UINT32_(value) << TCC_CTRLA_ALOCK_Pos)) /* Assignment of value for ALOCK in the TCC_CTRLA register */
+#define TCC_CTRLA_MSYNC_Pos                   _UINT32_(15)                                         /* (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) Position */
+#define TCC_CTRLA_MSYNC_Msk                   (_UINT32_(0x1) << TCC_CTRLA_MSYNC_Pos)               /* (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) Mask */
+#define TCC_CTRLA_MSYNC(value)                (TCC_CTRLA_MSYNC_Msk & (_UINT32_(value) << TCC_CTRLA_MSYNC_Pos)) /* Assignment of value for MSYNC in the TCC_CTRLA register */
+#define TCC_CTRLA_FCYCLE_Pos                  _UINT32_(16)                                         /* (TCC_CTRLA) Full Cycle Position */
+#define TCC_CTRLA_FCYCLE_Msk                  (_UINT32_(0x1) << TCC_CTRLA_FCYCLE_Pos)              /* (TCC_CTRLA) Full Cycle Mask */
+#define TCC_CTRLA_FCYCLE(value)               (TCC_CTRLA_FCYCLE_Msk & (_UINT32_(value) << TCC_CTRLA_FCYCLE_Pos)) /* Assignment of value for FCYCLE in the TCC_CTRLA register */
+#define TCC_CTRLA_DMAOS_Pos                   _UINT32_(23)                                         /* (TCC_CTRLA) DMA One-shot Trigger Mode Position */
+#define TCC_CTRLA_DMAOS_Msk                   (_UINT32_(0x1) << TCC_CTRLA_DMAOS_Pos)               /* (TCC_CTRLA) DMA One-shot Trigger Mode Mask */
+#define TCC_CTRLA_DMAOS(value)                (TCC_CTRLA_DMAOS_Msk & (_UINT32_(value) << TCC_CTRLA_DMAOS_Pos)) /* Assignment of value for DMAOS in the TCC_CTRLA register */
+#define TCC_CTRLA_CPTEN0_Pos                  _UINT32_(24)                                         /* (TCC_CTRLA) Capture Channel 0 Enable Position */
+#define TCC_CTRLA_CPTEN0_Msk                  (_UINT32_(0x1) << TCC_CTRLA_CPTEN0_Pos)              /* (TCC_CTRLA) Capture Channel 0 Enable Mask */
+#define TCC_CTRLA_CPTEN0(value)               (TCC_CTRLA_CPTEN0_Msk & (_UINT32_(value) << TCC_CTRLA_CPTEN0_Pos)) /* Assignment of value for CPTEN0 in the TCC_CTRLA register */
+#define TCC_CTRLA_CPTEN1_Pos                  _UINT32_(25)                                         /* (TCC_CTRLA) Capture Channel 1 Enable Position */
+#define TCC_CTRLA_CPTEN1_Msk                  (_UINT32_(0x1) << TCC_CTRLA_CPTEN1_Pos)              /* (TCC_CTRLA) Capture Channel 1 Enable Mask */
+#define TCC_CTRLA_CPTEN1(value)               (TCC_CTRLA_CPTEN1_Msk & (_UINT32_(value) << TCC_CTRLA_CPTEN1_Pos)) /* Assignment of value for CPTEN1 in the TCC_CTRLA register */
+#define TCC_CTRLA_Msk                         _UINT32_(0x0381FF63)                                 /* (TCC_CTRLA) Register Mask  */
+
+#define TCC_CTRLA_CPTEN_Pos                   _UINT32_(24)                                         /* (TCC_CTRLA Position) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk                   (_UINT32_(0x3) << TCC_CTRLA_CPTEN_Pos)               /* (TCC_CTRLA Mask) CPTEN */
+#define TCC_CTRLA_CPTEN(value)                (TCC_CTRLA_CPTEN_Msk & (_UINT32_(value) << TCC_CTRLA_CPTEN_Pos)) 
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#define TCC_CTRLBCLR_RESETVALUE               _UINT8_(0x00)                                        /*  (TCC_CTRLBCLR) Control B Clear  Reset Value */
+
+#define TCC_CTRLBCLR_DIR_Pos                  _UINT8_(0)                                           /* (TCC_CTRLBCLR) Counter Direction Position */
+#define TCC_CTRLBCLR_DIR_Msk                  (_UINT8_(0x1) << TCC_CTRLBCLR_DIR_Pos)               /* (TCC_CTRLBCLR) Counter Direction Mask */
+#define TCC_CTRLBCLR_DIR(value)               (TCC_CTRLBCLR_DIR_Msk & (_UINT8_(value) << TCC_CTRLBCLR_DIR_Pos)) /* Assignment of value for DIR in the TCC_CTRLBCLR register */
+#define TCC_CTRLBCLR_LUPD_Pos                 _UINT8_(1)                                           /* (TCC_CTRLBCLR) Lock Update Position */
+#define TCC_CTRLBCLR_LUPD_Msk                 (_UINT8_(0x1) << TCC_CTRLBCLR_LUPD_Pos)              /* (TCC_CTRLBCLR) Lock Update Mask */
+#define TCC_CTRLBCLR_LUPD(value)              (TCC_CTRLBCLR_LUPD_Msk & (_UINT8_(value) << TCC_CTRLBCLR_LUPD_Pos)) /* Assignment of value for LUPD in the TCC_CTRLBCLR register */
+#define TCC_CTRLBCLR_ONESHOT_Pos              _UINT8_(2)                                           /* (TCC_CTRLBCLR) One-Shot Position */
+#define TCC_CTRLBCLR_ONESHOT_Msk              (_UINT8_(0x1) << TCC_CTRLBCLR_ONESHOT_Pos)           /* (TCC_CTRLBCLR) One-Shot Mask */
+#define TCC_CTRLBCLR_ONESHOT(value)           (TCC_CTRLBCLR_ONESHOT_Msk & (_UINT8_(value) << TCC_CTRLBCLR_ONESHOT_Pos)) /* Assignment of value for ONESHOT in the TCC_CTRLBCLR register */
+#define TCC_CTRLBCLR_IDXCMD_Pos               _UINT8_(3)                                           /* (TCC_CTRLBCLR) Ramp Index Command Position */
+#define TCC_CTRLBCLR_IDXCMD_Msk               (_UINT8_(0x3) << TCC_CTRLBCLR_IDXCMD_Pos)            /* (TCC_CTRLBCLR) Ramp Index Command Mask */
+#define TCC_CTRLBCLR_IDXCMD(value)            (TCC_CTRLBCLR_IDXCMD_Msk & (_UINT8_(value) << TCC_CTRLBCLR_IDXCMD_Pos)) /* Assignment of value for IDXCMD in the TCC_CTRLBCLR register */
+#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val     _UINT8_(0x0)                                         /* (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B  */
+#define   TCC_CTRLBCLR_IDXCMD_SET_Val         _UINT8_(0x1)                                         /* (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle  */
+#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val       _UINT8_(0x2)                                         /* (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle  */
+#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val        _UINT8_(0x3)                                         /* (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle  */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE           (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) /* (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B Position */
+#define TCC_CTRLBCLR_IDXCMD_SET               (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) /* (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle Position */
+#define TCC_CTRLBCLR_IDXCMD_CLEAR             (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) /* (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle Position */
+#define TCC_CTRLBCLR_IDXCMD_HOLD              (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) /* (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle Position */
+#define TCC_CTRLBCLR_CMD_Pos                  _UINT8_(5)                                           /* (TCC_CTRLBCLR) TCC Command Position */
+#define TCC_CTRLBCLR_CMD_Msk                  (_UINT8_(0x7) << TCC_CTRLBCLR_CMD_Pos)               /* (TCC_CTRLBCLR) TCC Command Mask */
+#define TCC_CTRLBCLR_CMD(value)               (TCC_CTRLBCLR_CMD_Msk & (_UINT8_(value) << TCC_CTRLBCLR_CMD_Pos)) /* Assignment of value for CMD in the TCC_CTRLBCLR register */
+#define   TCC_CTRLBCLR_CMD_NONE_Val           _UINT8_(0x0)                                         /* (TCC_CTRLBCLR) No action  */
+#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val      _UINT8_(0x1)                                         /* (TCC_CTRLBCLR) Clear start, restart or retrigger  */
+#define   TCC_CTRLBCLR_CMD_STOP_Val           _UINT8_(0x2)                                         /* (TCC_CTRLBCLR) Force stop  */
+#define   TCC_CTRLBCLR_CMD_UPDATE_Val         _UINT8_(0x3)                                         /* (TCC_CTRLBCLR) Force update or double buffered registers  */
+#define   TCC_CTRLBCLR_CMD_READSYNC_Val       _UINT8_(0x4)                                         /* (TCC_CTRLBCLR) Force COUNT read synchronization  */
+#define   TCC_CTRLBCLR_CMD_DMAOS_Val          _UINT8_(0x5)                                         /* (TCC_CTRLBCLR) One-shot DMA trigger  */
+#define TCC_CTRLBCLR_CMD_NONE                 (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)  /* (TCC_CTRLBCLR) No action Position */
+#define TCC_CTRLBCLR_CMD_RETRIGGER            (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) Clear start, restart or retrigger Position */
+#define TCC_CTRLBCLR_CMD_STOP                 (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)  /* (TCC_CTRLBCLR) Force stop Position */
+#define TCC_CTRLBCLR_CMD_UPDATE               (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) Force update or double buffered registers Position */
+#define TCC_CTRLBCLR_CMD_READSYNC             (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) Force COUNT read synchronization Position */
+#define TCC_CTRLBCLR_CMD_DMAOS                (TCC_CTRLBCLR_CMD_DMAOS_Val << TCC_CTRLBCLR_CMD_Pos) /* (TCC_CTRLBCLR) One-shot DMA trigger Position */
+#define TCC_CTRLBCLR_Msk                      _UINT8_(0xFF)                                        /* (TCC_CTRLBCLR) Register Mask  */
+
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
+#define TCC_CTRLBSET_RESETVALUE               _UINT8_(0x00)                                        /*  (TCC_CTRLBSET) Control B Set  Reset Value */
+
+#define TCC_CTRLBSET_DIR_Pos                  _UINT8_(0)                                           /* (TCC_CTRLBSET) Counter Direction Position */
+#define TCC_CTRLBSET_DIR_Msk                  (_UINT8_(0x1) << TCC_CTRLBSET_DIR_Pos)               /* (TCC_CTRLBSET) Counter Direction Mask */
+#define TCC_CTRLBSET_DIR(value)               (TCC_CTRLBSET_DIR_Msk & (_UINT8_(value) << TCC_CTRLBSET_DIR_Pos)) /* Assignment of value for DIR in the TCC_CTRLBSET register */
+#define TCC_CTRLBSET_LUPD_Pos                 _UINT8_(1)                                           /* (TCC_CTRLBSET) Lock Update Position */
+#define TCC_CTRLBSET_LUPD_Msk                 (_UINT8_(0x1) << TCC_CTRLBSET_LUPD_Pos)              /* (TCC_CTRLBSET) Lock Update Mask */
+#define TCC_CTRLBSET_LUPD(value)              (TCC_CTRLBSET_LUPD_Msk & (_UINT8_(value) << TCC_CTRLBSET_LUPD_Pos)) /* Assignment of value for LUPD in the TCC_CTRLBSET register */
+#define TCC_CTRLBSET_ONESHOT_Pos              _UINT8_(2)                                           /* (TCC_CTRLBSET) One-Shot Position */
+#define TCC_CTRLBSET_ONESHOT_Msk              (_UINT8_(0x1) << TCC_CTRLBSET_ONESHOT_Pos)           /* (TCC_CTRLBSET) One-Shot Mask */
+#define TCC_CTRLBSET_ONESHOT(value)           (TCC_CTRLBSET_ONESHOT_Msk & (_UINT8_(value) << TCC_CTRLBSET_ONESHOT_Pos)) /* Assignment of value for ONESHOT in the TCC_CTRLBSET register */
+#define TCC_CTRLBSET_IDXCMD_Pos               _UINT8_(3)                                           /* (TCC_CTRLBSET) Ramp Index Command Position */
+#define TCC_CTRLBSET_IDXCMD_Msk               (_UINT8_(0x3) << TCC_CTRLBSET_IDXCMD_Pos)            /* (TCC_CTRLBSET) Ramp Index Command Mask */
+#define TCC_CTRLBSET_IDXCMD(value)            (TCC_CTRLBSET_IDXCMD_Msk & (_UINT8_(value) << TCC_CTRLBSET_IDXCMD_Pos)) /* Assignment of value for IDXCMD in the TCC_CTRLBSET register */
+#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val     _UINT8_(0x0)                                         /* (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B  */
+#define   TCC_CTRLBSET_IDXCMD_SET_Val         _UINT8_(0x1)                                         /* (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle  */
+#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val       _UINT8_(0x2)                                         /* (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle  */
+#define   TCC_CTRLBSET_IDXCMD_HOLD_Val        _UINT8_(0x3)                                         /* (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle  */
+#define TCC_CTRLBSET_IDXCMD_DISABLE           (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) /* (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B Position */
+#define TCC_CTRLBSET_IDXCMD_SET               (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) /* (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle Position */
+#define TCC_CTRLBSET_IDXCMD_CLEAR             (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) /* (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle Position */
+#define TCC_CTRLBSET_IDXCMD_HOLD              (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) /* (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle Position */
+#define TCC_CTRLBSET_CMD_Pos                  _UINT8_(5)                                           /* (TCC_CTRLBSET) TCC Command Position */
+#define TCC_CTRLBSET_CMD_Msk                  (_UINT8_(0x7) << TCC_CTRLBSET_CMD_Pos)               /* (TCC_CTRLBSET) TCC Command Mask */
+#define TCC_CTRLBSET_CMD(value)               (TCC_CTRLBSET_CMD_Msk & (_UINT8_(value) << TCC_CTRLBSET_CMD_Pos)) /* Assignment of value for CMD in the TCC_CTRLBSET register */
+#define   TCC_CTRLBSET_CMD_NONE_Val           _UINT8_(0x0)                                         /* (TCC_CTRLBSET) No action  */
+#define   TCC_CTRLBSET_CMD_RETRIGGER_Val      _UINT8_(0x1)                                         /* (TCC_CTRLBSET) Clear start, restart or retrigger  */
+#define   TCC_CTRLBSET_CMD_STOP_Val           _UINT8_(0x2)                                         /* (TCC_CTRLBSET) Force stop  */
+#define   TCC_CTRLBSET_CMD_UPDATE_Val         _UINT8_(0x3)                                         /* (TCC_CTRLBSET) Force update or double buffered registers  */
+#define   TCC_CTRLBSET_CMD_READSYNC_Val       _UINT8_(0x4)                                         /* (TCC_CTRLBSET) Force COUNT read synchronization  */
+#define   TCC_CTRLBSET_CMD_DMAOS_Val          _UINT8_(0x5)                                         /* (TCC_CTRLBSET) One-shot DMA trigger  */
+#define TCC_CTRLBSET_CMD_NONE                 (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)  /* (TCC_CTRLBSET) No action Position */
+#define TCC_CTRLBSET_CMD_RETRIGGER            (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) Clear start, restart or retrigger Position */
+#define TCC_CTRLBSET_CMD_STOP                 (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)  /* (TCC_CTRLBSET) Force stop Position */
+#define TCC_CTRLBSET_CMD_UPDATE               (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) Force update or double buffered registers Position */
+#define TCC_CTRLBSET_CMD_READSYNC             (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) Force COUNT read synchronization Position */
+#define TCC_CTRLBSET_CMD_DMAOS                (TCC_CTRLBSET_CMD_DMAOS_Val << TCC_CTRLBSET_CMD_Pos) /* (TCC_CTRLBSET) One-shot DMA trigger Position */
+#define TCC_CTRLBSET_Msk                      _UINT8_(0xFF)                                        /* (TCC_CTRLBSET) Register Mask  */
+
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */
+#define TCC_SYNCBUSY_RESETVALUE               _UINT32_(0x00)                                       /*  (TCC_SYNCBUSY) Synchronization Busy  Reset Value */
+
+#define TCC_SYNCBUSY_SWRST_Pos                _UINT32_(0)                                          /* (TCC_SYNCBUSY) Swrst Busy Position */
+#define TCC_SYNCBUSY_SWRST_Msk                (_UINT32_(0x1) << TCC_SYNCBUSY_SWRST_Pos)            /* (TCC_SYNCBUSY) Swrst Busy Mask */
+#define TCC_SYNCBUSY_SWRST(value)             (TCC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << TCC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the TCC_SYNCBUSY register */
+#define TCC_SYNCBUSY_ENABLE_Pos               _UINT32_(1)                                          /* (TCC_SYNCBUSY) Enable Busy Position */
+#define TCC_SYNCBUSY_ENABLE_Msk               (_UINT32_(0x1) << TCC_SYNCBUSY_ENABLE_Pos)           /* (TCC_SYNCBUSY) Enable Busy Mask */
+#define TCC_SYNCBUSY_ENABLE(value)            (TCC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << TCC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the TCC_SYNCBUSY register */
+#define TCC_SYNCBUSY_CTRLB_Pos                _UINT32_(2)                                          /* (TCC_SYNCBUSY) Ctrlb Busy Position */
+#define TCC_SYNCBUSY_CTRLB_Msk                (_UINT32_(0x1) << TCC_SYNCBUSY_CTRLB_Pos)            /* (TCC_SYNCBUSY) Ctrlb Busy Mask */
+#define TCC_SYNCBUSY_CTRLB(value)             (TCC_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CTRLB_Pos)) /* Assignment of value for CTRLB in the TCC_SYNCBUSY register */
+#define TCC_SYNCBUSY_STATUS_Pos               _UINT32_(3)                                          /* (TCC_SYNCBUSY) Status Busy Position */
+#define TCC_SYNCBUSY_STATUS_Msk               (_UINT32_(0x1) << TCC_SYNCBUSY_STATUS_Pos)           /* (TCC_SYNCBUSY) Status Busy Mask */
+#define TCC_SYNCBUSY_STATUS(value)            (TCC_SYNCBUSY_STATUS_Msk & (_UINT32_(value) << TCC_SYNCBUSY_STATUS_Pos)) /* Assignment of value for STATUS in the TCC_SYNCBUSY register */
+#define TCC_SYNCBUSY_COUNT_Pos                _UINT32_(4)                                          /* (TCC_SYNCBUSY) Count Busy Position */
+#define TCC_SYNCBUSY_COUNT_Msk                (_UINT32_(0x1) << TCC_SYNCBUSY_COUNT_Pos)            /* (TCC_SYNCBUSY) Count Busy Mask */
+#define TCC_SYNCBUSY_COUNT(value)             (TCC_SYNCBUSY_COUNT_Msk & (_UINT32_(value) << TCC_SYNCBUSY_COUNT_Pos)) /* Assignment of value for COUNT in the TCC_SYNCBUSY register */
+#define TCC_SYNCBUSY_PATT_Pos                 _UINT32_(5)                                          /* (TCC_SYNCBUSY) Pattern Busy Position */
+#define TCC_SYNCBUSY_PATT_Msk                 (_UINT32_(0x1) << TCC_SYNCBUSY_PATT_Pos)             /* (TCC_SYNCBUSY) Pattern Busy Mask */
+#define TCC_SYNCBUSY_PATT(value)              (TCC_SYNCBUSY_PATT_Msk & (_UINT32_(value) << TCC_SYNCBUSY_PATT_Pos)) /* Assignment of value for PATT in the TCC_SYNCBUSY register */
+#define TCC_SYNCBUSY_WAVE_Pos                 _UINT32_(6)                                          /* (TCC_SYNCBUSY) Wave Busy Position */
+#define TCC_SYNCBUSY_WAVE_Msk                 (_UINT32_(0x1) << TCC_SYNCBUSY_WAVE_Pos)             /* (TCC_SYNCBUSY) Wave Busy Mask */
+#define TCC_SYNCBUSY_WAVE(value)              (TCC_SYNCBUSY_WAVE_Msk & (_UINT32_(value) << TCC_SYNCBUSY_WAVE_Pos)) /* Assignment of value for WAVE in the TCC_SYNCBUSY register */
+#define TCC_SYNCBUSY_PER_Pos                  _UINT32_(7)                                          /* (TCC_SYNCBUSY) Period Busy Position */
+#define TCC_SYNCBUSY_PER_Msk                  (_UINT32_(0x1) << TCC_SYNCBUSY_PER_Pos)              /* (TCC_SYNCBUSY) Period Busy Mask */
+#define TCC_SYNCBUSY_PER(value)               (TCC_SYNCBUSY_PER_Msk & (_UINT32_(value) << TCC_SYNCBUSY_PER_Pos)) /* Assignment of value for PER in the TCC_SYNCBUSY register */
+#define TCC_SYNCBUSY_CC0_Pos                  _UINT32_(8)                                          /* (TCC_SYNCBUSY) Compare Channel 0 Busy Position */
+#define TCC_SYNCBUSY_CC0_Msk                  (_UINT32_(0x1) << TCC_SYNCBUSY_CC0_Pos)              /* (TCC_SYNCBUSY) Compare Channel 0 Busy Mask */
+#define TCC_SYNCBUSY_CC0(value)               (TCC_SYNCBUSY_CC0_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CC0_Pos)) /* Assignment of value for CC0 in the TCC_SYNCBUSY register */
+#define TCC_SYNCBUSY_CC1_Pos                  _UINT32_(9)                                          /* (TCC_SYNCBUSY) Compare Channel 1 Busy Position */
+#define TCC_SYNCBUSY_CC1_Msk                  (_UINT32_(0x1) << TCC_SYNCBUSY_CC1_Pos)              /* (TCC_SYNCBUSY) Compare Channel 1 Busy Mask */
+#define TCC_SYNCBUSY_CC1(value)               (TCC_SYNCBUSY_CC1_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CC1_Pos)) /* Assignment of value for CC1 in the TCC_SYNCBUSY register */
+#define TCC_SYNCBUSY_Msk                      _UINT32_(0x000003FF)                                 /* (TCC_SYNCBUSY) Register Mask  */
+
+#define TCC_SYNCBUSY_CC_Pos                   _UINT32_(8)                                          /* (TCC_SYNCBUSY Position) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk                   (_UINT32_(0x3) << TCC_SYNCBUSY_CC_Pos)               /* (TCC_SYNCBUSY Mask) CC */
+#define TCC_SYNCBUSY_CC(value)                (TCC_SYNCBUSY_CC_Msk & (_UINT32_(value) << TCC_SYNCBUSY_CC_Pos)) 
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#define TCC_FCTRLA_RESETVALUE                 _UINT32_(0x00)                                       /*  (TCC_FCTRLA) Recoverable Fault A Configuration  Reset Value */
+
+#define TCC_FCTRLA_SRC_Pos                    _UINT32_(0)                                          /* (TCC_FCTRLA) Fault A Source Position */
+#define TCC_FCTRLA_SRC_Msk                    (_UINT32_(0x3) << TCC_FCTRLA_SRC_Pos)                /* (TCC_FCTRLA) Fault A Source Mask */
+#define TCC_FCTRLA_SRC(value)                 (TCC_FCTRLA_SRC_Msk & (_UINT32_(value) << TCC_FCTRLA_SRC_Pos)) /* Assignment of value for SRC in the TCC_FCTRLA register */
+#define   TCC_FCTRLA_SRC_DISABLE_Val          _UINT32_(0x0)                                        /* (TCC_FCTRLA) Fault input disabled  */
+#define   TCC_FCTRLA_SRC_ENABLE_Val           _UINT32_(0x1)                                        /* (TCC_FCTRLA) MCEx (x=0,1) event input  */
+#define   TCC_FCTRLA_SRC_INVERT_Val           _UINT32_(0x2)                                        /* (TCC_FCTRLA) Inverted MCEx (x=0,1) event input  */
+#define   TCC_FCTRLA_SRC_ALTFAULT_Val         _UINT32_(0x3)                                        /* (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period  */
+#define TCC_FCTRLA_SRC_DISABLE                (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)   /* (TCC_FCTRLA) Fault input disabled Position */
+#define TCC_FCTRLA_SRC_ENABLE                 (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)    /* (TCC_FCTRLA) MCEx (x=0,1) event input Position */
+#define TCC_FCTRLA_SRC_INVERT                 (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)    /* (TCC_FCTRLA) Inverted MCEx (x=0,1) event input Position */
+#define TCC_FCTRLA_SRC_ALTFAULT               (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)  /* (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period Position */
+#define TCC_FCTRLA_KEEP_Pos                   _UINT32_(3)                                          /* (TCC_FCTRLA) Fault A Keeper Position */
+#define TCC_FCTRLA_KEEP_Msk                   (_UINT32_(0x1) << TCC_FCTRLA_KEEP_Pos)               /* (TCC_FCTRLA) Fault A Keeper Mask */
+#define TCC_FCTRLA_KEEP(value)                (TCC_FCTRLA_KEEP_Msk & (_UINT32_(value) << TCC_FCTRLA_KEEP_Pos)) /* Assignment of value for KEEP in the TCC_FCTRLA register */
+#define TCC_FCTRLA_QUAL_Pos                   _UINT32_(4)                                          /* (TCC_FCTRLA) Fault A Qualification Position */
+#define TCC_FCTRLA_QUAL_Msk                   (_UINT32_(0x1) << TCC_FCTRLA_QUAL_Pos)               /* (TCC_FCTRLA) Fault A Qualification Mask */
+#define TCC_FCTRLA_QUAL(value)                (TCC_FCTRLA_QUAL_Msk & (_UINT32_(value) << TCC_FCTRLA_QUAL_Pos)) /* Assignment of value for QUAL in the TCC_FCTRLA register */
+#define TCC_FCTRLA_BLANK_Pos                  _UINT32_(5)                                          /* (TCC_FCTRLA) Fault A Blanking Mode Position */
+#define TCC_FCTRLA_BLANK_Msk                  (_UINT32_(0x3) << TCC_FCTRLA_BLANK_Pos)              /* (TCC_FCTRLA) Fault A Blanking Mode Mask */
+#define TCC_FCTRLA_BLANK(value)               (TCC_FCTRLA_BLANK_Msk & (_UINT32_(value) << TCC_FCTRLA_BLANK_Pos)) /* Assignment of value for BLANK in the TCC_FCTRLA register */
+#define   TCC_FCTRLA_BLANK_START_Val          _UINT32_(0x0)                                        /* (TCC_FCTRLA) Blanking applied from start of the ramp  */
+#define   TCC_FCTRLA_BLANK_RISE_Val           _UINT32_(0x1)                                        /* (TCC_FCTRLA) Blanking applied from rising edge of the output waveform  */
+#define   TCC_FCTRLA_BLANK_FALL_Val           _UINT32_(0x2)                                        /* (TCC_FCTRLA) Blanking applied from falling edge of the output waveform  */
+#define   TCC_FCTRLA_BLANK_BOTH_Val           _UINT32_(0x3)                                        /* (TCC_FCTRLA) Blanking applied from each toggle of the output waveform  */
+#define TCC_FCTRLA_BLANK_START                (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos) /* (TCC_FCTRLA) Blanking applied from start of the ramp Position */
+#define TCC_FCTRLA_BLANK_RISE                 (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)  /* (TCC_FCTRLA) Blanking applied from rising edge of the output waveform Position */
+#define TCC_FCTRLA_BLANK_FALL                 (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)  /* (TCC_FCTRLA) Blanking applied from falling edge of the output waveform Position */
+#define TCC_FCTRLA_BLANK_BOTH                 (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)  /* (TCC_FCTRLA) Blanking applied from each toggle of the output waveform Position */
+#define TCC_FCTRLA_RESTART_Pos                _UINT32_(7)                                          /* (TCC_FCTRLA) Fault A Restart Position */
+#define TCC_FCTRLA_RESTART_Msk                (_UINT32_(0x1) << TCC_FCTRLA_RESTART_Pos)            /* (TCC_FCTRLA) Fault A Restart Mask */
+#define TCC_FCTRLA_RESTART(value)             (TCC_FCTRLA_RESTART_Msk & (_UINT32_(value) << TCC_FCTRLA_RESTART_Pos)) /* Assignment of value for RESTART in the TCC_FCTRLA register */
+#define TCC_FCTRLA_HALT_Pos                   _UINT32_(8)                                          /* (TCC_FCTRLA) Fault A Halt Mode Position */
+#define TCC_FCTRLA_HALT_Msk                   (_UINT32_(0x3) << TCC_FCTRLA_HALT_Pos)               /* (TCC_FCTRLA) Fault A Halt Mode Mask */
+#define TCC_FCTRLA_HALT(value)                (TCC_FCTRLA_HALT_Msk & (_UINT32_(value) << TCC_FCTRLA_HALT_Pos)) /* Assignment of value for HALT in the TCC_FCTRLA register */
+#define   TCC_FCTRLA_HALT_DISABLE_Val         _UINT32_(0x0)                                        /* (TCC_FCTRLA) Halt action disabled  */
+#define   TCC_FCTRLA_HALT_HW_Val              _UINT32_(0x1)                                        /* (TCC_FCTRLA) Hardware halt action  */
+#define   TCC_FCTRLA_HALT_SW_Val              _UINT32_(0x2)                                        /* (TCC_FCTRLA) Software halt action  */
+#define   TCC_FCTRLA_HALT_NR_Val              _UINT32_(0x3)                                        /* (TCC_FCTRLA) Non-recoverable fault  */
+#define TCC_FCTRLA_HALT_DISABLE               (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) /* (TCC_FCTRLA) Halt action disabled Position */
+#define TCC_FCTRLA_HALT_HW                    (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)      /* (TCC_FCTRLA) Hardware halt action Position */
+#define TCC_FCTRLA_HALT_SW                    (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)      /* (TCC_FCTRLA) Software halt action Position */
+#define TCC_FCTRLA_HALT_NR                    (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)      /* (TCC_FCTRLA) Non-recoverable fault Position */
+#define TCC_FCTRLA_CHSEL_Pos                  _UINT32_(10)                                         /* (TCC_FCTRLA) Fault A Capture Channel Position */
+#define TCC_FCTRLA_CHSEL_Msk                  (_UINT32_(0x3) << TCC_FCTRLA_CHSEL_Pos)              /* (TCC_FCTRLA) Fault A Capture Channel Mask */
+#define TCC_FCTRLA_CHSEL(value)               (TCC_FCTRLA_CHSEL_Msk & (_UINT32_(value) << TCC_FCTRLA_CHSEL_Pos)) /* Assignment of value for CHSEL in the TCC_FCTRLA register */
+#define   TCC_FCTRLA_CHSEL_CC0_Val            _UINT32_(0x0)                                        /* (TCC_FCTRLA) Capture value stored in channel 0  */
+#define   TCC_FCTRLA_CHSEL_CC1_Val            _UINT32_(0x1)                                        /* (TCC_FCTRLA) Capture value stored in channel 1  */
+#define   TCC_FCTRLA_CHSEL_CC2_Val            _UINT32_(0x2)                                        /* (TCC_FCTRLA) Capture value stored in channel 2  */
+#define   TCC_FCTRLA_CHSEL_CC3_Val            _UINT32_(0x3)                                        /* (TCC_FCTRLA) Capture value stored in channel 3  */
+#define TCC_FCTRLA_CHSEL_CC0                  (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)   /* (TCC_FCTRLA) Capture value stored in channel 0 Position */
+#define TCC_FCTRLA_CHSEL_CC1                  (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)   /* (TCC_FCTRLA) Capture value stored in channel 1 Position */
+#define TCC_FCTRLA_CHSEL_CC2                  (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)   /* (TCC_FCTRLA) Capture value stored in channel 2 Position */
+#define TCC_FCTRLA_CHSEL_CC3                  (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)   /* (TCC_FCTRLA) Capture value stored in channel 3 Position */
+#define TCC_FCTRLA_CAPTURE_Pos                _UINT32_(12)                                         /* (TCC_FCTRLA) Fault A Capture Action Position */
+#define TCC_FCTRLA_CAPTURE_Msk                (_UINT32_(0x7) << TCC_FCTRLA_CAPTURE_Pos)            /* (TCC_FCTRLA) Fault A Capture Action Mask */
+#define TCC_FCTRLA_CAPTURE(value)             (TCC_FCTRLA_CAPTURE_Msk & (_UINT32_(value) << TCC_FCTRLA_CAPTURE_Pos)) /* Assignment of value for CAPTURE in the TCC_FCTRLA register */
+#define   TCC_FCTRLA_CAPTURE_DISABLE_Val      _UINT32_(0x0)                                        /* (TCC_FCTRLA) No capture  */
+#define   TCC_FCTRLA_CAPTURE_CAPT_Val         _UINT32_(0x1)                                        /* (TCC_FCTRLA) Capture on fault  */
+#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val      _UINT32_(0x2)                                        /* (TCC_FCTRLA) Minimum capture  */
+#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val      _UINT32_(0x3)                                        /* (TCC_FCTRLA) Maximum capture  */
+#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val       _UINT32_(0x4)                                        /* (TCC_FCTRLA) Minimum local detection  */
+#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val       _UINT32_(0x5)                                        /* (TCC_FCTRLA) Maximum local detection  */
+#define   TCC_FCTRLA_CAPTURE_DERIV0_Val       _UINT32_(0x6)                                        /* (TCC_FCTRLA) Minimum and maximum local detection  */
+#define   TCC_FCTRLA_CAPTURE_CAPTMARK_Val     _UINT32_(0x7)                                        /* (TCC_FCTRLA) Capture with ramp index as MSB value  */
+#define TCC_FCTRLA_CAPTURE_DISABLE            (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) No capture Position */
+#define TCC_FCTRLA_CAPTURE_CAPT               (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Capture on fault Position */
+#define TCC_FCTRLA_CAPTURE_CAPTMIN            (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Minimum capture Position */
+#define TCC_FCTRLA_CAPTURE_CAPTMAX            (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Maximum capture Position */
+#define TCC_FCTRLA_CAPTURE_LOCMIN             (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Minimum local detection Position */
+#define TCC_FCTRLA_CAPTURE_LOCMAX             (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Maximum local detection Position */
+#define TCC_FCTRLA_CAPTURE_DERIV0             (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Minimum and maximum local detection Position */
+#define TCC_FCTRLA_CAPTURE_CAPTMARK           (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos) /* (TCC_FCTRLA) Capture with ramp index as MSB value Position */
+#define TCC_FCTRLA_BLANKPRESC_Pos             _UINT32_(15)                                         /* (TCC_FCTRLA) Fault A Blanking Prescaler Position */
+#define TCC_FCTRLA_BLANKPRESC_Msk             (_UINT32_(0x1) << TCC_FCTRLA_BLANKPRESC_Pos)         /* (TCC_FCTRLA) Fault A Blanking Prescaler Mask */
+#define TCC_FCTRLA_BLANKPRESC(value)          (TCC_FCTRLA_BLANKPRESC_Msk & (_UINT32_(value) << TCC_FCTRLA_BLANKPRESC_Pos)) /* Assignment of value for BLANKPRESC in the TCC_FCTRLA register */
+#define TCC_FCTRLA_BLANKVAL_Pos               _UINT32_(16)                                         /* (TCC_FCTRLA) Fault A Blanking Time Position */
+#define TCC_FCTRLA_BLANKVAL_Msk               (_UINT32_(0xFF) << TCC_FCTRLA_BLANKVAL_Pos)          /* (TCC_FCTRLA) Fault A Blanking Time Mask */
+#define TCC_FCTRLA_BLANKVAL(value)            (TCC_FCTRLA_BLANKVAL_Msk & (_UINT32_(value) << TCC_FCTRLA_BLANKVAL_Pos)) /* Assignment of value for BLANKVAL in the TCC_FCTRLA register */
+#define TCC_FCTRLA_FILTERVAL_Pos              _UINT32_(24)                                         /* (TCC_FCTRLA) Fault A Filter Value Position */
+#define TCC_FCTRLA_FILTERVAL_Msk              (_UINT32_(0xF) << TCC_FCTRLA_FILTERVAL_Pos)          /* (TCC_FCTRLA) Fault A Filter Value Mask */
+#define TCC_FCTRLA_FILTERVAL(value)           (TCC_FCTRLA_FILTERVAL_Msk & (_UINT32_(value) << TCC_FCTRLA_FILTERVAL_Pos)) /* Assignment of value for FILTERVAL in the TCC_FCTRLA register */
+#define TCC_FCTRLA_Msk                        _UINT32_(0x0FFFFFFB)                                 /* (TCC_FCTRLA) Register Mask  */
+
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#define TCC_FCTRLB_RESETVALUE                 _UINT32_(0x00)                                       /*  (TCC_FCTRLB) Recoverable Fault B Configuration  Reset Value */
+
+#define TCC_FCTRLB_SRC_Pos                    _UINT32_(0)                                          /* (TCC_FCTRLB) Fault B Source Position */
+#define TCC_FCTRLB_SRC_Msk                    (_UINT32_(0x3) << TCC_FCTRLB_SRC_Pos)                /* (TCC_FCTRLB) Fault B Source Mask */
+#define TCC_FCTRLB_SRC(value)                 (TCC_FCTRLB_SRC_Msk & (_UINT32_(value) << TCC_FCTRLB_SRC_Pos)) /* Assignment of value for SRC in the TCC_FCTRLB register */
+#define   TCC_FCTRLB_SRC_DISABLE_Val          _UINT32_(0x0)                                        /* (TCC_FCTRLB) Fault input disabled  */
+#define   TCC_FCTRLB_SRC_ENABLE_Val           _UINT32_(0x1)                                        /* (TCC_FCTRLB) MCEx (x=0,1) event input  */
+#define   TCC_FCTRLB_SRC_INVERT_Val           _UINT32_(0x2)                                        /* (TCC_FCTRLB) Inverted MCEx (x=0,1) event input  */
+#define   TCC_FCTRLB_SRC_ALTFAULT_Val         _UINT32_(0x3)                                        /* (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period  */
+#define TCC_FCTRLB_SRC_DISABLE                (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)   /* (TCC_FCTRLB) Fault input disabled Position */
+#define TCC_FCTRLB_SRC_ENABLE                 (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)    /* (TCC_FCTRLB) MCEx (x=0,1) event input Position */
+#define TCC_FCTRLB_SRC_INVERT                 (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)    /* (TCC_FCTRLB) Inverted MCEx (x=0,1) event input Position */
+#define TCC_FCTRLB_SRC_ALTFAULT               (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)  /* (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period Position */
+#define TCC_FCTRLB_KEEP_Pos                   _UINT32_(3)                                          /* (TCC_FCTRLB) Fault B Keeper Position */
+#define TCC_FCTRLB_KEEP_Msk                   (_UINT32_(0x1) << TCC_FCTRLB_KEEP_Pos)               /* (TCC_FCTRLB) Fault B Keeper Mask */
+#define TCC_FCTRLB_KEEP(value)                (TCC_FCTRLB_KEEP_Msk & (_UINT32_(value) << TCC_FCTRLB_KEEP_Pos)) /* Assignment of value for KEEP in the TCC_FCTRLB register */
+#define TCC_FCTRLB_QUAL_Pos                   _UINT32_(4)                                          /* (TCC_FCTRLB) Fault B Qualification Position */
+#define TCC_FCTRLB_QUAL_Msk                   (_UINT32_(0x1) << TCC_FCTRLB_QUAL_Pos)               /* (TCC_FCTRLB) Fault B Qualification Mask */
+#define TCC_FCTRLB_QUAL(value)                (TCC_FCTRLB_QUAL_Msk & (_UINT32_(value) << TCC_FCTRLB_QUAL_Pos)) /* Assignment of value for QUAL in the TCC_FCTRLB register */
+#define TCC_FCTRLB_BLANK_Pos                  _UINT32_(5)                                          /* (TCC_FCTRLB) Fault B Blanking Mode Position */
+#define TCC_FCTRLB_BLANK_Msk                  (_UINT32_(0x3) << TCC_FCTRLB_BLANK_Pos)              /* (TCC_FCTRLB) Fault B Blanking Mode Mask */
+#define TCC_FCTRLB_BLANK(value)               (TCC_FCTRLB_BLANK_Msk & (_UINT32_(value) << TCC_FCTRLB_BLANK_Pos)) /* Assignment of value for BLANK in the TCC_FCTRLB register */
+#define   TCC_FCTRLB_BLANK_START_Val          _UINT32_(0x0)                                        /* (TCC_FCTRLB) Blanking applied from start of the ramp  */
+#define   TCC_FCTRLB_BLANK_RISE_Val           _UINT32_(0x1)                                        /* (TCC_FCTRLB) Blanking applied from rising edge of the output waveform  */
+#define   TCC_FCTRLB_BLANK_FALL_Val           _UINT32_(0x2)                                        /* (TCC_FCTRLB) Blanking applied from falling edge of the output waveform  */
+#define   TCC_FCTRLB_BLANK_BOTH_Val           _UINT32_(0x3)                                        /* (TCC_FCTRLB) Blanking applied from each toggle of the output waveform  */
+#define TCC_FCTRLB_BLANK_START                (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos) /* (TCC_FCTRLB) Blanking applied from start of the ramp Position */
+#define TCC_FCTRLB_BLANK_RISE                 (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)  /* (TCC_FCTRLB) Blanking applied from rising edge of the output waveform Position */
+#define TCC_FCTRLB_BLANK_FALL                 (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)  /* (TCC_FCTRLB) Blanking applied from falling edge of the output waveform Position */
+#define TCC_FCTRLB_BLANK_BOTH                 (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)  /* (TCC_FCTRLB) Blanking applied from each toggle of the output waveform Position */
+#define TCC_FCTRLB_RESTART_Pos                _UINT32_(7)                                          /* (TCC_FCTRLB) Fault B Restart Position */
+#define TCC_FCTRLB_RESTART_Msk                (_UINT32_(0x1) << TCC_FCTRLB_RESTART_Pos)            /* (TCC_FCTRLB) Fault B Restart Mask */
+#define TCC_FCTRLB_RESTART(value)             (TCC_FCTRLB_RESTART_Msk & (_UINT32_(value) << TCC_FCTRLB_RESTART_Pos)) /* Assignment of value for RESTART in the TCC_FCTRLB register */
+#define TCC_FCTRLB_HALT_Pos                   _UINT32_(8)                                          /* (TCC_FCTRLB) Fault B Halt Mode Position */
+#define TCC_FCTRLB_HALT_Msk                   (_UINT32_(0x3) << TCC_FCTRLB_HALT_Pos)               /* (TCC_FCTRLB) Fault B Halt Mode Mask */
+#define TCC_FCTRLB_HALT(value)                (TCC_FCTRLB_HALT_Msk & (_UINT32_(value) << TCC_FCTRLB_HALT_Pos)) /* Assignment of value for HALT in the TCC_FCTRLB register */
+#define   TCC_FCTRLB_HALT_DISABLE_Val         _UINT32_(0x0)                                        /* (TCC_FCTRLB) Halt action disabled  */
+#define   TCC_FCTRLB_HALT_HW_Val              _UINT32_(0x1)                                        /* (TCC_FCTRLB) Hardware halt action  */
+#define   TCC_FCTRLB_HALT_SW_Val              _UINT32_(0x2)                                        /* (TCC_FCTRLB) Software halt action  */
+#define   TCC_FCTRLB_HALT_NR_Val              _UINT32_(0x3)                                        /* (TCC_FCTRLB) Non-recoverable fault  */
+#define TCC_FCTRLB_HALT_DISABLE               (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) /* (TCC_FCTRLB) Halt action disabled Position */
+#define TCC_FCTRLB_HALT_HW                    (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)      /* (TCC_FCTRLB) Hardware halt action Position */
+#define TCC_FCTRLB_HALT_SW                    (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)      /* (TCC_FCTRLB) Software halt action Position */
+#define TCC_FCTRLB_HALT_NR                    (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)      /* (TCC_FCTRLB) Non-recoverable fault Position */
+#define TCC_FCTRLB_CHSEL_Pos                  _UINT32_(10)                                         /* (TCC_FCTRLB) Fault B Capture Channel Position */
+#define TCC_FCTRLB_CHSEL_Msk                  (_UINT32_(0x3) << TCC_FCTRLB_CHSEL_Pos)              /* (TCC_FCTRLB) Fault B Capture Channel Mask */
+#define TCC_FCTRLB_CHSEL(value)               (TCC_FCTRLB_CHSEL_Msk & (_UINT32_(value) << TCC_FCTRLB_CHSEL_Pos)) /* Assignment of value for CHSEL in the TCC_FCTRLB register */
+#define   TCC_FCTRLB_CHSEL_CC0_Val            _UINT32_(0x0)                                        /* (TCC_FCTRLB) Capture value stored in channel 0  */
+#define   TCC_FCTRLB_CHSEL_CC1_Val            _UINT32_(0x1)                                        /* (TCC_FCTRLB) Capture value stored in channel 1  */
+#define   TCC_FCTRLB_CHSEL_CC2_Val            _UINT32_(0x2)                                        /* (TCC_FCTRLB) Capture value stored in channel 2  */
+#define   TCC_FCTRLB_CHSEL_CC3_Val            _UINT32_(0x3)                                        /* (TCC_FCTRLB) Capture value stored in channel 3  */
+#define TCC_FCTRLB_CHSEL_CC0                  (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)   /* (TCC_FCTRLB) Capture value stored in channel 0 Position */
+#define TCC_FCTRLB_CHSEL_CC1                  (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)   /* (TCC_FCTRLB) Capture value stored in channel 1 Position */
+#define TCC_FCTRLB_CHSEL_CC2                  (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)   /* (TCC_FCTRLB) Capture value stored in channel 2 Position */
+#define TCC_FCTRLB_CHSEL_CC3                  (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)   /* (TCC_FCTRLB) Capture value stored in channel 3 Position */
+#define TCC_FCTRLB_CAPTURE_Pos                _UINT32_(12)                                         /* (TCC_FCTRLB) Fault B Capture Action Position */
+#define TCC_FCTRLB_CAPTURE_Msk                (_UINT32_(0x7) << TCC_FCTRLB_CAPTURE_Pos)            /* (TCC_FCTRLB) Fault B Capture Action Mask */
+#define TCC_FCTRLB_CAPTURE(value)             (TCC_FCTRLB_CAPTURE_Msk & (_UINT32_(value) << TCC_FCTRLB_CAPTURE_Pos)) /* Assignment of value for CAPTURE in the TCC_FCTRLB register */
+#define   TCC_FCTRLB_CAPTURE_DISABLE_Val      _UINT32_(0x0)                                        /* (TCC_FCTRLB) No capture  */
+#define   TCC_FCTRLB_CAPTURE_CAPT_Val         _UINT32_(0x1)                                        /* (TCC_FCTRLB) Capture on fault  */
+#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val      _UINT32_(0x2)                                        /* (TCC_FCTRLB) Minimum capture  */
+#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val      _UINT32_(0x3)                                        /* (TCC_FCTRLB) Maximum capture  */
+#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val       _UINT32_(0x4)                                        /* (TCC_FCTRLB) Minimum local detection  */
+#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val       _UINT32_(0x5)                                        /* (TCC_FCTRLB) Maximum local detection  */
+#define   TCC_FCTRLB_CAPTURE_DERIV0_Val       _UINT32_(0x6)                                        /* (TCC_FCTRLB) Minimum and maximum local detection  */
+#define   TCC_FCTRLB_CAPTURE_CAPTMARK_Val     _UINT32_(0x7)                                        /* (TCC_FCTRLB) Capture with ramp index as MSB value  */
+#define TCC_FCTRLB_CAPTURE_DISABLE            (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) No capture Position */
+#define TCC_FCTRLB_CAPTURE_CAPT               (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Capture on fault Position */
+#define TCC_FCTRLB_CAPTURE_CAPTMIN            (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Minimum capture Position */
+#define TCC_FCTRLB_CAPTURE_CAPTMAX            (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Maximum capture Position */
+#define TCC_FCTRLB_CAPTURE_LOCMIN             (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Minimum local detection Position */
+#define TCC_FCTRLB_CAPTURE_LOCMAX             (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Maximum local detection Position */
+#define TCC_FCTRLB_CAPTURE_DERIV0             (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Minimum and maximum local detection Position */
+#define TCC_FCTRLB_CAPTURE_CAPTMARK           (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos) /* (TCC_FCTRLB) Capture with ramp index as MSB value Position */
+#define TCC_FCTRLB_BLANKPRESC_Pos             _UINT32_(15)                                         /* (TCC_FCTRLB) Fault B Blanking Prescaler Position */
+#define TCC_FCTRLB_BLANKPRESC_Msk             (_UINT32_(0x1) << TCC_FCTRLB_BLANKPRESC_Pos)         /* (TCC_FCTRLB) Fault B Blanking Prescaler Mask */
+#define TCC_FCTRLB_BLANKPRESC(value)          (TCC_FCTRLB_BLANKPRESC_Msk & (_UINT32_(value) << TCC_FCTRLB_BLANKPRESC_Pos)) /* Assignment of value for BLANKPRESC in the TCC_FCTRLB register */
+#define TCC_FCTRLB_BLANKVAL_Pos               _UINT32_(16)                                         /* (TCC_FCTRLB) Fault B Blanking Time Position */
+#define TCC_FCTRLB_BLANKVAL_Msk               (_UINT32_(0xFF) << TCC_FCTRLB_BLANKVAL_Pos)          /* (TCC_FCTRLB) Fault B Blanking Time Mask */
+#define TCC_FCTRLB_BLANKVAL(value)            (TCC_FCTRLB_BLANKVAL_Msk & (_UINT32_(value) << TCC_FCTRLB_BLANKVAL_Pos)) /* Assignment of value for BLANKVAL in the TCC_FCTRLB register */
+#define TCC_FCTRLB_FILTERVAL_Pos              _UINT32_(24)                                         /* (TCC_FCTRLB) Fault B Filter Value Position */
+#define TCC_FCTRLB_FILTERVAL_Msk              (_UINT32_(0xF) << TCC_FCTRLB_FILTERVAL_Pos)          /* (TCC_FCTRLB) Fault B Filter Value Mask */
+#define TCC_FCTRLB_FILTERVAL(value)           (TCC_FCTRLB_FILTERVAL_Msk & (_UINT32_(value) << TCC_FCTRLB_FILTERVAL_Pos)) /* Assignment of value for FILTERVAL in the TCC_FCTRLB register */
+#define TCC_FCTRLB_Msk                        _UINT32_(0x0FFFFFFB)                                 /* (TCC_FCTRLB) Register Mask  */
+
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#define TCC_DRVCTRL_RESETVALUE                _UINT32_(0x00)                                       /*  (TCC_DRVCTRL) Driver Control  Reset Value */
+
+#define TCC_DRVCTRL_NRE0_Pos                  _UINT32_(0)                                          /* (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable Position */
+#define TCC_DRVCTRL_NRE0_Msk                  (_UINT32_(0x1) << TCC_DRVCTRL_NRE0_Pos)              /* (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable Mask */
+#define TCC_DRVCTRL_NRE0(value)               (TCC_DRVCTRL_NRE0_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE0_Pos)) /* Assignment of value for NRE0 in the TCC_DRVCTRL register */
+#define TCC_DRVCTRL_NRE1_Pos                  _UINT32_(1)                                          /* (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable Position */
+#define TCC_DRVCTRL_NRE1_Msk                  (_UINT32_(0x1) << TCC_DRVCTRL_NRE1_Pos)              /* (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable Mask */
+#define TCC_DRVCTRL_NRE1(value)               (TCC_DRVCTRL_NRE1_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE1_Pos)) /* Assignment of value for NRE1 in the TCC_DRVCTRL register */
+#define TCC_DRVCTRL_NRV0_Pos                  _UINT32_(8)                                          /* (TCC_DRVCTRL) Non-Recoverable State 0 Output Value Position */
+#define TCC_DRVCTRL_NRV0_Msk                  (_UINT32_(0x1) << TCC_DRVCTRL_NRV0_Pos)              /* (TCC_DRVCTRL) Non-Recoverable State 0 Output Value Mask */
+#define TCC_DRVCTRL_NRV0(value)               (TCC_DRVCTRL_NRV0_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV0_Pos)) /* Assignment of value for NRV0 in the TCC_DRVCTRL register */
+#define TCC_DRVCTRL_NRV1_Pos                  _UINT32_(9)                                          /* (TCC_DRVCTRL) Non-Recoverable State 1 Output Value Position */
+#define TCC_DRVCTRL_NRV1_Msk                  (_UINT32_(0x1) << TCC_DRVCTRL_NRV1_Pos)              /* (TCC_DRVCTRL) Non-Recoverable State 1 Output Value Mask */
+#define TCC_DRVCTRL_NRV1(value)               (TCC_DRVCTRL_NRV1_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV1_Pos)) /* Assignment of value for NRV1 in the TCC_DRVCTRL register */
+#define TCC_DRVCTRL_INVEN0_Pos                _UINT32_(16)                                         /* (TCC_DRVCTRL) Output Waveform 0 Inversion Position */
+#define TCC_DRVCTRL_INVEN0_Msk                (_UINT32_(0x1) << TCC_DRVCTRL_INVEN0_Pos)            /* (TCC_DRVCTRL) Output Waveform 0 Inversion Mask */
+#define TCC_DRVCTRL_INVEN0(value)             (TCC_DRVCTRL_INVEN0_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN0_Pos)) /* Assignment of value for INVEN0 in the TCC_DRVCTRL register */
+#define TCC_DRVCTRL_INVEN1_Pos                _UINT32_(17)                                         /* (TCC_DRVCTRL) Output Waveform 1 Inversion Position */
+#define TCC_DRVCTRL_INVEN1_Msk                (_UINT32_(0x1) << TCC_DRVCTRL_INVEN1_Pos)            /* (TCC_DRVCTRL) Output Waveform 1 Inversion Mask */
+#define TCC_DRVCTRL_INVEN1(value)             (TCC_DRVCTRL_INVEN1_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN1_Pos)) /* Assignment of value for INVEN1 in the TCC_DRVCTRL register */
+#define TCC_DRVCTRL_FILTERVAL0_Pos            _UINT32_(24)                                         /* (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value Position */
+#define TCC_DRVCTRL_FILTERVAL0_Msk            (_UINT32_(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos)        /* (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value Mask */
+#define TCC_DRVCTRL_FILTERVAL0(value)         (TCC_DRVCTRL_FILTERVAL0_Msk & (_UINT32_(value) << TCC_DRVCTRL_FILTERVAL0_Pos)) /* Assignment of value for FILTERVAL0 in the TCC_DRVCTRL register */
+#define TCC_DRVCTRL_FILTERVAL1_Pos            _UINT32_(28)                                         /* (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value Position */
+#define TCC_DRVCTRL_FILTERVAL1_Msk            (_UINT32_(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos)        /* (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value Mask */
+#define TCC_DRVCTRL_FILTERVAL1(value)         (TCC_DRVCTRL_FILTERVAL1_Msk & (_UINT32_(value) << TCC_DRVCTRL_FILTERVAL1_Pos)) /* Assignment of value for FILTERVAL1 in the TCC_DRVCTRL register */
+#define TCC_DRVCTRL_Msk                       _UINT32_(0xFF030303)                                 /* (TCC_DRVCTRL) Register Mask  */
+
+#define TCC_DRVCTRL_NRE_Pos                   _UINT32_(0)                                          /* (TCC_DRVCTRL Position) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk                   (_UINT32_(0x3) << TCC_DRVCTRL_NRE_Pos)               /* (TCC_DRVCTRL Mask) NRE */
+#define TCC_DRVCTRL_NRE(value)                (TCC_DRVCTRL_NRE_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRE_Pos)) 
+#define TCC_DRVCTRL_NRV_Pos                   _UINT32_(8)                                          /* (TCC_DRVCTRL Position) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk                   (_UINT32_(0x3) << TCC_DRVCTRL_NRV_Pos)               /* (TCC_DRVCTRL Mask) NRV */
+#define TCC_DRVCTRL_NRV(value)                (TCC_DRVCTRL_NRV_Msk & (_UINT32_(value) << TCC_DRVCTRL_NRV_Pos)) 
+#define TCC_DRVCTRL_INVEN_Pos                 _UINT32_(16)                                         /* (TCC_DRVCTRL Position) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk                 (_UINT32_(0x3) << TCC_DRVCTRL_INVEN_Pos)             /* (TCC_DRVCTRL Mask) INVEN */
+#define TCC_DRVCTRL_INVEN(value)              (TCC_DRVCTRL_INVEN_Msk & (_UINT32_(value) << TCC_DRVCTRL_INVEN_Pos)) 
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
+#define TCC_DBGCTRL_RESETVALUE                _UINT8_(0x00)                                        /*  (TCC_DBGCTRL) Debug Control  Reset Value */
+
+#define TCC_DBGCTRL_DBGRUN_Pos                _UINT8_(0)                                           /* (TCC_DBGCTRL) Debug Running Mode Position */
+#define TCC_DBGCTRL_DBGRUN_Msk                (_UINT8_(0x1) << TCC_DBGCTRL_DBGRUN_Pos)             /* (TCC_DBGCTRL) Debug Running Mode Mask */
+#define TCC_DBGCTRL_DBGRUN(value)             (TCC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << TCC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the TCC_DBGCTRL register */
+#define TCC_DBGCTRL_FDDBD_Pos                 _UINT8_(2)                                           /* (TCC_DBGCTRL) Fault Detection on Debug Break Detection Position */
+#define TCC_DBGCTRL_FDDBD_Msk                 (_UINT8_(0x1) << TCC_DBGCTRL_FDDBD_Pos)              /* (TCC_DBGCTRL) Fault Detection on Debug Break Detection Mask */
+#define TCC_DBGCTRL_FDDBD(value)              (TCC_DBGCTRL_FDDBD_Msk & (_UINT8_(value) << TCC_DBGCTRL_FDDBD_Pos)) /* Assignment of value for FDDBD in the TCC_DBGCTRL register */
+#define TCC_DBGCTRL_Msk                       _UINT8_(0x05)                                        /* (TCC_DBGCTRL) Register Mask  */
+
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#define TCC_EVCTRL_RESETVALUE                 _UINT32_(0x00)                                       /*  (TCC_EVCTRL) Event Control  Reset Value */
+
+#define TCC_EVCTRL_EVACT0_Pos                 _UINT32_(0)                                          /* (TCC_EVCTRL) Timer/counter Input Event0 Action Position */
+#define TCC_EVCTRL_EVACT0_Msk                 (_UINT32_(0x7) << TCC_EVCTRL_EVACT0_Pos)             /* (TCC_EVCTRL) Timer/counter Input Event0 Action Mask */
+#define TCC_EVCTRL_EVACT0(value)              (TCC_EVCTRL_EVACT0_Msk & (_UINT32_(value) << TCC_EVCTRL_EVACT0_Pos)) /* Assignment of value for EVACT0 in the TCC_EVCTRL register */
+#define   TCC_EVCTRL_EVACT0_OFF_Val           _UINT32_(0x0)                                        /* (TCC_EVCTRL) Event action disabled  */
+#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val     _UINT32_(0x1)                                        /* (TCC_EVCTRL) Start, restart or re-trigger counter on event  */
+#define   TCC_EVCTRL_EVACT0_COUNTEV_Val       _UINT32_(0x2)                                        /* (TCC_EVCTRL) Count on event  */
+#define   TCC_EVCTRL_EVACT0_START_Val         _UINT32_(0x3)                                        /* (TCC_EVCTRL) Start counter on event  */
+#define   TCC_EVCTRL_EVACT0_INC_Val           _UINT32_(0x4)                                        /* (TCC_EVCTRL) Increment counter on event  */
+#define   TCC_EVCTRL_EVACT0_COUNT_Val         _UINT32_(0x5)                                        /* (TCC_EVCTRL) Count on active state of asynchronous event  */
+#define   TCC_EVCTRL_EVACT0_STAMP_Val         _UINT32_(0x6)                                        /* (TCC_EVCTRL) Stamp capture  */
+#define   TCC_EVCTRL_EVACT0_FAULT_Val         _UINT32_(0x7)                                        /* (TCC_EVCTRL) Non-recoverable fault  */
+#define TCC_EVCTRL_EVACT0_OFF                 (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Event action disabled Position */
+#define TCC_EVCTRL_EVACT0_RETRIGGER           (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Start, restart or re-trigger counter on event Position */
+#define TCC_EVCTRL_EVACT0_COUNTEV             (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Count on event Position */
+#define TCC_EVCTRL_EVACT0_START               (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Start counter on event Position */
+#define TCC_EVCTRL_EVACT0_INC                 (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Increment counter on event Position */
+#define TCC_EVCTRL_EVACT0_COUNT               (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Count on active state of asynchronous event Position */
+#define TCC_EVCTRL_EVACT0_STAMP               (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Stamp capture Position */
+#define TCC_EVCTRL_EVACT0_FAULT               (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) /* (TCC_EVCTRL) Non-recoverable fault Position */
+#define TCC_EVCTRL_EVACT1_Pos                 _UINT32_(3)                                          /* (TCC_EVCTRL) Timer/counter Input Event1 Action Position */
+#define TCC_EVCTRL_EVACT1_Msk                 (_UINT32_(0x7) << TCC_EVCTRL_EVACT1_Pos)             /* (TCC_EVCTRL) Timer/counter Input Event1 Action Mask */
+#define TCC_EVCTRL_EVACT1(value)              (TCC_EVCTRL_EVACT1_Msk & (_UINT32_(value) << TCC_EVCTRL_EVACT1_Pos)) /* Assignment of value for EVACT1 in the TCC_EVCTRL register */
+#define   TCC_EVCTRL_EVACT1_OFF_Val           _UINT32_(0x0)                                        /* (TCC_EVCTRL) Event action disabled  */
+#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val     _UINT32_(0x1)                                        /* (TCC_EVCTRL) Re-trigger counter on event  */
+#define   TCC_EVCTRL_EVACT1_DIR_Val           _UINT32_(0x2)                                        /* (TCC_EVCTRL) Direction control  */
+#define   TCC_EVCTRL_EVACT1_STOP_Val          _UINT32_(0x3)                                        /* (TCC_EVCTRL) Stop counter on event  */
+#define   TCC_EVCTRL_EVACT1_DEC_Val           _UINT32_(0x4)                                        /* (TCC_EVCTRL) Decrement counter on event  */
+#define   TCC_EVCTRL_EVACT1_PWP_Val           _UINT32_(0x6)                                        /* (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register  */
+#define   TCC_EVCTRL_EVACT1_FAULT_Val         _UINT32_(0x7)                                        /* (TCC_EVCTRL) Non-recoverable fault  */
+#define TCC_EVCTRL_EVACT1_OFF                 (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Event action disabled Position */
+#define TCC_EVCTRL_EVACT1_RETRIGGER           (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Re-trigger counter on event Position */
+#define TCC_EVCTRL_EVACT1_DIR                 (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Direction control Position */
+#define TCC_EVCTRL_EVACT1_STOP                (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Stop counter on event Position */
+#define TCC_EVCTRL_EVACT1_DEC                 (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Decrement counter on event Position */
+#define TCC_EVCTRL_EVACT1_PWP                 (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register Position */
+#define TCC_EVCTRL_EVACT1_FAULT               (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) /* (TCC_EVCTRL) Non-recoverable fault Position */
+#define TCC_EVCTRL_CNTSEL_Pos                 _UINT32_(6)                                          /* (TCC_EVCTRL) Timer/counter Output Event Mode Position */
+#define TCC_EVCTRL_CNTSEL_Msk                 (_UINT32_(0x3) << TCC_EVCTRL_CNTSEL_Pos)             /* (TCC_EVCTRL) Timer/counter Output Event Mode Mask */
+#define TCC_EVCTRL_CNTSEL(value)              (TCC_EVCTRL_CNTSEL_Msk & (_UINT32_(value) << TCC_EVCTRL_CNTSEL_Pos)) /* Assignment of value for CNTSEL in the TCC_EVCTRL register */
+#define   TCC_EVCTRL_CNTSEL_START_Val         _UINT32_(0x0)                                        /* (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts  */
+#define   TCC_EVCTRL_CNTSEL_END_Val           _UINT32_(0x1)                                        /* (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends  */
+#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val      _UINT32_(0x3)                                        /* (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends  */
+#define TCC_EVCTRL_CNTSEL_START               (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) /* (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts Position */
+#define TCC_EVCTRL_CNTSEL_END                 (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) /* (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends Position */
+#define TCC_EVCTRL_CNTSEL_BOUNDARY            (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) /* (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends Position */
+#define TCC_EVCTRL_OVFEO_Pos                  _UINT32_(8)                                          /* (TCC_EVCTRL) Overflow/Underflow Output Event Enable Position */
+#define TCC_EVCTRL_OVFEO_Msk                  (_UINT32_(0x1) << TCC_EVCTRL_OVFEO_Pos)              /* (TCC_EVCTRL) Overflow/Underflow Output Event Enable Mask */
+#define TCC_EVCTRL_OVFEO(value)               (TCC_EVCTRL_OVFEO_Msk & (_UINT32_(value) << TCC_EVCTRL_OVFEO_Pos)) /* Assignment of value for OVFEO in the TCC_EVCTRL register */
+#define TCC_EVCTRL_TRGEO_Pos                  _UINT32_(9)                                          /* (TCC_EVCTRL) Retrigger Output Event Enable Position */
+#define TCC_EVCTRL_TRGEO_Msk                  (_UINT32_(0x1) << TCC_EVCTRL_TRGEO_Pos)              /* (TCC_EVCTRL) Retrigger Output Event Enable Mask */
+#define TCC_EVCTRL_TRGEO(value)               (TCC_EVCTRL_TRGEO_Msk & (_UINT32_(value) << TCC_EVCTRL_TRGEO_Pos)) /* Assignment of value for TRGEO in the TCC_EVCTRL register */
+#define TCC_EVCTRL_CNTEO_Pos                  _UINT32_(10)                                         /* (TCC_EVCTRL) Timer/counter Output Event Enable Position */
+#define TCC_EVCTRL_CNTEO_Msk                  (_UINT32_(0x1) << TCC_EVCTRL_CNTEO_Pos)              /* (TCC_EVCTRL) Timer/counter Output Event Enable Mask */
+#define TCC_EVCTRL_CNTEO(value)               (TCC_EVCTRL_CNTEO_Msk & (_UINT32_(value) << TCC_EVCTRL_CNTEO_Pos)) /* Assignment of value for CNTEO in the TCC_EVCTRL register */
+#define TCC_EVCTRL_TCINV0_Pos                 _UINT32_(12)                                         /* (TCC_EVCTRL) Inverted Event 0 Input Enable Position */
+#define TCC_EVCTRL_TCINV0_Msk                 (_UINT32_(0x1) << TCC_EVCTRL_TCINV0_Pos)             /* (TCC_EVCTRL) Inverted Event 0 Input Enable Mask */
+#define TCC_EVCTRL_TCINV0(value)              (TCC_EVCTRL_TCINV0_Msk & (_UINT32_(value) << TCC_EVCTRL_TCINV0_Pos)) /* Assignment of value for TCINV0 in the TCC_EVCTRL register */
+#define TCC_EVCTRL_TCINV1_Pos                 _UINT32_(13)                                         /* (TCC_EVCTRL) Inverted Event 1 Input Enable Position */
+#define TCC_EVCTRL_TCINV1_Msk                 (_UINT32_(0x1) << TCC_EVCTRL_TCINV1_Pos)             /* (TCC_EVCTRL) Inverted Event 1 Input Enable Mask */
+#define TCC_EVCTRL_TCINV1(value)              (TCC_EVCTRL_TCINV1_Msk & (_UINT32_(value) << TCC_EVCTRL_TCINV1_Pos)) /* Assignment of value for TCINV1 in the TCC_EVCTRL register */
+#define TCC_EVCTRL_TCEI0_Pos                  _UINT32_(14)                                         /* (TCC_EVCTRL) Timer/counter Event 0 Input Enable Position */
+#define TCC_EVCTRL_TCEI0_Msk                  (_UINT32_(0x1) << TCC_EVCTRL_TCEI0_Pos)              /* (TCC_EVCTRL) Timer/counter Event 0 Input Enable Mask */
+#define TCC_EVCTRL_TCEI0(value)               (TCC_EVCTRL_TCEI0_Msk & (_UINT32_(value) << TCC_EVCTRL_TCEI0_Pos)) /* Assignment of value for TCEI0 in the TCC_EVCTRL register */
+#define TCC_EVCTRL_TCEI1_Pos                  _UINT32_(15)                                         /* (TCC_EVCTRL) Timer/counter Event 1 Input Enable Position */
+#define TCC_EVCTRL_TCEI1_Msk                  (_UINT32_(0x1) << TCC_EVCTRL_TCEI1_Pos)              /* (TCC_EVCTRL) Timer/counter Event 1 Input Enable Mask */
+#define TCC_EVCTRL_TCEI1(value)               (TCC_EVCTRL_TCEI1_Msk & (_UINT32_(value) << TCC_EVCTRL_TCEI1_Pos)) /* Assignment of value for TCEI1 in the TCC_EVCTRL register */
+#define TCC_EVCTRL_MCEI0_Pos                  _UINT32_(16)                                         /* (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable Position */
+#define TCC_EVCTRL_MCEI0_Msk                  (_UINT32_(0x1) << TCC_EVCTRL_MCEI0_Pos)              /* (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable Mask */
+#define TCC_EVCTRL_MCEI0(value)               (TCC_EVCTRL_MCEI0_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEI0_Pos)) /* Assignment of value for MCEI0 in the TCC_EVCTRL register */
+#define TCC_EVCTRL_MCEI1_Pos                  _UINT32_(17)                                         /* (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable Position */
+#define TCC_EVCTRL_MCEI1_Msk                  (_UINT32_(0x1) << TCC_EVCTRL_MCEI1_Pos)              /* (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable Mask */
+#define TCC_EVCTRL_MCEI1(value)               (TCC_EVCTRL_MCEI1_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEI1_Pos)) /* Assignment of value for MCEI1 in the TCC_EVCTRL register */
+#define TCC_EVCTRL_MCEO0_Pos                  _UINT32_(24)                                         /* (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable Position */
+#define TCC_EVCTRL_MCEO0_Msk                  (_UINT32_(0x1) << TCC_EVCTRL_MCEO0_Pos)              /* (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable Mask */
+#define TCC_EVCTRL_MCEO0(value)               (TCC_EVCTRL_MCEO0_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEO0_Pos)) /* Assignment of value for MCEO0 in the TCC_EVCTRL register */
+#define TCC_EVCTRL_MCEO1_Pos                  _UINT32_(25)                                         /* (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable Position */
+#define TCC_EVCTRL_MCEO1_Msk                  (_UINT32_(0x1) << TCC_EVCTRL_MCEO1_Pos)              /* (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable Mask */
+#define TCC_EVCTRL_MCEO1(value)               (TCC_EVCTRL_MCEO1_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEO1_Pos)) /* Assignment of value for MCEO1 in the TCC_EVCTRL register */
+#define TCC_EVCTRL_Msk                        _UINT32_(0x0303F7FF)                                 /* (TCC_EVCTRL) Register Mask  */
+
+#define TCC_EVCTRL_TCINV_Pos                  _UINT32_(12)                                         /* (TCC_EVCTRL Position) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk                  (_UINT32_(0x3) << TCC_EVCTRL_TCINV_Pos)              /* (TCC_EVCTRL Mask) TCINV */
+#define TCC_EVCTRL_TCINV(value)               (TCC_EVCTRL_TCINV_Msk & (_UINT32_(value) << TCC_EVCTRL_TCINV_Pos)) 
+#define TCC_EVCTRL_TCEI_Pos                   _UINT32_(14)                                         /* (TCC_EVCTRL Position) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk                   (_UINT32_(0x3) << TCC_EVCTRL_TCEI_Pos)               /* (TCC_EVCTRL Mask) TCEI */
+#define TCC_EVCTRL_TCEI(value)                (TCC_EVCTRL_TCEI_Msk & (_UINT32_(value) << TCC_EVCTRL_TCEI_Pos)) 
+#define TCC_EVCTRL_MCEI_Pos                   _UINT32_(16)                                         /* (TCC_EVCTRL Position) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk                   (_UINT32_(0x3) << TCC_EVCTRL_MCEI_Pos)               /* (TCC_EVCTRL Mask) MCEI */
+#define TCC_EVCTRL_MCEI(value)                (TCC_EVCTRL_MCEI_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEI_Pos)) 
+#define TCC_EVCTRL_MCEO_Pos                   _UINT32_(24)                                         /* (TCC_EVCTRL Position) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk                   (_UINT32_(0x3) << TCC_EVCTRL_MCEO_Pos)               /* (TCC_EVCTRL Mask) MCEO */
+#define TCC_EVCTRL_MCEO(value)                (TCC_EVCTRL_MCEO_Msk & (_UINT32_(value) << TCC_EVCTRL_MCEO_Pos)) 
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#define TCC_INTENCLR_RESETVALUE               _UINT32_(0x00)                                       /*  (TCC_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define TCC_INTENCLR_OVF_Pos                  _UINT32_(0)                                          /* (TCC_INTENCLR) Overflow Interrupt Enable Position */
+#define TCC_INTENCLR_OVF_Msk                  (_UINT32_(0x1) << TCC_INTENCLR_OVF_Pos)              /* (TCC_INTENCLR) Overflow Interrupt Enable Mask */
+#define TCC_INTENCLR_OVF(value)               (TCC_INTENCLR_OVF_Msk & (_UINT32_(value) << TCC_INTENCLR_OVF_Pos)) /* Assignment of value for OVF in the TCC_INTENCLR register */
+#define TCC_INTENCLR_TRG_Pos                  _UINT32_(1)                                          /* (TCC_INTENCLR) Retrigger Interrupt Enable Position */
+#define TCC_INTENCLR_TRG_Msk                  (_UINT32_(0x1) << TCC_INTENCLR_TRG_Pos)              /* (TCC_INTENCLR) Retrigger Interrupt Enable Mask */
+#define TCC_INTENCLR_TRG(value)               (TCC_INTENCLR_TRG_Msk & (_UINT32_(value) << TCC_INTENCLR_TRG_Pos)) /* Assignment of value for TRG in the TCC_INTENCLR register */
+#define TCC_INTENCLR_CNT_Pos                  _UINT32_(2)                                          /* (TCC_INTENCLR) Counter Interrupt Enable Position */
+#define TCC_INTENCLR_CNT_Msk                  (_UINT32_(0x1) << TCC_INTENCLR_CNT_Pos)              /* (TCC_INTENCLR) Counter Interrupt Enable Mask */
+#define TCC_INTENCLR_CNT(value)               (TCC_INTENCLR_CNT_Msk & (_UINT32_(value) << TCC_INTENCLR_CNT_Pos)) /* Assignment of value for CNT in the TCC_INTENCLR register */
+#define TCC_INTENCLR_ERR_Pos                  _UINT32_(3)                                          /* (TCC_INTENCLR) Error Interrupt Enable Position */
+#define TCC_INTENCLR_ERR_Msk                  (_UINT32_(0x1) << TCC_INTENCLR_ERR_Pos)              /* (TCC_INTENCLR) Error Interrupt Enable Mask */
+#define TCC_INTENCLR_ERR(value)               (TCC_INTENCLR_ERR_Msk & (_UINT32_(value) << TCC_INTENCLR_ERR_Pos)) /* Assignment of value for ERR in the TCC_INTENCLR register */
+#define TCC_INTENCLR_UFS_Pos                  _UINT32_(10)                                         /* (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable Position */
+#define TCC_INTENCLR_UFS_Msk                  (_UINT32_(0x1) << TCC_INTENCLR_UFS_Pos)              /* (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable Mask */
+#define TCC_INTENCLR_UFS(value)               (TCC_INTENCLR_UFS_Msk & (_UINT32_(value) << TCC_INTENCLR_UFS_Pos)) /* Assignment of value for UFS in the TCC_INTENCLR register */
+#define TCC_INTENCLR_DFS_Pos                  _UINT32_(11)                                         /* (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable Position */
+#define TCC_INTENCLR_DFS_Msk                  (_UINT32_(0x1) << TCC_INTENCLR_DFS_Pos)              /* (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable Mask */
+#define TCC_INTENCLR_DFS(value)               (TCC_INTENCLR_DFS_Msk & (_UINT32_(value) << TCC_INTENCLR_DFS_Pos)) /* Assignment of value for DFS in the TCC_INTENCLR register */
+#define TCC_INTENCLR_FAULTA_Pos               _UINT32_(12)                                         /* (TCC_INTENCLR) Recoverable Fault A Interrupt Enable Position */
+#define TCC_INTENCLR_FAULTA_Msk               (_UINT32_(0x1) << TCC_INTENCLR_FAULTA_Pos)           /* (TCC_INTENCLR) Recoverable Fault A Interrupt Enable Mask */
+#define TCC_INTENCLR_FAULTA(value)            (TCC_INTENCLR_FAULTA_Msk & (_UINT32_(value) << TCC_INTENCLR_FAULTA_Pos)) /* Assignment of value for FAULTA in the TCC_INTENCLR register */
+#define TCC_INTENCLR_FAULTB_Pos               _UINT32_(13)                                         /* (TCC_INTENCLR) Recoverable Fault B Interrupt Enable Position */
+#define TCC_INTENCLR_FAULTB_Msk               (_UINT32_(0x1) << TCC_INTENCLR_FAULTB_Pos)           /* (TCC_INTENCLR) Recoverable Fault B Interrupt Enable Mask */
+#define TCC_INTENCLR_FAULTB(value)            (TCC_INTENCLR_FAULTB_Msk & (_UINT32_(value) << TCC_INTENCLR_FAULTB_Pos)) /* Assignment of value for FAULTB in the TCC_INTENCLR register */
+#define TCC_INTENCLR_FAULT0_Pos               _UINT32_(14)                                         /* (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable Position */
+#define TCC_INTENCLR_FAULT0_Msk               (_UINT32_(0x1) << TCC_INTENCLR_FAULT0_Pos)           /* (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable Mask */
+#define TCC_INTENCLR_FAULT0(value)            (TCC_INTENCLR_FAULT0_Msk & (_UINT32_(value) << TCC_INTENCLR_FAULT0_Pos)) /* Assignment of value for FAULT0 in the TCC_INTENCLR register */
+#define TCC_INTENCLR_FAULT1_Pos               _UINT32_(15)                                         /* (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable Position */
+#define TCC_INTENCLR_FAULT1_Msk               (_UINT32_(0x1) << TCC_INTENCLR_FAULT1_Pos)           /* (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable Mask */
+#define TCC_INTENCLR_FAULT1(value)            (TCC_INTENCLR_FAULT1_Msk & (_UINT32_(value) << TCC_INTENCLR_FAULT1_Pos)) /* Assignment of value for FAULT1 in the TCC_INTENCLR register */
+#define TCC_INTENCLR_MC0_Pos                  _UINT32_(16)                                         /* (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable Position */
+#define TCC_INTENCLR_MC0_Msk                  (_UINT32_(0x1) << TCC_INTENCLR_MC0_Pos)              /* (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable Mask */
+#define TCC_INTENCLR_MC0(value)               (TCC_INTENCLR_MC0_Msk & (_UINT32_(value) << TCC_INTENCLR_MC0_Pos)) /* Assignment of value for MC0 in the TCC_INTENCLR register */
+#define TCC_INTENCLR_MC1_Pos                  _UINT32_(17)                                         /* (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable Position */
+#define TCC_INTENCLR_MC1_Msk                  (_UINT32_(0x1) << TCC_INTENCLR_MC1_Pos)              /* (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable Mask */
+#define TCC_INTENCLR_MC1(value)               (TCC_INTENCLR_MC1_Msk & (_UINT32_(value) << TCC_INTENCLR_MC1_Pos)) /* Assignment of value for MC1 in the TCC_INTENCLR register */
+#define TCC_INTENCLR_Msk                      _UINT32_(0x0003FC0F)                                 /* (TCC_INTENCLR) Register Mask  */
+
+#define TCC_INTENCLR_FAULT_Pos                _UINT32_(14)                                         /* (TCC_INTENCLR Position) Non-Recoverable Fault x Interrupt Enable */
+#define TCC_INTENCLR_FAULT_Msk                (_UINT32_(0x3) << TCC_INTENCLR_FAULT_Pos)            /* (TCC_INTENCLR Mask) FAULT */
+#define TCC_INTENCLR_FAULT(value)             (TCC_INTENCLR_FAULT_Msk & (_UINT32_(value) << TCC_INTENCLR_FAULT_Pos)) 
+#define TCC_INTENCLR_MC_Pos                   _UINT32_(16)                                         /* (TCC_INTENCLR Position) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk                   (_UINT32_(0x3) << TCC_INTENCLR_MC_Pos)               /* (TCC_INTENCLR Mask) MC */
+#define TCC_INTENCLR_MC(value)                (TCC_INTENCLR_MC_Msk & (_UINT32_(value) << TCC_INTENCLR_MC_Pos)) 
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#define TCC_INTENSET_RESETVALUE               _UINT32_(0x00)                                       /*  (TCC_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define TCC_INTENSET_OVF_Pos                  _UINT32_(0)                                          /* (TCC_INTENSET) Overflow Interrupt Enable Position */
+#define TCC_INTENSET_OVF_Msk                  (_UINT32_(0x1) << TCC_INTENSET_OVF_Pos)              /* (TCC_INTENSET) Overflow Interrupt Enable Mask */
+#define TCC_INTENSET_OVF(value)               (TCC_INTENSET_OVF_Msk & (_UINT32_(value) << TCC_INTENSET_OVF_Pos)) /* Assignment of value for OVF in the TCC_INTENSET register */
+#define TCC_INTENSET_TRG_Pos                  _UINT32_(1)                                          /* (TCC_INTENSET) Retrigger Interrupt Enable Position */
+#define TCC_INTENSET_TRG_Msk                  (_UINT32_(0x1) << TCC_INTENSET_TRG_Pos)              /* (TCC_INTENSET) Retrigger Interrupt Enable Mask */
+#define TCC_INTENSET_TRG(value)               (TCC_INTENSET_TRG_Msk & (_UINT32_(value) << TCC_INTENSET_TRG_Pos)) /* Assignment of value for TRG in the TCC_INTENSET register */
+#define TCC_INTENSET_CNT_Pos                  _UINT32_(2)                                          /* (TCC_INTENSET) Counter Interrupt Enable Position */
+#define TCC_INTENSET_CNT_Msk                  (_UINT32_(0x1) << TCC_INTENSET_CNT_Pos)              /* (TCC_INTENSET) Counter Interrupt Enable Mask */
+#define TCC_INTENSET_CNT(value)               (TCC_INTENSET_CNT_Msk & (_UINT32_(value) << TCC_INTENSET_CNT_Pos)) /* Assignment of value for CNT in the TCC_INTENSET register */
+#define TCC_INTENSET_ERR_Pos                  _UINT32_(3)                                          /* (TCC_INTENSET) Error Interrupt Enable Position */
+#define TCC_INTENSET_ERR_Msk                  (_UINT32_(0x1) << TCC_INTENSET_ERR_Pos)              /* (TCC_INTENSET) Error Interrupt Enable Mask */
+#define TCC_INTENSET_ERR(value)               (TCC_INTENSET_ERR_Msk & (_UINT32_(value) << TCC_INTENSET_ERR_Pos)) /* Assignment of value for ERR in the TCC_INTENSET register */
+#define TCC_INTENSET_UFS_Pos                  _UINT32_(10)                                         /* (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable Position */
+#define TCC_INTENSET_UFS_Msk                  (_UINT32_(0x1) << TCC_INTENSET_UFS_Pos)              /* (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable Mask */
+#define TCC_INTENSET_UFS(value)               (TCC_INTENSET_UFS_Msk & (_UINT32_(value) << TCC_INTENSET_UFS_Pos)) /* Assignment of value for UFS in the TCC_INTENSET register */
+#define TCC_INTENSET_DFS_Pos                  _UINT32_(11)                                         /* (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable Position */
+#define TCC_INTENSET_DFS_Msk                  (_UINT32_(0x1) << TCC_INTENSET_DFS_Pos)              /* (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable Mask */
+#define TCC_INTENSET_DFS(value)               (TCC_INTENSET_DFS_Msk & (_UINT32_(value) << TCC_INTENSET_DFS_Pos)) /* Assignment of value for DFS in the TCC_INTENSET register */
+#define TCC_INTENSET_FAULTA_Pos               _UINT32_(12)                                         /* (TCC_INTENSET) Recoverable Fault A Interrupt Enable Position */
+#define TCC_INTENSET_FAULTA_Msk               (_UINT32_(0x1) << TCC_INTENSET_FAULTA_Pos)           /* (TCC_INTENSET) Recoverable Fault A Interrupt Enable Mask */
+#define TCC_INTENSET_FAULTA(value)            (TCC_INTENSET_FAULTA_Msk & (_UINT32_(value) << TCC_INTENSET_FAULTA_Pos)) /* Assignment of value for FAULTA in the TCC_INTENSET register */
+#define TCC_INTENSET_FAULTB_Pos               _UINT32_(13)                                         /* (TCC_INTENSET) Recoverable Fault B Interrupt Enable Position */
+#define TCC_INTENSET_FAULTB_Msk               (_UINT32_(0x1) << TCC_INTENSET_FAULTB_Pos)           /* (TCC_INTENSET) Recoverable Fault B Interrupt Enable Mask */
+#define TCC_INTENSET_FAULTB(value)            (TCC_INTENSET_FAULTB_Msk & (_UINT32_(value) << TCC_INTENSET_FAULTB_Pos)) /* Assignment of value for FAULTB in the TCC_INTENSET register */
+#define TCC_INTENSET_FAULT0_Pos               _UINT32_(14)                                         /* (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable Position */
+#define TCC_INTENSET_FAULT0_Msk               (_UINT32_(0x1) << TCC_INTENSET_FAULT0_Pos)           /* (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable Mask */
+#define TCC_INTENSET_FAULT0(value)            (TCC_INTENSET_FAULT0_Msk & (_UINT32_(value) << TCC_INTENSET_FAULT0_Pos)) /* Assignment of value for FAULT0 in the TCC_INTENSET register */
+#define TCC_INTENSET_FAULT1_Pos               _UINT32_(15)                                         /* (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable Position */
+#define TCC_INTENSET_FAULT1_Msk               (_UINT32_(0x1) << TCC_INTENSET_FAULT1_Pos)           /* (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable Mask */
+#define TCC_INTENSET_FAULT1(value)            (TCC_INTENSET_FAULT1_Msk & (_UINT32_(value) << TCC_INTENSET_FAULT1_Pos)) /* Assignment of value for FAULT1 in the TCC_INTENSET register */
+#define TCC_INTENSET_MC0_Pos                  _UINT32_(16)                                         /* (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable Position */
+#define TCC_INTENSET_MC0_Msk                  (_UINT32_(0x1) << TCC_INTENSET_MC0_Pos)              /* (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable Mask */
+#define TCC_INTENSET_MC0(value)               (TCC_INTENSET_MC0_Msk & (_UINT32_(value) << TCC_INTENSET_MC0_Pos)) /* Assignment of value for MC0 in the TCC_INTENSET register */
+#define TCC_INTENSET_MC1_Pos                  _UINT32_(17)                                         /* (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable Position */
+#define TCC_INTENSET_MC1_Msk                  (_UINT32_(0x1) << TCC_INTENSET_MC1_Pos)              /* (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable Mask */
+#define TCC_INTENSET_MC1(value)               (TCC_INTENSET_MC1_Msk & (_UINT32_(value) << TCC_INTENSET_MC1_Pos)) /* Assignment of value for MC1 in the TCC_INTENSET register */
+#define TCC_INTENSET_Msk                      _UINT32_(0x0003FC0F)                                 /* (TCC_INTENSET) Register Mask  */
+
+#define TCC_INTENSET_FAULT_Pos                _UINT32_(14)                                         /* (TCC_INTENSET Position) Non-Recoverable Fault x Interrupt Enable */
+#define TCC_INTENSET_FAULT_Msk                (_UINT32_(0x3) << TCC_INTENSET_FAULT_Pos)            /* (TCC_INTENSET Mask) FAULT */
+#define TCC_INTENSET_FAULT(value)             (TCC_INTENSET_FAULT_Msk & (_UINT32_(value) << TCC_INTENSET_FAULT_Pos)) 
+#define TCC_INTENSET_MC_Pos                   _UINT32_(16)                                         /* (TCC_INTENSET Position) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk                   (_UINT32_(0x3) << TCC_INTENSET_MC_Pos)               /* (TCC_INTENSET Mask) MC */
+#define TCC_INTENSET_MC(value)                (TCC_INTENSET_MC_Msk & (_UINT32_(value) << TCC_INTENSET_MC_Pos)) 
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#define TCC_INTFLAG_RESETVALUE                _UINT32_(0x00)                                       /*  (TCC_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define TCC_INTFLAG_OVF_Pos                   _UINT32_(0)                                          /* (TCC_INTFLAG) Overflow Position */
+#define TCC_INTFLAG_OVF_Msk                   (_UINT32_(0x1) << TCC_INTFLAG_OVF_Pos)               /* (TCC_INTFLAG) Overflow Mask */
+#define TCC_INTFLAG_OVF(value)                (TCC_INTFLAG_OVF_Msk & (_UINT32_(value) << TCC_INTFLAG_OVF_Pos)) /* Assignment of value for OVF in the TCC_INTFLAG register */
+#define TCC_INTFLAG_TRG_Pos                   _UINT32_(1)                                          /* (TCC_INTFLAG) Retrigger Position */
+#define TCC_INTFLAG_TRG_Msk                   (_UINT32_(0x1) << TCC_INTFLAG_TRG_Pos)               /* (TCC_INTFLAG) Retrigger Mask */
+#define TCC_INTFLAG_TRG(value)                (TCC_INTFLAG_TRG_Msk & (_UINT32_(value) << TCC_INTFLAG_TRG_Pos)) /* Assignment of value for TRG in the TCC_INTFLAG register */
+#define TCC_INTFLAG_CNT_Pos                   _UINT32_(2)                                          /* (TCC_INTFLAG) Counter Position */
+#define TCC_INTFLAG_CNT_Msk                   (_UINT32_(0x1) << TCC_INTFLAG_CNT_Pos)               /* (TCC_INTFLAG) Counter Mask */
+#define TCC_INTFLAG_CNT(value)                (TCC_INTFLAG_CNT_Msk & (_UINT32_(value) << TCC_INTFLAG_CNT_Pos)) /* Assignment of value for CNT in the TCC_INTFLAG register */
+#define TCC_INTFLAG_ERR_Pos                   _UINT32_(3)                                          /* (TCC_INTFLAG) Error Position */
+#define TCC_INTFLAG_ERR_Msk                   (_UINT32_(0x1) << TCC_INTFLAG_ERR_Pos)               /* (TCC_INTFLAG) Error Mask */
+#define TCC_INTFLAG_ERR(value)                (TCC_INTFLAG_ERR_Msk & (_UINT32_(value) << TCC_INTFLAG_ERR_Pos)) /* Assignment of value for ERR in the TCC_INTFLAG register */
+#define TCC_INTFLAG_UFS_Pos                   _UINT32_(10)                                         /* (TCC_INTFLAG) Non-Recoverable Update Fault Position */
+#define TCC_INTFLAG_UFS_Msk                   (_UINT32_(0x1) << TCC_INTFLAG_UFS_Pos)               /* (TCC_INTFLAG) Non-Recoverable Update Fault Mask */
+#define TCC_INTFLAG_UFS(value)                (TCC_INTFLAG_UFS_Msk & (_UINT32_(value) << TCC_INTFLAG_UFS_Pos)) /* Assignment of value for UFS in the TCC_INTFLAG register */
+#define TCC_INTFLAG_DFS_Pos                   _UINT32_(11)                                         /* (TCC_INTFLAG) Non-Recoverable Debug Fault Position */
+#define TCC_INTFLAG_DFS_Msk                   (_UINT32_(0x1) << TCC_INTFLAG_DFS_Pos)               /* (TCC_INTFLAG) Non-Recoverable Debug Fault Mask */
+#define TCC_INTFLAG_DFS(value)                (TCC_INTFLAG_DFS_Msk & (_UINT32_(value) << TCC_INTFLAG_DFS_Pos)) /* Assignment of value for DFS in the TCC_INTFLAG register */
+#define TCC_INTFLAG_FAULTA_Pos                _UINT32_(12)                                         /* (TCC_INTFLAG) Recoverable Fault A Position */
+#define TCC_INTFLAG_FAULTA_Msk                (_UINT32_(0x1) << TCC_INTFLAG_FAULTA_Pos)            /* (TCC_INTFLAG) Recoverable Fault A Mask */
+#define TCC_INTFLAG_FAULTA(value)             (TCC_INTFLAG_FAULTA_Msk & (_UINT32_(value) << TCC_INTFLAG_FAULTA_Pos)) /* Assignment of value for FAULTA in the TCC_INTFLAG register */
+#define TCC_INTFLAG_FAULTB_Pos                _UINT32_(13)                                         /* (TCC_INTFLAG) Recoverable Fault B Position */
+#define TCC_INTFLAG_FAULTB_Msk                (_UINT32_(0x1) << TCC_INTFLAG_FAULTB_Pos)            /* (TCC_INTFLAG) Recoverable Fault B Mask */
+#define TCC_INTFLAG_FAULTB(value)             (TCC_INTFLAG_FAULTB_Msk & (_UINT32_(value) << TCC_INTFLAG_FAULTB_Pos)) /* Assignment of value for FAULTB in the TCC_INTFLAG register */
+#define TCC_INTFLAG_FAULT0_Pos                _UINT32_(14)                                         /* (TCC_INTFLAG) Non-Recoverable Fault 0 Position */
+#define TCC_INTFLAG_FAULT0_Msk                (_UINT32_(0x1) << TCC_INTFLAG_FAULT0_Pos)            /* (TCC_INTFLAG) Non-Recoverable Fault 0 Mask */
+#define TCC_INTFLAG_FAULT0(value)             (TCC_INTFLAG_FAULT0_Msk & (_UINT32_(value) << TCC_INTFLAG_FAULT0_Pos)) /* Assignment of value for FAULT0 in the TCC_INTFLAG register */
+#define TCC_INTFLAG_FAULT1_Pos                _UINT32_(15)                                         /* (TCC_INTFLAG) Non-Recoverable Fault 1 Position */
+#define TCC_INTFLAG_FAULT1_Msk                (_UINT32_(0x1) << TCC_INTFLAG_FAULT1_Pos)            /* (TCC_INTFLAG) Non-Recoverable Fault 1 Mask */
+#define TCC_INTFLAG_FAULT1(value)             (TCC_INTFLAG_FAULT1_Msk & (_UINT32_(value) << TCC_INTFLAG_FAULT1_Pos)) /* Assignment of value for FAULT1 in the TCC_INTFLAG register */
+#define TCC_INTFLAG_MC0_Pos                   _UINT32_(16)                                         /* (TCC_INTFLAG) Match or Capture 0 Position */
+#define TCC_INTFLAG_MC0_Msk                   (_UINT32_(0x1) << TCC_INTFLAG_MC0_Pos)               /* (TCC_INTFLAG) Match or Capture 0 Mask */
+#define TCC_INTFLAG_MC0(value)                (TCC_INTFLAG_MC0_Msk & (_UINT32_(value) << TCC_INTFLAG_MC0_Pos)) /* Assignment of value for MC0 in the TCC_INTFLAG register */
+#define TCC_INTFLAG_MC1_Pos                   _UINT32_(17)                                         /* (TCC_INTFLAG) Match or Capture 1 Position */
+#define TCC_INTFLAG_MC1_Msk                   (_UINT32_(0x1) << TCC_INTFLAG_MC1_Pos)               /* (TCC_INTFLAG) Match or Capture 1 Mask */
+#define TCC_INTFLAG_MC1(value)                (TCC_INTFLAG_MC1_Msk & (_UINT32_(value) << TCC_INTFLAG_MC1_Pos)) /* Assignment of value for MC1 in the TCC_INTFLAG register */
+#define TCC_INTFLAG_Msk                       _UINT32_(0x0003FC0F)                                 /* (TCC_INTFLAG) Register Mask  */
+
+#define TCC_INTFLAG_FAULT_Pos                 _UINT32_(14)                                         /* (TCC_INTFLAG Position) Non-Recoverable Fault x */
+#define TCC_INTFLAG_FAULT_Msk                 (_UINT32_(0x3) << TCC_INTFLAG_FAULT_Pos)             /* (TCC_INTFLAG Mask) FAULT */
+#define TCC_INTFLAG_FAULT(value)              (TCC_INTFLAG_FAULT_Msk & (_UINT32_(value) << TCC_INTFLAG_FAULT_Pos)) 
+#define TCC_INTFLAG_MC_Pos                    _UINT32_(16)                                         /* (TCC_INTFLAG Position) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk                    (_UINT32_(0x3) << TCC_INTFLAG_MC_Pos)                /* (TCC_INTFLAG Mask) MC */
+#define TCC_INTFLAG_MC(value)                 (TCC_INTFLAG_MC_Msk & (_UINT32_(value) << TCC_INTFLAG_MC_Pos)) 
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#define TCC_STATUS_RESETVALUE                 _UINT32_(0x01)                                       /*  (TCC_STATUS) Status  Reset Value */
+
+#define TCC_STATUS_STOP_Pos                   _UINT32_(0)                                          /* (TCC_STATUS) Stop Position */
+#define TCC_STATUS_STOP_Msk                   (_UINT32_(0x1) << TCC_STATUS_STOP_Pos)               /* (TCC_STATUS) Stop Mask */
+#define TCC_STATUS_STOP(value)                (TCC_STATUS_STOP_Msk & (_UINT32_(value) << TCC_STATUS_STOP_Pos)) /* Assignment of value for STOP in the TCC_STATUS register */
+#define TCC_STATUS_IDX_Pos                    _UINT32_(1)                                          /* (TCC_STATUS) Ramp Position */
+#define TCC_STATUS_IDX_Msk                    (_UINT32_(0x1) << TCC_STATUS_IDX_Pos)                /* (TCC_STATUS) Ramp Mask */
+#define TCC_STATUS_IDX(value)                 (TCC_STATUS_IDX_Msk & (_UINT32_(value) << TCC_STATUS_IDX_Pos)) /* Assignment of value for IDX in the TCC_STATUS register */
+#define TCC_STATUS_UFS_Pos                    _UINT32_(2)                                          /* (TCC_STATUS) Non-recoverable Update Fault State Position */
+#define TCC_STATUS_UFS_Msk                    (_UINT32_(0x1) << TCC_STATUS_UFS_Pos)                /* (TCC_STATUS) Non-recoverable Update Fault State Mask */
+#define TCC_STATUS_UFS(value)                 (TCC_STATUS_UFS_Msk & (_UINT32_(value) << TCC_STATUS_UFS_Pos)) /* Assignment of value for UFS in the TCC_STATUS register */
+#define TCC_STATUS_DFS_Pos                    _UINT32_(3)                                          /* (TCC_STATUS) Non-Recoverable Debug Fault State Position */
+#define TCC_STATUS_DFS_Msk                    (_UINT32_(0x1) << TCC_STATUS_DFS_Pos)                /* (TCC_STATUS) Non-Recoverable Debug Fault State Mask */
+#define TCC_STATUS_DFS(value)                 (TCC_STATUS_DFS_Msk & (_UINT32_(value) << TCC_STATUS_DFS_Pos)) /* Assignment of value for DFS in the TCC_STATUS register */
+#define TCC_STATUS_SLAVE_Pos                  _UINT32_(4)                                          /* (TCC_STATUS) Slave Position */
+#define TCC_STATUS_SLAVE_Msk                  (_UINT32_(0x1) << TCC_STATUS_SLAVE_Pos)              /* (TCC_STATUS) Slave Mask */
+#define TCC_STATUS_SLAVE(value)               (TCC_STATUS_SLAVE_Msk & (_UINT32_(value) << TCC_STATUS_SLAVE_Pos)) /* Assignment of value for SLAVE in the TCC_STATUS register */
+#define TCC_STATUS_PATTBUFV_Pos               _UINT32_(5)                                          /* (TCC_STATUS) Pattern Buffer Valid Position */
+#define TCC_STATUS_PATTBUFV_Msk               (_UINT32_(0x1) << TCC_STATUS_PATTBUFV_Pos)           /* (TCC_STATUS) Pattern Buffer Valid Mask */
+#define TCC_STATUS_PATTBUFV(value)            (TCC_STATUS_PATTBUFV_Msk & (_UINT32_(value) << TCC_STATUS_PATTBUFV_Pos)) /* Assignment of value for PATTBUFV in the TCC_STATUS register */
+#define TCC_STATUS_PERBUFV_Pos                _UINT32_(7)                                          /* (TCC_STATUS) Period Buffer Valid Position */
+#define TCC_STATUS_PERBUFV_Msk                (_UINT32_(0x1) << TCC_STATUS_PERBUFV_Pos)            /* (TCC_STATUS) Period Buffer Valid Mask */
+#define TCC_STATUS_PERBUFV(value)             (TCC_STATUS_PERBUFV_Msk & (_UINT32_(value) << TCC_STATUS_PERBUFV_Pos)) /* Assignment of value for PERBUFV in the TCC_STATUS register */
+#define TCC_STATUS_FAULTAIN_Pos               _UINT32_(8)                                          /* (TCC_STATUS) Recoverable Fault A Input Position */
+#define TCC_STATUS_FAULTAIN_Msk               (_UINT32_(0x1) << TCC_STATUS_FAULTAIN_Pos)           /* (TCC_STATUS) Recoverable Fault A Input Mask */
+#define TCC_STATUS_FAULTAIN(value)            (TCC_STATUS_FAULTAIN_Msk & (_UINT32_(value) << TCC_STATUS_FAULTAIN_Pos)) /* Assignment of value for FAULTAIN in the TCC_STATUS register */
+#define TCC_STATUS_FAULTBIN_Pos               _UINT32_(9)                                          /* (TCC_STATUS) Recoverable Fault B Input Position */
+#define TCC_STATUS_FAULTBIN_Msk               (_UINT32_(0x1) << TCC_STATUS_FAULTBIN_Pos)           /* (TCC_STATUS) Recoverable Fault B Input Mask */
+#define TCC_STATUS_FAULTBIN(value)            (TCC_STATUS_FAULTBIN_Msk & (_UINT32_(value) << TCC_STATUS_FAULTBIN_Pos)) /* Assignment of value for FAULTBIN in the TCC_STATUS register */
+#define TCC_STATUS_FAULT0IN_Pos               _UINT32_(10)                                         /* (TCC_STATUS) Non-Recoverable Fault0 Input Position */
+#define TCC_STATUS_FAULT0IN_Msk               (_UINT32_(0x1) << TCC_STATUS_FAULT0IN_Pos)           /* (TCC_STATUS) Non-Recoverable Fault0 Input Mask */
+#define TCC_STATUS_FAULT0IN(value)            (TCC_STATUS_FAULT0IN_Msk & (_UINT32_(value) << TCC_STATUS_FAULT0IN_Pos)) /* Assignment of value for FAULT0IN in the TCC_STATUS register */
+#define TCC_STATUS_FAULT1IN_Pos               _UINT32_(11)                                         /* (TCC_STATUS) Non-Recoverable Fault1 Input Position */
+#define TCC_STATUS_FAULT1IN_Msk               (_UINT32_(0x1) << TCC_STATUS_FAULT1IN_Pos)           /* (TCC_STATUS) Non-Recoverable Fault1 Input Mask */
+#define TCC_STATUS_FAULT1IN(value)            (TCC_STATUS_FAULT1IN_Msk & (_UINT32_(value) << TCC_STATUS_FAULT1IN_Pos)) /* Assignment of value for FAULT1IN in the TCC_STATUS register */
+#define TCC_STATUS_FAULTA_Pos                 _UINT32_(12)                                         /* (TCC_STATUS) Recoverable Fault A State Position */
+#define TCC_STATUS_FAULTA_Msk                 (_UINT32_(0x1) << TCC_STATUS_FAULTA_Pos)             /* (TCC_STATUS) Recoverable Fault A State Mask */
+#define TCC_STATUS_FAULTA(value)              (TCC_STATUS_FAULTA_Msk & (_UINT32_(value) << TCC_STATUS_FAULTA_Pos)) /* Assignment of value for FAULTA in the TCC_STATUS register */
+#define TCC_STATUS_FAULTB_Pos                 _UINT32_(13)                                         /* (TCC_STATUS) Recoverable Fault B State Position */
+#define TCC_STATUS_FAULTB_Msk                 (_UINT32_(0x1) << TCC_STATUS_FAULTB_Pos)             /* (TCC_STATUS) Recoverable Fault B State Mask */
+#define TCC_STATUS_FAULTB(value)              (TCC_STATUS_FAULTB_Msk & (_UINT32_(value) << TCC_STATUS_FAULTB_Pos)) /* Assignment of value for FAULTB in the TCC_STATUS register */
+#define TCC_STATUS_FAULT0_Pos                 _UINT32_(14)                                         /* (TCC_STATUS) Non-Recoverable Fault 0 State Position */
+#define TCC_STATUS_FAULT0_Msk                 (_UINT32_(0x1) << TCC_STATUS_FAULT0_Pos)             /* (TCC_STATUS) Non-Recoverable Fault 0 State Mask */
+#define TCC_STATUS_FAULT0(value)              (TCC_STATUS_FAULT0_Msk & (_UINT32_(value) << TCC_STATUS_FAULT0_Pos)) /* Assignment of value for FAULT0 in the TCC_STATUS register */
+#define TCC_STATUS_FAULT1_Pos                 _UINT32_(15)                                         /* (TCC_STATUS) Non-Recoverable Fault 1 State Position */
+#define TCC_STATUS_FAULT1_Msk                 (_UINT32_(0x1) << TCC_STATUS_FAULT1_Pos)             /* (TCC_STATUS) Non-Recoverable Fault 1 State Mask */
+#define TCC_STATUS_FAULT1(value)              (TCC_STATUS_FAULT1_Msk & (_UINT32_(value) << TCC_STATUS_FAULT1_Pos)) /* Assignment of value for FAULT1 in the TCC_STATUS register */
+#define TCC_STATUS_CCBUFV0_Pos                _UINT32_(16)                                         /* (TCC_STATUS) Compare Channel 0 Buffer Valid Position */
+#define TCC_STATUS_CCBUFV0_Msk                (_UINT32_(0x1) << TCC_STATUS_CCBUFV0_Pos)            /* (TCC_STATUS) Compare Channel 0 Buffer Valid Mask */
+#define TCC_STATUS_CCBUFV0(value)             (TCC_STATUS_CCBUFV0_Msk & (_UINT32_(value) << TCC_STATUS_CCBUFV0_Pos)) /* Assignment of value for CCBUFV0 in the TCC_STATUS register */
+#define TCC_STATUS_CCBUFV1_Pos                _UINT32_(17)                                         /* (TCC_STATUS) Compare Channel 1 Buffer Valid Position */
+#define TCC_STATUS_CCBUFV1_Msk                (_UINT32_(0x1) << TCC_STATUS_CCBUFV1_Pos)            /* (TCC_STATUS) Compare Channel 1 Buffer Valid Mask */
+#define TCC_STATUS_CCBUFV1(value)             (TCC_STATUS_CCBUFV1_Msk & (_UINT32_(value) << TCC_STATUS_CCBUFV1_Pos)) /* Assignment of value for CCBUFV1 in the TCC_STATUS register */
+#define TCC_STATUS_CMP0_Pos                   _UINT32_(24)                                         /* (TCC_STATUS) Compare Channel 0 Value Position */
+#define TCC_STATUS_CMP0_Msk                   (_UINT32_(0x1) << TCC_STATUS_CMP0_Pos)               /* (TCC_STATUS) Compare Channel 0 Value Mask */
+#define TCC_STATUS_CMP0(value)                (TCC_STATUS_CMP0_Msk & (_UINT32_(value) << TCC_STATUS_CMP0_Pos)) /* Assignment of value for CMP0 in the TCC_STATUS register */
+#define TCC_STATUS_CMP1_Pos                   _UINT32_(25)                                         /* (TCC_STATUS) Compare Channel 1 Value Position */
+#define TCC_STATUS_CMP1_Msk                   (_UINT32_(0x1) << TCC_STATUS_CMP1_Pos)               /* (TCC_STATUS) Compare Channel 1 Value Mask */
+#define TCC_STATUS_CMP1(value)                (TCC_STATUS_CMP1_Msk & (_UINT32_(value) << TCC_STATUS_CMP1_Pos)) /* Assignment of value for CMP1 in the TCC_STATUS register */
+#define TCC_STATUS_Msk                        _UINT32_(0x0303FFBF)                                 /* (TCC_STATUS) Register Mask  */
+
+#define TCC_STATUS_FAULT_Pos                  _UINT32_(14)                                         /* (TCC_STATUS Position) Non-Recoverable Fault x State */
+#define TCC_STATUS_FAULT_Msk                  (_UINT32_(0x3) << TCC_STATUS_FAULT_Pos)              /* (TCC_STATUS Mask) FAULT */
+#define TCC_STATUS_FAULT(value)               (TCC_STATUS_FAULT_Msk & (_UINT32_(value) << TCC_STATUS_FAULT_Pos)) 
+#define TCC_STATUS_CCBUFV_Pos                 _UINT32_(16)                                         /* (TCC_STATUS Position) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBUFV_Msk                 (_UINT32_(0x3) << TCC_STATUS_CCBUFV_Pos)             /* (TCC_STATUS Mask) CCBUFV */
+#define TCC_STATUS_CCBUFV(value)              (TCC_STATUS_CCBUFV_Msk & (_UINT32_(value) << TCC_STATUS_CCBUFV_Pos)) 
+#define TCC_STATUS_CMP_Pos                    _UINT32_(24)                                         /* (TCC_STATUS Position) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk                    (_UINT32_(0x3) << TCC_STATUS_CMP_Pos)                /* (TCC_STATUS Mask) CMP */
+#define TCC_STATUS_CMP(value)                 (TCC_STATUS_CMP_Msk & (_UINT32_(value) << TCC_STATUS_CMP_Pos)) 
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#define TCC_COUNT_RESETVALUE                  _UINT32_(0x00)                                       /*  (TCC_COUNT) Count  Reset Value */
+
+#define TCC_COUNT_COUNT_Pos                   _UINT32_(0)                                          /* (TCC_COUNT) Counter Value Position */
+#define TCC_COUNT_COUNT_Msk                   (_UINT32_(0xFFFF) << TCC_COUNT_COUNT_Pos)            /* (TCC_COUNT) Counter Value Mask */
+#define TCC_COUNT_COUNT(value)                (TCC_COUNT_COUNT_Msk & (_UINT32_(value) << TCC_COUNT_COUNT_Pos)) /* Assignment of value for COUNT in the TCC_COUNT register */
+#define TCC_COUNT_Msk                         _UINT32_(0x0000FFFF)                                 /* (TCC_COUNT) Register Mask  */
+
+/* DITH4 mode */
+#define TCC_COUNT_DITH4_COUNT_Pos             _UINT32_(4)                                          /* (TCC_COUNT) Counter Value Position */
+#define TCC_COUNT_DITH4_COUNT_Msk             (_UINT32_(0xFFF) << TCC_COUNT_DITH4_COUNT_Pos)       /* (TCC_COUNT) Counter Value Mask */
+#define TCC_COUNT_DITH4_COUNT(value)          (TCC_COUNT_DITH4_COUNT_Msk & (_UINT32_(value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_Msk                   _UINT32_(0x0000FFF0)                                 /* (TCC_COUNT_DITH4) Register Mask  */
+
+/* DITH5 mode */
+#define TCC_COUNT_DITH5_COUNT_Pos             _UINT32_(5)                                          /* (TCC_COUNT) Counter Value Position */
+#define TCC_COUNT_DITH5_COUNT_Msk             (_UINT32_(0x7FF) << TCC_COUNT_DITH5_COUNT_Pos)       /* (TCC_COUNT) Counter Value Mask */
+#define TCC_COUNT_DITH5_COUNT(value)          (TCC_COUNT_DITH5_COUNT_Msk & (_UINT32_(value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_Msk                   _UINT32_(0x0000FFE0)                                 /* (TCC_COUNT_DITH5) Register Mask  */
+
+/* DITH6 mode */
+#define TCC_COUNT_DITH6_COUNT_Pos             _UINT32_(6)                                          /* (TCC_COUNT) Counter Value Position */
+#define TCC_COUNT_DITH6_COUNT_Msk             (_UINT32_(0x3FF) << TCC_COUNT_DITH6_COUNT_Pos)       /* (TCC_COUNT) Counter Value Mask */
+#define TCC_COUNT_DITH6_COUNT(value)          (TCC_COUNT_DITH6_COUNT_Msk & (_UINT32_(value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_Msk                   _UINT32_(0x0000FFC0)                                 /* (TCC_COUNT_DITH6) Register Mask  */
+
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#define TCC_WAVE_RESETVALUE                   _UINT32_(0x00)                                       /*  (TCC_WAVE) Waveform Control  Reset Value */
+
+#define TCC_WAVE_WAVEGEN_Pos                  _UINT32_(0)                                          /* (TCC_WAVE) Waveform Generation Position */
+#define TCC_WAVE_WAVEGEN_Msk                  (_UINT32_(0x7) << TCC_WAVE_WAVEGEN_Pos)              /* (TCC_WAVE) Waveform Generation Mask */
+#define TCC_WAVE_WAVEGEN(value)               (TCC_WAVE_WAVEGEN_Msk & (_UINT32_(value) << TCC_WAVE_WAVEGEN_Pos)) /* Assignment of value for WAVEGEN in the TCC_WAVE register */
+#define   TCC_WAVE_WAVEGEN_NFRQ_Val           _UINT32_(0x0)                                        /* (TCC_WAVE) Normal frequency  */
+#define   TCC_WAVE_WAVEGEN_MFRQ_Val           _UINT32_(0x1)                                        /* (TCC_WAVE) Match frequency  */
+#define   TCC_WAVE_WAVEGEN_NPWM_Val           _UINT32_(0x2)                                        /* (TCC_WAVE) Normal PWM  */
+#define   TCC_WAVE_WAVEGEN_DPWM_Val           _UINT32_(0x3)                                        /* (TCC_WAVE) Dual compare PWM  */
+#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val     _UINT32_(0x4)                                        /* (TCC_WAVE) Dual-slope critical  */
+#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val       _UINT32_(0x5)                                        /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO  */
+#define   TCC_WAVE_WAVEGEN_DSBOTH_Val         _UINT32_(0x6)                                        /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP  */
+#define   TCC_WAVE_WAVEGEN_DSTOP_Val          _UINT32_(0x7)                                        /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP  */
+#define TCC_WAVE_WAVEGEN_NFRQ                 (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)  /* (TCC_WAVE) Normal frequency Position */
+#define TCC_WAVE_WAVEGEN_MFRQ                 (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)  /* (TCC_WAVE) Match frequency Position */
+#define TCC_WAVE_WAVEGEN_NPWM                 (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)  /* (TCC_WAVE) Normal PWM Position */
+#define TCC_WAVE_WAVEGEN_DPWM                 (TCC_WAVE_WAVEGEN_DPWM_Val << TCC_WAVE_WAVEGEN_Pos)  /* (TCC_WAVE) Dual compare PWM Position */
+#define TCC_WAVE_WAVEGEN_DSCRITICAL           (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Dual-slope critical Position */
+#define TCC_WAVE_WAVEGEN_DSBOTTOM             (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO Position */
+#define TCC_WAVE_WAVEGEN_DSBOTH               (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP Position */
+#define TCC_WAVE_WAVEGEN_DSTOP                (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) /* (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP Position */
+#define TCC_WAVE_RAMP_Pos                     _UINT32_(4)                                          /* (TCC_WAVE) Ramp Mode Position */
+#define TCC_WAVE_RAMP_Msk                     (_UINT32_(0x7) << TCC_WAVE_RAMP_Pos)                 /* (TCC_WAVE) Ramp Mode Mask */
+#define TCC_WAVE_RAMP(value)                  (TCC_WAVE_RAMP_Msk & (_UINT32_(value) << TCC_WAVE_RAMP_Pos)) /* Assignment of value for RAMP in the TCC_WAVE register */
+#define   TCC_WAVE_RAMP_RAMP1_Val             _UINT32_(0x0)                                        /* (TCC_WAVE) RAMP1 operation  */
+#define   TCC_WAVE_RAMP_RAMP2A_Val            _UINT32_(0x1)                                        /* (TCC_WAVE) Alternative RAMP2 operation  */
+#define   TCC_WAVE_RAMP_RAMP2_Val             _UINT32_(0x2)                                        /* (TCC_WAVE) RAMP2 operation  */
+#define   TCC_WAVE_RAMP_RAMP2C_Val            _UINT32_(0x3)                                        /* (TCC_WAVE) Critical RAMP2 operation  */
+#define   TCC_WAVE_RAMP_RAMP2CS_Val           _UINT32_(0x4)                                        /* (TCC_WAVE) Critical Swapped RAMP2 operation  */
+#define TCC_WAVE_RAMP_RAMP1                   (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)       /* (TCC_WAVE) RAMP1 operation Position */
+#define TCC_WAVE_RAMP_RAMP2A                  (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)      /* (TCC_WAVE) Alternative RAMP2 operation Position */
+#define TCC_WAVE_RAMP_RAMP2                   (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)       /* (TCC_WAVE) RAMP2 operation Position */
+#define TCC_WAVE_RAMP_RAMP2C                  (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos)      /* (TCC_WAVE) Critical RAMP2 operation Position */
+#define TCC_WAVE_RAMP_RAMP2CS                 (TCC_WAVE_RAMP_RAMP2CS_Val << TCC_WAVE_RAMP_Pos)     /* (TCC_WAVE) Critical Swapped RAMP2 operation Position */
+#define TCC_WAVE_CIPEREN_Pos                  _UINT32_(7)                                          /* (TCC_WAVE) Circular period Enable Position */
+#define TCC_WAVE_CIPEREN_Msk                  (_UINT32_(0x1) << TCC_WAVE_CIPEREN_Pos)              /* (TCC_WAVE) Circular period Enable Mask */
+#define TCC_WAVE_CIPEREN(value)               (TCC_WAVE_CIPEREN_Msk & (_UINT32_(value) << TCC_WAVE_CIPEREN_Pos)) /* Assignment of value for CIPEREN in the TCC_WAVE register */
+#define TCC_WAVE_CICCEN0_Pos                  _UINT32_(8)                                          /* (TCC_WAVE) Circular Channel 0 Enable Position */
+#define TCC_WAVE_CICCEN0_Msk                  (_UINT32_(0x1) << TCC_WAVE_CICCEN0_Pos)              /* (TCC_WAVE) Circular Channel 0 Enable Mask */
+#define TCC_WAVE_CICCEN0(value)               (TCC_WAVE_CICCEN0_Msk & (_UINT32_(value) << TCC_WAVE_CICCEN0_Pos)) /* Assignment of value for CICCEN0 in the TCC_WAVE register */
+#define TCC_WAVE_CICCEN1_Pos                  _UINT32_(9)                                          /* (TCC_WAVE) Circular Channel 1 Enable Position */
+#define TCC_WAVE_CICCEN1_Msk                  (_UINT32_(0x1) << TCC_WAVE_CICCEN1_Pos)              /* (TCC_WAVE) Circular Channel 1 Enable Mask */
+#define TCC_WAVE_CICCEN1(value)               (TCC_WAVE_CICCEN1_Msk & (_UINT32_(value) << TCC_WAVE_CICCEN1_Pos)) /* Assignment of value for CICCEN1 in the TCC_WAVE register */
+#define TCC_WAVE_POL0_Pos                     _UINT32_(16)                                         /* (TCC_WAVE) Channel 0 Polarity Position */
+#define TCC_WAVE_POL0_Msk                     (_UINT32_(0x1) << TCC_WAVE_POL0_Pos)                 /* (TCC_WAVE) Channel 0 Polarity Mask */
+#define TCC_WAVE_POL0(value)                  (TCC_WAVE_POL0_Msk & (_UINT32_(value) << TCC_WAVE_POL0_Pos)) /* Assignment of value for POL0 in the TCC_WAVE register */
+#define TCC_WAVE_POL1_Pos                     _UINT32_(17)                                         /* (TCC_WAVE) Channel 1 Polarity Position */
+#define TCC_WAVE_POL1_Msk                     (_UINT32_(0x1) << TCC_WAVE_POL1_Pos)                 /* (TCC_WAVE) Channel 1 Polarity Mask */
+#define TCC_WAVE_POL1(value)                  (TCC_WAVE_POL1_Msk & (_UINT32_(value) << TCC_WAVE_POL1_Pos)) /* Assignment of value for POL1 in the TCC_WAVE register */
+#define TCC_WAVE_Msk                          _UINT32_(0x000303F7)                                 /* (TCC_WAVE) Register Mask  */
+
+#define TCC_WAVE_CICCEN_Pos                   _UINT32_(8)                                          /* (TCC_WAVE Position) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk                   (_UINT32_(0x3) << TCC_WAVE_CICCEN_Pos)               /* (TCC_WAVE Mask) CICCEN */
+#define TCC_WAVE_CICCEN(value)                (TCC_WAVE_CICCEN_Msk & (_UINT32_(value) << TCC_WAVE_CICCEN_Pos)) 
+#define TCC_WAVE_POL_Pos                      _UINT32_(16)                                         /* (TCC_WAVE Position) Channel x Polarity */
+#define TCC_WAVE_POL_Msk                      (_UINT32_(0x3) << TCC_WAVE_POL_Pos)                  /* (TCC_WAVE Mask) POL */
+#define TCC_WAVE_POL(value)                   (TCC_WAVE_POL_Msk & (_UINT32_(value) << TCC_WAVE_POL_Pos)) 
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#define TCC_PER_RESETVALUE                    _UINT32_(0xFFFF)                                     /*  (TCC_PER) Period  Reset Value */
+
+#define TCC_PER_PER_Pos                       _UINT32_(0)                                          /* (TCC_PER) Period Value Position */
+#define TCC_PER_PER_Msk                       (_UINT32_(0xFFFF) << TCC_PER_PER_Pos)                /* (TCC_PER) Period Value Mask */
+#define TCC_PER_PER(value)                    (TCC_PER_PER_Msk & (_UINT32_(value) << TCC_PER_PER_Pos)) /* Assignment of value for PER in the TCC_PER register */
+#define TCC_PER_Msk                           _UINT32_(0x0000FFFF)                                 /* (TCC_PER) Register Mask  */
+
+/* DITH4 mode */
+#define TCC_PER_DITH4_DITHER_Pos              _UINT32_(0)                                          /* (TCC_PER) Dithering Cycle Number Position */
+#define TCC_PER_DITH4_DITHER_Msk              (_UINT32_(0xF) << TCC_PER_DITH4_DITHER_Pos)          /* (TCC_PER) Dithering Cycle Number Mask */
+#define TCC_PER_DITH4_DITHER(value)           (TCC_PER_DITH4_DITHER_Msk & (_UINT32_(value) << TCC_PER_DITH4_DITHER_Pos))
+#define TCC_PER_DITH4_PER_Pos                 _UINT32_(4)                                          /* (TCC_PER) Period Value Position */
+#define TCC_PER_DITH4_PER_Msk                 (_UINT32_(0xFFF) << TCC_PER_DITH4_PER_Pos)           /* (TCC_PER) Period Value Mask */
+#define TCC_PER_DITH4_PER(value)              (TCC_PER_DITH4_PER_Msk & (_UINT32_(value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_Msk                     _UINT32_(0x0000FFFF)                                 /* (TCC_PER_DITH4) Register Mask  */
+
+/* DITH5 mode */
+#define TCC_PER_DITH5_DITHER_Pos              _UINT32_(0)                                          /* (TCC_PER) Dithering Cycle Number Position */
+#define TCC_PER_DITH5_DITHER_Msk              (_UINT32_(0x1F) << TCC_PER_DITH5_DITHER_Pos)         /* (TCC_PER) Dithering Cycle Number Mask */
+#define TCC_PER_DITH5_DITHER(value)           (TCC_PER_DITH5_DITHER_Msk & (_UINT32_(value) << TCC_PER_DITH5_DITHER_Pos))
+#define TCC_PER_DITH5_PER_Pos                 _UINT32_(5)                                          /* (TCC_PER) Period Value Position */
+#define TCC_PER_DITH5_PER_Msk                 (_UINT32_(0x7FF) << TCC_PER_DITH5_PER_Pos)           /* (TCC_PER) Period Value Mask */
+#define TCC_PER_DITH5_PER(value)              (TCC_PER_DITH5_PER_Msk & (_UINT32_(value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_Msk                     _UINT32_(0x0000FFFF)                                 /* (TCC_PER_DITH5) Register Mask  */
+
+/* DITH6 mode */
+#define TCC_PER_DITH6_DITHER_Pos              _UINT32_(0)                                          /* (TCC_PER) Dithering Cycle Number Position */
+#define TCC_PER_DITH6_DITHER_Msk              (_UINT32_(0x3F) << TCC_PER_DITH6_DITHER_Pos)         /* (TCC_PER) Dithering Cycle Number Mask */
+#define TCC_PER_DITH6_DITHER(value)           (TCC_PER_DITH6_DITHER_Msk & (_UINT32_(value) << TCC_PER_DITH6_DITHER_Pos))
+#define TCC_PER_DITH6_PER_Pos                 _UINT32_(6)                                          /* (TCC_PER) Period Value Position */
+#define TCC_PER_DITH6_PER_Msk                 (_UINT32_(0x3FF) << TCC_PER_DITH6_PER_Pos)           /* (TCC_PER) Period Value Mask */
+#define TCC_PER_DITH6_PER(value)              (TCC_PER_DITH6_PER_Msk & (_UINT32_(value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_Msk                     _UINT32_(0x0000FFFF)                                 /* (TCC_PER_DITH6) Register Mask  */
+
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#define TCC_CC_RESETVALUE                     _UINT32_(0x00)                                       /*  (TCC_CC) Compare and Capture  Reset Value */
+
+#define TCC_CC_CC_Pos                         _UINT32_(0)                                          /* (TCC_CC) Channel Compare/Capture Value Position */
+#define TCC_CC_CC_Msk                         (_UINT32_(0xFFFF) << TCC_CC_CC_Pos)                  /* (TCC_CC) Channel Compare/Capture Value Mask */
+#define TCC_CC_CC(value)                      (TCC_CC_CC_Msk & (_UINT32_(value) << TCC_CC_CC_Pos)) /* Assignment of value for CC in the TCC_CC register */
+#define TCC_CC_Msk                            _UINT32_(0x0000FFFF)                                 /* (TCC_CC) Register Mask  */
+
+/* DITH4 mode */
+#define TCC_CC_DITH4_DITHER_Pos               _UINT32_(0)                                          /* (TCC_CC) Dithering Cycle Number Position */
+#define TCC_CC_DITH4_DITHER_Msk               (_UINT32_(0xF) << TCC_CC_DITH4_DITHER_Pos)           /* (TCC_CC) Dithering Cycle Number Mask */
+#define TCC_CC_DITH4_DITHER(value)            (TCC_CC_DITH4_DITHER_Msk & (_UINT32_(value) << TCC_CC_DITH4_DITHER_Pos))
+#define TCC_CC_DITH4_CC_Pos                   _UINT32_(4)                                          /* (TCC_CC) Channel Compare/Capture Value Position */
+#define TCC_CC_DITH4_CC_Msk                   (_UINT32_(0xFFF) << TCC_CC_DITH4_CC_Pos)             /* (TCC_CC) Channel Compare/Capture Value Mask */
+#define TCC_CC_DITH4_CC(value)                (TCC_CC_DITH4_CC_Msk & (_UINT32_(value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_Msk                      _UINT32_(0x0000FFFF)                                 /* (TCC_CC_DITH4) Register Mask  */
+
+/* DITH5 mode */
+#define TCC_CC_DITH5_DITHER_Pos               _UINT32_(0)                                          /* (TCC_CC) Dithering Cycle Number Position */
+#define TCC_CC_DITH5_DITHER_Msk               (_UINT32_(0x1F) << TCC_CC_DITH5_DITHER_Pos)          /* (TCC_CC) Dithering Cycle Number Mask */
+#define TCC_CC_DITH5_DITHER(value)            (TCC_CC_DITH5_DITHER_Msk & (_UINT32_(value) << TCC_CC_DITH5_DITHER_Pos))
+#define TCC_CC_DITH5_CC_Pos                   _UINT32_(5)                                          /* (TCC_CC) Channel Compare/Capture Value Position */
+#define TCC_CC_DITH5_CC_Msk                   (_UINT32_(0x7FF) << TCC_CC_DITH5_CC_Pos)             /* (TCC_CC) Channel Compare/Capture Value Mask */
+#define TCC_CC_DITH5_CC(value)                (TCC_CC_DITH5_CC_Msk & (_UINT32_(value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_Msk                      _UINT32_(0x0000FFFF)                                 /* (TCC_CC_DITH5) Register Mask  */
+
+/* DITH6 mode */
+#define TCC_CC_DITH6_DITHER_Pos               _UINT32_(0)                                          /* (TCC_CC) Dithering Cycle Number Position */
+#define TCC_CC_DITH6_DITHER_Msk               (_UINT32_(0x3F) << TCC_CC_DITH6_DITHER_Pos)          /* (TCC_CC) Dithering Cycle Number Mask */
+#define TCC_CC_DITH6_DITHER(value)            (TCC_CC_DITH6_DITHER_Msk & (_UINT32_(value) << TCC_CC_DITH6_DITHER_Pos))
+#define TCC_CC_DITH6_CC_Pos                   _UINT32_(6)                                          /* (TCC_CC) Channel Compare/Capture Value Position */
+#define TCC_CC_DITH6_CC_Msk                   (_UINT32_(0x3FF) << TCC_CC_DITH6_CC_Pos)             /* (TCC_CC) Channel Compare/Capture Value Mask */
+#define TCC_CC_DITH6_CC(value)                (TCC_CC_DITH6_CC_Msk & (_UINT32_(value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_Msk                      _UINT32_(0x0000FFFF)                                 /* (TCC_CC_DITH6) Register Mask  */
+
+
+/* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#define TCC_PERBUF_RESETVALUE                 _UINT32_(0xFFFF)                                     /*  (TCC_PERBUF) Period Buffer  Reset Value */
+
+#define TCC_PERBUF_PERBUF_Pos                 _UINT32_(0)                                          /* (TCC_PERBUF) Period Buffer Value Position */
+#define TCC_PERBUF_PERBUF_Msk                 (_UINT32_(0xFFFF) << TCC_PERBUF_PERBUF_Pos)          /* (TCC_PERBUF) Period Buffer Value Mask */
+#define TCC_PERBUF_PERBUF(value)              (TCC_PERBUF_PERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_PERBUF_Pos)) /* Assignment of value for PERBUF in the TCC_PERBUF register */
+#define TCC_PERBUF_Msk                        _UINT32_(0x0000FFFF)                                 /* (TCC_PERBUF) Register Mask  */
+
+/* DITH4 mode */
+#define TCC_PERBUF_DITH4_DITHERBUF_Pos        _UINT32_(0)                                          /* (TCC_PERBUF) Dithering Buffer Cycle Number Position */
+#define TCC_PERBUF_DITH4_DITHERBUF_Msk        (_UINT32_(0xF) << TCC_PERBUF_DITH4_DITHERBUF_Pos)    /* (TCC_PERBUF) Dithering Buffer Cycle Number Mask */
+#define TCC_PERBUF_DITH4_DITHERBUF(value)     (TCC_PERBUF_DITH4_DITHERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH4_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH4_PERBUF_Pos           _UINT32_(4)                                          /* (TCC_PERBUF) Period Buffer Value Position */
+#define TCC_PERBUF_DITH4_PERBUF_Msk           (_UINT32_(0xFFF) << TCC_PERBUF_DITH4_PERBUF_Pos)     /* (TCC_PERBUF) Period Buffer Value Mask */
+#define TCC_PERBUF_DITH4_PERBUF(value)        (TCC_PERBUF_DITH4_PERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH4_PERBUF_Pos))
+#define TCC_PERBUF_DITH4_Msk                  _UINT32_(0x0000FFFF)                                 /* (TCC_PERBUF_DITH4) Register Mask  */
+
+/* DITH5 mode */
+#define TCC_PERBUF_DITH5_DITHERBUF_Pos        _UINT32_(0)                                          /* (TCC_PERBUF) Dithering Buffer Cycle Number Position */
+#define TCC_PERBUF_DITH5_DITHERBUF_Msk        (_UINT32_(0x1F) << TCC_PERBUF_DITH5_DITHERBUF_Pos)   /* (TCC_PERBUF) Dithering Buffer Cycle Number Mask */
+#define TCC_PERBUF_DITH5_DITHERBUF(value)     (TCC_PERBUF_DITH5_DITHERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH5_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH5_PERBUF_Pos           _UINT32_(5)                                          /* (TCC_PERBUF) Period Buffer Value Position */
+#define TCC_PERBUF_DITH5_PERBUF_Msk           (_UINT32_(0x7FF) << TCC_PERBUF_DITH5_PERBUF_Pos)     /* (TCC_PERBUF) Period Buffer Value Mask */
+#define TCC_PERBUF_DITH5_PERBUF(value)        (TCC_PERBUF_DITH5_PERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH5_PERBUF_Pos))
+#define TCC_PERBUF_DITH5_Msk                  _UINT32_(0x0000FFFF)                                 /* (TCC_PERBUF_DITH5) Register Mask  */
+
+/* DITH6 mode */
+#define TCC_PERBUF_DITH6_DITHERBUF_Pos        _UINT32_(0)                                          /* (TCC_PERBUF) Dithering Buffer Cycle Number Position */
+#define TCC_PERBUF_DITH6_DITHERBUF_Msk        (_UINT32_(0x3F) << TCC_PERBUF_DITH6_DITHERBUF_Pos)   /* (TCC_PERBUF) Dithering Buffer Cycle Number Mask */
+#define TCC_PERBUF_DITH6_DITHERBUF(value)     (TCC_PERBUF_DITH6_DITHERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH6_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH6_PERBUF_Pos           _UINT32_(6)                                          /* (TCC_PERBUF) Period Buffer Value Position */
+#define TCC_PERBUF_DITH6_PERBUF_Msk           (_UINT32_(0x3FF) << TCC_PERBUF_DITH6_PERBUF_Pos)     /* (TCC_PERBUF) Period Buffer Value Mask */
+#define TCC_PERBUF_DITH6_PERBUF(value)        (TCC_PERBUF_DITH6_PERBUF_Msk & (_UINT32_(value) << TCC_PERBUF_DITH6_PERBUF_Pos))
+#define TCC_PERBUF_DITH6_Msk                  _UINT32_(0x0000FFFF)                                 /* (TCC_PERBUF_DITH6) Register Mask  */
+
+
+/* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#define TCC_CCBUF_RESETVALUE                  _UINT32_(0x00)                                       /*  (TCC_CCBUF) Compare and Capture Buffer  Reset Value */
+
+#define TCC_CCBUF_CCBUF_Pos                   _UINT32_(0)                                          /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Position */
+#define TCC_CCBUF_CCBUF_Msk                   (_UINT32_(0xFFFF) << TCC_CCBUF_CCBUF_Pos)            /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Mask */
+#define TCC_CCBUF_CCBUF(value)                (TCC_CCBUF_CCBUF_Msk & (_UINT32_(value) << TCC_CCBUF_CCBUF_Pos)) /* Assignment of value for CCBUF in the TCC_CCBUF register */
+#define TCC_CCBUF_Msk                         _UINT32_(0x0000FFFF)                                 /* (TCC_CCBUF) Register Mask  */
+
+/* DITH4 mode */
+#define TCC_CCBUF_DITH4_DITHERBUF_Pos         _UINT32_(0)                                          /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Position */
+#define TCC_CCBUF_DITH4_DITHERBUF_Msk         (_UINT32_(0xF) << TCC_CCBUF_DITH4_DITHERBUF_Pos)     /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Mask */
+#define TCC_CCBUF_DITH4_DITHERBUF(value)      (TCC_CCBUF_DITH4_DITHERBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH4_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH4_CCBUF_Pos             _UINT32_(4)                                          /* (TCC_CCBUF) Dithering Buffer Cycle Number Position */
+#define TCC_CCBUF_DITH4_CCBUF_Msk             (_UINT32_(0xFFF) << TCC_CCBUF_DITH4_CCBUF_Pos)       /* (TCC_CCBUF) Dithering Buffer Cycle Number Mask */
+#define TCC_CCBUF_DITH4_CCBUF(value)          (TCC_CCBUF_DITH4_CCBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH4_CCBUF_Pos))
+#define TCC_CCBUF_DITH4_Msk                   _UINT32_(0x0000FFFF)                                 /* (TCC_CCBUF_DITH4) Register Mask  */
+
+/* DITH5 mode */
+#define TCC_CCBUF_DITH5_DITHERBUF_Pos         _UINT32_(0)                                          /* (TCC_CCBUF) Dithering Buffer Cycle Number Position */
+#define TCC_CCBUF_DITH5_DITHERBUF_Msk         (_UINT32_(0x1F) << TCC_CCBUF_DITH5_DITHERBUF_Pos)    /* (TCC_CCBUF) Dithering Buffer Cycle Number Mask */
+#define TCC_CCBUF_DITH5_DITHERBUF(value)      (TCC_CCBUF_DITH5_DITHERBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH5_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH5_CCBUF_Pos             _UINT32_(5)                                          /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Position */
+#define TCC_CCBUF_DITH5_CCBUF_Msk             (_UINT32_(0x7FF) << TCC_CCBUF_DITH5_CCBUF_Pos)       /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Mask */
+#define TCC_CCBUF_DITH5_CCBUF(value)          (TCC_CCBUF_DITH5_CCBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH5_CCBUF_Pos))
+#define TCC_CCBUF_DITH5_Msk                   _UINT32_(0x0000FFFF)                                 /* (TCC_CCBUF_DITH5) Register Mask  */
+
+/* DITH6 mode */
+#define TCC_CCBUF_DITH6_DITHERBUF_Pos         _UINT32_(0)                                          /* (TCC_CCBUF) Dithering Buffer Cycle Number Position */
+#define TCC_CCBUF_DITH6_DITHERBUF_Msk         (_UINT32_(0x3F) << TCC_CCBUF_DITH6_DITHERBUF_Pos)    /* (TCC_CCBUF) Dithering Buffer Cycle Number Mask */
+#define TCC_CCBUF_DITH6_DITHERBUF(value)      (TCC_CCBUF_DITH6_DITHERBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH6_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH6_CCBUF_Pos             _UINT32_(6)                                          /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Position */
+#define TCC_CCBUF_DITH6_CCBUF_Msk             (_UINT32_(0x3FF) << TCC_CCBUF_DITH6_CCBUF_Pos)       /* (TCC_CCBUF) Channel Compare/Capture Buffer Value Mask */
+#define TCC_CCBUF_DITH6_CCBUF(value)          (TCC_CCBUF_DITH6_CCBUF_Msk & (_UINT32_(value) << TCC_CCBUF_DITH6_CCBUF_Pos))
+#define TCC_CCBUF_DITH6_Msk                   _UINT32_(0x0000FFFF)                                 /* (TCC_CCBUF_DITH6) Register Mask  */
+
+
+/* TCC register offsets definitions */
+#define TCC_CTRLA_REG_OFST             _UINT32_(0x00)      /* (TCC_CTRLA) Control A Offset */
+#define TCC_CTRLBCLR_REG_OFST          _UINT32_(0x04)      /* (TCC_CTRLBCLR) Control B Clear Offset */
+#define TCC_CTRLBSET_REG_OFST          _UINT32_(0x05)      /* (TCC_CTRLBSET) Control B Set Offset */
+#define TCC_SYNCBUSY_REG_OFST          _UINT32_(0x08)      /* (TCC_SYNCBUSY) Synchronization Busy Offset */
+#define TCC_FCTRLA_REG_OFST            _UINT32_(0x0C)      /* (TCC_FCTRLA) Recoverable Fault A Configuration Offset */
+#define TCC_FCTRLB_REG_OFST            _UINT32_(0x10)      /* (TCC_FCTRLB) Recoverable Fault B Configuration Offset */
+#define TCC_DRVCTRL_REG_OFST           _UINT32_(0x18)      /* (TCC_DRVCTRL) Driver Control Offset */
+#define TCC_DBGCTRL_REG_OFST           _UINT32_(0x1E)      /* (TCC_DBGCTRL) Debug Control Offset */
+#define TCC_EVCTRL_REG_OFST            _UINT32_(0x20)      /* (TCC_EVCTRL) Event Control Offset */
+#define TCC_INTENCLR_REG_OFST          _UINT32_(0x24)      /* (TCC_INTENCLR) Interrupt Enable Clear Offset */
+#define TCC_INTENSET_REG_OFST          _UINT32_(0x28)      /* (TCC_INTENSET) Interrupt Enable Set Offset */
+#define TCC_INTFLAG_REG_OFST           _UINT32_(0x2C)      /* (TCC_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define TCC_STATUS_REG_OFST            _UINT32_(0x30)      /* (TCC_STATUS) Status Offset */
+#define TCC_COUNT_REG_OFST             _UINT32_(0x34)      /* (TCC_COUNT) Count Offset */
+#define TCC_WAVE_REG_OFST              _UINT32_(0x3C)      /* (TCC_WAVE) Waveform Control Offset */
+#define TCC_PER_REG_OFST               _UINT32_(0x40)      /* (TCC_PER) Period Offset */
+#define TCC_CC_REG_OFST                _UINT32_(0x44)      /* (TCC_CC) Compare and Capture Offset */
+#define TCC_CC0_REG_OFST               _UINT32_(0x44)      /* (TCC_CC0) Compare and Capture Offset */
+#define TCC_CC1_REG_OFST               _UINT32_(0x48)      /* (TCC_CC1) Compare and Capture Offset */
+#define TCC_PERBUF_REG_OFST            _UINT32_(0x6C)      /* (TCC_PERBUF) Period Buffer Offset */
+#define TCC_CCBUF_REG_OFST             _UINT32_(0x70)      /* (TCC_CCBUF) Compare and Capture Buffer Offset */
+#define TCC_CCBUF0_REG_OFST            _UINT32_(0x70)      /* (TCC_CCBUF0) Compare and Capture Buffer Offset */
+#define TCC_CCBUF1_REG_OFST            _UINT32_(0x74)      /* (TCC_CCBUF1) Compare and Capture Buffer Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* TCC register API structure */
+typedef struct
+{  /* Timer Counter for Control Applications */
+  __IO  uint32_t                       TCC_CTRLA;          /* Offset: 0x00 (R/W  32) Control A */
+  __IO  uint8_t                        TCC_CTRLBCLR;       /* Offset: 0x04 (R/W  8) Control B Clear */
+  __IO  uint8_t                        TCC_CTRLBSET;       /* Offset: 0x05 (R/W  8) Control B Set */
+  __I   uint8_t                        Reserved1[0x02];
+  __I   uint32_t                       TCC_SYNCBUSY;       /* Offset: 0x08 (R/   32) Synchronization Busy */
+  __IO  uint32_t                       TCC_FCTRLA;         /* Offset: 0x0C (R/W  32) Recoverable Fault A Configuration */
+  __IO  uint32_t                       TCC_FCTRLB;         /* Offset: 0x10 (R/W  32) Recoverable Fault B Configuration */
+  __I   uint8_t                        Reserved2[0x04];
+  __IO  uint32_t                       TCC_DRVCTRL;        /* Offset: 0x18 (R/W  32) Driver Control */
+  __I   uint8_t                        Reserved3[0x02];
+  __IO  uint8_t                        TCC_DBGCTRL;        /* Offset: 0x1E (R/W  8) Debug Control */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint32_t                       TCC_EVCTRL;         /* Offset: 0x20 (R/W  32) Event Control */
+  __IO  uint32_t                       TCC_INTENCLR;       /* Offset: 0x24 (R/W  32) Interrupt Enable Clear */
+  __IO  uint32_t                       TCC_INTENSET;       /* Offset: 0x28 (R/W  32) Interrupt Enable Set */
+  __IO  uint32_t                       TCC_INTFLAG;        /* Offset: 0x2C (R/W  32) Interrupt Flag Status and Clear */
+  __IO  uint32_t                       TCC_STATUS;         /* Offset: 0x30 (R/W  32) Status */
+  __IO  uint32_t                       TCC_COUNT;          /* Offset: 0x34 (R/W  32) Count */
+  __I   uint8_t                        Reserved5[0x04];
+  __IO  uint32_t                       TCC_WAVE;           /* Offset: 0x3C (R/W  32) Waveform Control */
+  __IO  uint32_t                       TCC_PER;            /* Offset: 0x40 (R/W  32) Period */
+  __IO  uint32_t                       TCC_CC[2];          /* Offset: 0x44 (R/W  32) Compare and Capture */
+  __I   uint8_t                        Reserved6[0x20];
+  __IO  uint32_t                       TCC_PERBUF;         /* Offset: 0x6C (R/W  32) Period Buffer */
+  __IO  uint32_t                       TCC_CCBUF[2];       /* Offset: 0x70 (R/W  32) Compare and Capture Buffer */
+} tcc_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_TCC_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/usb.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/usb.h
new file mode 100644
index 00000000..89df6a0a
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/usb.h
@@ -0,0 +1,1281 @@
+/*
+ * Component description for USB
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_USB_COMPONENT_H_
+#define _PIC32CMGC00_USB_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR USB                       */
+/* ************************************************************************** */
+
+/* -------- USB_DEVICE_ADDR : (USB Offset: 0x00) (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
+#define USB_DEVICE_ADDR_ADDR_Pos              _UINT32_(0)                                          /* (USB_DEVICE_ADDR) Adress of data buffer Position */
+#define USB_DEVICE_ADDR_ADDR_Msk              (_UINT32_(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos)   /* (USB_DEVICE_ADDR) Adress of data buffer Mask */
+#define USB_DEVICE_ADDR_ADDR(value)           (USB_DEVICE_ADDR_ADDR_Msk & (_UINT32_(value) << USB_DEVICE_ADDR_ADDR_Pos)) /* Assignment of value for ADDR in the USB_DEVICE_ADDR register */
+#define USB_DEVICE_ADDR_Msk                   _UINT32_(0xFFFFFFFF)                                 /* (USB_DEVICE_ADDR) Register Mask  */
+
+
+/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x04) (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos     _UINT32_(0)                                          /* (USB_DEVICE_PCKSIZE) Byte Count Position */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk     (_UINT32_(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos) /* (USB_DEVICE_PCKSIZE) Byte Count Mask */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value)  (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & (_UINT32_(value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)) /* Assignment of value for BYTE_COUNT in the USB_DEVICE_PCKSIZE register */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos _UINT32_(14)                                         /* (USB_DEVICE_PCKSIZE) Multi Packet In or Out size Position */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_UINT32_(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) /* (USB_DEVICE_PCKSIZE) Multi Packet In or Out size Mask */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & (_UINT32_(value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)) /* Assignment of value for MULTI_PACKET_SIZE in the USB_DEVICE_PCKSIZE register */
+#define USB_DEVICE_PCKSIZE_SIZE_Pos           _UINT32_(28)                                         /* (USB_DEVICE_PCKSIZE) Enpoint size Position */
+#define USB_DEVICE_PCKSIZE_SIZE_Msk           (_UINT32_(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos)       /* (USB_DEVICE_PCKSIZE) Enpoint size Mask */
+#define USB_DEVICE_PCKSIZE_SIZE(value)        (USB_DEVICE_PCKSIZE_SIZE_Msk & (_UINT32_(value) << USB_DEVICE_PCKSIZE_SIZE_Pos)) /* Assignment of value for SIZE in the USB_DEVICE_PCKSIZE register */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos       _UINT32_(31)                                         /* (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet Position */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Msk       (_UINT32_(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)   /* (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet Mask */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP(value)    (USB_DEVICE_PCKSIZE_AUTO_ZLP_Msk & (_UINT32_(value) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)) /* Assignment of value for AUTO_ZLP in the USB_DEVICE_PCKSIZE register */
+#define USB_DEVICE_PCKSIZE_Msk                _UINT32_(0xFFFFFFFF)                                 /* (USB_DEVICE_PCKSIZE) Register Mask  */
+
+
+/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x08) (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
+#define USB_DEVICE_EXTREG_SUBPID_Pos          _UINT16_(0)                                          /* (USB_DEVICE_EXTREG) SUBPID field send with extended token Position */
+#define USB_DEVICE_EXTREG_SUBPID_Msk          (_UINT16_(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos)      /* (USB_DEVICE_EXTREG) SUBPID field send with extended token Mask */
+#define USB_DEVICE_EXTREG_SUBPID(value)       (USB_DEVICE_EXTREG_SUBPID_Msk & (_UINT16_(value) << USB_DEVICE_EXTREG_SUBPID_Pos)) /* Assignment of value for SUBPID in the USB_DEVICE_EXTREG register */
+#define USB_DEVICE_EXTREG_VARIABLE_Pos        _UINT16_(4)                                          /* (USB_DEVICE_EXTREG) Variable field send with extended token Position */
+#define USB_DEVICE_EXTREG_VARIABLE_Msk        (_UINT16_(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos)  /* (USB_DEVICE_EXTREG) Variable field send with extended token Mask */
+#define USB_DEVICE_EXTREG_VARIABLE(value)     (USB_DEVICE_EXTREG_VARIABLE_Msk & (_UINT16_(value) << USB_DEVICE_EXTREG_VARIABLE_Pos)) /* Assignment of value for VARIABLE in the USB_DEVICE_EXTREG register */
+#define USB_DEVICE_EXTREG_Msk                 _UINT16_(0x7FFF)                                     /* (USB_DEVICE_EXTREG) Register Mask  */
+
+
+/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x0A) (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
+#define USB_DEVICE_STATUS_BK_CRCERR_Pos       _UINT8_(0)                                           /* (USB_DEVICE_STATUS_BK) CRC Error Status Position */
+#define USB_DEVICE_STATUS_BK_CRCERR_Msk       (_UINT8_(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos)    /* (USB_DEVICE_STATUS_BK) CRC Error Status Mask */
+#define USB_DEVICE_STATUS_BK_CRCERR(value)    (USB_DEVICE_STATUS_BK_CRCERR_Msk & (_UINT8_(value) << USB_DEVICE_STATUS_BK_CRCERR_Pos)) /* Assignment of value for CRCERR in the USB_DEVICE_STATUS_BK register */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos    _UINT8_(1)                                           /* (USB_DEVICE_STATUS_BK) Error Flow Status Position */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Msk    (_UINT8_(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos) /* (USB_DEVICE_STATUS_BK) Error Flow Status Mask */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW(value) (USB_DEVICE_STATUS_BK_ERRORFLOW_Msk & (_UINT8_(value) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)) /* Assignment of value for ERRORFLOW in the USB_DEVICE_STATUS_BK register */
+#define USB_DEVICE_STATUS_BK_Msk              _UINT8_(0x03)                                        /* (USB_DEVICE_STATUS_BK) Register Mask  */
+
+
+/* -------- USB_HOST_ADDR : (USB Offset: 0x00) (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
+#define USB_HOST_ADDR_ADDR_Pos                _UINT32_(0)                                          /* (USB_HOST_ADDR) Adress of data buffer Position */
+#define USB_HOST_ADDR_ADDR_Msk                (_UINT32_(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos)     /* (USB_HOST_ADDR) Adress of data buffer Mask */
+#define USB_HOST_ADDR_ADDR(value)             (USB_HOST_ADDR_ADDR_Msk & (_UINT32_(value) << USB_HOST_ADDR_ADDR_Pos)) /* Assignment of value for ADDR in the USB_HOST_ADDR register */
+#define USB_HOST_ADDR_Msk                     _UINT32_(0xFFFFFFFF)                                 /* (USB_HOST_ADDR) Register Mask  */
+
+
+/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x04) (R/W 32) HOST_DESC_BANK Host Bank, Packet Size -------- */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos       _UINT32_(0)                                          /* (USB_HOST_PCKSIZE) Byte Count Position */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk       (_UINT32_(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos) /* (USB_HOST_PCKSIZE) Byte Count Mask */
+#define USB_HOST_PCKSIZE_BYTE_COUNT(value)    (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & (_UINT32_(value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)) /* Assignment of value for BYTE_COUNT in the USB_HOST_PCKSIZE register */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos _UINT32_(14)                                         /* (USB_HOST_PCKSIZE) Multi Packet In or Out size Position */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_UINT32_(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos) /* (USB_HOST_PCKSIZE) Multi Packet In or Out size Mask */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & (_UINT32_(value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)) /* Assignment of value for MULTI_PACKET_SIZE in the USB_HOST_PCKSIZE register */
+#define USB_HOST_PCKSIZE_SIZE_Pos             _UINT32_(28)                                         /* (USB_HOST_PCKSIZE) Pipe size Position */
+#define USB_HOST_PCKSIZE_SIZE_Msk             (_UINT32_(0x7) << USB_HOST_PCKSIZE_SIZE_Pos)         /* (USB_HOST_PCKSIZE) Pipe size Mask */
+#define USB_HOST_PCKSIZE_SIZE(value)          (USB_HOST_PCKSIZE_SIZE_Msk & (_UINT32_(value) << USB_HOST_PCKSIZE_SIZE_Pos)) /* Assignment of value for SIZE in the USB_HOST_PCKSIZE register */
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos         _UINT32_(31)                                         /* (USB_HOST_PCKSIZE) Automatic Zero Length Packet Position */
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Msk         (_UINT32_(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)     /* (USB_HOST_PCKSIZE) Automatic Zero Length Packet Mask */
+#define USB_HOST_PCKSIZE_AUTO_ZLP(value)      (USB_HOST_PCKSIZE_AUTO_ZLP_Msk & (_UINT32_(value) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)) /* Assignment of value for AUTO_ZLP in the USB_HOST_PCKSIZE register */
+#define USB_HOST_PCKSIZE_Msk                  _UINT32_(0xFFFFFFFF)                                 /* (USB_HOST_PCKSIZE) Register Mask  */
+
+
+/* -------- USB_HOST_EXTREG : (USB Offset: 0x08) (R/W 16) HOST_DESC_BANK Host Bank, Extended -------- */
+#define USB_HOST_EXTREG_SUBPID_Pos            _UINT16_(0)                                          /* (USB_HOST_EXTREG) SUBPID field send with extended token Position */
+#define USB_HOST_EXTREG_SUBPID_Msk            (_UINT16_(0xF) << USB_HOST_EXTREG_SUBPID_Pos)        /* (USB_HOST_EXTREG) SUBPID field send with extended token Mask */
+#define USB_HOST_EXTREG_SUBPID(value)         (USB_HOST_EXTREG_SUBPID_Msk & (_UINT16_(value) << USB_HOST_EXTREG_SUBPID_Pos)) /* Assignment of value for SUBPID in the USB_HOST_EXTREG register */
+#define USB_HOST_EXTREG_VARIABLE_Pos          _UINT16_(4)                                          /* (USB_HOST_EXTREG) Variable field send with extended token Position */
+#define USB_HOST_EXTREG_VARIABLE_Msk          (_UINT16_(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos)    /* (USB_HOST_EXTREG) Variable field send with extended token Mask */
+#define USB_HOST_EXTREG_VARIABLE(value)       (USB_HOST_EXTREG_VARIABLE_Msk & (_UINT16_(value) << USB_HOST_EXTREG_VARIABLE_Pos)) /* Assignment of value for VARIABLE in the USB_HOST_EXTREG register */
+#define USB_HOST_EXTREG_Msk                   _UINT16_(0x7FFF)                                     /* (USB_HOST_EXTREG) Register Mask  */
+
+
+/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x0A) (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank -------- */
+#define USB_HOST_STATUS_BK_CRCERR_Pos         _UINT8_(0)                                           /* (USB_HOST_STATUS_BK) CRC Error Status Position */
+#define USB_HOST_STATUS_BK_CRCERR_Msk         (_UINT8_(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos)      /* (USB_HOST_STATUS_BK) CRC Error Status Mask */
+#define USB_HOST_STATUS_BK_CRCERR(value)      (USB_HOST_STATUS_BK_CRCERR_Msk & (_UINT8_(value) << USB_HOST_STATUS_BK_CRCERR_Pos)) /* Assignment of value for CRCERR in the USB_HOST_STATUS_BK register */
+#define USB_HOST_STATUS_BK_ERRORFLOW_Pos      _UINT8_(1)                                           /* (USB_HOST_STATUS_BK) Error Flow Status Position */
+#define USB_HOST_STATUS_BK_ERRORFLOW_Msk      (_UINT8_(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)   /* (USB_HOST_STATUS_BK) Error Flow Status Mask */
+#define USB_HOST_STATUS_BK_ERRORFLOW(value)   (USB_HOST_STATUS_BK_ERRORFLOW_Msk & (_UINT8_(value) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)) /* Assignment of value for ERRORFLOW in the USB_HOST_STATUS_BK register */
+#define USB_HOST_STATUS_BK_Msk                _UINT8_(0x03)                                        /* (USB_HOST_STATUS_BK) Register Mask  */
+
+
+/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x0C) (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
+#define USB_HOST_CTRL_PIPE_RESETVALUE         _UINT16_(0x00)                                       /*  (USB_HOST_CTRL_PIPE) HOST_DESC_BANK Host Bank, Host Control Pipe  Reset Value */
+
+#define USB_HOST_CTRL_PIPE_PDADDR_Pos         _UINT16_(0)                                          /* (USB_HOST_CTRL_PIPE) Pipe Device Adress Position */
+#define USB_HOST_CTRL_PIPE_PDADDR_Msk         (_UINT16_(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos)    /* (USB_HOST_CTRL_PIPE) Pipe Device Adress Mask */
+#define USB_HOST_CTRL_PIPE_PDADDR(value)      (USB_HOST_CTRL_PIPE_PDADDR_Msk & (_UINT16_(value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)) /* Assignment of value for PDADDR in the USB_HOST_CTRL_PIPE register */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Pos         _UINT16_(8)                                          /* (USB_HOST_CTRL_PIPE) Pipe Endpoint Number Position */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Msk         (_UINT16_(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)     /* (USB_HOST_CTRL_PIPE) Pipe Endpoint Number Mask */
+#define USB_HOST_CTRL_PIPE_PEPNUM(value)      (USB_HOST_CTRL_PIPE_PEPNUM_Msk & (_UINT16_(value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)) /* Assignment of value for PEPNUM in the USB_HOST_CTRL_PIPE register */
+#define USB_HOST_CTRL_PIPE_PERMAX_Pos         _UINT16_(12)                                         /* (USB_HOST_CTRL_PIPE) Pipe Error Max Number Position */
+#define USB_HOST_CTRL_PIPE_PERMAX_Msk         (_UINT16_(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos)     /* (USB_HOST_CTRL_PIPE) Pipe Error Max Number Mask */
+#define USB_HOST_CTRL_PIPE_PERMAX(value)      (USB_HOST_CTRL_PIPE_PERMAX_Msk & (_UINT16_(value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)) /* Assignment of value for PERMAX in the USB_HOST_CTRL_PIPE register */
+#define USB_HOST_CTRL_PIPE_Msk                _UINT16_(0xFF7F)                                     /* (USB_HOST_CTRL_PIPE) Register Mask  */
+
+
+/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x0E) (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
+#define USB_HOST_STATUS_PIPE_DTGLER_Pos       _UINT16_(0)                                          /* (USB_HOST_STATUS_PIPE) Data Toggle Error Position */
+#define USB_HOST_STATUS_PIPE_DTGLER_Msk       (_UINT16_(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos)   /* (USB_HOST_STATUS_PIPE) Data Toggle Error Mask */
+#define USB_HOST_STATUS_PIPE_DTGLER(value)    (USB_HOST_STATUS_PIPE_DTGLER_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_DTGLER_Pos)) /* Assignment of value for DTGLER in the USB_HOST_STATUS_PIPE register */
+#define USB_HOST_STATUS_PIPE_DAPIDER_Pos      _UINT16_(1)                                          /* (USB_HOST_STATUS_PIPE) Data PID Error Position */
+#define USB_HOST_STATUS_PIPE_DAPIDER_Msk      (_UINT16_(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)  /* (USB_HOST_STATUS_PIPE) Data PID Error Mask */
+#define USB_HOST_STATUS_PIPE_DAPIDER(value)   (USB_HOST_STATUS_PIPE_DAPIDER_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)) /* Assignment of value for DAPIDER in the USB_HOST_STATUS_PIPE register */
+#define USB_HOST_STATUS_PIPE_PIDER_Pos        _UINT16_(2)                                          /* (USB_HOST_STATUS_PIPE) PID Error Position */
+#define USB_HOST_STATUS_PIPE_PIDER_Msk        (_UINT16_(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos)    /* (USB_HOST_STATUS_PIPE) PID Error Mask */
+#define USB_HOST_STATUS_PIPE_PIDER(value)     (USB_HOST_STATUS_PIPE_PIDER_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_PIDER_Pos)) /* Assignment of value for PIDER in the USB_HOST_STATUS_PIPE register */
+#define USB_HOST_STATUS_PIPE_TOUTER_Pos       _UINT16_(3)                                          /* (USB_HOST_STATUS_PIPE) Time Out Error Position */
+#define USB_HOST_STATUS_PIPE_TOUTER_Msk       (_UINT16_(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos)   /* (USB_HOST_STATUS_PIPE) Time Out Error Mask */
+#define USB_HOST_STATUS_PIPE_TOUTER(value)    (USB_HOST_STATUS_PIPE_TOUTER_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_TOUTER_Pos)) /* Assignment of value for TOUTER in the USB_HOST_STATUS_PIPE register */
+#define USB_HOST_STATUS_PIPE_CRC16ER_Pos      _UINT16_(4)                                          /* (USB_HOST_STATUS_PIPE) CRC16 Error Position */
+#define USB_HOST_STATUS_PIPE_CRC16ER_Msk      (_UINT16_(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)  /* (USB_HOST_STATUS_PIPE) CRC16 Error Mask */
+#define USB_HOST_STATUS_PIPE_CRC16ER(value)   (USB_HOST_STATUS_PIPE_CRC16ER_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)) /* Assignment of value for CRC16ER in the USB_HOST_STATUS_PIPE register */
+#define USB_HOST_STATUS_PIPE_ERCNT_Pos        _UINT16_(5)                                          /* (USB_HOST_STATUS_PIPE) Pipe Error Count Position */
+#define USB_HOST_STATUS_PIPE_ERCNT_Msk        (_UINT16_(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos)    /* (USB_HOST_STATUS_PIPE) Pipe Error Count Mask */
+#define USB_HOST_STATUS_PIPE_ERCNT(value)     (USB_HOST_STATUS_PIPE_ERCNT_Msk & (_UINT16_(value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)) /* Assignment of value for ERCNT in the USB_HOST_STATUS_PIPE register */
+#define USB_HOST_STATUS_PIPE_Msk              _UINT16_(0x00FF)                                     /* (USB_HOST_STATUS_PIPE) Register Mask  */
+
+
+/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x00) (R/W 8) DEVICE_ENDPOINT End Point Configuration -------- */
+#define USB_DEVICE_EPCFG_RESETVALUE           _UINT8_(0x00)                                        /*  (USB_DEVICE_EPCFG) DEVICE_ENDPOINT End Point Configuration  Reset Value */
+
+#define USB_DEVICE_EPCFG_EPTYPE0_Pos          _UINT8_(0)                                           /* (USB_DEVICE_EPCFG) End Point Type0 Position */
+#define USB_DEVICE_EPCFG_EPTYPE0_Msk          (_UINT8_(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos)       /* (USB_DEVICE_EPCFG) End Point Type0 Mask */
+#define USB_DEVICE_EPCFG_EPTYPE0(value)       (USB_DEVICE_EPCFG_EPTYPE0_Msk & (_UINT8_(value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)) /* Assignment of value for EPTYPE0 in the USB_DEVICE_EPCFG register */
+#define USB_DEVICE_EPCFG_EPTYPE1_Pos          _UINT8_(4)                                           /* (USB_DEVICE_EPCFG) End Point Type1 Position */
+#define USB_DEVICE_EPCFG_EPTYPE1_Msk          (_UINT8_(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos)       /* (USB_DEVICE_EPCFG) End Point Type1 Mask */
+#define USB_DEVICE_EPCFG_EPTYPE1(value)       (USB_DEVICE_EPCFG_EPTYPE1_Msk & (_UINT8_(value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)) /* Assignment of value for EPTYPE1 in the USB_DEVICE_EPCFG register */
+#define USB_DEVICE_EPCFG_NYETDIS_Pos          _UINT8_(7)                                           /* (USB_DEVICE_EPCFG) NYET Token Disable Position */
+#define USB_DEVICE_EPCFG_NYETDIS_Msk          (_UINT8_(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos)       /* (USB_DEVICE_EPCFG) NYET Token Disable Mask */
+#define USB_DEVICE_EPCFG_NYETDIS(value)       (USB_DEVICE_EPCFG_NYETDIS_Msk & (_UINT8_(value) << USB_DEVICE_EPCFG_NYETDIS_Pos)) /* Assignment of value for NYETDIS in the USB_DEVICE_EPCFG register */
+#define USB_DEVICE_EPCFG_Msk                  _UINT8_(0xF7)                                        /* (USB_DEVICE_EPCFG) Register Mask  */
+
+
+/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x04) ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
+#define USB_DEVICE_EPSTATUSCLR_RESETVALUE     _UINT8_(0x00)                                        /*  (USB_DEVICE_EPSTATUSCLR) DEVICE_ENDPOINT End Point Pipe Status Clear  Reset Value */
+
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos    _UINT8_(0)                                           /* (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear Position */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Msk    (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos) /* (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear Mask */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT(value) (USB_DEVICE_EPSTATUSCLR_DTGLOUT_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)) /* Assignment of value for DTGLOUT in the USB_DEVICE_EPSTATUSCLR register */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos     _UINT8_(1)                                           /* (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear Position */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Msk     (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)  /* (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear Mask */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN(value)  (USB_DEVICE_EPSTATUSCLR_DTGLIN_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)) /* Assignment of value for DTGLIN in the USB_DEVICE_EPSTATUSCLR register */
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos      _UINT8_(2)                                           /* (USB_DEVICE_EPSTATUSCLR) Current Bank Clear Position */
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Msk      (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)   /* (USB_DEVICE_EPSTATUSCLR) Current Bank Clear Mask */
+#define USB_DEVICE_EPSTATUSCLR_CURBK(value)   (USB_DEVICE_EPSTATUSCLR_CURBK_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)) /* Assignment of value for CURBK in the USB_DEVICE_EPSTATUSCLR register */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos   _UINT8_(4)                                           /* (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear Position */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Msk   (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos) /* (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear Mask */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ0_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)) /* Assignment of value for STALLRQ0 in the USB_DEVICE_EPSTATUSCLR register */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos   _UINT8_(5)                                           /* (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear Position */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Msk   (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos) /* (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear Mask */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ1_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)) /* Assignment of value for STALLRQ1 in the USB_DEVICE_EPSTATUSCLR register */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos     _UINT8_(6)                                           /* (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear Position */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Msk     (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)  /* (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear Mask */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY(value)  (USB_DEVICE_EPSTATUSCLR_BK0RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)) /* Assignment of value for BK0RDY in the USB_DEVICE_EPSTATUSCLR register */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos     _UINT8_(7)                                           /* (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear Position */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Msk     (_UINT8_(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)  /* (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear Mask */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY(value)  (USB_DEVICE_EPSTATUSCLR_BK1RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)) /* Assignment of value for BK1RDY in the USB_DEVICE_EPSTATUSCLR register */
+#define USB_DEVICE_EPSTATUSCLR_Msk            _UINT8_(0xF7)                                        /* (USB_DEVICE_EPSTATUSCLR) Register Mask  */
+
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos    _UINT8_(4)                                           /* (USB_DEVICE_EPSTATUSCLR Position) Stall x Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk    (_UINT8_(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos) /* (USB_DEVICE_EPSTATUSCLR Mask) STALLRQ */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)) 
+
+/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x05) ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set -------- */
+#define USB_DEVICE_EPSTATUSSET_RESETVALUE     _UINT8_(0x00)                                        /*  (USB_DEVICE_EPSTATUSSET) DEVICE_ENDPOINT End Point Pipe Status Set  Reset Value */
+
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos    _UINT8_(0)                                           /* (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set Position */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Msk    (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos) /* (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set Mask */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT(value) (USB_DEVICE_EPSTATUSSET_DTGLOUT_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)) /* Assignment of value for DTGLOUT in the USB_DEVICE_EPSTATUSSET register */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos     _UINT8_(1)                                           /* (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set Position */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Msk     (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)  /* (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set Mask */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN(value)  (USB_DEVICE_EPSTATUSSET_DTGLIN_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)) /* Assignment of value for DTGLIN in the USB_DEVICE_EPSTATUSSET register */
+#define USB_DEVICE_EPSTATUSSET_CURBK_Pos      _UINT8_(2)                                           /* (USB_DEVICE_EPSTATUSSET) Current Bank Set Position */
+#define USB_DEVICE_EPSTATUSSET_CURBK_Msk      (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)   /* (USB_DEVICE_EPSTATUSSET) Current Bank Set Mask */
+#define USB_DEVICE_EPSTATUSSET_CURBK(value)   (USB_DEVICE_EPSTATUSSET_CURBK_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)) /* Assignment of value for CURBK in the USB_DEVICE_EPSTATUSSET register */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos   _UINT8_(4)                                           /* (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set Position */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Msk   (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos) /* (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set Mask */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0(value) (USB_DEVICE_EPSTATUSSET_STALLRQ0_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)) /* Assignment of value for STALLRQ0 in the USB_DEVICE_EPSTATUSSET register */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos   _UINT8_(5)                                           /* (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set Position */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Msk   (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos) /* (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set Mask */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1(value) (USB_DEVICE_EPSTATUSSET_STALLRQ1_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)) /* Assignment of value for STALLRQ1 in the USB_DEVICE_EPSTATUSSET register */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos     _UINT8_(6)                                           /* (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set Position */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Msk     (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)  /* (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set Mask */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY(value)  (USB_DEVICE_EPSTATUSSET_BK0RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)) /* Assignment of value for BK0RDY in the USB_DEVICE_EPSTATUSSET register */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos     _UINT8_(7)                                           /* (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set Position */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Msk     (_UINT8_(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)  /* (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set Mask */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY(value)  (USB_DEVICE_EPSTATUSSET_BK1RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)) /* Assignment of value for BK1RDY in the USB_DEVICE_EPSTATUSSET register */
+#define USB_DEVICE_EPSTATUSSET_Msk            _UINT8_(0xF7)                                        /* (USB_DEVICE_EPSTATUSSET) Register Mask  */
+
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos    _UINT8_(4)                                           /* (USB_DEVICE_EPSTATUSSET Position) Stall x Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk    (_UINT8_(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos) /* (USB_DEVICE_EPSTATUSSET Mask) STALLRQ */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)) 
+
+/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x06) ( R/ 8) DEVICE_ENDPOINT End Point Pipe Status -------- */
+#define USB_DEVICE_EPSTATUS_RESETVALUE        _UINT8_(0x00)                                        /*  (USB_DEVICE_EPSTATUS) DEVICE_ENDPOINT End Point Pipe Status  Reset Value */
+
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos       _UINT8_(0)                                           /* (USB_DEVICE_EPSTATUS) Data Toggle Out Position */
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Msk       (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)    /* (USB_DEVICE_EPSTATUS) Data Toggle Out Mask */
+#define USB_DEVICE_EPSTATUS_DTGLOUT(value)    (USB_DEVICE_EPSTATUS_DTGLOUT_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)) /* Assignment of value for DTGLOUT in the USB_DEVICE_EPSTATUS register */
+#define USB_DEVICE_EPSTATUS_DTGLIN_Pos        _UINT8_(1)                                           /* (USB_DEVICE_EPSTATUS) Data Toggle In Position */
+#define USB_DEVICE_EPSTATUS_DTGLIN_Msk        (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)     /* (USB_DEVICE_EPSTATUS) Data Toggle In Mask */
+#define USB_DEVICE_EPSTATUS_DTGLIN(value)     (USB_DEVICE_EPSTATUS_DTGLIN_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)) /* Assignment of value for DTGLIN in the USB_DEVICE_EPSTATUS register */
+#define USB_DEVICE_EPSTATUS_CURBK_Pos         _UINT8_(2)                                           /* (USB_DEVICE_EPSTATUS) Current Bank Position */
+#define USB_DEVICE_EPSTATUS_CURBK_Msk         (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos)      /* (USB_DEVICE_EPSTATUS) Current Bank Mask */
+#define USB_DEVICE_EPSTATUS_CURBK(value)      (USB_DEVICE_EPSTATUS_CURBK_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_CURBK_Pos)) /* Assignment of value for CURBK in the USB_DEVICE_EPSTATUS register */
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos      _UINT8_(4)                                           /* (USB_DEVICE_EPSTATUS) Stall 0 Request Position */
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Msk      (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)   /* (USB_DEVICE_EPSTATUS) Stall 0 Request Mask */
+#define USB_DEVICE_EPSTATUS_STALLRQ0(value)   (USB_DEVICE_EPSTATUS_STALLRQ0_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)) /* Assignment of value for STALLRQ0 in the USB_DEVICE_EPSTATUS register */
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos      _UINT8_(5)                                           /* (USB_DEVICE_EPSTATUS) Stall 1 Request Position */
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Msk      (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)   /* (USB_DEVICE_EPSTATUS) Stall 1 Request Mask */
+#define USB_DEVICE_EPSTATUS_STALLRQ1(value)   (USB_DEVICE_EPSTATUS_STALLRQ1_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)) /* Assignment of value for STALLRQ1 in the USB_DEVICE_EPSTATUS register */
+#define USB_DEVICE_EPSTATUS_BK0RDY_Pos        _UINT8_(6)                                           /* (USB_DEVICE_EPSTATUS) Bank 0 ready Position */
+#define USB_DEVICE_EPSTATUS_BK0RDY_Msk        (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)     /* (USB_DEVICE_EPSTATUS) Bank 0 ready Mask */
+#define USB_DEVICE_EPSTATUS_BK0RDY(value)     (USB_DEVICE_EPSTATUS_BK0RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)) /* Assignment of value for BK0RDY in the USB_DEVICE_EPSTATUS register */
+#define USB_DEVICE_EPSTATUS_BK1RDY_Pos        _UINT8_(7)                                           /* (USB_DEVICE_EPSTATUS) Bank 1 ready Position */
+#define USB_DEVICE_EPSTATUS_BK1RDY_Msk        (_UINT8_(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)     /* (USB_DEVICE_EPSTATUS) Bank 1 ready Mask */
+#define USB_DEVICE_EPSTATUS_BK1RDY(value)     (USB_DEVICE_EPSTATUS_BK1RDY_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)) /* Assignment of value for BK1RDY in the USB_DEVICE_EPSTATUS register */
+#define USB_DEVICE_EPSTATUS_Msk               _UINT8_(0xF7)                                        /* (USB_DEVICE_EPSTATUS) Register Mask  */
+
+#define USB_DEVICE_EPSTATUS_STALLRQ_Pos       _UINT8_(4)                                           /* (USB_DEVICE_EPSTATUS Position) Stall x Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ_Msk       (_UINT8_(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)    /* (USB_DEVICE_EPSTATUS Mask) STALLRQ */
+#define USB_DEVICE_EPSTATUS_STALLRQ(value)    (USB_DEVICE_EPSTATUS_STALLRQ_Msk & (_UINT8_(value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)) 
+
+/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x07) (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag -------- */
+#define USB_DEVICE_EPINTFLAG_RESETVALUE       _UINT8_(0x00)                                        /*  (USB_DEVICE_EPINTFLAG) DEVICE_ENDPOINT End Point Interrupt Flag  Reset Value */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos       _UINT8_(0)                                           /* (USB_DEVICE_EPINTFLAG) Transfer Complete 0 Position */
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Msk       (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)    /* (USB_DEVICE_EPINTFLAG) Transfer Complete 0 Mask */
+#define USB_DEVICE_EPINTFLAG_TRCPT0(value)    (USB_DEVICE_EPINTFLAG_TRCPT0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)) /* Assignment of value for TRCPT0 in the USB_DEVICE_EPINTFLAG register */
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos       _UINT8_(1)                                           /* (USB_DEVICE_EPINTFLAG) Transfer Complete 1 Position */
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Msk       (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)    /* (USB_DEVICE_EPINTFLAG) Transfer Complete 1 Mask */
+#define USB_DEVICE_EPINTFLAG_TRCPT1(value)    (USB_DEVICE_EPINTFLAG_TRCPT1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)) /* Assignment of value for TRCPT1 in the USB_DEVICE_EPINTFLAG register */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos      _UINT8_(2)                                           /* (USB_DEVICE_EPINTFLAG) Error Flow 0 Position */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Msk      (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)   /* (USB_DEVICE_EPINTFLAG) Error Flow 0 Mask */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0(value)   (USB_DEVICE_EPINTFLAG_TRFAIL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)) /* Assignment of value for TRFAIL0 in the USB_DEVICE_EPINTFLAG register */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos      _UINT8_(3)                                           /* (USB_DEVICE_EPINTFLAG) Error Flow 1 Position */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Msk      (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)   /* (USB_DEVICE_EPINTFLAG) Error Flow 1 Mask */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1(value)   (USB_DEVICE_EPINTFLAG_TRFAIL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)) /* Assignment of value for TRFAIL1 in the USB_DEVICE_EPINTFLAG register */
+#define USB_DEVICE_EPINTFLAG_RXSTP_Pos        _UINT8_(4)                                           /* (USB_DEVICE_EPINTFLAG) Received Setup Position */
+#define USB_DEVICE_EPINTFLAG_RXSTP_Msk        (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)     /* (USB_DEVICE_EPINTFLAG) Received Setup Mask */
+#define USB_DEVICE_EPINTFLAG_RXSTP(value)     (USB_DEVICE_EPINTFLAG_RXSTP_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)) /* Assignment of value for RXSTP in the USB_DEVICE_EPINTFLAG register */
+#define USB_DEVICE_EPINTFLAG_STALL0_Pos       _UINT8_(5)                                           /* (USB_DEVICE_EPINTFLAG) Stall 0 In/out Position */
+#define USB_DEVICE_EPINTFLAG_STALL0_Msk       (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_STALL0_Pos)    /* (USB_DEVICE_EPINTFLAG) Stall 0 In/out Mask */
+#define USB_DEVICE_EPINTFLAG_STALL0(value)    (USB_DEVICE_EPINTFLAG_STALL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_STALL0_Pos)) /* Assignment of value for STALL0 in the USB_DEVICE_EPINTFLAG register */
+#define USB_DEVICE_EPINTFLAG_STALL1_Pos       _UINT8_(6)                                           /* (USB_DEVICE_EPINTFLAG) Stall 1 In/out Position */
+#define USB_DEVICE_EPINTFLAG_STALL1_Msk       (_UINT8_(0x1) << USB_DEVICE_EPINTFLAG_STALL1_Pos)    /* (USB_DEVICE_EPINTFLAG) Stall 1 In/out Mask */
+#define USB_DEVICE_EPINTFLAG_STALL1(value)    (USB_DEVICE_EPINTFLAG_STALL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_STALL1_Pos)) /* Assignment of value for STALL1 in the USB_DEVICE_EPINTFLAG register */
+#define USB_DEVICE_EPINTFLAG_Msk              _UINT8_(0x7F)                                        /* (USB_DEVICE_EPINTFLAG) Register Mask  */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT_Pos        _UINT8_(0)                                           /* (USB_DEVICE_EPINTFLAG Position) Transfer Complete x */
+#define USB_DEVICE_EPINTFLAG_TRCPT_Msk        (_UINT8_(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)     /* (USB_DEVICE_EPINTFLAG Mask) TRCPT */
+#define USB_DEVICE_EPINTFLAG_TRCPT(value)     (USB_DEVICE_EPINTFLAG_TRCPT_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)) 
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos       _UINT8_(2)                                           /* (USB_DEVICE_EPINTFLAG Position) Error Flow x */
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk       (_UINT8_(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)    /* (USB_DEVICE_EPINTFLAG Mask) TRFAIL */
+#define USB_DEVICE_EPINTFLAG_TRFAIL(value)    (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)) 
+#define USB_DEVICE_EPINTFLAG_STALL_Pos        _UINT8_(5)                                           /* (USB_DEVICE_EPINTFLAG Position) Stall x In/out */
+#define USB_DEVICE_EPINTFLAG_STALL_Msk        (_UINT8_(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos)     /* (USB_DEVICE_EPINTFLAG Mask) STALL */
+#define USB_DEVICE_EPINTFLAG_STALL(value)     (USB_DEVICE_EPINTFLAG_STALL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTFLAG_STALL_Pos)) 
+
+/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x08) (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
+#define USB_DEVICE_EPINTENCLR_RESETVALUE      _UINT8_(0x00)                                        /*  (USB_DEVICE_EPINTENCLR) DEVICE_ENDPOINT End Point Interrupt Clear Flag  Reset Value */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos      _UINT8_(0)                                           /* (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable Position */
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Msk      (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)   /* (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable Mask */
+#define USB_DEVICE_EPINTENCLR_TRCPT0(value)   (USB_DEVICE_EPINTENCLR_TRCPT0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)) /* Assignment of value for TRCPT0 in the USB_DEVICE_EPINTENCLR register */
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos      _UINT8_(1)                                           /* (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable Position */
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Msk      (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)   /* (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable Mask */
+#define USB_DEVICE_EPINTENCLR_TRCPT1(value)   (USB_DEVICE_EPINTENCLR_TRCPT1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)) /* Assignment of value for TRCPT1 in the USB_DEVICE_EPINTENCLR register */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos     _UINT8_(2)                                           /* (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable Position */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Msk     (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)  /* (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable Mask */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0(value)  (USB_DEVICE_EPINTENCLR_TRFAIL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)) /* Assignment of value for TRFAIL0 in the USB_DEVICE_EPINTENCLR register */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos     _UINT8_(3)                                           /* (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable Position */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Msk     (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)  /* (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable Mask */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1(value)  (USB_DEVICE_EPINTENCLR_TRFAIL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)) /* Assignment of value for TRFAIL1 in the USB_DEVICE_EPINTENCLR register */
+#define USB_DEVICE_EPINTENCLR_RXSTP_Pos       _UINT8_(4)                                           /* (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable Position */
+#define USB_DEVICE_EPINTENCLR_RXSTP_Msk       (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)    /* (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable Mask */
+#define USB_DEVICE_EPINTENCLR_RXSTP(value)    (USB_DEVICE_EPINTENCLR_RXSTP_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)) /* Assignment of value for RXSTP in the USB_DEVICE_EPINTENCLR register */
+#define USB_DEVICE_EPINTENCLR_STALL0_Pos      _UINT8_(5)                                           /* (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable Position */
+#define USB_DEVICE_EPINTENCLR_STALL0_Msk      (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_STALL0_Pos)   /* (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable Mask */
+#define USB_DEVICE_EPINTENCLR_STALL0(value)   (USB_DEVICE_EPINTENCLR_STALL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_STALL0_Pos)) /* Assignment of value for STALL0 in the USB_DEVICE_EPINTENCLR register */
+#define USB_DEVICE_EPINTENCLR_STALL1_Pos      _UINT8_(6)                                           /* (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable Position */
+#define USB_DEVICE_EPINTENCLR_STALL1_Msk      (_UINT8_(0x1) << USB_DEVICE_EPINTENCLR_STALL1_Pos)   /* (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable Mask */
+#define USB_DEVICE_EPINTENCLR_STALL1(value)   (USB_DEVICE_EPINTENCLR_STALL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_STALL1_Pos)) /* Assignment of value for STALL1 in the USB_DEVICE_EPINTENCLR register */
+#define USB_DEVICE_EPINTENCLR_Msk             _UINT8_(0x7F)                                        /* (USB_DEVICE_EPINTENCLR) Register Mask  */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT_Pos       _UINT8_(0)                                           /* (USB_DEVICE_EPINTENCLR Position) Transfer Complete x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT_Msk       (_UINT8_(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)    /* (USB_DEVICE_EPINTENCLR Mask) TRCPT */
+#define USB_DEVICE_EPINTENCLR_TRCPT(value)    (USB_DEVICE_EPINTENCLR_TRCPT_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)) 
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos      _UINT8_(2)                                           /* (USB_DEVICE_EPINTENCLR Position) Error Flow x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk      (_UINT8_(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)   /* (USB_DEVICE_EPINTENCLR Mask) TRFAIL */
+#define USB_DEVICE_EPINTENCLR_TRFAIL(value)   (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)) 
+#define USB_DEVICE_EPINTENCLR_STALL_Pos       _UINT8_(5)                                           /* (USB_DEVICE_EPINTENCLR Position) Stall x In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL_Msk       (_UINT8_(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos)    /* (USB_DEVICE_EPINTENCLR Mask) STALL */
+#define USB_DEVICE_EPINTENCLR_STALL(value)    (USB_DEVICE_EPINTENCLR_STALL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENCLR_STALL_Pos)) 
+
+/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x09) (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
+#define USB_DEVICE_EPINTENSET_RESETVALUE      _UINT8_(0x00)                                        /*  (USB_DEVICE_EPINTENSET) DEVICE_ENDPOINT End Point Interrupt Set Flag  Reset Value */
+
+#define USB_DEVICE_EPINTENSET_TRCPT0_Pos      _UINT8_(0)                                           /* (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable Position */
+#define USB_DEVICE_EPINTENSET_TRCPT0_Msk      (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_TRCPT0_Pos)   /* (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable Mask */
+#define USB_DEVICE_EPINTENSET_TRCPT0(value)   (USB_DEVICE_EPINTENSET_TRCPT0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRCPT0_Pos)) /* Assignment of value for TRCPT0 in the USB_DEVICE_EPINTENSET register */
+#define USB_DEVICE_EPINTENSET_TRCPT1_Pos      _UINT8_(1)                                           /* (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable Position */
+#define USB_DEVICE_EPINTENSET_TRCPT1_Msk      (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_TRCPT1_Pos)   /* (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable Mask */
+#define USB_DEVICE_EPINTENSET_TRCPT1(value)   (USB_DEVICE_EPINTENSET_TRCPT1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRCPT1_Pos)) /* Assignment of value for TRCPT1 in the USB_DEVICE_EPINTENSET register */
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos     _UINT8_(2)                                           /* (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable Position */
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Msk     (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)  /* (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable Mask */
+#define USB_DEVICE_EPINTENSET_TRFAIL0(value)  (USB_DEVICE_EPINTENSET_TRFAIL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)) /* Assignment of value for TRFAIL0 in the USB_DEVICE_EPINTENSET register */
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos     _UINT8_(3)                                           /* (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable Position */
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Msk     (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)  /* (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable Mask */
+#define USB_DEVICE_EPINTENSET_TRFAIL1(value)  (USB_DEVICE_EPINTENSET_TRFAIL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)) /* Assignment of value for TRFAIL1 in the USB_DEVICE_EPINTENSET register */
+#define USB_DEVICE_EPINTENSET_RXSTP_Pos       _UINT8_(4)                                           /* (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable Position */
+#define USB_DEVICE_EPINTENSET_RXSTP_Msk       (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos)    /* (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable Mask */
+#define USB_DEVICE_EPINTENSET_RXSTP(value)    (USB_DEVICE_EPINTENSET_RXSTP_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_RXSTP_Pos)) /* Assignment of value for RXSTP in the USB_DEVICE_EPINTENSET register */
+#define USB_DEVICE_EPINTENSET_STALL0_Pos      _UINT8_(5)                                           /* (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable Position */
+#define USB_DEVICE_EPINTENSET_STALL0_Msk      (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_STALL0_Pos)   /* (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable Mask */
+#define USB_DEVICE_EPINTENSET_STALL0(value)   (USB_DEVICE_EPINTENSET_STALL0_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_STALL0_Pos)) /* Assignment of value for STALL0 in the USB_DEVICE_EPINTENSET register */
+#define USB_DEVICE_EPINTENSET_STALL1_Pos      _UINT8_(6)                                           /* (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable Position */
+#define USB_DEVICE_EPINTENSET_STALL1_Msk      (_UINT8_(0x1) << USB_DEVICE_EPINTENSET_STALL1_Pos)   /* (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable Mask */
+#define USB_DEVICE_EPINTENSET_STALL1(value)   (USB_DEVICE_EPINTENSET_STALL1_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_STALL1_Pos)) /* Assignment of value for STALL1 in the USB_DEVICE_EPINTENSET register */
+#define USB_DEVICE_EPINTENSET_Msk             _UINT8_(0x7F)                                        /* (USB_DEVICE_EPINTENSET) Register Mask  */
+
+#define USB_DEVICE_EPINTENSET_TRCPT_Pos       _UINT8_(0)                                           /* (USB_DEVICE_EPINTENSET Position) Transfer Complete x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT_Msk       (_UINT8_(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos)    /* (USB_DEVICE_EPINTENSET Mask) TRCPT */
+#define USB_DEVICE_EPINTENSET_TRCPT(value)    (USB_DEVICE_EPINTENSET_TRCPT_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)) 
+#define USB_DEVICE_EPINTENSET_TRFAIL_Pos      _UINT8_(2)                                           /* (USB_DEVICE_EPINTENSET Position) Error Flow x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL_Msk      (_UINT8_(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)   /* (USB_DEVICE_EPINTENSET Mask) TRFAIL */
+#define USB_DEVICE_EPINTENSET_TRFAIL(value)   (USB_DEVICE_EPINTENSET_TRFAIL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)) 
+#define USB_DEVICE_EPINTENSET_STALL_Pos       _UINT8_(5)                                           /* (USB_DEVICE_EPINTENSET Position) Stall x In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL_Msk       (_UINT8_(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos)    /* (USB_DEVICE_EPINTENSET Mask) STALL */
+#define USB_DEVICE_EPINTENSET_STALL(value)    (USB_DEVICE_EPINTENSET_STALL_Msk & (_UINT8_(value) << USB_DEVICE_EPINTENSET_STALL_Pos)) 
+
+/* -------- USB_HOST_PCFG : (USB Offset: 0x00) (R/W 8) HOST_PIPE End Point Configuration -------- */
+#define USB_HOST_PCFG_RESETVALUE              _UINT8_(0x00)                                        /*  (USB_HOST_PCFG) HOST_PIPE End Point Configuration  Reset Value */
+
+#define USB_HOST_PCFG_PTOKEN_Pos              _UINT8_(0)                                           /* (USB_HOST_PCFG) Pipe Token Position */
+#define USB_HOST_PCFG_PTOKEN_Msk              (_UINT8_(0x3) << USB_HOST_PCFG_PTOKEN_Pos)           /* (USB_HOST_PCFG) Pipe Token Mask */
+#define USB_HOST_PCFG_PTOKEN(value)           (USB_HOST_PCFG_PTOKEN_Msk & (_UINT8_(value) << USB_HOST_PCFG_PTOKEN_Pos)) /* Assignment of value for PTOKEN in the USB_HOST_PCFG register */
+#define USB_HOST_PCFG_BK_Pos                  _UINT8_(2)                                           /* (USB_HOST_PCFG) Pipe Bank Position */
+#define USB_HOST_PCFG_BK_Msk                  (_UINT8_(0x1) << USB_HOST_PCFG_BK_Pos)               /* (USB_HOST_PCFG) Pipe Bank Mask */
+#define USB_HOST_PCFG_BK(value)               (USB_HOST_PCFG_BK_Msk & (_UINT8_(value) << USB_HOST_PCFG_BK_Pos)) /* Assignment of value for BK in the USB_HOST_PCFG register */
+#define USB_HOST_PCFG_PTYPE_Pos               _UINT8_(3)                                           /* (USB_HOST_PCFG) Pipe Type Position */
+#define USB_HOST_PCFG_PTYPE_Msk               (_UINT8_(0x7) << USB_HOST_PCFG_PTYPE_Pos)            /* (USB_HOST_PCFG) Pipe Type Mask */
+#define USB_HOST_PCFG_PTYPE(value)            (USB_HOST_PCFG_PTYPE_Msk & (_UINT8_(value) << USB_HOST_PCFG_PTYPE_Pos)) /* Assignment of value for PTYPE in the USB_HOST_PCFG register */
+#define USB_HOST_PCFG_Msk                     _UINT8_(0x3F)                                        /* (USB_HOST_PCFG) Register Mask  */
+
+
+/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x03) (R/W 8) HOST_PIPE Bus Access Period of Pipe -------- */
+#define USB_HOST_BINTERVAL_RESETVALUE         _UINT8_(0x00)                                        /*  (USB_HOST_BINTERVAL) HOST_PIPE Bus Access Period of Pipe  Reset Value */
+
+#define USB_HOST_BINTERVAL_BITINTERVAL_Pos    _UINT8_(0)                                           /* (USB_HOST_BINTERVAL) Bit Interval Position */
+#define USB_HOST_BINTERVAL_BITINTERVAL_Msk    (_UINT8_(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos) /* (USB_HOST_BINTERVAL) Bit Interval Mask */
+#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & (_UINT8_(value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)) /* Assignment of value for BITINTERVAL in the USB_HOST_BINTERVAL register */
+#define USB_HOST_BINTERVAL_Msk                _UINT8_(0xFF)                                        /* (USB_HOST_BINTERVAL) Register Mask  */
+
+
+/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x04) ( /W 8) HOST_PIPE End Point Pipe Status Clear -------- */
+#define USB_HOST_PSTATUSCLR_RESETVALUE        _UINT8_(0x00)                                        /*  (USB_HOST_PSTATUSCLR) HOST_PIPE End Point Pipe Status Clear  Reset Value */
+
+#define USB_HOST_PSTATUSCLR_DTGL_Pos          _UINT8_(0)                                           /* (USB_HOST_PSTATUSCLR) Data Toggle clear Position */
+#define USB_HOST_PSTATUSCLR_DTGL_Msk          (_UINT8_(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos)       /* (USB_HOST_PSTATUSCLR) Data Toggle clear Mask */
+#define USB_HOST_PSTATUSCLR_DTGL(value)       (USB_HOST_PSTATUSCLR_DTGL_Msk & (_UINT8_(value) << USB_HOST_PSTATUSCLR_DTGL_Pos)) /* Assignment of value for DTGL in the USB_HOST_PSTATUSCLR register */
+#define USB_HOST_PSTATUSCLR_CURBK_Pos         _UINT8_(2)                                           /* (USB_HOST_PSTATUSCLR) Curren Bank clear Position */
+#define USB_HOST_PSTATUSCLR_CURBK_Msk         (_UINT8_(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos)      /* (USB_HOST_PSTATUSCLR) Curren Bank clear Mask */
+#define USB_HOST_PSTATUSCLR_CURBK(value)      (USB_HOST_PSTATUSCLR_CURBK_Msk & (_UINT8_(value) << USB_HOST_PSTATUSCLR_CURBK_Pos)) /* Assignment of value for CURBK in the USB_HOST_PSTATUSCLR register */
+#define USB_HOST_PSTATUSCLR_PFREEZE_Pos       _UINT8_(4)                                           /* (USB_HOST_PSTATUSCLR) Pipe Freeze Clear Position */
+#define USB_HOST_PSTATUSCLR_PFREEZE_Msk       (_UINT8_(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)    /* (USB_HOST_PSTATUSCLR) Pipe Freeze Clear Mask */
+#define USB_HOST_PSTATUSCLR_PFREEZE(value)    (USB_HOST_PSTATUSCLR_PFREEZE_Msk & (_UINT8_(value) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)) /* Assignment of value for PFREEZE in the USB_HOST_PSTATUSCLR register */
+#define USB_HOST_PSTATUSCLR_BK0RDY_Pos        _UINT8_(6)                                           /* (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear Position */
+#define USB_HOST_PSTATUSCLR_BK0RDY_Msk        (_UINT8_(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)     /* (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear Mask */
+#define USB_HOST_PSTATUSCLR_BK0RDY(value)     (USB_HOST_PSTATUSCLR_BK0RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)) /* Assignment of value for BK0RDY in the USB_HOST_PSTATUSCLR register */
+#define USB_HOST_PSTATUSCLR_BK1RDY_Pos        _UINT8_(7)                                           /* (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear Position */
+#define USB_HOST_PSTATUSCLR_BK1RDY_Msk        (_UINT8_(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)     /* (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear Mask */
+#define USB_HOST_PSTATUSCLR_BK1RDY(value)     (USB_HOST_PSTATUSCLR_BK1RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)) /* Assignment of value for BK1RDY in the USB_HOST_PSTATUSCLR register */
+#define USB_HOST_PSTATUSCLR_Msk               _UINT8_(0xD5)                                        /* (USB_HOST_PSTATUSCLR) Register Mask  */
+
+
+/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x05) ( /W 8) HOST_PIPE End Point Pipe Status Set -------- */
+#define USB_HOST_PSTATUSSET_RESETVALUE        _UINT8_(0x00)                                        /*  (USB_HOST_PSTATUSSET) HOST_PIPE End Point Pipe Status Set  Reset Value */
+
+#define USB_HOST_PSTATUSSET_DTGL_Pos          _UINT8_(0)                                           /* (USB_HOST_PSTATUSSET) Data Toggle Set Position */
+#define USB_HOST_PSTATUSSET_DTGL_Msk          (_UINT8_(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos)       /* (USB_HOST_PSTATUSSET) Data Toggle Set Mask */
+#define USB_HOST_PSTATUSSET_DTGL(value)       (USB_HOST_PSTATUSSET_DTGL_Msk & (_UINT8_(value) << USB_HOST_PSTATUSSET_DTGL_Pos)) /* Assignment of value for DTGL in the USB_HOST_PSTATUSSET register */
+#define USB_HOST_PSTATUSSET_CURBK_Pos         _UINT8_(2)                                           /* (USB_HOST_PSTATUSSET) Current Bank Set Position */
+#define USB_HOST_PSTATUSSET_CURBK_Msk         (_UINT8_(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos)      /* (USB_HOST_PSTATUSSET) Current Bank Set Mask */
+#define USB_HOST_PSTATUSSET_CURBK(value)      (USB_HOST_PSTATUSSET_CURBK_Msk & (_UINT8_(value) << USB_HOST_PSTATUSSET_CURBK_Pos)) /* Assignment of value for CURBK in the USB_HOST_PSTATUSSET register */
+#define USB_HOST_PSTATUSSET_PFREEZE_Pos       _UINT8_(4)                                           /* (USB_HOST_PSTATUSSET) Pipe Freeze Set Position */
+#define USB_HOST_PSTATUSSET_PFREEZE_Msk       (_UINT8_(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos)    /* (USB_HOST_PSTATUSSET) Pipe Freeze Set Mask */
+#define USB_HOST_PSTATUSSET_PFREEZE(value)    (USB_HOST_PSTATUSSET_PFREEZE_Msk & (_UINT8_(value) << USB_HOST_PSTATUSSET_PFREEZE_Pos)) /* Assignment of value for PFREEZE in the USB_HOST_PSTATUSSET register */
+#define USB_HOST_PSTATUSSET_BK0RDY_Pos        _UINT8_(6)                                           /* (USB_HOST_PSTATUSSET) Bank 0 Ready Set Position */
+#define USB_HOST_PSTATUSSET_BK0RDY_Msk        (_UINT8_(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos)     /* (USB_HOST_PSTATUSSET) Bank 0 Ready Set Mask */
+#define USB_HOST_PSTATUSSET_BK0RDY(value)     (USB_HOST_PSTATUSSET_BK0RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUSSET_BK0RDY_Pos)) /* Assignment of value for BK0RDY in the USB_HOST_PSTATUSSET register */
+#define USB_HOST_PSTATUSSET_BK1RDY_Pos        _UINT8_(7)                                           /* (USB_HOST_PSTATUSSET) Bank 1 Ready Set Position */
+#define USB_HOST_PSTATUSSET_BK1RDY_Msk        (_UINT8_(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos)     /* (USB_HOST_PSTATUSSET) Bank 1 Ready Set Mask */
+#define USB_HOST_PSTATUSSET_BK1RDY(value)     (USB_HOST_PSTATUSSET_BK1RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUSSET_BK1RDY_Pos)) /* Assignment of value for BK1RDY in the USB_HOST_PSTATUSSET register */
+#define USB_HOST_PSTATUSSET_Msk               _UINT8_(0xD5)                                        /* (USB_HOST_PSTATUSSET) Register Mask  */
+
+
+/* -------- USB_HOST_PSTATUS : (USB Offset: 0x06) ( R/ 8) HOST_PIPE End Point Pipe Status -------- */
+#define USB_HOST_PSTATUS_RESETVALUE           _UINT8_(0x00)                                        /*  (USB_HOST_PSTATUS) HOST_PIPE End Point Pipe Status  Reset Value */
+
+#define USB_HOST_PSTATUS_DTGL_Pos             _UINT8_(0)                                           /* (USB_HOST_PSTATUS) Data Toggle Position */
+#define USB_HOST_PSTATUS_DTGL_Msk             (_UINT8_(0x1) << USB_HOST_PSTATUS_DTGL_Pos)          /* (USB_HOST_PSTATUS) Data Toggle Mask */
+#define USB_HOST_PSTATUS_DTGL(value)          (USB_HOST_PSTATUS_DTGL_Msk & (_UINT8_(value) << USB_HOST_PSTATUS_DTGL_Pos)) /* Assignment of value for DTGL in the USB_HOST_PSTATUS register */
+#define USB_HOST_PSTATUS_CURBK_Pos            _UINT8_(2)                                           /* (USB_HOST_PSTATUS) Current Bank Position */
+#define USB_HOST_PSTATUS_CURBK_Msk            (_UINT8_(0x1) << USB_HOST_PSTATUS_CURBK_Pos)         /* (USB_HOST_PSTATUS) Current Bank Mask */
+#define USB_HOST_PSTATUS_CURBK(value)         (USB_HOST_PSTATUS_CURBK_Msk & (_UINT8_(value) << USB_HOST_PSTATUS_CURBK_Pos)) /* Assignment of value for CURBK in the USB_HOST_PSTATUS register */
+#define USB_HOST_PSTATUS_PFREEZE_Pos          _UINT8_(4)                                           /* (USB_HOST_PSTATUS) Pipe Freeze Position */
+#define USB_HOST_PSTATUS_PFREEZE_Msk          (_UINT8_(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos)       /* (USB_HOST_PSTATUS) Pipe Freeze Mask */
+#define USB_HOST_PSTATUS_PFREEZE(value)       (USB_HOST_PSTATUS_PFREEZE_Msk & (_UINT8_(value) << USB_HOST_PSTATUS_PFREEZE_Pos)) /* Assignment of value for PFREEZE in the USB_HOST_PSTATUS register */
+#define USB_HOST_PSTATUS_BK0RDY_Pos           _UINT8_(6)                                           /* (USB_HOST_PSTATUS) Bank 0 ready Position */
+#define USB_HOST_PSTATUS_BK0RDY_Msk           (_UINT8_(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos)        /* (USB_HOST_PSTATUS) Bank 0 ready Mask */
+#define USB_HOST_PSTATUS_BK0RDY(value)        (USB_HOST_PSTATUS_BK0RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUS_BK0RDY_Pos)) /* Assignment of value for BK0RDY in the USB_HOST_PSTATUS register */
+#define USB_HOST_PSTATUS_BK1RDY_Pos           _UINT8_(7)                                           /* (USB_HOST_PSTATUS) Bank 1 ready Position */
+#define USB_HOST_PSTATUS_BK1RDY_Msk           (_UINT8_(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos)        /* (USB_HOST_PSTATUS) Bank 1 ready Mask */
+#define USB_HOST_PSTATUS_BK1RDY(value)        (USB_HOST_PSTATUS_BK1RDY_Msk & (_UINT8_(value) << USB_HOST_PSTATUS_BK1RDY_Pos)) /* Assignment of value for BK1RDY in the USB_HOST_PSTATUS register */
+#define USB_HOST_PSTATUS_Msk                  _UINT8_(0xD5)                                        /* (USB_HOST_PSTATUS) Register Mask  */
+
+
+/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x07) (R/W 8) HOST_PIPE Pipe Interrupt Flag -------- */
+#define USB_HOST_PINTFLAG_RESETVALUE          _UINT8_(0x00)                                        /*  (USB_HOST_PINTFLAG) HOST_PIPE Pipe Interrupt Flag  Reset Value */
+
+#define USB_HOST_PINTFLAG_TRCPT0_Pos          _UINT8_(0)                                           /* (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag Position */
+#define USB_HOST_PINTFLAG_TRCPT0_Msk          (_UINT8_(0x1) << USB_HOST_PINTFLAG_TRCPT0_Pos)       /* (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag Mask */
+#define USB_HOST_PINTFLAG_TRCPT0(value)       (USB_HOST_PINTFLAG_TRCPT0_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_TRCPT0_Pos)) /* Assignment of value for TRCPT0 in the USB_HOST_PINTFLAG register */
+#define USB_HOST_PINTFLAG_TRCPT1_Pos          _UINT8_(1)                                           /* (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag Position */
+#define USB_HOST_PINTFLAG_TRCPT1_Msk          (_UINT8_(0x1) << USB_HOST_PINTFLAG_TRCPT1_Pos)       /* (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag Mask */
+#define USB_HOST_PINTFLAG_TRCPT1(value)       (USB_HOST_PINTFLAG_TRCPT1_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_TRCPT1_Pos)) /* Assignment of value for TRCPT1 in the USB_HOST_PINTFLAG register */
+#define USB_HOST_PINTFLAG_TRFAIL_Pos          _UINT8_(2)                                           /* (USB_HOST_PINTFLAG) Error Flow Interrupt Flag Position */
+#define USB_HOST_PINTFLAG_TRFAIL_Msk          (_UINT8_(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos)       /* (USB_HOST_PINTFLAG) Error Flow Interrupt Flag Mask */
+#define USB_HOST_PINTFLAG_TRFAIL(value)       (USB_HOST_PINTFLAG_TRFAIL_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_TRFAIL_Pos)) /* Assignment of value for TRFAIL in the USB_HOST_PINTFLAG register */
+#define USB_HOST_PINTFLAG_PERR_Pos            _UINT8_(3)                                           /* (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag Position */
+#define USB_HOST_PINTFLAG_PERR_Msk            (_UINT8_(0x1) << USB_HOST_PINTFLAG_PERR_Pos)         /* (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag Mask */
+#define USB_HOST_PINTFLAG_PERR(value)         (USB_HOST_PINTFLAG_PERR_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_PERR_Pos)) /* Assignment of value for PERR in the USB_HOST_PINTFLAG register */
+#define USB_HOST_PINTFLAG_TXSTP_Pos           _UINT8_(4)                                           /* (USB_HOST_PINTFLAG) Transmit  Setup Interrupt Flag Position */
+#define USB_HOST_PINTFLAG_TXSTP_Msk           (_UINT8_(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos)        /* (USB_HOST_PINTFLAG) Transmit  Setup Interrupt Flag Mask */
+#define USB_HOST_PINTFLAG_TXSTP(value)        (USB_HOST_PINTFLAG_TXSTP_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_TXSTP_Pos)) /* Assignment of value for TXSTP in the USB_HOST_PINTFLAG register */
+#define USB_HOST_PINTFLAG_STALL_Pos           _UINT8_(5)                                           /* (USB_HOST_PINTFLAG) Stall Interrupt Flag Position */
+#define USB_HOST_PINTFLAG_STALL_Msk           (_UINT8_(0x1) << USB_HOST_PINTFLAG_STALL_Pos)        /* (USB_HOST_PINTFLAG) Stall Interrupt Flag Mask */
+#define USB_HOST_PINTFLAG_STALL(value)        (USB_HOST_PINTFLAG_STALL_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_STALL_Pos)) /* Assignment of value for STALL in the USB_HOST_PINTFLAG register */
+#define USB_HOST_PINTFLAG_Msk                 _UINT8_(0x3F)                                        /* (USB_HOST_PINTFLAG) Register Mask  */
+
+#define USB_HOST_PINTFLAG_TRCPT_Pos           _UINT8_(0)                                           /* (USB_HOST_PINTFLAG Position) Transfer Complete x Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT_Msk           (_UINT8_(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos)        /* (USB_HOST_PINTFLAG Mask) TRCPT */
+#define USB_HOST_PINTFLAG_TRCPT(value)        (USB_HOST_PINTFLAG_TRCPT_Msk & (_UINT8_(value) << USB_HOST_PINTFLAG_TRCPT_Pos)) 
+
+/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x08) (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear -------- */
+#define USB_HOST_PINTENCLR_RESETVALUE         _UINT8_(0x00)                                        /*  (USB_HOST_PINTENCLR) HOST_PIPE Pipe Interrupt Flag Clear  Reset Value */
+
+#define USB_HOST_PINTENCLR_TRCPT0_Pos         _UINT8_(0)                                           /* (USB_HOST_PINTENCLR) Transfer Complete 0 Disable Position */
+#define USB_HOST_PINTENCLR_TRCPT0_Msk         (_UINT8_(0x1) << USB_HOST_PINTENCLR_TRCPT0_Pos)      /* (USB_HOST_PINTENCLR) Transfer Complete 0 Disable Mask */
+#define USB_HOST_PINTENCLR_TRCPT0(value)      (USB_HOST_PINTENCLR_TRCPT0_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_TRCPT0_Pos)) /* Assignment of value for TRCPT0 in the USB_HOST_PINTENCLR register */
+#define USB_HOST_PINTENCLR_TRCPT1_Pos         _UINT8_(1)                                           /* (USB_HOST_PINTENCLR) Transfer Complete 1 Disable Position */
+#define USB_HOST_PINTENCLR_TRCPT1_Msk         (_UINT8_(0x1) << USB_HOST_PINTENCLR_TRCPT1_Pos)      /* (USB_HOST_PINTENCLR) Transfer Complete 1 Disable Mask */
+#define USB_HOST_PINTENCLR_TRCPT1(value)      (USB_HOST_PINTENCLR_TRCPT1_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_TRCPT1_Pos)) /* Assignment of value for TRCPT1 in the USB_HOST_PINTENCLR register */
+#define USB_HOST_PINTENCLR_TRFAIL_Pos         _UINT8_(2)                                           /* (USB_HOST_PINTENCLR) Error Flow Interrupt Disable Position */
+#define USB_HOST_PINTENCLR_TRFAIL_Msk         (_UINT8_(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos)      /* (USB_HOST_PINTENCLR) Error Flow Interrupt Disable Mask */
+#define USB_HOST_PINTENCLR_TRFAIL(value)      (USB_HOST_PINTENCLR_TRFAIL_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_TRFAIL_Pos)) /* Assignment of value for TRFAIL in the USB_HOST_PINTENCLR register */
+#define USB_HOST_PINTENCLR_PERR_Pos           _UINT8_(3)                                           /* (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable Position */
+#define USB_HOST_PINTENCLR_PERR_Msk           (_UINT8_(0x1) << USB_HOST_PINTENCLR_PERR_Pos)        /* (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable Mask */
+#define USB_HOST_PINTENCLR_PERR(value)        (USB_HOST_PINTENCLR_PERR_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_PERR_Pos)) /* Assignment of value for PERR in the USB_HOST_PINTENCLR register */
+#define USB_HOST_PINTENCLR_TXSTP_Pos          _UINT8_(4)                                           /* (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable Position */
+#define USB_HOST_PINTENCLR_TXSTP_Msk          (_UINT8_(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos)       /* (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable Mask */
+#define USB_HOST_PINTENCLR_TXSTP(value)       (USB_HOST_PINTENCLR_TXSTP_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_TXSTP_Pos)) /* Assignment of value for TXSTP in the USB_HOST_PINTENCLR register */
+#define USB_HOST_PINTENCLR_STALL_Pos          _UINT8_(5)                                           /* (USB_HOST_PINTENCLR) Stall Inetrrupt Disable Position */
+#define USB_HOST_PINTENCLR_STALL_Msk          (_UINT8_(0x1) << USB_HOST_PINTENCLR_STALL_Pos)       /* (USB_HOST_PINTENCLR) Stall Inetrrupt Disable Mask */
+#define USB_HOST_PINTENCLR_STALL(value)       (USB_HOST_PINTENCLR_STALL_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_STALL_Pos)) /* Assignment of value for STALL in the USB_HOST_PINTENCLR register */
+#define USB_HOST_PINTENCLR_Msk                _UINT8_(0x3F)                                        /* (USB_HOST_PINTENCLR) Register Mask  */
+
+#define USB_HOST_PINTENCLR_TRCPT_Pos          _UINT8_(0)                                           /* (USB_HOST_PINTENCLR Position) Transfer Complete x Disable */
+#define USB_HOST_PINTENCLR_TRCPT_Msk          (_UINT8_(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos)       /* (USB_HOST_PINTENCLR Mask) TRCPT */
+#define USB_HOST_PINTENCLR_TRCPT(value)       (USB_HOST_PINTENCLR_TRCPT_Msk & (_UINT8_(value) << USB_HOST_PINTENCLR_TRCPT_Pos)) 
+
+/* -------- USB_HOST_PINTENSET : (USB Offset: 0x09) (R/W 8) HOST_PIPE Pipe Interrupt Flag Set -------- */
+#define USB_HOST_PINTENSET_RESETVALUE         _UINT8_(0x00)                                        /*  (USB_HOST_PINTENSET) HOST_PIPE Pipe Interrupt Flag Set  Reset Value */
+
+#define USB_HOST_PINTENSET_TRCPT0_Pos         _UINT8_(0)                                           /* (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable Position */
+#define USB_HOST_PINTENSET_TRCPT0_Msk         (_UINT8_(0x1) << USB_HOST_PINTENSET_TRCPT0_Pos)      /* (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable Mask */
+#define USB_HOST_PINTENSET_TRCPT0(value)      (USB_HOST_PINTENSET_TRCPT0_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_TRCPT0_Pos)) /* Assignment of value for TRCPT0 in the USB_HOST_PINTENSET register */
+#define USB_HOST_PINTENSET_TRCPT1_Pos         _UINT8_(1)                                           /* (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable Position */
+#define USB_HOST_PINTENSET_TRCPT1_Msk         (_UINT8_(0x1) << USB_HOST_PINTENSET_TRCPT1_Pos)      /* (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable Mask */
+#define USB_HOST_PINTENSET_TRCPT1(value)      (USB_HOST_PINTENSET_TRCPT1_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_TRCPT1_Pos)) /* Assignment of value for TRCPT1 in the USB_HOST_PINTENSET register */
+#define USB_HOST_PINTENSET_TRFAIL_Pos         _UINT8_(2)                                           /* (USB_HOST_PINTENSET) Error Flow Interrupt Enable Position */
+#define USB_HOST_PINTENSET_TRFAIL_Msk         (_UINT8_(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos)      /* (USB_HOST_PINTENSET) Error Flow Interrupt Enable Mask */
+#define USB_HOST_PINTENSET_TRFAIL(value)      (USB_HOST_PINTENSET_TRFAIL_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_TRFAIL_Pos)) /* Assignment of value for TRFAIL in the USB_HOST_PINTENSET register */
+#define USB_HOST_PINTENSET_PERR_Pos           _UINT8_(3)                                           /* (USB_HOST_PINTENSET) Pipe Error Interrupt Enable Position */
+#define USB_HOST_PINTENSET_PERR_Msk           (_UINT8_(0x1) << USB_HOST_PINTENSET_PERR_Pos)        /* (USB_HOST_PINTENSET) Pipe Error Interrupt Enable Mask */
+#define USB_HOST_PINTENSET_PERR(value)        (USB_HOST_PINTENSET_PERR_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_PERR_Pos)) /* Assignment of value for PERR in the USB_HOST_PINTENSET register */
+#define USB_HOST_PINTENSET_TXSTP_Pos          _UINT8_(4)                                           /* (USB_HOST_PINTENSET) Transmit  Setup Interrupt Enable Position */
+#define USB_HOST_PINTENSET_TXSTP_Msk          (_UINT8_(0x1) << USB_HOST_PINTENSET_TXSTP_Pos)       /* (USB_HOST_PINTENSET) Transmit  Setup Interrupt Enable Mask */
+#define USB_HOST_PINTENSET_TXSTP(value)       (USB_HOST_PINTENSET_TXSTP_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_TXSTP_Pos)) /* Assignment of value for TXSTP in the USB_HOST_PINTENSET register */
+#define USB_HOST_PINTENSET_STALL_Pos          _UINT8_(5)                                           /* (USB_HOST_PINTENSET) Stall Interrupt Enable Position */
+#define USB_HOST_PINTENSET_STALL_Msk          (_UINT8_(0x1) << USB_HOST_PINTENSET_STALL_Pos)       /* (USB_HOST_PINTENSET) Stall Interrupt Enable Mask */
+#define USB_HOST_PINTENSET_STALL(value)       (USB_HOST_PINTENSET_STALL_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_STALL_Pos)) /* Assignment of value for STALL in the USB_HOST_PINTENSET register */
+#define USB_HOST_PINTENSET_Msk                _UINT8_(0x3F)                                        /* (USB_HOST_PINTENSET) Register Mask  */
+
+#define USB_HOST_PINTENSET_TRCPT_Pos          _UINT8_(0)                                           /* (USB_HOST_PINTENSET Position) Transfer Complete x Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT_Msk          (_UINT8_(0x3) << USB_HOST_PINTENSET_TRCPT_Pos)       /* (USB_HOST_PINTENSET Mask) TRCPT */
+#define USB_HOST_PINTENSET_TRCPT(value)       (USB_HOST_PINTENSET_TRCPT_Msk & (_UINT8_(value) << USB_HOST_PINTENSET_TRCPT_Pos)) 
+
+/* -------- USB_CTRLA : (USB Offset: 0x00) (R/W 8) Control A -------- */
+#define USB_CTRLA_RESETVALUE                  _UINT8_(0x00)                                        /*  (USB_CTRLA) Control A  Reset Value */
+
+#define USB_CTRLA_SWRST_Pos                   _UINT8_(0)                                           /* (USB_CTRLA) Software Reset Position */
+#define USB_CTRLA_SWRST_Msk                   (_UINT8_(0x1) << USB_CTRLA_SWRST_Pos)                /* (USB_CTRLA) Software Reset Mask */
+#define USB_CTRLA_SWRST(value)                (USB_CTRLA_SWRST_Msk & (_UINT8_(value) << USB_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the USB_CTRLA register */
+#define USB_CTRLA_ENABLE_Pos                  _UINT8_(1)                                           /* (USB_CTRLA) Enable Position */
+#define USB_CTRLA_ENABLE_Msk                  (_UINT8_(0x1) << USB_CTRLA_ENABLE_Pos)               /* (USB_CTRLA) Enable Mask */
+#define USB_CTRLA_ENABLE(value)               (USB_CTRLA_ENABLE_Msk & (_UINT8_(value) << USB_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the USB_CTRLA register */
+#define USB_CTRLA_RUNSTDBY_Pos                _UINT8_(2)                                           /* (USB_CTRLA) Run in Standby Mode Position */
+#define USB_CTRLA_RUNSTDBY_Msk                (_UINT8_(0x1) << USB_CTRLA_RUNSTDBY_Pos)             /* (USB_CTRLA) Run in Standby Mode Mask */
+#define USB_CTRLA_RUNSTDBY(value)             (USB_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << USB_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the USB_CTRLA register */
+#define USB_CTRLA_MODE_Pos                    _UINT8_(7)                                           /* (USB_CTRLA) Operating Mode Position */
+#define USB_CTRLA_MODE_Msk                    (_UINT8_(0x1) << USB_CTRLA_MODE_Pos)                 /* (USB_CTRLA) Operating Mode Mask */
+#define USB_CTRLA_MODE(value)                 (USB_CTRLA_MODE_Msk & (_UINT8_(value) << USB_CTRLA_MODE_Pos)) /* Assignment of value for MODE in the USB_CTRLA register */
+#define   USB_CTRLA_MODE_DEVICE_Val           _UINT8_(0x0)                                         /* (USB_CTRLA) Device Mode  */
+#define   USB_CTRLA_MODE_HOST_Val             _UINT8_(0x1)                                         /* (USB_CTRLA) Host Mode  */
+#define USB_CTRLA_MODE_DEVICE                 (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)    /* (USB_CTRLA) Device Mode Position */
+#define USB_CTRLA_MODE_HOST                   (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)      /* (USB_CTRLA) Host Mode Position */
+#define USB_CTRLA_Msk                         _UINT8_(0x87)                                        /* (USB_CTRLA) Register Mask  */
+
+
+/* -------- USB_SYNCBUSY : (USB Offset: 0x02) ( R/ 8) Synchronization Busy -------- */
+#define USB_SYNCBUSY_RESETVALUE               _UINT8_(0x00)                                        /*  (USB_SYNCBUSY) Synchronization Busy  Reset Value */
+
+#define USB_SYNCBUSY_SWRST_Pos                _UINT8_(0)                                           /* (USB_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define USB_SYNCBUSY_SWRST_Msk                (_UINT8_(0x1) << USB_SYNCBUSY_SWRST_Pos)             /* (USB_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define USB_SYNCBUSY_SWRST(value)             (USB_SYNCBUSY_SWRST_Msk & (_UINT8_(value) << USB_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the USB_SYNCBUSY register */
+#define USB_SYNCBUSY_ENABLE_Pos               _UINT8_(1)                                           /* (USB_SYNCBUSY) Enable Synchronization Busy Position */
+#define USB_SYNCBUSY_ENABLE_Msk               (_UINT8_(0x1) << USB_SYNCBUSY_ENABLE_Pos)            /* (USB_SYNCBUSY) Enable Synchronization Busy Mask */
+#define USB_SYNCBUSY_ENABLE(value)            (USB_SYNCBUSY_ENABLE_Msk & (_UINT8_(value) << USB_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the USB_SYNCBUSY register */
+#define USB_SYNCBUSY_Msk                      _UINT8_(0x03)                                        /* (USB_SYNCBUSY) Register Mask  */
+
+
+/* -------- USB_QOSCTRL : (USB Offset: 0x03) (R/W 8) USB Quality Of Service -------- */
+#define USB_QOSCTRL_RESETVALUE                _UINT8_(0x0F)                                        /*  (USB_QOSCTRL) USB Quality Of Service  Reset Value */
+
+#define USB_QOSCTRL_CQOS_Pos                  _UINT8_(0)                                           /* (USB_QOSCTRL) Configuration Quality of Service Position */
+#define USB_QOSCTRL_CQOS_Msk                  (_UINT8_(0x3) << USB_QOSCTRL_CQOS_Pos)               /* (USB_QOSCTRL) Configuration Quality of Service Mask */
+#define USB_QOSCTRL_CQOS(value)               (USB_QOSCTRL_CQOS_Msk & (_UINT8_(value) << USB_QOSCTRL_CQOS_Pos)) /* Assignment of value for CQOS in the USB_QOSCTRL register */
+#define USB_QOSCTRL_DQOS_Pos                  _UINT8_(2)                                           /* (USB_QOSCTRL) Data Quality of Service Position */
+#define USB_QOSCTRL_DQOS_Msk                  (_UINT8_(0x3) << USB_QOSCTRL_DQOS_Pos)               /* (USB_QOSCTRL) Data Quality of Service Mask */
+#define USB_QOSCTRL_DQOS(value)               (USB_QOSCTRL_DQOS_Msk & (_UINT8_(value) << USB_QOSCTRL_DQOS_Pos)) /* Assignment of value for DQOS in the USB_QOSCTRL register */
+#define USB_QOSCTRL_Msk                       _UINT8_(0x0F)                                        /* (USB_QOSCTRL) Register Mask  */
+
+
+/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x08) (R/W 16) DEVICE Control B -------- */
+#define USB_DEVICE_CTRLB_RESETVALUE           _UINT16_(0x01)                                       /*  (USB_DEVICE_CTRLB) DEVICE Control B  Reset Value */
+
+#define USB_DEVICE_CTRLB_DETACH_Pos           _UINT16_(0)                                          /* (USB_DEVICE_CTRLB) Detach Position */
+#define USB_DEVICE_CTRLB_DETACH_Msk           (_UINT16_(0x1) << USB_DEVICE_CTRLB_DETACH_Pos)       /* (USB_DEVICE_CTRLB) Detach Mask */
+#define USB_DEVICE_CTRLB_DETACH(value)        (USB_DEVICE_CTRLB_DETACH_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_DETACH_Pos)) /* Assignment of value for DETACH in the USB_DEVICE_CTRLB register */
+#define USB_DEVICE_CTRLB_UPRSM_Pos            _UINT16_(1)                                          /* (USB_DEVICE_CTRLB) Upstream Resume Position */
+#define USB_DEVICE_CTRLB_UPRSM_Msk            (_UINT16_(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos)        /* (USB_DEVICE_CTRLB) Upstream Resume Mask */
+#define USB_DEVICE_CTRLB_UPRSM(value)         (USB_DEVICE_CTRLB_UPRSM_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_UPRSM_Pos)) /* Assignment of value for UPRSM in the USB_DEVICE_CTRLB register */
+#define USB_DEVICE_CTRLB_SPDCONF_Pos          _UINT16_(2)                                          /* (USB_DEVICE_CTRLB) Speed Configuration Position */
+#define USB_DEVICE_CTRLB_SPDCONF_Msk          (_UINT16_(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos)      /* (USB_DEVICE_CTRLB) Speed Configuration Mask */
+#define USB_DEVICE_CTRLB_SPDCONF(value)       (USB_DEVICE_CTRLB_SPDCONF_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_SPDCONF_Pos)) /* Assignment of value for SPDCONF in the USB_DEVICE_CTRLB register */
+#define   USB_DEVICE_CTRLB_SPDCONF_FS_Val     _UINT16_(0x0)                                        /* (USB_DEVICE_CTRLB) FS : Full Speed  */
+#define   USB_DEVICE_CTRLB_SPDCONF_LS_Val     _UINT16_(0x1)                                        /* (USB_DEVICE_CTRLB) LS : Low Speed  */
+#define   USB_DEVICE_CTRLB_SPDCONF_HS_Val     _UINT16_(0x2)                                        /* (USB_DEVICE_CTRLB) HS : High Speed capable  */
+#define   USB_DEVICE_CTRLB_SPDCONF_HSTM_Val   _UINT16_(0x3)                                        /* (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode)  */
+#define USB_DEVICE_CTRLB_SPDCONF_FS           (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) /* (USB_DEVICE_CTRLB) FS : Full Speed Position */
+#define USB_DEVICE_CTRLB_SPDCONF_LS           (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) /* (USB_DEVICE_CTRLB) LS : Low Speed Position */
+#define USB_DEVICE_CTRLB_SPDCONF_HS           (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) /* (USB_DEVICE_CTRLB) HS : High Speed capable Position */
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM         (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) /* (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) Position */
+#define USB_DEVICE_CTRLB_NREPLY_Pos           _UINT16_(4)                                          /* (USB_DEVICE_CTRLB) No Reply Position */
+#define USB_DEVICE_CTRLB_NREPLY_Msk           (_UINT16_(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos)       /* (USB_DEVICE_CTRLB) No Reply Mask */
+#define USB_DEVICE_CTRLB_NREPLY(value)        (USB_DEVICE_CTRLB_NREPLY_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_NREPLY_Pos)) /* Assignment of value for NREPLY in the USB_DEVICE_CTRLB register */
+#define USB_DEVICE_CTRLB_TSTJ_Pos             _UINT16_(5)                                          /* (USB_DEVICE_CTRLB) Test mode J Position */
+#define USB_DEVICE_CTRLB_TSTJ_Msk             (_UINT16_(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos)         /* (USB_DEVICE_CTRLB) Test mode J Mask */
+#define USB_DEVICE_CTRLB_TSTJ(value)          (USB_DEVICE_CTRLB_TSTJ_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_TSTJ_Pos)) /* Assignment of value for TSTJ in the USB_DEVICE_CTRLB register */
+#define USB_DEVICE_CTRLB_TSTK_Pos             _UINT16_(6)                                          /* (USB_DEVICE_CTRLB) Test mode K Position */
+#define USB_DEVICE_CTRLB_TSTK_Msk             (_UINT16_(0x1) << USB_DEVICE_CTRLB_TSTK_Pos)         /* (USB_DEVICE_CTRLB) Test mode K Mask */
+#define USB_DEVICE_CTRLB_TSTK(value)          (USB_DEVICE_CTRLB_TSTK_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_TSTK_Pos)) /* Assignment of value for TSTK in the USB_DEVICE_CTRLB register */
+#define USB_DEVICE_CTRLB_TSTPCKT_Pos          _UINT16_(7)                                          /* (USB_DEVICE_CTRLB) Test packet mode Position */
+#define USB_DEVICE_CTRLB_TSTPCKT_Msk          (_UINT16_(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos)      /* (USB_DEVICE_CTRLB) Test packet mode Mask */
+#define USB_DEVICE_CTRLB_TSTPCKT(value)       (USB_DEVICE_CTRLB_TSTPCKT_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_TSTPCKT_Pos)) /* Assignment of value for TSTPCKT in the USB_DEVICE_CTRLB register */
+#define USB_DEVICE_CTRLB_OPMODE2_Pos          _UINT16_(8)                                          /* (USB_DEVICE_CTRLB) Specific Operational Mode Position */
+#define USB_DEVICE_CTRLB_OPMODE2_Msk          (_UINT16_(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos)      /* (USB_DEVICE_CTRLB) Specific Operational Mode Mask */
+#define USB_DEVICE_CTRLB_OPMODE2(value)       (USB_DEVICE_CTRLB_OPMODE2_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_OPMODE2_Pos)) /* Assignment of value for OPMODE2 in the USB_DEVICE_CTRLB register */
+#define USB_DEVICE_CTRLB_GNAK_Pos             _UINT16_(9)                                          /* (USB_DEVICE_CTRLB) Global NAK Position */
+#define USB_DEVICE_CTRLB_GNAK_Msk             (_UINT16_(0x1) << USB_DEVICE_CTRLB_GNAK_Pos)         /* (USB_DEVICE_CTRLB) Global NAK Mask */
+#define USB_DEVICE_CTRLB_GNAK(value)          (USB_DEVICE_CTRLB_GNAK_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_GNAK_Pos)) /* Assignment of value for GNAK in the USB_DEVICE_CTRLB register */
+#define USB_DEVICE_CTRLB_LPMHDSK_Pos          _UINT16_(10)                                         /* (USB_DEVICE_CTRLB) Link Power Management Handshake Position */
+#define USB_DEVICE_CTRLB_LPMHDSK_Msk          (_UINT16_(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos)      /* (USB_DEVICE_CTRLB) Link Power Management Handshake Mask */
+#define USB_DEVICE_CTRLB_LPMHDSK(value)       (USB_DEVICE_CTRLB_LPMHDSK_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)) /* Assignment of value for LPMHDSK in the USB_DEVICE_CTRLB register */
+#define   USB_DEVICE_CTRLB_LPMHDSK_NO_Val     _UINT16_(0x0)                                        /* (USB_DEVICE_CTRLB) No handshake. LPM is not supported  */
+#define   USB_DEVICE_CTRLB_LPMHDSK_ACK_Val    _UINT16_(0x1)                                        /* (USB_DEVICE_CTRLB) ACK  */
+#define   USB_DEVICE_CTRLB_LPMHDSK_NYET_Val   _UINT16_(0x2)                                        /* (USB_DEVICE_CTRLB) NYET  */
+#define   USB_DEVICE_CTRLB_LPMHDSK_STALL_Val  _UINT16_(0x3)                                        /* (USB_DEVICE_CTRLB) STALL  */
+#define USB_DEVICE_CTRLB_LPMHDSK_NO           (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) /* (USB_DEVICE_CTRLB) No handshake. LPM is not supported Position */
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK          (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) /* (USB_DEVICE_CTRLB) ACK Position */
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET         (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) /* (USB_DEVICE_CTRLB) NYET Position */
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL        (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) /* (USB_DEVICE_CTRLB) STALL Position */
+#define USB_DEVICE_CTRLB_Msk                  _UINT16_(0x0FFF)                                     /* (USB_DEVICE_CTRLB) Register Mask  */
+
+#define USB_DEVICE_CTRLB_OPMODE_Pos           _UINT16_(8)                                          /* (USB_DEVICE_CTRLB Position) Specific Operational Mode */
+#define USB_DEVICE_CTRLB_OPMODE_Msk           (_UINT16_(0x1) << USB_DEVICE_CTRLB_OPMODE_Pos)       /* (USB_DEVICE_CTRLB Mask) OPMODE */
+#define USB_DEVICE_CTRLB_OPMODE(value)        (USB_DEVICE_CTRLB_OPMODE_Msk & (_UINT16_(value) << USB_DEVICE_CTRLB_OPMODE_Pos)) 
+
+/* -------- USB_HOST_CTRLB : (USB Offset: 0x08) (R/W 16) HOST Control B -------- */
+#define USB_HOST_CTRLB_RESETVALUE             _UINT16_(0x00)                                       /*  (USB_HOST_CTRLB) HOST Control B  Reset Value */
+
+#define USB_HOST_CTRLB_RESUME_Pos             _UINT16_(1)                                          /* (USB_HOST_CTRLB) Send USB Resume Position */
+#define USB_HOST_CTRLB_RESUME_Msk             (_UINT16_(0x1) << USB_HOST_CTRLB_RESUME_Pos)         /* (USB_HOST_CTRLB) Send USB Resume Mask */
+#define USB_HOST_CTRLB_RESUME(value)          (USB_HOST_CTRLB_RESUME_Msk & (_UINT16_(value) << USB_HOST_CTRLB_RESUME_Pos)) /* Assignment of value for RESUME in the USB_HOST_CTRLB register */
+#define USB_HOST_CTRLB_SPDCONF_Pos            _UINT16_(2)                                          /* (USB_HOST_CTRLB) Speed Configuration for Host Position */
+#define USB_HOST_CTRLB_SPDCONF_Msk            (_UINT16_(0x3) << USB_HOST_CTRLB_SPDCONF_Pos)        /* (USB_HOST_CTRLB) Speed Configuration for Host Mask */
+#define USB_HOST_CTRLB_SPDCONF(value)         (USB_HOST_CTRLB_SPDCONF_Msk & (_UINT16_(value) << USB_HOST_CTRLB_SPDCONF_Pos)) /* Assignment of value for SPDCONF in the USB_HOST_CTRLB register */
+#define   USB_HOST_CTRLB_SPDCONF_NORMAL_Val   _UINT16_(0x0)                                        /* (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.  */
+#define   USB_HOST_CTRLB_SPDCONF_FS_Val       _UINT16_(0x3)                                        /* (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.  */
+#define USB_HOST_CTRLB_SPDCONF_NORMAL         (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos) /* (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. Position */
+#define USB_HOST_CTRLB_SPDCONF_FS             (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos) /* (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. Position */
+#define USB_HOST_CTRLB_AUTORESUME_Pos         _UINT16_(4)                                          /* (USB_HOST_CTRLB) Auto Resume Enable Position */
+#define USB_HOST_CTRLB_AUTORESUME_Msk         (_UINT16_(0x1) << USB_HOST_CTRLB_AUTORESUME_Pos)     /* (USB_HOST_CTRLB) Auto Resume Enable Mask */
+#define USB_HOST_CTRLB_AUTORESUME(value)      (USB_HOST_CTRLB_AUTORESUME_Msk & (_UINT16_(value) << USB_HOST_CTRLB_AUTORESUME_Pos)) /* Assignment of value for AUTORESUME in the USB_HOST_CTRLB register */
+#define USB_HOST_CTRLB_TSTJ_Pos               _UINT16_(5)                                          /* (USB_HOST_CTRLB) Test mode J Position */
+#define USB_HOST_CTRLB_TSTJ_Msk               (_UINT16_(0x1) << USB_HOST_CTRLB_TSTJ_Pos)           /* (USB_HOST_CTRLB) Test mode J Mask */
+#define USB_HOST_CTRLB_TSTJ(value)            (USB_HOST_CTRLB_TSTJ_Msk & (_UINT16_(value) << USB_HOST_CTRLB_TSTJ_Pos)) /* Assignment of value for TSTJ in the USB_HOST_CTRLB register */
+#define USB_HOST_CTRLB_TSTK_Pos               _UINT16_(6)                                          /* (USB_HOST_CTRLB) Test mode K Position */
+#define USB_HOST_CTRLB_TSTK_Msk               (_UINT16_(0x1) << USB_HOST_CTRLB_TSTK_Pos)           /* (USB_HOST_CTRLB) Test mode K Mask */
+#define USB_HOST_CTRLB_TSTK(value)            (USB_HOST_CTRLB_TSTK_Msk & (_UINT16_(value) << USB_HOST_CTRLB_TSTK_Pos)) /* Assignment of value for TSTK in the USB_HOST_CTRLB register */
+#define USB_HOST_CTRLB_SOFE_Pos               _UINT16_(8)                                          /* (USB_HOST_CTRLB) Start of Frame Generation Enable Position */
+#define USB_HOST_CTRLB_SOFE_Msk               (_UINT16_(0x1) << USB_HOST_CTRLB_SOFE_Pos)           /* (USB_HOST_CTRLB) Start of Frame Generation Enable Mask */
+#define USB_HOST_CTRLB_SOFE(value)            (USB_HOST_CTRLB_SOFE_Msk & (_UINT16_(value) << USB_HOST_CTRLB_SOFE_Pos)) /* Assignment of value for SOFE in the USB_HOST_CTRLB register */
+#define USB_HOST_CTRLB_BUSRESET_Pos           _UINT16_(9)                                          /* (USB_HOST_CTRLB) Send USB Reset Position */
+#define USB_HOST_CTRLB_BUSRESET_Msk           (_UINT16_(0x1) << USB_HOST_CTRLB_BUSRESET_Pos)       /* (USB_HOST_CTRLB) Send USB Reset Mask */
+#define USB_HOST_CTRLB_BUSRESET(value)        (USB_HOST_CTRLB_BUSRESET_Msk & (_UINT16_(value) << USB_HOST_CTRLB_BUSRESET_Pos)) /* Assignment of value for BUSRESET in the USB_HOST_CTRLB register */
+#define USB_HOST_CTRLB_VBUSOK_Pos             _UINT16_(10)                                         /* (USB_HOST_CTRLB) VBUS is OK Position */
+#define USB_HOST_CTRLB_VBUSOK_Msk             (_UINT16_(0x1) << USB_HOST_CTRLB_VBUSOK_Pos)         /* (USB_HOST_CTRLB) VBUS is OK Mask */
+#define USB_HOST_CTRLB_VBUSOK(value)          (USB_HOST_CTRLB_VBUSOK_Msk & (_UINT16_(value) << USB_HOST_CTRLB_VBUSOK_Pos)) /* Assignment of value for VBUSOK in the USB_HOST_CTRLB register */
+#define USB_HOST_CTRLB_L1RESUME_Pos           _UINT16_(11)                                         /* (USB_HOST_CTRLB) Send L1 Resume Position */
+#define USB_HOST_CTRLB_L1RESUME_Msk           (_UINT16_(0x1) << USB_HOST_CTRLB_L1RESUME_Pos)       /* (USB_HOST_CTRLB) Send L1 Resume Mask */
+#define USB_HOST_CTRLB_L1RESUME(value)        (USB_HOST_CTRLB_L1RESUME_Msk & (_UINT16_(value) << USB_HOST_CTRLB_L1RESUME_Pos)) /* Assignment of value for L1RESUME in the USB_HOST_CTRLB register */
+#define USB_HOST_CTRLB_Msk                    _UINT16_(0x0F7E)                                     /* (USB_HOST_CTRLB) Register Mask  */
+
+
+/* -------- USB_DEVICE_DADD : (USB Offset: 0x0A) (R/W 8) DEVICE Device Address -------- */
+#define USB_DEVICE_DADD_RESETVALUE            _UINT8_(0x00)                                        /*  (USB_DEVICE_DADD) DEVICE Device Address  Reset Value */
+
+#define USB_DEVICE_DADD_DADD_Pos              _UINT8_(0)                                           /* (USB_DEVICE_DADD) Device Address Position */
+#define USB_DEVICE_DADD_DADD_Msk              (_UINT8_(0x7F) << USB_DEVICE_DADD_DADD_Pos)          /* (USB_DEVICE_DADD) Device Address Mask */
+#define USB_DEVICE_DADD_DADD(value)           (USB_DEVICE_DADD_DADD_Msk & (_UINT8_(value) << USB_DEVICE_DADD_DADD_Pos)) /* Assignment of value for DADD in the USB_DEVICE_DADD register */
+#define USB_DEVICE_DADD_ADDEN_Pos             _UINT8_(7)                                           /* (USB_DEVICE_DADD) Device Address Enable Position */
+#define USB_DEVICE_DADD_ADDEN_Msk             (_UINT8_(0x1) << USB_DEVICE_DADD_ADDEN_Pos)          /* (USB_DEVICE_DADD) Device Address Enable Mask */
+#define USB_DEVICE_DADD_ADDEN(value)          (USB_DEVICE_DADD_ADDEN_Msk & (_UINT8_(value) << USB_DEVICE_DADD_ADDEN_Pos)) /* Assignment of value for ADDEN in the USB_DEVICE_DADD register */
+#define USB_DEVICE_DADD_Msk                   _UINT8_(0xFF)                                        /* (USB_DEVICE_DADD) Register Mask  */
+
+
+/* -------- USB_HOST_HSOFC : (USB Offset: 0x0A) (R/W 8) HOST Host Start Of Frame Control -------- */
+#define USB_HOST_HSOFC_RESETVALUE             _UINT8_(0x00)                                        /*  (USB_HOST_HSOFC) HOST Host Start Of Frame Control  Reset Value */
+
+#define USB_HOST_HSOFC_FLENC_Pos              _UINT8_(0)                                           /* (USB_HOST_HSOFC) Frame Length Control Position */
+#define USB_HOST_HSOFC_FLENC_Msk              (_UINT8_(0xF) << USB_HOST_HSOFC_FLENC_Pos)           /* (USB_HOST_HSOFC) Frame Length Control Mask */
+#define USB_HOST_HSOFC_FLENC(value)           (USB_HOST_HSOFC_FLENC_Msk & (_UINT8_(value) << USB_HOST_HSOFC_FLENC_Pos)) /* Assignment of value for FLENC in the USB_HOST_HSOFC register */
+#define USB_HOST_HSOFC_FLENCE_Pos             _UINT8_(7)                                           /* (USB_HOST_HSOFC) Frame Length Control Enable Position */
+#define USB_HOST_HSOFC_FLENCE_Msk             (_UINT8_(0x1) << USB_HOST_HSOFC_FLENCE_Pos)          /* (USB_HOST_HSOFC) Frame Length Control Enable Mask */
+#define USB_HOST_HSOFC_FLENCE(value)          (USB_HOST_HSOFC_FLENCE_Msk & (_UINT8_(value) << USB_HOST_HSOFC_FLENCE_Pos)) /* Assignment of value for FLENCE in the USB_HOST_HSOFC register */
+#define USB_HOST_HSOFC_Msk                    _UINT8_(0x8F)                                        /* (USB_HOST_HSOFC) Register Mask  */
+
+
+/* -------- USB_DEVICE_STATUS : (USB Offset: 0x0C) ( R/ 8) DEVICE Status -------- */
+#define USB_DEVICE_STATUS_RESETVALUE          _UINT8_(0x40)                                        /*  (USB_DEVICE_STATUS) DEVICE Status  Reset Value */
+
+#define USB_DEVICE_STATUS_SPEED_Pos           _UINT8_(2)                                           /* (USB_DEVICE_STATUS) Speed Status Position */
+#define USB_DEVICE_STATUS_SPEED_Msk           (_UINT8_(0x3) << USB_DEVICE_STATUS_SPEED_Pos)        /* (USB_DEVICE_STATUS) Speed Status Mask */
+#define USB_DEVICE_STATUS_SPEED(value)        (USB_DEVICE_STATUS_SPEED_Msk & (_UINT8_(value) << USB_DEVICE_STATUS_SPEED_Pos)) /* Assignment of value for SPEED in the USB_DEVICE_STATUS register */
+#define   USB_DEVICE_STATUS_SPEED_FS_Val      _UINT8_(0x0)                                         /* (USB_DEVICE_STATUS) Full-speed mode  */
+#define   USB_DEVICE_STATUS_SPEED_LS_Val      _UINT8_(0x1)                                         /* (USB_DEVICE_STATUS) Low-speed mode  */
+#define   USB_DEVICE_STATUS_SPEED_HS_Val      _UINT8_(0x2)                                         /* (USB_DEVICE_STATUS) High-speed mode  */
+#define USB_DEVICE_STATUS_SPEED_FS            (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos) /* (USB_DEVICE_STATUS) Full-speed mode Position */
+#define USB_DEVICE_STATUS_SPEED_LS            (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos) /* (USB_DEVICE_STATUS) Low-speed mode Position */
+#define USB_DEVICE_STATUS_SPEED_HS            (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos) /* (USB_DEVICE_STATUS) High-speed mode Position */
+#define USB_DEVICE_STATUS_LINESTATE_Pos       _UINT8_(6)                                           /* (USB_DEVICE_STATUS) USB Line State Status Position */
+#define USB_DEVICE_STATUS_LINESTATE_Msk       (_UINT8_(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos)    /* (USB_DEVICE_STATUS) USB Line State Status Mask */
+#define USB_DEVICE_STATUS_LINESTATE(value)    (USB_DEVICE_STATUS_LINESTATE_Msk & (_UINT8_(value) << USB_DEVICE_STATUS_LINESTATE_Pos)) /* Assignment of value for LINESTATE in the USB_DEVICE_STATUS register */
+#define   USB_DEVICE_STATUS_LINESTATE_0_Val   _UINT8_(0x0)                                         /* (USB_DEVICE_STATUS) SE0/RESET  */
+#define   USB_DEVICE_STATUS_LINESTATE_1_Val   _UINT8_(0x1)                                         /* (USB_DEVICE_STATUS) FS-J or LS-K State  */
+#define   USB_DEVICE_STATUS_LINESTATE_2_Val   _UINT8_(0x2)                                         /* (USB_DEVICE_STATUS) FS-K or LS-J State  */
+#define USB_DEVICE_STATUS_LINESTATE_0         (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos) /* (USB_DEVICE_STATUS) SE0/RESET Position */
+#define USB_DEVICE_STATUS_LINESTATE_1         (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos) /* (USB_DEVICE_STATUS) FS-J or LS-K State Position */
+#define USB_DEVICE_STATUS_LINESTATE_2         (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos) /* (USB_DEVICE_STATUS) FS-K or LS-J State Position */
+#define USB_DEVICE_STATUS_Msk                 _UINT8_(0xCC)                                        /* (USB_DEVICE_STATUS) Register Mask  */
+
+
+/* -------- USB_HOST_STATUS : (USB Offset: 0x0C) (R/W 8) HOST Status -------- */
+#define USB_HOST_STATUS_RESETVALUE            _UINT8_(0x00)                                        /*  (USB_HOST_STATUS) HOST Status  Reset Value */
+
+#define USB_HOST_STATUS_SPEED_Pos             _UINT8_(2)                                           /* (USB_HOST_STATUS) Speed Status Position */
+#define USB_HOST_STATUS_SPEED_Msk             (_UINT8_(0x3) << USB_HOST_STATUS_SPEED_Pos)          /* (USB_HOST_STATUS) Speed Status Mask */
+#define USB_HOST_STATUS_SPEED(value)          (USB_HOST_STATUS_SPEED_Msk & (_UINT8_(value) << USB_HOST_STATUS_SPEED_Pos)) /* Assignment of value for SPEED in the USB_HOST_STATUS register */
+#define USB_HOST_STATUS_LINESTATE_Pos         _UINT8_(6)                                           /* (USB_HOST_STATUS) USB Line State Status Position */
+#define USB_HOST_STATUS_LINESTATE_Msk         (_UINT8_(0x3) << USB_HOST_STATUS_LINESTATE_Pos)      /* (USB_HOST_STATUS) USB Line State Status Mask */
+#define USB_HOST_STATUS_LINESTATE(value)      (USB_HOST_STATUS_LINESTATE_Msk & (_UINT8_(value) << USB_HOST_STATUS_LINESTATE_Pos)) /* Assignment of value for LINESTATE in the USB_HOST_STATUS register */
+#define USB_HOST_STATUS_Msk                   _UINT8_(0xCC)                                        /* (USB_HOST_STATUS) Register Mask  */
+
+
+/* -------- USB_FSMSTATUS : (USB Offset: 0x0D) ( R/ 8) Finite State Machine Status -------- */
+#define USB_FSMSTATUS_RESETVALUE              _UINT8_(0x01)                                        /*  (USB_FSMSTATUS) Finite State Machine Status  Reset Value */
+
+#define USB_FSMSTATUS_FSMSTATE_Pos            _UINT8_(0)                                           /* (USB_FSMSTATUS) Fine State Machine Status Position */
+#define USB_FSMSTATUS_FSMSTATE_Msk            (_UINT8_(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos)        /* (USB_FSMSTATUS) Fine State Machine Status Mask */
+#define USB_FSMSTATUS_FSMSTATE(value)         (USB_FSMSTATUS_FSMSTATE_Msk & (_UINT8_(value) << USB_FSMSTATUS_FSMSTATE_Pos)) /* Assignment of value for FSMSTATE in the USB_FSMSTATUS register */
+#define   USB_FSMSTATUS_FSMSTATE_OFF_Val      _UINT8_(0x1)                                         /* (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state  */
+#define   USB_FSMSTATUS_FSMSTATE_ON_Val       _UINT8_(0x2)                                         /* (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states  */
+#define   USB_FSMSTATUS_FSMSTATE_SUSPEND_Val  _UINT8_(0x4)                                         /* (USB_FSMSTATUS) SUSPEND (L2)  */
+#define   USB_FSMSTATUS_FSMSTATE_SLEEP_Val    _UINT8_(0x8)                                         /* (USB_FSMSTATUS) SLEEP (L1)  */
+#define   USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _UINT8_(0x10)                                        /* (USB_FSMSTATUS) DNRESUME. Down Stream Resume.  */
+#define   USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _UINT8_(0x20)                                        /* (USB_FSMSTATUS) UPRESUME. Up Stream Resume.  */
+#define   USB_FSMSTATUS_FSMSTATE_RESET_Val    _UINT8_(0x40)                                        /* (USB_FSMSTATUS) RESET. USB lines Reset.  */
+#define USB_FSMSTATUS_FSMSTATE_OFF            (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state Position */
+#define USB_FSMSTATUS_FSMSTATE_ON             (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states Position */
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND        (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) SUSPEND (L2) Position */
+#define USB_FSMSTATUS_FSMSTATE_SLEEP          (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) SLEEP (L1) Position */
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME       (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) DNRESUME. Down Stream Resume. Position */
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME       (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) UPRESUME. Up Stream Resume. Position */
+#define USB_FSMSTATUS_FSMSTATE_RESET          (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos) /* (USB_FSMSTATUS) RESET. USB lines Reset. Position */
+#define USB_FSMSTATUS_Msk                     _UINT8_(0x7F)                                        /* (USB_FSMSTATUS) Register Mask  */
+
+
+/* -------- USB_DEVICE_FNUM : (USB Offset: 0x10) ( R/ 16) DEVICE Device Frame Number -------- */
+#define USB_DEVICE_FNUM_RESETVALUE            _UINT16_(0x00)                                       /*  (USB_DEVICE_FNUM) DEVICE Device Frame Number  Reset Value */
+
+#define USB_DEVICE_FNUM_MFNUM_Pos             _UINT16_(0)                                          /* (USB_DEVICE_FNUM) Micro Frame Number Position */
+#define USB_DEVICE_FNUM_MFNUM_Msk             (_UINT16_(0x7) << USB_DEVICE_FNUM_MFNUM_Pos)         /* (USB_DEVICE_FNUM) Micro Frame Number Mask */
+#define USB_DEVICE_FNUM_MFNUM(value)          (USB_DEVICE_FNUM_MFNUM_Msk & (_UINT16_(value) << USB_DEVICE_FNUM_MFNUM_Pos)) /* Assignment of value for MFNUM in the USB_DEVICE_FNUM register */
+#define USB_DEVICE_FNUM_FNUM_Pos              _UINT16_(3)                                          /* (USB_DEVICE_FNUM) Frame Number Position */
+#define USB_DEVICE_FNUM_FNUM_Msk              (_UINT16_(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos)        /* (USB_DEVICE_FNUM) Frame Number Mask */
+#define USB_DEVICE_FNUM_FNUM(value)           (USB_DEVICE_FNUM_FNUM_Msk & (_UINT16_(value) << USB_DEVICE_FNUM_FNUM_Pos)) /* Assignment of value for FNUM in the USB_DEVICE_FNUM register */
+#define USB_DEVICE_FNUM_FNCERR_Pos            _UINT16_(15)                                         /* (USB_DEVICE_FNUM) Frame Number CRC Error Position */
+#define USB_DEVICE_FNUM_FNCERR_Msk            (_UINT16_(0x1) << USB_DEVICE_FNUM_FNCERR_Pos)        /* (USB_DEVICE_FNUM) Frame Number CRC Error Mask */
+#define USB_DEVICE_FNUM_FNCERR(value)         (USB_DEVICE_FNUM_FNCERR_Msk & (_UINT16_(value) << USB_DEVICE_FNUM_FNCERR_Pos)) /* Assignment of value for FNCERR in the USB_DEVICE_FNUM register */
+#define USB_DEVICE_FNUM_Msk                   _UINT16_(0xBFFF)                                     /* (USB_DEVICE_FNUM) Register Mask  */
+
+
+/* -------- USB_HOST_FNUM : (USB Offset: 0x10) (R/W 16) HOST Host Frame Number -------- */
+#define USB_HOST_FNUM_RESETVALUE              _UINT16_(0x00)                                       /*  (USB_HOST_FNUM) HOST Host Frame Number  Reset Value */
+
+#define USB_HOST_FNUM_MFNUM_Pos               _UINT16_(0)                                          /* (USB_HOST_FNUM) Micro Frame Number Position */
+#define USB_HOST_FNUM_MFNUM_Msk               (_UINT16_(0x7) << USB_HOST_FNUM_MFNUM_Pos)           /* (USB_HOST_FNUM) Micro Frame Number Mask */
+#define USB_HOST_FNUM_MFNUM(value)            (USB_HOST_FNUM_MFNUM_Msk & (_UINT16_(value) << USB_HOST_FNUM_MFNUM_Pos)) /* Assignment of value for MFNUM in the USB_HOST_FNUM register */
+#define USB_HOST_FNUM_FNUM_Pos                _UINT16_(3)                                          /* (USB_HOST_FNUM) Frame Number Position */
+#define USB_HOST_FNUM_FNUM_Msk                (_UINT16_(0x7FF) << USB_HOST_FNUM_FNUM_Pos)          /* (USB_HOST_FNUM) Frame Number Mask */
+#define USB_HOST_FNUM_FNUM(value)             (USB_HOST_FNUM_FNUM_Msk & (_UINT16_(value) << USB_HOST_FNUM_FNUM_Pos)) /* Assignment of value for FNUM in the USB_HOST_FNUM register */
+#define USB_HOST_FNUM_Msk                     _UINT16_(0x3FFF)                                     /* (USB_HOST_FNUM) Register Mask  */
+
+
+/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x12) ( R/ 8) HOST Host Frame Length -------- */
+#define USB_HOST_FLENHIGH_RESETVALUE          _UINT8_(0x00)                                        /*  (USB_HOST_FLENHIGH) HOST Host Frame Length  Reset Value */
+
+#define USB_HOST_FLENHIGH_FLENHIGH_Pos        _UINT8_(0)                                           /* (USB_HOST_FLENHIGH) Frame Length Position */
+#define USB_HOST_FLENHIGH_FLENHIGH_Msk        (_UINT8_(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos)    /* (USB_HOST_FLENHIGH) Frame Length Mask */
+#define USB_HOST_FLENHIGH_FLENHIGH(value)     (USB_HOST_FLENHIGH_FLENHIGH_Msk & (_UINT8_(value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)) /* Assignment of value for FLENHIGH in the USB_HOST_FLENHIGH register */
+#define USB_HOST_FLENHIGH_Msk                 _UINT8_(0xFF)                                        /* (USB_HOST_FLENHIGH) Register Mask  */
+
+
+/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x14) (R/W 16) DEVICE Device Interrupt Enable Clear -------- */
+#define USB_DEVICE_INTENCLR_RESETVALUE        _UINT16_(0x00)                                       /*  (USB_DEVICE_INTENCLR) DEVICE Device Interrupt Enable Clear  Reset Value */
+
+#define USB_DEVICE_INTENCLR_SUSPEND_Pos       _UINT16_(0)                                          /* (USB_DEVICE_INTENCLR) Suspend Interrupt Enable Position */
+#define USB_DEVICE_INTENCLR_SUSPEND_Msk       (_UINT16_(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos)   /* (USB_DEVICE_INTENCLR) Suspend Interrupt Enable Mask */
+#define USB_DEVICE_INTENCLR_SUSPEND(value)    (USB_DEVICE_INTENCLR_SUSPEND_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_SUSPEND_Pos)) /* Assignment of value for SUSPEND in the USB_DEVICE_INTENCLR register */
+#define USB_DEVICE_INTENCLR_MSOF_Pos          _UINT16_(1)                                          /* (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode Position */
+#define USB_DEVICE_INTENCLR_MSOF_Msk          (_UINT16_(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos)      /* (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode Mask */
+#define USB_DEVICE_INTENCLR_MSOF(value)       (USB_DEVICE_INTENCLR_MSOF_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_MSOF_Pos)) /* Assignment of value for MSOF in the USB_DEVICE_INTENCLR register */
+#define USB_DEVICE_INTENCLR_SOF_Pos           _UINT16_(2)                                          /* (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable Position */
+#define USB_DEVICE_INTENCLR_SOF_Msk           (_UINT16_(0x1) << USB_DEVICE_INTENCLR_SOF_Pos)       /* (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable Mask */
+#define USB_DEVICE_INTENCLR_SOF(value)        (USB_DEVICE_INTENCLR_SOF_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_SOF_Pos)) /* Assignment of value for SOF in the USB_DEVICE_INTENCLR register */
+#define USB_DEVICE_INTENCLR_EORST_Pos         _UINT16_(3)                                          /* (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable Position */
+#define USB_DEVICE_INTENCLR_EORST_Msk         (_UINT16_(0x1) << USB_DEVICE_INTENCLR_EORST_Pos)     /* (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable Mask */
+#define USB_DEVICE_INTENCLR_EORST(value)      (USB_DEVICE_INTENCLR_EORST_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_EORST_Pos)) /* Assignment of value for EORST in the USB_DEVICE_INTENCLR register */
+#define USB_DEVICE_INTENCLR_WAKEUP_Pos        _UINT16_(4)                                          /* (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable Position */
+#define USB_DEVICE_INTENCLR_WAKEUP_Msk        (_UINT16_(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos)    /* (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable Mask */
+#define USB_DEVICE_INTENCLR_WAKEUP(value)     (USB_DEVICE_INTENCLR_WAKEUP_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_WAKEUP_Pos)) /* Assignment of value for WAKEUP in the USB_DEVICE_INTENCLR register */
+#define USB_DEVICE_INTENCLR_EORSM_Pos         _UINT16_(5)                                          /* (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable Position */
+#define USB_DEVICE_INTENCLR_EORSM_Msk         (_UINT16_(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos)     /* (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable Mask */
+#define USB_DEVICE_INTENCLR_EORSM(value)      (USB_DEVICE_INTENCLR_EORSM_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_EORSM_Pos)) /* Assignment of value for EORSM in the USB_DEVICE_INTENCLR register */
+#define USB_DEVICE_INTENCLR_UPRSM_Pos         _UINT16_(6)                                          /* (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable Position */
+#define USB_DEVICE_INTENCLR_UPRSM_Msk         (_UINT16_(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos)     /* (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable Mask */
+#define USB_DEVICE_INTENCLR_UPRSM(value)      (USB_DEVICE_INTENCLR_UPRSM_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_UPRSM_Pos)) /* Assignment of value for UPRSM in the USB_DEVICE_INTENCLR register */
+#define USB_DEVICE_INTENCLR_RAMACER_Pos       _UINT16_(7)                                          /* (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable Position */
+#define USB_DEVICE_INTENCLR_RAMACER_Msk       (_UINT16_(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos)   /* (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable Mask */
+#define USB_DEVICE_INTENCLR_RAMACER(value)    (USB_DEVICE_INTENCLR_RAMACER_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_RAMACER_Pos)) /* Assignment of value for RAMACER in the USB_DEVICE_INTENCLR register */
+#define USB_DEVICE_INTENCLR_LPMNYET_Pos       _UINT16_(8)                                          /* (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable Position */
+#define USB_DEVICE_INTENCLR_LPMNYET_Msk       (_UINT16_(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos)   /* (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable Mask */
+#define USB_DEVICE_INTENCLR_LPMNYET(value)    (USB_DEVICE_INTENCLR_LPMNYET_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_LPMNYET_Pos)) /* Assignment of value for LPMNYET in the USB_DEVICE_INTENCLR register */
+#define USB_DEVICE_INTENCLR_LPMSUSP_Pos       _UINT16_(9)                                          /* (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable Position */
+#define USB_DEVICE_INTENCLR_LPMSUSP_Msk       (_UINT16_(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)   /* (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable Mask */
+#define USB_DEVICE_INTENCLR_LPMSUSP(value)    (USB_DEVICE_INTENCLR_LPMSUSP_Msk & (_UINT16_(value) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)) /* Assignment of value for LPMSUSP in the USB_DEVICE_INTENCLR register */
+#define USB_DEVICE_INTENCLR_Msk               _UINT16_(0x03FF)                                     /* (USB_DEVICE_INTENCLR) Register Mask  */
+
+
+/* -------- USB_HOST_INTENCLR : (USB Offset: 0x14) (R/W 16) HOST Host Interrupt Enable Clear -------- */
+#define USB_HOST_INTENCLR_RESETVALUE          _UINT16_(0x00)                                       /*  (USB_HOST_INTENCLR) HOST Host Interrupt Enable Clear  Reset Value */
+
+#define USB_HOST_INTENCLR_HSOF_Pos            _UINT16_(2)                                          /* (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable Position */
+#define USB_HOST_INTENCLR_HSOF_Msk            (_UINT16_(0x1) << USB_HOST_INTENCLR_HSOF_Pos)        /* (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable Mask */
+#define USB_HOST_INTENCLR_HSOF(value)         (USB_HOST_INTENCLR_HSOF_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_HSOF_Pos)) /* Assignment of value for HSOF in the USB_HOST_INTENCLR register */
+#define USB_HOST_INTENCLR_RST_Pos             _UINT16_(3)                                          /* (USB_HOST_INTENCLR) BUS Reset Interrupt Disable Position */
+#define USB_HOST_INTENCLR_RST_Msk             (_UINT16_(0x1) << USB_HOST_INTENCLR_RST_Pos)         /* (USB_HOST_INTENCLR) BUS Reset Interrupt Disable Mask */
+#define USB_HOST_INTENCLR_RST(value)          (USB_HOST_INTENCLR_RST_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_RST_Pos)) /* Assignment of value for RST in the USB_HOST_INTENCLR register */
+#define USB_HOST_INTENCLR_WAKEUP_Pos          _UINT16_(4)                                          /* (USB_HOST_INTENCLR) Wake Up Interrupt Disable Position */
+#define USB_HOST_INTENCLR_WAKEUP_Msk          (_UINT16_(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos)      /* (USB_HOST_INTENCLR) Wake Up Interrupt Disable Mask */
+#define USB_HOST_INTENCLR_WAKEUP(value)       (USB_HOST_INTENCLR_WAKEUP_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_WAKEUP_Pos)) /* Assignment of value for WAKEUP in the USB_HOST_INTENCLR register */
+#define USB_HOST_INTENCLR_DNRSM_Pos           _UINT16_(5)                                          /* (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable Position */
+#define USB_HOST_INTENCLR_DNRSM_Msk           (_UINT16_(0x1) << USB_HOST_INTENCLR_DNRSM_Pos)       /* (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable Mask */
+#define USB_HOST_INTENCLR_DNRSM(value)        (USB_HOST_INTENCLR_DNRSM_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_DNRSM_Pos)) /* Assignment of value for DNRSM in the USB_HOST_INTENCLR register */
+#define USB_HOST_INTENCLR_UPRSM_Pos           _UINT16_(6)                                          /* (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable Position */
+#define USB_HOST_INTENCLR_UPRSM_Msk           (_UINT16_(0x1) << USB_HOST_INTENCLR_UPRSM_Pos)       /* (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable Mask */
+#define USB_HOST_INTENCLR_UPRSM(value)        (USB_HOST_INTENCLR_UPRSM_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_UPRSM_Pos)) /* Assignment of value for UPRSM in the USB_HOST_INTENCLR register */
+#define USB_HOST_INTENCLR_RAMACER_Pos         _UINT16_(7)                                          /* (USB_HOST_INTENCLR) Ram Access Interrupt Disable Position */
+#define USB_HOST_INTENCLR_RAMACER_Msk         (_UINT16_(0x1) << USB_HOST_INTENCLR_RAMACER_Pos)     /* (USB_HOST_INTENCLR) Ram Access Interrupt Disable Mask */
+#define USB_HOST_INTENCLR_RAMACER(value)      (USB_HOST_INTENCLR_RAMACER_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_RAMACER_Pos)) /* Assignment of value for RAMACER in the USB_HOST_INTENCLR register */
+#define USB_HOST_INTENCLR_DCONN_Pos           _UINT16_(8)                                          /* (USB_HOST_INTENCLR) Device Connection Interrupt Disable Position */
+#define USB_HOST_INTENCLR_DCONN_Msk           (_UINT16_(0x1) << USB_HOST_INTENCLR_DCONN_Pos)       /* (USB_HOST_INTENCLR) Device Connection Interrupt Disable Mask */
+#define USB_HOST_INTENCLR_DCONN(value)        (USB_HOST_INTENCLR_DCONN_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_DCONN_Pos)) /* Assignment of value for DCONN in the USB_HOST_INTENCLR register */
+#define USB_HOST_INTENCLR_DDISC_Pos           _UINT16_(9)                                          /* (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable Position */
+#define USB_HOST_INTENCLR_DDISC_Msk           (_UINT16_(0x1) << USB_HOST_INTENCLR_DDISC_Pos)       /* (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable Mask */
+#define USB_HOST_INTENCLR_DDISC(value)        (USB_HOST_INTENCLR_DDISC_Msk & (_UINT16_(value) << USB_HOST_INTENCLR_DDISC_Pos)) /* Assignment of value for DDISC in the USB_HOST_INTENCLR register */
+#define USB_HOST_INTENCLR_Msk                 _UINT16_(0x03FC)                                     /* (USB_HOST_INTENCLR) Register Mask  */
+
+
+/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x18) (R/W 16) DEVICE Device Interrupt Enable Set -------- */
+#define USB_DEVICE_INTENSET_RESETVALUE        _UINT16_(0x00)                                       /*  (USB_DEVICE_INTENSET) DEVICE Device Interrupt Enable Set  Reset Value */
+
+#define USB_DEVICE_INTENSET_SUSPEND_Pos       _UINT16_(0)                                          /* (USB_DEVICE_INTENSET) Suspend Interrupt Enable Position */
+#define USB_DEVICE_INTENSET_SUSPEND_Msk       (_UINT16_(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos)   /* (USB_DEVICE_INTENSET) Suspend Interrupt Enable Mask */
+#define USB_DEVICE_INTENSET_SUSPEND(value)    (USB_DEVICE_INTENSET_SUSPEND_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_SUSPEND_Pos)) /* Assignment of value for SUSPEND in the USB_DEVICE_INTENSET register */
+#define USB_DEVICE_INTENSET_MSOF_Pos          _UINT16_(1)                                          /* (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode Position */
+#define USB_DEVICE_INTENSET_MSOF_Msk          (_UINT16_(0x1) << USB_DEVICE_INTENSET_MSOF_Pos)      /* (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode Mask */
+#define USB_DEVICE_INTENSET_MSOF(value)       (USB_DEVICE_INTENSET_MSOF_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_MSOF_Pos)) /* Assignment of value for MSOF in the USB_DEVICE_INTENSET register */
+#define USB_DEVICE_INTENSET_SOF_Pos           _UINT16_(2)                                          /* (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable Position */
+#define USB_DEVICE_INTENSET_SOF_Msk           (_UINT16_(0x1) << USB_DEVICE_INTENSET_SOF_Pos)       /* (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable Mask */
+#define USB_DEVICE_INTENSET_SOF(value)        (USB_DEVICE_INTENSET_SOF_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_SOF_Pos)) /* Assignment of value for SOF in the USB_DEVICE_INTENSET register */
+#define USB_DEVICE_INTENSET_EORST_Pos         _UINT16_(3)                                          /* (USB_DEVICE_INTENSET) End of Reset Interrupt Enable Position */
+#define USB_DEVICE_INTENSET_EORST_Msk         (_UINT16_(0x1) << USB_DEVICE_INTENSET_EORST_Pos)     /* (USB_DEVICE_INTENSET) End of Reset Interrupt Enable Mask */
+#define USB_DEVICE_INTENSET_EORST(value)      (USB_DEVICE_INTENSET_EORST_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_EORST_Pos)) /* Assignment of value for EORST in the USB_DEVICE_INTENSET register */
+#define USB_DEVICE_INTENSET_WAKEUP_Pos        _UINT16_(4)                                          /* (USB_DEVICE_INTENSET) Wake Up Interrupt Enable Position */
+#define USB_DEVICE_INTENSET_WAKEUP_Msk        (_UINT16_(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos)    /* (USB_DEVICE_INTENSET) Wake Up Interrupt Enable Mask */
+#define USB_DEVICE_INTENSET_WAKEUP(value)     (USB_DEVICE_INTENSET_WAKEUP_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_WAKEUP_Pos)) /* Assignment of value for WAKEUP in the USB_DEVICE_INTENSET register */
+#define USB_DEVICE_INTENSET_EORSM_Pos         _UINT16_(5)                                          /* (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable Position */
+#define USB_DEVICE_INTENSET_EORSM_Msk         (_UINT16_(0x1) << USB_DEVICE_INTENSET_EORSM_Pos)     /* (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable Mask */
+#define USB_DEVICE_INTENSET_EORSM(value)      (USB_DEVICE_INTENSET_EORSM_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_EORSM_Pos)) /* Assignment of value for EORSM in the USB_DEVICE_INTENSET register */
+#define USB_DEVICE_INTENSET_UPRSM_Pos         _UINT16_(6)                                          /* (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable Position */
+#define USB_DEVICE_INTENSET_UPRSM_Msk         (_UINT16_(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos)     /* (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable Mask */
+#define USB_DEVICE_INTENSET_UPRSM(value)      (USB_DEVICE_INTENSET_UPRSM_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_UPRSM_Pos)) /* Assignment of value for UPRSM in the USB_DEVICE_INTENSET register */
+#define USB_DEVICE_INTENSET_RAMACER_Pos       _UINT16_(7)                                          /* (USB_DEVICE_INTENSET) Ram Access Interrupt Enable Position */
+#define USB_DEVICE_INTENSET_RAMACER_Msk       (_UINT16_(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos)   /* (USB_DEVICE_INTENSET) Ram Access Interrupt Enable Mask */
+#define USB_DEVICE_INTENSET_RAMACER(value)    (USB_DEVICE_INTENSET_RAMACER_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_RAMACER_Pos)) /* Assignment of value for RAMACER in the USB_DEVICE_INTENSET register */
+#define USB_DEVICE_INTENSET_LPMNYET_Pos       _UINT16_(8)                                          /* (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable Position */
+#define USB_DEVICE_INTENSET_LPMNYET_Msk       (_UINT16_(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos)   /* (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable Mask */
+#define USB_DEVICE_INTENSET_LPMNYET(value)    (USB_DEVICE_INTENSET_LPMNYET_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_LPMNYET_Pos)) /* Assignment of value for LPMNYET in the USB_DEVICE_INTENSET register */
+#define USB_DEVICE_INTENSET_LPMSUSP_Pos       _UINT16_(9)                                          /* (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable Position */
+#define USB_DEVICE_INTENSET_LPMSUSP_Msk       (_UINT16_(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos)   /* (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable Mask */
+#define USB_DEVICE_INTENSET_LPMSUSP(value)    (USB_DEVICE_INTENSET_LPMSUSP_Msk & (_UINT16_(value) << USB_DEVICE_INTENSET_LPMSUSP_Pos)) /* Assignment of value for LPMSUSP in the USB_DEVICE_INTENSET register */
+#define USB_DEVICE_INTENSET_Msk               _UINT16_(0x03FF)                                     /* (USB_DEVICE_INTENSET) Register Mask  */
+
+
+/* -------- USB_HOST_INTENSET : (USB Offset: 0x18) (R/W 16) HOST Host Interrupt Enable Set -------- */
+#define USB_HOST_INTENSET_RESETVALUE          _UINT16_(0x00)                                       /*  (USB_HOST_INTENSET) HOST Host Interrupt Enable Set  Reset Value */
+
+#define USB_HOST_INTENSET_HSOF_Pos            _UINT16_(2)                                          /* (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable Position */
+#define USB_HOST_INTENSET_HSOF_Msk            (_UINT16_(0x1) << USB_HOST_INTENSET_HSOF_Pos)        /* (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable Mask */
+#define USB_HOST_INTENSET_HSOF(value)         (USB_HOST_INTENSET_HSOF_Msk & (_UINT16_(value) << USB_HOST_INTENSET_HSOF_Pos)) /* Assignment of value for HSOF in the USB_HOST_INTENSET register */
+#define USB_HOST_INTENSET_RST_Pos             _UINT16_(3)                                          /* (USB_HOST_INTENSET) Bus Reset Interrupt Enable Position */
+#define USB_HOST_INTENSET_RST_Msk             (_UINT16_(0x1) << USB_HOST_INTENSET_RST_Pos)         /* (USB_HOST_INTENSET) Bus Reset Interrupt Enable Mask */
+#define USB_HOST_INTENSET_RST(value)          (USB_HOST_INTENSET_RST_Msk & (_UINT16_(value) << USB_HOST_INTENSET_RST_Pos)) /* Assignment of value for RST in the USB_HOST_INTENSET register */
+#define USB_HOST_INTENSET_WAKEUP_Pos          _UINT16_(4)                                          /* (USB_HOST_INTENSET) Wake Up Interrupt Enable Position */
+#define USB_HOST_INTENSET_WAKEUP_Msk          (_UINT16_(0x1) << USB_HOST_INTENSET_WAKEUP_Pos)      /* (USB_HOST_INTENSET) Wake Up Interrupt Enable Mask */
+#define USB_HOST_INTENSET_WAKEUP(value)       (USB_HOST_INTENSET_WAKEUP_Msk & (_UINT16_(value) << USB_HOST_INTENSET_WAKEUP_Pos)) /* Assignment of value for WAKEUP in the USB_HOST_INTENSET register */
+#define USB_HOST_INTENSET_DNRSM_Pos           _UINT16_(5)                                          /* (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable Position */
+#define USB_HOST_INTENSET_DNRSM_Msk           (_UINT16_(0x1) << USB_HOST_INTENSET_DNRSM_Pos)       /* (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable Mask */
+#define USB_HOST_INTENSET_DNRSM(value)        (USB_HOST_INTENSET_DNRSM_Msk & (_UINT16_(value) << USB_HOST_INTENSET_DNRSM_Pos)) /* Assignment of value for DNRSM in the USB_HOST_INTENSET register */
+#define USB_HOST_INTENSET_UPRSM_Pos           _UINT16_(6)                                          /* (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable Position */
+#define USB_HOST_INTENSET_UPRSM_Msk           (_UINT16_(0x1) << USB_HOST_INTENSET_UPRSM_Pos)       /* (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable Mask */
+#define USB_HOST_INTENSET_UPRSM(value)        (USB_HOST_INTENSET_UPRSM_Msk & (_UINT16_(value) << USB_HOST_INTENSET_UPRSM_Pos)) /* Assignment of value for UPRSM in the USB_HOST_INTENSET register */
+#define USB_HOST_INTENSET_RAMACER_Pos         _UINT16_(7)                                          /* (USB_HOST_INTENSET) Ram Access Interrupt Enable Position */
+#define USB_HOST_INTENSET_RAMACER_Msk         (_UINT16_(0x1) << USB_HOST_INTENSET_RAMACER_Pos)     /* (USB_HOST_INTENSET) Ram Access Interrupt Enable Mask */
+#define USB_HOST_INTENSET_RAMACER(value)      (USB_HOST_INTENSET_RAMACER_Msk & (_UINT16_(value) << USB_HOST_INTENSET_RAMACER_Pos)) /* Assignment of value for RAMACER in the USB_HOST_INTENSET register */
+#define USB_HOST_INTENSET_DCONN_Pos           _UINT16_(8)                                          /* (USB_HOST_INTENSET) Link Power Management Interrupt Enable Position */
+#define USB_HOST_INTENSET_DCONN_Msk           (_UINT16_(0x1) << USB_HOST_INTENSET_DCONN_Pos)       /* (USB_HOST_INTENSET) Link Power Management Interrupt Enable Mask */
+#define USB_HOST_INTENSET_DCONN(value)        (USB_HOST_INTENSET_DCONN_Msk & (_UINT16_(value) << USB_HOST_INTENSET_DCONN_Pos)) /* Assignment of value for DCONN in the USB_HOST_INTENSET register */
+#define USB_HOST_INTENSET_DDISC_Pos           _UINT16_(9)                                          /* (USB_HOST_INTENSET) Device Disconnection Interrupt Enable Position */
+#define USB_HOST_INTENSET_DDISC_Msk           (_UINT16_(0x1) << USB_HOST_INTENSET_DDISC_Pos)       /* (USB_HOST_INTENSET) Device Disconnection Interrupt Enable Mask */
+#define USB_HOST_INTENSET_DDISC(value)        (USB_HOST_INTENSET_DDISC_Msk & (_UINT16_(value) << USB_HOST_INTENSET_DDISC_Pos)) /* Assignment of value for DDISC in the USB_HOST_INTENSET register */
+#define USB_HOST_INTENSET_Msk                 _UINT16_(0x03FC)                                     /* (USB_HOST_INTENSET) Register Mask  */
+
+
+/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x1C) (R/W 16) DEVICE Device Interrupt Flag -------- */
+#define USB_DEVICE_INTFLAG_RESETVALUE         _UINT16_(0x00)                                       /*  (USB_DEVICE_INTFLAG) DEVICE Device Interrupt Flag  Reset Value */
+
+#define USB_DEVICE_INTFLAG_SUSPEND_Pos        _UINT16_(0)                                          /* (USB_DEVICE_INTFLAG) Suspend Position */
+#define USB_DEVICE_INTFLAG_SUSPEND_Msk        (_UINT16_(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos)    /* (USB_DEVICE_INTFLAG) Suspend Mask */
+#define USB_DEVICE_INTFLAG_SUSPEND(value)     (USB_DEVICE_INTFLAG_SUSPEND_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_SUSPEND_Pos)) /* Assignment of value for SUSPEND in the USB_DEVICE_INTFLAG register */
+#define USB_DEVICE_INTFLAG_MSOF_Pos           _UINT16_(1)                                          /* (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode Position */
+#define USB_DEVICE_INTFLAG_MSOF_Msk           (_UINT16_(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos)       /* (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode Mask */
+#define USB_DEVICE_INTFLAG_MSOF(value)        (USB_DEVICE_INTFLAG_MSOF_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_MSOF_Pos)) /* Assignment of value for MSOF in the USB_DEVICE_INTFLAG register */
+#define USB_DEVICE_INTFLAG_SOF_Pos            _UINT16_(2)                                          /* (USB_DEVICE_INTFLAG) Start Of Frame Position */
+#define USB_DEVICE_INTFLAG_SOF_Msk            (_UINT16_(0x1) << USB_DEVICE_INTFLAG_SOF_Pos)        /* (USB_DEVICE_INTFLAG) Start Of Frame Mask */
+#define USB_DEVICE_INTFLAG_SOF(value)         (USB_DEVICE_INTFLAG_SOF_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_SOF_Pos)) /* Assignment of value for SOF in the USB_DEVICE_INTFLAG register */
+#define USB_DEVICE_INTFLAG_EORST_Pos          _UINT16_(3)                                          /* (USB_DEVICE_INTFLAG) End of Reset Position */
+#define USB_DEVICE_INTFLAG_EORST_Msk          (_UINT16_(0x1) << USB_DEVICE_INTFLAG_EORST_Pos)      /* (USB_DEVICE_INTFLAG) End of Reset Mask */
+#define USB_DEVICE_INTFLAG_EORST(value)       (USB_DEVICE_INTFLAG_EORST_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_EORST_Pos)) /* Assignment of value for EORST in the USB_DEVICE_INTFLAG register */
+#define USB_DEVICE_INTFLAG_WAKEUP_Pos         _UINT16_(4)                                          /* (USB_DEVICE_INTFLAG) Wake Up Position */
+#define USB_DEVICE_INTFLAG_WAKEUP_Msk         (_UINT16_(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos)     /* (USB_DEVICE_INTFLAG) Wake Up Mask */
+#define USB_DEVICE_INTFLAG_WAKEUP(value)      (USB_DEVICE_INTFLAG_WAKEUP_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_WAKEUP_Pos)) /* Assignment of value for WAKEUP in the USB_DEVICE_INTFLAG register */
+#define USB_DEVICE_INTFLAG_EORSM_Pos          _UINT16_(5)                                          /* (USB_DEVICE_INTFLAG) End Of Resume Position */
+#define USB_DEVICE_INTFLAG_EORSM_Msk          (_UINT16_(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos)      /* (USB_DEVICE_INTFLAG) End Of Resume Mask */
+#define USB_DEVICE_INTFLAG_EORSM(value)       (USB_DEVICE_INTFLAG_EORSM_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_EORSM_Pos)) /* Assignment of value for EORSM in the USB_DEVICE_INTFLAG register */
+#define USB_DEVICE_INTFLAG_UPRSM_Pos          _UINT16_(6)                                          /* (USB_DEVICE_INTFLAG) Upstream Resume Position */
+#define USB_DEVICE_INTFLAG_UPRSM_Msk          (_UINT16_(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos)      /* (USB_DEVICE_INTFLAG) Upstream Resume Mask */
+#define USB_DEVICE_INTFLAG_UPRSM(value)       (USB_DEVICE_INTFLAG_UPRSM_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_UPRSM_Pos)) /* Assignment of value for UPRSM in the USB_DEVICE_INTFLAG register */
+#define USB_DEVICE_INTFLAG_RAMACER_Pos        _UINT16_(7)                                          /* (USB_DEVICE_INTFLAG) Ram Access Position */
+#define USB_DEVICE_INTFLAG_RAMACER_Msk        (_UINT16_(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos)    /* (USB_DEVICE_INTFLAG) Ram Access Mask */
+#define USB_DEVICE_INTFLAG_RAMACER(value)     (USB_DEVICE_INTFLAG_RAMACER_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_RAMACER_Pos)) /* Assignment of value for RAMACER in the USB_DEVICE_INTFLAG register */
+#define USB_DEVICE_INTFLAG_LPMNYET_Pos        _UINT16_(8)                                          /* (USB_DEVICE_INTFLAG) Link Power Management Not Yet Position */
+#define USB_DEVICE_INTFLAG_LPMNYET_Msk        (_UINT16_(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos)    /* (USB_DEVICE_INTFLAG) Link Power Management Not Yet Mask */
+#define USB_DEVICE_INTFLAG_LPMNYET(value)     (USB_DEVICE_INTFLAG_LPMNYET_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_LPMNYET_Pos)) /* Assignment of value for LPMNYET in the USB_DEVICE_INTFLAG register */
+#define USB_DEVICE_INTFLAG_LPMSUSP_Pos        _UINT16_(9)                                          /* (USB_DEVICE_INTFLAG) Link Power Management Suspend Position */
+#define USB_DEVICE_INTFLAG_LPMSUSP_Msk        (_UINT16_(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)    /* (USB_DEVICE_INTFLAG) Link Power Management Suspend Mask */
+#define USB_DEVICE_INTFLAG_LPMSUSP(value)     (USB_DEVICE_INTFLAG_LPMSUSP_Msk & (_UINT16_(value) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)) /* Assignment of value for LPMSUSP in the USB_DEVICE_INTFLAG register */
+#define USB_DEVICE_INTFLAG_Msk                _UINT16_(0x03FF)                                     /* (USB_DEVICE_INTFLAG) Register Mask  */
+
+
+/* -------- USB_HOST_INTFLAG : (USB Offset: 0x1C) (R/W 16) HOST Host Interrupt Flag -------- */
+#define USB_HOST_INTFLAG_RESETVALUE           _UINT16_(0x00)                                       /*  (USB_HOST_INTFLAG) HOST Host Interrupt Flag  Reset Value */
+
+#define USB_HOST_INTFLAG_HSOF_Pos             _UINT16_(2)                                          /* (USB_HOST_INTFLAG) Host Start Of Frame Position */
+#define USB_HOST_INTFLAG_HSOF_Msk             (_UINT16_(0x1) << USB_HOST_INTFLAG_HSOF_Pos)         /* (USB_HOST_INTFLAG) Host Start Of Frame Mask */
+#define USB_HOST_INTFLAG_HSOF(value)          (USB_HOST_INTFLAG_HSOF_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_HSOF_Pos)) /* Assignment of value for HSOF in the USB_HOST_INTFLAG register */
+#define USB_HOST_INTFLAG_RST_Pos              _UINT16_(3)                                          /* (USB_HOST_INTFLAG) Bus Reset Position */
+#define USB_HOST_INTFLAG_RST_Msk              (_UINT16_(0x1) << USB_HOST_INTFLAG_RST_Pos)          /* (USB_HOST_INTFLAG) Bus Reset Mask */
+#define USB_HOST_INTFLAG_RST(value)           (USB_HOST_INTFLAG_RST_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_RST_Pos)) /* Assignment of value for RST in the USB_HOST_INTFLAG register */
+#define USB_HOST_INTFLAG_WAKEUP_Pos           _UINT16_(4)                                          /* (USB_HOST_INTFLAG) Wake Up Position */
+#define USB_HOST_INTFLAG_WAKEUP_Msk           (_UINT16_(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos)       /* (USB_HOST_INTFLAG) Wake Up Mask */
+#define USB_HOST_INTFLAG_WAKEUP(value)        (USB_HOST_INTFLAG_WAKEUP_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_WAKEUP_Pos)) /* Assignment of value for WAKEUP in the USB_HOST_INTFLAG register */
+#define USB_HOST_INTFLAG_DNRSM_Pos            _UINT16_(5)                                          /* (USB_HOST_INTFLAG) Downstream Position */
+#define USB_HOST_INTFLAG_DNRSM_Msk            (_UINT16_(0x1) << USB_HOST_INTFLAG_DNRSM_Pos)        /* (USB_HOST_INTFLAG) Downstream Mask */
+#define USB_HOST_INTFLAG_DNRSM(value)         (USB_HOST_INTFLAG_DNRSM_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_DNRSM_Pos)) /* Assignment of value for DNRSM in the USB_HOST_INTFLAG register */
+#define USB_HOST_INTFLAG_UPRSM_Pos            _UINT16_(6)                                          /* (USB_HOST_INTFLAG) Upstream Resume from the Device Position */
+#define USB_HOST_INTFLAG_UPRSM_Msk            (_UINT16_(0x1) << USB_HOST_INTFLAG_UPRSM_Pos)        /* (USB_HOST_INTFLAG) Upstream Resume from the Device Mask */
+#define USB_HOST_INTFLAG_UPRSM(value)         (USB_HOST_INTFLAG_UPRSM_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_UPRSM_Pos)) /* Assignment of value for UPRSM in the USB_HOST_INTFLAG register */
+#define USB_HOST_INTFLAG_RAMACER_Pos          _UINT16_(7)                                          /* (USB_HOST_INTFLAG) Ram Access Position */
+#define USB_HOST_INTFLAG_RAMACER_Msk          (_UINT16_(0x1) << USB_HOST_INTFLAG_RAMACER_Pos)      /* (USB_HOST_INTFLAG) Ram Access Mask */
+#define USB_HOST_INTFLAG_RAMACER(value)       (USB_HOST_INTFLAG_RAMACER_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_RAMACER_Pos)) /* Assignment of value for RAMACER in the USB_HOST_INTFLAG register */
+#define USB_HOST_INTFLAG_DCONN_Pos            _UINT16_(8)                                          /* (USB_HOST_INTFLAG) Device Connection Position */
+#define USB_HOST_INTFLAG_DCONN_Msk            (_UINT16_(0x1) << USB_HOST_INTFLAG_DCONN_Pos)        /* (USB_HOST_INTFLAG) Device Connection Mask */
+#define USB_HOST_INTFLAG_DCONN(value)         (USB_HOST_INTFLAG_DCONN_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_DCONN_Pos)) /* Assignment of value for DCONN in the USB_HOST_INTFLAG register */
+#define USB_HOST_INTFLAG_DDISC_Pos            _UINT16_(9)                                          /* (USB_HOST_INTFLAG) Device Disconnection Position */
+#define USB_HOST_INTFLAG_DDISC_Msk            (_UINT16_(0x1) << USB_HOST_INTFLAG_DDISC_Pos)        /* (USB_HOST_INTFLAG) Device Disconnection Mask */
+#define USB_HOST_INTFLAG_DDISC(value)         (USB_HOST_INTFLAG_DDISC_Msk & (_UINT16_(value) << USB_HOST_INTFLAG_DDISC_Pos)) /* Assignment of value for DDISC in the USB_HOST_INTFLAG register */
+#define USB_HOST_INTFLAG_Msk                  _UINT16_(0x03FC)                                     /* (USB_HOST_INTFLAG) Register Mask  */
+
+
+/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x20) ( R/ 16) DEVICE End Point Interrupt Summary -------- */
+#define USB_DEVICE_EPINTSMRY_RESETVALUE       _UINT16_(0x00)                                       /*  (USB_DEVICE_EPINTSMRY) DEVICE End Point Interrupt Summary  Reset Value */
+
+#define USB_DEVICE_EPINTSMRY_EPINT0_Pos       _UINT16_(0)                                          /* (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt Position */
+#define USB_DEVICE_EPINTSMRY_EPINT0_Msk       (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT0_Pos)   /* (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt Mask */
+#define USB_DEVICE_EPINTSMRY_EPINT0(value)    (USB_DEVICE_EPINTSMRY_EPINT0_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT0_Pos)) /* Assignment of value for EPINT0 in the USB_DEVICE_EPINTSMRY register */
+#define USB_DEVICE_EPINTSMRY_EPINT1_Pos       _UINT16_(1)                                          /* (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt Position */
+#define USB_DEVICE_EPINTSMRY_EPINT1_Msk       (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT1_Pos)   /* (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt Mask */
+#define USB_DEVICE_EPINTSMRY_EPINT1(value)    (USB_DEVICE_EPINTSMRY_EPINT1_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT1_Pos)) /* Assignment of value for EPINT1 in the USB_DEVICE_EPINTSMRY register */
+#define USB_DEVICE_EPINTSMRY_EPINT2_Pos       _UINT16_(2)                                          /* (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt Position */
+#define USB_DEVICE_EPINTSMRY_EPINT2_Msk       (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT2_Pos)   /* (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt Mask */
+#define USB_DEVICE_EPINTSMRY_EPINT2(value)    (USB_DEVICE_EPINTSMRY_EPINT2_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT2_Pos)) /* Assignment of value for EPINT2 in the USB_DEVICE_EPINTSMRY register */
+#define USB_DEVICE_EPINTSMRY_EPINT3_Pos       _UINT16_(3)                                          /* (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt Position */
+#define USB_DEVICE_EPINTSMRY_EPINT3_Msk       (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT3_Pos)   /* (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt Mask */
+#define USB_DEVICE_EPINTSMRY_EPINT3(value)    (USB_DEVICE_EPINTSMRY_EPINT3_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT3_Pos)) /* Assignment of value for EPINT3 in the USB_DEVICE_EPINTSMRY register */
+#define USB_DEVICE_EPINTSMRY_EPINT4_Pos       _UINT16_(4)                                          /* (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt Position */
+#define USB_DEVICE_EPINTSMRY_EPINT4_Msk       (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT4_Pos)   /* (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt Mask */
+#define USB_DEVICE_EPINTSMRY_EPINT4(value)    (USB_DEVICE_EPINTSMRY_EPINT4_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT4_Pos)) /* Assignment of value for EPINT4 in the USB_DEVICE_EPINTSMRY register */
+#define USB_DEVICE_EPINTSMRY_EPINT5_Pos       _UINT16_(5)                                          /* (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt Position */
+#define USB_DEVICE_EPINTSMRY_EPINT5_Msk       (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT5_Pos)   /* (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt Mask */
+#define USB_DEVICE_EPINTSMRY_EPINT5(value)    (USB_DEVICE_EPINTSMRY_EPINT5_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT5_Pos)) /* Assignment of value for EPINT5 in the USB_DEVICE_EPINTSMRY register */
+#define USB_DEVICE_EPINTSMRY_EPINT6_Pos       _UINT16_(6)                                          /* (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt Position */
+#define USB_DEVICE_EPINTSMRY_EPINT6_Msk       (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT6_Pos)   /* (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt Mask */
+#define USB_DEVICE_EPINTSMRY_EPINT6(value)    (USB_DEVICE_EPINTSMRY_EPINT6_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT6_Pos)) /* Assignment of value for EPINT6 in the USB_DEVICE_EPINTSMRY register */
+#define USB_DEVICE_EPINTSMRY_EPINT7_Pos       _UINT16_(7)                                          /* (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt Position */
+#define USB_DEVICE_EPINTSMRY_EPINT7_Msk       (_UINT16_(0x1) << USB_DEVICE_EPINTSMRY_EPINT7_Pos)   /* (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt Mask */
+#define USB_DEVICE_EPINTSMRY_EPINT7(value)    (USB_DEVICE_EPINTSMRY_EPINT7_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT7_Pos)) /* Assignment of value for EPINT7 in the USB_DEVICE_EPINTSMRY register */
+#define USB_DEVICE_EPINTSMRY_Msk              _UINT16_(0x00FF)                                     /* (USB_DEVICE_EPINTSMRY) Register Mask  */
+
+#define USB_DEVICE_EPINTSMRY_EPINT_Pos        _UINT16_(0)                                          /* (USB_DEVICE_EPINTSMRY Position) End Point 7 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT_Msk        (_UINT16_(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos)   /* (USB_DEVICE_EPINTSMRY Mask) EPINT */
+#define USB_DEVICE_EPINTSMRY_EPINT(value)     (USB_DEVICE_EPINTSMRY_EPINT_Msk & (_UINT16_(value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)) 
+
+/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x20) ( R/ 16) HOST Pipe Interrupt Summary -------- */
+#define USB_HOST_PINTSMRY_RESETVALUE          _UINT16_(0x00)                                       /*  (USB_HOST_PINTSMRY) HOST Pipe Interrupt Summary  Reset Value */
+
+#define USB_HOST_PINTSMRY_EPINT0_Pos          _UINT16_(0)                                          /* (USB_HOST_PINTSMRY) Pipe 0 Interrupt Position */
+#define USB_HOST_PINTSMRY_EPINT0_Msk          (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT0_Pos)      /* (USB_HOST_PINTSMRY) Pipe 0 Interrupt Mask */
+#define USB_HOST_PINTSMRY_EPINT0(value)       (USB_HOST_PINTSMRY_EPINT0_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT0_Pos)) /* Assignment of value for EPINT0 in the USB_HOST_PINTSMRY register */
+#define USB_HOST_PINTSMRY_EPINT1_Pos          _UINT16_(1)                                          /* (USB_HOST_PINTSMRY) Pipe 1 Interrupt Position */
+#define USB_HOST_PINTSMRY_EPINT1_Msk          (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT1_Pos)      /* (USB_HOST_PINTSMRY) Pipe 1 Interrupt Mask */
+#define USB_HOST_PINTSMRY_EPINT1(value)       (USB_HOST_PINTSMRY_EPINT1_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT1_Pos)) /* Assignment of value for EPINT1 in the USB_HOST_PINTSMRY register */
+#define USB_HOST_PINTSMRY_EPINT2_Pos          _UINT16_(2)                                          /* (USB_HOST_PINTSMRY) Pipe 2 Interrupt Position */
+#define USB_HOST_PINTSMRY_EPINT2_Msk          (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT2_Pos)      /* (USB_HOST_PINTSMRY) Pipe 2 Interrupt Mask */
+#define USB_HOST_PINTSMRY_EPINT2(value)       (USB_HOST_PINTSMRY_EPINT2_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT2_Pos)) /* Assignment of value for EPINT2 in the USB_HOST_PINTSMRY register */
+#define USB_HOST_PINTSMRY_EPINT3_Pos          _UINT16_(3)                                          /* (USB_HOST_PINTSMRY) Pipe 3 Interrupt Position */
+#define USB_HOST_PINTSMRY_EPINT3_Msk          (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT3_Pos)      /* (USB_HOST_PINTSMRY) Pipe 3 Interrupt Mask */
+#define USB_HOST_PINTSMRY_EPINT3(value)       (USB_HOST_PINTSMRY_EPINT3_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT3_Pos)) /* Assignment of value for EPINT3 in the USB_HOST_PINTSMRY register */
+#define USB_HOST_PINTSMRY_EPINT4_Pos          _UINT16_(4)                                          /* (USB_HOST_PINTSMRY) Pipe 4 Interrupt Position */
+#define USB_HOST_PINTSMRY_EPINT4_Msk          (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT4_Pos)      /* (USB_HOST_PINTSMRY) Pipe 4 Interrupt Mask */
+#define USB_HOST_PINTSMRY_EPINT4(value)       (USB_HOST_PINTSMRY_EPINT4_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT4_Pos)) /* Assignment of value for EPINT4 in the USB_HOST_PINTSMRY register */
+#define USB_HOST_PINTSMRY_EPINT5_Pos          _UINT16_(5)                                          /* (USB_HOST_PINTSMRY) Pipe 5 Interrupt Position */
+#define USB_HOST_PINTSMRY_EPINT5_Msk          (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT5_Pos)      /* (USB_HOST_PINTSMRY) Pipe 5 Interrupt Mask */
+#define USB_HOST_PINTSMRY_EPINT5(value)       (USB_HOST_PINTSMRY_EPINT5_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT5_Pos)) /* Assignment of value for EPINT5 in the USB_HOST_PINTSMRY register */
+#define USB_HOST_PINTSMRY_EPINT6_Pos          _UINT16_(6)                                          /* (USB_HOST_PINTSMRY) Pipe 6 Interrupt Position */
+#define USB_HOST_PINTSMRY_EPINT6_Msk          (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT6_Pos)      /* (USB_HOST_PINTSMRY) Pipe 6 Interrupt Mask */
+#define USB_HOST_PINTSMRY_EPINT6(value)       (USB_HOST_PINTSMRY_EPINT6_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT6_Pos)) /* Assignment of value for EPINT6 in the USB_HOST_PINTSMRY register */
+#define USB_HOST_PINTSMRY_EPINT7_Pos          _UINT16_(7)                                          /* (USB_HOST_PINTSMRY) Pipe 7 Interrupt Position */
+#define USB_HOST_PINTSMRY_EPINT7_Msk          (_UINT16_(0x1) << USB_HOST_PINTSMRY_EPINT7_Pos)      /* (USB_HOST_PINTSMRY) Pipe 7 Interrupt Mask */
+#define USB_HOST_PINTSMRY_EPINT7(value)       (USB_HOST_PINTSMRY_EPINT7_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT7_Pos)) /* Assignment of value for EPINT7 in the USB_HOST_PINTSMRY register */
+#define USB_HOST_PINTSMRY_Msk                 _UINT16_(0x00FF)                                     /* (USB_HOST_PINTSMRY) Register Mask  */
+
+#define USB_HOST_PINTSMRY_EPINT_Pos           _UINT16_(0)                                          /* (USB_HOST_PINTSMRY Position) Pipe 7 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT_Msk           (_UINT16_(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos)      /* (USB_HOST_PINTSMRY Mask) EPINT */
+#define USB_HOST_PINTSMRY_EPINT(value)        (USB_HOST_PINTSMRY_EPINT_Msk & (_UINT16_(value) << USB_HOST_PINTSMRY_EPINT_Pos)) 
+
+/* -------- USB_DESCADD : (USB Offset: 0x24) (R/W 32) Descriptor Address -------- */
+#define USB_DESCADD_RESETVALUE                _UINT32_(0x00)                                       /*  (USB_DESCADD) Descriptor Address  Reset Value */
+
+#define USB_DESCADD_DESCADD_Pos               _UINT32_(0)                                          /* (USB_DESCADD) Descriptor Address Value Position */
+#define USB_DESCADD_DESCADD_Msk               (_UINT32_(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos)    /* (USB_DESCADD) Descriptor Address Value Mask */
+#define USB_DESCADD_DESCADD(value)            (USB_DESCADD_DESCADD_Msk & (_UINT32_(value) << USB_DESCADD_DESCADD_Pos)) /* Assignment of value for DESCADD in the USB_DESCADD register */
+#define USB_DESCADD_Msk                       _UINT32_(0xFFFFFFFF)                                 /* (USB_DESCADD) Register Mask  */
+
+
+/* -------- USB_PADCAL : (USB Offset: 0x28) (R/W 16) USB PAD Calibration -------- */
+#define USB_PADCAL_RESETVALUE                 _UINT16_(0x00)                                       /*  (USB_PADCAL) USB PAD Calibration  Reset Value */
+
+#define USB_PADCAL_TRANSP_Pos                 _UINT16_(0)                                          /* (USB_PADCAL) USB Pad Transp calibration Position */
+#define USB_PADCAL_TRANSP_Msk                 (_UINT16_(0x1F) << USB_PADCAL_TRANSP_Pos)            /* (USB_PADCAL) USB Pad Transp calibration Mask */
+#define USB_PADCAL_TRANSP(value)              (USB_PADCAL_TRANSP_Msk & (_UINT16_(value) << USB_PADCAL_TRANSP_Pos)) /* Assignment of value for TRANSP in the USB_PADCAL register */
+#define USB_PADCAL_TRANSN_Pos                 _UINT16_(6)                                          /* (USB_PADCAL) USB Pad Transn calibration Position */
+#define USB_PADCAL_TRANSN_Msk                 (_UINT16_(0x1F) << USB_PADCAL_TRANSN_Pos)            /* (USB_PADCAL) USB Pad Transn calibration Mask */
+#define USB_PADCAL_TRANSN(value)              (USB_PADCAL_TRANSN_Msk & (_UINT16_(value) << USB_PADCAL_TRANSN_Pos)) /* Assignment of value for TRANSN in the USB_PADCAL register */
+#define USB_PADCAL_TRIM_Pos                   _UINT16_(12)                                         /* (USB_PADCAL) USB Pad Trim calibration Position */
+#define USB_PADCAL_TRIM_Msk                   (_UINT16_(0x7) << USB_PADCAL_TRIM_Pos)               /* (USB_PADCAL) USB Pad Trim calibration Mask */
+#define USB_PADCAL_TRIM(value)                (USB_PADCAL_TRIM_Msk & (_UINT16_(value) << USB_PADCAL_TRIM_Pos)) /* Assignment of value for TRIM in the USB_PADCAL register */
+#define USB_PADCAL_Msk                        _UINT16_(0x77DF)                                     /* (USB_PADCAL) Register Mask  */
+
+
+/* USB register offsets definitions */
+#define USB_DEVICE_ADDR_REG_OFST       _UINT32_(0x00)      /* (USB_DEVICE_ADDR) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer Offset */
+#define USB_DEVICE_PCKSIZE_REG_OFST    _UINT32_(0x04)      /* (USB_DEVICE_PCKSIZE) DEVICE_DESC_BANK Endpoint Bank, Packet Size Offset */
+#define USB_DEVICE_EXTREG_REG_OFST     _UINT32_(0x08)      /* (USB_DEVICE_EXTREG) DEVICE_DESC_BANK Endpoint Bank, Extended Offset */
+#define USB_DEVICE_STATUS_BK_REG_OFST  _UINT32_(0x0A)      /* (USB_DEVICE_STATUS_BK) DEVICE_DESC_BANK Enpoint Bank, Status of Bank Offset */
+#define USB_HOST_ADDR_REG_OFST         _UINT32_(0x00)      /* (USB_HOST_ADDR) HOST_DESC_BANK Host Bank, Adress of Data Buffer Offset */
+#define USB_HOST_PCKSIZE_REG_OFST      _UINT32_(0x04)      /* (USB_HOST_PCKSIZE) HOST_DESC_BANK Host Bank, Packet Size Offset */
+#define USB_HOST_EXTREG_REG_OFST       _UINT32_(0x08)      /* (USB_HOST_EXTREG) HOST_DESC_BANK Host Bank, Extended Offset */
+#define USB_HOST_STATUS_BK_REG_OFST    _UINT32_(0x0A)      /* (USB_HOST_STATUS_BK) HOST_DESC_BANK Host Bank, Status of Bank Offset */
+#define USB_HOST_CTRL_PIPE_REG_OFST    _UINT32_(0x0C)      /* (USB_HOST_CTRL_PIPE) HOST_DESC_BANK Host Bank, Host Control Pipe Offset */
+#define USB_HOST_STATUS_PIPE_REG_OFST  _UINT32_(0x0E)      /* (USB_HOST_STATUS_PIPE) HOST_DESC_BANK Host Bank, Host Status Pipe Offset */
+#define USB_DEVICE_EPCFG_REG_OFST      _UINT32_(0x00)      /* (USB_DEVICE_EPCFG) DEVICE_ENDPOINT End Point Configuration Offset */
+#define USB_DEVICE_EPSTATUSCLR_REG_OFST _UINT32_(0x04)      /* (USB_DEVICE_EPSTATUSCLR) DEVICE_ENDPOINT End Point Pipe Status Clear Offset */
+#define USB_DEVICE_EPSTATUSSET_REG_OFST _UINT32_(0x05)      /* (USB_DEVICE_EPSTATUSSET) DEVICE_ENDPOINT End Point Pipe Status Set Offset */
+#define USB_DEVICE_EPSTATUS_REG_OFST   _UINT32_(0x06)      /* (USB_DEVICE_EPSTATUS) DEVICE_ENDPOINT End Point Pipe Status Offset */
+#define USB_DEVICE_EPINTFLAG_REG_OFST  _UINT32_(0x07)      /* (USB_DEVICE_EPINTFLAG) DEVICE_ENDPOINT End Point Interrupt Flag Offset */
+#define USB_DEVICE_EPINTENCLR_REG_OFST _UINT32_(0x08)      /* (USB_DEVICE_EPINTENCLR) DEVICE_ENDPOINT End Point Interrupt Clear Flag Offset */
+#define USB_DEVICE_EPINTENSET_REG_OFST _UINT32_(0x09)      /* (USB_DEVICE_EPINTENSET) DEVICE_ENDPOINT End Point Interrupt Set Flag Offset */
+#define USB_HOST_PCFG_REG_OFST         _UINT32_(0x00)      /* (USB_HOST_PCFG) HOST_PIPE End Point Configuration Offset */
+#define USB_HOST_BINTERVAL_REG_OFST    _UINT32_(0x03)      /* (USB_HOST_BINTERVAL) HOST_PIPE Bus Access Period of Pipe Offset */
+#define USB_HOST_PSTATUSCLR_REG_OFST   _UINT32_(0x04)      /* (USB_HOST_PSTATUSCLR) HOST_PIPE End Point Pipe Status Clear Offset */
+#define USB_HOST_PSTATUSSET_REG_OFST   _UINT32_(0x05)      /* (USB_HOST_PSTATUSSET) HOST_PIPE End Point Pipe Status Set Offset */
+#define USB_HOST_PSTATUS_REG_OFST      _UINT32_(0x06)      /* (USB_HOST_PSTATUS) HOST_PIPE End Point Pipe Status Offset */
+#define USB_HOST_PINTFLAG_REG_OFST     _UINT32_(0x07)      /* (USB_HOST_PINTFLAG) HOST_PIPE Pipe Interrupt Flag Offset */
+#define USB_HOST_PINTENCLR_REG_OFST    _UINT32_(0x08)      /* (USB_HOST_PINTENCLR) HOST_PIPE Pipe Interrupt Flag Clear Offset */
+#define USB_HOST_PINTENSET_REG_OFST    _UINT32_(0x09)      /* (USB_HOST_PINTENSET) HOST_PIPE Pipe Interrupt Flag Set Offset */
+#define USB_CTRLA_REG_OFST             _UINT32_(0x00)      /* (USB_CTRLA) Control A Offset */
+#define USB_SYNCBUSY_REG_OFST          _UINT32_(0x02)      /* (USB_SYNCBUSY) Synchronization Busy Offset */
+#define USB_QOSCTRL_REG_OFST           _UINT32_(0x03)      /* (USB_QOSCTRL) USB Quality Of Service Offset */
+#define USB_DEVICE_CTRLB_REG_OFST      _UINT32_(0x08)      /* (USB_DEVICE_CTRLB) DEVICE Control B Offset */
+#define USB_HOST_CTRLB_REG_OFST        _UINT32_(0x08)      /* (USB_HOST_CTRLB) HOST Control B Offset */
+#define USB_DEVICE_DADD_REG_OFST       _UINT32_(0x0A)      /* (USB_DEVICE_DADD) DEVICE Device Address Offset */
+#define USB_HOST_HSOFC_REG_OFST        _UINT32_(0x0A)      /* (USB_HOST_HSOFC) HOST Host Start Of Frame Control Offset */
+#define USB_DEVICE_STATUS_REG_OFST     _UINT32_(0x0C)      /* (USB_DEVICE_STATUS) DEVICE Status Offset */
+#define USB_HOST_STATUS_REG_OFST       _UINT32_(0x0C)      /* (USB_HOST_STATUS) HOST Status Offset */
+#define USB_FSMSTATUS_REG_OFST         _UINT32_(0x0D)      /* (USB_FSMSTATUS) Finite State Machine Status Offset */
+#define USB_DEVICE_FNUM_REG_OFST       _UINT32_(0x10)      /* (USB_DEVICE_FNUM) DEVICE Device Frame Number Offset */
+#define USB_HOST_FNUM_REG_OFST         _UINT32_(0x10)      /* (USB_HOST_FNUM) HOST Host Frame Number Offset */
+#define USB_HOST_FLENHIGH_REG_OFST     _UINT32_(0x12)      /* (USB_HOST_FLENHIGH) HOST Host Frame Length Offset */
+#define USB_DEVICE_INTENCLR_REG_OFST   _UINT32_(0x14)      /* (USB_DEVICE_INTENCLR) DEVICE Device Interrupt Enable Clear Offset */
+#define USB_HOST_INTENCLR_REG_OFST     _UINT32_(0x14)      /* (USB_HOST_INTENCLR) HOST Host Interrupt Enable Clear Offset */
+#define USB_DEVICE_INTENSET_REG_OFST   _UINT32_(0x18)      /* (USB_DEVICE_INTENSET) DEVICE Device Interrupt Enable Set Offset */
+#define USB_HOST_INTENSET_REG_OFST     _UINT32_(0x18)      /* (USB_HOST_INTENSET) HOST Host Interrupt Enable Set Offset */
+#define USB_DEVICE_INTFLAG_REG_OFST    _UINT32_(0x1C)      /* (USB_DEVICE_INTFLAG) DEVICE Device Interrupt Flag Offset */
+#define USB_HOST_INTFLAG_REG_OFST      _UINT32_(0x1C)      /* (USB_HOST_INTFLAG) HOST Host Interrupt Flag Offset */
+#define USB_DEVICE_EPINTSMRY_REG_OFST  _UINT32_(0x20)      /* (USB_DEVICE_EPINTSMRY) DEVICE End Point Interrupt Summary Offset */
+#define USB_HOST_PINTSMRY_REG_OFST     _UINT32_(0x20)      /* (USB_HOST_PINTSMRY) HOST Pipe Interrupt Summary Offset */
+#define USB_DESCADD_REG_OFST           _UINT32_(0x24)      /* (USB_DESCADD) Descriptor Address Offset */
+#define USB_PADCAL_REG_OFST            _UINT32_(0x28)      /* (USB_PADCAL) USB PAD Calibration Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* DEVICE_DESC_BANK register API structure */
+typedef struct
+{
+  __IO  uint32_t                       USB_ADDR;           /* Offset: 0x00 (R/W  32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+  __IO  uint32_t                       USB_PCKSIZE;        /* Offset: 0x04 (R/W  32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+  __IO  uint16_t                       USB_EXTREG;         /* Offset: 0x08 (R/W  16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+  __IO  uint8_t                        USB_STATUS_BK;      /* Offset: 0x0A (R/W  8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+  __I   uint8_t                        Reserved1[0x05];
+} usb_device_desc_bank_registers_t;
+
+/* HOST_DESC_BANK register API structure */
+typedef struct
+{
+  __IO  uint32_t                       USB_ADDR;           /* Offset: 0x00 (R/W  32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+  __IO  uint32_t                       USB_PCKSIZE;        /* Offset: 0x04 (R/W  32) HOST_DESC_BANK Host Bank, Packet Size */
+  __IO  uint16_t                       USB_EXTREG;         /* Offset: 0x08 (R/W  16) HOST_DESC_BANK Host Bank, Extended */
+  __IO  uint8_t                        USB_STATUS_BK;      /* Offset: 0x0A (R/W  8) HOST_DESC_BANK Host Bank, Status of Bank */
+  __I   uint8_t                        Reserved1[0x01];
+  __IO  uint16_t                       USB_CTRL_PIPE;      /* Offset: 0x0C (R/W  16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+  __IO  uint16_t                       USB_STATUS_PIPE;    /* Offset: 0x0E (R/W  16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+} usb_host_desc_bank_registers_t;
+
+/* DEVICE_ENDPOINT register API structure */
+typedef struct
+{
+  __IO  uint8_t                        USB_EPCFG;          /* Offset: 0x00 (R/W  8) DEVICE_ENDPOINT End Point Configuration */
+  __I   uint8_t                        Reserved1[0x03];
+  __O   uint8_t                        USB_EPSTATUSCLR;    /* Offset: 0x04 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+  __O   uint8_t                        USB_EPSTATUSSET;    /* Offset: 0x05 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Set */
+  __I   uint8_t                        USB_EPSTATUS;       /* Offset: 0x06 (R/   8) DEVICE_ENDPOINT End Point Pipe Status */
+  __IO  uint8_t                        USB_EPINTFLAG;      /* Offset: 0x07 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Flag */
+  __IO  uint8_t                        USB_EPINTENCLR;     /* Offset: 0x08 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+  __IO  uint8_t                        USB_EPINTENSET;     /* Offset: 0x09 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+  __I   uint8_t                        Reserved2[0x16];
+} usb_device_endpoint_registers_t;
+
+/* HOST_PIPE register API structure */
+typedef struct
+{
+  __IO  uint8_t                        USB_PCFG;           /* Offset: 0x00 (R/W  8) HOST_PIPE End Point Configuration */
+  __I   uint8_t                        Reserved1[0x02];
+  __IO  uint8_t                        USB_BINTERVAL;      /* Offset: 0x03 (R/W  8) HOST_PIPE Bus Access Period of Pipe */
+  __O   uint8_t                        USB_PSTATUSCLR;     /* Offset: 0x04 ( /W  8) HOST_PIPE End Point Pipe Status Clear */
+  __O   uint8_t                        USB_PSTATUSSET;     /* Offset: 0x05 ( /W  8) HOST_PIPE End Point Pipe Status Set */
+  __I   uint8_t                        USB_PSTATUS;        /* Offset: 0x06 (R/   8) HOST_PIPE End Point Pipe Status */
+  __IO  uint8_t                        USB_PINTFLAG;       /* Offset: 0x07 (R/W  8) HOST_PIPE Pipe Interrupt Flag */
+  __IO  uint8_t                        USB_PINTENCLR;      /* Offset: 0x08 (R/W  8) HOST_PIPE Pipe Interrupt Flag Clear */
+  __IO  uint8_t                        USB_PINTENSET;      /* Offset: 0x09 (R/W  8) HOST_PIPE Pipe Interrupt Flag Set */
+  __I   uint8_t                        Reserved2[0x16];
+} usb_host_pipe_registers_t;
+
+#define USB_DEVICE_DESC_BANK_NUMBER 2
+
+/* USB_DESCRIPTOR register API structure */
+typedef struct
+{  /* Full-Speed Universal Serial Bus */
+        usb_device_desc_bank_registers_t DEVICE_DESC_BANK[USB_DEVICE_DESC_BANK_NUMBER]; /* Offset: 0x00  */
+} usb_descriptor_device_registers_t;
+
+#define USB_HOST_DESC_BANK_NUMBER 2
+
+/* USB_DESCRIPTOR register API structure */
+typedef struct
+{  /* Full-Speed Universal Serial Bus */
+        usb_host_desc_bank_registers_t HOST_DESC_BANK[USB_HOST_DESC_BANK_NUMBER]; /* Offset: 0x00  */
+} usb_descriptor_host_registers_t;
+
+/* USB_DESCRIPTOR hardware registers */
+typedef union
+{  /* Full-Speed Universal Serial Bus */
+       usb_descriptor_device_registers_t DEVICE;         /* USB is Device */
+       usb_descriptor_host_registers_t HOST;           /* USB is Host */
+} usb_descriptor_registers_t;
+
+#define USB_DEVICE_ENDPOINT_NUMBER 8
+
+/* USB register API structure */
+typedef struct
+{  /* Full-Speed Universal Serial Bus */
+  __IO  uint8_t                        USB_CTRLA;          /* Offset: 0x00 (R/W  8) Control A */
+  __I   uint8_t                        Reserved1[0x01];
+  __I   uint8_t                        USB_SYNCBUSY;       /* Offset: 0x02 (R/   8) Synchronization Busy */
+  __IO  uint8_t                        USB_QOSCTRL;        /* Offset: 0x03 (R/W  8) USB Quality Of Service */
+  __I   uint8_t                        Reserved2[0x04];
+  __IO  uint16_t                       USB_CTRLB;          /* Offset: 0x08 (R/W  16) DEVICE Control B */
+  __IO  uint8_t                        USB_DADD;           /* Offset: 0x0A (R/W  8) DEVICE Device Address */
+  __I   uint8_t                        Reserved3[0x01];
+  __I   uint8_t                        USB_STATUS;         /* Offset: 0x0C (R/   8) DEVICE Status */
+  __I   uint8_t                        USB_FSMSTATUS;      /* Offset: 0x0D (R/   8) Finite State Machine Status */
+  __I   uint8_t                        Reserved4[0x02];
+  __I   uint16_t                       USB_FNUM;           /* Offset: 0x10 (R/   16) DEVICE Device Frame Number */
+  __I   uint8_t                        Reserved5[0x02];
+  __IO  uint16_t                       USB_INTENCLR;       /* Offset: 0x14 (R/W  16) DEVICE Device Interrupt Enable Clear */
+  __I   uint8_t                        Reserved6[0x02];
+  __IO  uint16_t                       USB_INTENSET;       /* Offset: 0x18 (R/W  16) DEVICE Device Interrupt Enable Set */
+  __I   uint8_t                        Reserved7[0x02];
+  __IO  uint16_t                       USB_INTFLAG;        /* Offset: 0x1C (R/W  16) DEVICE Device Interrupt Flag */
+  __I   uint8_t                        Reserved8[0x02];
+  __I   uint16_t                       USB_EPINTSMRY;      /* Offset: 0x20 (R/   16) DEVICE End Point Interrupt Summary */
+  __I   uint8_t                        Reserved9[0x02];
+  __IO  uint32_t                       USB_DESCADD;        /* Offset: 0x24 (R/W  32) Descriptor Address */
+  __IO  uint16_t                       USB_PADCAL;         /* Offset: 0x28 (R/W  16) USB PAD Calibration */
+  __I   uint8_t                        Reserved10[0xD6];
+        usb_device_endpoint_registers_t DEVICE_ENDPOINT[USB_DEVICE_ENDPOINT_NUMBER]; /* Offset: 0x100  */
+} usb_device_registers_t;
+
+#define USB_HOST_PIPE_NUMBER 8
+
+/* USB register API structure */
+typedef struct
+{  /* Full-Speed Universal Serial Bus */
+  __IO  uint8_t                        USB_CTRLA;          /* Offset: 0x00 (R/W  8) Control A */
+  __I   uint8_t                        Reserved1[0x01];
+  __I   uint8_t                        USB_SYNCBUSY;       /* Offset: 0x02 (R/   8) Synchronization Busy */
+  __IO  uint8_t                        USB_QOSCTRL;        /* Offset: 0x03 (R/W  8) USB Quality Of Service */
+  __I   uint8_t                        Reserved2[0x04];
+  __IO  uint16_t                       USB_CTRLB;          /* Offset: 0x08 (R/W  16) HOST Control B */
+  __IO  uint8_t                        USB_HSOFC;          /* Offset: 0x0A (R/W  8) HOST Host Start Of Frame Control */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        USB_STATUS;         /* Offset: 0x0C (R/W  8) HOST Status */
+  __I   uint8_t                        USB_FSMSTATUS;      /* Offset: 0x0D (R/   8) Finite State Machine Status */
+  __I   uint8_t                        Reserved4[0x02];
+  __IO  uint16_t                       USB_FNUM;           /* Offset: 0x10 (R/W  16) HOST Host Frame Number */
+  __I   uint8_t                        USB_FLENHIGH;       /* Offset: 0x12 (R/   8) HOST Host Frame Length */
+  __I   uint8_t                        Reserved5[0x01];
+  __IO  uint16_t                       USB_INTENCLR;       /* Offset: 0x14 (R/W  16) HOST Host Interrupt Enable Clear */
+  __I   uint8_t                        Reserved6[0x02];
+  __IO  uint16_t                       USB_INTENSET;       /* Offset: 0x18 (R/W  16) HOST Host Interrupt Enable Set */
+  __I   uint8_t                        Reserved7[0x02];
+  __IO  uint16_t                       USB_INTFLAG;        /* Offset: 0x1C (R/W  16) HOST Host Interrupt Flag */
+  __I   uint8_t                        Reserved8[0x02];
+  __I   uint16_t                       USB_PINTSMRY;       /* Offset: 0x20 (R/   16) HOST Pipe Interrupt Summary */
+  __I   uint8_t                        Reserved9[0x02];
+  __IO  uint32_t                       USB_DESCADD;        /* Offset: 0x24 (R/W  32) Descriptor Address */
+  __IO  uint16_t                       USB_PADCAL;         /* Offset: 0x28 (R/W  16) USB PAD Calibration */
+  __I   uint8_t                        Reserved10[0xD6];
+        usb_host_pipe_registers_t      HOST_PIPE[USB_HOST_PIPE_NUMBER]; /* Offset: 0x100  */
+} usb_host_registers_t;
+
+/* USB hardware registers */
+typedef union
+{  /* Full-Speed Universal Serial Bus */
+       usb_device_registers_t         DEVICE;         /* USB is Device */
+       usb_host_registers_t           HOST;           /* USB is Host */
+} usb_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* USB_DESCRIPTOR memory section attribute */
+#define SECTION_USB_DESCRIPTOR
+
+#endif /* _PIC32CMGC00_USB_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/wdt.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/wdt.h
new file mode 100644
index 00000000..b915a74c
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/component/wdt.h
@@ -0,0 +1,228 @@
+/*
+ * Component description for WDT
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CMGC00_WDT_COMPONENT_H_
+#define _PIC32CMGC00_WDT_COMPONENT_H_
+
+/* ************************************************************************** */
+/*                      SOFTWARE API DEFINITION FOR WDT                       */
+/* ************************************************************************** */
+
+/* -------- WDT_CTRLA : (WDT Offset: 0x00) (R/W 8) Control -------- */
+#define WDT_CTRLA_RESETVALUE                  _UINT8_(0x00)                                        /*  (WDT_CTRLA) Control  Reset Value */
+
+#define WDT_CTRLA_ENABLE_Pos                  _UINT8_(1)                                           /* (WDT_CTRLA) Enable Position */
+#define WDT_CTRLA_ENABLE_Msk                  (_UINT8_(0x1) << WDT_CTRLA_ENABLE_Pos)               /* (WDT_CTRLA) Enable Mask */
+#define WDT_CTRLA_ENABLE(value)               (WDT_CTRLA_ENABLE_Msk & (_UINT8_(value) << WDT_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the WDT_CTRLA register */
+#define WDT_CTRLA_WEN_Pos                     _UINT8_(2)                                           /* (WDT_CTRLA) Watchdog Timer Window Mode Enable Position */
+#define WDT_CTRLA_WEN_Msk                     (_UINT8_(0x1) << WDT_CTRLA_WEN_Pos)                  /* (WDT_CTRLA) Watchdog Timer Window Mode Enable Mask */
+#define WDT_CTRLA_WEN(value)                  (WDT_CTRLA_WEN_Msk & (_UINT8_(value) << WDT_CTRLA_WEN_Pos)) /* Assignment of value for WEN in the WDT_CTRLA register */
+#define WDT_CTRLA_RUNSTDBY_Pos                _UINT8_(6)                                           /* (WDT_CTRLA) Run During Standby Position */
+#define WDT_CTRLA_RUNSTDBY_Msk                (_UINT8_(0x1) << WDT_CTRLA_RUNSTDBY_Pos)             /* (WDT_CTRLA) Run During Standby Mask */
+#define WDT_CTRLA_RUNSTDBY(value)             (WDT_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << WDT_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the WDT_CTRLA register */
+#define WDT_CTRLA_ALWAYSON_Pos                _UINT8_(7)                                           /* (WDT_CTRLA) Always-On Position */
+#define WDT_CTRLA_ALWAYSON_Msk                (_UINT8_(0x1) << WDT_CTRLA_ALWAYSON_Pos)             /* (WDT_CTRLA) Always-On Mask */
+#define WDT_CTRLA_ALWAYSON(value)             (WDT_CTRLA_ALWAYSON_Msk & (_UINT8_(value) << WDT_CTRLA_ALWAYSON_Pos)) /* Assignment of value for ALWAYSON in the WDT_CTRLA register */
+#define WDT_CTRLA_Msk                         _UINT8_(0xC6)                                        /* (WDT_CTRLA) Register Mask  */
+
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x01) (R/W 8) Configuration -------- */
+#define WDT_CONFIG_RESETVALUE                 _UINT8_(0xBB)                                        /*  (WDT_CONFIG) Configuration  Reset Value */
+
+#define WDT_CONFIG_PER_Pos                    _UINT8_(0)                                           /* (WDT_CONFIG) Time-Out Period Position */
+#define WDT_CONFIG_PER_Msk                    (_UINT8_(0xF) << WDT_CONFIG_PER_Pos)                 /* (WDT_CONFIG) Time-Out Period Mask */
+#define WDT_CONFIG_PER(value)                 (WDT_CONFIG_PER_Msk & (_UINT8_(value) << WDT_CONFIG_PER_Pos)) /* Assignment of value for PER in the WDT_CONFIG register */
+#define   WDT_CONFIG_PER_CYC8_Val             _UINT8_(0x0)                                         /* (WDT_CONFIG) 8 clock cycles  */
+#define   WDT_CONFIG_PER_CYC16_Val            _UINT8_(0x1)                                         /* (WDT_CONFIG) 16 clock cycles  */
+#define   WDT_CONFIG_PER_CYC32_Val            _UINT8_(0x2)                                         /* (WDT_CONFIG) 32 clock cycles  */
+#define   WDT_CONFIG_PER_CYC64_Val            _UINT8_(0x3)                                         /* (WDT_CONFIG) 64 clock cycles  */
+#define   WDT_CONFIG_PER_CYC128_Val           _UINT8_(0x4)                                         /* (WDT_CONFIG) 128 clock cycles  */
+#define   WDT_CONFIG_PER_CYC256_Val           _UINT8_(0x5)                                         /* (WDT_CONFIG) 256 clock cycles  */
+#define   WDT_CONFIG_PER_CYC512_Val           _UINT8_(0x6)                                         /* (WDT_CONFIG) 512 clock cycles  */
+#define   WDT_CONFIG_PER_CYC1024_Val          _UINT8_(0x7)                                         /* (WDT_CONFIG) 1024 clock cycles  */
+#define   WDT_CONFIG_PER_CYC2048_Val          _UINT8_(0x8)                                         /* (WDT_CONFIG) 2048 clock cycles  */
+#define   WDT_CONFIG_PER_CYC4096_Val          _UINT8_(0x9)                                         /* (WDT_CONFIG) 4096 clock cycles  */
+#define   WDT_CONFIG_PER_CYC8192_Val          _UINT8_(0xA)                                         /* (WDT_CONFIG) 8192 clock cycles  */
+#define   WDT_CONFIG_PER_CYC16384_Val         _UINT8_(0xB)                                         /* (WDT_CONFIG) 16384 clock cycles  */
+#define WDT_CONFIG_PER_CYC8                   (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos)      /* (WDT_CONFIG) 8 clock cycles Position */
+#define WDT_CONFIG_PER_CYC16                  (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos)     /* (WDT_CONFIG) 16 clock cycles Position */
+#define WDT_CONFIG_PER_CYC32                  (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos)     /* (WDT_CONFIG) 32 clock cycles Position */
+#define WDT_CONFIG_PER_CYC64                  (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos)     /* (WDT_CONFIG) 64 clock cycles Position */
+#define WDT_CONFIG_PER_CYC128                 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos)    /* (WDT_CONFIG) 128 clock cycles Position */
+#define WDT_CONFIG_PER_CYC256                 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos)    /* (WDT_CONFIG) 256 clock cycles Position */
+#define WDT_CONFIG_PER_CYC512                 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos)    /* (WDT_CONFIG) 512 clock cycles Position */
+#define WDT_CONFIG_PER_CYC1024                (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos)   /* (WDT_CONFIG) 1024 clock cycles Position */
+#define WDT_CONFIG_PER_CYC2048                (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos)   /* (WDT_CONFIG) 2048 clock cycles Position */
+#define WDT_CONFIG_PER_CYC4096                (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos)   /* (WDT_CONFIG) 4096 clock cycles Position */
+#define WDT_CONFIG_PER_CYC8192                (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos)   /* (WDT_CONFIG) 8192 clock cycles Position */
+#define WDT_CONFIG_PER_CYC16384               (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos)  /* (WDT_CONFIG) 16384 clock cycles Position */
+#define WDT_CONFIG_WINDOW_Pos                 _UINT8_(4)                                           /* (WDT_CONFIG) Window Mode Time-Out Period Position */
+#define WDT_CONFIG_WINDOW_Msk                 (_UINT8_(0xF) << WDT_CONFIG_WINDOW_Pos)              /* (WDT_CONFIG) Window Mode Time-Out Period Mask */
+#define WDT_CONFIG_WINDOW(value)              (WDT_CONFIG_WINDOW_Msk & (_UINT8_(value) << WDT_CONFIG_WINDOW_Pos)) /* Assignment of value for WINDOW in the WDT_CONFIG register */
+#define   WDT_CONFIG_WINDOW_CYC8_Val          _UINT8_(0x0)                                         /* (WDT_CONFIG) 8 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC16_Val         _UINT8_(0x1)                                         /* (WDT_CONFIG) 16 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC32_Val         _UINT8_(0x2)                                         /* (WDT_CONFIG) 32 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC64_Val         _UINT8_(0x3)                                         /* (WDT_CONFIG) 64 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC128_Val        _UINT8_(0x4)                                         /* (WDT_CONFIG) 128 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC256_Val        _UINT8_(0x5)                                         /* (WDT_CONFIG) 256 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC512_Val        _UINT8_(0x6)                                         /* (WDT_CONFIG) 512 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC1024_Val       _UINT8_(0x7)                                         /* (WDT_CONFIG) 1024 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC2048_Val       _UINT8_(0x8)                                         /* (WDT_CONFIG) 2048 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC4096_Val       _UINT8_(0x9)                                         /* (WDT_CONFIG) 4096 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC8192_Val       _UINT8_(0xA)                                         /* (WDT_CONFIG) 8192 clock cycles  */
+#define   WDT_CONFIG_WINDOW_CYC16384_Val      _UINT8_(0xB)                                         /* (WDT_CONFIG) 16384 clock cycles  */
+#define WDT_CONFIG_WINDOW_CYC8                (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 8 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC16               (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 16 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC32               (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 32 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC64               (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 64 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC128              (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 128 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC256              (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 256 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC512              (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 512 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC1024             (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 1024 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC2048             (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 2048 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC4096             (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 4096 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC8192             (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 8192 clock cycles Position */
+#define WDT_CONFIG_WINDOW_CYC16384            (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos) /* (WDT_CONFIG) 16384 clock cycles Position */
+#define WDT_CONFIG_Msk                        _UINT8_(0xFF)                                        /* (WDT_CONFIG) Register Mask  */
+
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x02) (R/W 8) Early Warning Interrupt Control -------- */
+#define WDT_EWCTRL_RESETVALUE                 _UINT8_(0x0B)                                        /*  (WDT_EWCTRL) Early Warning Interrupt Control  Reset Value */
+
+#define WDT_EWCTRL_EWOFFSET_Pos               _UINT8_(0)                                           /* (WDT_EWCTRL) Early Warning Interrupt Time Offset Position */
+#define WDT_EWCTRL_EWOFFSET_Msk               (_UINT8_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)            /* (WDT_EWCTRL) Early Warning Interrupt Time Offset Mask */
+#define WDT_EWCTRL_EWOFFSET(value)            (WDT_EWCTRL_EWOFFSET_Msk & (_UINT8_(value) << WDT_EWCTRL_EWOFFSET_Pos)) /* Assignment of value for EWOFFSET in the WDT_EWCTRL register */
+#define   WDT_EWCTRL_EWOFFSET_CYC8_Val        _UINT8_(0x0)                                         /* (WDT_EWCTRL) 8 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC16_Val       _UINT8_(0x1)                                         /* (WDT_EWCTRL) 16 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC32_Val       _UINT8_(0x2)                                         /* (WDT_EWCTRL) 32 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC64_Val       _UINT8_(0x3)                                         /* (WDT_EWCTRL) 64 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC128_Val      _UINT8_(0x4)                                         /* (WDT_EWCTRL) 128 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC256_Val      _UINT8_(0x5)                                         /* (WDT_EWCTRL) 256 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC512_Val      _UINT8_(0x6)                                         /* (WDT_EWCTRL) 512 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC1024_Val     _UINT8_(0x7)                                         /* (WDT_EWCTRL) 1024 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC2048_Val     _UINT8_(0x8)                                         /* (WDT_EWCTRL) 2048 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC4096_Val     _UINT8_(0x9)                                         /* (WDT_EWCTRL) 4096 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC8192_Val     _UINT8_(0xA)                                         /* (WDT_EWCTRL) 8192 clock cycles  */
+#define   WDT_EWCTRL_EWOFFSET_CYC16384_Val    _UINT8_(0xB)                                         /* (WDT_EWCTRL) 16384 clock cycles  */
+#define WDT_EWCTRL_EWOFFSET_CYC8              (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 8 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC16             (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 16 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC32             (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 32 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC64             (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 64 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC128            (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 128 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC256            (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 256 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC512            (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 512 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC1024           (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 1024 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC2048           (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 2048 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC4096           (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 4096 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC8192           (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 8192 clock cycles Position */
+#define WDT_EWCTRL_EWOFFSET_CYC16384          (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos) /* (WDT_EWCTRL) 16384 clock cycles Position */
+#define WDT_EWCTRL_Msk                        _UINT8_(0x0F)                                        /* (WDT_EWCTRL) Register Mask  */
+
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#define WDT_INTENCLR_RESETVALUE               _UINT8_(0x00)                                        /*  (WDT_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define WDT_INTENCLR_EW_Pos                   _UINT8_(0)                                           /* (WDT_INTENCLR) Early Warning Interrupt Enable Position */
+#define WDT_INTENCLR_EW_Msk                   (_UINT8_(0x1) << WDT_INTENCLR_EW_Pos)                /* (WDT_INTENCLR) Early Warning Interrupt Enable Mask */
+#define WDT_INTENCLR_EW(value)                (WDT_INTENCLR_EW_Msk & (_UINT8_(value) << WDT_INTENCLR_EW_Pos)) /* Assignment of value for EW in the WDT_INTENCLR register */
+#define WDT_INTENCLR_Msk                      _UINT8_(0x01)                                        /* (WDT_INTENCLR) Register Mask  */
+
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#define WDT_INTENSET_RESETVALUE               _UINT8_(0x00)                                        /*  (WDT_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define WDT_INTENSET_EW_Pos                   _UINT8_(0)                                           /* (WDT_INTENSET) Early Warning Interrupt Enable Position */
+#define WDT_INTENSET_EW_Msk                   (_UINT8_(0x1) << WDT_INTENSET_EW_Pos)                /* (WDT_INTENSET) Early Warning Interrupt Enable Mask */
+#define WDT_INTENSET_EW(value)                (WDT_INTENSET_EW_Msk & (_UINT8_(value) << WDT_INTENSET_EW_Pos)) /* Assignment of value for EW in the WDT_INTENSET register */
+#define WDT_INTENSET_Msk                      _UINT8_(0x01)                                        /* (WDT_INTENSET) Register Mask  */
+
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#define WDT_INTFLAG_RESETVALUE                _UINT8_(0x00)                                        /*  (WDT_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define WDT_INTFLAG_EW_Pos                    _UINT8_(0)                                           /* (WDT_INTFLAG) Early Warning Position */
+#define WDT_INTFLAG_EW_Msk                    (_UINT8_(0x1) << WDT_INTFLAG_EW_Pos)                 /* (WDT_INTFLAG) Early Warning Mask */
+#define WDT_INTFLAG_EW(value)                 (WDT_INTFLAG_EW_Msk & (_UINT8_(value) << WDT_INTFLAG_EW_Pos)) /* Assignment of value for EW in the WDT_INTFLAG register */
+#define WDT_INTFLAG_Msk                       _UINT8_(0x01)                                        /* (WDT_INTFLAG) Register Mask  */
+
+
+/* -------- WDT_SYNCBUSY : (WDT Offset: 0x08) ( R/ 32) Synchronization Busy -------- */
+#define WDT_SYNCBUSY_RESETVALUE               _UINT32_(0x00)                                       /*  (WDT_SYNCBUSY) Synchronization Busy  Reset Value */
+
+#define WDT_SYNCBUSY_ENABLE_Pos               _UINT32_(1)                                          /* (WDT_SYNCBUSY) Enable Synchronization Busy Position */
+#define WDT_SYNCBUSY_ENABLE_Msk               (_UINT32_(0x1) << WDT_SYNCBUSY_ENABLE_Pos)           /* (WDT_SYNCBUSY) Enable Synchronization Busy Mask */
+#define WDT_SYNCBUSY_ENABLE(value)            (WDT_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << WDT_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the WDT_SYNCBUSY register */
+#define WDT_SYNCBUSY_WEN_Pos                  _UINT32_(2)                                          /* (WDT_SYNCBUSY) Window Enable Synchronization Busy Position */
+#define WDT_SYNCBUSY_WEN_Msk                  (_UINT32_(0x1) << WDT_SYNCBUSY_WEN_Pos)              /* (WDT_SYNCBUSY) Window Enable Synchronization Busy Mask */
+#define WDT_SYNCBUSY_WEN(value)               (WDT_SYNCBUSY_WEN_Msk & (_UINT32_(value) << WDT_SYNCBUSY_WEN_Pos)) /* Assignment of value for WEN in the WDT_SYNCBUSY register */
+#define WDT_SYNCBUSY_RUNSTDBY_Pos             _UINT32_(3)                                          /* (WDT_SYNCBUSY) Run During Standby Synchronization Busy Position */
+#define WDT_SYNCBUSY_RUNSTDBY_Msk             (_UINT32_(0x1) << WDT_SYNCBUSY_RUNSTDBY_Pos)         /* (WDT_SYNCBUSY) Run During Standby Synchronization Busy Mask */
+#define WDT_SYNCBUSY_RUNSTDBY(value)          (WDT_SYNCBUSY_RUNSTDBY_Msk & (_UINT32_(value) << WDT_SYNCBUSY_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the WDT_SYNCBUSY register */
+#define WDT_SYNCBUSY_ALWAYSON_Pos             _UINT32_(4)                                          /* (WDT_SYNCBUSY) Always-On Synchronization Busy Position */
+#define WDT_SYNCBUSY_ALWAYSON_Msk             (_UINT32_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos)         /* (WDT_SYNCBUSY) Always-On Synchronization Busy Mask */
+#define WDT_SYNCBUSY_ALWAYSON(value)          (WDT_SYNCBUSY_ALWAYSON_Msk & (_UINT32_(value) << WDT_SYNCBUSY_ALWAYSON_Pos)) /* Assignment of value for ALWAYSON in the WDT_SYNCBUSY register */
+#define WDT_SYNCBUSY_CLEAR_Pos                _UINT32_(5)                                          /* (WDT_SYNCBUSY) Clear Synchronization Busy Position */
+#define WDT_SYNCBUSY_CLEAR_Msk                (_UINT32_(0x1) << WDT_SYNCBUSY_CLEAR_Pos)            /* (WDT_SYNCBUSY) Clear Synchronization Busy Mask */
+#define WDT_SYNCBUSY_CLEAR(value)             (WDT_SYNCBUSY_CLEAR_Msk & (_UINT32_(value) << WDT_SYNCBUSY_CLEAR_Pos)) /* Assignment of value for CLEAR in the WDT_SYNCBUSY register */
+#define WDT_SYNCBUSY_Msk                      _UINT32_(0x0000003E)                                 /* (WDT_SYNCBUSY) Register Mask  */
+
+
+/* -------- WDT_CLEAR : (WDT Offset: 0x0C) ( /W 8) Clear -------- */
+#define WDT_CLEAR_RESETVALUE                  _UINT8_(0x00)                                        /*  (WDT_CLEAR) Clear  Reset Value */
+
+#define WDT_CLEAR_CLEAR_Pos                   _UINT8_(0)                                           /* (WDT_CLEAR) Watchdog Clear Position */
+#define WDT_CLEAR_CLEAR_Msk                   (_UINT8_(0xFF) << WDT_CLEAR_CLEAR_Pos)               /* (WDT_CLEAR) Watchdog Clear Mask */
+#define WDT_CLEAR_CLEAR(value)                (WDT_CLEAR_CLEAR_Msk & (_UINT8_(value) << WDT_CLEAR_CLEAR_Pos)) /* Assignment of value for CLEAR in the WDT_CLEAR register */
+#define   WDT_CLEAR_CLEAR_KEY_Val             _UINT8_(0xA5)                                        /* (WDT_CLEAR) Clear Key  */
+#define WDT_CLEAR_CLEAR_KEY                   (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)     /* (WDT_CLEAR) Clear Key Position */
+#define WDT_CLEAR_Msk                         _UINT8_(0xFF)                                        /* (WDT_CLEAR) Register Mask  */
+
+
+/* WDT register offsets definitions */
+#define WDT_CTRLA_REG_OFST             _UINT32_(0x00)      /* (WDT_CTRLA) Control Offset */
+#define WDT_CONFIG_REG_OFST            _UINT32_(0x01)      /* (WDT_CONFIG) Configuration Offset */
+#define WDT_EWCTRL_REG_OFST            _UINT32_(0x02)      /* (WDT_EWCTRL) Early Warning Interrupt Control Offset */
+#define WDT_INTENCLR_REG_OFST          _UINT32_(0x04)      /* (WDT_INTENCLR) Interrupt Enable Clear Offset */
+#define WDT_INTENSET_REG_OFST          _UINT32_(0x05)      /* (WDT_INTENSET) Interrupt Enable Set Offset */
+#define WDT_INTFLAG_REG_OFST           _UINT32_(0x06)      /* (WDT_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define WDT_SYNCBUSY_REG_OFST          _UINT32_(0x08)      /* (WDT_SYNCBUSY) Synchronization Busy Offset */
+#define WDT_CLEAR_REG_OFST             _UINT32_(0x0C)      /* (WDT_CLEAR) Clear Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* WDT register API structure */
+typedef struct
+{  /* Watchdog Timer */
+  __IO  uint8_t                        WDT_CTRLA;          /* Offset: 0x00 (R/W  8) Control */
+  __IO  uint8_t                        WDT_CONFIG;         /* Offset: 0x01 (R/W  8) Configuration */
+  __IO  uint8_t                        WDT_EWCTRL;         /* Offset: 0x02 (R/W  8) Early Warning Interrupt Control */
+  __I   uint8_t                        Reserved1[0x01];
+  __IO  uint8_t                        WDT_INTENCLR;       /* Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO  uint8_t                        WDT_INTENSET;       /* Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO  uint8_t                        WDT_INTFLAG;        /* Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __I   uint32_t                       WDT_SYNCBUSY;       /* Offset: 0x08 (R/   32) Synchronization Busy */
+  __O   uint8_t                        WDT_CLEAR;          /* Offset: 0x0C ( /W  8) Clear */
+} wdt_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _PIC32CMGC00_WDT_COMPONENT_H_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ac.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ac.h
new file mode 100644
index 00000000..5a8785d4
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ac.h
@@ -0,0 +1,42 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_AC_INSTANCE_
+#define _PIC32CMGC00_AC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for AC peripheral ========== */
+#define AC_ATEST_IMPLEMENTED                     (1)        /* Defines if the ATEST register is implemented */
+#define AC_ATEST_SIZE                            (2)        /* Defines the number of effective bits in ATEST register */
+#define AC_BRIDGE_ID                             (1)        /* H2PB Bridge ID */
+#define AC_DACVALUE_BIT                          (7)        /* Defines the number of bits in DACCTRLn.VALUE */
+#define AC_GCLK_ID                               (34)       
+#define AC_INSTANCE_ID                           (40)       /* Instance index for AC */
+#define AC_IO_INPUTS                             (4)        /* Defines the number of AC pair inputs connected to IO pins */
+#define AC_LOAD_CALIB                            (0)        /* Defines if calibration is required */
+#define AC_MCLK_ID_APB                           (50)       /* Index for AC APB clock */
+#define AC_NUM_CMP                               (2)        /* Number of comparators */
+#define AC_PAC_ID                                (40)       /* Index for AC registers write protection */
+#define AC_PAIRS                                 (1)        /* Defines the number of AC pairs */
+#define AC_PERIPH_ID                             (21)       /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_AC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/adc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/adc.h
new file mode 100644
index 00000000..0b4b178a
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/adc.h
@@ -0,0 +1,50 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_ADC_INSTANCE_
+#define _PIC32CMGC00_ADC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for ADC peripheral ========== */
+#define ADC_APB_FIFO_DEPTH                       (16)       /* -- */
+#define ADC_BRIDGE_ID                            (1)        /* H2PB Bridge ID */
+#define ADC_CHNSAR_NMBR1                         (16)       /* -- */
+#define ADC_CHNSAR_NMBR2                         (0)        /* -- */
+#define ADC_CHNSAR_NMBR3                         (0)        /* -- */
+#define ADC_CHNSAR_NMBR4                         (0)        /* -- */
+#define ADC_DCMP_NMBR                            (1)        /* -- */
+#define ADC_DMAC_ID_PFFRDY                       (37)       
+#define ADC_EARLY_INTR_PRESENT                   (1)        /* -- */
+#define ADC_FLTR_NMBR                            (1)        /* -- */
+#define ADC_GCLK_ID                              (33)       
+#define ADC_INSTANCE_ID                          (39)       /* Instance index for ADC */
+#define ADC_MCLK_ID_APB                          (49)       /* Index for ADC APB clock */
+#define ADC_OCP_ADDR_WIDTH                       (0)        /* -- */
+#define ADC_OCP_FIFO_DEPTH                       (0)        /* -- */
+#define ADC_OCP_PORT_PRESENT                     (0)        /* -- */
+#define ADC_PAC_ID                               (39)       /* Index for ADC registers write protection */
+#define ADC_PERIPH_ID                            (12)       /* H2PB Peripheral ID */
+#define ADC_SARCORE_NMBR                         (1)        /* -- */
+#define ADC_TRGS_NMBR                            (16)       /* -- */
+#define ADC_VREF_STARTUP_TIME                    (50)       /* -- */
+
+#endif /* _PIC32CMGC00_ADC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/at.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/at.h
new file mode 100644
index 00000000..9cbb93b4
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/at.h
@@ -0,0 +1,38 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_AT_INSTANCE_
+#define _PIC32CMGC00_AT_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for AT peripheral ========== */
+#define AT_CTRLAPRIV_IMPLEMENTED                 (1)        /* Implement the CTRLA.PRIV bit and privilege access filtering to registers.0 = CTRLA.PRIV not implemented1 = CTRLA.PRIV implemented */
+#define AT_TMPR_OSC_NUM_INV                      (881)      /* Number of inverters in tamper oscillator */
+#define AT_WPCTRL_IMPLEMENTED                    (0)        /* Implement the WPCTRL register for write protection. 1 = Use WPCTRL register is preset . Used to control write protection enable/disable. 0 = No WPCTRL sfr, only used in legacy device with a PACUse at_wrprot to control write protection enable/disable */
+#define AT_WPCTRL_KEY                            (0x412054) /* WPCTRL 24-bit key value. See register description for usage.Set to a unique value for each macro. ASCII of "A T" */
+#define AT_BRIDGE_ID                             (2)        /* H2PB Bridge ID */
+#define AT_INSTANCE_ID                           (45)       /* Instance index for AT */
+#define AT_MCLK_ID_APB                           (56)       /* Index for AT APB clock */
+#define AT_PAC_ID                                (45)       /* Index for AT registers write protection */
+#define AT_PERIPH_ID                             (6)        /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_AT_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/bromc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/bromc.h
new file mode 100644
index 00000000..ab1a9605
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/bromc.h
@@ -0,0 +1,56 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_BROMC_INSTANCE_
+#define _PIC32CMGC00_BROMC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for BROMC peripheral ========== */
+#define BROMC_BRIDGE_ID                          (1)        /* H2PB Bridge ID */
+#define BROMC_BOOTCRC_MODE                       (2)        /* -- */
+#define BROMC_CTRLAPRIV_IMPLEMENTED              (1)        /* -- */
+#define BROMC_FUSES_DATA_MSB                     (127)      /* See Flash Control Chapter for Values */
+#define BROMC_FUSES_RDY_MSB                      (14)       /* See Flash Control Chapter for Values */
+#define BROMC_FUSES_UCFG_ROWID                   (14)       /* See Chapter 5 CCFG Fuse map for Values */
+#define BROMC_FUSES_UCFG_START                   (0)        /* See Chapter 5 CCFG Fuse map for Values */
+#define BROMC_NUM_COOLDN_CYCLES                  (2)        /* -- */
+#define BROMC_NUM_WARMUP_CYCLES                  (2)        /* -- */
+#define BROMC_PADDR_MSB                          (12)       /* -- */
+#define BROMC_PDATA_MSB                          (31)       /* -- */
+#define BROMC_PPROT_MSB                          (5)        /* -- */
+#define BROMC_PSTRB_MSB                          (3)        /* -- */
+#define BROMC_ROM_ADDR_MSB                       (13)       /* -- */
+#define BROMC_ROM_CRC_EN                         (1)        /* -- */
+#define BROMC_ROM_DATA_MSB                       (31)       /* -- */
+#define BROMC_ROM_DATA_SIZE                      (16384)    /* -- */
+#define BROMC_ROM_KEN                            (0)        /* -- */
+#define BROMC_ROM_PRMWS_DEFAULT                  (0)        /* -- */
+#define BROMC_ROM_SPLIT                          (0x3400)   /* (8K for PK code)  (Note: This parameter may change once boot and PK code sizes are known) */
+#define BROMC_WPCTRL_IMPLEMENTED                 (0)        /* -- */
+#define BROMC_WPCTRL_KEY                         (0x42524F) /* -- */
+#define BROMC_INSTANCE_ID                        (23)       /* Instance index for BROMC */
+#define BROMC_MCLK_ID_AHB                        (32)       /* Index for BROMC AHB clock */
+#define BROMC_MCLK_ID_APB                        (33)       /* Index for BROMC APB clock */
+#define BROMC_PAC_ID                             (23)       /* Index for BROMC registers write protection */
+#define BROMC_PERIPH_ID                          (2)        /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_BROMC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/can0.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/can0.h
new file mode 100644
index 00000000..afd68840
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/can0.h
@@ -0,0 +1,44 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_CAN0_INSTANCE_
+#define _PIC32CMGC00_CAN0_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for CAN0 peripheral ========== */
+#define CAN0_BRIDGE_ID                           (0)        /* H2PB Bridge ID */
+#define CAN0_ECC_ERR_IMPLEMENTED                 (0)        /* ECC error implemented? */
+#define CAN0_GCLK_ID                             (6)        
+#define CAN0_INSTANCE_ID                         (17)       /* Instance index for CAN0 */
+#define CAN0_INTERNAL_TB_SOF                     (3)        /* 0: No SOF and no internal Time base, 1: SOF and no internal Time */
+#define CAN0_MCLK_ID_AHB                         (23)       /* Index for CAN0 AHB clock */
+#define CAN0_MSG_RAM_ADDR                        (0x20)     /* 8-bits MSB */
+#define CAN0_NUMBER_TS                           (1)        /* 0: 4 Timestamp reg, 1: 8 timestamp reg, 2: 16 timestamp reg */
+#define CAN0_PAC_ID                              (17)       /* Index for CAN0 registers write protection */
+#define CAN0_PERIPH_ID                           (23)       /* H2PB Peripheral ID */
+#define CAN0_PRIV_IMPLEMENTED                    (1)        /* Privilege access is implemented? 0: CTRLA.PRIV bit not implemented, 1: CTRLA.PRIV bit implemented */
+#define CAN0_RXD_SYNC_METHOD                     (0)        /* RXD Synchronization Method */
+#define CAN0_SYNT_TIMESTAMP                      (0x00000)  /* CAN_SYNT_TIMESTAMP[19:16]: CREL.YEAR reset value (BCD-coded),CAN_SYNT_TIMESTAMP[15:8]: CREL.MON reset value (BCD-coded), CAN_SYNT_TIMESTAMP[7:0]: CREL.DAY reset value (BCD-coded) */
+#define CAN0_WPCTRL_IMPLEMENTED                  (0)        /* Write protection control register implemented? */
+#define CAN0_WPCTRL_KEY                          (0x43414E) /* Write protection 24 bit key */
+
+#endif /* _PIC32CMGC00_CAN0_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/can1.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/can1.h
new file mode 100644
index 00000000..19f2f714
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/can1.h
@@ -0,0 +1,44 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_CAN1_INSTANCE_
+#define _PIC32CMGC00_CAN1_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for CAN1 peripheral ========== */
+#define CAN1_BRIDGE_ID                           (0)        /* H2PB Bridge ID */
+#define CAN1_ECC_ERR_IMPLEMENTED                 (0)        /* ECC error implemented? */
+#define CAN1_GCLK_ID                             (7)        
+#define CAN1_INSTANCE_ID                         (18)       /* Instance index for CAN1 */
+#define CAN1_INTERNAL_TB_SOF                     (3)        /* 0: No SOF and no internal Time base, 1: SOF and no internal Time */
+#define CAN1_MCLK_ID_AHB                         (24)       /* Index for CAN1 AHB clock */
+#define CAN1_MSG_RAM_ADDR                        (0x20)     /* 8-bits MSB */
+#define CAN1_NUMBER_TS                           (1)        /* 0: 4 Timestamp reg, 1: 8 timestamp reg, 2: 16 timestamp reg */
+#define CAN1_PAC_ID                              (18)       /* Index for CAN1 registers write protection */
+#define CAN1_PERIPH_ID                           (24)       /* H2PB Peripheral ID */
+#define CAN1_PRIV_IMPLEMENTED                    (1)        /* Privilege access is implemented? 0: CTRLA.PRIV bit not implemented, 1: CTRLA.PRIV bit implemented */
+#define CAN1_RXD_SYNC_METHOD                     (0)        /* RXD Synchronization Method */
+#define CAN1_SYNT_TIMESTAMP                      (0x00000)  /* CAN_SYNT_TIMESTAMP[19:16]: CREL.YEAR reset value (BCD-coded),CAN_SYNT_TIMESTAMP[15:8]: CREL.MON reset value (BCD-coded), CAN_SYNT_TIMESTAMP[7:0]: CREL.DAY reset value (BCD-coded) */
+#define CAN1_WPCTRL_IMPLEMENTED                  (0)        /* Write protection control register implemented? */
+#define CAN1_WPCTRL_KEY                          (0x43414E) /* Write protection 24 bit key */
+
+#endif /* _PIC32CMGC00_CAN1_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ccl0.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ccl0.h
new file mode 100644
index 00000000..a441c0f9
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ccl0.h
@@ -0,0 +1,36 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_CCL0_INSTANCE_
+#define _PIC32CMGC00_CCL0_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for CCL0 peripheral ========== */
+#define CCL0_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define CCL0_GCLK_ID                             (36)       
+#define CCL0_INSTANCE_ID                         (42)       /* Instance index for CCL0 */
+#define CCL0_LUT_NUM                             (4)        /* Number of LUT in a CCL */
+#define CCL0_MCLK_ID_APB                         (52)       /* Index for CCL0 APB clock */
+#define CCL0_PAC_ID                              (42)       /* Index for CCL0 registers write protection */
+#define CCL0_PERIPH_ID                           (23)       /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_CCL0_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ccl1.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ccl1.h
new file mode 100644
index 00000000..700f9bb4
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ccl1.h
@@ -0,0 +1,36 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_CCL1_INSTANCE_
+#define _PIC32CMGC00_CCL1_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for CCL1 peripheral ========== */
+#define CCL1_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define CCL1_GCLK_ID                             (37)       
+#define CCL1_INSTANCE_ID                         (43)       /* Instance index for CCL1 */
+#define CCL1_LUT_NUM                             (4)        /* Number of LUT in a CCL */
+#define CCL1_MCLK_ID_APB                         (53)       /* Index for CCL1 APB clock */
+#define CCL1_PAC_ID                              (43)       /* Index for CCL1 registers write protection */
+#define CCL1_PERIPH_ID                           (24)       /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_CCL1_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/dmac.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/dmac.h
new file mode 100644
index 00000000..950bc2f3
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/dmac.h
@@ -0,0 +1,44 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_DMAC_INSTANCE_
+#define _PIC32CMGC00_DMAC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for DMAC peripheral ========== */
+#define DMAC_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define DMAC_CH_NUM                              (8)        /* -- */
+#define DMAC_EVIN_NUM                            (4)        /* -- */
+#define DMAC_EVOUT_NUM                           (4)        /* -- */
+#define DMAC_INSTANCE_ID                         (21)       /* Instance index for DMAC */
+#define DMAC_LVL_NUM                             (4)        /* -- */
+#define DMAC_MCLK_ID_AHB                         (28)       /* Index for DMAC AHB clock */
+#define DMAC_MCLK_ID_APB                         (29)       /* Index for DMAC APB clock */
+#define DMAC_PAC_ID                              (21)       /* Index for DMAC registers write protection */
+#define DMAC_PERIPH_ID                           (1)        /* H2PB Peripheral ID */
+#define DMAC_QOSCTRL_D_RESETVALUE                (2)        /* -- */
+#define DMAC_QOSCTRL_F_RESETVALUE                (2)        /* -- */
+#define DMAC_QOSCTRL_WRB_RESETVALUE              (2)        /* -- */
+#define DMAC_SPLIT_IRQ_NUM                       (4)        /* -- */
+#define DMAC_TRIG_NUM                            (43)       /* -- */
+
+#endif /* _PIC32CMGC00_DMAC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/dsu.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/dsu.h
new file mode 100644
index 00000000..b085ba42
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/dsu.h
@@ -0,0 +1,71 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_DSU_INSTANCE_
+#define _PIC32CMGC00_DSU_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for DSU peripheral ========== */
+#define DSU_BRIDGE_ID                            (0)        /* H2PB Bridge ID */
+#define DSU_DMAC_ID_DCC0                         (1)        
+#define DSU_DMAC_ID_DCC1                         (2)        
+#define DSU_BASE_ADDR_INTERNAL                   (0x44000000) /* -- */
+#define DSU_BRCTRL_KEY                           (0x445355) /* -- */
+#define DSU_CORESIGHT_REVISION                   (0x0)      /* -- */
+#define DSU_CPU_NUM                              (0)        /* -- */
+#define DSU_CTRLAPRIV_IMPLEMENTED                (1)        /* -- */
+#define DSU_CTRLB_IMPLEMENTED_MASK               (0x00000000) /* -- */
+#define DSU_DAL1_VAL                             (0x55)     /* -- */
+#define DSU_DAL2_VAL                             (0xAA)     /* -- */
+#define DSU_FUSES_DATA_MSB                       (127)      /* 128-bit bus */
+#define DSU_FUSES_ID_DEVID_ROWID                 (8)        /* DEVID on RowID Index = 8 */
+#define DSU_FUSES_ID_DEVID_SIZE                  (8)        /* -- */
+#define DSU_FUSES_ID_DEVID_START                 (24)       /* DEVID field is DSUCFG0[31:24] */
+#define DSU_FUSES_RDY_MSB                        (14)       /* 15 bit fuse ready bus */
+#define DSU_ID_MASKID                            (0x00)     /* Microchip Device Mask ID which provides the value for bits [15:8] of the ID - Part Number. */
+#define DSU_ID_VER                               (0x0)      /* ID Version Code provides the Mask Revision value for the device. Use metal changeable cells to configure this value. */
+#define DSU_PRVKEY_IMPLEMENTED                   (0)        /* key sourced by PUF, not DSU */
+#define DSU_SD_KEY                               (0xFFABAFD0) /* -- */
+#define DSU_SWCCS_IMPLEMENTED                    (1)        /* -- */
+#define DSU_TDID_DIE                             (0x00)     /* -- */
+#define DSU_TDID_MASK                            (0x00)     /* -- */
+#define DSU_TZ_IMPLEMENTED                       (1)        /* -- */
+#define DSU_WPCTRL_IMPLEMENTED                   (0)        /* -- */
+#define DSU_WPCTRL_KEY                           (0x445355) /* -- */
+#define DSU_INSTANCE_ID                          (0)        /* Instance index for DSU */
+#define DSU_MCLK_ID_AHB                          (0)        /* Index for DSU AHB clock */
+#define DSU_PAC_ID                               (0)        /* Index for DSU registers write protection */
+#define DSU_PERIPH_ID                            (0)        /* H2PB Peripheral ID */
+
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#define DSU_CORESIGHT_ENTRY                      { 0xE00FF001, 0x0, 0x0, 0x0 } /* -- */
+#define DSU_DCFG_MASK                            { 0xFF0FFF0F, 0x10FC7F80, 0xC0800203, 0x0, 0x0, 0x0, 0x0, 0x0 } /* -- */
+#define DSU_FUSES_DCFG_ROWID                     { 8, 8, 8, 8, 9, 9, 9, 9 } /* DSUCFG7-0 = FCCFG39-32 */
+#define DSU_FUSES_DCFG_SIZE                      { 32, 32, 32, 32, 32, 32, 32, 32 } /* -- */
+#define DSU_FUSES_DCFG_START                     { 0, 32, 64, 96, 0, 32, 64, 96 } /* -- */
+#define DSU_TESTMODE_IMPLEMENTED_MASK            { 0x000007FF, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+
+#endif /* _PIC32CMGC00_DSU_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/eic.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/eic.h
new file mode 100644
index 00000000..74010da7
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/eic.h
@@ -0,0 +1,39 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_EIC_INSTANCE_
+#define _PIC32CMGC00_EIC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for EIC peripheral ========== */
+#define EIC_BRIDGE_ID                            (0)        /* H2PB Bridge ID */
+#define EIC_EXTINT_NUM                           (16)       /* -- */
+#define EIC_GCLK_ID                              (5)        
+#define EIC_INSTANCE_ID                          (13)       /* Instance index for EIC */
+#define EIC_MCLK_ID_APB                          (13)       /* Index for EIC APB clock */
+#define EIC_NUMBER_OF_CONFIG_REGS                (2)        /* =(EIC_EXTINT_NUM +7) / 8 */
+#define EIC_NUMBER_OF_INTERRUPTS                 (16)       /* =(EIC_EXTINT_NUM) */
+#define EIC_PAC_ID                               (13)       /* Index for EIC registers write protection */
+#define EIC_PERIPH_ID                            (16)       /* H2PB Peripheral ID */
+#define EIC_SECURE_IMPLEMENTED                   (1)        /* -- */
+
+#endif /* _PIC32CMGC00_EIC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/evsys.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/evsys.h
new file mode 100644
index 00000000..eed9a57f
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/evsys.h
@@ -0,0 +1,58 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_EVSYS_INSTANCE_
+#define _PIC32CMGC00_EVSYS_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for EVSYS peripheral ========== */
+#define EVSYS_ASYNCHRONOUS_CHANNELS              (0xFFFFF000) /* -- */
+#define EVSYS_BRIDGE_ID                          (1)        /* H2PB Bridge ID */
+#define EVSYS_CHANNELS                           (12)       /* -- */
+#define EVSYS_CHANNELS_BITS                      (4)        /* =LEN( BIN(EVSYS_CHANNELS-1)) - 2)derived parameter */
+#define EVSYS_GCLK_ID_CH0                        (8)        
+#define EVSYS_GCLK_ID_CH1                        (9)        
+#define EVSYS_GCLK_ID_CH10                       (18)       
+#define EVSYS_GCLK_ID_CH11                       (19)       
+#define EVSYS_GCLK_ID_CH2                        (10)       
+#define EVSYS_GCLK_ID_CH3                        (11)       
+#define EVSYS_GCLK_ID_CH4                        (12)       
+#define EVSYS_GCLK_ID_CH5                        (13)       
+#define EVSYS_GCLK_ID_CH6                        (14)       
+#define EVSYS_GCLK_ID_CH7                        (15)       
+#define EVSYS_GCLK_ID_CH8                        (16)       
+#define EVSYS_GCLK_ID_CH9                        (17)       
+#define EVSYS_GENERATORS                         (90)       /* Should be 90 */
+#define EVSYS_GENERATORS_BITS                    (7)        /* =LEN( BIN(EVSYS_GENERATORS-1)) - 2)derived parameter */
+#define EVSYS_INSTANCE_ID                        (25)       /* Instance index for EVSYS */
+#define EVSYS_MCLK_ID_APB                        (35)       /* Index for EVSYS APB clock */
+#define EVSYS_PAC_ID                             (25)       /* Index for EVSYS registers write protection */
+#define EVSYS_PERIPH_ID                          (3)        /* H2PB Peripheral ID */
+#define EVSYS_SECURE_IMPLEMENTED                 (0)        /* -- */
+#define EVSYS_SPLIT_IRQ_NUM                      (12)       /* -- */
+#define EVSYS_SYNCH_NUM                          (12)       /* -- */
+#define EVSYS_SYNCH_NUM_BITS                     (4)        /* =LEN( BIN(EVSYS_SYNCH_NUM-1)) - 2)derived parameter */
+#define EVSYS_USERS                              (62)       /* Should be 62 */
+#define EVSYS_USERS_BITS                         (6)        /* =LEN( BIN(EVSYS_USERS-1)) - 2)derived parameter */
+#define EVSYS_USERS_GROUPS                       (2)        /* =(EVSYS_USERS+31) / 32derived parameter */
+
+#endif /* _PIC32CMGC00_EVSYS_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/fcr.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/fcr.h
new file mode 100644
index 00000000..b2640f4e
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/fcr.h
@@ -0,0 +1,101 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_FCR_INSTANCE_
+#define _PIC32CMGC00_FCR_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for FCR peripheral ========== */
+#define FCR_BFM_PNL_ADDR_MSB                     (13)       /* -- */
+#define FCR_BFM_SYS_ADDR_MSB                     (13)       /* -- */
+#define FCR_BRIDGE_ID                            (0)        /* H2PB Bridge ID */
+#define FCR_CFM_PNL_ADDR_MSB                     (14)       /* -- */
+#define FCR_CFM_SYS_ADDR_MSB                     (14)       /* -- */
+#define FCR_AHB_PORTS_NB                         (1)        /* -- */
+#define FCR_BFM_ADDR_BASE                        (0x08000000) /* -- */
+#define FCR_CAL_ADDR                             (0x0A007080) /* -- */
+#define FCR_CAL_NUM_READS                        (14)       /* -- */
+#define FCR_CFM_ADDR_BASE                        (0x0A000000) /* -- */
+#define FCR_CRC_PRESENT                          (1)        /* -- */
+#define FCR_CTRLAPRIV_IMPLEMENTED                (1)        /* -- */
+#define FCR_ECC_PRESENT                          (1)        /* -- */
+#define FCR_F1RR_ADDR                            (0x0A007000) /* -- */
+#define FCR_F2RR_ADDR                            (0)        /* Not applicable for QSilver */
+#define FCR_FCD_ADDR_BASE                        (0x0B000000) /* -- */
+#define FCR_FFF_ADDR                             (0x0A007040) /* -- */
+#define FCR_FLT_PRESENT                          (1)        /* -- */
+#define FCR_FUSES_DATA_CYCLES                    (4)        /* -- */
+#define FCR_FUSES_READY_CYCLES                   (2)        /* -- */
+#define FCR_HDATA_SIZE                           (32)       /* -- */
+#define FCR_INTFLAGSET_IMPLEMENTED               (1)        /* -- */
+#define FCR_NOT_FFF_VALUE                        (0xA5A5A5A5) /* -- */
+#define FCR_NUM_RR_SFR                           (1)        /* -- */
+#define FCR_OTPLOCK_ADDR                         (0x0A007060) /* -- */
+#define FCR_PBUCFG_ADDR                          (0x0A003400) /* -- */
+#define FCR_PCHE_AHB_NUM                         (0)        /* -- */
+#define FCR_PCHE_NUM_LINES                       (4)        /* -- */
+#define FCR_PCHE_PRESENT                         (1)        /* -- */
+#define FCR_PCHE_TAG_MASK                        (0xF9F8000F) /* -- */
+#define FCR_PDMO_MSB                             (7)        /* -- */
+#define FCR_PERIOD_MIN                           (75)       /* -- */
+#define FCR_PERIOD_NOM                           (116)      /* -- */
+#define FCR_PFM_ADDR_BASE                        (0x0C000000) /* -- */
+#define FCR_RR_NUM_READS                         (1)        /* -- */
+#define FCR_TCALH_NS                             (10000)    /* -- */
+#define FCR_VSS_CFG0_BASE                        (0x0A004000) /* -- */
+#define FCR_VSS_CFG1_BASE                        (0x0A005000) /* -- */
+#define FCR_VSS_CFG2_BASE                        (0)        /* -- */
+#define FCR_VSS_CFG3_BASE                        (0)        /* -- */
+#define FCR_VSS_CFG4_BASE                        (0)        /* -- */
+#define FCR_VSS_CFG5_BASE                        (0)        /* -- */
+#define FCR_WPCTRL_IMPLEMENTED                   (0)        /* -- */
+#define FCR_WPCTRL_KEY                           (0x464352) /* -- */
+#define FCR_FUSES_DATA_MSB                       (127)      /* -- */
+#define FCR_FUSES_RDY_MSB                        (14)       /* -- */
+#define FCR_INSTANCE_ID                          (1)        /* Instance index for FCR */
+#define FCR_MCLK_ID_AHB                          (1)        /* Index for FCR AHB clock */
+#define FCR_NVR_NUM_PAGES                        (12)       /* -- */
+#define FCR_PAC_ID                               (1)        /* Index for FCR registers write protection */
+#define FCR_PERIPH_ID                            (1)        /* H2PB Peripheral ID */
+#define FCR_PFM_ACC_HT_NS                        (30)       /* -- */
+#define FCR_PFM_ACC_NS                           (25)       /* -- */
+#define FCR_PFM_ACC_RECALL_NS                    (70)       /* -- */
+#define FCR_PFM_DATA_MSB                         (127)      /* -- */
+#define FCR_PFM_NUM_PANELS                       (1)        /* -- */
+#define FCR_PFM_NUM_RR                           (2)        /* -- */
+#define FCR_PFM_PAGE_ADDR_MSB                    (11)       /* -- */
+#define FCR_PFM_PNL_ADDR_MSB                     (18)       /* -- */
+#define FCR_PFM_PNL_DATA_MSB                     (139)      /* -- */
+#define FCR_PFM_PNL_WDATA_MSB                    (34)       /* Parameter only in DOS Rev C, not in RTL */
+#define FCR_PFM_ROW_ADDR_MSB                     (9)        /* -- */
+#define FCR_PFM_SRHT_PRESENT                     (0)        /* -- */
+#define FCR_PFM_SYS_ADDR_MSB                     (18)       /* -- */
+#define FCR_PFM_TDPDH_NS                         (5000)     /* -- */
+#define FCR_PFM_TDPDS_NS                         (100)      /* -- */
+#define FCR_PFM_TLKCFG_NS                        (1000)     /* -- */
+#define FCR_PFM_TMH_NS                           (100)      /* See Note 2 */
+#define FCR_PFM_TMS_NS                           (5000)     /* See Note 2 */
+#define FCR_PFM_TONWAIT_NS                       (6000)     /* -- */
+#define FCR_PFM_TRHR_NS                          (1000)     /* -- */
+#define FCR_PFM_TRT_NS                           (500)      /* -- */
+
+#endif /* _PIC32CMGC00_FCR_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/fcw.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/fcw.h
new file mode 100644
index 00000000..dd75792b
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/fcw.h
@@ -0,0 +1,92 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_FCW_INSTANCE_
+#define _PIC32CMGC00_FCW_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for FCW peripheral ========== */
+#define FCW_BFM_PNL_ADDR_MSB                     (13)       /* -- */
+#define FCW_BFM_SYS_ADDR_MSB                     (13)       /* -- */
+#define FCW_BRIDGE_ID                            (0)        /* H2PB Bridge ID */
+#define FCW_CFM_PNL_ADDR_MSB                     (14)       /* -- */
+#define FCW_CFM_SYS_ADDR_MSB                     (14)       /* -- */
+#define FCW_BFM_ADDR_BASE                        (0x08000000) /* -- */
+#define FCW_CFM_ADDR_BASE                        (0x0A000000) /* -- */
+#define FCW_CTRLAPRIV_IMPLEMENTED                (1)        /* -- */
+#define FCW_INTFLAGSET_IMPLEMENTED               (1)        /* -- */
+#define FCW_NUM_DATA_SFR                         (4)        /* (PFM_DATA_MSB+1)/32 */
+#define FCW_PERIOD_MIN                           (75)       /* -- */
+#define FCW_PERIOD_NOM                           (116)      /* -- */
+#define FCW_PFM_ADDR_BASE                        (0x0C000000) /* -- */
+#define FCW_PWP_MSB                              (6)        /* -- */
+#define FCW_PWP_REGIONS                          (4)        /* -- */
+#define FCW_SD_USE_CPCNT                         (1)        /* -- */
+#define FCW_TAMPER_ADDR                          (0x0A003200) /* -- */
+#define FCW_TAMPER_DATA                          (0x00000000) /* -- */
+#define FCW_TAMPER_PRESENT                       (1)        /* -- */
+#define FCW_TPAR_MSB                             (3)        /* (PFM_PNL_DATA_MSB - PFM_DATA_MSB)/4 */
+#define FCW_VSS_CFG0_BASE                        (0x0A004000) /* -- */
+#define FCW_VSS_CFG1_BASE                        (0x0A005000) /* -- */
+#define FCW_VSS_CFG2_BASE                        (0)        /* Not applicable for QS */
+#define FCW_VSS_CFG3_BASE                        (0)        /* Not applicable for QS */
+#define FCW_VSS_CFG4_BASE                        (0)        /* Not applicable for QS */
+#define FCW_VSS_CFG5_BASE                        (0)        /* Not applicable for QS */
+#define FCW_WPCTRL_IMPLEMENTED                   (0)        /* -- */
+#define FCW_WPCTRL_KEY                           (0x464357) /* -- */
+#define FCW_FLASH_SIZE                           (524288)   
+#define FCW_INSTANCE_ID                          (2)        /* Instance index for FCW */
+#define FCW_MCLK_ID_AHB                          (2)        /* Index for FCW AHB clock */
+#define FCW_NVR_NUM_PAGES                        (12)       /* -- */
+#define FCW_PAC_ID                               (2)        /* Index for FCW registers write protection */
+#define FCW_PERIPH_ID                            (2)        /* H2PB Peripheral ID */
+#define FCW_PFM_DATA_MSB                         (127)      /* -- */
+#define FCW_PFM_NUM_PANELS                       (1)        /* -- */
+#define FCW_PFM_NUM_RR                           (2)        /* -- */
+#define FCW_PFM_PAGE_ADDR_MSB                    (11)       /* -- */
+#define FCW_PFM_PNL_ADDR_MSB                     (18)       /* -- */
+#define FCW_PFM_PNL_DATA_MSB                     (139)      /* -- */
+#define FCW_PFM_ROW_ADDR_MSB                     (9)        /* -- */
+#define FCW_PFM_SIZE                             (6)        /* -- */
+#define FCW_PFM_SYS_ADDR_MSB                     (18)       /* -- */
+#define FCW_PFM_TADH_NS                          (15)       /* See Note 2 */
+#define FCW_PFM_TADS_NS                          (15)       /* See Note 2 */
+#define FCW_PFM_TERASE_NS                        (18000000) /* See Note 3 */
+#define FCW_PFM_TERASE_RETRY_NS                  (4500000)  /* See Note 3 */
+#define FCW_PFM_TNVS_NS                          (4000)     /* See Note 2 */
+#define FCW_PFM_TPGH_NS                          (15)       /* See Note 2 */
+#define FCW_PFM_TPGS_NS                          (8000)     /* See Note 2 */
+#define FCW_PFM_TPREPGH_NS                       (15)       /* See Note 2 */
+#define FCW_PFM_TPREPGS_NS                       (1000)     /* See Note 2 */
+#define FCW_PFM_TPREPROG_NS                      (3000)     /* See Note 3 */
+#define FCW_PFM_TPROG_NS                         (18000)    /* See Note 3 */
+#define FCW_PFM_TPUMPENH                         (100)      /* See Note 2 */
+#define FCW_PFM_TPUMPENS                         (1000)     /* See Note 2 */
+#define FCW_PFM_TPUMP_CYCLES                     (1029)     /* See Note 2 */
+#define FCW_PFM_TRCV_ERASE_NS                    (50000)    /* See Note 2 */
+#define FCW_PFM_TRCV_PROG_NS                     (5000)     /* See Note 2 */
+#define FCW_PFM_TRW_NS                           (100)      /* See Note 2 */
+#define FCW_PFM_TSCE_NS                          (18000000) /* See Note 3 */
+#define FCW_PFM_TWH_NS                           (5)        /* value irrelevant, must be >0 */
+#define FCW_PFM_TWS_NS                           (5)        /* value irrelevant, must be >0 */
+
+#endif /* _PIC32CMGC00_FCW_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/freqm.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/freqm.h
new file mode 100644
index 00000000..90116eaf
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/freqm.h
@@ -0,0 +1,38 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_FREQM_INSTANCE_
+#define _PIC32CMGC00_FREQM_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for FREQM peripheral ========== */
+#define FREQM_BRIDGE_ID                          (0)        /* H2PB Bridge ID */
+#define FREQM_GCLK_ID_MSR0                       (2)        
+#define FREQM_GCLK_ID_MSR1                       (3)        
+#define FREQM_GCLK_ID_REF                        (4)        
+#define FREQM_INSTANCE_ID                        (10)       /* Instance index for FREQM */
+#define FREQM_MCLK_ID_APB                        (10)       /* Index for FREQM APB clock */
+#define FREQM_MSRCLK_NB                          (2)        /* Number of measured clock sources */
+#define FREQM_PAC_ID                             (10)       /* Index for FREQM registers write protection */
+#define FREQM_PERIPH_ID                          (6)        /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_FREQM_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/fuses.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/fuses.h
new file mode 100644
index 00000000..19b5bea9
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/fuses.h
@@ -0,0 +1,26 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_FUSES_INSTANCE_
+#define _PIC32CMGC00_FUSES_INSTANCE_
+
+#endif /* _PIC32CMGC00_FUSES_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/gclk.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/gclk.h
new file mode 100644
index 00000000..ab5f7ed5
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/gclk.h
@@ -0,0 +1,38 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_GCLK_INSTANCE_
+#define _PIC32CMGC00_GCLK_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for GCLK peripheral ========== */
+#define GCLK_BRIDGE_ID                           (0)        /* H2PB Bridge ID */
+#define GCLK_GEN_NUM                             (12)       /* -- */
+#define GCLK_INSTANCE_ID                         (8)        /* Instance index for GCLK */
+#define GCLK_IO_NUM                              (8)        /* derived, # of "1" in GCLK_GEN_IO_EXIST */
+#define GCLK_MCLK_ID_APB                         (8)        /* Index for GCLK APB clock */
+#define GCLK_MUXED_NUM                           (39)       /* Number of GCLK channels */
+#define GCLK_PAC_ID                              (8)        /* Index for GCLK registers write protection */
+#define GCLK_PERIPH_ID                           (4)        /* H2PB Peripheral ID */
+#define GCLK_SOURCE_NUM                          (11)       /* -- */
+
+#endif /* _PIC32CMGC00_GCLK_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/h2pb0.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/h2pb0.h
new file mode 100644
index 00000000..620a99d9
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/h2pb0.h
@@ -0,0 +1,54 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_H2PB0_INSTANCE_
+#define _PIC32CMGC00_H2PB0_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for H2PB0 peripheral ========== */
+#define H2PB0_BRIDGE_ID                          (0)        /* H2PB Bridge ID */
+#define H2PB0_BASE_MSB                           (13)       /* derived parameter */
+#define H2PB0_CLK_DIV_EN                         (0)        /* 1="n:1 clock"0="1:1 clock" */
+#define H2PB0_MST_MAX                            (1)        /* derived parameter */
+#define H2PB0_MST_N                              (2)        /* -- */
+#define H2PB0_NONSEC_INIT_VAL                    (0x00000001) /* -- */
+#define H2PB0_OWN_SFR_SLOT                       (25)       /* -- */
+#define H2PB0_PADDR_IDXB                         (5)        /* derived parameter */
+#define H2PB0_PADDR_LSB                          (13)       /* -- */
+#define H2PB0_PADDR_MSB                          (17)       /* derived local parameter */
+#define H2PB0_PADDR_SIZE                         (18)       /* local parameter */
+#define H2PB0_PAGE_SIZE                          (8192)     /* derived parameter */
+#define H2PB0_SLV_MAX                            (31)       /* derived parameter */
+#define H2PB0_SLV_N                              (32)       /* -- */
+#define H2PB0_USE_DPATH_PIPER                    (0)        /* 1="all pipelined"0="address pipelined" */
+#define H2PB0_USE_EARLY_PREAD                    (0)        /* -- */
+#define H2PB0_USE_HSEL                           (1)        /* -- */
+#define H2PB0_USE_PSTRB_FOR_READS                (1)        /* -- */
+#define H2PB0_WPCTRL_IMPLEMENTED                 (0)        /* -- */
+#define H2PB0_WPCTRL_KEY                         (0x504230) /* -- */
+#define H2PB0_INSTANCE_ID                        (19)       /* Instance index for H2PB0 */
+#define H2PB0_MCLK_ID_AHB                        (25)       /* Index for H2PB0 AHB clock */
+#define H2PB0_MCLK_ID_APB                        (26)       /* Index for H2PB0 APB clock */
+#define H2PB0_PAC_ID                             (19)       /* Index for H2PB0 registers write protection */
+#define H2PB0_PERIPH_ID                          (25)       /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_H2PB0_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/h2pb1.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/h2pb1.h
new file mode 100644
index 00000000..7555caf4
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/h2pb1.h
@@ -0,0 +1,54 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_H2PB1_INSTANCE_
+#define _PIC32CMGC00_H2PB1_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for H2PB1 peripheral ========== */
+#define H2PB1_BRIDGE_ID                          (1)        /* H2PB Bridge ID */
+#define H2PB1_BASE_MSB                           (13)       /* derived parameter */
+#define H2PB1_CLK_DIV_EN                         (0)        /* 1="n:1 clock"0="1:1 clock" */
+#define H2PB1_MST_MAX                            (1)        /* derived parameter */
+#define H2PB1_MST_N                              (2)        /* -- */
+#define H2PB1_NONSEC_INIT_VAL                    (0x00000000) /* -- */
+#define H2PB1_OWN_SFR_SLOT                       (28)       /* -- */
+#define H2PB1_PADDR_IDXB                         (5)        /* derived parameter */
+#define H2PB1_PADDR_LSB                          (13)       /* -- */
+#define H2PB1_PADDR_MSB                          (17)       /* derived local parameter */
+#define H2PB1_PADDR_SIZE                         (18)       /* local parameter */
+#define H2PB1_PAGE_SIZE                          (8192)     /* derived parameter */
+#define H2PB1_SLV_MAX                            (31)       /* derived parameter */
+#define H2PB1_SLV_N                              (32)       /* -- */
+#define H2PB1_USE_DPATH_PIPER                    (0)        /* 1="all pipelined"0="address pipelined" */
+#define H2PB1_USE_EARLY_PREAD                    (0)        /* -- */
+#define H2PB1_USE_HSEL                           (1)        /* -- */
+#define H2PB1_USE_PSTRB_FOR_READS                (1)        /* -- */
+#define H2PB1_WPCTRL_IMPLEMENTED                 (0)        /* -- */
+#define H2PB1_WPCTRL_KEY                         (0x504231) /* -- */
+#define H2PB1_INSTANCE_ID                        (46)       /* Instance index for H2PB1 */
+#define H2PB1_MCLK_ID_AHB                        (57)       /* Index for H2PB1 AHB clock */
+#define H2PB1_MCLK_ID_APB                        (58)       /* Index for H2PB1 APB clock */
+#define H2PB1_PAC_ID                             (46)       /* Index for H2PB1 registers write protection */
+#define H2PB1_PERIPH_ID                          (28)       /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_H2PB1_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/h2pb2.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/h2pb2.h
new file mode 100644
index 00000000..9a201421
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/h2pb2.h
@@ -0,0 +1,54 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_H2PB2_INSTANCE_
+#define _PIC32CMGC00_H2PB2_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for H2PB2 peripheral ========== */
+#define H2PB2_BRIDGE_ID                          (2)        /* H2PB Bridge ID */
+#define H2PB2_BASE_MSB                           (15)       /* derived parameter */
+#define H2PB2_CLK_DIV_EN                         (1)        /* 1="n:1 clock"0="1:1 clock" */
+#define H2PB2_MST_MAX                            (0)        /* derived parameter */
+#define H2PB2_MST_N                              (1)        /* -- */
+#define H2PB2_NONSEC_INIT_VAL                    (0x00)     /* -- */
+#define H2PB2_OWN_SFR_SLOT                       (7)        /* -- */
+#define H2PB2_PADDR_IDXB                         (3)        /* derived parameter */
+#define H2PB2_PADDR_LSB                          (13)       /* -- */
+#define H2PB2_PADDR_MSB                          (15)       /* derived local parameter */
+#define H2PB2_PADDR_SIZE                         (16)       /* local parameter */
+#define H2PB2_PAGE_SIZE                          (8192)     /* derived parameter */
+#define H2PB2_SLV_MAX                            (7)        /* derived parameter */
+#define H2PB2_SLV_N                              (8)        /* -- */
+#define H2PB2_USE_DPATH_PIPER                    (1)        /* 1="all pipelined"0="address pipelined" */
+#define H2PB2_USE_EARLY_PREAD                    (0)        /* -- */
+#define H2PB2_USE_HSEL                           (1)        /* -- */
+#define H2PB2_USE_PSTRB_FOR_READS                (1)        /* -- */
+#define H2PB2_WPCTRL_IMPLEMENTED                 (0)        /* -- */
+#define H2PB2_WPCTRL_KEY                         (0x504232) /* -- */
+#define H2PB2_INSTANCE_ID                        (47)       /* Instance index for H2PB2 */
+#define H2PB2_MCLK_ID_AHB                        (59)       /* Index for H2PB2 AHB clock */
+#define H2PB2_MCLK_ID_APB                        (60)       /* Index for H2PB2 APB clock */
+#define H2PB2_PAC_ID                             (47)       /* Index for H2PB2 registers write protection */
+#define H2PB2_PERIPH_ID                          (7)        /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_H2PB2_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/hmatrix2.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/hmatrix2.h
new file mode 100644
index 00000000..07e7ede9
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/hmatrix2.h
@@ -0,0 +1,35 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_HMATRIX2_INSTANCE_
+#define _PIC32CMGC00_HMATRIX2_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for HMATRIX2 peripheral ========== */
+#define HMATRIX2_BRIDGE_ID                       (0)        /* H2PB Bridge ID */
+#define HMATRIX2_INSTANCE_ID                     (22)       /* Instance index for HMATRIX2 */
+#define HMATRIX2_MCLK_ID_AHB                     (30)       /* Index for HMATRIX2 AHB clock */
+#define HMATRIX2_MCLK_ID_APB                     (31)       /* Index for HMATRIX2 APB clock */
+#define HMATRIX2_PAC_ID                          (22)       /* Index for HMATRIX2 registers write protection */
+#define HMATRIX2_PERIPH_ID                       (8)        /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_HMATRIX2_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/mclk.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/mclk.h
new file mode 100644
index 00000000..091fb7e6
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/mclk.h
@@ -0,0 +1,59 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_MCLK_INSTANCE_
+#define _PIC32CMGC00_MCLK_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for MCLK peripheral ========== */
+#define MCLK_BRIDGE_ID                           (0)        /* H2PB Bridge ID */
+#define MCLK_INSTANCE_ID                         (9)        /* Instance index for MCLK */
+#define MCLK_JTAG_IMPLEMENTED                    (1)        /* -- */
+#define MCLK_CKDIV_REGS_BITS                     (8)        /* -- */
+#define MCLK_CKDIV_WRLOCK                        (0x00000000) /* -- */
+#define MCLK_CLKMSK_NUM                          (65)       /* -- */
+#define MCLK_CPU_CLK_DIVIDER                     (0)        /* -- */
+#define MCLK_CPU_CLK_IDLE                        (0)        /* -- */
+#define MCLK_CPU_CLK_OFFDLY                      (2)        /* -- */
+#define MCLK_CPU_CLK_ONDLY                       (0)        /* -- */
+#define MCLK_DIV_CLK_NUM                         (3)        /* one for all other, one for H2PB2 domain, one for MBISTINTF */
+#define MCLK_ID_APB                              (9)        /* Index for MCLK APB clock */
+#define MCLK_SYNC_EDGES                          (1)        /* -- */
+#define MCLK_SYS_CLK_DIVIDER                     (0)        /* -- */
+#define MCLK_SYS_CLK_OFFDLY                      (2)        /* -- */
+#define MCLK_PAC_ID                              (9)        /* Index for MCLK registers write protection */
+#define MCLK_PERIPH_ID                           (5)        /* H2PB Peripheral ID */
+
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#define MCLK_CKDIV_RESET_VALUE                   { 0x1, 0x2, 0x4, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } /* values must be binary divisor numberunused divisors must be 8'h1 */
+#define MCLK_CKPER_DIVIDER                       { 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } /* -- */
+#define MCLK_CKPER_IMPLEMENTED                   { 0xFFFFFFFF, 0xFFFFFFFF, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define MCLK_CKPER_MASTER                        { 0x11800004, 0x40400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define MCLK_CKPER_REQEXISTS                     { 0xD9FFFFFF, 0xE1FFFFFF, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define MCLK_CKPER_RSTVAL                        { 0xFFEEFFFF, 0xFFFFFFFF, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define MCLK_CKPER_WILLRISE                      { 0x00080000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+
+#endif /* _PIC32CMGC00_MCLK_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/mcramc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/mcramc.h
new file mode 100644
index 00000000..c3c676cf
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/mcramc.h
@@ -0,0 +1,69 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_MCRAMC_INSTANCE_
+#define _PIC32CMGC00_MCRAMC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for MCRAMC peripheral ========== */
+#define MCRAMC_AHB_CLOCK_ENABLE                  (0)        /* -- */
+#define MCRAMC_AHB_ECC                           (1)        /* -- */
+#define MCRAMC_AHB_PORTS_NB                      (8)        /* -- */
+#define MCRAMC_AHB_READ_PREBUFFERING             (0)        /* -- */
+#define MCRAMC_AHB_REQUEST_ISOLATION_REGISTER    (0)        /* -- */
+#define MCRAMC_ARBITRATION_TYPE                  (2)        /* Parameter should be "ENUM_HOPSCOTCH"Fix for text parameter in ConstellationCONST_DEV-1173 */
+#define MCRAMC_BIT_STROBE_RAM                    (0)        /* parameter n/a if STORE_BYTE_STROBE=0 */
+#define MCRAMC_BRIDGE_ID                         (0)        /* H2PB Bridge ID */
+#define MCRAMC_CHANNELS_NB                       (2)        /* -- */
+#define MCRAMC_ECC_SYNDROM_REGISTER              (0)        /* -- */
+#define MCRAMC_HADDR_READ_ISOLATION_REGISTER     (0)        /* -- */
+#define MCRAMC_HRDATA_ISOLATION_CONFIGURABLE     (1)        /* -- */
+#define MCRAMC_HRDATA_ISOLATION_DEFAULT          (0)        /* default to 0 wait states */
+#define MCRAMC_INSTANCE_ID                       (16)       /* Instance index for MCRAMC */
+#define MCRAMC_M0_CLOCK_ENABLE                   (0)        /* -- */
+#define MCRAMC_M0_DATA_SIZE                      (32)       /* -- */
+#define MCRAMC_M0_HYBRID_READ_WRITE_ACCESS       (0)        /* -- */
+#define MCRAMC_M0_PORT_SLICES_NB                 (0)        /* -- */
+#define MCRAMC_MCLK_ID_AHB                       (22)       /* Index for MCRAMC AHB clock */
+#define MCRAMC_MCLK_ID_APB                       (21)       /* Index for MCRAMC APB clock */
+#define MCRAMC_CLK_GATER                         (0)        /* -- */
+#define MCRAMC_PADDR_SIZE                        (13)       /* -- */
+#define MCRAMC_MEMORY_AUTO_CORRECTION            (1)        /* -- */
+#define MCRAMC_MEMORY_ENABLE_POLARITY            (0)        /* -- */
+#define MCRAMC_MW_CLOCK_ENABLE                   (0)        /* -- */
+#define MCRAMC_MW_DATA_SIZE                      (32)       /* -- */
+#define MCRAMC_MW_PORT_SLICES_NB                 (0)        /* -- */
+#define MCRAMC_PAC_ID                            (16)       /* Index for MCRAMC registers write protection */
+#define MCRAMC_PERIPH_ID                         (22)       /* H2PB Peripheral ID */
+#define MCRAMC_PRIVILEGED_BIT_CHECK              (1)        /* -- */
+#define MCRAMC_RAM_ADD_SIZE                      (14)       /* -- */
+#define MCRAMC_RAM_AHB_ADDRESS_OFFSET            (0)        /* -- */
+#define MCRAMC_RAM_ERASE                         (0)        /* -- */
+#define MCRAMC_STORE_BYTE_STROBE                 (0)        /* -- */
+#define MCRAMC_ULTRA                             (1)        /* -- */
+#define MCRAMC_WP_KEY                            (0x465852) /* "FXR" */
+#define MCRAMC_WRITE_ENABLE_POLARITY             (0)        /* -- */
+#define MCRAMC_WRITE_ENABLE_USED                 (1)        /* -- */
+#define MCRAMC_WRITE_MASK_POLARITY               (0)        /* -- */
+#define MCRAMC_WRITE_PROTECT_REGISTER            (0)        /* -- */
+
+#endif /* _PIC32CMGC00_MCRAMC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/osc32kctrl.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/osc32kctrl.h
new file mode 100644
index 00000000..e1456499
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/osc32kctrl.h
@@ -0,0 +1,34 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_OSC32KCTRL_INSTANCE_
+#define _PIC32CMGC00_OSC32KCTRL_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for OSC32KCTRL peripheral ========== */
+#define OSC32KCTRL_BRIDGE_ID                     (2)        /* H2PB Bridge ID */
+#define OSC32KCTRL_INSTANCE_ID                   (7)        /* Instance index for OSC32KCTRL */
+#define OSC32KCTRL_MCLK_ID_APB                   (7)        /* Index for OSC32KCTRL APB clock */
+#define OSC32KCTRL_PAC_ID                        (7)        /* Index for OSC32KCTRL registers write protection */
+#define OSC32KCTRL_PERIPH_ID                     (4)        /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_OSC32KCTRL_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/oscctrl.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/oscctrl.h
new file mode 100644
index 00000000..d060b4f4
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/oscctrl.h
@@ -0,0 +1,52 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_OSCCTRL_INSTANCE_
+#define _PIC32CMGC00_OSCCTRL_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for OSCCTRL peripheral ========== */
+#define OSCCTRL_BRIDGE_ID                        (0)        /* H2PB Bridge ID */
+#define OSCCTRL_DFLL48M_ATEST_IMPLEMENTED        (1)        /* -- */
+#define OSCCTRL_DFLL48M_ATEST_SIZE               (8)        /* -- */
+#define OSCCTRL_DFLL48M_IS_STARTUP_OSCILLATOR    (1)        /* -- */
+#define OSCCTRL_DFLL48M_RC48MCAL0_PORVAL         (0x00000000) /* -- */
+#define OSCCTRL_DIV_8MHZ_NUM                     (2)        /* -- */
+#define OSCCTRL_FRACDIVS_NUM                     (0)        /* -- */
+#define OSCCTRL_FRACDIV_DIVIDER_RESET_VAL        (0)        /* -- */
+#define OSCCTRL_FRACDIV_PLLSRC                   (0)        /* -- */
+#define OSCCTRL_GCLK_ID_DFLL48M                  (0)        
+#define OSCCTRL_GCLK_ID_PLL                      (1)        
+#define OSCCTRL_INSTANCE_ID                      (6)        /* Instance index for OSCCTRL */
+#define OSCCTRL_MCLK_ID_APB                      (6)        /* Index for OSCCTRL APB clock */
+#define OSCCTRL_PAC_ID                           (6)        /* Index for OSCCTRL registers write protection */
+#define OSCCTRL_PERIPH_ID                        (3)        /* H2PB Peripheral ID */
+#define OSCCTRL_PLL0_OUTPUTS_NUM                 (5)        /* -- */
+#define OSCCTRL_PLL1_OUTPUTS_NUM                 (0)        /* -- */
+#define OSCCTRL_PLLS_NUM                         (1)        /* -- */
+#define OSCCTRL_USBHS_NUM                        (1)        /* should be 0, but IP has bug */
+#define OSCCTRL_XOSC_ATEST_IMPLEMENTED           (1)        /* -- */
+#define OSCCTRL_XOSC_ATEST_SIZE                  (4)        /* -- */
+#define OSCCTRL_XOSC_CFD_CLK_SELECT_SIZE         (4)        /* -- */
+#define OSCCTRL_XOSC_CFD_HAS_RETENTION           (0)        /* -- */
+
+#endif /* _PIC32CMGC00_OSCCTRL_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/pac.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/pac.h
new file mode 100644
index 00000000..4140ea76
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/pac.h
@@ -0,0 +1,46 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_PAC_INSTANCE_
+#define _PIC32CMGC00_PAC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for PAC peripheral ========== */
+#define PAC_BRIDGE_ID                            (0)        /* H2PB Bridge ID */
+#define PAC_INSTANCE_ID                          (14)       /* Instance index for PAC */
+#define PAC_MCLK_ID_APB                          (14)       /* Index for PAC APB clock */
+#define PAC_CTRLAPRIV_IMPLEMENTED                (1)        /* -- */
+#define PAC_ERRORS_INBAND                        (1)        /* -- */
+#define PAC_ID                                   (14)       /* Index for PAC registers write protection */
+#define PAC_INTFLAGSET_IMPLEMENTED               (0)        /* -- */
+#define PAC_PERIPH_ID                            (17)       /* H2PB Peripheral ID */
+
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#define PAC_LOCK_RESET_VALUE                     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PAC_PER_WRPROT_MASK                      { 0xFFFFFFFF, 0x0003FFFF, 0x00000000, 0x00000000 } /* Peripheral implemented mask. If PAC_PER_WRPROT_MASK[x]=1 then the PAC implements an SFR bit in INTFLAG, STATUS, and LOCK with the location of <REG>(x/32)[x mod 32] */
+#define PAC_STATUS_RESET_VALUE                   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* WRP STATUS Reset Value for Peripherals. On reset STATUS(x/32)[x mod 32]=PAC_STATUS_RESET_VALUE[x]The reset value for each peripheral should always be 0. The parameter exists if there is an unforeseen circumstance requiring it to be 1. Test blocks are not one of them as they are protected by dsu_test_mode. */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+
+#endif /* _PIC32CMGC00_PAC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/pm.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/pm.h
new file mode 100644
index 00000000..47887cdc
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/pm.h
@@ -0,0 +1,36 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_PM_INSTANCE_
+#define _PIC32CMGC00_PM_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for PM peripheral ========== */
+#define PM_BACKUP_IMPLEMENTED                    (1)        /* -- */
+#define PM_BRIDGE_ID                             (2)        /* H2PB Bridge ID */
+#define PM_INSTANCE_ID                           (3)        /* Instance index for PM */
+#define PM_MCLK_ID_APB                           (3)        /* Index for PM APB clock */
+#define PM_PAC_ID                                (3)        /* Index for PM registers write protection */
+#define PM_PD_NUM                                (1)        /* Number of Switchable Power Domains2 total domains (PD_CORE_SW and PD_CORE_BU) */
+#define PM_PERIPH_ID                             (0)        /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_PM_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/port.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/port.h
new file mode 100644
index 00000000..ba56aa65
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/port.h
@@ -0,0 +1,84 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_PORT_INSTANCE_
+#define _PIC32CMGC00_PORT_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for PORT peripheral ========== */
+#define PORT_AHB_IMPLEMENTED                     (0)        /* No AHB bus */
+#define PORT_BITS                                (117)      /* -- */
+#define PORT_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define PORT_DRVSTR                              (0)        /* No DRVSTR bits */
+#define PORT_EV_NUM                              (4)        /* -- */
+#define PORT_GROUPS                              (4)        /* -- */
+#define PORT_HADDR_MSB                           (31)       /* -- */
+#define PORT_INSTANCE_ID                         (20)       /* Instance index for PORT */
+#define PORT_IOBUS_IMPLEMENTED                   (0)        /* No IOBUS */
+#define PORT_MCLK_ID_APB                         (27)       /* Index for PORT APB clock */
+#define PORT_MSB                                 (116)      /* PORT_BITS-1 */
+#define PORT_ODRAIN                              (1)        /* -- */
+#define PORT_PAC_ID                              (20)       /* Index for PORT registers write protection */
+#define PORT_PERIPH_ID                           (0)        /* H2PB Peripheral ID */
+#define PORT_PPP_IMPLEMENTED                     (0)        /* No IOBUS2 */
+#define PORT_SECURE_IMPLEMENTED                  (1)        /* Mixed Secure Enabled */
+#define PORT_SLEWLIM                             (2)        /* Number of SLEWLIM bit */
+
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#define PORT_DIR_DEFAULT_VAL                     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_DIR_IMPLEMENTED                     { 0x001FFFFF, 0x0003FFFF, 0x000FFFFF, 0x001FFFFF } /* DIR RegistersImplemented */
+#define PORT_DRVSTR1_DEFAULT_VAL                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_DRVSTR1_IMPLEMENTED                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* PINCFG.DRVSTR1RegistersImplemented */
+#define PORT_DRVSTR_DEFAULT_VAL                  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_DRVSTR_IMPLEMENTED                  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* PINCFG.DRVSTR0RegistersImplemented */
+#define PORT_EVENT_IMPLEMENTED                   { 0x001FFFFF, 0x0003FFFF, 0x000FFFFF, 0x001FFFFF } /* Event RegistersImplemented */
+#define PORT_INEN_DEFAULT_VAL                    { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_INEN_IMPLEMENTED                    { 0x001FFFFF, 0x0003FFFF, 0x000FFFFF, 0x001FFFFF } /* PINCFG.INENRegistersImplemented */
+#define PORT_NONSEC_DEFAULT_VAL                  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_NONSEC_IMPLEMENTED                  { 0x001FFFFF, 0x0003FFFF, 0x000FFFFF, 0x001FFFFF } /* NONSECRegistersImplemented */
+#define PORT_ODRAIN_DEFAULT_VAL                  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_ODRAIN_IMPLEMENTED                  { 0x001FFFFF, 0x0003FFFF, 0x000FFFFF, 0x001FFFFF } /* PINCFG.ODRAINRegistersImplemented */
+#define PORT_OUT_DEFAULT_VAL                     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_OUT_IMPLEMENTED                     { 0x001FFFFF, 0x0003FFFF, 0x000FFFFF, 0x001FFFFF } /* OUT RegistersImplemented */
+#define PORT_PIN_IMPLEMENTED                     { 0x001FFFFF, 0x0003FFFF, 0x000FFFFF, 0x001FFFFF } /* Port PinsImplemented */
+#define PORT_PMUXBIT0_DEFAULT_VAL                { 0x00000000, 0x00000000, 0x00000000, 0x0000000C } /* -- */
+#define PORT_PMUXBIT0_IMPLEMENTED                { 0x001FFFFF, 0x0003FFF9, 0x000FFE7F, 0x001FFFC3 } /* Bit 0 of PMUX field */
+#define PORT_PMUXBIT1_DEFAULT_VAL                { 0x00000000, 0x00000000, 0x000001E0, 0x0000000C } /* -- */
+#define PORT_PMUXBIT1_IMPLEMENTED                { 0x0007FFFF, 0x000387F9, 0x000FFE7F, 0x001FFFF3 } /* Bit 1 of PMUX field */
+#define PORT_PMUXBIT2_DEFAULT_VAL                { 0x00000000, 0x00000000, 0x000001E0, 0x0000000C } /* -- */
+#define PORT_PMUXBIT2_IMPLEMENTED                { 0x001BFFFF, 0x00007FF9, 0x0000067F, 0x00003FC3 } /* Bit 2 of PMUX field */
+#define PORT_PMUXBIT3_DEFAULT_VAL                { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_PMUXBIT3_IMPLEMENTED                { 0x001FFFFF, 0x0003FFF9, 0x000BFE7F, 0x001FDFF3 } /* Bit 3 of PMUX field */
+#define PORT_PMUXEN_DEFAULT_VAL                  { 0x00000000, 0x00000000, 0x000001E0, 0x00000000 } /* -- */
+#define PORT_PMUXEN_IMPLEMENTED                  { 0x001FFFFF, 0x0003FFFF, 0x000FFFFF, 0x001FFFFF } /* PINCFG.PMUXEN bit */
+#define PORT_PULLEN_DEFAULT_VAL                  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_PULLEN_IMPLEMENTED                  { 0x001FFFFF, 0x0003FFFF, 0x000FFFFF, 0x001FFFFF } /* PINCFG.PULLENRegistersImplemented */
+#define PORT_SLEWLIM1_DEFAULT_VAL                { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_SLEWLIM1_IMPLEMENTED                { 0x0007C07F, 0x00038078, 0x000FF87F, 0x001FCFC3 } /* PINCFG.SLEWLIM1RegistersImplemented */
+#define PORT_SLEWLIM_DEFAULT_VAL                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } /* -- */
+#define PORT_SLEWLIM_IMPLEMENTED                 { 0x0007C07F, 0x00038078, 0x000FF87F, 0x001FCFC3 } /* PINCFG.SLEWLIM0RegistersImplemented */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+
+#endif /* _PIC32CMGC00_PORT_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ptc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ptc.h
new file mode 100644
index 00000000..ebb8f345
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/ptc.h
@@ -0,0 +1,50 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_PTC_INSTANCE_
+#define _PIC32CMGC00_PTC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for PTC peripheral ========== */
+#define PTC_BRIDGE_ID                            (1)        /* H2PB Bridge ID */
+#define PTC_DMAC_ID_EOC                          (38)       
+#define PTC_DMAC_ID_SEQ                          (39)       
+#define PTC_DMAC_ID_WCOMP                        (40)       
+#define PTC_GCLK_ID                              (35)       
+#define PTC_INSTANCE_ID                          (41)       /* Instance index for PTC */
+#define PTC_MCLK_ID_APB                          (51)       /* Index for PTC APB clock */
+#define PTC_PAC_ID                               (41)       /* Index for PTC registers write protection */
+#define PTC_PERIPH_ID                            (22)       /* H2PB Peripheral ID */
+#define PTC_ATEST_IMPLEMENTED                    (1)        /* Defines if the ATEST register is implemented (1 = implemented) */
+#define PTC_ATEST_SIZE                           (8)        /* Defines the number of effective bits in ATEST register */
+#define PTC_CAL_IMPLEMENTED                      (1)        /* Defines if the CALIB register is implemented (1 = implemented) */
+#define PTC_CAL_PORVAL                           (0x00000000) /* Defines the CALIB register reset value after POR0x00000000 to 0xFFFFFFFF */
+#define PTC_CAL_SIZE                             (16)       /* Defines Bitfield size for CALIB register */
+#define PTC_LINES_NUM                            (36)       /* Number of PTC lines desired (0 to 64) */
+#define PTC_PADDR_MSB                            (12)       /* APB Address Bus Size MSB */
+#define PTC_PADDR_SIZE                           (13)       /* Number of bits of the paddr input busPossible Values = PTC_PADDR_MSB -1 */
+#define PTC_PDATA_MSB                            (31)       /* APB Data Bus Size MSB */
+#define PTC_PRIV_IMPLEMENTED                     (1)        /* Implement the PRIV register for privilege/non-privilege bus accesses.0 = Register not present1 = Register present */
+#define PTC_WPCTRL_IMPLEMENTED                   (0)        /* Implement the WPCTRL register for write protection.0 = Use apb_ptc_wrprot to control write protection enable/disable1 = Use WPCTRL register to control write protection enable/disable. */
+#define PTC_WPCTRL_KEY                           (0x505443) /* WPCTRL 24-bit key value. See register description for usage.Set to a unique value for each macro. */
+
+#endif /* _PIC32CMGC00_PTC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/rstc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/rstc.h
new file mode 100644
index 00000000..1f634c15
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/rstc.h
@@ -0,0 +1,40 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_RSTC_INSTANCE_
+#define _PIC32CMGC00_RSTC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for RSTC peripheral ========== */
+#define RSTC_BACKUP_IMPLEMENTED                  (1)        
+#define RSTC_BRIDGE_ID                           (2)        /* H2PB Bridge ID */
+#define RSTC_CM_DBGRESET_STRETCHED               (3)        /* Reset stretcher size for Cortex CPU related to DBGRESET. */
+#define RSTC_CM_HRESET_N_STRETCHED               (3)        /* Reset stretcher size for Cortex CPU related to HRESETn. */
+#define RSTC_CM_PORESET_STRETCHED                (3)        /* Reset stretcher size for Cortex CPU related to PORESET. */
+#define RSTC_HIB_IMPLEMENTED                     (1)        
+#define RSTC_INSTANCE_ID                         (5)        /* Instance index for RSTC */
+#define RSTC_MCLK_ID_APB                         (5)        /* Index for RSTC APB clock */
+#define RSTC_PAC_ID                              (5)        /* Index for RSTC registers write protection */
+#define RSTC_PERIPH_ID                           (2)        /* H2PB Peripheral ID */
+#define RSTC_VBAT_IMPLEMENTED                    (0)        /* One if VBAT (Battery backup mode) is supported */
+
+#endif /* _PIC32CMGC00_RSTC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/rtc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/rtc.h
new file mode 100644
index 00000000..40dad667
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/rtc.h
@@ -0,0 +1,39 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_RTC_INSTANCE_
+#define _PIC32CMGC00_RTC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for RTC peripheral ========== */
+#define RTC_BRIDGE_ID                            (2)        /* H2PB Bridge ID */
+#define RTC_DMAC_ID_TIMESTAMP                    (3)        
+#define RTC_INSTANCE_ID                          (12)       /* Instance index for RTC */
+#define RTC_MCLK_ID_APB                          (12)       /* Index for RTC APB clock */
+#define RTC_NUM_OF_ALARMS                        (2)        /* -- */
+#define RTC_NUM_OF_BKREGS                        (0)        /* -- */
+#define RTC_NUM_OF_COMP16                        (4)        /* =2 * RTC_NUM_OF_ALARMS */
+#define RTC_NUM_OF_TAMPERS                       (8)        /* -- */
+#define RTC_PAC_ID                               (12)       /* Index for RTC registers write protection */
+#define RTC_PERIPH_ID                            (3)        /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_RTC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom0.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom0.h
new file mode 100644
index 00000000..24b249d5
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom0.h
@@ -0,0 +1,52 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_SERCOM0_INSTANCE_
+#define _PIC32CMGC00_SERCOM0_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for SERCOM0 peripheral ========== */
+#define SERCOM0_BRIDGE_ID                        (1)        /* H2PB Bridge ID */
+#define SERCOM0_CLK_REDUCTION                    (1)        /* Reduce clock options to pin 1 for SPI and USART */
+#define SERCOM0_DMA                              (1)        /* DMA support implemented? */
+#define SERCOM0_DMAC_ID_RX                       (4)        
+#define SERCOM0_DMAC_ID_TX                       (5)        
+#define SERCOM0_FIFO_IMPLEMENTED                 (1)        /* FIFO Rx/Tx implemented? */
+#define SERCOM0_FIFO_SIZE                        (16)       /* Rx-Tx FIFO size in bytes */
+#define SERCOM0_FSYNC_IMPLEMENTED                (1)        /* SPI Frame Synch mode implemented? */
+#define SERCOM0_GCLK_ID_CORE                     (21)       
+#define SERCOM0_GCLK_ID_SLOW                     (20)       
+#define SERCOM0_INSTANCE_ID                      (26)       /* Instance index for SERCOM0 */
+#define SERCOM0_MCLK_ID_APB                      (36)       /* Index for SERCOM0 APB clock */
+#define SERCOM0_PAC_ID                           (26)       /* Index for SERCOM0 registers write protection */
+#define SERCOM0_PERIPH_ID                        (4)        /* H2PB Peripheral ID */
+#define SERCOM0_SPI                              (1)        /* SPI mode implemented? */
+#define SERCOM0_TWIM                             (1)        /* TWI Master mode implemented? */
+#define SERCOM0_TWIS                             (1)        /* TWI Slave mode implemented? */
+#define SERCOM0_ULTRA_IMPLEMENTATION             (0)        /* ULTRA platform compatibility? */
+#define SERCOM0_USART                            (1)        /* USART mode implemented? */
+#define SERCOM0_USART_AUTOBAUD                   (1)        /* USART autobaud implemented? */
+#define SERCOM0_USART_IRDA                       (1)        /* USART IrDA implemented? */
+#define SERCOM0_USART_LIN_MASTER                 (1)        /* USART LIN Master mode implemented? */
+#define SERCOM0_USART_RS485                      (1)        /* USART RS485 mode implemented? */
+
+#endif /* _PIC32CMGC00_SERCOM0_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom1.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom1.h
new file mode 100644
index 00000000..d45beac9
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom1.h
@@ -0,0 +1,52 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_SERCOM1_INSTANCE_
+#define _PIC32CMGC00_SERCOM1_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for SERCOM1 peripheral ========== */
+#define SERCOM1_BRIDGE_ID                        (1)        /* H2PB Bridge ID */
+#define SERCOM1_CLK_REDUCTION                    (1)        /* Reduce clock options to pin 1 for SPI and USART */
+#define SERCOM1_DMA                              (1)        /* DMA support implemented? */
+#define SERCOM1_DMAC_ID_RX                       (6)        
+#define SERCOM1_DMAC_ID_TX                       (7)        
+#define SERCOM1_FIFO_IMPLEMENTED                 (1)        /* FIFO Rx/Tx implemented? */
+#define SERCOM1_FIFO_SIZE                        (16)       /* Rx-Tx FIFO size in bytes */
+#define SERCOM1_FSYNC_IMPLEMENTED                (1)        /* SPI Frame Synch mode implemented? */
+#define SERCOM1_GCLK_ID_CORE                     (22)       
+#define SERCOM1_GCLK_ID_SLOW                     (20)       
+#define SERCOM1_INSTANCE_ID                      (27)       /* Instance index for SERCOM1 */
+#define SERCOM1_MCLK_ID_APB                      (37)       /* Index for SERCOM1 APB clock */
+#define SERCOM1_PAC_ID                           (27)       /* Index for SERCOM1 registers write protection */
+#define SERCOM1_PERIPH_ID                        (5)        /* H2PB Peripheral ID */
+#define SERCOM1_SPI                              (1)        /* SPI mode implemented? */
+#define SERCOM1_TWIM                             (1)        /* TWI Master mode implemented? */
+#define SERCOM1_TWIS                             (1)        /* TWI Slave mode implemented? */
+#define SERCOM1_ULTRA_IMPLEMENTATION             (0)        /* ULTRA platform compatibility? */
+#define SERCOM1_USART                            (1)        /* USART mode implemented? */
+#define SERCOM1_USART_AUTOBAUD                   (1)        /* USART autobaud implemented? */
+#define SERCOM1_USART_IRDA                       (1)        /* USART IrDA implemented? */
+#define SERCOM1_USART_LIN_MASTER                 (1)        /* USART LIN Master mode implemented? */
+#define SERCOM1_USART_RS485                      (1)        /* USART RS485 mode implemented? */
+
+#endif /* _PIC32CMGC00_SERCOM1_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom2.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom2.h
new file mode 100644
index 00000000..ce5a059c
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom2.h
@@ -0,0 +1,52 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_SERCOM2_INSTANCE_
+#define _PIC32CMGC00_SERCOM2_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for SERCOM2 peripheral ========== */
+#define SERCOM2_BRIDGE_ID                        (1)        /* H2PB Bridge ID */
+#define SERCOM2_CLK_REDUCTION                    (1)        /* Reduce clock options to pin 1 for SPI and USART */
+#define SERCOM2_DMA                              (1)        /* DMA support implemented? */
+#define SERCOM2_DMAC_ID_RX                       (8)        
+#define SERCOM2_DMAC_ID_TX                       (9)        
+#define SERCOM2_FIFO_IMPLEMENTED                 (1)        /* FIFO Rx/Tx implemented? */
+#define SERCOM2_FIFO_SIZE                        (16)       /* Rx-Tx FIFO size in bytes */
+#define SERCOM2_FSYNC_IMPLEMENTED                (1)        /* SPI Frame Synch mode implemented? */
+#define SERCOM2_GCLK_ID_CORE                     (23)       
+#define SERCOM2_GCLK_ID_SLOW                     (20)       
+#define SERCOM2_INSTANCE_ID                      (28)       /* Instance index for SERCOM2 */
+#define SERCOM2_MCLK_ID_APB                      (38)       /* Index for SERCOM2 APB clock */
+#define SERCOM2_PAC_ID                           (28)       /* Index for SERCOM2 registers write protection */
+#define SERCOM2_PERIPH_ID                        (6)        /* H2PB Peripheral ID */
+#define SERCOM2_SPI                              (1)        /* SPI mode implemented? */
+#define SERCOM2_TWIM                             (1)        /* TWI Master mode implemented? */
+#define SERCOM2_TWIS                             (1)        /* TWI Slave mode implemented? */
+#define SERCOM2_ULTRA_IMPLEMENTATION             (0)        /* ULTRA platform compatibility? */
+#define SERCOM2_USART                            (1)        /* USART mode implemented? */
+#define SERCOM2_USART_AUTOBAUD                   (1)        /* USART autobaud implemented? */
+#define SERCOM2_USART_IRDA                       (1)        /* USART IrDA implemented? */
+#define SERCOM2_USART_LIN_MASTER                 (1)        /* USART LIN Master mode implemented? */
+#define SERCOM2_USART_RS485                      (1)        /* USART RS485 mode implemented? */
+
+#endif /* _PIC32CMGC00_SERCOM2_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom3.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom3.h
new file mode 100644
index 00000000..885a4dcc
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom3.h
@@ -0,0 +1,52 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_SERCOM3_INSTANCE_
+#define _PIC32CMGC00_SERCOM3_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for SERCOM3 peripheral ========== */
+#define SERCOM3_BRIDGE_ID                        (1)        /* H2PB Bridge ID */
+#define SERCOM3_CLK_REDUCTION                    (1)        /* Reduce clock options to pin 1 for SPI and USART */
+#define SERCOM3_DMA                              (1)        /* DMA support implemented? */
+#define SERCOM3_DMAC_ID_RX                       (10)       
+#define SERCOM3_DMAC_ID_TX                       (11)       
+#define SERCOM3_FIFO_IMPLEMENTED                 (1)        /* FIFO Rx/Tx implemented? */
+#define SERCOM3_FIFO_SIZE                        (16)       /* Rx-Tx FIFO size in bytes */
+#define SERCOM3_FSYNC_IMPLEMENTED                (1)        /* SPI Frame Synch mode implemented? */
+#define SERCOM3_GCLK_ID_CORE                     (24)       
+#define SERCOM3_GCLK_ID_SLOW                     (20)       
+#define SERCOM3_INSTANCE_ID                      (29)       /* Instance index for SERCOM3 */
+#define SERCOM3_MCLK_ID_APB                      (39)       /* Index for SERCOM3 APB clock */
+#define SERCOM3_PAC_ID                           (29)       /* Index for SERCOM3 registers write protection */
+#define SERCOM3_PERIPH_ID                        (7)        /* H2PB Peripheral ID */
+#define SERCOM3_SPI                              (1)        /* SPI mode implemented? */
+#define SERCOM3_TWIM                             (1)        /* TWI Master mode implemented? */
+#define SERCOM3_TWIS                             (1)        /* TWI Slave mode implemented? */
+#define SERCOM3_ULTRA_IMPLEMENTATION             (0)        /* ULTRA platform compatibility? */
+#define SERCOM3_USART                            (1)        /* USART mode implemented? */
+#define SERCOM3_USART_AUTOBAUD                   (1)        /* USART autobaud implemented? */
+#define SERCOM3_USART_IRDA                       (1)        /* USART IrDA implemented? */
+#define SERCOM3_USART_LIN_MASTER                 (1)        /* USART LIN Master mode implemented? */
+#define SERCOM3_USART_RS485                      (1)        /* USART RS485 mode implemented? */
+
+#endif /* _PIC32CMGC00_SERCOM3_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom4.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom4.h
new file mode 100644
index 00000000..626ddf60
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom4.h
@@ -0,0 +1,51 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_SERCOM4_INSTANCE_
+#define _PIC32CMGC00_SERCOM4_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for SERCOM4 peripheral ========== */
+#define SERCOM4_BRIDGE_ID                        (1)        /* H2PB Bridge ID */
+#define SERCOM4_CLK_REDUCTION                    (1)        /* Reduce clock options to pin 1 for SPI and USART */
+#define SERCOM4_DMA                              (1)        /* DMA support implemented? */
+#define SERCOM4_DMAC_ID_RX                       (24)       
+#define SERCOM4_DMAC_ID_TX                       (25)       
+#define SERCOM4_FIFO_IMPLEMENTED                 (1)        /* FIFO Rx/Tx implemented? */
+#define SERCOM4_FIFO_SIZE                        (16)       /* Rx-Tx FIFO size in bytes */
+#define SERCOM4_FSYNC_IMPLEMENTED                (1)        /* SPI Frame Synch mode implemented? */
+#define SERCOM4_GCLK_ID_CORE                     (28)       
+#define SERCOM4_INSTANCE_ID                      (34)       /* Instance index for SERCOM4 */
+#define SERCOM4_MCLK_ID_APB                      (44)       /* Index for SERCOM4 APB clock */
+#define SERCOM4_PAC_ID                           (34)       /* Index for SERCOM4 registers write protection */
+#define SERCOM4_PERIPH_ID                        (16)       /* H2PB Peripheral ID */
+#define SERCOM4_SPI                              (1)        /* SPI mode implemented? */
+#define SERCOM4_TWIM                             (0)        /* TWI Master mode implemented? */
+#define SERCOM4_TWIS                             (0)        /* TWI Slave mode implemented? */
+#define SERCOM4_ULTRA_IMPLEMENTATION             (0)        /* ULTRA platform compatibility? */
+#define SERCOM4_USART                            (1)        /* USART mode implemented? */
+#define SERCOM4_USART_AUTOBAUD                   (1)        /* USART autobaud implemented? */
+#define SERCOM4_USART_IRDA                       (1)        /* USART IrDA implemented? */
+#define SERCOM4_USART_LIN_MASTER                 (1)        /* USART LIN Master mode implemented? */
+#define SERCOM4_USART_RS485                      (1)        /* USART RS485 mode implemented? */
+
+#endif /* _PIC32CMGC00_SERCOM4_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom5.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom5.h
new file mode 100644
index 00000000..3c84a8b1
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/sercom5.h
@@ -0,0 +1,51 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_SERCOM5_INSTANCE_
+#define _PIC32CMGC00_SERCOM5_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for SERCOM5 peripheral ========== */
+#define SERCOM5_BRIDGE_ID                        (1)        /* H2PB Bridge ID */
+#define SERCOM5_CLK_REDUCTION                    (1)        /* Reduce clock options to pin 1 for SPI and USART */
+#define SERCOM5_DMA                              (1)        /* DMA support implemented? */
+#define SERCOM5_DMAC_ID_RX                       (26)       
+#define SERCOM5_DMAC_ID_TX                       (27)       
+#define SERCOM5_FIFO_IMPLEMENTED                 (1)        /* FIFO Rx/Tx implemented? */
+#define SERCOM5_FIFO_SIZE                        (16)       /* Rx-Tx FIFO size in bytes */
+#define SERCOM5_FSYNC_IMPLEMENTED                (1)        /* SPI Frame Synch mode implemented? */
+#define SERCOM5_GCLK_ID_CORE                     (29)       
+#define SERCOM5_INSTANCE_ID                      (35)       /* Instance index for SERCOM5 */
+#define SERCOM5_MCLK_ID_APB                      (45)       /* Index for SERCOM5 APB clock */
+#define SERCOM5_PAC_ID                           (35)       /* Index for SERCOM5 registers write protection */
+#define SERCOM5_PERIPH_ID                        (17)       /* H2PB Peripheral ID */
+#define SERCOM5_SPI                              (1)        /* SPI mode implemented? */
+#define SERCOM5_TWIM                             (0)        /* TWI Master mode implemented? */
+#define SERCOM5_TWIS                             (0)        /* TWI Slave mode implemented? */
+#define SERCOM5_ULTRA_IMPLEMENTATION             (0)        /* ULTRA platform compatibility? */
+#define SERCOM5_USART                            (1)        /* USART mode implemented? */
+#define SERCOM5_USART_AUTOBAUD                   (1)        /* USART autobaud implemented? */
+#define SERCOM5_USART_IRDA                       (1)        /* USART IrDA implemented? */
+#define SERCOM5_USART_LIN_MASTER                 (1)        /* USART LIN Master mode implemented? */
+#define SERCOM5_USART_RS485                      (1)        /* USART RS485 mode implemented? */
+
+#endif /* _PIC32CMGC00_SERCOM5_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/supc.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/supc.h
new file mode 100644
index 00000000..0d90cdc7
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/supc.h
@@ -0,0 +1,44 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_SUPC_INSTANCE_
+#define _PIC32CMGC00_SUPC_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for SUPC peripheral ========== */
+#define SUPC_ADDVREG_NUM                         (1)        /* Jira PWR109-210 */
+#define SUPC_ADDVREG_PLL_NUM                     (0)        /* -- */
+#define SUPC_ADDVREG_PLL_START_INDEX             (1)        /* -- */
+#define SUPC_BKOUT_NUM                           (2)        /* -- */
+#define SUPC_BORVDDUSB_NUM                       (1)        /* (Jira PWR109-219) */
+#define SUPC_BRIDGE_ID                           (2)        /* H2PB Bridge ID */
+#define SUPC_CHRG_PUMP_NUM                       (2)        /* -- */
+#define SUPC_INSTANCE_ID                         (4)        /* Instance index for SUPC */
+#define SUPC_IOB_IMPLEMENTED                     (0)        /* -- */
+#define SUPC_MCLK_ID_APB                         (4)        /* Index for SUPC APB clock */
+#define SUPC_PAC_ID                              (4)        /* Index for SUPC registers write protection */
+#define SUPC_PERIPH_ID                           (1)        /* H2PB Peripheral ID */
+#define SUPC_USER_LDO_IMPLEMENTED                (1)        /* -- */
+#define SUPC_VBAT_IMPLEMENTED                    (0)        /* -- */
+#define SUPC_VREGSW_NUM                          (1)        /* -- */
+
+#endif /* _PIC32CMGC00_SUPC_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc0.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc0.h
new file mode 100644
index 00000000..bf276717
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc0.h
@@ -0,0 +1,47 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_TCC0_INSTANCE_
+#define _PIC32CMGC00_TCC0_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for TCC0 peripheral ========== */
+#define TCC0_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define TCC0_CC_NUM                              (2)        /* Number of Compare/Capture units */
+#define TCC0_DITHERING                           (0)        /* Dithering feature implemented */
+#define TCC0_DMAC_ID_MC0                         (13)       
+#define TCC0_DMAC_ID_MC1                         (14)       
+#define TCC0_DMAC_ID_OVF                         (12)       
+#define TCC0_DTI                                 (0)        /* Dead-Time-Insertion feature implemented */
+#define TCC0_GCLK_ID_TCC01                       (25)       
+#define TCC0_INSTANCE_ID                         (30)       /* Instance index for TCC0 */
+#define TCC0_MASTER_SLAVE_MODE                   (1)        /* TCC type 0 : NA, 1 : Master, 2 : Slave */
+#define TCC0_MCLK_ID_APB                         (40)       /* Index for TCC0 APB clock */
+#define TCC0_OTMX                                (0)        /* Output Matrix feature implemented */
+#define TCC0_OW_NUM                              (2)        /* Number of Output Waveforms */
+#define TCC0_PAC_ID                              (30)       /* Index for TCC0 registers write protection */
+#define TCC0_PERIPH_ID                           (8)        /* H2PB Peripheral ID */
+#define TCC0_PG                                  (0)        /* Pattern Generation feature implemented */
+#define TCC0_SIZE                                (16)       
+#define TCC0_SWAP                                (0)        /* DTI outputs swap feature implemented */
+
+#endif /* _PIC32CMGC00_TCC0_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc1.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc1.h
new file mode 100644
index 00000000..69117cdd
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc1.h
@@ -0,0 +1,47 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_TCC1_INSTANCE_
+#define _PIC32CMGC00_TCC1_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for TCC1 peripheral ========== */
+#define TCC1_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define TCC1_CC_NUM                              (2)        /* Number of Compare/Capture units */
+#define TCC1_DITHERING                           (0)        /* Dithering feature implemented */
+#define TCC1_DMAC_ID_MC0                         (16)       
+#define TCC1_DMAC_ID_MC1                         (17)       
+#define TCC1_DMAC_ID_OVF                         (15)       
+#define TCC1_DTI                                 (0)        /* Dead-Time-Insertion feature implemented */
+#define TCC1_GCLK_ID_TCC01                       (25)       
+#define TCC1_INSTANCE_ID                         (31)       /* Instance index for TCC1 */
+#define TCC1_MASTER_SLAVE_MODE                   (2)        /* TCC type 0 : NA, 1 : Master, 2 : Slave */
+#define TCC1_MCLK_ID_APB                         (41)       /* Index for TCC1 APB clock */
+#define TCC1_OTMX                                (0)        /* Output Matrix feature implemented */
+#define TCC1_OW_NUM                              (2)        /* Number of Output Waveforms */
+#define TCC1_PAC_ID                              (31)       /* Index for TCC1 registers write protection */
+#define TCC1_PERIPH_ID                           (9)        /* H2PB Peripheral ID */
+#define TCC1_PG                                  (0)        /* Pattern Generation feature implemented */
+#define TCC1_SIZE                                (16)       
+#define TCC1_SWAP                                (0)        /* DTI outputs swap feature implemented */
+
+#endif /* _PIC32CMGC00_TCC1_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc2.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc2.h
new file mode 100644
index 00000000..448e01df
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc2.h
@@ -0,0 +1,47 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_TCC2_INSTANCE_
+#define _PIC32CMGC00_TCC2_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for TCC2 peripheral ========== */
+#define TCC2_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define TCC2_CC_NUM                              (2)        /* Number of Compare/Capture units */
+#define TCC2_DITHERING                           (0)        /* Dithering feature implemented */
+#define TCC2_DMAC_ID_MC0                         (19)       
+#define TCC2_DMAC_ID_MC1                         (20)       
+#define TCC2_DMAC_ID_OVF                         (18)       
+#define TCC2_DTI                                 (0)        /* Dead-Time-Insertion feature implemented */
+#define TCC2_GCLK_ID                             (26)       
+#define TCC2_INSTANCE_ID                         (32)       /* Instance index for TCC2 */
+#define TCC2_MASTER_SLAVE_MODE                   (0)        /* TCC type 0 : NA, 1 : Master, 2 : Slave */
+#define TCC2_MCLK_ID_APB                         (42)       /* Index for TCC2 APB clock */
+#define TCC2_OTMX                                (0)        /* Output Matrix feature implemented */
+#define TCC2_OW_NUM                              (2)        /* Number of Output Waveforms */
+#define TCC2_PAC_ID                              (32)       /* Index for TCC2 registers write protection */
+#define TCC2_PERIPH_ID                           (10)       /* H2PB Peripheral ID */
+#define TCC2_PG                                  (0)        /* Pattern Generation feature implemented */
+#define TCC2_SIZE                                (16)       
+#define TCC2_SWAP                                (0)        /* DTI outputs swap feature implemented */
+
+#endif /* _PIC32CMGC00_TCC2_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc3.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc3.h
new file mode 100644
index 00000000..9d44f35a
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc3.h
@@ -0,0 +1,47 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_TCC3_INSTANCE_
+#define _PIC32CMGC00_TCC3_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for TCC3 peripheral ========== */
+#define TCC3_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define TCC3_CC_NUM                              (2)        /* Number of Compare/Capture units */
+#define TCC3_DITHERING                           (0)        /* Dithering feature implemented */
+#define TCC3_DMAC_ID_MC0                         (22)       
+#define TCC3_DMAC_ID_MC1                         (23)       
+#define TCC3_DMAC_ID_OVF                         (21)       
+#define TCC3_DTI                                 (0)        /* Dead-Time-Insertion feature implemented */
+#define TCC3_GCLK_ID                             (27)       
+#define TCC3_INSTANCE_ID                         (33)       /* Instance index for TCC3 */
+#define TCC3_MASTER_SLAVE_MODE                   (0)        /* TCC type 0 : NA, 1 : Master, 2 : Slave */
+#define TCC3_MCLK_ID_APB                         (43)       /* Index for TCC3 APB clock */
+#define TCC3_OTMX                                (0)        /* Output Matrix feature implemented */
+#define TCC3_OW_NUM                              (2)        /* Number of Output Waveforms */
+#define TCC3_PAC_ID                              (33)       /* Index for TCC3 registers write protection */
+#define TCC3_PERIPH_ID                           (11)       /* H2PB Peripheral ID */
+#define TCC3_PG                                  (0)        /* Pattern Generation feature implemented */
+#define TCC3_SIZE                                (16)       
+#define TCC3_SWAP                                (0)        /* DTI outputs swap feature implemented */
+
+#endif /* _PIC32CMGC00_TCC3_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc4.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc4.h
new file mode 100644
index 00000000..ef012edf
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc4.h
@@ -0,0 +1,47 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_TCC4_INSTANCE_
+#define _PIC32CMGC00_TCC4_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for TCC4 peripheral ========== */
+#define TCC4_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define TCC4_CC_NUM                              (2)        /* Number of Compare/Capture units */
+#define TCC4_DITHERING                           (0)        /* Dithering feature implemented */
+#define TCC4_DMAC_ID_MC0                         (29)       
+#define TCC4_DMAC_ID_MC1                         (30)       
+#define TCC4_DMAC_ID_OVF                         (28)       
+#define TCC4_DTI                                 (0)        /* Dead-Time-Insertion feature implemented */
+#define TCC4_GCLK_ID                             (30)       
+#define TCC4_INSTANCE_ID                         (36)       /* Instance index for TCC4 */
+#define TCC4_MASTER_SLAVE_MODE                   (0)        /* TCC type 0 : NA, 1 : Master, 2 : Slave */
+#define TCC4_MCLK_ID_APB                         (46)       /* Index for TCC4 APB clock */
+#define TCC4_OTMX                                (0)        /* Output Matrix feature implemented */
+#define TCC4_OW_NUM                              (2)        /* Number of Output Waveforms */
+#define TCC4_PAC_ID                              (36)       /* Index for TCC4 registers write protection */
+#define TCC4_PERIPH_ID                           (18)       /* H2PB Peripheral ID */
+#define TCC4_PG                                  (0)        /* Pattern Generation feature implemented */
+#define TCC4_SIZE                                (16)       
+#define TCC4_SWAP                                (0)        /* DTI outputs swap feature implemented */
+
+#endif /* _PIC32CMGC00_TCC4_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc5.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc5.h
new file mode 100644
index 00000000..52794301
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc5.h
@@ -0,0 +1,47 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_TCC5_INSTANCE_
+#define _PIC32CMGC00_TCC5_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for TCC5 peripheral ========== */
+#define TCC5_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define TCC5_CC_NUM                              (2)        /* Number of Compare/Capture units */
+#define TCC5_DITHERING                           (0)        /* Dithering feature implemented */
+#define TCC5_DMAC_ID_MC0                         (32)       
+#define TCC5_DMAC_ID_MC1                         (33)       
+#define TCC5_DMAC_ID_OVF                         (31)       
+#define TCC5_DTI                                 (0)        /* Dead-Time-Insertion feature implemented */
+#define TCC5_GCLK_ID                             (31)       
+#define TCC5_INSTANCE_ID                         (37)       /* Instance index for TCC5 */
+#define TCC5_MASTER_SLAVE_MODE                   (0)        /* TCC type 0 : NA, 1 : Master, 2 : Slave */
+#define TCC5_MCLK_ID_APB                         (47)       /* Index for TCC5 APB clock */
+#define TCC5_OTMX                                (0)        /* Output Matrix feature implemented */
+#define TCC5_OW_NUM                              (2)        /* Number of Output Waveforms */
+#define TCC5_PAC_ID                              (37)       /* Index for TCC5 registers write protection */
+#define TCC5_PERIPH_ID                           (19)       /* H2PB Peripheral ID */
+#define TCC5_PG                                  (0)        /* Pattern Generation feature implemented */
+#define TCC5_SIZE                                (16)       
+#define TCC5_SWAP                                (0)        /* DTI outputs swap feature implemented */
+
+#endif /* _PIC32CMGC00_TCC5_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc6.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc6.h
new file mode 100644
index 00000000..9289f6b2
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/tcc6.h
@@ -0,0 +1,47 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_TCC6_INSTANCE_
+#define _PIC32CMGC00_TCC6_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for TCC6 peripheral ========== */
+#define TCC6_BRIDGE_ID                           (1)        /* H2PB Bridge ID */
+#define TCC6_CC_NUM                              (2)        /* Number of Compare/Capture units */
+#define TCC6_DITHERING                           (0)        /* Dithering feature implemented */
+#define TCC6_DMAC_ID_MC0                         (35)       
+#define TCC6_DMAC_ID_MC1                         (36)       
+#define TCC6_DMAC_ID_OVF                         (34)       
+#define TCC6_DTI                                 (0)        /* Dead-Time-Insertion feature implemented */
+#define TCC6_GCLK_ID                             (32)       
+#define TCC6_INSTANCE_ID                         (38)       /* Instance index for TCC6 */
+#define TCC6_MASTER_SLAVE_MODE                   (0)        /* TCC type 0 : NA, 1 : Master, 2 : Slave */
+#define TCC6_MCLK_ID_APB                         (48)       /* Index for TCC6 APB clock */
+#define TCC6_OTMX                                (0)        /* Output Matrix feature implemented */
+#define TCC6_OW_NUM                              (2)        /* Number of Output Waveforms */
+#define TCC6_PAC_ID                              (38)       /* Index for TCC6 registers write protection */
+#define TCC6_PERIPH_ID                           (20)       /* H2PB Peripheral ID */
+#define TCC6_PG                                  (0)        /* Pattern Generation feature implemented */
+#define TCC6_SIZE                                (16)       
+#define TCC6_SWAP                                (0)        /* DTI outputs swap feature implemented */
+
+#endif /* _PIC32CMGC00_TCC6_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/usb.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/usb.h
new file mode 100644
index 00000000..4d54221f
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/usb.h
@@ -0,0 +1,52 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_USB_INSTANCE_
+#define _PIC32CMGC00_USB_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for USB peripheral ========== */
+#define USB_AHB_2_USB_FIFO_DEPTH                 (4)        /* bytes number, should be at least 2, and 2^n (4,8,16 ...) */
+#define USB_AHB_2_USB_RD_DATA_BITS               (8)        /* 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode */
+#define USB_AHB_2_USB_WR_DATA_BITS               (32)       /* 8, 16 or 32 : here, AHB transfer is made in word mode */
+#define USB_AHB_2_USB_WR_THRESHOLD               (2)        /* as soon as there are N bytes-free inside the fifo, ahb read transfer is requested */
+#define USB_BRIDGE_ID                            (1)        /* H2PB Bridge ID */
+#define USB_DATA_BUS_16_8                        (0)        /* UTMI/SIE data bus size : 0 -> 8 bits, 1 -> 16 bits */
+#define USB_EPNUM                                (8)        /* parameter for rtl : max of ENDPOINT and PIPE NUM */
+#define USB_EPT_NUM                              (8)        /* Number of USB end points */
+#define USB_GCLK_ID                              (38)       
+#define USB_INITIAL_CONTROL_QOS                  (3)        /* CONTROL QOS RESET value */
+#define USB_INITIAL_DATA_QOS                     (3)        /* DATA QOS RESET value */
+#define USB_INSTANCE_ID                          (44)       /* Instance index for USB */
+#define USB_MCLK_ID_AHB                          (54)       /* Index for USB AHB clock */
+#define USB_MCLK_ID_APB                          (55)       /* Index for USB APB clock */
+#define USB_MISSING_SOF_DET_IMPLEMENTED          (1)        /* 48 mHz xPLL feature implemented */
+#define USB_PAC_ID                               (44)       /* Index for USB registers write protection */
+#define USB_PERIPH_ID                            (25)       /* H2PB Peripheral ID */
+#define USB_PIPE_NUM                             (8)        /* Number of USB pipes */
+#define USB_SYSTEM_CLOCK_IS_CKUSB                (0)        /* Dual (1'b0) or Single (1'b1) clock system */
+#define USB_2_AHB_FIFO_DEPTH                     (4)        /* bytes number, should be at least 2, and 2^n (4,8,16 ...) */
+#define USB_2_AHB_RD_DATA_BITS                   (16)       /* 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode */
+#define USB_2_AHB_RD_THRESHOLD                   (2)        /* as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested */
+#define USB_2_AHB_WR_DATA_BITS                   (8)        /* 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode */
+
+#endif /* _PIC32CMGC00_USB_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/wdt.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/wdt.h
new file mode 100644
index 00000000..373af12b
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/instance/wdt.h
@@ -0,0 +1,35 @@
+/*
+ * Instance header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* file generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CMGC00_WDT_INSTANCE_
+#define _PIC32CMGC00_WDT_INSTANCE_
+
+
+/* ========== Instance Parameter definitions for WDT peripheral ========== */
+#define WDT_BRIDGE_ID                            (0)        /* H2PB Bridge ID */
+#define WDT_FUSES_UPDATE_SUPPORT                 (0)        /* WDT Fuse Update Support */
+#define WDT_INSTANCE_ID                          (11)       /* Instance index for WDT */
+#define WDT_MCLK_ID_APB                          (11)       /* Index for WDT APB clock */
+#define WDT_PAC_ID                               (11)       /* Index for WDT registers write protection */
+#define WDT_PERIPH_ID                            (7)        /* H2PB Peripheral ID */
+
+#endif /* _PIC32CMGC00_WDT_INSTANCE_ */
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32c.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32c.h
new file mode 100644
index 00000000..573033c6
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32c.h
@@ -0,0 +1,36 @@
+/*
+ * Top level header file
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef _PIC32C_H_
+#define _PIC32C_H_
+
+#if   defined(__PIC32CM5112GC00048__) || defined(__PIC32CM5112GC00048__)
+  #include "pic32cm5112gc00048.h"
+#elif defined(__PIC32CM5112GC00064__) || defined(__PIC32CM5112GC00064__)
+  #include "pic32cm5112gc00064.h"
+#elif defined(__PIC32CM5112GC00100__) || defined(__PIC32CM5112GC00100__)
+  #include "pic32cm5112gc00100.h"
+#else
+  #error Library does not support the specified device
+#endif
+
+#endif /* _PIC32C_H_ */
+
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32cm5112gc00048.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32cm5112gc00048.h
new file mode 100644
index 00000000..9d2b9c91
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32cm5112gc00048.h
@@ -0,0 +1,1029 @@
+/*
+ * Header file for PIC32CM5112GC00048
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* File generated from device description file (ATDF) version 2024-11-05T16:47:51Z */
+#ifndef _PIC32CM5112GC00048_H_
+#define _PIC32CM5112GC00048_H_
+
+/* Header version uses Semantic Versioning 2.0.0 (https://semver.org/) */
+#define HEADER_FORMAT_VERSION "2.1.1"
+
+#define HEADER_FORMAT_VERSION_MAJOR (2)
+#define HEADER_FORMAT_VERSION_MINOR (1)
+#define HEADER_FORMAT_VERSION_PATCH (1)
+
+/* PIC32CM5112GC00048 definitions
+  This file defines all structures and symbols for PIC32CM5112GC00048:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  include <stdint.h>
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#  if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_)
+#    error "Integer constant value macros already defined elsewhere"
+#  endif
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with sizes of integer constants for C/C++ */
+#  define _UINT8_(x)   ((uint8_t)(x))    /* C code: 8-bits unsigned integer constant value */
+#  define _UINT16_(x)  ((uint16_t)(x))   /* C code: 16-bits unsigned integer constant value */
+#  define _UINT32_(x)  ((uint32_t)(x))   /* C code: 32-bits unsigned integer constant value */
+
+#else /* Assembler */
+
+#  define _UINT8_(x) x    /* Assembler: 8-bits unsigned integer constant value */
+#  define _UINT16_(x) x   /* Assembler: 16-bits unsigned integer constant value */
+#  define _UINT32_(x) x   /* Assembler: 32-bits unsigned integer constant value */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/*                  CMSIS DEFINITIONS FOR PIC32CM5112GC00048                  */
+/* ************************************************************************** */
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  CORTEX-M23 Processor Exceptions Numbers ******************************/
+  Reset_IRQn                = -15, /* -15 Reset Vector, invoked on Power up and warm reset */
+  NonMaskableInt_IRQn       = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */
+  HardFault_IRQn            = -13, /* -13 Hard Fault, all classes of Fault    */
+  SVCall_IRQn               =  -5, /* -5  System Service Call via SVC instruction */
+  PendSV_IRQn               =  -2, /* -2  Pendable request for system service */
+  SysTick_IRQn              =  -1, /* -1  System Tick Timer                   */
+
+/* ************* PIC32CM5112GC00048 specific Interrupt Numbers ************** */
+  FCR_IRQn                  =   0, /* 0   Polaris Flash Read Controller (FCR) */
+  FCW_IRQn                  =   1, /* 1   Polaris Flash Write Controller (FCW) */
+  PM_IRQn                   =   2, /* 2   Power Manager (PM)                  */
+  SUPC_IRQn                 =   3, /* 3   Supply Controller (SUPC)            */
+  OSCCTRL_XOSCRDY_IRQn      =   4, /* 4   Oscillators Control (OSCCTRL)       */
+  OSCCTRL_DFLLRDY_IRQn      =   5, /* 5   Oscillators Control (OSCCTRL)       */
+  OSCCTRL_PLLLOCKR_0_IRQn   =   6, /* 6   Oscillators Control (OSCCTRL)       */
+  OSC32KCTRL_XOSC32KRDY_IRQn =   7, /* 7   32kHz Oscillators Control (OSC32KCTRL) */
+  OSC32KCTRL_XOSC32KFAIL_IRQn =   8, /* 8   32kHz Oscillators Control (OSC32KCTRL) */
+  MCLK_IRQn                 =   9, /* 9   Polaris Main Clock Controller (MCLK) */
+  FREQM_IRQn                =  10, /* 10  Frequency Meter (FREQM)             */
+  WDT_IRQn                  =  11, /* 11  Watchdog Timer (WDT)                */
+  RTC_TAMPER_IRQn           =  12, /* 12  Real-Time Counter (RTC)             */
+  RTC_OVF_IRQn              =  13, /* 13  Real-Time Counter (RTC)             */
+  RTC_PER0_IRQn             =  14, /* 14  Real-Time Counter (RTC)             */
+  RTC_CMP0_IRQn             =  15, /* 15  Real-Time Counter (RTC)             */
+  EIC_EXTINT0_IRQn          =  16, /* 16  External Interrupt Controller (EIC) */
+  EIC_EXTINT1_IRQn          =  17, /* 17  External Interrupt Controller (EIC) */
+  EIC_EXTINT2_IRQn          =  18, /* 18  External Interrupt Controller (EIC) */
+  EIC_EXTINT3_IRQn          =  19, /* 19  External Interrupt Controller (EIC) */
+  EIC_EXTINT4_IRQn          =  20, /* 20  External Interrupt Controller (EIC) */
+  EIC_EXTINT5_IRQn          =  21, /* 21  External Interrupt Controller (EIC) */
+  EIC_EXTINT6_IRQn          =  22, /* 22  External Interrupt Controller (EIC) */
+  EIC_EXTINT7_IRQn          =  23, /* 23  External Interrupt Controller (EIC) */
+  EIC_EXTINT8_IRQn          =  24, /* 24  External Interrupt Controller (EIC) */
+  EIC_EXTINT9_IRQn          =  25, /* 25  External Interrupt Controller (EIC) */
+  EIC_EXTINT10_IRQn         =  26, /* 26  External Interrupt Controller (EIC) */
+  EIC_EXTINT11_IRQn         =  27, /* 27  External Interrupt Controller (EIC) */
+  EIC_EXTINT12_IRQn         =  28, /* 28  External Interrupt Controller (EIC) */
+  EIC_EXTINT13_IRQn         =  29, /* 29  External Interrupt Controller (EIC) */
+  EIC_EXTINT14_IRQn         =  30, /* 30  External Interrupt Controller (EIC) */
+  EIC_EXTINT15_IRQn         =  31, /* 31  External Interrupt Controller (EIC) */
+  EIC_NSCHK_IRQn            =  32, /* 32  External Interrupt Controller (EIC) */
+  MCRAMC_IRQn               =  34, /* 34  Multi-Channel RAM Controller (MCRAMC) */
+  CAN0_INT0_IRQn            =  35, /* 35  Control Area Network (CAN0)         */
+  CAN0_INT1_IRQn            =  36, /* 36  Control Area Network (CAN0)         */
+  CAN0_BERR_IRQn            =  37, /* 37  Control Area Network (CAN0)         */
+  CAN1_INT0_IRQn            =  38, /* 38  Control Area Network (CAN1)         */
+  CAN1_INT1_IRQn            =  39, /* 39  Control Area Network (CAN1)         */
+  CAN1_BERR_IRQn            =  40, /* 40  Control Area Network (CAN1)         */
+  PORT_IRQn                 =  41, /* 41  Port Module (PORT)                  */
+  DMAC_TCMPL0_IRQn          =  42, /* 42  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL1_IRQn          =  43, /* 43  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL2_IRQn          =  44, /* 44  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL3_IRQn          =  45, /* 45  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL4_IRQn          =  46, /* 46  Direct Memory Access Controller (DMAC) */
+  HMATRIX2_IRQn             =  47, /* 47  HSB Matrix (HMATRIX2)               */
+  EVSYS_EVD0_IRQn           =  48, /* 48  Event System Interface (EVSYS)      */
+  EVSYS_EVD1_IRQn           =  49, /* 49  Event System Interface (EVSYS)      */
+  EVSYS_EVD2_IRQn           =  50, /* 50  Event System Interface (EVSYS)      */
+  EVSYS_EVD3_IRQn           =  51, /* 51  Event System Interface (EVSYS)      */
+  EVSYS_EVD4_IRQn           =  52, /* 52  Event System Interface (EVSYS)      */
+  EVSYS_EVD5_IRQn           =  53, /* 53  Event System Interface (EVSYS)      */
+  EVSYS_EVD6_IRQn           =  54, /* 54  Event System Interface (EVSYS)      */
+  EVSYS_EVD7_IRQn           =  55, /* 55  Event System Interface (EVSYS)      */
+  EVSYS_EVD8_IRQn           =  56, /* 56  Event System Interface (EVSYS)      */
+  EVSYS_EVD9_IRQn           =  57, /* 57  Event System Interface (EVSYS)      */
+  EVSYS_EVD10_IRQn          =  58, /* 58  Event System Interface (EVSYS)      */
+  EVSYS_EVD11_IRQn          =  59, /* 59  Event System Interface (EVSYS)      */
+  SERCOM0_6_IRQn            =  60, /* 60  Serial Communication Interface (SERCOM0) */
+  SERCOM0_5_IRQn            =  61, /* 61  Serial Communication Interface (SERCOM0) */
+  SERCOM0_0_IRQn            =  62, /* 62  Serial Communication Interface (SERCOM0) */
+  SERCOM0_1_IRQn            =  63, /* 63  Serial Communication Interface (SERCOM0) */
+  SERCOM0_2_IRQn            =  64, /* 64  Serial Communication Interface (SERCOM0) */
+  SERCOM0_3_IRQn            =  65, /* 65  Serial Communication Interface (SERCOM0) */
+  SERCOM0_4_IRQn            =  66, /* 66  Serial Communication Interface (SERCOM0) */
+  SERCOM1_6_IRQn            =  67, /* 67  Serial Communication Interface (SERCOM1) */
+  SERCOM1_5_IRQn            =  68, /* 68  Serial Communication Interface (SERCOM1) */
+  SERCOM1_0_IRQn            =  69, /* 69  Serial Communication Interface (SERCOM1) */
+  SERCOM1_1_IRQn            =  70, /* 70  Serial Communication Interface (SERCOM1) */
+  SERCOM1_2_IRQn            =  71, /* 71  Serial Communication Interface (SERCOM1) */
+  SERCOM1_3_IRQn            =  72, /* 72  Serial Communication Interface (SERCOM1) */
+  SERCOM1_4_IRQn            =  73, /* 73  Serial Communication Interface (SERCOM1) */
+  SERCOM2_6_IRQn            =  74, /* 74  Serial Communication Interface (SERCOM2) */
+  SERCOM2_5_IRQn            =  75, /* 75  Serial Communication Interface (SERCOM2) */
+  SERCOM2_0_IRQn            =  76, /* 76  Serial Communication Interface (SERCOM2) */
+  SERCOM2_1_IRQn            =  77, /* 77  Serial Communication Interface (SERCOM2) */
+  SERCOM2_2_IRQn            =  78, /* 78  Serial Communication Interface (SERCOM2) */
+  SERCOM2_3_IRQn            =  79, /* 79  Serial Communication Interface (SERCOM2) */
+  SERCOM2_4_IRQn            =  80, /* 80  Serial Communication Interface (SERCOM2) */
+  SERCOM3_6_IRQn            =  81, /* 81  Serial Communication Interface (SERCOM3) */
+  SERCOM3_5_IRQn            =  82, /* 82  Serial Communication Interface (SERCOM3) */
+  SERCOM3_0_IRQn            =  83, /* 83  Serial Communication Interface (SERCOM3) */
+  SERCOM3_1_IRQn            =  84, /* 84  Serial Communication Interface (SERCOM3) */
+  SERCOM3_2_IRQn            =  85, /* 85  Serial Communication Interface (SERCOM3) */
+  SERCOM3_3_IRQn            =  86, /* 86  Serial Communication Interface (SERCOM3) */
+  SERCOM3_4_IRQn            =  87, /* 87  Serial Communication Interface (SERCOM3) */
+  TCC0_DFS_IRQn             =  88, /* 88  Timer Counter for Control Applications (TCC0) */
+  TCC0_CNT_IRQn             =  89, /* 89  Timer Counter for Control Applications (TCC0) */
+  TCC0_MC0_IRQn             =  90, /* 90  Timer Counter for Control Applications (TCC0) */
+  TCC0_MC1_IRQn             =  91, /* 91  Timer Counter for Control Applications (TCC0) */
+  TCC1_DFS_IRQn             =  92, /* 92  Timer Counter for Control Applications (TCC1) */
+  TCC1_CNT_IRQn             =  93, /* 93  Timer Counter for Control Applications (TCC1) */
+  TCC1_MC0_IRQn             =  94, /* 94  Timer Counter for Control Applications (TCC1) */
+  TCC1_MC1_IRQn             =  95, /* 95  Timer Counter for Control Applications (TCC1) */
+  TCC2_DFS_IRQn             =  96, /* 96  Timer Counter for Control Applications (TCC2) */
+  TCC2_CNT_IRQn             =  97, /* 97  Timer Counter for Control Applications (TCC2) */
+  TCC2_MC0_IRQn             =  98, /* 98  Timer Counter for Control Applications (TCC2) */
+  TCC2_MC1_IRQn             =  99, /* 99  Timer Counter for Control Applications (TCC2) */
+  TCC3_DFS_IRQn             = 100, /* 100 Timer Counter for Control Applications (TCC3) */
+  TCC3_CNT_IRQn             = 101, /* 101 Timer Counter for Control Applications (TCC3) */
+  TCC3_MC0_IRQn             = 102, /* 102 Timer Counter for Control Applications (TCC3) */
+  TCC3_MC1_IRQn             = 103, /* 103 Timer Counter for Control Applications (TCC3) */
+  SERCOM4_6_IRQn            = 104, /* 104 Serial Communication Interface (SERCOM4) */
+  SERCOM4_5_IRQn            = 105, /* 105 Serial Communication Interface (SERCOM4) */
+  SERCOM4_0_IRQn            = 106, /* 106 Serial Communication Interface (SERCOM4) */
+  SERCOM4_1_IRQn            = 107, /* 107 Serial Communication Interface (SERCOM4) */
+  SERCOM4_2_IRQn            = 108, /* 108 Serial Communication Interface (SERCOM4) */
+  SERCOM4_3_IRQn            = 109, /* 109 Serial Communication Interface (SERCOM4) */
+  SERCOM4_4_IRQn            = 110, /* 110 Serial Communication Interface (SERCOM4) */
+  SERCOM5_6_IRQn            = 111, /* 111 Serial Communication Interface (SERCOM5) */
+  SERCOM5_5_IRQn            = 112, /* 112 Serial Communication Interface (SERCOM5) */
+  SERCOM5_0_IRQn            = 113, /* 113 Serial Communication Interface (SERCOM5) */
+  SERCOM5_1_IRQn            = 114, /* 114 Serial Communication Interface (SERCOM5) */
+  SERCOM5_2_IRQn            = 115, /* 115 Serial Communication Interface (SERCOM5) */
+  SERCOM5_3_IRQn            = 116, /* 116 Serial Communication Interface (SERCOM5) */
+  SERCOM5_4_IRQn            = 117, /* 117 Serial Communication Interface (SERCOM5) */
+  TCC4_DFS_IRQn             = 118, /* 118 Timer Counter for Control Applications (TCC4) */
+  TCC4_CNT_IRQn             = 119, /* 119 Timer Counter for Control Applications (TCC4) */
+  TCC4_MC0_IRQn             = 120, /* 120 Timer Counter for Control Applications (TCC4) */
+  TCC4_MC1_IRQn             = 121, /* 121 Timer Counter for Control Applications (TCC4) */
+  TCC5_DFS_IRQn             = 122, /* 122 Timer Counter for Control Applications (TCC5) */
+  TCC5_CNT_IRQn             = 123, /* 123 Timer Counter for Control Applications (TCC5) */
+  TCC5_MC0_IRQn             = 124, /* 124 Timer Counter for Control Applications (TCC5) */
+  TCC5_MC1_IRQn             = 125, /* 125 Timer Counter for Control Applications (TCC5) */
+  TCC6_DFS_IRQn             = 126, /* 126 Timer Counter for Control Applications (TCC6) */
+  TCC6_CNT_IRQn             = 127, /* 127 Timer Counter for Control Applications (TCC6) */
+  TCC6_MC0_IRQn             = 128, /* 128 Timer Counter for Control Applications (TCC6) */
+  TCC6_MC1_IRQn             = 129, /* 129 Timer Counter for Control Applications (TCC6) */
+  ADC_REQ0_IRQn             = 130, /* 130 ADC Controller (ADC)                */
+  ADC_REQ1_IRQn             = 131, /* 131 ADC Controller (ADC)                */
+  AC_IRQn                   = 132, /* 132 Analog Comparator Controller (AC)   */
+  PTC_IRQn                  = 133, /* 133 Polaris Peripheral Touch Controller (PTC) */
+  USB_EORSMDNRSM_IRQn       = 134, /* 134 Full-Speed Universal Serial Bus (USB) */
+  USB_SOFHSOF_IRQn          = 135, /* 135 Full-Speed Universal Serial Bus (USB) */
+  USB_TRCPT00_IRQn          = 136, /* 136 Full-Speed Universal Serial Bus (USB) */
+  USB_TRCPT10_IRQn          = 137, /* 137 Full-Speed Universal Serial Bus (USB) */
+  AT_IRQn                   = 138, /* 138 Anti-Tamper Controller (AT) (AT)    */
+
+  PERIPH_MAX_IRQn           = 138  /* Max peripheral ID */
+} IRQn_Type;
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+  /* CORTEX-M23 handlers */
+  void* pfnReset_Handler;                        /* -15 Reset Vector, invoked on Power up and warm reset */
+  void* pfnNonMaskableInt_Handler;               /* -14 Non maskable Interrupt, cannot be stopped or preempted */
+  void* pfnHardFault_Handler;                    /* -13 Hard Fault, all classes of Fault */
+  void* pvReservedC12;
+  void* pvReservedC11;
+  void* pvReservedC10;
+  void* pvReservedC9;
+  void* pvReservedC8;
+  void* pvReservedC7;
+  void* pvReservedC6;
+  void* pfnSVCall_Handler;                       /*  -5 System Service Call via SVC instruction */
+  void* pvReservedC4;
+  void* pvReservedC3;
+  void* pfnPendSV_Handler;                       /*  -2 Pendable request for system service */
+  void* pfnSysTick_Handler;                      /*  -1 System Tick Timer */
+
+  /* Peripheral handlers */
+  void* pfnFCR_Handler;                          /*   0 Polaris Flash Read Controller (FCR) */
+  void* pfnFCW_Handler;                          /*   1 Polaris Flash Write Controller (FCW) */
+  void* pfnPM_Handler;                           /*   2 Power Manager (PM) */
+  void* pfnSUPC_Handler;                         /*   3 Supply Controller (SUPC) */
+  void* pfnOSCCTRL_XOSCRDY_Handler;              /*   4 Oscillators Control (OSCCTRL) */
+  void* pfnOSCCTRL_DFLLRDY_Handler;              /*   5 Oscillators Control (OSCCTRL) */
+  void* pfnOSCCTRL_PLLLOCKR_0_Handler;           /*   6 Oscillators Control (OSCCTRL) */
+  void* pfnOSC32KCTRL_XOSC32KRDY_Handler;        /*   7 32kHz Oscillators Control (OSC32KCTRL) */
+  void* pfnOSC32KCTRL_XOSC32KFAIL_Handler;       /*   8 32kHz Oscillators Control (OSC32KCTRL) */
+  void* pfnMCLK_Handler;                         /*   9 Polaris Main Clock Controller (MCLK) */
+  void* pfnFREQM_Handler;                        /*  10 Frequency Meter (FREQM) */
+  void* pfnWDT_Handler;                          /*  11 Watchdog Timer (WDT) */
+  void* pfnRTC_TAMPER_Handler;                   /*  12 Real-Time Counter (RTC) */
+  void* pfnRTC_OVF_Handler;                      /*  13 Real-Time Counter (RTC) */
+  void* pfnRTC_PER0_Handler;                     /*  14 Real-Time Counter (RTC) */
+  void* pfnRTC_CMP0_Handler;                     /*  15 Real-Time Counter (RTC) */
+  void* pfnEIC_EXTINT0_Handler;                  /*  16 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT1_Handler;                  /*  17 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT2_Handler;                  /*  18 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT3_Handler;                  /*  19 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT4_Handler;                  /*  20 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT5_Handler;                  /*  21 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT6_Handler;                  /*  22 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT7_Handler;                  /*  23 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT8_Handler;                  /*  24 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT9_Handler;                  /*  25 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT10_Handler;                 /*  26 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT11_Handler;                 /*  27 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT12_Handler;                 /*  28 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT13_Handler;                 /*  29 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT14_Handler;                 /*  30 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT15_Handler;                 /*  31 External Interrupt Controller (EIC) */
+  void* pfnEIC_NSCHK_Handler;                    /*  32 External Interrupt Controller (EIC) */
+  void* pvReserved33;
+  void* pfnMCRAMC_Handler;                       /*  34 Multi-Channel RAM Controller (MCRAMC) */
+  void* pfnCAN0_INT0_Handler;                    /*  35 Control Area Network (CAN0) */
+  void* pfnCAN0_INT1_Handler;                    /*  36 Control Area Network (CAN0) */
+  void* pfnCAN0_BERR_Handler;                    /*  37 Control Area Network (CAN0) */
+  void* pfnCAN1_INT0_Handler;                    /*  38 Control Area Network (CAN1) */
+  void* pfnCAN1_INT1_Handler;                    /*  39 Control Area Network (CAN1) */
+  void* pfnCAN1_BERR_Handler;                    /*  40 Control Area Network (CAN1) */
+  void* pfnPORT_Handler;                         /*  41 Port Module (PORT) */
+  void* pfnDMAC_TCMPL0_Handler;                  /*  42 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL1_Handler;                  /*  43 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL2_Handler;                  /*  44 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL3_Handler;                  /*  45 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL4_Handler;                  /*  46 Direct Memory Access Controller (DMAC) */
+  void* pfnHMATRIX2_Handler;                     /*  47 HSB Matrix (HMATRIX2) */
+  void* pfnEVSYS_EVD0_Handler;                   /*  48 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD1_Handler;                   /*  49 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD2_Handler;                   /*  50 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD3_Handler;                   /*  51 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD4_Handler;                   /*  52 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD5_Handler;                   /*  53 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD6_Handler;                   /*  54 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD7_Handler;                   /*  55 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD8_Handler;                   /*  56 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD9_Handler;                   /*  57 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD10_Handler;                  /*  58 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD11_Handler;                  /*  59 Event System Interface (EVSYS) */
+  void* pfnSERCOM0_6_Handler;                    /*  60 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_5_Handler;                    /*  61 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_0_Handler;                    /*  62 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_1_Handler;                    /*  63 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_2_Handler;                    /*  64 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_3_Handler;                    /*  65 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_4_Handler;                    /*  66 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM1_6_Handler;                    /*  67 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_5_Handler;                    /*  68 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_0_Handler;                    /*  69 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_1_Handler;                    /*  70 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_2_Handler;                    /*  71 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_3_Handler;                    /*  72 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_4_Handler;                    /*  73 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM2_6_Handler;                    /*  74 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_5_Handler;                    /*  75 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_0_Handler;                    /*  76 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_1_Handler;                    /*  77 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_2_Handler;                    /*  78 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_3_Handler;                    /*  79 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_4_Handler;                    /*  80 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM3_6_Handler;                    /*  81 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_5_Handler;                    /*  82 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_0_Handler;                    /*  83 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_1_Handler;                    /*  84 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_2_Handler;                    /*  85 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_3_Handler;                    /*  86 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_4_Handler;                    /*  87 Serial Communication Interface (SERCOM3) */
+  void* pfnTCC0_DFS_Handler;                     /*  88 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC0_CNT_Handler;                     /*  89 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC0_MC0_Handler;                     /*  90 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC0_MC1_Handler;                     /*  91 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC1_DFS_Handler;                     /*  92 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC1_CNT_Handler;                     /*  93 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC1_MC0_Handler;                     /*  94 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC1_MC1_Handler;                     /*  95 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC2_DFS_Handler;                     /*  96 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC2_CNT_Handler;                     /*  97 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC2_MC0_Handler;                     /*  98 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC2_MC1_Handler;                     /*  99 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC3_DFS_Handler;                     /* 100 Timer Counter for Control Applications (TCC3) */
+  void* pfnTCC3_CNT_Handler;                     /* 101 Timer Counter for Control Applications (TCC3) */
+  void* pfnTCC3_MC0_Handler;                     /* 102 Timer Counter for Control Applications (TCC3) */
+  void* pfnTCC3_MC1_Handler;                     /* 103 Timer Counter for Control Applications (TCC3) */
+  void* pfnSERCOM4_6_Handler;                    /* 104 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_5_Handler;                    /* 105 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_0_Handler;                    /* 106 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_1_Handler;                    /* 107 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_2_Handler;                    /* 108 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_3_Handler;                    /* 109 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_4_Handler;                    /* 110 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM5_6_Handler;                    /* 111 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_5_Handler;                    /* 112 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_0_Handler;                    /* 113 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_1_Handler;                    /* 114 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_2_Handler;                    /* 115 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_3_Handler;                    /* 116 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_4_Handler;                    /* 117 Serial Communication Interface (SERCOM5) */
+  void* pfnTCC4_DFS_Handler;                     /* 118 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC4_CNT_Handler;                     /* 119 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC4_MC0_Handler;                     /* 120 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC4_MC1_Handler;                     /* 121 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC5_DFS_Handler;                     /* 122 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC5_CNT_Handler;                     /* 123 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC5_MC0_Handler;                     /* 124 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC5_MC1_Handler;                     /* 125 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC6_DFS_Handler;                     /* 126 Timer Counter for Control Applications (TCC6) */
+  void* pfnTCC6_CNT_Handler;                     /* 127 Timer Counter for Control Applications (TCC6) */
+  void* pfnTCC6_MC0_Handler;                     /* 128 Timer Counter for Control Applications (TCC6) */
+  void* pfnTCC6_MC1_Handler;                     /* 129 Timer Counter for Control Applications (TCC6) */
+  void* pfnADC_REQ0_Handler;                     /* 130 ADC Controller (ADC) */
+  void* pfnADC_REQ1_Handler;                     /* 131 ADC Controller (ADC) */
+  void* pfnAC_Handler;                           /* 132 Analog Comparator Controller (AC) */
+  void* pfnPTC_Handler;                          /* 133 Polaris Peripheral Touch Controller (PTC) */
+  void* pfnUSB_EORSMDNRSM_Handler;               /* 134 Full-Speed Universal Serial Bus (USB) */
+  void* pfnUSB_SOFHSOF_Handler;                  /* 135 Full-Speed Universal Serial Bus (USB) */
+  void* pfnUSB_TRCPT00_Handler;                  /* 136 Full-Speed Universal Serial Bus (USB) */
+  void* pfnUSB_TRCPT10_Handler;                  /* 137 Full-Speed Universal Serial Bus (USB) */
+  void* pfnAT_Handler;                           /* 138 Anti-Tamper Controller (AT) (AT) */
+} DeviceVectors;
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS
+/* CORTEX-M23 exception handlers */
+void Reset_Handler                 ( void );
+void NonMaskableInt_Handler        ( void );
+void HardFault_Handler             ( void );
+void SVCall_Handler                ( void );
+void PendSV_Handler                ( void );
+void SysTick_Handler               ( void );
+#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */
+
+#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
+/* Peripherals interrupt handlers */
+void FCR_Handler                   ( void );
+void FCW_Handler                   ( void );
+void PM_Handler                    ( void );
+void SUPC_Handler                  ( void );
+void OSCCTRL_XOSCRDY_Handler       ( void );
+void OSCCTRL_DFLLRDY_Handler       ( void );
+void OSCCTRL_PLLLOCKR_0_Handler    ( void );
+void OSC32KCTRL_XOSC32KRDY_Handler ( void );
+void OSC32KCTRL_XOSC32KFAIL_Handler( void );
+void MCLK_Handler                  ( void );
+void FREQM_Handler                 ( void );
+void WDT_Handler                   ( void );
+void RTC_TAMPER_Handler            ( void );
+void RTC_OVF_Handler               ( void );
+void RTC_PER0_Handler              ( void );
+void RTC_CMP0_Handler              ( void );
+void EIC_EXTINT0_Handler           ( void );
+void EIC_EXTINT1_Handler           ( void );
+void EIC_EXTINT2_Handler           ( void );
+void EIC_EXTINT3_Handler           ( void );
+void EIC_EXTINT4_Handler           ( void );
+void EIC_EXTINT5_Handler           ( void );
+void EIC_EXTINT6_Handler           ( void );
+void EIC_EXTINT7_Handler           ( void );
+void EIC_EXTINT8_Handler           ( void );
+void EIC_EXTINT9_Handler           ( void );
+void EIC_EXTINT10_Handler          ( void );
+void EIC_EXTINT11_Handler          ( void );
+void EIC_EXTINT12_Handler          ( void );
+void EIC_EXTINT13_Handler          ( void );
+void EIC_EXTINT14_Handler          ( void );
+void EIC_EXTINT15_Handler          ( void );
+void EIC_NSCHK_Handler             ( void );
+void MCRAMC_Handler                ( void );
+void CAN0_INT0_Handler             ( void );
+void CAN0_INT1_Handler             ( void );
+void CAN0_BERR_Handler             ( void );
+void CAN1_INT0_Handler             ( void );
+void CAN1_INT1_Handler             ( void );
+void CAN1_BERR_Handler             ( void );
+void PORT_Handler                  ( void );
+void DMAC_TCMPL0_Handler           ( void );
+void DMAC_TCMPL1_Handler           ( void );
+void DMAC_TCMPL2_Handler           ( void );
+void DMAC_TCMPL3_Handler           ( void );
+void DMAC_TCMPL4_Handler           ( void );
+void HMATRIX2_Handler              ( void );
+void EVSYS_EVD0_Handler            ( void );
+void EVSYS_EVD1_Handler            ( void );
+void EVSYS_EVD2_Handler            ( void );
+void EVSYS_EVD3_Handler            ( void );
+void EVSYS_EVD4_Handler            ( void );
+void EVSYS_EVD5_Handler            ( void );
+void EVSYS_EVD6_Handler            ( void );
+void EVSYS_EVD7_Handler            ( void );
+void EVSYS_EVD8_Handler            ( void );
+void EVSYS_EVD9_Handler            ( void );
+void EVSYS_EVD10_Handler           ( void );
+void EVSYS_EVD11_Handler           ( void );
+void SERCOM0_6_Handler             ( void );
+void SERCOM0_5_Handler             ( void );
+void SERCOM0_0_Handler             ( void );
+void SERCOM0_1_Handler             ( void );
+void SERCOM0_2_Handler             ( void );
+void SERCOM0_3_Handler             ( void );
+void SERCOM0_4_Handler             ( void );
+void SERCOM1_6_Handler             ( void );
+void SERCOM1_5_Handler             ( void );
+void SERCOM1_0_Handler             ( void );
+void SERCOM1_1_Handler             ( void );
+void SERCOM1_2_Handler             ( void );
+void SERCOM1_3_Handler             ( void );
+void SERCOM1_4_Handler             ( void );
+void SERCOM2_6_Handler             ( void );
+void SERCOM2_5_Handler             ( void );
+void SERCOM2_0_Handler             ( void );
+void SERCOM2_1_Handler             ( void );
+void SERCOM2_2_Handler             ( void );
+void SERCOM2_3_Handler             ( void );
+void SERCOM2_4_Handler             ( void );
+void SERCOM3_6_Handler             ( void );
+void SERCOM3_5_Handler             ( void );
+void SERCOM3_0_Handler             ( void );
+void SERCOM3_1_Handler             ( void );
+void SERCOM3_2_Handler             ( void );
+void SERCOM3_3_Handler             ( void );
+void SERCOM3_4_Handler             ( void );
+void TCC0_DFS_Handler              ( void );
+void TCC0_CNT_Handler              ( void );
+void TCC0_MC0_Handler              ( void );
+void TCC0_MC1_Handler              ( void );
+void TCC1_DFS_Handler              ( void );
+void TCC1_CNT_Handler              ( void );
+void TCC1_MC0_Handler              ( void );
+void TCC1_MC1_Handler              ( void );
+void TCC2_DFS_Handler              ( void );
+void TCC2_CNT_Handler              ( void );
+void TCC2_MC0_Handler              ( void );
+void TCC2_MC1_Handler              ( void );
+void TCC3_DFS_Handler              ( void );
+void TCC3_CNT_Handler              ( void );
+void TCC3_MC0_Handler              ( void );
+void TCC3_MC1_Handler              ( void );
+void SERCOM4_6_Handler             ( void );
+void SERCOM4_5_Handler             ( void );
+void SERCOM4_0_Handler             ( void );
+void SERCOM4_1_Handler             ( void );
+void SERCOM4_2_Handler             ( void );
+void SERCOM4_3_Handler             ( void );
+void SERCOM4_4_Handler             ( void );
+void SERCOM5_6_Handler             ( void );
+void SERCOM5_5_Handler             ( void );
+void SERCOM5_0_Handler             ( void );
+void SERCOM5_1_Handler             ( void );
+void SERCOM5_2_Handler             ( void );
+void SERCOM5_3_Handler             ( void );
+void SERCOM5_4_Handler             ( void );
+void TCC4_DFS_Handler              ( void );
+void TCC4_CNT_Handler              ( void );
+void TCC4_MC0_Handler              ( void );
+void TCC4_MC1_Handler              ( void );
+void TCC5_DFS_Handler              ( void );
+void TCC5_CNT_Handler              ( void );
+void TCC5_MC0_Handler              ( void );
+void TCC5_MC1_Handler              ( void );
+void TCC6_DFS_Handler              ( void );
+void TCC6_CNT_Handler              ( void );
+void TCC6_MC0_Handler              ( void );
+void TCC6_MC1_Handler              ( void );
+void ADC_REQ0_Handler              ( void );
+void ADC_REQ1_Handler              ( void );
+void AC_Handler                    ( void );
+void PTC_Handler                   ( void );
+void USB_EORSMDNRSM_Handler        ( void );
+void USB_SOFHSOF_Handler           ( void );
+void USB_TRCPT00_Handler           ( void );
+void USB_TRCPT10_Handler           ( void );
+void AT_Handler                    ( void );
+#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* Configuration of the CORTEX-M23 Processor and Core Peripherals */
+#define __CM23_REV                    0x0000 /* Cortex-M23 Core Revision                                                  */
+#define __FPU_PRESENT                      0 /* No FPU                                                                    */
+#define __MPU_PRESENT                      1 /* MPU implemented                                                           */
+#define __NVIC_PRIO_BITS                   2 /* Number of NVIC Priority Bits                                              */
+#define __SAUREGION_PRESENT                0 /* Number of Security Attribute Unit Regions (No SAU)                        */
+#define __VTOR_PRESENT                     1 /* Include Vector Table Offset Register                                      */
+#define __Vendor_SysTickConfig             0 /* Standard SYSTICK used                                                     */
+#define __ARCH_ARM                         1
+#define __ARCH_ARM_CORTEX_M                1
+
+/* CMSIS includes */
+#include "core_cm23.h"
+#if defined USE_CMSIS_INIT
+#include "system_pic32cmgc00.h"
+#endif /* USE_CMSIS_INIT */
+
+/* ************************************************************************** */
+/*         SOFTWARE PERIPHERAL API DEFINITIONS FOR PIC32CM5112GC00048         */
+/* ************************************************************************** */
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/at.h"
+#include "component/bromc.h"
+#include "component/can.h"
+#include "component/ccl.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/fcr.h"
+#include "component/fcw.h"
+#include "component/freqm.h"
+#include "component/fuses.h"
+#include "component/gclk.h"
+#include "component/h2pb.h"
+#include "component/hmatrix2.h"
+#include "component/mclk.h"
+#include "component/mcramc.h"
+#include "component/osc32kctrl.h"
+#include "component/oscctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/ptc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+
+/* ************************************************************************** */
+/*                INSTANCE DEFINITIONS FOR PIC32CM5112GC00048                 */
+/* ************************************************************************** */
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/at.h"
+#include "instance/bromc.h"
+#include "instance/can0.h"
+#include "instance/can1.h"
+#include "instance/ccl0.h"
+#include "instance/ccl1.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/fcr.h"
+#include "instance/fcw.h"
+#include "instance/freqm.h"
+#include "instance/fuses.h"
+#include "instance/gclk.h"
+#include "instance/h2pb0.h"
+#include "instance/h2pb1.h"
+#include "instance/h2pb2.h"
+#include "instance/hmatrix2.h"
+#include "instance/mclk.h"
+#include "instance/mcramc.h"
+#include "instance/osc32kctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/pac.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/ptc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/supc.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/tcc5.h"
+#include "instance/tcc6.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+
+/* ************************************************************************** */
+/*              PERIPHERAL ID DEFINITIONS FOR PIC32CM5112GC00048              */
+/* ************************************************************************** */
+#define ID_DSU           (  0) /* Instance index for DSU (DSU) */
+#define ID_FCR           (  1) /* Instance index for FCR (FCR) */
+#define ID_FCW           (  2) /* Instance index for FCW (FCW) */
+#define ID_PM            (  3) /* Instance index for PM (PM) */
+#define ID_SUPC          (  4) /* Instance index for SUPC (SUPC) */
+#define ID_RSTC          (  5) /* Instance index for RSTC (RSTC) */
+#define ID_OSCCTRL       (  6) /* Instance index for OSCCTRL (OSCCTRL) */
+#define ID_OSC32KCTRL    (  7) /* Instance index for OSC32KCTRL (OSC32KCTRL) */
+#define ID_GCLK          (  8) /* Instance index for GCLK (GCLK) */
+#define ID_MCLK          (  9) /* Instance index for MCLK (MCLK) */
+#define ID_FREQM         ( 10) /* Instance index for FREQM (FREQM) */
+#define ID_WDT           ( 11) /* Instance index for WDT (WDT) */
+#define ID_RTC           ( 12) /* Instance index for RTC (RTC) */
+#define ID_EIC           ( 13) /* Instance index for EIC (EIC) */
+#define ID_PAC           ( 14) /* Instance index for PAC (PAC) */
+#define ID_MCRAMC        ( 16) /* Instance index for MCRAMC (MCRAMC) */
+#define ID_CAN0          ( 17) /* Instance index for CAN0 (CAN0) */
+#define ID_CAN1          ( 18) /* Instance index for CAN1 (CAN1) */
+#define ID_H2PB0         ( 19) /* Instance index for H2PB0 (H2PB0) */
+#define ID_PORT          ( 20) /* Instance index for PORT (PORT) */
+#define ID_DMAC          ( 21) /* Instance index for DMAC (DMAC) */
+#define ID_HMATRIX2      ( 22) /* Instance index for HMATRIX2 (HMATRIX2) */
+#define ID_BROMC         ( 23) /* Instance index for BROMC (BROMC) */
+#define ID_EVSYS         ( 25) /* Instance index for EVSYS (EVSYS) */
+#define ID_SERCOM0       ( 26) /* Instance index for SERCOM0 (SERCOM0) */
+#define ID_SERCOM1       ( 27) /* Instance index for SERCOM1 (SERCOM1) */
+#define ID_SERCOM2       ( 28) /* Instance index for SERCOM2 (SERCOM2) */
+#define ID_SERCOM3       ( 29) /* Instance index for SERCOM3 (SERCOM3) */
+#define ID_TCC0          ( 30) /* Instance index for TCC0 (TCC0) */
+#define ID_TCC1          ( 31) /* Instance index for TCC1 (TCC1) */
+#define ID_TCC2          ( 32) /* Instance index for TCC2 (TCC2) */
+#define ID_TCC3          ( 33) /* Instance index for TCC3 (TCC3) */
+#define ID_SERCOM4       ( 34) /* Instance index for SERCOM4 (SERCOM4) */
+#define ID_SERCOM5       ( 35) /* Instance index for SERCOM5 (SERCOM5) */
+#define ID_TCC4          ( 36) /* Instance index for TCC4 (TCC4) */
+#define ID_TCC5          ( 37) /* Instance index for TCC5 (TCC5) */
+#define ID_TCC6          ( 38) /* Instance index for TCC6 (TCC6) */
+#define ID_ADC           ( 39) /* Instance index for ADC (ADC) */
+#define ID_AC            ( 40) /* Instance index for AC (AC) */
+#define ID_PTC           ( 41) /* Instance index for PTC (PTC) */
+#define ID_CCL0          ( 42) /* Instance index for CCL0 (CCL0) */
+#define ID_CCL1          ( 43) /* Instance index for CCL1 (CCL1) */
+#define ID_USB           ( 44) /* Instance index for USB (USB) */
+#define ID_AT            ( 45) /* Instance index for AT (AT) */
+#define ID_H2PB1         ( 46) /* Instance index for H2PB1 (H2PB1) */
+#define ID_H2PB2         ( 47) /* Instance index for H2PB2 (H2PB2) */
+
+#define ID_PERIPH_MAX    ( 47) /* Number of peripheral IDs */
+
+/* ************************************************************************** */
+/*       REGISTER STRUCTURE ADDRESS DEFINITIONS FOR PIC32CM5112GC00048        */
+/* ************************************************************************** */
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#define AC_REGS                          ((ac_registers_t*)0x4482a000)                 /* AC Registers Address         */
+#define ADC_REGS                         ((adc_registers_t*)0x44818000)                /* ADC Registers Address        */
+#define AT_REGS                          ((at_registers_t*)0x4500c000)                 /* AT Registers Address         */
+#define BROMC_REGS                       ((bromc_registers_t*)0x44804000)              /* BROMC Registers Address      */
+#define CAN0_REGS                        ((can_registers_t*)0x4402e000)                /* CAN0 Registers Address       */
+#define CAN1_REGS                        ((can_registers_t*)0x44030000)                /* CAN1 Registers Address       */
+#define CCL0_REGS                        ((ccl_registers_t*)0x4482e000)                /* CCL0 Registers Address       */
+#define CCL1_REGS                        ((ccl_registers_t*)0x44830000)                /* CCL1 Registers Address       */
+#define DMAC_REGS                        ((dmac_registers_t*)0x44802000)               /* DMAC Registers Address       */
+#define DSU_REGS                         ((dsu_registers_t*)0x44000000)                /* DSU Registers Address        */
+#define EIC_REGS                         ((eic_registers_t*)0x44020000)                /* EIC Registers Address        */
+#define EVSYS_REGS                       ((evsys_registers_t*)0x44806000)              /* EVSYS Registers Address      */
+#define FCR_REGS                         ((fcr_registers_t*)0x44002000)                /* FCR Registers Address        */
+#define FCW_REGS                         ((fcw_registers_t*)0x44004000)                /* FCW Registers Address        */
+#define FREQM_REGS                       ((freqm_registers_t*)0x4400c000)              /* FREQM Registers Address      */
+#define FUSES_ROMCFG_REGS                ((fuses_romcfg_registers_t*)0x0a003000)       /* FUSES Registers Address      */
+#define FUSES_BOOTCFG1_REGS              ((fuses_bootcfg1_registers_t*)0x0a002000)     /* FUSES Registers Address      */
+#define FUSES_BOOTCFG1A_REGS             ((fuses_bootcfg1_registers_t*)0x0a000000)     /* FUSES Registers Address      */
+#define FUSES_CALOTP_REGS                ((fuses_calotp_registers_t*)0x0a007000)       /* FUSES Registers Address      */
+#define GCLK_REGS                        ((gclk_registers_t*)0x44008000)               /* GCLK Registers Address       */
+#define H2PB0_REGS                       ((h2pb_registers_t*)0x44032000)               /* H2PB0 Registers Address      */
+#define H2PB1_REGS                       ((h2pb_registers_t*)0x44838000)               /* H2PB1 Registers Address      */
+#define H2PB2_REGS                       ((h2pb_registers_t*)0x4500e000)               /* H2PB2 Registers Address      */
+#define HMATRIX2_REGS                    ((hmatrix2_registers_t*)0x44010000)           /* HMATRIX2 Registers Address   */
+#define MCLK_REGS                        ((mclk_registers_t*)0x4400a000)               /* MCLK Registers Address       */
+#define MCRAMC_REGS                      ((mcramc_registers_t*)0x4402c000)             /* MCRAMC Registers Address     */
+#define OSC32KCTRL_REGS                  ((osc32kctrl_registers_t*)0x45008000)         /* OSC32KCTRL Registers Address */
+#define OSCCTRL_REGS                     ((oscctrl_registers_t*)0x44006000)            /* OSCCTRL Registers Address    */
+#define PAC_REGS                         ((pac_registers_t*)0x44022000)                /* PAC Registers Address        */
+#define PM_REGS                          ((pm_registers_t*)0x45000000)                 /* PM Registers Address         */
+#define PORT_REGS                        ((port_registers_t*)0x44800000)               /* PORT Registers Address       */
+#define PTC_REGS                         ((ptc_registers_t*)0x4482c000)                /* PTC Registers Address        */
+#define RSTC_REGS                        ((rstc_registers_t*)0x45004000)               /* RSTC Registers Address       */
+#define RTC_REGS                         ((rtc_registers_t*)0x45006000)                /* RTC Registers Address        */
+#define SERCOM0_REGS                     ((sercom_registers_t*)0x44808000)             /* SERCOM0 Registers Address    */
+#define SERCOM1_REGS                     ((sercom_registers_t*)0x4480a000)             /* SERCOM1 Registers Address    */
+#define SERCOM2_REGS                     ((sercom_registers_t*)0x4480c000)             /* SERCOM2 Registers Address    */
+#define SERCOM3_REGS                     ((sercom_registers_t*)0x4480e000)             /* SERCOM3 Registers Address    */
+#define SERCOM4_REGS                     ((sercom_registers_t*)0x44820000)             /* SERCOM4 Registers Address    */
+#define SERCOM5_REGS                     ((sercom_registers_t*)0x44822000)             /* SERCOM5 Registers Address    */
+#define SUPC_REGS                        ((supc_registers_t*)0x45002000)               /* SUPC Registers Address       */
+#define TCC0_REGS                        ((tcc_registers_t*)0x44810000)                /* TCC0 Registers Address       */
+#define TCC1_REGS                        ((tcc_registers_t*)0x44812000)                /* TCC1 Registers Address       */
+#define TCC2_REGS                        ((tcc_registers_t*)0x44814000)                /* TCC2 Registers Address       */
+#define TCC3_REGS                        ((tcc_registers_t*)0x44816000)                /* TCC3 Registers Address       */
+#define TCC4_REGS                        ((tcc_registers_t*)0x44824000)                /* TCC4 Registers Address       */
+#define TCC5_REGS                        ((tcc_registers_t*)0x44826000)                /* TCC5 Registers Address       */
+#define TCC6_REGS                        ((tcc_registers_t*)0x44828000)                /* TCC6 Registers Address       */
+#define USB_REGS                         ((usb_registers_t*)0x44832000)                /* USB Registers Address        */
+#define WDT_REGS                         ((wdt_registers_t*)0x4400e000)                /* WDT Registers Address        */
+#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ************************************************************************** */
+/*              BASE ADDRESS DEFINITIONS FOR PIC32CM5112GC00048               */
+/* ************************************************************************** */
+#define AC_BASE_ADDRESS                  _UINT32_(0x4482a000)                          /* AC Base Address */
+#define ADC_BASE_ADDRESS                 _UINT32_(0x44818000)                          /* ADC Base Address */
+#define AT_BASE_ADDRESS                  _UINT32_(0x4500c000)                          /* AT Base Address */
+#define BROMC_BASE_ADDRESS               _UINT32_(0x44804000)                          /* BROMC Base Address */
+#define CAN0_BASE_ADDRESS                _UINT32_(0x4402e000)                          /* CAN0 Base Address */
+#define CAN1_BASE_ADDRESS                _UINT32_(0x44030000)                          /* CAN1 Base Address */
+#define CCL0_BASE_ADDRESS                _UINT32_(0x4482e000)                          /* CCL0 Base Address */
+#define CCL1_BASE_ADDRESS                _UINT32_(0x44830000)                          /* CCL1 Base Address */
+#define DMAC_BASE_ADDRESS                _UINT32_(0x44802000)                          /* DMAC Base Address */
+#define DSU_BASE_ADDRESS                 _UINT32_(0x44000000)                          /* DSU Base Address */
+#define EIC_BASE_ADDRESS                 _UINT32_(0x44020000)                          /* EIC Base Address */
+#define EVSYS_BASE_ADDRESS               _UINT32_(0x44806000)                          /* EVSYS Base Address */
+#define FCR_BASE_ADDRESS                 _UINT32_(0x44002000)                          /* FCR Base Address */
+#define FCW_BASE_ADDRESS                 _UINT32_(0x44004000)                          /* FCW Base Address */
+#define FREQM_BASE_ADDRESS               _UINT32_(0x4400c000)                          /* FREQM Base Address */
+#define FUSES_ROMCFG_BASE_ADDRESS        _UINT32_(0x0a003000)                          /* FUSES Base Address */
+#define FUSES_BOOTCFG1_BASE_ADDRESS      _UINT32_(0x0a002000)                          /* FUSES Base Address */
+#define FUSES_BOOTCFG1A_BASE_ADDRESS     _UINT32_(0x0a000000)                          /* FUSES Base Address */
+#define FUSES_CALOTP_BASE_ADDRESS        _UINT32_(0x0a007000)                          /* FUSES Base Address */
+#define GCLK_BASE_ADDRESS                _UINT32_(0x44008000)                          /* GCLK Base Address */
+#define H2PB0_BASE_ADDRESS               _UINT32_(0x44032000)                          /* H2PB0 Base Address */
+#define H2PB1_BASE_ADDRESS               _UINT32_(0x44838000)                          /* H2PB1 Base Address */
+#define H2PB2_BASE_ADDRESS               _UINT32_(0x4500e000)                          /* H2PB2 Base Address */
+#define HMATRIX2_BASE_ADDRESS            _UINT32_(0x44010000)                          /* HMATRIX2 Base Address */
+#define MCLK_BASE_ADDRESS                _UINT32_(0x4400a000)                          /* MCLK Base Address */
+#define MCRAMC_BASE_ADDRESS              _UINT32_(0x4402c000)                          /* MCRAMC Base Address */
+#define OSC32KCTRL_BASE_ADDRESS          _UINT32_(0x45008000)                          /* OSC32KCTRL Base Address */
+#define OSCCTRL_BASE_ADDRESS             _UINT32_(0x44006000)                          /* OSCCTRL Base Address */
+#define PAC_BASE_ADDRESS                 _UINT32_(0x44022000)                          /* PAC Base Address */
+#define PM_BASE_ADDRESS                  _UINT32_(0x45000000)                          /* PM Base Address */
+#define PORT_BASE_ADDRESS                _UINT32_(0x44800000)                          /* PORT Base Address */
+#define PTC_BASE_ADDRESS                 _UINT32_(0x4482c000)                          /* PTC Base Address */
+#define RSTC_BASE_ADDRESS                _UINT32_(0x45004000)                          /* RSTC Base Address */
+#define RTC_BASE_ADDRESS                 _UINT32_(0x45006000)                          /* RTC Base Address */
+#define SERCOM0_BASE_ADDRESS             _UINT32_(0x44808000)                          /* SERCOM0 Base Address */
+#define SERCOM1_BASE_ADDRESS             _UINT32_(0x4480a000)                          /* SERCOM1 Base Address */
+#define SERCOM2_BASE_ADDRESS             _UINT32_(0x4480c000)                          /* SERCOM2 Base Address */
+#define SERCOM3_BASE_ADDRESS             _UINT32_(0x4480e000)                          /* SERCOM3 Base Address */
+#define SERCOM4_BASE_ADDRESS             _UINT32_(0x44820000)                          /* SERCOM4 Base Address */
+#define SERCOM5_BASE_ADDRESS             _UINT32_(0x44822000)                          /* SERCOM5 Base Address */
+#define SUPC_BASE_ADDRESS                _UINT32_(0x45002000)                          /* SUPC Base Address */
+#define TCC0_BASE_ADDRESS                _UINT32_(0x44810000)                          /* TCC0 Base Address */
+#define TCC1_BASE_ADDRESS                _UINT32_(0x44812000)                          /* TCC1 Base Address */
+#define TCC2_BASE_ADDRESS                _UINT32_(0x44814000)                          /* TCC2 Base Address */
+#define TCC3_BASE_ADDRESS                _UINT32_(0x44816000)                          /* TCC3 Base Address */
+#define TCC4_BASE_ADDRESS                _UINT32_(0x44824000)                          /* TCC4 Base Address */
+#define TCC5_BASE_ADDRESS                _UINT32_(0x44826000)                          /* TCC5 Base Address */
+#define TCC6_BASE_ADDRESS                _UINT32_(0x44828000)                          /* TCC6 Base Address */
+#define USB_BASE_ADDRESS                 _UINT32_(0x44832000)                          /* USB Base Address */
+#define WDT_BASE_ADDRESS                 _UINT32_(0x4400e000)                          /* WDT Base Address */
+
+/* ************************************************************************** */
+/*                   PIO DEFINITIONS FOR PIC32CM5112GC00048                   */
+/* ************************************************************************** */
+#include "pio/pic32cm5112gc00048.h"
+
+/* ************************************************************************** */
+/*             MEMORY MAPPING DEFINITIONS FOR PIC32CM5112GC00048              */
+/* ************************************************************************** */
+#define BROMC_ROM_SIZE                 _UINT32_(0x00010000)    /*   64kB Memory segment type: rom */
+#define FCR_BFM_SIZE                   _UINT32_(0x00004000)    /*   16kB Memory segment type: flash */
+#define FCR_CFM_BOOTCFG1A_SIZE         _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_USEROTP_SIZE           _UINT32_(0x00001000)    /*    4kB Memory segment type: user_signatures */
+#define FCR_CFM_BOOTCFG1_SIZE          _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_ROMCFG_SIZE            _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_VSS0_SIZE              _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_VSS1_SIZE              _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_TEST_SIZE              _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_CALOTP_SIZE            _UINT32_(0x00001000)    /*    4kB Memory segment type: other */
+#define FCR_PFM_SIZE                   _UINT32_(0x00080000)    /*  512kB Memory segment type: flash */
+#define MCRAMC_RET_SIZE                _UINT32_(0x00020000)    /*  128kB Memory segment type: ram */
+#define APB0_BRIDGE_SIZE               _UINT32_(0x00034000)    /*  208kB Memory segment type: io */
+#define APB1_BRIDGE_SIZE               _UINT32_(0x0003a000)    /*  232kB Memory segment type: io */
+#define APB2_BRIDGE_SIZE               _UINT32_(0x00010000)    /*   64kB Memory segment type: io */
+#define PPB_SIZE                       _UINT32_(0x00100000)    /* 1024kB Memory segment type: io */
+
+#define BROMC_ROM_ADDR                 _UINT32_(0x04000000)    /* BROMC_ROM base address (type: rom)*/
+#define FCR_BFM_ADDR                   _UINT32_(0x08000000)    /* FCR_BFM base address (type: flash)*/
+#define FCR_CFM_BOOTCFG1A_ADDR         _UINT32_(0x0a000000)    /* FCR_CFM_BOOTCFG1A base address (type: flash)*/
+#define FCR_CFM_USEROTP_ADDR           _UINT32_(0x0a001000)    /* FCR_CFM_USEROTP base address (type: user_signatures)*/
+#define FCR_CFM_BOOTCFG1_ADDR          _UINT32_(0x0a002000)    /* FCR_CFM_BOOTCFG1 base address (type: flash)*/
+#define FCR_CFM_ROMCFG_ADDR            _UINT32_(0x0a003000)    /* FCR_CFM_ROMCFG base address (type: flash)*/
+#define FCR_CFM_VSS0_ADDR              _UINT32_(0x0a004000)    /* FCR_CFM_VSS0 base address (type: flash)*/
+#define FCR_CFM_VSS1_ADDR              _UINT32_(0x0a005000)    /* FCR_CFM_VSS1 base address (type: flash)*/
+#define FCR_CFM_TEST_ADDR              _UINT32_(0x0a006000)    /* FCR_CFM_TEST base address (type: flash)*/
+#define FCR_CFM_CALOTP_ADDR            _UINT32_(0x0a007000)    /* FCR_CFM_CALOTP base address (type: other)*/
+#define FCR_PFM_ADDR                   _UINT32_(0x0c000000)    /* FCR_PFM base address (type: flash)*/
+#define MCRAMC_RET_ADDR                _UINT32_(0x20000000)    /* MCRAMC_RET base address (type: ram)*/
+#define APB0_BRIDGE_ADDR               _UINT32_(0x44000000)    /* APB0_BRIDGE base address (type: io)*/
+#define APB1_BRIDGE_ADDR               _UINT32_(0x44800000)    /* APB1_BRIDGE base address (type: io)*/
+#define APB2_BRIDGE_ADDR               _UINT32_(0x45000000)    /* APB2_BRIDGE base address (type: io)*/
+#define PPB_ADDR                       _UINT32_(0xe0000000)    /* PPB base address (type: io)*/
+
+/* ************************************************************************** */
+/*                  DEVICE SIGNATURES FOR PIC32CM5112GC00048                  */
+/* ************************************************************************** */
+#define CHIP_DSU_DID                   _UINT32_(0X0AC02053)
+
+/* ************************************************************************** */
+/*               ELECTRICAL DEFINITIONS FOR PIC32CM5112GC00048                */
+/* ************************************************************************** */
+
+/* ************************************************************************** */
+/*                  Event Generator IDs for C32CM5112GC00048                  */
+/* ************************************************************************** */
+#define EVENT_ID_GEN_SUPC_LVDET                           1 /* ID for SUPC event generator LVDET */
+#define EVENT_ID_GEN_OSCCTRL_XOSCFAIL                     2 /* ID for OSCCTRL event generator XOSCFAIL */
+#define EVENT_ID_GEN_OSC32KCTRL_XOSC32KFAIL               3 /* ID for OSC32KCTRL event generator XOSC32KFAIL */
+#define EVENT_ID_GEN_FREQM_DONE                           4 /* ID for FREQM event generator DONE */
+#define EVENT_ID_GEN_FREQM_WINMON                         5 /* ID for FREQM event generator WINMON */
+#define EVENT_ID_GEN_RTC_PER0                             6 /* ID for RTC event generator PER0 */
+#define EVENT_ID_GEN_RTC_PER1                             7 /* ID for RTC event generator PER1 */
+#define EVENT_ID_GEN_RTC_PER2                             8 /* ID for RTC event generator PER2 */
+#define EVENT_ID_GEN_RTC_PER3                             9 /* ID for RTC event generator PER3 */
+#define EVENT_ID_GEN_RTC_PER4                            10 /* ID for RTC event generator PER4 */
+#define EVENT_ID_GEN_RTC_PER5                            11 /* ID for RTC event generator PER5 */
+#define EVENT_ID_GEN_RTC_PER6                            12 /* ID for RTC event generator PER6 */
+#define EVENT_ID_GEN_RTC_PER7                            13 /* ID for RTC event generator PER7 */
+#define EVENT_ID_GEN_RTC_CMP0                            14 /* ID for RTC event generator CMP0 */
+#define EVENT_ID_GEN_RTC_CMP1                            15 /* ID for RTC event generator CMP1 */
+#define EVENT_ID_GEN_RTC_CMP2                            16 /* ID for RTC event generator CMP2 */
+#define EVENT_ID_GEN_RTC_CMP3                            17 /* ID for RTC event generator CMP3 */
+#define EVENT_ID_GEN_RTC_TAMPER                          18 /* ID for RTC event generator TAMPER */
+#define EVENT_ID_GEN_RTC_OVF                             19 /* ID for RTC event generator OVF */
+#define EVENT_ID_GEN_RTC_PERD                            20 /* ID for RTC event generator PERD */
+#define EVENT_ID_GEN_EIC_EXTINT0                         21 /* ID for EIC event generator EXTINT0 */
+#define EVENT_ID_GEN_EIC_EXTINT1                         22 /* ID for EIC event generator EXTINT1 */
+#define EVENT_ID_GEN_EIC_EXTINT2                         23 /* ID for EIC event generator EXTINT2 */
+#define EVENT_ID_GEN_EIC_EXTINT3                         24 /* ID for EIC event generator EXTINT3 */
+#define EVENT_ID_GEN_EIC_EXTINT4                         25 /* ID for EIC event generator EXTINT4 */
+#define EVENT_ID_GEN_EIC_EXTINT5                         26 /* ID for EIC event generator EXTINT5 */
+#define EVENT_ID_GEN_EIC_EXTINT6                         27 /* ID for EIC event generator EXTINT6 */
+#define EVENT_ID_GEN_EIC_EXTINT7                         28 /* ID for EIC event generator EXTINT7 */
+#define EVENT_ID_GEN_EIC_EXTINT8                         29 /* ID for EIC event generator EXTINT8 */
+#define EVENT_ID_GEN_EIC_EXTINT9                         30 /* ID for EIC event generator EXTINT9 */
+#define EVENT_ID_GEN_EIC_EXTINT10                        31 /* ID for EIC event generator EXTINT10 */
+#define EVENT_ID_GEN_EIC_EXTINT11                        32 /* ID for EIC event generator EXTINT11 */
+#define EVENT_ID_GEN_EIC_EXTINT12                        33 /* ID for EIC event generator EXTINT12 */
+#define EVENT_ID_GEN_EIC_EXTINT13                        34 /* ID for EIC event generator EXTINT13 */
+#define EVENT_ID_GEN_EIC_EXTINT14                        35 /* ID for EIC event generator EXTINT14 */
+#define EVENT_ID_GEN_EIC_EXTINT15                        36 /* ID for EIC event generator EXTINT15 */
+#define EVENT_ID_GEN_DMAC_CH0                            37 /* ID for DMAC event generator CH0 */
+#define EVENT_ID_GEN_DMAC_CH1                            38 /* ID for DMAC event generator CH1 */
+#define EVENT_ID_GEN_DMAC_CH2                            39 /* ID for DMAC event generator CH2 */
+#define EVENT_ID_GEN_DMAC_CH3                            40 /* ID for DMAC event generator CH3 */
+#define EVENT_ID_GEN_TCC0_OVF                            41 /* ID for TCC0 event generator OVF */
+#define EVENT_ID_GEN_TCC0_TRG                            42 /* ID for TCC0 event generator TRG */
+#define EVENT_ID_GEN_TCC0_CNT                            43 /* ID for TCC0 event generator CNT */
+#define EVENT_ID_GEN_TCC0_MC0                            44 /* ID for TCC0 event generator MC0 */
+#define EVENT_ID_GEN_TCC0_MC1                            45 /* ID for TCC0 event generator MC1 */
+#define EVENT_ID_GEN_TCC1_OVF                            46 /* ID for TCC1 event generator OVF */
+#define EVENT_ID_GEN_TCC1_TRG                            47 /* ID for TCC1 event generator TRG */
+#define EVENT_ID_GEN_TCC1_CNT                            48 /* ID for TCC1 event generator CNT */
+#define EVENT_ID_GEN_TCC1_MC0                            49 /* ID for TCC1 event generator MC0 */
+#define EVENT_ID_GEN_TCC1_MC1                            50 /* ID for TCC1 event generator MC1 */
+#define EVENT_ID_GEN_TCC2_OVF                            51 /* ID for TCC2 event generator OVF */
+#define EVENT_ID_GEN_TCC2_TRG                            52 /* ID for TCC2 event generator TRG */
+#define EVENT_ID_GEN_TCC2_CNT                            53 /* ID for TCC2 event generator CNT */
+#define EVENT_ID_GEN_TCC2_MC0                            54 /* ID for TCC2 event generator MC0 */
+#define EVENT_ID_GEN_TCC2_MC1                            55 /* ID for TCC2 event generator MC1 */
+#define EVENT_ID_GEN_TCC3_OVF                            56 /* ID for TCC3 event generator OVF */
+#define EVENT_ID_GEN_TCC3_TRG                            57 /* ID for TCC3 event generator TRG */
+#define EVENT_ID_GEN_TCC3_CNT                            58 /* ID for TCC3 event generator CNT */
+#define EVENT_ID_GEN_TCC3_MC0                            59 /* ID for TCC3 event generator MC0 */
+#define EVENT_ID_GEN_TCC3_MC1                            60 /* ID for TCC3 event generator MC1 */
+#define EVENT_ID_GEN_TCC4_OVF                            61 /* ID for TCC4 event generator OVF */
+#define EVENT_ID_GEN_TCC4_TRG                            62 /* ID for TCC4 event generator TRG */
+#define EVENT_ID_GEN_TCC4_CNT                            63 /* ID for TCC4 event generator CNT */
+#define EVENT_ID_GEN_TCC4_MC0                            64 /* ID for TCC4 event generator MC0 */
+#define EVENT_ID_GEN_TCC4_MC1                            65 /* ID for TCC4 event generator MC1 */
+#define EVENT_ID_GEN_TCC5_OVF                            66 /* ID for TCC5 event generator OVF */
+#define EVENT_ID_GEN_TCC5_TRG                            67 /* ID for TCC5 event generator TRG */
+#define EVENT_ID_GEN_TCC5_CNT                            68 /* ID for TCC5 event generator CNT */
+#define EVENT_ID_GEN_TCC5_MC0                            69 /* ID for TCC5 event generator MC0 */
+#define EVENT_ID_GEN_TCC5_MC1                            70 /* ID for TCC5 event generator MC1 */
+#define EVENT_ID_GEN_TCC6_OVF                            71 /* ID for TCC6 event generator OVF */
+#define EVENT_ID_GEN_TCC6_TRG                            72 /* ID for TCC6 event generator TRG */
+#define EVENT_ID_GEN_TCC6_CNT                            73 /* ID for TCC6 event generator CNT */
+#define EVENT_ID_GEN_TCC6_MC0                            74 /* ID for TCC6 event generator MC0 */
+#define EVENT_ID_GEN_TCC6_MC1                            75 /* ID for TCC6 event generator MC1 */
+#define EVENT_ID_GEN_ADC_CHRDY                           76 /* ID for ADC event generator CHRDY */
+#define EVENT_ID_GEN_ADC_CMP                             77 /* ID for ADC event generator CMP */
+#define EVENT_ID_GEN_AC_COMP0                            78 /* ID for AC event generator COMP0 */
+#define EVENT_ID_GEN_AC_COMP1                            79 /* ID for AC event generator COMP1 */
+#define EVENT_ID_GEN_AC_WIN0                             80 /* ID for AC event generator WIN0 */
+#define EVENT_ID_GEN_PTC_EOC                             81 /* ID for PTC event generator EOC */
+#define EVENT_ID_GEN_PTC_WCOMP                           82 /* ID for PTC event generator WCOMP */
+#define EVENT_ID_GEN_CCL0_LUTOUT0                        83 /* ID for CCL0 event generator LUTOUT0 */
+#define EVENT_ID_GEN_CCL0_LUTOUT1                        84 /* ID for CCL0 event generator LUTOUT1 */
+#define EVENT_ID_GEN_CCL0_LUTOUT2                        85 /* ID for CCL0 event generator LUTOUT2 */
+#define EVENT_ID_GEN_CCL0_LUTOUT3                        86 /* ID for CCL0 event generator LUTOUT3 */
+#define EVENT_ID_GEN_CCL1_LUTOUT0                        87 /* ID for CCL1 event generator LUTOUT0 */
+#define EVENT_ID_GEN_CCL1_LUTOUT1                        88 /* ID for CCL1 event generator LUTOUT1 */
+#define EVENT_ID_GEN_CCL1_LUTOUT2                        89 /* ID for CCL1 event generator LUTOUT2 */
+#define EVENT_ID_GEN_CCL1_LUTOUT3                        90 /* ID for CCL1 event generator LUTOUT3 */
+
+/* ************************************************************************** */
+/*                    Event User IDs for C32CM5112GC00048                     */
+/* ************************************************************************** */
+#define EVENT_ID_USER_FREQM_START                         0 /* ID for FREQM event user START */
+#define EVENT_ID_USER_RTC_TAMPER                          1 /* ID for RTC event user TAMPER */
+#define EVENT_ID_USER_PORT_EV0                            2 /* ID for PORT event user EV0 */
+#define EVENT_ID_USER_PORT_EV1                            3 /* ID for PORT event user EV1 */
+#define EVENT_ID_USER_PORT_EV2                            4 /* ID for PORT event user EV2 */
+#define EVENT_ID_USER_PORT_EV3                            5 /* ID for PORT event user EV3 */
+#define EVENT_ID_USER_DMAC_CH0                            6 /* ID for DMAC event user CH0 */
+#define EVENT_ID_USER_DMAC_CH1                            7 /* ID for DMAC event user CH1 */
+#define EVENT_ID_USER_DMAC_CH2                            8 /* ID for DMAC event user CH2 */
+#define EVENT_ID_USER_DMAC_CH3                            9 /* ID for DMAC event user CH3 */
+#define EVENT_ID_USER_TCC0_EV0                           10 /* ID for TCC0 event user EV0 */
+#define EVENT_ID_USER_TCC0_EV1                           11 /* ID for TCC0 event user EV1 */
+#define EVENT_ID_USER_TCC0_MC0                           12 /* ID for TCC0 event user MC0 */
+#define EVENT_ID_USER_TCC0_MC1                           13 /* ID for TCC0 event user MC1 */
+#define EVENT_ID_USER_TCC1_EV0                           14 /* ID for TCC1 event user EV0 */
+#define EVENT_ID_USER_TCC1_EV1                           15 /* ID for TCC1 event user EV1 */
+#define EVENT_ID_USER_TCC1_MC0                           16 /* ID for TCC1 event user MC0 */
+#define EVENT_ID_USER_TCC1_MC1                           17 /* ID for TCC1 event user MC1 */
+#define EVENT_ID_USER_TCC2_EV0                           18 /* ID for TCC2 event user EV0 */
+#define EVENT_ID_USER_TCC2_EV1                           19 /* ID for TCC2 event user EV1 */
+#define EVENT_ID_USER_TCC2_MC0                           20 /* ID for TCC2 event user MC0 */
+#define EVENT_ID_USER_TCC2_MC1                           21 /* ID for TCC2 event user MC1 */
+#define EVENT_ID_USER_TCC3_EV0                           22 /* ID for TCC3 event user EV0 */
+#define EVENT_ID_USER_TCC3_EV1                           23 /* ID for TCC3 event user EV1 */
+#define EVENT_ID_USER_TCC3_MC0                           24 /* ID for TCC3 event user MC0 */
+#define EVENT_ID_USER_TCC3_MC1                           25 /* ID for TCC3 event user MC1 */
+#define EVENT_ID_USER_TCC4_EV0                           26 /* ID for TCC4 event user EV0 */
+#define EVENT_ID_USER_TCC4_EV1                           27 /* ID for TCC4 event user EV1 */
+#define EVENT_ID_USER_TCC4_MC0                           28 /* ID for TCC4 event user MC0 */
+#define EVENT_ID_USER_TCC4_MC1                           29 /* ID for TCC4 event user MC1 */
+#define EVENT_ID_USER_TCC5_EV0                           30 /* ID for TCC5 event user EV0 */
+#define EVENT_ID_USER_TCC5_EV1                           31 /* ID for TCC5 event user EV1 */
+#define EVENT_ID_USER_TCC5_MC0                           32 /* ID for TCC5 event user MC0 */
+#define EVENT_ID_USER_TCC5_MC1                           33 /* ID for TCC5 event user MC1 */
+#define EVENT_ID_USER_TCC6_EV0                           34 /* ID for TCC6 event user EV0 */
+#define EVENT_ID_USER_TCC6_EV1                           35 /* ID for TCC6 event user EV1 */
+#define EVENT_ID_USER_TCC6_MC0                           36 /* ID for TCC6 event user MC0 */
+#define EVENT_ID_USER_TCC6_MC1                           37 /* ID for TCC6 event user MC1 */
+#define EVENT_ID_USER_ADC_TRIG0                          38 /* ID for ADC event user TRIG0 */
+#define EVENT_ID_USER_ADC_TRIG1                          39 /* ID for ADC event user TRIG1 */
+#define EVENT_ID_USER_ADC_TRIG2                          40 /* ID for ADC event user TRIG2 */
+#define EVENT_ID_USER_ADC_TRIG3                          41 /* ID for ADC event user TRIG3 */
+#define EVENT_ID_USER_ADC_TRIG4                          42 /* ID for ADC event user TRIG4 */
+#define EVENT_ID_USER_ADC_TRIG5                          43 /* ID for ADC event user TRIG5 */
+#define EVENT_ID_USER_ADC_TRIG6                          44 /* ID for ADC event user TRIG6 */
+#define EVENT_ID_USER_ADC_TRIG7                          45 /* ID for ADC event user TRIG7 */
+#define EVENT_ID_USER_ADC_TRIG8                          46 /* ID for ADC event user TRIG8 */
+#define EVENT_ID_USER_ADC_TRIG9                          47 /* ID for ADC event user TRIG9 */
+#define EVENT_ID_USER_ADC_TRIG10                         48 /* ID for ADC event user TRIG10 */
+#define EVENT_ID_USER_AC_SOC0                            49 /* ID for AC event user SOC0 */
+#define EVENT_ID_USER_AC_SOC1                            50 /* ID for AC event user SOC1 */
+#define EVENT_ID_USER_PTC_DSEQR                          51 /* ID for PTC event user DSEQR */
+#define EVENT_ID_USER_PTC_STCONV                         52 /* ID for PTC event user STCONV */
+#define EVENT_ID_USER_CCL0_LUTIN0                        53 /* ID for CCL0 event user LUTIN0 */
+#define EVENT_ID_USER_CCL0_LUTIN1                        54 /* ID for CCL0 event user LUTIN1 */
+#define EVENT_ID_USER_CCL0_LUTIN2                        55 /* ID for CCL0 event user LUTIN2 */
+#define EVENT_ID_USER_CCL0_LUTIN3                        56 /* ID for CCL0 event user LUTIN3 */
+#define EVENT_ID_USER_CCL1_LUTIN0                        57 /* ID for CCL1 event user LUTIN0 */
+#define EVENT_ID_USER_CCL1_LUTIN1                        58 /* ID for CCL1 event user LUTIN1 */
+#define EVENT_ID_USER_CCL1_LUTIN2                        59 /* ID for CCL1 event user LUTIN2 */
+#define EVENT_ID_USER_CCL1_LUTIN3                        60 /* ID for CCL1 event user LUTIN3 */
+#define EVENT_ID_USER_AT_TAMPSRC5                        61 /* ID for AT event user TAMPSRC5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PIC32CM5112GC00048_H_ */
+
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32cm5112gc00064.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32cm5112gc00064.h
new file mode 100644
index 00000000..c5f5198e
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32cm5112gc00064.h
@@ -0,0 +1,1029 @@
+/*
+ * Header file for PIC32CM5112GC00064
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* File generated from device description file (ATDF) version 2024-11-05T16:47:48Z */
+#ifndef _PIC32CM5112GC00064_H_
+#define _PIC32CM5112GC00064_H_
+
+/* Header version uses Semantic Versioning 2.0.0 (https://semver.org/) */
+#define HEADER_FORMAT_VERSION "2.1.1"
+
+#define HEADER_FORMAT_VERSION_MAJOR (2)
+#define HEADER_FORMAT_VERSION_MINOR (1)
+#define HEADER_FORMAT_VERSION_PATCH (1)
+
+/* PIC32CM5112GC00064 definitions
+  This file defines all structures and symbols for PIC32CM5112GC00064:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  include <stdint.h>
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#  if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_)
+#    error "Integer constant value macros already defined elsewhere"
+#  endif
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with sizes of integer constants for C/C++ */
+#  define _UINT8_(x)   ((uint8_t)(x))    /* C code: 8-bits unsigned integer constant value */
+#  define _UINT16_(x)  ((uint16_t)(x))   /* C code: 16-bits unsigned integer constant value */
+#  define _UINT32_(x)  ((uint32_t)(x))   /* C code: 32-bits unsigned integer constant value */
+
+#else /* Assembler */
+
+#  define _UINT8_(x) x    /* Assembler: 8-bits unsigned integer constant value */
+#  define _UINT16_(x) x   /* Assembler: 16-bits unsigned integer constant value */
+#  define _UINT32_(x) x   /* Assembler: 32-bits unsigned integer constant value */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/*                  CMSIS DEFINITIONS FOR PIC32CM5112GC00064                  */
+/* ************************************************************************** */
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  CORTEX-M23 Processor Exceptions Numbers ******************************/
+  Reset_IRQn                = -15, /* -15 Reset Vector, invoked on Power up and warm reset */
+  NonMaskableInt_IRQn       = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */
+  HardFault_IRQn            = -13, /* -13 Hard Fault, all classes of Fault    */
+  SVCall_IRQn               =  -5, /* -5  System Service Call via SVC instruction */
+  PendSV_IRQn               =  -2, /* -2  Pendable request for system service */
+  SysTick_IRQn              =  -1, /* -1  System Tick Timer                   */
+
+/* ************* PIC32CM5112GC00064 specific Interrupt Numbers ************** */
+  FCR_IRQn                  =   0, /* 0   Polaris Flash Read Controller (FCR) */
+  FCW_IRQn                  =   1, /* 1   Polaris Flash Write Controller (FCW) */
+  PM_IRQn                   =   2, /* 2   Power Manager (PM)                  */
+  SUPC_IRQn                 =   3, /* 3   Supply Controller (SUPC)            */
+  OSCCTRL_XOSCRDY_IRQn      =   4, /* 4   Oscillators Control (OSCCTRL)       */
+  OSCCTRL_DFLLRDY_IRQn      =   5, /* 5   Oscillators Control (OSCCTRL)       */
+  OSCCTRL_PLLLOCKR_0_IRQn   =   6, /* 6   Oscillators Control (OSCCTRL)       */
+  OSC32KCTRL_XOSC32KRDY_IRQn =   7, /* 7   32kHz Oscillators Control (OSC32KCTRL) */
+  OSC32KCTRL_XOSC32KFAIL_IRQn =   8, /* 8   32kHz Oscillators Control (OSC32KCTRL) */
+  MCLK_IRQn                 =   9, /* 9   Polaris Main Clock Controller (MCLK) */
+  FREQM_IRQn                =  10, /* 10  Frequency Meter (FREQM)             */
+  WDT_IRQn                  =  11, /* 11  Watchdog Timer (WDT)                */
+  RTC_TAMPER_IRQn           =  12, /* 12  Real-Time Counter (RTC)             */
+  RTC_OVF_IRQn              =  13, /* 13  Real-Time Counter (RTC)             */
+  RTC_PER0_IRQn             =  14, /* 14  Real-Time Counter (RTC)             */
+  RTC_CMP0_IRQn             =  15, /* 15  Real-Time Counter (RTC)             */
+  EIC_EXTINT0_IRQn          =  16, /* 16  External Interrupt Controller (EIC) */
+  EIC_EXTINT1_IRQn          =  17, /* 17  External Interrupt Controller (EIC) */
+  EIC_EXTINT2_IRQn          =  18, /* 18  External Interrupt Controller (EIC) */
+  EIC_EXTINT3_IRQn          =  19, /* 19  External Interrupt Controller (EIC) */
+  EIC_EXTINT4_IRQn          =  20, /* 20  External Interrupt Controller (EIC) */
+  EIC_EXTINT5_IRQn          =  21, /* 21  External Interrupt Controller (EIC) */
+  EIC_EXTINT6_IRQn          =  22, /* 22  External Interrupt Controller (EIC) */
+  EIC_EXTINT7_IRQn          =  23, /* 23  External Interrupt Controller (EIC) */
+  EIC_EXTINT8_IRQn          =  24, /* 24  External Interrupt Controller (EIC) */
+  EIC_EXTINT9_IRQn          =  25, /* 25  External Interrupt Controller (EIC) */
+  EIC_EXTINT10_IRQn         =  26, /* 26  External Interrupt Controller (EIC) */
+  EIC_EXTINT11_IRQn         =  27, /* 27  External Interrupt Controller (EIC) */
+  EIC_EXTINT12_IRQn         =  28, /* 28  External Interrupt Controller (EIC) */
+  EIC_EXTINT13_IRQn         =  29, /* 29  External Interrupt Controller (EIC) */
+  EIC_EXTINT14_IRQn         =  30, /* 30  External Interrupt Controller (EIC) */
+  EIC_EXTINT15_IRQn         =  31, /* 31  External Interrupt Controller (EIC) */
+  EIC_NSCHK_IRQn            =  32, /* 32  External Interrupt Controller (EIC) */
+  MCRAMC_IRQn               =  34, /* 34  Multi-Channel RAM Controller (MCRAMC) */
+  CAN0_INT0_IRQn            =  35, /* 35  Control Area Network (CAN0)         */
+  CAN0_INT1_IRQn            =  36, /* 36  Control Area Network (CAN0)         */
+  CAN0_BERR_IRQn            =  37, /* 37  Control Area Network (CAN0)         */
+  CAN1_INT0_IRQn            =  38, /* 38  Control Area Network (CAN1)         */
+  CAN1_INT1_IRQn            =  39, /* 39  Control Area Network (CAN1)         */
+  CAN1_BERR_IRQn            =  40, /* 40  Control Area Network (CAN1)         */
+  PORT_IRQn                 =  41, /* 41  Port Module (PORT)                  */
+  DMAC_TCMPL0_IRQn          =  42, /* 42  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL1_IRQn          =  43, /* 43  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL2_IRQn          =  44, /* 44  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL3_IRQn          =  45, /* 45  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL4_IRQn          =  46, /* 46  Direct Memory Access Controller (DMAC) */
+  HMATRIX2_IRQn             =  47, /* 47  HSB Matrix (HMATRIX2)               */
+  EVSYS_EVD0_IRQn           =  48, /* 48  Event System Interface (EVSYS)      */
+  EVSYS_EVD1_IRQn           =  49, /* 49  Event System Interface (EVSYS)      */
+  EVSYS_EVD2_IRQn           =  50, /* 50  Event System Interface (EVSYS)      */
+  EVSYS_EVD3_IRQn           =  51, /* 51  Event System Interface (EVSYS)      */
+  EVSYS_EVD4_IRQn           =  52, /* 52  Event System Interface (EVSYS)      */
+  EVSYS_EVD5_IRQn           =  53, /* 53  Event System Interface (EVSYS)      */
+  EVSYS_EVD6_IRQn           =  54, /* 54  Event System Interface (EVSYS)      */
+  EVSYS_EVD7_IRQn           =  55, /* 55  Event System Interface (EVSYS)      */
+  EVSYS_EVD8_IRQn           =  56, /* 56  Event System Interface (EVSYS)      */
+  EVSYS_EVD9_IRQn           =  57, /* 57  Event System Interface (EVSYS)      */
+  EVSYS_EVD10_IRQn          =  58, /* 58  Event System Interface (EVSYS)      */
+  EVSYS_EVD11_IRQn          =  59, /* 59  Event System Interface (EVSYS)      */
+  SERCOM0_6_IRQn            =  60, /* 60  Serial Communication Interface (SERCOM0) */
+  SERCOM0_5_IRQn            =  61, /* 61  Serial Communication Interface (SERCOM0) */
+  SERCOM0_0_IRQn            =  62, /* 62  Serial Communication Interface (SERCOM0) */
+  SERCOM0_1_IRQn            =  63, /* 63  Serial Communication Interface (SERCOM0) */
+  SERCOM0_2_IRQn            =  64, /* 64  Serial Communication Interface (SERCOM0) */
+  SERCOM0_3_IRQn            =  65, /* 65  Serial Communication Interface (SERCOM0) */
+  SERCOM0_4_IRQn            =  66, /* 66  Serial Communication Interface (SERCOM0) */
+  SERCOM1_6_IRQn            =  67, /* 67  Serial Communication Interface (SERCOM1) */
+  SERCOM1_5_IRQn            =  68, /* 68  Serial Communication Interface (SERCOM1) */
+  SERCOM1_0_IRQn            =  69, /* 69  Serial Communication Interface (SERCOM1) */
+  SERCOM1_1_IRQn            =  70, /* 70  Serial Communication Interface (SERCOM1) */
+  SERCOM1_2_IRQn            =  71, /* 71  Serial Communication Interface (SERCOM1) */
+  SERCOM1_3_IRQn            =  72, /* 72  Serial Communication Interface (SERCOM1) */
+  SERCOM1_4_IRQn            =  73, /* 73  Serial Communication Interface (SERCOM1) */
+  SERCOM2_6_IRQn            =  74, /* 74  Serial Communication Interface (SERCOM2) */
+  SERCOM2_5_IRQn            =  75, /* 75  Serial Communication Interface (SERCOM2) */
+  SERCOM2_0_IRQn            =  76, /* 76  Serial Communication Interface (SERCOM2) */
+  SERCOM2_1_IRQn            =  77, /* 77  Serial Communication Interface (SERCOM2) */
+  SERCOM2_2_IRQn            =  78, /* 78  Serial Communication Interface (SERCOM2) */
+  SERCOM2_3_IRQn            =  79, /* 79  Serial Communication Interface (SERCOM2) */
+  SERCOM2_4_IRQn            =  80, /* 80  Serial Communication Interface (SERCOM2) */
+  SERCOM3_6_IRQn            =  81, /* 81  Serial Communication Interface (SERCOM3) */
+  SERCOM3_5_IRQn            =  82, /* 82  Serial Communication Interface (SERCOM3) */
+  SERCOM3_0_IRQn            =  83, /* 83  Serial Communication Interface (SERCOM3) */
+  SERCOM3_1_IRQn            =  84, /* 84  Serial Communication Interface (SERCOM3) */
+  SERCOM3_2_IRQn            =  85, /* 85  Serial Communication Interface (SERCOM3) */
+  SERCOM3_3_IRQn            =  86, /* 86  Serial Communication Interface (SERCOM3) */
+  SERCOM3_4_IRQn            =  87, /* 87  Serial Communication Interface (SERCOM3) */
+  TCC0_DFS_IRQn             =  88, /* 88  Timer Counter for Control Applications (TCC0) */
+  TCC0_CNT_IRQn             =  89, /* 89  Timer Counter for Control Applications (TCC0) */
+  TCC0_MC0_IRQn             =  90, /* 90  Timer Counter for Control Applications (TCC0) */
+  TCC0_MC1_IRQn             =  91, /* 91  Timer Counter for Control Applications (TCC0) */
+  TCC1_DFS_IRQn             =  92, /* 92  Timer Counter for Control Applications (TCC1) */
+  TCC1_CNT_IRQn             =  93, /* 93  Timer Counter for Control Applications (TCC1) */
+  TCC1_MC0_IRQn             =  94, /* 94  Timer Counter for Control Applications (TCC1) */
+  TCC1_MC1_IRQn             =  95, /* 95  Timer Counter for Control Applications (TCC1) */
+  TCC2_DFS_IRQn             =  96, /* 96  Timer Counter for Control Applications (TCC2) */
+  TCC2_CNT_IRQn             =  97, /* 97  Timer Counter for Control Applications (TCC2) */
+  TCC2_MC0_IRQn             =  98, /* 98  Timer Counter for Control Applications (TCC2) */
+  TCC2_MC1_IRQn             =  99, /* 99  Timer Counter for Control Applications (TCC2) */
+  TCC3_DFS_IRQn             = 100, /* 100 Timer Counter for Control Applications (TCC3) */
+  TCC3_CNT_IRQn             = 101, /* 101 Timer Counter for Control Applications (TCC3) */
+  TCC3_MC0_IRQn             = 102, /* 102 Timer Counter for Control Applications (TCC3) */
+  TCC3_MC1_IRQn             = 103, /* 103 Timer Counter for Control Applications (TCC3) */
+  SERCOM4_6_IRQn            = 104, /* 104 Serial Communication Interface (SERCOM4) */
+  SERCOM4_5_IRQn            = 105, /* 105 Serial Communication Interface (SERCOM4) */
+  SERCOM4_0_IRQn            = 106, /* 106 Serial Communication Interface (SERCOM4) */
+  SERCOM4_1_IRQn            = 107, /* 107 Serial Communication Interface (SERCOM4) */
+  SERCOM4_2_IRQn            = 108, /* 108 Serial Communication Interface (SERCOM4) */
+  SERCOM4_3_IRQn            = 109, /* 109 Serial Communication Interface (SERCOM4) */
+  SERCOM4_4_IRQn            = 110, /* 110 Serial Communication Interface (SERCOM4) */
+  SERCOM5_6_IRQn            = 111, /* 111 Serial Communication Interface (SERCOM5) */
+  SERCOM5_5_IRQn            = 112, /* 112 Serial Communication Interface (SERCOM5) */
+  SERCOM5_0_IRQn            = 113, /* 113 Serial Communication Interface (SERCOM5) */
+  SERCOM5_1_IRQn            = 114, /* 114 Serial Communication Interface (SERCOM5) */
+  SERCOM5_2_IRQn            = 115, /* 115 Serial Communication Interface (SERCOM5) */
+  SERCOM5_3_IRQn            = 116, /* 116 Serial Communication Interface (SERCOM5) */
+  SERCOM5_4_IRQn            = 117, /* 117 Serial Communication Interface (SERCOM5) */
+  TCC4_DFS_IRQn             = 118, /* 118 Timer Counter for Control Applications (TCC4) */
+  TCC4_CNT_IRQn             = 119, /* 119 Timer Counter for Control Applications (TCC4) */
+  TCC4_MC0_IRQn             = 120, /* 120 Timer Counter for Control Applications (TCC4) */
+  TCC4_MC1_IRQn             = 121, /* 121 Timer Counter for Control Applications (TCC4) */
+  TCC5_DFS_IRQn             = 122, /* 122 Timer Counter for Control Applications (TCC5) */
+  TCC5_CNT_IRQn             = 123, /* 123 Timer Counter for Control Applications (TCC5) */
+  TCC5_MC0_IRQn             = 124, /* 124 Timer Counter for Control Applications (TCC5) */
+  TCC5_MC1_IRQn             = 125, /* 125 Timer Counter for Control Applications (TCC5) */
+  TCC6_DFS_IRQn             = 126, /* 126 Timer Counter for Control Applications (TCC6) */
+  TCC6_CNT_IRQn             = 127, /* 127 Timer Counter for Control Applications (TCC6) */
+  TCC6_MC0_IRQn             = 128, /* 128 Timer Counter for Control Applications (TCC6) */
+  TCC6_MC1_IRQn             = 129, /* 129 Timer Counter for Control Applications (TCC6) */
+  ADC_REQ0_IRQn             = 130, /* 130 ADC Controller (ADC)                */
+  ADC_REQ1_IRQn             = 131, /* 131 ADC Controller (ADC)                */
+  AC_IRQn                   = 132, /* 132 Analog Comparator Controller (AC)   */
+  PTC_IRQn                  = 133, /* 133 Polaris Peripheral Touch Controller (PTC) */
+  USB_EORSMDNRSM_IRQn       = 134, /* 134 Full-Speed Universal Serial Bus (USB) */
+  USB_SOFHSOF_IRQn          = 135, /* 135 Full-Speed Universal Serial Bus (USB) */
+  USB_TRCPT00_IRQn          = 136, /* 136 Full-Speed Universal Serial Bus (USB) */
+  USB_TRCPT10_IRQn          = 137, /* 137 Full-Speed Universal Serial Bus (USB) */
+  AT_IRQn                   = 138, /* 138 Anti-Tamper Controller (AT) (AT)    */
+
+  PERIPH_MAX_IRQn           = 138  /* Max peripheral ID */
+} IRQn_Type;
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+  /* CORTEX-M23 handlers */
+  void* pfnReset_Handler;                        /* -15 Reset Vector, invoked on Power up and warm reset */
+  void* pfnNonMaskableInt_Handler;               /* -14 Non maskable Interrupt, cannot be stopped or preempted */
+  void* pfnHardFault_Handler;                    /* -13 Hard Fault, all classes of Fault */
+  void* pvReservedC12;
+  void* pvReservedC11;
+  void* pvReservedC10;
+  void* pvReservedC9;
+  void* pvReservedC8;
+  void* pvReservedC7;
+  void* pvReservedC6;
+  void* pfnSVCall_Handler;                       /*  -5 System Service Call via SVC instruction */
+  void* pvReservedC4;
+  void* pvReservedC3;
+  void* pfnPendSV_Handler;                       /*  -2 Pendable request for system service */
+  void* pfnSysTick_Handler;                      /*  -1 System Tick Timer */
+
+  /* Peripheral handlers */
+  void* pfnFCR_Handler;                          /*   0 Polaris Flash Read Controller (FCR) */
+  void* pfnFCW_Handler;                          /*   1 Polaris Flash Write Controller (FCW) */
+  void* pfnPM_Handler;                           /*   2 Power Manager (PM) */
+  void* pfnSUPC_Handler;                         /*   3 Supply Controller (SUPC) */
+  void* pfnOSCCTRL_XOSCRDY_Handler;              /*   4 Oscillators Control (OSCCTRL) */
+  void* pfnOSCCTRL_DFLLRDY_Handler;              /*   5 Oscillators Control (OSCCTRL) */
+  void* pfnOSCCTRL_PLLLOCKR_0_Handler;           /*   6 Oscillators Control (OSCCTRL) */
+  void* pfnOSC32KCTRL_XOSC32KRDY_Handler;        /*   7 32kHz Oscillators Control (OSC32KCTRL) */
+  void* pfnOSC32KCTRL_XOSC32KFAIL_Handler;       /*   8 32kHz Oscillators Control (OSC32KCTRL) */
+  void* pfnMCLK_Handler;                         /*   9 Polaris Main Clock Controller (MCLK) */
+  void* pfnFREQM_Handler;                        /*  10 Frequency Meter (FREQM) */
+  void* pfnWDT_Handler;                          /*  11 Watchdog Timer (WDT) */
+  void* pfnRTC_TAMPER_Handler;                   /*  12 Real-Time Counter (RTC) */
+  void* pfnRTC_OVF_Handler;                      /*  13 Real-Time Counter (RTC) */
+  void* pfnRTC_PER0_Handler;                     /*  14 Real-Time Counter (RTC) */
+  void* pfnRTC_CMP0_Handler;                     /*  15 Real-Time Counter (RTC) */
+  void* pfnEIC_EXTINT0_Handler;                  /*  16 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT1_Handler;                  /*  17 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT2_Handler;                  /*  18 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT3_Handler;                  /*  19 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT4_Handler;                  /*  20 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT5_Handler;                  /*  21 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT6_Handler;                  /*  22 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT7_Handler;                  /*  23 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT8_Handler;                  /*  24 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT9_Handler;                  /*  25 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT10_Handler;                 /*  26 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT11_Handler;                 /*  27 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT12_Handler;                 /*  28 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT13_Handler;                 /*  29 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT14_Handler;                 /*  30 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT15_Handler;                 /*  31 External Interrupt Controller (EIC) */
+  void* pfnEIC_NSCHK_Handler;                    /*  32 External Interrupt Controller (EIC) */
+  void* pvReserved33;
+  void* pfnMCRAMC_Handler;                       /*  34 Multi-Channel RAM Controller (MCRAMC) */
+  void* pfnCAN0_INT0_Handler;                    /*  35 Control Area Network (CAN0) */
+  void* pfnCAN0_INT1_Handler;                    /*  36 Control Area Network (CAN0) */
+  void* pfnCAN0_BERR_Handler;                    /*  37 Control Area Network (CAN0) */
+  void* pfnCAN1_INT0_Handler;                    /*  38 Control Area Network (CAN1) */
+  void* pfnCAN1_INT1_Handler;                    /*  39 Control Area Network (CAN1) */
+  void* pfnCAN1_BERR_Handler;                    /*  40 Control Area Network (CAN1) */
+  void* pfnPORT_Handler;                         /*  41 Port Module (PORT) */
+  void* pfnDMAC_TCMPL0_Handler;                  /*  42 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL1_Handler;                  /*  43 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL2_Handler;                  /*  44 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL3_Handler;                  /*  45 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL4_Handler;                  /*  46 Direct Memory Access Controller (DMAC) */
+  void* pfnHMATRIX2_Handler;                     /*  47 HSB Matrix (HMATRIX2) */
+  void* pfnEVSYS_EVD0_Handler;                   /*  48 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD1_Handler;                   /*  49 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD2_Handler;                   /*  50 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD3_Handler;                   /*  51 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD4_Handler;                   /*  52 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD5_Handler;                   /*  53 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD6_Handler;                   /*  54 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD7_Handler;                   /*  55 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD8_Handler;                   /*  56 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD9_Handler;                   /*  57 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD10_Handler;                  /*  58 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD11_Handler;                  /*  59 Event System Interface (EVSYS) */
+  void* pfnSERCOM0_6_Handler;                    /*  60 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_5_Handler;                    /*  61 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_0_Handler;                    /*  62 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_1_Handler;                    /*  63 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_2_Handler;                    /*  64 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_3_Handler;                    /*  65 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_4_Handler;                    /*  66 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM1_6_Handler;                    /*  67 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_5_Handler;                    /*  68 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_0_Handler;                    /*  69 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_1_Handler;                    /*  70 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_2_Handler;                    /*  71 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_3_Handler;                    /*  72 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_4_Handler;                    /*  73 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM2_6_Handler;                    /*  74 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_5_Handler;                    /*  75 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_0_Handler;                    /*  76 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_1_Handler;                    /*  77 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_2_Handler;                    /*  78 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_3_Handler;                    /*  79 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_4_Handler;                    /*  80 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM3_6_Handler;                    /*  81 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_5_Handler;                    /*  82 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_0_Handler;                    /*  83 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_1_Handler;                    /*  84 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_2_Handler;                    /*  85 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_3_Handler;                    /*  86 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_4_Handler;                    /*  87 Serial Communication Interface (SERCOM3) */
+  void* pfnTCC0_DFS_Handler;                     /*  88 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC0_CNT_Handler;                     /*  89 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC0_MC0_Handler;                     /*  90 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC0_MC1_Handler;                     /*  91 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC1_DFS_Handler;                     /*  92 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC1_CNT_Handler;                     /*  93 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC1_MC0_Handler;                     /*  94 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC1_MC1_Handler;                     /*  95 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC2_DFS_Handler;                     /*  96 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC2_CNT_Handler;                     /*  97 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC2_MC0_Handler;                     /*  98 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC2_MC1_Handler;                     /*  99 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC3_DFS_Handler;                     /* 100 Timer Counter for Control Applications (TCC3) */
+  void* pfnTCC3_CNT_Handler;                     /* 101 Timer Counter for Control Applications (TCC3) */
+  void* pfnTCC3_MC0_Handler;                     /* 102 Timer Counter for Control Applications (TCC3) */
+  void* pfnTCC3_MC1_Handler;                     /* 103 Timer Counter for Control Applications (TCC3) */
+  void* pfnSERCOM4_6_Handler;                    /* 104 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_5_Handler;                    /* 105 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_0_Handler;                    /* 106 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_1_Handler;                    /* 107 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_2_Handler;                    /* 108 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_3_Handler;                    /* 109 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_4_Handler;                    /* 110 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM5_6_Handler;                    /* 111 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_5_Handler;                    /* 112 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_0_Handler;                    /* 113 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_1_Handler;                    /* 114 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_2_Handler;                    /* 115 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_3_Handler;                    /* 116 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_4_Handler;                    /* 117 Serial Communication Interface (SERCOM5) */
+  void* pfnTCC4_DFS_Handler;                     /* 118 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC4_CNT_Handler;                     /* 119 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC4_MC0_Handler;                     /* 120 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC4_MC1_Handler;                     /* 121 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC5_DFS_Handler;                     /* 122 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC5_CNT_Handler;                     /* 123 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC5_MC0_Handler;                     /* 124 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC5_MC1_Handler;                     /* 125 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC6_DFS_Handler;                     /* 126 Timer Counter for Control Applications (TCC6) */
+  void* pfnTCC6_CNT_Handler;                     /* 127 Timer Counter for Control Applications (TCC6) */
+  void* pfnTCC6_MC0_Handler;                     /* 128 Timer Counter for Control Applications (TCC6) */
+  void* pfnTCC6_MC1_Handler;                     /* 129 Timer Counter for Control Applications (TCC6) */
+  void* pfnADC_REQ0_Handler;                     /* 130 ADC Controller (ADC) */
+  void* pfnADC_REQ1_Handler;                     /* 131 ADC Controller (ADC) */
+  void* pfnAC_Handler;                           /* 132 Analog Comparator Controller (AC) */
+  void* pfnPTC_Handler;                          /* 133 Polaris Peripheral Touch Controller (PTC) */
+  void* pfnUSB_EORSMDNRSM_Handler;               /* 134 Full-Speed Universal Serial Bus (USB) */
+  void* pfnUSB_SOFHSOF_Handler;                  /* 135 Full-Speed Universal Serial Bus (USB) */
+  void* pfnUSB_TRCPT00_Handler;                  /* 136 Full-Speed Universal Serial Bus (USB) */
+  void* pfnUSB_TRCPT10_Handler;                  /* 137 Full-Speed Universal Serial Bus (USB) */
+  void* pfnAT_Handler;                           /* 138 Anti-Tamper Controller (AT) (AT) */
+} DeviceVectors;
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS
+/* CORTEX-M23 exception handlers */
+void Reset_Handler                 ( void );
+void NonMaskableInt_Handler        ( void );
+void HardFault_Handler             ( void );
+void SVCall_Handler                ( void );
+void PendSV_Handler                ( void );
+void SysTick_Handler               ( void );
+#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */
+
+#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
+/* Peripherals interrupt handlers */
+void FCR_Handler                   ( void );
+void FCW_Handler                   ( void );
+void PM_Handler                    ( void );
+void SUPC_Handler                  ( void );
+void OSCCTRL_XOSCRDY_Handler       ( void );
+void OSCCTRL_DFLLRDY_Handler       ( void );
+void OSCCTRL_PLLLOCKR_0_Handler    ( void );
+void OSC32KCTRL_XOSC32KRDY_Handler ( void );
+void OSC32KCTRL_XOSC32KFAIL_Handler( void );
+void MCLK_Handler                  ( void );
+void FREQM_Handler                 ( void );
+void WDT_Handler                   ( void );
+void RTC_TAMPER_Handler            ( void );
+void RTC_OVF_Handler               ( void );
+void RTC_PER0_Handler              ( void );
+void RTC_CMP0_Handler              ( void );
+void EIC_EXTINT0_Handler           ( void );
+void EIC_EXTINT1_Handler           ( void );
+void EIC_EXTINT2_Handler           ( void );
+void EIC_EXTINT3_Handler           ( void );
+void EIC_EXTINT4_Handler           ( void );
+void EIC_EXTINT5_Handler           ( void );
+void EIC_EXTINT6_Handler           ( void );
+void EIC_EXTINT7_Handler           ( void );
+void EIC_EXTINT8_Handler           ( void );
+void EIC_EXTINT9_Handler           ( void );
+void EIC_EXTINT10_Handler          ( void );
+void EIC_EXTINT11_Handler          ( void );
+void EIC_EXTINT12_Handler          ( void );
+void EIC_EXTINT13_Handler          ( void );
+void EIC_EXTINT14_Handler          ( void );
+void EIC_EXTINT15_Handler          ( void );
+void EIC_NSCHK_Handler             ( void );
+void MCRAMC_Handler                ( void );
+void CAN0_INT0_Handler             ( void );
+void CAN0_INT1_Handler             ( void );
+void CAN0_BERR_Handler             ( void );
+void CAN1_INT0_Handler             ( void );
+void CAN1_INT1_Handler             ( void );
+void CAN1_BERR_Handler             ( void );
+void PORT_Handler                  ( void );
+void DMAC_TCMPL0_Handler           ( void );
+void DMAC_TCMPL1_Handler           ( void );
+void DMAC_TCMPL2_Handler           ( void );
+void DMAC_TCMPL3_Handler           ( void );
+void DMAC_TCMPL4_Handler           ( void );
+void HMATRIX2_Handler              ( void );
+void EVSYS_EVD0_Handler            ( void );
+void EVSYS_EVD1_Handler            ( void );
+void EVSYS_EVD2_Handler            ( void );
+void EVSYS_EVD3_Handler            ( void );
+void EVSYS_EVD4_Handler            ( void );
+void EVSYS_EVD5_Handler            ( void );
+void EVSYS_EVD6_Handler            ( void );
+void EVSYS_EVD7_Handler            ( void );
+void EVSYS_EVD8_Handler            ( void );
+void EVSYS_EVD9_Handler            ( void );
+void EVSYS_EVD10_Handler           ( void );
+void EVSYS_EVD11_Handler           ( void );
+void SERCOM0_6_Handler             ( void );
+void SERCOM0_5_Handler             ( void );
+void SERCOM0_0_Handler             ( void );
+void SERCOM0_1_Handler             ( void );
+void SERCOM0_2_Handler             ( void );
+void SERCOM0_3_Handler             ( void );
+void SERCOM0_4_Handler             ( void );
+void SERCOM1_6_Handler             ( void );
+void SERCOM1_5_Handler             ( void );
+void SERCOM1_0_Handler             ( void );
+void SERCOM1_1_Handler             ( void );
+void SERCOM1_2_Handler             ( void );
+void SERCOM1_3_Handler             ( void );
+void SERCOM1_4_Handler             ( void );
+void SERCOM2_6_Handler             ( void );
+void SERCOM2_5_Handler             ( void );
+void SERCOM2_0_Handler             ( void );
+void SERCOM2_1_Handler             ( void );
+void SERCOM2_2_Handler             ( void );
+void SERCOM2_3_Handler             ( void );
+void SERCOM2_4_Handler             ( void );
+void SERCOM3_6_Handler             ( void );
+void SERCOM3_5_Handler             ( void );
+void SERCOM3_0_Handler             ( void );
+void SERCOM3_1_Handler             ( void );
+void SERCOM3_2_Handler             ( void );
+void SERCOM3_3_Handler             ( void );
+void SERCOM3_4_Handler             ( void );
+void TCC0_DFS_Handler              ( void );
+void TCC0_CNT_Handler              ( void );
+void TCC0_MC0_Handler              ( void );
+void TCC0_MC1_Handler              ( void );
+void TCC1_DFS_Handler              ( void );
+void TCC1_CNT_Handler              ( void );
+void TCC1_MC0_Handler              ( void );
+void TCC1_MC1_Handler              ( void );
+void TCC2_DFS_Handler              ( void );
+void TCC2_CNT_Handler              ( void );
+void TCC2_MC0_Handler              ( void );
+void TCC2_MC1_Handler              ( void );
+void TCC3_DFS_Handler              ( void );
+void TCC3_CNT_Handler              ( void );
+void TCC3_MC0_Handler              ( void );
+void TCC3_MC1_Handler              ( void );
+void SERCOM4_6_Handler             ( void );
+void SERCOM4_5_Handler             ( void );
+void SERCOM4_0_Handler             ( void );
+void SERCOM4_1_Handler             ( void );
+void SERCOM4_2_Handler             ( void );
+void SERCOM4_3_Handler             ( void );
+void SERCOM4_4_Handler             ( void );
+void SERCOM5_6_Handler             ( void );
+void SERCOM5_5_Handler             ( void );
+void SERCOM5_0_Handler             ( void );
+void SERCOM5_1_Handler             ( void );
+void SERCOM5_2_Handler             ( void );
+void SERCOM5_3_Handler             ( void );
+void SERCOM5_4_Handler             ( void );
+void TCC4_DFS_Handler              ( void );
+void TCC4_CNT_Handler              ( void );
+void TCC4_MC0_Handler              ( void );
+void TCC4_MC1_Handler              ( void );
+void TCC5_DFS_Handler              ( void );
+void TCC5_CNT_Handler              ( void );
+void TCC5_MC0_Handler              ( void );
+void TCC5_MC1_Handler              ( void );
+void TCC6_DFS_Handler              ( void );
+void TCC6_CNT_Handler              ( void );
+void TCC6_MC0_Handler              ( void );
+void TCC6_MC1_Handler              ( void );
+void ADC_REQ0_Handler              ( void );
+void ADC_REQ1_Handler              ( void );
+void AC_Handler                    ( void );
+void PTC_Handler                   ( void );
+void USB_EORSMDNRSM_Handler        ( void );
+void USB_SOFHSOF_Handler           ( void );
+void USB_TRCPT00_Handler           ( void );
+void USB_TRCPT10_Handler           ( void );
+void AT_Handler                    ( void );
+#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* Configuration of the CORTEX-M23 Processor and Core Peripherals */
+#define __CM23_REV                    0x0000 /* Cortex-M23 Core Revision                                                  */
+#define __FPU_PRESENT                      0 /* No FPU                                                                    */
+#define __MPU_PRESENT                      1 /* MPU implemented                                                           */
+#define __NVIC_PRIO_BITS                   2 /* Number of NVIC Priority Bits                                              */
+#define __SAUREGION_PRESENT                0 /* Number of Security Attribute Unit Regions (No SAU)                        */
+#define __VTOR_PRESENT                     1 /* Include Vector Table Offset Register                                      */
+#define __Vendor_SysTickConfig             0 /* Standard SYSTICK used                                                     */
+#define __ARCH_ARM                         1
+#define __ARCH_ARM_CORTEX_M                1
+
+/* CMSIS includes */
+#include "core_cm23.h"
+#if defined USE_CMSIS_INIT
+#include "system_pic32cmgc00.h"
+#endif /* USE_CMSIS_INIT */
+
+/* ************************************************************************** */
+/*         SOFTWARE PERIPHERAL API DEFINITIONS FOR PIC32CM5112GC00064         */
+/* ************************************************************************** */
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/at.h"
+#include "component/bromc.h"
+#include "component/can.h"
+#include "component/ccl.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/fcr.h"
+#include "component/fcw.h"
+#include "component/freqm.h"
+#include "component/fuses.h"
+#include "component/gclk.h"
+#include "component/h2pb.h"
+#include "component/hmatrix2.h"
+#include "component/mclk.h"
+#include "component/mcramc.h"
+#include "component/osc32kctrl.h"
+#include "component/oscctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/ptc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+
+/* ************************************************************************** */
+/*                INSTANCE DEFINITIONS FOR PIC32CM5112GC00064                 */
+/* ************************************************************************** */
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/at.h"
+#include "instance/bromc.h"
+#include "instance/can0.h"
+#include "instance/can1.h"
+#include "instance/ccl0.h"
+#include "instance/ccl1.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/fcr.h"
+#include "instance/fcw.h"
+#include "instance/freqm.h"
+#include "instance/fuses.h"
+#include "instance/gclk.h"
+#include "instance/h2pb0.h"
+#include "instance/h2pb1.h"
+#include "instance/h2pb2.h"
+#include "instance/hmatrix2.h"
+#include "instance/mclk.h"
+#include "instance/mcramc.h"
+#include "instance/osc32kctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/pac.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/ptc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/supc.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/tcc5.h"
+#include "instance/tcc6.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+
+/* ************************************************************************** */
+/*              PERIPHERAL ID DEFINITIONS FOR PIC32CM5112GC00064              */
+/* ************************************************************************** */
+#define ID_DSU           (  0) /* Instance index for DSU (DSU) */
+#define ID_FCR           (  1) /* Instance index for FCR (FCR) */
+#define ID_FCW           (  2) /* Instance index for FCW (FCW) */
+#define ID_PM            (  3) /* Instance index for PM (PM) */
+#define ID_SUPC          (  4) /* Instance index for SUPC (SUPC) */
+#define ID_RSTC          (  5) /* Instance index for RSTC (RSTC) */
+#define ID_OSCCTRL       (  6) /* Instance index for OSCCTRL (OSCCTRL) */
+#define ID_OSC32KCTRL    (  7) /* Instance index for OSC32KCTRL (OSC32KCTRL) */
+#define ID_GCLK          (  8) /* Instance index for GCLK (GCLK) */
+#define ID_MCLK          (  9) /* Instance index for MCLK (MCLK) */
+#define ID_FREQM         ( 10) /* Instance index for FREQM (FREQM) */
+#define ID_WDT           ( 11) /* Instance index for WDT (WDT) */
+#define ID_RTC           ( 12) /* Instance index for RTC (RTC) */
+#define ID_EIC           ( 13) /* Instance index for EIC (EIC) */
+#define ID_PAC           ( 14) /* Instance index for PAC (PAC) */
+#define ID_MCRAMC        ( 16) /* Instance index for MCRAMC (MCRAMC) */
+#define ID_CAN0          ( 17) /* Instance index for CAN0 (CAN0) */
+#define ID_CAN1          ( 18) /* Instance index for CAN1 (CAN1) */
+#define ID_H2PB0         ( 19) /* Instance index for H2PB0 (H2PB0) */
+#define ID_PORT          ( 20) /* Instance index for PORT (PORT) */
+#define ID_DMAC          ( 21) /* Instance index for DMAC (DMAC) */
+#define ID_HMATRIX2      ( 22) /* Instance index for HMATRIX2 (HMATRIX2) */
+#define ID_BROMC         ( 23) /* Instance index for BROMC (BROMC) */
+#define ID_EVSYS         ( 25) /* Instance index for EVSYS (EVSYS) */
+#define ID_SERCOM0       ( 26) /* Instance index for SERCOM0 (SERCOM0) */
+#define ID_SERCOM1       ( 27) /* Instance index for SERCOM1 (SERCOM1) */
+#define ID_SERCOM2       ( 28) /* Instance index for SERCOM2 (SERCOM2) */
+#define ID_SERCOM3       ( 29) /* Instance index for SERCOM3 (SERCOM3) */
+#define ID_TCC0          ( 30) /* Instance index for TCC0 (TCC0) */
+#define ID_TCC1          ( 31) /* Instance index for TCC1 (TCC1) */
+#define ID_TCC2          ( 32) /* Instance index for TCC2 (TCC2) */
+#define ID_TCC3          ( 33) /* Instance index for TCC3 (TCC3) */
+#define ID_SERCOM4       ( 34) /* Instance index for SERCOM4 (SERCOM4) */
+#define ID_SERCOM5       ( 35) /* Instance index for SERCOM5 (SERCOM5) */
+#define ID_TCC4          ( 36) /* Instance index for TCC4 (TCC4) */
+#define ID_TCC5          ( 37) /* Instance index for TCC5 (TCC5) */
+#define ID_TCC6          ( 38) /* Instance index for TCC6 (TCC6) */
+#define ID_ADC           ( 39) /* Instance index for ADC (ADC) */
+#define ID_AC            ( 40) /* Instance index for AC (AC) */
+#define ID_PTC           ( 41) /* Instance index for PTC (PTC) */
+#define ID_CCL0          ( 42) /* Instance index for CCL0 (CCL0) */
+#define ID_CCL1          ( 43) /* Instance index for CCL1 (CCL1) */
+#define ID_USB           ( 44) /* Instance index for USB (USB) */
+#define ID_AT            ( 45) /* Instance index for AT (AT) */
+#define ID_H2PB1         ( 46) /* Instance index for H2PB1 (H2PB1) */
+#define ID_H2PB2         ( 47) /* Instance index for H2PB2 (H2PB2) */
+
+#define ID_PERIPH_MAX    ( 47) /* Number of peripheral IDs */
+
+/* ************************************************************************** */
+/*       REGISTER STRUCTURE ADDRESS DEFINITIONS FOR PIC32CM5112GC00064        */
+/* ************************************************************************** */
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#define AC_REGS                          ((ac_registers_t*)0x4482a000)                 /* AC Registers Address         */
+#define ADC_REGS                         ((adc_registers_t*)0x44818000)                /* ADC Registers Address        */
+#define AT_REGS                          ((at_registers_t*)0x4500c000)                 /* AT Registers Address         */
+#define BROMC_REGS                       ((bromc_registers_t*)0x44804000)              /* BROMC Registers Address      */
+#define CAN0_REGS                        ((can_registers_t*)0x4402e000)                /* CAN0 Registers Address       */
+#define CAN1_REGS                        ((can_registers_t*)0x44030000)                /* CAN1 Registers Address       */
+#define CCL0_REGS                        ((ccl_registers_t*)0x4482e000)                /* CCL0 Registers Address       */
+#define CCL1_REGS                        ((ccl_registers_t*)0x44830000)                /* CCL1 Registers Address       */
+#define DMAC_REGS                        ((dmac_registers_t*)0x44802000)               /* DMAC Registers Address       */
+#define DSU_REGS                         ((dsu_registers_t*)0x44000000)                /* DSU Registers Address        */
+#define EIC_REGS                         ((eic_registers_t*)0x44020000)                /* EIC Registers Address        */
+#define EVSYS_REGS                       ((evsys_registers_t*)0x44806000)              /* EVSYS Registers Address      */
+#define FCR_REGS                         ((fcr_registers_t*)0x44002000)                /* FCR Registers Address        */
+#define FCW_REGS                         ((fcw_registers_t*)0x44004000)                /* FCW Registers Address        */
+#define FREQM_REGS                       ((freqm_registers_t*)0x4400c000)              /* FREQM Registers Address      */
+#define FUSES_ROMCFG_REGS                ((fuses_romcfg_registers_t*)0x0a003000)       /* FUSES Registers Address      */
+#define FUSES_BOOTCFG1_REGS              ((fuses_bootcfg1_registers_t*)0x0a002000)     /* FUSES Registers Address      */
+#define FUSES_BOOTCFG1A_REGS             ((fuses_bootcfg1_registers_t*)0x0a000000)     /* FUSES Registers Address      */
+#define FUSES_CALOTP_REGS                ((fuses_calotp_registers_t*)0x0a007000)       /* FUSES Registers Address      */
+#define GCLK_REGS                        ((gclk_registers_t*)0x44008000)               /* GCLK Registers Address       */
+#define H2PB0_REGS                       ((h2pb_registers_t*)0x44032000)               /* H2PB0 Registers Address      */
+#define H2PB1_REGS                       ((h2pb_registers_t*)0x44838000)               /* H2PB1 Registers Address      */
+#define H2PB2_REGS                       ((h2pb_registers_t*)0x4500e000)               /* H2PB2 Registers Address      */
+#define HMATRIX2_REGS                    ((hmatrix2_registers_t*)0x44010000)           /* HMATRIX2 Registers Address   */
+#define MCLK_REGS                        ((mclk_registers_t*)0x4400a000)               /* MCLK Registers Address       */
+#define MCRAMC_REGS                      ((mcramc_registers_t*)0x4402c000)             /* MCRAMC Registers Address     */
+#define OSC32KCTRL_REGS                  ((osc32kctrl_registers_t*)0x45008000)         /* OSC32KCTRL Registers Address */
+#define OSCCTRL_REGS                     ((oscctrl_registers_t*)0x44006000)            /* OSCCTRL Registers Address    */
+#define PAC_REGS                         ((pac_registers_t*)0x44022000)                /* PAC Registers Address        */
+#define PM_REGS                          ((pm_registers_t*)0x45000000)                 /* PM Registers Address         */
+#define PORT_REGS                        ((port_registers_t*)0x44800000)               /* PORT Registers Address       */
+#define PTC_REGS                         ((ptc_registers_t*)0x4482c000)                /* PTC Registers Address        */
+#define RSTC_REGS                        ((rstc_registers_t*)0x45004000)               /* RSTC Registers Address       */
+#define RTC_REGS                         ((rtc_registers_t*)0x45006000)                /* RTC Registers Address        */
+#define SERCOM0_REGS                     ((sercom_registers_t*)0x44808000)             /* SERCOM0 Registers Address    */
+#define SERCOM1_REGS                     ((sercom_registers_t*)0x4480a000)             /* SERCOM1 Registers Address    */
+#define SERCOM2_REGS                     ((sercom_registers_t*)0x4480c000)             /* SERCOM2 Registers Address    */
+#define SERCOM3_REGS                     ((sercom_registers_t*)0x4480e000)             /* SERCOM3 Registers Address    */
+#define SERCOM4_REGS                     ((sercom_registers_t*)0x44820000)             /* SERCOM4 Registers Address    */
+#define SERCOM5_REGS                     ((sercom_registers_t*)0x44822000)             /* SERCOM5 Registers Address    */
+#define SUPC_REGS                        ((supc_registers_t*)0x45002000)               /* SUPC Registers Address       */
+#define TCC0_REGS                        ((tcc_registers_t*)0x44810000)                /* TCC0 Registers Address       */
+#define TCC1_REGS                        ((tcc_registers_t*)0x44812000)                /* TCC1 Registers Address       */
+#define TCC2_REGS                        ((tcc_registers_t*)0x44814000)                /* TCC2 Registers Address       */
+#define TCC3_REGS                        ((tcc_registers_t*)0x44816000)                /* TCC3 Registers Address       */
+#define TCC4_REGS                        ((tcc_registers_t*)0x44824000)                /* TCC4 Registers Address       */
+#define TCC5_REGS                        ((tcc_registers_t*)0x44826000)                /* TCC5 Registers Address       */
+#define TCC6_REGS                        ((tcc_registers_t*)0x44828000)                /* TCC6 Registers Address       */
+#define USB_REGS                         ((usb_registers_t*)0x44832000)                /* USB Registers Address        */
+#define WDT_REGS                         ((wdt_registers_t*)0x4400e000)                /* WDT Registers Address        */
+#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ************************************************************************** */
+/*              BASE ADDRESS DEFINITIONS FOR PIC32CM5112GC00064               */
+/* ************************************************************************** */
+#define AC_BASE_ADDRESS                  _UINT32_(0x4482a000)                          /* AC Base Address */
+#define ADC_BASE_ADDRESS                 _UINT32_(0x44818000)                          /* ADC Base Address */
+#define AT_BASE_ADDRESS                  _UINT32_(0x4500c000)                          /* AT Base Address */
+#define BROMC_BASE_ADDRESS               _UINT32_(0x44804000)                          /* BROMC Base Address */
+#define CAN0_BASE_ADDRESS                _UINT32_(0x4402e000)                          /* CAN0 Base Address */
+#define CAN1_BASE_ADDRESS                _UINT32_(0x44030000)                          /* CAN1 Base Address */
+#define CCL0_BASE_ADDRESS                _UINT32_(0x4482e000)                          /* CCL0 Base Address */
+#define CCL1_BASE_ADDRESS                _UINT32_(0x44830000)                          /* CCL1 Base Address */
+#define DMAC_BASE_ADDRESS                _UINT32_(0x44802000)                          /* DMAC Base Address */
+#define DSU_BASE_ADDRESS                 _UINT32_(0x44000000)                          /* DSU Base Address */
+#define EIC_BASE_ADDRESS                 _UINT32_(0x44020000)                          /* EIC Base Address */
+#define EVSYS_BASE_ADDRESS               _UINT32_(0x44806000)                          /* EVSYS Base Address */
+#define FCR_BASE_ADDRESS                 _UINT32_(0x44002000)                          /* FCR Base Address */
+#define FCW_BASE_ADDRESS                 _UINT32_(0x44004000)                          /* FCW Base Address */
+#define FREQM_BASE_ADDRESS               _UINT32_(0x4400c000)                          /* FREQM Base Address */
+#define FUSES_ROMCFG_BASE_ADDRESS        _UINT32_(0x0a003000)                          /* FUSES Base Address */
+#define FUSES_BOOTCFG1_BASE_ADDRESS      _UINT32_(0x0a002000)                          /* FUSES Base Address */
+#define FUSES_BOOTCFG1A_BASE_ADDRESS     _UINT32_(0x0a000000)                          /* FUSES Base Address */
+#define FUSES_CALOTP_BASE_ADDRESS        _UINT32_(0x0a007000)                          /* FUSES Base Address */
+#define GCLK_BASE_ADDRESS                _UINT32_(0x44008000)                          /* GCLK Base Address */
+#define H2PB0_BASE_ADDRESS               _UINT32_(0x44032000)                          /* H2PB0 Base Address */
+#define H2PB1_BASE_ADDRESS               _UINT32_(0x44838000)                          /* H2PB1 Base Address */
+#define H2PB2_BASE_ADDRESS               _UINT32_(0x4500e000)                          /* H2PB2 Base Address */
+#define HMATRIX2_BASE_ADDRESS            _UINT32_(0x44010000)                          /* HMATRIX2 Base Address */
+#define MCLK_BASE_ADDRESS                _UINT32_(0x4400a000)                          /* MCLK Base Address */
+#define MCRAMC_BASE_ADDRESS              _UINT32_(0x4402c000)                          /* MCRAMC Base Address */
+#define OSC32KCTRL_BASE_ADDRESS          _UINT32_(0x45008000)                          /* OSC32KCTRL Base Address */
+#define OSCCTRL_BASE_ADDRESS             _UINT32_(0x44006000)                          /* OSCCTRL Base Address */
+#define PAC_BASE_ADDRESS                 _UINT32_(0x44022000)                          /* PAC Base Address */
+#define PM_BASE_ADDRESS                  _UINT32_(0x45000000)                          /* PM Base Address */
+#define PORT_BASE_ADDRESS                _UINT32_(0x44800000)                          /* PORT Base Address */
+#define PTC_BASE_ADDRESS                 _UINT32_(0x4482c000)                          /* PTC Base Address */
+#define RSTC_BASE_ADDRESS                _UINT32_(0x45004000)                          /* RSTC Base Address */
+#define RTC_BASE_ADDRESS                 _UINT32_(0x45006000)                          /* RTC Base Address */
+#define SERCOM0_BASE_ADDRESS             _UINT32_(0x44808000)                          /* SERCOM0 Base Address */
+#define SERCOM1_BASE_ADDRESS             _UINT32_(0x4480a000)                          /* SERCOM1 Base Address */
+#define SERCOM2_BASE_ADDRESS             _UINT32_(0x4480c000)                          /* SERCOM2 Base Address */
+#define SERCOM3_BASE_ADDRESS             _UINT32_(0x4480e000)                          /* SERCOM3 Base Address */
+#define SERCOM4_BASE_ADDRESS             _UINT32_(0x44820000)                          /* SERCOM4 Base Address */
+#define SERCOM5_BASE_ADDRESS             _UINT32_(0x44822000)                          /* SERCOM5 Base Address */
+#define SUPC_BASE_ADDRESS                _UINT32_(0x45002000)                          /* SUPC Base Address */
+#define TCC0_BASE_ADDRESS                _UINT32_(0x44810000)                          /* TCC0 Base Address */
+#define TCC1_BASE_ADDRESS                _UINT32_(0x44812000)                          /* TCC1 Base Address */
+#define TCC2_BASE_ADDRESS                _UINT32_(0x44814000)                          /* TCC2 Base Address */
+#define TCC3_BASE_ADDRESS                _UINT32_(0x44816000)                          /* TCC3 Base Address */
+#define TCC4_BASE_ADDRESS                _UINT32_(0x44824000)                          /* TCC4 Base Address */
+#define TCC5_BASE_ADDRESS                _UINT32_(0x44826000)                          /* TCC5 Base Address */
+#define TCC6_BASE_ADDRESS                _UINT32_(0x44828000)                          /* TCC6 Base Address */
+#define USB_BASE_ADDRESS                 _UINT32_(0x44832000)                          /* USB Base Address */
+#define WDT_BASE_ADDRESS                 _UINT32_(0x4400e000)                          /* WDT Base Address */
+
+/* ************************************************************************** */
+/*                   PIO DEFINITIONS FOR PIC32CM5112GC00064                   */
+/* ************************************************************************** */
+#include "pio/pic32cm5112gc00064.h"
+
+/* ************************************************************************** */
+/*             MEMORY MAPPING DEFINITIONS FOR PIC32CM5112GC00064              */
+/* ************************************************************************** */
+#define BROMC_ROM_SIZE                 _UINT32_(0x00010000)    /*   64kB Memory segment type: rom */
+#define FCR_BFM_SIZE                   _UINT32_(0x00004000)    /*   16kB Memory segment type: flash */
+#define FCR_CFM_BOOTCFG1A_SIZE         _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_USEROTP_SIZE           _UINT32_(0x00001000)    /*    4kB Memory segment type: user_signatures */
+#define FCR_CFM_BOOTCFG1_SIZE          _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_ROMCFG_SIZE            _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_VSS0_SIZE              _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_VSS1_SIZE              _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_TEST_SIZE              _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_CALOTP_SIZE            _UINT32_(0x00001000)    /*    4kB Memory segment type: other */
+#define FCR_PFM_SIZE                   _UINT32_(0x00080000)    /*  512kB Memory segment type: flash */
+#define MCRAMC_RET_SIZE                _UINT32_(0x00020000)    /*  128kB Memory segment type: ram */
+#define APB0_BRIDGE_SIZE               _UINT32_(0x00034000)    /*  208kB Memory segment type: io */
+#define APB1_BRIDGE_SIZE               _UINT32_(0x0003a000)    /*  232kB Memory segment type: io */
+#define APB2_BRIDGE_SIZE               _UINT32_(0x00010000)    /*   64kB Memory segment type: io */
+#define PPB_SIZE                       _UINT32_(0x00100000)    /* 1024kB Memory segment type: io */
+
+#define BROMC_ROM_ADDR                 _UINT32_(0x04000000)    /* BROMC_ROM base address (type: rom)*/
+#define FCR_BFM_ADDR                   _UINT32_(0x08000000)    /* FCR_BFM base address (type: flash)*/
+#define FCR_CFM_BOOTCFG1A_ADDR         _UINT32_(0x0a000000)    /* FCR_CFM_BOOTCFG1A base address (type: flash)*/
+#define FCR_CFM_USEROTP_ADDR           _UINT32_(0x0a001000)    /* FCR_CFM_USEROTP base address (type: user_signatures)*/
+#define FCR_CFM_BOOTCFG1_ADDR          _UINT32_(0x0a002000)    /* FCR_CFM_BOOTCFG1 base address (type: flash)*/
+#define FCR_CFM_ROMCFG_ADDR            _UINT32_(0x0a003000)    /* FCR_CFM_ROMCFG base address (type: flash)*/
+#define FCR_CFM_VSS0_ADDR              _UINT32_(0x0a004000)    /* FCR_CFM_VSS0 base address (type: flash)*/
+#define FCR_CFM_VSS1_ADDR              _UINT32_(0x0a005000)    /* FCR_CFM_VSS1 base address (type: flash)*/
+#define FCR_CFM_TEST_ADDR              _UINT32_(0x0a006000)    /* FCR_CFM_TEST base address (type: flash)*/
+#define FCR_CFM_CALOTP_ADDR            _UINT32_(0x0a007000)    /* FCR_CFM_CALOTP base address (type: other)*/
+#define FCR_PFM_ADDR                   _UINT32_(0x0c000000)    /* FCR_PFM base address (type: flash)*/
+#define MCRAMC_RET_ADDR                _UINT32_(0x20000000)    /* MCRAMC_RET base address (type: ram)*/
+#define APB0_BRIDGE_ADDR               _UINT32_(0x44000000)    /* APB0_BRIDGE base address (type: io)*/
+#define APB1_BRIDGE_ADDR               _UINT32_(0x44800000)    /* APB1_BRIDGE base address (type: io)*/
+#define APB2_BRIDGE_ADDR               _UINT32_(0x45000000)    /* APB2_BRIDGE base address (type: io)*/
+#define PPB_ADDR                       _UINT32_(0xe0000000)    /* PPB base address (type: io)*/
+
+/* ************************************************************************** */
+/*                  DEVICE SIGNATURES FOR PIC32CM5112GC00064                  */
+/* ************************************************************************** */
+#define CHIP_DSU_DID                   _UINT32_(0X0AC01053)
+
+/* ************************************************************************** */
+/*               ELECTRICAL DEFINITIONS FOR PIC32CM5112GC00064                */
+/* ************************************************************************** */
+
+/* ************************************************************************** */
+/*                  Event Generator IDs for C32CM5112GC00064                  */
+/* ************************************************************************** */
+#define EVENT_ID_GEN_SUPC_LVDET                           1 /* ID for SUPC event generator LVDET */
+#define EVENT_ID_GEN_OSCCTRL_XOSCFAIL                     2 /* ID for OSCCTRL event generator XOSCFAIL */
+#define EVENT_ID_GEN_OSC32KCTRL_XOSC32KFAIL               3 /* ID for OSC32KCTRL event generator XOSC32KFAIL */
+#define EVENT_ID_GEN_FREQM_DONE                           4 /* ID for FREQM event generator DONE */
+#define EVENT_ID_GEN_FREQM_WINMON                         5 /* ID for FREQM event generator WINMON */
+#define EVENT_ID_GEN_RTC_PER0                             6 /* ID for RTC event generator PER0 */
+#define EVENT_ID_GEN_RTC_PER1                             7 /* ID for RTC event generator PER1 */
+#define EVENT_ID_GEN_RTC_PER2                             8 /* ID for RTC event generator PER2 */
+#define EVENT_ID_GEN_RTC_PER3                             9 /* ID for RTC event generator PER3 */
+#define EVENT_ID_GEN_RTC_PER4                            10 /* ID for RTC event generator PER4 */
+#define EVENT_ID_GEN_RTC_PER5                            11 /* ID for RTC event generator PER5 */
+#define EVENT_ID_GEN_RTC_PER6                            12 /* ID for RTC event generator PER6 */
+#define EVENT_ID_GEN_RTC_PER7                            13 /* ID for RTC event generator PER7 */
+#define EVENT_ID_GEN_RTC_CMP0                            14 /* ID for RTC event generator CMP0 */
+#define EVENT_ID_GEN_RTC_CMP1                            15 /* ID for RTC event generator CMP1 */
+#define EVENT_ID_GEN_RTC_CMP2                            16 /* ID for RTC event generator CMP2 */
+#define EVENT_ID_GEN_RTC_CMP3                            17 /* ID for RTC event generator CMP3 */
+#define EVENT_ID_GEN_RTC_TAMPER                          18 /* ID for RTC event generator TAMPER */
+#define EVENT_ID_GEN_RTC_OVF                             19 /* ID for RTC event generator OVF */
+#define EVENT_ID_GEN_RTC_PERD                            20 /* ID for RTC event generator PERD */
+#define EVENT_ID_GEN_EIC_EXTINT0                         21 /* ID for EIC event generator EXTINT0 */
+#define EVENT_ID_GEN_EIC_EXTINT1                         22 /* ID for EIC event generator EXTINT1 */
+#define EVENT_ID_GEN_EIC_EXTINT2                         23 /* ID for EIC event generator EXTINT2 */
+#define EVENT_ID_GEN_EIC_EXTINT3                         24 /* ID for EIC event generator EXTINT3 */
+#define EVENT_ID_GEN_EIC_EXTINT4                         25 /* ID for EIC event generator EXTINT4 */
+#define EVENT_ID_GEN_EIC_EXTINT5                         26 /* ID for EIC event generator EXTINT5 */
+#define EVENT_ID_GEN_EIC_EXTINT6                         27 /* ID for EIC event generator EXTINT6 */
+#define EVENT_ID_GEN_EIC_EXTINT7                         28 /* ID for EIC event generator EXTINT7 */
+#define EVENT_ID_GEN_EIC_EXTINT8                         29 /* ID for EIC event generator EXTINT8 */
+#define EVENT_ID_GEN_EIC_EXTINT9                         30 /* ID for EIC event generator EXTINT9 */
+#define EVENT_ID_GEN_EIC_EXTINT10                        31 /* ID for EIC event generator EXTINT10 */
+#define EVENT_ID_GEN_EIC_EXTINT11                        32 /* ID for EIC event generator EXTINT11 */
+#define EVENT_ID_GEN_EIC_EXTINT12                        33 /* ID for EIC event generator EXTINT12 */
+#define EVENT_ID_GEN_EIC_EXTINT13                        34 /* ID for EIC event generator EXTINT13 */
+#define EVENT_ID_GEN_EIC_EXTINT14                        35 /* ID for EIC event generator EXTINT14 */
+#define EVENT_ID_GEN_EIC_EXTINT15                        36 /* ID for EIC event generator EXTINT15 */
+#define EVENT_ID_GEN_DMAC_CH0                            37 /* ID for DMAC event generator CH0 */
+#define EVENT_ID_GEN_DMAC_CH1                            38 /* ID for DMAC event generator CH1 */
+#define EVENT_ID_GEN_DMAC_CH2                            39 /* ID for DMAC event generator CH2 */
+#define EVENT_ID_GEN_DMAC_CH3                            40 /* ID for DMAC event generator CH3 */
+#define EVENT_ID_GEN_TCC0_OVF                            41 /* ID for TCC0 event generator OVF */
+#define EVENT_ID_GEN_TCC0_TRG                            42 /* ID for TCC0 event generator TRG */
+#define EVENT_ID_GEN_TCC0_CNT                            43 /* ID for TCC0 event generator CNT */
+#define EVENT_ID_GEN_TCC0_MC0                            44 /* ID for TCC0 event generator MC0 */
+#define EVENT_ID_GEN_TCC0_MC1                            45 /* ID for TCC0 event generator MC1 */
+#define EVENT_ID_GEN_TCC1_OVF                            46 /* ID for TCC1 event generator OVF */
+#define EVENT_ID_GEN_TCC1_TRG                            47 /* ID for TCC1 event generator TRG */
+#define EVENT_ID_GEN_TCC1_CNT                            48 /* ID for TCC1 event generator CNT */
+#define EVENT_ID_GEN_TCC1_MC0                            49 /* ID for TCC1 event generator MC0 */
+#define EVENT_ID_GEN_TCC1_MC1                            50 /* ID for TCC1 event generator MC1 */
+#define EVENT_ID_GEN_TCC2_OVF                            51 /* ID for TCC2 event generator OVF */
+#define EVENT_ID_GEN_TCC2_TRG                            52 /* ID for TCC2 event generator TRG */
+#define EVENT_ID_GEN_TCC2_CNT                            53 /* ID for TCC2 event generator CNT */
+#define EVENT_ID_GEN_TCC2_MC0                            54 /* ID for TCC2 event generator MC0 */
+#define EVENT_ID_GEN_TCC2_MC1                            55 /* ID for TCC2 event generator MC1 */
+#define EVENT_ID_GEN_TCC3_OVF                            56 /* ID for TCC3 event generator OVF */
+#define EVENT_ID_GEN_TCC3_TRG                            57 /* ID for TCC3 event generator TRG */
+#define EVENT_ID_GEN_TCC3_CNT                            58 /* ID for TCC3 event generator CNT */
+#define EVENT_ID_GEN_TCC3_MC0                            59 /* ID for TCC3 event generator MC0 */
+#define EVENT_ID_GEN_TCC3_MC1                            60 /* ID for TCC3 event generator MC1 */
+#define EVENT_ID_GEN_TCC4_OVF                            61 /* ID for TCC4 event generator OVF */
+#define EVENT_ID_GEN_TCC4_TRG                            62 /* ID for TCC4 event generator TRG */
+#define EVENT_ID_GEN_TCC4_CNT                            63 /* ID for TCC4 event generator CNT */
+#define EVENT_ID_GEN_TCC4_MC0                            64 /* ID for TCC4 event generator MC0 */
+#define EVENT_ID_GEN_TCC4_MC1                            65 /* ID for TCC4 event generator MC1 */
+#define EVENT_ID_GEN_TCC5_OVF                            66 /* ID for TCC5 event generator OVF */
+#define EVENT_ID_GEN_TCC5_TRG                            67 /* ID for TCC5 event generator TRG */
+#define EVENT_ID_GEN_TCC5_CNT                            68 /* ID for TCC5 event generator CNT */
+#define EVENT_ID_GEN_TCC5_MC0                            69 /* ID for TCC5 event generator MC0 */
+#define EVENT_ID_GEN_TCC5_MC1                            70 /* ID for TCC5 event generator MC1 */
+#define EVENT_ID_GEN_TCC6_OVF                            71 /* ID for TCC6 event generator OVF */
+#define EVENT_ID_GEN_TCC6_TRG                            72 /* ID for TCC6 event generator TRG */
+#define EVENT_ID_GEN_TCC6_CNT                            73 /* ID for TCC6 event generator CNT */
+#define EVENT_ID_GEN_TCC6_MC0                            74 /* ID for TCC6 event generator MC0 */
+#define EVENT_ID_GEN_TCC6_MC1                            75 /* ID for TCC6 event generator MC1 */
+#define EVENT_ID_GEN_ADC_CHRDY                           76 /* ID for ADC event generator CHRDY */
+#define EVENT_ID_GEN_ADC_CMP                             77 /* ID for ADC event generator CMP */
+#define EVENT_ID_GEN_AC_COMP0                            78 /* ID for AC event generator COMP0 */
+#define EVENT_ID_GEN_AC_COMP1                            79 /* ID for AC event generator COMP1 */
+#define EVENT_ID_GEN_AC_WIN0                             80 /* ID for AC event generator WIN0 */
+#define EVENT_ID_GEN_PTC_EOC                             81 /* ID for PTC event generator EOC */
+#define EVENT_ID_GEN_PTC_WCOMP                           82 /* ID for PTC event generator WCOMP */
+#define EVENT_ID_GEN_CCL0_LUTOUT0                        83 /* ID for CCL0 event generator LUTOUT0 */
+#define EVENT_ID_GEN_CCL0_LUTOUT1                        84 /* ID for CCL0 event generator LUTOUT1 */
+#define EVENT_ID_GEN_CCL0_LUTOUT2                        85 /* ID for CCL0 event generator LUTOUT2 */
+#define EVENT_ID_GEN_CCL0_LUTOUT3                        86 /* ID for CCL0 event generator LUTOUT3 */
+#define EVENT_ID_GEN_CCL1_LUTOUT0                        87 /* ID for CCL1 event generator LUTOUT0 */
+#define EVENT_ID_GEN_CCL1_LUTOUT1                        88 /* ID for CCL1 event generator LUTOUT1 */
+#define EVENT_ID_GEN_CCL1_LUTOUT2                        89 /* ID for CCL1 event generator LUTOUT2 */
+#define EVENT_ID_GEN_CCL1_LUTOUT3                        90 /* ID for CCL1 event generator LUTOUT3 */
+
+/* ************************************************************************** */
+/*                    Event User IDs for C32CM5112GC00064                     */
+/* ************************************************************************** */
+#define EVENT_ID_USER_FREQM_START                         0 /* ID for FREQM event user START */
+#define EVENT_ID_USER_RTC_TAMPER                          1 /* ID for RTC event user TAMPER */
+#define EVENT_ID_USER_PORT_EV0                            2 /* ID for PORT event user EV0 */
+#define EVENT_ID_USER_PORT_EV1                            3 /* ID for PORT event user EV1 */
+#define EVENT_ID_USER_PORT_EV2                            4 /* ID for PORT event user EV2 */
+#define EVENT_ID_USER_PORT_EV3                            5 /* ID for PORT event user EV3 */
+#define EVENT_ID_USER_DMAC_CH0                            6 /* ID for DMAC event user CH0 */
+#define EVENT_ID_USER_DMAC_CH1                            7 /* ID for DMAC event user CH1 */
+#define EVENT_ID_USER_DMAC_CH2                            8 /* ID for DMAC event user CH2 */
+#define EVENT_ID_USER_DMAC_CH3                            9 /* ID for DMAC event user CH3 */
+#define EVENT_ID_USER_TCC0_EV0                           10 /* ID for TCC0 event user EV0 */
+#define EVENT_ID_USER_TCC0_EV1                           11 /* ID for TCC0 event user EV1 */
+#define EVENT_ID_USER_TCC0_MC0                           12 /* ID for TCC0 event user MC0 */
+#define EVENT_ID_USER_TCC0_MC1                           13 /* ID for TCC0 event user MC1 */
+#define EVENT_ID_USER_TCC1_EV0                           14 /* ID for TCC1 event user EV0 */
+#define EVENT_ID_USER_TCC1_EV1                           15 /* ID for TCC1 event user EV1 */
+#define EVENT_ID_USER_TCC1_MC0                           16 /* ID for TCC1 event user MC0 */
+#define EVENT_ID_USER_TCC1_MC1                           17 /* ID for TCC1 event user MC1 */
+#define EVENT_ID_USER_TCC2_EV0                           18 /* ID for TCC2 event user EV0 */
+#define EVENT_ID_USER_TCC2_EV1                           19 /* ID for TCC2 event user EV1 */
+#define EVENT_ID_USER_TCC2_MC0                           20 /* ID for TCC2 event user MC0 */
+#define EVENT_ID_USER_TCC2_MC1                           21 /* ID for TCC2 event user MC1 */
+#define EVENT_ID_USER_TCC3_EV0                           22 /* ID for TCC3 event user EV0 */
+#define EVENT_ID_USER_TCC3_EV1                           23 /* ID for TCC3 event user EV1 */
+#define EVENT_ID_USER_TCC3_MC0                           24 /* ID for TCC3 event user MC0 */
+#define EVENT_ID_USER_TCC3_MC1                           25 /* ID for TCC3 event user MC1 */
+#define EVENT_ID_USER_TCC4_EV0                           26 /* ID for TCC4 event user EV0 */
+#define EVENT_ID_USER_TCC4_EV1                           27 /* ID for TCC4 event user EV1 */
+#define EVENT_ID_USER_TCC4_MC0                           28 /* ID for TCC4 event user MC0 */
+#define EVENT_ID_USER_TCC4_MC1                           29 /* ID for TCC4 event user MC1 */
+#define EVENT_ID_USER_TCC5_EV0                           30 /* ID for TCC5 event user EV0 */
+#define EVENT_ID_USER_TCC5_EV1                           31 /* ID for TCC5 event user EV1 */
+#define EVENT_ID_USER_TCC5_MC0                           32 /* ID for TCC5 event user MC0 */
+#define EVENT_ID_USER_TCC5_MC1                           33 /* ID for TCC5 event user MC1 */
+#define EVENT_ID_USER_TCC6_EV0                           34 /* ID for TCC6 event user EV0 */
+#define EVENT_ID_USER_TCC6_EV1                           35 /* ID for TCC6 event user EV1 */
+#define EVENT_ID_USER_TCC6_MC0                           36 /* ID for TCC6 event user MC0 */
+#define EVENT_ID_USER_TCC6_MC1                           37 /* ID for TCC6 event user MC1 */
+#define EVENT_ID_USER_ADC_TRIG0                          38 /* ID for ADC event user TRIG0 */
+#define EVENT_ID_USER_ADC_TRIG1                          39 /* ID for ADC event user TRIG1 */
+#define EVENT_ID_USER_ADC_TRIG2                          40 /* ID for ADC event user TRIG2 */
+#define EVENT_ID_USER_ADC_TRIG3                          41 /* ID for ADC event user TRIG3 */
+#define EVENT_ID_USER_ADC_TRIG4                          42 /* ID for ADC event user TRIG4 */
+#define EVENT_ID_USER_ADC_TRIG5                          43 /* ID for ADC event user TRIG5 */
+#define EVENT_ID_USER_ADC_TRIG6                          44 /* ID for ADC event user TRIG6 */
+#define EVENT_ID_USER_ADC_TRIG7                          45 /* ID for ADC event user TRIG7 */
+#define EVENT_ID_USER_ADC_TRIG8                          46 /* ID for ADC event user TRIG8 */
+#define EVENT_ID_USER_ADC_TRIG9                          47 /* ID for ADC event user TRIG9 */
+#define EVENT_ID_USER_ADC_TRIG10                         48 /* ID for ADC event user TRIG10 */
+#define EVENT_ID_USER_AC_SOC0                            49 /* ID for AC event user SOC0 */
+#define EVENT_ID_USER_AC_SOC1                            50 /* ID for AC event user SOC1 */
+#define EVENT_ID_USER_PTC_DSEQR                          51 /* ID for PTC event user DSEQR */
+#define EVENT_ID_USER_PTC_STCONV                         52 /* ID for PTC event user STCONV */
+#define EVENT_ID_USER_CCL0_LUTIN0                        53 /* ID for CCL0 event user LUTIN0 */
+#define EVENT_ID_USER_CCL0_LUTIN1                        54 /* ID for CCL0 event user LUTIN1 */
+#define EVENT_ID_USER_CCL0_LUTIN2                        55 /* ID for CCL0 event user LUTIN2 */
+#define EVENT_ID_USER_CCL0_LUTIN3                        56 /* ID for CCL0 event user LUTIN3 */
+#define EVENT_ID_USER_CCL1_LUTIN0                        57 /* ID for CCL1 event user LUTIN0 */
+#define EVENT_ID_USER_CCL1_LUTIN1                        58 /* ID for CCL1 event user LUTIN1 */
+#define EVENT_ID_USER_CCL1_LUTIN2                        59 /* ID for CCL1 event user LUTIN2 */
+#define EVENT_ID_USER_CCL1_LUTIN3                        60 /* ID for CCL1 event user LUTIN3 */
+#define EVENT_ID_USER_AT_TAMPSRC5                        61 /* ID for AT event user TAMPSRC5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PIC32CM5112GC00064_H_ */
+
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32cm5112gc00100.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32cm5112gc00100.h
new file mode 100644
index 00000000..7444d72d
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pic32cm5112gc00100.h
@@ -0,0 +1,1029 @@
+/*
+ * Header file for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/* File generated from device description file (ATDF) version 2024-11-05T16:47:43Z */
+#ifndef _PIC32CM5112GC00100_H_
+#define _PIC32CM5112GC00100_H_
+
+/* Header version uses Semantic Versioning 2.0.0 (https://semver.org/) */
+#define HEADER_FORMAT_VERSION "2.1.1"
+
+#define HEADER_FORMAT_VERSION_MAJOR (2)
+#define HEADER_FORMAT_VERSION_MINOR (1)
+#define HEADER_FORMAT_VERSION_PATCH (1)
+
+/* PIC32CM5112GC00100 definitions
+  This file defines all structures and symbols for PIC32CM5112GC00100:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  include <stdint.h>
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#  if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_)
+#    error "Integer constant value macros already defined elsewhere"
+#  endif
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with sizes of integer constants for C/C++ */
+#  define _UINT8_(x)   ((uint8_t)(x))    /* C code: 8-bits unsigned integer constant value */
+#  define _UINT16_(x)  ((uint16_t)(x))   /* C code: 16-bits unsigned integer constant value */
+#  define _UINT32_(x)  ((uint32_t)(x))   /* C code: 32-bits unsigned integer constant value */
+
+#else /* Assembler */
+
+#  define _UINT8_(x) x    /* Assembler: 8-bits unsigned integer constant value */
+#  define _UINT16_(x) x   /* Assembler: 16-bits unsigned integer constant value */
+#  define _UINT32_(x) x   /* Assembler: 32-bits unsigned integer constant value */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/*                  CMSIS DEFINITIONS FOR PIC32CM5112GC00100                  */
+/* ************************************************************************** */
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  CORTEX-M23 Processor Exceptions Numbers ******************************/
+  Reset_IRQn                = -15, /* -15 Reset Vector, invoked on Power up and warm reset */
+  NonMaskableInt_IRQn       = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */
+  HardFault_IRQn            = -13, /* -13 Hard Fault, all classes of Fault    */
+  SVCall_IRQn               =  -5, /* -5  System Service Call via SVC instruction */
+  PendSV_IRQn               =  -2, /* -2  Pendable request for system service */
+  SysTick_IRQn              =  -1, /* -1  System Tick Timer                   */
+
+/* ************* PIC32CM5112GC00100 specific Interrupt Numbers ************** */
+  FCR_IRQn                  =   0, /* 0   Polaris Flash Read Controller (FCR) */
+  FCW_IRQn                  =   1, /* 1   Polaris Flash Write Controller (FCW) */
+  PM_IRQn                   =   2, /* 2   Power Manager (PM)                  */
+  SUPC_IRQn                 =   3, /* 3   Supply Controller (SUPC)            */
+  OSCCTRL_XOSCRDY_IRQn      =   4, /* 4   Oscillators Control (OSCCTRL)       */
+  OSCCTRL_DFLLRDY_IRQn      =   5, /* 5   Oscillators Control (OSCCTRL)       */
+  OSCCTRL_PLLLOCKR_0_IRQn   =   6, /* 6   Oscillators Control (OSCCTRL)       */
+  OSC32KCTRL_XOSC32KRDY_IRQn =   7, /* 7   32kHz Oscillators Control (OSC32KCTRL) */
+  OSC32KCTRL_XOSC32KFAIL_IRQn =   8, /* 8   32kHz Oscillators Control (OSC32KCTRL) */
+  MCLK_IRQn                 =   9, /* 9   Polaris Main Clock Controller (MCLK) */
+  FREQM_IRQn                =  10, /* 10  Frequency Meter (FREQM)             */
+  WDT_IRQn                  =  11, /* 11  Watchdog Timer (WDT)                */
+  RTC_TAMPER_IRQn           =  12, /* 12  Real-Time Counter (RTC)             */
+  RTC_OVF_IRQn              =  13, /* 13  Real-Time Counter (RTC)             */
+  RTC_PER0_IRQn             =  14, /* 14  Real-Time Counter (RTC)             */
+  RTC_CMP0_IRQn             =  15, /* 15  Real-Time Counter (RTC)             */
+  EIC_EXTINT0_IRQn          =  16, /* 16  External Interrupt Controller (EIC) */
+  EIC_EXTINT1_IRQn          =  17, /* 17  External Interrupt Controller (EIC) */
+  EIC_EXTINT2_IRQn          =  18, /* 18  External Interrupt Controller (EIC) */
+  EIC_EXTINT3_IRQn          =  19, /* 19  External Interrupt Controller (EIC) */
+  EIC_EXTINT4_IRQn          =  20, /* 20  External Interrupt Controller (EIC) */
+  EIC_EXTINT5_IRQn          =  21, /* 21  External Interrupt Controller (EIC) */
+  EIC_EXTINT6_IRQn          =  22, /* 22  External Interrupt Controller (EIC) */
+  EIC_EXTINT7_IRQn          =  23, /* 23  External Interrupt Controller (EIC) */
+  EIC_EXTINT8_IRQn          =  24, /* 24  External Interrupt Controller (EIC) */
+  EIC_EXTINT9_IRQn          =  25, /* 25  External Interrupt Controller (EIC) */
+  EIC_EXTINT10_IRQn         =  26, /* 26  External Interrupt Controller (EIC) */
+  EIC_EXTINT11_IRQn         =  27, /* 27  External Interrupt Controller (EIC) */
+  EIC_EXTINT12_IRQn         =  28, /* 28  External Interrupt Controller (EIC) */
+  EIC_EXTINT13_IRQn         =  29, /* 29  External Interrupt Controller (EIC) */
+  EIC_EXTINT14_IRQn         =  30, /* 30  External Interrupt Controller (EIC) */
+  EIC_EXTINT15_IRQn         =  31, /* 31  External Interrupt Controller (EIC) */
+  EIC_NSCHK_IRQn            =  32, /* 32  External Interrupt Controller (EIC) */
+  MCRAMC_IRQn               =  34, /* 34  Multi-Channel RAM Controller (MCRAMC) */
+  CAN0_INT0_IRQn            =  35, /* 35  Control Area Network (CAN0)         */
+  CAN0_INT1_IRQn            =  36, /* 36  Control Area Network (CAN0)         */
+  CAN0_BERR_IRQn            =  37, /* 37  Control Area Network (CAN0)         */
+  CAN1_INT0_IRQn            =  38, /* 38  Control Area Network (CAN1)         */
+  CAN1_INT1_IRQn            =  39, /* 39  Control Area Network (CAN1)         */
+  CAN1_BERR_IRQn            =  40, /* 40  Control Area Network (CAN1)         */
+  PORT_IRQn                 =  41, /* 41  Port Module (PORT)                  */
+  DMAC_TCMPL0_IRQn          =  42, /* 42  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL1_IRQn          =  43, /* 43  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL2_IRQn          =  44, /* 44  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL3_IRQn          =  45, /* 45  Direct Memory Access Controller (DMAC) */
+  DMAC_TCMPL4_IRQn          =  46, /* 46  Direct Memory Access Controller (DMAC) */
+  HMATRIX2_IRQn             =  47, /* 47  HSB Matrix (HMATRIX2)               */
+  EVSYS_EVD0_IRQn           =  48, /* 48  Event System Interface (EVSYS)      */
+  EVSYS_EVD1_IRQn           =  49, /* 49  Event System Interface (EVSYS)      */
+  EVSYS_EVD2_IRQn           =  50, /* 50  Event System Interface (EVSYS)      */
+  EVSYS_EVD3_IRQn           =  51, /* 51  Event System Interface (EVSYS)      */
+  EVSYS_EVD4_IRQn           =  52, /* 52  Event System Interface (EVSYS)      */
+  EVSYS_EVD5_IRQn           =  53, /* 53  Event System Interface (EVSYS)      */
+  EVSYS_EVD6_IRQn           =  54, /* 54  Event System Interface (EVSYS)      */
+  EVSYS_EVD7_IRQn           =  55, /* 55  Event System Interface (EVSYS)      */
+  EVSYS_EVD8_IRQn           =  56, /* 56  Event System Interface (EVSYS)      */
+  EVSYS_EVD9_IRQn           =  57, /* 57  Event System Interface (EVSYS)      */
+  EVSYS_EVD10_IRQn          =  58, /* 58  Event System Interface (EVSYS)      */
+  EVSYS_EVD11_IRQn          =  59, /* 59  Event System Interface (EVSYS)      */
+  SERCOM0_6_IRQn            =  60, /* 60  Serial Communication Interface (SERCOM0) */
+  SERCOM0_5_IRQn            =  61, /* 61  Serial Communication Interface (SERCOM0) */
+  SERCOM0_0_IRQn            =  62, /* 62  Serial Communication Interface (SERCOM0) */
+  SERCOM0_1_IRQn            =  63, /* 63  Serial Communication Interface (SERCOM0) */
+  SERCOM0_2_IRQn            =  64, /* 64  Serial Communication Interface (SERCOM0) */
+  SERCOM0_3_IRQn            =  65, /* 65  Serial Communication Interface (SERCOM0) */
+  SERCOM0_4_IRQn            =  66, /* 66  Serial Communication Interface (SERCOM0) */
+  SERCOM1_6_IRQn            =  67, /* 67  Serial Communication Interface (SERCOM1) */
+  SERCOM1_5_IRQn            =  68, /* 68  Serial Communication Interface (SERCOM1) */
+  SERCOM1_0_IRQn            =  69, /* 69  Serial Communication Interface (SERCOM1) */
+  SERCOM1_1_IRQn            =  70, /* 70  Serial Communication Interface (SERCOM1) */
+  SERCOM1_2_IRQn            =  71, /* 71  Serial Communication Interface (SERCOM1) */
+  SERCOM1_3_IRQn            =  72, /* 72  Serial Communication Interface (SERCOM1) */
+  SERCOM1_4_IRQn            =  73, /* 73  Serial Communication Interface (SERCOM1) */
+  SERCOM2_6_IRQn            =  74, /* 74  Serial Communication Interface (SERCOM2) */
+  SERCOM2_5_IRQn            =  75, /* 75  Serial Communication Interface (SERCOM2) */
+  SERCOM2_0_IRQn            =  76, /* 76  Serial Communication Interface (SERCOM2) */
+  SERCOM2_1_IRQn            =  77, /* 77  Serial Communication Interface (SERCOM2) */
+  SERCOM2_2_IRQn            =  78, /* 78  Serial Communication Interface (SERCOM2) */
+  SERCOM2_3_IRQn            =  79, /* 79  Serial Communication Interface (SERCOM2) */
+  SERCOM2_4_IRQn            =  80, /* 80  Serial Communication Interface (SERCOM2) */
+  SERCOM3_6_IRQn            =  81, /* 81  Serial Communication Interface (SERCOM3) */
+  SERCOM3_5_IRQn            =  82, /* 82  Serial Communication Interface (SERCOM3) */
+  SERCOM3_0_IRQn            =  83, /* 83  Serial Communication Interface (SERCOM3) */
+  SERCOM3_1_IRQn            =  84, /* 84  Serial Communication Interface (SERCOM3) */
+  SERCOM3_2_IRQn            =  85, /* 85  Serial Communication Interface (SERCOM3) */
+  SERCOM3_3_IRQn            =  86, /* 86  Serial Communication Interface (SERCOM3) */
+  SERCOM3_4_IRQn            =  87, /* 87  Serial Communication Interface (SERCOM3) */
+  TCC0_DFS_IRQn             =  88, /* 88  Timer Counter for Control Applications (TCC0) */
+  TCC0_CNT_IRQn             =  89, /* 89  Timer Counter for Control Applications (TCC0) */
+  TCC0_MC0_IRQn             =  90, /* 90  Timer Counter for Control Applications (TCC0) */
+  TCC0_MC1_IRQn             =  91, /* 91  Timer Counter for Control Applications (TCC0) */
+  TCC1_DFS_IRQn             =  92, /* 92  Timer Counter for Control Applications (TCC1) */
+  TCC1_CNT_IRQn             =  93, /* 93  Timer Counter for Control Applications (TCC1) */
+  TCC1_MC0_IRQn             =  94, /* 94  Timer Counter for Control Applications (TCC1) */
+  TCC1_MC1_IRQn             =  95, /* 95  Timer Counter for Control Applications (TCC1) */
+  TCC2_DFS_IRQn             =  96, /* 96  Timer Counter for Control Applications (TCC2) */
+  TCC2_CNT_IRQn             =  97, /* 97  Timer Counter for Control Applications (TCC2) */
+  TCC2_MC0_IRQn             =  98, /* 98  Timer Counter for Control Applications (TCC2) */
+  TCC2_MC1_IRQn             =  99, /* 99  Timer Counter for Control Applications (TCC2) */
+  TCC3_DFS_IRQn             = 100, /* 100 Timer Counter for Control Applications (TCC3) */
+  TCC3_CNT_IRQn             = 101, /* 101 Timer Counter for Control Applications (TCC3) */
+  TCC3_MC0_IRQn             = 102, /* 102 Timer Counter for Control Applications (TCC3) */
+  TCC3_MC1_IRQn             = 103, /* 103 Timer Counter for Control Applications (TCC3) */
+  SERCOM4_6_IRQn            = 104, /* 104 Serial Communication Interface (SERCOM4) */
+  SERCOM4_5_IRQn            = 105, /* 105 Serial Communication Interface (SERCOM4) */
+  SERCOM4_0_IRQn            = 106, /* 106 Serial Communication Interface (SERCOM4) */
+  SERCOM4_1_IRQn            = 107, /* 107 Serial Communication Interface (SERCOM4) */
+  SERCOM4_2_IRQn            = 108, /* 108 Serial Communication Interface (SERCOM4) */
+  SERCOM4_3_IRQn            = 109, /* 109 Serial Communication Interface (SERCOM4) */
+  SERCOM4_4_IRQn            = 110, /* 110 Serial Communication Interface (SERCOM4) */
+  SERCOM5_6_IRQn            = 111, /* 111 Serial Communication Interface (SERCOM5) */
+  SERCOM5_5_IRQn            = 112, /* 112 Serial Communication Interface (SERCOM5) */
+  SERCOM5_0_IRQn            = 113, /* 113 Serial Communication Interface (SERCOM5) */
+  SERCOM5_1_IRQn            = 114, /* 114 Serial Communication Interface (SERCOM5) */
+  SERCOM5_2_IRQn            = 115, /* 115 Serial Communication Interface (SERCOM5) */
+  SERCOM5_3_IRQn            = 116, /* 116 Serial Communication Interface (SERCOM5) */
+  SERCOM5_4_IRQn            = 117, /* 117 Serial Communication Interface (SERCOM5) */
+  TCC4_DFS_IRQn             = 118, /* 118 Timer Counter for Control Applications (TCC4) */
+  TCC4_CNT_IRQn             = 119, /* 119 Timer Counter for Control Applications (TCC4) */
+  TCC4_MC0_IRQn             = 120, /* 120 Timer Counter for Control Applications (TCC4) */
+  TCC4_MC1_IRQn             = 121, /* 121 Timer Counter for Control Applications (TCC4) */
+  TCC5_DFS_IRQn             = 122, /* 122 Timer Counter for Control Applications (TCC5) */
+  TCC5_CNT_IRQn             = 123, /* 123 Timer Counter for Control Applications (TCC5) */
+  TCC5_MC0_IRQn             = 124, /* 124 Timer Counter for Control Applications (TCC5) */
+  TCC5_MC1_IRQn             = 125, /* 125 Timer Counter for Control Applications (TCC5) */
+  TCC6_DFS_IRQn             = 126, /* 126 Timer Counter for Control Applications (TCC6) */
+  TCC6_CNT_IRQn             = 127, /* 127 Timer Counter for Control Applications (TCC6) */
+  TCC6_MC0_IRQn             = 128, /* 128 Timer Counter for Control Applications (TCC6) */
+  TCC6_MC1_IRQn             = 129, /* 129 Timer Counter for Control Applications (TCC6) */
+  ADC_REQ0_IRQn             = 130, /* 130 ADC Controller (ADC)                */
+  ADC_REQ1_IRQn             = 131, /* 131 ADC Controller (ADC)                */
+  AC_IRQn                   = 132, /* 132 Analog Comparator Controller (AC)   */
+  PTC_IRQn                  = 133, /* 133 Polaris Peripheral Touch Controller (PTC) */
+  USB_EORSMDNRSM_IRQn       = 134, /* 134 Full-Speed Universal Serial Bus (USB) */
+  USB_SOFHSOF_IRQn          = 135, /* 135 Full-Speed Universal Serial Bus (USB) */
+  USB_TRCPT00_IRQn          = 136, /* 136 Full-Speed Universal Serial Bus (USB) */
+  USB_TRCPT10_IRQn          = 137, /* 137 Full-Speed Universal Serial Bus (USB) */
+  AT_IRQn                   = 138, /* 138 Anti-Tamper Controller (AT) (AT)    */
+
+  PERIPH_MAX_IRQn           = 138  /* Max peripheral ID */
+} IRQn_Type;
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+  /* CORTEX-M23 handlers */
+  void* pfnReset_Handler;                        /* -15 Reset Vector, invoked on Power up and warm reset */
+  void* pfnNonMaskableInt_Handler;               /* -14 Non maskable Interrupt, cannot be stopped or preempted */
+  void* pfnHardFault_Handler;                    /* -13 Hard Fault, all classes of Fault */
+  void* pvReservedC12;
+  void* pvReservedC11;
+  void* pvReservedC10;
+  void* pvReservedC9;
+  void* pvReservedC8;
+  void* pvReservedC7;
+  void* pvReservedC6;
+  void* pfnSVCall_Handler;                       /*  -5 System Service Call via SVC instruction */
+  void* pvReservedC4;
+  void* pvReservedC3;
+  void* pfnPendSV_Handler;                       /*  -2 Pendable request for system service */
+  void* pfnSysTick_Handler;                      /*  -1 System Tick Timer */
+
+  /* Peripheral handlers */
+  void* pfnFCR_Handler;                          /*   0 Polaris Flash Read Controller (FCR) */
+  void* pfnFCW_Handler;                          /*   1 Polaris Flash Write Controller (FCW) */
+  void* pfnPM_Handler;                           /*   2 Power Manager (PM) */
+  void* pfnSUPC_Handler;                         /*   3 Supply Controller (SUPC) */
+  void* pfnOSCCTRL_XOSCRDY_Handler;              /*   4 Oscillators Control (OSCCTRL) */
+  void* pfnOSCCTRL_DFLLRDY_Handler;              /*   5 Oscillators Control (OSCCTRL) */
+  void* pfnOSCCTRL_PLLLOCKR_0_Handler;           /*   6 Oscillators Control (OSCCTRL) */
+  void* pfnOSC32KCTRL_XOSC32KRDY_Handler;        /*   7 32kHz Oscillators Control (OSC32KCTRL) */
+  void* pfnOSC32KCTRL_XOSC32KFAIL_Handler;       /*   8 32kHz Oscillators Control (OSC32KCTRL) */
+  void* pfnMCLK_Handler;                         /*   9 Polaris Main Clock Controller (MCLK) */
+  void* pfnFREQM_Handler;                        /*  10 Frequency Meter (FREQM) */
+  void* pfnWDT_Handler;                          /*  11 Watchdog Timer (WDT) */
+  void* pfnRTC_TAMPER_Handler;                   /*  12 Real-Time Counter (RTC) */
+  void* pfnRTC_OVF_Handler;                      /*  13 Real-Time Counter (RTC) */
+  void* pfnRTC_PER0_Handler;                     /*  14 Real-Time Counter (RTC) */
+  void* pfnRTC_CMP0_Handler;                     /*  15 Real-Time Counter (RTC) */
+  void* pfnEIC_EXTINT0_Handler;                  /*  16 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT1_Handler;                  /*  17 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT2_Handler;                  /*  18 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT3_Handler;                  /*  19 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT4_Handler;                  /*  20 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT5_Handler;                  /*  21 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT6_Handler;                  /*  22 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT7_Handler;                  /*  23 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT8_Handler;                  /*  24 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT9_Handler;                  /*  25 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT10_Handler;                 /*  26 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT11_Handler;                 /*  27 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT12_Handler;                 /*  28 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT13_Handler;                 /*  29 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT14_Handler;                 /*  30 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT15_Handler;                 /*  31 External Interrupt Controller (EIC) */
+  void* pfnEIC_NSCHK_Handler;                    /*  32 External Interrupt Controller (EIC) */
+  void* pvReserved33;
+  void* pfnMCRAMC_Handler;                       /*  34 Multi-Channel RAM Controller (MCRAMC) */
+  void* pfnCAN0_INT0_Handler;                    /*  35 Control Area Network (CAN0) */
+  void* pfnCAN0_INT1_Handler;                    /*  36 Control Area Network (CAN0) */
+  void* pfnCAN0_BERR_Handler;                    /*  37 Control Area Network (CAN0) */
+  void* pfnCAN1_INT0_Handler;                    /*  38 Control Area Network (CAN1) */
+  void* pfnCAN1_INT1_Handler;                    /*  39 Control Area Network (CAN1) */
+  void* pfnCAN1_BERR_Handler;                    /*  40 Control Area Network (CAN1) */
+  void* pfnPORT_Handler;                         /*  41 Port Module (PORT) */
+  void* pfnDMAC_TCMPL0_Handler;                  /*  42 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL1_Handler;                  /*  43 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL2_Handler;                  /*  44 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL3_Handler;                  /*  45 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_TCMPL4_Handler;                  /*  46 Direct Memory Access Controller (DMAC) */
+  void* pfnHMATRIX2_Handler;                     /*  47 HSB Matrix (HMATRIX2) */
+  void* pfnEVSYS_EVD0_Handler;                   /*  48 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD1_Handler;                   /*  49 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD2_Handler;                   /*  50 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD3_Handler;                   /*  51 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD4_Handler;                   /*  52 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD5_Handler;                   /*  53 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD6_Handler;                   /*  54 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD7_Handler;                   /*  55 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD8_Handler;                   /*  56 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD9_Handler;                   /*  57 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD10_Handler;                  /*  58 Event System Interface (EVSYS) */
+  void* pfnEVSYS_EVD11_Handler;                  /*  59 Event System Interface (EVSYS) */
+  void* pfnSERCOM0_6_Handler;                    /*  60 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_5_Handler;                    /*  61 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_0_Handler;                    /*  62 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_1_Handler;                    /*  63 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_2_Handler;                    /*  64 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_3_Handler;                    /*  65 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_4_Handler;                    /*  66 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM1_6_Handler;                    /*  67 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_5_Handler;                    /*  68 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_0_Handler;                    /*  69 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_1_Handler;                    /*  70 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_2_Handler;                    /*  71 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_3_Handler;                    /*  72 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_4_Handler;                    /*  73 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM2_6_Handler;                    /*  74 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_5_Handler;                    /*  75 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_0_Handler;                    /*  76 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_1_Handler;                    /*  77 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_2_Handler;                    /*  78 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_3_Handler;                    /*  79 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_4_Handler;                    /*  80 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM3_6_Handler;                    /*  81 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_5_Handler;                    /*  82 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_0_Handler;                    /*  83 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_1_Handler;                    /*  84 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_2_Handler;                    /*  85 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_3_Handler;                    /*  86 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_4_Handler;                    /*  87 Serial Communication Interface (SERCOM3) */
+  void* pfnTCC0_DFS_Handler;                     /*  88 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC0_CNT_Handler;                     /*  89 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC0_MC0_Handler;                     /*  90 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC0_MC1_Handler;                     /*  91 Timer Counter for Control Applications (TCC0) */
+  void* pfnTCC1_DFS_Handler;                     /*  92 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC1_CNT_Handler;                     /*  93 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC1_MC0_Handler;                     /*  94 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC1_MC1_Handler;                     /*  95 Timer Counter for Control Applications (TCC1) */
+  void* pfnTCC2_DFS_Handler;                     /*  96 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC2_CNT_Handler;                     /*  97 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC2_MC0_Handler;                     /*  98 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC2_MC1_Handler;                     /*  99 Timer Counter for Control Applications (TCC2) */
+  void* pfnTCC3_DFS_Handler;                     /* 100 Timer Counter for Control Applications (TCC3) */
+  void* pfnTCC3_CNT_Handler;                     /* 101 Timer Counter for Control Applications (TCC3) */
+  void* pfnTCC3_MC0_Handler;                     /* 102 Timer Counter for Control Applications (TCC3) */
+  void* pfnTCC3_MC1_Handler;                     /* 103 Timer Counter for Control Applications (TCC3) */
+  void* pfnSERCOM4_6_Handler;                    /* 104 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_5_Handler;                    /* 105 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_0_Handler;                    /* 106 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_1_Handler;                    /* 107 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_2_Handler;                    /* 108 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_3_Handler;                    /* 109 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_4_Handler;                    /* 110 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM5_6_Handler;                    /* 111 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_5_Handler;                    /* 112 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_0_Handler;                    /* 113 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_1_Handler;                    /* 114 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_2_Handler;                    /* 115 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_3_Handler;                    /* 116 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_4_Handler;                    /* 117 Serial Communication Interface (SERCOM5) */
+  void* pfnTCC4_DFS_Handler;                     /* 118 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC4_CNT_Handler;                     /* 119 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC4_MC0_Handler;                     /* 120 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC4_MC1_Handler;                     /* 121 Timer Counter for Control Applications (TCC4) */
+  void* pfnTCC5_DFS_Handler;                     /* 122 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC5_CNT_Handler;                     /* 123 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC5_MC0_Handler;                     /* 124 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC5_MC1_Handler;                     /* 125 Timer Counter for Control Applications (TCC5) */
+  void* pfnTCC6_DFS_Handler;                     /* 126 Timer Counter for Control Applications (TCC6) */
+  void* pfnTCC6_CNT_Handler;                     /* 127 Timer Counter for Control Applications (TCC6) */
+  void* pfnTCC6_MC0_Handler;                     /* 128 Timer Counter for Control Applications (TCC6) */
+  void* pfnTCC6_MC1_Handler;                     /* 129 Timer Counter for Control Applications (TCC6) */
+  void* pfnADC_REQ0_Handler;                     /* 130 ADC Controller (ADC) */
+  void* pfnADC_REQ1_Handler;                     /* 131 ADC Controller (ADC) */
+  void* pfnAC_Handler;                           /* 132 Analog Comparator Controller (AC) */
+  void* pfnPTC_Handler;                          /* 133 Polaris Peripheral Touch Controller (PTC) */
+  void* pfnUSB_EORSMDNRSM_Handler;               /* 134 Full-Speed Universal Serial Bus (USB) */
+  void* pfnUSB_SOFHSOF_Handler;                  /* 135 Full-Speed Universal Serial Bus (USB) */
+  void* pfnUSB_TRCPT00_Handler;                  /* 136 Full-Speed Universal Serial Bus (USB) */
+  void* pfnUSB_TRCPT10_Handler;                  /* 137 Full-Speed Universal Serial Bus (USB) */
+  void* pfnAT_Handler;                           /* 138 Anti-Tamper Controller (AT) (AT) */
+} DeviceVectors;
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS
+/* CORTEX-M23 exception handlers */
+void Reset_Handler                 ( void );
+void NonMaskableInt_Handler        ( void );
+void HardFault_Handler             ( void );
+void SVCall_Handler                ( void );
+void PendSV_Handler                ( void );
+void SysTick_Handler               ( void );
+#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */
+
+#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
+/* Peripherals interrupt handlers */
+void FCR_Handler                   ( void );
+void FCW_Handler                   ( void );
+void PM_Handler                    ( void );
+void SUPC_Handler                  ( void );
+void OSCCTRL_XOSCRDY_Handler       ( void );
+void OSCCTRL_DFLLRDY_Handler       ( void );
+void OSCCTRL_PLLLOCKR_0_Handler    ( void );
+void OSC32KCTRL_XOSC32KRDY_Handler ( void );
+void OSC32KCTRL_XOSC32KFAIL_Handler( void );
+void MCLK_Handler                  ( void );
+void FREQM_Handler                 ( void );
+void WDT_Handler                   ( void );
+void RTC_TAMPER_Handler            ( void );
+void RTC_OVF_Handler               ( void );
+void RTC_PER0_Handler              ( void );
+void RTC_CMP0_Handler              ( void );
+void EIC_EXTINT0_Handler           ( void );
+void EIC_EXTINT1_Handler           ( void );
+void EIC_EXTINT2_Handler           ( void );
+void EIC_EXTINT3_Handler           ( void );
+void EIC_EXTINT4_Handler           ( void );
+void EIC_EXTINT5_Handler           ( void );
+void EIC_EXTINT6_Handler           ( void );
+void EIC_EXTINT7_Handler           ( void );
+void EIC_EXTINT8_Handler           ( void );
+void EIC_EXTINT9_Handler           ( void );
+void EIC_EXTINT10_Handler          ( void );
+void EIC_EXTINT11_Handler          ( void );
+void EIC_EXTINT12_Handler          ( void );
+void EIC_EXTINT13_Handler          ( void );
+void EIC_EXTINT14_Handler          ( void );
+void EIC_EXTINT15_Handler          ( void );
+void EIC_NSCHK_Handler             ( void );
+void MCRAMC_Handler                ( void );
+void CAN0_INT0_Handler             ( void );
+void CAN0_INT1_Handler             ( void );
+void CAN0_BERR_Handler             ( void );
+void CAN1_INT0_Handler             ( void );
+void CAN1_INT1_Handler             ( void );
+void CAN1_BERR_Handler             ( void );
+void PORT_Handler                  ( void );
+void DMAC_TCMPL0_Handler           ( void );
+void DMAC_TCMPL1_Handler           ( void );
+void DMAC_TCMPL2_Handler           ( void );
+void DMAC_TCMPL3_Handler           ( void );
+void DMAC_TCMPL4_Handler           ( void );
+void HMATRIX2_Handler              ( void );
+void EVSYS_EVD0_Handler            ( void );
+void EVSYS_EVD1_Handler            ( void );
+void EVSYS_EVD2_Handler            ( void );
+void EVSYS_EVD3_Handler            ( void );
+void EVSYS_EVD4_Handler            ( void );
+void EVSYS_EVD5_Handler            ( void );
+void EVSYS_EVD6_Handler            ( void );
+void EVSYS_EVD7_Handler            ( void );
+void EVSYS_EVD8_Handler            ( void );
+void EVSYS_EVD9_Handler            ( void );
+void EVSYS_EVD10_Handler           ( void );
+void EVSYS_EVD11_Handler           ( void );
+void SERCOM0_6_Handler             ( void );
+void SERCOM0_5_Handler             ( void );
+void SERCOM0_0_Handler             ( void );
+void SERCOM0_1_Handler             ( void );
+void SERCOM0_2_Handler             ( void );
+void SERCOM0_3_Handler             ( void );
+void SERCOM0_4_Handler             ( void );
+void SERCOM1_6_Handler             ( void );
+void SERCOM1_5_Handler             ( void );
+void SERCOM1_0_Handler             ( void );
+void SERCOM1_1_Handler             ( void );
+void SERCOM1_2_Handler             ( void );
+void SERCOM1_3_Handler             ( void );
+void SERCOM1_4_Handler             ( void );
+void SERCOM2_6_Handler             ( void );
+void SERCOM2_5_Handler             ( void );
+void SERCOM2_0_Handler             ( void );
+void SERCOM2_1_Handler             ( void );
+void SERCOM2_2_Handler             ( void );
+void SERCOM2_3_Handler             ( void );
+void SERCOM2_4_Handler             ( void );
+void SERCOM3_6_Handler             ( void );
+void SERCOM3_5_Handler             ( void );
+void SERCOM3_0_Handler             ( void );
+void SERCOM3_1_Handler             ( void );
+void SERCOM3_2_Handler             ( void );
+void SERCOM3_3_Handler             ( void );
+void SERCOM3_4_Handler             ( void );
+void TCC0_DFS_Handler              ( void );
+void TCC0_CNT_Handler              ( void );
+void TCC0_MC0_Handler              ( void );
+void TCC0_MC1_Handler              ( void );
+void TCC1_DFS_Handler              ( void );
+void TCC1_CNT_Handler              ( void );
+void TCC1_MC0_Handler              ( void );
+void TCC1_MC1_Handler              ( void );
+void TCC2_DFS_Handler              ( void );
+void TCC2_CNT_Handler              ( void );
+void TCC2_MC0_Handler              ( void );
+void TCC2_MC1_Handler              ( void );
+void TCC3_DFS_Handler              ( void );
+void TCC3_CNT_Handler              ( void );
+void TCC3_MC0_Handler              ( void );
+void TCC3_MC1_Handler              ( void );
+void SERCOM4_6_Handler             ( void );
+void SERCOM4_5_Handler             ( void );
+void SERCOM4_0_Handler             ( void );
+void SERCOM4_1_Handler             ( void );
+void SERCOM4_2_Handler             ( void );
+void SERCOM4_3_Handler             ( void );
+void SERCOM4_4_Handler             ( void );
+void SERCOM5_6_Handler             ( void );
+void SERCOM5_5_Handler             ( void );
+void SERCOM5_0_Handler             ( void );
+void SERCOM5_1_Handler             ( void );
+void SERCOM5_2_Handler             ( void );
+void SERCOM5_3_Handler             ( void );
+void SERCOM5_4_Handler             ( void );
+void TCC4_DFS_Handler              ( void );
+void TCC4_CNT_Handler              ( void );
+void TCC4_MC0_Handler              ( void );
+void TCC4_MC1_Handler              ( void );
+void TCC5_DFS_Handler              ( void );
+void TCC5_CNT_Handler              ( void );
+void TCC5_MC0_Handler              ( void );
+void TCC5_MC1_Handler              ( void );
+void TCC6_DFS_Handler              ( void );
+void TCC6_CNT_Handler              ( void );
+void TCC6_MC0_Handler              ( void );
+void TCC6_MC1_Handler              ( void );
+void ADC_REQ0_Handler              ( void );
+void ADC_REQ1_Handler              ( void );
+void AC_Handler                    ( void );
+void PTC_Handler                   ( void );
+void USB_EORSMDNRSM_Handler        ( void );
+void USB_SOFHSOF_Handler           ( void );
+void USB_TRCPT00_Handler           ( void );
+void USB_TRCPT10_Handler           ( void );
+void AT_Handler                    ( void );
+#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* Configuration of the CORTEX-M23 Processor and Core Peripherals */
+#define __CM23_REV                    0x0000 /* Cortex-M23 Core Revision                                                  */
+#define __FPU_PRESENT                      0 /* No FPU                                                                    */
+#define __MPU_PRESENT                      1 /* MPU implemented                                                           */
+#define __NVIC_PRIO_BITS                   2 /* Number of NVIC Priority Bits                                              */
+#define __SAUREGION_PRESENT                0 /* Number of Security Attribute Unit Regions (No SAU)                        */
+#define __VTOR_PRESENT                     1 /* Include Vector Table Offset Register                                      */
+#define __Vendor_SysTickConfig             0 /* Standard SYSTICK used                                                     */
+#define __ARCH_ARM                         1
+#define __ARCH_ARM_CORTEX_M                1
+
+/* CMSIS includes */
+#include "core_cm23.h"
+#if defined USE_CMSIS_INIT
+#include "system_pic32cmgc00.h"
+#endif /* USE_CMSIS_INIT */
+
+/* ************************************************************************** */
+/*         SOFTWARE PERIPHERAL API DEFINITIONS FOR PIC32CM5112GC00100         */
+/* ************************************************************************** */
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/at.h"
+#include "component/bromc.h"
+#include "component/can.h"
+#include "component/ccl.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/fcr.h"
+#include "component/fcw.h"
+#include "component/freqm.h"
+#include "component/fuses.h"
+#include "component/gclk.h"
+#include "component/h2pb.h"
+#include "component/hmatrix2.h"
+#include "component/mclk.h"
+#include "component/mcramc.h"
+#include "component/osc32kctrl.h"
+#include "component/oscctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/ptc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+
+/* ************************************************************************** */
+/*                INSTANCE DEFINITIONS FOR PIC32CM5112GC00100                 */
+/* ************************************************************************** */
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/at.h"
+#include "instance/bromc.h"
+#include "instance/can0.h"
+#include "instance/can1.h"
+#include "instance/ccl0.h"
+#include "instance/ccl1.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/fcr.h"
+#include "instance/fcw.h"
+#include "instance/freqm.h"
+#include "instance/fuses.h"
+#include "instance/gclk.h"
+#include "instance/h2pb0.h"
+#include "instance/h2pb1.h"
+#include "instance/h2pb2.h"
+#include "instance/hmatrix2.h"
+#include "instance/mclk.h"
+#include "instance/mcramc.h"
+#include "instance/osc32kctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/pac.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/ptc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/supc.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/tcc5.h"
+#include "instance/tcc6.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+
+/* ************************************************************************** */
+/*              PERIPHERAL ID DEFINITIONS FOR PIC32CM5112GC00100              */
+/* ************************************************************************** */
+#define ID_DSU           (  0) /* Instance index for DSU (DSU) */
+#define ID_FCR           (  1) /* Instance index for FCR (FCR) */
+#define ID_FCW           (  2) /* Instance index for FCW (FCW) */
+#define ID_PM            (  3) /* Instance index for PM (PM) */
+#define ID_SUPC          (  4) /* Instance index for SUPC (SUPC) */
+#define ID_RSTC          (  5) /* Instance index for RSTC (RSTC) */
+#define ID_OSCCTRL       (  6) /* Instance index for OSCCTRL (OSCCTRL) */
+#define ID_OSC32KCTRL    (  7) /* Instance index for OSC32KCTRL (OSC32KCTRL) */
+#define ID_GCLK          (  8) /* Instance index for GCLK (GCLK) */
+#define ID_MCLK          (  9) /* Instance index for MCLK (MCLK) */
+#define ID_FREQM         ( 10) /* Instance index for FREQM (FREQM) */
+#define ID_WDT           ( 11) /* Instance index for WDT (WDT) */
+#define ID_RTC           ( 12) /* Instance index for RTC (RTC) */
+#define ID_EIC           ( 13) /* Instance index for EIC (EIC) */
+#define ID_PAC           ( 14) /* Instance index for PAC (PAC) */
+#define ID_MCRAMC        ( 16) /* Instance index for MCRAMC (MCRAMC) */
+#define ID_CAN0          ( 17) /* Instance index for CAN0 (CAN0) */
+#define ID_CAN1          ( 18) /* Instance index for CAN1 (CAN1) */
+#define ID_H2PB0         ( 19) /* Instance index for H2PB0 (H2PB0) */
+#define ID_PORT          ( 20) /* Instance index for PORT (PORT) */
+#define ID_DMAC          ( 21) /* Instance index for DMAC (DMAC) */
+#define ID_HMATRIX2      ( 22) /* Instance index for HMATRIX2 (HMATRIX2) */
+#define ID_BROMC         ( 23) /* Instance index for BROMC (BROMC) */
+#define ID_EVSYS         ( 25) /* Instance index for EVSYS (EVSYS) */
+#define ID_SERCOM0       ( 26) /* Instance index for SERCOM0 (SERCOM0) */
+#define ID_SERCOM1       ( 27) /* Instance index for SERCOM1 (SERCOM1) */
+#define ID_SERCOM2       ( 28) /* Instance index for SERCOM2 (SERCOM2) */
+#define ID_SERCOM3       ( 29) /* Instance index for SERCOM3 (SERCOM3) */
+#define ID_TCC0          ( 30) /* Instance index for TCC0 (TCC0) */
+#define ID_TCC1          ( 31) /* Instance index for TCC1 (TCC1) */
+#define ID_TCC2          ( 32) /* Instance index for TCC2 (TCC2) */
+#define ID_TCC3          ( 33) /* Instance index for TCC3 (TCC3) */
+#define ID_SERCOM4       ( 34) /* Instance index for SERCOM4 (SERCOM4) */
+#define ID_SERCOM5       ( 35) /* Instance index for SERCOM5 (SERCOM5) */
+#define ID_TCC4          ( 36) /* Instance index for TCC4 (TCC4) */
+#define ID_TCC5          ( 37) /* Instance index for TCC5 (TCC5) */
+#define ID_TCC6          ( 38) /* Instance index for TCC6 (TCC6) */
+#define ID_ADC           ( 39) /* Instance index for ADC (ADC) */
+#define ID_AC            ( 40) /* Instance index for AC (AC) */
+#define ID_PTC           ( 41) /* Instance index for PTC (PTC) */
+#define ID_CCL0          ( 42) /* Instance index for CCL0 (CCL0) */
+#define ID_CCL1          ( 43) /* Instance index for CCL1 (CCL1) */
+#define ID_USB           ( 44) /* Instance index for USB (USB) */
+#define ID_AT            ( 45) /* Instance index for AT (AT) */
+#define ID_H2PB1         ( 46) /* Instance index for H2PB1 (H2PB1) */
+#define ID_H2PB2         ( 47) /* Instance index for H2PB2 (H2PB2) */
+
+#define ID_PERIPH_MAX    ( 47) /* Number of peripheral IDs */
+
+/* ************************************************************************** */
+/*       REGISTER STRUCTURE ADDRESS DEFINITIONS FOR PIC32CM5112GC00100        */
+/* ************************************************************************** */
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#define AC_REGS                          ((ac_registers_t*)0x4482a000)                 /* AC Registers Address         */
+#define ADC_REGS                         ((adc_registers_t*)0x44818000)                /* ADC Registers Address        */
+#define AT_REGS                          ((at_registers_t*)0x4500c000)                 /* AT Registers Address         */
+#define BROMC_REGS                       ((bromc_registers_t*)0x44804000)              /* BROMC Registers Address      */
+#define CAN0_REGS                        ((can_registers_t*)0x4402e000)                /* CAN0 Registers Address       */
+#define CAN1_REGS                        ((can_registers_t*)0x44030000)                /* CAN1 Registers Address       */
+#define CCL0_REGS                        ((ccl_registers_t*)0x4482e000)                /* CCL0 Registers Address       */
+#define CCL1_REGS                        ((ccl_registers_t*)0x44830000)                /* CCL1 Registers Address       */
+#define DMAC_REGS                        ((dmac_registers_t*)0x44802000)               /* DMAC Registers Address       */
+#define DSU_REGS                         ((dsu_registers_t*)0x44000000)                /* DSU Registers Address        */
+#define EIC_REGS                         ((eic_registers_t*)0x44020000)                /* EIC Registers Address        */
+#define EVSYS_REGS                       ((evsys_registers_t*)0x44806000)              /* EVSYS Registers Address      */
+#define FCR_REGS                         ((fcr_registers_t*)0x44002000)                /* FCR Registers Address        */
+#define FCW_REGS                         ((fcw_registers_t*)0x44004000)                /* FCW Registers Address        */
+#define FREQM_REGS                       ((freqm_registers_t*)0x4400c000)              /* FREQM Registers Address      */
+#define FUSES_ROMCFG_REGS                ((fuses_romcfg_registers_t*)0x0a003000)       /* FUSES Registers Address      */
+#define FUSES_BOOTCFG1_REGS              ((fuses_bootcfg1_registers_t*)0x0a002000)     /* FUSES Registers Address      */
+#define FUSES_BOOTCFG1A_REGS             ((fuses_bootcfg1_registers_t*)0x0a000000)     /* FUSES Registers Address      */
+#define FUSES_CALOTP_REGS                ((fuses_calotp_registers_t*)0x0a007000)       /* FUSES Registers Address      */
+#define GCLK_REGS                        ((gclk_registers_t*)0x44008000)               /* GCLK Registers Address       */
+#define H2PB0_REGS                       ((h2pb_registers_t*)0x44032000)               /* H2PB0 Registers Address      */
+#define H2PB1_REGS                       ((h2pb_registers_t*)0x44838000)               /* H2PB1 Registers Address      */
+#define H2PB2_REGS                       ((h2pb_registers_t*)0x4500e000)               /* H2PB2 Registers Address      */
+#define HMATRIX2_REGS                    ((hmatrix2_registers_t*)0x44010000)           /* HMATRIX2 Registers Address   */
+#define MCLK_REGS                        ((mclk_registers_t*)0x4400a000)               /* MCLK Registers Address       */
+#define MCRAMC_REGS                      ((mcramc_registers_t*)0x4402c000)             /* MCRAMC Registers Address     */
+#define OSC32KCTRL_REGS                  ((osc32kctrl_registers_t*)0x45008000)         /* OSC32KCTRL Registers Address */
+#define OSCCTRL_REGS                     ((oscctrl_registers_t*)0x44006000)            /* OSCCTRL Registers Address    */
+#define PAC_REGS                         ((pac_registers_t*)0x44022000)                /* PAC Registers Address        */
+#define PM_REGS                          ((pm_registers_t*)0x45000000)                 /* PM Registers Address         */
+#define PORT_REGS                        ((port_registers_t*)0x44800000)               /* PORT Registers Address       */
+#define PTC_REGS                         ((ptc_registers_t*)0x4482c000)                /* PTC Registers Address        */
+#define RSTC_REGS                        ((rstc_registers_t*)0x45004000)               /* RSTC Registers Address       */
+#define RTC_REGS                         ((rtc_registers_t*)0x45006000)                /* RTC Registers Address        */
+#define SERCOM0_REGS                     ((sercom_registers_t*)0x44808000)             /* SERCOM0 Registers Address    */
+#define SERCOM1_REGS                     ((sercom_registers_t*)0x4480a000)             /* SERCOM1 Registers Address    */
+#define SERCOM2_REGS                     ((sercom_registers_t*)0x4480c000)             /* SERCOM2 Registers Address    */
+#define SERCOM3_REGS                     ((sercom_registers_t*)0x4480e000)             /* SERCOM3 Registers Address    */
+#define SERCOM4_REGS                     ((sercom_registers_t*)0x44820000)             /* SERCOM4 Registers Address    */
+#define SERCOM5_REGS                     ((sercom_registers_t*)0x44822000)             /* SERCOM5 Registers Address    */
+#define SUPC_REGS                        ((supc_registers_t*)0x45002000)               /* SUPC Registers Address       */
+#define TCC0_REGS                        ((tcc_registers_t*)0x44810000)                /* TCC0 Registers Address       */
+#define TCC1_REGS                        ((tcc_registers_t*)0x44812000)                /* TCC1 Registers Address       */
+#define TCC2_REGS                        ((tcc_registers_t*)0x44814000)                /* TCC2 Registers Address       */
+#define TCC3_REGS                        ((tcc_registers_t*)0x44816000)                /* TCC3 Registers Address       */
+#define TCC4_REGS                        ((tcc_registers_t*)0x44824000)                /* TCC4 Registers Address       */
+#define TCC5_REGS                        ((tcc_registers_t*)0x44826000)                /* TCC5 Registers Address       */
+#define TCC6_REGS                        ((tcc_registers_t*)0x44828000)                /* TCC6 Registers Address       */
+#define USB_REGS                         ((usb_registers_t*)0x44832000)                /* USB Registers Address        */
+#define WDT_REGS                         ((wdt_registers_t*)0x4400e000)                /* WDT Registers Address        */
+#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ************************************************************************** */
+/*              BASE ADDRESS DEFINITIONS FOR PIC32CM5112GC00100               */
+/* ************************************************************************** */
+#define AC_BASE_ADDRESS                  _UINT32_(0x4482a000)                          /* AC Base Address */
+#define ADC_BASE_ADDRESS                 _UINT32_(0x44818000)                          /* ADC Base Address */
+#define AT_BASE_ADDRESS                  _UINT32_(0x4500c000)                          /* AT Base Address */
+#define BROMC_BASE_ADDRESS               _UINT32_(0x44804000)                          /* BROMC Base Address */
+#define CAN0_BASE_ADDRESS                _UINT32_(0x4402e000)                          /* CAN0 Base Address */
+#define CAN1_BASE_ADDRESS                _UINT32_(0x44030000)                          /* CAN1 Base Address */
+#define CCL0_BASE_ADDRESS                _UINT32_(0x4482e000)                          /* CCL0 Base Address */
+#define CCL1_BASE_ADDRESS                _UINT32_(0x44830000)                          /* CCL1 Base Address */
+#define DMAC_BASE_ADDRESS                _UINT32_(0x44802000)                          /* DMAC Base Address */
+#define DSU_BASE_ADDRESS                 _UINT32_(0x44000000)                          /* DSU Base Address */
+#define EIC_BASE_ADDRESS                 _UINT32_(0x44020000)                          /* EIC Base Address */
+#define EVSYS_BASE_ADDRESS               _UINT32_(0x44806000)                          /* EVSYS Base Address */
+#define FCR_BASE_ADDRESS                 _UINT32_(0x44002000)                          /* FCR Base Address */
+#define FCW_BASE_ADDRESS                 _UINT32_(0x44004000)                          /* FCW Base Address */
+#define FREQM_BASE_ADDRESS               _UINT32_(0x4400c000)                          /* FREQM Base Address */
+#define FUSES_ROMCFG_BASE_ADDRESS        _UINT32_(0x0a003000)                          /* FUSES Base Address */
+#define FUSES_BOOTCFG1_BASE_ADDRESS      _UINT32_(0x0a002000)                          /* FUSES Base Address */
+#define FUSES_BOOTCFG1A_BASE_ADDRESS     _UINT32_(0x0a000000)                          /* FUSES Base Address */
+#define FUSES_CALOTP_BASE_ADDRESS        _UINT32_(0x0a007000)                          /* FUSES Base Address */
+#define GCLK_BASE_ADDRESS                _UINT32_(0x44008000)                          /* GCLK Base Address */
+#define H2PB0_BASE_ADDRESS               _UINT32_(0x44032000)                          /* H2PB0 Base Address */
+#define H2PB1_BASE_ADDRESS               _UINT32_(0x44838000)                          /* H2PB1 Base Address */
+#define H2PB2_BASE_ADDRESS               _UINT32_(0x4500e000)                          /* H2PB2 Base Address */
+#define HMATRIX2_BASE_ADDRESS            _UINT32_(0x44010000)                          /* HMATRIX2 Base Address */
+#define MCLK_BASE_ADDRESS                _UINT32_(0x4400a000)                          /* MCLK Base Address */
+#define MCRAMC_BASE_ADDRESS              _UINT32_(0x4402c000)                          /* MCRAMC Base Address */
+#define OSC32KCTRL_BASE_ADDRESS          _UINT32_(0x45008000)                          /* OSC32KCTRL Base Address */
+#define OSCCTRL_BASE_ADDRESS             _UINT32_(0x44006000)                          /* OSCCTRL Base Address */
+#define PAC_BASE_ADDRESS                 _UINT32_(0x44022000)                          /* PAC Base Address */
+#define PM_BASE_ADDRESS                  _UINT32_(0x45000000)                          /* PM Base Address */
+#define PORT_BASE_ADDRESS                _UINT32_(0x44800000)                          /* PORT Base Address */
+#define PTC_BASE_ADDRESS                 _UINT32_(0x4482c000)                          /* PTC Base Address */
+#define RSTC_BASE_ADDRESS                _UINT32_(0x45004000)                          /* RSTC Base Address */
+#define RTC_BASE_ADDRESS                 _UINT32_(0x45006000)                          /* RTC Base Address */
+#define SERCOM0_BASE_ADDRESS             _UINT32_(0x44808000)                          /* SERCOM0 Base Address */
+#define SERCOM1_BASE_ADDRESS             _UINT32_(0x4480a000)                          /* SERCOM1 Base Address */
+#define SERCOM2_BASE_ADDRESS             _UINT32_(0x4480c000)                          /* SERCOM2 Base Address */
+#define SERCOM3_BASE_ADDRESS             _UINT32_(0x4480e000)                          /* SERCOM3 Base Address */
+#define SERCOM4_BASE_ADDRESS             _UINT32_(0x44820000)                          /* SERCOM4 Base Address */
+#define SERCOM5_BASE_ADDRESS             _UINT32_(0x44822000)                          /* SERCOM5 Base Address */
+#define SUPC_BASE_ADDRESS                _UINT32_(0x45002000)                          /* SUPC Base Address */
+#define TCC0_BASE_ADDRESS                _UINT32_(0x44810000)                          /* TCC0 Base Address */
+#define TCC1_BASE_ADDRESS                _UINT32_(0x44812000)                          /* TCC1 Base Address */
+#define TCC2_BASE_ADDRESS                _UINT32_(0x44814000)                          /* TCC2 Base Address */
+#define TCC3_BASE_ADDRESS                _UINT32_(0x44816000)                          /* TCC3 Base Address */
+#define TCC4_BASE_ADDRESS                _UINT32_(0x44824000)                          /* TCC4 Base Address */
+#define TCC5_BASE_ADDRESS                _UINT32_(0x44826000)                          /* TCC5 Base Address */
+#define TCC6_BASE_ADDRESS                _UINT32_(0x44828000)                          /* TCC6 Base Address */
+#define USB_BASE_ADDRESS                 _UINT32_(0x44832000)                          /* USB Base Address */
+#define WDT_BASE_ADDRESS                 _UINT32_(0x4400e000)                          /* WDT Base Address */
+
+/* ************************************************************************** */
+/*                   PIO DEFINITIONS FOR PIC32CM5112GC00100                   */
+/* ************************************************************************** */
+#include "pio/pic32cm5112gc00100.h"
+
+/* ************************************************************************** */
+/*             MEMORY MAPPING DEFINITIONS FOR PIC32CM5112GC00100              */
+/* ************************************************************************** */
+#define BROMC_ROM_SIZE                 _UINT32_(0x00010000)    /*   64kB Memory segment type: rom */
+#define FCR_BFM_SIZE                   _UINT32_(0x00004000)    /*   16kB Memory segment type: flash */
+#define FCR_CFM_BOOTCFG1A_SIZE         _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_USEROTP_SIZE           _UINT32_(0x00001000)    /*    4kB Memory segment type: user_signatures */
+#define FCR_CFM_BOOTCFG1_SIZE          _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_ROMCFG_SIZE            _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_VSS0_SIZE              _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_VSS1_SIZE              _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_TEST_SIZE              _UINT32_(0x00001000)    /*    4kB Memory segment type: flash */
+#define FCR_CFM_CALOTP_SIZE            _UINT32_(0x00001000)    /*    4kB Memory segment type: other */
+#define FCR_PFM_SIZE                   _UINT32_(0x00080000)    /*  512kB Memory segment type: flash */
+#define MCRAMC_RET_SIZE                _UINT32_(0x00020000)    /*  128kB Memory segment type: ram */
+#define APB0_BRIDGE_SIZE               _UINT32_(0x00034000)    /*  208kB Memory segment type: io */
+#define APB1_BRIDGE_SIZE               _UINT32_(0x0003a000)    /*  232kB Memory segment type: io */
+#define APB2_BRIDGE_SIZE               _UINT32_(0x00010000)    /*   64kB Memory segment type: io */
+#define PPB_SIZE                       _UINT32_(0x00100000)    /* 1024kB Memory segment type: io */
+
+#define BROMC_ROM_ADDR                 _UINT32_(0x04000000)    /* BROMC_ROM base address (type: rom)*/
+#define FCR_BFM_ADDR                   _UINT32_(0x08000000)    /* FCR_BFM base address (type: flash)*/
+#define FCR_CFM_BOOTCFG1A_ADDR         _UINT32_(0x0a000000)    /* FCR_CFM_BOOTCFG1A base address (type: flash)*/
+#define FCR_CFM_USEROTP_ADDR           _UINT32_(0x0a001000)    /* FCR_CFM_USEROTP base address (type: user_signatures)*/
+#define FCR_CFM_BOOTCFG1_ADDR          _UINT32_(0x0a002000)    /* FCR_CFM_BOOTCFG1 base address (type: flash)*/
+#define FCR_CFM_ROMCFG_ADDR            _UINT32_(0x0a003000)    /* FCR_CFM_ROMCFG base address (type: flash)*/
+#define FCR_CFM_VSS0_ADDR              _UINT32_(0x0a004000)    /* FCR_CFM_VSS0 base address (type: flash)*/
+#define FCR_CFM_VSS1_ADDR              _UINT32_(0x0a005000)    /* FCR_CFM_VSS1 base address (type: flash)*/
+#define FCR_CFM_TEST_ADDR              _UINT32_(0x0a006000)    /* FCR_CFM_TEST base address (type: flash)*/
+#define FCR_CFM_CALOTP_ADDR            _UINT32_(0x0a007000)    /* FCR_CFM_CALOTP base address (type: other)*/
+#define FCR_PFM_ADDR                   _UINT32_(0x0c000000)    /* FCR_PFM base address (type: flash)*/
+#define MCRAMC_RET_ADDR                _UINT32_(0x20000000)    /* MCRAMC_RET base address (type: ram)*/
+#define APB0_BRIDGE_ADDR               _UINT32_(0x44000000)    /* APB0_BRIDGE base address (type: io)*/
+#define APB1_BRIDGE_ADDR               _UINT32_(0x44800000)    /* APB1_BRIDGE base address (type: io)*/
+#define APB2_BRIDGE_ADDR               _UINT32_(0x45000000)    /* APB2_BRIDGE base address (type: io)*/
+#define PPB_ADDR                       _UINT32_(0xe0000000)    /* PPB base address (type: io)*/
+
+/* ************************************************************************** */
+/*                  DEVICE SIGNATURES FOR PIC32CM5112GC00100                  */
+/* ************************************************************************** */
+#define CHIP_DSU_DID                   _UINT32_(0X0AC00053)
+
+/* ************************************************************************** */
+/*               ELECTRICAL DEFINITIONS FOR PIC32CM5112GC00100                */
+/* ************************************************************************** */
+
+/* ************************************************************************** */
+/*                  Event Generator IDs for C32CM5112GC00100                  */
+/* ************************************************************************** */
+#define EVENT_ID_GEN_SUPC_LVDET                           1 /* ID for SUPC event generator LVDET */
+#define EVENT_ID_GEN_OSCCTRL_XOSCFAIL                     2 /* ID for OSCCTRL event generator XOSCFAIL */
+#define EVENT_ID_GEN_OSC32KCTRL_XOSC32KFAIL               3 /* ID for OSC32KCTRL event generator XOSC32KFAIL */
+#define EVENT_ID_GEN_FREQM_DONE                           4 /* ID for FREQM event generator DONE */
+#define EVENT_ID_GEN_FREQM_WINMON                         5 /* ID for FREQM event generator WINMON */
+#define EVENT_ID_GEN_RTC_PER0                             6 /* ID for RTC event generator PER0 */
+#define EVENT_ID_GEN_RTC_PER1                             7 /* ID for RTC event generator PER1 */
+#define EVENT_ID_GEN_RTC_PER2                             8 /* ID for RTC event generator PER2 */
+#define EVENT_ID_GEN_RTC_PER3                             9 /* ID for RTC event generator PER3 */
+#define EVENT_ID_GEN_RTC_PER4                            10 /* ID for RTC event generator PER4 */
+#define EVENT_ID_GEN_RTC_PER5                            11 /* ID for RTC event generator PER5 */
+#define EVENT_ID_GEN_RTC_PER6                            12 /* ID for RTC event generator PER6 */
+#define EVENT_ID_GEN_RTC_PER7                            13 /* ID for RTC event generator PER7 */
+#define EVENT_ID_GEN_RTC_CMP0                            14 /* ID for RTC event generator CMP0 */
+#define EVENT_ID_GEN_RTC_CMP1                            15 /* ID for RTC event generator CMP1 */
+#define EVENT_ID_GEN_RTC_CMP2                            16 /* ID for RTC event generator CMP2 */
+#define EVENT_ID_GEN_RTC_CMP3                            17 /* ID for RTC event generator CMP3 */
+#define EVENT_ID_GEN_RTC_TAMPER                          18 /* ID for RTC event generator TAMPER */
+#define EVENT_ID_GEN_RTC_OVF                             19 /* ID for RTC event generator OVF */
+#define EVENT_ID_GEN_RTC_PERD                            20 /* ID for RTC event generator PERD */
+#define EVENT_ID_GEN_EIC_EXTINT0                         21 /* ID for EIC event generator EXTINT0 */
+#define EVENT_ID_GEN_EIC_EXTINT1                         22 /* ID for EIC event generator EXTINT1 */
+#define EVENT_ID_GEN_EIC_EXTINT2                         23 /* ID for EIC event generator EXTINT2 */
+#define EVENT_ID_GEN_EIC_EXTINT3                         24 /* ID for EIC event generator EXTINT3 */
+#define EVENT_ID_GEN_EIC_EXTINT4                         25 /* ID for EIC event generator EXTINT4 */
+#define EVENT_ID_GEN_EIC_EXTINT5                         26 /* ID for EIC event generator EXTINT5 */
+#define EVENT_ID_GEN_EIC_EXTINT6                         27 /* ID for EIC event generator EXTINT6 */
+#define EVENT_ID_GEN_EIC_EXTINT7                         28 /* ID for EIC event generator EXTINT7 */
+#define EVENT_ID_GEN_EIC_EXTINT8                         29 /* ID for EIC event generator EXTINT8 */
+#define EVENT_ID_GEN_EIC_EXTINT9                         30 /* ID for EIC event generator EXTINT9 */
+#define EVENT_ID_GEN_EIC_EXTINT10                        31 /* ID for EIC event generator EXTINT10 */
+#define EVENT_ID_GEN_EIC_EXTINT11                        32 /* ID for EIC event generator EXTINT11 */
+#define EVENT_ID_GEN_EIC_EXTINT12                        33 /* ID for EIC event generator EXTINT12 */
+#define EVENT_ID_GEN_EIC_EXTINT13                        34 /* ID for EIC event generator EXTINT13 */
+#define EVENT_ID_GEN_EIC_EXTINT14                        35 /* ID for EIC event generator EXTINT14 */
+#define EVENT_ID_GEN_EIC_EXTINT15                        36 /* ID for EIC event generator EXTINT15 */
+#define EVENT_ID_GEN_DMAC_CH0                            37 /* ID for DMAC event generator CH0 */
+#define EVENT_ID_GEN_DMAC_CH1                            38 /* ID for DMAC event generator CH1 */
+#define EVENT_ID_GEN_DMAC_CH2                            39 /* ID for DMAC event generator CH2 */
+#define EVENT_ID_GEN_DMAC_CH3                            40 /* ID for DMAC event generator CH3 */
+#define EVENT_ID_GEN_TCC0_OVF                            41 /* ID for TCC0 event generator OVF */
+#define EVENT_ID_GEN_TCC0_TRG                            42 /* ID for TCC0 event generator TRG */
+#define EVENT_ID_GEN_TCC0_CNT                            43 /* ID for TCC0 event generator CNT */
+#define EVENT_ID_GEN_TCC0_MC0                            44 /* ID for TCC0 event generator MC0 */
+#define EVENT_ID_GEN_TCC0_MC1                            45 /* ID for TCC0 event generator MC1 */
+#define EVENT_ID_GEN_TCC1_OVF                            46 /* ID for TCC1 event generator OVF */
+#define EVENT_ID_GEN_TCC1_TRG                            47 /* ID for TCC1 event generator TRG */
+#define EVENT_ID_GEN_TCC1_CNT                            48 /* ID for TCC1 event generator CNT */
+#define EVENT_ID_GEN_TCC1_MC0                            49 /* ID for TCC1 event generator MC0 */
+#define EVENT_ID_GEN_TCC1_MC1                            50 /* ID for TCC1 event generator MC1 */
+#define EVENT_ID_GEN_TCC2_OVF                            51 /* ID for TCC2 event generator OVF */
+#define EVENT_ID_GEN_TCC2_TRG                            52 /* ID for TCC2 event generator TRG */
+#define EVENT_ID_GEN_TCC2_CNT                            53 /* ID for TCC2 event generator CNT */
+#define EVENT_ID_GEN_TCC2_MC0                            54 /* ID for TCC2 event generator MC0 */
+#define EVENT_ID_GEN_TCC2_MC1                            55 /* ID for TCC2 event generator MC1 */
+#define EVENT_ID_GEN_TCC3_OVF                            56 /* ID for TCC3 event generator OVF */
+#define EVENT_ID_GEN_TCC3_TRG                            57 /* ID for TCC3 event generator TRG */
+#define EVENT_ID_GEN_TCC3_CNT                            58 /* ID for TCC3 event generator CNT */
+#define EVENT_ID_GEN_TCC3_MC0                            59 /* ID for TCC3 event generator MC0 */
+#define EVENT_ID_GEN_TCC3_MC1                            60 /* ID for TCC3 event generator MC1 */
+#define EVENT_ID_GEN_TCC4_OVF                            61 /* ID for TCC4 event generator OVF */
+#define EVENT_ID_GEN_TCC4_TRG                            62 /* ID for TCC4 event generator TRG */
+#define EVENT_ID_GEN_TCC4_CNT                            63 /* ID for TCC4 event generator CNT */
+#define EVENT_ID_GEN_TCC4_MC0                            64 /* ID for TCC4 event generator MC0 */
+#define EVENT_ID_GEN_TCC4_MC1                            65 /* ID for TCC4 event generator MC1 */
+#define EVENT_ID_GEN_TCC5_OVF                            66 /* ID for TCC5 event generator OVF */
+#define EVENT_ID_GEN_TCC5_TRG                            67 /* ID for TCC5 event generator TRG */
+#define EVENT_ID_GEN_TCC5_CNT                            68 /* ID for TCC5 event generator CNT */
+#define EVENT_ID_GEN_TCC5_MC0                            69 /* ID for TCC5 event generator MC0 */
+#define EVENT_ID_GEN_TCC5_MC1                            70 /* ID for TCC5 event generator MC1 */
+#define EVENT_ID_GEN_TCC6_OVF                            71 /* ID for TCC6 event generator OVF */
+#define EVENT_ID_GEN_TCC6_TRG                            72 /* ID for TCC6 event generator TRG */
+#define EVENT_ID_GEN_TCC6_CNT                            73 /* ID for TCC6 event generator CNT */
+#define EVENT_ID_GEN_TCC6_MC0                            74 /* ID for TCC6 event generator MC0 */
+#define EVENT_ID_GEN_TCC6_MC1                            75 /* ID for TCC6 event generator MC1 */
+#define EVENT_ID_GEN_ADC_CHRDY                           76 /* ID for ADC event generator CHRDY */
+#define EVENT_ID_GEN_ADC_CMP                             77 /* ID for ADC event generator CMP */
+#define EVENT_ID_GEN_AC_COMP0                            78 /* ID for AC event generator COMP0 */
+#define EVENT_ID_GEN_AC_COMP1                            79 /* ID for AC event generator COMP1 */
+#define EVENT_ID_GEN_AC_WIN0                             80 /* ID for AC event generator WIN0 */
+#define EVENT_ID_GEN_PTC_EOC                             81 /* ID for PTC event generator EOC */
+#define EVENT_ID_GEN_PTC_WCOMP                           82 /* ID for PTC event generator WCOMP */
+#define EVENT_ID_GEN_CCL0_LUTOUT0                        83 /* ID for CCL0 event generator LUTOUT0 */
+#define EVENT_ID_GEN_CCL0_LUTOUT1                        84 /* ID for CCL0 event generator LUTOUT1 */
+#define EVENT_ID_GEN_CCL0_LUTOUT2                        85 /* ID for CCL0 event generator LUTOUT2 */
+#define EVENT_ID_GEN_CCL0_LUTOUT3                        86 /* ID for CCL0 event generator LUTOUT3 */
+#define EVENT_ID_GEN_CCL1_LUTOUT0                        87 /* ID for CCL1 event generator LUTOUT0 */
+#define EVENT_ID_GEN_CCL1_LUTOUT1                        88 /* ID for CCL1 event generator LUTOUT1 */
+#define EVENT_ID_GEN_CCL1_LUTOUT2                        89 /* ID for CCL1 event generator LUTOUT2 */
+#define EVENT_ID_GEN_CCL1_LUTOUT3                        90 /* ID for CCL1 event generator LUTOUT3 */
+
+/* ************************************************************************** */
+/*                    Event User IDs for C32CM5112GC00100                     */
+/* ************************************************************************** */
+#define EVENT_ID_USER_FREQM_START                         0 /* ID for FREQM event user START */
+#define EVENT_ID_USER_RTC_TAMPER                          1 /* ID for RTC event user TAMPER */
+#define EVENT_ID_USER_PORT_EV0                            2 /* ID for PORT event user EV0 */
+#define EVENT_ID_USER_PORT_EV1                            3 /* ID for PORT event user EV1 */
+#define EVENT_ID_USER_PORT_EV2                            4 /* ID for PORT event user EV2 */
+#define EVENT_ID_USER_PORT_EV3                            5 /* ID for PORT event user EV3 */
+#define EVENT_ID_USER_DMAC_CH0                            6 /* ID for DMAC event user CH0 */
+#define EVENT_ID_USER_DMAC_CH1                            7 /* ID for DMAC event user CH1 */
+#define EVENT_ID_USER_DMAC_CH2                            8 /* ID for DMAC event user CH2 */
+#define EVENT_ID_USER_DMAC_CH3                            9 /* ID for DMAC event user CH3 */
+#define EVENT_ID_USER_TCC0_EV0                           10 /* ID for TCC0 event user EV0 */
+#define EVENT_ID_USER_TCC0_EV1                           11 /* ID for TCC0 event user EV1 */
+#define EVENT_ID_USER_TCC0_MC0                           12 /* ID for TCC0 event user MC0 */
+#define EVENT_ID_USER_TCC0_MC1                           13 /* ID for TCC0 event user MC1 */
+#define EVENT_ID_USER_TCC1_EV0                           14 /* ID for TCC1 event user EV0 */
+#define EVENT_ID_USER_TCC1_EV1                           15 /* ID for TCC1 event user EV1 */
+#define EVENT_ID_USER_TCC1_MC0                           16 /* ID for TCC1 event user MC0 */
+#define EVENT_ID_USER_TCC1_MC1                           17 /* ID for TCC1 event user MC1 */
+#define EVENT_ID_USER_TCC2_EV0                           18 /* ID for TCC2 event user EV0 */
+#define EVENT_ID_USER_TCC2_EV1                           19 /* ID for TCC2 event user EV1 */
+#define EVENT_ID_USER_TCC2_MC0                           20 /* ID for TCC2 event user MC0 */
+#define EVENT_ID_USER_TCC2_MC1                           21 /* ID for TCC2 event user MC1 */
+#define EVENT_ID_USER_TCC3_EV0                           22 /* ID for TCC3 event user EV0 */
+#define EVENT_ID_USER_TCC3_EV1                           23 /* ID for TCC3 event user EV1 */
+#define EVENT_ID_USER_TCC3_MC0                           24 /* ID for TCC3 event user MC0 */
+#define EVENT_ID_USER_TCC3_MC1                           25 /* ID for TCC3 event user MC1 */
+#define EVENT_ID_USER_TCC4_EV0                           26 /* ID for TCC4 event user EV0 */
+#define EVENT_ID_USER_TCC4_EV1                           27 /* ID for TCC4 event user EV1 */
+#define EVENT_ID_USER_TCC4_MC0                           28 /* ID for TCC4 event user MC0 */
+#define EVENT_ID_USER_TCC4_MC1                           29 /* ID for TCC4 event user MC1 */
+#define EVENT_ID_USER_TCC5_EV0                           30 /* ID for TCC5 event user EV0 */
+#define EVENT_ID_USER_TCC5_EV1                           31 /* ID for TCC5 event user EV1 */
+#define EVENT_ID_USER_TCC5_MC0                           32 /* ID for TCC5 event user MC0 */
+#define EVENT_ID_USER_TCC5_MC1                           33 /* ID for TCC5 event user MC1 */
+#define EVENT_ID_USER_TCC6_EV0                           34 /* ID for TCC6 event user EV0 */
+#define EVENT_ID_USER_TCC6_EV1                           35 /* ID for TCC6 event user EV1 */
+#define EVENT_ID_USER_TCC6_MC0                           36 /* ID for TCC6 event user MC0 */
+#define EVENT_ID_USER_TCC6_MC1                           37 /* ID for TCC6 event user MC1 */
+#define EVENT_ID_USER_ADC_TRIG0                          38 /* ID for ADC event user TRIG0 */
+#define EVENT_ID_USER_ADC_TRIG1                          39 /* ID for ADC event user TRIG1 */
+#define EVENT_ID_USER_ADC_TRIG2                          40 /* ID for ADC event user TRIG2 */
+#define EVENT_ID_USER_ADC_TRIG3                          41 /* ID for ADC event user TRIG3 */
+#define EVENT_ID_USER_ADC_TRIG4                          42 /* ID for ADC event user TRIG4 */
+#define EVENT_ID_USER_ADC_TRIG5                          43 /* ID for ADC event user TRIG5 */
+#define EVENT_ID_USER_ADC_TRIG6                          44 /* ID for ADC event user TRIG6 */
+#define EVENT_ID_USER_ADC_TRIG7                          45 /* ID for ADC event user TRIG7 */
+#define EVENT_ID_USER_ADC_TRIG8                          46 /* ID for ADC event user TRIG8 */
+#define EVENT_ID_USER_ADC_TRIG9                          47 /* ID for ADC event user TRIG9 */
+#define EVENT_ID_USER_ADC_TRIG10                         48 /* ID for ADC event user TRIG10 */
+#define EVENT_ID_USER_AC_SOC0                            49 /* ID for AC event user SOC0 */
+#define EVENT_ID_USER_AC_SOC1                            50 /* ID for AC event user SOC1 */
+#define EVENT_ID_USER_PTC_DSEQR                          51 /* ID for PTC event user DSEQR */
+#define EVENT_ID_USER_PTC_STCONV                         52 /* ID for PTC event user STCONV */
+#define EVENT_ID_USER_CCL0_LUTIN0                        53 /* ID for CCL0 event user LUTIN0 */
+#define EVENT_ID_USER_CCL0_LUTIN1                        54 /* ID for CCL0 event user LUTIN1 */
+#define EVENT_ID_USER_CCL0_LUTIN2                        55 /* ID for CCL0 event user LUTIN2 */
+#define EVENT_ID_USER_CCL0_LUTIN3                        56 /* ID for CCL0 event user LUTIN3 */
+#define EVENT_ID_USER_CCL1_LUTIN0                        57 /* ID for CCL1 event user LUTIN0 */
+#define EVENT_ID_USER_CCL1_LUTIN1                        58 /* ID for CCL1 event user LUTIN1 */
+#define EVENT_ID_USER_CCL1_LUTIN2                        59 /* ID for CCL1 event user LUTIN2 */
+#define EVENT_ID_USER_CCL1_LUTIN3                        60 /* ID for CCL1 event user LUTIN3 */
+#define EVENT_ID_USER_AT_TAMPSRC5                        61 /* ID for AT event user TAMPSRC5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PIC32CM5112GC00100_H_ */
+
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pio/pic32cm5112gc00048.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pio/pic32cm5112gc00048.h
new file mode 100644
index 00000000..fb85146a
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pio/pic32cm5112gc00048.h
@@ -0,0 +1,1058 @@
+/*
+ * Peripheral I/O description for PIC32CM5112GC00048
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:51Z  */
+#ifndef _PIC32CM5112GC00048_GPIO_H_
+#define _PIC32CM5112GC00048_GPIO_H_
+
+/* ======================= Peripheral I/O pin numbers ======================= */
+#define PIN_PA00                    (    0)  /* Pin Number for PA00 */
+#define PIN_PA01                    (    1)  /* Pin Number for PA01 */
+#define PIN_PA02                    (    2)  /* Pin Number for PA02 */
+#define PIN_PA03                    (    3)  /* Pin Number for PA03 */
+#define PIN_PA04                    (    4)  /* Pin Number for PA04 */
+#define PIN_PA05                    (    5)  /* Pin Number for PA05 */
+#define PIN_PA06                    (    6)  /* Pin Number for PA06 */
+#define PIN_PA07                    (    7)  /* Pin Number for PA07 */
+#define PIN_PA08                    (    8)  /* Pin Number for PA08 */
+#define PIN_PA09                    (    9)  /* Pin Number for PA09 */
+#define PIN_PB00                    (   32)  /* Pin Number for PB00 */
+#define PIN_PB01                    (   33)  /* Pin Number for PB01 */
+#define PIN_PB02                    (   34)  /* Pin Number for PB02 */
+#define PIN_PB03                    (   35)  /* Pin Number for PB03 */
+#define PIN_PB04                    (   36)  /* Pin Number for PB04 */
+#define PIN_PB05                    (   37)  /* Pin Number for PB05 */
+#define PIN_PB06                    (   38)  /* Pin Number for PB06 */
+#define PIN_PC00                    (   64)  /* Pin Number for PC00 */
+#define PIN_PC01                    (   65)  /* Pin Number for PC01 */
+#define PIN_PC02                    (   66)  /* Pin Number for PC02 */
+#define PIN_PC03                    (   67)  /* Pin Number for PC03 */
+#define PIN_PC04                    (   68)  /* Pin Number for PC04 */
+#define PIN_PC05                    (   69)  /* Pin Number for PC05 */
+#define PIN_PC06                    (   70)  /* Pin Number for PC06 */
+#define PIN_PC07                    (   71)  /* Pin Number for PC07 */
+#define PIN_PC08                    (   72)  /* Pin Number for PC08 */
+#define PIN_PD00                    (   96)  /* Pin Number for PD00 */
+#define PIN_PD01                    (   97)  /* Pin Number for PD01 */
+#define PIN_PD02                    (   98)  /* Pin Number for PD02 */
+#define PIN_PD03                    (   99)  /* Pin Number for PD03 */
+#define PIN_PD04                    (  100)  /* Pin Number for PD04 */
+#define PIN_PD05                    (  101)  /* Pin Number for PD05 */
+#define PIN_PD06                    (  102)  /* Pin Number for PD06 */
+#define PIN_PD07                    (  103)  /* Pin Number for PD07 */
+#define PIN_PD08                    (  104)  /* Pin Number for PD08 */
+#define PIN_PD09                    (  105)  /* Pin Number for PD09 */
+
+/* ========================== Peripheral I/O masks ========================== */
+#define PORT_PA00                   (_UINT32_(1) << 0) /* PORT mask for PA00 */
+#define PORT_PA01                   (_UINT32_(1) << 1) /* PORT mask for PA01 */
+#define PORT_PA02                   (_UINT32_(1) << 2) /* PORT mask for PA02 */
+#define PORT_PA03                   (_UINT32_(1) << 3) /* PORT mask for PA03 */
+#define PORT_PA04                   (_UINT32_(1) << 4) /* PORT mask for PA04 */
+#define PORT_PA05                   (_UINT32_(1) << 5) /* PORT mask for PA05 */
+#define PORT_PA06                   (_UINT32_(1) << 6) /* PORT mask for PA06 */
+#define PORT_PA07                   (_UINT32_(1) << 7) /* PORT mask for PA07 */
+#define PORT_PA08                   (_UINT32_(1) << 8) /* PORT mask for PA08 */
+#define PORT_PA09                   (_UINT32_(1) << 9) /* PORT mask for PA09 */
+#define PORT_PB00                   (_UINT32_(1) << 0) /* PORT mask for PB00 */
+#define PORT_PB01                   (_UINT32_(1) << 1) /* PORT mask for PB01 */
+#define PORT_PB02                   (_UINT32_(1) << 2) /* PORT mask for PB02 */
+#define PORT_PB03                   (_UINT32_(1) << 3) /* PORT mask for PB03 */
+#define PORT_PB04                   (_UINT32_(1) << 4) /* PORT mask for PB04 */
+#define PORT_PB05                   (_UINT32_(1) << 5) /* PORT mask for PB05 */
+#define PORT_PB06                   (_UINT32_(1) << 6) /* PORT mask for PB06 */
+#define PORT_PC00                   (_UINT32_(1) << 0) /* PORT mask for PC00 */
+#define PORT_PC01                   (_UINT32_(1) << 1) /* PORT mask for PC01 */
+#define PORT_PC02                   (_UINT32_(1) << 2) /* PORT mask for PC02 */
+#define PORT_PC03                   (_UINT32_(1) << 3) /* PORT mask for PC03 */
+#define PORT_PC04                   (_UINT32_(1) << 4) /* PORT mask for PC04 */
+#define PORT_PC05                   (_UINT32_(1) << 5) /* PORT mask for PC05 */
+#define PORT_PC06                   (_UINT32_(1) << 6) /* PORT mask for PC06 */
+#define PORT_PC07                   (_UINT32_(1) << 7) /* PORT mask for PC07 */
+#define PORT_PC08                   (_UINT32_(1) << 8) /* PORT mask for PC08 */
+#define PORT_PD00                   (_UINT32_(1) << 0) /* PORT mask for PD00 */
+#define PORT_PD01                   (_UINT32_(1) << 1) /* PORT mask for PD01 */
+#define PORT_PD02                   (_UINT32_(1) << 2) /* PORT mask for PD02 */
+#define PORT_PD03                   (_UINT32_(1) << 3) /* PORT mask for PD03 */
+#define PORT_PD04                   (_UINT32_(1) << 4) /* PORT mask for PD04 */
+#define PORT_PD05                   (_UINT32_(1) << 5) /* PORT mask for PD05 */
+#define PORT_PD06                   (_UINT32_(1) << 6) /* PORT mask for PD06 */
+#define PORT_PD07                   (_UINT32_(1) << 7) /* PORT mask for PD07 */
+#define PORT_PD08                   (_UINT32_(1) << 8) /* PORT mask for PD08 */
+#define PORT_PD09                   (_UINT32_(1) << 9) /* PORT mask for PD09 */
+
+/* =================== PORT definition for AC peripheral ==================== */
+#define PIN_PA07B_AC_AIN0                          _UINT32_(7) 
+#define MUX_PA07B_AC_AIN0                          _UINT32_(1) 
+#define PINMUX_PA07B_AC_AIN0                       ((PIN_PA07B_AC_AIN0 << 16) | MUX_PA07B_AC_AIN0)
+#define PORT_PA07B_AC_AIN0                         (_UINT32_(1) << 7)
+
+#define PIN_PA08B_AC_AIN1                          _UINT32_(8) 
+#define MUX_PA08B_AC_AIN1                          _UINT32_(1) 
+#define PINMUX_PA08B_AC_AIN1                       ((PIN_PA08B_AC_AIN1 << 16) | MUX_PA08B_AC_AIN1)
+#define PORT_PA08B_AC_AIN1                         (_UINT32_(1) << 8)
+
+#define PIN_PB00B_AC_AIN2                          _UINT32_(32)
+#define MUX_PB00B_AC_AIN2                          _UINT32_(1) 
+#define PINMUX_PB00B_AC_AIN2                       ((PIN_PB00B_AC_AIN2 << 16) | MUX_PB00B_AC_AIN2)
+#define PORT_PB00B_AC_AIN2                         (_UINT32_(1) << 0)
+
+#define PIN_PB03B_AC_AIN3                          _UINT32_(35)
+#define MUX_PB03B_AC_AIN3                          _UINT32_(1) 
+#define PINMUX_PB03B_AC_AIN3                       ((PIN_PB03B_AC_AIN3 << 16) | MUX_PB03B_AC_AIN3)
+#define PORT_PB03B_AC_AIN3                         (_UINT32_(1) << 3)
+
+#define PIN_PA01B_AC_CMP0                          _UINT32_(1) 
+#define MUX_PA01B_AC_CMP0                          _UINT32_(1) 
+#define PINMUX_PA01B_AC_CMP0                       ((PIN_PA01B_AC_CMP0 << 16) | MUX_PA01B_AC_CMP0)
+#define PORT_PA01B_AC_CMP0                         (_UINT32_(1) << 1)
+
+#define PIN_PA02B_AC_CMP1                          _UINT32_(2) 
+#define MUX_PA02B_AC_CMP1                          _UINT32_(1) 
+#define PINMUX_PA02B_AC_CMP1                       ((PIN_PA02B_AC_CMP1 << 16) | MUX_PA02B_AC_CMP1)
+#define PORT_PA02B_AC_CMP1                         (_UINT32_(1) << 2)
+
+/* =================== PORT definition for ADC peripheral =================== */
+#define PIN_PA03B_ADC_ADC0_AIN0                    _UINT32_(3) 
+#define MUX_PA03B_ADC_ADC0_AIN0                    _UINT32_(1) 
+#define PINMUX_PA03B_ADC_ADC0_AIN0                 ((PIN_PA03B_ADC_ADC0_AIN0 << 16) | MUX_PA03B_ADC_ADC0_AIN0)
+#define PORT_PA03B_ADC_ADC0_AIN0                   (_UINT32_(1) << 3)
+
+#define PIN_PA04B_ADC_ADC0_AIN1                    _UINT32_(4) 
+#define MUX_PA04B_ADC_ADC0_AIN1                    _UINT32_(1) 
+#define PINMUX_PA04B_ADC_ADC0_AIN1                 ((PIN_PA04B_ADC_ADC0_AIN1 << 16) | MUX_PA04B_ADC_ADC0_AIN1)
+#define PORT_PA04B_ADC_ADC0_AIN1                   (_UINT32_(1) << 4)
+
+#define PIN_PA05B_ADC_ADC0_AIN2                    _UINT32_(5) 
+#define MUX_PA05B_ADC_ADC0_AIN2                    _UINT32_(1) 
+#define PINMUX_PA05B_ADC_ADC0_AIN2                 ((PIN_PA05B_ADC_ADC0_AIN2 << 16) | MUX_PA05B_ADC_ADC0_AIN2)
+#define PORT_PA05B_ADC_ADC0_AIN2                   (_UINT32_(1) << 5)
+
+#define PIN_PA06B_ADC_ADC0_AIN3                    _UINT32_(6) 
+#define MUX_PA06B_ADC_ADC0_AIN3                    _UINT32_(1) 
+#define PINMUX_PA06B_ADC_ADC0_AIN3                 ((PIN_PA06B_ADC_ADC0_AIN3 << 16) | MUX_PA06B_ADC_ADC0_AIN3)
+#define PORT_PA06B_ADC_ADC0_AIN3                   (_UINT32_(1) << 6)
+
+#define PIN_PA07B_ADC_ADC0_AIN4                    _UINT32_(7) 
+#define MUX_PA07B_ADC_ADC0_AIN4                    _UINT32_(1) 
+#define PINMUX_PA07B_ADC_ADC0_AIN4                 ((PIN_PA07B_ADC_ADC0_AIN4 << 16) | MUX_PA07B_ADC_ADC0_AIN4)
+#define PORT_PA07B_ADC_ADC0_AIN4                   (_UINT32_(1) << 7)
+
+#define PIN_PA08B_ADC_ADC0_AIN5                    _UINT32_(8) 
+#define MUX_PA08B_ADC_ADC0_AIN5                    _UINT32_(1) 
+#define PINMUX_PA08B_ADC_ADC0_AIN5                 ((PIN_PA08B_ADC_ADC0_AIN5 << 16) | MUX_PA08B_ADC_ADC0_AIN5)
+#define PORT_PA08B_ADC_ADC0_AIN5                   (_UINT32_(1) << 8)
+
+#define PIN_PA09B_ADC_ADC0_AIN6                    _UINT32_(9) 
+#define MUX_PA09B_ADC_ADC0_AIN6                    _UINT32_(1) 
+#define PINMUX_PA09B_ADC_ADC0_AIN6                 ((PIN_PA09B_ADC_ADC0_AIN6 << 16) | MUX_PA09B_ADC_ADC0_AIN6)
+#define PORT_PA09B_ADC_ADC0_AIN6                   (_UINT32_(1) << 9)
+
+#define PIN_PB00B_ADC_ADC0_AIN7                    _UINT32_(32)
+#define MUX_PB00B_ADC_ADC0_AIN7                    _UINT32_(1) 
+#define PINMUX_PB00B_ADC_ADC0_AIN7                 ((PIN_PB00B_ADC_ADC0_AIN7 << 16) | MUX_PB00B_ADC_ADC0_AIN7)
+#define PORT_PB00B_ADC_ADC0_AIN7                   (_UINT32_(1) << 0)
+
+#define PIN_PB03B_ADC_ADC0_AIN8                    _UINT32_(35)
+#define MUX_PB03B_ADC_ADC0_AIN8                    _UINT32_(1) 
+#define PINMUX_PB03B_ADC_ADC0_AIN8                 ((PIN_PB03B_ADC_ADC0_AIN8 << 16) | MUX_PB03B_ADC_ADC0_AIN8)
+#define PORT_PB03B_ADC_ADC0_AIN8                   (_UINT32_(1) << 3)
+
+#define PIN_PB04B_ADC_ADC0_AIN9                    _UINT32_(36)
+#define MUX_PB04B_ADC_ADC0_AIN9                    _UINT32_(1) 
+#define PINMUX_PB04B_ADC_ADC0_AIN9                 ((PIN_PB04B_ADC_ADC0_AIN9 << 16) | MUX_PB04B_ADC_ADC0_AIN9)
+#define PORT_PB04B_ADC_ADC0_AIN9                   (_UINT32_(1) << 4)
+
+#define PIN_PB05B_ADC_ADC0_AIN10                   _UINT32_(37)
+#define MUX_PB05B_ADC_ADC0_AIN10                   _UINT32_(1) 
+#define PINMUX_PB05B_ADC_ADC0_AIN10                ((PIN_PB05B_ADC_ADC0_AIN10 << 16) | MUX_PB05B_ADC_ADC0_AIN10)
+#define PORT_PB05B_ADC_ADC0_AIN10                  (_UINT32_(1) << 5)
+
+#define PIN_PB06B_ADC_ADC0_AIN11                   _UINT32_(38)
+#define MUX_PB06B_ADC_ADC0_AIN11                   _UINT32_(1) 
+#define PINMUX_PB06B_ADC_ADC0_AIN11                ((PIN_PB06B_ADC_ADC0_AIN11 << 16) | MUX_PB06B_ADC_ADC0_AIN11)
+#define PORT_PB06B_ADC_ADC0_AIN11                  (_UINT32_(1) << 6)
+
+#define PIN_PA04B_ADC_ADC0_ANN0                    _UINT32_(4) 
+#define MUX_PA04B_ADC_ADC0_ANN0                    _UINT32_(1) 
+#define PINMUX_PA04B_ADC_ADC0_ANN0                 ((PIN_PA04B_ADC_ADC0_ANN0 << 16) | MUX_PA04B_ADC_ADC0_ANN0)
+#define PORT_PA04B_ADC_ADC0_ANN0                   (_UINT32_(1) << 4)
+
+#define PIN_PA06B_ADC_ADC0_ANN2                    _UINT32_(6) 
+#define MUX_PA06B_ADC_ADC0_ANN2                    _UINT32_(1) 
+#define PINMUX_PA06B_ADC_ADC0_ANN2                 ((PIN_PA06B_ADC_ADC0_ANN2 << 16) | MUX_PA06B_ADC_ADC0_ANN2)
+#define PORT_PA06B_ADC_ADC0_ANN2                   (_UINT32_(1) << 6)
+
+#define PIN_PA08B_ADC_ADC0_ANN4                    _UINT32_(8) 
+#define MUX_PA08B_ADC_ADC0_ANN4                    _UINT32_(1) 
+#define PINMUX_PA08B_ADC_ADC0_ANN4                 ((PIN_PA08B_ADC_ADC0_ANN4 << 16) | MUX_PA08B_ADC_ADC0_ANN4)
+#define PORT_PA08B_ADC_ADC0_ANN4                   (_UINT32_(1) << 8)
+
+/* ================== PORT definition for CAN0 peripheral =================== */
+#define PIN_PC01H_CAN0_RX                          _UINT32_(65)
+#define MUX_PC01H_CAN0_RX                          _UINT32_(7) 
+#define PINMUX_PC01H_CAN0_RX                       ((PIN_PC01H_CAN0_RX << 16) | MUX_PC01H_CAN0_RX)
+#define PORT_PC01H_CAN0_RX                         (_UINT32_(1) << 1)
+
+#define PIN_PD06H_CAN0_RX                          _UINT32_(102)
+#define MUX_PD06H_CAN0_RX                          _UINT32_(7) 
+#define PINMUX_PD06H_CAN0_RX                       ((PIN_PD06H_CAN0_RX << 16) | MUX_PD06H_CAN0_RX)
+#define PORT_PD06H_CAN0_RX                         (_UINT32_(1) << 6)
+
+#define PIN_PC02H_CAN0_TX                          _UINT32_(66)
+#define MUX_PC02H_CAN0_TX                          _UINT32_(7) 
+#define PINMUX_PC02H_CAN0_TX                       ((PIN_PC02H_CAN0_TX << 16) | MUX_PC02H_CAN0_TX)
+#define PORT_PC02H_CAN0_TX                         (_UINT32_(1) << 2)
+
+#define PIN_PD08H_CAN0_TX                          _UINT32_(104)
+#define MUX_PD08H_CAN0_TX                          _UINT32_(7) 
+#define PINMUX_PD08H_CAN0_TX                       ((PIN_PD08H_CAN0_TX << 16) | MUX_PD08H_CAN0_TX)
+#define PORT_PD08H_CAN0_TX                         (_UINT32_(1) << 8)
+
+/* ================== PORT definition for CAN1 peripheral =================== */
+#define PIN_PA00H_CAN1_RX                          _UINT32_(0) 
+#define MUX_PA00H_CAN1_RX                          _UINT32_(7) 
+#define PINMUX_PA00H_CAN1_RX                       ((PIN_PA00H_CAN1_RX << 16) | MUX_PA00H_CAN1_RX)
+#define PORT_PA00H_CAN1_RX                         (_UINT32_(1) << 0)
+
+#define PIN_PC05H_CAN1_RX                          _UINT32_(69)
+#define MUX_PC05H_CAN1_RX                          _UINT32_(7) 
+#define PINMUX_PC05H_CAN1_RX                       ((PIN_PC05H_CAN1_RX << 16) | MUX_PC05H_CAN1_RX)
+#define PORT_PC05H_CAN1_RX                         (_UINT32_(1) << 5)
+
+#define PIN_PA01H_CAN1_TX                          _UINT32_(1) 
+#define MUX_PA01H_CAN1_TX                          _UINT32_(7) 
+#define PINMUX_PA01H_CAN1_TX                       ((PIN_PA01H_CAN1_TX << 16) | MUX_PA01H_CAN1_TX)
+#define PORT_PA01H_CAN1_TX                         (_UINT32_(1) << 1)
+
+#define PIN_PC06H_CAN1_TX                          _UINT32_(70)
+#define MUX_PC06H_CAN1_TX                          _UINT32_(7) 
+#define PINMUX_PC06H_CAN1_TX                       ((PIN_PC06H_CAN1_TX << 16) | MUX_PC06H_CAN1_TX)
+#define PORT_PC06H_CAN1_TX                         (_UINT32_(1) << 6)
+
+/* ================== PORT definition for CCL0 peripheral =================== */
+#define PIN_PC01I_CCL0_IN0                         _UINT32_(65)
+#define MUX_PC01I_CCL0_IN0                         _UINT32_(8) 
+#define PINMUX_PC01I_CCL0_IN0                      ((PIN_PC01I_CCL0_IN0 << 16) | MUX_PC01I_CCL0_IN0)
+#define PORT_PC01I_CCL0_IN0                        (_UINT32_(1) << 1)
+
+#define PIN_PC02I_CCL0_IN1                         _UINT32_(66)
+#define MUX_PC02I_CCL0_IN1                         _UINT32_(8) 
+#define PINMUX_PC02I_CCL0_IN1                      ((PIN_PC02I_CCL0_IN1 << 16) | MUX_PC02I_CCL0_IN1)
+#define PORT_PC02I_CCL0_IN1                        (_UINT32_(1) << 2)
+
+#define PIN_PD00I_CCL0_IN3                         _UINT32_(96)
+#define MUX_PD00I_CCL0_IN3                         _UINT32_(8) 
+#define PINMUX_PD00I_CCL0_IN3                      ((PIN_PD00I_CCL0_IN3 << 16) | MUX_PD00I_CCL0_IN3)
+#define PORT_PD00I_CCL0_IN3                        (_UINT32_(1) << 0)
+
+#define PIN_PD01I_CCL0_IN4                         _UINT32_(97)
+#define MUX_PD01I_CCL0_IN4                         _UINT32_(8) 
+#define PINMUX_PD01I_CCL0_IN4                      ((PIN_PD01I_CCL0_IN4 << 16) | MUX_PD01I_CCL0_IN4)
+#define PORT_PD01I_CCL0_IN4                        (_UINT32_(1) << 1)
+
+#define PIN_PA00I_CCL0_IN6                         _UINT32_(0) 
+#define MUX_PA00I_CCL0_IN6                         _UINT32_(8) 
+#define PINMUX_PA00I_CCL0_IN6                      ((PIN_PA00I_CCL0_IN6 << 16) | MUX_PA00I_CCL0_IN6)
+#define PORT_PA00I_CCL0_IN6                        (_UINT32_(1) << 0)
+
+#define PIN_PA01I_CCL0_IN7                         _UINT32_(1) 
+#define MUX_PA01I_CCL0_IN7                         _UINT32_(8) 
+#define PINMUX_PA01I_CCL0_IN7                      ((PIN_PA01I_CCL0_IN7 << 16) | MUX_PA01I_CCL0_IN7)
+#define PORT_PA01I_CCL0_IN7                        (_UINT32_(1) << 1)
+
+#define PIN_PB05I_CCL0_IN9                         _UINT32_(37)
+#define MUX_PB05I_CCL0_IN9                         _UINT32_(8) 
+#define PINMUX_PB05I_CCL0_IN9                      ((PIN_PB05I_CCL0_IN9 << 16) | MUX_PB05I_CCL0_IN9)
+#define PORT_PB05I_CCL0_IN9                        (_UINT32_(1) << 5)
+
+#define PIN_PB06I_CCL0_IN10                        _UINT32_(38)
+#define MUX_PB06I_CCL0_IN10                        _UINT32_(8) 
+#define PINMUX_PB06I_CCL0_IN10                     ((PIN_PB06I_CCL0_IN10 << 16) | MUX_PB06I_CCL0_IN10)
+#define PORT_PB06I_CCL0_IN10                       (_UINT32_(1) << 6)
+
+#define PIN_PC03I_CCL0_OUT0                        _UINT32_(67)
+#define MUX_PC03I_CCL0_OUT0                        _UINT32_(8) 
+#define PINMUX_PC03I_CCL0_OUT0                     ((PIN_PC03I_CCL0_OUT0 << 16) | MUX_PC03I_CCL0_OUT0)
+#define PORT_PC03I_CCL0_OUT0                       (_UINT32_(1) << 3)
+
+#define PIN_PD08I_CCL0_OUT1                        _UINT32_(104)
+#define MUX_PD08I_CCL0_OUT1                        _UINT32_(8) 
+#define PINMUX_PD08I_CCL0_OUT1                     ((PIN_PD08I_CCL0_OUT1 << 16) | MUX_PD08I_CCL0_OUT1)
+#define PORT_PD08I_CCL0_OUT1                       (_UINT32_(1) << 8)
+
+#define PIN_PA02I_CCL0_OUT2                        _UINT32_(2) 
+#define MUX_PA02I_CCL0_OUT2                        _UINT32_(8) 
+#define PINMUX_PA02I_CCL0_OUT2                     ((PIN_PA02I_CCL0_OUT2 << 16) | MUX_PA02I_CCL0_OUT2)
+#define PORT_PA02I_CCL0_OUT2                       (_UINT32_(1) << 2)
+
+#define PIN_PC00I_CCL0_OUT3                        _UINT32_(64)
+#define MUX_PC00I_CCL0_OUT3                        _UINT32_(8) 
+#define PINMUX_PC00I_CCL0_OUT3                     ((PIN_PC00I_CCL0_OUT3 << 16) | MUX_PC00I_CCL0_OUT3)
+#define PORT_PC00I_CCL0_OUT3                       (_UINT32_(1) << 0)
+
+/* ================== PORT definition for CCL1 peripheral =================== */
+#define PIN_PC04I_CCL1_IN0                         _UINT32_(68)
+#define MUX_PC04I_CCL1_IN0                         _UINT32_(8) 
+#define PINMUX_PC04I_CCL1_IN0                      ((PIN_PC04I_CCL1_IN0 << 16) | MUX_PC04I_CCL1_IN0)
+#define PORT_PC04I_CCL1_IN0                        (_UINT32_(1) << 4)
+
+#define PIN_PC05I_CCL1_IN1                         _UINT32_(69)
+#define MUX_PC05I_CCL1_IN1                         _UINT32_(8) 
+#define PINMUX_PC05I_CCL1_IN1                      ((PIN_PC05I_CCL1_IN1 << 16) | MUX_PC05I_CCL1_IN1)
+#define PORT_PC05I_CCL1_IN1                        (_UINT32_(1) << 5)
+
+#define PIN_PD06I_CCL1_IN3                         _UINT32_(102)
+#define MUX_PD06I_CCL1_IN3                         _UINT32_(8) 
+#define PINMUX_PD06I_CCL1_IN3                      ((PIN_PD06I_CCL1_IN3 << 16) | MUX_PD06I_CCL1_IN3)
+#define PORT_PD06I_CCL1_IN3                        (_UINT32_(1) << 6)
+
+#define PIN_PD07I_CCL1_IN4                         _UINT32_(103)
+#define MUX_PD07I_CCL1_IN4                         _UINT32_(8) 
+#define PINMUX_PD07I_CCL1_IN4                      ((PIN_PD07I_CCL1_IN4 << 16) | MUX_PD07I_CCL1_IN4)
+#define PORT_PD07I_CCL1_IN4                        (_UINT32_(1) << 7)
+
+#define PIN_PA09I_CCL1_IN6                         _UINT32_(9) 
+#define MUX_PA09I_CCL1_IN6                         _UINT32_(8) 
+#define PINMUX_PA09I_CCL1_IN6                      ((PIN_PA09I_CCL1_IN6 << 16) | MUX_PA09I_CCL1_IN6)
+#define PORT_PA09I_CCL1_IN6                        (_UINT32_(1) << 9)
+
+#define PIN_PA06I_CCL1_IN7                         _UINT32_(6) 
+#define MUX_PA06I_CCL1_IN7                         _UINT32_(8) 
+#define PINMUX_PA06I_CCL1_IN7                      ((PIN_PA06I_CCL1_IN7 << 16) | MUX_PA06I_CCL1_IN7)
+#define PORT_PA06I_CCL1_IN7                        (_UINT32_(1) << 6)
+
+#define PIN_PB04I_CCL1_IN9                         _UINT32_(36)
+#define MUX_PB04I_CCL1_IN9                         _UINT32_(8) 
+#define PINMUX_PB04I_CCL1_IN9                      ((PIN_PB04I_CCL1_IN9 << 16) | MUX_PB04I_CCL1_IN9)
+#define PORT_PB04I_CCL1_IN9                        (_UINT32_(1) << 4)
+
+#define PIN_PB03I_CCL1_IN10                        _UINT32_(35)
+#define MUX_PB03I_CCL1_IN10                        _UINT32_(8) 
+#define PINMUX_PB03I_CCL1_IN10                     ((PIN_PB03I_CCL1_IN10 << 16) | MUX_PB03I_CCL1_IN10)
+#define PORT_PB03I_CCL1_IN10                       (_UINT32_(1) << 3)
+
+#define PIN_PC06I_CCL1_OUT0                        _UINT32_(70)
+#define MUX_PC06I_CCL1_OUT0                        _UINT32_(8) 
+#define PINMUX_PC06I_CCL1_OUT0                     ((PIN_PC06I_CCL1_OUT0 << 16) | MUX_PC06I_CCL1_OUT0)
+#define PORT_PC06I_CCL1_OUT0                       (_UINT32_(1) << 6)
+
+#define PIN_PD09I_CCL1_OUT1                        _UINT32_(105)
+#define MUX_PD09I_CCL1_OUT1                        _UINT32_(8) 
+#define PINMUX_PD09I_CCL1_OUT1                     ((PIN_PD09I_CCL1_OUT1 << 16) | MUX_PD09I_CCL1_OUT1)
+#define PORT_PD09I_CCL1_OUT1                       (_UINT32_(1) << 9)
+
+#define PIN_PA05I_CCL1_OUT2                        _UINT32_(5) 
+#define MUX_PA05I_CCL1_OUT2                        _UINT32_(8) 
+#define PINMUX_PA05I_CCL1_OUT2                     ((PIN_PA05I_CCL1_OUT2 << 16) | MUX_PA05I_CCL1_OUT2)
+#define PORT_PA05I_CCL1_OUT2                       (_UINT32_(1) << 5)
+
+#define PIN_PB00I_CCL1_OUT3                        _UINT32_(32)
+#define MUX_PB00I_CCL1_OUT3                        _UINT32_(8) 
+#define PINMUX_PB00I_CCL1_OUT3                     ((PIN_PB00I_CCL1_OUT3 << 16) | MUX_PB00I_CCL1_OUT3)
+#define PORT_PB00I_CCL1_OUT3                       (_UINT32_(1) << 0)
+
+/* =================== PORT definition for EIC peripheral =================== */
+#define PIN_PA00A_EIC_EXTINT0                      _UINT32_(0) 
+#define MUX_PA00A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PA00A_EIC_EXTINT0                   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0                     (_UINT32_(1) << 0)
+#define PIN_PA00A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PA00 External Interrupt Line */
+
+#define PIN_PB00A_EIC_EXTINT0                      _UINT32_(32)
+#define MUX_PB00A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PB00A_EIC_EXTINT0                   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0                     (_UINT32_(1) << 0)
+#define PIN_PB00A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PB00 External Interrupt Line */
+
+#define PIN_PC00A_EIC_EXTINT0                      _UINT32_(64)
+#define MUX_PC00A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PC00A_EIC_EXTINT0                   ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
+#define PORT_PC00A_EIC_EXTINT0                     (_UINT32_(1) << 0)
+#define PIN_PC00A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PC00 External Interrupt Line */
+
+#define PIN_PA01A_EIC_EXTINT1                      _UINT32_(1) 
+#define MUX_PA01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PA01A_EIC_EXTINT1                   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PA01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PA01 External Interrupt Line */
+
+#define PIN_PB01A_EIC_EXTINT1                      _UINT32_(33)
+#define MUX_PB01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PB01A_EIC_EXTINT1                   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PB01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PB01 External Interrupt Line */
+
+#define PIN_PC01A_EIC_EXTINT1                      _UINT32_(65)
+#define MUX_PC01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PC01A_EIC_EXTINT1                   ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
+#define PORT_PC01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PC01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PC01 External Interrupt Line */
+
+#define PIN_PD01A_EIC_EXTINT1                      _UINT32_(97)
+#define MUX_PD01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PD01A_EIC_EXTINT1                   ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1)
+#define PORT_PD01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PD01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PD01 External Interrupt Line */
+
+#define PIN_PA02A_EIC_EXTINT2                      _UINT32_(2) 
+#define MUX_PA02A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PA02A_EIC_EXTINT2                   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2                     (_UINT32_(1) << 2)
+#define PIN_PA02A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PA02 External Interrupt Line */
+
+#define PIN_PB02A_EIC_EXTINT2                      _UINT32_(34)
+#define MUX_PB02A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PB02A_EIC_EXTINT2                   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2                     (_UINT32_(1) << 2)
+#define PIN_PB02A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PB02 External Interrupt Line */
+
+#define PIN_PC02A_EIC_EXTINT2                      _UINT32_(66)
+#define MUX_PC02A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PC02A_EIC_EXTINT2                   ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
+#define PORT_PC02A_EIC_EXTINT2                     (_UINT32_(1) << 2)
+#define PIN_PC02A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PC02 External Interrupt Line */
+
+#define PIN_PD04A_EIC_EXTINT2                      _UINT32_(100)
+#define MUX_PD04A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PD04A_EIC_EXTINT2                   ((PIN_PD04A_EIC_EXTINT2 << 16) | MUX_PD04A_EIC_EXTINT2)
+#define PORT_PD04A_EIC_EXTINT2                     (_UINT32_(1) << 4)
+#define PIN_PD04A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PD04 External Interrupt Line */
+
+#define PIN_PA03A_EIC_EXTINT3                      _UINT32_(3) 
+#define MUX_PA03A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PA03A_EIC_EXTINT3                   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3                     (_UINT32_(1) << 3)
+#define PIN_PA03A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PA03 External Interrupt Line */
+
+#define PIN_PB03A_EIC_EXTINT3                      _UINT32_(35)
+#define MUX_PB03A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PB03A_EIC_EXTINT3                   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3                     (_UINT32_(1) << 3)
+#define PIN_PB03A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PB03 External Interrupt Line */
+
+#define PIN_PC03A_EIC_EXTINT3                      _UINT32_(67)
+#define MUX_PC03A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PC03A_EIC_EXTINT3                   ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
+#define PORT_PC03A_EIC_EXTINT3                     (_UINT32_(1) << 3)
+#define PIN_PC03A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PC03 External Interrupt Line */
+
+#define PIN_PD05A_EIC_EXTINT3                      _UINT32_(101)
+#define MUX_PD05A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PD05A_EIC_EXTINT3                   ((PIN_PD05A_EIC_EXTINT3 << 16) | MUX_PD05A_EIC_EXTINT3)
+#define PORT_PD05A_EIC_EXTINT3                     (_UINT32_(1) << 5)
+#define PIN_PD05A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PD05 External Interrupt Line */
+
+#define PIN_PA04A_EIC_EXTINT4                      _UINT32_(4) 
+#define MUX_PA04A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PA04A_EIC_EXTINT4                   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4                     (_UINT32_(1) << 4)
+#define PIN_PA04A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PA04 External Interrupt Line */
+
+#define PIN_PB04A_EIC_EXTINT4                      _UINT32_(36)
+#define MUX_PB04A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PB04A_EIC_EXTINT4                   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4                     (_UINT32_(1) << 4)
+#define PIN_PB04A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PB04 External Interrupt Line */
+
+#define PIN_PC04A_EIC_EXTINT4                      _UINT32_(68)
+#define MUX_PC04A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PC04A_EIC_EXTINT4                   ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4)
+#define PORT_PC04A_EIC_EXTINT4                     (_UINT32_(1) << 4)
+#define PIN_PC04A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PC04 External Interrupt Line */
+
+#define PIN_PD07A_EIC_EXTINT4                      _UINT32_(103)
+#define MUX_PD07A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PD07A_EIC_EXTINT4                   ((PIN_PD07A_EIC_EXTINT4 << 16) | MUX_PD07A_EIC_EXTINT4)
+#define PORT_PD07A_EIC_EXTINT4                     (_UINT32_(1) << 7)
+#define PIN_PD07A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PD07 External Interrupt Line */
+
+#define PIN_PA05A_EIC_EXTINT5                      _UINT32_(5) 
+#define MUX_PA05A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PA05A_EIC_EXTINT5                   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5                     (_UINT32_(1) << 5)
+#define PIN_PA05A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PA05 External Interrupt Line */
+
+#define PIN_PB05A_EIC_EXTINT5                      _UINT32_(37)
+#define MUX_PB05A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PB05A_EIC_EXTINT5                   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5                     (_UINT32_(1) << 5)
+#define PIN_PB05A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PB05 External Interrupt Line */
+
+#define PIN_PC05A_EIC_EXTINT5                      _UINT32_(69)
+#define MUX_PC05A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PC05A_EIC_EXTINT5                   ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
+#define PORT_PC05A_EIC_EXTINT5                     (_UINT32_(1) << 5)
+#define PIN_PC05A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PC05 External Interrupt Line */
+
+#define PIN_PD08A_EIC_EXTINT5                      _UINT32_(104)
+#define MUX_PD08A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PD08A_EIC_EXTINT5                   ((PIN_PD08A_EIC_EXTINT5 << 16) | MUX_PD08A_EIC_EXTINT5)
+#define PORT_PD08A_EIC_EXTINT5                     (_UINT32_(1) << 8)
+#define PIN_PD08A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PD08 External Interrupt Line */
+
+#define PIN_PA06A_EIC_EXTINT6                      _UINT32_(6) 
+#define MUX_PA06A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PA06A_EIC_EXTINT6                   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6                     (_UINT32_(1) << 6)
+#define PIN_PA06A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PA06 External Interrupt Line */
+
+#define PIN_PB06A_EIC_EXTINT6                      _UINT32_(38)
+#define MUX_PB06A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PB06A_EIC_EXTINT6                   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6                     (_UINT32_(1) << 6)
+#define PIN_PB06A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PB06 External Interrupt Line */
+
+#define PIN_PC06A_EIC_EXTINT6                      _UINT32_(70)
+#define MUX_PC06A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PC06A_EIC_EXTINT6                   ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
+#define PORT_PC06A_EIC_EXTINT6                     (_UINT32_(1) << 6)
+#define PIN_PC06A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PC06 External Interrupt Line */
+
+#define PIN_PD09A_EIC_EXTINT6                      _UINT32_(105)
+#define MUX_PD09A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PD09A_EIC_EXTINT6                   ((PIN_PD09A_EIC_EXTINT6 << 16) | MUX_PD09A_EIC_EXTINT6)
+#define PORT_PD09A_EIC_EXTINT6                     (_UINT32_(1) << 9)
+#define PIN_PD09A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PD09 External Interrupt Line */
+
+#define PIN_PA07A_EIC_EXTINT7                      _UINT32_(7) 
+#define MUX_PA07A_EIC_EXTINT7                      _UINT32_(0) 
+#define PINMUX_PA07A_EIC_EXTINT7                   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7                     (_UINT32_(1) << 7)
+#define PIN_PA07A_EIC_EXTINT_NUM                   _UINT32_(7)  /* EIC signal: PIN_PA07 External Interrupt Line */
+
+#define PIN_PA08A_EIC_EXTINT8                      _UINT32_(8) 
+#define MUX_PA08A_EIC_EXTINT8                      _UINT32_(0) 
+#define PINMUX_PA08A_EIC_EXTINT8                   ((PIN_PA08A_EIC_EXTINT8 << 16) | MUX_PA08A_EIC_EXTINT8)
+#define PORT_PA08A_EIC_EXTINT8                     (_UINT32_(1) << 8)
+#define PIN_PA08A_EIC_EXTINT_NUM                   _UINT32_(8)  /* EIC signal: PIN_PA08 External Interrupt Line */
+
+#define PIN_PA09A_EIC_EXTINT9                      _UINT32_(9) 
+#define MUX_PA09A_EIC_EXTINT9                      _UINT32_(0) 
+#define PINMUX_PA09A_EIC_EXTINT9                   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9                     (_UINT32_(1) << 9)
+#define PIN_PA09A_EIC_EXTINT_NUM                   _UINT32_(9)  /* EIC signal: PIN_PA09 External Interrupt Line */
+
+#define PIN_PD00A_EIC_NMI                          _UINT32_(96)
+#define MUX_PD00A_EIC_NMI                          _UINT32_(0) 
+#define PINMUX_PD00A_EIC_NMI                       ((PIN_PD00A_EIC_NMI << 16) | MUX_PD00A_EIC_NMI)
+#define PORT_PD00A_EIC_NMI                         (_UINT32_(1) << 0)
+
+/* ================== PORT definition for GCLK peripheral =================== */
+#define PIN_PB06K_GCLK_IO0                         _UINT32_(38)
+#define MUX_PB06K_GCLK_IO0                         _UINT32_(10)
+#define PINMUX_PB06K_GCLK_IO0                      ((PIN_PB06K_GCLK_IO0 << 16) | MUX_PB06K_GCLK_IO0)
+#define PORT_PB06K_GCLK_IO0                        (_UINT32_(1) << 6)
+
+#define PIN_PD05K_GCLK_IO0                         _UINT32_(101)
+#define MUX_PD05K_GCLK_IO0                         _UINT32_(10)
+#define PINMUX_PD05K_GCLK_IO0                      ((PIN_PD05K_GCLK_IO0 << 16) | MUX_PD05K_GCLK_IO0)
+#define PORT_PD05K_GCLK_IO0                        (_UINT32_(1) << 5)
+
+#define PIN_PC00K_GCLK_IO1                         _UINT32_(64)
+#define MUX_PC00K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PC00K_GCLK_IO1                      ((PIN_PC00K_GCLK_IO1 << 16) | MUX_PC00K_GCLK_IO1)
+#define PORT_PC00K_GCLK_IO1                        (_UINT32_(1) << 0)
+
+#define PIN_PC05K_GCLK_IO1                         _UINT32_(69)
+#define MUX_PC05K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PC05K_GCLK_IO1                      ((PIN_PC05K_GCLK_IO1 << 16) | MUX_PC05K_GCLK_IO1)
+#define PORT_PC05K_GCLK_IO1                        (_UINT32_(1) << 5)
+
+#define PIN_PD04K_GCLK_IO1                         _UINT32_(100)
+#define MUX_PD04K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PD04K_GCLK_IO1                      ((PIN_PD04K_GCLK_IO1 << 16) | MUX_PD04K_GCLK_IO1)
+#define PORT_PD04K_GCLK_IO1                        (_UINT32_(1) << 4)
+
+#define PIN_PC01K_GCLK_IO2                         _UINT32_(65)
+#define MUX_PC01K_GCLK_IO2                         _UINT32_(10)
+#define PINMUX_PC01K_GCLK_IO2                      ((PIN_PC01K_GCLK_IO2 << 16) | MUX_PC01K_GCLK_IO2)
+#define PORT_PC01K_GCLK_IO2                        (_UINT32_(1) << 1)
+
+#define PIN_PC02K_GCLK_IO3                         _UINT32_(66)
+#define MUX_PC02K_GCLK_IO3                         _UINT32_(10)
+#define PINMUX_PC02K_GCLK_IO3                      ((PIN_PC02K_GCLK_IO3 << 16) | MUX_PC02K_GCLK_IO3)
+#define PORT_PC02K_GCLK_IO3                        (_UINT32_(1) << 2)
+
+#define PIN_PC03K_GCLK_IO4                         _UINT32_(67)
+#define MUX_PC03K_GCLK_IO4                         _UINT32_(10)
+#define PINMUX_PC03K_GCLK_IO4                      ((PIN_PC03K_GCLK_IO4 << 16) | MUX_PC03K_GCLK_IO4)
+#define PORT_PC03K_GCLK_IO4                        (_UINT32_(1) << 3)
+
+#define PIN_PC04K_GCLK_IO5                         _UINT32_(68)
+#define MUX_PC04K_GCLK_IO5                         _UINT32_(10)
+#define PINMUX_PC04K_GCLK_IO5                      ((PIN_PC04K_GCLK_IO5 << 16) | MUX_PC04K_GCLK_IO5)
+#define PORT_PC04K_GCLK_IO5                        (_UINT32_(1) << 4)
+
+/* =================== PORT definition for PTC peripheral =================== */
+#define PIN_PD06P_PTC_DRV0                         _UINT32_(102)
+#define MUX_PD06P_PTC_DRV0                         _UINT32_(15)
+#define PINMUX_PD06P_PTC_DRV0                      ((PIN_PD06P_PTC_DRV0 << 16) | MUX_PD06P_PTC_DRV0)
+#define PORT_PD06P_PTC_DRV0                        (_UINT32_(1) << 6)
+
+#define PIN_PD07P_PTC_DRV1                         _UINT32_(103)
+#define MUX_PD07P_PTC_DRV1                         _UINT32_(15)
+#define PINMUX_PD07P_PTC_DRV1                      ((PIN_PD07P_PTC_DRV1 << 16) | MUX_PD07P_PTC_DRV1)
+#define PORT_PD07P_PTC_DRV1                        (_UINT32_(1) << 7)
+
+#define PIN_PD08P_PTC_DRV2                         _UINT32_(104)
+#define MUX_PD08P_PTC_DRV2                         _UINT32_(15)
+#define PINMUX_PD08P_PTC_DRV2                      ((PIN_PD08P_PTC_DRV2 << 16) | MUX_PD08P_PTC_DRV2)
+#define PORT_PD08P_PTC_DRV2                        (_UINT32_(1) << 8)
+
+#define PIN_PD09P_PTC_DRV3                         _UINT32_(105)
+#define MUX_PD09P_PTC_DRV3                         _UINT32_(15)
+#define PINMUX_PD09P_PTC_DRV3                      ((PIN_PD09P_PTC_DRV3 << 16) | MUX_PD09P_PTC_DRV3)
+#define PORT_PD09P_PTC_DRV3                        (_UINT32_(1) << 9)
+
+#define PIN_PA00P_PTC_DRV4                         _UINT32_(0) 
+#define MUX_PA00P_PTC_DRV4                         _UINT32_(15)
+#define PINMUX_PA00P_PTC_DRV4                      ((PIN_PA00P_PTC_DRV4 << 16) | MUX_PA00P_PTC_DRV4)
+#define PORT_PA00P_PTC_DRV4                        (_UINT32_(1) << 0)
+
+#define PIN_PA01P_PTC_DRV5                         _UINT32_(1) 
+#define MUX_PA01P_PTC_DRV5                         _UINT32_(15)
+#define PINMUX_PA01P_PTC_DRV5                      ((PIN_PA01P_PTC_DRV5 << 16) | MUX_PA01P_PTC_DRV5)
+#define PORT_PA01P_PTC_DRV5                        (_UINT32_(1) << 1)
+
+#define PIN_PA02P_PTC_DRV6                         _UINT32_(2) 
+#define MUX_PA02P_PTC_DRV6                         _UINT32_(15)
+#define PINMUX_PA02P_PTC_DRV6                      ((PIN_PA02P_PTC_DRV6 << 16) | MUX_PA02P_PTC_DRV6)
+#define PORT_PA02P_PTC_DRV6                        (_UINT32_(1) << 2)
+
+#define PIN_PA03P_PTC_DRV7                         _UINT32_(3) 
+#define MUX_PA03P_PTC_DRV7                         _UINT32_(15)
+#define PINMUX_PA03P_PTC_DRV7                      ((PIN_PA03P_PTC_DRV7 << 16) | MUX_PA03P_PTC_DRV7)
+#define PORT_PA03P_PTC_DRV7                        (_UINT32_(1) << 3)
+
+#define PIN_PA04P_PTC_DRV8                         _UINT32_(4) 
+#define MUX_PA04P_PTC_DRV8                         _UINT32_(15)
+#define PINMUX_PA04P_PTC_DRV8                      ((PIN_PA04P_PTC_DRV8 << 16) | MUX_PA04P_PTC_DRV8)
+#define PORT_PA04P_PTC_DRV8                        (_UINT32_(1) << 4)
+
+#define PIN_PA05P_PTC_DRV9                         _UINT32_(5) 
+#define MUX_PA05P_PTC_DRV9                         _UINT32_(15)
+#define PINMUX_PA05P_PTC_DRV9                      ((PIN_PA05P_PTC_DRV9 << 16) | MUX_PA05P_PTC_DRV9)
+#define PORT_PA05P_PTC_DRV9                        (_UINT32_(1) << 5)
+
+#define PIN_PA06P_PTC_DRV10                        _UINT32_(6) 
+#define MUX_PA06P_PTC_DRV10                        _UINT32_(15)
+#define PINMUX_PA06P_PTC_DRV10                     ((PIN_PA06P_PTC_DRV10 << 16) | MUX_PA06P_PTC_DRV10)
+#define PORT_PA06P_PTC_DRV10                       (_UINT32_(1) << 6)
+
+#define PIN_PA07P_PTC_DRV11                        _UINT32_(7) 
+#define MUX_PA07P_PTC_DRV11                        _UINT32_(15)
+#define PINMUX_PA07P_PTC_DRV11                     ((PIN_PA07P_PTC_DRV11 << 16) | MUX_PA07P_PTC_DRV11)
+#define PORT_PA07P_PTC_DRV11                       (_UINT32_(1) << 7)
+
+#define PIN_PA08P_PTC_DRV12                        _UINT32_(8) 
+#define MUX_PA08P_PTC_DRV12                        _UINT32_(15)
+#define PINMUX_PA08P_PTC_DRV12                     ((PIN_PA08P_PTC_DRV12 << 16) | MUX_PA08P_PTC_DRV12)
+#define PORT_PA08P_PTC_DRV12                       (_UINT32_(1) << 8)
+
+#define PIN_PA09P_PTC_DRV13                        _UINT32_(9) 
+#define MUX_PA09P_PTC_DRV13                        _UINT32_(15)
+#define PINMUX_PA09P_PTC_DRV13                     ((PIN_PA09P_PTC_DRV13 << 16) | MUX_PA09P_PTC_DRV13)
+#define PORT_PA09P_PTC_DRV13                       (_UINT32_(1) << 9)
+
+#define PIN_PB00P_PTC_DRV14                        _UINT32_(32)
+#define MUX_PB00P_PTC_DRV14                        _UINT32_(15)
+#define PINMUX_PB00P_PTC_DRV14                     ((PIN_PB00P_PTC_DRV14 << 16) | MUX_PB00P_PTC_DRV14)
+#define PORT_PB00P_PTC_DRV14                       (_UINT32_(1) << 0)
+
+#define PIN_PB03P_PTC_DRV15                        _UINT32_(35)
+#define MUX_PB03P_PTC_DRV15                        _UINT32_(15)
+#define PINMUX_PB03P_PTC_DRV15                     ((PIN_PB03P_PTC_DRV15 << 16) | MUX_PB03P_PTC_DRV15)
+#define PORT_PB03P_PTC_DRV15                       (_UINT32_(1) << 3)
+
+#define PIN_PB04P_PTC_DRV16                        _UINT32_(36)
+#define MUX_PB04P_PTC_DRV16                        _UINT32_(15)
+#define PINMUX_PB04P_PTC_DRV16                     ((PIN_PB04P_PTC_DRV16 << 16) | MUX_PB04P_PTC_DRV16)
+#define PORT_PB04P_PTC_DRV16                       (_UINT32_(1) << 4)
+
+#define PIN_PB05P_PTC_DRV17                        _UINT32_(37)
+#define MUX_PB05P_PTC_DRV17                        _UINT32_(15)
+#define PINMUX_PB05P_PTC_DRV17                     ((PIN_PB05P_PTC_DRV17 << 16) | MUX_PB05P_PTC_DRV17)
+#define PORT_PB05P_PTC_DRV17                       (_UINT32_(1) << 5)
+
+#define PIN_PB06P_PTC_DRV18                        _UINT32_(38)
+#define MUX_PB06P_PTC_DRV18                        _UINT32_(15)
+#define PINMUX_PB06P_PTC_DRV18                     ((PIN_PB06P_PTC_DRV18 << 16) | MUX_PB06P_PTC_DRV18)
+#define PORT_PB06P_PTC_DRV18                       (_UINT32_(1) << 6)
+
+#define PIN_PC00P_PTC_DRV19                        _UINT32_(64)
+#define MUX_PC00P_PTC_DRV19                        _UINT32_(15)
+#define PINMUX_PC00P_PTC_DRV19                     ((PIN_PC00P_PTC_DRV19 << 16) | MUX_PC00P_PTC_DRV19)
+#define PORT_PC00P_PTC_DRV19                       (_UINT32_(1) << 0)
+
+#define PIN_PC01P_PTC_DRV20                        _UINT32_(65)
+#define MUX_PC01P_PTC_DRV20                        _UINT32_(15)
+#define PINMUX_PC01P_PTC_DRV20                     ((PIN_PC01P_PTC_DRV20 << 16) | MUX_PC01P_PTC_DRV20)
+#define PORT_PC01P_PTC_DRV20                       (_UINT32_(1) << 1)
+
+#define PIN_PC02P_PTC_DRV21                        _UINT32_(66)
+#define MUX_PC02P_PTC_DRV21                        _UINT32_(15)
+#define PINMUX_PC02P_PTC_DRV21                     ((PIN_PC02P_PTC_DRV21 << 16) | MUX_PC02P_PTC_DRV21)
+#define PORT_PC02P_PTC_DRV21                       (_UINT32_(1) << 2)
+
+#define PIN_PC03P_PTC_ECI0                         _UINT32_(67)
+#define MUX_PC03P_PTC_ECI0                         _UINT32_(15)
+#define PINMUX_PC03P_PTC_ECI0                      ((PIN_PC03P_PTC_ECI0 << 16) | MUX_PC03P_PTC_ECI0)
+#define PORT_PC03P_PTC_ECI0                        (_UINT32_(1) << 3)
+
+#define PIN_PC04P_PTC_ECI1                         _UINT32_(68)
+#define MUX_PC04P_PTC_ECI1                         _UINT32_(15)
+#define PINMUX_PC04P_PTC_ECI1                      ((PIN_PC04P_PTC_ECI1 << 16) | MUX_PC04P_PTC_ECI1)
+#define PORT_PC04P_PTC_ECI1                        (_UINT32_(1) << 4)
+
+#define PIN_PD06P_PTC_PTCXY0                       _UINT32_(102)
+#define MUX_PD06P_PTC_PTCXY0                       _UINT32_(15)
+#define PINMUX_PD06P_PTC_PTCXY0                    ((PIN_PD06P_PTC_PTCXY0 << 16) | MUX_PD06P_PTC_PTCXY0)
+#define PORT_PD06P_PTC_PTCXY0                      (_UINT32_(1) << 6)
+
+#define PIN_PD07P_PTC_PTCXY1                       _UINT32_(103)
+#define MUX_PD07P_PTC_PTCXY1                       _UINT32_(15)
+#define PINMUX_PD07P_PTC_PTCXY1                    ((PIN_PD07P_PTC_PTCXY1 << 16) | MUX_PD07P_PTC_PTCXY1)
+#define PORT_PD07P_PTC_PTCXY1                      (_UINT32_(1) << 7)
+
+#define PIN_PD08P_PTC_PTCXY2                       _UINT32_(104)
+#define MUX_PD08P_PTC_PTCXY2                       _UINT32_(15)
+#define PINMUX_PD08P_PTC_PTCXY2                    ((PIN_PD08P_PTC_PTCXY2 << 16) | MUX_PD08P_PTC_PTCXY2)
+#define PORT_PD08P_PTC_PTCXY2                      (_UINT32_(1) << 8)
+
+#define PIN_PD09P_PTC_PTCXY3                       _UINT32_(105)
+#define MUX_PD09P_PTC_PTCXY3                       _UINT32_(15)
+#define PINMUX_PD09P_PTC_PTCXY3                    ((PIN_PD09P_PTC_PTCXY3 << 16) | MUX_PD09P_PTC_PTCXY3)
+#define PORT_PD09P_PTC_PTCXY3                      (_UINT32_(1) << 9)
+
+#define PIN_PA00P_PTC_PTCXY4                       _UINT32_(0) 
+#define MUX_PA00P_PTC_PTCXY4                       _UINT32_(15)
+#define PINMUX_PA00P_PTC_PTCXY4                    ((PIN_PA00P_PTC_PTCXY4 << 16) | MUX_PA00P_PTC_PTCXY4)
+#define PORT_PA00P_PTC_PTCXY4                      (_UINT32_(1) << 0)
+
+#define PIN_PA01P_PTC_PTCXY5                       _UINT32_(1) 
+#define MUX_PA01P_PTC_PTCXY5                       _UINT32_(15)
+#define PINMUX_PA01P_PTC_PTCXY5                    ((PIN_PA01P_PTC_PTCXY5 << 16) | MUX_PA01P_PTC_PTCXY5)
+#define PORT_PA01P_PTC_PTCXY5                      (_UINT32_(1) << 1)
+
+#define PIN_PA02P_PTC_PTCXY6                       _UINT32_(2) 
+#define MUX_PA02P_PTC_PTCXY6                       _UINT32_(15)
+#define PINMUX_PA02P_PTC_PTCXY6                    ((PIN_PA02P_PTC_PTCXY6 << 16) | MUX_PA02P_PTC_PTCXY6)
+#define PORT_PA02P_PTC_PTCXY6                      (_UINT32_(1) << 2)
+
+#define PIN_PA03P_PTC_PTCXY7                       _UINT32_(3) 
+#define MUX_PA03P_PTC_PTCXY7                       _UINT32_(15)
+#define PINMUX_PA03P_PTC_PTCXY7                    ((PIN_PA03P_PTC_PTCXY7 << 16) | MUX_PA03P_PTC_PTCXY7)
+#define PORT_PA03P_PTC_PTCXY7                      (_UINT32_(1) << 3)
+
+#define PIN_PA04P_PTC_PTCXY8                       _UINT32_(4) 
+#define MUX_PA04P_PTC_PTCXY8                       _UINT32_(15)
+#define PINMUX_PA04P_PTC_PTCXY8                    ((PIN_PA04P_PTC_PTCXY8 << 16) | MUX_PA04P_PTC_PTCXY8)
+#define PORT_PA04P_PTC_PTCXY8                      (_UINT32_(1) << 4)
+
+#define PIN_PA05P_PTC_PTCXY9                       _UINT32_(5) 
+#define MUX_PA05P_PTC_PTCXY9                       _UINT32_(15)
+#define PINMUX_PA05P_PTC_PTCXY9                    ((PIN_PA05P_PTC_PTCXY9 << 16) | MUX_PA05P_PTC_PTCXY9)
+#define PORT_PA05P_PTC_PTCXY9                      (_UINT32_(1) << 5)
+
+#define PIN_PA06P_PTC_PTCXY10                      _UINT32_(6) 
+#define MUX_PA06P_PTC_PTCXY10                      _UINT32_(15)
+#define PINMUX_PA06P_PTC_PTCXY10                   ((PIN_PA06P_PTC_PTCXY10 << 16) | MUX_PA06P_PTC_PTCXY10)
+#define PORT_PA06P_PTC_PTCXY10                     (_UINT32_(1) << 6)
+
+#define PIN_PA07P_PTC_PTCXY11                      _UINT32_(7) 
+#define MUX_PA07P_PTC_PTCXY11                      _UINT32_(15)
+#define PINMUX_PA07P_PTC_PTCXY11                   ((PIN_PA07P_PTC_PTCXY11 << 16) | MUX_PA07P_PTC_PTCXY11)
+#define PORT_PA07P_PTC_PTCXY11                     (_UINT32_(1) << 7)
+
+#define PIN_PA08P_PTC_PTCXY12                      _UINT32_(8) 
+#define MUX_PA08P_PTC_PTCXY12                      _UINT32_(15)
+#define PINMUX_PA08P_PTC_PTCXY12                   ((PIN_PA08P_PTC_PTCXY12 << 16) | MUX_PA08P_PTC_PTCXY12)
+#define PORT_PA08P_PTC_PTCXY12                     (_UINT32_(1) << 8)
+
+#define PIN_PA09P_PTC_PTCXY13                      _UINT32_(9) 
+#define MUX_PA09P_PTC_PTCXY13                      _UINT32_(15)
+#define PINMUX_PA09P_PTC_PTCXY13                   ((PIN_PA09P_PTC_PTCXY13 << 16) | MUX_PA09P_PTC_PTCXY13)
+#define PORT_PA09P_PTC_PTCXY13                     (_UINT32_(1) << 9)
+
+#define PIN_PB00P_PTC_PTCXY14                      _UINT32_(32)
+#define MUX_PB00P_PTC_PTCXY14                      _UINT32_(15)
+#define PINMUX_PB00P_PTC_PTCXY14                   ((PIN_PB00P_PTC_PTCXY14 << 16) | MUX_PB00P_PTC_PTCXY14)
+#define PORT_PB00P_PTC_PTCXY14                     (_UINT32_(1) << 0)
+
+#define PIN_PB03P_PTC_PTCXY15                      _UINT32_(35)
+#define MUX_PB03P_PTC_PTCXY15                      _UINT32_(15)
+#define PINMUX_PB03P_PTC_PTCXY15                   ((PIN_PB03P_PTC_PTCXY15 << 16) | MUX_PB03P_PTC_PTCXY15)
+#define PORT_PB03P_PTC_PTCXY15                     (_UINT32_(1) << 3)
+
+#define PIN_PB04P_PTC_PTCXY16                      _UINT32_(36)
+#define MUX_PB04P_PTC_PTCXY16                      _UINT32_(15)
+#define PINMUX_PB04P_PTC_PTCXY16                   ((PIN_PB04P_PTC_PTCXY16 << 16) | MUX_PB04P_PTC_PTCXY16)
+#define PORT_PB04P_PTC_PTCXY16                     (_UINT32_(1) << 4)
+
+#define PIN_PB05P_PTC_PTCXY17                      _UINT32_(37)
+#define MUX_PB05P_PTC_PTCXY17                      _UINT32_(15)
+#define PINMUX_PB05P_PTC_PTCXY17                   ((PIN_PB05P_PTC_PTCXY17 << 16) | MUX_PB05P_PTC_PTCXY17)
+#define PORT_PB05P_PTC_PTCXY17                     (_UINT32_(1) << 5)
+
+#define PIN_PB06P_PTC_PTCXY18                      _UINT32_(38)
+#define MUX_PB06P_PTC_PTCXY18                      _UINT32_(15)
+#define PINMUX_PB06P_PTC_PTCXY18                   ((PIN_PB06P_PTC_PTCXY18 << 16) | MUX_PB06P_PTC_PTCXY18)
+#define PORT_PB06P_PTC_PTCXY18                     (_UINT32_(1) << 6)
+
+#define PIN_PC00P_PTC_PTCXY19                      _UINT32_(64)
+#define MUX_PC00P_PTC_PTCXY19                      _UINT32_(15)
+#define PINMUX_PC00P_PTC_PTCXY19                   ((PIN_PC00P_PTC_PTCXY19 << 16) | MUX_PC00P_PTC_PTCXY19)
+#define PORT_PC00P_PTC_PTCXY19                     (_UINT32_(1) << 0)
+
+#define PIN_PC01P_PTC_PTCXY20                      _UINT32_(65)
+#define MUX_PC01P_PTC_PTCXY20                      _UINT32_(15)
+#define PINMUX_PC01P_PTC_PTCXY20                   ((PIN_PC01P_PTC_PTCXY20 << 16) | MUX_PC01P_PTC_PTCXY20)
+#define PORT_PC01P_PTC_PTCXY20                     (_UINT32_(1) << 1)
+
+#define PIN_PC02P_PTC_PTCXY21                      _UINT32_(66)
+#define MUX_PC02P_PTC_PTCXY21                      _UINT32_(15)
+#define PINMUX_PC02P_PTC_PTCXY21                   ((PIN_PC02P_PTC_PTCXY21 << 16) | MUX_PC02P_PTC_PTCXY21)
+#define PORT_PC02P_PTC_PTCXY21                     (_UINT32_(1) << 2)
+
+/* ================= PORT definition for SERCOM0 peripheral ================= */
+#define PIN_PC00D_SERCOM0_PAD0                     _UINT32_(64)
+#define MUX_PC00D_SERCOM0_PAD0                     _UINT32_(3) 
+#define PINMUX_PC00D_SERCOM0_PAD0                  ((PIN_PC00D_SERCOM0_PAD0 << 16) | MUX_PC00D_SERCOM0_PAD0)
+#define PORT_PC00D_SERCOM0_PAD0                    (_UINT32_(1) << 0)
+
+#define PIN_PC01D_SERCOM0_PAD1                     _UINT32_(65)
+#define MUX_PC01D_SERCOM0_PAD1                     _UINT32_(3) 
+#define PINMUX_PC01D_SERCOM0_PAD1                  ((PIN_PC01D_SERCOM0_PAD1 << 16) | MUX_PC01D_SERCOM0_PAD1)
+#define PORT_PC01D_SERCOM0_PAD1                    (_UINT32_(1) << 1)
+
+#define PIN_PC02D_SERCOM0_PAD2                     _UINT32_(66)
+#define MUX_PC02D_SERCOM0_PAD2                     _UINT32_(3) 
+#define PINMUX_PC02D_SERCOM0_PAD2                  ((PIN_PC02D_SERCOM0_PAD2 << 16) | MUX_PC02D_SERCOM0_PAD2)
+#define PORT_PC02D_SERCOM0_PAD2                    (_UINT32_(1) << 2)
+
+#define PIN_PC03D_SERCOM0_PAD3                     _UINT32_(67)
+#define MUX_PC03D_SERCOM0_PAD3                     _UINT32_(3) 
+#define PINMUX_PC03D_SERCOM0_PAD3                  ((PIN_PC03D_SERCOM0_PAD3 << 16) | MUX_PC03D_SERCOM0_PAD3)
+#define PORT_PC03D_SERCOM0_PAD3                    (_UINT32_(1) << 3)
+
+/* ================= PORT definition for SERCOM1 peripheral ================= */
+#define PIN_PD01D_SERCOM1_PAD0                     _UINT32_(97)
+#define MUX_PD01D_SERCOM1_PAD0                     _UINT32_(3) 
+#define PINMUX_PD01D_SERCOM1_PAD0                  ((PIN_PD01D_SERCOM1_PAD0 << 16) | MUX_PD01D_SERCOM1_PAD0)
+#define PORT_PD01D_SERCOM1_PAD0                    (_UINT32_(1) << 1)
+
+#define PIN_PD00D_SERCOM1_PAD1                     _UINT32_(96)
+#define MUX_PD00D_SERCOM1_PAD1                     _UINT32_(3) 
+#define PINMUX_PD00D_SERCOM1_PAD1                  ((PIN_PD00D_SERCOM1_PAD1 << 16) | MUX_PD00D_SERCOM1_PAD1)
+#define PORT_PD00D_SERCOM1_PAD1                    (_UINT32_(1) << 0)
+
+#define PIN_PC06D_SERCOM1_PAD2                     _UINT32_(70)
+#define MUX_PC06D_SERCOM1_PAD2                     _UINT32_(3) 
+#define PINMUX_PC06D_SERCOM1_PAD2                  ((PIN_PC06D_SERCOM1_PAD2 << 16) | MUX_PC06D_SERCOM1_PAD2)
+#define PORT_PC06D_SERCOM1_PAD2                    (_UINT32_(1) << 6)
+
+#define PIN_PC05D_SERCOM1_PAD3                     _UINT32_(69)
+#define MUX_PC05D_SERCOM1_PAD3                     _UINT32_(3) 
+#define PINMUX_PC05D_SERCOM1_PAD3                  ((PIN_PC05D_SERCOM1_PAD3 << 16) | MUX_PC05D_SERCOM1_PAD3)
+#define PORT_PC05D_SERCOM1_PAD3                    (_UINT32_(1) << 5)
+
+/* ================= PORT definition for SERCOM2 peripheral ================= */
+#define PIN_PC04D_SERCOM2_PAD0                     _UINT32_(68)
+#define MUX_PC04D_SERCOM2_PAD0                     _UINT32_(3) 
+#define PINMUX_PC04D_SERCOM2_PAD0                  ((PIN_PC04D_SERCOM2_PAD0 << 16) | MUX_PC04D_SERCOM2_PAD0)
+#define PORT_PC04D_SERCOM2_PAD0                    (_UINT32_(1) << 4)
+
+#define PIN_PD06D_SERCOM2_PAD1                     _UINT32_(102)
+#define MUX_PD06D_SERCOM2_PAD1                     _UINT32_(3) 
+#define PINMUX_PD06D_SERCOM2_PAD1                  ((PIN_PD06D_SERCOM2_PAD1 << 16) | MUX_PD06D_SERCOM2_PAD1)
+#define PORT_PD06D_SERCOM2_PAD1                    (_UINT32_(1) << 6)
+
+#define PIN_PD07D_SERCOM2_PAD2                     _UINT32_(103)
+#define MUX_PD07D_SERCOM2_PAD2                     _UINT32_(3) 
+#define PINMUX_PD07D_SERCOM2_PAD2                  ((PIN_PD07D_SERCOM2_PAD2 << 16) | MUX_PD07D_SERCOM2_PAD2)
+#define PORT_PD07D_SERCOM2_PAD2                    (_UINT32_(1) << 7)
+
+#define PIN_PD08D_SERCOM2_PAD3                     _UINT32_(104)
+#define MUX_PD08D_SERCOM2_PAD3                     _UINT32_(3) 
+#define PINMUX_PD08D_SERCOM2_PAD3                  ((PIN_PD08D_SERCOM2_PAD3 << 16) | MUX_PD08D_SERCOM2_PAD3)
+#define PORT_PD08D_SERCOM2_PAD3                    (_UINT32_(1) << 8)
+
+/* ================= PORT definition for SERCOM3 peripheral ================= */
+#define PIN_PD09D_SERCOM3_PAD0                     _UINT32_(105)
+#define MUX_PD09D_SERCOM3_PAD0                     _UINT32_(3) 
+#define PINMUX_PD09D_SERCOM3_PAD0                  ((PIN_PD09D_SERCOM3_PAD0 << 16) | MUX_PD09D_SERCOM3_PAD0)
+#define PORT_PD09D_SERCOM3_PAD0                    (_UINT32_(1) << 9)
+
+#define PIN_PA00D_SERCOM3_PAD1                     _UINT32_(0) 
+#define MUX_PA00D_SERCOM3_PAD1                     _UINT32_(3) 
+#define PINMUX_PA00D_SERCOM3_PAD1                  ((PIN_PA00D_SERCOM3_PAD1 << 16) | MUX_PA00D_SERCOM3_PAD1)
+#define PORT_PA00D_SERCOM3_PAD1                    (_UINT32_(1) << 0)
+
+#define PIN_PA01D_SERCOM3_PAD2                     _UINT32_(1) 
+#define MUX_PA01D_SERCOM3_PAD2                     _UINT32_(3) 
+#define PINMUX_PA01D_SERCOM3_PAD2                  ((PIN_PA01D_SERCOM3_PAD2 << 16) | MUX_PA01D_SERCOM3_PAD2)
+#define PORT_PA01D_SERCOM3_PAD2                    (_UINT32_(1) << 1)
+
+#define PIN_PA02D_SERCOM3_PAD3                     _UINT32_(2) 
+#define MUX_PA02D_SERCOM3_PAD3                     _UINT32_(3) 
+#define PINMUX_PA02D_SERCOM3_PAD3                  ((PIN_PA02D_SERCOM3_PAD3 << 16) | MUX_PA02D_SERCOM3_PAD3)
+#define PORT_PA02D_SERCOM3_PAD3                    (_UINT32_(1) << 2)
+
+/* ================= PORT definition for SERCOM4 peripheral ================= */
+#define PIN_PA03D_SERCOM4_PAD0                     _UINT32_(3) 
+#define MUX_PA03D_SERCOM4_PAD0                     _UINT32_(3) 
+#define PINMUX_PA03D_SERCOM4_PAD0                  ((PIN_PA03D_SERCOM4_PAD0 << 16) | MUX_PA03D_SERCOM4_PAD0)
+#define PORT_PA03D_SERCOM4_PAD0                    (_UINT32_(1) << 3)
+
+#define PIN_PA04D_SERCOM4_PAD1                     _UINT32_(4) 
+#define MUX_PA04D_SERCOM4_PAD1                     _UINT32_(3) 
+#define PINMUX_PA04D_SERCOM4_PAD1                  ((PIN_PA04D_SERCOM4_PAD1 << 16) | MUX_PA04D_SERCOM4_PAD1)
+#define PORT_PA04D_SERCOM4_PAD1                    (_UINT32_(1) << 4)
+
+#define PIN_PA05D_SERCOM4_PAD2                     _UINT32_(5) 
+#define MUX_PA05D_SERCOM4_PAD2                     _UINT32_(3) 
+#define PINMUX_PA05D_SERCOM4_PAD2                  ((PIN_PA05D_SERCOM4_PAD2 << 16) | MUX_PA05D_SERCOM4_PAD2)
+#define PORT_PA05D_SERCOM4_PAD2                    (_UINT32_(1) << 5)
+
+#define PIN_PA06D_SERCOM4_PAD3                     _UINT32_(6) 
+#define MUX_PA06D_SERCOM4_PAD3                     _UINT32_(3) 
+#define PINMUX_PA06D_SERCOM4_PAD3                  ((PIN_PA06D_SERCOM4_PAD3 << 16) | MUX_PA06D_SERCOM4_PAD3)
+#define PORT_PA06D_SERCOM4_PAD3                    (_UINT32_(1) << 6)
+
+/* ================= PORT definition for SERCOM5 peripheral ================= */
+#define PIN_PB03D_SERCOM5_PAD0                     _UINT32_(35)
+#define MUX_PB03D_SERCOM5_PAD0                     _UINT32_(3) 
+#define PINMUX_PB03D_SERCOM5_PAD0                  ((PIN_PB03D_SERCOM5_PAD0 << 16) | MUX_PB03D_SERCOM5_PAD0)
+#define PORT_PB03D_SERCOM5_PAD0                    (_UINT32_(1) << 3)
+
+#define PIN_PB04D_SERCOM5_PAD1                     _UINT32_(36)
+#define MUX_PB04D_SERCOM5_PAD1                     _UINT32_(3) 
+#define PINMUX_PB04D_SERCOM5_PAD1                  ((PIN_PB04D_SERCOM5_PAD1 << 16) | MUX_PB04D_SERCOM5_PAD1)
+#define PORT_PB04D_SERCOM5_PAD1                    (_UINT32_(1) << 4)
+
+#define PIN_PB05D_SERCOM5_PAD2                     _UINT32_(37)
+#define MUX_PB05D_SERCOM5_PAD2                     _UINT32_(3) 
+#define PINMUX_PB05D_SERCOM5_PAD2                  ((PIN_PB05D_SERCOM5_PAD2 << 16) | MUX_PB05D_SERCOM5_PAD2)
+#define PORT_PB05D_SERCOM5_PAD2                    (_UINT32_(1) << 5)
+
+#define PIN_PB06D_SERCOM5_PAD3                     _UINT32_(38)
+#define MUX_PB06D_SERCOM5_PAD3                     _UINT32_(3) 
+#define PINMUX_PB06D_SERCOM5_PAD3                  ((PIN_PB06D_SERCOM5_PAD3 << 16) | MUX_PB06D_SERCOM5_PAD3)
+#define PORT_PB06D_SERCOM5_PAD3                    (_UINT32_(1) << 6)
+
+/* ================== PORT definition for TCC0 peripheral =================== */
+#define PIN_PC00F_TCC0_WO0                         _UINT32_(64)
+#define MUX_PC00F_TCC0_WO0                         _UINT32_(5) 
+#define PINMUX_PC00F_TCC0_WO0                      ((PIN_PC00F_TCC0_WO0 << 16) | MUX_PC00F_TCC0_WO0)
+#define PORT_PC00F_TCC0_WO0                        (_UINT32_(1) << 0)
+
+#define PIN_PC01F_TCC0_WO1                         _UINT32_(65)
+#define MUX_PC01F_TCC0_WO1                         _UINT32_(5) 
+#define PINMUX_PC01F_TCC0_WO1                      ((PIN_PC01F_TCC0_WO1 << 16) | MUX_PC01F_TCC0_WO1)
+#define PORT_PC01F_TCC0_WO1                        (_UINT32_(1) << 1)
+
+/* ================== PORT definition for TCC1 peripheral =================== */
+#define PIN_PC02F_TCC1_WO0                         _UINT32_(66)
+#define MUX_PC02F_TCC1_WO0                         _UINT32_(5) 
+#define PINMUX_PC02F_TCC1_WO0                      ((PIN_PC02F_TCC1_WO0 << 16) | MUX_PC02F_TCC1_WO0)
+#define PORT_PC02F_TCC1_WO0                        (_UINT32_(1) << 2)
+
+#define PIN_PC03F_TCC1_WO1                         _UINT32_(67)
+#define MUX_PC03F_TCC1_WO1                         _UINT32_(5) 
+#define PINMUX_PC03F_TCC1_WO1                      ((PIN_PC03F_TCC1_WO1 << 16) | MUX_PC03F_TCC1_WO1)
+#define PORT_PC03F_TCC1_WO1                        (_UINT32_(1) << 3)
+
+/* ================== PORT definition for TCC2 peripheral =================== */
+#define PIN_PC04F_TCC2_WO0                         _UINT32_(68)
+#define MUX_PC04F_TCC2_WO0                         _UINT32_(5) 
+#define PINMUX_PC04F_TCC2_WO0                      ((PIN_PC04F_TCC2_WO0 << 16) | MUX_PC04F_TCC2_WO0)
+#define PORT_PC04F_TCC2_WO0                        (_UINT32_(1) << 4)
+
+#define PIN_PC05F_TCC2_WO1                         _UINT32_(69)
+#define MUX_PC05F_TCC2_WO1                         _UINT32_(5) 
+#define PINMUX_PC05F_TCC2_WO1                      ((PIN_PC05F_TCC2_WO1 << 16) | MUX_PC05F_TCC2_WO1)
+#define PORT_PC05F_TCC2_WO1                        (_UINT32_(1) << 5)
+
+/* ================== PORT definition for TCC3 peripheral =================== */
+#define PIN_PD00F_TCC3_WO0                         _UINT32_(96)
+#define MUX_PD00F_TCC3_WO0                         _UINT32_(5) 
+#define PINMUX_PD00F_TCC3_WO0                      ((PIN_PD00F_TCC3_WO0 << 16) | MUX_PD00F_TCC3_WO0)
+#define PORT_PD00F_TCC3_WO0                        (_UINT32_(1) << 0)
+
+#define PIN_PD01F_TCC3_WO1                         _UINT32_(97)
+#define MUX_PD01F_TCC3_WO1                         _UINT32_(5) 
+#define PINMUX_PD01F_TCC3_WO1                      ((PIN_PD01F_TCC3_WO1 << 16) | MUX_PD01F_TCC3_WO1)
+#define PORT_PD01F_TCC3_WO1                        (_UINT32_(1) << 1)
+
+/* ================== PORT definition for TCC4 peripheral =================== */
+#define PIN_PD07F_TCC4_WO0                         _UINT32_(103)
+#define MUX_PD07F_TCC4_WO0                         _UINT32_(5) 
+#define PINMUX_PD07F_TCC4_WO0                      ((PIN_PD07F_TCC4_WO0 << 16) | MUX_PD07F_TCC4_WO0)
+#define PORT_PD07F_TCC4_WO0                        (_UINT32_(1) << 7)
+
+#define PIN_PD08F_TCC4_WO1                         _UINT32_(104)
+#define MUX_PD08F_TCC4_WO1                         _UINT32_(5) 
+#define PINMUX_PD08F_TCC4_WO1                      ((PIN_PD08F_TCC4_WO1 << 16) | MUX_PD08F_TCC4_WO1)
+#define PORT_PD08F_TCC4_WO1                        (_UINT32_(1) << 8)
+
+/* ================== PORT definition for TCC5 peripheral =================== */
+#define PIN_PD09F_TCC5_WO0                         _UINT32_(105)
+#define MUX_PD09F_TCC5_WO0                         _UINT32_(5) 
+#define PINMUX_PD09F_TCC5_WO0                      ((PIN_PD09F_TCC5_WO0 << 16) | MUX_PD09F_TCC5_WO0)
+#define PORT_PD09F_TCC5_WO0                        (_UINT32_(1) << 9)
+
+#define PIN_PA00F_TCC5_WO1                         _UINT32_(0) 
+#define MUX_PA00F_TCC5_WO1                         _UINT32_(5) 
+#define PINMUX_PA00F_TCC5_WO1                      ((PIN_PA00F_TCC5_WO1 << 16) | MUX_PA00F_TCC5_WO1)
+#define PORT_PA00F_TCC5_WO1                        (_UINT32_(1) << 0)
+
+/* ================== PORT definition for TCC6 peripheral =================== */
+#define PIN_PA01F_TCC6_WO0                         _UINT32_(1) 
+#define MUX_PA01F_TCC6_WO0                         _UINT32_(5) 
+#define PINMUX_PA01F_TCC6_WO0                      ((PIN_PA01F_TCC6_WO0 << 16) | MUX_PA01F_TCC6_WO0)
+#define PORT_PA01F_TCC6_WO0                        (_UINT32_(1) << 1)
+
+#define PIN_PA02F_TCC6_WO1                         _UINT32_(2) 
+#define MUX_PA02F_TCC6_WO1                         _UINT32_(5) 
+#define PINMUX_PA02F_TCC6_WO1                      ((PIN_PA02F_TCC6_WO1 << 16) | MUX_PA02F_TCC6_WO1)
+#define PORT_PA02F_TCC6_WO1                        (_UINT32_(1) << 2)
+
+/* =================== PORT definition for USB peripheral =================== */
+#define PIN_PD01H_USB_SOF                          _UINT32_(97)
+#define MUX_PD01H_USB_SOF                          _UINT32_(7) 
+#define PINMUX_PD01H_USB_SOF                       ((PIN_PD01H_USB_SOF << 16) | MUX_PD01H_USB_SOF)
+#define PORT_PD01H_USB_SOF                         (_UINT32_(1) << 1)
+
+#define PIN_PD02H_USB_USBDM                        _UINT32_(98)
+#define MUX_PD02H_USB_USBDM                        _UINT32_(7) 
+#define PINMUX_PD02H_USB_USBDM                     ((PIN_PD02H_USB_USBDM << 16) | MUX_PD02H_USB_USBDM)
+#define PORT_PD02H_USB_USBDM                       (_UINT32_(1) << 2)
+
+#define PIN_PD03H_USB_USBDP                        _UINT32_(99)
+#define MUX_PD03H_USB_USBDP                        _UINT32_(7) 
+#define PINMUX_PD03H_USB_USBDP                     ((PIN_PD03H_USB_USBDP << 16) | MUX_PD03H_USB_USBDP)
+#define PORT_PD03H_USB_USBDP                       (_UINT32_(1) << 3)
+
+
+
+#endif /* _PIC32CM5112GC00048_GPIO_H_ */
+
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pio/pic32cm5112gc00064.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pio/pic32cm5112gc00064.h
new file mode 100644
index 00000000..7bf949dd
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pio/pic32cm5112gc00064.h
@@ -0,0 +1,1435 @@
+/*
+ * Peripheral I/O description for PIC32CM5112GC00064
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:48Z  */
+#ifndef _PIC32CM5112GC00064_GPIO_H_
+#define _PIC32CM5112GC00064_GPIO_H_
+
+/* ======================= Peripheral I/O pin numbers ======================= */
+#define PIN_PA00                    (    0)  /* Pin Number for PA00 */
+#define PIN_PA01                    (    1)  /* Pin Number for PA01 */
+#define PIN_PA02                    (    2)  /* Pin Number for PA02 */
+#define PIN_PA03                    (    3)  /* Pin Number for PA03 */
+#define PIN_PA04                    (    4)  /* Pin Number for PA04 */
+#define PIN_PA05                    (    5)  /* Pin Number for PA05 */
+#define PIN_PA06                    (    6)  /* Pin Number for PA06 */
+#define PIN_PA07                    (    7)  /* Pin Number for PA07 */
+#define PIN_PA08                    (    8)  /* Pin Number for PA08 */
+#define PIN_PA09                    (    9)  /* Pin Number for PA09 */
+#define PIN_PA10                    (   10)  /* Pin Number for PA10 */
+#define PIN_PA11                    (   11)  /* Pin Number for PA11 */
+#define PIN_PA12                    (   12)  /* Pin Number for PA12 */
+#define PIN_PA13                    (   13)  /* Pin Number for PA13 */
+#define PIN_PB00                    (   32)  /* Pin Number for PB00 */
+#define PIN_PB01                    (   33)  /* Pin Number for PB01 */
+#define PIN_PB02                    (   34)  /* Pin Number for PB02 */
+#define PIN_PB03                    (   35)  /* Pin Number for PB03 */
+#define PIN_PB04                    (   36)  /* Pin Number for PB04 */
+#define PIN_PB05                    (   37)  /* Pin Number for PB05 */
+#define PIN_PB06                    (   38)  /* Pin Number for PB06 */
+#define PIN_PB07                    (   39)  /* Pin Number for PB07 */
+#define PIN_PB08                    (   40)  /* Pin Number for PB08 */
+#define PIN_PB09                    (   41)  /* Pin Number for PB09 */
+#define PIN_PB10                    (   42)  /* Pin Number for PB10 */
+#define PIN_PC00                    (   64)  /* Pin Number for PC00 */
+#define PIN_PC01                    (   65)  /* Pin Number for PC01 */
+#define PIN_PC02                    (   66)  /* Pin Number for PC02 */
+#define PIN_PC03                    (   67)  /* Pin Number for PC03 */
+#define PIN_PC04                    (   68)  /* Pin Number for PC04 */
+#define PIN_PC05                    (   69)  /* Pin Number for PC05 */
+#define PIN_PC06                    (   70)  /* Pin Number for PC06 */
+#define PIN_PC07                    (   71)  /* Pin Number for PC07 */
+#define PIN_PC08                    (   72)  /* Pin Number for PC08 */
+#define PIN_PC09                    (   73)  /* Pin Number for PC09 */
+#define PIN_PC10                    (   74)  /* Pin Number for PC10 */
+#define PIN_PD00                    (   96)  /* Pin Number for PD00 */
+#define PIN_PD01                    (   97)  /* Pin Number for PD01 */
+#define PIN_PD02                    (   98)  /* Pin Number for PD02 */
+#define PIN_PD03                    (   99)  /* Pin Number for PD03 */
+#define PIN_PD04                    (  100)  /* Pin Number for PD04 */
+#define PIN_PD05                    (  101)  /* Pin Number for PD05 */
+#define PIN_PD06                    (  102)  /* Pin Number for PD06 */
+#define PIN_PD07                    (  103)  /* Pin Number for PD07 */
+#define PIN_PD08                    (  104)  /* Pin Number for PD08 */
+#define PIN_PD09                    (  105)  /* Pin Number for PD09 */
+#define PIN_PD10                    (  106)  /* Pin Number for PD10 */
+#define PIN_PD11                    (  107)  /* Pin Number for PD11 */
+#define PIN_PD12                    (  108)  /* Pin Number for PD12 */
+#define PIN_PD13                    (  109)  /* Pin Number for PD13 */
+
+/* ========================== Peripheral I/O masks ========================== */
+#define PORT_PA00                   (_UINT32_(1) << 0) /* PORT mask for PA00 */
+#define PORT_PA01                   (_UINT32_(1) << 1) /* PORT mask for PA01 */
+#define PORT_PA02                   (_UINT32_(1) << 2) /* PORT mask for PA02 */
+#define PORT_PA03                   (_UINT32_(1) << 3) /* PORT mask for PA03 */
+#define PORT_PA04                   (_UINT32_(1) << 4) /* PORT mask for PA04 */
+#define PORT_PA05                   (_UINT32_(1) << 5) /* PORT mask for PA05 */
+#define PORT_PA06                   (_UINT32_(1) << 6) /* PORT mask for PA06 */
+#define PORT_PA07                   (_UINT32_(1) << 7) /* PORT mask for PA07 */
+#define PORT_PA08                   (_UINT32_(1) << 8) /* PORT mask for PA08 */
+#define PORT_PA09                   (_UINT32_(1) << 9) /* PORT mask for PA09 */
+#define PORT_PA10                   (_UINT32_(1) << 10) /* PORT mask for PA10 */
+#define PORT_PA11                   (_UINT32_(1) << 11) /* PORT mask for PA11 */
+#define PORT_PA12                   (_UINT32_(1) << 12) /* PORT mask for PA12 */
+#define PORT_PA13                   (_UINT32_(1) << 13) /* PORT mask for PA13 */
+#define PORT_PB00                   (_UINT32_(1) << 0) /* PORT mask for PB00 */
+#define PORT_PB01                   (_UINT32_(1) << 1) /* PORT mask for PB01 */
+#define PORT_PB02                   (_UINT32_(1) << 2) /* PORT mask for PB02 */
+#define PORT_PB03                   (_UINT32_(1) << 3) /* PORT mask for PB03 */
+#define PORT_PB04                   (_UINT32_(1) << 4) /* PORT mask for PB04 */
+#define PORT_PB05                   (_UINT32_(1) << 5) /* PORT mask for PB05 */
+#define PORT_PB06                   (_UINT32_(1) << 6) /* PORT mask for PB06 */
+#define PORT_PB07                   (_UINT32_(1) << 7) /* PORT mask for PB07 */
+#define PORT_PB08                   (_UINT32_(1) << 8) /* PORT mask for PB08 */
+#define PORT_PB09                   (_UINT32_(1) << 9) /* PORT mask for PB09 */
+#define PORT_PB10                   (_UINT32_(1) << 10) /* PORT mask for PB10 */
+#define PORT_PC00                   (_UINT32_(1) << 0) /* PORT mask for PC00 */
+#define PORT_PC01                   (_UINT32_(1) << 1) /* PORT mask for PC01 */
+#define PORT_PC02                   (_UINT32_(1) << 2) /* PORT mask for PC02 */
+#define PORT_PC03                   (_UINT32_(1) << 3) /* PORT mask for PC03 */
+#define PORT_PC04                   (_UINT32_(1) << 4) /* PORT mask for PC04 */
+#define PORT_PC05                   (_UINT32_(1) << 5) /* PORT mask for PC05 */
+#define PORT_PC06                   (_UINT32_(1) << 6) /* PORT mask for PC06 */
+#define PORT_PC07                   (_UINT32_(1) << 7) /* PORT mask for PC07 */
+#define PORT_PC08                   (_UINT32_(1) << 8) /* PORT mask for PC08 */
+#define PORT_PC09                   (_UINT32_(1) << 9) /* PORT mask for PC09 */
+#define PORT_PC10                   (_UINT32_(1) << 10) /* PORT mask for PC10 */
+#define PORT_PD00                   (_UINT32_(1) << 0) /* PORT mask for PD00 */
+#define PORT_PD01                   (_UINT32_(1) << 1) /* PORT mask for PD01 */
+#define PORT_PD02                   (_UINT32_(1) << 2) /* PORT mask for PD02 */
+#define PORT_PD03                   (_UINT32_(1) << 3) /* PORT mask for PD03 */
+#define PORT_PD04                   (_UINT32_(1) << 4) /* PORT mask for PD04 */
+#define PORT_PD05                   (_UINT32_(1) << 5) /* PORT mask for PD05 */
+#define PORT_PD06                   (_UINT32_(1) << 6) /* PORT mask for PD06 */
+#define PORT_PD07                   (_UINT32_(1) << 7) /* PORT mask for PD07 */
+#define PORT_PD08                   (_UINT32_(1) << 8) /* PORT mask for PD08 */
+#define PORT_PD09                   (_UINT32_(1) << 9) /* PORT mask for PD09 */
+#define PORT_PD10                   (_UINT32_(1) << 10) /* PORT mask for PD10 */
+#define PORT_PD11                   (_UINT32_(1) << 11) /* PORT mask for PD11 */
+#define PORT_PD12                   (_UINT32_(1) << 12) /* PORT mask for PD12 */
+#define PORT_PD13                   (_UINT32_(1) << 13) /* PORT mask for PD13 */
+
+/* =================== PORT definition for AC peripheral ==================== */
+#define PIN_PA07B_AC_AIN0                          _UINT32_(7) 
+#define MUX_PA07B_AC_AIN0                          _UINT32_(1) 
+#define PINMUX_PA07B_AC_AIN0                       ((PIN_PA07B_AC_AIN0 << 16) | MUX_PA07B_AC_AIN0)
+#define PORT_PA07B_AC_AIN0                         (_UINT32_(1) << 7)
+
+#define PIN_PA08B_AC_AIN1                          _UINT32_(8) 
+#define MUX_PA08B_AC_AIN1                          _UINT32_(1) 
+#define PINMUX_PA08B_AC_AIN1                       ((PIN_PA08B_AC_AIN1 << 16) | MUX_PA08B_AC_AIN1)
+#define PORT_PA08B_AC_AIN1                         (_UINT32_(1) << 8)
+
+#define PIN_PB00B_AC_AIN2                          _UINT32_(32)
+#define MUX_PB00B_AC_AIN2                          _UINT32_(1) 
+#define PINMUX_PB00B_AC_AIN2                       ((PIN_PB00B_AC_AIN2 << 16) | MUX_PB00B_AC_AIN2)
+#define PORT_PB00B_AC_AIN2                         (_UINT32_(1) << 0)
+
+#define PIN_PB03B_AC_AIN3                          _UINT32_(35)
+#define MUX_PB03B_AC_AIN3                          _UINT32_(1) 
+#define PINMUX_PB03B_AC_AIN3                       ((PIN_PB03B_AC_AIN3 << 16) | MUX_PB03B_AC_AIN3)
+#define PORT_PB03B_AC_AIN3                         (_UINT32_(1) << 3)
+
+#define PIN_PA01B_AC_CMP0                          _UINT32_(1) 
+#define MUX_PA01B_AC_CMP0                          _UINT32_(1) 
+#define PINMUX_PA01B_AC_CMP0                       ((PIN_PA01B_AC_CMP0 << 16) | MUX_PA01B_AC_CMP0)
+#define PORT_PA01B_AC_CMP0                         (_UINT32_(1) << 1)
+
+#define PIN_PA13B_AC_CMP0                          _UINT32_(13)
+#define MUX_PA13B_AC_CMP0                          _UINT32_(1) 
+#define PINMUX_PA13B_AC_CMP0                       ((PIN_PA13B_AC_CMP0 << 16) | MUX_PA13B_AC_CMP0)
+#define PORT_PA13B_AC_CMP0                         (_UINT32_(1) << 13)
+
+#define PIN_PA02B_AC_CMP1                          _UINT32_(2) 
+#define MUX_PA02B_AC_CMP1                          _UINT32_(1) 
+#define PINMUX_PA02B_AC_CMP1                       ((PIN_PA02B_AC_CMP1 << 16) | MUX_PA02B_AC_CMP1)
+#define PORT_PA02B_AC_CMP1                         (_UINT32_(1) << 2)
+
+#define PIN_PB07B_AC_CMP1                          _UINT32_(39)
+#define MUX_PB07B_AC_CMP1                          _UINT32_(1) 
+#define PINMUX_PB07B_AC_CMP1                       ((PIN_PB07B_AC_CMP1 << 16) | MUX_PB07B_AC_CMP1)
+#define PORT_PB07B_AC_CMP1                         (_UINT32_(1) << 7)
+
+/* =================== PORT definition for ADC peripheral =================== */
+#define PIN_PA03B_ADC_ADC0_AIN0                    _UINT32_(3) 
+#define MUX_PA03B_ADC_ADC0_AIN0                    _UINT32_(1) 
+#define PINMUX_PA03B_ADC_ADC0_AIN0                 ((PIN_PA03B_ADC_ADC0_AIN0 << 16) | MUX_PA03B_ADC_ADC0_AIN0)
+#define PORT_PA03B_ADC_ADC0_AIN0                   (_UINT32_(1) << 3)
+
+#define PIN_PA04B_ADC_ADC0_AIN1                    _UINT32_(4) 
+#define MUX_PA04B_ADC_ADC0_AIN1                    _UINT32_(1) 
+#define PINMUX_PA04B_ADC_ADC0_AIN1                 ((PIN_PA04B_ADC_ADC0_AIN1 << 16) | MUX_PA04B_ADC_ADC0_AIN1)
+#define PORT_PA04B_ADC_ADC0_AIN1                   (_UINT32_(1) << 4)
+
+#define PIN_PA05B_ADC_ADC0_AIN2                    _UINT32_(5) 
+#define MUX_PA05B_ADC_ADC0_AIN2                    _UINT32_(1) 
+#define PINMUX_PA05B_ADC_ADC0_AIN2                 ((PIN_PA05B_ADC_ADC0_AIN2 << 16) | MUX_PA05B_ADC_ADC0_AIN2)
+#define PORT_PA05B_ADC_ADC0_AIN2                   (_UINT32_(1) << 5)
+
+#define PIN_PA06B_ADC_ADC0_AIN3                    _UINT32_(6) 
+#define MUX_PA06B_ADC_ADC0_AIN3                    _UINT32_(1) 
+#define PINMUX_PA06B_ADC_ADC0_AIN3                 ((PIN_PA06B_ADC_ADC0_AIN3 << 16) | MUX_PA06B_ADC_ADC0_AIN3)
+#define PORT_PA06B_ADC_ADC0_AIN3                   (_UINT32_(1) << 6)
+
+#define PIN_PA07B_ADC_ADC0_AIN4                    _UINT32_(7) 
+#define MUX_PA07B_ADC_ADC0_AIN4                    _UINT32_(1) 
+#define PINMUX_PA07B_ADC_ADC0_AIN4                 ((PIN_PA07B_ADC_ADC0_AIN4 << 16) | MUX_PA07B_ADC_ADC0_AIN4)
+#define PORT_PA07B_ADC_ADC0_AIN4                   (_UINT32_(1) << 7)
+
+#define PIN_PA08B_ADC_ADC0_AIN5                    _UINT32_(8) 
+#define MUX_PA08B_ADC_ADC0_AIN5                    _UINT32_(1) 
+#define PINMUX_PA08B_ADC_ADC0_AIN5                 ((PIN_PA08B_ADC_ADC0_AIN5 << 16) | MUX_PA08B_ADC_ADC0_AIN5)
+#define PORT_PA08B_ADC_ADC0_AIN5                   (_UINT32_(1) << 8)
+
+#define PIN_PA09B_ADC_ADC0_AIN6                    _UINT32_(9) 
+#define MUX_PA09B_ADC_ADC0_AIN6                    _UINT32_(1) 
+#define PINMUX_PA09B_ADC_ADC0_AIN6                 ((PIN_PA09B_ADC_ADC0_AIN6 << 16) | MUX_PA09B_ADC_ADC0_AIN6)
+#define PORT_PA09B_ADC_ADC0_AIN6                   (_UINT32_(1) << 9)
+
+#define PIN_PB00B_ADC_ADC0_AIN7                    _UINT32_(32)
+#define MUX_PB00B_ADC_ADC0_AIN7                    _UINT32_(1) 
+#define PINMUX_PB00B_ADC_ADC0_AIN7                 ((PIN_PB00B_ADC_ADC0_AIN7 << 16) | MUX_PB00B_ADC_ADC0_AIN7)
+#define PORT_PB00B_ADC_ADC0_AIN7                   (_UINT32_(1) << 0)
+
+#define PIN_PB03B_ADC_ADC0_AIN8                    _UINT32_(35)
+#define MUX_PB03B_ADC_ADC0_AIN8                    _UINT32_(1) 
+#define PINMUX_PB03B_ADC_ADC0_AIN8                 ((PIN_PB03B_ADC_ADC0_AIN8 << 16) | MUX_PB03B_ADC_ADC0_AIN8)
+#define PORT_PB03B_ADC_ADC0_AIN8                   (_UINT32_(1) << 3)
+
+#define PIN_PB04B_ADC_ADC0_AIN9                    _UINT32_(36)
+#define MUX_PB04B_ADC_ADC0_AIN9                    _UINT32_(1) 
+#define PINMUX_PB04B_ADC_ADC0_AIN9                 ((PIN_PB04B_ADC_ADC0_AIN9 << 16) | MUX_PB04B_ADC_ADC0_AIN9)
+#define PORT_PB04B_ADC_ADC0_AIN9                   (_UINT32_(1) << 4)
+
+#define PIN_PB05B_ADC_ADC0_AIN10                   _UINT32_(37)
+#define MUX_PB05B_ADC_ADC0_AIN10                   _UINT32_(1) 
+#define PINMUX_PB05B_ADC_ADC0_AIN10                ((PIN_PB05B_ADC_ADC0_AIN10 << 16) | MUX_PB05B_ADC_ADC0_AIN10)
+#define PORT_PB05B_ADC_ADC0_AIN10                  (_UINT32_(1) << 5)
+
+#define PIN_PB06B_ADC_ADC0_AIN11                   _UINT32_(38)
+#define MUX_PB06B_ADC_ADC0_AIN11                   _UINT32_(1) 
+#define PINMUX_PB06B_ADC_ADC0_AIN11                ((PIN_PB06B_ADC_ADC0_AIN11 << 16) | MUX_PB06B_ADC_ADC0_AIN11)
+#define PORT_PB06B_ADC_ADC0_AIN11                  (_UINT32_(1) << 6)
+
+#define PIN_PA04B_ADC_ADC0_ANN0                    _UINT32_(4) 
+#define MUX_PA04B_ADC_ADC0_ANN0                    _UINT32_(1) 
+#define PINMUX_PA04B_ADC_ADC0_ANN0                 ((PIN_PA04B_ADC_ADC0_ANN0 << 16) | MUX_PA04B_ADC_ADC0_ANN0)
+#define PORT_PA04B_ADC_ADC0_ANN0                   (_UINT32_(1) << 4)
+
+#define PIN_PA06B_ADC_ADC0_ANN2                    _UINT32_(6) 
+#define MUX_PA06B_ADC_ADC0_ANN2                    _UINT32_(1) 
+#define PINMUX_PA06B_ADC_ADC0_ANN2                 ((PIN_PA06B_ADC_ADC0_ANN2 << 16) | MUX_PA06B_ADC_ADC0_ANN2)
+#define PORT_PA06B_ADC_ADC0_ANN2                   (_UINT32_(1) << 6)
+
+#define PIN_PA08B_ADC_ADC0_ANN4                    _UINT32_(8) 
+#define MUX_PA08B_ADC_ADC0_ANN4                    _UINT32_(1) 
+#define PINMUX_PA08B_ADC_ADC0_ANN4                 ((PIN_PA08B_ADC_ADC0_ANN4 << 16) | MUX_PA08B_ADC_ADC0_ANN4)
+#define PORT_PA08B_ADC_ADC0_ANN4                   (_UINT32_(1) << 8)
+
+/* ================== PORT definition for CAN0 peripheral =================== */
+#define PIN_PA10H_CAN0_RX                          _UINT32_(10)
+#define MUX_PA10H_CAN0_RX                          _UINT32_(7) 
+#define PINMUX_PA10H_CAN0_RX                       ((PIN_PA10H_CAN0_RX << 16) | MUX_PA10H_CAN0_RX)
+#define PORT_PA10H_CAN0_RX                         (_UINT32_(1) << 10)
+
+#define PIN_PC01H_CAN0_RX                          _UINT32_(65)
+#define MUX_PC01H_CAN0_RX                          _UINT32_(7) 
+#define PINMUX_PC01H_CAN0_RX                       ((PIN_PC01H_CAN0_RX << 16) | MUX_PC01H_CAN0_RX)
+#define PORT_PC01H_CAN0_RX                         (_UINT32_(1) << 1)
+
+#define PIN_PD06H_CAN0_RX                          _UINT32_(102)
+#define MUX_PD06H_CAN0_RX                          _UINT32_(7) 
+#define PINMUX_PD06H_CAN0_RX                       ((PIN_PD06H_CAN0_RX << 16) | MUX_PD06H_CAN0_RX)
+#define PORT_PD06H_CAN0_RX                         (_UINT32_(1) << 6)
+
+#define PIN_PA11H_CAN0_TX                          _UINT32_(11)
+#define MUX_PA11H_CAN0_TX                          _UINT32_(7) 
+#define PINMUX_PA11H_CAN0_TX                       ((PIN_PA11H_CAN0_TX << 16) | MUX_PA11H_CAN0_TX)
+#define PORT_PA11H_CAN0_TX                         (_UINT32_(1) << 11)
+
+#define PIN_PC02H_CAN0_TX                          _UINT32_(66)
+#define MUX_PC02H_CAN0_TX                          _UINT32_(7) 
+#define PINMUX_PC02H_CAN0_TX                       ((PIN_PC02H_CAN0_TX << 16) | MUX_PC02H_CAN0_TX)
+#define PORT_PC02H_CAN0_TX                         (_UINT32_(1) << 2)
+
+#define PIN_PD08H_CAN0_TX                          _UINT32_(104)
+#define MUX_PD08H_CAN0_TX                          _UINT32_(7) 
+#define PINMUX_PD08H_CAN0_TX                       ((PIN_PD08H_CAN0_TX << 16) | MUX_PD08H_CAN0_TX)
+#define PORT_PD08H_CAN0_TX                         (_UINT32_(1) << 8)
+
+/* ================== PORT definition for CAN1 peripheral =================== */
+#define PIN_PA00H_CAN1_RX                          _UINT32_(0) 
+#define MUX_PA00H_CAN1_RX                          _UINT32_(7) 
+#define PINMUX_PA00H_CAN1_RX                       ((PIN_PA00H_CAN1_RX << 16) | MUX_PA00H_CAN1_RX)
+#define PORT_PA00H_CAN1_RX                         (_UINT32_(1) << 0)
+
+#define PIN_PC05H_CAN1_RX                          _UINT32_(69)
+#define MUX_PC05H_CAN1_RX                          _UINT32_(7) 
+#define PINMUX_PC05H_CAN1_RX                       ((PIN_PC05H_CAN1_RX << 16) | MUX_PC05H_CAN1_RX)
+#define PORT_PC05H_CAN1_RX                         (_UINT32_(1) << 5)
+
+#define PIN_PD12H_CAN1_RX                          _UINT32_(108)
+#define MUX_PD12H_CAN1_RX                          _UINT32_(7) 
+#define PINMUX_PD12H_CAN1_RX                       ((PIN_PD12H_CAN1_RX << 16) | MUX_PD12H_CAN1_RX)
+#define PORT_PD12H_CAN1_RX                         (_UINT32_(1) << 12)
+
+#define PIN_PA01H_CAN1_TX                          _UINT32_(1) 
+#define MUX_PA01H_CAN1_TX                          _UINT32_(7) 
+#define PINMUX_PA01H_CAN1_TX                       ((PIN_PA01H_CAN1_TX << 16) | MUX_PA01H_CAN1_TX)
+#define PORT_PA01H_CAN1_TX                         (_UINT32_(1) << 1)
+
+#define PIN_PC06H_CAN1_TX                          _UINT32_(70)
+#define MUX_PC06H_CAN1_TX                          _UINT32_(7) 
+#define PINMUX_PC06H_CAN1_TX                       ((PIN_PC06H_CAN1_TX << 16) | MUX_PC06H_CAN1_TX)
+#define PORT_PC06H_CAN1_TX                         (_UINT32_(1) << 6)
+
+#define PIN_PD13H_CAN1_TX                          _UINT32_(109)
+#define MUX_PD13H_CAN1_TX                          _UINT32_(7) 
+#define PINMUX_PD13H_CAN1_TX                       ((PIN_PD13H_CAN1_TX << 16) | MUX_PD13H_CAN1_TX)
+#define PORT_PD13H_CAN1_TX                         (_UINT32_(1) << 13)
+
+/* ================== PORT definition for CCL0 peripheral =================== */
+#define PIN_PC01I_CCL0_IN0                         _UINT32_(65)
+#define MUX_PC01I_CCL0_IN0                         _UINT32_(8) 
+#define PINMUX_PC01I_CCL0_IN0                      ((PIN_PC01I_CCL0_IN0 << 16) | MUX_PC01I_CCL0_IN0)
+#define PORT_PC01I_CCL0_IN0                        (_UINT32_(1) << 1)
+
+#define PIN_PC02I_CCL0_IN1                         _UINT32_(66)
+#define MUX_PC02I_CCL0_IN1                         _UINT32_(8) 
+#define PINMUX_PC02I_CCL0_IN1                      ((PIN_PC02I_CCL0_IN1 << 16) | MUX_PC02I_CCL0_IN1)
+#define PORT_PC02I_CCL0_IN1                        (_UINT32_(1) << 2)
+
+#define PIN_PC09I_CCL0_IN2                         _UINT32_(73)
+#define MUX_PC09I_CCL0_IN2                         _UINT32_(8) 
+#define PINMUX_PC09I_CCL0_IN2                      ((PIN_PC09I_CCL0_IN2 << 16) | MUX_PC09I_CCL0_IN2)
+#define PORT_PC09I_CCL0_IN2                        (_UINT32_(1) << 9)
+
+#define PIN_PD00I_CCL0_IN3                         _UINT32_(96)
+#define MUX_PD00I_CCL0_IN3                         _UINT32_(8) 
+#define PINMUX_PD00I_CCL0_IN3                      ((PIN_PD00I_CCL0_IN3 << 16) | MUX_PD00I_CCL0_IN3)
+#define PORT_PD00I_CCL0_IN3                        (_UINT32_(1) << 0)
+
+#define PIN_PD01I_CCL0_IN4                         _UINT32_(97)
+#define MUX_PD01I_CCL0_IN4                         _UINT32_(8) 
+#define PINMUX_PD01I_CCL0_IN4                      ((PIN_PD01I_CCL0_IN4 << 16) | MUX_PD01I_CCL0_IN4)
+#define PORT_PD01I_CCL0_IN4                        (_UINT32_(1) << 1)
+
+#define PIN_PD10I_CCL0_IN5                         _UINT32_(106)
+#define MUX_PD10I_CCL0_IN5                         _UINT32_(8) 
+#define PINMUX_PD10I_CCL0_IN5                      ((PIN_PD10I_CCL0_IN5 << 16) | MUX_PD10I_CCL0_IN5)
+#define PORT_PD10I_CCL0_IN5                        (_UINT32_(1) << 10)
+
+#define PIN_PA00I_CCL0_IN6                         _UINT32_(0) 
+#define MUX_PA00I_CCL0_IN6                         _UINT32_(8) 
+#define PINMUX_PA00I_CCL0_IN6                      ((PIN_PA00I_CCL0_IN6 << 16) | MUX_PA00I_CCL0_IN6)
+#define PORT_PA00I_CCL0_IN6                        (_UINT32_(1) << 0)
+
+#define PIN_PA01I_CCL0_IN7                         _UINT32_(1) 
+#define MUX_PA01I_CCL0_IN7                         _UINT32_(8) 
+#define PINMUX_PA01I_CCL0_IN7                      ((PIN_PA01I_CCL0_IN7 << 16) | MUX_PA01I_CCL0_IN7)
+#define PORT_PA01I_CCL0_IN7                        (_UINT32_(1) << 1)
+
+#define PIN_PA10I_CCL0_IN8                         _UINT32_(10)
+#define MUX_PA10I_CCL0_IN8                         _UINT32_(8) 
+#define PINMUX_PA10I_CCL0_IN8                      ((PIN_PA10I_CCL0_IN8 << 16) | MUX_PA10I_CCL0_IN8)
+#define PORT_PA10I_CCL0_IN8                        (_UINT32_(1) << 10)
+
+#define PIN_PB05I_CCL0_IN9                         _UINT32_(37)
+#define MUX_PB05I_CCL0_IN9                         _UINT32_(8) 
+#define PINMUX_PB05I_CCL0_IN9                      ((PIN_PB05I_CCL0_IN9 << 16) | MUX_PB05I_CCL0_IN9)
+#define PORT_PB05I_CCL0_IN9                        (_UINT32_(1) << 5)
+
+#define PIN_PB06I_CCL0_IN10                        _UINT32_(38)
+#define MUX_PB06I_CCL0_IN10                        _UINT32_(8) 
+#define PINMUX_PB06I_CCL0_IN10                     ((PIN_PB06I_CCL0_IN10 << 16) | MUX_PB06I_CCL0_IN10)
+#define PORT_PB06I_CCL0_IN10                       (_UINT32_(1) << 6)
+
+#define PIN_PB10I_CCL0_IN11                        _UINT32_(42)
+#define MUX_PB10I_CCL0_IN11                        _UINT32_(8) 
+#define PINMUX_PB10I_CCL0_IN11                     ((PIN_PB10I_CCL0_IN11 << 16) | MUX_PB10I_CCL0_IN11)
+#define PORT_PB10I_CCL0_IN11                       (_UINT32_(1) << 10)
+
+#define PIN_PC03I_CCL0_OUT0                        _UINT32_(67)
+#define MUX_PC03I_CCL0_OUT0                        _UINT32_(8) 
+#define PINMUX_PC03I_CCL0_OUT0                     ((PIN_PC03I_CCL0_OUT0 << 16) | MUX_PC03I_CCL0_OUT0)
+#define PORT_PC03I_CCL0_OUT0                       (_UINT32_(1) << 3)
+
+#define PIN_PD08I_CCL0_OUT1                        _UINT32_(104)
+#define MUX_PD08I_CCL0_OUT1                        _UINT32_(8) 
+#define PINMUX_PD08I_CCL0_OUT1                     ((PIN_PD08I_CCL0_OUT1 << 16) | MUX_PD08I_CCL0_OUT1)
+#define PORT_PD08I_CCL0_OUT1                       (_UINT32_(1) << 8)
+
+#define PIN_PA02I_CCL0_OUT2                        _UINT32_(2) 
+#define MUX_PA02I_CCL0_OUT2                        _UINT32_(8) 
+#define PINMUX_PA02I_CCL0_OUT2                     ((PIN_PA02I_CCL0_OUT2 << 16) | MUX_PA02I_CCL0_OUT2)
+#define PORT_PA02I_CCL0_OUT2                       (_UINT32_(1) << 2)
+
+#define PIN_PC00I_CCL0_OUT3                        _UINT32_(64)
+#define MUX_PC00I_CCL0_OUT3                        _UINT32_(8) 
+#define PINMUX_PC00I_CCL0_OUT3                     ((PIN_PC00I_CCL0_OUT3 << 16) | MUX_PC00I_CCL0_OUT3)
+#define PORT_PC00I_CCL0_OUT3                       (_UINT32_(1) << 0)
+
+/* ================== PORT definition for CCL1 peripheral =================== */
+#define PIN_PC04I_CCL1_IN0                         _UINT32_(68)
+#define MUX_PC04I_CCL1_IN0                         _UINT32_(8) 
+#define PINMUX_PC04I_CCL1_IN0                      ((PIN_PC04I_CCL1_IN0 << 16) | MUX_PC04I_CCL1_IN0)
+#define PORT_PC04I_CCL1_IN0                        (_UINT32_(1) << 4)
+
+#define PIN_PC05I_CCL1_IN1                         _UINT32_(69)
+#define MUX_PC05I_CCL1_IN1                         _UINT32_(8) 
+#define PINMUX_PC05I_CCL1_IN1                      ((PIN_PC05I_CCL1_IN1 << 16) | MUX_PC05I_CCL1_IN1)
+#define PORT_PC05I_CCL1_IN1                        (_UINT32_(1) << 5)
+
+#define PIN_PC10I_CCL1_IN2                         _UINT32_(74)
+#define MUX_PC10I_CCL1_IN2                         _UINT32_(8) 
+#define PINMUX_PC10I_CCL1_IN2                      ((PIN_PC10I_CCL1_IN2 << 16) | MUX_PC10I_CCL1_IN2)
+#define PORT_PC10I_CCL1_IN2                        (_UINT32_(1) << 10)
+
+#define PIN_PD06I_CCL1_IN3                         _UINT32_(102)
+#define MUX_PD06I_CCL1_IN3                         _UINT32_(8) 
+#define PINMUX_PD06I_CCL1_IN3                      ((PIN_PD06I_CCL1_IN3 << 16) | MUX_PD06I_CCL1_IN3)
+#define PORT_PD06I_CCL1_IN3                        (_UINT32_(1) << 6)
+
+#define PIN_PD07I_CCL1_IN4                         _UINT32_(103)
+#define MUX_PD07I_CCL1_IN4                         _UINT32_(8) 
+#define PINMUX_PD07I_CCL1_IN4                      ((PIN_PD07I_CCL1_IN4 << 16) | MUX_PD07I_CCL1_IN4)
+#define PORT_PD07I_CCL1_IN4                        (_UINT32_(1) << 7)
+
+#define PIN_PD11I_CCL1_IN5                         _UINT32_(107)
+#define MUX_PD11I_CCL1_IN5                         _UINT32_(8) 
+#define PINMUX_PD11I_CCL1_IN5                      ((PIN_PD11I_CCL1_IN5 << 16) | MUX_PD11I_CCL1_IN5)
+#define PORT_PD11I_CCL1_IN5                        (_UINT32_(1) << 11)
+
+#define PIN_PD12I_CCL1_IN5                         _UINT32_(108)
+#define MUX_PD12I_CCL1_IN5                         _UINT32_(8) 
+#define PINMUX_PD12I_CCL1_IN5                      ((PIN_PD12I_CCL1_IN5 << 16) | MUX_PD12I_CCL1_IN5)
+#define PORT_PD12I_CCL1_IN5                        (_UINT32_(1) << 12)
+
+#define PIN_PA09I_CCL1_IN6                         _UINT32_(9) 
+#define MUX_PA09I_CCL1_IN6                         _UINT32_(8) 
+#define PINMUX_PA09I_CCL1_IN6                      ((PIN_PA09I_CCL1_IN6 << 16) | MUX_PA09I_CCL1_IN6)
+#define PORT_PA09I_CCL1_IN6                        (_UINT32_(1) << 9)
+
+#define PIN_PA06I_CCL1_IN7                         _UINT32_(6) 
+#define MUX_PA06I_CCL1_IN7                         _UINT32_(8) 
+#define PINMUX_PA06I_CCL1_IN7                      ((PIN_PA06I_CCL1_IN7 << 16) | MUX_PA06I_CCL1_IN7)
+#define PORT_PA06I_CCL1_IN7                        (_UINT32_(1) << 6)
+
+#define PIN_PA11I_CCL1_IN8                         _UINT32_(11)
+#define MUX_PA11I_CCL1_IN8                         _UINT32_(8) 
+#define PINMUX_PA11I_CCL1_IN8                      ((PIN_PA11I_CCL1_IN8 << 16) | MUX_PA11I_CCL1_IN8)
+#define PORT_PA11I_CCL1_IN8                        (_UINT32_(1) << 11)
+
+#define PIN_PA12I_CCL1_IN8                         _UINT32_(12)
+#define MUX_PA12I_CCL1_IN8                         _UINT32_(8) 
+#define PINMUX_PA12I_CCL1_IN8                      ((PIN_PA12I_CCL1_IN8 << 16) | MUX_PA12I_CCL1_IN8)
+#define PORT_PA12I_CCL1_IN8                        (_UINT32_(1) << 12)
+
+#define PIN_PB04I_CCL1_IN9                         _UINT32_(36)
+#define MUX_PB04I_CCL1_IN9                         _UINT32_(8) 
+#define PINMUX_PB04I_CCL1_IN9                      ((PIN_PB04I_CCL1_IN9 << 16) | MUX_PB04I_CCL1_IN9)
+#define PORT_PB04I_CCL1_IN9                        (_UINT32_(1) << 4)
+
+#define PIN_PB03I_CCL1_IN10                        _UINT32_(35)
+#define MUX_PB03I_CCL1_IN10                        _UINT32_(8) 
+#define PINMUX_PB03I_CCL1_IN10                     ((PIN_PB03I_CCL1_IN10 << 16) | MUX_PB03I_CCL1_IN10)
+#define PORT_PB03I_CCL1_IN10                       (_UINT32_(1) << 3)
+
+#define PIN_PB07I_CCL1_IN11                        _UINT32_(39)
+#define MUX_PB07I_CCL1_IN11                        _UINT32_(8) 
+#define PINMUX_PB07I_CCL1_IN11                     ((PIN_PB07I_CCL1_IN11 << 16) | MUX_PB07I_CCL1_IN11)
+#define PORT_PB07I_CCL1_IN11                       (_UINT32_(1) << 7)
+
+#define PIN_PB08I_CCL1_IN11                        _UINT32_(40)
+#define MUX_PB08I_CCL1_IN11                        _UINT32_(8) 
+#define PINMUX_PB08I_CCL1_IN11                     ((PIN_PB08I_CCL1_IN11 << 16) | MUX_PB08I_CCL1_IN11)
+#define PORT_PB08I_CCL1_IN11                       (_UINT32_(1) << 8)
+
+#define PIN_PC06I_CCL1_OUT0                        _UINT32_(70)
+#define MUX_PC06I_CCL1_OUT0                        _UINT32_(8) 
+#define PINMUX_PC06I_CCL1_OUT0                     ((PIN_PC06I_CCL1_OUT0 << 16) | MUX_PC06I_CCL1_OUT0)
+#define PORT_PC06I_CCL1_OUT0                       (_UINT32_(1) << 6)
+
+#define PIN_PD09I_CCL1_OUT1                        _UINT32_(105)
+#define MUX_PD09I_CCL1_OUT1                        _UINT32_(8) 
+#define PINMUX_PD09I_CCL1_OUT1                     ((PIN_PD09I_CCL1_OUT1 << 16) | MUX_PD09I_CCL1_OUT1)
+#define PORT_PD09I_CCL1_OUT1                       (_UINT32_(1) << 9)
+
+#define PIN_PA05I_CCL1_OUT2                        _UINT32_(5) 
+#define MUX_PA05I_CCL1_OUT2                        _UINT32_(8) 
+#define PINMUX_PA05I_CCL1_OUT2                     ((PIN_PA05I_CCL1_OUT2 << 16) | MUX_PA05I_CCL1_OUT2)
+#define PORT_PA05I_CCL1_OUT2                       (_UINT32_(1) << 5)
+
+#define PIN_PB00I_CCL1_OUT3                        _UINT32_(32)
+#define MUX_PB00I_CCL1_OUT3                        _UINT32_(8) 
+#define PINMUX_PB00I_CCL1_OUT3                     ((PIN_PB00I_CCL1_OUT3 << 16) | MUX_PB00I_CCL1_OUT3)
+#define PORT_PB00I_CCL1_OUT3                       (_UINT32_(1) << 0)
+
+/* =================== PORT definition for EIC peripheral =================== */
+#define PIN_PA00A_EIC_EXTINT0                      _UINT32_(0) 
+#define MUX_PA00A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PA00A_EIC_EXTINT0                   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0                     (_UINT32_(1) << 0)
+#define PIN_PA00A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PA00 External Interrupt Line */
+
+#define PIN_PB00A_EIC_EXTINT0                      _UINT32_(32)
+#define MUX_PB00A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PB00A_EIC_EXTINT0                   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0                     (_UINT32_(1) << 0)
+#define PIN_PB00A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PB00 External Interrupt Line */
+
+#define PIN_PC00A_EIC_EXTINT0                      _UINT32_(64)
+#define MUX_PC00A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PC00A_EIC_EXTINT0                   ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
+#define PORT_PC00A_EIC_EXTINT0                     (_UINT32_(1) << 0)
+#define PIN_PC00A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PC00 External Interrupt Line */
+
+#define PIN_PA01A_EIC_EXTINT1                      _UINT32_(1) 
+#define MUX_PA01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PA01A_EIC_EXTINT1                   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PA01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PA01 External Interrupt Line */
+
+#define PIN_PB01A_EIC_EXTINT1                      _UINT32_(33)
+#define MUX_PB01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PB01A_EIC_EXTINT1                   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PB01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PB01 External Interrupt Line */
+
+#define PIN_PC01A_EIC_EXTINT1                      _UINT32_(65)
+#define MUX_PC01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PC01A_EIC_EXTINT1                   ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
+#define PORT_PC01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PC01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PC01 External Interrupt Line */
+
+#define PIN_PD01A_EIC_EXTINT1                      _UINT32_(97)
+#define MUX_PD01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PD01A_EIC_EXTINT1                   ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1)
+#define PORT_PD01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PD01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PD01 External Interrupt Line */
+
+#define PIN_PA02A_EIC_EXTINT2                      _UINT32_(2) 
+#define MUX_PA02A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PA02A_EIC_EXTINT2                   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2                     (_UINT32_(1) << 2)
+#define PIN_PA02A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PA02 External Interrupt Line */
+
+#define PIN_PB02A_EIC_EXTINT2                      _UINT32_(34)
+#define MUX_PB02A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PB02A_EIC_EXTINT2                   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2                     (_UINT32_(1) << 2)
+#define PIN_PB02A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PB02 External Interrupt Line */
+
+#define PIN_PC02A_EIC_EXTINT2                      _UINT32_(66)
+#define MUX_PC02A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PC02A_EIC_EXTINT2                   ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
+#define PORT_PC02A_EIC_EXTINT2                     (_UINT32_(1) << 2)
+#define PIN_PC02A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PC02 External Interrupt Line */
+
+#define PIN_PD04A_EIC_EXTINT2                      _UINT32_(100)
+#define MUX_PD04A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PD04A_EIC_EXTINT2                   ((PIN_PD04A_EIC_EXTINT2 << 16) | MUX_PD04A_EIC_EXTINT2)
+#define PORT_PD04A_EIC_EXTINT2                     (_UINT32_(1) << 4)
+#define PIN_PD04A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PD04 External Interrupt Line */
+
+#define PIN_PA03A_EIC_EXTINT3                      _UINT32_(3) 
+#define MUX_PA03A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PA03A_EIC_EXTINT3                   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3                     (_UINT32_(1) << 3)
+#define PIN_PA03A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PA03 External Interrupt Line */
+
+#define PIN_PB03A_EIC_EXTINT3                      _UINT32_(35)
+#define MUX_PB03A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PB03A_EIC_EXTINT3                   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3                     (_UINT32_(1) << 3)
+#define PIN_PB03A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PB03 External Interrupt Line */
+
+#define PIN_PC03A_EIC_EXTINT3                      _UINT32_(67)
+#define MUX_PC03A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PC03A_EIC_EXTINT3                   ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
+#define PORT_PC03A_EIC_EXTINT3                     (_UINT32_(1) << 3)
+#define PIN_PC03A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PC03 External Interrupt Line */
+
+#define PIN_PD05A_EIC_EXTINT3                      _UINT32_(101)
+#define MUX_PD05A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PD05A_EIC_EXTINT3                   ((PIN_PD05A_EIC_EXTINT3 << 16) | MUX_PD05A_EIC_EXTINT3)
+#define PORT_PD05A_EIC_EXTINT3                     (_UINT32_(1) << 5)
+#define PIN_PD05A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PD05 External Interrupt Line */
+
+#define PIN_PA04A_EIC_EXTINT4                      _UINT32_(4) 
+#define MUX_PA04A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PA04A_EIC_EXTINT4                   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4                     (_UINT32_(1) << 4)
+#define PIN_PA04A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PA04 External Interrupt Line */
+
+#define PIN_PB04A_EIC_EXTINT4                      _UINT32_(36)
+#define MUX_PB04A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PB04A_EIC_EXTINT4                   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4                     (_UINT32_(1) << 4)
+#define PIN_PB04A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PB04 External Interrupt Line */
+
+#define PIN_PC04A_EIC_EXTINT4                      _UINT32_(68)
+#define MUX_PC04A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PC04A_EIC_EXTINT4                   ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4)
+#define PORT_PC04A_EIC_EXTINT4                     (_UINT32_(1) << 4)
+#define PIN_PC04A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PC04 External Interrupt Line */
+
+#define PIN_PD07A_EIC_EXTINT4                      _UINT32_(103)
+#define MUX_PD07A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PD07A_EIC_EXTINT4                   ((PIN_PD07A_EIC_EXTINT4 << 16) | MUX_PD07A_EIC_EXTINT4)
+#define PORT_PD07A_EIC_EXTINT4                     (_UINT32_(1) << 7)
+#define PIN_PD07A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PD07 External Interrupt Line */
+
+#define PIN_PA05A_EIC_EXTINT5                      _UINT32_(5) 
+#define MUX_PA05A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PA05A_EIC_EXTINT5                   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5                     (_UINT32_(1) << 5)
+#define PIN_PA05A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PA05 External Interrupt Line */
+
+#define PIN_PB05A_EIC_EXTINT5                      _UINT32_(37)
+#define MUX_PB05A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PB05A_EIC_EXTINT5                   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5                     (_UINT32_(1) << 5)
+#define PIN_PB05A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PB05 External Interrupt Line */
+
+#define PIN_PC05A_EIC_EXTINT5                      _UINT32_(69)
+#define MUX_PC05A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PC05A_EIC_EXTINT5                   ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
+#define PORT_PC05A_EIC_EXTINT5                     (_UINT32_(1) << 5)
+#define PIN_PC05A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PC05 External Interrupt Line */
+
+#define PIN_PD08A_EIC_EXTINT5                      _UINT32_(104)
+#define MUX_PD08A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PD08A_EIC_EXTINT5                   ((PIN_PD08A_EIC_EXTINT5 << 16) | MUX_PD08A_EIC_EXTINT5)
+#define PORT_PD08A_EIC_EXTINT5                     (_UINT32_(1) << 8)
+#define PIN_PD08A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PD08 External Interrupt Line */
+
+#define PIN_PA06A_EIC_EXTINT6                      _UINT32_(6) 
+#define MUX_PA06A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PA06A_EIC_EXTINT6                   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6                     (_UINT32_(1) << 6)
+#define PIN_PA06A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PA06 External Interrupt Line */
+
+#define PIN_PB06A_EIC_EXTINT6                      _UINT32_(38)
+#define MUX_PB06A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PB06A_EIC_EXTINT6                   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6                     (_UINT32_(1) << 6)
+#define PIN_PB06A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PB06 External Interrupt Line */
+
+#define PIN_PC06A_EIC_EXTINT6                      _UINT32_(70)
+#define MUX_PC06A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PC06A_EIC_EXTINT6                   ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
+#define PORT_PC06A_EIC_EXTINT6                     (_UINT32_(1) << 6)
+#define PIN_PC06A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PC06 External Interrupt Line */
+
+#define PIN_PD09A_EIC_EXTINT6                      _UINT32_(105)
+#define MUX_PD09A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PD09A_EIC_EXTINT6                   ((PIN_PD09A_EIC_EXTINT6 << 16) | MUX_PD09A_EIC_EXTINT6)
+#define PORT_PD09A_EIC_EXTINT6                     (_UINT32_(1) << 9)
+#define PIN_PD09A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PD09 External Interrupt Line */
+
+#define PIN_PA07A_EIC_EXTINT7                      _UINT32_(7) 
+#define MUX_PA07A_EIC_EXTINT7                      _UINT32_(0) 
+#define PINMUX_PA07A_EIC_EXTINT7                   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7                     (_UINT32_(1) << 7)
+#define PIN_PA07A_EIC_EXTINT_NUM                   _UINT32_(7)  /* EIC signal: PIN_PA07 External Interrupt Line */
+
+#define PIN_PA08A_EIC_EXTINT8                      _UINT32_(8) 
+#define MUX_PA08A_EIC_EXTINT8                      _UINT32_(0) 
+#define PINMUX_PA08A_EIC_EXTINT8                   ((PIN_PA08A_EIC_EXTINT8 << 16) | MUX_PA08A_EIC_EXTINT8)
+#define PORT_PA08A_EIC_EXTINT8                     (_UINT32_(1) << 8)
+#define PIN_PA08A_EIC_EXTINT_NUM                   _UINT32_(8)  /* EIC signal: PIN_PA08 External Interrupt Line */
+
+#define PIN_PB07A_EIC_EXTINT8                      _UINT32_(39)
+#define MUX_PB07A_EIC_EXTINT8                      _UINT32_(0) 
+#define PINMUX_PB07A_EIC_EXTINT8                   ((PIN_PB07A_EIC_EXTINT8 << 16) | MUX_PB07A_EIC_EXTINT8)
+#define PORT_PB07A_EIC_EXTINT8                     (_UINT32_(1) << 7)
+#define PIN_PB07A_EIC_EXTINT_NUM                   _UINT32_(8)  /* EIC signal: PIN_PB07 External Interrupt Line */
+
+#define PIN_PD10A_EIC_EXTINT8                      _UINT32_(106)
+#define MUX_PD10A_EIC_EXTINT8                      _UINT32_(0) 
+#define PINMUX_PD10A_EIC_EXTINT8                   ((PIN_PD10A_EIC_EXTINT8 << 16) | MUX_PD10A_EIC_EXTINT8)
+#define PORT_PD10A_EIC_EXTINT8                     (_UINT32_(1) << 10)
+#define PIN_PD10A_EIC_EXTINT_NUM                   _UINT32_(8)  /* EIC signal: PIN_PD10 External Interrupt Line */
+
+#define PIN_PA09A_EIC_EXTINT9                      _UINT32_(9) 
+#define MUX_PA09A_EIC_EXTINT9                      _UINT32_(0) 
+#define PINMUX_PA09A_EIC_EXTINT9                   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9                     (_UINT32_(1) << 9)
+#define PIN_PA09A_EIC_EXTINT_NUM                   _UINT32_(9)  /* EIC signal: PIN_PA09 External Interrupt Line */
+
+#define PIN_PB08A_EIC_EXTINT9                      _UINT32_(40)
+#define MUX_PB08A_EIC_EXTINT9                      _UINT32_(0) 
+#define PINMUX_PB08A_EIC_EXTINT9                   ((PIN_PB08A_EIC_EXTINT9 << 16) | MUX_PB08A_EIC_EXTINT9)
+#define PORT_PB08A_EIC_EXTINT9                     (_UINT32_(1) << 8)
+#define PIN_PB08A_EIC_EXTINT_NUM                   _UINT32_(9)  /* EIC signal: PIN_PB08 External Interrupt Line */
+
+#define PIN_PC09A_EIC_EXTINT9                      _UINT32_(73)
+#define MUX_PC09A_EIC_EXTINT9                      _UINT32_(0) 
+#define PINMUX_PC09A_EIC_EXTINT9                   ((PIN_PC09A_EIC_EXTINT9 << 16) | MUX_PC09A_EIC_EXTINT9)
+#define PORT_PC09A_EIC_EXTINT9                     (_UINT32_(1) << 9)
+#define PIN_PC09A_EIC_EXTINT_NUM                   _UINT32_(9)  /* EIC signal: PIN_PC09 External Interrupt Line */
+
+#define PIN_PD11A_EIC_EXTINT9                      _UINT32_(107)
+#define MUX_PD11A_EIC_EXTINT9                      _UINT32_(0) 
+#define PINMUX_PD11A_EIC_EXTINT9                   ((PIN_PD11A_EIC_EXTINT9 << 16) | MUX_PD11A_EIC_EXTINT9)
+#define PORT_PD11A_EIC_EXTINT9                     (_UINT32_(1) << 11)
+#define PIN_PD11A_EIC_EXTINT_NUM                   _UINT32_(9)  /* EIC signal: PIN_PD11 External Interrupt Line */
+
+#define PIN_PA10A_EIC_EXTINT10                     _UINT32_(10)
+#define MUX_PA10A_EIC_EXTINT10                     _UINT32_(0) 
+#define PINMUX_PA10A_EIC_EXTINT10                  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10                    (_UINT32_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM                   _UINT32_(10) /* EIC signal: PIN_PA10 External Interrupt Line */
+
+#define PIN_PB09A_EIC_EXTINT10                     _UINT32_(41)
+#define MUX_PB09A_EIC_EXTINT10                     _UINT32_(0) 
+#define PINMUX_PB09A_EIC_EXTINT10                  ((PIN_PB09A_EIC_EXTINT10 << 16) | MUX_PB09A_EIC_EXTINT10)
+#define PORT_PB09A_EIC_EXTINT10                    (_UINT32_(1) << 9)
+#define PIN_PB09A_EIC_EXTINT_NUM                   _UINT32_(10) /* EIC signal: PIN_PB09 External Interrupt Line */
+
+#define PIN_PC10A_EIC_EXTINT10                     _UINT32_(74)
+#define MUX_PC10A_EIC_EXTINT10                     _UINT32_(0) 
+#define PINMUX_PC10A_EIC_EXTINT10                  ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10)
+#define PORT_PC10A_EIC_EXTINT10                    (_UINT32_(1) << 10)
+#define PIN_PC10A_EIC_EXTINT_NUM                   _UINT32_(10) /* EIC signal: PIN_PC10 External Interrupt Line */
+
+#define PIN_PD12A_EIC_EXTINT10                     _UINT32_(108)
+#define MUX_PD12A_EIC_EXTINT10                     _UINT32_(0) 
+#define PINMUX_PD12A_EIC_EXTINT10                  ((PIN_PD12A_EIC_EXTINT10 << 16) | MUX_PD12A_EIC_EXTINT10)
+#define PORT_PD12A_EIC_EXTINT10                    (_UINT32_(1) << 12)
+#define PIN_PD12A_EIC_EXTINT_NUM                   _UINT32_(10) /* EIC signal: PIN_PD12 External Interrupt Line */
+
+#define PIN_PA11A_EIC_EXTINT11                     _UINT32_(11)
+#define MUX_PA11A_EIC_EXTINT11                     _UINT32_(0) 
+#define PINMUX_PA11A_EIC_EXTINT11                  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11                    (_UINT32_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM                   _UINT32_(11) /* EIC signal: PIN_PA11 External Interrupt Line */
+
+#define PIN_PB10A_EIC_EXTINT11                     _UINT32_(42)
+#define MUX_PB10A_EIC_EXTINT11                     _UINT32_(0) 
+#define PINMUX_PB10A_EIC_EXTINT11                  ((PIN_PB10A_EIC_EXTINT11 << 16) | MUX_PB10A_EIC_EXTINT11)
+#define PORT_PB10A_EIC_EXTINT11                    (_UINT32_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM                   _UINT32_(11) /* EIC signal: PIN_PB10 External Interrupt Line */
+
+#define PIN_PD13A_EIC_EXTINT11                     _UINT32_(109)
+#define MUX_PD13A_EIC_EXTINT11                     _UINT32_(0) 
+#define PINMUX_PD13A_EIC_EXTINT11                  ((PIN_PD13A_EIC_EXTINT11 << 16) | MUX_PD13A_EIC_EXTINT11)
+#define PORT_PD13A_EIC_EXTINT11                    (_UINT32_(1) << 13)
+#define PIN_PD13A_EIC_EXTINT_NUM                   _UINT32_(11) /* EIC signal: PIN_PD13 External Interrupt Line */
+
+#define PIN_PA12A_EIC_EXTINT12                     _UINT32_(12)
+#define MUX_PA12A_EIC_EXTINT12                     _UINT32_(0) 
+#define PINMUX_PA12A_EIC_EXTINT12                  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12                    (_UINT32_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM                   _UINT32_(12) /* EIC signal: PIN_PA12 External Interrupt Line */
+
+#define PIN_PA13A_EIC_EXTINT13                     _UINT32_(13)
+#define MUX_PA13A_EIC_EXTINT13                     _UINT32_(0) 
+#define PINMUX_PA13A_EIC_EXTINT13                  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13                    (_UINT32_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM                   _UINT32_(13) /* EIC signal: PIN_PA13 External Interrupt Line */
+
+#define PIN_PD00A_EIC_NMI                          _UINT32_(96)
+#define MUX_PD00A_EIC_NMI                          _UINT32_(0) 
+#define PINMUX_PD00A_EIC_NMI                       ((PIN_PD00A_EIC_NMI << 16) | MUX_PD00A_EIC_NMI)
+#define PORT_PD00A_EIC_NMI                         (_UINT32_(1) << 0)
+
+/* ================== PORT definition for GCLK peripheral =================== */
+#define PIN_PB06K_GCLK_IO0                         _UINT32_(38)
+#define MUX_PB06K_GCLK_IO0                         _UINT32_(10)
+#define PINMUX_PB06K_GCLK_IO0                      ((PIN_PB06K_GCLK_IO0 << 16) | MUX_PB06K_GCLK_IO0)
+#define PORT_PB06K_GCLK_IO0                        (_UINT32_(1) << 6)
+
+#define PIN_PC09K_GCLK_IO0                         _UINT32_(73)
+#define MUX_PC09K_GCLK_IO0                         _UINT32_(10)
+#define PINMUX_PC09K_GCLK_IO0                      ((PIN_PC09K_GCLK_IO0 << 16) | MUX_PC09K_GCLK_IO0)
+#define PORT_PC09K_GCLK_IO0                        (_UINT32_(1) << 9)
+
+#define PIN_PD05K_GCLK_IO0                         _UINT32_(101)
+#define MUX_PD05K_GCLK_IO0                         _UINT32_(10)
+#define PINMUX_PD05K_GCLK_IO0                      ((PIN_PD05K_GCLK_IO0 << 16) | MUX_PD05K_GCLK_IO0)
+#define PORT_PD05K_GCLK_IO0                        (_UINT32_(1) << 5)
+
+#define PIN_PC00K_GCLK_IO1                         _UINT32_(64)
+#define MUX_PC00K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PC00K_GCLK_IO1                      ((PIN_PC00K_GCLK_IO1 << 16) | MUX_PC00K_GCLK_IO1)
+#define PORT_PC00K_GCLK_IO1                        (_UINT32_(1) << 0)
+
+#define PIN_PC10K_GCLK_IO1                         _UINT32_(74)
+#define MUX_PC10K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PC10K_GCLK_IO1                      ((PIN_PC10K_GCLK_IO1 << 16) | MUX_PC10K_GCLK_IO1)
+#define PORT_PC10K_GCLK_IO1                        (_UINT32_(1) << 10)
+
+#define PIN_PC05K_GCLK_IO1                         _UINT32_(69)
+#define MUX_PC05K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PC05K_GCLK_IO1                      ((PIN_PC05K_GCLK_IO1 << 16) | MUX_PC05K_GCLK_IO1)
+#define PORT_PC05K_GCLK_IO1                        (_UINT32_(1) << 5)
+
+#define PIN_PD04K_GCLK_IO1                         _UINT32_(100)
+#define MUX_PD04K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PD04K_GCLK_IO1                      ((PIN_PD04K_GCLK_IO1 << 16) | MUX_PD04K_GCLK_IO1)
+#define PORT_PD04K_GCLK_IO1                        (_UINT32_(1) << 4)
+
+#define PIN_PC01K_GCLK_IO2                         _UINT32_(65)
+#define MUX_PC01K_GCLK_IO2                         _UINT32_(10)
+#define PINMUX_PC01K_GCLK_IO2                      ((PIN_PC01K_GCLK_IO2 << 16) | MUX_PC01K_GCLK_IO2)
+#define PORT_PC01K_GCLK_IO2                        (_UINT32_(1) << 1)
+
+#define PIN_PC02K_GCLK_IO3                         _UINT32_(66)
+#define MUX_PC02K_GCLK_IO3                         _UINT32_(10)
+#define PINMUX_PC02K_GCLK_IO3                      ((PIN_PC02K_GCLK_IO3 << 16) | MUX_PC02K_GCLK_IO3)
+#define PORT_PC02K_GCLK_IO3                        (_UINT32_(1) << 2)
+
+#define PIN_PC03K_GCLK_IO4                         _UINT32_(67)
+#define MUX_PC03K_GCLK_IO4                         _UINT32_(10)
+#define PINMUX_PC03K_GCLK_IO4                      ((PIN_PC03K_GCLK_IO4 << 16) | MUX_PC03K_GCLK_IO4)
+#define PORT_PC03K_GCLK_IO4                        (_UINT32_(1) << 3)
+
+#define PIN_PC04K_GCLK_IO5                         _UINT32_(68)
+#define MUX_PC04K_GCLK_IO5                         _UINT32_(10)
+#define PINMUX_PC04K_GCLK_IO5                      ((PIN_PC04K_GCLK_IO5 << 16) | MUX_PC04K_GCLK_IO5)
+#define PORT_PC04K_GCLK_IO5                        (_UINT32_(1) << 4)
+
+#define PIN_PB10K_GCLK_IO6                         _UINT32_(42)
+#define MUX_PB10K_GCLK_IO6                         _UINT32_(10)
+#define PINMUX_PB10K_GCLK_IO6                      ((PIN_PB10K_GCLK_IO6 << 16) | MUX_PB10K_GCLK_IO6)
+#define PORT_PB10K_GCLK_IO6                        (_UINT32_(1) << 10)
+
+#define PIN_PB09K_GCLK_IO7                         _UINT32_(41)
+#define MUX_PB09K_GCLK_IO7                         _UINT32_(10)
+#define PINMUX_PB09K_GCLK_IO7                      ((PIN_PB09K_GCLK_IO7 << 16) | MUX_PB09K_GCLK_IO7)
+#define PORT_PB09K_GCLK_IO7                        (_UINT32_(1) << 9)
+
+/* =================== PORT definition for PTC peripheral =================== */
+#define PIN_PD06P_PTC_DRV0                         _UINT32_(102)
+#define MUX_PD06P_PTC_DRV0                         _UINT32_(15)
+#define PINMUX_PD06P_PTC_DRV0                      ((PIN_PD06P_PTC_DRV0 << 16) | MUX_PD06P_PTC_DRV0)
+#define PORT_PD06P_PTC_DRV0                        (_UINT32_(1) << 6)
+
+#define PIN_PD07P_PTC_DRV1                         _UINT32_(103)
+#define MUX_PD07P_PTC_DRV1                         _UINT32_(15)
+#define PINMUX_PD07P_PTC_DRV1                      ((PIN_PD07P_PTC_DRV1 << 16) | MUX_PD07P_PTC_DRV1)
+#define PORT_PD07P_PTC_DRV1                        (_UINT32_(1) << 7)
+
+#define PIN_PD08P_PTC_DRV2                         _UINT32_(104)
+#define MUX_PD08P_PTC_DRV2                         _UINT32_(15)
+#define PINMUX_PD08P_PTC_DRV2                      ((PIN_PD08P_PTC_DRV2 << 16) | MUX_PD08P_PTC_DRV2)
+#define PORT_PD08P_PTC_DRV2                        (_UINT32_(1) << 8)
+
+#define PIN_PD09P_PTC_DRV3                         _UINT32_(105)
+#define MUX_PD09P_PTC_DRV3                         _UINT32_(15)
+#define PINMUX_PD09P_PTC_DRV3                      ((PIN_PD09P_PTC_DRV3 << 16) | MUX_PD09P_PTC_DRV3)
+#define PORT_PD09P_PTC_DRV3                        (_UINT32_(1) << 9)
+
+#define PIN_PA00P_PTC_DRV4                         _UINT32_(0) 
+#define MUX_PA00P_PTC_DRV4                         _UINT32_(15)
+#define PINMUX_PA00P_PTC_DRV4                      ((PIN_PA00P_PTC_DRV4 << 16) | MUX_PA00P_PTC_DRV4)
+#define PORT_PA00P_PTC_DRV4                        (_UINT32_(1) << 0)
+
+#define PIN_PA01P_PTC_DRV5                         _UINT32_(1) 
+#define MUX_PA01P_PTC_DRV5                         _UINT32_(15)
+#define PINMUX_PA01P_PTC_DRV5                      ((PIN_PA01P_PTC_DRV5 << 16) | MUX_PA01P_PTC_DRV5)
+#define PORT_PA01P_PTC_DRV5                        (_UINT32_(1) << 1)
+
+#define PIN_PA02P_PTC_DRV6                         _UINT32_(2) 
+#define MUX_PA02P_PTC_DRV6                         _UINT32_(15)
+#define PINMUX_PA02P_PTC_DRV6                      ((PIN_PA02P_PTC_DRV6 << 16) | MUX_PA02P_PTC_DRV6)
+#define PORT_PA02P_PTC_DRV6                        (_UINT32_(1) << 2)
+
+#define PIN_PA03P_PTC_DRV7                         _UINT32_(3) 
+#define MUX_PA03P_PTC_DRV7                         _UINT32_(15)
+#define PINMUX_PA03P_PTC_DRV7                      ((PIN_PA03P_PTC_DRV7 << 16) | MUX_PA03P_PTC_DRV7)
+#define PORT_PA03P_PTC_DRV7                        (_UINT32_(1) << 3)
+
+#define PIN_PA04P_PTC_DRV8                         _UINT32_(4) 
+#define MUX_PA04P_PTC_DRV8                         _UINT32_(15)
+#define PINMUX_PA04P_PTC_DRV8                      ((PIN_PA04P_PTC_DRV8 << 16) | MUX_PA04P_PTC_DRV8)
+#define PORT_PA04P_PTC_DRV8                        (_UINT32_(1) << 4)
+
+#define PIN_PA05P_PTC_DRV9                         _UINT32_(5) 
+#define MUX_PA05P_PTC_DRV9                         _UINT32_(15)
+#define PINMUX_PA05P_PTC_DRV9                      ((PIN_PA05P_PTC_DRV9 << 16) | MUX_PA05P_PTC_DRV9)
+#define PORT_PA05P_PTC_DRV9                        (_UINT32_(1) << 5)
+
+#define PIN_PA06P_PTC_DRV10                        _UINT32_(6) 
+#define MUX_PA06P_PTC_DRV10                        _UINT32_(15)
+#define PINMUX_PA06P_PTC_DRV10                     ((PIN_PA06P_PTC_DRV10 << 16) | MUX_PA06P_PTC_DRV10)
+#define PORT_PA06P_PTC_DRV10                       (_UINT32_(1) << 6)
+
+#define PIN_PA07P_PTC_DRV11                        _UINT32_(7) 
+#define MUX_PA07P_PTC_DRV11                        _UINT32_(15)
+#define PINMUX_PA07P_PTC_DRV11                     ((PIN_PA07P_PTC_DRV11 << 16) | MUX_PA07P_PTC_DRV11)
+#define PORT_PA07P_PTC_DRV11                       (_UINT32_(1) << 7)
+
+#define PIN_PA08P_PTC_DRV12                        _UINT32_(8) 
+#define MUX_PA08P_PTC_DRV12                        _UINT32_(15)
+#define PINMUX_PA08P_PTC_DRV12                     ((PIN_PA08P_PTC_DRV12 << 16) | MUX_PA08P_PTC_DRV12)
+#define PORT_PA08P_PTC_DRV12                       (_UINT32_(1) << 8)
+
+#define PIN_PA09P_PTC_DRV13                        _UINT32_(9) 
+#define MUX_PA09P_PTC_DRV13                        _UINT32_(15)
+#define PINMUX_PA09P_PTC_DRV13                     ((PIN_PA09P_PTC_DRV13 << 16) | MUX_PA09P_PTC_DRV13)
+#define PORT_PA09P_PTC_DRV13                       (_UINT32_(1) << 9)
+
+#define PIN_PB00P_PTC_DRV14                        _UINT32_(32)
+#define MUX_PB00P_PTC_DRV14                        _UINT32_(15)
+#define PINMUX_PB00P_PTC_DRV14                     ((PIN_PB00P_PTC_DRV14 << 16) | MUX_PB00P_PTC_DRV14)
+#define PORT_PB00P_PTC_DRV14                       (_UINT32_(1) << 0)
+
+#define PIN_PB03P_PTC_DRV15                        _UINT32_(35)
+#define MUX_PB03P_PTC_DRV15                        _UINT32_(15)
+#define PINMUX_PB03P_PTC_DRV15                     ((PIN_PB03P_PTC_DRV15 << 16) | MUX_PB03P_PTC_DRV15)
+#define PORT_PB03P_PTC_DRV15                       (_UINT32_(1) << 3)
+
+#define PIN_PB04P_PTC_DRV16                        _UINT32_(36)
+#define MUX_PB04P_PTC_DRV16                        _UINT32_(15)
+#define PINMUX_PB04P_PTC_DRV16                     ((PIN_PB04P_PTC_DRV16 << 16) | MUX_PB04P_PTC_DRV16)
+#define PORT_PB04P_PTC_DRV16                       (_UINT32_(1) << 4)
+
+#define PIN_PB05P_PTC_DRV17                        _UINT32_(37)
+#define MUX_PB05P_PTC_DRV17                        _UINT32_(15)
+#define PINMUX_PB05P_PTC_DRV17                     ((PIN_PB05P_PTC_DRV17 << 16) | MUX_PB05P_PTC_DRV17)
+#define PORT_PB05P_PTC_DRV17                       (_UINT32_(1) << 5)
+
+#define PIN_PB06P_PTC_DRV18                        _UINT32_(38)
+#define MUX_PB06P_PTC_DRV18                        _UINT32_(15)
+#define PINMUX_PB06P_PTC_DRV18                     ((PIN_PB06P_PTC_DRV18 << 16) | MUX_PB06P_PTC_DRV18)
+#define PORT_PB06P_PTC_DRV18                       (_UINT32_(1) << 6)
+
+#define PIN_PC00P_PTC_DRV19                        _UINT32_(64)
+#define MUX_PC00P_PTC_DRV19                        _UINT32_(15)
+#define PINMUX_PC00P_PTC_DRV19                     ((PIN_PC00P_PTC_DRV19 << 16) | MUX_PC00P_PTC_DRV19)
+#define PORT_PC00P_PTC_DRV19                       (_UINT32_(1) << 0)
+
+#define PIN_PC01P_PTC_DRV20                        _UINT32_(65)
+#define MUX_PC01P_PTC_DRV20                        _UINT32_(15)
+#define PINMUX_PC01P_PTC_DRV20                     ((PIN_PC01P_PTC_DRV20 << 16) | MUX_PC01P_PTC_DRV20)
+#define PORT_PC01P_PTC_DRV20                       (_UINT32_(1) << 1)
+
+#define PIN_PC02P_PTC_DRV21                        _UINT32_(66)
+#define MUX_PC02P_PTC_DRV21                        _UINT32_(15)
+#define PINMUX_PC02P_PTC_DRV21                     ((PIN_PC02P_PTC_DRV21 << 16) | MUX_PC02P_PTC_DRV21)
+#define PORT_PC02P_PTC_DRV21                       (_UINT32_(1) << 2)
+
+#define PIN_PA10P_PTC_DRV22                        _UINT32_(10)
+#define MUX_PA10P_PTC_DRV22                        _UINT32_(15)
+#define PINMUX_PA10P_PTC_DRV22                     ((PIN_PA10P_PTC_DRV22 << 16) | MUX_PA10P_PTC_DRV22)
+#define PORT_PA10P_PTC_DRV22                       (_UINT32_(1) << 10)
+
+#define PIN_PA11P_PTC_DRV23                        _UINT32_(11)
+#define MUX_PA11P_PTC_DRV23                        _UINT32_(15)
+#define PINMUX_PA11P_PTC_DRV23                     ((PIN_PA11P_PTC_DRV23 << 16) | MUX_PA11P_PTC_DRV23)
+#define PORT_PA11P_PTC_DRV23                       (_UINT32_(1) << 11)
+
+#define PIN_PA12P_PTC_DRV24                        _UINT32_(12)
+#define MUX_PA12P_PTC_DRV24                        _UINT32_(15)
+#define PINMUX_PA12P_PTC_DRV24                     ((PIN_PA12P_PTC_DRV24 << 16) | MUX_PA12P_PTC_DRV24)
+#define PORT_PA12P_PTC_DRV24                       (_UINT32_(1) << 12)
+
+#define PIN_PA13P_PTC_DRV25                        _UINT32_(13)
+#define MUX_PA13P_PTC_DRV25                        _UINT32_(15)
+#define PINMUX_PA13P_PTC_DRV25                     ((PIN_PA13P_PTC_DRV25 << 16) | MUX_PA13P_PTC_DRV25)
+#define PORT_PA13P_PTC_DRV25                       (_UINT32_(1) << 13)
+
+#define PIN_PB07P_PTC_DRV26                        _UINT32_(39)
+#define MUX_PB07P_PTC_DRV26                        _UINT32_(15)
+#define PINMUX_PB07P_PTC_DRV26                     ((PIN_PB07P_PTC_DRV26 << 16) | MUX_PB07P_PTC_DRV26)
+#define PORT_PB07P_PTC_DRV26                       (_UINT32_(1) << 7)
+
+#define PIN_PB08P_PTC_DRV27                        _UINT32_(40)
+#define MUX_PB08P_PTC_DRV27                        _UINT32_(15)
+#define PINMUX_PB08P_PTC_DRV27                     ((PIN_PB08P_PTC_DRV27 << 16) | MUX_PB08P_PTC_DRV27)
+#define PORT_PB08P_PTC_DRV27                       (_UINT32_(1) << 8)
+
+#define PIN_PB09P_PTC_DRV28                        _UINT32_(41)
+#define MUX_PB09P_PTC_DRV28                        _UINT32_(15)
+#define PINMUX_PB09P_PTC_DRV28                     ((PIN_PB09P_PTC_DRV28 << 16) | MUX_PB09P_PTC_DRV28)
+#define PORT_PB09P_PTC_DRV28                       (_UINT32_(1) << 9)
+
+#define PIN_PB10P_PTC_DRV29                        _UINT32_(42)
+#define MUX_PB10P_PTC_DRV29                        _UINT32_(15)
+#define PINMUX_PB10P_PTC_DRV29                     ((PIN_PB10P_PTC_DRV29 << 16) | MUX_PB10P_PTC_DRV29)
+#define PORT_PB10P_PTC_DRV29                       (_UINT32_(1) << 10)
+
+#define PIN_PC09P_PTC_DRV30                        _UINT32_(73)
+#define MUX_PC09P_PTC_DRV30                        _UINT32_(15)
+#define PINMUX_PC09P_PTC_DRV30                     ((PIN_PC09P_PTC_DRV30 << 16) | MUX_PC09P_PTC_DRV30)
+#define PORT_PC09P_PTC_DRV30                       (_UINT32_(1) << 9)
+
+#define PIN_PC10P_PTC_DRV31                        _UINT32_(74)
+#define MUX_PC10P_PTC_DRV31                        _UINT32_(15)
+#define PINMUX_PC10P_PTC_DRV31                     ((PIN_PC10P_PTC_DRV31 << 16) | MUX_PC10P_PTC_DRV31)
+#define PORT_PC10P_PTC_DRV31                       (_UINT32_(1) << 10)
+
+#define PIN_PC03P_PTC_ECI0                         _UINT32_(67)
+#define MUX_PC03P_PTC_ECI0                         _UINT32_(15)
+#define PINMUX_PC03P_PTC_ECI0                      ((PIN_PC03P_PTC_ECI0 << 16) | MUX_PC03P_PTC_ECI0)
+#define PORT_PC03P_PTC_ECI0                        (_UINT32_(1) << 3)
+
+#define PIN_PC04P_PTC_ECI1                         _UINT32_(68)
+#define MUX_PC04P_PTC_ECI1                         _UINT32_(15)
+#define PINMUX_PC04P_PTC_ECI1                      ((PIN_PC04P_PTC_ECI1 << 16) | MUX_PC04P_PTC_ECI1)
+#define PORT_PC04P_PTC_ECI1                        (_UINT32_(1) << 4)
+
+#define PIN_PD06P_PTC_PTCXY0                       _UINT32_(102)
+#define MUX_PD06P_PTC_PTCXY0                       _UINT32_(15)
+#define PINMUX_PD06P_PTC_PTCXY0                    ((PIN_PD06P_PTC_PTCXY0 << 16) | MUX_PD06P_PTC_PTCXY0)
+#define PORT_PD06P_PTC_PTCXY0                      (_UINT32_(1) << 6)
+
+#define PIN_PD07P_PTC_PTCXY1                       _UINT32_(103)
+#define MUX_PD07P_PTC_PTCXY1                       _UINT32_(15)
+#define PINMUX_PD07P_PTC_PTCXY1                    ((PIN_PD07P_PTC_PTCXY1 << 16) | MUX_PD07P_PTC_PTCXY1)
+#define PORT_PD07P_PTC_PTCXY1                      (_UINT32_(1) << 7)
+
+#define PIN_PD08P_PTC_PTCXY2                       _UINT32_(104)
+#define MUX_PD08P_PTC_PTCXY2                       _UINT32_(15)
+#define PINMUX_PD08P_PTC_PTCXY2                    ((PIN_PD08P_PTC_PTCXY2 << 16) | MUX_PD08P_PTC_PTCXY2)
+#define PORT_PD08P_PTC_PTCXY2                      (_UINT32_(1) << 8)
+
+#define PIN_PD09P_PTC_PTCXY3                       _UINT32_(105)
+#define MUX_PD09P_PTC_PTCXY3                       _UINT32_(15)
+#define PINMUX_PD09P_PTC_PTCXY3                    ((PIN_PD09P_PTC_PTCXY3 << 16) | MUX_PD09P_PTC_PTCXY3)
+#define PORT_PD09P_PTC_PTCXY3                      (_UINT32_(1) << 9)
+
+#define PIN_PA00P_PTC_PTCXY4                       _UINT32_(0) 
+#define MUX_PA00P_PTC_PTCXY4                       _UINT32_(15)
+#define PINMUX_PA00P_PTC_PTCXY4                    ((PIN_PA00P_PTC_PTCXY4 << 16) | MUX_PA00P_PTC_PTCXY4)
+#define PORT_PA00P_PTC_PTCXY4                      (_UINT32_(1) << 0)
+
+#define PIN_PA01P_PTC_PTCXY5                       _UINT32_(1) 
+#define MUX_PA01P_PTC_PTCXY5                       _UINT32_(15)
+#define PINMUX_PA01P_PTC_PTCXY5                    ((PIN_PA01P_PTC_PTCXY5 << 16) | MUX_PA01P_PTC_PTCXY5)
+#define PORT_PA01P_PTC_PTCXY5                      (_UINT32_(1) << 1)
+
+#define PIN_PA02P_PTC_PTCXY6                       _UINT32_(2) 
+#define MUX_PA02P_PTC_PTCXY6                       _UINT32_(15)
+#define PINMUX_PA02P_PTC_PTCXY6                    ((PIN_PA02P_PTC_PTCXY6 << 16) | MUX_PA02P_PTC_PTCXY6)
+#define PORT_PA02P_PTC_PTCXY6                      (_UINT32_(1) << 2)
+
+#define PIN_PA03P_PTC_PTCXY7                       _UINT32_(3) 
+#define MUX_PA03P_PTC_PTCXY7                       _UINT32_(15)
+#define PINMUX_PA03P_PTC_PTCXY7                    ((PIN_PA03P_PTC_PTCXY7 << 16) | MUX_PA03P_PTC_PTCXY7)
+#define PORT_PA03P_PTC_PTCXY7                      (_UINT32_(1) << 3)
+
+#define PIN_PA04P_PTC_PTCXY8                       _UINT32_(4) 
+#define MUX_PA04P_PTC_PTCXY8                       _UINT32_(15)
+#define PINMUX_PA04P_PTC_PTCXY8                    ((PIN_PA04P_PTC_PTCXY8 << 16) | MUX_PA04P_PTC_PTCXY8)
+#define PORT_PA04P_PTC_PTCXY8                      (_UINT32_(1) << 4)
+
+#define PIN_PA05P_PTC_PTCXY9                       _UINT32_(5) 
+#define MUX_PA05P_PTC_PTCXY9                       _UINT32_(15)
+#define PINMUX_PA05P_PTC_PTCXY9                    ((PIN_PA05P_PTC_PTCXY9 << 16) | MUX_PA05P_PTC_PTCXY9)
+#define PORT_PA05P_PTC_PTCXY9                      (_UINT32_(1) << 5)
+
+#define PIN_PA06P_PTC_PTCXY10                      _UINT32_(6) 
+#define MUX_PA06P_PTC_PTCXY10                      _UINT32_(15)
+#define PINMUX_PA06P_PTC_PTCXY10                   ((PIN_PA06P_PTC_PTCXY10 << 16) | MUX_PA06P_PTC_PTCXY10)
+#define PORT_PA06P_PTC_PTCXY10                     (_UINT32_(1) << 6)
+
+#define PIN_PA07P_PTC_PTCXY11                      _UINT32_(7) 
+#define MUX_PA07P_PTC_PTCXY11                      _UINT32_(15)
+#define PINMUX_PA07P_PTC_PTCXY11                   ((PIN_PA07P_PTC_PTCXY11 << 16) | MUX_PA07P_PTC_PTCXY11)
+#define PORT_PA07P_PTC_PTCXY11                     (_UINT32_(1) << 7)
+
+#define PIN_PA08P_PTC_PTCXY12                      _UINT32_(8) 
+#define MUX_PA08P_PTC_PTCXY12                      _UINT32_(15)
+#define PINMUX_PA08P_PTC_PTCXY12                   ((PIN_PA08P_PTC_PTCXY12 << 16) | MUX_PA08P_PTC_PTCXY12)
+#define PORT_PA08P_PTC_PTCXY12                     (_UINT32_(1) << 8)
+
+#define PIN_PA09P_PTC_PTCXY13                      _UINT32_(9) 
+#define MUX_PA09P_PTC_PTCXY13                      _UINT32_(15)
+#define PINMUX_PA09P_PTC_PTCXY13                   ((PIN_PA09P_PTC_PTCXY13 << 16) | MUX_PA09P_PTC_PTCXY13)
+#define PORT_PA09P_PTC_PTCXY13                     (_UINT32_(1) << 9)
+
+#define PIN_PB00P_PTC_PTCXY14                      _UINT32_(32)
+#define MUX_PB00P_PTC_PTCXY14                      _UINT32_(15)
+#define PINMUX_PB00P_PTC_PTCXY14                   ((PIN_PB00P_PTC_PTCXY14 << 16) | MUX_PB00P_PTC_PTCXY14)
+#define PORT_PB00P_PTC_PTCXY14                     (_UINT32_(1) << 0)
+
+#define PIN_PB03P_PTC_PTCXY15                      _UINT32_(35)
+#define MUX_PB03P_PTC_PTCXY15                      _UINT32_(15)
+#define PINMUX_PB03P_PTC_PTCXY15                   ((PIN_PB03P_PTC_PTCXY15 << 16) | MUX_PB03P_PTC_PTCXY15)
+#define PORT_PB03P_PTC_PTCXY15                     (_UINT32_(1) << 3)
+
+#define PIN_PB04P_PTC_PTCXY16                      _UINT32_(36)
+#define MUX_PB04P_PTC_PTCXY16                      _UINT32_(15)
+#define PINMUX_PB04P_PTC_PTCXY16                   ((PIN_PB04P_PTC_PTCXY16 << 16) | MUX_PB04P_PTC_PTCXY16)
+#define PORT_PB04P_PTC_PTCXY16                     (_UINT32_(1) << 4)
+
+#define PIN_PB05P_PTC_PTCXY17                      _UINT32_(37)
+#define MUX_PB05P_PTC_PTCXY17                      _UINT32_(15)
+#define PINMUX_PB05P_PTC_PTCXY17                   ((PIN_PB05P_PTC_PTCXY17 << 16) | MUX_PB05P_PTC_PTCXY17)
+#define PORT_PB05P_PTC_PTCXY17                     (_UINT32_(1) << 5)
+
+#define PIN_PB06P_PTC_PTCXY18                      _UINT32_(38)
+#define MUX_PB06P_PTC_PTCXY18                      _UINT32_(15)
+#define PINMUX_PB06P_PTC_PTCXY18                   ((PIN_PB06P_PTC_PTCXY18 << 16) | MUX_PB06P_PTC_PTCXY18)
+#define PORT_PB06P_PTC_PTCXY18                     (_UINT32_(1) << 6)
+
+#define PIN_PC00P_PTC_PTCXY19                      _UINT32_(64)
+#define MUX_PC00P_PTC_PTCXY19                      _UINT32_(15)
+#define PINMUX_PC00P_PTC_PTCXY19                   ((PIN_PC00P_PTC_PTCXY19 << 16) | MUX_PC00P_PTC_PTCXY19)
+#define PORT_PC00P_PTC_PTCXY19                     (_UINT32_(1) << 0)
+
+#define PIN_PC01P_PTC_PTCXY20                      _UINT32_(65)
+#define MUX_PC01P_PTC_PTCXY20                      _UINT32_(15)
+#define PINMUX_PC01P_PTC_PTCXY20                   ((PIN_PC01P_PTC_PTCXY20 << 16) | MUX_PC01P_PTC_PTCXY20)
+#define PORT_PC01P_PTC_PTCXY20                     (_UINT32_(1) << 1)
+
+#define PIN_PC02P_PTC_PTCXY21                      _UINT32_(66)
+#define MUX_PC02P_PTC_PTCXY21                      _UINT32_(15)
+#define PINMUX_PC02P_PTC_PTCXY21                   ((PIN_PC02P_PTC_PTCXY21 << 16) | MUX_PC02P_PTC_PTCXY21)
+#define PORT_PC02P_PTC_PTCXY21                     (_UINT32_(1) << 2)
+
+#define PIN_PA10P_PTC_PTCXY22                      _UINT32_(10)
+#define MUX_PA10P_PTC_PTCXY22                      _UINT32_(15)
+#define PINMUX_PA10P_PTC_PTCXY22                   ((PIN_PA10P_PTC_PTCXY22 << 16) | MUX_PA10P_PTC_PTCXY22)
+#define PORT_PA10P_PTC_PTCXY22                     (_UINT32_(1) << 10)
+
+#define PIN_PA11P_PTC_PTCXY23                      _UINT32_(11)
+#define MUX_PA11P_PTC_PTCXY23                      _UINT32_(15)
+#define PINMUX_PA11P_PTC_PTCXY23                   ((PIN_PA11P_PTC_PTCXY23 << 16) | MUX_PA11P_PTC_PTCXY23)
+#define PORT_PA11P_PTC_PTCXY23                     (_UINT32_(1) << 11)
+
+#define PIN_PA12P_PTC_PTCXY24                      _UINT32_(12)
+#define MUX_PA12P_PTC_PTCXY24                      _UINT32_(15)
+#define PINMUX_PA12P_PTC_PTCXY24                   ((PIN_PA12P_PTC_PTCXY24 << 16) | MUX_PA12P_PTC_PTCXY24)
+#define PORT_PA12P_PTC_PTCXY24                     (_UINT32_(1) << 12)
+
+#define PIN_PA13P_PTC_PTCXY25                      _UINT32_(13)
+#define MUX_PA13P_PTC_PTCXY25                      _UINT32_(15)
+#define PINMUX_PA13P_PTC_PTCXY25                   ((PIN_PA13P_PTC_PTCXY25 << 16) | MUX_PA13P_PTC_PTCXY25)
+#define PORT_PA13P_PTC_PTCXY25                     (_UINT32_(1) << 13)
+
+#define PIN_PB07P_PTC_PTCXY26                      _UINT32_(39)
+#define MUX_PB07P_PTC_PTCXY26                      _UINT32_(15)
+#define PINMUX_PB07P_PTC_PTCXY26                   ((PIN_PB07P_PTC_PTCXY26 << 16) | MUX_PB07P_PTC_PTCXY26)
+#define PORT_PB07P_PTC_PTCXY26                     (_UINT32_(1) << 7)
+
+#define PIN_PB08P_PTC_PTCXY27                      _UINT32_(40)
+#define MUX_PB08P_PTC_PTCXY27                      _UINT32_(15)
+#define PINMUX_PB08P_PTC_PTCXY27                   ((PIN_PB08P_PTC_PTCXY27 << 16) | MUX_PB08P_PTC_PTCXY27)
+#define PORT_PB08P_PTC_PTCXY27                     (_UINT32_(1) << 8)
+
+#define PIN_PB09P_PTC_PTCXY28                      _UINT32_(41)
+#define MUX_PB09P_PTC_PTCXY28                      _UINT32_(15)
+#define PINMUX_PB09P_PTC_PTCXY28                   ((PIN_PB09P_PTC_PTCXY28 << 16) | MUX_PB09P_PTC_PTCXY28)
+#define PORT_PB09P_PTC_PTCXY28                     (_UINT32_(1) << 9)
+
+#define PIN_PB10P_PTC_PTCXY29                      _UINT32_(42)
+#define MUX_PB10P_PTC_PTCXY29                      _UINT32_(15)
+#define PINMUX_PB10P_PTC_PTCXY29                   ((PIN_PB10P_PTC_PTCXY29 << 16) | MUX_PB10P_PTC_PTCXY29)
+#define PORT_PB10P_PTC_PTCXY29                     (_UINT32_(1) << 10)
+
+#define PIN_PC09P_PTC_PTCXY30                      _UINT32_(73)
+#define MUX_PC09P_PTC_PTCXY30                      _UINT32_(15)
+#define PINMUX_PC09P_PTC_PTCXY30                   ((PIN_PC09P_PTC_PTCXY30 << 16) | MUX_PC09P_PTC_PTCXY30)
+#define PORT_PC09P_PTC_PTCXY30                     (_UINT32_(1) << 9)
+
+#define PIN_PC10P_PTC_PTCXY31                      _UINT32_(74)
+#define MUX_PC10P_PTC_PTCXY31                      _UINT32_(15)
+#define PINMUX_PC10P_PTC_PTCXY31                   ((PIN_PC10P_PTC_PTCXY31 << 16) | MUX_PC10P_PTC_PTCXY31)
+#define PORT_PC10P_PTC_PTCXY31                     (_UINT32_(1) << 10)
+
+/* ================= PORT definition for SERCOM0 peripheral ================= */
+#define PIN_PC00D_SERCOM0_PAD0                     _UINT32_(64)
+#define MUX_PC00D_SERCOM0_PAD0                     _UINT32_(3) 
+#define PINMUX_PC00D_SERCOM0_PAD0                  ((PIN_PC00D_SERCOM0_PAD0 << 16) | MUX_PC00D_SERCOM0_PAD0)
+#define PORT_PC00D_SERCOM0_PAD0                    (_UINT32_(1) << 0)
+
+#define PIN_PC01D_SERCOM0_PAD1                     _UINT32_(65)
+#define MUX_PC01D_SERCOM0_PAD1                     _UINT32_(3) 
+#define PINMUX_PC01D_SERCOM0_PAD1                  ((PIN_PC01D_SERCOM0_PAD1 << 16) | MUX_PC01D_SERCOM0_PAD1)
+#define PORT_PC01D_SERCOM0_PAD1                    (_UINT32_(1) << 1)
+
+#define PIN_PC02D_SERCOM0_PAD2                     _UINT32_(66)
+#define MUX_PC02D_SERCOM0_PAD2                     _UINT32_(3) 
+#define PINMUX_PC02D_SERCOM0_PAD2                  ((PIN_PC02D_SERCOM0_PAD2 << 16) | MUX_PC02D_SERCOM0_PAD2)
+#define PORT_PC02D_SERCOM0_PAD2                    (_UINT32_(1) << 2)
+
+#define PIN_PC03D_SERCOM0_PAD3                     _UINT32_(67)
+#define MUX_PC03D_SERCOM0_PAD3                     _UINT32_(3) 
+#define PINMUX_PC03D_SERCOM0_PAD3                  ((PIN_PC03D_SERCOM0_PAD3 << 16) | MUX_PC03D_SERCOM0_PAD3)
+#define PORT_PC03D_SERCOM0_PAD3                    (_UINT32_(1) << 3)
+
+/* ================= PORT definition for SERCOM1 peripheral ================= */
+#define PIN_PD01D_SERCOM1_PAD0                     _UINT32_(97)
+#define MUX_PD01D_SERCOM1_PAD0                     _UINT32_(3) 
+#define PINMUX_PD01D_SERCOM1_PAD0                  ((PIN_PD01D_SERCOM1_PAD0 << 16) | MUX_PD01D_SERCOM1_PAD0)
+#define PORT_PD01D_SERCOM1_PAD0                    (_UINT32_(1) << 1)
+
+#define PIN_PD00D_SERCOM1_PAD1                     _UINT32_(96)
+#define MUX_PD00D_SERCOM1_PAD1                     _UINT32_(3) 
+#define PINMUX_PD00D_SERCOM1_PAD1                  ((PIN_PD00D_SERCOM1_PAD1 << 16) | MUX_PD00D_SERCOM1_PAD1)
+#define PORT_PD00D_SERCOM1_PAD1                    (_UINT32_(1) << 0)
+
+#define PIN_PC06D_SERCOM1_PAD2                     _UINT32_(70)
+#define MUX_PC06D_SERCOM1_PAD2                     _UINT32_(3) 
+#define PINMUX_PC06D_SERCOM1_PAD2                  ((PIN_PC06D_SERCOM1_PAD2 << 16) | MUX_PC06D_SERCOM1_PAD2)
+#define PORT_PC06D_SERCOM1_PAD2                    (_UINT32_(1) << 6)
+
+#define PIN_PD10D_SERCOM1_PAD2                     _UINT32_(106)
+#define MUX_PD10D_SERCOM1_PAD2                     _UINT32_(3) 
+#define PINMUX_PD10D_SERCOM1_PAD2                  ((PIN_PD10D_SERCOM1_PAD2 << 16) | MUX_PD10D_SERCOM1_PAD2)
+#define PORT_PD10D_SERCOM1_PAD2                    (_UINT32_(1) << 10)
+
+#define PIN_PC05D_SERCOM1_PAD3                     _UINT32_(69)
+#define MUX_PC05D_SERCOM1_PAD3                     _UINT32_(3) 
+#define PINMUX_PC05D_SERCOM1_PAD3                  ((PIN_PC05D_SERCOM1_PAD3 << 16) | MUX_PC05D_SERCOM1_PAD3)
+#define PORT_PC05D_SERCOM1_PAD3                    (_UINT32_(1) << 5)
+
+#define PIN_PD11D_SERCOM1_PAD3                     _UINT32_(107)
+#define MUX_PD11D_SERCOM1_PAD3                     _UINT32_(3) 
+#define PINMUX_PD11D_SERCOM1_PAD3                  ((PIN_PD11D_SERCOM1_PAD3 << 16) | MUX_PD11D_SERCOM1_PAD3)
+#define PORT_PD11D_SERCOM1_PAD3                    (_UINT32_(1) << 11)
+
+/* ================= PORT definition for SERCOM2 peripheral ================= */
+#define PIN_PC04D_SERCOM2_PAD0                     _UINT32_(68)
+#define MUX_PC04D_SERCOM2_PAD0                     _UINT32_(3) 
+#define PINMUX_PC04D_SERCOM2_PAD0                  ((PIN_PC04D_SERCOM2_PAD0 << 16) | MUX_PC04D_SERCOM2_PAD0)
+#define PORT_PC04D_SERCOM2_PAD0                    (_UINT32_(1) << 4)
+
+#define PIN_PD06D_SERCOM2_PAD1                     _UINT32_(102)
+#define MUX_PD06D_SERCOM2_PAD1                     _UINT32_(3) 
+#define PINMUX_PD06D_SERCOM2_PAD1                  ((PIN_PD06D_SERCOM2_PAD1 << 16) | MUX_PD06D_SERCOM2_PAD1)
+#define PORT_PD06D_SERCOM2_PAD1                    (_UINT32_(1) << 6)
+
+#define PIN_PD07D_SERCOM2_PAD2                     _UINT32_(103)
+#define MUX_PD07D_SERCOM2_PAD2                     _UINT32_(3) 
+#define PINMUX_PD07D_SERCOM2_PAD2                  ((PIN_PD07D_SERCOM2_PAD2 << 16) | MUX_PD07D_SERCOM2_PAD2)
+#define PORT_PD07D_SERCOM2_PAD2                    (_UINT32_(1) << 7)
+
+#define PIN_PD08D_SERCOM2_PAD3                     _UINT32_(104)
+#define MUX_PD08D_SERCOM2_PAD3                     _UINT32_(3) 
+#define PINMUX_PD08D_SERCOM2_PAD3                  ((PIN_PD08D_SERCOM2_PAD3 << 16) | MUX_PD08D_SERCOM2_PAD3)
+#define PORT_PD08D_SERCOM2_PAD3                    (_UINT32_(1) << 8)
+
+/* ================= PORT definition for SERCOM3 peripheral ================= */
+#define PIN_PD09D_SERCOM3_PAD0                     _UINT32_(105)
+#define MUX_PD09D_SERCOM3_PAD0                     _UINT32_(3) 
+#define PINMUX_PD09D_SERCOM3_PAD0                  ((PIN_PD09D_SERCOM3_PAD0 << 16) | MUX_PD09D_SERCOM3_PAD0)
+#define PORT_PD09D_SERCOM3_PAD0                    (_UINT32_(1) << 9)
+
+#define PIN_PA00D_SERCOM3_PAD1                     _UINT32_(0) 
+#define MUX_PA00D_SERCOM3_PAD1                     _UINT32_(3) 
+#define PINMUX_PA00D_SERCOM3_PAD1                  ((PIN_PA00D_SERCOM3_PAD1 << 16) | MUX_PA00D_SERCOM3_PAD1)
+#define PORT_PA00D_SERCOM3_PAD1                    (_UINT32_(1) << 0)
+
+#define PIN_PA01D_SERCOM3_PAD2                     _UINT32_(1) 
+#define MUX_PA01D_SERCOM3_PAD2                     _UINT32_(3) 
+#define PINMUX_PA01D_SERCOM3_PAD2                  ((PIN_PA01D_SERCOM3_PAD2 << 16) | MUX_PA01D_SERCOM3_PAD2)
+#define PORT_PA01D_SERCOM3_PAD2                    (_UINT32_(1) << 1)
+
+#define PIN_PA02D_SERCOM3_PAD3                     _UINT32_(2) 
+#define MUX_PA02D_SERCOM3_PAD3                     _UINT32_(3) 
+#define PINMUX_PA02D_SERCOM3_PAD3                  ((PIN_PA02D_SERCOM3_PAD3 << 16) | MUX_PA02D_SERCOM3_PAD3)
+#define PORT_PA02D_SERCOM3_PAD3                    (_UINT32_(1) << 2)
+
+/* ================= PORT definition for SERCOM4 peripheral ================= */
+#define PIN_PA03D_SERCOM4_PAD0                     _UINT32_(3) 
+#define MUX_PA03D_SERCOM4_PAD0                     _UINT32_(3) 
+#define PINMUX_PA03D_SERCOM4_PAD0                  ((PIN_PA03D_SERCOM4_PAD0 << 16) | MUX_PA03D_SERCOM4_PAD0)
+#define PORT_PA03D_SERCOM4_PAD0                    (_UINT32_(1) << 3)
+
+#define PIN_PA04D_SERCOM4_PAD1                     _UINT32_(4) 
+#define MUX_PA04D_SERCOM4_PAD1                     _UINT32_(3) 
+#define PINMUX_PA04D_SERCOM4_PAD1                  ((PIN_PA04D_SERCOM4_PAD1 << 16) | MUX_PA04D_SERCOM4_PAD1)
+#define PORT_PA04D_SERCOM4_PAD1                    (_UINT32_(1) << 4)
+
+#define PIN_PA05D_SERCOM4_PAD2                     _UINT32_(5) 
+#define MUX_PA05D_SERCOM4_PAD2                     _UINT32_(3) 
+#define PINMUX_PA05D_SERCOM4_PAD2                  ((PIN_PA05D_SERCOM4_PAD2 << 16) | MUX_PA05D_SERCOM4_PAD2)
+#define PORT_PA05D_SERCOM4_PAD2                    (_UINT32_(1) << 5)
+
+#define PIN_PA06D_SERCOM4_PAD3                     _UINT32_(6) 
+#define MUX_PA06D_SERCOM4_PAD3                     _UINT32_(3) 
+#define PINMUX_PA06D_SERCOM4_PAD3                  ((PIN_PA06D_SERCOM4_PAD3 << 16) | MUX_PA06D_SERCOM4_PAD3)
+#define PORT_PA06D_SERCOM4_PAD3                    (_UINT32_(1) << 6)
+
+/* ================= PORT definition for SERCOM5 peripheral ================= */
+#define PIN_PB03D_SERCOM5_PAD0                     _UINT32_(35)
+#define MUX_PB03D_SERCOM5_PAD0                     _UINT32_(3) 
+#define PINMUX_PB03D_SERCOM5_PAD0                  ((PIN_PB03D_SERCOM5_PAD0 << 16) | MUX_PB03D_SERCOM5_PAD0)
+#define PORT_PB03D_SERCOM5_PAD0                    (_UINT32_(1) << 3)
+
+#define PIN_PB04D_SERCOM5_PAD1                     _UINT32_(36)
+#define MUX_PB04D_SERCOM5_PAD1                     _UINT32_(3) 
+#define PINMUX_PB04D_SERCOM5_PAD1                  ((PIN_PB04D_SERCOM5_PAD1 << 16) | MUX_PB04D_SERCOM5_PAD1)
+#define PORT_PB04D_SERCOM5_PAD1                    (_UINT32_(1) << 4)
+
+#define PIN_PB05D_SERCOM5_PAD2                     _UINT32_(37)
+#define MUX_PB05D_SERCOM5_PAD2                     _UINT32_(3) 
+#define PINMUX_PB05D_SERCOM5_PAD2                  ((PIN_PB05D_SERCOM5_PAD2 << 16) | MUX_PB05D_SERCOM5_PAD2)
+#define PORT_PB05D_SERCOM5_PAD2                    (_UINT32_(1) << 5)
+
+#define PIN_PB06D_SERCOM5_PAD3                     _UINT32_(38)
+#define MUX_PB06D_SERCOM5_PAD3                     _UINT32_(3) 
+#define PINMUX_PB06D_SERCOM5_PAD3                  ((PIN_PB06D_SERCOM5_PAD3 << 16) | MUX_PB06D_SERCOM5_PAD3)
+#define PORT_PB06D_SERCOM5_PAD3                    (_UINT32_(1) << 6)
+
+/* ================== PORT definition for TCC0 peripheral =================== */
+#define PIN_PC00F_TCC0_WO0                         _UINT32_(64)
+#define MUX_PC00F_TCC0_WO0                         _UINT32_(5) 
+#define PINMUX_PC00F_TCC0_WO0                      ((PIN_PC00F_TCC0_WO0 << 16) | MUX_PC00F_TCC0_WO0)
+#define PORT_PC00F_TCC0_WO0                        (_UINT32_(1) << 0)
+
+#define PIN_PC01F_TCC0_WO1                         _UINT32_(65)
+#define MUX_PC01F_TCC0_WO1                         _UINT32_(5) 
+#define PINMUX_PC01F_TCC0_WO1                      ((PIN_PC01F_TCC0_WO1 << 16) | MUX_PC01F_TCC0_WO1)
+#define PORT_PC01F_TCC0_WO1                        (_UINT32_(1) << 1)
+
+/* ================== PORT definition for TCC1 peripheral =================== */
+#define PIN_PC02F_TCC1_WO0                         _UINT32_(66)
+#define MUX_PC02F_TCC1_WO0                         _UINT32_(5) 
+#define PINMUX_PC02F_TCC1_WO0                      ((PIN_PC02F_TCC1_WO0 << 16) | MUX_PC02F_TCC1_WO0)
+#define PORT_PC02F_TCC1_WO0                        (_UINT32_(1) << 2)
+
+#define PIN_PC09F_TCC1_WO0                         _UINT32_(73)
+#define MUX_PC09F_TCC1_WO0                         _UINT32_(5) 
+#define PINMUX_PC09F_TCC1_WO0                      ((PIN_PC09F_TCC1_WO0 << 16) | MUX_PC09F_TCC1_WO0)
+#define PORT_PC09F_TCC1_WO0                        (_UINT32_(1) << 9)
+
+#define PIN_PC03F_TCC1_WO1                         _UINT32_(67)
+#define MUX_PC03F_TCC1_WO1                         _UINT32_(5) 
+#define PINMUX_PC03F_TCC1_WO1                      ((PIN_PC03F_TCC1_WO1 << 16) | MUX_PC03F_TCC1_WO1)
+#define PORT_PC03F_TCC1_WO1                        (_UINT32_(1) << 3)
+
+#define PIN_PC10F_TCC1_WO1                         _UINT32_(74)
+#define MUX_PC10F_TCC1_WO1                         _UINT32_(5) 
+#define PINMUX_PC10F_TCC1_WO1                      ((PIN_PC10F_TCC1_WO1 << 16) | MUX_PC10F_TCC1_WO1)
+#define PORT_PC10F_TCC1_WO1                        (_UINT32_(1) << 10)
+
+/* ================== PORT definition for TCC2 peripheral =================== */
+#define PIN_PB09F_TCC2_WO0                         _UINT32_(41)
+#define MUX_PB09F_TCC2_WO0                         _UINT32_(5) 
+#define PINMUX_PB09F_TCC2_WO0                      ((PIN_PB09F_TCC2_WO0 << 16) | MUX_PB09F_TCC2_WO0)
+#define PORT_PB09F_TCC2_WO0                        (_UINT32_(1) << 9)
+
+#define PIN_PC04F_TCC2_WO0                         _UINT32_(68)
+#define MUX_PC04F_TCC2_WO0                         _UINT32_(5) 
+#define PINMUX_PC04F_TCC2_WO0                      ((PIN_PC04F_TCC2_WO0 << 16) | MUX_PC04F_TCC2_WO0)
+#define PORT_PC04F_TCC2_WO0                        (_UINT32_(1) << 4)
+
+#define PIN_PB08F_TCC2_WO1                         _UINT32_(40)
+#define MUX_PB08F_TCC2_WO1                         _UINT32_(5) 
+#define PINMUX_PB08F_TCC2_WO1                      ((PIN_PB08F_TCC2_WO1 << 16) | MUX_PB08F_TCC2_WO1)
+#define PORT_PB08F_TCC2_WO1                        (_UINT32_(1) << 8)
+
+#define PIN_PC05F_TCC2_WO1                         _UINT32_(69)
+#define MUX_PC05F_TCC2_WO1                         _UINT32_(5) 
+#define PINMUX_PC05F_TCC2_WO1                      ((PIN_PC05F_TCC2_WO1 << 16) | MUX_PC05F_TCC2_WO1)
+#define PORT_PC05F_TCC2_WO1                        (_UINT32_(1) << 5)
+
+/* ================== PORT definition for TCC3 peripheral =================== */
+#define PIN_PD00F_TCC3_WO0                         _UINT32_(96)
+#define MUX_PD00F_TCC3_WO0                         _UINT32_(5) 
+#define PINMUX_PD00F_TCC3_WO0                      ((PIN_PD00F_TCC3_WO0 << 16) | MUX_PD00F_TCC3_WO0)
+#define PORT_PD00F_TCC3_WO0                        (_UINT32_(1) << 0)
+
+#define PIN_PD01F_TCC3_WO1                         _UINT32_(97)
+#define MUX_PD01F_TCC3_WO1                         _UINT32_(5) 
+#define PINMUX_PD01F_TCC3_WO1                      ((PIN_PD01F_TCC3_WO1 << 16) | MUX_PD01F_TCC3_WO1)
+#define PORT_PD01F_TCC3_WO1                        (_UINT32_(1) << 1)
+
+/* ================== PORT definition for TCC4 peripheral =================== */
+#define PIN_PA10F_TCC4_WO0                         _UINT32_(10)
+#define MUX_PA10F_TCC4_WO0                         _UINT32_(5) 
+#define PINMUX_PA10F_TCC4_WO0                      ((PIN_PA10F_TCC4_WO0 << 16) | MUX_PA10F_TCC4_WO0)
+#define PORT_PA10F_TCC4_WO0                        (_UINT32_(1) << 10)
+
+#define PIN_PD07F_TCC4_WO0                         _UINT32_(103)
+#define MUX_PD07F_TCC4_WO0                         _UINT32_(5) 
+#define PINMUX_PD07F_TCC4_WO0                      ((PIN_PD07F_TCC4_WO0 << 16) | MUX_PD07F_TCC4_WO0)
+#define PORT_PD07F_TCC4_WO0                        (_UINT32_(1) << 7)
+
+#define PIN_PA11F_TCC4_WO1                         _UINT32_(11)
+#define MUX_PA11F_TCC4_WO1                         _UINT32_(5) 
+#define PINMUX_PA11F_TCC4_WO1                      ((PIN_PA11F_TCC4_WO1 << 16) | MUX_PA11F_TCC4_WO1)
+#define PORT_PA11F_TCC4_WO1                        (_UINT32_(1) << 11)
+
+#define PIN_PD08F_TCC4_WO1                         _UINT32_(104)
+#define MUX_PD08F_TCC4_WO1                         _UINT32_(5) 
+#define PINMUX_PD08F_TCC4_WO1                      ((PIN_PD08F_TCC4_WO1 << 16) | MUX_PD08F_TCC4_WO1)
+#define PORT_PD08F_TCC4_WO1                        (_UINT32_(1) << 8)
+
+/* ================== PORT definition for TCC5 peripheral =================== */
+#define PIN_PD10F_TCC5_WO0                         _UINT32_(106)
+#define MUX_PD10F_TCC5_WO0                         _UINT32_(5) 
+#define PINMUX_PD10F_TCC5_WO0                      ((PIN_PD10F_TCC5_WO0 << 16) | MUX_PD10F_TCC5_WO0)
+#define PORT_PD10F_TCC5_WO0                        (_UINT32_(1) << 10)
+
+#define PIN_PD09F_TCC5_WO0                         _UINT32_(105)
+#define MUX_PD09F_TCC5_WO0                         _UINT32_(5) 
+#define PINMUX_PD09F_TCC5_WO0                      ((PIN_PD09F_TCC5_WO0 << 16) | MUX_PD09F_TCC5_WO0)
+#define PORT_PD09F_TCC5_WO0                        (_UINT32_(1) << 9)
+
+#define PIN_PA00F_TCC5_WO1                         _UINT32_(0) 
+#define MUX_PA00F_TCC5_WO1                         _UINT32_(5) 
+#define PINMUX_PA00F_TCC5_WO1                      ((PIN_PA00F_TCC5_WO1 << 16) | MUX_PA00F_TCC5_WO1)
+#define PORT_PA00F_TCC5_WO1                        (_UINT32_(1) << 0)
+
+#define PIN_PD11F_TCC5_WO1                         _UINT32_(107)
+#define MUX_PD11F_TCC5_WO1                         _UINT32_(5) 
+#define PINMUX_PD11F_TCC5_WO1                      ((PIN_PD11F_TCC5_WO1 << 16) | MUX_PD11F_TCC5_WO1)
+#define PORT_PD11F_TCC5_WO1                        (_UINT32_(1) << 11)
+
+/* ================== PORT definition for TCC6 peripheral =================== */
+#define PIN_PA01F_TCC6_WO0                         _UINT32_(1) 
+#define MUX_PA01F_TCC6_WO0                         _UINT32_(5) 
+#define PINMUX_PA01F_TCC6_WO0                      ((PIN_PA01F_TCC6_WO0 << 16) | MUX_PA01F_TCC6_WO0)
+#define PORT_PA01F_TCC6_WO0                        (_UINT32_(1) << 1)
+
+#define PIN_PD12F_TCC6_WO0                         _UINT32_(108)
+#define MUX_PD12F_TCC6_WO0                         _UINT32_(5) 
+#define PINMUX_PD12F_TCC6_WO0                      ((PIN_PD12F_TCC6_WO0 << 16) | MUX_PD12F_TCC6_WO0)
+#define PORT_PD12F_TCC6_WO0                        (_UINT32_(1) << 12)
+
+#define PIN_PA02F_TCC6_WO1                         _UINT32_(2) 
+#define MUX_PA02F_TCC6_WO1                         _UINT32_(5) 
+#define PINMUX_PA02F_TCC6_WO1                      ((PIN_PA02F_TCC6_WO1 << 16) | MUX_PA02F_TCC6_WO1)
+#define PORT_PA02F_TCC6_WO1                        (_UINT32_(1) << 2)
+
+#define PIN_PD13F_TCC6_WO1                         _UINT32_(109)
+#define MUX_PD13F_TCC6_WO1                         _UINT32_(5) 
+#define PINMUX_PD13F_TCC6_WO1                      ((PIN_PD13F_TCC6_WO1 << 16) | MUX_PD13F_TCC6_WO1)
+#define PORT_PD13F_TCC6_WO1                        (_UINT32_(1) << 13)
+
+/* =================== PORT definition for USB peripheral =================== */
+#define PIN_PD01H_USB_SOF                          _UINT32_(97)
+#define MUX_PD01H_USB_SOF                          _UINT32_(7) 
+#define PINMUX_PD01H_USB_SOF                       ((PIN_PD01H_USB_SOF << 16) | MUX_PD01H_USB_SOF)
+#define PORT_PD01H_USB_SOF                         (_UINT32_(1) << 1)
+
+#define PIN_PD02H_USB_USBDM                        _UINT32_(98)
+#define MUX_PD02H_USB_USBDM                        _UINT32_(7) 
+#define PINMUX_PD02H_USB_USBDM                     ((PIN_PD02H_USB_USBDM << 16) | MUX_PD02H_USB_USBDM)
+#define PORT_PD02H_USB_USBDM                       (_UINT32_(1) << 2)
+
+#define PIN_PD03H_USB_USBDP                        _UINT32_(99)
+#define MUX_PD03H_USB_USBDP                        _UINT32_(7) 
+#define PINMUX_PD03H_USB_USBDP                     ((PIN_PD03H_USB_USBDP << 16) | MUX_PD03H_USB_USBDP)
+#define PORT_PD03H_USB_USBDP                       (_UINT32_(1) << 3)
+
+
+
+#endif /* _PIC32CM5112GC00064_GPIO_H_ */
+
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pio/pic32cm5112gc00100.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pio/pic32cm5112gc00100.h
new file mode 100644
index 00000000..702dc6d0
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/pio/pic32cm5112gc00100.h
@@ -0,0 +1,2020 @@
+/*
+ * Peripheral I/O description for PIC32CM5112GC00100
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*  file generated from device description file (ATDF) version 2024-11-05T16:47:43Z  */
+#ifndef _PIC32CM5112GC00100_GPIO_H_
+#define _PIC32CM5112GC00100_GPIO_H_
+
+/* ======================= Peripheral I/O pin numbers ======================= */
+#define PIN_PA00                    (    0)  /* Pin Number for PA00 */
+#define PIN_PA01                    (    1)  /* Pin Number for PA01 */
+#define PIN_PA02                    (    2)  /* Pin Number for PA02 */
+#define PIN_PA03                    (    3)  /* Pin Number for PA03 */
+#define PIN_PA04                    (    4)  /* Pin Number for PA04 */
+#define PIN_PA05                    (    5)  /* Pin Number for PA05 */
+#define PIN_PA06                    (    6)  /* Pin Number for PA06 */
+#define PIN_PA07                    (    7)  /* Pin Number for PA07 */
+#define PIN_PA08                    (    8)  /* Pin Number for PA08 */
+#define PIN_PA09                    (    9)  /* Pin Number for PA09 */
+#define PIN_PA10                    (   10)  /* Pin Number for PA10 */
+#define PIN_PA11                    (   11)  /* Pin Number for PA11 */
+#define PIN_PA12                    (   12)  /* Pin Number for PA12 */
+#define PIN_PA13                    (   13)  /* Pin Number for PA13 */
+#define PIN_PA14                    (   14)  /* Pin Number for PA14 */
+#define PIN_PA15                    (   15)  /* Pin Number for PA15 */
+#define PIN_PA16                    (   16)  /* Pin Number for PA16 */
+#define PIN_PA17                    (   17)  /* Pin Number for PA17 */
+#define PIN_PA18                    (   18)  /* Pin Number for PA18 */
+#define PIN_PA19                    (   19)  /* Pin Number for PA19 */
+#define PIN_PA20                    (   20)  /* Pin Number for PA20 */
+#define PIN_PB00                    (   32)  /* Pin Number for PB00 */
+#define PIN_PB01                    (   33)  /* Pin Number for PB01 */
+#define PIN_PB02                    (   34)  /* Pin Number for PB02 */
+#define PIN_PB03                    (   35)  /* Pin Number for PB03 */
+#define PIN_PB04                    (   36)  /* Pin Number for PB04 */
+#define PIN_PB05                    (   37)  /* Pin Number for PB05 */
+#define PIN_PB06                    (   38)  /* Pin Number for PB06 */
+#define PIN_PB07                    (   39)  /* Pin Number for PB07 */
+#define PIN_PB08                    (   40)  /* Pin Number for PB08 */
+#define PIN_PB09                    (   41)  /* Pin Number for PB09 */
+#define PIN_PB10                    (   42)  /* Pin Number for PB10 */
+#define PIN_PB11                    (   43)  /* Pin Number for PB11 */
+#define PIN_PB12                    (   44)  /* Pin Number for PB12 */
+#define PIN_PB13                    (   45)  /* Pin Number for PB13 */
+#define PIN_PB14                    (   46)  /* Pin Number for PB14 */
+#define PIN_PB15                    (   47)  /* Pin Number for PB15 */
+#define PIN_PB16                    (   48)  /* Pin Number for PB16 */
+#define PIN_PB17                    (   49)  /* Pin Number for PB17 */
+#define PIN_PC00                    (   64)  /* Pin Number for PC00 */
+#define PIN_PC01                    (   65)  /* Pin Number for PC01 */
+#define PIN_PC02                    (   66)  /* Pin Number for PC02 */
+#define PIN_PC03                    (   67)  /* Pin Number for PC03 */
+#define PIN_PC04                    (   68)  /* Pin Number for PC04 */
+#define PIN_PC05                    (   69)  /* Pin Number for PC05 */
+#define PIN_PC06                    (   70)  /* Pin Number for PC06 */
+#define PIN_PC07                    (   71)  /* Pin Number for PC07 */
+#define PIN_PC08                    (   72)  /* Pin Number for PC08 */
+#define PIN_PC09                    (   73)  /* Pin Number for PC09 */
+#define PIN_PC10                    (   74)  /* Pin Number for PC10 */
+#define PIN_PC11                    (   75)  /* Pin Number for PC11 */
+#define PIN_PC12                    (   76)  /* Pin Number for PC12 */
+#define PIN_PC13                    (   77)  /* Pin Number for PC13 */
+#define PIN_PC14                    (   78)  /* Pin Number for PC14 */
+#define PIN_PC15                    (   79)  /* Pin Number for PC15 */
+#define PIN_PC16                    (   80)  /* Pin Number for PC16 */
+#define PIN_PC17                    (   81)  /* Pin Number for PC17 */
+#define PIN_PC18                    (   82)  /* Pin Number for PC18 */
+#define PIN_PC19                    (   83)  /* Pin Number for PC19 */
+#define PIN_PD00                    (   96)  /* Pin Number for PD00 */
+#define PIN_PD01                    (   97)  /* Pin Number for PD01 */
+#define PIN_PD02                    (   98)  /* Pin Number for PD02 */
+#define PIN_PD03                    (   99)  /* Pin Number for PD03 */
+#define PIN_PD04                    (  100)  /* Pin Number for PD04 */
+#define PIN_PD05                    (  101)  /* Pin Number for PD05 */
+#define PIN_PD06                    (  102)  /* Pin Number for PD06 */
+#define PIN_PD07                    (  103)  /* Pin Number for PD07 */
+#define PIN_PD08                    (  104)  /* Pin Number for PD08 */
+#define PIN_PD09                    (  105)  /* Pin Number for PD09 */
+#define PIN_PD10                    (  106)  /* Pin Number for PD10 */
+#define PIN_PD11                    (  107)  /* Pin Number for PD11 */
+#define PIN_PD12                    (  108)  /* Pin Number for PD12 */
+#define PIN_PD13                    (  109)  /* Pin Number for PD13 */
+#define PIN_PD14                    (  110)  /* Pin Number for PD14 */
+#define PIN_PD15                    (  111)  /* Pin Number for PD15 */
+#define PIN_PD16                    (  112)  /* Pin Number for PD16 */
+#define PIN_PD17                    (  113)  /* Pin Number for PD17 */
+#define PIN_PD18                    (  114)  /* Pin Number for PD18 */
+#define PIN_PD19                    (  115)  /* Pin Number for PD19 */
+#define PIN_PD20                    (  116)  /* Pin Number for PD20 */
+
+/* ========================== Peripheral I/O masks ========================== */
+#define PORT_PA00                   (_UINT32_(1) << 0) /* PORT mask for PA00 */
+#define PORT_PA01                   (_UINT32_(1) << 1) /* PORT mask for PA01 */
+#define PORT_PA02                   (_UINT32_(1) << 2) /* PORT mask for PA02 */
+#define PORT_PA03                   (_UINT32_(1) << 3) /* PORT mask for PA03 */
+#define PORT_PA04                   (_UINT32_(1) << 4) /* PORT mask for PA04 */
+#define PORT_PA05                   (_UINT32_(1) << 5) /* PORT mask for PA05 */
+#define PORT_PA06                   (_UINT32_(1) << 6) /* PORT mask for PA06 */
+#define PORT_PA07                   (_UINT32_(1) << 7) /* PORT mask for PA07 */
+#define PORT_PA08                   (_UINT32_(1) << 8) /* PORT mask for PA08 */
+#define PORT_PA09                   (_UINT32_(1) << 9) /* PORT mask for PA09 */
+#define PORT_PA10                   (_UINT32_(1) << 10) /* PORT mask for PA10 */
+#define PORT_PA11                   (_UINT32_(1) << 11) /* PORT mask for PA11 */
+#define PORT_PA12                   (_UINT32_(1) << 12) /* PORT mask for PA12 */
+#define PORT_PA13                   (_UINT32_(1) << 13) /* PORT mask for PA13 */
+#define PORT_PA14                   (_UINT32_(1) << 14) /* PORT mask for PA14 */
+#define PORT_PA15                   (_UINT32_(1) << 15) /* PORT mask for PA15 */
+#define PORT_PA16                   (_UINT32_(1) << 16) /* PORT mask for PA16 */
+#define PORT_PA17                   (_UINT32_(1) << 17) /* PORT mask for PA17 */
+#define PORT_PA18                   (_UINT32_(1) << 18) /* PORT mask for PA18 */
+#define PORT_PA19                   (_UINT32_(1) << 19) /* PORT mask for PA19 */
+#define PORT_PA20                   (_UINT32_(1) << 20) /* PORT mask for PA20 */
+#define PORT_PB00                   (_UINT32_(1) << 0) /* PORT mask for PB00 */
+#define PORT_PB01                   (_UINT32_(1) << 1) /* PORT mask for PB01 */
+#define PORT_PB02                   (_UINT32_(1) << 2) /* PORT mask for PB02 */
+#define PORT_PB03                   (_UINT32_(1) << 3) /* PORT mask for PB03 */
+#define PORT_PB04                   (_UINT32_(1) << 4) /* PORT mask for PB04 */
+#define PORT_PB05                   (_UINT32_(1) << 5) /* PORT mask for PB05 */
+#define PORT_PB06                   (_UINT32_(1) << 6) /* PORT mask for PB06 */
+#define PORT_PB07                   (_UINT32_(1) << 7) /* PORT mask for PB07 */
+#define PORT_PB08                   (_UINT32_(1) << 8) /* PORT mask for PB08 */
+#define PORT_PB09                   (_UINT32_(1) << 9) /* PORT mask for PB09 */
+#define PORT_PB10                   (_UINT32_(1) << 10) /* PORT mask for PB10 */
+#define PORT_PB11                   (_UINT32_(1) << 11) /* PORT mask for PB11 */
+#define PORT_PB12                   (_UINT32_(1) << 12) /* PORT mask for PB12 */
+#define PORT_PB13                   (_UINT32_(1) << 13) /* PORT mask for PB13 */
+#define PORT_PB14                   (_UINT32_(1) << 14) /* PORT mask for PB14 */
+#define PORT_PB15                   (_UINT32_(1) << 15) /* PORT mask for PB15 */
+#define PORT_PB16                   (_UINT32_(1) << 16) /* PORT mask for PB16 */
+#define PORT_PB17                   (_UINT32_(1) << 17) /* PORT mask for PB17 */
+#define PORT_PC00                   (_UINT32_(1) << 0) /* PORT mask for PC00 */
+#define PORT_PC01                   (_UINT32_(1) << 1) /* PORT mask for PC01 */
+#define PORT_PC02                   (_UINT32_(1) << 2) /* PORT mask for PC02 */
+#define PORT_PC03                   (_UINT32_(1) << 3) /* PORT mask for PC03 */
+#define PORT_PC04                   (_UINT32_(1) << 4) /* PORT mask for PC04 */
+#define PORT_PC05                   (_UINT32_(1) << 5) /* PORT mask for PC05 */
+#define PORT_PC06                   (_UINT32_(1) << 6) /* PORT mask for PC06 */
+#define PORT_PC07                   (_UINT32_(1) << 7) /* PORT mask for PC07 */
+#define PORT_PC08                   (_UINT32_(1) << 8) /* PORT mask for PC08 */
+#define PORT_PC09                   (_UINT32_(1) << 9) /* PORT mask for PC09 */
+#define PORT_PC10                   (_UINT32_(1) << 10) /* PORT mask for PC10 */
+#define PORT_PC11                   (_UINT32_(1) << 11) /* PORT mask for PC11 */
+#define PORT_PC12                   (_UINT32_(1) << 12) /* PORT mask for PC12 */
+#define PORT_PC13                   (_UINT32_(1) << 13) /* PORT mask for PC13 */
+#define PORT_PC14                   (_UINT32_(1) << 14) /* PORT mask for PC14 */
+#define PORT_PC15                   (_UINT32_(1) << 15) /* PORT mask for PC15 */
+#define PORT_PC16                   (_UINT32_(1) << 16) /* PORT mask for PC16 */
+#define PORT_PC17                   (_UINT32_(1) << 17) /* PORT mask for PC17 */
+#define PORT_PC18                   (_UINT32_(1) << 18) /* PORT mask for PC18 */
+#define PORT_PC19                   (_UINT32_(1) << 19) /* PORT mask for PC19 */
+#define PORT_PD00                   (_UINT32_(1) << 0) /* PORT mask for PD00 */
+#define PORT_PD01                   (_UINT32_(1) << 1) /* PORT mask for PD01 */
+#define PORT_PD02                   (_UINT32_(1) << 2) /* PORT mask for PD02 */
+#define PORT_PD03                   (_UINT32_(1) << 3) /* PORT mask for PD03 */
+#define PORT_PD04                   (_UINT32_(1) << 4) /* PORT mask for PD04 */
+#define PORT_PD05                   (_UINT32_(1) << 5) /* PORT mask for PD05 */
+#define PORT_PD06                   (_UINT32_(1) << 6) /* PORT mask for PD06 */
+#define PORT_PD07                   (_UINT32_(1) << 7) /* PORT mask for PD07 */
+#define PORT_PD08                   (_UINT32_(1) << 8) /* PORT mask for PD08 */
+#define PORT_PD09                   (_UINT32_(1) << 9) /* PORT mask for PD09 */
+#define PORT_PD10                   (_UINT32_(1) << 10) /* PORT mask for PD10 */
+#define PORT_PD11                   (_UINT32_(1) << 11) /* PORT mask for PD11 */
+#define PORT_PD12                   (_UINT32_(1) << 12) /* PORT mask for PD12 */
+#define PORT_PD13                   (_UINT32_(1) << 13) /* PORT mask for PD13 */
+#define PORT_PD14                   (_UINT32_(1) << 14) /* PORT mask for PD14 */
+#define PORT_PD15                   (_UINT32_(1) << 15) /* PORT mask for PD15 */
+#define PORT_PD16                   (_UINT32_(1) << 16) /* PORT mask for PD16 */
+#define PORT_PD17                   (_UINT32_(1) << 17) /* PORT mask for PD17 */
+#define PORT_PD18                   (_UINT32_(1) << 18) /* PORT mask for PD18 */
+#define PORT_PD19                   (_UINT32_(1) << 19) /* PORT mask for PD19 */
+#define PORT_PD20                   (_UINT32_(1) << 20) /* PORT mask for PD20 */
+
+/* =================== PORT definition for AC peripheral ==================== */
+#define PIN_PA07B_AC_AIN0                          _UINT32_(7) 
+#define MUX_PA07B_AC_AIN0                          _UINT32_(1) 
+#define PINMUX_PA07B_AC_AIN0                       ((PIN_PA07B_AC_AIN0 << 16) | MUX_PA07B_AC_AIN0)
+#define PORT_PA07B_AC_AIN0                         (_UINT32_(1) << 7)
+
+#define PIN_PA08B_AC_AIN1                          _UINT32_(8) 
+#define MUX_PA08B_AC_AIN1                          _UINT32_(1) 
+#define PINMUX_PA08B_AC_AIN1                       ((PIN_PA08B_AC_AIN1 << 16) | MUX_PA08B_AC_AIN1)
+#define PORT_PA08B_AC_AIN1                         (_UINT32_(1) << 8)
+
+#define PIN_PB00B_AC_AIN2                          _UINT32_(32)
+#define MUX_PB00B_AC_AIN2                          _UINT32_(1) 
+#define PINMUX_PB00B_AC_AIN2                       ((PIN_PB00B_AC_AIN2 << 16) | MUX_PB00B_AC_AIN2)
+#define PORT_PB00B_AC_AIN2                         (_UINT32_(1) << 0)
+
+#define PIN_PB03B_AC_AIN3                          _UINT32_(35)
+#define MUX_PB03B_AC_AIN3                          _UINT32_(1) 
+#define PINMUX_PB03B_AC_AIN3                       ((PIN_PB03B_AC_AIN3 << 16) | MUX_PB03B_AC_AIN3)
+#define PORT_PB03B_AC_AIN3                         (_UINT32_(1) << 3)
+
+#define PIN_PA01B_AC_CMP0                          _UINT32_(1) 
+#define MUX_PA01B_AC_CMP0                          _UINT32_(1) 
+#define PINMUX_PA01B_AC_CMP0                       ((PIN_PA01B_AC_CMP0 << 16) | MUX_PA01B_AC_CMP0)
+#define PORT_PA01B_AC_CMP0                         (_UINT32_(1) << 1)
+
+#define PIN_PA13B_AC_CMP0                          _UINT32_(13)
+#define MUX_PA13B_AC_CMP0                          _UINT32_(1) 
+#define PINMUX_PA13B_AC_CMP0                       ((PIN_PA13B_AC_CMP0 << 16) | MUX_PA13B_AC_CMP0)
+#define PORT_PA13B_AC_CMP0                         (_UINT32_(1) << 13)
+
+#define PIN_PA02B_AC_CMP1                          _UINT32_(2) 
+#define MUX_PA02B_AC_CMP1                          _UINT32_(1) 
+#define PINMUX_PA02B_AC_CMP1                       ((PIN_PA02B_AC_CMP1 << 16) | MUX_PA02B_AC_CMP1)
+#define PORT_PA02B_AC_CMP1                         (_UINT32_(1) << 2)
+
+#define PIN_PB07B_AC_CMP1                          _UINT32_(39)
+#define MUX_PB07B_AC_CMP1                          _UINT32_(1) 
+#define PINMUX_PB07B_AC_CMP1                       ((PIN_PB07B_AC_CMP1 << 16) | MUX_PB07B_AC_CMP1)
+#define PORT_PB07B_AC_CMP1                         (_UINT32_(1) << 7)
+
+/* =================== PORT definition for ADC peripheral =================== */
+#define PIN_PA03B_ADC_ADC0_AIN0                    _UINT32_(3) 
+#define MUX_PA03B_ADC_ADC0_AIN0                    _UINT32_(1) 
+#define PINMUX_PA03B_ADC_ADC0_AIN0                 ((PIN_PA03B_ADC_ADC0_AIN0 << 16) | MUX_PA03B_ADC_ADC0_AIN0)
+#define PORT_PA03B_ADC_ADC0_AIN0                   (_UINT32_(1) << 3)
+
+#define PIN_PA04B_ADC_ADC0_AIN1                    _UINT32_(4) 
+#define MUX_PA04B_ADC_ADC0_AIN1                    _UINT32_(1) 
+#define PINMUX_PA04B_ADC_ADC0_AIN1                 ((PIN_PA04B_ADC_ADC0_AIN1 << 16) | MUX_PA04B_ADC_ADC0_AIN1)
+#define PORT_PA04B_ADC_ADC0_AIN1                   (_UINT32_(1) << 4)
+
+#define PIN_PA05B_ADC_ADC0_AIN2                    _UINT32_(5) 
+#define MUX_PA05B_ADC_ADC0_AIN2                    _UINT32_(1) 
+#define PINMUX_PA05B_ADC_ADC0_AIN2                 ((PIN_PA05B_ADC_ADC0_AIN2 << 16) | MUX_PA05B_ADC_ADC0_AIN2)
+#define PORT_PA05B_ADC_ADC0_AIN2                   (_UINT32_(1) << 5)
+
+#define PIN_PA06B_ADC_ADC0_AIN3                    _UINT32_(6) 
+#define MUX_PA06B_ADC_ADC0_AIN3                    _UINT32_(1) 
+#define PINMUX_PA06B_ADC_ADC0_AIN3                 ((PIN_PA06B_ADC_ADC0_AIN3 << 16) | MUX_PA06B_ADC_ADC0_AIN3)
+#define PORT_PA06B_ADC_ADC0_AIN3                   (_UINT32_(1) << 6)
+
+#define PIN_PA07B_ADC_ADC0_AIN4                    _UINT32_(7) 
+#define MUX_PA07B_ADC_ADC0_AIN4                    _UINT32_(1) 
+#define PINMUX_PA07B_ADC_ADC0_AIN4                 ((PIN_PA07B_ADC_ADC0_AIN4 << 16) | MUX_PA07B_ADC_ADC0_AIN4)
+#define PORT_PA07B_ADC_ADC0_AIN4                   (_UINT32_(1) << 7)
+
+#define PIN_PA08B_ADC_ADC0_AIN5                    _UINT32_(8) 
+#define MUX_PA08B_ADC_ADC0_AIN5                    _UINT32_(1) 
+#define PINMUX_PA08B_ADC_ADC0_AIN5                 ((PIN_PA08B_ADC_ADC0_AIN5 << 16) | MUX_PA08B_ADC_ADC0_AIN5)
+#define PORT_PA08B_ADC_ADC0_AIN5                   (_UINT32_(1) << 8)
+
+#define PIN_PA09B_ADC_ADC0_AIN6                    _UINT32_(9) 
+#define MUX_PA09B_ADC_ADC0_AIN6                    _UINT32_(1) 
+#define PINMUX_PA09B_ADC_ADC0_AIN6                 ((PIN_PA09B_ADC_ADC0_AIN6 << 16) | MUX_PA09B_ADC_ADC0_AIN6)
+#define PORT_PA09B_ADC_ADC0_AIN6                   (_UINT32_(1) << 9)
+
+#define PIN_PB00B_ADC_ADC0_AIN7                    _UINT32_(32)
+#define MUX_PB00B_ADC_ADC0_AIN7                    _UINT32_(1) 
+#define PINMUX_PB00B_ADC_ADC0_AIN7                 ((PIN_PB00B_ADC_ADC0_AIN7 << 16) | MUX_PB00B_ADC_ADC0_AIN7)
+#define PORT_PB00B_ADC_ADC0_AIN7                   (_UINT32_(1) << 0)
+
+#define PIN_PB03B_ADC_ADC0_AIN8                    _UINT32_(35)
+#define MUX_PB03B_ADC_ADC0_AIN8                    _UINT32_(1) 
+#define PINMUX_PB03B_ADC_ADC0_AIN8                 ((PIN_PB03B_ADC_ADC0_AIN8 << 16) | MUX_PB03B_ADC_ADC0_AIN8)
+#define PORT_PB03B_ADC_ADC0_AIN8                   (_UINT32_(1) << 3)
+
+#define PIN_PB04B_ADC_ADC0_AIN9                    _UINT32_(36)
+#define MUX_PB04B_ADC_ADC0_AIN9                    _UINT32_(1) 
+#define PINMUX_PB04B_ADC_ADC0_AIN9                 ((PIN_PB04B_ADC_ADC0_AIN9 << 16) | MUX_PB04B_ADC_ADC0_AIN9)
+#define PORT_PB04B_ADC_ADC0_AIN9                   (_UINT32_(1) << 4)
+
+#define PIN_PB05B_ADC_ADC0_AIN10                   _UINT32_(37)
+#define MUX_PB05B_ADC_ADC0_AIN10                   _UINT32_(1) 
+#define PINMUX_PB05B_ADC_ADC0_AIN10                ((PIN_PB05B_ADC_ADC0_AIN10 << 16) | MUX_PB05B_ADC_ADC0_AIN10)
+#define PORT_PB05B_ADC_ADC0_AIN10                  (_UINT32_(1) << 5)
+
+#define PIN_PB06B_ADC_ADC0_AIN11                   _UINT32_(38)
+#define MUX_PB06B_ADC_ADC0_AIN11                   _UINT32_(1) 
+#define PINMUX_PB06B_ADC_ADC0_AIN11                ((PIN_PB06B_ADC_ADC0_AIN11 << 16) | MUX_PB06B_ADC_ADC0_AIN11)
+#define PORT_PB06B_ADC_ADC0_AIN11                  (_UINT32_(1) << 6)
+
+#define PIN_PA04B_ADC_ADC0_ANN0                    _UINT32_(4) 
+#define MUX_PA04B_ADC_ADC0_ANN0                    _UINT32_(1) 
+#define PINMUX_PA04B_ADC_ADC0_ANN0                 ((PIN_PA04B_ADC_ADC0_ANN0 << 16) | MUX_PA04B_ADC_ADC0_ANN0)
+#define PORT_PA04B_ADC_ADC0_ANN0                   (_UINT32_(1) << 4)
+
+#define PIN_PA06B_ADC_ADC0_ANN2                    _UINT32_(6) 
+#define MUX_PA06B_ADC_ADC0_ANN2                    _UINT32_(1) 
+#define PINMUX_PA06B_ADC_ADC0_ANN2                 ((PIN_PA06B_ADC_ADC0_ANN2 << 16) | MUX_PA06B_ADC_ADC0_ANN2)
+#define PORT_PA06B_ADC_ADC0_ANN2                   (_UINT32_(1) << 6)
+
+#define PIN_PA08B_ADC_ADC0_ANN4                    _UINT32_(8) 
+#define MUX_PA08B_ADC_ADC0_ANN4                    _UINT32_(1) 
+#define PINMUX_PA08B_ADC_ADC0_ANN4                 ((PIN_PA08B_ADC_ADC0_ANN4 << 16) | MUX_PA08B_ADC_ADC0_ANN4)
+#define PORT_PA08B_ADC_ADC0_ANN4                   (_UINT32_(1) << 8)
+
+/* ================== PORT definition for CAN0 peripheral =================== */
+#define PIN_PA10H_CAN0_RX                          _UINT32_(10)
+#define MUX_PA10H_CAN0_RX                          _UINT32_(7) 
+#define PINMUX_PA10H_CAN0_RX                       ((PIN_PA10H_CAN0_RX << 16) | MUX_PA10H_CAN0_RX)
+#define PORT_PA10H_CAN0_RX                         (_UINT32_(1) << 10)
+
+#define PIN_PC01H_CAN0_RX                          _UINT32_(65)
+#define MUX_PC01H_CAN0_RX                          _UINT32_(7) 
+#define PINMUX_PC01H_CAN0_RX                       ((PIN_PC01H_CAN0_RX << 16) | MUX_PC01H_CAN0_RX)
+#define PORT_PC01H_CAN0_RX                         (_UINT32_(1) << 1)
+
+#define PIN_PD06H_CAN0_RX                          _UINT32_(102)
+#define MUX_PD06H_CAN0_RX                          _UINT32_(7) 
+#define PINMUX_PD06H_CAN0_RX                       ((PIN_PD06H_CAN0_RX << 16) | MUX_PD06H_CAN0_RX)
+#define PORT_PD06H_CAN0_RX                         (_UINT32_(1) << 6)
+
+#define PIN_PA11H_CAN0_TX                          _UINT32_(11)
+#define MUX_PA11H_CAN0_TX                          _UINT32_(7) 
+#define PINMUX_PA11H_CAN0_TX                       ((PIN_PA11H_CAN0_TX << 16) | MUX_PA11H_CAN0_TX)
+#define PORT_PA11H_CAN0_TX                         (_UINT32_(1) << 11)
+
+#define PIN_PC02H_CAN0_TX                          _UINT32_(66)
+#define MUX_PC02H_CAN0_TX                          _UINT32_(7) 
+#define PINMUX_PC02H_CAN0_TX                       ((PIN_PC02H_CAN0_TX << 16) | MUX_PC02H_CAN0_TX)
+#define PORT_PC02H_CAN0_TX                         (_UINT32_(1) << 2)
+
+#define PIN_PD08H_CAN0_TX                          _UINT32_(104)
+#define MUX_PD08H_CAN0_TX                          _UINT32_(7) 
+#define PINMUX_PD08H_CAN0_TX                       ((PIN_PD08H_CAN0_TX << 16) | MUX_PD08H_CAN0_TX)
+#define PORT_PD08H_CAN0_TX                         (_UINT32_(1) << 8)
+
+/* ================== PORT definition for CAN1 peripheral =================== */
+#define PIN_PA00H_CAN1_RX                          _UINT32_(0) 
+#define MUX_PA00H_CAN1_RX                          _UINT32_(7) 
+#define PINMUX_PA00H_CAN1_RX                       ((PIN_PA00H_CAN1_RX << 16) | MUX_PA00H_CAN1_RX)
+#define PORT_PA00H_CAN1_RX                         (_UINT32_(1) << 0)
+
+#define PIN_PC05H_CAN1_RX                          _UINT32_(69)
+#define MUX_PC05H_CAN1_RX                          _UINT32_(7) 
+#define PINMUX_PC05H_CAN1_RX                       ((PIN_PC05H_CAN1_RX << 16) | MUX_PC05H_CAN1_RX)
+#define PORT_PC05H_CAN1_RX                         (_UINT32_(1) << 5)
+
+#define PIN_PD12H_CAN1_RX                          _UINT32_(108)
+#define MUX_PD12H_CAN1_RX                          _UINT32_(7) 
+#define PINMUX_PD12H_CAN1_RX                       ((PIN_PD12H_CAN1_RX << 16) | MUX_PD12H_CAN1_RX)
+#define PORT_PD12H_CAN1_RX                         (_UINT32_(1) << 12)
+
+#define PIN_PA01H_CAN1_TX                          _UINT32_(1) 
+#define MUX_PA01H_CAN1_TX                          _UINT32_(7) 
+#define PINMUX_PA01H_CAN1_TX                       ((PIN_PA01H_CAN1_TX << 16) | MUX_PA01H_CAN1_TX)
+#define PORT_PA01H_CAN1_TX                         (_UINT32_(1) << 1)
+
+#define PIN_PC06H_CAN1_TX                          _UINT32_(70)
+#define MUX_PC06H_CAN1_TX                          _UINT32_(7) 
+#define PINMUX_PC06H_CAN1_TX                       ((PIN_PC06H_CAN1_TX << 16) | MUX_PC06H_CAN1_TX)
+#define PORT_PC06H_CAN1_TX                         (_UINT32_(1) << 6)
+
+#define PIN_PD13H_CAN1_TX                          _UINT32_(109)
+#define MUX_PD13H_CAN1_TX                          _UINT32_(7) 
+#define PINMUX_PD13H_CAN1_TX                       ((PIN_PD13H_CAN1_TX << 16) | MUX_PD13H_CAN1_TX)
+#define PORT_PD13H_CAN1_TX                         (_UINT32_(1) << 13)
+
+/* ================== PORT definition for CCL0 peripheral =================== */
+#define PIN_PC12I_CCL0_IN0                         _UINT32_(76)
+#define MUX_PC12I_CCL0_IN0                         _UINT32_(8) 
+#define PINMUX_PC12I_CCL0_IN0                      ((PIN_PC12I_CCL0_IN0 << 16) | MUX_PC12I_CCL0_IN0)
+#define PORT_PC12I_CCL0_IN0                        (_UINT32_(1) << 12)
+
+#define PIN_PC01I_CCL0_IN0                         _UINT32_(65)
+#define MUX_PC01I_CCL0_IN0                         _UINT32_(8) 
+#define PINMUX_PC01I_CCL0_IN0                      ((PIN_PC01I_CCL0_IN0 << 16) | MUX_PC01I_CCL0_IN0)
+#define PORT_PC01I_CCL0_IN0                        (_UINT32_(1) << 1)
+
+#define PIN_PC02I_CCL0_IN1                         _UINT32_(66)
+#define MUX_PC02I_CCL0_IN1                         _UINT32_(8) 
+#define PINMUX_PC02I_CCL0_IN1                      ((PIN_PC02I_CCL0_IN1 << 16) | MUX_PC02I_CCL0_IN1)
+#define PORT_PC02I_CCL0_IN1                        (_UINT32_(1) << 2)
+
+#define PIN_PC14I_CCL0_IN1                         _UINT32_(78)
+#define MUX_PC14I_CCL0_IN1                         _UINT32_(8) 
+#define PINMUX_PC14I_CCL0_IN1                      ((PIN_PC14I_CCL0_IN1 << 16) | MUX_PC14I_CCL0_IN1)
+#define PORT_PC14I_CCL0_IN1                        (_UINT32_(1) << 14)
+
+#define PIN_PC15I_CCL0_IN2                         _UINT32_(79)
+#define MUX_PC15I_CCL0_IN2                         _UINT32_(8) 
+#define PINMUX_PC15I_CCL0_IN2                      ((PIN_PC15I_CCL0_IN2 << 16) | MUX_PC15I_CCL0_IN2)
+#define PORT_PC15I_CCL0_IN2                        (_UINT32_(1) << 15)
+
+#define PIN_PC09I_CCL0_IN2                         _UINT32_(73)
+#define MUX_PC09I_CCL0_IN2                         _UINT32_(8) 
+#define PINMUX_PC09I_CCL0_IN2                      ((PIN_PC09I_CCL0_IN2 << 16) | MUX_PC09I_CCL0_IN2)
+#define PORT_PC09I_CCL0_IN2                        (_UINT32_(1) << 9)
+
+#define PIN_PD00I_CCL0_IN3                         _UINT32_(96)
+#define MUX_PD00I_CCL0_IN3                         _UINT32_(8) 
+#define PINMUX_PD00I_CCL0_IN3                      ((PIN_PD00I_CCL0_IN3 << 16) | MUX_PD00I_CCL0_IN3)
+#define PORT_PD00I_CCL0_IN3                        (_UINT32_(1) << 0)
+
+#define PIN_PD18I_CCL0_IN3                         _UINT32_(114)
+#define MUX_PD18I_CCL0_IN3                         _UINT32_(8) 
+#define PINMUX_PD18I_CCL0_IN3                      ((PIN_PD18I_CCL0_IN3 << 16) | MUX_PD18I_CCL0_IN3)
+#define PORT_PD18I_CCL0_IN3                        (_UINT32_(1) << 18)
+
+#define PIN_PD01I_CCL0_IN4                         _UINT32_(97)
+#define MUX_PD01I_CCL0_IN4                         _UINT32_(8) 
+#define PINMUX_PD01I_CCL0_IN4                      ((PIN_PD01I_CCL0_IN4 << 16) | MUX_PD01I_CCL0_IN4)
+#define PORT_PD01I_CCL0_IN4                        (_UINT32_(1) << 1)
+
+#define PIN_PD17I_CCL0_IN4                         _UINT32_(113)
+#define MUX_PD17I_CCL0_IN4                         _UINT32_(8) 
+#define PINMUX_PD17I_CCL0_IN4                      ((PIN_PD17I_CCL0_IN4 << 16) | MUX_PD17I_CCL0_IN4)
+#define PORT_PD17I_CCL0_IN4                        (_UINT32_(1) << 17)
+
+#define PIN_PD10I_CCL0_IN5                         _UINT32_(106)
+#define MUX_PD10I_CCL0_IN5                         _UINT32_(8) 
+#define PINMUX_PD10I_CCL0_IN5                      ((PIN_PD10I_CCL0_IN5 << 16) | MUX_PD10I_CCL0_IN5)
+#define PORT_PD10I_CCL0_IN5                        (_UINT32_(1) << 10)
+
+#define PIN_PD19I_CCL0_IN5                         _UINT32_(115)
+#define MUX_PD19I_CCL0_IN5                         _UINT32_(8) 
+#define PINMUX_PD19I_CCL0_IN5                      ((PIN_PD19I_CCL0_IN5 << 16) | MUX_PD19I_CCL0_IN5)
+#define PORT_PD19I_CCL0_IN5                        (_UINT32_(1) << 19)
+
+#define PIN_PA00I_CCL0_IN6                         _UINT32_(0) 
+#define MUX_PA00I_CCL0_IN6                         _UINT32_(8) 
+#define PINMUX_PA00I_CCL0_IN6                      ((PIN_PA00I_CCL0_IN6 << 16) | MUX_PA00I_CCL0_IN6)
+#define PORT_PA00I_CCL0_IN6                        (_UINT32_(1) << 0)
+
+#define PIN_PA14I_CCL0_IN6                         _UINT32_(14)
+#define MUX_PA14I_CCL0_IN6                         _UINT32_(8) 
+#define PINMUX_PA14I_CCL0_IN6                      ((PIN_PA14I_CCL0_IN6 << 16) | MUX_PA14I_CCL0_IN6)
+#define PORT_PA14I_CCL0_IN6                        (_UINT32_(1) << 14)
+
+#define PIN_PA01I_CCL0_IN7                         _UINT32_(1) 
+#define MUX_PA01I_CCL0_IN7                         _UINT32_(8) 
+#define PINMUX_PA01I_CCL0_IN7                      ((PIN_PA01I_CCL0_IN7 << 16) | MUX_PA01I_CCL0_IN7)
+#define PORT_PA01I_CCL0_IN7                        (_UINT32_(1) << 1)
+
+#define PIN_PA15I_CCL0_IN7                         _UINT32_(15)
+#define MUX_PA15I_CCL0_IN7                         _UINT32_(8) 
+#define PINMUX_PA15I_CCL0_IN7                      ((PIN_PA15I_CCL0_IN7 << 16) | MUX_PA15I_CCL0_IN7)
+#define PORT_PA15I_CCL0_IN7                        (_UINT32_(1) << 15)
+
+#define PIN_PA10I_CCL0_IN8                         _UINT32_(10)
+#define MUX_PA10I_CCL0_IN8                         _UINT32_(8) 
+#define PINMUX_PA10I_CCL0_IN8                      ((PIN_PA10I_CCL0_IN8 << 16) | MUX_PA10I_CCL0_IN8)
+#define PORT_PA10I_CCL0_IN8                        (_UINT32_(1) << 10)
+
+#define PIN_PA18I_CCL0_IN8                         _UINT32_(18)
+#define MUX_PA18I_CCL0_IN8                         _UINT32_(8) 
+#define PINMUX_PA18I_CCL0_IN8                      ((PIN_PA18I_CCL0_IN8 << 16) | MUX_PA18I_CCL0_IN8)
+#define PORT_PA18I_CCL0_IN8                        (_UINT32_(1) << 18)
+
+#define PIN_PB12I_CCL0_IN9                         _UINT32_(44)
+#define MUX_PB12I_CCL0_IN9                         _UINT32_(8) 
+#define PINMUX_PB12I_CCL0_IN9                      ((PIN_PB12I_CCL0_IN9 << 16) | MUX_PB12I_CCL0_IN9)
+#define PORT_PB12I_CCL0_IN9                        (_UINT32_(1) << 12)
+
+#define PIN_PB05I_CCL0_IN9                         _UINT32_(37)
+#define MUX_PB05I_CCL0_IN9                         _UINT32_(8) 
+#define PINMUX_PB05I_CCL0_IN9                      ((PIN_PB05I_CCL0_IN9 << 16) | MUX_PB05I_CCL0_IN9)
+#define PORT_PB05I_CCL0_IN9                        (_UINT32_(1) << 5)
+
+#define PIN_PB14I_CCL0_IN10                        _UINT32_(46)
+#define MUX_PB14I_CCL0_IN10                        _UINT32_(8) 
+#define PINMUX_PB14I_CCL0_IN10                     ((PIN_PB14I_CCL0_IN10 << 16) | MUX_PB14I_CCL0_IN10)
+#define PORT_PB14I_CCL0_IN10                       (_UINT32_(1) << 14)
+
+#define PIN_PB06I_CCL0_IN10                        _UINT32_(38)
+#define MUX_PB06I_CCL0_IN10                        _UINT32_(8) 
+#define PINMUX_PB06I_CCL0_IN10                     ((PIN_PB06I_CCL0_IN10 << 16) | MUX_PB06I_CCL0_IN10)
+#define PORT_PB06I_CCL0_IN10                       (_UINT32_(1) << 6)
+
+#define PIN_PB15I_CCL0_IN11                        _UINT32_(47)
+#define MUX_PB15I_CCL0_IN11                        _UINT32_(8) 
+#define PINMUX_PB15I_CCL0_IN11                     ((PIN_PB15I_CCL0_IN11 << 16) | MUX_PB15I_CCL0_IN11)
+#define PORT_PB15I_CCL0_IN11                       (_UINT32_(1) << 15)
+
+#define PIN_PB10I_CCL0_IN11                        _UINT32_(42)
+#define MUX_PB10I_CCL0_IN11                        _UINT32_(8) 
+#define PINMUX_PB10I_CCL0_IN11                     ((PIN_PB10I_CCL0_IN11 << 16) | MUX_PB10I_CCL0_IN11)
+#define PORT_PB10I_CCL0_IN11                       (_UINT32_(1) << 10)
+
+#define PIN_PC13I_CCL0_OUT0                        _UINT32_(77)
+#define MUX_PC13I_CCL0_OUT0                        _UINT32_(8) 
+#define PINMUX_PC13I_CCL0_OUT0                     ((PIN_PC13I_CCL0_OUT0 << 16) | MUX_PC13I_CCL0_OUT0)
+#define PORT_PC13I_CCL0_OUT0                       (_UINT32_(1) << 13)
+
+#define PIN_PC03I_CCL0_OUT0                        _UINT32_(67)
+#define MUX_PC03I_CCL0_OUT0                        _UINT32_(8) 
+#define PINMUX_PC03I_CCL0_OUT0                     ((PIN_PC03I_CCL0_OUT0 << 16) | MUX_PC03I_CCL0_OUT0)
+#define PORT_PC03I_CCL0_OUT0                       (_UINT32_(1) << 3)
+
+#define PIN_PD14I_CCL0_OUT1                        _UINT32_(110)
+#define MUX_PD14I_CCL0_OUT1                        _UINT32_(8) 
+#define PINMUX_PD14I_CCL0_OUT1                     ((PIN_PD14I_CCL0_OUT1 << 16) | MUX_PD14I_CCL0_OUT1)
+#define PORT_PD14I_CCL0_OUT1                       (_UINT32_(1) << 14)
+
+#define PIN_PD08I_CCL0_OUT1                        _UINT32_(104)
+#define MUX_PD08I_CCL0_OUT1                        _UINT32_(8) 
+#define PINMUX_PD08I_CCL0_OUT1                     ((PIN_PD08I_CCL0_OUT1 << 16) | MUX_PD08I_CCL0_OUT1)
+#define PORT_PD08I_CCL0_OUT1                       (_UINT32_(1) << 8)
+
+#define PIN_PA02I_CCL0_OUT2                        _UINT32_(2) 
+#define MUX_PA02I_CCL0_OUT2                        _UINT32_(8) 
+#define PINMUX_PA02I_CCL0_OUT2                     ((PIN_PA02I_CCL0_OUT2 << 16) | MUX_PA02I_CCL0_OUT2)
+#define PORT_PA02I_CCL0_OUT2                       (_UINT32_(1) << 2)
+
+#define PIN_PA19I_CCL0_OUT2                        _UINT32_(19)
+#define MUX_PA19I_CCL0_OUT2                        _UINT32_(8) 
+#define PINMUX_PA19I_CCL0_OUT2                     ((PIN_PA19I_CCL0_OUT2 << 16) | MUX_PA19I_CCL0_OUT2)
+#define PORT_PA19I_CCL0_OUT2                       (_UINT32_(1) << 19)
+
+#define PIN_PB16I_CCL0_OUT3                        _UINT32_(48)
+#define MUX_PB16I_CCL0_OUT3                        _UINT32_(8) 
+#define PINMUX_PB16I_CCL0_OUT3                     ((PIN_PB16I_CCL0_OUT3 << 16) | MUX_PB16I_CCL0_OUT3)
+#define PORT_PB16I_CCL0_OUT3                       (_UINT32_(1) << 16)
+
+#define PIN_PC00I_CCL0_OUT3                        _UINT32_(64)
+#define MUX_PC00I_CCL0_OUT3                        _UINT32_(8) 
+#define PINMUX_PC00I_CCL0_OUT3                     ((PIN_PC00I_CCL0_OUT3 << 16) | MUX_PC00I_CCL0_OUT3)
+#define PORT_PC00I_CCL0_OUT3                       (_UINT32_(1) << 0)
+
+/* ================== PORT definition for CCL1 peripheral =================== */
+#define PIN_PC11I_CCL1_IN0                         _UINT32_(75)
+#define MUX_PC11I_CCL1_IN0                         _UINT32_(8) 
+#define PINMUX_PC11I_CCL1_IN0                      ((PIN_PC11I_CCL1_IN0 << 16) | MUX_PC11I_CCL1_IN0)
+#define PORT_PC11I_CCL1_IN0                        (_UINT32_(1) << 11)
+
+#define PIN_PC04I_CCL1_IN0                         _UINT32_(68)
+#define MUX_PC04I_CCL1_IN0                         _UINT32_(8) 
+#define PINMUX_PC04I_CCL1_IN0                      ((PIN_PC04I_CCL1_IN0 << 16) | MUX_PC04I_CCL1_IN0)
+#define PORT_PC04I_CCL1_IN0                        (_UINT32_(1) << 4)
+
+#define PIN_PC17I_CCL1_IN1                         _UINT32_(81)
+#define MUX_PC17I_CCL1_IN1                         _UINT32_(8) 
+#define PINMUX_PC17I_CCL1_IN1                      ((PIN_PC17I_CCL1_IN1 << 16) | MUX_PC17I_CCL1_IN1)
+#define PORT_PC17I_CCL1_IN1                        (_UINT32_(1) << 17)
+
+#define PIN_PC05I_CCL1_IN1                         _UINT32_(69)
+#define MUX_PC05I_CCL1_IN1                         _UINT32_(8) 
+#define PINMUX_PC05I_CCL1_IN1                      ((PIN_PC05I_CCL1_IN1 << 16) | MUX_PC05I_CCL1_IN1)
+#define PORT_PC05I_CCL1_IN1                        (_UINT32_(1) << 5)
+
+#define PIN_PC16I_CCL1_IN2                         _UINT32_(80)
+#define MUX_PC16I_CCL1_IN2                         _UINT32_(8) 
+#define PINMUX_PC16I_CCL1_IN2                      ((PIN_PC16I_CCL1_IN2 << 16) | MUX_PC16I_CCL1_IN2)
+#define PORT_PC16I_CCL1_IN2                        (_UINT32_(1) << 16)
+
+#define PIN_PC10I_CCL1_IN2                         _UINT32_(74)
+#define MUX_PC10I_CCL1_IN2                         _UINT32_(8) 
+#define PINMUX_PC10I_CCL1_IN2                      ((PIN_PC10I_CCL1_IN2 << 16) | MUX_PC10I_CCL1_IN2)
+#define PORT_PC10I_CCL1_IN2                        (_UINT32_(1) << 10)
+
+#define PIN_PD06I_CCL1_IN3                         _UINT32_(102)
+#define MUX_PD06I_CCL1_IN3                         _UINT32_(8) 
+#define PINMUX_PD06I_CCL1_IN3                      ((PIN_PD06I_CCL1_IN3 << 16) | MUX_PD06I_CCL1_IN3)
+#define PORT_PD06I_CCL1_IN3                        (_UINT32_(1) << 6)
+
+#define PIN_PD20I_CCL1_IN3                         _UINT32_(116)
+#define MUX_PD20I_CCL1_IN3                         _UINT32_(8) 
+#define PINMUX_PD20I_CCL1_IN3                      ((PIN_PD20I_CCL1_IN3 << 16) | MUX_PD20I_CCL1_IN3)
+#define PORT_PD20I_CCL1_IN3                        (_UINT32_(1) << 20)
+
+#define PIN_PD16I_CCL1_IN4                         _UINT32_(112)
+#define MUX_PD16I_CCL1_IN4                         _UINT32_(8) 
+#define PINMUX_PD16I_CCL1_IN4                      ((PIN_PD16I_CCL1_IN4 << 16) | MUX_PD16I_CCL1_IN4)
+#define PORT_PD16I_CCL1_IN4                        (_UINT32_(1) << 16)
+
+#define PIN_PD07I_CCL1_IN4                         _UINT32_(103)
+#define MUX_PD07I_CCL1_IN4                         _UINT32_(8) 
+#define PINMUX_PD07I_CCL1_IN4                      ((PIN_PD07I_CCL1_IN4 << 16) | MUX_PD07I_CCL1_IN4)
+#define PORT_PD07I_CCL1_IN4                        (_UINT32_(1) << 7)
+
+#define PIN_PD11I_CCL1_IN5                         _UINT32_(107)
+#define MUX_PD11I_CCL1_IN5                         _UINT32_(8) 
+#define PINMUX_PD11I_CCL1_IN5                      ((PIN_PD11I_CCL1_IN5 << 16) | MUX_PD11I_CCL1_IN5)
+#define PORT_PD11I_CCL1_IN5                        (_UINT32_(1) << 11)
+
+#define PIN_PD12I_CCL1_IN5                         _UINT32_(108)
+#define MUX_PD12I_CCL1_IN5                         _UINT32_(8) 
+#define PINMUX_PD12I_CCL1_IN5                      ((PIN_PD12I_CCL1_IN5 << 16) | MUX_PD12I_CCL1_IN5)
+#define PORT_PD12I_CCL1_IN5                        (_UINT32_(1) << 12)
+
+#define PIN_PA16I_CCL1_IN6                         _UINT32_(16)
+#define MUX_PA16I_CCL1_IN6                         _UINT32_(8) 
+#define PINMUX_PA16I_CCL1_IN6                      ((PIN_PA16I_CCL1_IN6 << 16) | MUX_PA16I_CCL1_IN6)
+#define PORT_PA16I_CCL1_IN6                        (_UINT32_(1) << 16)
+
+#define PIN_PA09I_CCL1_IN6                         _UINT32_(9) 
+#define MUX_PA09I_CCL1_IN6                         _UINT32_(8) 
+#define PINMUX_PA09I_CCL1_IN6                      ((PIN_PA09I_CCL1_IN6 << 16) | MUX_PA09I_CCL1_IN6)
+#define PORT_PA09I_CCL1_IN6                        (_UINT32_(1) << 9)
+
+#define PIN_PA17I_CCL1_IN7                         _UINT32_(17)
+#define MUX_PA17I_CCL1_IN7                         _UINT32_(8) 
+#define PINMUX_PA17I_CCL1_IN7                      ((PIN_PA17I_CCL1_IN7 << 16) | MUX_PA17I_CCL1_IN7)
+#define PORT_PA17I_CCL1_IN7                        (_UINT32_(1) << 17)
+
+#define PIN_PA06I_CCL1_IN7                         _UINT32_(6) 
+#define MUX_PA06I_CCL1_IN7                         _UINT32_(8) 
+#define PINMUX_PA06I_CCL1_IN7                      ((PIN_PA06I_CCL1_IN7 << 16) | MUX_PA06I_CCL1_IN7)
+#define PORT_PA06I_CCL1_IN7                        (_UINT32_(1) << 6)
+
+#define PIN_PA11I_CCL1_IN8                         _UINT32_(11)
+#define MUX_PA11I_CCL1_IN8                         _UINT32_(8) 
+#define PINMUX_PA11I_CCL1_IN8                      ((PIN_PA11I_CCL1_IN8 << 16) | MUX_PA11I_CCL1_IN8)
+#define PORT_PA11I_CCL1_IN8                        (_UINT32_(1) << 11)
+
+#define PIN_PA12I_CCL1_IN8                         _UINT32_(12)
+#define MUX_PA12I_CCL1_IN8                         _UINT32_(8) 
+#define PINMUX_PA12I_CCL1_IN8                      ((PIN_PA12I_CCL1_IN8 << 16) | MUX_PA12I_CCL1_IN8)
+#define PORT_PA12I_CCL1_IN8                        (_UINT32_(1) << 12)
+
+#define PIN_PB11I_CCL1_IN9                         _UINT32_(43)
+#define MUX_PB11I_CCL1_IN9                         _UINT32_(8) 
+#define PINMUX_PB11I_CCL1_IN9                      ((PIN_PB11I_CCL1_IN9 << 16) | MUX_PB11I_CCL1_IN9)
+#define PORT_PB11I_CCL1_IN9                        (_UINT32_(1) << 11)
+
+#define PIN_PB04I_CCL1_IN9                         _UINT32_(36)
+#define MUX_PB04I_CCL1_IN9                         _UINT32_(8) 
+#define PINMUX_PB04I_CCL1_IN9                      ((PIN_PB04I_CCL1_IN9 << 16) | MUX_PB04I_CCL1_IN9)
+#define PORT_PB04I_CCL1_IN9                        (_UINT32_(1) << 4)
+
+#define PIN_PB13I_CCL1_IN10                        _UINT32_(45)
+#define MUX_PB13I_CCL1_IN10                        _UINT32_(8) 
+#define PINMUX_PB13I_CCL1_IN10                     ((PIN_PB13I_CCL1_IN10 << 16) | MUX_PB13I_CCL1_IN10)
+#define PORT_PB13I_CCL1_IN10                       (_UINT32_(1) << 13)
+
+#define PIN_PB03I_CCL1_IN10                        _UINT32_(35)
+#define MUX_PB03I_CCL1_IN10                        _UINT32_(8) 
+#define PINMUX_PB03I_CCL1_IN10                     ((PIN_PB03I_CCL1_IN10 << 16) | MUX_PB03I_CCL1_IN10)
+#define PORT_PB03I_CCL1_IN10                       (_UINT32_(1) << 3)
+
+#define PIN_PB07I_CCL1_IN11                        _UINT32_(39)
+#define MUX_PB07I_CCL1_IN11                        _UINT32_(8) 
+#define PINMUX_PB07I_CCL1_IN11                     ((PIN_PB07I_CCL1_IN11 << 16) | MUX_PB07I_CCL1_IN11)
+#define PORT_PB07I_CCL1_IN11                       (_UINT32_(1) << 7)
+
+#define PIN_PB08I_CCL1_IN11                        _UINT32_(40)
+#define MUX_PB08I_CCL1_IN11                        _UINT32_(8) 
+#define PINMUX_PB08I_CCL1_IN11                     ((PIN_PB08I_CCL1_IN11 << 16) | MUX_PB08I_CCL1_IN11)
+#define PORT_PB08I_CCL1_IN11                       (_UINT32_(1) << 8)
+
+#define PIN_PC19I_CCL1_OUT0                        _UINT32_(83)
+#define MUX_PC19I_CCL1_OUT0                        _UINT32_(8) 
+#define PINMUX_PC19I_CCL1_OUT0                     ((PIN_PC19I_CCL1_OUT0 << 16) | MUX_PC19I_CCL1_OUT0)
+#define PORT_PC19I_CCL1_OUT0                       (_UINT32_(1) << 19)
+
+#define PIN_PC06I_CCL1_OUT0                        _UINT32_(70)
+#define MUX_PC06I_CCL1_OUT0                        _UINT32_(8) 
+#define PINMUX_PC06I_CCL1_OUT0                     ((PIN_PC06I_CCL1_OUT0 << 16) | MUX_PC06I_CCL1_OUT0)
+#define PORT_PC06I_CCL1_OUT0                       (_UINT32_(1) << 6)
+
+#define PIN_PD15I_CCL1_OUT1                        _UINT32_(111)
+#define MUX_PD15I_CCL1_OUT1                        _UINT32_(8) 
+#define PINMUX_PD15I_CCL1_OUT1                     ((PIN_PD15I_CCL1_OUT1 << 16) | MUX_PD15I_CCL1_OUT1)
+#define PORT_PD15I_CCL1_OUT1                       (_UINT32_(1) << 15)
+
+#define PIN_PD09I_CCL1_OUT1                        _UINT32_(105)
+#define MUX_PD09I_CCL1_OUT1                        _UINT32_(8) 
+#define PINMUX_PD09I_CCL1_OUT1                     ((PIN_PD09I_CCL1_OUT1 << 16) | MUX_PD09I_CCL1_OUT1)
+#define PORT_PD09I_CCL1_OUT1                       (_UINT32_(1) << 9)
+
+#define PIN_PA05I_CCL1_OUT2                        _UINT32_(5) 
+#define MUX_PA05I_CCL1_OUT2                        _UINT32_(8) 
+#define PINMUX_PA05I_CCL1_OUT2                     ((PIN_PA05I_CCL1_OUT2 << 16) | MUX_PA05I_CCL1_OUT2)
+#define PORT_PA05I_CCL1_OUT2                       (_UINT32_(1) << 5)
+
+#define PIN_PA20I_CCL1_OUT2                        _UINT32_(20)
+#define MUX_PA20I_CCL1_OUT2                        _UINT32_(8) 
+#define PINMUX_PA20I_CCL1_OUT2                     ((PIN_PA20I_CCL1_OUT2 << 16) | MUX_PA20I_CCL1_OUT2)
+#define PORT_PA20I_CCL1_OUT2                       (_UINT32_(1) << 20)
+
+#define PIN_PB00I_CCL1_OUT3                        _UINT32_(32)
+#define MUX_PB00I_CCL1_OUT3                        _UINT32_(8) 
+#define PINMUX_PB00I_CCL1_OUT3                     ((PIN_PB00I_CCL1_OUT3 << 16) | MUX_PB00I_CCL1_OUT3)
+#define PORT_PB00I_CCL1_OUT3                       (_UINT32_(1) << 0)
+
+#define PIN_PB17I_CCL1_OUT3                        _UINT32_(49)
+#define MUX_PB17I_CCL1_OUT3                        _UINT32_(8) 
+#define PINMUX_PB17I_CCL1_OUT3                     ((PIN_PB17I_CCL1_OUT3 << 16) | MUX_PB17I_CCL1_OUT3)
+#define PORT_PB17I_CCL1_OUT3                       (_UINT32_(1) << 17)
+
+/* =================== PORT definition for EIC peripheral =================== */
+#define PIN_PA00A_EIC_EXTINT0                      _UINT32_(0) 
+#define MUX_PA00A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PA00A_EIC_EXTINT0                   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0                     (_UINT32_(1) << 0)
+#define PIN_PA00A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PA00 External Interrupt Line */
+
+#define PIN_PA16A_EIC_EXTINT0                      _UINT32_(16)
+#define MUX_PA16A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PA16A_EIC_EXTINT0                   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0                     (_UINT32_(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PA16 External Interrupt Line */
+
+#define PIN_PB00A_EIC_EXTINT0                      _UINT32_(32)
+#define MUX_PB00A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PB00A_EIC_EXTINT0                   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0                     (_UINT32_(1) << 0)
+#define PIN_PB00A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PB00 External Interrupt Line */
+
+#define PIN_PB15A_EIC_EXTINT0                      _UINT32_(47)
+#define MUX_PB15A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PB15A_EIC_EXTINT0                   ((PIN_PB15A_EIC_EXTINT0 << 16) | MUX_PB15A_EIC_EXTINT0)
+#define PORT_PB15A_EIC_EXTINT0                     (_UINT32_(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PB15 External Interrupt Line */
+
+#define PIN_PC00A_EIC_EXTINT0                      _UINT32_(64)
+#define MUX_PC00A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PC00A_EIC_EXTINT0                   ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
+#define PORT_PC00A_EIC_EXTINT0                     (_UINT32_(1) << 0)
+#define PIN_PC00A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PC00 External Interrupt Line */
+
+#define PIN_PC16A_EIC_EXTINT0                      _UINT32_(80)
+#define MUX_PC16A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PC16A_EIC_EXTINT0                   ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0)
+#define PORT_PC16A_EIC_EXTINT0                     (_UINT32_(1) << 16)
+#define PIN_PC16A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PC16 External Interrupt Line */
+
+#define PIN_PD18A_EIC_EXTINT0                      _UINT32_(114)
+#define MUX_PD18A_EIC_EXTINT0                      _UINT32_(0) 
+#define PINMUX_PD18A_EIC_EXTINT0                   ((PIN_PD18A_EIC_EXTINT0 << 16) | MUX_PD18A_EIC_EXTINT0)
+#define PORT_PD18A_EIC_EXTINT0                     (_UINT32_(1) << 18)
+#define PIN_PD18A_EIC_EXTINT_NUM                   _UINT32_(0)  /* EIC signal: PIN_PD18 External Interrupt Line */
+
+#define PIN_PA01A_EIC_EXTINT1                      _UINT32_(1) 
+#define MUX_PA01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PA01A_EIC_EXTINT1                   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PA01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PA01 External Interrupt Line */
+
+#define PIN_PA17A_EIC_EXTINT1                      _UINT32_(17)
+#define MUX_PA17A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PA17A_EIC_EXTINT1                   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1                     (_UINT32_(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PA17 External Interrupt Line */
+
+#define PIN_PB01A_EIC_EXTINT1                      _UINT32_(33)
+#define MUX_PB01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PB01A_EIC_EXTINT1                   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PB01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PB01 External Interrupt Line */
+
+#define PIN_PB16A_EIC_EXTINT1                      _UINT32_(48)
+#define MUX_PB16A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PB16A_EIC_EXTINT1                   ((PIN_PB16A_EIC_EXTINT1 << 16) | MUX_PB16A_EIC_EXTINT1)
+#define PORT_PB16A_EIC_EXTINT1                     (_UINT32_(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PB16 External Interrupt Line */
+
+#define PIN_PC01A_EIC_EXTINT1                      _UINT32_(65)
+#define MUX_PC01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PC01A_EIC_EXTINT1                   ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
+#define PORT_PC01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PC01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PC01 External Interrupt Line */
+
+#define PIN_PC17A_EIC_EXTINT1                      _UINT32_(81)
+#define MUX_PC17A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PC17A_EIC_EXTINT1                   ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1)
+#define PORT_PC17A_EIC_EXTINT1                     (_UINT32_(1) << 17)
+#define PIN_PC17A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PC17 External Interrupt Line */
+
+#define PIN_PD01A_EIC_EXTINT1                      _UINT32_(97)
+#define MUX_PD01A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PD01A_EIC_EXTINT1                   ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1)
+#define PORT_PD01A_EIC_EXTINT1                     (_UINT32_(1) << 1)
+#define PIN_PD01A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PD01 External Interrupt Line */
+
+#define PIN_PD19A_EIC_EXTINT1                      _UINT32_(115)
+#define MUX_PD19A_EIC_EXTINT1                      _UINT32_(0) 
+#define PINMUX_PD19A_EIC_EXTINT1                   ((PIN_PD19A_EIC_EXTINT1 << 16) | MUX_PD19A_EIC_EXTINT1)
+#define PORT_PD19A_EIC_EXTINT1                     (_UINT32_(1) << 19)
+#define PIN_PD19A_EIC_EXTINT_NUM                   _UINT32_(1)  /* EIC signal: PIN_PD19 External Interrupt Line */
+
+#define PIN_PA02A_EIC_EXTINT2                      _UINT32_(2) 
+#define MUX_PA02A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PA02A_EIC_EXTINT2                   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2                     (_UINT32_(1) << 2)
+#define PIN_PA02A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PA02 External Interrupt Line */
+
+#define PIN_PA18A_EIC_EXTINT2                      _UINT32_(18)
+#define MUX_PA18A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PA18A_EIC_EXTINT2                   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2                     (_UINT32_(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PA18 External Interrupt Line */
+
+#define PIN_PB02A_EIC_EXTINT2                      _UINT32_(34)
+#define MUX_PB02A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PB02A_EIC_EXTINT2                   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2                     (_UINT32_(1) << 2)
+#define PIN_PB02A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PB02 External Interrupt Line */
+
+#define PIN_PB12A_EIC_EXTINT2                      _UINT32_(44)
+#define MUX_PB12A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PB12A_EIC_EXTINT2                   ((PIN_PB12A_EIC_EXTINT2 << 16) | MUX_PB12A_EIC_EXTINT2)
+#define PORT_PB12A_EIC_EXTINT2                     (_UINT32_(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PB12 External Interrupt Line */
+
+#define PIN_PB17A_EIC_EXTINT2                      _UINT32_(49)
+#define MUX_PB17A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PB17A_EIC_EXTINT2                   ((PIN_PB17A_EIC_EXTINT2 << 16) | MUX_PB17A_EIC_EXTINT2)
+#define PORT_PB17A_EIC_EXTINT2                     (_UINT32_(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PB17 External Interrupt Line */
+
+#define PIN_PC02A_EIC_EXTINT2                      _UINT32_(66)
+#define MUX_PC02A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PC02A_EIC_EXTINT2                   ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
+#define PORT_PC02A_EIC_EXTINT2                     (_UINT32_(1) << 2)
+#define PIN_PC02A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PC02 External Interrupt Line */
+
+#define PIN_PC18A_EIC_EXTINT2                      _UINT32_(82)
+#define MUX_PC18A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PC18A_EIC_EXTINT2                   ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2)
+#define PORT_PC18A_EIC_EXTINT2                     (_UINT32_(1) << 18)
+#define PIN_PC18A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PC18 External Interrupt Line */
+
+#define PIN_PD04A_EIC_EXTINT2                      _UINT32_(100)
+#define MUX_PD04A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PD04A_EIC_EXTINT2                   ((PIN_PD04A_EIC_EXTINT2 << 16) | MUX_PD04A_EIC_EXTINT2)
+#define PORT_PD04A_EIC_EXTINT2                     (_UINT32_(1) << 4)
+#define PIN_PD04A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PD04 External Interrupt Line */
+
+#define PIN_PD20A_EIC_EXTINT2                      _UINT32_(116)
+#define MUX_PD20A_EIC_EXTINT2                      _UINT32_(0) 
+#define PINMUX_PD20A_EIC_EXTINT2                   ((PIN_PD20A_EIC_EXTINT2 << 16) | MUX_PD20A_EIC_EXTINT2)
+#define PORT_PD20A_EIC_EXTINT2                     (_UINT32_(1) << 20)
+#define PIN_PD20A_EIC_EXTINT_NUM                   _UINT32_(2)  /* EIC signal: PIN_PD20 External Interrupt Line */
+
+#define PIN_PA03A_EIC_EXTINT3                      _UINT32_(3) 
+#define MUX_PA03A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PA03A_EIC_EXTINT3                   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3                     (_UINT32_(1) << 3)
+#define PIN_PA03A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PA03 External Interrupt Line */
+
+#define PIN_PA19A_EIC_EXTINT3                      _UINT32_(19)
+#define MUX_PA19A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PA19A_EIC_EXTINT3                   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3                     (_UINT32_(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PA19 External Interrupt Line */
+
+#define PIN_PB03A_EIC_EXTINT3                      _UINT32_(35)
+#define MUX_PB03A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PB03A_EIC_EXTINT3                   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3                     (_UINT32_(1) << 3)
+#define PIN_PB03A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PB03 External Interrupt Line */
+
+#define PIN_PC03A_EIC_EXTINT3                      _UINT32_(67)
+#define MUX_PC03A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PC03A_EIC_EXTINT3                   ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
+#define PORT_PC03A_EIC_EXTINT3                     (_UINT32_(1) << 3)
+#define PIN_PC03A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PC03 External Interrupt Line */
+
+#define PIN_PC19A_EIC_EXTINT3                      _UINT32_(83)
+#define MUX_PC19A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PC19A_EIC_EXTINT3                   ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3)
+#define PORT_PC19A_EIC_EXTINT3                     (_UINT32_(1) << 19)
+#define PIN_PC19A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PC19 External Interrupt Line */
+
+#define PIN_PD05A_EIC_EXTINT3                      _UINT32_(101)
+#define MUX_PD05A_EIC_EXTINT3                      _UINT32_(0) 
+#define PINMUX_PD05A_EIC_EXTINT3                   ((PIN_PD05A_EIC_EXTINT3 << 16) | MUX_PD05A_EIC_EXTINT3)
+#define PORT_PD05A_EIC_EXTINT3                     (_UINT32_(1) << 5)
+#define PIN_PD05A_EIC_EXTINT_NUM                   _UINT32_(3)  /* EIC signal: PIN_PD05 External Interrupt Line */
+
+#define PIN_PA04A_EIC_EXTINT4                      _UINT32_(4) 
+#define MUX_PA04A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PA04A_EIC_EXTINT4                   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4                     (_UINT32_(1) << 4)
+#define PIN_PA04A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PA04 External Interrupt Line */
+
+#define PIN_PA20A_EIC_EXTINT4                      _UINT32_(20)
+#define MUX_PA20A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PA20A_EIC_EXTINT4                   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4                     (_UINT32_(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PA20 External Interrupt Line */
+
+#define PIN_PB04A_EIC_EXTINT4                      _UINT32_(36)
+#define MUX_PB04A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PB04A_EIC_EXTINT4                   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4                     (_UINT32_(1) << 4)
+#define PIN_PB04A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PB04 External Interrupt Line */
+
+#define PIN_PC04A_EIC_EXTINT4                      _UINT32_(68)
+#define MUX_PC04A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PC04A_EIC_EXTINT4                   ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4)
+#define PORT_PC04A_EIC_EXTINT4                     (_UINT32_(1) << 4)
+#define PIN_PC04A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PC04 External Interrupt Line */
+
+#define PIN_PD07A_EIC_EXTINT4                      _UINT32_(103)
+#define MUX_PD07A_EIC_EXTINT4                      _UINT32_(0) 
+#define PINMUX_PD07A_EIC_EXTINT4                   ((PIN_PD07A_EIC_EXTINT4 << 16) | MUX_PD07A_EIC_EXTINT4)
+#define PORT_PD07A_EIC_EXTINT4                     (_UINT32_(1) << 7)
+#define PIN_PD07A_EIC_EXTINT_NUM                   _UINT32_(4)  /* EIC signal: PIN_PD07 External Interrupt Line */
+
+#define PIN_PA05A_EIC_EXTINT5                      _UINT32_(5) 
+#define MUX_PA05A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PA05A_EIC_EXTINT5                   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5                     (_UINT32_(1) << 5)
+#define PIN_PA05A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PA05 External Interrupt Line */
+
+#define PIN_PB05A_EIC_EXTINT5                      _UINT32_(37)
+#define MUX_PB05A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PB05A_EIC_EXTINT5                   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5                     (_UINT32_(1) << 5)
+#define PIN_PB05A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PB05 External Interrupt Line */
+
+#define PIN_PC05A_EIC_EXTINT5                      _UINT32_(69)
+#define MUX_PC05A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PC05A_EIC_EXTINT5                   ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
+#define PORT_PC05A_EIC_EXTINT5                     (_UINT32_(1) << 5)
+#define PIN_PC05A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PC05 External Interrupt Line */
+
+#define PIN_PD08A_EIC_EXTINT5                      _UINT32_(104)
+#define MUX_PD08A_EIC_EXTINT5                      _UINT32_(0) 
+#define PINMUX_PD08A_EIC_EXTINT5                   ((PIN_PD08A_EIC_EXTINT5 << 16) | MUX_PD08A_EIC_EXTINT5)
+#define PORT_PD08A_EIC_EXTINT5                     (_UINT32_(1) << 8)
+#define PIN_PD08A_EIC_EXTINT_NUM                   _UINT32_(5)  /* EIC signal: PIN_PD08 External Interrupt Line */
+
+#define PIN_PA06A_EIC_EXTINT6                      _UINT32_(6) 
+#define MUX_PA06A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PA06A_EIC_EXTINT6                   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6                     (_UINT32_(1) << 6)
+#define PIN_PA06A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PA06 External Interrupt Line */
+
+#define PIN_PB06A_EIC_EXTINT6                      _UINT32_(38)
+#define MUX_PB06A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PB06A_EIC_EXTINT6                   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6                     (_UINT32_(1) << 6)
+#define PIN_PB06A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PB06 External Interrupt Line */
+
+#define PIN_PC06A_EIC_EXTINT6                      _UINT32_(70)
+#define MUX_PC06A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PC06A_EIC_EXTINT6                   ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
+#define PORT_PC06A_EIC_EXTINT6                     (_UINT32_(1) << 6)
+#define PIN_PC06A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PC06 External Interrupt Line */
+
+#define PIN_PD09A_EIC_EXTINT6                      _UINT32_(105)
+#define MUX_PD09A_EIC_EXTINT6                      _UINT32_(0) 
+#define PINMUX_PD09A_EIC_EXTINT6                   ((PIN_PD09A_EIC_EXTINT6 << 16) | MUX_PD09A_EIC_EXTINT6)
+#define PORT_PD09A_EIC_EXTINT6                     (_UINT32_(1) << 9)
+#define PIN_PD09A_EIC_EXTINT_NUM                   _UINT32_(6)  /* EIC signal: PIN_PD09 External Interrupt Line */
+
+#define PIN_PA07A_EIC_EXTINT7                      _UINT32_(7) 
+#define MUX_PA07A_EIC_EXTINT7                      _UINT32_(0) 
+#define PINMUX_PA07A_EIC_EXTINT7                   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7                     (_UINT32_(1) << 7)
+#define PIN_PA07A_EIC_EXTINT_NUM                   _UINT32_(7)  /* EIC signal: PIN_PA07 External Interrupt Line */
+
+#define PIN_PA08A_EIC_EXTINT8                      _UINT32_(8) 
+#define MUX_PA08A_EIC_EXTINT8                      _UINT32_(0) 
+#define PINMUX_PA08A_EIC_EXTINT8                   ((PIN_PA08A_EIC_EXTINT8 << 16) | MUX_PA08A_EIC_EXTINT8)
+#define PORT_PA08A_EIC_EXTINT8                     (_UINT32_(1) << 8)
+#define PIN_PA08A_EIC_EXTINT_NUM                   _UINT32_(8)  /* EIC signal: PIN_PA08 External Interrupt Line */
+
+#define PIN_PB07A_EIC_EXTINT8                      _UINT32_(39)
+#define MUX_PB07A_EIC_EXTINT8                      _UINT32_(0) 
+#define PINMUX_PB07A_EIC_EXTINT8                   ((PIN_PB07A_EIC_EXTINT8 << 16) | MUX_PB07A_EIC_EXTINT8)
+#define PORT_PB07A_EIC_EXTINT8                     (_UINT32_(1) << 7)
+#define PIN_PB07A_EIC_EXTINT_NUM                   _UINT32_(8)  /* EIC signal: PIN_PB07 External Interrupt Line */
+
+#define PIN_PD10A_EIC_EXTINT8                      _UINT32_(106)
+#define MUX_PD10A_EIC_EXTINT8                      _UINT32_(0) 
+#define PINMUX_PD10A_EIC_EXTINT8                   ((PIN_PD10A_EIC_EXTINT8 << 16) | MUX_PD10A_EIC_EXTINT8)
+#define PORT_PD10A_EIC_EXTINT8                     (_UINT32_(1) << 10)
+#define PIN_PD10A_EIC_EXTINT_NUM                   _UINT32_(8)  /* EIC signal: PIN_PD10 External Interrupt Line */
+
+#define PIN_PA09A_EIC_EXTINT9                      _UINT32_(9) 
+#define MUX_PA09A_EIC_EXTINT9                      _UINT32_(0) 
+#define PINMUX_PA09A_EIC_EXTINT9                   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9                     (_UINT32_(1) << 9)
+#define PIN_PA09A_EIC_EXTINT_NUM                   _UINT32_(9)  /* EIC signal: PIN_PA09 External Interrupt Line */
+
+#define PIN_PB08A_EIC_EXTINT9                      _UINT32_(40)
+#define MUX_PB08A_EIC_EXTINT9                      _UINT32_(0) 
+#define PINMUX_PB08A_EIC_EXTINT9                   ((PIN_PB08A_EIC_EXTINT9 << 16) | MUX_PB08A_EIC_EXTINT9)
+#define PORT_PB08A_EIC_EXTINT9                     (_UINT32_(1) << 8)
+#define PIN_PB08A_EIC_EXTINT_NUM                   _UINT32_(9)  /* EIC signal: PIN_PB08 External Interrupt Line */
+
+#define PIN_PC09A_EIC_EXTINT9                      _UINT32_(73)
+#define MUX_PC09A_EIC_EXTINT9                      _UINT32_(0) 
+#define PINMUX_PC09A_EIC_EXTINT9                   ((PIN_PC09A_EIC_EXTINT9 << 16) | MUX_PC09A_EIC_EXTINT9)
+#define PORT_PC09A_EIC_EXTINT9                     (_UINT32_(1) << 9)
+#define PIN_PC09A_EIC_EXTINT_NUM                   _UINT32_(9)  /* EIC signal: PIN_PC09 External Interrupt Line */
+
+#define PIN_PD11A_EIC_EXTINT9                      _UINT32_(107)
+#define MUX_PD11A_EIC_EXTINT9                      _UINT32_(0) 
+#define PINMUX_PD11A_EIC_EXTINT9                   ((PIN_PD11A_EIC_EXTINT9 << 16) | MUX_PD11A_EIC_EXTINT9)
+#define PORT_PD11A_EIC_EXTINT9                     (_UINT32_(1) << 11)
+#define PIN_PD11A_EIC_EXTINT_NUM                   _UINT32_(9)  /* EIC signal: PIN_PD11 External Interrupt Line */
+
+#define PIN_PA10A_EIC_EXTINT10                     _UINT32_(10)
+#define MUX_PA10A_EIC_EXTINT10                     _UINT32_(0) 
+#define PINMUX_PA10A_EIC_EXTINT10                  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10                    (_UINT32_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM                   _UINT32_(10) /* EIC signal: PIN_PA10 External Interrupt Line */
+
+#define PIN_PB09A_EIC_EXTINT10                     _UINT32_(41)
+#define MUX_PB09A_EIC_EXTINT10                     _UINT32_(0) 
+#define PINMUX_PB09A_EIC_EXTINT10                  ((PIN_PB09A_EIC_EXTINT10 << 16) | MUX_PB09A_EIC_EXTINT10)
+#define PORT_PB09A_EIC_EXTINT10                    (_UINT32_(1) << 9)
+#define PIN_PB09A_EIC_EXTINT_NUM                   _UINT32_(10) /* EIC signal: PIN_PB09 External Interrupt Line */
+
+#define PIN_PC10A_EIC_EXTINT10                     _UINT32_(74)
+#define MUX_PC10A_EIC_EXTINT10                     _UINT32_(0) 
+#define PINMUX_PC10A_EIC_EXTINT10                  ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10)
+#define PORT_PC10A_EIC_EXTINT10                    (_UINT32_(1) << 10)
+#define PIN_PC10A_EIC_EXTINT_NUM                   _UINT32_(10) /* EIC signal: PIN_PC10 External Interrupt Line */
+
+#define PIN_PD12A_EIC_EXTINT10                     _UINT32_(108)
+#define MUX_PD12A_EIC_EXTINT10                     _UINT32_(0) 
+#define PINMUX_PD12A_EIC_EXTINT10                  ((PIN_PD12A_EIC_EXTINT10 << 16) | MUX_PD12A_EIC_EXTINT10)
+#define PORT_PD12A_EIC_EXTINT10                    (_UINT32_(1) << 12)
+#define PIN_PD12A_EIC_EXTINT_NUM                   _UINT32_(10) /* EIC signal: PIN_PD12 External Interrupt Line */
+
+#define PIN_PA11A_EIC_EXTINT11                     _UINT32_(11)
+#define MUX_PA11A_EIC_EXTINT11                     _UINT32_(0) 
+#define PINMUX_PA11A_EIC_EXTINT11                  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11                    (_UINT32_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM                   _UINT32_(11) /* EIC signal: PIN_PA11 External Interrupt Line */
+
+#define PIN_PB10A_EIC_EXTINT11                     _UINT32_(42)
+#define MUX_PB10A_EIC_EXTINT11                     _UINT32_(0) 
+#define PINMUX_PB10A_EIC_EXTINT11                  ((PIN_PB10A_EIC_EXTINT11 << 16) | MUX_PB10A_EIC_EXTINT11)
+#define PORT_PB10A_EIC_EXTINT11                    (_UINT32_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM                   _UINT32_(11) /* EIC signal: PIN_PB10 External Interrupt Line */
+
+#define PIN_PC11A_EIC_EXTINT11                     _UINT32_(75)
+#define MUX_PC11A_EIC_EXTINT11                     _UINT32_(0) 
+#define PINMUX_PC11A_EIC_EXTINT11                  ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11)
+#define PORT_PC11A_EIC_EXTINT11                    (_UINT32_(1) << 11)
+#define PIN_PC11A_EIC_EXTINT_NUM                   _UINT32_(11) /* EIC signal: PIN_PC11 External Interrupt Line */
+
+#define PIN_PD13A_EIC_EXTINT11                     _UINT32_(109)
+#define MUX_PD13A_EIC_EXTINT11                     _UINT32_(0) 
+#define PINMUX_PD13A_EIC_EXTINT11                  ((PIN_PD13A_EIC_EXTINT11 << 16) | MUX_PD13A_EIC_EXTINT11)
+#define PORT_PD13A_EIC_EXTINT11                    (_UINT32_(1) << 13)
+#define PIN_PD13A_EIC_EXTINT_NUM                   _UINT32_(11) /* EIC signal: PIN_PD13 External Interrupt Line */
+
+#define PIN_PA12A_EIC_EXTINT12                     _UINT32_(12)
+#define MUX_PA12A_EIC_EXTINT12                     _UINT32_(0) 
+#define PINMUX_PA12A_EIC_EXTINT12                  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12                    (_UINT32_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM                   _UINT32_(12) /* EIC signal: PIN_PA12 External Interrupt Line */
+
+#define PIN_PB11A_EIC_EXTINT12                     _UINT32_(43)
+#define MUX_PB11A_EIC_EXTINT12                     _UINT32_(0) 
+#define PINMUX_PB11A_EIC_EXTINT12                  ((PIN_PB11A_EIC_EXTINT12 << 16) | MUX_PB11A_EIC_EXTINT12)
+#define PORT_PB11A_EIC_EXTINT12                    (_UINT32_(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM                   _UINT32_(12) /* EIC signal: PIN_PB11 External Interrupt Line */
+
+#define PIN_PC12A_EIC_EXTINT12                     _UINT32_(76)
+#define MUX_PC12A_EIC_EXTINT12                     _UINT32_(0) 
+#define PINMUX_PC12A_EIC_EXTINT12                  ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12)
+#define PORT_PC12A_EIC_EXTINT12                    (_UINT32_(1) << 12)
+#define PIN_PC12A_EIC_EXTINT_NUM                   _UINT32_(12) /* EIC signal: PIN_PC12 External Interrupt Line */
+
+#define PIN_PD14A_EIC_EXTINT12                     _UINT32_(110)
+#define MUX_PD14A_EIC_EXTINT12                     _UINT32_(0) 
+#define PINMUX_PD14A_EIC_EXTINT12                  ((PIN_PD14A_EIC_EXTINT12 << 16) | MUX_PD14A_EIC_EXTINT12)
+#define PORT_PD14A_EIC_EXTINT12                    (_UINT32_(1) << 14)
+#define PIN_PD14A_EIC_EXTINT_NUM                   _UINT32_(12) /* EIC signal: PIN_PD14 External Interrupt Line */
+
+#define PIN_PA13A_EIC_EXTINT13                     _UINT32_(13)
+#define MUX_PA13A_EIC_EXTINT13                     _UINT32_(0) 
+#define PINMUX_PA13A_EIC_EXTINT13                  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13                    (_UINT32_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM                   _UINT32_(13) /* EIC signal: PIN_PA13 External Interrupt Line */
+
+#define PIN_PC13A_EIC_EXTINT13                     _UINT32_(77)
+#define MUX_PC13A_EIC_EXTINT13                     _UINT32_(0) 
+#define PINMUX_PC13A_EIC_EXTINT13                  ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13)
+#define PORT_PC13A_EIC_EXTINT13                    (_UINT32_(1) << 13)
+#define PIN_PC13A_EIC_EXTINT_NUM                   _UINT32_(13) /* EIC signal: PIN_PC13 External Interrupt Line */
+
+#define PIN_PD15A_EIC_EXTINT13                     _UINT32_(111)
+#define MUX_PD15A_EIC_EXTINT13                     _UINT32_(0) 
+#define PINMUX_PD15A_EIC_EXTINT13                  ((PIN_PD15A_EIC_EXTINT13 << 16) | MUX_PD15A_EIC_EXTINT13)
+#define PORT_PD15A_EIC_EXTINT13                    (_UINT32_(1) << 15)
+#define PIN_PD15A_EIC_EXTINT_NUM                   _UINT32_(13) /* EIC signal: PIN_PD15 External Interrupt Line */
+
+#define PIN_PA14A_EIC_EXTINT14                     _UINT32_(14)
+#define MUX_PA14A_EIC_EXTINT14                     _UINT32_(0) 
+#define PINMUX_PA14A_EIC_EXTINT14                  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14                    (_UINT32_(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM                   _UINT32_(14) /* EIC signal: PIN_PA14 External Interrupt Line */
+
+#define PIN_PB13A_EIC_EXTINT14                     _UINT32_(45)
+#define MUX_PB13A_EIC_EXTINT14                     _UINT32_(0) 
+#define PINMUX_PB13A_EIC_EXTINT14                  ((PIN_PB13A_EIC_EXTINT14 << 16) | MUX_PB13A_EIC_EXTINT14)
+#define PORT_PB13A_EIC_EXTINT14                    (_UINT32_(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM                   _UINT32_(14) /* EIC signal: PIN_PB13 External Interrupt Line */
+
+#define PIN_PC14A_EIC_EXTINT14                     _UINT32_(78)
+#define MUX_PC14A_EIC_EXTINT14                     _UINT32_(0) 
+#define PINMUX_PC14A_EIC_EXTINT14                  ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14)
+#define PORT_PC14A_EIC_EXTINT14                    (_UINT32_(1) << 14)
+#define PIN_PC14A_EIC_EXTINT_NUM                   _UINT32_(14) /* EIC signal: PIN_PC14 External Interrupt Line */
+
+#define PIN_PD16A_EIC_EXTINT14                     _UINT32_(112)
+#define MUX_PD16A_EIC_EXTINT14                     _UINT32_(0) 
+#define PINMUX_PD16A_EIC_EXTINT14                  ((PIN_PD16A_EIC_EXTINT14 << 16) | MUX_PD16A_EIC_EXTINT14)
+#define PORT_PD16A_EIC_EXTINT14                    (_UINT32_(1) << 16)
+#define PIN_PD16A_EIC_EXTINT_NUM                   _UINT32_(14) /* EIC signal: PIN_PD16 External Interrupt Line */
+
+#define PIN_PA15A_EIC_EXTINT15                     _UINT32_(15)
+#define MUX_PA15A_EIC_EXTINT15                     _UINT32_(0) 
+#define PINMUX_PA15A_EIC_EXTINT15                  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15                    (_UINT32_(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM                   _UINT32_(15) /* EIC signal: PIN_PA15 External Interrupt Line */
+
+#define PIN_PB14A_EIC_EXTINT15                     _UINT32_(46)
+#define MUX_PB14A_EIC_EXTINT15                     _UINT32_(0) 
+#define PINMUX_PB14A_EIC_EXTINT15                  ((PIN_PB14A_EIC_EXTINT15 << 16) | MUX_PB14A_EIC_EXTINT15)
+#define PORT_PB14A_EIC_EXTINT15                    (_UINT32_(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM                   _UINT32_(15) /* EIC signal: PIN_PB14 External Interrupt Line */
+
+#define PIN_PC15A_EIC_EXTINT15                     _UINT32_(79)
+#define MUX_PC15A_EIC_EXTINT15                     _UINT32_(0) 
+#define PINMUX_PC15A_EIC_EXTINT15                  ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15)
+#define PORT_PC15A_EIC_EXTINT15                    (_UINT32_(1) << 15)
+#define PIN_PC15A_EIC_EXTINT_NUM                   _UINT32_(15) /* EIC signal: PIN_PC15 External Interrupt Line */
+
+#define PIN_PD17A_EIC_EXTINT15                     _UINT32_(113)
+#define MUX_PD17A_EIC_EXTINT15                     _UINT32_(0) 
+#define PINMUX_PD17A_EIC_EXTINT15                  ((PIN_PD17A_EIC_EXTINT15 << 16) | MUX_PD17A_EIC_EXTINT15)
+#define PORT_PD17A_EIC_EXTINT15                    (_UINT32_(1) << 17)
+#define PIN_PD17A_EIC_EXTINT_NUM                   _UINT32_(15) /* EIC signal: PIN_PD17 External Interrupt Line */
+
+#define PIN_PD00A_EIC_NMI                          _UINT32_(96)
+#define MUX_PD00A_EIC_NMI                          _UINT32_(0) 
+#define PINMUX_PD00A_EIC_NMI                       ((PIN_PD00A_EIC_NMI << 16) | MUX_PD00A_EIC_NMI)
+#define PORT_PD00A_EIC_NMI                         (_UINT32_(1) << 0)
+
+/* ================== PORT definition for GCLK peripheral =================== */
+#define PIN_PB06K_GCLK_IO0                         _UINT32_(38)
+#define MUX_PB06K_GCLK_IO0                         _UINT32_(10)
+#define PINMUX_PB06K_GCLK_IO0                      ((PIN_PB06K_GCLK_IO0 << 16) | MUX_PB06K_GCLK_IO0)
+#define PORT_PB06K_GCLK_IO0                        (_UINT32_(1) << 6)
+
+#define PIN_PB15K_GCLK_IO0                         _UINT32_(47)
+#define MUX_PB15K_GCLK_IO0                         _UINT32_(10)
+#define PINMUX_PB15K_GCLK_IO0                      ((PIN_PB15K_GCLK_IO0 << 16) | MUX_PB15K_GCLK_IO0)
+#define PORT_PB15K_GCLK_IO0                        (_UINT32_(1) << 15)
+
+#define PIN_PC09K_GCLK_IO0                         _UINT32_(73)
+#define MUX_PC09K_GCLK_IO0                         _UINT32_(10)
+#define PINMUX_PC09K_GCLK_IO0                      ((PIN_PC09K_GCLK_IO0 << 16) | MUX_PC09K_GCLK_IO0)
+#define PORT_PC09K_GCLK_IO0                        (_UINT32_(1) << 9)
+
+#define PIN_PD05K_GCLK_IO0                         _UINT32_(101)
+#define MUX_PD05K_GCLK_IO0                         _UINT32_(10)
+#define PINMUX_PD05K_GCLK_IO0                      ((PIN_PD05K_GCLK_IO0 << 16) | MUX_PD05K_GCLK_IO0)
+#define PORT_PD05K_GCLK_IO0                        (_UINT32_(1) << 5)
+
+#define PIN_PC00K_GCLK_IO1                         _UINT32_(64)
+#define MUX_PC00K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PC00K_GCLK_IO1                      ((PIN_PC00K_GCLK_IO1 << 16) | MUX_PC00K_GCLK_IO1)
+#define PORT_PC00K_GCLK_IO1                        (_UINT32_(1) << 0)
+
+#define PIN_PC10K_GCLK_IO1                         _UINT32_(74)
+#define MUX_PC10K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PC10K_GCLK_IO1                      ((PIN_PC10K_GCLK_IO1 << 16) | MUX_PC10K_GCLK_IO1)
+#define PORT_PC10K_GCLK_IO1                        (_UINT32_(1) << 10)
+
+#define PIN_PC05K_GCLK_IO1                         _UINT32_(69)
+#define MUX_PC05K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PC05K_GCLK_IO1                      ((PIN_PC05K_GCLK_IO1 << 16) | MUX_PC05K_GCLK_IO1)
+#define PORT_PC05K_GCLK_IO1                        (_UINT32_(1) << 5)
+
+#define PIN_PD04K_GCLK_IO1                         _UINT32_(100)
+#define MUX_PD04K_GCLK_IO1                         _UINT32_(10)
+#define PINMUX_PD04K_GCLK_IO1                      ((PIN_PD04K_GCLK_IO1 << 16) | MUX_PD04K_GCLK_IO1)
+#define PORT_PD04K_GCLK_IO1                        (_UINT32_(1) << 4)
+
+#define PIN_PC01K_GCLK_IO2                         _UINT32_(65)
+#define MUX_PC01K_GCLK_IO2                         _UINT32_(10)
+#define PINMUX_PC01K_GCLK_IO2                      ((PIN_PC01K_GCLK_IO2 << 16) | MUX_PC01K_GCLK_IO2)
+#define PORT_PC01K_GCLK_IO2                        (_UINT32_(1) << 1)
+
+#define PIN_PC02K_GCLK_IO3                         _UINT32_(66)
+#define MUX_PC02K_GCLK_IO3                         _UINT32_(10)
+#define PINMUX_PC02K_GCLK_IO3                      ((PIN_PC02K_GCLK_IO3 << 16) | MUX_PC02K_GCLK_IO3)
+#define PORT_PC02K_GCLK_IO3                        (_UINT32_(1) << 2)
+
+#define PIN_PC03K_GCLK_IO4                         _UINT32_(67)
+#define MUX_PC03K_GCLK_IO4                         _UINT32_(10)
+#define PINMUX_PC03K_GCLK_IO4                      ((PIN_PC03K_GCLK_IO4 << 16) | MUX_PC03K_GCLK_IO4)
+#define PORT_PC03K_GCLK_IO4                        (_UINT32_(1) << 3)
+
+#define PIN_PC04K_GCLK_IO5                         _UINT32_(68)
+#define MUX_PC04K_GCLK_IO5                         _UINT32_(10)
+#define PINMUX_PC04K_GCLK_IO5                      ((PIN_PC04K_GCLK_IO5 << 16) | MUX_PC04K_GCLK_IO5)
+#define PORT_PC04K_GCLK_IO5                        (_UINT32_(1) << 4)
+
+#define PIN_PB16K_GCLK_IO6                         _UINT32_(48)
+#define MUX_PB16K_GCLK_IO6                         _UINT32_(10)
+#define PINMUX_PB16K_GCLK_IO6                      ((PIN_PB16K_GCLK_IO6 << 16) | MUX_PB16K_GCLK_IO6)
+#define PORT_PB16K_GCLK_IO6                        (_UINT32_(1) << 16)
+
+#define PIN_PB10K_GCLK_IO6                         _UINT32_(42)
+#define MUX_PB10K_GCLK_IO6                         _UINT32_(10)
+#define PINMUX_PB10K_GCLK_IO6                      ((PIN_PB10K_GCLK_IO6 << 16) | MUX_PB10K_GCLK_IO6)
+#define PORT_PB10K_GCLK_IO6                        (_UINT32_(1) << 10)
+
+#define PIN_PB09K_GCLK_IO7                         _UINT32_(41)
+#define MUX_PB09K_GCLK_IO7                         _UINT32_(10)
+#define PINMUX_PB09K_GCLK_IO7                      ((PIN_PB09K_GCLK_IO7 << 16) | MUX_PB09K_GCLK_IO7)
+#define PORT_PB09K_GCLK_IO7                        (_UINT32_(1) << 9)
+
+/* =================== PORT definition for PTC peripheral =================== */
+#define PIN_PD06P_PTC_DRV0                         _UINT32_(102)
+#define MUX_PD06P_PTC_DRV0                         _UINT32_(15)
+#define PINMUX_PD06P_PTC_DRV0                      ((PIN_PD06P_PTC_DRV0 << 16) | MUX_PD06P_PTC_DRV0)
+#define PORT_PD06P_PTC_DRV0                        (_UINT32_(1) << 6)
+
+#define PIN_PD07P_PTC_DRV1                         _UINT32_(103)
+#define MUX_PD07P_PTC_DRV1                         _UINT32_(15)
+#define PINMUX_PD07P_PTC_DRV1                      ((PIN_PD07P_PTC_DRV1 << 16) | MUX_PD07P_PTC_DRV1)
+#define PORT_PD07P_PTC_DRV1                        (_UINT32_(1) << 7)
+
+#define PIN_PD08P_PTC_DRV2                         _UINT32_(104)
+#define MUX_PD08P_PTC_DRV2                         _UINT32_(15)
+#define PINMUX_PD08P_PTC_DRV2                      ((PIN_PD08P_PTC_DRV2 << 16) | MUX_PD08P_PTC_DRV2)
+#define PORT_PD08P_PTC_DRV2                        (_UINT32_(1) << 8)
+
+#define PIN_PD09P_PTC_DRV3                         _UINT32_(105)
+#define MUX_PD09P_PTC_DRV3                         _UINT32_(15)
+#define PINMUX_PD09P_PTC_DRV3                      ((PIN_PD09P_PTC_DRV3 << 16) | MUX_PD09P_PTC_DRV3)
+#define PORT_PD09P_PTC_DRV3                        (_UINT32_(1) << 9)
+
+#define PIN_PA00P_PTC_DRV4                         _UINT32_(0) 
+#define MUX_PA00P_PTC_DRV4                         _UINT32_(15)
+#define PINMUX_PA00P_PTC_DRV4                      ((PIN_PA00P_PTC_DRV4 << 16) | MUX_PA00P_PTC_DRV4)
+#define PORT_PA00P_PTC_DRV4                        (_UINT32_(1) << 0)
+
+#define PIN_PA01P_PTC_DRV5                         _UINT32_(1) 
+#define MUX_PA01P_PTC_DRV5                         _UINT32_(15)
+#define PINMUX_PA01P_PTC_DRV5                      ((PIN_PA01P_PTC_DRV5 << 16) | MUX_PA01P_PTC_DRV5)
+#define PORT_PA01P_PTC_DRV5                        (_UINT32_(1) << 1)
+
+#define PIN_PA02P_PTC_DRV6                         _UINT32_(2) 
+#define MUX_PA02P_PTC_DRV6                         _UINT32_(15)
+#define PINMUX_PA02P_PTC_DRV6                      ((PIN_PA02P_PTC_DRV6 << 16) | MUX_PA02P_PTC_DRV6)
+#define PORT_PA02P_PTC_DRV6                        (_UINT32_(1) << 2)
+
+#define PIN_PA03P_PTC_DRV7                         _UINT32_(3) 
+#define MUX_PA03P_PTC_DRV7                         _UINT32_(15)
+#define PINMUX_PA03P_PTC_DRV7                      ((PIN_PA03P_PTC_DRV7 << 16) | MUX_PA03P_PTC_DRV7)
+#define PORT_PA03P_PTC_DRV7                        (_UINT32_(1) << 3)
+
+#define PIN_PA04P_PTC_DRV8                         _UINT32_(4) 
+#define MUX_PA04P_PTC_DRV8                         _UINT32_(15)
+#define PINMUX_PA04P_PTC_DRV8                      ((PIN_PA04P_PTC_DRV8 << 16) | MUX_PA04P_PTC_DRV8)
+#define PORT_PA04P_PTC_DRV8                        (_UINT32_(1) << 4)
+
+#define PIN_PA05P_PTC_DRV9                         _UINT32_(5) 
+#define MUX_PA05P_PTC_DRV9                         _UINT32_(15)
+#define PINMUX_PA05P_PTC_DRV9                      ((PIN_PA05P_PTC_DRV9 << 16) | MUX_PA05P_PTC_DRV9)
+#define PORT_PA05P_PTC_DRV9                        (_UINT32_(1) << 5)
+
+#define PIN_PA06P_PTC_DRV10                        _UINT32_(6) 
+#define MUX_PA06P_PTC_DRV10                        _UINT32_(15)
+#define PINMUX_PA06P_PTC_DRV10                     ((PIN_PA06P_PTC_DRV10 << 16) | MUX_PA06P_PTC_DRV10)
+#define PORT_PA06P_PTC_DRV10                       (_UINT32_(1) << 6)
+
+#define PIN_PA07P_PTC_DRV11                        _UINT32_(7) 
+#define MUX_PA07P_PTC_DRV11                        _UINT32_(15)
+#define PINMUX_PA07P_PTC_DRV11                     ((PIN_PA07P_PTC_DRV11 << 16) | MUX_PA07P_PTC_DRV11)
+#define PORT_PA07P_PTC_DRV11                       (_UINT32_(1) << 7)
+
+#define PIN_PA08P_PTC_DRV12                        _UINT32_(8) 
+#define MUX_PA08P_PTC_DRV12                        _UINT32_(15)
+#define PINMUX_PA08P_PTC_DRV12                     ((PIN_PA08P_PTC_DRV12 << 16) | MUX_PA08P_PTC_DRV12)
+#define PORT_PA08P_PTC_DRV12                       (_UINT32_(1) << 8)
+
+#define PIN_PA09P_PTC_DRV13                        _UINT32_(9) 
+#define MUX_PA09P_PTC_DRV13                        _UINT32_(15)
+#define PINMUX_PA09P_PTC_DRV13                     ((PIN_PA09P_PTC_DRV13 << 16) | MUX_PA09P_PTC_DRV13)
+#define PORT_PA09P_PTC_DRV13                       (_UINT32_(1) << 9)
+
+#define PIN_PB00P_PTC_DRV14                        _UINT32_(32)
+#define MUX_PB00P_PTC_DRV14                        _UINT32_(15)
+#define PINMUX_PB00P_PTC_DRV14                     ((PIN_PB00P_PTC_DRV14 << 16) | MUX_PB00P_PTC_DRV14)
+#define PORT_PB00P_PTC_DRV14                       (_UINT32_(1) << 0)
+
+#define PIN_PB03P_PTC_DRV15                        _UINT32_(35)
+#define MUX_PB03P_PTC_DRV15                        _UINT32_(15)
+#define PINMUX_PB03P_PTC_DRV15                     ((PIN_PB03P_PTC_DRV15 << 16) | MUX_PB03P_PTC_DRV15)
+#define PORT_PB03P_PTC_DRV15                       (_UINT32_(1) << 3)
+
+#define PIN_PB04P_PTC_DRV16                        _UINT32_(36)
+#define MUX_PB04P_PTC_DRV16                        _UINT32_(15)
+#define PINMUX_PB04P_PTC_DRV16                     ((PIN_PB04P_PTC_DRV16 << 16) | MUX_PB04P_PTC_DRV16)
+#define PORT_PB04P_PTC_DRV16                       (_UINT32_(1) << 4)
+
+#define PIN_PB05P_PTC_DRV17                        _UINT32_(37)
+#define MUX_PB05P_PTC_DRV17                        _UINT32_(15)
+#define PINMUX_PB05P_PTC_DRV17                     ((PIN_PB05P_PTC_DRV17 << 16) | MUX_PB05P_PTC_DRV17)
+#define PORT_PB05P_PTC_DRV17                       (_UINT32_(1) << 5)
+
+#define PIN_PB06P_PTC_DRV18                        _UINT32_(38)
+#define MUX_PB06P_PTC_DRV18                        _UINT32_(15)
+#define PINMUX_PB06P_PTC_DRV18                     ((PIN_PB06P_PTC_DRV18 << 16) | MUX_PB06P_PTC_DRV18)
+#define PORT_PB06P_PTC_DRV18                       (_UINT32_(1) << 6)
+
+#define PIN_PC00P_PTC_DRV19                        _UINT32_(64)
+#define MUX_PC00P_PTC_DRV19                        _UINT32_(15)
+#define PINMUX_PC00P_PTC_DRV19                     ((PIN_PC00P_PTC_DRV19 << 16) | MUX_PC00P_PTC_DRV19)
+#define PORT_PC00P_PTC_DRV19                       (_UINT32_(1) << 0)
+
+#define PIN_PC01P_PTC_DRV20                        _UINT32_(65)
+#define MUX_PC01P_PTC_DRV20                        _UINT32_(15)
+#define PINMUX_PC01P_PTC_DRV20                     ((PIN_PC01P_PTC_DRV20 << 16) | MUX_PC01P_PTC_DRV20)
+#define PORT_PC01P_PTC_DRV20                       (_UINT32_(1) << 1)
+
+#define PIN_PC02P_PTC_DRV21                        _UINT32_(66)
+#define MUX_PC02P_PTC_DRV21                        _UINT32_(15)
+#define PINMUX_PC02P_PTC_DRV21                     ((PIN_PC02P_PTC_DRV21 << 16) | MUX_PC02P_PTC_DRV21)
+#define PORT_PC02P_PTC_DRV21                       (_UINT32_(1) << 2)
+
+#define PIN_PA10P_PTC_DRV22                        _UINT32_(10)
+#define MUX_PA10P_PTC_DRV22                        _UINT32_(15)
+#define PINMUX_PA10P_PTC_DRV22                     ((PIN_PA10P_PTC_DRV22 << 16) | MUX_PA10P_PTC_DRV22)
+#define PORT_PA10P_PTC_DRV22                       (_UINT32_(1) << 10)
+
+#define PIN_PA11P_PTC_DRV23                        _UINT32_(11)
+#define MUX_PA11P_PTC_DRV23                        _UINT32_(15)
+#define PINMUX_PA11P_PTC_DRV23                     ((PIN_PA11P_PTC_DRV23 << 16) | MUX_PA11P_PTC_DRV23)
+#define PORT_PA11P_PTC_DRV23                       (_UINT32_(1) << 11)
+
+#define PIN_PA12P_PTC_DRV24                        _UINT32_(12)
+#define MUX_PA12P_PTC_DRV24                        _UINT32_(15)
+#define PINMUX_PA12P_PTC_DRV24                     ((PIN_PA12P_PTC_DRV24 << 16) | MUX_PA12P_PTC_DRV24)
+#define PORT_PA12P_PTC_DRV24                       (_UINT32_(1) << 12)
+
+#define PIN_PA13P_PTC_DRV25                        _UINT32_(13)
+#define MUX_PA13P_PTC_DRV25                        _UINT32_(15)
+#define PINMUX_PA13P_PTC_DRV25                     ((PIN_PA13P_PTC_DRV25 << 16) | MUX_PA13P_PTC_DRV25)
+#define PORT_PA13P_PTC_DRV25                       (_UINT32_(1) << 13)
+
+#define PIN_PB07P_PTC_DRV26                        _UINT32_(39)
+#define MUX_PB07P_PTC_DRV26                        _UINT32_(15)
+#define PINMUX_PB07P_PTC_DRV26                     ((PIN_PB07P_PTC_DRV26 << 16) | MUX_PB07P_PTC_DRV26)
+#define PORT_PB07P_PTC_DRV26                       (_UINT32_(1) << 7)
+
+#define PIN_PB08P_PTC_DRV27                        _UINT32_(40)
+#define MUX_PB08P_PTC_DRV27                        _UINT32_(15)
+#define PINMUX_PB08P_PTC_DRV27                     ((PIN_PB08P_PTC_DRV27 << 16) | MUX_PB08P_PTC_DRV27)
+#define PORT_PB08P_PTC_DRV27                       (_UINT32_(1) << 8)
+
+#define PIN_PB09P_PTC_DRV28                        _UINT32_(41)
+#define MUX_PB09P_PTC_DRV28                        _UINT32_(15)
+#define PINMUX_PB09P_PTC_DRV28                     ((PIN_PB09P_PTC_DRV28 << 16) | MUX_PB09P_PTC_DRV28)
+#define PORT_PB09P_PTC_DRV28                       (_UINT32_(1) << 9)
+
+#define PIN_PB10P_PTC_DRV29                        _UINT32_(42)
+#define MUX_PB10P_PTC_DRV29                        _UINT32_(15)
+#define PINMUX_PB10P_PTC_DRV29                     ((PIN_PB10P_PTC_DRV29 << 16) | MUX_PB10P_PTC_DRV29)
+#define PORT_PB10P_PTC_DRV29                       (_UINT32_(1) << 10)
+
+#define PIN_PC09P_PTC_DRV30                        _UINT32_(73)
+#define MUX_PC09P_PTC_DRV30                        _UINT32_(15)
+#define PINMUX_PC09P_PTC_DRV30                     ((PIN_PC09P_PTC_DRV30 << 16) | MUX_PC09P_PTC_DRV30)
+#define PORT_PC09P_PTC_DRV30                       (_UINT32_(1) << 9)
+
+#define PIN_PC10P_PTC_DRV31                        _UINT32_(74)
+#define MUX_PC10P_PTC_DRV31                        _UINT32_(15)
+#define PINMUX_PC10P_PTC_DRV31                     ((PIN_PC10P_PTC_DRV31 << 16) | MUX_PC10P_PTC_DRV31)
+#define PORT_PC10P_PTC_DRV31                       (_UINT32_(1) << 10)
+
+#define PIN_PA14P_PTC_DRV32                        _UINT32_(14)
+#define MUX_PA14P_PTC_DRV32                        _UINT32_(15)
+#define PINMUX_PA14P_PTC_DRV32                     ((PIN_PA14P_PTC_DRV32 << 16) | MUX_PA14P_PTC_DRV32)
+#define PORT_PA14P_PTC_DRV32                       (_UINT32_(1) << 14)
+
+#define PIN_PA15P_PTC_DRV33                        _UINT32_(15)
+#define MUX_PA15P_PTC_DRV33                        _UINT32_(15)
+#define PINMUX_PA15P_PTC_DRV33                     ((PIN_PA15P_PTC_DRV33 << 16) | MUX_PA15P_PTC_DRV33)
+#define PORT_PA15P_PTC_DRV33                       (_UINT32_(1) << 15)
+
+#define PIN_PA16P_PTC_DRV34                        _UINT32_(16)
+#define MUX_PA16P_PTC_DRV34                        _UINT32_(15)
+#define PINMUX_PA16P_PTC_DRV34                     ((PIN_PA16P_PTC_DRV34 << 16) | MUX_PA16P_PTC_DRV34)
+#define PORT_PA16P_PTC_DRV34                       (_UINT32_(1) << 16)
+
+#define PIN_PA17P_PTC_DRV35                        _UINT32_(17)
+#define MUX_PA17P_PTC_DRV35                        _UINT32_(15)
+#define PINMUX_PA17P_PTC_DRV35                     ((PIN_PA17P_PTC_DRV35 << 16) | MUX_PA17P_PTC_DRV35)
+#define PORT_PA17P_PTC_DRV35                       (_UINT32_(1) << 17)
+
+#define PIN_PC03P_PTC_ECI0                         _UINT32_(67)
+#define MUX_PC03P_PTC_ECI0                         _UINT32_(15)
+#define PINMUX_PC03P_PTC_ECI0                      ((PIN_PC03P_PTC_ECI0 << 16) | MUX_PC03P_PTC_ECI0)
+#define PORT_PC03P_PTC_ECI0                        (_UINT32_(1) << 3)
+
+#define PIN_PC04P_PTC_ECI1                         _UINT32_(68)
+#define MUX_PC04P_PTC_ECI1                         _UINT32_(15)
+#define PINMUX_PC04P_PTC_ECI1                      ((PIN_PC04P_PTC_ECI1 << 16) | MUX_PC04P_PTC_ECI1)
+#define PORT_PC04P_PTC_ECI1                        (_UINT32_(1) << 4)
+
+#define PIN_PD06P_PTC_PTCXY0                       _UINT32_(102)
+#define MUX_PD06P_PTC_PTCXY0                       _UINT32_(15)
+#define PINMUX_PD06P_PTC_PTCXY0                    ((PIN_PD06P_PTC_PTCXY0 << 16) | MUX_PD06P_PTC_PTCXY0)
+#define PORT_PD06P_PTC_PTCXY0                      (_UINT32_(1) << 6)
+
+#define PIN_PD07P_PTC_PTCXY1                       _UINT32_(103)
+#define MUX_PD07P_PTC_PTCXY1                       _UINT32_(15)
+#define PINMUX_PD07P_PTC_PTCXY1                    ((PIN_PD07P_PTC_PTCXY1 << 16) | MUX_PD07P_PTC_PTCXY1)
+#define PORT_PD07P_PTC_PTCXY1                      (_UINT32_(1) << 7)
+
+#define PIN_PD08P_PTC_PTCXY2                       _UINT32_(104)
+#define MUX_PD08P_PTC_PTCXY2                       _UINT32_(15)
+#define PINMUX_PD08P_PTC_PTCXY2                    ((PIN_PD08P_PTC_PTCXY2 << 16) | MUX_PD08P_PTC_PTCXY2)
+#define PORT_PD08P_PTC_PTCXY2                      (_UINT32_(1) << 8)
+
+#define PIN_PD09P_PTC_PTCXY3                       _UINT32_(105)
+#define MUX_PD09P_PTC_PTCXY3                       _UINT32_(15)
+#define PINMUX_PD09P_PTC_PTCXY3                    ((PIN_PD09P_PTC_PTCXY3 << 16) | MUX_PD09P_PTC_PTCXY3)
+#define PORT_PD09P_PTC_PTCXY3                      (_UINT32_(1) << 9)
+
+#define PIN_PA00P_PTC_PTCXY4                       _UINT32_(0) 
+#define MUX_PA00P_PTC_PTCXY4                       _UINT32_(15)
+#define PINMUX_PA00P_PTC_PTCXY4                    ((PIN_PA00P_PTC_PTCXY4 << 16) | MUX_PA00P_PTC_PTCXY4)
+#define PORT_PA00P_PTC_PTCXY4                      (_UINT32_(1) << 0)
+
+#define PIN_PA01P_PTC_PTCXY5                       _UINT32_(1) 
+#define MUX_PA01P_PTC_PTCXY5                       _UINT32_(15)
+#define PINMUX_PA01P_PTC_PTCXY5                    ((PIN_PA01P_PTC_PTCXY5 << 16) | MUX_PA01P_PTC_PTCXY5)
+#define PORT_PA01P_PTC_PTCXY5                      (_UINT32_(1) << 1)
+
+#define PIN_PA02P_PTC_PTCXY6                       _UINT32_(2) 
+#define MUX_PA02P_PTC_PTCXY6                       _UINT32_(15)
+#define PINMUX_PA02P_PTC_PTCXY6                    ((PIN_PA02P_PTC_PTCXY6 << 16) | MUX_PA02P_PTC_PTCXY6)
+#define PORT_PA02P_PTC_PTCXY6                      (_UINT32_(1) << 2)
+
+#define PIN_PA03P_PTC_PTCXY7                       _UINT32_(3) 
+#define MUX_PA03P_PTC_PTCXY7                       _UINT32_(15)
+#define PINMUX_PA03P_PTC_PTCXY7                    ((PIN_PA03P_PTC_PTCXY7 << 16) | MUX_PA03P_PTC_PTCXY7)
+#define PORT_PA03P_PTC_PTCXY7                      (_UINT32_(1) << 3)
+
+#define PIN_PA04P_PTC_PTCXY8                       _UINT32_(4) 
+#define MUX_PA04P_PTC_PTCXY8                       _UINT32_(15)
+#define PINMUX_PA04P_PTC_PTCXY8                    ((PIN_PA04P_PTC_PTCXY8 << 16) | MUX_PA04P_PTC_PTCXY8)
+#define PORT_PA04P_PTC_PTCXY8                      (_UINT32_(1) << 4)
+
+#define PIN_PA05P_PTC_PTCXY9                       _UINT32_(5) 
+#define MUX_PA05P_PTC_PTCXY9                       _UINT32_(15)
+#define PINMUX_PA05P_PTC_PTCXY9                    ((PIN_PA05P_PTC_PTCXY9 << 16) | MUX_PA05P_PTC_PTCXY9)
+#define PORT_PA05P_PTC_PTCXY9                      (_UINT32_(1) << 5)
+
+#define PIN_PA06P_PTC_PTCXY10                      _UINT32_(6) 
+#define MUX_PA06P_PTC_PTCXY10                      _UINT32_(15)
+#define PINMUX_PA06P_PTC_PTCXY10                   ((PIN_PA06P_PTC_PTCXY10 << 16) | MUX_PA06P_PTC_PTCXY10)
+#define PORT_PA06P_PTC_PTCXY10                     (_UINT32_(1) << 6)
+
+#define PIN_PA07P_PTC_PTCXY11                      _UINT32_(7) 
+#define MUX_PA07P_PTC_PTCXY11                      _UINT32_(15)
+#define PINMUX_PA07P_PTC_PTCXY11                   ((PIN_PA07P_PTC_PTCXY11 << 16) | MUX_PA07P_PTC_PTCXY11)
+#define PORT_PA07P_PTC_PTCXY11                     (_UINT32_(1) << 7)
+
+#define PIN_PA08P_PTC_PTCXY12                      _UINT32_(8) 
+#define MUX_PA08P_PTC_PTCXY12                      _UINT32_(15)
+#define PINMUX_PA08P_PTC_PTCXY12                   ((PIN_PA08P_PTC_PTCXY12 << 16) | MUX_PA08P_PTC_PTCXY12)
+#define PORT_PA08P_PTC_PTCXY12                     (_UINT32_(1) << 8)
+
+#define PIN_PA09P_PTC_PTCXY13                      _UINT32_(9) 
+#define MUX_PA09P_PTC_PTCXY13                      _UINT32_(15)
+#define PINMUX_PA09P_PTC_PTCXY13                   ((PIN_PA09P_PTC_PTCXY13 << 16) | MUX_PA09P_PTC_PTCXY13)
+#define PORT_PA09P_PTC_PTCXY13                     (_UINT32_(1) << 9)
+
+#define PIN_PB00P_PTC_PTCXY14                      _UINT32_(32)
+#define MUX_PB00P_PTC_PTCXY14                      _UINT32_(15)
+#define PINMUX_PB00P_PTC_PTCXY14                   ((PIN_PB00P_PTC_PTCXY14 << 16) | MUX_PB00P_PTC_PTCXY14)
+#define PORT_PB00P_PTC_PTCXY14                     (_UINT32_(1) << 0)
+
+#define PIN_PB03P_PTC_PTCXY15                      _UINT32_(35)
+#define MUX_PB03P_PTC_PTCXY15                      _UINT32_(15)
+#define PINMUX_PB03P_PTC_PTCXY15                   ((PIN_PB03P_PTC_PTCXY15 << 16) | MUX_PB03P_PTC_PTCXY15)
+#define PORT_PB03P_PTC_PTCXY15                     (_UINT32_(1) << 3)
+
+#define PIN_PB04P_PTC_PTCXY16                      _UINT32_(36)
+#define MUX_PB04P_PTC_PTCXY16                      _UINT32_(15)
+#define PINMUX_PB04P_PTC_PTCXY16                   ((PIN_PB04P_PTC_PTCXY16 << 16) | MUX_PB04P_PTC_PTCXY16)
+#define PORT_PB04P_PTC_PTCXY16                     (_UINT32_(1) << 4)
+
+#define PIN_PB05P_PTC_PTCXY17                      _UINT32_(37)
+#define MUX_PB05P_PTC_PTCXY17                      _UINT32_(15)
+#define PINMUX_PB05P_PTC_PTCXY17                   ((PIN_PB05P_PTC_PTCXY17 << 16) | MUX_PB05P_PTC_PTCXY17)
+#define PORT_PB05P_PTC_PTCXY17                     (_UINT32_(1) << 5)
+
+#define PIN_PB06P_PTC_PTCXY18                      _UINT32_(38)
+#define MUX_PB06P_PTC_PTCXY18                      _UINT32_(15)
+#define PINMUX_PB06P_PTC_PTCXY18                   ((PIN_PB06P_PTC_PTCXY18 << 16) | MUX_PB06P_PTC_PTCXY18)
+#define PORT_PB06P_PTC_PTCXY18                     (_UINT32_(1) << 6)
+
+#define PIN_PC00P_PTC_PTCXY19                      _UINT32_(64)
+#define MUX_PC00P_PTC_PTCXY19                      _UINT32_(15)
+#define PINMUX_PC00P_PTC_PTCXY19                   ((PIN_PC00P_PTC_PTCXY19 << 16) | MUX_PC00P_PTC_PTCXY19)
+#define PORT_PC00P_PTC_PTCXY19                     (_UINT32_(1) << 0)
+
+#define PIN_PC01P_PTC_PTCXY20                      _UINT32_(65)
+#define MUX_PC01P_PTC_PTCXY20                      _UINT32_(15)
+#define PINMUX_PC01P_PTC_PTCXY20                   ((PIN_PC01P_PTC_PTCXY20 << 16) | MUX_PC01P_PTC_PTCXY20)
+#define PORT_PC01P_PTC_PTCXY20                     (_UINT32_(1) << 1)
+
+#define PIN_PC02P_PTC_PTCXY21                      _UINT32_(66)
+#define MUX_PC02P_PTC_PTCXY21                      _UINT32_(15)
+#define PINMUX_PC02P_PTC_PTCXY21                   ((PIN_PC02P_PTC_PTCXY21 << 16) | MUX_PC02P_PTC_PTCXY21)
+#define PORT_PC02P_PTC_PTCXY21                     (_UINT32_(1) << 2)
+
+#define PIN_PA10P_PTC_PTCXY22                      _UINT32_(10)
+#define MUX_PA10P_PTC_PTCXY22                      _UINT32_(15)
+#define PINMUX_PA10P_PTC_PTCXY22                   ((PIN_PA10P_PTC_PTCXY22 << 16) | MUX_PA10P_PTC_PTCXY22)
+#define PORT_PA10P_PTC_PTCXY22                     (_UINT32_(1) << 10)
+
+#define PIN_PA11P_PTC_PTCXY23                      _UINT32_(11)
+#define MUX_PA11P_PTC_PTCXY23                      _UINT32_(15)
+#define PINMUX_PA11P_PTC_PTCXY23                   ((PIN_PA11P_PTC_PTCXY23 << 16) | MUX_PA11P_PTC_PTCXY23)
+#define PORT_PA11P_PTC_PTCXY23                     (_UINT32_(1) << 11)
+
+#define PIN_PA12P_PTC_PTCXY24                      _UINT32_(12)
+#define MUX_PA12P_PTC_PTCXY24                      _UINT32_(15)
+#define PINMUX_PA12P_PTC_PTCXY24                   ((PIN_PA12P_PTC_PTCXY24 << 16) | MUX_PA12P_PTC_PTCXY24)
+#define PORT_PA12P_PTC_PTCXY24                     (_UINT32_(1) << 12)
+
+#define PIN_PA13P_PTC_PTCXY25                      _UINT32_(13)
+#define MUX_PA13P_PTC_PTCXY25                      _UINT32_(15)
+#define PINMUX_PA13P_PTC_PTCXY25                   ((PIN_PA13P_PTC_PTCXY25 << 16) | MUX_PA13P_PTC_PTCXY25)
+#define PORT_PA13P_PTC_PTCXY25                     (_UINT32_(1) << 13)
+
+#define PIN_PB07P_PTC_PTCXY26                      _UINT32_(39)
+#define MUX_PB07P_PTC_PTCXY26                      _UINT32_(15)
+#define PINMUX_PB07P_PTC_PTCXY26                   ((PIN_PB07P_PTC_PTCXY26 << 16) | MUX_PB07P_PTC_PTCXY26)
+#define PORT_PB07P_PTC_PTCXY26                     (_UINT32_(1) << 7)
+
+#define PIN_PB08P_PTC_PTCXY27                      _UINT32_(40)
+#define MUX_PB08P_PTC_PTCXY27                      _UINT32_(15)
+#define PINMUX_PB08P_PTC_PTCXY27                   ((PIN_PB08P_PTC_PTCXY27 << 16) | MUX_PB08P_PTC_PTCXY27)
+#define PORT_PB08P_PTC_PTCXY27                     (_UINT32_(1) << 8)
+
+#define PIN_PB09P_PTC_PTCXY28                      _UINT32_(41)
+#define MUX_PB09P_PTC_PTCXY28                      _UINT32_(15)
+#define PINMUX_PB09P_PTC_PTCXY28                   ((PIN_PB09P_PTC_PTCXY28 << 16) | MUX_PB09P_PTC_PTCXY28)
+#define PORT_PB09P_PTC_PTCXY28                     (_UINT32_(1) << 9)
+
+#define PIN_PB10P_PTC_PTCXY29                      _UINT32_(42)
+#define MUX_PB10P_PTC_PTCXY29                      _UINT32_(15)
+#define PINMUX_PB10P_PTC_PTCXY29                   ((PIN_PB10P_PTC_PTCXY29 << 16) | MUX_PB10P_PTC_PTCXY29)
+#define PORT_PB10P_PTC_PTCXY29                     (_UINT32_(1) << 10)
+
+#define PIN_PC09P_PTC_PTCXY30                      _UINT32_(73)
+#define MUX_PC09P_PTC_PTCXY30                      _UINT32_(15)
+#define PINMUX_PC09P_PTC_PTCXY30                   ((PIN_PC09P_PTC_PTCXY30 << 16) | MUX_PC09P_PTC_PTCXY30)
+#define PORT_PC09P_PTC_PTCXY30                     (_UINT32_(1) << 9)
+
+#define PIN_PC10P_PTC_PTCXY31                      _UINT32_(74)
+#define MUX_PC10P_PTC_PTCXY31                      _UINT32_(15)
+#define PINMUX_PC10P_PTC_PTCXY31                   ((PIN_PC10P_PTC_PTCXY31 << 16) | MUX_PC10P_PTC_PTCXY31)
+#define PORT_PC10P_PTC_PTCXY31                     (_UINT32_(1) << 10)
+
+#define PIN_PA14P_PTC_PTCXY32                      _UINT32_(14)
+#define MUX_PA14P_PTC_PTCXY32                      _UINT32_(15)
+#define PINMUX_PA14P_PTC_PTCXY32                   ((PIN_PA14P_PTC_PTCXY32 << 16) | MUX_PA14P_PTC_PTCXY32)
+#define PORT_PA14P_PTC_PTCXY32                     (_UINT32_(1) << 14)
+
+#define PIN_PA15P_PTC_PTCXY33                      _UINT32_(15)
+#define MUX_PA15P_PTC_PTCXY33                      _UINT32_(15)
+#define PINMUX_PA15P_PTC_PTCXY33                   ((PIN_PA15P_PTC_PTCXY33 << 16) | MUX_PA15P_PTC_PTCXY33)
+#define PORT_PA15P_PTC_PTCXY33                     (_UINT32_(1) << 15)
+
+#define PIN_PA16P_PTC_PTCXY34                      _UINT32_(16)
+#define MUX_PA16P_PTC_PTCXY34                      _UINT32_(15)
+#define PINMUX_PA16P_PTC_PTCXY34                   ((PIN_PA16P_PTC_PTCXY34 << 16) | MUX_PA16P_PTC_PTCXY34)
+#define PORT_PA16P_PTC_PTCXY34                     (_UINT32_(1) << 16)
+
+#define PIN_PA17P_PTC_PTCXY35                      _UINT32_(17)
+#define MUX_PA17P_PTC_PTCXY35                      _UINT32_(15)
+#define PINMUX_PA17P_PTC_PTCXY35                   ((PIN_PA17P_PTC_PTCXY35 << 16) | MUX_PA17P_PTC_PTCXY35)
+#define PORT_PA17P_PTC_PTCXY35                     (_UINT32_(1) << 17)
+
+/* ================= PORT definition for SERCOM0 peripheral ================= */
+#define PIN_PB15D_SERCOM0_PAD0                     _UINT32_(47)
+#define MUX_PB15D_SERCOM0_PAD0                     _UINT32_(3) 
+#define PINMUX_PB15D_SERCOM0_PAD0                  ((PIN_PB15D_SERCOM0_PAD0 << 16) | MUX_PB15D_SERCOM0_PAD0)
+#define PORT_PB15D_SERCOM0_PAD0                    (_UINT32_(1) << 15)
+
+#define PIN_PC00D_SERCOM0_PAD0                     _UINT32_(64)
+#define MUX_PC00D_SERCOM0_PAD0                     _UINT32_(3) 
+#define PINMUX_PC00D_SERCOM0_PAD0                  ((PIN_PC00D_SERCOM0_PAD0 << 16) | MUX_PC00D_SERCOM0_PAD0)
+#define PORT_PC00D_SERCOM0_PAD0                    (_UINT32_(1) << 0)
+
+#define PIN_PB16D_SERCOM0_PAD1                     _UINT32_(48)
+#define MUX_PB16D_SERCOM0_PAD1                     _UINT32_(3) 
+#define PINMUX_PB16D_SERCOM0_PAD1                  ((PIN_PB16D_SERCOM0_PAD1 << 16) | MUX_PB16D_SERCOM0_PAD1)
+#define PORT_PB16D_SERCOM0_PAD1                    (_UINT32_(1) << 16)
+
+#define PIN_PC01D_SERCOM0_PAD1                     _UINT32_(65)
+#define MUX_PC01D_SERCOM0_PAD1                     _UINT32_(3) 
+#define PINMUX_PC01D_SERCOM0_PAD1                  ((PIN_PC01D_SERCOM0_PAD1 << 16) | MUX_PC01D_SERCOM0_PAD1)
+#define PORT_PC01D_SERCOM0_PAD1                    (_UINT32_(1) << 1)
+
+#define PIN_PB17D_SERCOM0_PAD2                     _UINT32_(49)
+#define MUX_PB17D_SERCOM0_PAD2                     _UINT32_(3) 
+#define PINMUX_PB17D_SERCOM0_PAD2                  ((PIN_PB17D_SERCOM0_PAD2 << 16) | MUX_PB17D_SERCOM0_PAD2)
+#define PORT_PB17D_SERCOM0_PAD2                    (_UINT32_(1) << 17)
+
+#define PIN_PC02D_SERCOM0_PAD2                     _UINT32_(66)
+#define MUX_PC02D_SERCOM0_PAD2                     _UINT32_(3) 
+#define PINMUX_PC02D_SERCOM0_PAD2                  ((PIN_PC02D_SERCOM0_PAD2 << 16) | MUX_PC02D_SERCOM0_PAD2)
+#define PORT_PC02D_SERCOM0_PAD2                    (_UINT32_(1) << 2)
+
+#define PIN_PC11D_SERCOM0_PAD3                     _UINT32_(75)
+#define MUX_PC11D_SERCOM0_PAD3                     _UINT32_(3) 
+#define PINMUX_PC11D_SERCOM0_PAD3                  ((PIN_PC11D_SERCOM0_PAD3 << 16) | MUX_PC11D_SERCOM0_PAD3)
+#define PORT_PC11D_SERCOM0_PAD3                    (_UINT32_(1) << 11)
+
+#define PIN_PC03D_SERCOM0_PAD3                     _UINT32_(67)
+#define MUX_PC03D_SERCOM0_PAD3                     _UINT32_(3) 
+#define PINMUX_PC03D_SERCOM0_PAD3                  ((PIN_PC03D_SERCOM0_PAD3 << 16) | MUX_PC03D_SERCOM0_PAD3)
+#define PORT_PC03D_SERCOM0_PAD3                    (_UINT32_(1) << 3)
+
+/* ================= PORT definition for SERCOM1 peripheral ================= */
+#define PIN_PC15D_SERCOM1_PAD0                     _UINT32_(79)
+#define MUX_PC15D_SERCOM1_PAD0                     _UINT32_(3) 
+#define PINMUX_PC15D_SERCOM1_PAD0                  ((PIN_PC15D_SERCOM1_PAD0 << 16) | MUX_PC15D_SERCOM1_PAD0)
+#define PORT_PC15D_SERCOM1_PAD0                    (_UINT32_(1) << 15)
+
+#define PIN_PD01D_SERCOM1_PAD0                     _UINT32_(97)
+#define MUX_PD01D_SERCOM1_PAD0                     _UINT32_(3) 
+#define PINMUX_PD01D_SERCOM1_PAD0                  ((PIN_PD01D_SERCOM1_PAD0 << 16) | MUX_PD01D_SERCOM1_PAD0)
+#define PORT_PD01D_SERCOM1_PAD0                    (_UINT32_(1) << 1)
+
+#define PIN_PC14D_SERCOM1_PAD1                     _UINT32_(78)
+#define MUX_PC14D_SERCOM1_PAD1                     _UINT32_(3) 
+#define PINMUX_PC14D_SERCOM1_PAD1                  ((PIN_PC14D_SERCOM1_PAD1 << 16) | MUX_PC14D_SERCOM1_PAD1)
+#define PORT_PC14D_SERCOM1_PAD1                    (_UINT32_(1) << 14)
+
+#define PIN_PD00D_SERCOM1_PAD1                     _UINT32_(96)
+#define MUX_PD00D_SERCOM1_PAD1                     _UINT32_(3) 
+#define PINMUX_PD00D_SERCOM1_PAD1                  ((PIN_PD00D_SERCOM1_PAD1 << 16) | MUX_PD00D_SERCOM1_PAD1)
+#define PORT_PD00D_SERCOM1_PAD1                    (_UINT32_(1) << 0)
+
+#define PIN_PC13D_SERCOM1_PAD2                     _UINT32_(77)
+#define MUX_PC13D_SERCOM1_PAD2                     _UINT32_(3) 
+#define PINMUX_PC13D_SERCOM1_PAD2                  ((PIN_PC13D_SERCOM1_PAD2 << 16) | MUX_PC13D_SERCOM1_PAD2)
+#define PORT_PC13D_SERCOM1_PAD2                    (_UINT32_(1) << 13)
+
+#define PIN_PC06D_SERCOM1_PAD2                     _UINT32_(70)
+#define MUX_PC06D_SERCOM1_PAD2                     _UINT32_(3) 
+#define PINMUX_PC06D_SERCOM1_PAD2                  ((PIN_PC06D_SERCOM1_PAD2 << 16) | MUX_PC06D_SERCOM1_PAD2)
+#define PORT_PC06D_SERCOM1_PAD2                    (_UINT32_(1) << 6)
+
+#define PIN_PD10D_SERCOM1_PAD2                     _UINT32_(106)
+#define MUX_PD10D_SERCOM1_PAD2                     _UINT32_(3) 
+#define PINMUX_PD10D_SERCOM1_PAD2                  ((PIN_PD10D_SERCOM1_PAD2 << 16) | MUX_PD10D_SERCOM1_PAD2)
+#define PORT_PD10D_SERCOM1_PAD2                    (_UINT32_(1) << 10)
+
+#define PIN_PC12D_SERCOM1_PAD3                     _UINT32_(76)
+#define MUX_PC12D_SERCOM1_PAD3                     _UINT32_(3) 
+#define PINMUX_PC12D_SERCOM1_PAD3                  ((PIN_PC12D_SERCOM1_PAD3 << 16) | MUX_PC12D_SERCOM1_PAD3)
+#define PORT_PC12D_SERCOM1_PAD3                    (_UINT32_(1) << 12)
+
+#define PIN_PC05D_SERCOM1_PAD3                     _UINT32_(69)
+#define MUX_PC05D_SERCOM1_PAD3                     _UINT32_(3) 
+#define PINMUX_PC05D_SERCOM1_PAD3                  ((PIN_PC05D_SERCOM1_PAD3 << 16) | MUX_PC05D_SERCOM1_PAD3)
+#define PORT_PC05D_SERCOM1_PAD3                    (_UINT32_(1) << 5)
+
+#define PIN_PD11D_SERCOM1_PAD3                     _UINT32_(107)
+#define MUX_PD11D_SERCOM1_PAD3                     _UINT32_(3) 
+#define PINMUX_PD11D_SERCOM1_PAD3                  ((PIN_PD11D_SERCOM1_PAD3 << 16) | MUX_PD11D_SERCOM1_PAD3)
+#define PORT_PD11D_SERCOM1_PAD3                    (_UINT32_(1) << 11)
+
+/* ================= PORT definition for SERCOM2 peripheral ================= */
+#define PIN_PC04D_SERCOM2_PAD0                     _UINT32_(68)
+#define MUX_PC04D_SERCOM2_PAD0                     _UINT32_(3) 
+#define PINMUX_PC04D_SERCOM2_PAD0                  ((PIN_PC04D_SERCOM2_PAD0 << 16) | MUX_PC04D_SERCOM2_PAD0)
+#define PORT_PC04D_SERCOM2_PAD0                    (_UINT32_(1) << 4)
+
+#define PIN_PC19D_SERCOM2_PAD0                     _UINT32_(83)
+#define MUX_PC19D_SERCOM2_PAD0                     _UINT32_(3) 
+#define PINMUX_PC19D_SERCOM2_PAD0                  ((PIN_PC19D_SERCOM2_PAD0 << 16) | MUX_PC19D_SERCOM2_PAD0)
+#define PORT_PC19D_SERCOM2_PAD0                    (_UINT32_(1) << 19)
+
+#define PIN_PC18D_SERCOM2_PAD1                     _UINT32_(82)
+#define MUX_PC18D_SERCOM2_PAD1                     _UINT32_(3) 
+#define PINMUX_PC18D_SERCOM2_PAD1                  ((PIN_PC18D_SERCOM2_PAD1 << 16) | MUX_PC18D_SERCOM2_PAD1)
+#define PORT_PC18D_SERCOM2_PAD1                    (_UINT32_(1) << 18)
+
+#define PIN_PD06D_SERCOM2_PAD1                     _UINT32_(102)
+#define MUX_PD06D_SERCOM2_PAD1                     _UINT32_(3) 
+#define PINMUX_PD06D_SERCOM2_PAD1                  ((PIN_PD06D_SERCOM2_PAD1 << 16) | MUX_PD06D_SERCOM2_PAD1)
+#define PORT_PD06D_SERCOM2_PAD1                    (_UINT32_(1) << 6)
+
+#define PIN_PC17D_SERCOM2_PAD2                     _UINT32_(81)
+#define MUX_PC17D_SERCOM2_PAD2                     _UINT32_(3) 
+#define PINMUX_PC17D_SERCOM2_PAD2                  ((PIN_PC17D_SERCOM2_PAD2 << 16) | MUX_PC17D_SERCOM2_PAD2)
+#define PORT_PC17D_SERCOM2_PAD2                    (_UINT32_(1) << 17)
+
+#define PIN_PD07D_SERCOM2_PAD2                     _UINT32_(103)
+#define MUX_PD07D_SERCOM2_PAD2                     _UINT32_(3) 
+#define PINMUX_PD07D_SERCOM2_PAD2                  ((PIN_PD07D_SERCOM2_PAD2 << 16) | MUX_PD07D_SERCOM2_PAD2)
+#define PORT_PD07D_SERCOM2_PAD2                    (_UINT32_(1) << 7)
+
+#define PIN_PC16D_SERCOM2_PAD3                     _UINT32_(80)
+#define MUX_PC16D_SERCOM2_PAD3                     _UINT32_(3) 
+#define PINMUX_PC16D_SERCOM2_PAD3                  ((PIN_PC16D_SERCOM2_PAD3 << 16) | MUX_PC16D_SERCOM2_PAD3)
+#define PORT_PC16D_SERCOM2_PAD3                    (_UINT32_(1) << 16)
+
+#define PIN_PD08D_SERCOM2_PAD3                     _UINT32_(104)
+#define MUX_PD08D_SERCOM2_PAD3                     _UINT32_(3) 
+#define PINMUX_PD08D_SERCOM2_PAD3                  ((PIN_PD08D_SERCOM2_PAD3 << 16) | MUX_PD08D_SERCOM2_PAD3)
+#define PORT_PD08D_SERCOM2_PAD3                    (_UINT32_(1) << 8)
+
+/* ================= PORT definition for SERCOM3 peripheral ================= */
+#define PIN_PD16D_SERCOM3_PAD0                     _UINT32_(112)
+#define MUX_PD16D_SERCOM3_PAD0                     _UINT32_(3) 
+#define PINMUX_PD16D_SERCOM3_PAD0                  ((PIN_PD16D_SERCOM3_PAD0 << 16) | MUX_PD16D_SERCOM3_PAD0)
+#define PORT_PD16D_SERCOM3_PAD0                    (_UINT32_(1) << 16)
+
+#define PIN_PD09D_SERCOM3_PAD0                     _UINT32_(105)
+#define MUX_PD09D_SERCOM3_PAD0                     _UINT32_(3) 
+#define PINMUX_PD09D_SERCOM3_PAD0                  ((PIN_PD09D_SERCOM3_PAD0 << 16) | MUX_PD09D_SERCOM3_PAD0)
+#define PORT_PD09D_SERCOM3_PAD0                    (_UINT32_(1) << 9)
+
+#define PIN_PA00D_SERCOM3_PAD1                     _UINT32_(0) 
+#define MUX_PA00D_SERCOM3_PAD1                     _UINT32_(3) 
+#define PINMUX_PA00D_SERCOM3_PAD1                  ((PIN_PA00D_SERCOM3_PAD1 << 16) | MUX_PA00D_SERCOM3_PAD1)
+#define PORT_PA00D_SERCOM3_PAD1                    (_UINT32_(1) << 0)
+
+#define PIN_PD15D_SERCOM3_PAD1                     _UINT32_(111)
+#define MUX_PD15D_SERCOM3_PAD1                     _UINT32_(3) 
+#define PINMUX_PD15D_SERCOM3_PAD1                  ((PIN_PD15D_SERCOM3_PAD1 << 16) | MUX_PD15D_SERCOM3_PAD1)
+#define PORT_PD15D_SERCOM3_PAD1                    (_UINT32_(1) << 15)
+
+#define PIN_PA01D_SERCOM3_PAD2                     _UINT32_(1) 
+#define MUX_PA01D_SERCOM3_PAD2                     _UINT32_(3) 
+#define PINMUX_PA01D_SERCOM3_PAD2                  ((PIN_PA01D_SERCOM3_PAD2 << 16) | MUX_PA01D_SERCOM3_PAD2)
+#define PORT_PA01D_SERCOM3_PAD2                    (_UINT32_(1) << 1)
+
+#define PIN_PD17D_SERCOM3_PAD2                     _UINT32_(113)
+#define MUX_PD17D_SERCOM3_PAD2                     _UINT32_(3) 
+#define PINMUX_PD17D_SERCOM3_PAD2                  ((PIN_PD17D_SERCOM3_PAD2 << 16) | MUX_PD17D_SERCOM3_PAD2)
+#define PORT_PD17D_SERCOM3_PAD2                    (_UINT32_(1) << 17)
+
+#define PIN_PA02D_SERCOM3_PAD3                     _UINT32_(2) 
+#define MUX_PA02D_SERCOM3_PAD3                     _UINT32_(3) 
+#define PINMUX_PA02D_SERCOM3_PAD3                  ((PIN_PA02D_SERCOM3_PAD3 << 16) | MUX_PA02D_SERCOM3_PAD3)
+#define PORT_PA02D_SERCOM3_PAD3                    (_UINT32_(1) << 2)
+
+#define PIN_PD14D_SERCOM3_PAD3                     _UINT32_(110)
+#define MUX_PD14D_SERCOM3_PAD3                     _UINT32_(3) 
+#define PINMUX_PD14D_SERCOM3_PAD3                  ((PIN_PD14D_SERCOM3_PAD3 << 16) | MUX_PD14D_SERCOM3_PAD3)
+#define PORT_PD14D_SERCOM3_PAD3                    (_UINT32_(1) << 14)
+
+/* ================= PORT definition for SERCOM4 peripheral ================= */
+#define PIN_PA03D_SERCOM4_PAD0                     _UINT32_(3) 
+#define MUX_PA03D_SERCOM4_PAD0                     _UINT32_(3) 
+#define PINMUX_PA03D_SERCOM4_PAD0                  ((PIN_PA03D_SERCOM4_PAD0 << 16) | MUX_PA03D_SERCOM4_PAD0)
+#define PORT_PA03D_SERCOM4_PAD0                    (_UINT32_(1) << 3)
+
+#define PIN_PD19D_SERCOM4_PAD0                     _UINT32_(115)
+#define MUX_PD19D_SERCOM4_PAD0                     _UINT32_(3) 
+#define PINMUX_PD19D_SERCOM4_PAD0                  ((PIN_PD19D_SERCOM4_PAD0 << 16) | MUX_PD19D_SERCOM4_PAD0)
+#define PORT_PD19D_SERCOM4_PAD0                    (_UINT32_(1) << 19)
+
+#define PIN_PA04D_SERCOM4_PAD1                     _UINT32_(4) 
+#define MUX_PA04D_SERCOM4_PAD1                     _UINT32_(3) 
+#define PINMUX_PA04D_SERCOM4_PAD1                  ((PIN_PA04D_SERCOM4_PAD1 << 16) | MUX_PA04D_SERCOM4_PAD1)
+#define PORT_PA04D_SERCOM4_PAD1                    (_UINT32_(1) << 4)
+
+#define PIN_PD20D_SERCOM4_PAD1                     _UINT32_(116)
+#define MUX_PD20D_SERCOM4_PAD1                     _UINT32_(3) 
+#define PINMUX_PD20D_SERCOM4_PAD1                  ((PIN_PD20D_SERCOM4_PAD1 << 16) | MUX_PD20D_SERCOM4_PAD1)
+#define PORT_PD20D_SERCOM4_PAD1                    (_UINT32_(1) << 20)
+
+#define PIN_PA05D_SERCOM4_PAD2                     _UINT32_(5) 
+#define MUX_PA05D_SERCOM4_PAD2                     _UINT32_(3) 
+#define PINMUX_PA05D_SERCOM4_PAD2                  ((PIN_PA05D_SERCOM4_PAD2 << 16) | MUX_PA05D_SERCOM4_PAD2)
+#define PORT_PA05D_SERCOM4_PAD2                    (_UINT32_(1) << 5)
+
+#define PIN_PD18D_SERCOM4_PAD2                     _UINT32_(114)
+#define MUX_PD18D_SERCOM4_PAD2                     _UINT32_(3) 
+#define PINMUX_PD18D_SERCOM4_PAD2                  ((PIN_PD18D_SERCOM4_PAD2 << 16) | MUX_PD18D_SERCOM4_PAD2)
+#define PORT_PD18D_SERCOM4_PAD2                    (_UINT32_(1) << 18)
+
+#define PIN_PA14D_SERCOM4_PAD3                     _UINT32_(14)
+#define MUX_PA14D_SERCOM4_PAD3                     _UINT32_(3) 
+#define PINMUX_PA14D_SERCOM4_PAD3                  ((PIN_PA14D_SERCOM4_PAD3 << 16) | MUX_PA14D_SERCOM4_PAD3)
+#define PORT_PA14D_SERCOM4_PAD3                    (_UINT32_(1) << 14)
+
+#define PIN_PA06D_SERCOM4_PAD3                     _UINT32_(6) 
+#define MUX_PA06D_SERCOM4_PAD3                     _UINT32_(3) 
+#define PINMUX_PA06D_SERCOM4_PAD3                  ((PIN_PA06D_SERCOM4_PAD3 << 16) | MUX_PA06D_SERCOM4_PAD3)
+#define PORT_PA06D_SERCOM4_PAD3                    (_UINT32_(1) << 6)
+
+/* ================= PORT definition for SERCOM5 peripheral ================= */
+#define PIN_PA16D_SERCOM5_PAD0                     _UINT32_(16)
+#define MUX_PA16D_SERCOM5_PAD0                     _UINT32_(3) 
+#define PINMUX_PA16D_SERCOM5_PAD0                  ((PIN_PA16D_SERCOM5_PAD0 << 16) | MUX_PA16D_SERCOM5_PAD0)
+#define PORT_PA16D_SERCOM5_PAD0                    (_UINT32_(1) << 16)
+
+#define PIN_PB03D_SERCOM5_PAD0                     _UINT32_(35)
+#define MUX_PB03D_SERCOM5_PAD0                     _UINT32_(3) 
+#define PINMUX_PB03D_SERCOM5_PAD0                  ((PIN_PB03D_SERCOM5_PAD0 << 16) | MUX_PB03D_SERCOM5_PAD0)
+#define PORT_PB03D_SERCOM5_PAD0                    (_UINT32_(1) << 3)
+
+#define PIN_PA17D_SERCOM5_PAD1                     _UINT32_(17)
+#define MUX_PA17D_SERCOM5_PAD1                     _UINT32_(3) 
+#define PINMUX_PA17D_SERCOM5_PAD1                  ((PIN_PA17D_SERCOM5_PAD1 << 16) | MUX_PA17D_SERCOM5_PAD1)
+#define PORT_PA17D_SERCOM5_PAD1                    (_UINT32_(1) << 17)
+
+#define PIN_PB04D_SERCOM5_PAD1                     _UINT32_(36)
+#define MUX_PB04D_SERCOM5_PAD1                     _UINT32_(3) 
+#define PINMUX_PB04D_SERCOM5_PAD1                  ((PIN_PB04D_SERCOM5_PAD1 << 16) | MUX_PB04D_SERCOM5_PAD1)
+#define PORT_PB04D_SERCOM5_PAD1                    (_UINT32_(1) << 4)
+
+#define PIN_PA18D_SERCOM5_PAD2                     _UINT32_(18)
+#define MUX_PA18D_SERCOM5_PAD2                     _UINT32_(3) 
+#define PINMUX_PA18D_SERCOM5_PAD2                  ((PIN_PA18D_SERCOM5_PAD2 << 16) | MUX_PA18D_SERCOM5_PAD2)
+#define PORT_PA18D_SERCOM5_PAD2                    (_UINT32_(1) << 18)
+
+#define PIN_PB05D_SERCOM5_PAD2                     _UINT32_(37)
+#define MUX_PB05D_SERCOM5_PAD2                     _UINT32_(3) 
+#define PINMUX_PB05D_SERCOM5_PAD2                  ((PIN_PB05D_SERCOM5_PAD2 << 16) | MUX_PB05D_SERCOM5_PAD2)
+#define PORT_PB05D_SERCOM5_PAD2                    (_UINT32_(1) << 5)
+
+#define PIN_PA15D_SERCOM5_PAD3                     _UINT32_(15)
+#define MUX_PA15D_SERCOM5_PAD3                     _UINT32_(3) 
+#define PINMUX_PA15D_SERCOM5_PAD3                  ((PIN_PA15D_SERCOM5_PAD3 << 16) | MUX_PA15D_SERCOM5_PAD3)
+#define PORT_PA15D_SERCOM5_PAD3                    (_UINT32_(1) << 15)
+
+#define PIN_PB06D_SERCOM5_PAD3                     _UINT32_(38)
+#define MUX_PB06D_SERCOM5_PAD3                     _UINT32_(3) 
+#define PINMUX_PB06D_SERCOM5_PAD3                  ((PIN_PB06D_SERCOM5_PAD3 << 16) | MUX_PB06D_SERCOM5_PAD3)
+#define PORT_PB06D_SERCOM5_PAD3                    (_UINT32_(1) << 6)
+
+/* ================== PORT definition for TCC0 peripheral =================== */
+#define PIN_PA19F_TCC0_WO0                         _UINT32_(19)
+#define MUX_PA19F_TCC0_WO0                         _UINT32_(5) 
+#define PINMUX_PA19F_TCC0_WO0                      ((PIN_PA19F_TCC0_WO0 << 16) | MUX_PA19F_TCC0_WO0)
+#define PORT_PA19F_TCC0_WO0                        (_UINT32_(1) << 19)
+
+#define PIN_PB11F_TCC0_WO0                         _UINT32_(43)
+#define MUX_PB11F_TCC0_WO0                         _UINT32_(5) 
+#define PINMUX_PB11F_TCC0_WO0                      ((PIN_PB11F_TCC0_WO0 << 16) | MUX_PB11F_TCC0_WO0)
+#define PORT_PB11F_TCC0_WO0                        (_UINT32_(1) << 11)
+
+#define PIN_PC00F_TCC0_WO0                         _UINT32_(64)
+#define MUX_PC00F_TCC0_WO0                         _UINT32_(5) 
+#define PINMUX_PC00F_TCC0_WO0                      ((PIN_PC00F_TCC0_WO0 << 16) | MUX_PC00F_TCC0_WO0)
+#define PORT_PC00F_TCC0_WO0                        (_UINT32_(1) << 0)
+
+#define PIN_PA20F_TCC0_WO1                         _UINT32_(20)
+#define MUX_PA20F_TCC0_WO1                         _UINT32_(5) 
+#define PINMUX_PA20F_TCC0_WO1                      ((PIN_PA20F_TCC0_WO1 << 16) | MUX_PA20F_TCC0_WO1)
+#define PORT_PA20F_TCC0_WO1                        (_UINT32_(1) << 20)
+
+#define PIN_PB12F_TCC0_WO1                         _UINT32_(44)
+#define MUX_PB12F_TCC0_WO1                         _UINT32_(5) 
+#define PINMUX_PB12F_TCC0_WO1                      ((PIN_PB12F_TCC0_WO1 << 16) | MUX_PB12F_TCC0_WO1)
+#define PORT_PB12F_TCC0_WO1                        (_UINT32_(1) << 12)
+
+#define PIN_PC01F_TCC0_WO1                         _UINT32_(65)
+#define MUX_PC01F_TCC0_WO1                         _UINT32_(5) 
+#define PINMUX_PC01F_TCC0_WO1                      ((PIN_PC01F_TCC0_WO1 << 16) | MUX_PC01F_TCC0_WO1)
+#define PORT_PC01F_TCC0_WO1                        (_UINT32_(1) << 1)
+
+/* ================== PORT definition for TCC1 peripheral =================== */
+#define PIN_PC02F_TCC1_WO0                         _UINT32_(66)
+#define MUX_PC02F_TCC1_WO0                         _UINT32_(5) 
+#define PINMUX_PC02F_TCC1_WO0                      ((PIN_PC02F_TCC1_WO0 << 16) | MUX_PC02F_TCC1_WO0)
+#define PORT_PC02F_TCC1_WO0                        (_UINT32_(1) << 2)
+
+#define PIN_PC09F_TCC1_WO0                         _UINT32_(73)
+#define MUX_PC09F_TCC1_WO0                         _UINT32_(5) 
+#define PINMUX_PC09F_TCC1_WO0                      ((PIN_PC09F_TCC1_WO0 << 16) | MUX_PC09F_TCC1_WO0)
+#define PORT_PC09F_TCC1_WO0                        (_UINT32_(1) << 9)
+
+#define PIN_PC03F_TCC1_WO1                         _UINT32_(67)
+#define MUX_PC03F_TCC1_WO1                         _UINT32_(5) 
+#define PINMUX_PC03F_TCC1_WO1                      ((PIN_PC03F_TCC1_WO1 << 16) | MUX_PC03F_TCC1_WO1)
+#define PORT_PC03F_TCC1_WO1                        (_UINT32_(1) << 3)
+
+#define PIN_PC10F_TCC1_WO1                         _UINT32_(74)
+#define MUX_PC10F_TCC1_WO1                         _UINT32_(5) 
+#define PINMUX_PC10F_TCC1_WO1                      ((PIN_PC10F_TCC1_WO1 << 16) | MUX_PC10F_TCC1_WO1)
+#define PORT_PC10F_TCC1_WO1                        (_UINT32_(1) << 10)
+
+/* ================== PORT definition for TCC2 peripheral =================== */
+#define PIN_PB09F_TCC2_WO0                         _UINT32_(41)
+#define MUX_PB09F_TCC2_WO0                         _UINT32_(5) 
+#define PINMUX_PB09F_TCC2_WO0                      ((PIN_PB09F_TCC2_WO0 << 16) | MUX_PB09F_TCC2_WO0)
+#define PORT_PB09F_TCC2_WO0                        (_UINT32_(1) << 9)
+
+#define PIN_PC04F_TCC2_WO0                         _UINT32_(68)
+#define MUX_PC04F_TCC2_WO0                         _UINT32_(5) 
+#define PINMUX_PC04F_TCC2_WO0                      ((PIN_PC04F_TCC2_WO0 << 16) | MUX_PC04F_TCC2_WO0)
+#define PORT_PC04F_TCC2_WO0                        (_UINT32_(1) << 4)
+
+#define PIN_PB08F_TCC2_WO1                         _UINT32_(40)
+#define MUX_PB08F_TCC2_WO1                         _UINT32_(5) 
+#define PINMUX_PB08F_TCC2_WO1                      ((PIN_PB08F_TCC2_WO1 << 16) | MUX_PB08F_TCC2_WO1)
+#define PORT_PB08F_TCC2_WO1                        (_UINT32_(1) << 8)
+
+#define PIN_PC05F_TCC2_WO1                         _UINT32_(69)
+#define MUX_PC05F_TCC2_WO1                         _UINT32_(5) 
+#define PINMUX_PC05F_TCC2_WO1                      ((PIN_PC05F_TCC2_WO1 << 16) | MUX_PC05F_TCC2_WO1)
+#define PORT_PC05F_TCC2_WO1                        (_UINT32_(1) << 5)
+
+/* ================== PORT definition for TCC3 peripheral =================== */
+#define PIN_PB13F_TCC3_WO0                         _UINT32_(45)
+#define MUX_PB13F_TCC3_WO0                         _UINT32_(5) 
+#define PINMUX_PB13F_TCC3_WO0                      ((PIN_PB13F_TCC3_WO0 << 16) | MUX_PB13F_TCC3_WO0)
+#define PORT_PB13F_TCC3_WO0                        (_UINT32_(1) << 13)
+
+#define PIN_PD00F_TCC3_WO0                         _UINT32_(96)
+#define MUX_PD00F_TCC3_WO0                         _UINT32_(5) 
+#define PINMUX_PD00F_TCC3_WO0                      ((PIN_PD00F_TCC3_WO0 << 16) | MUX_PD00F_TCC3_WO0)
+#define PORT_PD00F_TCC3_WO0                        (_UINT32_(1) << 0)
+
+#define PIN_PB14F_TCC3_WO1                         _UINT32_(46)
+#define MUX_PB14F_TCC3_WO1                         _UINT32_(5) 
+#define PINMUX_PB14F_TCC3_WO1                      ((PIN_PB14F_TCC3_WO1 << 16) | MUX_PB14F_TCC3_WO1)
+#define PORT_PB14F_TCC3_WO1                        (_UINT32_(1) << 14)
+
+#define PIN_PD01F_TCC3_WO1                         _UINT32_(97)
+#define MUX_PD01F_TCC3_WO1                         _UINT32_(5) 
+#define PINMUX_PD01F_TCC3_WO1                      ((PIN_PD01F_TCC3_WO1 << 16) | MUX_PD01F_TCC3_WO1)
+#define PORT_PD01F_TCC3_WO1                        (_UINT32_(1) << 1)
+
+/* ================== PORT definition for TCC4 peripheral =================== */
+#define PIN_PA10F_TCC4_WO0                         _UINT32_(10)
+#define MUX_PA10F_TCC4_WO0                         _UINT32_(5) 
+#define PINMUX_PA10F_TCC4_WO0                      ((PIN_PA10F_TCC4_WO0 << 16) | MUX_PA10F_TCC4_WO0)
+#define PORT_PA10F_TCC4_WO0                        (_UINT32_(1) << 10)
+
+#define PIN_PD07F_TCC4_WO0                         _UINT32_(103)
+#define MUX_PD07F_TCC4_WO0                         _UINT32_(5) 
+#define PINMUX_PD07F_TCC4_WO0                      ((PIN_PD07F_TCC4_WO0 << 16) | MUX_PD07F_TCC4_WO0)
+#define PORT_PD07F_TCC4_WO0                        (_UINT32_(1) << 7)
+
+#define PIN_PA11F_TCC4_WO1                         _UINT32_(11)
+#define MUX_PA11F_TCC4_WO1                         _UINT32_(5) 
+#define PINMUX_PA11F_TCC4_WO1                      ((PIN_PA11F_TCC4_WO1 << 16) | MUX_PA11F_TCC4_WO1)
+#define PORT_PA11F_TCC4_WO1                        (_UINT32_(1) << 11)
+
+#define PIN_PD08F_TCC4_WO1                         _UINT32_(104)
+#define MUX_PD08F_TCC4_WO1                         _UINT32_(5) 
+#define PINMUX_PD08F_TCC4_WO1                      ((PIN_PD08F_TCC4_WO1 << 16) | MUX_PD08F_TCC4_WO1)
+#define PORT_PD08F_TCC4_WO1                        (_UINT32_(1) << 8)
+
+/* ================== PORT definition for TCC5 peripheral =================== */
+#define PIN_PD10F_TCC5_WO0                         _UINT32_(106)
+#define MUX_PD10F_TCC5_WO0                         _UINT32_(5) 
+#define PINMUX_PD10F_TCC5_WO0                      ((PIN_PD10F_TCC5_WO0 << 16) | MUX_PD10F_TCC5_WO0)
+#define PORT_PD10F_TCC5_WO0                        (_UINT32_(1) << 10)
+
+#define PIN_PD09F_TCC5_WO0                         _UINT32_(105)
+#define MUX_PD09F_TCC5_WO0                         _UINT32_(5) 
+#define PINMUX_PD09F_TCC5_WO0                      ((PIN_PD09F_TCC5_WO0 << 16) | MUX_PD09F_TCC5_WO0)
+#define PORT_PD09F_TCC5_WO0                        (_UINT32_(1) << 9)
+
+#define PIN_PA00F_TCC5_WO1                         _UINT32_(0) 
+#define MUX_PA00F_TCC5_WO1                         _UINT32_(5) 
+#define PINMUX_PA00F_TCC5_WO1                      ((PIN_PA00F_TCC5_WO1 << 16) | MUX_PA00F_TCC5_WO1)
+#define PORT_PA00F_TCC5_WO1                        (_UINT32_(1) << 0)
+
+#define PIN_PD11F_TCC5_WO1                         _UINT32_(107)
+#define MUX_PD11F_TCC5_WO1                         _UINT32_(5) 
+#define PINMUX_PD11F_TCC5_WO1                      ((PIN_PD11F_TCC5_WO1 << 16) | MUX_PD11F_TCC5_WO1)
+#define PORT_PD11F_TCC5_WO1                        (_UINT32_(1) << 11)
+
+/* ================== PORT definition for TCC6 peripheral =================== */
+#define PIN_PA01F_TCC6_WO0                         _UINT32_(1) 
+#define MUX_PA01F_TCC6_WO0                         _UINT32_(5) 
+#define PINMUX_PA01F_TCC6_WO0                      ((PIN_PA01F_TCC6_WO0 << 16) | MUX_PA01F_TCC6_WO0)
+#define PORT_PA01F_TCC6_WO0                        (_UINT32_(1) << 1)
+
+#define PIN_PD12F_TCC6_WO0                         _UINT32_(108)
+#define MUX_PD12F_TCC6_WO0                         _UINT32_(5) 
+#define PINMUX_PD12F_TCC6_WO0                      ((PIN_PD12F_TCC6_WO0 << 16) | MUX_PD12F_TCC6_WO0)
+#define PORT_PD12F_TCC6_WO0                        (_UINT32_(1) << 12)
+
+#define PIN_PA02F_TCC6_WO1                         _UINT32_(2) 
+#define MUX_PA02F_TCC6_WO1                         _UINT32_(5) 
+#define PINMUX_PA02F_TCC6_WO1                      ((PIN_PA02F_TCC6_WO1 << 16) | MUX_PA02F_TCC6_WO1)
+#define PORT_PA02F_TCC6_WO1                        (_UINT32_(1) << 2)
+
+#define PIN_PD13F_TCC6_WO1                         _UINT32_(109)
+#define MUX_PD13F_TCC6_WO1                         _UINT32_(5) 
+#define PINMUX_PD13F_TCC6_WO1                      ((PIN_PD13F_TCC6_WO1 << 16) | MUX_PD13F_TCC6_WO1)
+#define PORT_PD13F_TCC6_WO1                        (_UINT32_(1) << 13)
+
+/* =================== PORT definition for USB peripheral =================== */
+#define PIN_PD01H_USB_SOF                          _UINT32_(97)
+#define MUX_PD01H_USB_SOF                          _UINT32_(7) 
+#define PINMUX_PD01H_USB_SOF                       ((PIN_PD01H_USB_SOF << 16) | MUX_PD01H_USB_SOF)
+#define PORT_PD01H_USB_SOF                         (_UINT32_(1) << 1)
+
+#define PIN_PD02H_USB_USBDM                        _UINT32_(98)
+#define MUX_PD02H_USB_USBDM                        _UINT32_(7) 
+#define PINMUX_PD02H_USB_USBDM                     ((PIN_PD02H_USB_USBDM << 16) | MUX_PD02H_USB_USBDM)
+#define PORT_PD02H_USB_USBDM                       (_UINT32_(1) << 2)
+
+#define PIN_PD03H_USB_USBDP                        _UINT32_(99)
+#define MUX_PD03H_USB_USBDP                        _UINT32_(7) 
+#define PINMUX_PD03H_USB_USBDP                     ((PIN_PD03H_USB_USBDP << 16) | MUX_PD03H_USB_USBDP)
+#define PORT_PD03H_USB_USBDP                       (_UINT32_(1) << 3)
+
+
+
+#endif /* _PIC32CM5112GC00100_GPIO_H_ */
+
diff --git a/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/system_pic32cmgc00.h b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/system_pic32cmgc00.h
new file mode 100644
index 00000000..462ef7b6
--- /dev/null
+++ b/pic32c/pic32cm_gc_sg/pic32cm_gc00/include/system_pic32cmgc00.h
@@ -0,0 +1,40 @@
+/*
+ * Low-level initialization functions called upon device startup
+ *
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef _SYSTEM_PIC32CMGC00_H_INCLUDED_
+#define _SYSTEM_PIC32CMGC00_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;   /*!< System Clock Frequency (Core Clock)  */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_PIC32CMGC00_H_INCLUDED */