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MingcongBaiMingcongBai
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BACKPORT: FROMLIST: drm/xe/guc: use SZ_4K for alignment
Per the "Firmware" chapter in "drm/xe Intel GFX Driver", as well as "Volume 8: Command Stream Programming" in "Intel® Arc™ A-Series Graphics and Intel Data Center GPU Flex Series Open-Source Programmer's Reference Manual For the discrete GPUs code named "Alchemist" and "Arctic Sound-M"" and "Intel® Iris® Xe MAX Graphics Open Source Programmer's Reference Manual For the 2020 Discrete GPU formerly named "DG1"": "The RINGBUF register sets (defined in Memory Interface Registers) are used to specify the ring buffer memory areas. The ring buffer must start on a 4KB boundary and be allocated in linear memory. The length of any one ring buffer is limited to 2MB." The Graphics micro (μ) Controller (GuC) really expects command buffers aligned to 4K boundaries. Current code uses `PAGE_SIZE' as an assumed alignment reference but 4K kernel page sizes is by no means a guarantee. On 16K-paged kernels, this causes driver failures after loading the GuC firmware: [ 7.398317] xe 0000:09:00.0: [drm] Found dg2/g10 (device ID 56a1) display version 13.00 stepping C0 [ 7.410429] xe 0000:09:00.0: [drm] Using GuC firmware from i915/dg2_guc_70.bin version 70.36.0 [ 10.719989] xe 0000:09:00.0: [drm] *ERROR* GT0: load failed: status = 0x800001EC, time = 3297ms, freq = 2400MHz (req 2400MHz), done = 0 [ 10.732106] xe 0000:09:00.0: [drm] *ERROR* GT0: load failed: status: Reset = 0, BootROM = 0x76, UKernel = 0x01, MIA = 0x00, Auth = 0x02 [ 10.744214] xe 0000:09:00.0: [drm] *ERROR* CRITICAL: Xe has declared device 0000:09:00.0 as wedged. Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/xe/kernel/issues/new [ 10.828908] xe 0000:09:00.0: [drm] *ERROR* GT0: GuC mmio request 0x4100: no reply 0x4100 Correct this by revising all instances of `PAGE_SIZE' to `SZ_4K' and revise `PAGE_ALIGN()' calls to `ALIGN()' with `SZ_4K' as the second argument (overriding `PAGE_SIZE'). Cc: [email protected] Fixes: 84d15f4 ("drm/xe/guc: Add capture size check in GuC log buffer") Fixes: 9c8c7a7 ("drm/xe/guc: Prepare GuC register list and update ADS size for error capture") Fixes: dd08ebf ("drm/xe: Introduce a new DRM driver for Intel GPUs") Tested-by: Mingcong Bai <[email protected]> Tested-by: Haien Liang <[email protected]> Tested-by: Shirong Liu <[email protected]> Tested-by: Haofeng Wu <[email protected]> Link: FanFansfan@22c55ab Co-developed-by: Shang Yatsen <[email protected]> Signed-off-by: Shang Yatsen <[email protected]> Co-developed-by: Kexy Biscuit <[email protected]> Signed-off-by: Kexy Biscuit <[email protected]> Signed-off-by: Mingcong Bai <[email protected]> Reviewed-by: Matthew Brost <[email protected]> [Mingcong Bai: Resolved a minor merge conflict post-6.16 in drivers/gpu/drm/xe/xe_guc_ads.c] Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Mingcong Bai <[email protected]>
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‎drivers/gpu/drm/xe/xe_guc.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
9191

9292
static u32 guc_ctl_log_params_flags(struct xe_guc *guc)
9393
{
94-
u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT;
94+
u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> XE_PTE_SHIFT;
9595
u32 flags;
9696

9797
#if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)
@@ -144,7 +144,7 @@ static u32 guc_ctl_log_params_flags(struct xe_guc *guc)
144144

145145
static u32 guc_ctl_ads_flags(struct xe_guc *guc)
146146
{
147-
u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT;
147+
u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> XE_PTE_SHIFT;
148148
u32 flags = ads << GUC_ADS_ADDR_SHIFT;
149149

150150
return flags;

‎drivers/gpu/drm/xe/xe_guc_ads.c‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -144,17 +144,17 @@ static size_t guc_ads_regset_size(struct xe_guc_ads *ads)
144144

145145
static size_t guc_ads_golden_lrc_size(struct xe_guc_ads *ads)
146146
{
147-
return PAGE_ALIGN(ads->golden_lrc_size);
147+
return ALIGN(ads->golden_lrc_size, SZ_4K);
148148
}
149149

150150
static u32 guc_ads_waklv_size(struct xe_guc_ads *ads)
151151
{
152-
return PAGE_ALIGN(ads->ads_waklv_size);
152+
return ALIGN(ads->ads_waklv_size, SZ_4K);
153153
}
154154

155155
static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
156156
{
157-
return PAGE_ALIGN(ads->capture_size);
157+
return ALIGN(ads->capture_size, SZ_4K);
158158
}
159159

160160
static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
@@ -169,7 +169,7 @@ static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
169169

170170
static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
171171
{
172-
return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
172+
return ALIGN(ads_to_guc(ads)->fw.private_data_size, SZ_4K);
173173
}
174174

175175
static size_t guc_ads_regset_offset(struct xe_guc_ads *ads)
@@ -184,7 +184,7 @@ static size_t guc_ads_golden_lrc_offset(struct xe_guc_ads *ads)
184184
offset = guc_ads_regset_offset(ads) +
185185
guc_ads_regset_size(ads);
186186

187-
return PAGE_ALIGN(offset);
187+
return ALIGN(offset, SZ_4K);
188188
}
189189

190190
static size_t guc_ads_waklv_offset(struct xe_guc_ads *ads)
@@ -194,7 +194,7 @@ static size_t guc_ads_waklv_offset(struct xe_guc_ads *ads)
194194
offset = guc_ads_golden_lrc_offset(ads) +
195195
guc_ads_golden_lrc_size(ads);
196196

197-
return PAGE_ALIGN(offset);
197+
return ALIGN(offset, SZ_4K);
198198
}
199199

200200
static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
@@ -204,7 +204,7 @@ static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
204204
offset = guc_ads_waklv_offset(ads) +
205205
guc_ads_waklv_size(ads);
206206

207-
return PAGE_ALIGN(offset);
207+
return ALIGN(offset, SZ_4K);
208208
}
209209

210210
static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
@@ -214,7 +214,7 @@ static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
214214
offset = guc_ads_capture_offset(ads) +
215215
guc_ads_capture_size(ads);
216216

217-
return PAGE_ALIGN(offset);
217+
return ALIGN(offset, SZ_4K);
218218
}
219219

220220
static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
@@ -224,7 +224,7 @@ static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
224224
offset = guc_ads_um_queues_offset(ads) +
225225
guc_ads_um_queues_size(ads);
226226

227-
return PAGE_ALIGN(offset);
227+
return ALIGN(offset, SZ_4K);
228228
}
229229

230230
static size_t guc_ads_size(struct xe_guc_ads *ads)
@@ -277,7 +277,7 @@ static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads)
277277
continue;
278278

279279
real_size = xe_gt_lrc_size(gt, class);
280-
alloc_size = PAGE_ALIGN(real_size);
280+
alloc_size = ALIGN(real_size, SZ_4K);
281281
total_size += alloc_size;
282282
}
283283

@@ -647,12 +647,12 @@ static int guc_capture_prep_lists(struct xe_guc_ads *ads)
647647
offsetof(struct __guc_ads_blob, system_info));
648648

649649
/* first, set aside the first page for a capture_list with zero descriptors */
650-
total_size = PAGE_SIZE;
650+
total_size = SZ_4K;
651651
if (!xe_guc_capture_getnullheader(guc, &ptr, &size))
652652
xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, size);
653653

654654
null_ggtt = ads_ggtt + capture_offset;
655-
capture_offset += PAGE_SIZE;
655+
capture_offset += SZ_4K;
656656

657657
/*
658658
* Populate capture list : at this point adps is already allocated and
@@ -718,8 +718,8 @@ static int guc_capture_prep_lists(struct xe_guc_ads *ads)
718718

719719
if (ads->capture_size != PAGE_ALIGN(total_size))
720720
xe_gt_dbg(gt, "Updated ADS capture size %d (was %d)\n",
721-
PAGE_ALIGN(total_size), ads->capture_size);
722-
return PAGE_ALIGN(total_size);
721+
ALIGN(total_size, SZ_4K), ads->capture_size);
722+
return ALIGN(total_size, SZ_4K);
723723
}
724724

725725
static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,
@@ -967,7 +967,7 @@ static void guc_golden_lrc_populate(struct xe_guc_ads *ads)
967967
xe_gt_assert(gt, gt->default_lrc[class]);
968968

969969
real_size = xe_gt_lrc_size(gt, class);
970-
alloc_size = PAGE_ALIGN(real_size);
970+
alloc_size = ALIGN(real_size, SZ_4K);
971971
total_size += alloc_size;
972972

973973
xe_map_memcpy_to(xe, ads_to_map(ads), offset,

‎drivers/gpu/drm/xe/xe_guc_capture.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -591,8 +591,8 @@ guc_capture_getlistsize(struct xe_guc *guc, u32 owner, u32 type,
591591
return -ENODATA;
592592

593593
if (size)
594-
*size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) +
595-
(num_regs * sizeof(struct guc_mmio_reg)));
594+
*size = ALIGN((sizeof(struct guc_debug_capture_list)) +
595+
(num_regs * sizeof(struct guc_mmio_reg)), SZ_4K);
596596

597597
return 0;
598598
}
@@ -739,7 +739,7 @@ size_t xe_guc_capture_ads_input_worst_size(struct xe_guc *guc)
739739
* sequence, that is, during the pre-hwconfig phase before we have
740740
* the exact engine fusing info.
741741
*/
742-
total_size = PAGE_SIZE; /* Pad a page in front for empty lists */
742+
total_size = SZ_4K; /* Pad a page in front for empty lists */
743743
for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {
744744
for (j = 0; j < GUC_CAPTURE_LIST_CLASS_MAX; j++) {
745745
if (xe_guc_capture_getlistsize(guc, i,
@@ -759,7 +759,7 @@ size_t xe_guc_capture_ads_input_worst_size(struct xe_guc *guc)
759759
total_size += global_size;
760760
}
761761

762-
return PAGE_ALIGN(total_size);
762+
return ALIGN(total_size, SZ_4K);
763763
}
764764

765765
static int guc_capture_output_size_est(struct xe_guc *guc)

‎drivers/gpu/drm/xe/xe_guc_ct.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -219,7 +219,7 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
219219
struct xe_gt *gt = ct_to_gt(ct);
220220
int err;
221221

222-
xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
222+
xe_gt_assert(gt, !(guc_ct_size() % SZ_4K));
223223

224224
ct->g2h_wq = alloc_ordered_workqueue("xe-g2h-wq", WQ_MEM_RECLAIM);
225225
if (!ct->g2h_wq)

‎drivers/gpu/drm/xe/xe_guc_log.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ static size_t guc_log_size(void)
5858
* | Capture logs |
5959
* +===============================+ + CAPTURE_SIZE
6060
*/
61-
return PAGE_SIZE + CRASH_BUFFER_SIZE + DEBUG_BUFFER_SIZE +
61+
return SZ_4K + CRASH_BUFFER_SIZE + DEBUG_BUFFER_SIZE +
6262
CAPTURE_BUFFER_SIZE;
6363
}
6464

@@ -328,7 +328,7 @@ u32 xe_guc_get_log_buffer_size(struct xe_guc_log *log, enum guc_log_buffer_type
328328
u32 xe_guc_get_log_buffer_offset(struct xe_guc_log *log, enum guc_log_buffer_type type)
329329
{
330330
enum guc_log_buffer_type i;
331-
u32 offset = PAGE_SIZE;/* for the log_buffer_states */
331+
u32 offset = SZ_4K; /* for the log_buffer_states */
332332

333333
for (i = GUC_LOG_BUFFER_CRASH_DUMP; i < GUC_LOG_BUFFER_TYPE_MAX; ++i) {
334334
if (i == type)

‎drivers/gpu/drm/xe/xe_guc_pc.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1190,7 +1190,7 @@ int xe_guc_pc_start(struct xe_guc_pc *pc)
11901190
{
11911191
struct xe_device *xe = pc_to_xe(pc);
11921192
struct xe_gt *gt = pc_to_gt(pc);
1193-
u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
1193+
u32 size = ALIGN(sizeof(struct slpc_shared_data), SZ_4K);
11941194
unsigned int fw_ref;
11951195
ktime_t earlier;
11961196
int ret;
@@ -1318,7 +1318,7 @@ int xe_guc_pc_init(struct xe_guc_pc *pc)
13181318
struct xe_tile *tile = gt_to_tile(gt);
13191319
struct xe_device *xe = gt_to_xe(gt);
13201320
struct xe_bo *bo;
1321-
u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
1321+
u32 size = ALIGN(sizeof(struct slpc_shared_data), SZ_4K);
13221322
int err;
13231323

13241324
if (xe->info.skip_guc_pc)

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