Stop using device_has for non-mbed options

As asked by @0xc0170 in PR #3934, we won't be using device_has for indicating RF/Crypto features any longer. RF config options moved to the SL_RAIL lib.json, crypto config options will come with mbedTLS integration.

Author: stevew817

features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp

@@ -80,23 +80,23 @@ static const RAIL_ChannelConfigEntry_t entry[] = {
 };
 
 #if MBED_CONF_SL_RAIL_BAND == 868
-#ifndef DEVICE_RF_SUBGHZ
+#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG
 #error "Sub-Gigahertz band is not supported on this target."
 #endif
 static const RAIL_ChannelConfig_t channels = {
   (RAIL_ChannelConfigEntry_t *) &entry[0],
   1
 };
 #elif MBED_CONF_SL_RAIL_BAND == 915
-#ifndef DEVICE_RF_SUBGHZ
+#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG
 #error "Sub-Gigahertz band is not supported on this target."
 #endif
 static const RAIL_ChannelConfig_t channels = {
   (RAIL_ChannelConfigEntry_t *) &entry[1],
   1
 };
 #elif MBED_CONF_SL_RAIL_BAND == 2400
-#ifndef DEVICE_RF_2P4GHZ
+#ifndef MBED_CONF_SL_RAIL_HAS_2P4
 #error "2.4GHz band is not supported on this target."
 #endif
 static const RAIL_ChannelConfig_t channels = {
@@ -113,7 +113,7 @@ static const RAIL_IEEE802154_Config_t config = { false, false,
 
 static const RAIL_Init_t railInitParams = { 140, 38400000, RAIL_CAL_ALL_PENDING };
 
-#if defined (DEVICE_RF_2P4GHZ)
+#if defined (MBED_CONF_SL_RAIL_HAS_2P4)
     // Set up the PA for 2.4 GHz operation
 static const RADIO_PAInit_t paInit2p4 = {
         PA_SEL_2P4_HP,    /* Power Amplifier mode */
@@ -124,7 +124,7 @@ static const RADIO_PAInit_t paInit2p4 = {
     };
 #endif
 
-#if defined (DEVICE_RF_SUBGHZ)
+#if defined (MBED_CONF_SL_RAIL_HAS_SUBGIG)
     // Set up the PA for sub-GHz operation
 static const RADIO_PAInit_t paInitSubGhz = {
         PA_SEL_SUBGIG,    /* Power Amplifier mode */
@@ -175,21 +175,19 @@ static int8_t rf_device_register(void)
 #endif
 
     // Set up PTI since it makes life so much easier
-#if defined(DEVICE_SL_PTI)
+#if defined(MBED_CONF_SL_RAIL_PTI) && (MBED_CONF_SL_RAIL_PTI == 1)
     RADIO_PTIInit_t ptiInit = {
-        RADIO_PTI_MODE_UART,    
-        1600000,                
-        6,       
-        // TODO: Configure PTI pinout using config system.
-        // Not very urgent, since all boards use the same pins now.               
-        gpioPortB,              
-        12,                     
-        6,                      
-        gpioPortB,              
-        11,                     
-        6,                      
-        gpioPortB,              
-        13,                     
+        MBED_CONF_SL_RAIL_PTI_MODE,
+        MBED_CONF_SL_RAIL_PTI_BAUDRATE,
+        MBED_CONF_SL_RAIL_PTI_DOUT_LOCATION,
+        MBED_CONF_SL_RAIL_PTI_DOUT_PORT,
+        MBED_CONF_SL_RAIL_PTI_DOUT_PIN,
+        MBED_CONF_SL_RAIL_PTI_DCLK_LOCATION,
+        MBED_CONF_SL_RAIL_PTI_DCLK_PORT,
+        MBED_CONF_SL_RAIL_PTI_DCLK_PIN,
+        MBED_CONF_SL_RAIL_PTI_DFRAME_LOCATION,
+        MBED_CONF_SL_RAIL_PTI_DFRAME_PORT,
+        MBED_CONF_SL_RAIL_PTI_DFRAME_PIN
     };
 
     RADIO_PTI_Init(&ptiInit);
@@ -198,13 +196,13 @@ static int8_t rf_device_register(void)
     // Set up RAIL
     RAIL_RfInit(&railInitParams);
     RAIL_ChannelConfig(&channels);
-#if MBED_CONF_SL_RAIL_BAND == 2400
+#if (MBED_CONF_SL_RAIL_BAND == 2400)
     RAIL_RadioConfig((void*) ieee802154_config_base);
     channel = 11;
 #elif (MBED_CONF_SL_RAIL_BAND == 915)
     RAIL_RadioConfig((void*) ieee802154_config_915);
     channel = 1;
-#elif MBED_CONF_SL_RAIL_BAND == 868
+#elif (MBED_CONF_SL_RAIL_BAND == 868)
     RAIL_RadioConfig((void*) ieee802154_config_863);
     channel = 0;
 #endif

targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c

@@ -42,7 +42,7 @@ void mbed_sdk_init()
     EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT;
     EMU_DCDCInit(&dcdcInit);
 
-#if defined(DEVICE_RF_2P4GHZ) || defined(DEVICE_RF_SUBGHZ)
+#if defined(_EFR_DEVICE)
     CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_WSTK_DEFAULT;
     // Initialize the HFXO using the settings from the WSTK bspconfig.h
     // Note: This configures things like the capacitive tuning CTUNE variable

targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json

@@ -1,6 +1,35 @@
 {
     "name": "sl-rail",
     "config": {
-        "band": 2400
+        "band": {
+          "help" : "Configure this to 2400, 915 or 868 depending on which band you want to run on (and have available on the board)",
+          "value" : 2400
+        },
+        "PTI": true,
+        "has-2p4": false,
+        "has-subgig": false,
+        "pti-mode": "RADIO_PTI_MODE_UART",
+        "pti-baudrate" : 1600000,
+        "pti-dout-location": 6,
+        "pti-dout-port": "gpioPortB",
+        "pti-dout-pin": 12,
+        "pti-dclk-location": 6,
+        "pti-dclk-port": "gpioPortB",
+        "pti-dclk-pin": 11,
+        "pti-dframe-location": 6,
+        "pti-dframe-port": "gpioPortB",
+        "pti-dframe-pin": 13
+    },
+    "target_overrides": {
+        "THUNDERBOARD_SENSE": {
+            "sl-rail.has-2p4": true
+        },
+        "THUNDERBOARD_SENSE_12": {
+            "sl-rail.has-2p4": true
+        },
+        "EFR32MG1_BRD4150": {
+            "sl-rail.has-2p4": true,
+            "sl-rail.has-subgig": true
+        }
     }
 }

targets/targets.json

@@ -1920,7 +1920,7 @@
     },
     "EFM32GG990F1024": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFM32GG", "1024K"],
+        "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"],
         "core": "Cortex-M3",
         "macros": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -1973,7 +1973,7 @@
     },
     "EFM32LG990F256": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFM32LG", "256K"],
+        "extra_labels_add": ["EFM32LG", "256K", "SL_AES"],
         "core": "Cortex-M3",
         "macros": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -2026,7 +2026,7 @@
     },
     "EFM32WG990F256": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFM32WG", "256K"],
+        "extra_labels_add": ["EFM32WG", "256K", "SL_AES"],
         "core": "Cortex-M4F",
         "macros": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -2079,7 +2079,7 @@
     },
     "EFM32ZG222F32": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFM32ZG", "32K"],
+        "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"],
         "core": "Cortex-M0+",
         "default_toolchain": "uARM",
         "macros": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
@@ -2133,7 +2133,7 @@
     },
     "EFM32HG322F64": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFM32HG", "64K"],
+        "extra_labels_add": ["EFM32HG", "64K", "SL_AES"],
         "core": "Cortex-M0+",
         "default_toolchain": "uARM",
         "macros": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
@@ -2187,7 +2187,7 @@
     },
     "EFM32PG1B100F256GM32": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFM32PG", "256K"],
+        "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"],
         "core": "Cortex-M4F",
         "macros": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -2239,7 +2239,7 @@
     },
     "EFR32MG1P132F256GM48": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL"],
+        "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
         "core": "Cortex-M4F",
         "macros": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -2249,7 +2249,7 @@
     },
     "EFR32MG1P233F256GM48": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL"],
+        "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
         "core": "Cortex-M4F",
         "macros": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -2258,7 +2258,7 @@
     },
     "EFR32MG1_BRD4150": {
         "inherits": ["EFR32MG1P132F256GM48"],
-        "device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "RF_SUBGHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "forced_reset_timeout": 2,
         "config": {
             "hf_clock_src": {
@@ -2301,7 +2301,7 @@
     },
     "THUNDERBOARD_SENSE": {
         "inherits": ["EFR32MG1P233F256GM48"],
-        "device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "forced_reset_timeout": 5,
         "config": {
             "hf_clock_src": {
@@ -2338,7 +2338,7 @@
     },
     "EFM32PG12B500F1024GL125": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFM32PG12", "1024K"],
+        "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"],
         "core": "Cortex-M4F",
         "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -2347,7 +2347,7 @@
     },
     "EFM32PG12_STK3402": {
         "inherits": ["EFM32PG12B500F1024GL125"],
-        "device_has": ["AES", "SHA", "ECC", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "forced_reset_timeout": 2,
         "config": {
             "hf_clock_src": {
@@ -2389,7 +2389,7 @@
     },
 	"EFR32MG12P332F1024GL125": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL"],
+        "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"],
         "core": "Cortex-M4F",
         "macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -2398,7 +2398,7 @@
     },
 	"THUNDERBOARD_SENSE_12": {
         "inherits": ["EFR32MG12P332F1024GL125"],
-        "device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "forced_reset_timeout": 5,
         "config": {
             "hf_clock_src": {