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Chris Trowbridge
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Add QSPI and relevant test support for target EP_AGORA
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‎TESTS/mbed_hal/qspi/flash_configs/NORDIC/EP_AGORA/flash_config.h‎

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/* mbed Microcontroller Library
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* Copyright (c) 2018-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_QSPI_FLASH_CONFIG_H
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#define MBED_QSPI_FLASH_CONFIG_H
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#include "../../W25Q32JV_config.h"
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// NRF doesn't uses read/write opcodes, instead it uses commands id's.
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// Before sending it to H/W opcodes are mapped to id's in Mbed hal qspi implementation
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//
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// for more details see:
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// targets\TARGET_NORDIC\TARGET_NRF5x\TARGET_SDK_15_0\modules\nrfx\mdk\nrf52840_bitfields.h
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// targets\TARGET_NORDIC\TARGET_NRF5x\qspi_api.c
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// NRF doesn't support read 1IO (opcode 0x03)
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#undef QSPI_CMD_READ_1IO
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#define QSPI_CMD_READ_1IO QSPI_CMD_READ_1IO_FAST
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#ifdef QSPI_SECTOR_COUNT
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#undef QSPI_SECTOR_COUNT
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#define QSPI_SECTOR_COUNT 1024 // for W25Q32JV
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#endif
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#endif // MBED_QSPI_FLASH_CONFIG_H

‎TESTS/mbed_hal/qspi/flash_configs/W25Q32JV_config.h‎

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/* mbed Microcontroller Library
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* Copyright (c) 2018-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_QSPI_FLASH_W25Q32JV_H
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#define MBED_QSPI_FLASH_W25Q32JV_H
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#define QSPI_FLASH_CHIP_STRING "Winbond W25Q32JV"
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// Command for reading status register
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#define QSPI_CMD_RDSR 0x05
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// Command for reading configuration register
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#define QSPI_CMD_RDCR0 0x35
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#define QSPI_CMD_RDCR1 0x15
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// Command for writing status/configuration register
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#define QSPI_CMD_WRSR 0x01
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// Command for writing configuration register
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#define QSPI_CMD_WRCR0 0x31
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#define QSPI_CMD_WRCR1 0x11
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// Command for reading security register
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#define QSPI_CMD_RDSCUR 0x48
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// Command for setting Reset Enable
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#define QSPI_CMD_RSTEN 0x66
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// Command for setting Reset
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#define QSPI_CMD_RST 0x99
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// Command for setting write enable
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#define QSPI_CMD_WREN 0x06
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// Command for setting write disable
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#define QSPI_CMD_WRDI 0x04
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// WRSR operations max time [us] (datasheet max time + 15%)
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#define QSPI_WRSR_MAX_TIME 34500 // 30ms
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// general wait max time [us]
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#define QSPI_WAIT_MAX_TIME 100000 // 100ms
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// Commands for writing (page programming)
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#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
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// write operations max time [us] (datasheet max time + 15%)
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#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
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#define QSPI_PAGE_SIZE 256 // 256B
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#define QSPI_SECTOR_SIZE 4096 // 4kB
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#define QSPI_SECTOR_COUNT 1024
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// Commands for reading
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#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
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#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
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#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
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#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
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#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
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#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
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#define QSPI_READ_1IO_DUMMY_CYCLE 0
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#define QSPI_READ_FAST_DUMMY_CYCLE 8
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#define QSPI_READ_2IO_DUMMY_CYCLE 4
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#define QSPI_READ_1I2O_DUMMY_CYCLE 8
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#define QSPI_READ_4IO_DUMMY_CYCLE 6
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#define QSPI_READ_1I4O_DUMMY_CYCLE 8
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// Commands for erasing
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#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
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#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
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#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
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#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
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// erase operations max time [us] (datasheet max time + 15%)
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#define QSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
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#define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s
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#define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
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// max frequency for basic rw operation (for fast mode)
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#define QSPI_COMMON_MAX_FREQUENCY 32000000
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#define QSPI_STATUS_REG_SIZE 1
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#define QSPI_CONFIG_REG_0_SIZE 1
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#define QSPI_CONFIG_REG_1_SIZE 1
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#define QSPI_SECURITY_REG_SIZE 1
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#define QSPI_MAX_REG_SIZE 1
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// status register
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#define STATUS_BIT_WIP (1 << 0) // write in progress bit
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#define STATUS_BIT_WEL (1 << 1) // write enable latch
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#define STATUS_BIT_BP0 (1 << 2) // block protect 0
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#define STATUS_BIT_BP1 (1 << 3) // block protect 1
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#define STATUS_BIT_BP2 (1 << 4) // block protect 2
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#define STATUS_BIT_BP_TB (1 << 5) // block protect top/bottom
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#define STATUS_BIT_SP (1 << 6) // sector protect
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#define STATUS_BIT_SRWD (1 << 7) // status register protect
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// configuration register 0
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// bit 2 reserved
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#define CONFIG0_BIT_SRL (1 << 0) // status register lock
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#define CONFIG0_BIT_QE (1 << 1) // quad enable
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#define CONFIG0_BIT_LB1 (1 << 3) // security register lock 1
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#define CONFIG0_BIT_LB2 (1 << 4) // security register lock 2
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#define CONFIG0_BIT_LB3 (1 << 5) // security register lock 3
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#define CONFIG0_BIT_CMP (1 << 6) // complement protect
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#define CONFIG0_BIT_SUS (1 << 7) // suspend status
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// configuration register 1
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// bits 0, 1, 3, 4, 7 reserved
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#define CONFIG1_BIT_WPS (1 << 2) // write protect selection
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#define CONFIG1_BIT_DRV2 (1 << 5) // output driver strength 2
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#define CONFIG1_BIT_DRV1 (1 << 6) // output driver strength 1
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#define QUAD_ENABLE() \
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\
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uint8_t reg_data[QSPI_CONFIG_REG_0_SIZE]; \
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\
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memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
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if (read_register(QSPI_CMD_RDCR0, reg_data, \
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QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = reg_data[0] & ~(CONFIG0_BIT_QE); \
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if (write_register(QSPI_CMD_WRCR0, reg_data, \
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QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
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if (read_register(QSPI_CMD_RDCR0, reg_data, \
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QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & (CONFIG0_BIT_QE)) == 0 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#define QUAD_DISABLE() \
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\
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uint8_t reg_data[QSPI_CONFIG_REG_0_SIZE]; \
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\
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memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
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if (read_register(QSPI_CMD_RDCR0, reg_data, \
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QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = reg_data[0] | (CONFIG0_BIT_QE); \
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if (write_register(QSPI_CMD_WRCR0, reg_data, \
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QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
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memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
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if (read_register(QSPI_CMD_RDCR0, reg_data, \
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QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & CONFIG0_BIT_QE) != 1 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#endif // MBED_QSPI_FLASH_W25Q32JV_H

‎TESTS/mbed_hal/qspi/flash_configs/flash_configs.h‎

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#undef QSPI_CMD_WRITE_QPI
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#elif defined(TARGET_NRF52840)
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#if TARGET_EP_AGORA
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#include "NORDIC/EP_AGORA/flash_config.h"
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#else
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#include "NORDIC/NRF52840_DK/flash_config.h"
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#endif
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#elif defined(TARGET_EFM32GG11_STK3701)
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#include "SiliconLabs/EFM32GG11_STK3701/flash_config.h"

‎targets/targets.json‎

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"macro_name": "MODEM_ON_BOARD_UART"
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}
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},
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"components_add": ["SPIF"],
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"components_remove": ["QSPIF"],
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"macros_add": [
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"CONFIG_GPIO_AS_PINRESET"
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]

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