Merge pull request #14822 from jeromecoutant/PR_H7_M4

STM32H7: correction for FLASH API for CM4

Author: 0xc0170

targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h747xx.h

@@ -13916,9 +13916,13 @@ typedef struct
 */
 #define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U
 #define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
+#ifdef CORE_CM4
+#define FLASH_SIZE                           0x200000UL /* 2 MB */
+#else
 #define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
                                              ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
                                              (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 2 MB   */
+#endif
 #define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
 #define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
 #define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */

targets/TARGET_STM/TARGET_STM32H7/flash_api.c

@@ -148,6 +148,8 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
 #if defined(CORE_CM7)
     SCB_CleanInvalidateDCache_by_Addr((uint32_t *)StartAddress, FullSize);
     SCB_InvalidateICache();
+#else /* CORE_CM4 */
+   __HAL_ART_ENABLE();
 #endif /* CORE_CM7 */
 #else /* DUAL_CORE */
     SCB_CleanInvalidateDCache_by_Addr((uint32_t *)StartAddress, FullSize);