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Deepika
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Update linker script for using SRAM1 and SRAM2 in ARM
To have the flexibilty in application; to use any of the section (data/bss/heap) without updating linker script in every use case, following decisions are made: 1. Fixed size and small sections moved to SRAM2 (32K) Vectors Crash data Remaining section - RW / ZI 2. Large memory space should be used for variable sections RW/ZI Heap - (Minimum - 0x12000) Stack - At bottom
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4 files changed

+130
-36
lines changed

4 files changed

+130
-36
lines changed

‎TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -204,8 +204,9 @@ void test_isr_stack_in_range(void)
204204
{
205205
// MSP stack should be very near end (test using within 128 bytes)
206206
uint32_t msp = __get_MSP();
207-
bool result = inrange(msp, mbed_stack_isr_start + mbed_stack_isr_size - 128, 128);
208-
207+
printf ("mbed_stack_isr_start = 0x%x mbed_stack_isr_size = 0x%x\n", mbed_stack_isr_start, mbed_stack_isr_size);
208+
bool result = inrange(msp, mbed_stack_isr_start, mbed_stack_isr_size);
209+
printf ("msp = 0x%x = 0x%x\n", msp);
209210
TEST_ASSERT_TRUE_MESSAGE(result, "Interrupt stack in wrong location");
210211
}
211212

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_ARM_STD/stm32l443xx.sct‎

Lines changed: 59 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -29,36 +29,82 @@
2929
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3030

3131
#if !defined(MBED_APP_START)
32-
#define MBED_APP_START 0x08000000
32+
#define MBED_APP_START 0x08000000
3333
#endif
3434

35+
; 256KB FLASH (0x40000)
3536
#if !defined(MBED_APP_SIZE)
36-
#define MBED_APP_SIZE 0x40000
37+
#define MBED_APP_SIZE 0x40000
38+
#endif
39+
40+
; 48KB SRAM (0xC000) + 16KB SRAM (0x4000)
41+
#if !defined(MBED_RAM_START)
42+
#define MBED_RAM_START 0x20000000
43+
#endif
44+
45+
; RW data 48k L4-SRAM1
46+
#if !defined(MBED_RAM_SIZE)
47+
#define MBED_RAM_SIZE 0xC000
48+
#endif
49+
50+
#if !defined(MBED_RAM2_START)
51+
#define MBED_RAM2_START 0x10000000
52+
#endif
53+
54+
; RW data 16k L4-ECC-SRAM2 retained in standby
55+
#if !defined(MBED_RAM2_SIZE)
56+
#define MBED_RAM2_SIZE 0x4000
3757
#endif
3858

3959
#if !defined(MBED_BOOT_STACK_SIZE)
40-
#define MBED_BOOT_STACK_SIZE 0x400
60+
#define MBED_BOOT_STACK_SIZE 0x400
4161
#endif
4262

43-
#define Stack_Size MBED_BOOT_STACK_SIZE
63+
; Total: 99 vectors = 396 bytes (0x18C+0x4) to be reserved in RAM
64+
#if !defined(VECTOR_SIZE)
65+
#define VECTOR_SIZE 0x190
66+
#endif
4467

45-
; 256KB FLASH (0x40000) + 48KB SRAM (0xC000) + 16KB SRAM (0x4000)
46-
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
68+
; Crash report not enabled as default
69+
#if !defined(MBED_CRASH_REPORT_RAM_SIZE)
70+
#define MBED_CRASH_REPORT_RAM_SIZE 0x0
71+
#endif
4772

48-
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
73+
;Vectors + Crash report - Fixed at start of RAM2 in sequence
74+
#define MBED_IRAM2_SIZE (MBED_RAM2_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
75+
76+
#define MBED_CRASH_REPORT_RAM_START (MBED_RAM2_START + VECTOR_SIZE)
77+
#define MBED_IRAM2_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
78+
79+
; Minimum heap should be larger then smallest RAM bank (else can use
80+
; that bank for heap) and less then largest RAM bank.
81+
#define MINIMUM_HEAP 0x4000
82+
#define RAM_FIXED_SIZE 0x0
83+
84+
;Splitting the RW and ZI section in IRAM1 (MBED_RAM_SIZE-MINIMUM_HEAP = 0x8000 available)
85+
;and IRAM2 (MBED_IRAM2_SIZE = 0x3E70 available)
86+
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
87+
88+
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
4989
*.o (RESET, +First)
5090
*(InRoot$$Sections)
5191
.ANY (+RO)
5292
}
5393

54-
RW_IRAM1 0x20000000 0x0000C000-Stack_Size { ; RW data 48k L4-SRAM1
55-
.ANY (+RW +ZI)
94+
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
5695
}
5796

58-
; Total: 99 vectors = 396 bytes (0x18C+0x4) to be reserved in RAM
59-
RW_IRAM2 (0x10000000+0x190) (0x04000-0x190) { ; RW data 16k L4-ECC-SRAM2 retained in standby
60-
.ANY (+RW +ZI)
97+
RW_IRAM1 MBED_RAM_START (MBED_RAM_SIZE-MINIMUM_HEAP) { ; RW data
98+
.ANY (+RW +ZI)
6199
}
62-
ARM_LIB_STACK (0x20000000+0x0000C000) EMPTY -Stack_Size { ; stack
100+
101+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
102+
}
103+
104+
RW_IRAM2 MBED_IRAM2_START MBED_IRAM2_SIZE {
105+
.ANY (+RW +ZI)
106+
}
107+
108+
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
63109
}
64110
}

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct‎

Lines changed: 59 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -29,44 +29,82 @@
2929
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3030

3131
#if !defined(MBED_APP_START)
32-
#define MBED_APP_START 0x08000000
32+
#define MBED_APP_START 0x08000000
3333
#endif
3434

35+
; 1MB FLASH (0x100000)
3536
#if !defined(MBED_APP_SIZE)
36-
#define MBED_APP_SIZE 0x100000
37+
#define MBED_APP_SIZE 0x100000
3738
#endif
3839

39-
#define MBED_RAM_START 0x20000000
40-
#define MBED_RAM_SIZE 0x00018000
41-
#define MBED_CRASH_REPORT_RAM_START (MBED_RAM_START)
42-
#define MBED_CRASH_REPORT_RAM_SIZE 0x100
43-
#define MBED_RAM0_START (MBED_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
44-
#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
40+
; 128KB SRAM (0x20000)
41+
#if !defined(MBED_RAM_START)
42+
#define MBED_RAM_START 0x20000000
43+
#endif
44+
45+
; RW data 96k L4-SRAM1
46+
#if !defined(MBED_RAM_SIZE)
47+
#define MBED_RAM_SIZE 0x18000
48+
#endif
49+
50+
#if !defined(MBED_RAM2_START)
51+
#define MBED_RAM2_START 0x10000000
52+
#endif
53+
54+
; RW data 32k L4-ECC-SRAM2
55+
#if !defined(MBED_RAM2_SIZE)
56+
#define MBED_RAM2_SIZE 0x8000
57+
#endif
4558

4659
#if !defined(MBED_BOOT_STACK_SIZE)
47-
#define MBED_BOOT_STACK_SIZE 0x400
60+
#define MBED_BOOT_STACK_SIZE 0x400
61+
#endif
62+
63+
; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
64+
#if !defined(VECTOR_SIZE)
65+
#define VECTOR_SIZE 0x188
66+
#endif
67+
68+
; Crash report enabled as default
69+
#if !defined(MBED_CRASH_REPORT_RAM_SIZE)
70+
#define MBED_CRASH_REPORT_RAM_SIZE 0x100
4871
#endif
4972

50-
#define Stack_Size MBED_BOOT_STACK_SIZE
73+
;Vectors + Crash report - Fixed at start of RAM2 in sequence
74+
#define MBED_IRAM2_SIZE (MBED_RAM2_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
75+
76+
#define MBED_CRASH_REPORT_RAM_START (MBED_RAM2_START + VECTOR_SIZE)
77+
#define MBED_IRAM2_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
5178

52-
; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
53-
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
79+
; Minimum heap should be larger then smallest RAM bank (else can use
80+
; that bank for heap) and less then largest RAM bank.
81+
#define MINIMUM_HEAP 0x12000
82+
#define RAM_FIXED_SIZE MBED_BOOT_STACK_SIZE
5483

55-
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
84+
;Splitting the RW and ZI section in IRAM1 (MBED_RAM_SIZE-MINIMUM_HEAP = 0x6000 available)
85+
;and IRAM2 (MBED_IRAM2_SIZE = 0x7D78 available)
86+
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
87+
88+
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
5689
*.o (RESET, +First)
5790
*(InRoot$$Sections)
5891
.ANY (+RO)
5992
}
60-
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
93+
94+
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
6195
}
62-
RW_IRAM1 MBED_RAM0_START MBED_RAM0_SIZE-Stack_Size { ; RW data 96k L4-SRAM1
63-
.ANY (+RW, +Last)
96+
97+
RW_IRAM1 MBED_RAM_START (MBED_RAM_SIZE-MINIMUM_HEAP) { ; RW data
98+
.ANY (+RW +ZI)
6499
}
65-
; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
66-
RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; ZI data 32k L4-ECC-SRAM2
67-
.ANY (+ZI)
100+
101+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
68102
}
69-
ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
103+
104+
RW_IRAM2 MBED_IRAM2_START MBED_IRAM2_SIZE {
105+
.ANY (+RW +ZI)
70106
}
71-
}
72107

108+
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
109+
}
110+
}

‎targets/TARGET_STM/mbed_rtx.h‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,4 +137,13 @@
137137
#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 3072
138138
#endif
139139

140+
#if (defined(TARGET_STM32L475VG) || defined(TARGET_STM32L443RC))
141+
#if defined(__ARMCC_VERSION)
142+
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[];
143+
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[];
144+
#define HEAP_START Image$$ARM_LIB_HEAP$$ZI$$Base
145+
#define HEAP_SIZE Image$$ARM_LIB_HEAP$$ZI$$Length
146+
#endif
147+
#endif
148+
140149
#endif // MBED_MBED_RTX_H

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