From 076bbe9d5634011bf74f64445ce9770f10d8791d Mon Sep 17 00:00:00 2001 From: d-kato Date: Wed, 6 Nov 2019 13:28:04 +0900 Subject: [PATCH 1/3] Fix missing mbed_get_a9_tick_irq in non-RTOS build --- .../TARGET_GR_LYCHEE/device/os_tick_ostm.c | 17 +++++++---------- .../TARGET_RZ_A1H/device/os_tick_ostm.c | 17 +++++++---------- .../TARGET_VK_RZ_A1H/device/os_tick_ostm.c | 18 +++++++----------- 3 files changed, 21 insertions(+), 31 deletions(-) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c index 0e4023b806a..435531a3f3b 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c @@ -22,28 +22,25 @@ * limitations under the License. */ -#ifdef MBED_CONF_RTOS_PRESENT - -#include "os_tick.h" #include "irq_ctrl.h" #include "cmsis.h" #include "mbed_drv_cfg.h" +// Define OS Timer channel and interrupt number +#define OSTM (OSTM0) +#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) + +#ifdef MBED_CONF_RTOS_PRESENT +#include "os_tick.h" // Define OS TImer interrupt priority #ifndef OSTM_IRQ_PRIORITY #define OSTM_IRQ_PRIORITY 0xFFU #endif -// Define OS Timer channel and interrupt number -#define OSTM (OSTM0) -#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) - - static uint32_t OSTM_Clock; // Timer tick frequency static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag - // Setup OS Tick. int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { @@ -190,10 +187,10 @@ uint32_t OS_Tick_GetOverflow (void) { return (IRQ_GetPending(OSTM_IRQn)); } +#endif // Get Cortex-A9 OS Timer interrupt number IRQn_ID_t mbed_get_a9_tick_irqn(){ return OSTM_IRQn; } -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c index 0e4023b806a..435531a3f3b 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c @@ -22,28 +22,25 @@ * limitations under the License. */ -#ifdef MBED_CONF_RTOS_PRESENT - -#include "os_tick.h" #include "irq_ctrl.h" #include "cmsis.h" #include "mbed_drv_cfg.h" +// Define OS Timer channel and interrupt number +#define OSTM (OSTM0) +#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) + +#ifdef MBED_CONF_RTOS_PRESENT +#include "os_tick.h" // Define OS TImer interrupt priority #ifndef OSTM_IRQ_PRIORITY #define OSTM_IRQ_PRIORITY 0xFFU #endif -// Define OS Timer channel and interrupt number -#define OSTM (OSTM0) -#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) - - static uint32_t OSTM_Clock; // Timer tick frequency static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag - // Setup OS Tick. int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { @@ -190,10 +187,10 @@ uint32_t OS_Tick_GetOverflow (void) { return (IRQ_GetPending(OSTM_IRQn)); } +#endif // Get Cortex-A9 OS Timer interrupt number IRQn_ID_t mbed_get_a9_tick_irqn(){ return OSTM_IRQn; } -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c index e974310cead..435531a3f3b 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c @@ -22,28 +22,25 @@ * limitations under the License. */ -#ifdef MBED_CONF_RTOS_PRESENT - -#include "os_tick.h" #include "irq_ctrl.h" #include "cmsis.h" #include "mbed_drv_cfg.h" +// Define OS Timer channel and interrupt number +#define OSTM (OSTM0) +#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) + +#ifdef MBED_CONF_RTOS_PRESENT +#include "os_tick.h" // Define OS TImer interrupt priority #ifndef OSTM_IRQ_PRIORITY #define OSTM_IRQ_PRIORITY 0xFFU #endif -// Define OS Timer channel and interrupt number -#define OSTM (OSTM0) -#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) - - static uint32_t OSTM_Clock; // Timer tick frequency static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag - // Setup OS Tick. int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { @@ -190,11 +187,10 @@ uint32_t OS_Tick_GetOverflow (void) { return (IRQ_GetPending(OSTM_IRQn)); } +#endif // Get Cortex-A9 OS Timer interrupt number IRQn_ID_t mbed_get_a9_tick_irqn(){ return OSTM_IRQn; } -#endif - From 86f648d0b7e0f8c69fbd2596d97a480c95ef2e28 Mon Sep 17 00:00:00 2001 From: d-kato Date: Wed, 6 Nov 2019 20:48:30 +0900 Subject: [PATCH 2/3] serial_putc waits for the transmission to complete --- targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c index 7bbac37a0ab..58f2ae925dd 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c @@ -592,6 +592,7 @@ void serial_putc(serial_t *obj, int c) { while (!serial_writable(obj)); obj->serial.uart->SCFTDR = c; serial_put_done(obj); + while ((obj->serial.uart->SCFSR & 0x40) == 0); // Wait TEND = 1 } static void serial_put_done(serial_t *obj) From 4fbb87d2bbb7812a187be74f288d57178138de25 Mon Sep 17 00:00:00 2001 From: d-kato Date: Thu, 7 Nov 2019 12:19:10 +0900 Subject: [PATCH 3/3] Moved transmission completion wait to hal_deepsleep --- targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c | 1 - targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c | 11 +++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c index 58f2ae925dd..7bbac37a0ab 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c @@ -592,7 +592,6 @@ void serial_putc(serial_t *obj, int c) { while (!serial_writable(obj)); obj->serial.uart->SCFTDR = c; serial_put_done(obj); - while ((obj->serial.uart->SCFSR & 0x40) == 0); // Wait TEND = 1 } static void serial_put_done(serial_t *obj) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c index 025231f2bb4..3dc76da7b67 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c @@ -128,6 +128,17 @@ void hal_deepsleep(void) { wk_CPGSTBCR13 = CPGSTBCR13; #endif + /* Waits for the serial transmission to complete */ + const struct st_scif *SCIF[SCIF_COUNT] = SCIF_ADDRESS_LIST; + + for (int uart = 0; uart < SCIF_COUNT; uart++) { + if ((wk_CPGSTBCR4 & (1 << (7 - uart))) == 0) { // Is the power turned on? + if ((SCIF[uart]->SCSCR & 0x00A0) == 0x00A0) { // Is transmission enabled? (TE = 1, TIE = 1) + while ((SCIF[uart]->SCFSR & 0x0040) == 0); // Waits for the transmission to complete (TEND = 1) + } + } + } + /* MTU2 (for low power ticker) */ CPGSTBCR3 |= ~(CPG_STBCR3_BIT_MSTP33); dummy_8 = CPGSTBCR3;