diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_HRM1017/PinNames.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_HRM1017/PinNames.h deleted file mode 100644 index 031b2ad26aa..00000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_HRM1017/PinNames.h +++ /dev/null @@ -1,153 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, -// p31=31, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - - LED1 = p18, - LED2 = p19, - LED3 = p18, - LED4 = p19, - - BUTTON1 = p16, - BUTTON2 = p17, - - RX_PIN_NUMBER = p11, - TX_PIN_NUMBER = p9, - CTS_PIN_NUMBER = p10, - RTS_PIN_NUMBER = p8, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPI_PSELMOSI0 = p20, - SPI_PSELMISO0 = p22, - SPI_PSELSS0 = p24, - SPI_PSELSCK0 = p25, - - SPI_PSELMOSI1 = p12, - SPI_PSELMISO1 = p13, - SPI_PSELSS1 = p14, - SPI_PSELSCK1 = p15, - - SPIS_PSELMOSI = p12, - SPIS_PSELMISO = p13, - SPIS_PSELSS = p14, - SPIS_PSELSCK = p15, - - I2C_SDA0 = p22, - I2C_SCL0 = p20, - - I2C_SDA1 = p13, - I2C_SCL1 = p15, - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_HRM1017/device.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_HRM1017/device.h deleted file mode 100644 index 2427e752ea9..00000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_HRM1017/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_TY51822R3/PinNames.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_TY51822R3/PinNames.h deleted file mode 100644 index 76e1958aeeb..00000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_TY51822R3/PinNames.h +++ /dev/null @@ -1,178 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - - LED1 = p21, - LED2 = p22, - LED3 = p23, - LED4 = p24, - - BUTTON1 = p17, - BUTTON2 = p18, - BUTTON3 = p19, - BUTTON4 = p20, - - RX_PIN_NUMBER = p11, - TX_PIN_NUMBER = p9, - CTS_PIN_NUMBER = p10, - RTS_PIN_NUMBER = p8, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPI_PSELMOSI0 = p25, - SPI_PSELMISO0 = p28, - SPI_PSELSS0 = p24, - SPI_PSELSCK0 = p29, - - SPI_PSELMOSI1 = p13, - SPI_PSELMISO1 = p14, - SPI_PSELSS1 = p12, - SPI_PSELSCK1 = p15, - - SPIS_PSELMOSI = p13, - SPIS_PSELMISO = p14, - SPIS_PSELSS = p12, - SPIS_PSELSCK = p15, - - I2C_SDA0 = p30, - I2C_SCL0 = p7, - - D0 = p12, - D1 = p13, - D2 = p14, - D3 = p15, - D4 = p16, - D5 = p17, - D6 = p18, - D7 = p19, - - D8 = p20, - D9 = p23, - D10 = p24, - D11 = p25, - D12 = p28, - D13 = p29, - - D14 = p30, - D15 = p7, - - A0 = p1, - A1 = p2, - A2 = p3, - A3 = p4, - A4 = p5, - A5 = p6, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_TY51822R3/device.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_TY51822R3/device.h deleted file mode 100644 index 3b470c68647..00000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_TY51822R3/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h deleted file mode 100644 index 9cef1835a0c..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h +++ /dev/null @@ -1,55 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Default peripherals - -// SPI: MOSI, MISO, CLK, SEL -#define MBED_SPI0 P0_26, P0_25, P0_24, P0_15 - -#define MBED_UART0 P0_7, P0_18 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 P0_11, P0_10 - -typedef enum { - ADC_0 = 0, - ADC_1, - ADC_2, - ADC_3, - ADC_4, - ADC_5, - ADC_6, - ADC_7, - ADC_8, - ADC_9, - ADC_10, - ADC_11, -} ADCName; - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h deleted file mode 100644 index e2fb12338d7..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h +++ /dev/null @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PIN_SHIFT 8 - -typedef enum { -// LPC824 Pin Names (PIN[11:8] + IOCON offset[7:0]) - - P0_0 = ( 0 << PIN_SHIFT) | 0x44, - P0_1 = ( 1 << PIN_SHIFT) | 0x2C, - P0_2 = ( 2 << PIN_SHIFT) | 0x18, - P0_3 = ( 3 << PIN_SHIFT) | 0x14, - P0_4 = ( 4 << PIN_SHIFT) | 0x10, - P0_5 = ( 5 << PIN_SHIFT) | 0x0C, - P0_6 = ( 6 << PIN_SHIFT) | 0x40, - P0_7 = ( 7 << PIN_SHIFT) | 0x3C, - P0_8 = ( 8 << PIN_SHIFT) | 0x38, - P0_9 = ( 9 << PIN_SHIFT) | 0x34, - P0_10 = (10 << PIN_SHIFT) | 0x20, - P0_11 = (11 << PIN_SHIFT) | 0x1C, - P0_12 = (12 << PIN_SHIFT) | 0x08, - P0_13 = (13 << PIN_SHIFT) | 0x04, - P0_14 = (14 << PIN_SHIFT) | 0x48, - P0_15 = (15 << PIN_SHIFT) | 0x28, - P0_16 = (16 << PIN_SHIFT) | 0x24, - P0_17 = (17 << PIN_SHIFT) | 0x00, - P0_18 = (18 << PIN_SHIFT) | 0x78, - P0_19 = (19 << PIN_SHIFT) | 0x74, - P0_20 = (20 << PIN_SHIFT) | 0x70, - P0_21 = (21 << PIN_SHIFT) | 0x6C, - P0_22 = (22 << PIN_SHIFT) | 0x68, - P0_23 = (23 << PIN_SHIFT) | 0x64, - P0_24 = (24 << PIN_SHIFT) | 0x60, - P0_25 = (25 << PIN_SHIFT) | 0x5C, - P0_26 = (26 << PIN_SHIFT) | 0x58, - P0_27 = (27 << PIN_SHIFT) | 0x54, - P0_28 = (28 << PIN_SHIFT) | 0x50, - - dp2 = P0_4, - dp3 = P0_28, - dp4 = P0_11, - dp5 = P0_10, - dp6 = P0_16, - dp7 = P0_27, - dp8 = P0_26, - dp9 = P0_25, - dp10 = P0_24, - dp11 = P0_15, - dp12 = P0_1, - - dp15 = P0_6, - dp16 = P0_0, - dp17 = P0_14, - dp18 = P0_23, - dp19 = P0_22, - dp20 = P0_21, - dp21 = P0_20, - dp22 = P0_19, - dp23 = P0_17, - dp24 = P0_13, - dp25 = P0_12, - dp26 = P0_5, - - LED_RED = P0_20, - LED_GREEN = P0_21, - LED_BLUE = P0_22, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = LED_BLUE, - - // Serial to USB pins - USBTX = P0_7, - USBRX = P0_18, - - // I2C pins - SCL = P0_10, - SDA = P0_11, - I2C_SCL = P0_10, - I2C_SDA = P0_11, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - -typedef struct { - unsigned char n; - unsigned char offset; -} SWM_Map; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h deleted file mode 100644 index 2427e752ea9..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct deleted file mode 100644 index 8738dd70430..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct +++ /dev/null @@ -1,48 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 32K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x8000 -#endif - -; 4KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x2000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S deleted file mode 100644 index 744eda77ad9..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S +++ /dev/null @@ -1,195 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC8xx.s -; * @purpose: CMSIS Cortex-M0+ Core Device Startup File -; * for the NXP LPC8xx Device Series -; * @version: V1.0 -; * @date: 16. Aug. 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD 0 ; Reserved - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD 0 ; Reserved - DCD I2C1_IRQHandler ; I2C1 controller - DCD I2C0_IRQHandler ; I2C0 controller - DCD SCT_IRQHandler ; Smart Counter Timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CMP_IRQHandler ; Comparator - DCD WDT_IRQHandler ; PIO1 (0:11) - DCD BOD_IRQHandler ; Brown Out Detect - DCD Flash_IRQHandler ; Flash interrupt - DCD WKT_IRQHandler ; Wakeup timer - DCD ADC_SEQA_IRQHandler ; ADC sequence A completion - DCD ADC_SEQB_IRQHandler ; ADC sequence B completion - DCD ADC_THCMP_IRQHandler ; ADC threshold compare - DCD ADC_OVR_IRQHandler ; ADC overrun - DCD DMA__RQHandler ; DMA interrupt - DCD I2C2_IRQHandler ; I2C2 controller - DCD I2C3_IRQHandler ; I2C3 controller - DCD 0 ; Reserved - DCD PININT0_IRQHandler ; PIO INT0 - DCD PININT1_IRQHandler ; PIO INT1 - DCD PININT2_IRQHandler ; PIO INT2 - DCD PININT3_IRQHandler ; PIO INT3 - DCD PININT4_IRQHandler ; PIO INT4 - DCD PININT5_IRQHandler ; PIO INT5 - DCD PININT6_IRQHandler ; PIO INT6 - DCD PININT7_IRQHandler ; PIO INT7 - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT NMI_Handler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT MRT_IRQHandler [WEAK] - EXPORT CMP_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT Flash_IRQHandler [WEAK] - EXPORT WKT_IRQHandler [WEAK] - EXPORT ADC_SEQA_IRQHandler [WEAK] - EXPORT ADC_SEQB_IRQHandler [WEAK] - EXPORT ADC_THCMP_IRQHandler [WEAK] - EXPORT ADC_OVR_IRQHandler [WEAK] - EXPORT DMA__RQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT I2C3_IRQHandler [WEAK] - EXPORT PININT0_IRQHandler [WEAK] - EXPORT PININT1_IRQHandler [WEAK] - EXPORT PININT2_IRQHandler [WEAK] - EXPORT PININT3_IRQHandler [WEAK] - EXPORT PININT4_IRQHandler [WEAK] - EXPORT PININT5_IRQHandler [WEAK] - EXPORT PININT6_IRQHandler [WEAK] - EXPORT PININT7_IRQHandler [WEAK] - -NMI_Handler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -I2C1_IRQHandler -I2C0_IRQHandler -SCT_IRQHandler -MRT_IRQHandler -CMP_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -Flash_IRQHandler -WKT_IRQHandler -ADC_SEQA_IRQHandler -ADC_SEQB_IRQHandler -ADC_THCMP_IRQHandler -ADC_OVR_IRQHandler -DMA__RQHandler -I2C2_IRQHandler -I2C3_IRQHandler -PININT0_IRQHandler -PININT1_IRQHandler -PININT2_IRQHandler -PININT3_IRQHandler -PININT4_IRQHandler -PININT5_IRQHandler -PININT6_IRQHandler -PININT7_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/LPC824.ld b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/LPC824.ld deleted file mode 100644 index 4817d52b1bc..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/LPC824.ld +++ /dev/null @@ -1,157 +0,0 @@ -/* Linker script for mbed LPC824-GCC-ARM based on LPC1114-GCC-ARM-LPC1114.ld */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - /* Define each memory region */ - FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */ - RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - *(.text.SystemInit) - . = 0x200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S deleted file mode 100644 index c4273d680b7..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S +++ /dev/null @@ -1,228 +0,0 @@ -/* File: startup_ARMCM0.S - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.2 - * Date: 15 Nov 2011 - * - * Copyright (c) 2011, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv6-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x80 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x80 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - -/* LPC824 interrupts */ - .long SPI0_IRQHandler // SPI0 controller - .long SPI1_IRQHandler // SPI1 controller - .long 0 // Reserved - .long UART0_IRQHandler // UART0 - .long UART1_IRQHandler // UART1 - .long UART2_IRQHandler // UART2 - .long 0 // Reserved - .long I2C1_IRQHandler // I2C ch1 controller - .long I2C0_IRQHandler // I2C ch0 controller - .long SCT_IRQHandler // Smart Counter Timer - .long MRT_IRQHandler // Multi-Rate Timer - .long CMP_IRQHandler // Comparator - .long WDT_IRQHandler // PIO1 (0:11) - .long BOD_IRQHandler // Brown Out Detect - .long Flash_IRQHandler // Flash interrupt - .long WKT_IRQHandler // Wakeup timer - .long ADC_SEQA_IRQHandler // ADC sequence A completion - .long ADC_SEQB_IRQHandler // ADC sequence B completion - .long ADC_THCMP_IRQHandler // ADC threshold compare - .long ADC_OVR_IRQHandler // ADC overrun - .long DMA_IRQHandler // DMA interrupt - .long I2C2_IRQHandler // I2C2 controller - .long I2C3_IRQHandler // I2C3 controller - .long 0 // Reserved - .long PININT0_IRQHandler // PIO INT0 - .long PININT1_IRQHandler // PIO INT1 - .long PININT2_IRQHandler // PIO INT2 - .long PININT3_IRQHandler // PIO INT3 - .long PININT4_IRQHandler // PIO INT4 - .long PININT5_IRQHandler // PIO INT5 - .long PININT6_IRQHandler // PIO INT6 - .long PININT7_IRQHandler // PIO INT7 - - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler SVC_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler SPI0_IRQHandler - def_irq_default_handler SPI1_IRQHandler - def_irq_default_handler UART0_IRQHandler - def_irq_default_handler UART1_IRQHandler - def_irq_default_handler UART2_IRQHandler - def_irq_default_handler I2C0_IRQHandler - def_irq_default_handler I2C1_IRQHandler - def_irq_default_handler I2C2_IRQHandler - def_irq_default_handler I2C3_IRQHandler - def_irq_default_handler SCT_IRQHandler - def_irq_default_handler MRT_IRQHandler - def_irq_default_handler CMP_IRQHandler - def_irq_default_handler WDT_IRQHandler - def_irq_default_handler BOD_IRQHandler - def_irq_default_handler Flash_IRQHandler - def_irq_default_handler WKT_IRQHandler - def_irq_default_handler ADC_SEQA_IRQHandler - def_irq_default_handler ADC_SEQB_IRQHandler - def_irq_default_handler ADC_THCMP_IRQHandler - def_irq_default_handler ADC_OVR_IRQHandler - def_irq_default_handler DMA_IRQHandler - def_irq_default_handler PININT0_IRQHandler - def_irq_default_handler PININT1_IRQHandler - def_irq_default_handler PININT2_IRQHandler - def_irq_default_handler PININT3_IRQHandler - def_irq_default_handler PININT4_IRQHandler - def_irq_default_handler PININT5_IRQHandler - def_irq_default_handler PININT6_IRQHandler - def_irq_default_handler PININT7_IRQHandler - - .end - diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/system_LPC8xx.c b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/system_LPC8xx.c deleted file mode 100644 index e2b41234992..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/system_LPC8xx.c +++ /dev/null @@ -1,389 +0,0 @@ -/****************************************************************************** - * @file: system_LPC8xx.c - * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File - * for the NXP LPC8xx Device Series - * @version: V1.0 - * @date: 16. Aug. 2012 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#include -#include "LPC82x.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ----------------------------------*/ -// -// Clock Configuration -#define CLOCK_SETUP 1 -// System Oscillator Control Register (SYSOSCCTRL) -// BYPASS: System Oscillator Bypass Enable -// If enabled then PLL input (sys_osc_clk) is fed -// directly from XTALIN and XTALOUT pins. -// FREQRANGE: System Oscillator Frequency Range -// Determines frequency range for Low-power oscillator. -// <0=> 1 - 20 MHz -// <1=> 15 - 25 MHz -// -#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 -// -// Watchdog Oscillator Control Register (WDTOSCCTRL) -// DIVSEL: Select Divider for Fclkana -// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) -// <0-31> -// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) -// <0=> Undefined -// <1=> 0.6 MHz -// <2=> 1.05 MHz -// <3=> 1.4 MHz -// <4=> 1.75 MHz -// <5=> 2.1 MHz -// <6=> 2.4 MHz -// <7=> 2.7 MHz -// <8=> 3.0 MHz -// <9=> 3.25 MHz -// <10=> 3.5 MHz -// <11=> 3.75 MHz -// <12=> 4.0 MHz -// <13=> 4.2 MHz -// <14=> 4.4 MHz -// <15=> 4.6 MHz -#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 -// -// System PLL Control Register (SYSPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// -#define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000 -// -// System PLL Clock Source Select Register (SYSPLLCLKSEL) -// SEL: System PLL Clock Source -// <0=> IRC -// <1=> Crystal Oscillator -// <2=> Reserved -// <3=> CLKIN. External clock input. -// -#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 -// -// Main Clock Source Select Register (MAINCLKSEL) -// SEL: Clock Source for Main Clock -// <0=> IRC Oscillator -// <1=> PLL input -// <2=> Watchdog Oscillator -// <3=> PLL output -// -#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 -// System AHB Clock Divider Register (SYSAHBCLKDIV) -// DIV: System AHB Clock Divider -// Divides main clock to provide system clock to core, memories, and peripherals. -// 0 = is disabled -// <0-255> -// -#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 -// - -//#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal: - -/* -#if (CLOCK_SETUP == 0) - #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 - #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000 - #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000 - #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 -#elif (CLOCK_SETUP == 2) -// #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000 - #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 - #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 - #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 -#endif -*/ - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) - #error "SYSOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) - #error "WDTOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) - #error "SYSPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) - #error "SYSPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) - #error "MAINCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) - #error "SYSAHBCLKDIV: Value out of range!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __XTAL (12000000UL) /* Oscillator frequency */ -#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ -#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ -#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */ - - -#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) -#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) - -#if (CLOCK_SETUP) /* Clock Setup */ - #if (__FREQSEL == 0) - #define __WDT_OSC_CLK ( 0) /* undefined */ - #elif (__FREQSEL == 1) - #define __WDT_OSC_CLK ( 500000 / __DIVSEL) - #elif (__FREQSEL == 2) - #define __WDT_OSC_CLK ( 800000 / __DIVSEL) - #elif (__FREQSEL == 3) - #define __WDT_OSC_CLK (1100000 / __DIVSEL) - #elif (__FREQSEL == 4) - #define __WDT_OSC_CLK (1400000 / __DIVSEL) - #elif (__FREQSEL == 5) - #define __WDT_OSC_CLK (1600000 / __DIVSEL) - #elif (__FREQSEL == 6) - #define __WDT_OSC_CLK (1800000 / __DIVSEL) - #elif (__FREQSEL == 7) - #define __WDT_OSC_CLK (2000000 / __DIVSEL) - #elif (__FREQSEL == 8) - #define __WDT_OSC_CLK (2200000 / __DIVSEL) - #elif (__FREQSEL == 9) - #define __WDT_OSC_CLK (2400000 / __DIVSEL) - #elif (__FREQSEL == 10) - #define __WDT_OSC_CLK (2600000 / __DIVSEL) - #elif (__FREQSEL == 11) - #define __WDT_OSC_CLK (2700000 / __DIVSEL) - #elif (__FREQSEL == 12) - #define __WDT_OSC_CLK (2900000 / __DIVSEL) - #elif (__FREQSEL == 13) - #define __WDT_OSC_CLK (3100000 / __DIVSEL) - #elif (__FREQSEL == 14) - #define __WDT_OSC_CLK (3200000 / __DIVSEL) - #else - #define __WDT_OSC_CLK (3400000 / __DIVSEL) - #endif - - /* sys_pllclkin calculation */ - #if ((SYSPLLCLKSEL_Val & 0x03) == 0) - #define __SYS_PLLCLKIN (__IRC_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) - #define __SYS_PLLCLKIN (__SYS_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 3) - #define __SYS_PLLCLKIN (__CLKIN_CLK) - #else - #define __SYS_PLLCLKIN (0) - #endif - - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) - - /* main clock calculation */ - #if ((MAINCLKSEL_Val & 0x03) == 0) - #define __MAIN_CLOCK (__IRC_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 1) - #define __MAIN_CLOCK (__SYS_PLLCLKIN) - #elif ((MAINCLKSEL_Val & 0x03) == 2) - #if (__FREQSEL == 0) - #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" - #else - #define __MAIN_CLOCK (__WDT_OSC_CLK) - #endif - #elif ((MAINCLKSEL_Val & 0x03) == 3) - #define __MAIN_CLOCK (__SYS_PLLCLKOUT) - #else - #define __MAIN_CLOCK (0) - #endif - - #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) - -#else - #define __SYSTEM_CLOCK (__IRC_OSC_CLK) -#endif // CLOCK_SETUP - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ -uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - uint32_t wdt_osc = 0; - - /* Determine clock frequency according to clock register values */ - switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { - case 0: wdt_osc = 0; break; - case 1: wdt_osc = 500000; break; - case 2: wdt_osc = 800000; break; - case 3: wdt_osc = 1100000; break; - case 4: wdt_osc = 1400000; break; - case 5: wdt_osc = 1600000; break; - case 6: wdt_osc = 1800000; break; - case 7: wdt_osc = 2000000; break; - case 8: wdt_osc = 2200000; break; - case 9: wdt_osc = 2400000; break; - case 10: wdt_osc = 2600000; break; - case 11: wdt_osc = 2700000; break; - case 12: wdt_osc = 2900000; break; - case 13: wdt_osc = 3100000; break; - case 14: wdt_osc = 3200000; break; - case 15: wdt_osc = 3400000; break; - } - wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; - - switch (LPC_SYSCON->MAINCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* Input Clock to System PLL */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK; - break; - case 2: /* Reserved */ - SystemCoreClock = 0; - break; - case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK; - break; - } - break; - case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; - break; - case 3: /* System PLL Clock Out */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - case 2: /* Reserved */ - SystemCoreClock = 0; - break; - case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - } - break; - } - - SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; - -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) { - volatile uint32_t i; - - /* System clock to the IOCON & the SWM need to be enabled or - most of the I/O related peripherals won't work. */ - LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) ); - -#if (CLOCK_SETUP) /* Clock Setup */ - -#if ((SYSPLLCLKSEL_Val & 0x03) == 1) - LPC_IOCON->PIO0_8 &= ~(0x3 << 3); - LPC_IOCON->PIO0_9 &= ~(0x3 << 3); - LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */ - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */ - for (i = 0; i < 200; i++) __NOP(); - LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; -#endif - -#if ((SYSPLLCLKSEL_Val & 0x03) == 3) - LPC_IOCON->PIO0_1 &= ~(0x3 << 3); - LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */ - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */ - LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->SYSPLLCLKUEN = 0; - LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */ - while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ - -#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ - LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */ - while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ -#endif - -#if (((MAINCLKSEL_Val & 0x03) == 2) ) - LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */ - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ - LPC_SYSCON->MAINCLKUEN = 0; - LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */ - while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ - - LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; -#endif -} diff --git a/targets/TARGET_NXP/mbed_rtx.h b/targets/TARGET_NXP/mbed_rtx.h index 58267509584..f8a404e348e 100644 --- a/targets/TARGET_NXP/mbed_rtx.h +++ b/targets/TARGET_NXP/mbed_rtx.h @@ -77,7 +77,7 @@ #define INITIAL_SP (0x10001000UL) #endif -#elif defined(TARGET_LPC824) || defined(TARGET_SSCI824) +#elif defined(TARGET_LPC824) #ifndef INITIAL_SP #define INITIAL_SP (0x10002000UL) diff --git a/targets/targets.json b/targets/targets.json index 0d8e2dd31a0..30b4997d1c2 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1217,40 +1217,6 @@ "0824" ] }, - "SSCI824": { - "inherits": [ - "LPCTarget" - ], - "core": "Cortex-M0+", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC82X" - ], - "is_disk_virtual": true, - "supported_toolchains": [ - "uARM", - "GCC_ARM" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE" - ], - "default_lib": "small", - "release_versions": [ - "2" - ], - "detect_code": [ - "1018" - ] - }, "MCU_LPC4088": { "inherits": [ "LPCTarget" @@ -7816,45 +7782,6 @@ "TARGET_SEEED_TINY_BLE" ] }, - "HRM1017": { - "inherits": [ - "MCU_NRF51_16K" - ], - "macros_add": [ - "TARGET_NRF_LFCLK_RC" - ], - "release_versions": [ - "2" - ], - "device_name": "nRF51822_xxAA", - "detect_code": [ - "1017" - ] - }, - "HRM1017_BOOT": { - "inherits": [ - "MCU_NRF51_16K_BOOT" - ], - "extra_labels_add": [ - "HRM1017" - ], - "macros_add": [ - "TARGET_HRM1017", - "TARGET_NRF_LFCLK_RC" - ] - }, - "HRM1017_OTA": { - "inherits": [ - "MCU_NRF51_16K_OTA" - ], - "extra_labels_add": [ - "HRM1017" - ], - "macros_add": [ - "TARGET_HRM1017", - "TARGET_NRF_LFCLK_RC" - ] - }, "RBLAB_NRF51822": { "supported_form_factors": [ "ARDUINO" @@ -8360,67 +8287,6 @@ "0452" ] }, - "TY51822R3": { - "inherits": [ - "MCU_NRF51_32K_UNIFIED" - ], - "macros_add": [ - "TARGET_NRF_32MHZ_XTAL" - ], - "device_has": [ - "USTICKER", - "LPTICKER", - "ANALOGIN", - "I2C", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_ASYNCH", - "SLEEP", - "SPI", - "SPI_ASYNCH", - "SPISLAVE" - ], - "detect_code": [ - "1019" - ], - "release_versions": [ - "2", - "5" - ], - "overrides": { - "uart_hwfc": 0 - }, - "device_name": "nRF51822_xxAC" - }, - "TY51822R3_BOOT": { - "inherits": [ - "MCU_NRF51_32K_BOOT" - ], - "extra_labels_add": [ - "TY51822R3" - ], - "macros_add": [ - "TARGET_TY51822R3", - "TARGET_NRF_32MHZ_XTAL" - ] - }, - "TY51822R3_OTA": { - "inherits": [ - "MCU_NRF51_32K_OTA" - ], - "extra_labels_add": [ - "NRF51_DK" - ], - "macros_add": [ - "TARGET_TY51822R3", - "TARGET_NRF_32MHZ_XTAL" - ] - }, "ARM_MPS2_Target": { "inherits": [ "Target"