From 8145b69959cac929b2c5eeb2a1a0583e7f9250c6 Mon Sep 17 00:00:00 2001 From: JojoS62 Date: Wed, 21 Oct 2020 18:54:47 +0200 Subject: [PATCH 1/7] add setting for LSE drive load level --- targets/TARGET_STM/mbed_overrides.c | 67 +++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index f8c19b69916..4b8fa087472 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -27,10 +27,69 @@ */ #include "cmsis.h" #include "objects.h" +#include "platform/mbed_error.h" int mbed_sdk_inited = 0; extern void SetSysClock(void); +#if MBED_CONF_TARGET_LSE_AVAILABLE + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +# if MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL +# define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL +# else +# define LSE_DRIVE_LOAD_LEVEL RCC_LSE_HIGHDRIVE_MODE +# endif +#else // defined(STM32F4xx) +# if MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL +# define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL +# else +# define LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_MEDIUMHIGH +# endif +#endif + +/** + * @brief configure the LSE crystal driver load + * This settings ist target hardware dependend and + * depends on the crystal that is used for LSE clock. + * For low power requirements, crystals with low load capacitors can be used and + * driver setting is RCC_LSEDRIVE_LOW. + * For higher stablity, crystals with higher load capacitys can be used and + * driver setting is RCC_LSEDRIVE_HIGH. + * + * A detailed description about this setting can be found here: + * https://www.st.com/resource/en/application_note/cd00221665-oscillator-design-guide-for-stm8afals-stm32-mcus-and-mpus-stmicroelectronics.pdf + * + * LSE maybe used later, but crystal load drive setting is necessary before + * enabling LSE. + * + * @param None + * @retval None + */ + +static void LSEDriveConfig(void) { + // this config can be changed only when LSE is stopped + // LSE could be enabled before a reset and will remain running, disable first + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + error("LSEDriveConfig : failed to disable LSE\n"); + } + + // set LSE drive level. Exception only for F4_g2 series +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL); +#else + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL); +#endif +} +#endif // MBED_CONF_TARGET_LSE_AVAILABLE + /** * @brief Setup the target board-specific configuration * of the microcontroller @@ -120,6 +179,11 @@ void mbed_sdk_init() /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings */ +#if MBED_CONF_TARGET_LSE_AVAILABLE + // LSE maybe used later, but crystal load drive setting is necessary before + // enabling LSE + LSEDriveConfig(); +#endif SetSysClock(); SystemCoreClockUpdate(); @@ -142,6 +206,9 @@ void mbed_sdk_init() /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings */ +#if MBED_CONF_TARGET_LSE_AVAILABLE + LSEDriveConfig(); +#endif SetSysClock(); SystemCoreClockUpdate(); #endif /* DUAL_CORE */ From a209d44a076277593c8b29004079725f765b00d9 Mon Sep 17 00:00:00 2001 From: JojoS62 Date: Thu, 22 Oct 2020 11:20:51 +0200 Subject: [PATCH 2/7] simplify checking for F4_g2 exception --- targets/TARGET_STM/mbed_overrides.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index 4b8fa087472..688f34ebe84 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -34,14 +34,14 @@ extern void SetSysClock(void); #if MBED_CONF_TARGET_LSE_AVAILABLE -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +// set defaults for LSE drive load level, with exception for F4_g2 MCU +#ifdef RCC_LSE_HIGHDRIVE_MODE # if MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL # define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL # else # define LSE_DRIVE_LOAD_LEVEL RCC_LSE_HIGHDRIVE_MODE # endif -#else // defined(STM32F4xx) +#else # if MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL # define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL # else @@ -80,13 +80,12 @@ static void LSEDriveConfig(void) { } // set LSE drive level. Exception only for F4_g2 series -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) - HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL); -#else HAL_PWR_EnableBkUpAccess(); - __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL); -#endif + #ifdef __HAL_RCC_LSEDRIVE_CONFIG + __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL); + #else + HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL); + #endif } #endif // MBED_CONF_TARGET_LSE_AVAILABLE From e7f1430d37032fa93c76628096d3d55a6dc55c37 Mon Sep 17 00:00:00 2001 From: JojoS62 Date: Thu, 22 Oct 2020 11:24:51 +0200 Subject: [PATCH 3/7] remove duplicate LSEDRIVE_CONFIG --- targets/TARGET_STM/TARGET_STM32L5/system_clock.c | 1 - .../TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c | 1 - 2 files changed, 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L5/system_clock.c b/targets/TARGET_STM/TARGET_STM32L5/system_clock.c index 0f44cf70aad..d6b788761d3 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L5/system_clock.c @@ -134,7 +134,6 @@ uint8_t SetSysClock_PLL_MSI(void) __HAL_RCC_RTCAPB_CLK_ENABLE(); #if MBED_CONF_TARGET_LSE_AVAILABLE - __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c index 801b1400d23..f9169760b0e 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c @@ -72,7 +72,6 @@ void SetSysClock(void) Config_HSE(); - __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */ From 80847e958d2423ea677b1c89e34245765a23e6a0 Mon Sep 17 00:00:00 2001 From: JojoS62 Date: Thu, 22 Oct 2020 11:27:42 +0200 Subject: [PATCH 4/7] simplify default setting --- targets/TARGET_STM/mbed_overrides.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index 688f34ebe84..ff1bb1b8c65 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -35,15 +35,11 @@ extern void SetSysClock(void); #if MBED_CONF_TARGET_LSE_AVAILABLE // set defaults for LSE drive load level, with exception for F4_g2 MCU -#ifdef RCC_LSE_HIGHDRIVE_MODE -# if MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL -# define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL -# else -# define LSE_DRIVE_LOAD_LEVEL RCC_LSE_HIGHDRIVE_MODE -# endif +#if MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL +# define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL #else -# if MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL -# define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL +# ifdef RCC_LSE_HIGHDRIVE_MODE +# define LSE_DRIVE_LOAD_LEVEL RCC_LSE_HIGHDRIVE_MODE # else # define LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_MEDIUMHIGH # endif From 64072a925e84162c1379aeceb0c5b0397af8ac02 Mon Sep 17 00:00:00 2001 From: JojoS62 Date: Thu, 22 Oct 2020 20:11:15 +0200 Subject: [PATCH 5/7] fix for targets with non-modifiable transconductance --- targets/TARGET_STM/mbed_overrides.c | 31 +++++++++++++++++------------ 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index ff1bb1b8c65..4461d9ffa4e 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -32,18 +32,23 @@ int mbed_sdk_inited = 0; extern void SetSysClock(void); -#if MBED_CONF_TARGET_LSE_AVAILABLE +#if defined(RCC_LSE_HIGHDRIVE_MODE) || defined(RCC_LSEDRIVE_HIGH) +# define LSE_CONFIG_AVAILABLE +#endif -// set defaults for LSE drive load level, with exception for F4_g2 MCU -#if MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL -# define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL -#else -# ifdef RCC_LSE_HIGHDRIVE_MODE -# define LSE_DRIVE_LOAD_LEVEL RCC_LSE_HIGHDRIVE_MODE +// set defaults for LSE drive load level +#if defined(LSE_CONFIG_AVAILABLE) + +# ifdef MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL +# define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL # else -# define LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_MEDIUMHIGH +# ifdef RCC_LSE_HIGHDRIVE_MODE +# define LSE_DRIVE_LOAD_LEVEL RCC_LSE_HIGHDRIVE_MODE +# else +# define LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_MEDIUMHIGH +# endif # endif -#endif + /** * @brief configure the LSE crystal driver load @@ -77,13 +82,13 @@ static void LSEDriveConfig(void) { // set LSE drive level. Exception only for F4_g2 series HAL_PWR_EnableBkUpAccess(); - #ifdef __HAL_RCC_LSEDRIVE_CONFIG + #if defined(LSE_CONFIG_AVAILABLE) __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL); #else HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL); #endif } -#endif // MBED_CONF_TARGET_LSE_AVAILABLE +#endif // LSE_CONFIG_AVAILABLE /** * @brief Setup the target board-specific configuration @@ -174,7 +179,7 @@ void mbed_sdk_init() /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings */ -#if MBED_CONF_TARGET_LSE_AVAILABLE +#if defined(LSE_CONFIG_AVAILABLE) // LSE maybe used later, but crystal load drive setting is necessary before // enabling LSE LSEDriveConfig(); @@ -201,7 +206,7 @@ void mbed_sdk_init() /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings */ -#if MBED_CONF_TARGET_LSE_AVAILABLE +#if defined(LSE_CONFIG_AVAILABLE) LSEDriveConfig(); #endif SetSysClock(); From 622a452661d8a33a66e8543fa473e0c39f7eca12 Mon Sep 17 00:00:00 2001 From: JojoS62 Date: Fri, 23 Oct 2020 17:00:28 +0200 Subject: [PATCH 6/7] fix macro usage error use unique #if defined() --- targets/TARGET_STM/mbed_overrides.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index 4461d9ffa4e..3f511874482 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -39,10 +39,10 @@ extern void SetSysClock(void); // set defaults for LSE drive load level #if defined(LSE_CONFIG_AVAILABLE) -# ifdef MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL +# if defined(MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL) # define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL # else -# ifdef RCC_LSE_HIGHDRIVE_MODE +# if defined(RCC_LSE_HIGHDRIVE_MODE) # define LSE_DRIVE_LOAD_LEVEL RCC_LSE_HIGHDRIVE_MODE # else # define LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_MEDIUMHIGH @@ -82,7 +82,7 @@ static void LSEDriveConfig(void) { // set LSE drive level. Exception only for F4_g2 series HAL_PWR_EnableBkUpAccess(); - #if defined(LSE_CONFIG_AVAILABLE) + #if defined(__HAL_RCC_LSEDRIVE_CONFIG) __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL); #else HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL); From 6264e0abc4cb3ee2cc4e9a21cd4e8076c60882f8 Mon Sep 17 00:00:00 2001 From: JojoS62 Date: Fri, 23 Oct 2020 19:38:55 +0200 Subject: [PATCH 7/7] add defaults values set all defaults to initial low as after a reset most STM32 eval boards use low power crystals and work with this setting --- targets/TARGET_STM/mbed_overrides.c | 4 +-- targets/targets.json | 50 +++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index 3f511874482..fd5f1287de8 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -43,9 +43,9 @@ extern void SetSysClock(void); # define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL # else # if defined(RCC_LSE_HIGHDRIVE_MODE) -# define LSE_DRIVE_LOAD_LEVEL RCC_LSE_HIGHDRIVE_MODE +# define LSE_DRIVE_LOAD_LEVEL RCC_LSE_LOWPOWER_MODE # else -# define LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_MEDIUMHIGH +# define LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_LOW # endif # endif diff --git a/targets/targets.json b/targets/targets.json index 2bb0dee4d79..d02488a6dbb 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1198,6 +1198,11 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lse_drive_load_level": { + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", + "value": "RCC_LSEDRIVE_LOW", + "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" } }, "macros_add": [ @@ -1407,6 +1412,11 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lse_drive_load_level": { + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", + "value": "RCC_LSEDRIVE_LOW", + "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" } }, "device_has_add": [ @@ -2116,6 +2126,11 @@ "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", "value": 1 + }, + "lse_drive_load_level": { + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", + "value": "RCC_LSEDRIVE_LOW", + "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" } }, "overrides": { @@ -2359,6 +2374,11 @@ "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", "value": 1 + }, + "lse_drive_load_level": { + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", + "value": "RCC_LSEDRIVE_LOW", + "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" } }, "extra_labels_add": [ @@ -2462,6 +2482,11 @@ "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", "value": 1 + }, + "lse_drive_load_level": { + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", + "value": "RCC_LSEDRIVE_LOW", + "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" } }, "extra_labels_add": [ @@ -2625,6 +2650,11 @@ "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", "value": 1 + }, + "lse_drive_load_level": { + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", + "value": "RCC_LSEDRIVE_LOW", + "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" } }, "components_add": [ @@ -2888,6 +2918,11 @@ "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", "value": 1 + }, + "lse_drive_load_level": { + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", + "value": "RCC_LSEDRIVE_LOW", + "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" } }, "macros_add": [ @@ -3121,6 +3156,11 @@ "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", "value": 1 + }, + "lse_drive_load_level": { + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", + "value": "RCC_LSEDRIVE_LOW", + "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" } }, "macros_add": [ @@ -3641,6 +3681,11 @@ "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", "value": 1 + }, + "lse_drive_load_level": { + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", + "value": "RCC_LSEDRIVE_LOW", + "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" } }, "overrides": { @@ -3740,6 +3785,11 @@ "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", "value": 1 + }, + "lse_drive_load_level": { + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", + "value": "RCC_LSEDRIVE_LOW", + "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" } }, "macros_add": [