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STM32: add setting for LSE drive load level #13797

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Merged
merged 7 commits into from
Nov 18, 2020
Merged

STM32: add setting for LSE drive load level #13797

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8145b69
add setting for LSE drive load level
JojoS62 Oct 21, 2020
a209d44
simplify checking for F4_g2 exception
JojoS62 Oct 22, 2020
e7f1430
remove duplicate LSEDRIVE_CONFIG
JojoS62 Oct 22, 2020
80847e9
simplify default setting
JojoS62 Oct 22, 2020
64072a9
fix for targets with non-modifiable
JojoS62 Oct 22, 2020
622a452
fix macro usage error
JojoS62 Oct 23, 2020
6264e0a
add defaults values
JojoS62 Oct 23, 2020
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1 change: 0 additions & 1 deletion targets/TARGET_STM/TARGET_STM32L5/system_clock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,6 @@ uint8_t SetSysClock_PLL_MSI(void)
__HAL_RCC_RTCAPB_CLK_ENABLE();

#if MBED_CONF_TARGET_LSE_AVAILABLE
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
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1 change: 0 additions & 1 deletion targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c
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Expand Up @@ -72,7 +72,6 @@ void SetSysClock(void)

Config_HSE();

__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

/* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
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67 changes: 67 additions & 0 deletions targets/TARGET_STM/mbed_overrides.c
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Expand Up @@ -27,10 +27,69 @@
*/
#include "cmsis.h"
#include "objects.h"
#include "platform/mbed_error.h"

int mbed_sdk_inited = 0;
extern void SetSysClock(void);

#if defined(RCC_LSE_HIGHDRIVE_MODE) || defined(RCC_LSEDRIVE_HIGH)
# define LSE_CONFIG_AVAILABLE
#endif

// set defaults for LSE drive load level
#if defined(LSE_CONFIG_AVAILABLE)

# if defined(MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL)
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@zimjjan zimjjan Jun 21, 2021 •
edited
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I'm not entirely sure if something changed since [1] was documented, but I think the build system will interpret the "macro_name" from target.json without adding the "MBED_CONF_" prefix, which will lead to the setting never being applied. I noticed this while I was backporting this to mbedos 5 so I might be wrong.

[1] https://os.mbed.com/docs/mbed-os/v6.11/program-setup/advanced-configuration.html

Edited: added the comment here, as adding it to all the target.json lines would have been a pain.

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Hi
I am sorry, I didn't understand well the question.
I don't think there is something different between mbedos 5 and 6 about json configuration.
And no need to add this line for each target as it can be defined at the family level.

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Sorry, I didn't made my point in an understandable way:
The implementation requires MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL to be defined to set LSEDRV from the config. However, in target.json the actual parameter is set to "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL" which will result in the target not being generated as MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL, but without the prefix MBED_CONF_. (See [1] above comment)

This results in the value from target.json (or anywhere else, where the setting is overridden from) never being used in the first place, as far as I understand.

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I'm sorry, was resolved here #13939
Never mind. My fault.

# define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL
# else
# if defined(RCC_LSE_HIGHDRIVE_MODE)
# define LSE_DRIVE_LOAD_LEVEL RCC_LSE_LOWPOWER_MODE
# else
# define LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_LOW
# endif
# endif


/**
* @brief configure the LSE crystal driver load
* This settings ist target hardware dependend and
* depends on the crystal that is used for LSE clock.
* For low power requirements, crystals with low load capacitors can be used and
* driver setting is RCC_LSEDRIVE_LOW.
* For higher stablity, crystals with higher load capacitys can be used and
* driver setting is RCC_LSEDRIVE_HIGH.
*
* A detailed description about this setting can be found here:
* https://www.st.com/resource/en/application_note/cd00221665-oscillator-design-guide-for-stm8afals-stm32-mcus-and-mpus-stmicroelectronics.pdf
*
* LSE maybe used later, but crystal load drive setting is necessary before
* enabling LSE.
*
* @param None
* @retval None
*/

static void LSEDriveConfig(void) {
// this config can be changed only when LSE is stopped
// LSE could be enabled before a reset and will remain running, disable first
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
error("LSEDriveConfig : failed to disable LSE\n");
}

// set LSE drive level. Exception only for F4_g2 series
HAL_PWR_EnableBkUpAccess();
#if defined(__HAL_RCC_LSEDRIVE_CONFIG)
__HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL);
#else
HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL);
#endif
}
#endif // LSE_CONFIG_AVAILABLE

/**
* @brief Setup the target board-specific configuration
* of the microcontroller
Expand Down Expand Up @@ -120,6 +179,11 @@ void mbed_sdk_init()

/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
#if defined(LSE_CONFIG_AVAILABLE)
// LSE maybe used later, but crystal load drive setting is necessary before
// enabling LSE
LSEDriveConfig();
#endif
SetSysClock();
SystemCoreClockUpdate();

Expand All @@ -142,6 +206,9 @@ void mbed_sdk_init()

/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
#if defined(LSE_CONFIG_AVAILABLE)
LSEDriveConfig();
#endif
SetSysClock();
SystemCoreClockUpdate();
#endif /* DUAL_CORE */
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50 changes: 50 additions & 0 deletions targets/targets.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1198,6 +1198,11 @@
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
"macro_name": "CLOCK_SOURCE"
},
"lse_drive_load_level": {
"help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
"value": "RCC_LSEDRIVE_LOW",
"macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
}
},
"macros_add": [
Expand Down Expand Up @@ -1407,6 +1412,11 @@
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
"macro_name": "CLOCK_SOURCE"
},
"lse_drive_load_level": {
"help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
"value": "RCC_LSEDRIVE_LOW",
"macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
}
},
"device_has_add": [
Expand Down Expand Up @@ -2116,6 +2126,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
},
"lse_drive_load_level": {
"help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
"value": "RCC_LSEDRIVE_LOW",
"macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
}
},
"overrides": {
Expand Down Expand Up @@ -2359,6 +2374,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
},
"lse_drive_load_level": {
"help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
"value": "RCC_LSEDRIVE_LOW",
"macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
}
},
"extra_labels_add": [
Expand Down Expand Up @@ -2462,6 +2482,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
},
"lse_drive_load_level": {
"help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
"value": "RCC_LSEDRIVE_LOW",
"macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
}
},
"extra_labels_add": [
Expand Down Expand Up @@ -2625,6 +2650,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
},
"lse_drive_load_level": {
"help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
"value": "RCC_LSEDRIVE_LOW",
"macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
}
},
"components_add": [
Expand Down Expand Up @@ -2888,6 +2918,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
},
"lse_drive_load_level": {
"help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
"value": "RCC_LSEDRIVE_LOW",
"macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
}
},
"macros_add": [
Expand Down Expand Up @@ -3121,6 +3156,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
},
"lse_drive_load_level": {
"help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
"value": "RCC_LSEDRIVE_LOW",
"macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
}
},
"macros_add": [
Expand Down Expand Up @@ -3641,6 +3681,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
},
"lse_drive_load_level": {
"help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
"value": "RCC_LSEDRIVE_LOW",
"macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
}
},
"overrides": {
Expand Down Expand Up @@ -3740,6 +3785,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
},
"lse_drive_load_level": {
"help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
"value": "RCC_LSEDRIVE_LOW",
"macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
}
},
"macros_add": [
Expand Down