diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/flash.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/flash.h new file mode 100644 index 00000000000..57a1f648321 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/flash.h @@ -0,0 +1,47 @@ +/** + ******************************************************************************* + * @file flash.h + * @brief This file provides flash definition.\n + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2020 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FLASH_H +#define __FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "rda_flash512ud32_b.h" +#include "txzp_driver_def.h" + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __FLASH_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/rda_flash512ud32_b.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/rda_flash512ud32_b.h new file mode 100644 index 00000000000..a2bc3bcd545 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/rda_flash512ud32_b.h @@ -0,0 +1,502 @@ +/** + ******************************************************************************* + * @file rda_flash512ud32_b.h + * @brief This file provides rda_flash512ud32 definition.\n + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RDA_FLASH512UD32_B_H +#define __RDA_FLASH512UD32_B_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "flash.h" +//#include "driver_com.h" +#include "TMPM4KNA.h" + + +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup RDA_FLASH512UD32 RDA_FLASH512UD32 + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +#if defined ( __CC_ARM ) /* RealView Compiler */ +extern uint32_t Load$$FLASH_CODE_RAM$$Base; +extern uint32_t Image$$FLASH_CODE_RAM$$Base; +extern uint32_t Load$$FLASH_CODE_RAM$$Length; +extern uint32_t Image$$FLASH_DEMO_A$$Base; +extern uint32_t Load$$FLASH_DEMO_B$$Base; +extern uint32_t Image$$RAM_DEMO_A$$Base; +extern uint32_t Image$$RAM_DEMO_B$$Base; + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ +#pragma section = "FLASH_CODE_RAM" +#pragma section = "FLASH_CODE_ROM" +#pragma section = "FLASH_DEMO_A" +#pragma section = "FLASH_DEMO_B" +#pragma section = "RAM_DEMO_A" +#pragma section = "RAM_DEMO_B" + +#endif + +/** + * @addtogroup RDA_FLASH512UD32_Private_define RDA_FLASH512UD32 Private Define + * @{ + */ +#if defined ( __CC_ARM ) /* RealView Compiler */ +#define FLASH_API_ROM (uint32_t *)&Load$$FLASH_CODE_RAM$$Base + +#define FLASH_API_RAM (uint32_t *)&Image$$FLASH_CODE_RAM$$Base +#define SIZE_FLASH_API (uint32_t)&Load$$FLASH_CODE_RAM$$Length + +#define DEMO_A_FLASH (uint32_t *)&Image$$FLASH_DEMO_A$$Base +#define DEMO_B_FLASH (uint32_t *)&Load$$FLASH_DEMO_B$$Base + +#define DEMO_A_RAM (uint32_t *)&Image$$RAM_DEMO_A$$Base +#define DEMO_B_RAM (uint32_t *)&Image$$RAM_DEMO_B$$Base + + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ +#define FLASH_API_ROM ((uint32_t *)__section_begin("FLASH_CODE_ROM")) + +#define FLASH_API_RAM ((uint32_t *)__section_begin("FLASH_CODE_RAM")) +#define SIZE_FLASH_API ((uint32_t)__section_size("FLASH_CODE_ROM")) + +#define DEMO_A_FLASH ((uint32_t *)__section_begin("FLASH_DEMO_A")) +#define DEMO_B_FLASH ((uint32_t *)__section_begin("FLASH_DEMO_B")) + +#define DEMO_A_RAM ((uint32_t *)__section_begin("RAM_DEMO_A")) +#define DEMO_B_RAM ((uint32_t *)__section_begin("RAM_DEMO_B")) + +#endif + +/* code start address */ +#define DEMO_START_ADDR ((uint32_t)DEMO_A_FLASH) + +#define USERINFOSIZE (128) /*= num) { + result = ADC_PARAM_OK; + } + + return (result); +} +#endif +/** + * @} + */ /* End of group ADC_Private_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_INCLUDE_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_cg.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_cg.h new file mode 100644 index 00000000000..2d88d299699 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_cg.h @@ -0,0 +1,129 @@ +/** + ******************************************************************************* + * @file txzp_cg.h + * @brief This file provides all the functions prototypes for CG driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __CG_H +#define __CG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup CG CG + * @brief CG Driver. + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_define CG Exported Define + * @{ + */ +/** + * @defgroup CG_CGOSCCR_OSCF fosc high-speed oscillator Select Status. + * @brief fosc high-speed oscillator Select Status. + * @{ + */ +#define CG_CGOSCCR_OSCF_IHOSC ((uint32_t)0x00000000) /*!< IHOSC */ +#define CG_CGOSCCR_OSCF_EHOSC ((uint32_t)0x00000200) /*!< EHOSC */ +/** + * @} + */ /* End of group CG_CGOSCCR_OSCF */ +/** + * @} + */ /* End of group CG_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_define CG Exported Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_typedef CG Exported Typedef + * @{ + */ +/** + * @brief CG member. +*/ +/*----------------------------------*/ +typedef struct { + TSB_CG_TypeDef *p_instance; /*!< Registers base address. */ +} cg_t; + +/** + * @} + */ /* End of group CG_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_functions CG Exported Functions + * @{ + */ +uint32_t cg_get_mphyt0(cg_t *p_obj); +/** + * @} + */ /* End of group CG_Exported_functions */ + +/** + * @} + */ /* End of group CG */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __CG_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_driver_def.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_driver_def.h new file mode 100644 index 00000000000..002cac76bba --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_driver_def.h @@ -0,0 +1,109 @@ +/** + ******************************************************************************* + * @file txzp_driver_def.h + * @brief All common macro and definition for TXZ peripheral drivers + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TXZ_DRIVER_DEF_H +#define __TXZ_DRIVER_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF + * @brief All common macro and definition for TXZ peripheral drivers + * @{ + */ + +/** @defgroup Device_Header_Included Device Header Included + * @brief Include the Device header file of a Target. + * @{ + */ +#include "TMPM4KNA.h" /*!< TMPM4KNA Group Header file. */ +/** + * @} + */ /* End of group Device_Header */ + + +/** @defgroup TXZ_Exported_typedef TXZ Exported typedef + * @{ + */ +typedef enum { + TXZ_SUCCESS = 0U, + TXZ_ERROR = 1U +} TXZ_Result; + +typedef enum { + TXZ_BUSY = 0U, + TXZ_DONE = 1U +} TXZ_WorkState; + +typedef enum { + TXZ_DISABLE = 0U, + TXZ_ENABLE = 1U +} TXZ_FunctionalState; +/** + * @} + */ /* End of group TXZ_Exported_typedef */ + +/** @defgroup TXZ_Exported_macro TXZ Exported macro + * @{ + */ +#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0) + +/** + * @brief To report the name of the source file and source line number where the + * assert_param error has occurred, "DEBUG" must be defined. And detailed + * definition of assert_failed() is needed to be implemented, which can be + * done, for example, in the main.c file. + */ +#ifdef DEBUG +void assert_failed(char *file, int32_t line); +#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) +#else +#define assert_param(expr) +#endif /* DEBUG */ + +/** + * @} + */ /* End of group TXZ_Exported_macro */ + +/** + * @} + */ /* End of group Periph_Driver */ + +/** + * @} + */ /* End of group TXZ_DRIVER_DEF */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TXZ_DRIVER_DEF_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_gpio.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_gpio.h new file mode 100644 index 00000000000..0dd0bfcbbe4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_gpio.h @@ -0,0 +1,1284 @@ +/** + ******************************************************************************* + * @file txzp_gpio.h + * @brief This file provides all the functions prototypes for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __GPIO_H +#define __GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*selects perticularly TMPM4KNA out of TMPM4KyA family */ +#ifndef TMPM4KNA +#define TMPM4KNA +#endif +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup GPIO GPIO + * @brief GPIO Driver. + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_define GPIO Exported Define + * @{ + */ + + +/** + * @defgroup GPIO_Result Result + * @brief GPIO Result Macro Definition. + * @{ + */ +#define GPIO_RESULT_SUCCESS (0) /*!< Success */ +#define GPIO_RESULT_FAILURE (-1) /*!< Failure */ +#define GPIO_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ +/** + * @} + */ /* End of group GPIO_Result */ + +/** + * @} + */ /* End of group GPIO_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ + +/** + * @enum gpio_pinstate_t + * @brief Pin State Reset/Set Enumerated Type Definition. + */ +typedef enum { + GPIO_PIN_RESET = 0, /*!< 0: Clear */ + GPIO_PIN_SET, /*!< 1: Set */ +} gpio_pinstate_t; + +/** + * @enum gpio_pininout_t + * @brief Pin Input/Output Enumerated Type Definition. + */ +typedef enum { + GPIO_PIN_INPUT = 0, /*!< 0: Input */ + GPIO_PIN_OUTPUT, /*!< 1: Output */ + GPIO_PIN_INOUT, /*!< 2: Input/Output */ +} gpio_pininout_t; + +/** + * @enum gpio_gr_t + * @brief Port Group Enumerated Type Definition. + */ +typedef enum { + GPIO_PORT_A = 0x0, /*!< 0: PA */ + GPIO_PORT_B, /*!< 1: PB */ + GPIO_PORT_C, /*!< 2: PC */ + GPIO_PORT_D, /*!< 3: PD */ + GPIO_PORT_E, /*!< 4: PE */ + GPIO_PORT_F, /*!< 5: PF */ + GPIO_PORT_G, /*!< 6: PG */ + GPIO_PORT_H, /*!< 7: PH */ + GPIO_PORT_J, /*!< 8: PJ */ + GPIO_PORT_K, /*!< 9: PK */ + GPIO_PORT_L, /*!< 10:PL */ + GPIO_PORT_M, /*!< 11:PM */ + GPIO_PORT_N, /*!< 12:PN */ + GPIO_PORT_U, /*!< 13:PU */ + GPIO_PORT_V, /*!< 14:PV */ + GPIO_GROUP_Max /*!< Max Number */ +} gpio_gr_t; + +/** + * @enum gpio_num_t + * @brief Port Number Enumerated Type Definition. + */ +typedef enum { + GPIO_PORT_0 = 0x0, /*!< 0: Port0 */ + GPIO_PORT_1 = 0x1, /*!< 1: Port1 */ + GPIO_PORT_2 = 0x2, /*!< 2: Port2 */ + GPIO_PORT_3 = 0x3, /*!< 3: Port3 */ + GPIO_PORT_4 = 0x4, /*!< 4: Port4 */ + GPIO_PORT_5 = 0x5, /*!< 5: Port5 */ + GPIO_PORT_6 = 0x6, /*!< 6: Port6 */ + GPIO_PORT_7 = 0x7, /*!< 7: Port7 */ + GPIO_PORT_Max = 0x08 /*!< Max Number */ +} gpio_num_t; + +/** + * @enum gpio_mode_t + * @brief Port Mode Enumerated Type Definition. + */ +typedef enum { + GPIO_Mode_DATA = 0x0, /*!< 0x0: PxDATA */ + GPIO_Mode_CR = 0x4, /*!< 0x4: PxCR */ + GPIO_Mode_FR1 = 0x8, /*!< 0x8: PxFR1 */ + GPIO_Mode_FR2 = 0xC, /*!< 0xC: PxFR2 */ + GPIO_Mode_FR3 = 0x10, /*!< 0x10: PxFR3 */ + GPIO_Mode_FR4 = 0x14, /*!< 0x14: PxFR4 */ + GPIO_Mode_FR5 = 0x18, /*!< 0x18: PxFR5 */ + GPIO_Mode_FR6 = 0x1C, /*!< 0x1C: PxFR6 */ + GPIO_Mode_FR7 = 0x20, /*!< 0x1C: PxFR7 */ + GPIO_Mode_OD = 0x28, /*!< 0x28: PxOD */ + GPIO_Mode_PUP = 0x2C, /*!< 0x2C: PxPUP */ + GPIO_Mode_PDN = 0x30, /*!< 0x30: PxPDN */ + GPIO_Mode_IE = 0x38 /*!< 0x38: PxIE */ +} gpio_mode_t; + +/** + * @enum gpio_fr_t + * @brief Port Function Number Enumerated Type Definition. + */ +typedef enum { + GPIO_FR_1 = 1, /*!< 1: PxFR1 */ + GPIO_FR_2, /*!< 2: PxFR2 */ + GPIO_FR_3, /*!< 3: PxFR3 */ + GPIO_FR_4, /*!< 4: PxFR4 */ + GPIO_FR_5, /*!< 5: PxFR5 */ + GPIO_FR_6, /*!< 6: PxFR6 */ + GPIO_FR_7, /*!< 7: PxFR7 */ + GPIO_FR_NA, /*!< 8: N/A */ + GPIO_FR_Max, /*!< Max Number */ +} gpio_fr_t; +/** + * @enum gpio_pa0_func_t + * @brief PortA0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PA0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PA0_TSPI0CSIN = 0x1, /*!< 1: TSPI0CSIN */ + GPIO_PA0_T32A00INB0 = 0x4, /*!< 4: T32A00INB0 */ +} gpio_pa0_func_t; + +/** + * @enum gpio_pa1_func_t + * @brief PortA1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PA1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PA1_INT15 = 0x0, /*!< 0: INT15 */ + GPIO_PA1_TSPI0CS1 = 0x1, /*!< 1: TSPI0CS1 */ + GPIO_PA1_T32A00INB1 = 0x4, /*!< 4: T32A00INB1 */ +} gpio_pa1_func_t; + +/** + * @enum gpio_pa2_func_t + * @brief PortA2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PA2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PA2_INT00 = 0x0, /*!< 0: INT00 */ + GPIO_PA2_TSPI0RXD = 0x1, /*!< 1: TSPI0RXD */ + GPIO_PA2_T32A00INA0 = 0x4, /*!< 4: T32A00INA0 */ + GPIO_PA2_T32A00INC0 = 0x5, /*!< 5: T32A00INC0 */ + GPIO_PA2_PMD2DBG = 0x6, /*!< 6: PMD2DBG */ + GPIO_PA2_TRGIN0 = 0x7, /*!< 7: TRGIN0 */ +} gpio_pa2_func_t; + +/** + * @enum gpio_pa3_func_t + * @brief PortA3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PA3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PA3_INT01b = 0x0, /*!< 0: INT00 */ + GPIO_PA3_TSPI0TXD = 0x1, /*!< 1: TSPI0TXD */ + GPIO_PA3_T32A00OUTA = 0x4, /*!< 4: T32A00OUTA */ + GPIO_PA3_T32A00OUTC = 0x5, /*!< 5: T32A00OUTC */ + GPIO_PA3_TRGIN1 = 0x7, /*!< 7: TRGIN1 */ +} gpio_pa3_func_t; + +/** + * @enum gpio_pa4_func_t + * @brief PortA4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PA4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PA4_INT01a = 0x0, /*!< 0: INT01a */ + GPIO_PA4_TSPI0SCK = 0x1, /*!< 1: TSPI0SCK */ + GPIO_PA4_T32A00OUTB = 0x4, /*!< 4: T32A00OUTB */ + GPIO_PA4_TRGIN2 = 0x7, /*!< 7: TRGIN2 */ +} gpio_pa4_func_t; + +/** + * @enum gpio_pb0_func_t + * @brief PortB0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB0_UO0 = 0x4, /*!< 4: UO0 */ +} gpio_pb0_func_t; + +/** + * @enum gpio_pb1_func_t + * @brief PortB1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB1_XO0 = 0x4, /*!< 4: XO0 */ +} gpio_pb1_func_t; + +/** + * @enum gpio_pb2_func_t + * @brief PortB2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB2_VO0 = 0x4, /*!< 4: VO0 */ +} gpio_pb2_func_t; + +/** + * @enum gpio_pb3_func_t + * @brief PortB3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB3_YO0 = 0x4, /*!< 4: YO0 */ +} gpio_pb3_func_t; + +/** + * @enum gpio_pb4_func_t + * @brief PortB4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB4_WO0 = 0x4, /*!< 4: WO0 */ +} gpio_pb4_func_t; + +/** + * @enum gpio_pb5_func_t + * @brief PortB5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB5_ZO0 = 0x4, /*!< 4: ZO0 */ +} gpio_pb5_func_t; + +/** + * @enum gpio_pb6_func_t + * @brief PortB6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB6_EMG0 = 0x4, /*!< 4: EMG0 */ +} gpio_pb6_func_t; + +/** + * @enum gpio_pb7_func_t + * @brief PortB7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB7_OVV0 = 0x4, /*!< 4: OVV0 */ + GPIO_PB7_PMD0DBG = 0x5, /*!< 5: PMD0DBG */ +} gpio_pb7_func_t; + +/** + * @enum gpio_pc0_func_t + * @brief PortC0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC0_UT0TXDA = 0x1, /*!< 1: UT0TXDA */ + GPIO_PC0_UT0RXD = 0x2, /*!< 2: UT0RXD */ + GPIO_PC0_EI2C0SDA = 0x3, /*!< 3: EI2C0SDA */ + GPIO_PC0_I2C0SDA = 0x4, /*!< 4: I2C0SDA */ + GPIO_PC0_T32A02INA0 = 0x5, /*!< 5: T32A02INA0 */ + GPIO_PC0_T32A02INC0 = 0x6, /*!< 6: T32A02INC0 */ +} gpio_pc0_func_t; + +/** + * @enum gpio_pc1_func_t + * @brief PortC1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC1_INT02a = 0x0, /*!< 0: INT10 */ + GPIO_PC1_UT0RXD = 0x1, /*!< 1: UT3RXD */ + GPIO_PC1_UT0TXDA = 0x2, /*!< 2: UT3TXDA */ + GPIO_PC1_EI2C0SCL = 0x3, /*!< 3: TSPI3RXD */ + GPIO_PC1_I2C0SCL = 0x4, /*!< 4: T32A3INA0 */ + GPIO_PC1_T32A02OUTA = 0x5, /*!< 5: T32A2INC0 */ + GPIO_PC1_T32A02OUTC = 0x6, /*!< 5: T32A2INC0 */ +} gpio_pc1_func_t; + +/** + * @enum gpio_pc2_func_t + * @brief PortC2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC2_INT10 = 0x0, /*!< 0: INT10 */ + GPIO_PC2_TSPI0CS0 = 0x3, /*!< 3: TSPI0CS0 */ + GPIO_PC2_T32A03OUTA = 0x5, /*!< 5: T32A03OUTA */ + GPIO_PC2_T32A03OUTC = 0x6, /*!< 6: T32A03OUTC */ + GPIO_PC2_PMD0DBG = 0x7, /*!< 7: PMD0DBG */ +} gpio_pc2_func_t; + +/** + * @enum gpio_pc3_func_t + * @brief PortC3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC3_INT03a = 0x0, /*!< 0: INT03a */ + GPIO_PC3_TSPI0RXD = 0x3, /*!< 3: TSPI0CS0 */ + GPIO_PC3_T32A03OUTB = 0x5, /*!< 5: T32A03OUTB */ + GPIO_PC3_PMD1DBG = 0x7, /*!< 7: PMD1DBG */ +} gpio_pc3_func_t; + +/** + * @enum gpio_pc4_func_t + * @brief PortC4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC4_UT1TXDA = 0x1, /*!< 1: UT1TXDA */ + GPIO_PC4_UT1RXD = 0x2, /*!< 2: UT1RXD */ + GPIO_PC4_TSPI0TXD = 0x3, /*!< 3: TSPI0TXD */ +} gpio_pc4_func_t; + +/** + * @enum gpio_pc5_func_t + * @brief PortC5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC5_UT1RXD = 0x1, /*!< 1: UT1RXD */ + GPIO_PC5_UT1TXDA = 0x2, /*!< 2: UT1TXDA */ + GPIO_PC5_TSPI0SCK = 0x3, /*!< 3: TSPI0SCK */ +} gpio_pc5_func_t; + +/** + * @enum gpio_pc6_func_t + * @brief PortC6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC6_INT02b = 0x0, /*!< 0: INT02b */ + GPIO_PC6_TSPI0CS1 = 0x3, /*!< 3: TSPI0CS1 */ + GPIO_PC6_T32A02INA1 = 0x5, /*!< 5: T32A02INA1 */ + GPIO_PC6_T32A02INC1 = 0x6, /*!< 6: T32A02INC1 */ +} gpio_pc6_func_t; +/** + * @enum gpio_pc7_func_t + * @brief PortC7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC7_TSPI0CSIN = 0x3, /*!< 3: TSPI0CSIN */ + GPIO_PC7_T32A02INB0 = 0x5, /*!< 5: T32A02INB0 */ +} gpio_pc7_func_t; + +/** + * @enum gpio_pd0_func_t + * @brief PortD0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD0_INT17b = 0x0, /*!< 0: INT17b */ + GPIO_PD0_T32A02INB1 = 0x4, /*!< 4: T32A02INB1 */ +} gpio_pd0_func_t; + +/** + * @enum gpio_pd1_func_t + * @brief PortD1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD1_INT17a = 0x0, /*!< 0: INT17a */ + GPIO_PD1_T32A02OUTB = 0x4, /*!< 4: T32A02OUTB */ +} gpio_pd1_func_t; + +/** + * @enum gpio_pd2_func_t + * @brief PortD2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD2_INT03b = 0x0, /*!< 0: INT03b */ + GPIO_PD2_UT0CTS_N = 0x1, /*!< 1: UT0CTS_N */ + GPIO_PD2_T32A03INA0 = 0x4, /*!< 4: T32A03INA0 */ + GPIO_PD2_T32A03INC0 = 0x5, /*!< 5: T32A03INC0 */ +} gpio_pd2_func_t; + +/** + * @enum gpio_pd3_func_t + * @brief PortD3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD3_UT0RTS_N = 0x1, /*!< 1: UT0RTS_N */ + GPIO_PD3_I2C1SDA = 0x2, /*!< 2: I2C1SDA */ + GPIO_PD3_EI2C1SDA = 0x3, /*!< 3: EI2C1SDA */ + GPIO_PD3_T32A03INA1 = 0x4, /*!< 4: T32A03INA1 */ + GPIO_PD3_T32A03INC1 = 0x5, /*!< 5: T32A03INC1 */ + GPIO_PD3_ENC2A = 0x6, /*!< 6: ENC2A */ +} gpio_pd3_func_t; + +/** + * @enum gpio_pd4_func_t + * @brief PortD4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD4_INT18b = 0x0, /*!< 0: INT18b */ + GPIO_PD4_I2C1SCL = 0x2, /*!< 2: I2C1SCL */ + GPIO_PD4_EI2C1SCL = 0x3, /*!< 3: EI2C1SCL */ + GPIO_PD4_T32A03INB0 = 0x4, /*!< 4: T32A03INB0 */ + GPIO_PD4_ENC2B = 0x6, /*!< 6: ENC2B */ +} gpio_pd4_func_t; + +/** + * @enum gpio_pd5_func_t + * @brief PortD5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD5_INT18a = 0x0, /*!< 0: INT18a */ + GPIO_PD5_T32A03INB1 = 0x4, /*!< 4: T32A03INB1 */ + GPIO_PD5_ENC2Z = 0x6, /*!< 6: ENC2Z */ +} gpio_pd5_func_t; + +/** + * @enum gpio_pe0_func_t + * @brief PortE0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE0_UO1 = 0x6, /*!< 6: UO1 */ +} gpio_pe0_func_t; + +/** + * @enum gpio_pe1_func_t + * @brief PortE1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE1_INT04b = 0x0, /*!< 0: INT04b */ + GPIO_PE1_T32A03INA0 = 0x4, /*!< 4: T32A03INA0 */ + GPIO_PE1_T32A03INC0 = 0x5, /*!< 5: T32A03INC0 */ + GPIO_PE1_XO1 = 0x6, /*!< 6: XO1 */ +} gpio_pe1_func_t; + +/** + * @enum gpio_pe2_func_t + * @brief PortE2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE2_T32A03OUTA = 0x4, /*!< 4: T32A03OUTA */ + GPIO_PE2_T32A03OUTC = 0x5, /*!< 5: T32A03OUTC */ + GPIO_PE2_VO1 = 0x6, /*!< 6: VO1 */ +} gpio_pe2_func_t; + +/** +* @enum gpio_pe3_func_t +* @brief PortE3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PE3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE3_INT04a = 0x0, /*!< 0: INT04a */ + GPIO_PE3_T32A03INA1 = 0x4, /*!< 4: T32A03INA1 */ + GPIO_PE3_T32A03INC1 = 0x5, /*!< 5: T32A03INC1 */ + GPIO_PE3_YO1 = 0x6, /*!< 6: YO1 */ +} gpio_pe3_func_t; + +/** +* @enum gpio_pe4_func_t +* @brief PortE4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PE4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE4_INT11a = 0x0, /*!< 0: INT11a */ + GPIO_PE4_T32A03INB0 = 0x4, /*!< 4: T32A03INB0 */ + GPIO_PE4_WO1 = 0x6, /*!< 6: WO1 */ +} gpio_pe4_func_t; + +/** + * @enum gpio_pe5_func_t + * @brief PortE5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE5_INT05a = 0x0, /*!< 0: INT05a */ + GPIO_PE5_INT11b = 0x0, /*!< 0: INT11b */ + GPIO_PE5_T32A03INB1 = 0x4, /*!< 4: T32A03INB1 */ + GPIO_PE5_ZO1 = 0x6, /*!< 6: ZO1 */ +} gpio_pe5_func_t; + +/** + * @enum gpio_pe6_func_t + * @brief PortE6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE6_INT05b = 0x0, /*!< 0: INT05a */ + GPIO_PE6_T32A03OUTB = 0x4, /*!< 4: T32A03OUTB */ + GPIO_PE6_EMG1 = 0x6, /*!< 6: EMG1 */ +} gpio_pe6_func_t; + +/** + * @enum gpio_pe7_func_t + * @brief PortE7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE7_OVV1 = 0x6, /*!< 6: OVV1 */ + GPIO_PE7_PMD1DBG = 0x7, /*!< 7: PMD1DBG */ +} gpio_pe7_func_t; + +/** + * @enum gpio_pf0_func_t + * @brief PortF0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF0_UT2TXDA = 0x1, /*!< 1: UT2TXDA */ + GPIO_PF0_UT2RXD = 0x2, /*!< 2: UT2RXD */ + GPIO_PF0_T32A05INA0 = 0x4, /*!< 4: T32A05INA0 */ + GPIO_PF0_T32A05INC0 = 0x5, /*!< 5: T32A05INC0 */ + GPIO_PF0_TMS_SWDIO = 0x7, /*!< 7: TMS_SWDIO */ +} gpio_pf0_func_t; + +/** + * @enum gpio_pf1_func_t + * @brief PortF1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF1_INT06a = 0x0, /*!< 0: INT06a */ + GPIO_PF1_UT2RXD = 0x1, /*!< 1: UT2RXD */ + GPIO_PF1_UT2TXDA = 0x2, /*!< 2: UT2TXDA */ + GPIO_PF1_T32A05OUTA = 0x4, /*!< 4: T32A05OUTA */ + GPIO_PF1_T32A05OUTC = 0x5, /*!< 5: T32A05OUTC */ + GPIO_PF1_TCK_SWCLK = 0x7, /*!< 7: TCK_SWCLK */ +} gpio_pf1_func_t; + +/** + * @enum gpio_pf2_func_t + * @brief PortF2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF2_INT06b = 0x0, /*!< 0: INT06b */ + GPIO_PF2_T32A05INA1 = 0x4, /*!< 4: T32A05INA1 */ + GPIO_PF2_T32A05INC1 = 0x5, /*!< 5: TRGIN2 */ + GPIO_PF2_TDO_SWV = 0x7, /*!< 7: TDO_SWV */ +} gpio_pf2_func_t; + +/** + * @enum gpio_pf3_func_t + * @brief PortF3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF3_UT3TXDA = 0x1, /*!< 1: UT3TXDA */ + GPIO_PF3_UT3RXD = 0x2, /*!< 2: UT3RXD */ + GPIO_PF3_T32A01INA0 = 0x4, /*!< 4: T32A01INA0 */ + GPIO_PF3_T32A01INC0 = 0x5, /*!< 5: T32A01INC0 */ + GPIO_PF3_ENC1A = 0x6, /*!< 6: ENC1A */ + GPIO_PF3_TDI = 0x7, /*!< 7: TDI */ +} gpio_pf3_func_t; + +/** + * @enum gpio_pf4_func_t + * @brief PortF4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF4_INT14a = 0x0, /*!< 0: INT14a */ + GPIO_PF4_UT3RXD = 0x1, /*!< 1: UT3RXD */ + GPIO_PF4_UT3TXDA = 0x2, /*!< 2: UT3TXDA */ + GPIO_PF4_NBDSYNC = 0x3, /*!< 3: NBDSYNC */ + GPIO_PF4_T32A01OUTA = 0x4, /*!< 4: NBDSYNC */ + GPIO_PF4_T32A01OUTC = 0x5, /*!< 5: T32A01OUTC */ + GPIO_PF4_ENC1B = 0x6, /*!< 6: ENC1B */ + GPIO_PF4_TRST_N = 0x7, /*!< 7: TRST_N */ +} gpio_pf4_func_t; + +/** + * @enum gpio_pf5_func_t + * @brief PortF5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF5_INT14b = 0x0, /*!< 0: INT14b */ + GPIO_PF5_NBDCLK = 0x3, /*!< 3: NBDCLK */ + GPIO_PF5_T32A01INA1 = 0x4, /*!< 4: T32A01INA1 */ + GPIO_PF5_T32A01INC1 = 0x5, /*!< 5: T32A01INC1 */ + GPIO_PF5_ENC1Z = 0x6, /*!< 6: ENC1Z */ + GPIO_PF5_TRACECLK = 0x7, /*!< 7: TRACECLK */ +} gpio_pf5_func_t; + +/** + * @enum gpio_pf6_func_t + * @brief PortF6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF6_UT3TXDA = 0x1, /*!< 1: UT3TXDA */ + GPIO_PF6_UT3RXD = 0x2, /*!< 2: UT3RXD */ + GPIO_PF6_NBDDATA0 = 0x3, /*!< 3: NBDDATA0 */ + GPIO_PF6_T32A01INB0 = 0x4, /*!< 4: T32A01INB0 */ + GPIO_PF6_TRACEDATA0 = 0x7, /*!< 7: TRACEDATA0 */ +} gpio_pf6_func_t; + +/** + * @enum gpio_pf7_func_t + * @brief PortF7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF7_UT3RXD = 0x1, /*!< 1: UT3RXD */ + GPIO_PF7_UT3TXDA = 0x2, /*!< 2: UT3TXDA */ + GPIO_PF7_NBDDATA1 = 0x3, /*!< 3: NBDDATA1 */ + GPIO_PF7_T32A01INB1 = 0x4, /*!< 4: T32A01INB1 */ + GPIO_PF7_TRACEDATA1 = 0x7, /*!< 7: TRACEDATA1 */ +} gpio_pf7_func_t; + +/** + * @enum gpio_pg0_func_t + * @brief PortG0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PG0_T32A04INA0 = 0x4, /*!< 4: T32A04INA0 */ + GPIO_PG0_T32A04INC0 = 0x5, /*!< 5: T32A04INC0 */ +} gpio_pg0_func_t; + +/** + * @enum gpio_pg1_func_t + * @brief PortG1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG1_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG1_TSPI1CS1 = 0x1, /*!< 1: TSPI1CS1 */ + GPIO_PG1_T32A04INA1 = 0x4, /*!< 4: T32A04INA1 */ + GPIO_PG1_T32A04INC1 = 0x5, /*!< 5: T32A04INC1 */ +} gpio_pg1_func_t; + +/** + * @enum gpio_pg2_func_t + * @brief PortG2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG2_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG2_TSPI1CS0 = 0x1, /*!< 1: TSPI1CS0 */ + GPIO_PG2_T32A04OUTA = 0x4, /*!< 4: T32A04OUTA */ + GPIO_PG2_T32A04OUTC = 0x5, /*!< 5: T32A04OUTC */ +} gpio_pg2_func_t; + +/** + * @enum gpio_pg3_func_t + * @brief PortG3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG3_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG3_INT21 = 0x0, /*!< 0: XO1 */ + GPIO_PG3_TSPI1CSIN = 0x1, /*!< 1: TSPI1CSIN */ + GPIO_PG3_T32A04OUTB = 0x4, /*!< 4: T32A04OUTB */ +} gpio_pg3_func_t; + +/** + * @enum gpio_pg4_func_t + * @brief PortG4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG4_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG4_TSPI1RXD = 0x1, /*!< 1: TSPI1RXD */ + GPIO_PG4_T32A04INB0 = 0x4, /*!< 4: T32A04INB0 */ +} gpio_pg4_func_t; + +/** + * @enum gpio_pg5_func_t + * @brief PortG5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG5_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG5_TSPI1TXD = 0x1, /*!< 1: TSPI1TXD */ + GPIO_PG5_T32A04INB1 = 0x4, /*!< 4: T32A04INB1 */ +} gpio_pg5_func_t; + +/** + * @enum gpio_pg6_func_t + * @brief PortG6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG6_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG6_TSPI1SCK = 0x1, /*!< 1: TSPI1TXD */ +} gpio_pg6_func_t; + +/** + * @enum gpio_ph0_func_t + * @brief PortH0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PH0_X1 = 0x0, /*!< 0: X1 */ + GPIO_PH0_EHCLKIN = 0x0, /*!< 0: X1 */ +} gpio_ph0_func_t; + +/** + * @enum gpio_ph1_func_t + * @brief PortH1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PH1_X2 = 0x0, /*!< 0: X2 */ +} gpio_ph1_func_t; + +/** + * @enum gpio_pj0_func_t + * @brief PortJ0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ0_AINC00 = 0x0, /*!< 0: AINC00 */ +} gpio_pj0_func_t; + +/** + * @enum gpio_pj1_func_t + * @brief PortJ1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ1_AINC01 = 0x0, /*!< 0: AINC01 */ +} gpio_pj1_func_t; + +/** + * @enum gpio_pj2_func_t + * @brief PortJ2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ2_AINC02 = 0x0, /*!< 0: AINC02 */ +} gpio_pj2_func_t; + +/** +* @enum gpio_pj3_func_t +* @brief PortJ3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PJ3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ3_AINC03 = 0x0, /*!< 0: AINC03 */ +} gpio_pj3_func_t; + +/** +* @enum gpio_pj4_func_t +* @brief PortJ4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PJ4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ4_AINC04 = 0x0, /*!< 0: AINC04 */ +} gpio_pj4_func_t; + +/** + * @enum gpio_pj5_func_t + * @brief PortJ5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ5_AINC05 = 0x0, /*!< 0: AINC05 */ +} gpio_pj5_func_t; + +/** + * @enum gpio_pk0_func_t + * @brief PortK0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PK0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PK0_AINB00 = 0x0, /*!< 0: AINB00 */ +} gpio_pk0_func_t; + +/** + * @enum gpio_pk1_func_t + * @brief PortK1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PK1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PK1_AINB01 = 0x0, /*!< 0: AINB01 */ +} gpio_pk1_func_t; + +/** + * @enum gpio_pk2_func_t + * @brief PortK2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PK2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PK2_AINB02 = 0x0, /*!< 0: AINB02 */ +} gpio_pk2_func_t; + +/** +* @enum gpio_pk3_func_t +* @brief PortK3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PK3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PK3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PK3_AINB03 = 0x0, /*!< 0: AINB03 */ +} gpio_pk3_func_t; + +/** +* @enum gpio_pk4_func_t +* @brief PortK4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PK4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PK4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PK4_AINB04 = 0x0, /*!< 0: AINB01 */ +} gpio_pk4_func_t; + +/** + * @enum gpio_pl0_func_t + * @brief PortL0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL0_AINA16 = 0x0, /*!< 0: AINA16 */ +} gpio_pl0_func_t; + +/** + * @enum gpio_pl1_func_t + * @brief PortL1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL1_AINA15 = 0x0, /*!< 0: AINA15 */ +} gpio_pl1_func_t; + +/** + * @enum gpio_pl2_func_t + * @brief PortL2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL2_AINA17 = 0x0, /*!< 0: NBDDATA2 */ +} gpio_pl2_func_t; + +/** +* @enum gpio_pl3_func_t +* @brief PortL3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL3_AINA14 = 0x0, /*!< 0: AINA14 */ +} gpio_pl3_func_t; + +/** +* @enum gpio_pl4_func_t +* @brief PortL4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL4_AINA18 = 0x0, /*!< 0: AINA18 */ +} gpio_pl4_func_t; + +/** +* @enum gpio_pl5_func_t +* @brief PortL5 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL5_AINA13 = 0x0, /*!< 0: AINA13 */ +} gpio_pl5_func_t; + +/** +* @enum gpio_pl6_func_t +* @brief PortL6 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL6_AINA09 = 0x0, /*!< 0: AINA09 */ +} gpio_pl6_func_t; + +/** +* @enum gpio_pl7_func_t +* @brief PortL7 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL7_AINA08 = 0x0, /*!< 0: AINA08 */ +} gpio_pl7_func_t; + +/** +* @enum gpio_pm0_func_t +* @brief PortM0 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PM0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PM0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PM0_AINA07 = 0x0, /*!< 0: AINA07 */ +} gpio_pm0_func_t; + +/** + * @enum gpio_pm1_func_t + * @brief PortM1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PM1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PM1_AINA06 = 0x0, /*!< 0: AINA06 */ +} gpio_pm1_func_t; + +/** +* @enum gpio_pm2_func_t +* @brief PortM2 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PM2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PM2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PM2_AINA05 = 0x0, /*!< 0: AINA05 */ +} gpio_pm2_func_t; + +/** +* @enum gpio_pn0_func_t +* @brief PortN0 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PN0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PN0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PN0_UT0TXDA = 0x1, /*!< 0: UT0TXDA */ + GPIO_PN0_UT0RXD = 0x2, /*!< 0: UT0RXD */ + GPIO_PN0_NBDDATA2 = 0x3, /*!< 0: NBDDATA2 */ + GPIO_PN0_T32A05INA0 = 0x4, /*!< 0: T32A05INA0 */ + GPIO_PN0_T32A05INC0 = 0x5, /*!< 0: T32A05INC0 */ + GPIO_PN0_ENC0A = 0x6, /*!< 0: ENC0A */ + GPIO_PN0_TRACEDATA2 = 0x7, /*!< 0: TRACEDATA2 */ +} gpio_pn0_func_t; + +/** + * @enum gpio_pn1_func_t + * @brief PortN1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PN1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PN1_INT16a = 0x0, /*!< 0: INT16a */ + GPIO_PN1_UT0RXD = 0x1, /*!< 0: UT0RXD */ + GPIO_PN1_UT0TXDA = 0x2, /*!< 0: UT0TXDA */ + GPIO_PN1_NBDDATA3 = 0x3, /*!< 0: NBDDATA3 */ + GPIO_PN1_T32A05OUTA = 0x4, /*!< 0: T32A05OUTA */ + GPIO_PN1_T32A05OUTC = 0x5, /*!< 0: T32A05OUTC */ + GPIO_PN1_ENC0B = 0x6, /*!< 0: ENC0B */ + GPIO_PN1_TRACEDATA3 = 0x7, /*!< 0: TRACEDATA3 */ +} gpio_pn1_func_t; + +/** +* @enum gpio_pn2_func_t +* @brief PortN2 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PN2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PN2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PN2_INT16b = 0x0, /*!< 0: INT16b */ + GPIO_PN2_UT0CTS_N = 0x1, /*!< 0: UT0CTS */ + GPIO_PN2_T32A05INA1 = 0x4, /*!< 0: T32A05INA1 */ + GPIO_PN2_T32A05INC1 = 0x5, /*!< 0: T32A05INC1 */ + GPIO_PN2_ENC0Z = 0x6, /*!< 0: ENC0Z */ +} gpio_pn2_func_t; +/** +* @enum gpio_pu0_func_t +* @brief PortU0 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PU0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU0_INT12 = 0x0, /*!< 0: INT12 */ + GPIO_PU0_UT2TXDA = 0x1, /*!< 0: UT2TXDA */ + GPIO_PU0_UT2RXD = 0x2, /*!< 0: UT2RXD */ + GPIO_PU0_I2C1SDA = 0x3, /*!< 0: I2C1SDA */ + GPIO_PU0_T32A02INB1 = 0x4, /*!< 0: T32A02INB1 */ + GPIO_PU0_UO2 = 0x6, /*!< 0: UO2 */ + GPIO_PU0_EI2C1SDA = 0x7, /*!< 0: EI2C1SDA */ +} gpio_pu0_func_t; + +/** + * @enum gpio_pu1_func_t + * @brief PortU1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU1_INT07a = 0x0, /*!< 0: INT07a */ + GPIO_PU1_UT2RXD = 0x1, /*!< 0: UT2RXD */ + GPIO_PU1_UT2TXDA = 0x2, /*!< 0: UT2TXDA */ + GPIO_PU1_I2C1SCL = 0x3, /*!< 0: I2C1SCL */ + GPIO_PU1_T32A02INA0 = 0x4, /*!< 0: T32A02INA0 */ + GPIO_PU1_T32A02INC0 = 0x5, /*!< 0: T32A02INC0 */ + GPIO_PU1_XO2 = 0x6, /*!< 0: XO2 */ + GPIO_PU1_EI2C1SCL = 0x7, /*!< 0: EI2C1SCL */ +} gpio_pu1_func_t; + +/** +* @enum gpio_pu2_func_t +* @brief PortU2 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PU2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU2_INT07b = 0x0, /*!< 0: INT07b */ + GPIO_PU2_T32A02OUTA = 0x4, /*!< 0: T32A02OUTA */ + GPIO_PU2_T32A02OUTC = 0x5, /*!< 0: T32A02OUTC */ + GPIO_PU2_VO2 = 0x6, /*!< 0: VO2 */ +} gpio_pu2_func_t; +/** +* @enum gpio_pu3_func_t +* @brief PortU0 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PU3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU3_INT08a = 0x0, /*!< 0: INT08a */ + GPIO_PU3_UT1RTS_N = 0x1, /*!< 0: UT1RTS_N */ + GPIO_PU3_T32A02INB0 = 0x4, /*!< 0: T32A02INB0 */ + GPIO_PU3_ENC2A = 0x5, /*!< 0: ENC2A */ + GPIO_PU3_YO2 = 0x6, /*!< 0: YO2 */ +} gpio_pu3_func_t; + +/** + * @enum gpio_pu4_func_t + * @brief PortU4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU4_INT08b = 0x0, /*!< 0: INT08b */ + GPIO_PU4_UT1CTS_N = 0x1, /*!< 0: UT1CTS_N */ + GPIO_PU4_T32A02OUTB = 0x4, /*!< 0: T32A02OUTB */ + GPIO_PU4_T32A02INC1 = 0x5, /*!< 0: T32A02INC1 */ + GPIO_PU4_WO2 = 0x6, /*!< 0: WO2 */ +} gpio_pu4_func_t; + +/** +* @enum gpio_pu5_func_t +* @brief PortU5 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PU5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU5_INT13 = 0x0, /*!< 0: INT13 */ + GPIO_PU5_UT1TXDA = 0x1, /*!< 0: UT1TXDA */ + GPIO_PU5_UT1RXD = 0x2, /*!< 0: UT1RXD */ + GPIO_PU5_T32A02INA1 = 0x4, /*!< 0: T32A02INA1 */ + GPIO_PU5_ENC2B = 0x5, /*!< 0: ENC2B */ + GPIO_PU5_ZO2 = 0x6, /*!< 0: ZO2 */ +} gpio_pu5_func_t; + +/** +* @enum gpio_pu6_func_t +* @brief PortU6 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PU6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU6_INT09 = 0x0, /*!< 0: INT09 */ + GPIO_PU6_UX1RXD = 0x1, /*!< 0: UX1RXD */ + GPIO_PU6_UT1TXDA = 0x2, /*!< 0: UT1TXDA */ + GPIO_PU6_ENC2Z = 0x5, /*!< 0: ENC2Z */ + GPIO_PU6_EMG2 = 0x6, /*!< 0: EMG2 */ +} gpio_pu6_func_t; + +/** + * @enum gpio_pu7_func_t + * @brief PortU7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU7_OVV2 = 0x6, /*!< 0: OVV2 */ + GPIO_PU7_PMD2DBG = 0x7, /*!< 0: PMD2DBG */ +} gpio_pu7_func_t; + +/** +* @enum gpio_pv0_func_t +* @brief PortV0 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PV0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PV0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PV0_TSPI1CSIN = 0x2, /*!< 0: TSPI1CSIN */ + GPIO_PV0_T32A01OUTB = 0x4, /*!< 0: T32A01OUTB */ +} gpio_pv0_func_t; + +/** +* @enum gpio_pv1_func_t +* @brief PortV1 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PV1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PV1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PV1_UT0RTS_N = 0x1, /*!< 0: UT0RTS_N */ + GPIO_PV1_TSPI1RXD = 0x2, /*!< 0: TSPI1RXD */ +} gpio_pv1_func_t; + +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief GPIO handle structure definenition. +*/ +/*----------------------------------*/ + +typedef struct gpio_pa_handle { + TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ + TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ + TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ + TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ + TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ + TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ + TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ + TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ + TSB_PJ_TypeDef *p_pj_instance; /*!< Registers base address. */ + TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ + TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ + TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */ + TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ + TSB_PU_TypeDef *p_pu_instance; /*!< Registers base address. */ + TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ +} _gpio_t; + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_functions GPIO Exported Functions + * @{ + */ +TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group); +TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group); +TXZ_Result gpio_func(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t func, uint32_t inout); +TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val); +TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val); +TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val); +TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate); + +/** + * @} + */ /* End of group GPIO_Exported_functions */ + +/** + * @} + */ /* End of group GPIO */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __GPIO_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c.h new file mode 100644 index 00000000000..34493c222e1 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c.h @@ -0,0 +1,819 @@ +/** + ******************************************************************************* + * @file txzp_i2c.h + * @brief This file provides all the functions prototypes for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __I2C_H +#define __I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +#ifdef DEBUG +/** + * @name I2C_NULL Pointer + * @brief NULL Pointer. + * @{ + */ +#define I2C_NULL ((void *)0) +/** + * @} + */ /* End of name I2C_NULL Pointer */ +#endif + +/** + * @name I2CxST Macro Definition. + * @brief I2CxST Register Macro Definition. + * @{ + */ +#define I2CxST_NACK ((uint32_t)0x00000008) /*!< NACK Interrupt Status. */ +#define I2CxST_I2CBF ((uint32_t)0x00000004) /*!< I2CBF Interrupt Status. */ +#define I2CxST_I2CAL ((uint32_t)0x00000002) /*!< I2CAL Interrupt Status. */ +#define I2CxST_I2C ((uint32_t)0x00000001) /*!< I2C Interrupt Status. */ +#define I2CxST_CLEAR ((uint32_t)0x0000000F) /*!< All Bits Clear. */ +/** + * @} + */ /* End of name I2CxST Macro Definition */ + +/** + * @name I2CxCR1 Macro Definition. + * @brief I2CxCR1 Register Macro Definition. + * @{ + */ +#define I2CxCR1_ACK ((uint32_t)0x00000010) /*!< ACK */ +#define I2CxCR1_NOACK ((uint32_t)0x00000008) /*!< NOACK */ +#define I2CxCR1_BC ((uint32_t)0x000000E0) /*!< BC */ + +/** + * @} + */ /* End of name I2CxCR1 Macro Definition */ + +/** + * @name I2CxDBR Macro Definition. + * @brief I2CxDBR Register Macro Definition. + * @{ + */ +#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */ +/** + * @} + */ /* End of name I2CxDBR Macro Definition */ + + +/** + * @name I2CxCR2 Macro Definition. + * @brief I2CxCR2 Register Macro Definition. + * @{ + */ +#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) /*!< PIN=1 */ +#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) /*!< I2CM=0 */ +#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) /*!< I2CM=1 */ +#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) /*!< SWRES=10 */ +#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) /*!< SWRES=01 */ +#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) /*!< MST=1,TRX=1,BB=1,PIN=1,I2CM=1 */ +#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) /*!< MST=1,TRX=1,BB=0,PIN=1,I2CM=1 */ +#define I2CxCR2_INIT ((uint32_t)0x00000008) /*!< MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00 */ + +/** + * @} + */ /* End of name I2CxCR2 Macro Definition */ + +/** + * @name I2CxSR Macro Definition. + * @brief I2CxSR Register Macro Definition. + * @{ + */ +#define I2CxSR_MST ((uint32_t)0x00000080) /*!< MST */ +#define I2CxSR_TRX ((uint32_t)0x00000040) /*!< TRX */ +#define I2CxSR_BB ((uint32_t)0x00000020) /*!< BB */ +#define I2CxSR_PIN ((uint32_t)0x00000010) /*!< PIN */ +#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ +#define I2CxSR_AAS ((uint32_t)0x00000004) /*!< AAS */ +#define I2CxSR_AD0 ((uint32_t)0x00000002) /*!< AD0 */ +#define I2CxSR_LRB ((uint32_t)0x00000001) /*!< LRB */ +/** + * @} + */ /* End of name I2CxSR Macro Definition */ + +/** + * @name I2CxPRS Macro Definition. + * @brief I2CxPRS Register Macro Definition. + * @{ + */ +#define I2CxPRS_PRCK ((uint32_t)0x0000001F) /*!< PRCK */ +/** + * @} + */ /* End of name I2CxPRS Macro Definition */ + +/** + * @name I2CxIE Macro Definition. + * @brief I2CxIE Register Macro Definition. + * @{ + */ +#define I2CxIE_SELPINCD ((uint32_t)0x00000040) /*!< SELPINCD */ +#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) /*!< DMARI2CTX */ +#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) /*!< DMARI2CRX */ +#define I2CxIE_I2C ((uint32_t)0x00000001) /*!< INTI2C */ +#define I2CxIE_CLEAR ((uint32_t)0x00000000) /*!< All Clear Setting */ + +/** + * @} + */ /* End of name I2CxIE Macro Definition */ + + +/** + * @name I2CxOP Macro Definition. + * @brief I2CxOP Register Macro Definition. + * @{ + */ +#define I2CxOP_DISAL ((uint32_t)0x00000080) /*!< DISAL */ +#define I2CxOP_SA2ST ((uint32_t)0x00000040) /*!< SA2ST */ +#define I2CxOP_SAST ((uint32_t)0x00000020) /*!< SAST */ +#define I2CxOP_NFSEL ((uint32_t)0x00000010) /*!< NFSEL */ +#define I2CxOP_RSTA ((uint32_t)0x00000008) /*!< RSTA */ +#define I2CxOP_GCDI ((uint32_t)0x00000004) /*!< GDDI */ +#define I2CxOP_SREN ((uint32_t)0x00000002) /*!< SREN */ +#define I2CxOP_MFACK ((uint32_t)0x00000001) /*!< MFACK */ +#ifndef I2C_MULTI_MASTER +#define I2CxOP_INIT ((uint32_t)0x00000084) /*!< Initial Settings. */ +#else +#define I2CxOP_INIT ((uint32_t)0x00000004) /*!< Initial Settings. */ +#endif +#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) /*!< Slave Initial Settings. */ +/** + * @} + */ /* End of name I2CxOP Macro Definition */ + +/** + * @name I2CxAR Macro Definition. + * @brief I2CxAR Register Macro Definition. + * @{ + */ +#define I2CxAR_ALS ((uint32_t)0x00000001) /*!< ALS. */ +#define I2CxAR_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ +#define I2CxAR2_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ + +/** + * @} + */ /* End of name I2CxAR Macro Definition */ + + +/** + * @name I2CxPM Macro Definition. + * @brief I2CxPM Register Macro Definition. + * @{ + */ +#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */ +/** + * @} + */ /* End of name I2CxPM Macro Definition */ + +/** + * @name I2CxWUPCR_INT Macro Definition. + * @brief I2CxWUPCR_INT Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */ +#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */ +/** + * @} + */ /* End of name I2CxWUPCR_INT Macro Definition */ + +/** + * @name I2CxWUPCR_RST Macro Definition. + * @brief I2CxWUPCR_RST Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */ +#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */ +/** + * @} + */ /* End of name I2CxWUPCR_RST Macro Definition */ + + +/** + * @name I2CxWUPCR_ACK Macro Definition. + * @brief I2CxWUPCR_ACK Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */ +#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */ +/** + * @} + */ /* End of name I2CxWUPCR_RST Macro Definition */ +/** + * @} + */ /* End of group UTILITIES_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Clock setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sck; /*!< Select internal SCL output clock frequency. */ + uint32_t prsck; /*!< Prescaler clock frequency for generating the Serial clock. */ +} I2C_clock_setting_t; + +/*----------------------------------*/ +/** + * @brief Wakeup Control setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sgcdi; /*!< Select general call detect ON/OFF. */ + uint32_t ack; /*!< Select ACK output. */ + uint32_t reset; /*!< I2C BUS Rest. */ + uint32_t intend; /*!< Interrupt release. */ +} I2CS_wup_setting_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + I2C_clock_setting_t clock; /*!< Serial clock setting. */ +} I2C_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + I2CS_wup_setting_t wup; /*!< Wakeup Control setting. */ +} I2CS_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief I2C handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_I2C_TypeDef *p_instance; /*!< Registers base address. */ + I2C_initial_setting_t init; /*!< Initial setting. */ +} I2C_t; +#if defined(I2CSxWUP_EN) +/*----------------------------------*/ +/** + * @brief I2CS handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_I2CS_TypeDef *p_instance; /*!< Registers base address. */ + I2CS_initial_setting_t init; /*!< Initial setting. */ +} I2CS_t; +#endif +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +__STATIC_INLINE void I2C_reset(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj); +__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj); +__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj); +__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data); +__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj); +__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack); +__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj); +__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj); +__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj); +__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx); +__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj); +__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr); +__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj); + +/*--------------------------------------------------*/ +/** + * @brief I2C software reset. + * @param p_obj :I2C object. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_reset(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; + p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; + } +#else + p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; + p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief I2C bus port high + * @param p_obj :I2C object. + * @retval true :SDA and SCL Port High. + * @retval false :Bus Error. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); + } + return (0); +#else + return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Generate stop condition. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; + } +#else + p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Read from Data buffer + * @param p_obj :I2C object. + * @retval result :Read data. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); + } + return (0); +#else + return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Write to Data buffer. + * @param p_obj :I2C object. + * @param data :Write data. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); + } +#else + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return restart condition + * @param p_obj :I2C object. + * @retval true :Restart Detected. + * @retval false :Restart Non-Detected. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + __IO uint32_t opreg = p_obj->p_instance->OP; + p_obj->p_instance->OP &= ~I2CxOP_RSTA; + return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); + } + return (0); +#else + __IO uint32_t opreg = p_obj->p_instance->OP; + p_obj->p_instance->OP &= ~I2CxOP_RSTA; + return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Set Ack condition + * @param p_obj :I2C object. + * @param nack :1 NACK, 0 ACK. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + if (nack) { + p_obj->p_instance->OP |= I2CxOP_MFACK; + } else { + p_obj->p_instance->OP &= ~I2CxOP_MFACK; + } + } +#else + if (nack) { + p_obj->p_instance->OP |= I2CxOP_MFACK; + } else { + p_obj->p_instance->OP &= ~I2CxOP_MFACK; + } +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return received Ack condition + * @param p_obj :I2C object. + * @retval true :NACK Received. + * @retval false :ACK Received. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return Busy condition + * @param p_obj :I2C object. + * @retval true :I2C bus busy. + * @retval false :I2C bus free. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return The Master status + * @param p_obj :I2C object. + * @retval true :Master mode. + * @retval false :Slave mode. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return The Transmitter + * @param p_obj :I2C object. + * @retval true :Transmitter. + * @retval false :Receiver. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Interrupt Status + * @param p_obj :I2C object. + * @retval true :Interruput Occured. + * @retval false :No Interruput Occured. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); + } + return (0); +#else + return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Interrupt Status Clear + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->ST = I2CxST_CLEAR; + } +#else + p_obj->p_instance->ST = I2CxST_CLEAR; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->IE = I2CxIE_I2C; + } +#else + p_obj->p_instance->IE = I2CxIE_I2C; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt setting. + * @param p_obj :I2C object. + * @param tx :Direction of transfer(1=tx 0=rx). + * @retval - + * @note For DMA transfer. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + if (tx) { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); + } else { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); + } + } +#else + if (tx) { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); + } else { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); + } +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable Interrupt setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->IE = I2CxIE_CLEAR; + } +#else + p_obj->p_instance->IE = I2CxIE_CLEAR; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Set slave address. + * @param p_obj :I2C object. + * @param addr :slave address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); + p_obj->p_instance->AR2 = I2CxAR2_INIT; + } +#else + p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); + p_obj->p_instance->AR2 = I2CxAR2_INIT; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Detecting Slave Address + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) + && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); + } + return (0); +#else + return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) + && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); +#endif +} + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +void I2C_init(I2C_t *p_obj); +void I2C_start_condition(I2C_t *p_obj, uint32_t data); +uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting); +void I2C_slave_init(I2C_t *p_obj); +#if defined(I2CSxWUP_EN) +void I2CS_init(I2CS_t *p_obj); +void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); +void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); +#endif +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __I2C_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c_api.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c_api.h new file mode 100644 index 00000000000..4fdf3eee92b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c_api.h @@ -0,0 +1,320 @@ +/** + ******************************************************************************* + * @file txzp_i2c_api.h + * @brief This file provides all the functions prototypes for I2C Driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __I2C_API_H +#define __I2C_API_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_i2c.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ +/** + * @defgroup I2C_NullPointer Null Pointer + * @brief I2C NULL Pointer. + * @{ + */ +#define I2C_NULL ((void *)0) +/** + * @} + */ /* End of group I2C_NullPointer */ + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ + +/** + * @defgroup I2C_ACK I2C ACK Macros + * @brief I2C Type of Acknowledge. + * @{ + */ +#define I2C_NACK (0) /*!< NACK Received. */ +#define I2C_ACK (1) /*!< ACK Received. */ +/** + * @} + */ /* End of group I2C_ACK */ + + +/** + * @defgroup I2C_ERROR I2C ERROR Macros + * @brief I2C Error definitions. + * @{ + */ +#define I2C_ERROR_NO_ERROR (0) /*!< No Error. */ +#if 0 +#define I2C_ERROR_NO_SLAVE (-1) /*!< No Slave Error. */ +#define I2C_ERROR_BUS_BUSY (-2) /*!< Bus Busy Error.(now, not support) */ +#endif +#define I2C_ERROR_PARAM (-3) /*!< Parameter Error. */ +#define I2C_ERROR_OTHERS (-4) /*!< Others Error. */ +#define I2C_ERROR_ARBITRATION (-5) /*!< Arbitration Error. */ +/** + * @} + */ /* End of group I2C_ERROR */ + + +/** + * @defgroup I2C_Events I2C Events Macros + * @brief I2C Asynch Events. + * @{ + */ +#define I2C_EVENT_ERROR (1 << 1) /*!< Error. */ +#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) /*!< No Slave. */ +#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) /*!< Transfer Complete. */ +#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) /*!< End of Transfer. */ +#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK) +/** + * @} + */ /* End of group I2C_Events */ + +/** + * @defgroup I2C_SlaveReceive I2C Slave Receive Return Macros + * @brief I2C Received Contents of Slave. + * @{ + */ +#define I2C_NO_DATA (0) /*!< the slave has not been addressed. */ +#define I2C_READ_ADDRESSED (1) /*!< the master has requested a read from this slave. */ +#define I2C_WRITE_GENERAL (2) /*!< the master is writing to all slave.(now, not support) */ +#define I2C_WRITE_ADDRESSED (3) /*!< the master is writing to this slave. */ +/** + * @} + */ /* End of group I2C_SlaveReceive */ + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ + +/*----------------------------------*/ +/** + * @brief i2c Port Enumerated Type Definition. +*/ +/*----------------------------------*/ +typedef enum { + I2C_PORT_PG2 = 0, /*!< 0: PG2 I2C0 */ + I2C_PORT_PG3, /*!< 1: PG3 I2C0 */ + I2C_PORT_PF2, /*!< 2: PF2 I2C1 */ + I2C_PORT_PF3, /*!< 3: PF3 I2C1 */ + I2C_PORT_PG4, /*!< 4: PG4 I2C2 */ + I2C_PORT_PG5, /*!< 5: PG5 I2C2 */ + I2C_PORT_PJ6, /*!< 6: PJ6 I2C3 */ + I2C_PORT_PJ7, /*!< 7: PJ7 I2C3 */ + I2C_PORT_PJ2, /*!< 8: PJ2 I2C4 */ + I2C_PORT_PJ3, /*!< 9: PJ3 I2C4 */ +} +i2c_port_t; + +/*----------------------*/ +/* I2C Setting */ +/*----------------------*/ +/* #define I2C_CHANNEL0 */ +#define I2C_CHANNEL3 +/* #define I2C_CHANNEL2 */ +/* #define I2C_CHANNEL3 */ +/* #define I2C_CHANNEL4 */ +#if defined(I2C_CHANNEL0) +#define I2Cx_TEXT "I2C0" +#define I2C_CFG_PORT_SCL (I2C_PORT_PG3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PG2) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL1) +#define I2Cx_TEXT "I2C1" +#define I2C_CFG_PORT_SCL (I2C_PORT_PF3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PF2) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL2) +#define I2Cx_TEXT "I2C2" +#define I2C_CFG_PORT_SCL (I2C_PORT_PG5) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PG4) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL3) +#define I2Cx_TEXT "I2C3" +#define I2C_CFG_PORT_SCL (I2C_PORT_PJ7) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PJ6) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL4) +#define I2Cx_TEXT "I2C4" +#define I2C_CFG_PORT_SCL (I2C_PORT_PJ3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PJ2) /*!< SDA Port. */ +#else +#error "target channel is non-select." +#endif + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief I2C internal information structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t bus_free; /*!< Bus free information. */ + uint8_t start; /*!< Start condition information. */ + uint32_t irqn; /*!< IRQ number table pointer. */ + struct { + uint32_t address; /*!< Slave address. */ + uint32_t stop; /*!< Stop control */ + uint32_t event; /*!< I2C Event information. */ + uint32_t state; /*!< Transfer State. */ + } asynch; +} i2c_internal_info_t; + +/*----------------------------------*/ +/** + * @brief I2C buffer structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_buffer; /*!< Buffer address. */ + uint32_t length; /*!< Buffer length. */ + uint32_t pos; /*!< Buffer pointer. */ +} i2c_buffer_t; + +/*----------------------------------*/ +/** + * @brief I2C handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + I2C_t i2c; /*!< I2C class structure. */ + i2c_internal_info_t info; /*!< Internal Information. */ + i2c_buffer_t tx_buff; /*!< Tx buffer structure. */ + i2c_buffer_t rx_buff; /*!< Rx buffer structure. */ +} _i2c_t; + +/** + * @} + */ /* End of group UTILITIES_Exported_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_functions + * @{ + */ +TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl); +TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz); +void i2c_reset_t(_i2c_t *p_obj); +TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj); +TXZ_Result i2c_start_t(_i2c_t *p_obj); +TXZ_Result i2c_stop_t(_i2c_t *p_obj); +int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); +int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); +int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last); +int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data); +uint8_t i2c_active_t(_i2c_t *p_obj); +TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop); +uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj); +void i2c_abort_asynch_t(_i2c_t *p_obj); + +/* For slave */ +void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave); +int32_t i2c_slave_receive_t(_i2c_t *p_obj); +int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); +int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); +void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address); +TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length); +uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj); +void i2c_slave_abort_asynch_t(_i2c_t *p_obj); + +/** + * @} + */ /* End of group UTILITIES_Exported_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __I2C_API_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_t32a.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_t32a.h new file mode 100644 index 00000000000..cff3563c80c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_t32a.h @@ -0,0 +1,1037 @@ +/** + ******************************************************************************* + * @file txzp_t32a.h + * @brief This file provides all the functions prototypes for T32A driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __T32A_H +#define __T32A_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup T32A T32A + * @brief T32A Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Exported_define T32A Exported Define + * @{ + */ + +/** + * @defgroup T32A_Result Result + * @brief T32A Result Macro Definition. + * @{ + */ +#define T32A_RESULT_SUCCESS (0) /*!< Success */ +#define T32A_RESULT_FAILURE (-1) /*!< Failure */ +#define T32A_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ +/** + * @} + */ /* End of group T32A_Result */ + +/** + * @defgroup T32A_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define T32A_NULL ((void *)0) /*!< NULL Pointer For T32A */ +/** + * @} + */ /* End of group T32A_NullPointer */ + +/** +* @defgroup T32A_HALT T32A Debug HALT Control +* @brief Debug HALT Control Run/Stop HALT Macro Definition. +* @{ +*/ +#define T32A_DBG_HALT_RUN ((uint32_t)0x00000000) /*!< Run */ +#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) /*!< Stop */ +/** + * @} + */ /* End of group T32A_HALT */ + +/** +* @defgroup T32A_MODE32 T32A 16bit/32bit MODE +* @brief T32A 16bit/32bit MODE MODE32 Macro Definition. +* @{ +*/ +#define T32A_MODE_16 ((uint32_t)0x00000000) /*!< 16bit Mode */ +#define T32A_MODE_32 ((uint32_t)0x00000001) /*!< 32bit Mode */ +/** + * @} + */ /* End of group T32A_MODE32 */ + +/** +* @defgroup T32A_RUNFLGx T32A RUNFLG Control +* @brief Run/Stop RUNFLGx Macro Definition. +* @{ +*/ +#define T32A_RUNFLG_RUN ((uint32_t)0x00000010) /*!< Run */ +#define T32A_RUNFLG_STOP ((uint32_t)0x00000000) /*!< Stop */ +/** + * @} + */ /* End of group T32A_RUNFLGx */ + +/** + * @defgroup T32A_SFTSTPx T32A SW STOP Control + * @brief T32A SW STOPx SFTSTPx Macro Definition. + * @{ + */ +#define T32A_COUNT_DONT_STOP ((uint32_t)0x0000000) /*!< No effect */ +#define T32A_COUNT_STOP ((uint32_t)0x0000004) /*!< Counter Stop */ +/** + * @} + */ /* End of group T32A_SFTSTPx */ + +/** + * @defgroup T32A_SFTSTAx T32A SW START Control + * @brief T32A SW STARTx SFTSTAx Macro Definition. + * @{ + */ +#define T32A_COUNT_DONT_START ((uint32_t)0x0000000) /*!< No effect */ +#define T32A_COUNT_START ((uint32_t)0x0000002) /*!< Counter Start */ +/** + * @} + */ /* End of group T32A_SFTSTAx */ + +/** + * @defgroup T32A_RUNx T32A RUN Disable/Enable Control + * @brief RUN Disable/Enable RUNx Macro Definition. + * @{ + */ +#define T32A_RUN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define T32A_RUN_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group T32A_RUNx */ + + +/** + * @defgroup T32A_PRSCLx T32A PRESCALER Control + * @brief PRESCALER Control PRSCLx Macro Definition. + * @{ + */ +#define T32A_PRSCLx_1 ((uint32_t)0x00000000) /*!< 1/1 */ +#define T32A_PRSCLx_2 ((uint32_t)0x10000000) /*!< 1/2 */ +#define T32A_PRSCLx_8 ((uint32_t)0x20000000) /*!< 1/8 */ +#define T32A_PRSCLx_32 ((uint32_t)0x30000000) /*!< 1/32 */ +#define T32A_PRSCLx_128 ((uint32_t)0x40000000) /*!< 1/128 */ +#define T32A_PRSCLx_256 ((uint32_t)0x50000000) /*!< 1/256 */ +#define T32A_PRSCLx_512 ((uint32_t)0x60000000) /*!< 1/512 */ +#define T32A_PRSCLx_1024 ((uint32_t)0x70000000) /*!< 1/1024 */ +/** + * @} + */ /* End of group T32A_PRSCLx */ + +/** + * @defgroup T32A_CLKx T32A COLCK Control + * @brief CLOCK Control CLKA Macro Definition. + * @{ + */ +#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /*!< prescaler */ +#define T32A_CLKx_INTRG ((uint32_t)0x01000000) /*!< internal triger */ +#define T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000) /*!< other timer rising edge */ +#define T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000) /*!< other timer trailing edge */ +#define T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000) /*!< external triger rising edge */ +#define T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) /*!< external triger trailing edge */ +/** + * @} + */ /* End of group T32A_CLKx */ + +/** + * @defgroup T32A_WBFx T32A Double Buffer Disable/Enable Control + * @brief Double Buffer Disable/Enable WBFx Macro Definition. + * @{ + */ +#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /*!< Enable */ +/** + * @} + */ /* End of group T32A_WBFx */ + +/** +* @defgroup T32A_UPDNx T32A Counter Up/Down Control +* @brief Counter Up/Down Control UPDNx Macro Definition. +* @{ +*/ +#define T32A_COUNT_UP ((uint32_t)0x00000000) /*!< count up */ +#define T32A_COUNT_DOWN ((uint32_t)0x00010000) /*!< count down */ +#define T32A_COUNT_UPDOWN ((uint32_t)0x00020000) /*!< count updown */ +#define T32A_COUNT_PLS ((uint32_t)0x00030000) /*!< count pulse */ +/** + * @} + */ /* End of group T32A_UPDNx */ + +/** +* @defgroup T32A_RELDx T32A Counter Reload Control +* @brief Counter Reload Control RELDx Macro Definition. +* @{ +*/ +#define T32A_RELOAD_NON ((uint32_t)0x00000000) /*!< Nothing(Free run) */ +#define T32A_RELOAD_INTRG ((uint32_t)0x00000100) /*!< internal trigger */ +#define T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200) /*!< external trigger rising edge */ +#define T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300) /*!< external trigger trailing edge */ +#define T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400) /*!< other timer rising edge */ +#define T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500) /*!< other timer trailing edge */ +#define T32A_RELOAD_SYNC ((uint32_t)0x00000600) /*!< sync(slave channel) */ +#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /*!< match up Timer Register */ +/** + * @} + */ /* End of group T32A_RELDx */ + +/** +* @defgroup T32A_STOPx T32A Counter Stop Control +* @brief Counter Stop Control STOPx Macro Definition. +* @{ +*/ +#define T32A_STOP_NON ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_STOP_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ +#define T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020) /*!< external trigger rising edge */ +#define T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030) /*!< external trigger trailing edge */ +#define T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040) /*!< other timer rising edge */ +#define T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050) /*!< other timer trailing edge */ +#define T32A_STOP_SYNC ((uint32_t)0x00000060) /*!< sync(slave channel) */ +#define T32A_STOP_TREGx ((uint32_t)0x00000070) /*!< match up Timer Register A */ +/** + * @} + */ /* End of group T32A_STOPx */ + + +/** +* @defgroup T32A_STARTx T32A Counter Start Control +* @brief Counter Start Control STARTx Macro Definition. +* @{ +*/ +#define T32A_START_NON ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_START_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ +#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /*!< external trigger rising edge */ +#define T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003) /*!< external trigger trailing edge */ +#define T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004) /*!< other timer rising edge */ +#define T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005) /*!< other timer trailing edge */ +#define T32A_START_SYNC ((uint32_t)0x00000006) /*!< sync(slave channel) */ +#define T32A_START_Rsvd ((uint32_t)0x00000007) /*!< Reserved */ +/** + * @} + */ /* End of group T32A_STARTx */ + +/** + * @defgroup T32A_OCRx T32AxOUTA Control + * @brief T32AxOUTA Control OCRx Macro Definition. + * @{ + */ +#define T32A_OCR_DISABLE ((uint32_t)0x00000000) /*!< Nothig */ +#define T32A_OCR_SET ((uint32_t)0x00000001) /*!< Hi */ +#define T32A_OCR_CLR ((uint32_t)0x00000002) /*!< Low */ +#define T32A_OCR_INVERSION ((uint32_t)0x00000003) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRx */ + +/** + * @defgroup T32A_OCRCAPx1 T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 + * @brief T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 OCRCAPx1 Macro Definition. + * @{ + */ +#define T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCAPx1_SET ((uint32_t)0x00000040) /*!< Hi */ +#define T32A_OCRCAPx1_CLR ((uint32_t)0x00000080) /*!< Low */ +#define T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCAPx1 */ + +/** + * @defgroup T32A_OCRCAPx0 T32AxOUTA Control of T32AxCAPx0 counter value + * @brief T32AxOUTA Control of T32AxCAPx0 T32AxRGx1 OCRCAPx0 Macro Definition. + * @{ + */ +#define T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCAPx0_SET ((uint32_t)0x00000010) /*!< Hi */ +#define T32A_OCRCAPx0_CLR ((uint32_t)0x00000020) /*!< Low */ +#define T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCAPx0 */ + +/** + * @defgroup T32A_OCRCMPx1 T32AxOUTA Control of T32AxRGx1 Counter Value + * @brief T32AxOUTA Control of T32AxRGx1 Counter Value OCRCMPx1 Macro Definition. + * @{ + */ +#define T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /*!< Hi */ +#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) /*!< Low */ +#define T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCMPx1 */ + +/** + * @defgroup T32A_OCRCMPx0 T32AxOUTA Control of T32AxRGx0 Counter Value + * @brief T32AxOUTA Control of T32AxRGx0 Counter Value OCRCMPx0 Macro Definition. + * @{ + */ +#define T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /*!< Hi */ +#define T32A_OCRCMPx0_CLR ((uint32_t)0x00000002) /*!< Low */ +#define T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCMPx0 */ + +/** + * @defgroup T32A_RGx0 T32A Timer Register x0 MASK + * @brief T32A Timer Register A0 MASK RGx0 Macro Definition. + * @{ + */ +#define T32A_RGx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RGx0 */ + +/** + * @defgroup T32A_RGx1 T32A Timer Register x1 MASK + * @brief T32A Timer Register A1 MASK RGx1 Macro Definition. + * @{ + */ +#define T32A_RGx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RGx0 */ + +/** + * @defgroup T32A_TMRx T32A Counter Capture Register x MASK + * @brief T32A Counter Capture Register x MASK TMRx Macro Definition. + * @{ + */ +#define T32A_TMRx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_TMRx */ + +/** + * @defgroup T32A_RELD T32A Counter Reload Register x MASK + * @brief T32A Counter Reload Register x MASK TMRx Macro Definition. + * @{ + */ +#define T32A_RELDx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RELD */ + +/** +* @defgroup T32A_CAPMx1 T32A Capture Control Register x1 +* @brief Capture Control Register A1 CAPMx1 Macro Definition. +* @{ +*/ +#define T32A_CAPMx1_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_CAPMx1_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ +#define T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020) /*!< INx0 rising edge */ +#define T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030) /*!< INx0 trailing edge */ +#define T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040) /*!< INx1 rising edge */ +#define T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050) /*!< INx1 trailing edge */ +#define T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060) /*!< other timer rising edge */ +#define T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) /*!< other timer trailing edge */ +/** + * @} + */ /* End of group T32A_CAPMx1 */ + +/** +* @defgroup T32A_CAPMx0 T32A Capture Control Register x0 +* @brief Capture Control Register x0 CAPMx0 Macro Definition. +* @{ +*/ +#define T32A_CAPMx0_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_CAPMx0_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ +#define T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002) /*!< INx0 rising edge */ +#define T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003) /*!< INx0 trailing edge */ +#define T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004) /*!< INx1 rising edge */ +#define T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005) /*!< INx1 trailing edge */ +#define T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006) /*!< other timer rising edge */ +#define T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) /*!< other timer trailing edge */ +/** + * @} + */ /* End of group T32A_CAPMx0 */ + +/** + * @defgroup T32A_CAPx0 T32A Capture Register x0 MASK + * @brief T32A Capture Register x0 MASK CAPx0 Macro Definition. + * @{ + */ +#define T32A_CAPx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_CAPx0 */ + +/** + * @defgroup T32A_CAPx1 T32A Capture Register x1 MASK + * @brief T32A Capture Register x1 MASK CAPx1 Macro Definition. + * @{ + */ +#define T32A_CAPx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_CAPx1 */ + +/** + * @defgroup T32A_IMSTERR T32A Statuserr Interrupt Request MASK + * @brief T32A Statuserr Interrupt Request MASK IMSTERR Macro Definition. + * @{ + */ +#define T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000) +#define T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010) +/** + * @} + */ /* End of group T32A_IMSTERR */ + +/** + * @defgroup T32A_IMUFx T32A Underflow Interrupt Request MASK + * @brief T32A Underflow Interrupt Request MASK IMUFx Macro Definition. + * @{ + */ +#define T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) /*!< request */ +/** + * @} + */ /* End of group T32A_IMUFx */ + +/** + * @defgroup T32A_IMOFx T32A Overflow Interrupt Request MASK + * @brief T32A Overflow Interrupt Request MASK IMOFx Macro Definition. + * @{ + */ +#define T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) /*!< request */ +/** + * @} + */ /* End of group T32A_IMOFx */ + +/** + * @defgroup T32A_IMx1 T32A Match Up T32AxRGx1 Interrupt Request MASK + * @brief T32A Match Up T32AxRGx1 Interrupt Request MASK IMx1 Macro Definition. + * @{ + */ +#define T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) /*!< request */ +/** + * @} + */ /* End of group T32A_IMx1 */ + +/** + * @defgroup T32A_IMx0 T32A Match Up T32AxRGx0 Interrupt Request MASK + * @brief T32A Match Up T32AxRGx0 Interrupt Request MASK IMx0 Macro Definition. + * @{ + */ +#define T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) /*!< request */ +/** + * @} + */ /* End of group T32A_IMx0 */ + +/** + * @defgroup T32A_INTSTERR T32A_Statuerr Flag Status + * @brief T32A Statuserr Flag Status INTSTERR Macro Definition. + * @{ + */ +#define T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010) +#define T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010) +/** + * @} + */ /* End of group T32A_INTSTERR */ + +/** + * @defgroup T32A_INTUFA T32A Underflow Flag Status + * @brief T32A Underflow Flag Status INTUFA Macro Definition. + * @{ + */ +#define T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008) /*!< Underflow Flag Mask */ +#define T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) /*!< Underflow Flag Clear */ +/** + * @} + */ /* End of group T32A_INTUFA */ + +/** + * @defgroup T32A_INTOFA T32A Overflow Flag Status + * @brief T32A Overflow Flag Status INTOFA Macro Definition. + * @{ + */ +#define T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004) /*!< Overflow Flag Mask */ +#define T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) /*!< Overflow Flag Clear */ +/** + * @} + */ /* End of group T32A_INTOFA */ + +/** + * @defgroup T32A_INTA1 T32A Match Up T32AxRGx1 Flag Status + * @brief T32A Match Up T32AxRGx1 Flag Status INTA1 Macro Definition. + * @{ + */ +#define T32A_INTx1_FLG_MASK ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Mask */ +#define T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Clear */ +/** + * @} + */ /* End of group T32A_INTA1 */ + +/** + * @defgroup T32A_INTA0 T32A Match Up T32AxRGx0 Flag Status + * @brief T32A Match Up T32AxRGx0 Flag Status INTA0 Macro Definition. + * @{ + */ +#define T32A_INTx0_FLG_MASK ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Mask */ +#define T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Clear */ +/** + * @} + */ /* End of group T32A_INTA0 */ + +/** + * @defgroup T32A_DMAENx2 T32A DMA Converter1 Request control + * @brief T32A DMA Converter1 Disable/Enable DMAENx2 Macro Definition. + * @{ + */ +#define T32A_DMAENx2_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx2 */ + +/** + * @defgroup T32A_DMAENx1 T32A DMA InputCapture1 Request control + * @brief T32A DMA InputCapture1 Disable/Enable DMAENx1 Macro Definition. + * @{ + */ +#define T32A_DMAENx1_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx1 */ + +/** + * @defgroup T32A_DMAENx0 T32A DMA InputCapture0 Request control + * @brief T32A DMA InputCapture0 Disable/Enable DMAENx0 Macro Definition. + * @{ + */ +#define T32A_DMAENx0_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx0 */ + +/** +* @defgroup T32A_PDN T32A Pulse Mode Count Down Control +* @brief Pulse Mode Count Down Control PDN Macro Definition. +* @{ +*/ +#define T32A_PDN_NON0 ((uint32_t)0x00000000) /*!< Do not count down */ +#define T32A_PDN_NON1 ((uint32_t)0x00001000) /*!< Do not count down */ +#define T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000) /*!< T32AxINC0 rising edge */ +#define T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000) /*!< T32AxINC0 trailing edge */ +#define T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000) /*!< T32AxINC1 rising edge */ +#define T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000) /*!< T32AxINC1 trailing edge */ +#define T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000) /*!< T32AxINC0 rising edge/trailing edge */ +#define T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) /*!< T32AxINC1 rising edge/trailing edge */ +/** + * @} + */ /* End of group T32A_PDN */ + +/** +* @defgroup T32A_PUP T32A Pulse Mode Count UP Control +* @brief Pulse Mode Count UP Control PUP Macro Definition. +* @{ +*/ +#define T32A_PUP_NON0 ((uint32_t)0x00000000) /*!< Do not count up */ +#define T32A_PUP_NON1 ((uint32_t)0x00000100) /*!< Do not count up */ +#define T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200) /*!< T32AxINC0 rising edge */ +#define T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300) /*!< T32AxINC0 trailing edge */ +#define T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400) /*!< T32AxINC1 rising edge */ +#define T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500) /*!< T32AxINC1 trailing edge */ +#define T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600) /*!< T32AxINC0 rising edge/trailing edge */ +#define T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) /*!< T32AxINC1 rising edge/trailing edge */ +/** + * @} + */ /* End of group T32A_PUP */ + +/** +* @defgroup T32A_NF T32A Noise Filter control +* @brief Noise Filter control NF Macro Definition. +* @{ +*/ +#define T32A_NF_NON ((uint32_t)0x00000000) /*!< Nothing */ +#define T32A_NF_2 ((uint32_t)0x00000010) /*!< Noise Filter less than 2/T0 */ +#define T32A_NF_4 ((uint32_t)0x00000020) /*!< Noise Filter less than 4/T0 */ +#define T32A_NF_8 ((uint32_t)0x00000030) /*!< Noise Filter less than 8/T0 */ +/** + * @} + */ /* End of group T32A_NF */ + +/** + * @defgroup T32A_PDIR T32A Phase 2 Pulse Direction control + * @brief Phase 2 Pulse Direction control PDIR Macro Definition. + * @{ + */ +#define T32A_PDIR_FORWARD ((uint32_t)0x00000000) /*!< forward */ +#define T32A_PDIR_BACKWARD ((uint32_t)0x00000002) /*!< backward */ +/** + * @} + */ /* End of group T32A_PDIR */ + +/** + * @defgroup T32A_PMODE T32A Pulse Count Mode control + * @brief Pulse Count Mode control PDIR Macro Definition. + * @{ + */ +#define T32A_PMODE_PHASE_2 ((uint32_t)0x00000000) /*!< Phase 2 Pulse Counter Mode */ +#define T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) /*!< Phase 1 Pulse Counter Mode */ +/** + * @} + */ /* End of group T32A_PMODE */ + +/** + * @} + */ /* End of group T32A_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup T32A_Exported_Typedef T32A Exported Typedef + * @{ + */ + +/** + * @enum t32_type_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_TIMERA = 0, /*!< 0: Timer A */ + T32A_TIMERB, /*!< 1: Timer B */ + T32A_TIMERC, /*!< 2: Timer C */ + T32A_TIMERMAX, +} t32_type_t; + +/** + * @enum t32_regnum_t + * @brief Use of Timer register number. + */ +typedef enum { + T32A_REG0 = 0, /*!< 0: Register 0 */ + T32A_REG1, /*!< 1: Register 1 */ + T32A_RELOAD, /*!< 2: Reload Register */ +} t32_regnum_t; +/** + * @enum t32_mode_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_MATCH = 0, /*!< 0: compare match detection 0 */ + T32A_OVERFLOW, /*!< 1: Overfloe detection */ + T32A_UNDERFLOW, /*!< 2: Underflow detection */ + T32A_CAPTURE0, /*!< 3: Capture 0 */ + T32A_CAPTURE1, /*!< 4: Capture 0 */ +} t32_mode_t; + +/** + * @enum t32_triger_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_INTRG = 0, /*!< 0: internal triger */ + T32A_TIM_RISING_EDGE, /*!< 1: Same Channel other timer rising edge */ + T32A_TIM_TRAILING_EDGE, /*!< 2: Same Channel other timer trailing edge */ + T32A_EXTTRG_RISING_EDGE, /*!< 3: external triger rising edge */ + T32A_EXTTRG_TRAILING_EDGE, /*!< 4: external triger trailing edge */ +} t32_triger_t; +/** + * @} + */ /* End of group T32A_Exported_Typedef */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Exported_Typedef T32A Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct t32a_mode_t + * @brief TimerA Mode Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t halt; /*!< T32A Debug HALT Control. + : Use @ref T32A_HALT */ + uint32_t mode; /*!< T32A 16bit/32bit MODE . + : Use @ref T32A_MODE32 */ +} t32a_mode_t; + +/*----------------------------------*/ +/** + * @struct t32a_runx_t + * @brief TimerA Run Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t runflg; /*!< TimerA Run Control Flag. + : Use @ref T32A_RUNFLGx */ + uint32_t sftstp; /*!< SW Counter STOP Control. + : Use @ref T32A_SFTSTPx */ + uint32_t sftsta; /*!< SW Counter START Control. + : Use @ref T32A_SFTSTAx */ + uint32_t run; /*!< TimerA Run Control. + : Use @ref T32A_RUNx */ +} t32a_runx_t; + +/*----------------------------------*/ +/** + * @struct t32a_crx_t + * @brief Counter Register Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t prscl; /*!< T32A PRESCALER Control. + : Use @ref T32A_PRSCLx */ + uint32_t clk; /*!< T32A COLCK Control. + : Use @ref T32A_CLKx */ + uint32_t wbf; /*!< T32A Double Buffer Disable/Enable Control. + : Use @ref T32A_WBFx */ + uint32_t updn; /*!< T32A Counter Up/Down Control. + : Use @ref T32A_UPDNx */ + uint32_t reld; /*!< T32A Counter Reload Control. + : Use @ref T32A_RELDx */ + uint32_t stop; /*!< T32A Counter Stop Control. + : Use @ref T32A_STOPx */ + uint32_t start; /*!< T32A Counter Start Controlc. + : Use @ref T32A_STARTx */ +} t32a_crx_t; + +/*----------------------------------*/ +/** + * @struct t32a_outcrx0_t + * @brief TimerA Output Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ocr; /*!< T32AxOUTA Control. + : Use @ref T32A_OCRx */ +} t32a_outcrx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_outcrx1_t + * @brief T32AxOUTA Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ocrcap1; /*!< T32AxOUTA Control of T32AxCAPx1 T32AxRGx1. + : Use @ref T32A_OCRCAPx1 */ + uint32_t ocrcap0; /*!< T32AxOUTA Control of T32AxCAPx0 T32AxRGx1. + : Use @ref T32A_OCRCAPx0 */ + uint32_t ocrcmp1; /*!< T32AxOUTA Control of T32AxRGx1 Counter Value + : Use @ref T32A_OCRCMPx1 */ + uint32_t ocrcmp0; /*!< T32AxOUTA Control of T32AxRGx0 Counter Value + : Use @ref T32A_OCRCMPx0 */ +} t32a_outcrx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_capcrx_t + * @brief Capture Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capmx1; /*!< T32A Capture Control Register x1. + : Use @ref T32A_CAPMx1 */ + uint32_t capmx0; /*!< T32A Capture Control Register A0. + : Use @ref T32A_CAPMx0 */ +} t32a_capcrx_t; + +/*----------------------------------*/ +/** + * @struct t32a_rgx0_t + * @brief T32A Timer Register x0 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t rgx0; /*!< T32A Timer Register x0. + : Use @ref T32A_RGx0 */ +} t32a_rgx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_rgx1_t + * @brief T32A Timer Register x1 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t rgx1; /*!< T32A Timer Register x1. + : Use @ref T32A_RGx1 */ +} t32a_rgx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_tmrx_t + * @brief T32A Counter Capture Register A Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tmrx; /*!< T32A Counter Capture Register x. + : Use @ref T32A_TMRx */ +} t32a_tmrx_t; + +/*----------------------------------*/ +/** + * @struct t32a_reldx_t + * @brief T32A Counter Reload Register Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t reld; /*!< T32A Counter Reload Register. + : Use @ref T32A_RELD */ +} t32a_reldx_t; + +/*----------------------------------*/ +/** + * @struct t32a_capx0_t + * @brief T32A Capture Register x0 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capx0; /*!< T32A Capture Register x0. + : Use @ref T32A_CAPx0 */ +} t32a_capx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_capx1_t + * @brief T32A Capture Register x0 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capx1; /*!< T32A Capture Register x1. + : Use @ref T32A_CAPx1 */ +} t32a_capx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_imx_t + * @brief Interrupt mask register Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t imsterr; /*!< T32A State Transition Err Interrupt Request MASK (Only use Timer C). + : Use @ref T32A_IMSTERR */ + uint32_t imuf; /*!< T32A Underflow Interrupt Request MASK. + : Use @ref T32A_IMUFx */ + uint32_t imof; /*!< T32A Underflow Interrupt Request MASK. + : Use @ref T32A_IMOFx */ + uint32_t imx1; /*!< T32A Match Up T32AxRGx1 Interrupt Request MASK. + : Use @ref T32A_IMx1 */ + uint32_t imx0; /*!< T32A Match Up T32AxRGx0 Interrupt Request MASK. + : Use @ref T32A_IMx0 */ +} t32a_imx_t; + +/*----------------------------------*/ +/** + * @struct t32a_stx_t + * @brief Status register structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intsterr; /*!< T32A State Transition Err Flag Status (Only use Timer C). + : Use @ref T32A_INTSTERR */ + uint32_t intuf; /*!< T32A Underflow Flag Status. + : Use @ref T32A_INTUFA */ + uint32_t intof; /*!< T32A Overflow Flag Status. + : Use @ref T32A_INTOFA */ + uint32_t intx1; /*!< T32A Match Up T32AxRGx1 Flag Status. + : Use @ref T32A_INTA1 */ + uint32_t intx0; /*!< T32A Match Up T32AxRGx0 Flag Status. + : Use @ref T32A_INTA0 */ +} t32a_stx_t; + +/*----------------------------------*/ +/** + * @struct t32a_dma_req_t + * @brief DMA Request register setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t dmaenx2; /*!< T32A DMA Converter1 Request control. + : Use @ref T32A_DMAENx2 */ + uint32_t dmaenx1; /*!< T32A DMA InputCapture1 Request control. + : Use @ref T32A_DMAENx1 */ + uint32_t dmaenx0; /*!< T32A DMA InputCapture0 Request control. + : Use @ref T32A_DMAENx0 */ +} t32a_dma_req_t; + +/*----------------------------------*/ +/** + * @struct t32a_pulse_cr_t + * @brief Pulse Count Control register setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t pdn; /*!< Pulse Mode Count Down Control. + : Use @ref T32A_PDN */ + uint32_t pup; /*!< Pulse Mode Count UP Control. + : Use @ref T32A_PUP */ + uint32_t nf; /*!< Noise Filter control. + : Use @ref T32A_NF */ + uint32_t pdir; /*!< Phase 2 Pulse Direction control. + : Use @ref T32A_PDIR */ + uint32_t pmode; /*!< Pulse Count Mode control. + : Use @ref T32A_PMODE */ +} t32a_pulse_cr_t; + +/*----------------------------------*/ +/** + * @struct t32a_cpx0_t + * @brief T32A Compare Register x0 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t crgx0; /*!< T32A Compare Register x0. + : Use @ref T32A_CRGx0 */ +} t32a_cpx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_cpx1_t + * @brief T32A Compare Register x1 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t crgx1; /*!< T32A Compare Register x1. + : Use @ref T32A_CRGx1 */ +} t32a_cpx1_t; + +/** + * @struct t32a_initial_setting_t + * @brief Initial Timer setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + t32a_runx_t runx; /*!< Timer Run Control Setting */ + t32a_crx_t crx; /*!< Counter Register Control Setting */ + t32a_outcrx0_t outcrx0; /*!< Timer Output Control Setting */ + t32a_outcrx1_t outcrx1; /*!< T32AxOUTx Control Setting */ + t32a_capcrx_t capcrx; /*!< Capture Control Setting */ + t32a_rgx0_t rgx0; /*!< T32A Timer Register x0 Setting */ + t32a_rgx1_t rgx1; /*!< T32A Timer Register x1 Setting */ + t32a_tmrx_t tmrx; /*!< T32A Counter Capture Register Setting */ + t32a_reldx_t reldx; /*!< T32A Counter Reload Register Setting */ + t32a_capx0_t capx0; /*!< T32A Capture Register x0 Setting */ + t32a_capx1_t capx1; /*!< T32A Capture Register x1 Setting */ + t32a_imx_t imx; /*!< Interrupt mask register Setting */ + t32a_dma_req_t dma_req; /*!< DMA Request register Setting */ + t32a_pulse_cr_t pls_cr; /*!< Pulse Count Control Register Setting (Only use Timer C) */ + t32a_cpx0_t crgx0; /*!< T32A Compare Register x0 Setting */ + t32a_cpx1_t crgx1; /*!< T32A Compare Register x1 Setting */ + void (*handler_T)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Event handler. */ + void (*handler_TC0)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap0 Event handler. */ + void (*handler_TC1)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap1 Event handler. */ +} t32a_initial_setting_t; + +/** + * @struct t32a_initial_mode_t + * @brief Initial Mode setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + t32a_mode_t mode; /*!< Timer Mode Setting */ +} t32a_initial_mode_t; + + +/*----------------------------------*/ +/** + * @brief T32A handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct t32a_handle { + TSB_T32A_TypeDef *p_instance; /*!< Registers base address. */ + t32a_initial_mode_t init_mode; /*!< Timer Mode Initial Setting */ + t32a_initial_setting_t init[T32A_TIMERMAX]; /*!< Initial setting. */ +} t32a_t; + +/** @} */ +/* End of group T32A_Exported_Types */ +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Exported_functions T32A Exported Functions + * @{ + */ +TXZ_Result t32a_mode_init(t32a_t *p_obj); +TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value); +TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val); +TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type); +void t32a_timer_IRQHandler(t32a_t *p_obj); +void t32a_timer_cap0_IRQHandler(t32a_t *p_obj); +void t32a_timer_cap1_IRQHandler(t32a_t *p_obj); +TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl); +/** + * @} + */ /* End of group T32A_Exported_functions */ + +/** + * @} + */ /* End of group T32A */ + +/** + * @} + */ /* End of group Periph_Driver */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __T32A_H */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_tspi.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_tspi.h new file mode 100644 index 00000000000..182ec3bce7d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_tspi.h @@ -0,0 +1,1542 @@ +/** + ******************************************************************************* + * @file txzp_tspi.h + * @brief This file provides all the functions prototypes for TSPI driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __TSPI_H +#define __TSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup TSPI TSPI + * @brief TSPI Driver. + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_define TSPI Exported Define + * @{ + */ +/** + * @defgroup TSPI_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define TSPI_NULL ((void *)0) +/** + * @} + */ /* End of group TSPI_NullPointer */ + +/** + * @defgroup TSPI_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group TSPI_ParameterResult */ + +/** + * @defgroup TSPI_Result Result + * @brief TSPI Result Macro Definition. + * @{ + */ +#define TSPI_RESULT_SUCCESS (0) /*!< Success */ +#define TSPI_RESULT_FAILURE (-1) /*!< Failure */ +/** + * @} + */ /* End of group TSPI_Result */ + +/** + * @defgroup TSPI_SW_Reset SW Reset + * @brief Software Rest Macro Definition. + * @{ + */ +#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattarn 10 */ +#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattarn 01 */ +/** + * @} + */ /* End of group TSPI_SW_Reset */ + + +/** + * @defgroup TSPI_Enable TSPI Enable/Disable Control + * @brief Enable/Disable TSPIE Macro Definition. + * @{ + */ +#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Enable */ + +/** + * @defgroup TSPI_Infinite_Transfer Infinite_Transfer + * @brief Enable/Disable INF Macro Definition. + * @{ + */ +#define TSPI_INF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_INF_ENABLE ((uint32_t)0x00010000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Triger_Control Triger Control + * @brief Enable/Disable TRGEN Macro Definition. + * @{ + */ +#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Control Transmission Control + * @brief Enable/Disable TRXE Macro Definition. + * @{ + */ +#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */ +#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Mode Transmission Mode + * @brief TSPIIMS Mode Macro Definisiton. + * @{ + */ +#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */ +#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */ +/** + * @} + */ /* End of group TSPI_Transmission_Mode */ + + +/** + * @defgroup TSPI_Operation_Select Operation Select + * @brief Master/Slave MSTR Operation Macro Definisiton. + * @{ + */ +#define TSPI_MASTER_OPERATION ((uint32_t)0x00001000) /*!< MASTER MODE */ +#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */ +/** + * @} + */ /* End of group TSPI_Operation_Select */ + + +/** + * @defgroup TSPI_Transfer_Mode Transfer Mode + * @brief Transfer Mode TMMD Macro Definisiton. + * @{ + */ +#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */ +#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */ +#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */ +#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */ +/** + * @} + */ /* End of group TSPI_Transfer_Mode */ + + +/** + * @defgroup TSPI_CSSEL_Select CSSEL Select + * @brief TSPIIxCS0/1/2/3 Select Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */ +#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */ +#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */ +#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */ +/** + * @} + */ /* End of group TSPI_CSSEL_Select */ + +/** + * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range + * @brief Transfer Frame Range Macro Definisiton. + * @{ + */ +#define TSPI_TRANS_RANGE_CONTINUE ((uint32_t)0x00000000) /*!< Continue Transfer Frame :0 */ +#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */ +/** + * @} + */ /* End of group TSPI_Transfer_Frame_Range */ +/** + * @defgroup TSPI_IDLE_Output_value IDLE Output Value + * @brief IDLE time Output Value TIDLE Macro Definisiton. + * @{ + */ +#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */ +#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */ +#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */ +#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_IDLE_Output_value */ + +/** + * @defgroup TSPI_RXDLY_value RXDLY Value + * @brief IDLE time Output Value TIDLE Macro Definisiton. + * @{ + */ +#define TSPI_RXDLY_FSYS_FSCK_2 ((uint32_t)0x00000000) /*!< fsys / fsck = 2 */ +#define TSPI_RXDLY_FSYS_FSCK_4 ((uint32_t)0x00010000) /*!< fsys / fsck = 4 */ +#define TSPI_RXDLY_FSYS_FSCK_6 ((uint32_t)0x00020000) /*!< fsys / fsck = 6 */ +#define TSPI_RXDLY_FSYS_FSCK_8 ((uint32_t)0x00030000) /*!< fsys / fsck = 8 */ +#define TSPI_RXDLY_FSYS_FSCK_10 ((uint32_t)0x00040000) /*!< fsys / fsck = 10 */ +#define TSPI_RXDLY_FSYS_FSCK_12 ((uint32_t)0x00050000) /*!< fsys / fsck = 12 */ +#define TSPI_RXDLY_FSYS_FSCK_14 ((uint32_t)0x00060000) /*!< fsys / fsck = 14 */ +#define TSPI_RXDLY_FSYS_FSCK_16 ((uint32_t)0x00070000) /*!< fsys / fsck >= 16 */ +#define TSPI_RXDLY_FSYS_FSCK_MASK ((uint32_t)0x00070000) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_RXDLY_value*/ + + +/** +* @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value +* @brief In case of Under Run Output Value TXDEMP Macro Definisiton. +* @{ +*/ +#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */ +#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_Underrun_Output_value */ + + +/** + * @defgroup TSPI_TxFillLevel Tx Fill Level + * @brief Transmit Fill Level Macro Definisiton. + * @{ + */ +#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */ +#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */ +#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */ +#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */ +#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */ +#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */ +#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */ +#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */ +/*! + * @} + */ /* End of group TSPI_TxFillLevel */ + + +/** + * @defgroup TSPI_RxFillLevel Rx Fill Level + * @brief Receive Fill Level Macro Definisiton. + * @{ + */ +#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 8 */ +#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */ +#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */ +#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */ +#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */ +#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */ +#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */ +#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */ +#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000700) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_RxFillLevel */ + + +/** + * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrpt + * @brief Enable/Disable Transmit FIFO Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterrupt */ + + +/** + * @defgroup TSPI_TxInterrupt Tx Interrpt + * @brief Enable/Disable Transmit Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxInterrupt */ + + +/** + * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrpt + * @brief Enable/Disable Receive FIFO Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterrupt */ + + +/** + * @defgroup TSPI_RxInterrupt Rx Interrpt + * @brief Enable/Disable Receive Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxInterrupt */ + + +/** + * @defgroup TSPI_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ErrorInterrupt */ + + +/** + * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt + * @brief Enable/Disable Transmit DMA Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */ +#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxDMAInterrupt */ + + +/** + * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt + * @brief Enable/Disable Receive DMA Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */ +#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxDMAInterrupt */ + + +/** + * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear + * @brief Tx Buffer Clear Macro Definisiton. + * @{ + */ +#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Tx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear + * @brief Rx Buffer Clear Macro Definisiton. + * @{ + */ +#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Rx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock + * @brief Baudrate Input Clock Macro Definisiton. + * @{ + */ +#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */ +#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */ +#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */ +#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */ +#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */ +#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */ +#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */ +#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */ +#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */ +#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Clock */ + + +/** + * @defgroup TSPI_Baudrate_Divider Baudrate Divider + * @brief Baudrate IDivider Macro Definisiton. + * @{ + */ +#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */ +#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */ +#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */ +#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */ +#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */ +#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */ +#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */ +#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */ +#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */ +#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */ +#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */ +#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */ +#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */ +#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */ +#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */ +#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Divider */ + + +/** + * @defgroup TSPI_DataDirection Data Direction + * @brief Data Direction Macro Definisiton. + * @{ + */ +#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */ +/*! + * @} + */ /* End of group TSPI_DataDirection */ + + +/** + * @defgroup TSPI_DataLength Data Length + * @brief Data Length Macro Definisiton. + * @{ + */ +#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */ +#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */ +#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */ +#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */ +#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */ +#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */ +#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */ +#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */ +#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */ +#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */ +#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */ +#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */ +#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */ +#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */ +#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */ +#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */ +#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */ +#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */ +#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */ +#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */ +#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */ +#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */ +#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */ +#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */ +#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */ +#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */ +/** + * @} + */ /* End of group TSPI_DataLength */ + + +/** + * @defgroup TSPI_Frame_Interval_Time Frame Interval time + * @brief Frame Interval time Macro Definisiton. + * @{ + */ +#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Frame_Interval_Time */ + + +/** + * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity + * @brief TSPIxCS3 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS3_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity + * @brief TSPIxCS2 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS2_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity + * @brief TSPIxCS1 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS1_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity + * @brief TSPIxCS0 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS0_Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity + * @brief Serial Clock Polarity Macro Definisiton. + * @{ + */ +#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */ +#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */ +/** + * @} + */ /* End of group Serial Clock Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity + * @brief Serial Clock IDLE Polarity Macro Definisiton. + * @{ + */ +#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */ +#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */ + + +/** + * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time + * @brief Minimum IDLE Time Macro Definisiton. + * @{ + */ +#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Minimum_IDLE_Time */ + + +/** + * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay + * @brief Serial Clock Delay Macro Definisiton. + * @{ + */ +#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_Delay */ + + +/** + * @defgroup TSPI_Negate_Delay Negate Delay + * @brief Negate Delay Macro Definisiton. + * @{ + */ +#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */ +#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */ +#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */ +#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */ +#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */ +#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */ +#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */ +#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */ +#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */ +#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */ +#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */ +#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */ +#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */ +#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */ +#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Negate_Delay */ + + +/** + * @defgroup TSPI_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definisiton. + * @{ + */ +#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ParityEnable */ + + +/** + * @defgroup TSPI_ParityBit Parity Bit + * @brief Parity Bit Macro Definisiton. + * @{ + */ +#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */ +/** + * @} + */ /* End of group TSPI_ParityBit */ + +/** + * @defgroup TSPI_Sectcr0 Sect Bit + * @brief Sectcr0 Macro Definisiton. + * @{ + */ +#define TSPI_SECTCR0_SECT_FRAME_MODE ((uint32_t)0x00000000) /*!< Frame Mode */ +#define TSPI_SECTCR0_SECT_SECTOR_MODE ((uint32_t)0x00000001) /*!< Sector mode */ +/** + * @} + */ /* End of group TSPI_Sectcr0 */ + +/** +* @defgroup TSPI_Sectcr1 Sectl3 Bit length setting +* @brief Sectcr1 Macro Definisiton. +* @{ +*/ +#define TSPI_SECTCR1_SECTL3_0 ((uint32_t)0x00000000) /*!< Sectl3 Bit length 0 */ +#define TSPI_SECTCR1_SECTL3_1 ((uint32_t)0x01000000) /*!< Sectl3 Bit length 1 */ +#define TSPI_SECTCR1_SECTL3_2 ((uint32_t)0x02000000) /*!< Sectl3 Bit length 2 */ +#define TSPI_SECTCR1_SECTL3_3 ((uint32_t)0x03000000) /*!< Sectl3 Bit length 3 */ +#define TSPI_SECTCR1_SECTL3_4 ((uint32_t)0x04000000) /*!< Sectl3 Bit length 4 */ +#define TSPI_SECTCR1_SECTL3_5 ((uint32_t)0x05000000) /*!< Sectl3 Bit length 5 */ +#define TSPI_SECTCR1_SECTL3_6 ((uint32_t)0x06000000) /*!< Sectl3 Bit length 6 */ +#define TSPI_SECTCR1_SECTL3_7 ((uint32_t)0x07000000) /*!< Sectl3 Bit length 7 */ +#define TSPI_SECTCR1_SECTL3_8 ((uint32_t)0x08000000) /*!< Sectl3 Bit length 8 */ +#define TSPI_SECTCR1_SECTL3_9 ((uint32_t)0x09000000) /*!< Sectl3 Bit length 9 */ +#define TSPI_SECTCR1_SECTL3_10 ((uint32_t)0x0a000000) /*!< Sectl3 Bit length 10 */ +#define TSPI_SECTCR1_SECTL3_11 ((uint32_t)0x0b000000) /*!< Sectl3 Bit length 11 */ +#define TSPI_SECTCR1_SECTL3_12 ((uint32_t)0x0c000000) /*!< Sectl3 Bit length 12 */ +#define TSPI_SECTCR1_SECTL3_13 ((uint32_t)0x0d000000) /*!< Sectl3 Bit length 13 */ +#define TSPI_SECTCR1_SECTL3_14 ((uint32_t)0x0e000000) /*!< Sectl3 Bit length 14 */ +#define TSPI_SECTCR1_SECTL3_15 ((uint32_t)0x0f000000) /*!< Sectl3 Bit length 15 */ +#define TSPI_SECTCR1_SECTL3_16 ((uint32_t)0x10000000) /*!< Sectl3 Bit length 16 */ +#define TSPI_SECTCR1_SECTL3_17 ((uint32_t)0x11000000) /*!< Sectl3 Bit length 17 */ +#define TSPI_SECTCR1_SECTL3_18 ((uint32_t)0x12000000) /*!< Sectl3 Bit length 18 */ +#define TSPI_SECTCR1_SECTL3_19 ((uint32_t)0x13000000) /*!< Sectl3 Bit length 19 */ +#define TSPI_SECTCR1_SECTL3_20 ((uint32_t)0x14000000) /*!< Sectl3 Bit length 20 */ +#define TSPI_SECTCR1_SECTL3_21 ((uint32_t)0x15000000) /*!< Sectl3 Bit length 21 */ +#define TSPI_SECTCR1_SECTL3_22 ((uint32_t)0x16000000) /*!< Sectl3 Bit length 22 */ +#define TSPI_SECTCR1_SECTL3_23 ((uint32_t)0x17000000) /*!< Sectl3 Bit length 23 */ +#define TSPI_SECTCR1_SECTL3_24 ((uint32_t)0x18000000) /*!< Sectl3 Bit length 24 */ +#define TSPI_SECTCR1_SECTL3_25 ((uint32_t)0x19000000) /*!< Sectl3 Bit length 25 */ +#define TSPI_SECTCR1_SECTL3_26 ((uint32_t)0x1a000000) /*!< Sectl3 Bit length 26 */ +#define TSPI_SECTCR1_SECTL3_27 ((uint32_t)0x1b000000) /*!< Sectl3 Bit length 27 */ +#define TSPI_SECTCR1_SECTL3_28 ((uint32_t)0x1c000000) /*!< Sectl3 Bit length 28 */ +#define TSPI_SECTCR1_SECTL3_29 ((uint32_t)0x1d000000) /*!< Sectl3 Bit length 29 */ +#define TSPI_SECTCR1_SECTL3_30 ((uint32_t)0x1e000000) /*!< Sectl3 Bit length 30 */ +#define TSPI_SECTCR1_SECTL3_31 ((uint32_t)0x1f000000) /*!< Sectl3 Bit length 31 */ +#define TSPI_SECTCR1_SECTL3_32 ((uint32_t)0x20000000) /*!< Sectl3 Bit length 32 */ +#define TSPI_SECTCR1_SECTL3_MASK ((uint32_t)0x3f000000) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_Sectcr1 Sectl3 */ + +/** +* @defgroup TSPI_Sectcr1 Sectl2 Bit length setting +* @brief Sectcr1 Macro Definisiton. +* @{ +*/ +#define TSPI_SECTCR1_SECTL2_0 ((uint32_t)0x00000000) /*!< Sectl2 Bit length 0 */ +#define TSPI_SECTCR1_SECTL2_1 ((uint32_t)0x00010000) /*!< Sectl2 Bit length 1 */ +#define TSPI_SECTCR1_SECTL2_2 ((uint32_t)0x00020000) /*!< Sectl2 Bit length 2 */ +#define TSPI_SECTCR1_SECTL2_3 ((uint32_t)0x00030000) /*!< Sectl2 Bit length 3 */ +#define TSPI_SECTCR1_SECTL2_4 ((uint32_t)0x00040000) /*!< Sectl2 Bit length 4 */ +#define TSPI_SECTCR1_SECTL2_5 ((uint32_t)0x00050000) /*!< Sectl2 Bit length 5 */ +#define TSPI_SECTCR1_SECTL2_6 ((uint32_t)0x00060000) /*!< Sectl2 Bit length 6 */ +#define TSPI_SECTCR1_SECTL2_7 ((uint32_t)0x00070000) /*!< Sectl2 Bit length 7 */ +#define TSPI_SECTCR1_SECTL2_8 ((uint32_t)0x00080000) /*!< Sectl2 Bit length 8 */ +#define TSPI_SECTCR1_SECTL2_9 ((uint32_t)0x00090000) /*!< Sectl2 Bit length 9 */ +#define TSPI_SECTCR1_SECTL2_10 ((uint32_t)0x000a0000) /*!< Sectl2 Bit length 10 */ +#define TSPI_SECTCR1_SECTL2_11 ((uint32_t)0x000b0000) /*!< Sectl2 Bit length 11 */ +#define TSPI_SECTCR1_SECTL2_12 ((uint32_t)0x000c0000) /*!< Sectl2 Bit length 12 */ +#define TSPI_SECTCR1_SECTL2_13 ((uint32_t)0x000d0000) /*!< Sectl2 Bit length 13 */ +#define TSPI_SECTCR1_SECTL2_14 ((uint32_t)0x000e0000) /*!< Sectl2 Bit length 14 */ +#define TSPI_SECTCR1_SECTL2_15 ((uint32_t)0x000f0000) /*!< Sectl2 Bit length 15 */ +#define TSPI_SECTCR1_SECTL2_16 ((uint32_t)0x00100000) /*!< Sectl2 Bit length 16 */ +#define TSPI_SECTCR1_SECTL2_17 ((uint32_t)0x00110000) /*!< Sectl2 Bit length 17 */ +#define TSPI_SECTCR1_SECTL2_18 ((uint32_t)0x00120000) /*!< Sectl2 Bit length 18 */ +#define TSPI_SECTCR1_SECTL2_19 ((uint32_t)0x00130000) /*!< Sectl2 Bit length 19 */ +#define TSPI_SECTCR1_SECTL2_20 ((uint32_t)0x00140000) /*!< Sectl2 Bit length 20 */ +#define TSPI_SECTCR1_SECTL2_21 ((uint32_t)0x00150000) /*!< Sectl2 Bit length 21 */ +#define TSPI_SECTCR1_SECTL2_22 ((uint32_t)0x00160000) /*!< Sectl2 Bit length 22 */ +#define TSPI_SECTCR1_SECTL2_23 ((uint32_t)0x00170000) /*!< Sectl2 Bit length 23 */ +#define TSPI_SECTCR1_SECTL2_24 ((uint32_t)0x00180000) /*!< Sectl2 Bit length 24 */ +#define TSPI_SECTCR1_SECTL2_25 ((uint32_t)0x00190000) /*!< Sectl2 Bit length 25 */ +#define TSPI_SECTCR1_SECTL2_26 ((uint32_t)0x001a0000) /*!< Sectl2 Bit length 26 */ +#define TSPI_SECTCR1_SECTL2_27 ((uint32_t)0x001b0000) /*!< Sectl2 Bit length 27 */ +#define TSPI_SECTCR1_SECTL2_28 ((uint32_t)0x001c0000) /*!< Sectl2 Bit length 28 */ +#define TSPI_SECTCR1_SECTL2_29 ((uint32_t)0x001d0000) /*!< Sectl2 Bit length 29 */ +#define TSPI_SECTCR1_SECTL2_30 ((uint32_t)0x001e0000) /*!< Sectl2 Bit length 30 */ +#define TSPI_SECTCR1_SECTL2_31 ((uint32_t)0x001f0000) /*!< Sectl2 Bit length 31 */ +#define TSPI_SECTCR1_SECTL2_32 ((uint32_t)0x00200000) /*!< Sectl2 Bit length 32 */ +#define TSPI_SECTCR1_SECTL2_MASK ((uint32_t)0x003f0000) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_Sectcr1 Sectl2 */ + +/** +* @defgroup TSPI_Sectcr1 Sectl1 Bit length setting +* @brief Sectcr1 Macro Definisiton. +* @{ +*/ +#define TSPI_SECTCR1_SECTL1_1 ((uint32_t)0x00000100) /*!< Sectl1 Bit length 1 */ +#define TSPI_SECTCR1_SECTL1_2 ((uint32_t)0x00000200) /*!< Sectl1 Bit length 2 */ +#define TSPI_SECTCR1_SECTL1_3 ((uint32_t)0x00000300) /*!< Sectl1 Bit length 3 */ +#define TSPI_SECTCR1_SECTL1_4 ((uint32_t)0x00000400) /*!< Sectl1 Bit length 4 */ +#define TSPI_SECTCR1_SECTL1_5 ((uint32_t)0x00000500) /*!< Sectl1 Bit length 5 */ +#define TSPI_SECTCR1_SECTL1_6 ((uint32_t)0x00000600) /*!< Sectl1 Bit length 6 */ +#define TSPI_SECTCR1_SECTL1_7 ((uint32_t)0x00000700) /*!< Sectl1 Bit length 7 */ +#define TSPI_SECTCR1_SECTL1_8 ((uint32_t)0x00000800) /*!< Sectl1 Bit length 8 */ +#define TSPI_SECTCR1_SECTL1_9 ((uint32_t)0x00000900) /*!< Sectl1 Bit length 9 */ +#define TSPI_SECTCR1_SECTL1_10 ((uint32_t)0x00000a00) /*!< Sectl1 Bit length 10 */ +#define TSPI_SECTCR1_SECTL1_11 ((uint32_t)0x00000b00) /*!< Sectl1 Bit length 11 */ +#define TSPI_SECTCR1_SECTL1_12 ((uint32_t)0x00000c00) /*!< Sectl1 Bit length 12 */ +#define TSPI_SECTCR1_SECTL1_13 ((uint32_t)0x00000d00) /*!< Sectl1 Bit length 13 */ +#define TSPI_SECTCR1_SECTL1_14 ((uint32_t)0x00000e00) /*!< Sectl1 Bit length 14 */ +#define TSPI_SECTCR1_SECTL1_15 ((uint32_t)0x00000f00) /*!< Sectl1 Bit length 15 */ +#define TSPI_SECTCR1_SECTL1_16 ((uint32_t)0x00001000) /*!< Sectl1 Bit length 16 */ +#define TSPI_SECTCR1_SECTL1_17 ((uint32_t)0x00001100) /*!< Sectl1 Bit length 17 */ +#define TSPI_SECTCR1_SECTL1_18 ((uint32_t)0x00001200) /*!< Sectl1 Bit length 18 */ +#define TSPI_SECTCR1_SECTL1_19 ((uint32_t)0x00001300) /*!< Sectl1 Bit length 19 */ +#define TSPI_SECTCR1_SECTL1_20 ((uint32_t)0x00001400) /*!< Sectl1 Bit length 20 */ +#define TSPI_SECTCR1_SECTL1_21 ((uint32_t)0x00001500) /*!< Sectl1 Bit length 21 */ +#define TSPI_SECTCR1_SECTL1_22 ((uint32_t)0x00001600) /*!< Sectl1 Bit length 22 */ +#define TSPI_SECTCR1_SECTL1_23 ((uint32_t)0x00001700) /*!< Sectl1 Bit length 23 */ +#define TSPI_SECTCR1_SECTL1_24 ((uint32_t)0x00001800) /*!< Sectl1 Bit length 24 */ +#define TSPI_SECTCR1_SECTL1_25 ((uint32_t)0x00001900) /*!< Sectl1 Bit length 25 */ +#define TSPI_SECTCR1_SECTL1_26 ((uint32_t)0x00001a00) /*!< Sectl1 Bit length 26 */ +#define TSPI_SECTCR1_SECTL1_27 ((uint32_t)0x00001b00) /*!< Sectl1 Bit length 27 */ +#define TSPI_SECTCR1_SECTL1_28 ((uint32_t)0x00001c00) /*!< Sectl1 Bit length 28 */ +#define TSPI_SECTCR1_SECTL1_29 ((uint32_t)0x00001d00) /*!< Sectl1 Bit length 29 */ +#define TSPI_SECTCR1_SECTL1_30 ((uint32_t)0x00001e00) /*!< Sectl1 Bit length 30 */ +#define TSPI_SECTCR1_SECTL1_31 ((uint32_t)0x00001f00) /*!< Sectl1 Bit length 31 */ +#define TSPI_SECTCR1_SECTL1_32 ((uint32_t)0x00002000) /*!< Sectl1 Bit length 32 */ +#define TSPI_SECTCR1_SECTL1_MASK ((uint32_t)0x00003f00) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_Sectcr1 Sectl1 */ + +/** +* @defgroup TSPI_Sectcr1 Sectl0 Bit length setting +* @brief Sectcr1 Macro Definisiton. +* @{ +*/ +#define TSPI_SECTCR1_SECTL0_1 ((uint32_t)0x00000001) /*!< Sectl0 Bit length 1 */ +#define TSPI_SECTCR1_SECTL0_2 ((uint32_t)0x00000002) /*!< Sectl0 Bit length 2 */ +#define TSPI_SECTCR1_SECTL0_3 ((uint32_t)0x00000003) /*!< Sectl0 Bit length 3 */ +#define TSPI_SECTCR1_SECTL0_4 ((uint32_t)0x00000004) /*!< Sectl0 Bit length 4 */ +#define TSPI_SECTCR1_SECTL0_5 ((uint32_t)0x00000005) /*!< Sectl0 Bit length 5 */ +#define TSPI_SECTCR1_SECTL0_6 ((uint32_t)0x00000006) /*!< Sectl0 Bit length 6 */ +#define TSPI_SECTCR1_SECTL0_7 ((uint32_t)0x00000007) /*!< Sectl0 Bit length 7 */ +#define TSPI_SECTCR1_SECTL0_8 ((uint32_t)0x00000008) /*!< Sectl0 Bit length 8 */ +#define TSPI_SECTCR1_SECTL0_9 ((uint32_t)0x00000009) /*!< Sectl0 Bit length 9 */ +#define TSPI_SECTCR1_SECTL0_10 ((uint32_t)0x0000000a) /*!< Sectl0 Bit length 10 */ +#define TSPI_SECTCR1_SECTL0_11 ((uint32_t)0x0000000b) /*!< Sectl0 Bit length 11 */ +#define TSPI_SECTCR1_SECTL0_12 ((uint32_t)0x0000000c) /*!< Sectl0 Bit length 12 */ +#define TSPI_SECTCR1_SECTL0_13 ((uint32_t)0x0000000d) /*!< Sectl0 Bit length 13 */ +#define TSPI_SECTCR1_SECTL0_14 ((uint32_t)0x0000000e) /*!< Sectl0 Bit length 14 */ +#define TSPI_SECTCR1_SECTL0_15 ((uint32_t)0x0000000f) /*!< Sectl0 Bit length 15 */ +#define TSPI_SECTCR1_SECTL0_16 ((uint32_t)0x00000010) /*!< Sectl0 Bit length 16 */ +#define TSPI_SECTCR1_SECTL0_17 ((uint32_t)0x00000011) /*!< Sectl0 Bit length 17 */ +#define TSPI_SECTCR1_SECTL0_18 ((uint32_t)0x00000012) /*!< Sectl0 Bit length 18 */ +#define TSPI_SECTCR1_SECTL0_19 ((uint32_t)0x00000013) /*!< Sectl0 Bit length 19 */ +#define TSPI_SECTCR1_SECTL0_20 ((uint32_t)0x00000014) /*!< Sectl0 Bit length 20 */ +#define TSPI_SECTCR1_SECTL0_21 ((uint32_t)0x00000015) /*!< Sectl0 Bit length 21 */ +#define TSPI_SECTCR1_SECTL0_22 ((uint32_t)0x00000016) /*!< Sectl0 Bit length 22 */ +#define TSPI_SECTCR1_SECTL0_23 ((uint32_t)0x00000017) /*!< Sectl0 Bit length 23 */ +#define TSPI_SECTCR1_SECTL0_24 ((uint32_t)0x00000018) /*!< Sectl0 Bit length 24 */ +#define TSPI_SECTCR1_SECTL0_25 ((uint32_t)0x00000019) /*!< Sectl0 Bit length 25 */ +#define TSPI_SECTCR1_SECTL0_26 ((uint32_t)0x0000001a) /*!< Sectl0 Bit length 26 */ +#define TSPI_SECTCR1_SECTL0_27 ((uint32_t)0x0000001b) /*!< Sectl0 Bit length 27 */ +#define TSPI_SECTCR1_SECTL0_28 ((uint32_t)0x0000001c) /*!< Sectl0 Bit length 28 */ +#define TSPI_SECTCR1_SECTL0_29 ((uint32_t)0x0000001d) /*!< Sectl0 Bit length 29 */ +#define TSPI_SECTCR1_SECTL0_30 ((uint32_t)0x0000001e) /*!< Sectl0 Bit length 30 */ +#define TSPI_SECTCR1_SECTL0_31 ((uint32_t)0x0000001f) /*!< Sectl0 Bit length 31 */ +#define TSPI_SECTCR1_SECTL0_32 ((uint32_t)0x00000020) /*!< Sectl0 Bit length 32 */ +#define TSPI_SECTCR1_SECTL0_MASK ((uint32_t)0x0000003f) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_Sectcr1 Sectl0 */ + +/** + * @defgroup TSPI_Status_Setting_flag Status Setting Flag + * @brief Enable/Disable Status Setting Flag Macro Definisiton. + * @{ + */ +#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group TSPI_Status_Setting_flag */ + + +/** + * @defgroup TSPI_TxState Transmitting State Flag + * @brief Transmitting State Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */ +#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_TxState */ + + +/** + * @defgroup TSPI_TxDone Transmitting Complete Flag + * @brief Transmitting Complete Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */ +#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */ +#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxDone */ + + +/** + * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrpt Flag + * @brief Transmitting FIFO Interrpt Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */ +#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag + * @brief Transmitting FIFO Empty Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_TxFIFOEmptyFlag */ + +/** + * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level + * @brief Current Transmitting FIFO Level Macro Definisiton. + * @{ + */ +#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */ +#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */ +#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */ +#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */ +#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */ +#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */ +#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */ +#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_TxReachFillLevel */ + + +/** + * @defgroup TSPI_RxState Receive State Flag + * @brief Receive State Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */ +#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_RxState */ + + +/** + * @defgroup TSPI_RxDone Receive Complete Flag + * @brief Receive Complete Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */ +#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */ +#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxDone */ + + +/** + * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrpt Flag + * @brief Rx FIFO Interrpt Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */ +#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag + * @brief Receiving FIFO Full Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_RxFIFOFullFlag */ + + +/** + * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level + * @brief Current Receive FIFO Level Macro Definisiton. + * @{ + */ +#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */ +#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */ +#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */ +#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */ +#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */ +#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */ +#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */ +#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_RxReachFillLevel */ + + +/** + * @defgroup TSPI_TRGErr Triger Error + * @brief Triger Error Macro Definisiton. + * @{ + */ +#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */ +#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_TRGErr */ + +/** + * @defgroup TSPI_UnderrunErr Underrun Error + * @brief Underrun Error Macro Definisiton. + * @{ + */ +#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */ +#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_UnderrunErr */ + +/** + * @defgroup TSPI_OverrunErr Overrun Error + * @brief Overrun Error Macro Definisiton. + * @{ + */ +#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */ +#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_OverrunErr */ + + +/** + * @defgroup TSPI_ParityErr Parity Error + * @brief Parity Error Macro Definisiton. + * @{ + */ +#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */ +#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_ParityErr */ + +/** +* @defgroup TSPI_Data_allign Data allign +* @brief Data allign Macro Definisiton. +* @{ +*/ +#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */ +#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */ +#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */ +/** + * @} + */ /* End of group TSPI_Data_allign */ + +/** +* @defgroup TSPI_FifoMax FIFO MAX +* @brief FIFO MAX LEVEL +* @{ +*/ +#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */ +/** + * @} + */ /* End of group TSPI_FifoMax */ + +/** +* @defgroup TSPI_ErrCode Error Code +* @brief Error Code Macro Definisiton. +* @{ +*/ +#define NOERROR ((uint32_t)0x00000000) /*!< no error */ +#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */ +#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */ +#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */ +#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */ +#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */ +#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */ +#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */ +#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */ +#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */ +#define INITERR ((uint32_t)0x000000) /*!< transmit mode error */ +/** +* @} + */ /* End of group TSPI_ErrCode */ + +/** +* @defgroup TSPI_Buffer_Size Receive Buffer size +* @brief Error Code Macro Definisiton. +* @{ +*/ +#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */ +/** +* @} + */ /* End of group TSPI_Buffer_Size */ +/** + * @} + */ /* End of group TSPI_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/* No define */ +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct tspi_receive8_t + * @brief Receive event information structure definenition. + * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive8_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive16_t + * @brief Receive event information structure definenition. + * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive16_t; + +/** + * @struct tspi_receive32_t + * @brief Receive event information structure definenition. + * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive32_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive_t + * @brief Receive event information structure definenition. +*/ +/*----------------------------------*/ +typedef union { + tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */ + tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */ + tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */ +} tspi_receive_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit8_t + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit8_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit16_t + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit16_t; +/*----------------------------------*/ +/** + * @struct tspi_transmit32_t + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit32_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit_t + * @brief Transmit data information structure definenition. +*/ +/*----------------------------------*/ +typedef union { + tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */ + tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */ + tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */ +} tspi_transmit_t; + +/*----------------------------------*/ +/** + * @struct tspi_control1_t + * @brief Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inf; /*!< INF Transmission Infinity Control. + : Use @ref TSPI_Infinity_Control */ + uint32_t trgen; /*!< TRGEN Transmission Triger Control. + : Use @ref TSPI_Triger_Control */ + uint32_t trxe; /*!< TRXE Transmission Control. + : Use @ref TSPI_Transmission_Control */ + uint32_t tspims; /*!< TSPI/SIO Transmission Mode. + : Use @ref TSPI_Transmission_Mode */ + uint32_t mstr; /*!< Master/Slave Operation Select. + : Use @ref TSPI_Operation_Select */ + uint32_t tmmd; /*!< Transfer Mode Select. + : Use @ref TSPI_Transfer_Mode */ + uint32_t cssel; /*!< CSSEL Select. + : Use @ref TSPI_CSSEL_Select */ + uint32_t fc; /*!< Transfer Frame Value. + : Range ( TSPI_TRANS_RANGE_CONTINUE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */ +} tspi_control1_t; + +/*----------------------------------*/ +/** + * @struct tspi_control2_t + * @brief Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tidle; /*!< IDLE Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t txdemp; /*!< Under Run Occur Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t rxdly; /*!< Fsys Select. + : Use @ref TSPI_RXDLY_value */ + uint32_t til; /*!< Transmit Fill Level. + : Use @ref TSPI_TxFillLevel */ + uint32_t ril; /*!< Receive Fill Level. + : Use @ref TSPI_RxFillLevel */ + uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt. + : Use @ref TSPI_TxFIFOInterrupt */ + uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt. + : Use @ref TSPI_TxInterrupt */ + uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt. + : Use @ref TSPI_RxFIFOInterrupt */ + uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt. + : Use @ref TSPI_RxInterrupt */ + uint32_t interr; /*!< Enable/Disable Error Interrupt. + : Use @ref TSPI_ErrorInterrupt */ + uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt. + : Use @ref TSPI_TxDMAInterrupt */ + uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt. + : Use @ref TSPI_RxDMAInterrupt */ +} tspi_control2_t; + +/*----------------------------------*/ +/** + * @struct tspi_control3_t + * @brief Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tfempclr; /*!< Transmit Buffer Clear. + : Use @ref TSPI_Tx_Buffer_Clear */ + uint32_t rffllclr; /*!< Receive Buffer Clear. + : Use @ref TSPI_Rx_Buffer_Clear */ +} tspi_control3_t; + +/*----------------------------------*/ +/** + * @struct tspi_baudrate_t + * @brief Clock setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t brck; /*!< Baudrate Input Clock. + : Use @ref TSPI_Baudrate_Clock */ + uint32_t brs; /*!< Baudrate Divider. + : Use @ref TSPI_Baudrate_Divider */ +} tspi_baudrate_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr0_t + * @brief Format control0. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t dir; /*!< Data Direction. + : Use @ref TSPI_DataDirection */ + uint32_t fl; /*!< Data Length. + : Use @ref TSPI_DataLength */ + uint32_t fint; /*!< Frame Interval time. + : Use @ref TSPI_Frame_Interval_Time */ + uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS3_Polarity */ + uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS2_Polarity */ + uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS1_Polarity */ + uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS0_Polarity */ + uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge. + : Use @ref TSPI_Serial_Clock_Polarity */ + uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low. + : Use @ref TSPI_Serial_Clock_IDLE_Polarity */ + uint32_t csint; /*!< Minimum IDLE Time. + : Use @ref TSPI_Minimum_IDLE_Time */ + uint32_t cssckdl; /*!< Serial Clock Delay. + : Use @ref TSPI_Serial_Clock_Delay */ + uint32_t sckcsdl; /*!< Negate Delay. + : Use @ref TSPI_Negate_Delay */ +} tspi_fmtr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr1_t + * @brief Format control1. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t reserved; /*!< SIO Slave MOde. + : */ + uint32_t vpe; /*!< Enable/Disable Parity Function. + : Use @ref TSPI_ParityEnable */ + uint32_t vpm; /*!< Odd/Even Parity Bit. + : Use @ref TSPI_ParityBit */ +} tspi_fmtr1_t; + +/*----------------------------------*/ +/** + * @struct tspi_sectcr0_t + * @brief Sector Mode Control0 setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sect; /*!< Sector Mode Setting Bit. + : Use @ref TSPI_Mode Setting Bit */ +} tspi_sectcr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_sectcr1_t + * @brief Sector Mode Control0 setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sectl3; /*!< Sector3 Bit length setting + : Use @ref TSPI_Sector3 Bit length setting */ + uint32_t sectl2; /*!< Sector3 Bit length setting + : Use @ref TSPI_Sector2 Bit length setting */ + uint32_t sectl1; /*!< Sector3 Bit length setting + : Use @ref TSPI_Sector1 Bit length setting */ + uint32_t sectl0; /*!< Sector3 Bit length setting + : Use @ref TSPI_Sector1 Bit length setting */ +} tspi_sectcr1_t; +/*----------------------------------*/ +/** + * @struct tspi_status_t + * @brief Status register. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tspisue; /*!< Enable/Disable Status Setting Flag. + : Use @ref TSPI_Status_Setting_flag */ + uint32_t txrun; /*!< Stop/Active Tx Active Flag. + : Use @ref TSPI_TxState */ + uint32_t txend; /*!< Tx Data Send Complete Flag. + : Use @ref TSPI_TxDone */ + uint32_t inttxwf; /*!< Tx FIFO Interrpt Flag. + : Use @ref TSPI_TxFIFOInterruptFlag */ + uint32_t tfemp; /*!< Tx FIFO Empty Flag. + : Use @ref TSPI_TxFIFOEmptyFlag */ + uint32_t tlvll; /*!< Tx Reach Fill Level + : Use @ref TSPI_TxReachFillLevel */ + uint32_t rxrun; /*!< Stop/Active Rx Active Flag. + : Use @ref TSPI_RxState */ + uint32_t rxend; /*!< Rx Data Receive Complete Flag. + : Use @ref TSPI_RxDone */ + uint32_t intrxff; /*!< Rx FIFO Interrpt Flag + : Use @ref TSPI_RxFIFOInterruptFlag */ + uint32_t rffll; /*!< Rx FIFO Full Flag + : Use @ref TSPI_RxFIFOFullFlag */ + uint32_t rlvl; /*!< Rx Reach Fill Level + : Use @ref TSPI_RxReachFillLevel */ +} tspi_status_t; + +/*----------------------------------*/ +/** + * @struct tspi_error_t + * @brief Error flag. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t udrerr; /*!< Underrun Error. + : Use @ref TSPI_UnderrunErr */ + uint32_t ovrerr; /*!< Overrun Error. + : Use @ref TSPI_OverrunErr */ + uint32_t perr; /*!< Parity Error. + : Use @ref TSPI_ParityErr */ +} tspi_error_t; + + +/*----------------------------------*/ +/** + * @struct tspi_initial_setting_t + * @brief Initial setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + tspi_control1_t cnt1; /*!< Control1 setting. + : Use @ref tspi_control1_t */ + tspi_control2_t cnt2; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_control3_t cnt3; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_baudrate_t brd; /*!< Baudrate setting. + : Use @ref tspi_baudrate_t */ + tspi_fmtr0_t fmr0; /*!< Format control0 setting. + : Use @ref tspi_fmtr0_t */ + tspi_fmtr1_t fmr1; /*!< Format control1 setting. + : Use @ref tspi_fmtr1_t */ + tspi_sectcr0_t sectcr0; /*!< Sector Mode Control0 setting. + : Use @ref tspi_sectcr0_t */ + tspi_sectcr1_t sectcr1; /*!< Sector Mode Control1 setting. + : Use @ref tspi_sectcr1_t */ +} tspi_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief TSPI handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct tspi_handle { + TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */ + tspi_initial_setting_t init; /*!< Initial setting. */ + uint32_t errcode; /*!< ErrorCode */ + /*------------------------------------------*/ + /*! + @brief Transmit Informatin. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmited data. */ + tspi_transmit_t info; /*!< Transmit Data Information. */ + uint8_t tx_allign; /*!< Transmit Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Informatin. + */ + /*------------------------------------------*/ + struct { + tspi_receive_t info; /*!< Receive Data Information. */ + uint8_t rx_allign; /*!< Receive Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} tspi_t; +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_functions TSPI Exported Functions + * @{ + */ +TXZ_Result tspi_init(tspi_t *p_obj); +TXZ_Result tspi_deinit(tspi_t *p_obj); +TXZ_Result tspi_format(tspi_t *p_obj); +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info); +void tspi_irq_handler_transmit(tspi_t *p_obj); +void tspi_irq_handler_receive(tspi_t *p_obj); +void tspi_error_irq_handler(tspi_t *p_obj); +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status); +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error); +TXZ_Result tspi_error_clear(tspi_t *p_obj); +TXZ_Result tspi_discard_transmit(tspi_t *p_obj); +TXZ_Result tspi_discard_receive(tspi_t *p_obj); +/** + * @} + */ /* End of group TSPI_Exported_functions */ +/** + * @} + */ /* End of group TSPI */ +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TSPI_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart.h new file mode 100644 index 00000000000..14e1ab5912d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart.h @@ -0,0 +1,810 @@ +/** + ******************************************************************************* + * @file txzp_uart.h + * @brief This file provides all the functions prototypes for UART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __UART_H +#define __UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup UART UART + * @brief UART Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_define UART Exported Define + * @{ + */ + +/** + * @defgroup UART_FifoMax Max Num of FIFO + * @brief Max Num of Tx/Rx Fifo. + * @{ + */ +#define UART_TX_FIFO_MAX ((uint32_t)0x00000008) /*!< TX FIFO Max. */ +#define UART_RX_FIFO_MAX ((uint32_t)0x00000008) /*!< RX FIFO Max. */ +/** + * @} + */ /* End of group UART_FifoMax */ + +/** + * @defgroup UART_HalfClockSelect Half Clock Select + * @brief Output Terminal Select + * @{ + */ +#define UART_HALF_CLOCK_UTxTXDA ((uint32_t)0x00000000) /*!< Half Clock output terminal select UTxTXDA. */ +#define UART_HALF_CLOCK_UTxTXDB ((uint32_t)0x00040000) /*!< Half Clock output terminal select UTxTXDB. */ +/** + * @} + */ /* End of group UART_HalfClockSelect */ + +/** + * @defgroup UART_HalfClockMode Half Clock Mode + * @brief Half Clock Mode Setting. + * @{ + */ +#define UART_HALF_CLOCK_MODE_1 ((uint32_t)0x00000000) /*!< Half Clock 1 terminal Mode. */ +#define UART_HALF_CLOCK_MODE_2 ((uint32_t)0x00020000) /*!< Half Clock 2 terminal Mode. */ +/** + * @} + */ /* End of group UART_HalfClockMode */ + +/** + * @defgroup UART_HalfClockCTR Half Clock Mode Control + * @brief Half Clock Control. + * @{ + */ +#define UART_HALF_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< Half Clock Mode Disable. */ +#define UART_HALF_CLOCK_ENABLE ((uint32_t)0x00010000) /*!< Half Clock Mode Enable. */ +/** + * @} + */ /* End of group UART_HalfClockCTR */ + +/** + * @defgroup UART_LoopBack Loop Back Function + * @brief Half Clock Control. + * @{ + */ +#define UART_LOOPBACK_DISABLE ((uint32_t)0x00000000) /*!< Loop Back Function Disable. */ +#define UART_LOOPBACK_ENABLE ((uint32_t)0x00008000) /*!< Loop Back Function Enable. */ +/** + * @} + */ /* End of group UART_LoopBack */ + + +/** + * @defgroup UART_NoiseFilter Noise Filter + * @brief Noise Filter Setting. + * @{ + */ +#define UART_NOISE_FILTER_NON ((uint32_t)0x00000000) /*!< No Filetering. */ +#define UART_NOISE_FILTER_2_T0 ((uint32_t)0x00001000) /*!< A signal below the 2/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_4_T0 ((uint32_t)0x00002000) /*!< A signal below the 4/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_8_T0 ((uint32_t)0x00003000) /*!< A signal below the 8/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_2_CLOCK ((uint32_t)0x00004000) /*!< A signal below the 2/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_3_CLOCK ((uint32_t)0x00005000) /*!< A signal below the 3/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_4_CLOCK ((uint32_t)0x00006000) /*!< A signal below the 4/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_5_CLOCK ((uint32_t)0x00007000) /*!< A signal below the 5/Clock is filtering as noise */ +/** + * @} + */ /* End of group UART_NoiseFilter */ + + +/** + * @defgroup UART_CTSHandshake CTS Handshake + * @brief Available CTS Handshake Macro Definisiton. + * @{ + */ +#define UART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_CTS_ENABLE ((uint32_t)0x00000400) /*!< Available. */ +/** + * @} + */ /* End of group UART_CTSHandshake */ + + +/** + * @defgroup UART_RTSHandshake RTS Handshake + * @brief Available RTS Handshake Macro Definisiton. + * @{ + */ +#define UART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RTS_ENABLE ((uint32_t)0x00000200) /*!< Available. */ +/** + * @} + */ /* End of group UART_RTSHandshake */ + + +/** + * @defgroup UART_DataComplementation Data Complementation + * @brief Enable/Disable Data Signal Complementation Macro Definisiton. + * @{ + */ +#define UART_DATA_COMPLEMENTION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_DATA_COMPLEMENTION_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group UART_DataComplementation */ + + +/** + * @defgroup UART_DataDirection Data Direction + * @brief Data Direction Macro Definisiton. + * @{ + */ +#define UART_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define UART_DATA_DIRECTION_MSB ((uint32_t)0x00000020) /*!< MSB first */ +/*! + * @} + */ /* End of group UART_DataDirection */ + + +/** + * @defgroup UART_StopBit Stop Bit + * @brief Stop Bit Macro Definisiton. + * @{ + */ +#define UART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ +#define UART_STOP_BIT_2 ((uint32_t)0x00000010) /*!< 2 bit */ +/** + * @} + */ /* End of group UART_StopBit */ + + +/** + * @defgroup UART_ParityBit Parity Bit + * @brief Parity Bit Macro Definisiton. + * @{ + */ +#define UART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define UART_PARITY_BIT_EVEN ((uint32_t)0x00000008) /*!< Even Parity */ +/** + * @} + */ /* End of group UART_ParityBit */ + + +/** + * @defgroup UART_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definisiton. + * @{ + */ +#define UART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_PARITY_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group UART_ParityEnable */ + + +/** + * @defgroup UART_DataLength Data Length + * @brief Data Length Macro Definisiton. + * @{ + */ +#define UART_DATA_LENGTH_7 ((uint32_t)0x00000000) /*!< 7 bit */ +#define UART_DATA_LENGTH_8 ((uint32_t)0x00000001) /*!< 8 bit */ +#define UART_DATA_LENGTH_9 ((uint32_t)0x00000002) /*!< 9 bit */ +/** + * @} + */ /* End of group UART_DataLength */ + + +/** + * @defgroup UART_TxFillLevelRange Tx Fill Level Range + * @brief Transmit Fill Level Range Macro Definisiton. + * @brief Range of Value be set "(UART_TX_FILL_LEVEL_MIN <= Value <= UART_TX_FILL_LEVEL_MAX)". + * @{ + */ +#define UART_TX_FILL_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :1 */ +#define UART_TX_FILL_RANGE_MAX ((uint32_t)0x00000007) /*!< Maximum Value :7 */ +/*! + * @} + */ /* End of group UART_TxFillLevelRange */ + + +/** + * @defgroup UART_RxFillLevelRange Rx Fill Level Range + * @brief Receive Fill Level Range Macro Definisiton. + * @brief Range of Value be set "(UART_RX_FILL_LEVEL_MIN <= Value <= UART_RX_FILL_LEVEL_MAX)". + * @{ + */ +#define UART_RX_FILL_RANGE_MIN ((uint32_t)0x00000001) /*!< Minimum Value :1 */ +#define UART_RX_FILL_RANGE_MAX ((uint32_t)0x00000008) /*!< Maximum Value :8 */ +/** + * @} + */ /* End of group UART_RxFillLevelRange */ + + +/** + * @defgroup UART_TxFIFOInterrupt Tx FIFO Interrpt + * @brief Available Transmit FIFO Interrupt Macro Definisiton. + * @{ + */ +#define UART_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Available. */ +/** + * @} + */ /* End of group UART_TxFIFOInterrupt */ + + +/** + * @defgroup UART_TxInterrupt Tx Interrpt + * @brief Available Transmit Interrupt Macro Definisiton. + * @{ + */ +#define UART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Available. */ +/** + * @} + */ /* End of group UART_TxInterrupt */ + + +/** + * @defgroup UART_RxFIFOInterrupt Rx FIFO Interrpt + * @brief Available Receive FIFO Interrupt Macro Definisiton. + * @{ + */ +#define UART_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ +/** + * @} + */ /* End of group UART_RxFIFOInterrupt */ + + +/** + * @defgroup UART_RxInterrupt Rx Interrpt + * @brief Available Receive Interrupt Macro Definisiton. + * @{ + */ +#define UART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ +/** + * @} + */ /* End of group UART_RxInterrupt */ + + +/** + * @defgroup UART_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definisiton. + * @{ + */ +#define UART_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group UART_ErrorInterrupt */ + + +/** + * @defgroup UART_Prescaler Prescaler + * @brief Prescaler Macro Definisiton. + * @{ + */ +#define UART_PLESCALER_1 ((uint32_t)0x00000000) /*!< 1/1 */ +#define UART_PLESCALER_2 ((uint32_t)0x00000010) /*!< 1/2 */ +#define UART_PLESCALER_4 ((uint32_t)0x00000020) /*!< 1/4 */ +#define UART_PLESCALER_8 ((uint32_t)0x00000030) /*!< 1/8 */ +#define UART_PLESCALER_16 ((uint32_t)0x00000040) /*!< 1/16 */ +#define UART_PLESCALER_32 ((uint32_t)0x00000050) /*!< 1/32 */ +#define UART_PLESCALER_64 ((uint32_t)0x00000060) /*!< 1/64 */ +#define UART_PLESCALER_128 ((uint32_t)0x00000070) /*!< 1/128 */ +#define UART_PLESCALER_256 ((uint32_t)0x00000080) /*!< 1/256 */ +#define UART_PLESCALER_512 ((uint32_t)0x00000090) /*!< 1/512 */ +/** + * @} + */ /* End of group UART_Prescaler */ + + +/** + * @defgroup UART_Clock_Mask Clock Mask + * @brief Clock Mask Macro Definisiton. + * @{ + */ +#define UART_UARTxCLK_MASK ((uint32_t)0x00000000) /*!< [1:0] is always 0 */ +/** + * @} + */ /* End of group UART_Clock_Mask */ + + +/** + * @defgroup UART_Division Division + * @brief Enable/Disable Division Macro Definisiton. + * @{ + */ +#define UART_DIVISION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /*!< Enable */ +/** + * @} + */ /* End of group UART_Division */ + + +/** + * @defgroup UART_RangeK Range K + * @brief Range of K Macro Definisiton. + * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= UART_RANGE_K_MAX)". + * @{ + */ +#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ +#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ +/** + * @} + */ /* End of group UART_RangeK */ + + +/** + * @defgroup UART_RangeN Range N + * @brief Range of N Macro Definisiton. + * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= UART_RANGE_N_MAX)". + * @{ + */ +#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /*!< Minimum Value :N=1 */ +#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ +/** + * @} + */ /* End of group UART_RangeN */ + + +/** + * @defgroup UART_SettingEnable Setting Enable + * @brief Enable/Disable Setting Macro Definisiton. + * @{ + */ +#define UART_SETTING_MASK ((uint32_t)0x80000000) /*!< for Mask */ +#define UART_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define UART_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group UART_SettingEnable */ + + +/** + * @defgroup UART_TxState Tx State + * @brief Transmitting State Macro Definisiton. + * @{ + */ +#define UART_TX_STATE_MASK ((uint32_t)0x00008000) /*!< for Mask */ +#define UART_TX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ +#define UART_TX_STATE_RUN ((uint32_t)0x00008000) /*!< Run */ +/** + * @} + */ /* End of group UART_TxState */ + + +/** + * @defgroup UART_TxDone Transmitting Done + * @brief Transmitting Done Macro Definisiton. + * @{ + */ +#define UART_TX_MASK ((uint32_t)0x00004000) /*!< for Mask */ +#define UART_TX_DONE ((uint32_t)0x00004000) /*!< Transmitting Done */ +/** + * @} + */ /* End of group UART_TxDone */ + + +/** + * @defgroup UART_TxReachFillLevel Tx Reach Fill Level + * @brief Reach Transmitting Fill Level Macro Definisiton. + * @{ + */ +#define UART_TX_REACH_FILL_MASK ((uint32_t)0x00002000) /*!< for Mask */ +#define UART_TX_REACH_FILL_LEVEL ((uint32_t)0x00002000) /*!< Reach Transmitting Fill Level */ +/** + * @} + */ /* End of group UART_TxReachFillLevel */ + + +/** + * @defgroup UART_TxFifoLevel Tx FIFO Fill Level + * @brief Transmitting FIFO Fill Level Macro Definisiton. + * @{ + */ +#define UART_TX_FIFO_LEVEL_MASK ((uint32_t)0x00000F00) /*!< for Mask */ +/** + * @} + */ /* End of group UART_TxFifoLevel */ + + +/** + * @defgroup UART_RxState Rx State + * @brief Receive State Macro Definisiton. + * @{ + */ +#define UART_RX_STATE_MASK ((uint32_t)0x00000080) /*!< for Mask */ +#define UART_RX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ +#define UART_RX_STATE_RUN ((uint32_t)0x00000080) /*!< Run */ +/** + * @} + */ /* End of group UART_RxState */ + + +/** + * @defgroup UART_RxDone Rx Done + * @brief Receive Done Macro Definisiton. + * @{ + */ +#define UART_RX_MASK ((uint32_t)0x00000040) /*!< for Mask */ +#define UART_RX_DONE ((uint32_t)0x00000040) /*!< Receive Done */ +/** + * @} + */ /* End of group UART_RxDone */ + + +/** + * @defgroup UART_RxReachFillLevel Rx Reach Fill Level + * @brief Reach Receive Fill Level Macro Definisiton. + * @{ + */ +#define UART_RX_REACH_FILL_MASK ((uint32_t)0x00000020) /*!< for Mask */ +#define UART_RX_REACH_FILL_LEVEL ((uint32_t)0x00000020) /*!< Reach Receive Fill Level */ +/** + * @} + */ /* End of group UART_RxReachFillLevel */ + + +/** + * @defgroup UART_RxFifoLevel Rx FIFO Fill Level + * @brief Receive FIFO Fill Level Macro Definisiton. + * @{ + */ +#define UART_RX_FIFO_LEVEL_MASK ((uint32_t)0x0000000F) /*!< for Mask */ +/** + * @} + */ /* End of group UART_RxFifoLevel */ + + +/** + * @defgroup UART_TriggerErr Trigger Error + * @brief Trigger Error Macro Definisiton. + * @{ + */ +#define UART_TRIGGER_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_TRIGGER_ERR ((uint32_t)0x00000010) /*!< Error */ +/** + * @} + */ /* End of group UART_TxTriggerErr */ + + +/** + * @defgroup UART_OverrunErr Overrun Error + * @brief Overrun Error Macro Definisiton. + * @{ + */ +#define UART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ +/** + * @} + */ /* End of group UART_OverrunErr */ + + +/** + * @defgroup UART_ParityErr Parity Error + * @brief Parity Error Macro Definisiton. + * @{ + */ +#define UART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_PARITY_ERR ((uint32_t)0x00000004) /*!< Error */ +/** + * @} + */ /* End of group UART_ParityErr */ + + +/** + * @defgroup UART_FramingErr Framing Error + * @brief Framing Error Macro Definisiton. + * @{ + */ +#define UART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_FRAMING_ERR ((uint32_t)0x00000002) /*!< Error */ +/** + * @} + */ /* End of group UART_FramingErr */ + + +/** + * @defgroup UART_BreakErr Break Error + * @brief Break Error Macro Definisiton. + * @{ + */ +#define UART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_BREAK_ERR ((uint32_t)0x00000001) /*!< Error */ +/** + * @} + */ /* End of group UART_BreakErr */ + +/** + * @} + */ /* End of group UART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_define UART Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_typedef UART Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Receive event information structure definenition. + * @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this. + * @attention "num" must be over FIFO max num. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} uart_receive8_t; + +/*----------------------------------*/ +/** + * @brief Receive event information structure definenition. + * @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} uart_receive16_t; + +/*----------------------------------*/ +/** + * @brief Receive event information structure definenition. +*/ +/*----------------------------------*/ +typedef union { + uart_receive8_t rx8; /*!< @ref uart_receive8_t */ + uart_receive16_t rx16; /*!< @ref uart_receive16_t */ +} uart_receive_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} uart_transmit8_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to transmit data. + Rransmit data valid range is ( 0x0000 <= range <= 0x01FF ) */ + uint32_t num; /*!< The number of transmit data. */ +} uart_transmit16_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definenition. +*/ +/*----------------------------------*/ +typedef union { + uart_transmit8_t tx8; /*!< @ref uart_transmit8_t */ + uart_transmit16_t tx16; /*!< @ref uart_transmit16_t */ +} uart_transmit_t; + +/*----------------------------------*/ +/** + * @brief Clock setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t prsel; /*!< Prescaler. + : Use @ref UART_Prescaler */ +} uart_clock_t; + +/*----------------------------------*/ +/** + * @brief Boudrate setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ken; /*!< Enable/Disable Division Definisiton. + : Use @ref UART_Division */ + uint32_t brk; /*!< Division Value K. + : K Range ( UART_RANGE_K_MIN <= K =< UART_RANGE_K_MAX ) @ref UART_RangeK */ + uint32_t brn; /*!< Division Value N. + : N Range ( UART_RANGE_N_MIN <= N =< UART_RANGE_N_MAX ) @ref UART_RangeN */ +} uart_boudrate_t; + +/*----------------------------------*/ +/** + * @brief Transmit FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inttx; /*!< Available Transmit FIFO Interrupt. + : Use @ref UART_TxFIFOInterrupt */ + uint32_t level; /*!< Transmit Fill Level. + : Range ( UART_TX_FILL_RANGE_MIN <= K =< UART_TX_FILL_RANGE_MAX ) @ref UART_TxFillLevelRange */ +} uart_tx_fifo_t; + +/*----------------------------------*/ +/** + * @brief Receive FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intrx; /*!< Available Receive FIFO Interrupt. + : Use @ref UART_RxFIFOInterrupt */ + uint32_t level; /*!< Receive Fill Level. + : Range ( UART_RX_FILL_RANGE_MIN <= K =< UART_RX_FILL_RANGE_MAX ) @ref UART_RxFillLevelRange */ +} uart_rx_fifo_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + uart_clock_t clock; /*!< Clock setting. + : Use @ref uart_clock_t */ + uart_boudrate_t boudrate; /*!< Boudrate setting. + : Use @ref uart_boudrate_t */ + uint32_t inttx; /*!< Available Transmit Interrupt. + : Use @ref UART_TxInterrupt */ + uint32_t intrx; /*!< Available Receive Interrupt. + : Use @ref UART_RxInterrupt */ + uint32_t interr; /*!< Available Error Interrupt. + : Use @ref UART_ErrorInterrupt */ + uart_tx_fifo_t txfifo; /*!< Transmit FIFO setting. + : Use @ref uart_tx_fifo_t */ + uart_rx_fifo_t rxfifo; /*!< Receive FIFO setting. + : Use @ref uart_rx_fifo_t */ + uint32_t hct; /*!< Half Clock Terminal Select. + : Use @ref UART_HalfClockSelect */ + uint32_t hcm; /*!< Half Clock Mode Select. + : Use @ref UART_HalfClockMode */ + uint32_t hcc; /*!< Half Clock Control. + : Use @ref UART_HalfClockCTR */ + uint32_t lbc; /*!< Loop Back Control. + : Use @ref UART_LoopBack */ + uint32_t nf; /*!< UTxRXD Noise Filter. + : Use @ref UART_NoiseFilter */ + uint32_t ctse; /*!< Available CTS Handshake. + : Use @ref UART_CTSHandshake */ + uint32_t rtse; /*!< Available RTS Handshake. + : Use @ref UART_RTSHandshake */ + uint32_t iv; /*!< Data Signal Complementation. + : Use @ref UART_DataComplementation */ + uint32_t dir; /*!< Data Direction. + : Use @ref UART_DataDirection */ + uint32_t sblen; /*!< Stop Bit. + : Use @ref UART_StopBit */ + uint32_t even; /*!< Odd/Even Parity Bit. + : Use @ref UART_ParityBit */ + uint32_t pe; /*!< Enable/Disable Parity Bit. + : Use @ref UART_ParityEnable */ + uint32_t sm; /*!< Data Length. + : Use @ref UART_DataLength */ +} uart_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief UART handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_UART_TypeDef *p_instance; /*!< Registers base address. */ + uart_initial_setting_t init; /*!< Initial setting. */ + /*------------------------------------------*/ + /*! + @brief Transmit Informatin. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmited data. */ + uart_transmit_t info; /*!< Transmit Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Informatin. + */ + /*------------------------------------------*/ + struct { + uart_receive_t info; /*!< Receive Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result, uart_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} uart_t; + +/** + * @} + */ /* End of group UART_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_functions UART Exported Functions + * @{ + */ +TXZ_Result uart_init(uart_t *p_obj); +TXZ_Result uart_deinit(uart_t *p_obj); +TXZ_Result uart_discard_transmit(uart_t *p_obj); +TXZ_Result uart_discard_receive(uart_t *p_obj); +TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info); +TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info); +void uart_transmit_irq_handler(uart_t *p_obj); +void uart_receive_irq_handler(uart_t *p_obj); +void uart_error_irq_handler(uart_t *p_obj); +TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status); +TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error); +TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_setting); +/** + * @} + */ /* End of group UART_Exported_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart_include.h new file mode 100644 index 00000000000..5e18c322bf3 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart_include.h @@ -0,0 +1,484 @@ +/** + ******************************************************************************* + * @file txzp_uart_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __UART_INCLUDE_H +#define __UART_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_define + * @{ + */ + +/** + * @defgroup UART_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define UART_NULL ((void *)0) +/** + * @} + */ /* End of group UART_NullPointer */ + +/** + * @defgroup UART_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define UART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define UART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group UART_ParameterResult */ + +/** + * @defgroup UARTxSWRST UARTxSWRST Register + * @brief UARTxSWRST Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | SWRSTF | + * | 6:2 | - | + * | 1:0 | SWRST | + * @{ + */ +/* SWRSTF */ +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /*!< SWRSTF :Mask. */ +#define UARTxSWRST_SWRSTF_IDLE ((uint32_t)0x00000000) /*!< SWRSTF :Not be "Software Reset". */ +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /*!< SWRSTF :During "Software Reset". */ +/* SWRST */ +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /*!< SWRST :"10" */ +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /*!< SWRST :"01" */ +/** + * @} + */ /* End of group UARTxSWRST */ + +/** + * @defgroup UARTxCR0 UARTxCR0 Register + * @brief UARTxCR0 Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-19 | - | + * | 18 | HBSST | + * | 17 | HBSMD | + * | 16 | HBSEN | + * | 15 | LPB | + * | 14-12 | NF[2:0] | + * | 11 | - | + * | 10 | CTSE | + * | 9 | RTSE | + * | 8 | WU | + * | 7 | - | + * | 6 | IV | + * | 5 | DIR | + * | 4 | SBLEN | + * | 3 | EVEN | + * | 2 | PE | + * | 1-0 | SM[1:0] | + * @{ + */ +/* HBSST */ +#define UARTxCR0_HBSST_MASK ((uint32_t)0x00040000) /*!< HBSST :Mask. */ +/* HBSMD */ +#define UARTxCR0_HBSMD_MASK ((uint32_t)0x00020000) /*!< HBSMD :Mask. */ +/* HBSEN */ +#define UARTxCR0_HBSEN_MASK ((uint32_t)0x00010000) /*!< HBSEN :Mask. */ +#define UARTxCR0_HBSEN_DISABLE ((uint32_t)0x00000000) /*!< HBSEN :Disable. */ +#define UARTxCR0_HBSEN_ENABLE ((uint32_t)0x00010000) /*!< HBSEN :Enable. */ +/* LPB */ +#define UARTxCR0_LPB_MASK ((uint32_t)0x00008000) /*!< LPB :Mask. */ +#define UARTxCR0_LPB_DISABLE ((uint32_t)0x00000000) /*!< LPB :Disable. */ +#define UARTxCR0_LPB_ENABLE ((uint32_t)0x00008000) /*!< LPB :Enable. */ +/* WU */ +#define UARTxCR0_WU_MASK ((uint32_t)0x00000100) /*!< WU :Mask. */ +#define UARTxCR0_WU_DISABLE ((uint32_t)0x00000000) /*!< WU :Disable. */ +#define UARTxCR0_WU_ENABLE ((uint32_t)0x00000100) /*!< WU :Enable. */ +/** + * @} + */ /* End of group UARTxCR0 */ + +/** + * @defgroup UARTxCR1 UARTxCR1 Register + * @brief UARTxCR1 Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-15 | - | + * | 14-12 | TIL[2:0] | + * | 11 | - | + * | 10-8 | RIL[2:0] | + * | 7 | INTTXFE | + * | 6 | INTTXWE | + * | 5 | INTRXFE | + * | 4 | INTRXWE | + * | 3 | - | + * | 2 | INTERR | + * | 1 | DMATE | + * | 0 | DMARE | + * @{ + */ +/* RIL */ +#define UARTxCR1_RIL_MASK ((uint32_t)0x00000700) /*!< RIL :Mask. */ +/* DMATE */ +#define UARTxCR1_DMATE_MASK ((uint32_t)0x00000002) /*!< DMATE :Mask. */ +#define UARTxCR1_DMATE_DISABLE ((uint32_t)0x00000000) /*!< DMATE :Disable. */ +#define UARTxCR1_DMATE_ENABLE ((uint32_t)0x00000002) /*!< DMATE :Enable. */ +/* DMARE */ +#define UARTxCR1_DMARE_MASK ((uint32_t)0x00000001) /*!< DMARE :Mask. */ +#define UARTxCR1_DMARE_DISABLE ((uint32_t)0x00000000) /*!< DMARE :Disable. */ +#define UARTxCR1_DMARE_ENABLE ((uint32_t)0x00000001) /*!< DMARE :Enable. */ +/** + * @} + */ /* End of group UARTxCR1 */ + +/** + * @defgroup UARTxTRANS UARTxTRANS Register + * @brief UARTxTRANS Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-4 | - | + * | 3 | BK | + * | 2 | TXTRG | + * | 1 | TXE | + * | 0 | RXE | + * @{ + */ +/* BK */ +#define UARTxTRANS_BK_MASK ((uint32_t)0x00000008) /*!< BK :Mask */ +#define UARTxTRANS_BK_STOP ((uint32_t)0x00000000) /*!< BK :Stop */ +#define UARTxTRANS_BK_SEND ((uint32_t)0x00000008) /*!< BK :Send */ +/* TXTRG */ +#define UARTxTRANS_TXTRG_MASK ((uint32_t)0x00000004) /*!< TXTRG :Mask */ +#define UARTxTRANS_TXTRG_DISABLE ((uint32_t)0x00000000) /*!< TXTRG :Disable */ +#define UARTxTRANS_TXTRG_ENABLE ((uint32_t)0x00000004) /*!< TXTRG :Enable */ +/* TXE */ +#define UARTxTRANS_TXE_MASK ((uint32_t)0x00000002) /*!< TXE :Mask */ +#define UARTxTRANS_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable */ +#define UARTxTRANS_TXE_ENABLE ((uint32_t)0x00000002) /*!< TXE :Enable */ +/* RXE */ +#define UARTxTRANS_RXE_MASK ((uint32_t)0x00000001) /*!< RXE :Mask */ +#define UARTxTRANS_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable */ +#define UARTxTRANS_RXE_ENABLE ((uint32_t)0x00000001) /*!< RXE :Enable */ +/* TXE,RXE */ +#define UARTxTRANS_TXE_RXE_MASK ((uint32_t)0x00000003) /*!< TXE/RXE:Mask */ +/** + * @} + */ /* End of group UARTxTRANS */ + +/** + * @defgroup UARTxDR UARTxDR Register + * @brief UARTxDR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-19 | - | + * | 18 | PERR | + * | 17 | FERR | + * | 16 | BERR | + * | 15:9 | - | + * | 8:0 | DR | + * @{ + */ +/* DR */ +#define UARTxDR_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 9bit */ +#define UARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define UARTxDR_DR_7BIT_MASK ((uint32_t)0x0000007F) /*!< DR :Mask for 7bit */ +/** + * @} + */ /* End of group UARTxDR */ + +/** + * @defgroup UARTxSR UARTxSR Register + * @brief UARTxSR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31 | SUE | + * | 30:16 | - | + * | 15 | TXRUN | + * | 14 | TXEND | + * | 13 | TXFF | + * | 12 | - | + * | 11:8 | TLVL | + * | 7 | RXRUN | + * | 6 | RXEND | + * | 5 | RXFF | + * | 4 | - | + * | 3:0 | RLVL | + * @{ + */ +/* SUE */ +#define UARTxSR_SUE_MASK ((uint32_t)0x80000000) /*!< SUE :Mask. */ +/* TXEND */ +#define UARTxSR_TXEND_MASK ((uint32_t)0x00004000) /*!< TEXND :Mask. */ +#define UARTxSR_TXEND_R_END ((uint32_t)0x00004000) /*!< TXEND :[read] Transfer done. */ +#define UARTxSR_TXEND_W_CLEAR ((uint32_t)0x00004000) /*!< TXEND :[write] Clear Flag. */ +/* TXFF */ +#define UARTxSR_TXFF_MASK ((uint32_t)0x00002000) /*!< TXFF :Mask. */ +#define UARTxSR_TXFF_R_REACHED ((uint32_t)0x00002000) /*!< TXFF :[read] Reached the transfer level. */ +#define UARTxSR_TXFF_W_CLEAR ((uint32_t)0x00002000) /*!< TXFF :[write] Clear Flag. */ +/* TLVL */ +#define UARTxSR_TLVL_MASK ((uint32_t)0x00000F00) /*!< TLVL :Mask. */ +/* RXEND */ +#define UARTxSR_RXEND_MASK ((uint32_t)0x00000040) /*!< RXEND :Mask. */ +#define UARTxSR_RXEND_R_END ((uint32_t)0x00000040) /*!< RXEND :[read] Receive done. */ +#define UARTxSR_RXEND_W_CLEAR ((uint32_t)0x00000040) /*!< RXEND :[write] Clear Flag. */ +/* RXFF */ +#define UARTxSR_RXFF_MASK ((uint32_t)0x00000020) /*!< RXFF :Mask. */ +#define UARTxSR_RXFF_R_REACHED ((uint32_t)0x00000020) /*!< RXFF :[read] Receive done. */ +#define UARTxSR_RXFF_W_CLEAR ((uint32_t)0x00000020) /*!< RXFF :[write] Clear Flag. */ +/* RLVL */ +#define UARTxSR_RLVL_MASK ((uint32_t)0x0000000F) /*!< RLVL :Mask. */ +/** + * @} + */ /* End of group UARTxSR */ + +/** + * @defgroup UARTxFIFOCLR UARTxFIFOCLR Register + * @brief UARTxFIFOCLR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-2 | - | + * | 1 | TFCLR | + * | 0 | RFCLR | + * @{ + */ +/* TFCLR */ +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /*!< TFCLR :Clear the transmit buff. */ +/* RFCLR */ +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /*!< RFCLR :Clear the receive buff. */ +/** + * @} + */ /* End of group UARTxFIFOCLR */ + +/** + * @defgroup UARTxERR UARTxERR Register + * @brief UARTxERR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-5 | - | + * | 4 | TRGERR | + * | 3 | OVRERR | + * | 2 | PERR | + * | 1 | FERR | + * | 0 | BERR | + * @{ + */ +/* TRGERR */ +#define UARTxERR_TRGERR_MASK ((uint32_t)0x00000010) /*!< TRGERR :Mask. */ +#define UARTxERR_TRGERR_R_NO_ERR ((uint32_t)0x00000000) /*!< TRGERR :[read] No Error. */ +#define UARTxERR_TRGERR_R_ERR ((uint32_t)0x00000010) /*!< TRGERR :[read] Error. */ +#define UARTxERR_TRGERR_W_CLEAR ((uint32_t)0x00000010) /*!< TRGERR :[write] Clear Flag. */ +/* OVRERR */ +#define UARTxERR_OVRERR_MASK ((uint32_t)0x00000008) /*!< OVRERR :Mask. */ +#define UARTxERR_OVRERR_R_NO_ERR ((uint32_t)0x00000000) /*!< OVRERR :[read] No Error. */ +#define UARTxERR_OVRERR_R_ERR ((uint32_t)0x00000008) /*!< OVRERR :[read] Error. */ +#define UARTxERR_OVRERR_W_CLEAR ((uint32_t)0x00000008) /*!< OVRERR :[write] Clear Flag. */ +/* PERR */ +#define UARTxERR_PERR_MASK ((uint32_t)0x00000004) /*!< PERR :Mask. */ +#define UARTxERR_PERR_R_NO_ERR ((uint32_t)0x00000000) /*!< PERR :[read] No Error. */ +#define UARTxERR_PERR_R_ERR ((uint32_t)0x00000004) /*!< PERR :[read] Error. */ +#define UARTxERR_PERR_W_CLEAR ((uint32_t)0x00000004) /*!< PERR :[write] Clear Flag. */ +/* FERR */ +#define UARTxERR_FERR_MASK ((uint32_t)0x00000002) /*!< FERR :Mask. */ +#define UARTxERR_FERR_R_NO_ERR ((uint32_t)0x00000000) /*!< FERR :[read] No Error. */ +#define UARTxERR_FERR_R_ERR ((uint32_t)0x00000002) /*!< FERR :[read] Error. */ +#define UARTxERR_FERR_W_CLEAR ((uint32_t)0x00000002) /*!< FERR :[write] Clear Flag. */ +/* BERR */ +#define UARTxERR_BERR_MASK ((uint32_t)0x00000001) /*!< BERR :Mask. */ +#define UARTxERR_BERR_R_NO_ERR ((uint32_t)0x00000000) /*!< BERR :[read] No Error. */ +#define UARTxERR_BERR_R_ERR ((uint32_t)0x00000001) /*!< BERR :[read] Error. */ +#define UARTxERR_BERR_W_CLEAR ((uint32_t)0x00000001) /*!< BERR :[write] Clear Flag. */ +/** + * @} + */ /* End of group UARTxERR */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_fuctions + * @{ + */ +__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); +/*--------------------------------------------------*/ +/** + * @brief Disable UARTxTRANS TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef DEBUG + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable UARTxTRANS TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef DEBUG + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable UARTxTRANS RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef DEBUG + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable UARTxTRANS RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef DEBUG + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1; +#endif +} + + +/** + * @} + */ /* End of group UART_Private_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/rda_flash512ud32_b.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/rda_flash512ud32_b.c new file mode 100644 index 00000000000..7d22fb49d99 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/rda_flash512ud32_b.c @@ -0,0 +1,1568 @@ +/** + ******************************************************************************* + * @file rda_flash512ud32_b.c + * @brief This file provides API functions for FLASH rda.\n + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2020 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include +#include +#include "flash.h" +#include "TMPM4KNA.h" + +#if defined(__FLASH_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup RDA_FLASH512UD32 RDA_FLASH512UD32 + * @{ + */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup RDA_FLASH512UD32_Private_config RDA_FLASH512UD32 Private Config + * @{ + */ + + +/** + * @} + */ /* End of group RDA_FLASH512UD32_Private_config */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup RDA_FLASH512UD32_Private_define RDA_FLASH512UD32 Private Define + * @{ + */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */ +#define FC_MAX_PAGES (uint8_t)(0x80) /*!< Maxmum pages */ +#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */ +#define FC_MAX_AREAS (uint8_t)(0x1) /*!< Maxmum areas */ +#define FC_MAX_DATA_PAGES (uint8_t)(0x21) /*!< Maxmum pages */ +#define FC_MAX_DATA_BLOCKS (uint8_t)(0x8) /*!< Maxmum blocks */ +#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */ +#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */ +#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */ +#define FC_BANK_USER_INFO (0x00000007UL) /*!< Bank Change User Information Area */ +#define FC_BANK_CODE_FLASH (0x00000000UL) /*!< Bank Change Code Flash */ +#define FC_BUFFER_DISABLE (0x00000007UL) /*!< Flash Buffer Disable nad Clear */ +#define FC_BUFFER_ENABLE (0x00000000UL) /*!< Flash Buffer Enable */ + +#define FC_PROTECT_ADDR (0x00002000UL) /*!< The lower address of protect command */ +#define FC_SWAP_ADDR (0x00003000UL) /*!< The lower address of swap command */ +#define FC_BUSY_MAX_WAIT (0x00001000UL) /*!< Busy wait count */ + +#define FC_ACCR_FDLC_4 (0x00000300UL) /*!< Data Flash read clock 4clock */ +#define FC_ACCR_FDLC_5 (0x00000400UL) /*!< Data Flash read clock 5clock */ +#define FC_ACCR_FDLC_6 (0x00000500UL) /*!< Data Flash read clock 6clock */ +#define FC_ACCR_FCLC_1 (0x00000000UL) /*!< Code Flash read clock 1clock */ +#define FC_ACCR_FCLC_2 (0x00000001UL) /*!< Code Flash read clock 2clock */ +#define FC_ACCR_FCLC_3 (0x00000002UL) /*!< Code Flash read clock 3clock */ +#define FC_ACCR_FCLC_4 (0x00000003UL) /*!< Code Flash read clock 4clock */ +#define FC_ACCR_FCLC_5 (0x00000004UL) /*!< Code Flash read clock 5clock */ +#define FC_ACCR_FCLC_6 (0x00000005UL) /*!< Code Flash read clock 6clock */ +#define SYSCORECLOCK_80M (80000000UL) /*!< 80MHz */ + +/* FCSR0 register */ +#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL) /*!< RW, Selects expect area0 */ +#define FC_AREASEL_EXPECT_AREA4 (uint32_t)(0x00000000UL) /*!< RW, Selects expect area4 */ +#define FC_AREASEL_AREA0 (uint32_t)(0x00000007UL) /*!< RW, Selects area0 */ +#define FC_AREASEL_AREA4 (uint32_t)(0x00070000UL) /*!< RW, Selects area4 */ +#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFF8F0FF8UL) /*!< RW, Selects area0 */ +#define FC_AREASEL_MASK_AREA4 (uint32_t)(0xFF880FFFUL) /*!< RW, Selects area4 */ +#define FC_AREASEL_WRITE_MODE (uint32_t)(0x04000000UL) /*!< R, Write Mode */ +#define FC_AREASEL4_WRITE_MODE (uint32_t)(0x40000000UL) /*!< R, Write Mode */ + +#define FC_SEC_MASK (uint32_t)(0x00000001UL) /*!< Flash security bit mask */ +#define FC_SEC_ENABLE (uint32_t)(0x00000001UL) /*!< Flash security enable */ + +static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = { + (0x5E000000UL), /*!< CODE FLASH Page0 */ + (0x5E001000UL), /*!< CODE FLASH Page1 */ + (0x5E002000UL), /*!< CODE FLASH Page2 */ + (0x5E003000UL), /*!< CODE FLASH Page3 */ + (0x5E004000UL), /*!< CODE FLASH Page4 */ + (0x5E005000UL), /*!< CODE FLASH Page5 */ + (0x5E006000UL), /*!< CODE FLASH Page6 */ + (0x5E007000UL), /*!< CODE FLASH Page7 */ + (0x5E008000UL), /*!< CODE FLASH Page8 */ + (0x5E009000UL), /*!< CODE FLASH Page9 */ + (0x5E00A000UL), /*!< CODE FLASH Page10 */ + (0x5E00B000UL), /*!< CODE FLASH Page11 */ + (0x5E00C000UL), /*!< CODE FLASH Page12 */ + (0x5E00D000UL), /*!< CODE FLASH Page13 */ + (0x5E00E000UL), /*!< CODE FLASH Page14 */ + (0x5E00F000UL), /*!< CODE FLASH Page15 */ + (0x5E010000UL), /*!< CODE FLASH Page16 */ + (0x5E011000UL), /*!< CODE FLASH Page17 */ + (0x5E012000UL), /*!< CODE FLASH Page18 */ + (0x5E013000UL), /*!< CODE FLASH Page19 */ + (0x5E014000UL), /*!< CODE FLASH Page20 */ + (0x5E015000UL), /*!< CODE FLASH Page21 */ + (0x5E016000UL), /*!< CODE FLASH Page22 */ + (0x5E017000UL), /*!< CODE FLASH Page23 */ + (0x5E018000UL), /*!< CODE FLASH Page24 */ + (0x5E019000UL), /*!< CODE FLASH Page25 */ + (0x5E01A000UL), /*!< CODE FLASH Page26 */ + (0x5E01B000UL), /*!< CODE FLASH Page27 */ + (0x5E01C000UL), /*!< CODE FLASH Page28 */ + (0x5E01D000UL), /*!< CODE FLASH Page29 */ + (0x5E01E000UL), /*!< CODE FLASH Page30 */ + (0x5E01F000UL) /*!< CODE FLASH Page31 */ +}; + +static uint32_t fc_const_code_flash_block_address[FC_MAX_BLOCKS] = { + (0x5E000000UL), /*!< CODE FLASH Block0 */ + (0x5E008000UL), /*!< CODE FLASH Block1 */ + (0x5E010000UL), /*!< CODE FLASH Block2 */ + (0x5E018000UL), /*!< CODE FLASH Block3 */ + (0x5E020000UL), /*!< CODE FLASH Block4 */ + (0x5E028000UL), /*!< CODE FLASH Block5 */ + (0x5E030000UL), /*!< CODE FLASH Block6 */ + (0x5E038000UL), /*!< CODE FLASH Block7 */ + (0x5E040000UL), /*!< CODE FLASH Block8 */ + (0x5E048000UL), /*!< CODE FLASH Block9 */ + (0x5E050000UL), /*!< CODE FLASH Block10 */ + (0x5E058000UL), /*!< CODE FLASH Block11 */ + (0x5E060000UL), /*!< CODE FLASH Block12 */ + (0x5E068000UL), /*!< CODE FLASH Block13 */ + (0x5E070000UL), /*!< CODE FLASH Block14 */ + (0x5E078000UL) /*!< CODE FLASH Block15 */ +}; + +static uint32_t fc_const_data_flash_address[FC_MAX_DATA_PAGES] = { + (0x30000000UL), /*!< DATA FLASH Page0 */ + (0x30000100UL), /*!< DATA FLASH Page1 */ + (0x30000200UL), /*!< DATA FLASH Page2 */ + (0x30000300UL), /*!< DATA FLASH Page3 */ + (0x30000400UL), /*!< DATA FLASH Page4 */ + (0x30000500UL), /*!< DATA FLASH Page5 */ + (0x30000600UL), /*!< DATA FLASH Page6 */ + (0x30000700UL), /*!< DATA FLASH Page7 */ + (0x30000800UL), /*!< DATA FLASH Page8 */ + (0x30000900UL), /*!< DATA FLASH Page9 */ + (0x30000A00UL), /*!< DATA FLASH Page10 */ + (0x30000B00UL), /*!< DATA FLASH Page11 */ + (0x30000C00UL), /*!< DATA FLASH Page12 */ + (0x30000D00UL), /*!< DATA FLASH Page13 */ + (0x30000E00UL), /*!< DATA FLASH Page14 */ + (0x30000F00UL), /*!< DATA FLASH Page15 */ + (0x30001000UL), /*!< DATA FLASH Page16 */ + (0x30001100UL), /*!< DATA FLASH Page17 */ + (0x30001200UL), /*!< DATA FLASH Page18 */ + (0x30001300UL), /*!< DATA FLASH Page19 */ + (0x30001400UL), /*!< DATA FLASH Page20 */ + (0x30001500UL), /*!< DATA FLASH Page21 */ + (0x30001600UL), /*!< DATA FLASH Page22 */ + (0x30001700UL), /*!< DATA FLASH Page23 */ + (0x30001800UL), /*!< DATA FLASH Page24 */ + (0x30001900UL), /*!< DATA FLASH Page25 */ + (0x30001A00UL), /*!< DATA FLASH Page26 */ + (0x30001B00UL), /*!< DATA FLASH Page27 */ + (0x30001C00UL), /*!< DATA FLASH Page28 */ + (0x30001D00UL), /*!< DATA FLASH Page29 */ + (0x30001E00UL), /*!< DATA FLASH Page30 */ + (0x30001F00UL), /*!< DATA FLASH Page31 */ + (0x30002000UL) /*!< DATA FLASH Page32 */ +}; + +static uint32_t fc_const_data_flash_block_address[FC_MAX_DATA_BLOCKS] = { + (0x30000000UL), /*!< DATA FLASH Block0 */ + (0x30001000UL), /*!< DATA FLASH Block1 */ + (0x30002000UL), /*!< DATA FLASH Block2 */ + (0x30003000UL), /*!< DATA FLASH Block3 */ + (0x30004000UL), /*!< DATA FLASH Block4 */ + (0x30005000UL), /*!< DATA FLASH Block5 */ + (0x30006000UL), /*!< DATA FLASH Block6 */ + (0x30007000UL) /*!< DATA FLASH Block7 */ +}; + +static uint32_t fc_const_data_flash_area_address[FC_MAX_AREAS] = { + (0x30000000UL) /*!< DATA FLASH AREA0 */ +}; + +/** + * @} + */ /* End of group RDA_FLASH512UD32_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup RDA_FLASH512UD32_Private_enum RDA_FLASH512UD32 Private Enum + * @{ + */ + +/** + * @} + */ /* End of group RDA_FLASH512UD32_Private_enum */ + + +/*------------------------------------------------------------------------------*/ +/* Private Variables */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup RDA_FLASH512UD32_Private_variables RDA_FLASH512UD32 Private Variables + * @{ + */ + +/** + * @} + */ /* End of group RDA_FLASH512UD32_Private_variables */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup RDA_FLASH512UD32_Private_functions RDA_FLASH512UD32 Private Functions + * @{ + */ +__STATIC_INLINE uint32_t fc_enable_areasel(void); +__STATIC_INLINE uint32_t fc_disable_areasel(void); +__STATIC_INLINE uint32_t fc_enable_areasel4(void); +__STATIC_INLINE uint32_t fc_disable_areasel4(void); + +static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +static uint32_t fc_write_data_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size); + +static void fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind); + +static uint32_t fc_get_status(fc_sr0_t status); +static uint32_t fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +static uint32_t fc_blank_check(uint32_t *address, uint32_t size); + +static void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size); + +static void fc_protect_program_command(uint32_t protect_bit, fc_protect_kind_t kind); +static void fc_protect_erase_command(void); + +static void fc_bank_change(uint32_t bank); + +__STATIC_INLINE uint32_t fc_protect_mask_set(uint32_t protect_bit, fc_protect_kind_t kind); + +/*--------------------------------------------------*/ +/** + * @brief Read clock set. + * @param - + * @retval none. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +void fc_read_clock_set(void) +{ + uint32_t regval = 0; + + SystemCoreClockUpdate(); + if (SystemCoreClock > SYSCORECLOCK_80M) { + regval = (uint32_t)(FC_ACCR_FDLC_5 | FC_ACCR_FCLC_5); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->FCACCR = regval; + while (TSB_FC->FCACCR != (uint32_t)(FC_ACCR_FDLC_5 | FC_ACCR_FCLC_5)) { + /* no processing */ + } + } else { + regval = (uint32_t)(FC_ACCR_FDLC_4 | FC_ACCR_FCLC_4); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->FCACCR = regval; + while (TSB_FC->FCACCR != (uint32_t)(FC_ACCR_FDLC_4 | FC_ACCR_FCLC_4)) { + /* no processing */ + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief fc fixed clock set. + * @param sysclock : system clock (Hz) + * @retval none. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +void fc_fixed_clock_set(uint32_t sysclock) +{ + uint32_t regval = 0; + + if (sysclock > SYSCORECLOCK_80M) { + regval = (uint32_t)(FC_ACCR_FDLC_5 | FC_ACCR_FCLC_5); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->FCACCR = regval; + while (TSB_FC->FCACCR != (uint32_t)(FC_ACCR_FDLC_5 | FC_ACCR_FCLC_5)) { + /* no processing */ + } + } else { + regval = (uint32_t)(FC_ACCR_FDLC_4 | FC_ACCR_FCLC_4); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->FCACCR = regval; + while (TSB_FC->FCACCR != (uint32_t)(FC_ACCR_FDLC_4 | FC_ACCR_FCLC_4)) { + /* no processing */ + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Check FCSR0_RDYBSY. + * @param - + * @retval BUSY = 0 + * @note + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t Get_param_FC_RDYBSY(void) +{ + uint32_t retval = 0 ; + + retval = TSB_FC->SR0 & FCSR0_RDYBSY_MASK ; + + return retval ; +} +#if defined(_CC_ARM) +/*--------------------------------------------------*/ +/** + * @brief copy fc_func. + * @param - + * @retval - + * @note + */ +/*--------------------------------------------------*/ +void copy_fc_func(void) +{ + Copy_Routine(FLASH_API_RAM, FLASH_API_ROM, SIZE_FLASH_API); /* copy flash API to RAM */ + + return; +} + +/*--------------------------------------------------*/ +/** + * @brief copy user_data. + * @param - + * @retval - + * @note + */ +/*--------------------------------------------------*/ +void copy_user_data(char *data_a, char *data_b, uint32_t size) +{ + /* copy A to RAM */ + Copy_Routine(DEMO_A_RAM, (uint32_t *)data_a, size); + + /* copy B to RAM */ + Copy_Routine(DEMO_B_RAM, (uint32_t *)data_b, size); + + return; +} + +/*--------------------------------------------------*/ +/** + * @brief copy user_program. + * @param - + * @retval - + * @note + */ +/*--------------------------------------------------*/ +void copy_user_program(uint32_t size) +{ + /* copy A to RAM */ + Copy_Routine(DEMO_A_RAM, DEMO_A_FLASH, size); + + /* copy B to RAM */ + Copy_Routine(DEMO_B_RAM, DEMO_B_FLASH, size); + + return; +} + +/*--------------------------------------------------*/ +/** + * @brief rewrite_user_program. + * @param - + * @retval - + * @note + */ +/*--------------------------------------------------*/ +uint32_t rewrite_user_program(uint32_t size) +{ + uint32_t ret; + + ret = fc_write_code_flash(DEMO_B_RAM, DEMO_A_FLASH, size); + if (ret != TXZ_ERROR) { + ret = fc_write_code_flash(DEMO_A_RAM, DEMO_B_FLASH, size); + if (ret != TXZ_ERROR) { + ret = TXZ_SUCCESS; + } + } + + return (ret); +} + +#endif +/*--------------------------------------------------*/ +/** + * @brief Auto protect erase command of the code flash ROM. + * @param - + * @return Result. + * @retval TXZ_SUCCESS : Success. + * @retval TXZ_ERROR : Failure. + * @note It works in the inner RAM. + * This function protect specified block of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_protect_erase_code_flash(void) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum blocks. */ + fc_protect_erase_command(); + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief fc_write_page_data_flash. + * @param - + * @retval - + * @note + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_write_page_data_flash(uint32_t page, uint32_t size) +{ + uint32_t ret; + uint8_t SetData[4], Data; + uint32_t i; + + Data = 0; + for (i = 0; i < size; i += 0x4U) { + SetData[0] = Data++; + SetData[1] = Data++; + SetData[2] = Data++; + SetData[3] = Data++; + + ret = fc_write_data_flash((uint32_t *)SetData, + (uint32_t *)(fc_const_data_flash_address[page] + i), + 0x4); + } + + return (ret); +} + +/*--------------------------------------------------*/ +/** + * @brief Auro page erase command of the user information area. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified page of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_user_information_area(uint32_t User_Information_Area) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + fc_bank_change(FC_BANK_USER_INFO); + + /* Erases the specific page. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, + (uint32_t *)User_Information_Area, + FC_ERASE_KIND_PAGE); + /* Checks a blank of the specific page. */ + if (fc_blank_check((uint32_t *)User_Information_Area, FC_PAGE_SIZE) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + + fc_bank_change(FC_BANK_CODE_FLASH); + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Raed of the user information area. + * @param dst_address :destination address + * @param size :data size + * @retval - + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +void fc_read_user_information_area(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + fc_bank_change(FC_BANK_USER_INFO); + + { + char *d = (char *)dst_address; + char *s = (char *)src_address; + int i; + for (i = 0; i < size; i++) { + *d++ = *s++; + } + } + + fc_bank_change(FC_BANK_CODE_FLASH); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto write command of the user information area. + * @param src_address :source address + * @param size :data size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function writes 16bytes data to the code Flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_write_user_information_area(uint32_t *src_address, uint32_t size, uint32_t User_Information_Area) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + uint32_t i; + + fc_bank_change(FC_BANK_USER_INFO); + + /* Checks the code Flash ROM status */ + for (i = 0; i < size; i += (uint32_t)(0x10UL)) { + /* Writes 16bytes data. */ + fc_write_command((uint32_t *)((uint32_t)src_address + i), + (uint32_t *)((uint32_t)User_Information_Area - FC_CODE_FLASH_ADDRESS_TOP + i), + (uint32_t)(0x10UL)); + } + + /* Verifies user data and data of the Flash ROM. */ + retval = fc_verify_check(src_address, (uint32_t *)User_Information_Area, size); + + fc_bank_change(FC_BANK_CODE_FLASH); + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Enables the AREA0. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +__STATIC_INLINE uint32_t fc_enable_areasel(void) +{ + uint32_t retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; + + reg |= FC_AREASEL_AREA0; + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->AREASEL = reg; + + /* Confirms the FCAREASEL register the SSF0 was set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITE_MODE) == FC_AREASEL_WRITE_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Enables the AREA4. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +__STATIC_INLINE uint32_t fc_enable_areasel4(void) +{ + uint32_t retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA4; + + reg |= FC_AREASEL_AREA4; + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area4 */ + TSB_FC->AREASEL = reg; + + /* Confirms the FCAREASEL register the SSF4 was set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL4_WRITE_MODE) == FC_AREASEL4_WRITE_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Disables the AREA0. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +__STATIC_INLINE uint32_t fc_disable_areasel(void) +{ + uint32_t retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; + + reg |= FC_AREASEL_EXPECT_AREA0; + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->AREASEL = reg; + + /* Confirms the SSF0 of the FCAREASEL register is not set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITE_MODE) != FC_AREASEL_WRITE_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Disables the AREA4. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +__STATIC_INLINE uint32_t fc_disable_areasel4(void) +{ + uint32_t retval = TXZ_ERROR; + + + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area4 */ + TSB_FC->AREASEL = FC_AREASEL_EXPECT_AREA4; + + /* Confirms the SSF0 of the FCAREASEL register is not set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL4_WRITE_MODE) != FC_AREASEL4_WRITE_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Writes data of the Flash ROM. + * @param src_address + * @param dst_address + * @param size + * @return - + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + uint32_t retval; + volatile uint32_t *addr1; + volatile uint32_t *addr2; + volatile uint32_t *addr3; + uint32_t *source = (uint32_t *) src_address; + + if ((uint32_t)dst_address >= 0x30000000) { + addr1 = (uint32_t *)((uint32_t)FC_CODE_DATA_ADDRESS_TOP + FC_CMD_BC1_ADDR); + addr2 = (uint32_t *)((uint32_t)FC_CODE_DATA_ADDRESS_TOP + FC_CMD_BC2_ADDR); + addr3 = (uint32_t *)((uint32_t)dst_address); + /* Enables the AREA4. Write Mode. */ + retval = fc_enable_areasel4(); + } else { + addr1 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); + addr2 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); + addr3 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + (uint32_t)dst_address); + /* Enables the AREA0. Write Mode. */ + retval = fc_enable_areasel(); + } + + if (retval == TXZ_SUCCESS) { + uint32_t i; + + *addr1 = (0x000000AAUL); /* bus cycle 1 */ + *addr2 = (0x00000055UL); /* bus cycle 2 */ + if ((uint32_t)dst_address >= 0x30000000) { + *addr1 = (0x000000C0UL); /* bus cycle 3 */ + } else { + *addr1 = (0x000000A0UL); /* bus cycle 3 */ + } + for (i = (0UL); i < size; i += (0x4UL)) { + *addr3 = *source; + source++; + } + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {}; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) {}; + } + + if ((uint32_t)addr1 > 0x5E000000) { + /* Disables the AREA0. Read Mode. */ + retval = fc_disable_areasel(); + } else { + /* Disables the AREA4. Read Mode. */ + retval = fc_disable_areasel4(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Verifies data of the Flash ROM. + * @param src_address :source address + * @param dst_address :destination address + * @param size :data size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static uint32_t fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + char *s = (char *)src_address; + char *d = (char *)dst_address; + uint32_t i; + for (i = 0; i < size; i++) { + if (*s++ != *d++) { + return (TXZ_ERROR); + } + } + return (TXZ_SUCCESS); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto page erase command of the flash ROM. + * @param flash top address + * @param erase top address + * @param kind : Chip, Area, Block, Page, etc. + * @return - + * @note This function erases specified place of the flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind) +{ + uint32_t retval; + volatile uint32_t *addr1 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC1_ADDR); + volatile uint32_t *addr2 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC2_ADDR); + volatile uint32_t *addr3 = (uint32_t *) erase_top_address; + + if ((uint32_t)addr1 > 0x5E000000) { + /* Enables the AREA0. Write Mode. */ + retval = fc_enable_areasel(); + } else { + /* Enables the AREA4. Write Mode. */ + retval = fc_enable_areasel4(); + } + + if (retval == TXZ_SUCCESS) { + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr1 = (0x00000080UL); + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr3 = kind; + + /* Confirmation of the works start of ROM. */ + { + uint32_t busy_count = 0; + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + if (++busy_count > FC_BUSY_MAX_WAIT) { + break; + } + }; + } + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) { }; + } + if ((uint32_t)addr1 > 0x5E000000) { + /* Disables the AREA0. Read Mode. */ + retval = fc_disable_areasel(); + } else { + /* Disables the AREA4. Read Mode. */ + retval = fc_disable_areasel4(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Checks a blank of the Flash ROM every 4bytes. + * @param addrress + * @param size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static uint32_t fc_blank_check(uint32_t *address, uint32_t size) +{ + uint32_t retval = TXZ_SUCCESS; + uint32_t i; + + for (i = 0; i < (size / sizeof(uint32_t)); i++) { + uint32_t *addr = &address[i]; + if (*addr != FC_BRANK_VALUE) { + retval = TXZ_ERROR; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Get the status of the flash auto operation. + * @param status + * @return Result. + * @retval TXZ_BUSY : Busy. + * @retval TXZ_DONE : Done. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static uint32_t fc_get_status(fc_sr0_t status) +{ + uint32_t retval; + uint32_t work32; + + /* Reads the FCSR0. Masks the other specfic status */ + work32 = TSB_FC->SR0 & (uint32_t)status; + + /* Confirms the specific status of the flash ROM */ + if (work32 == (uint32_t)status) { + retval = TXZ_DONE; + } else { + retval = TXZ_BUSY; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto write command of the code flash ROM. + * @param src_address :source address + * @param dst_address :destination address + * @param size :data size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function writes 16bytes data to the code Flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + uint32_t i; + /* Checks the code Flash ROM status */ + for (i = 0; i < size; i += (uint32_t)(0x10UL)) { + /* Writes 16bytes data. */ + fc_write_command((uint32_t *)((uint32_t)src_address + i), + (uint32_t *)((uint32_t)dst_address + i), + (uint32_t)(0x10UL)); + } + + /* Verifies user data and data of the Flash ROM. */ + retval = fc_verify_check(src_address, dst_address, size); + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto page erase command of the code flash ROM. + * @param first_page : The first page to erase + * @param num_of_pages : The number of pages to erase. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified page of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum pages. */ + if ((first_page + num_of_pages) <= FC_MAX_PAGES) { + uint8_t i; + for (i = 0; i < num_of_pages; i++) { + /* Erases the specific page. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_code_flash_address[first_page + i], + FC_ERASE_KIND_PAGE); + } + /* Checks a blank of the specific page. */ + if (fc_blank_check((uint32_t *)fc_const_code_flash_address[first_page], + FC_PAGE_SIZE * (uint32_t)num_of_pages) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief copy 32-bit data from source to dest + * @param the address of source and dast, the data size + * @retval None. + * @note - + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size) +{ + uint32_t *dest_addr, *source_addr, tmpsize; + uint32_t i, tmps, tmpd, mask; + + dest_addr = dest; + source_addr = source; + + tmpsize = size >> 2U; + for (i = 0U; i < tmpsize; i++) { /* 32bits copy */ + *dest_addr = *source_addr; + dest_addr++; + source_addr++; + } + if (size & 0x00000003U) { /* if the last data size is not 0(maybe 1,2 or 3), copy the last data */ + mask = 0xFFFFFF00U; + i = size & 0x00000003U; + tmps = *source_addr; + tmpd = *dest_addr; + while (i - 1U) { + mask = mask << 8U; + i--; + } + tmps = tmps & (~mask); + tmpd = tmpd & (mask); + *dest_addr = tmps + tmpd; /* 32bits copy, but only change the bytes need to be changed */ + } else { + /* Do nothing */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief Auto page erase command of the data flash. + * @param first_page : The first page to erase + * @param num_of_pages : The number of pages to erase. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified page of the data Flash and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_page_data_flash(fc_data_flash_page_number_t first_page, uint8_t num_of_pages) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the data Flash status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum pages. */ + if ((first_page + num_of_pages) <= FC_MAX_DATA_PAGES) { + uint8_t i; + for (i = 0; i < num_of_pages; i++) { + /* Erases the specific page. */ + fc_erase_command((uint32_t *)FC_DATA_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_data_flash_address[first_page + i], + FC_ERASE_KIND_PAGE); + } + /* Checks a blank of the specific page. */ + if (fc_blank_check((uint32_t *)fc_const_data_flash_address[first_page], + FC_DATA_PAGE_SIZE * (uint32_t)num_of_pages) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto write command of the data flash. + * @param src_address :source address + * @param dst_address :destination address + * @param size :data size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function writes 16bytes data to the DATA Flash. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static uint32_t fc_write_data_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code DATA Flash status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + uint32_t i; + /* Checks the DATA Flash status */ + for (i = 0; i < size; i += (uint32_t)(0x4UL)) { + /* Writes 4bytes data. */ + fc_write_command((uint32_t *)((uint32_t)src_address + i), + (uint32_t *)((uint32_t)dst_address + i), + (uint32_t)(0x4UL)); + } + /* Verifies user data and data of the Flash ROM. */ + retval = fc_verify_check(src_address, dst_address, size); + } else { + retval = TXZ_BUSY; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto block erase command of the data flash. + * @param first_block : The first block to erase + * @param num_of_block : The number of blocks to erase. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified block of the data Flash and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_block_data_flash(fc_data_flash_block_number_t first_block, uint8_t num_of_block) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the data Flash status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + if ((first_block + num_of_block) <= FC_MAX_DATA_BLOCKS) { + uint8_t i; + for (i = 0; i < num_of_block; i++) { + /* Erases the specific block. */ + fc_erase_command((uint32_t *)FC_DATA_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_data_flash_block_address[first_block + i], + FC_ERASE_KIND_BLOCK); + } + /* Checks a blank of the specific block. */ + if (fc_blank_check((uint32_t *)fc_const_data_flash_block_address[first_block], + FC_DATA_BLOCK_SIZE * (uint32_t)num_of_block) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto area erase command of the data flash. + * @param area : The area block to erase + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified block of the data Flash and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_area_data_flash(fc_data_flash_area_number_t area) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the data Flash status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum blocks. */ + if (area == 0) { + /* Erases the specific block. */ + fc_erase_command((uint32_t *)FC_DATA_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_data_flash_area_address[area], + FC_ERASE_KIND_AREA); + /* Checks a blank of the specific block. */ + if (fc_blank_check((uint32_t *)fc_const_data_flash_area_address[area], FC_DATA_AREA_SIZE) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto protect page program command of the code flash ROM. + * @param page : The page to protect program + * @return Result. + * @retval TXZ_SUCCESS : Success. + * @retval TXZ_ERROR : Failure. + * @note It works in the inner RAM. + * This function protect specified block of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_protect_page_code_flash(fc_code_flash_page_number_t page) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum blocks. */ + if (page <= FC_CODE_FLASH_PAGE7) { + fc_protect_program_command(page, FC_PROTECT_KIND_PAGE); + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto protect block program command of the code flash ROM. + * @param block : The block to protect program + * @return Result. + * @retval TXZ_SUCCESS : Success. + * @retval TXZ_ERROR : Failure. + * @note It works in the inner RAM. + * This function protect specified block of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_protect_block_code_flash(fc_code_flash_block_number_t block) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum blocks. */ + if ((block >= FC_CODE_FLASH_BLOCK1) && (block <= FC_CODE_FLASH_BLOCK3)) { + fc_protect_program_command(block, FC_PROTECT_KIND_BLOCK); + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto ptotect bit program command of the flash ROM. + * @param protect_bit + * @param kind + * @return - + * @note This function protect specified place of the flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void fc_protect_program_command(uint32_t protect_bit, fc_protect_kind_t kind) +{ + uint32_t retval = TXZ_SUCCESS; + volatile uint32_t *addr1 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); + volatile uint32_t *addr2 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); + volatile uint32_t *addr3; + + if (kind == FC_PROTECT_KIND_PAGE) { + if (protect_bit <= 7) { + addr3 = (uint32_t *)(FC_CODE_FLASH_ADDRESS_TOP + FC_PROTECT_ADDR + (protect_bit << 4)); + } else { + retval = TXZ_ERROR; + } + } else if (kind == FC_PROTECT_KIND_BLOCK) { + if ((protect_bit >= 1) && (protect_bit <= 3)) { + addr3 = (uint32_t *)(FC_CODE_FLASH_ADDRESS_TOP + FC_PROTECT_ADDR + 0x80 + ((protect_bit - 1) << 4)); + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + if (retval == TXZ_SUCCESS) { + retval = fc_protect_mask_set(protect_bit, kind); + /* Enables the AREA0. Write Mode. */ + retval = fc_enable_areasel(); + + if (retval == TXZ_SUCCESS) { + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr1 = (0x0000009AUL); + *addr3 = (0x0000009AUL); + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {}; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) {}; + } + /* Disables the AREA0. Read Mode. */ + retval = fc_disable_areasel(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Auto ptotect bit erase command of the flash ROM. + * @param - + * @return - + * @note This function protect specified place of the flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void fc_protect_erase_command(void) +{ + uint32_t retval = TXZ_SUCCESS; + volatile uint32_t *addr1 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); + volatile uint32_t *addr2 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); + volatile uint32_t *addr3 = (uint32_t *)(FC_CODE_FLASH_ADDRESS_TOP + FC_PROTECT_ADDR); + + { + /* Enables the AREA0. Write Mode. */ + retval = fc_enable_areasel(); + + if (retval == TXZ_SUCCESS) { + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr1 = (0x00000080UL); + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr3 = (0x00000060UL); + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {}; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) {}; + } + /* Disables the AREA0. Read Mode. */ + retval = fc_disable_areasel(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Protect Mask Set. + * @param protect_bit + * @param kind + * @return Result. + * @retval TXZ_SUCCESS : Success. + * @retval TXZ_ERROR : Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +__STATIC_INLINE uint32_t fc_protect_mask_set(uint32_t protect_bit, fc_protect_kind_t kind) +{ + uint32_t retval = TXZ_ERROR; + uint32_t reg = 0xFFFFFFFF; + + if (kind == FC_PROTECT_KIND_PAGE) { + reg = (TSB_FC->PMR0) | (1 << protect_bit); + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->PMR0 = reg; + + retval = TXZ_SUCCESS; + } else if (kind == FC_PROTECT_KIND_BLOCK) { + reg = (TSB_FC->PMR1) | (1 << protect_bit); + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->PMR1 = reg; + + retval = TXZ_SUCCESS; + } + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto block erase command of the code flash ROM. + * @param first_block : The first block to erase + * @param num_of_block : The number of blocks to erase. + * @return Result. + * @retval TXZ_SUCCESS : Success. + * @retval TXZ_ERROR : Failure. + * @note It works in the inner RAM. + * This function erases specified block of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_block_code_flash(fc_code_flash_block_number_t first_block, uint8_t num_of_block) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + if ((first_block + num_of_block) <= FC_MAX_BLOCKS) { + uint8_t i; + for (i = 0; i < num_of_block; i++) { + /* Erases the specific block. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_code_flash_block_address[first_block + i], + FC_ERASE_KIND_BLOCK); + } + /* Checks a blank of the specific block. */ + if (fc_blank_check((uint32_t *)fc_const_code_flash_block_address[first_block], FC_BLOCK_SIZE * (uint32_t)num_of_block) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief bank change. + * @param bank : FC_BANK_USER_INFO, FC_BANK_CODE_FLASH + * @return - + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void fc_bank_change(uint32_t bank) +{ + if (bank == FC_BANK_USER_INFO) { + /* Flash Buffer disable */ + TSB_FC->BUFDISCLR = FC_BUFFER_DISABLE; + while (TSB_FC->BUFDISCLR != FC_BUFFER_DISABLE); + /* change user information area */ + TSB_FC->BNKCR = FC_BANK_USER_INFO; + while (TSB_FC->BNKCR != FC_BANK_USER_INFO); + } else if (bank == FC_BANK_CODE_FLASH) { + /* change code flash */ + TSB_FC->BNKCR = FC_BANK_CODE_FLASH; + while (TSB_FC->BNKCR != FC_BANK_CODE_FLASH); + /* Flash Buffer enable */ + TSB_FC->BUFDISCLR = FC_BUFFER_ENABLE; + while (TSB_FC->BUFDISCLR != FC_BUFFER_ENABLE); + } else { + /* do nothing */ + } +} + +/*--------------------------------------------------*/ + + +/** + * @} + */ /* End of group RDA_FLASH512UD32_Private_functions */ + +/** + * @} + */ /* End of group RDA_FLASH512UD32 */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__FLASH_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc.c new file mode 100644 index 00000000000..6e12fe28786 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc.c @@ -0,0 +1,714 @@ +/** + ******************************************************************************* + * @file txzp_adc.c + * @brief This file provides API functions for ADC driver. \n + * Channel Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_adc_include.h" +#include "txzp_adc.h" + +#if defined(__ADC_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup ADC + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ +#define WAIT_UNIT_1US ((uint32_t)(1000000)) /*!< 1S-1us transfor unit. */ +#define WAIT_FORLOOP_STEPS ((uint32_t)(5)) /*!< for loop steps. */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_fuctions ADC Private Fuctions + * @{ + */ +#ifdef DEBUG +__STATIC_INLINE int32_t check_param_convert_time(uint32_t param); +__STATIC_INLINE int32_t check_param_rcut(uint32_t param); +#endif +static void clear_ch_instance_info(adc_ch_t *p_ch); + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Convert time's parameter. + * @param param :Convert time's parameter + * @retval ADC_PARAM_OK :Valid + * @retval ADC_PARAM_NG :Invalid + * @note Macro definition is @ref ADC_CONVERT_TIME. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_convert_time(uint32_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_CONVERT_TIME_0_96_AVDD_4_5: + case ADC_CONVERT_TIME_0_91_AVDD_4_5: + case ADC_CONVERT_TIME_1_09_AVDD_4_5: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the AD RCUT's parameter. + * @param param :AD RCUT's parameter + * @retval ADC_PARAM_OK :Valid + * @retval ADC_PARAM_NG :Invalid + * @note Macro definition is @ref ADC_RCUT. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rcut(uint32_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_RCUT_NORMAL: + case ADC_RCUT_LOW: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +#endif + + +/*--------------------------------------------------*/ +/** + * @brief Channel Instance Information Clear. + * @param p_ch :Channel Instance Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +static void clear_ch_instance_info(adc_ch_t *p_ch) +{ + p_ch->p_tset = ADC_NULL; + p_ch->p_reg = ADC_NULL; + p_ch->init.type = ADC_CONVERSION_DISABLE; +} + +/** + * @} + */ /* End of group ADC_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup ADC_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the ADC object. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +void wait_m(uint32_t count) +{ + uint32_t i, steps; + + /*-----------------------------------------*/ + /* step : 1000000us = fsys :1 */ + /* step = EOSC_SYS_CLOCK/1000000 */ + /*-----------------------------------------*/ + /* system core clock update */ + SystemCoreClockUpdate(); + steps = count * (SystemCoreClock / WAIT_UNIT_1US) / WAIT_FORLOOP_STEPS; + + for (i = 0; i < steps; ++i) { + __NOP(); + } +} +TXZ_Result adc_init(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + /* Check the parameter. */ + assert_param(check_param_convert_time(p_obj->init.convert_time)); + assert_param(check_param_rcut(p_obj->init.rcut)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Init Variable */ + /*------------------------------*/ + { + uint32_t i; + + for (i = 0; i < ADC_NUM_MAX; i++) { + clear_ch_instance_info(&p_obj->info.ch[i]); + } + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + + switch (p_obj->init.convert_time) { + case ADC_CONVERT_TIME_0_96_AVDD_4_5: + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (p_obj->init.rcut | ADxMOD0_DACON_ON); + /*--- ADxCLK ---*/ + wait_m(3); + p_obj->p_instance->CLK = (ADxCLK_EXAZ0_0_96 | ADxCLK_VADCLK_4); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->EXAZSEL = 0; + p_obj->p_instance->MOD1 = ADxMOD1_TIME_0_96_AVDD_4_5; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = ADxMOD2; + break; + case ADC_CONVERT_TIME_0_91_AVDD_4_5: + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (p_obj->init.rcut | ADxMOD0_DACON_ON); + /*--- ADxCLK ---*/ + wait_m(3); + p_obj->p_instance->CLK = (ADxCLK_EXAZ0_0_91_1_09 | ADxCLK_VADCLK_4); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->EXAZSEL = 0; + p_obj->p_instance->MOD1 = ADxMOD1_TIME_0_91_AVDD_4_5; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = ADxMOD2; + break; + case ADC_CONVERT_TIME_1_09_AVDD_4_5: + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (p_obj->init.rcut | ADxMOD0_DACON_ON); + /*--- ADxCLK ---*/ + wait_m(3); + p_obj->p_instance->CLK = (ADxCLK_EXAZ0_0_91_1_09 | ADxCLK_VADCLK_8); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->EXAZSEL = 0; + p_obj->p_instance->MOD1 = ADxMOD1_TIME_1_09_AVDD_4_5; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = ADxMOD2; + break; + default: + result = TXZ_ERROR; + /* no process */ + break; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the ADC object. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_deinit(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + /*------------------------------*/ + /* Wait Stop */ + /*------------------------------*/ + /*--- ADxST ---*/ + /* When all convetion stop, ADxST is set "0". */ + while (p_obj->p_instance->ST != 0) { + /* no processing */ + } + /*------------------------------*/ + /* Channel Class Destruct */ + /*------------------------------*/ + { + uint32_t i; + adc_ch_t *p_ch; + + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type == ADC_CONVERSION_DISABLE) { + if (adc_ch_deinit(p_ch) == TXZ_SUCCESS) { + clear_ch_instance_info(p_ch); + } + } + } + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCMPEN ---*/ + p_obj->p_instance->CMPEN = (ADxCMPEN_CMP1EN_DISABLE | ADxCMPEN_CMP0EN_DISABLE); + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_IREF_CUT | ADxMOD0_DACON_OFF); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief ADC Channel Setting. + * @param p_obj :ADC object. + * @param ch :Channel. Range is (value < ADC_NUM_MAX). + * @param p_setting :Channel Setting Source Address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_setting)); + /* Check the parameter. */ + assert_param(check_param_channel(ch, ADC_NUM_MAX)); + assert_param(check_param_ain(p_setting->ain, ADC_AIN_RANGE_MIN, ADC_AIN_RANGE_MAX)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Channel Class Construct */ + /*------------------------------*/ + { + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + p_ch->p_tset = (__IO uint32_t *)(&p_obj->p_instance->TSET0 + ch); + p_ch->p_reg = (__I uint32_t *)(&p_obj->p_instance->REG0 + ch); + p_ch->init.interrupt = ADC_INT_DISABLE; + p_ch->init.type = ADC_CONVERSION_SGL; + p_ch->init.ain = p_setting->ain; + result = adc_ch_init(p_ch); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief ADC Channel Clear. + * @param p_obj :ADC object. + * @param ch :Channel. Range is (value < ADC_NUM_MAX). + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + /* Check the parameter. */ + assert_param(check_param_channel(ch, ADC_NUM_MAX)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Channel Class Destruct */ + /*------------------------------*/ + { + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + result = adc_ch_deinit(p_ch); + /* Init Variable */ + clear_ch_instance_info(p_ch); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get AD value. + * @param p_obj :ADC object. + * @param ch :Channel. Range is (value < ADC_NUM_MAX). + * @param p_value :AD value. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_value)); + /* Check the parameter. */ + assert_param(check_param_channel(ch, ADC_NUM_MAX)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Get Value */ + /*------------------------------*/ + { + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + result = adc_ch_get_value(p_ch, p_value); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Start blocking single conversion. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_start(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Enable Conversion */ + /*------------------------------*/ + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Stop blocking single conversion. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_stop(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Conversion */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + /*------------------------------*/ + /* Wait Stop */ + /*------------------------------*/ + /*--- ADxST ---*/ + /* When all convetion stop, ADxST is set "0". */ + while (p_obj->p_instance->ST != 0) { + /* no processing */ + } + /*------------------------------*/ + /* Dummy Read */ + /*------------------------------*/ + /* Read is needed before the next convertion. */ + { + uint32_t i; + adc_ch_t *p_ch; + uint32_t value; + + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type == ADC_CONVERSION_DISABLE) { + if (adc_ch_get_value(p_ch, &value) != TXZ_SUCCESS) { + /* no processing */ + } + } + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Start non-blocking single conversion. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_startIt(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Interrupt Setting */ + /*------------------------------*/ + { + uint32_t i; + adc_ch_t *p_ch; + adc_ch_t *p_chInt = ADC_NULL; + + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type != ADC_CONVERSION_DISABLE) { + if (adc_ch_int_disable(p_ch) != TXZ_SUCCESS) { + result = TXZ_ERROR; + } + p_chInt = p_ch; + } + } + /* Last Channel Number: Enable Interrupt */ + if (p_chInt != ADC_NULL) { + if (adc_ch_int_enable(p_chInt) != TXZ_SUCCESS) { + result = TXZ_ERROR; + } + } + } + /*------------------------------*/ + /* Enable Conversion */ + /*------------------------------*/ + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Stop non-blocking single conversion. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_stopIt(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Stop Conversion */ + /*------------------------------*/ + result = adc_stop(p_obj); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for single conversion done. + * @param p_obj :ADC object. + * @retval - + * @note Call by Single Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_irq_handler(adc_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->handler != ADC_NULL) { + p_obj->handler(p_obj->init.id, TXZ_SUCCESS); + } +} +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__ADC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc_ch.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc_ch.c new file mode 100644 index 00000000000..f2c020d0b32 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc_ch.c @@ -0,0 +1,350 @@ +/** + ******************************************************************************* + * @file txzp_adc_ch.c + * @brief This file provides API functions for ADC driver. \n + * Channel Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_adc_include.h" +#include "txzp_adc_ch.h" + +#if defined(__ADC_CH_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup ADC + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_fuctions ADC Private Fuctions + * @{ + */ +#ifdef DEBUG +/* no define */ +#endif +__STATIC_INLINE uint32_t get_conversion_data(uint32_t reg); + +#ifdef DEBUG +/* no define */ +#endif +/*--------------------------------------------------*/ +/** + * @brief Get convertion data from ADxREGn. + * @param reg : ADxREGn data. + * @retval Convertion data. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t get_conversion_data(uint32_t reg) +{ + uint32_t result = (uint32_t)((reg & ADxREGn_ADRn_MASK) >> 4); + + return (result); +} +/** + * @} + */ /* End of group ADC_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup ADC_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the ADC Channel object. + * @param p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_init(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_tset)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_reg)); + /* Check the parameter. */ + /* No check */ +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxREGx ---*/ + /* Read is needed before the next convertion. */ + { + volatile uint32_t reg; + reg = *p_obj->p_reg; + } + /*--- ADxTSET ---*/ + *p_obj->p_tset = (p_obj->init.interrupt | p_obj->init.type | p_obj->init.ain); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the ADC Channel object. + * @param p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + *p_obj->p_tset = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_DISABLE | 0); + /*--- ADxREGx ---*/ + /* Read is needed before the next convertion. */ + { + volatile uint32_t reg; + reg = *p_obj->p_reg; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt. + * @param p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_tset)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_reg)); + /* Check the parameter. */ + /* No check */ +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + { + uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); + + *p_obj->p_tset = (tset | ADxTSETn_ENINT_ENABLE); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable Interrupt. + * @param p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_tset)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_reg)); + /* Check the parameter. */ + /* No check */ +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + { + uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); + + *p_obj->p_tset = (tset | ADxTSETn_ENINT_DISABLE); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get conversion value. + * @param p_obj :ADC Channel object. + * @param p_value :AD value. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has done. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) +{ + TXZ_Result result = TXZ_ERROR; + uint32_t reg = *p_obj->p_reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Check Result */ + /*------------------------------*/ + if ((reg & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { + *p_value = get_conversion_data(reg); + result = TXZ_SUCCESS; + } + + return (result); +} +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__ADC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_cg.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_cg.c new file mode 100644 index 00000000000..d24ed481109 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_cg.c @@ -0,0 +1,287 @@ +/** + ******************************************************************************* + * @file txzp_cg.c + * @brief This file provides API functions for CG driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_cg.h" + +#if defined(__CG_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup CG + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ +#define CG_FSYS_MASK ((uint32_t)0x00070000) /*!< CG FSYS mask */ + +#define CG_FSYS_1 ((uint32_t)0x00000000) /*!< CG fc register value */ +#define CG_FSYS_2 ((uint32_t)0x00010000) /*!< CG fc/2 register value */ +#define CG_FSYS_4 ((uint32_t)0x00020000) /*!< CG fc/4 register value */ +#define CG_FSYS_8 ((uint32_t)0x00030000) /*!< CG fc/8 register value */ +#define CG_FSYS_16 ((uint32_t)0x00040000) /*!< CG fc/16 register value */ + +#define CG_FSYS_1_MUL ((uint32_t)0x00000001) /*!< CG fc multiplication value */ +#define CG_FSYS_2_MUL ((uint32_t)0x00000002) /*!< CG fc/2 multiplication value */ +#define CG_FSYS_4_MUL ((uint32_t)0x00000004) /*!< CG fc/4 multiplication value */ +#define CG_FSYS_8_MUL ((uint32_t)0x00000008) /*!< CG fc/8 multiplication value */ +#define CG_FSYS_16_MUL ((uint32_t)0x00000010) /*!< CG fc/16 multiplication value */ + +#define CG_PRCKST_MASK ((uint32_t)0x0F000000) /*!< CG PRCKST mask */ + +#define CG_PRCKST_1 ((uint32_t)0x00000000) /*!< CG T0 fc register status */ +#define CG_PRCKST_2 ((uint32_t)0x01000000) /*!< CG T0 fc/2 register status */ +#define CG_PRCKST_4 ((uint32_t)0x02000000) /*!< CG T0 fc/4 register status */ +#define CG_PRCKST_8 ((uint32_t)0x03000000) /*!< CG T0 fc/8 register status */ +#define CG_PRCKST_16 ((uint32_t)0x04000000) /*!< CG T0 fc/16 register status */ +#define CG_PRCKST_32 ((uint32_t)0x05000000) /*!< CG T0 fc/32 register status */ +#define CG_PRCKST_64 ((uint32_t)0x06000000) /*!< CG T0 fc/64 register status */ +#define CG_PRCKST_128 ((uint32_t)0x07000000) /*!< CG T0 fc/128 register status */ +#define CG_PRCKST_256 ((uint32_t)0x08000000) /*!< CG T0 fc/256 register status */ +#define CG_PRCKST_512 ((uint32_t)0x09000000) /*!< CG T0 fc/512 register status */ + +#define CG_PRCK_1_DIV ((uint32_t)0x00000001) /*!< CG T0 fc division value */ +#define CG_PRCK_2_DIV ((uint32_t)0x00000002) /*!< CG T0 fc/2 division value */ +#define CG_PRCK_4_DIV ((uint32_t)0x00000004) /*!< CG T0 fc/4 division value */ +#define CG_PRCK_8_DIV ((uint32_t)0x00000008) /*!< CG T0 fc/8 division value */ +#define CG_PRCK_16_DIV ((uint32_t)0x00000010) /*!< CG T0 fc/16 division value */ +#define CG_PRCK_32_DIV ((uint32_t)0x00000020) /*!< CG T0 fc/32 division value */ +#define CG_PRCK_64_DIV ((uint32_t)0x00000040) /*!< CG T0 fc/64 division value */ +#define CG_PRCK_128_DIV ((uint32_t)0x00000080) /*!< CG T0 fc/128 division value */ +#define CG_PRCK_256_DIV ((uint32_t)0x00000100) /*!< CG T0 fc/256 division value */ +#define CG_PRCK_512_DIV ((uint32_t)0x00000200) /*!< CG T0 fc/512 division value */ + + +#define CG_MCKSELPST_MASK ((uint32_t)0xC0000000) /*!< CG MCKSEL mask */ + +#define CG_MCKSELPST_1 ((uint32_t)0x00000000) /*!< CG T0 fc/PRCK value */ +#define CG_MCKSELPST_2 ((uint32_t)0x40000000) /*!< CG T0 fc/PRCK/2 value */ +#define CG_MCKSELPST_4 ((uint32_t)0x80000000) /*!< CG T0 fc/PRCK/4 value */ + +#define CG_FSYSM_1_DIV ((uint32_t)0x00000001) /*!< CG fsysm T0 division value */ +#define CG_FSYSM_2_DIV ((uint32_t)0x00000002) /*!< CG fsysm T0/2 division value */ +#define CG_FSYSM_4_DIV ((uint32_t)0x00000004) /*!< CG fsysm T0/4 division value */ + +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_typedef CG Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_fuctions CG Private Fuctions + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_functions CG Exported Functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Update Middle PrescalerClock according register values. + * @param p_obj :CG object. + * @retval Middle PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_mphyt0(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + /* Get Gear status. */ + switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) { + case CG_FSYS_1: /* Gear -> fc */ + result = SystemCoreClock * CG_FSYS_1_MUL; + break; + case CG_FSYS_2: /* Gear -> fc/2 */ + result = SystemCoreClock * CG_FSYS_2_MUL; + break; + case CG_FSYS_4: /* Gear -> fc/4 */ + result = SystemCoreClock * CG_FSYS_4_MUL; + break; + case CG_FSYS_8: /* Gear -> fc/8 */ + result = SystemCoreClock * CG_FSYS_8_MUL; + break; + case CG_FSYS_16: /* Gear -> fc/16 */ + result = SystemCoreClock * CG_FSYS_16_MUL; + break; + default: + result = 0U; + break; + } + switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) { + case CG_PRCKST_1: /* T0 -> fc */ + result /= CG_PRCK_1_DIV; + break; + case CG_PRCKST_2: /* T0 -> fc/2 */ + result /= CG_PRCK_2_DIV; + break; + case CG_PRCKST_4: /* T0 -> fc/4 */ + result /= CG_PRCK_4_DIV; + break; + case CG_PRCKST_8: /* T0 -> fc/8 */ + result /= CG_PRCK_8_DIV; + break; + case CG_PRCKST_16: /* T0 -> fc/16 */ + result /= CG_PRCK_16_DIV; + break; + case CG_PRCKST_32: /* T0 -> fc/32 */ + result /= CG_PRCK_32_DIV; + break; + case CG_PRCKST_64: /* T0 -> fc/64 */ + result /= CG_PRCK_64_DIV; + break; + case CG_PRCKST_128: /* T0 -> fc/128 */ + result /= CG_PRCK_128_DIV; + break; + case CG_PRCKST_256: /* T0 -> fc/256 */ + result /= CG_PRCK_256_DIV; + break; + case CG_PRCKST_512: /* T0 -> fc/512 */ + result /= CG_PRCK_512_DIV; + break; + default: + result = 0U; + break; + } + + switch (p_obj->p_instance->SYSCR & CG_MCKSELPST_MASK) { + case CG_MCKSELPST_1: /* T0 -> fc/PRCK */ + result /= CG_FSYSM_1_DIV; + break; + case CG_MCKSELPST_2: /* T0 -> fc/PRCK/2 */ + result /= CG_FSYSM_2_DIV; + break; + case CG_MCKSELPST_4: /* T0 -> fc/PRCK/4 */ + result /= CG_FSYSM_4_DIV; + break; + default: + result = 0U; + break; + } + return (result); +} + +/** + * @} + */ /* End of group CG_Exported_functions */ + +/** + * @} + */ /* End of group CG */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__CG_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_gpio.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_gpio.c new file mode 100644 index 00000000000..8c385e9e03f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_gpio.c @@ -0,0 +1,1813 @@ +/** + ******************************************************************************* + * @file txzp_gpio.c + * @brief This file provides API functions for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ + +#include "txzp_gpio.h" + +#if defined(__GPIO_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup GPIO + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_define GPIO Private Define + * @{ + */ +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name Bit Operation Macro + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PORT_BASE (0x400E0000UL) /*!< Port Register Base Adress */ +#define BITBAND_PORT_OFFSET (0x0000100UL) /*!< Port Register Offset Value */ +#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) /*!< Operational target Port Adress */ +#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /*!< Operational target Control Register Adress */ +#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)(base)) |= (uint32_t)(0x0000001UL<< (bitnum))) /*!< Target Pin Bit set */ +#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)(base)) &= ~((uint32_t)(0x0000001UL<< (bitnum)))) /*!< Target Pin Bit clear */ +#define BITBAND_PORT_READ(val, base, bitnum) ((val) = ((*((__IO uint32_t *)(base)) & (uint32_t)((0x0000001UL)<< (bitnum))) >> (bitnum))) /*!< Target Pin Bit read */ +/** + * @} + */ /* End of Bit Operation Macro */ +/** + * @} + */ /* End of group GPIO_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_define GPIO Private Define + * @{ + */ + +#define GPIO_THRESHOLD 12 +#define GPIO_OFFSET 3 + +/** + * @} + */ /* End of group GPIO_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_typedef GPIO Private Typedef + * @{ + */ + +/*! + * @brief Pin Exist Table + * @details Bit0 :GPIO_Mode_DATA + * @details Bit1 :GPIO_Mode_CR + * @details Bit2 :GPIO_Mode_FR1 + * @details Bit3 :GPIO_Mode_FR2 + + * @details Bit4 :GPIO_Mode_FR3 + * @details Bit5 :GPIO_Mode_FR4 + * @details Bit6 :GPIO_Mode_FR5 + * @details Bit7 :GPIO_Mode_FR6 + + * @details Bit8 :GPIO_Mode_FR7 + * @details Bit9 :GPIO_Mode_OD + * @details Bit10 :GPIO_Mode_PUP + * @details Bit11 :GPIO_Mode_PDN + + * @details Bit12 :GPIO_Mode_IE + */ + +static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = { + /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ + { 0x1E27, 0x1E27, 0x1FE7, 0x1F67, 0x1F27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_A */ + { 0x1E23, 0x1E23, 0x1E23, 0x1E23, 0x1E23, 0x1E23, 0x1E23, 0x1E63 }, /** GPIO_PORT_B */ + { 0x1EFF, 0x1EFF, 0x1FD3, 0x1F53, 0x1E1F, 0x1E1F, 0x1ED3, 0x1E53 }, /** GPIO_PORT_C */ + { 0x1E23, 0x1E23, 0x1E67, 0x1EFF, 0x1EBB, 0x1EA3, 0x0000, 0x0000 }, /** GPIO_PORT_D */ + { 0x1E83, 0x1EE3, 0x1EE3, 0x1EE3, 0x1EA3, 0x1EA3, 0x1EA3, 0x1F83 }, /** GPIO_PORT_E */ + { 0x1F6F, 0x1F6F, 0x1F63, 0x1FEF, 0x1FFF, 0x1FF3, 0x1F3F, 0x1F3F }, /** GPIO_PORT_F */ + { 0x1E63, 0x1E67, 0x1E67, 0x1E27, 0x1E27, 0x1E27, 0x1E07, 0x0000 }, /** GPIO_PORT_G */ + { 0x1803, 0x1803, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_H */ + { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x0000, 0x0000 }, /** GPIO_PORT_J */ + { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_K */ + { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_L */ + { 0x1E03, 0x1E03, 0x1E03, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_M */ + { 0x1FFF, 0x1FFF, 0x1EE7, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_N */ + { 0x1FBF, 0x1FFF, 0x1EE3, 0x1EE7, 0x1EE7, 0x1EEF, 0x1ECF, 0x1F83 }, /** GPIO_PORT_U */ + { 0x1E2B, 0x1E0F, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_V */ +}; + +/** + * @} + */ /* End of group GPIO_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_fuctions GPIO Private Fuctions + * @{ + */ + +#ifdef DEBUG +__INLINE static int32_t check_param_port_num(uint32_t param); +__INLINE static int32_t check_param_port_mode(uint32_t param); +#endif +static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); +static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Port Number. + * @param param :Port Number parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref gpio_num_t +*/ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_port_num(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case GPIO_PORT_0: + case GPIO_PORT_1: + case GPIO_PORT_2: + case GPIO_PORT_3: + case GPIO_PORT_4: + case GPIO_PORT_5: + case GPIO_PORT_6: + case GPIO_PORT_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Port Mode. + * @param param :Port Mode parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref gpio_mode_t +*/ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_port_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case GPIO_Mode_DATA: + case GPIO_Mode_CR: + case GPIO_Mode_FR1: + case GPIO_Mode_FR2: + case GPIO_Mode_FR3: + case GPIO_Mode_FR4: + case GPIO_Mode_FR5: + case GPIO_Mode_FR6: + case GPIO_Mode_FR7: + case GPIO_Mode_OD: + case GPIO_Mode_PUP: + case GPIO_Mode_PDN: + case GPIO_Mode_IE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + return (result); +} +#endif + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_pin_exist(gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) + * @brief Check the Pin Exist. + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + */ +/*--------------------------------------------------*/ + +static uint8_t change_mode_to_num(uint32_t mode) +{ + uint8_t retVal = 0; + + if (mode == GPIO_Mode_DATA) { + retVal = 0; + } else if (mode == GPIO_Mode_CR) { + retVal = 1; + } else if (mode == GPIO_Mode_FR1) { + retVal = 2; + } else if (mode == GPIO_Mode_FR2) { + retVal = 3; + } else if (mode == GPIO_Mode_FR3) { + retVal = 4; + } else if (mode == GPIO_Mode_FR4) { + retVal = 5; + } else if (mode == GPIO_Mode_FR5) { + retVal = 6; + } else if (mode == GPIO_Mode_FR6) { + retVal = 7; + } else if (mode == GPIO_Mode_FR7) { + retVal = 8; + } else if (mode == GPIO_Mode_OD) { + retVal = 9; + } else if (mode == GPIO_Mode_PUP) { + retVal = 10; + } else if (mode == GPIO_Mode_PDN) { + retVal = 11; + } else if (mode == GPIO_Mode_IE) { + retVal = 12; + } else { + retVal = 13; + } + + return retVal; +} + +static uint8_t change_func_to_num(uint32_t mode) +{ + uint8_t retVal = 0; + + if (mode == GPIO_FR_1) { + retVal = 2; + } else if (mode == GPIO_FR_2) { + retVal = 3; + } else if (mode == GPIO_FR_3) { + retVal = 4; + } else if (mode == GPIO_FR_4) { + retVal = 5; + } else if (mode == GPIO_FR_5) { + retVal = 6; + } else if (mode == GPIO_FR_6) { + retVal = 7; + } else if (mode == GPIO_FR_7) { + retVal = 8; + } else if (mode == GPIO_FR_NA) { + retVal = 1; + } else if (mode == 0) { + retVal = 1; + } else { + retVal = 13; + } + + return retVal; +} + +static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) +{ + int32_t result = PARAM_NG; + uint8_t chgmode; + uint16_t tmp; + + chgmode = change_mode_to_num(mode); + if ((chgmode < 13) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) { + tmp = (PinExistTbl[group][num] >> chgmode) & 0x01; + result = PARAM_OK; + if (tmp == 0) { + result = PARAM_NG; + } + } else { + result = PARAM_NG; + } + + return (result); +} +static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) +{ + int32_t result = PARAM_NG; + uint8_t chgfunc; + uint16_t tmp; + + chgfunc = change_func_to_num(mode); + /* param check skip if func is INPUT or OUTPUT */ + if (chgfunc == 1) { + return (PARAM_OK); + } + if ((chgfunc < 13) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) { + tmp = (PinExistTbl[group][num] >> chgfunc) & 0x01; + result = PARAM_OK; + if (tmp == 0) { + result = PARAM_NG; + } + } else { + result = PARAM_NG; + } + + return (result); +} +/** + * @} + */ /* End of group GPIO_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup GPIO_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the GPIO object. + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + switch (group) { + case GPIO_PORT_A: + p_obj->p_pa_instance->DATA = 0x00; + p_obj->p_pa_instance->CR = 0x00; + p_obj->p_pa_instance->FR1 = 0x00; + p_obj->p_pa_instance->FR4 = 0x00; + p_obj->p_pa_instance->FR5 = 0x00; + p_obj->p_pa_instance->FR6 = 0x00; + p_obj->p_pa_instance->FR7 = 0x00; + p_obj->p_pa_instance->OD = 0x00; + p_obj->p_pa_instance->PUP = 0x00; + p_obj->p_pa_instance->PDN = 0x00; + p_obj->p_pa_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA00 = 1U; + break; + case GPIO_PORT_B: + p_obj->p_pb_instance->DATA = 0x00; + p_obj->p_pb_instance->CR = 0x00; + p_obj->p_pb_instance->FR4 = 0x00; + p_obj->p_pb_instance->OD = 0x00; + p_obj->p_pb_instance->PUP = 0x00; + p_obj->p_pb_instance->PDN = 0x00; + p_obj->p_pb_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA01 = 1U; + break; + case GPIO_PORT_C: + p_obj->p_pc_instance->DATA = 0x00; + p_obj->p_pc_instance->CR = 0x00; + p_obj->p_pc_instance->FR1 = 0x00; + p_obj->p_pc_instance->FR2 = 0x00; + p_obj->p_pc_instance->FR3 = 0x00; + p_obj->p_pc_instance->FR4 = 0x00; + p_obj->p_pc_instance->FR5 = 0x00; + p_obj->p_pc_instance->FR6 = 0x00; + p_obj->p_pc_instance->FR7 = 0x00; + p_obj->p_pc_instance->OD = 0x00; + p_obj->p_pc_instance->PUP = 0x00; + p_obj->p_pc_instance->PDN = 0x00; + p_obj->p_pc_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA02 = 1U; + break; + case GPIO_PORT_D: + p_obj->p_pd_instance->DATA = 0x00; + p_obj->p_pd_instance->CR = 0x00; + p_obj->p_pd_instance->FR1 = 0x00; + p_obj->p_pd_instance->FR2 = 0x00; + p_obj->p_pd_instance->FR3 = 0x00; + p_obj->p_pd_instance->FR4 = 0x00; + p_obj->p_pd_instance->FR5 = 0x00; + p_obj->p_pd_instance->FR6 = 0x00; + p_obj->p_pd_instance->OD = 0x00; + p_obj->p_pd_instance->PUP = 0x00; + p_obj->p_pd_instance->PDN = 0x00; + p_obj->p_pd_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA03 = 1U; + break; + case GPIO_PORT_E: + p_obj->p_pe_instance->DATA = 0x00; + p_obj->p_pe_instance->CR = 0x00; + p_obj->p_pe_instance->FR4 = 0x00; + p_obj->p_pe_instance->FR5 = 0x00; + p_obj->p_pe_instance->FR6 = 0x00; + p_obj->p_pe_instance->FR7 = 0x00; + p_obj->p_pe_instance->OD = 0x00; + p_obj->p_pe_instance->PUP = 0x00; + p_obj->p_pe_instance->PDN = 0x00; + p_obj->p_pe_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA04 = 1U; + break; + case GPIO_PORT_F: + p_obj->p_pf_instance->DATA = 0x00; + p_obj->p_pf_instance->CR = 0x00; + p_obj->p_pf_instance->FR1 = 0x00; + p_obj->p_pf_instance->FR2 = 0x00; + p_obj->p_pf_instance->FR3 = 0x00; + p_obj->p_pf_instance->FR4 = 0x00; + p_obj->p_pf_instance->FR5 = 0x00; + p_obj->p_pf_instance->FR6 = 0x00; + p_obj->p_pf_instance->FR7 = 0x00; + p_obj->p_pf_instance->OD = 0x00; + p_obj->p_pf_instance->PUP = 0x00; + p_obj->p_pf_instance->PDN = 0x00; + p_obj->p_pf_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA05 = 1U; + break; + case GPIO_PORT_G: + p_obj->p_pg_instance->DATA = 0x00; + p_obj->p_pg_instance->CR = 0x00; + p_obj->p_pg_instance->FR1 = 0x00; + p_obj->p_pg_instance->FR4 = 0x00; + p_obj->p_pg_instance->FR5 = 0x00; + p_obj->p_pg_instance->OD = 0x00; + p_obj->p_pg_instance->PUP = 0x00; + p_obj->p_pg_instance->PDN = 0x00; + p_obj->p_pg_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA06 = 1U; + break; + case GPIO_PORT_H: + p_obj->p_ph_instance->DATA = 0x00; + p_obj->p_ph_instance->PDN = 0x00; + p_obj->p_ph_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA07 = 1U; + break; + case GPIO_PORT_J: + p_obj->p_pj_instance->DATA = 0x00; + p_obj->p_pj_instance->CR = 0x00; + p_obj->p_pj_instance->OD = 0x00; + p_obj->p_pj_instance->PUP = 0x00; + p_obj->p_pj_instance->PDN = 0x00; + p_obj->p_pj_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA08 = 1U; + break; + case GPIO_PORT_K: + p_obj->p_pk_instance->DATA = 0x00; + p_obj->p_pk_instance->CR = 0x06; + p_obj->p_pk_instance->OD = 0x00; + p_obj->p_pk_instance->PUP = 0x15; + p_obj->p_pk_instance->PDN = 0x08; + p_obj->p_pk_instance->IE = 0x1D; + TSB_CG_FSYSMENA_IPMENA09 = 1U; + break; + case GPIO_PORT_L: + p_obj->p_pl_instance->DATA = 0x00; + p_obj->p_pl_instance->CR = 0x00; + p_obj->p_pl_instance->OD = 0x00; + p_obj->p_pl_instance->PUP = 0x00; + p_obj->p_pl_instance->PDN = 0x00; + p_obj->p_pl_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA10 = 1U; + break; + case GPIO_PORT_M: + p_obj->p_pm_instance->DATA = 0x00; + p_obj->p_pm_instance->CR = 0x00; + p_obj->p_pm_instance->OD = 0x00; + p_obj->p_pm_instance->PUP = 0x00; + p_obj->p_pm_instance->PDN = 0x00; + p_obj->p_pm_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA11 = 1U; + break; + case GPIO_PORT_N: + p_obj->p_pn_instance->DATA = 0x00; + p_obj->p_pn_instance->CR = 0x00; + p_obj->p_pn_instance->FR1 = 0x00; + p_obj->p_pn_instance->FR2 = 0x00; + p_obj->p_pn_instance->FR3 = 0x00; + p_obj->p_pn_instance->FR4 = 0x00; + p_obj->p_pn_instance->FR5 = 0x00; + p_obj->p_pn_instance->FR6 = 0x00; + p_obj->p_pn_instance->FR7 = 0x00; + p_obj->p_pn_instance->OD = 0x00; + p_obj->p_pn_instance->PUP = 0x00; + p_obj->p_pn_instance->PDN = 0x00; + p_obj->p_pn_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA12 = 1U; + break; + case GPIO_PORT_U: + p_obj->p_pu_instance->DATA = 0x00; + p_obj->p_pu_instance->CR = 0x00; + p_obj->p_pu_instance->FR1 = 0x00; + p_obj->p_pu_instance->FR2 = 0x00; + p_obj->p_pu_instance->FR3 = 0x00; + p_obj->p_pu_instance->FR4 = 0x00; + p_obj->p_pu_instance->FR5 = 0x00; + p_obj->p_pu_instance->FR6 = 0x00; + p_obj->p_pu_instance->FR7 = 0x00; + p_obj->p_pu_instance->OD = 0x00; + p_obj->p_pu_instance->PUP = 0x00; + p_obj->p_pu_instance->PDN = 0x00; + p_obj->p_pu_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA16 = 1U; + break; + case GPIO_PORT_V: + p_obj->p_pv_instance->DATA = 0x00; + p_obj->p_pv_instance->CR = 0x00; + p_obj->p_pv_instance->FR1 = 0x00; + p_obj->p_pv_instance->FR2 = 0x00; + p_obj->p_pv_instance->FR4 = 0x00; + p_obj->p_pv_instance->OD = 0x00; + p_obj->p_pv_instance->PUP = 0x00; + p_obj->p_pv_instance->PDN = 0x00; + p_obj->p_pv_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA17 = 1U; + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the GPIO object. + * @param p_obj :GPIO object. + * @param group :GPIO Port Group.: Use @ref gpio_gr_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (group) { + case GPIO_PORT_A: + p_obj->p_pa_instance->DATA = 0x00; + p_obj->p_pa_instance->CR = 0x00; + p_obj->p_pa_instance->FR1 = 0x00; + p_obj->p_pa_instance->FR4 = 0x00; + p_obj->p_pa_instance->FR5 = 0x00; + p_obj->p_pa_instance->FR6 = 0x00; + p_obj->p_pa_instance->FR7 = 0x00; + p_obj->p_pa_instance->OD = 0x00; + p_obj->p_pa_instance->PUP = 0x00; + p_obj->p_pa_instance->PDN = 0x00; + p_obj->p_pa_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA00 = 0U; + break; + case GPIO_PORT_B: + p_obj->p_pb_instance->DATA = 0x00; + p_obj->p_pb_instance->CR = 0x00; + p_obj->p_pb_instance->FR4 = 0x00; + p_obj->p_pb_instance->OD = 0x00; + p_obj->p_pb_instance->PUP = 0x00; + p_obj->p_pb_instance->PDN = 0x00; + p_obj->p_pb_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA01 = 0U; + break; + case GPIO_PORT_C: + p_obj->p_pc_instance->DATA = 0x00; + p_obj->p_pc_instance->CR = 0x00; + p_obj->p_pc_instance->FR1 = 0x00; + p_obj->p_pc_instance->FR2 = 0x00; + p_obj->p_pc_instance->FR3 = 0x00; + p_obj->p_pc_instance->FR4 = 0x00; + p_obj->p_pc_instance->FR5 = 0x00; + p_obj->p_pc_instance->FR6 = 0x00; + p_obj->p_pc_instance->FR7 = 0x00; + p_obj->p_pc_instance->OD = 0x00; + p_obj->p_pc_instance->PUP = 0x00; + p_obj->p_pc_instance->PDN = 0x00; + p_obj->p_pc_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA02 = 0U; + break; + case GPIO_PORT_D: + p_obj->p_pd_instance->DATA = 0x00; + p_obj->p_pd_instance->CR = 0x00; + p_obj->p_pd_instance->FR1 = 0x00; + p_obj->p_pd_instance->FR2 = 0x00; + p_obj->p_pd_instance->FR3 = 0x00; + p_obj->p_pd_instance->FR4 = 0x00; + p_obj->p_pd_instance->FR5 = 0x00; + p_obj->p_pd_instance->FR6 = 0x00; + p_obj->p_pd_instance->OD = 0x00; + p_obj->p_pd_instance->PUP = 0x00; + p_obj->p_pd_instance->PDN = 0x00; + p_obj->p_pd_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA03 = 0U; + break; + case GPIO_PORT_E: + p_obj->p_pe_instance->DATA = 0x00; + p_obj->p_pe_instance->CR = 0x00; + p_obj->p_pe_instance->FR4 = 0x00; + p_obj->p_pe_instance->FR5 = 0x00; + p_obj->p_pe_instance->FR6 = 0x00; + p_obj->p_pe_instance->FR7 = 0x00; + p_obj->p_pe_instance->OD = 0x00; + p_obj->p_pe_instance->PUP = 0x00; + p_obj->p_pe_instance->PDN = 0x00; + p_obj->p_pe_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA04 = 0U; + break; + case GPIO_PORT_F: + p_obj->p_pf_instance->DATA = 0x00; + p_obj->p_pf_instance->CR = 0x00; + p_obj->p_pf_instance->FR1 = 0x00; + p_obj->p_pf_instance->FR2 = 0x00; + p_obj->p_pf_instance->FR3 = 0x00; + p_obj->p_pf_instance->FR4 = 0x00; + p_obj->p_pf_instance->FR5 = 0x00; + p_obj->p_pf_instance->FR6 = 0x00; + p_obj->p_pf_instance->FR7 = 0x00; + p_obj->p_pf_instance->OD = 0x00; + p_obj->p_pf_instance->PUP = 0x00; + p_obj->p_pf_instance->PDN = 0x00; + p_obj->p_pf_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA05 = 0U; + break; + case GPIO_PORT_G: + p_obj->p_pg_instance->DATA = 0x00; + p_obj->p_pg_instance->CR = 0x00; + p_obj->p_pg_instance->FR1 = 0x00; + p_obj->p_pg_instance->FR4 = 0x00; + p_obj->p_pg_instance->FR5 = 0x00; + p_obj->p_pg_instance->OD = 0x00; + p_obj->p_pg_instance->PUP = 0x00; + p_obj->p_pg_instance->PDN = 0x00; + p_obj->p_pg_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA06 = 0U; + break; + case GPIO_PORT_H: + p_obj->p_ph_instance->DATA = 0x00; + p_obj->p_ph_instance->PDN = 0x00; + p_obj->p_ph_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA07 = 0U; + break; + case GPIO_PORT_J: + p_obj->p_pj_instance->DATA = 0x00; + p_obj->p_pj_instance->CR = 0x00; + p_obj->p_pj_instance->OD = 0x00; + p_obj->p_pj_instance->PUP = 0x00; + p_obj->p_pj_instance->PDN = 0x00; + p_obj->p_pj_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA08 = 0U; + break; + case GPIO_PORT_K: + p_obj->p_pk_instance->DATA = 0x00; + p_obj->p_pk_instance->CR = 0x06; + p_obj->p_pk_instance->OD = 0x00; + p_obj->p_pk_instance->PUP = 0x15; + p_obj->p_pk_instance->PDN = 0x08; + p_obj->p_pk_instance->IE = 0x1D; + TSB_CG_FSYSMENA_IPMENA09 = 0U; + break; + case GPIO_PORT_L: + p_obj->p_pl_instance->DATA = 0x00; + p_obj->p_pl_instance->CR = 0x00; + p_obj->p_pl_instance->OD = 0x00; + p_obj->p_pl_instance->PUP = 0x00; + p_obj->p_pl_instance->PDN = 0x00; + p_obj->p_pl_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA10 = 0U; + break; + case GPIO_PORT_M: + p_obj->p_pm_instance->DATA = 0x00; + p_obj->p_pm_instance->CR = 0x00; + p_obj->p_pm_instance->OD = 0x00; + p_obj->p_pm_instance->PUP = 0x00; + p_obj->p_pm_instance->PDN = 0x00; + p_obj->p_pm_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA11 = 0U; + break; + case GPIO_PORT_N: + p_obj->p_pn_instance->DATA = 0x00; + p_obj->p_pn_instance->CR = 0x00; + p_obj->p_pn_instance->FR1 = 0x00; + p_obj->p_pn_instance->FR2 = 0x00; + p_obj->p_pn_instance->FR3 = 0x00; + p_obj->p_pn_instance->FR4 = 0x00; + p_obj->p_pn_instance->FR5 = 0x00; + p_obj->p_pn_instance->FR6 = 0x00; + p_obj->p_pn_instance->FR7 = 0x00; + p_obj->p_pn_instance->OD = 0x00; + p_obj->p_pn_instance->PUP = 0x00; + p_obj->p_pn_instance->PDN = 0x00; + p_obj->p_pn_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA12 = 0U; + break; + case GPIO_PORT_U: + p_obj->p_pu_instance->DATA = 0x00; + p_obj->p_pu_instance->CR = 0x00; + p_obj->p_pu_instance->FR1 = 0x00; + p_obj->p_pu_instance->FR2 = 0x00; + p_obj->p_pu_instance->FR3 = 0x00; + p_obj->p_pu_instance->FR4 = 0x00; + p_obj->p_pu_instance->FR5 = 0x00; + p_obj->p_pu_instance->FR6 = 0x00; + p_obj->p_pu_instance->FR7 = 0x00; + p_obj->p_pu_instance->OD = 0x00; + p_obj->p_pu_instance->PUP = 0x00; + p_obj->p_pu_instance->PDN = 0x00; + p_obj->p_pu_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA16 = 0U; + break; + case GPIO_PORT_V: + p_obj->p_pv_instance->DATA = 0x00; + p_obj->p_pv_instance->CR = 0x00; + p_obj->p_pv_instance->FR1 = 0x00; + p_obj->p_pv_instance->FR2 = 0x00; + p_obj->p_pv_instance->FR4 = 0x00; + p_obj->p_pv_instance->OD = 0x00; + p_obj->p_pv_instance->PUP = 0x00; + p_obj->p_pv_instance->PDN = 0x00; + p_obj->p_pv_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA17 = 0U; + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Port Mode Write + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param mode :GPIO Port Mode. : Use @ref gpio_num_t + * @param val :value + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t i; + int32_t param_result = PARAM_NG; +#ifdef DEBUG + /* Check the parameters */ + check_param_port_mode(mode); + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(&p_obj)); +#endif + + /* Check the parameters, the NULL of address */ + for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) { + param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); + if (param_result == PARAM_OK) { + break; + } else { + result = TXZ_ERROR; + } + } + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + return (result); + } + + switch (group) { + case GPIO_PORT_A: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pa_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pa_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pa_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pa_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pa_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pa_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pa_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pa_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pa_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pa_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pa_instance->IE = val; + } + break; + case GPIO_PORT_B: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pb_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pb_instance->CR = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pb_instance->FR4 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pb_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pb_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pb_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pb_instance->IE = val; + } + break; + case GPIO_PORT_C: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pc_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pc_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pc_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pc_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR3) { + p_obj->p_pc_instance->FR3 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pc_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pc_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pc_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pc_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pc_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pc_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pc_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pc_instance->IE = val; + } + break; + case GPIO_PORT_D: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pd_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pd_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pd_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pd_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR3) { + p_obj->p_pd_instance->FR3 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pd_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pd_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pd_instance->FR6 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pd_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pd_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pd_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pd_instance->IE = val; + } + break; + case GPIO_PORT_E: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pe_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pe_instance->CR = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pe_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pe_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pe_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pe_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pe_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pe_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pe_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pe_instance->IE = val; + } + break; + case GPIO_PORT_F: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pf_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pf_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pf_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pf_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR3) { + p_obj->p_pf_instance->FR3 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pf_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pf_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pf_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pf_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pf_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pf_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pf_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pf_instance->IE = val; + } + break; + case GPIO_PORT_G: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pg_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pg_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pg_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pg_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pg_instance->FR5 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pg_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pg_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pg_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pg_instance->IE = val; + } + break; + case GPIO_PORT_H: + if (mode == GPIO_Mode_DATA) { + p_obj->p_ph_instance->DATA = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_ph_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_ph_instance->IE = val; + } + break; + case GPIO_PORT_J: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pj_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pj_instance->CR = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pj_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pj_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pj_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pj_instance->IE = val; + } + break; + case GPIO_PORT_K: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pk_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pk_instance->CR = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pk_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pk_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pk_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pk_instance->IE = val; + } + break; + case GPIO_PORT_L: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pl_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pl_instance->CR = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pl_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pl_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pl_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pl_instance->IE = val; + } + break; + case GPIO_PORT_M: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pm_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pm_instance->CR = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pm_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pm_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pm_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pm_instance->IE = val; + } + break; + case GPIO_PORT_N: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pn_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pn_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pn_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pn_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR3) { + p_obj->p_pn_instance->FR3 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pn_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pn_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pn_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pn_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pn_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pn_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pn_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pn_instance->IE = val; + } + break; + case GPIO_PORT_U: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pu_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pu_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pu_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pu_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR3) { + p_obj->p_pu_instance->FR3 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pu_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pu_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pu_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pu_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pu_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pu_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pu_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pu_instance->IE = val; + } + break; + case GPIO_PORT_V: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pv_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pv_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pv_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pv_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pv_instance->FR4 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pv_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pv_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pv_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pv_instance->IE = val; + } + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @fn TXZ_Result gpio_read_mode(gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) + * @brief Port Mode Read + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t + * @param[out] val :value store address + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t param_result = PARAM_NG; + uint32_t i; +#ifdef DEBUG + /* Check the parameters */ + check_param_port_mode(mode); + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + /* Check the parameters, the NULL of address */ + for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) { + param_result = (int32_t)check_param_pin_exist(p_obj, group, i, mode); + if (param_result == PARAM_OK) { + break; + } else { + /* No Process */ + } + } + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + return (result); + } + + switch (group) { + case GPIO_PORT_A: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pa_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pa_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pa_instance->FR1 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pa_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pa_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pa_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pa_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pa_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pa_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pa_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pa_instance->IE ; + } + break; + case GPIO_PORT_B: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pb_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pb_instance->CR ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pb_instance->FR4 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pb_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pb_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pb_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pb_instance->IE ; + } + break; + case GPIO_PORT_C: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pc_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pc_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pc_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pc_instance->FR2 ; + } else if (mode == GPIO_Mode_FR3) { + *val = p_obj->p_pc_instance->FR3 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pc_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pc_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pc_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pc_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pc_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pc_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pc_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pc_instance->IE ; + } + break; + case GPIO_PORT_D: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pd_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pd_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pd_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pd_instance->FR2 ; + } else if (mode == GPIO_Mode_FR3) { + *val = p_obj->p_pd_instance->FR3 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pd_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pd_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pd_instance->FR6 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pd_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pd_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pd_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pd_instance->IE ; + } + break; + case GPIO_PORT_E: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pe_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pe_instance->CR ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pe_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pe_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pe_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pe_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pe_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pe_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pe_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pe_instance->IE ; + } + break; + case GPIO_PORT_F: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pf_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pf_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pf_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pf_instance->FR2 ; + } else if (mode == GPIO_Mode_FR3) { + *val = p_obj->p_pf_instance->FR3 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pf_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pf_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pf_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pf_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pf_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pf_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pf_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pf_instance->IE ; + } + break; + case GPIO_PORT_G: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pg_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pg_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pg_instance->FR1 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pg_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pg_instance->FR5 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pg_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pg_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pg_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pg_instance->IE; + } + break; + case GPIO_PORT_H: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_ph_instance->DATA; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_ph_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_ph_instance->IE ; + } + break; + case GPIO_PORT_J: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pj_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pj_instance->CR ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pj_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pj_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pj_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pj_instance->IE ; + } + break; + case GPIO_PORT_K: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pk_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pk_instance->CR ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pk_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pk_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pk_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pk_instance->IE ; + } + break; + case GPIO_PORT_L: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pl_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pl_instance->CR ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pl_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pl_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pl_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pl_instance->IE ; + } + break; + case GPIO_PORT_M: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pm_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pm_instance->CR ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pm_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pm_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pm_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pm_instance->IE ; + } + break; + case GPIO_PORT_N: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pn_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pn_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pn_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pn_instance->FR2 ; + } else if (mode == GPIO_Mode_FR3) { + *val = p_obj->p_pn_instance->FR3 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pn_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pn_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pn_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pn_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pn_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pn_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pn_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pn_instance->IE ; + } + break; + case GPIO_PORT_U: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pu_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pu_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pu_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pu_instance->FR2 ; + } else if (mode == GPIO_Mode_FR3) { + *val = p_obj->p_pu_instance->FR3 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pu_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pu_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pu_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pu_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pu_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pu_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pu_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pu_instance->IE ; + } + break; + case GPIO_PORT_V: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pv_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pv_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pv_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pv_instance->FR2 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pv_instance->FR4 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pv_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pv_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pv_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pv_instance->IE ; + } + break; + default: + result = TXZ_ERROR; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Port Function switching + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param func :GPIO Portxx Func. : Use @ref gpio_pa0_func_t - @ref gpio_pl4_func_t + * @param inout :GPIO bit Value.: Use @ref gpio_pinstate_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_func(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t func, uint32_t inout) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t param_result = PARAM_NG; + uint32_t port_base; + uint32_t mode_base; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + param_result = check_param_func_pin_exist(p_obj, group, num, func); + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + return (result); + } + + if (group > GPIO_THRESHOLD) { + group += GPIO_OFFSET; + } + + port_base = BITBAND_PORT_BASE(group); + + /* Initialization PxFR OFF */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_CLR(mode_base, num); + + /* Initialize Input */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + + switch (func) { + case 0: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 1: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 2: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 3: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 4: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 5: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 6: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 7: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Port Bit Write + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t base; +#ifdef DEBUG + /* Check the parameters */ + check_param_port_num(num); + check_param_port_mode(mode); +#endif + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + return (result); + } + if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) { + result = TXZ_ERROR; + return (result); + } + + if (group > GPIO_THRESHOLD) { + group += GPIO_OFFSET; + } + + base = BITBAND_PORT_BASE(group); + base = BITBAND_PORT_MODE_BASE(base, mode); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(base, num); + } else { + BITBAND_PORT_CLR(base, num); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @fn TXZ_Result gpio_read_bit(gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) + * @brief Port Bit Read + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @param[out] *pinstate : store Value of GPIO BitPin. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing.: Use @ref gpio_pinstate_t + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t base; + uint32_t val; +#ifdef DEBUG + /* Check the parameters */ + check_param_port_num(num); + check_param_port_mode(mode); +#endif + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + return (result); + } + if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) { + result = TXZ_ERROR; + return (result); + } + + if (group > GPIO_THRESHOLD) { + group += GPIO_OFFSET; + } + + base = BITBAND_PORT_BASE(group); + base = BITBAND_PORT_MODE_BASE(base, mode); + BITBAND_PORT_READ(val, base, num); + if (val == GPIO_PIN_RESET) { + *pinstate = GPIO_PIN_RESET; + } else if (val == GPIO_PIN_SET) { + *pinstate = GPIO_PIN_SET; + } else { + result = TXZ_ERROR; + } + + return result; +} + +/** + * @} + */ /* End of group GPIO_Exported_functions */ + +/** + * @} + */ /* End of group GPIO */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__GPIO_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c.c new file mode 100644 index 00000000000..1874ede5986 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c.c @@ -0,0 +1,414 @@ +/** + ******************************************************************************* + * @file txzp_i2c.c + * @brief This file provides API functions for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_i2c.h" + +#if defined(__I2C_H) + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_variables + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_variables */ + +/*------------------------------------------------------------------------------*/ +/* Const Table */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_const + * @{ + */ +/*----------------------------------*/ +/** + * @brief SCK Divider value table. + * @details SCK = b000 - b111. + * @note NFSEL=0 (Digital Setting) Divider value. +*/ +/*----------------------------------*/ +static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20, 24, 32, 48, 80, 144, 272, 528 }; +static const uint32_t I2C_SCK_LOW_MUL_TBL[8] = { 12, 14, 18, 26, 42, 74, 138, 266 }; + +/** + * @} + */ /* End of group UTILITIES_Private_const */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Initializing I2C Regester + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_init(I2C_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + p_obj->p_instance->CR2 = I2CxCR2_I2CM_ENABLE; + p_obj->p_instance->OP = I2CxOP_INIT; + p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); + p_obj->p_instance->AR = I2CxAR_INIT; + p_obj->p_instance->AR2 = I2CxAR2_INIT; + p_obj->p_instance->CR2 = I2CxCR2_INIT; + p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); + p_obj->p_instance->IE = I2CxIE_CLEAR; +} + +/*--------------------------------------------------*/ +/** + * @brief Generate start condition + * @param p_obj :I2C object. + * @param data :Slave address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_start_condition(I2C_t *p_obj, uint32_t data) +{ + __IO uint32_t opreg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + opreg = p_obj->p_instance->OP; + opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); + if (I2C_master(p_obj)) { + if ((p_obj->p_instance->SR & I2CxSR_BB)) { + opreg |= I2CxOP_SREN; + } + } + p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); + p_obj->p_instance->OP = opreg; + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); + p_obj->p_instance->CR2 = I2CxCR2_START_CONDITION; +} + +/*--------------------------------------------------*/ +/** + * @brief Return the I2c clock setting + * @param p_obj :I2C object. + * @param frequency :Maximum frequency. + * @param fsys :SystemCoreClock. + * @param p_setting :Clock data pointer. + * @retval Non-zero :Scl frequency. + * @retval 0 :Error. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting) +{ + uint32_t result = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_setting)); +#endif /* #ifdef DEBUG */ + + if (frequency <= 1000000) { + uint64_t sck, tmp_sck; + uint64_t prsck, tmp_prsck; + uint64_t fscl, tmp_fscl; + uint64_t fx; + uint64_t max_fx, min_fx; + uint64_t low_width, low_width_min; + + sck = tmp_sck = 0; + prsck = tmp_prsck = 1; + fscl = tmp_fscl = 0; + + if (frequency <= 400000) { + max_fx = 11428572U; /* Tpresck: 87.5ns 1/87.5 = 0.0114285714 */ + min_fx = 6666666U; /* Tpresck:150.0ns 1/150 = 0.0066666667 */ + low_width_min = 1600; + } else { + max_fx = 26666667U; /* Tpresck:37.5ns 1/37.5 = 0.0266666667 */ + min_fx = 15384615U; /* Tpresck:65.0ns 1/65 = 0.0153846154 */ + low_width_min = 675; + } + for (prsck = 1; prsck <= 32; prsck++) { + fx = ((uint64_t)fsys / prsck); + + if ((fx < max_fx) && (fx >= min_fx)) { + for (sck = 0; sck <= 7; sck++) { + low_width = (uint64_t)(1000000000 * prsck * I2C_SCK_LOW_MUL_TBL[sck]) / fsys; + if (low_width < low_width_min) { + continue; + } + fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); + + if ((fscl <= frequency) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + tmp_sck = sck; + tmp_prsck = (prsck < 32) ? prsck : 0; + } + } + } + } + result = (uint32_t)tmp_fscl; + p_setting->sck = (uint32_t)tmp_sck; + p_setting->prsck = (tmp_prsck < 32) ? (uint32_t)tmp_prsck : 0; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Slave mode setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_slave_init(I2C_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + p_obj->p_instance->OP = I2CxOP_SLAVE_INIT; + p_obj->p_instance->CR1 = (I2CxCR1_ACK | p_obj->init.clock.sck); + p_obj->p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + p_obj->p_instance->CR2 = I2CxCR2_INIT; + p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); +} +#if defined(I2CSxWUP_EN) +/*--------------------------------------------------*/ +/** + * @brief I2C Wakeup Control setting. + * @param p_obj :I2CS object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_init(I2CS_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + p_obj->p_instance->WUPCR1 = (p_obj->init.wup.sgcdi | p_obj->init.wup.ack | p_obj->init.wup.reset | p_obj->init.wup.intend); +} + +/*--------------------------------------------------*/ +/** + * @brief Primary Slave Address setting. + * @param p_obj :I2CS object. + * @param addr :Primary Slave Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + p_obj->p_instance->WUPCR2 = (0x0000000E & adr); +} + +/*--------------------------------------------------*/ +/** + * @brief Secondary Slave Address setting. + * @param p_obj :I2CS object. + * @param addr :Secondary Slave Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + p_obj->p_instance->WUPCR3 = (0x0000000E & adr); + p_obj->p_instance->WUPCR3 |= 0x00000001; /* WUPSA2EN: Secondary Slave Address Use Setting */ +} +#endif +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#endif /* defined(__I2C_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c_api.c new file mode 100644 index 00000000000..2e3c4b35f93 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c_api.c @@ -0,0 +1,1381 @@ +/** + ******************************************************************************* + * @file txzp_i2c_api.c + * @brief This file provides API functions for BSP I2C driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_i2c_api.h" + +#if defined(__I2C_API_H) + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define I2C_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define I2C_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name timeout + * @brief This timeouts are not based on accurate values, this just guarantee that + the application will not remain stuck if the I2C communication is corrupted. + * @{ + */ +#define I2C_TIMEOUT (100000) /*>! fail safe. */ + +/** + * @} + */ /* End of name timeout */ + +#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ +#define I2C_CH0 (0) /*!< I2C Channel 0. */ +#define I2C_CH1 (1) /*!< I2C Channel 1. */ +#define I2C_CH2 (2) /*!< I2C Channel 2. */ +#define I2C_CH3 (3) /*!< I2C Channel 3. */ +#define I2C_CH4 (4) /*!< I2C Channel 3. */ +#define I2C_CH_NUM (5) /*!< Number of I2C Channel. */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ +/*----------------------------------*/ +/** + * @brief Transfer State. +*/ +/*----------------------------------*/ +enum { + I2C_TRANSFER_STATE_IDLE = 0U, /*!< Idle. */ + I2C_TRANSFER_STATE_BUSY /*!< Busy. */ +} TransferState; + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief For IRQn_Type number definition. +*/ +/*----------------------------------*/ +typedef struct { + IRQn_Type i2c; + IRQn_Type al; + IRQn_Type bf; + IRQn_Type na; +} i2c_irq_t; + +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_variables + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_variables */ + +/*------------------------------------------------------------------------------*/ +/* Const Table */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_const + * @{ + */ +/*----------------------------------*/ +/** + * @brief Channel 0 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = { + { INTI2C0NST_IRQn, INTI2C0ATX_IRQn, INTI2C0BRX_IRQn, INTI2C0NA_IRQn } +}; + +/** + * @} + */ /* End of group UTILITIES_Private_const */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +#ifdef DEBUG +__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn); +__STATIC_INLINE int32_t check_param_address(int32_t address); +#endif +__STATIC_INLINE void enable_irq(uint32_t irqn); +__STATIC_INLINE void disable_irq(uint32_t irqn); +__STATIC_INLINE void clear_irq(uint32_t irqn); +__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn); +__STATIC_INLINE void reset_asynch(_i2c_t *p_obj); +__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj); +static void i2c_irq_handler(_i2c_t *p_obj); +static void i2c_slave_irq_handler(_i2c_t *p_obj); + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Compare the IRQn's parameter. + * @param irqn :I2C IRQn List. + * @retval I2C_PARAM_OK :Available. + * @retval I2C_PARAM_NG :Not Available. + * @note -. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn) +{ + int32_t result = I2C_PARAM_NG; + + if (irqn == (uint32_t)&I2C_CH0_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH1_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH2_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH3_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH4_IRQN_TBL) { + result = I2C_PARAM_OK; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Compare the Slave address's parameter. + * @param address :Address. + * @retval I2C_PARAM_OK :Available. + * @retval I2C_PARAM_NG :Not Available. + * @note Here, 10bit address has not supported. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_address(int32_t address) +{ + int32_t result = I2C_PARAM_NG; + + if ((address >= 0) && (address <= 255)) { + result = I2C_PARAM_OK; + } + return (result); +} +#endif + +/*--------------------------------------------------*/ +/** + * @brief Enable I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_EnableIRQ(p_irqn->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_DisableIRQ(p_irqn->i2c); + NVIC_DisableIRQ(p_irqn->al); + NVIC_DisableIRQ(p_irqn->bf); + NVIC_DisableIRQ(p_irqn->na); +} + +/*--------------------------------------------------*/ +/** + * @brief ClearPending I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void clear_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_ClearPendingIRQ(p_irqn->i2c); + NVIC_ClearPendingIRQ(p_irqn->al); + NVIC_ClearPendingIRQ(p_irqn->bf); + NVIC_ClearPendingIRQ(p_irqn->na); +} +/*--------------------------------------------------*/ +/** + * @brief Reset Asynch Transfer + * @param p_obj :i2c object + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void reset_asynch(_i2c_t *p_obj) +{ + disable_irq(p_obj->info.irqn); + I2C_disable_interrupt(&p_obj->i2c); +} + +__STATIC_INLINE int32_t I2C_status_arbitration(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); +#endif +} +/*--------------------------------------------------*/ +/** + * @brief Waiting i2c status + * @param p_obj :i2c object + * @retval 0 :Success. + * @retval -1 :Failure. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj) +{ + int32_t timeout; + + timeout = I2C_TIMEOUT; + while (!I2C_int_status(&p_obj->i2c)) { + if (I2C_status_arbitration(&p_obj->i2c)) { + volatile uint32_t dummy = 0; + dummy = I2C_read_data(&p_obj->i2c); + return (-5); + } + if ((timeout--) == 0) { + return (-1); + } + } + if (I2C_status_arbitration(&p_obj->i2c)) { + volatile uint32_t dummy = 0; + dummy = I2C_read_data(&p_obj->i2c); + return (-5); + } + return (0); +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Transfer handler + * @param p_obj :i2c object. + * @retval - + * @note Called by i2c_irq_handler_asynch_t. + */ +/*--------------------------------------------------*/ +static void i2c_irq_handler(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + + if ((!I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) { + p_obj->info.asynch.event = I2C_EVENT_ERROR; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + if (I2C_transmitter(&p_obj->i2c)) { + int32_t start = I2C_restart(&p_obj->i2c); + + if (!I2C_get_ack(&p_obj->i2c)) { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); + } else if (p_obj->rx_buff.length != 0) { + I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U)); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + if (p_obj->tx_buff.pos == 0) { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else if (p_obj->rx_buff.length != 0) { + if (p_obj->tx_buff.pos == 0) { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } else { + int32_t start = I2C_restart(&p_obj->i2c); + + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + if (!start) { + p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + } + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1) ? 0 : 1))); + I2C_write_data(&p_obj->i2c, 0); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Transfer handler + * @param p_obj :i2c object. + * @retval - + * @note Called by i2c_slave_irq_handler_asynch_t. + */ +/*--------------------------------------------------*/ +static void i2c_slave_irq_handler(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + + if ((I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) { + p_obj->info.asynch.event = I2C_EVENT_ERROR; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + int32_t start = I2C_slave_detected(&p_obj->i2c); + if (start) { + uint8_t sa = (uint8_t)I2C_read_data(&p_obj->i2c); + } + if (I2C_transmitter(&p_obj->i2c)) { + if (!I2C_get_ack(&p_obj->i2c)) { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); + } else { + /* dummy, wait nack */ + I2C_write_data(&p_obj->i2c, 0); + } + } else { + /* error event not be set */ + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + if (!start) { + p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + } + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1) ? 0 : 1))); + I2C_write_data(&p_obj->i2c, 0); + } else { + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + I2C_slave_init(&p_obj->i2c); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Enable I2C IRQ + * @param p_obj :i2c object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void i2c_enable_irq(_i2c_t *p_obj) +{ + enable_irq(p_obj->info.irqn); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable I2C IRQ + * @param p_obj :i2c object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void i2c_disable_irq(_i2c_t *p_obj) +{ + disable_irq(p_obj->info.irqn); +} + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Reset I2C peripheral + * @param p_obj :i2c object. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_reset_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + /* Software reset */ + I2C_reset(&p_obj->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure the I2C frequency + * @param p_obj :i2c object. + * @param hz :frequency in Hz. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_port_high(&p_obj->i2c)) { + uint32_t fval; + + SystemCoreClockUpdate(); + + fval = I2C_get_clock_setting(&p_obj->i2c, (uint32_t)hz, SystemCoreClock, &p_obj->i2c.init.clock); + if (fval != 0) { + //I2C_init(&p_obj->i2c); + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + p_obj->info.asynch.address = 0; + p_obj->info.asynch.stop = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + p_obj->info.asynch.event = 0; + p_obj->tx_buff.p_buffer = I2C_NULL; + p_obj->tx_buff.length = 0; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = I2C_NULL; + p_obj->rx_buff.length = 0; + p_obj->rx_buff.pos = 0; + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check bus free on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + p_obj->info.bus_free = 1; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Creates a start condition on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure.(now, not use) + * @note Start condition is not generate yet, after this function returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_start_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + p_obj->info.start = 1; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Creates a stop condition on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_stop_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t timeout; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_stop_condition(&p_obj->i2c); + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + + timeout = I2C_TIMEOUT; + while (i2c_active_t(p_obj)) { + if ((timeout--) == 0) { + result = TXZ_ERROR; + break; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking reading data + * @param p_obj :i2c object. + * @param address :Slave address(7-bit) and last bit is 0. + * @param p_data :Address of Read data. + * @param length :Number of the bytes to read. + * @param stop :Stop to be generated after the transfer is done. + * @retval Number of read bytes. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) +{ + int32_t result = 0; + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + if (length > 0) { + /* Start Condition */ + if (i2c_start_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + result = i2c_byte_write_t(p_obj, (int32_t)((uint32_t)address | 1U)); + if (result == I2C_ACK) { + /* Read all bytes */ + while (count < length) { + int32_t data = i2c_byte_read_t(p_obj, ((count < (length - 1)) ? 0 : 1)); + if (data < 0) { + result = data; + break; + } + p_data[count++] = (uint8_t)data; + } + result = count; + } else if (result == I2C_ERROR_ARBITRATION) { + } else if (result == (-2)) { //I2C_ERROR_BUS_BUSY + } else { + stop = 1; + result = (-1) ;//I2C_ERROR_NO_SLAVE; + } + /* Stop Condition */ + if (stop) { + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking sending data + * @param p_obj :i2c object. + * @param address :Slave address(7-bit) and last bit is 0. + * @param p_data :Destination address of Write data. + * @param length :Number of the bytes to write. + * @param stop :Stop to be generated after the transfer is done. + * @retval Number of write bytes. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) +{ + int32_t result = 0; + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + /* Start Condition */ + if (i2c_start_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + result = i2c_byte_write_t(p_obj, address); + if (result == I2C_ACK) { + /* Write all bytes */ + while (count < length) { + int32_t data = i2c_byte_write_t(p_obj, (int32_t)p_data[count++]); + if (data < I2C_ACK) { + result = data; + break; + } + } + if (result >= 0) { + result = count; + } + } else if (result == I2C_ERROR_ARBITRATION) { + } else if (result == (-2)) { //I2C_ERROR_BUS_BUSY + } else { + stop = 1; + result = (-1); //I2C_ERROR_NO_SLAVE; + } + /* Stop Condition */ + if (stop) { + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Read one byte + * @param p_obj :i2c object. + * @param last :last acknowledge. + * @retval The read byte (but -1 is timout error). + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last) +{ + int32_t result; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + I2C_set_ack(&p_obj->i2c, last); + I2C_write_data(&p_obj->i2c, 0); + result = wait_status(p_obj); + if (result < 0) { + // result = -1; + } else { + result = (int32_t)I2C_read_data(&p_obj->i2c); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Write one byte + * @param p_obj :i2c object. + * @param data :Write data. + * @retval 0 :NACK was received. + * @retval 1 :ACK was received. + * @retval -1 :Timout error. + * @note Macro definition of return values is @ref I2C_ACK. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data) +{ + int32_t result; + int32_t timeout; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + if (p_obj->info.start == 1) { + p_obj->info.start = 0; + if (p_obj->info.bus_free == 1) { + timeout = I2C_TIMEOUT; + while (i2c_active_t(p_obj)) { + if ((timeout--) == 0) { + p_obj->info.bus_free = 0; + return (-1); + } + } + } + /* Start Condition */ + I2C_start_condition(&p_obj->i2c, (uint32_t)data); + if ((p_obj->info.bus_free == 1) && (!I2C_master(&p_obj->i2c))) { + p_obj->i2c.p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + p_obj->info.bus_free = 0; + if (I2C_status_arbitration(&p_obj->i2c)) { + return (-5); + } + return (-2); + } + } else { + I2C_write_data(&p_obj->i2c, (uint32_t)data); + } + p_obj->info.bus_free = 0; + result = wait_status(p_obj); + if (result < 0) { + return (result); + } + if (!I2C_get_ack(&p_obj->i2c)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Attempts to determine if the I2C bus is already in use + * @param p_obj :i2c object. + * @retval 0 :Non-active. + * @retval 1 :Active. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint8_t i2c_active_t(_i2c_t *p_obj) +{ + uint8_t result; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_status_busy(&p_obj->i2c)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Start I2C asynchronous transfer + * @param p_obj :i2c object. + * @param p_tx :Buffer of write data. + * @param tx_length :Length of write data. + * @param p_rx :Buffer of read data. + * @param rx_length :Length of read data. + * @param address :Slave address(7-bit) and last bit is 0. + * @param stop :Stop to be generated after the transfer is done. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Master and non-blocking function. + * @note Events of this function will be notified on i2c_irq_handler_asynch_t. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) { + reset_asynch(p_obj); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); + p_obj->info.asynch.address = (uint32_t)address; + p_obj->info.asynch.event = 0; + p_obj->info.asynch.stop = (uint32_t)stop; + p_obj->tx_buff.p_buffer = p_tx; + p_obj->tx_buff.length = (uint32_t)tx_length; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = p_rx; + p_obj->rx_buff.length = (uint32_t)rx_length; + p_obj->rx_buff.pos = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; + I2C_enable_interrupt(&p_obj->i2c); + if ((tx_length == 0) && (rx_length != 0)) { + I2C_start_condition(&p_obj->i2c, (uint32_t)((uint32_t)address | 1U)); + } else { + I2C_start_condition(&p_obj->i2c, (uint32_t)address); + } + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + enable_irq(p_obj->info.irqn); + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief The asynchronous IRQ handler + * @param p_obj :i2c object. + * @retval zero :Transfer in progress. + * @retval non-zero :Event information. + * @note Macro definition of return values is @ref I2C_Events. + * @attention This function should be implement as INTI2Cx_IRQHandler. + */ +/*--------------------------------------------------*/ +uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + i2c_irq_handler(p_obj); + + return (p_obj->info.asynch.event & I2C_EVENT_ALL); +} + +/*--------------------------------------------------*/ +/** + * @brief Abort asynchronous transfer + * @param p_obj :i2c object. + * @retval - + * @note After error event occurred on i2c_irq_handler_asynch_t, + * @note call this function and clear error status. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_abort_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + reset_asynch(p_obj); + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + i2c_reset_t(p_obj); + I2C_init(&p_obj->i2c); + clear_irq(p_obj->info.irqn); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure I2C as slave or master. + * @param p_obj :i2c object. + * @param enable_slave :Enable slave mode. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + disable_irq(p_obj->info.irqn); + + if (enable_slave) { + I2C_slave_init(&p_obj->i2c); + } else { + /* Slave Disable Settings. */ + i2c_reset_t(p_obj); + I2C_init(&p_obj->i2c); + } + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + I2C_clear_int_status(&p_obj->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Check to see if the I2C slave has been addressed. + * @param p_obj :i2c object. + * @retval I2C_NO_DATA :The slave has not been addressed. + * @retval I2C_READ_ADDRESSED :Read addresses. + * @retval I2C_WRITE_GENERAL :Write to all slaves(now, not support). + * @retval I2C_WRITE_ADDRESSED :Write addressed. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_receive_t(_i2c_t *p_obj) +{ + int32_t result = I2C_NO_DATA; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_slave_detected(&p_obj->i2c)) { + uint32_t sa = I2C_read_data(&p_obj->i2c); + + if (!I2C_transmitter(&p_obj->i2c)) { + result = I2C_WRITE_ADDRESSED; + } else { + result = I2C_READ_ADDRESSED; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking reading data. + * @param p_obj :i2c object. + * @param p_data :Destination address of read data. + * @param length :Number of bytes to read. + * @retval Number of read bytes. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) +{ + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); +#endif /* #ifdef DEBUG */ + + /* Read all bytes */ + while (count < length) { + I2C_clear_int_status(&p_obj->i2c); + I2C_set_ack(&p_obj->i2c, ((count < (length - 1)) ? 0 : 1)); + I2C_write_data(&p_obj->i2c, 0); + if (wait_status(p_obj) < 0) { + break; + } + if (I2C_slave_detected(&p_obj->i2c)) { + return (count); + } + p_data[count++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + I2C_slave_init(&p_obj->i2c); + return (count); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking sending data. + * @param p_obj :i2c object. + * @param p_data :Source address of write data. + * @param length :Number of bytes to write. + * @retval Number of written bytes. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) +{ + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); +#endif /* #ifdef DEBUG */ + + /* Write all bytes */ + while (count < length) { + I2C_clear_int_status(&p_obj->i2c); + I2C_write_data(&p_obj->i2c, (uint32_t)p_data[count++]); + if (wait_status(p_obj) < 0) { + break; + } + if (!I2C_get_ack(&p_obj->i2c)) { + /* continue */ + } else { + break; + } + } + I2C_slave_init(&p_obj->i2c); + return (count); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure I2C slave address. + * @param p_obj :i2c object. + * @param address :Address to be set. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(check_param_address((int32_t)address)); +#endif /* #ifdef DEBUG */ + + I2C_set_address(&p_obj->i2c, address); +} + + +/*--------------------------------------------------*/ +/** + * @brief Start I2C asynchronous transfer + * @param p_obj :i2c object. + * @param p_tx :Buffer of write data. + * @param tx_length :Length of write data. + * @param p_rx :Buffer of read data. + * @param rx_length :Length of read data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Slave and non-blocking function. + * @note Events of this function will be notified on i2c_slave_irq_handler_asynch_t. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) { + reset_asynch(p_obj); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); + p_obj->info.asynch.address = 0; + p_obj->info.asynch.event = 0; + p_obj->info.asynch.stop = 0; + p_obj->tx_buff.p_buffer = p_tx; + p_obj->tx_buff.length = (uint32_t)tx_length; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = p_rx; + p_obj->rx_buff.length = (uint32_t)rx_length; + p_obj->rx_buff.pos = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; + I2C_enable_interrupt(&p_obj->i2c); + enable_irq(p_obj->info.irqn); + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief The asynchronous IRQ handler + * @param p_obj :i2c object. + * @retval zero :Transfer in progress. + * @retval non-zero :Event information. + * @note Macro definition of return values is @ref I2C_Events. + * @attention This function should be implement as INTI2Cx_IRQHandler. + */ +/*--------------------------------------------------*/ +uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + i2c_slave_irq_handler(p_obj); + + return (p_obj->info.asynch.event & I2C_EVENT_ALL); +} + +/*--------------------------------------------------*/ +/** + * @brief Abort asynchronous transfer + * @param p_obj :i2c object. + * @retval - + * @note For a non-blocking function. + * @note After error event occurred on i2c_slave_irq_handler_asynch_t, + * @note call this function and clear error status. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_abort_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + reset_asynch(p_obj); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + I2C_slave_init(&p_obj->i2c); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); +} + +/** + * @} + */ /* End of group UTILITIES_Exported_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#endif /* defined(__I2C_API_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_t32a.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_t32a.c new file mode 100644 index 00000000000..2cd5fd8c0f0 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_t32a.c @@ -0,0 +1,2004 @@ +/** + ******************************************************************************* + * @file txzp_t32a.c + * @brief This file provides API functions for T32A driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_t32a.h" + +#if defined(__T32A_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup T32A + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_define T32A Private Define + * @{ + */ +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ +/** + * @} + */ /* End of group T32A_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_define T32A Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_typedef T32A Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Private_member T32A Private Member + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_member */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_fuctions TSPI Private Fuctions + * @{ + */ +#ifdef DEBUG +__INLINE static int32_t check_param_mode_halt(uint32_t param); +__INLINE static int32_t check_param_mode_mode32(uint32_t param); +__INLINE static int32_t check_param_runx_sftstpx(uint32_t param); +__INLINE static int32_t check_param_runx_sftstax(uint32_t param); +__INLINE static int32_t check_param_runx_runx(uint32_t param); +__INLINE static int32_t check_param_crx_prsclx(uint32_t param); +__INLINE static int32_t check_param_crx_clkx(uint32_t param); +__INLINE static int32_t check_param_crx_wbfx(uint32_t param); +__INLINE static int32_t check_param_crx_updnx(uint32_t param); +__INLINE static int32_t check_param_crx_reldx(uint32_t param); +__INLINE static int32_t check_param_crx_stopx(uint32_t param); +__INLINE static int32_t check_param_crx_startx(uint32_t param); +__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param); +__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param); +__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param); +__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param); +__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param); +__INLINE static int32_t check_param_reldx_reld(uint32_t param); +__INLINE static int32_t check_param_imx_imsterr(uint32_t param); +__INLINE static int32_t check_param_imx_imufx(uint32_t param); +__INLINE static int32_t check_param_imx_imofx(uint32_t param); +__INLINE static int32_t check_param_imx_imx1(uint32_t param); +__INLINE static int32_t check_param_imx_imx0(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pup(uint32_t param); +__INLINE static int32_t check_param_pls_cr_nf(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param); +#endif + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Mode HALT's parameter. + * @param param :Mode HALT's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_HALT + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_mode_halt(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DBG_HALT_RUN: + case T32A_DBG_HALT_STOP: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Mode mode32's parameter. + * @param param :Mode mode32's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_MODE32 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_mode_mode32(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_MODE_16: + case T32A_MODE_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the SW Counter STOP Control's parameter. + * @param param :SW Counter STOP Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_SFTSTPx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_sftstpx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_DONT_STOP: + case T32A_COUNT_STOP: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the SW START Control's parameter. + * @param param :SW START Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_SFTSTAx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_sftstax(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_DONT_START: + case T32A_COUNT_START: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A RUN Disable/Enable Control's parameter. + * @param param :T32A RUN Disable/Enable Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PRSCLx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_runx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_RUN_DISABLE: + case T32A_RUN_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A PRESCALER Control's parameter. + * @param param :T32A PRESCALER Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PRSCLx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_prsclx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PRSCLx_1: + case T32A_PRSCLx_2: + case T32A_PRSCLx_8: + case T32A_PRSCLx_32: + case T32A_PRSCLx_128: + case T32A_PRSCLx_256: + case T32A_PRSCLx_512: + case T32A_PRSCLx_1024: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A PRESCALER Control's parameter. + * @param param :T32A PRESCALER Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CLKx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_clkx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CLKx_PRSCLx: + case T32A_CLKx_INTRG: + case T32A_CLKx_TIM_RISING_EDGE: + case T32A_CLKx_TIM_TRAILING_EDGE: + case T32A_CLKx_EXTTRG_RISING_EDGE: + case T32A_CLKx_EXTTRG_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Double Buffer Disable/Enable Control's parameter. + * @param param :Double Buffer Disable/Enable Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_WBFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_wbfx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_WBF_DISABLE: + case T32A_WBF_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Up/Down Control's parameter. + * @param param :T32A Counter Up/Down Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_UPDNx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_updnx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_UP: + case T32A_COUNT_DOWN: + case T32A_COUNT_UPDOWN: + case T32A_COUNT_PLS: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Reload Control's parameter. + * @param param :T32A Counter Reload Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RELDx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_reldx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_RELOAD_NON: + case T32A_RELOAD_INTRG: + case T32A_RELOAD_EXTTRG_RISING_EDGE: + case T32A_RELOAD_EXTTRG_TRAILING_EDGE: + case T32A_RELOAD_TIM_RISING_EDGE: + case T32A_RELOAD_TIM_TRAILING_EDGE: + case T32A_RELOAD_SYNC: + case T32A_RELOAD_TREGx: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Stop Control's parameter. + * @param param :T32A Counter Stop Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_STOPx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_stopx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_STOP_NON: + case T32A_STOP_INTRG: + case T32A_STOP_EXTTRG_RISING_EDGE: + case T32A_STOP_EXTTRG_TRAILING_EDGE: + case T32A_STOP_TIM_RISING_EDGE: + case T32A_STOP_TIM_TRAILING_EDGE: + case T32A_STOP_SYNC: + case T32A_STOP_TREGx: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Start Control's parameter. + * @param param :T32A Counter Start Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_STARTx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_startx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_START_NON: + case T32A_START_INTRG: + case T32A_START_EXTTRG_RISING_EDGE: + case T32A_START_EXTTRG_TRAILING_EDGE: + case T32A_START_TIM_RISING_EDGE: + case T32A_START_TIM_TRAILING_EDGE: + case T32A_START_SYNC: + result = PARAM_OK; + break; + case T32A_START_Rsvd: + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control's parameter. + * @param param :T32AxOUTA Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCR_DISABLE: + case T32A_OCR_SET: + case T32A_OCR_CLR: + case T32A_OCR_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter. + * @param param :T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCAPx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCAPx1_DISABLE: + case T32A_OCRCAPx1_SET: + case T32A_OCRCAPx1_CLR: + case T32A_OCRCAPx1_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter. + * @param param :T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCAPx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCAPx0_DISABLE: + case T32A_OCRCAPx0_SET: + case T32A_OCRCAPx0_CLR: + case T32A_OCRCAPx0_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. + * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCMPx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCMPx1_DISABLE: + case T32A_OCRCMPx1_SET: + case T32A_OCRCMPx1_CLR: + case T32A_OCRCMPx1_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. + * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCMPx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCMPx0_DISABLE: + case T32A_OCRCMPx0_SET: + case T32A_OCRCMPx0_CLR: + case T32A_OCRCMPx0_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Capture Control Register A1's parameter. + * @param param :T32A Capture Control Register A1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CAPMx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CAPMx1_DISABLE: + case T32A_CAPMx1_INTRG: + case T32A_CAPMx1_INx0_RISING_EDGE: + case T32A_CAPMx1_INx0_TRAILING_EDGE: + case T32A_CAPMx1_INx1_RISING_EDGE: + case T32A_CAPMx1_INx1_TRAILING_EDGE: + case T32A_CAPMx1_TIM_RISING_EDGE: + case T32A_CAPMx1_TIM_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Capture Control Register A0's parameter. + * @param param :T32A Capture Control Register A0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CAPMx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CAPMx0_DISABLE: + case T32A_CAPMx0_INTRG: + case T32A_CAPMx0_INx0_RISING_EDGE: + case T32A_CAPMx0_INx0_TRAILING_EDGE: + case T32A_CAPMx0_INx1_RISING_EDGE: + case T32A_CAPMx0_INx1_TRAILING_EDGE: + case T32A_CAPMx0_TIM_RISING_EDGE: + case T32A_CAPMx0_TIM_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Timer Register A0's parameter. + * @param param :T32A Timer Register A0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RGx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RGx0_MASK) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Timer Register A1's parameter. + * @param param :T32A Timer Register A1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RGx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RGx1_MASK) { + result = PARAM_OK; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Reload Register A's parameter. + * @param param :T32A Counter Reload Register A's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RELD + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_reldx_reld(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RELDx_MASK) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Statuserr Interrupt Request MASK's parameter. + * @param param :T32A Statuserr Interrupt Request MASK's parameter. + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMSTEER + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imsterr(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMSTERR_MASK_NOREQ: + case T32A_IMSTERR_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Overflow Interrupt Request MASK's parameter. + * @param param :T32A Overflow Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMUFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imufx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMOFx_MASK_NOREQ: + case T32A_IMOFx_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Overflow Interrupt Request MASK's parameter. + * @param param :T32A Overflow Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMOFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imofx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMOFx_MASK_NOREQ: + case T32A_IMOFx_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter. + * @param param :T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMx1_MASK_NOREQ: + case T32A_IMx1_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter. + * @param param :T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMx0_MASK_NOREQ: + case T32A_IMx0_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA Converter1 Request control's parameter. + * @param param :T32A DMA Converter1 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx2 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx2_DISABLE: + case T32A_DMAENx2_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA InputCapture1 Request control's parameter. + * @param param :T32A DMA InputCapture1 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx1_DISABLE: + case T32A_DMAENx1_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA InputCapture0 Request control's parameter. + * @param param :T32A DMA InputCapture0 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx0_DISABLE: + case T32A_DMAENx0_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Mode Count Down Control's parameter. + * @param param :T32A Pulse Mode Count Down Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PDN + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PDN_NON0: + case T32A_PDN_NON1: + case T32A_PDN_INC0_RISING_EDGE: + case T32A_PDN_INC0_TRAILING_EDGE: + case T32A_PDN_INC1_RISING_EDGE: + case T32A_PDN_INC1_TRAILING_EDGE: + case T32A_PDN_INC0_BOTH_EDGE: + case T32A_PDN_INC1_BOTH_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Mode Count UP Control's parameter. + * @param param :T32A Pulse Mode Count UP Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PUP + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pup(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PUP_NON0: + case T32A_PUP_NON1: + case T32A_PUP_INC0_RISING_EDGE: + case T32A_PUP_INC0_TRAILING_EDGE: + case T32A_PUP_INC1_RISING_EDGE: + case T32A_PUP_INC1_TRAILING_EDGE: + case T32A_PUP_INC0_BOTH_EDGE: + case T32A_PUP_INC1_BOTH_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Noise Filter control's parameter. + * @param param :T32A Noise Filter control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_NF + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_nf(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_NF_NON: + case T32A_NF_2: + case T32A_NF_4: + case T32A_NF_8: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Phase 2 Pulse Direction control's parameter. + * @param param :T32A Phase 2 Pulse Direction control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PDIR + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PDIR_FORWARD: + case T32A_PDIR_BACKWARD: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Count Mode control's parameter. + * @param param :T32A Pulse Count Mode control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PMODE + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PMODE_PHASE_2: + case T32A_PMODE_PHASE_1: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + + + +#endif +/** + * @} + */ /* End of group T32A_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Exported_functions + + */ +/*--------------------------------------------------*/ +/** + * @brief Mode Initialize the T32A object. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_mode_init(t32a_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + check_param_mode_halt(p_obj->init_mode.mode.halt); + check_param_mode_mode32(p_obj->init_mode.mode.mode); +#endif /* DEBUG */ + /* Timer Mode Set */ + p_obj->p_instance->MOD = 0; + p_obj->p_instance->MOD = (p_obj->init_mode.mode.halt | p_obj->init_mode.mode.mode); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Initialize the T32A object. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + /* Check the parameter of TimerA Mode Set */ + check_param_mode_halt(p_obj->init_mode.mode.halt); + check_param_mode_mode32(p_obj->init_mode.mode.mode); + /* Check the parameter of TimerA Run Control Set */ + check_param_runx_sftstpx(p_obj->init[type].runx.sftstp); + check_param_runx_sftstax(p_obj->init[type].runx.sftsta); + check_param_runx_runx(p_obj->init[type].runx.run); + /* Check the parameter of Counter Register Control Set */ + check_param_crx_prsclx(p_obj->init[type].crx.prscl); + check_param_crx_clkx(p_obj->init[type].crx.clk); + check_param_crx_wbfx(p_obj->init[type].crx.wbf); + check_param_crx_updnx(p_obj->init[type].crx.updn); + check_param_crx_reldx(p_obj->init[type].crx.reld); + check_param_crx_stopx(p_obj->init[type].crx.stop); + check_param_crx_startx(p_obj->init[type].crx.start); + /* Check the parameter of TimerA Output Control Set */ + check_param_outcrx0_ocrx(p_obj->init[type].outcrx0.ocr); + /* Check the parameter of T32AxOUTA Control Set */ + check_param_outcrx1_ocrcapx1(p_obj->init[type].outcrx1.ocrcap1); + check_param_outcrx1_ocrcapx0(p_obj->init[type].outcrx1.ocrcap0); + check_param_outcrx1_ocrcmpx1(p_obj->init[type].outcrx1.ocrcmp1); + check_param_outcrx1_ocrcmpx0(p_obj->init[type].outcrx1.ocrcmp0); + /* Check the parameter of Capture Control Set */ + check_param_capcrx_capmx1(p_obj->init[type].capcrx.capmx1); + check_param_capcrx_capmx0(p_obj->init[type].capcrx.capmx0); + /* Check the parameter of T32A Timer Register 0 Set */ + check_param_rgx0_rgx0(p_obj->init[type].rgx0.rgx0); + /* Check the parameter of T32A Timer Register 1 Set */ + check_param_rgx1_rgx1(p_obj->init[type].rgx1.rgx1); + /* Check the parameter of T32A Counter Reload Register Set */ + check_param_reldx_reld(p_obj->init[type].reldx.reld); + /* Check the parameter of Interrupt mask register Set */ + check_param_imx_imsterr(p_obj->init[type].imx.imsterr); + check_param_imx_imufx(p_obj->init[type].imx.imuf); + check_param_imx_imofx(p_obj->init[type].imx.imof); + check_param_imx_imx1(p_obj->init[type].imx.imx1); + check_param_imx_imx0(p_obj->init[type].imx.imx0); + /* Check the parameter of DMA Request register Set */ + check_param_dma_req_dmaenx2(p_obj->init[type].dma_req.dmaenx2); + check_param_dma_req_dmaenx1(p_obj->init[type].dma_req.dmaenx1); + check_param_dma_req_dmaenx0(p_obj->init[type].dma_req.dmaenx0); +#endif + + switch (type) { + case T32A_TIMERA: + /* Timer A */ + if (p_obj->init_mode.mode.mode != T32A_MODE_16) { + result = TXZ_ERROR; + return (result); + } + /* TimerA Run Control Disable */ + p_obj->p_instance->RUNA = 0; + /* Counter Register Control Set */ + p_obj->p_instance->CRA = 0; + p_obj->p_instance->CRA = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerA Output Control Set */ + p_obj->p_instance->OUTCRA0 = 0; + p_obj->p_instance->OUTCRA0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTA Control Set */ + p_obj->p_instance->OUTCRA1 = 0; + p_obj->p_instance->OUTCRA1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register A0 Set */ + p_obj->p_instance->RGA0 = 0; + p_obj->p_instance->RGA0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register A1 Set */ + p_obj->p_instance->RGA1 = 0; + p_obj->p_instance->RGA1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDA = 0; + p_obj->p_instance->RELDA = p_obj->init[type].reldx.reld; + /* TimerB Capture Control Set */ + p_obj->p_instance->CAPCRA = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMA = 0; + p_obj->p_instance->IMA = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAA = 0; + p_obj->p_instance->DMAA = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* TimerA Run Control Set */ + p_obj->p_instance->RUNA = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + case T32A_TIMERB: + /* Timer B */ + if (p_obj->init_mode.mode.mode != T32A_MODE_16) { + result = TXZ_ERROR; + return (result); + } + /* TimerB Run Control Disable */ + p_obj->p_instance->RUNB = 0; + /* Counter Register Control Set */ + p_obj->p_instance->CRB = 0; + p_obj->p_instance->CRB = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerB Output Control Set */ + p_obj->p_instance->OUTCRB0 = 0; + p_obj->p_instance->OUTCRB0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTB Control Set */ + p_obj->p_instance->OUTCRB1 = 0; + p_obj->p_instance->OUTCRB1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register B0 Set */ + p_obj->p_instance->RGB0 = 0; + p_obj->p_instance->RGB0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register B1 Set */ + p_obj->p_instance->RGB1 = 0; + p_obj->p_instance->RGB1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDB = 0; + p_obj->p_instance->RELDB = p_obj->init[type].reldx.reld; + /* TimerB Capture Control Set */ + p_obj->p_instance->CAPCRB = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMB = 0; + p_obj->p_instance->IMB = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAB = 0; + p_obj->p_instance->DMAB = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* TimerB Run Control Set */ + p_obj->p_instance->RUNB = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + case T32A_TIMERC: + /* Timer C */ + if (p_obj->init_mode.mode.mode != T32A_MODE_32) { + result = TXZ_ERROR; + return (result); + } + /* TimerC Run Control Disable */ + p_obj->p_instance->RUNC = 0; +#ifdef DEBUG + /* Pulse Count Control register Set */ + check_param_pls_cr_pdn(p_obj->init[type].pls_cr.pdn); + check_param_pls_cr_pup(p_obj->init[type].pls_cr.pup); + check_param_pls_cr_nf(p_obj->init[type].pls_cr.nf); + check_param_pls_cr_pdir(p_obj->init[type].pls_cr.pdir); + check_param_pls_cr_pmode(p_obj->init[type].pls_cr.pmode); +#endif + /* Counter Register Control Set */ + p_obj->p_instance->CRC = 0; + p_obj->p_instance->CRC = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerC Output Control Set */ + p_obj->p_instance->OUTCRC0 = 0; + p_obj->p_instance->OUTCRC0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTC Control Set */ + p_obj->p_instance->OUTCRC1 = 0; + p_obj->p_instance->OUTCRC1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register C0 Set */ + p_obj->p_instance->RGC0 = 0; + p_obj->p_instance->RGC0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register C1 Set */ + p_obj->p_instance->RGC1 = 0; + p_obj->p_instance->RGC1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDC = 0; + p_obj->p_instance->RELDC = p_obj->init[type].reldx.reld; + /* TimerC Capture Control Set */ + p_obj->p_instance->CAPCRC = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMC = 0; + p_obj->p_instance->IMC = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAC = 0; + p_obj->p_instance->DMAC = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* Pulse Count Control register Set */ + p_obj->p_instance->PLSCR = 0; + p_obj->p_instance->PLSCR = (p_obj->init[type].pls_cr.pdn | p_obj->init[type].pls_cr.pup | p_obj->init[type].pls_cr.nf | \ + p_obj->init[type].pls_cr.pdir | p_obj->init[type].pls_cr.pmode); + /* TimerC Run Control Set */ + p_obj->p_instance->RUNC = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the T32A object. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNA = T32A_RUN_DISABLE; + break; + case T32A_TIMERB: + /* Timer B */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNB = T32A_RUN_DISABLE; + break; + case T32A_TIMERC: + /* Timer C */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNC = T32A_RUN_DISABLE; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Timer Start in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + if (((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0) { + /* Timer A RUN */ + p_obj->p_instance->RUNA |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERB: + if (((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0) { + /* Timer B RUN */ + p_obj->p_instance->RUNB |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERC: + if (((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0) { + /* Timer C RUN */ + p_obj->p_instance->RUNC |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Stop in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A Stop */ + p_obj->p_instance->RUNA = T32A_RUN_DISABLE; + break; + case T32A_TIMERB: + /* Timer B Stop */ + p_obj->p_instance->RUNB = T32A_RUN_DISABLE; + break; + case T32A_TIMERC: + /* SW Counter Stop & Timer C Stop */ + p_obj->p_instance->RUNC = T32A_RUN_DISABLE; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Start in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + if (((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0) { + /* Timer A SW Counter start */ + p_obj->p_instance->RUNA |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERB: + if (((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0) { + /* Timer SW Counter start */ + p_obj->p_instance->RUNB |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERC: + if (((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0) { + /* Timer C SW Counter start */ + p_obj->p_instance->RUNC |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Stop in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* TimerA SW Counter Stop */ + p_obj->p_instance->RUNA = T32A_COUNT_STOP; + break; + case T32A_TIMERB: + /* Timer B SW Counter Stop */ + p_obj->p_instance->RUNB = T32A_COUNT_STOP; + break; + case T32A_TIMERC: + /* Timer C SW Counter Stop */ + p_obj->p_instance->RUNC = T32A_COUNT_STOP; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Register Value Setting + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @param num :T32A Register Number. : Use @ref t32_regnum_t + * @param value :Setting Value. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A */ + if (num == T32A_REG0) { + p_obj->p_instance->RGA0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGA1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDA = value; + } + break; + case T32A_TIMERB: + /* Timer B */ + if (num == T32A_REG0) { + p_obj->p_instance->RGB0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGB1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDB = value; + } + break; + case T32A_TIMERC: + /* Timer C */ + if (num == T32A_REG0) { + p_obj->p_instance->RGC0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGC1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDC = value; + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Timer Register Value Read + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @param p_val :Save area for register value. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val) +{ + TXZ_Result result = TXZ_SUCCESS; + switch (type) { + case T32A_TIMERA: + /* Timer A */ + *p_val = p_obj->p_instance->TMRA; + break; + case T32A_TIMERB: + /* Timer B */ + *p_val = p_obj->p_instance->TMRB; + break; + case T32A_TIMERC: + /* Timer C */ + *p_val = p_obj->p_instance->TMRC; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-4 | - | - | + * | 3 | INTUFA | Under Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | + * | 2 | INTOFA | Over Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | + * | 1 | INTx1 | Match up TimerRegister x1 Intterrupt. Use @ref T32A_INTx1_FLG_MASK. | + * | 0 | INTx0 | Match up TimerRegister x0 Intterrupt. Use @ref T32A_INTx0_FLG_MASK. | + * + * @param p_obj :T32A object. + * @param p_status :Save area for status. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + switch (type) { + case T32A_TIMERA: + /* Timer A */ + *p_status = p_obj->p_instance->STA; + break; + case T32A_TIMERB: + /* Timer B */ + *p_status = p_obj->p_instance->STB; + break; + case T32A_TIMERC: + /* Timer C */ + *p_status = p_obj->p_instance->STC; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for Timer interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_T(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_T(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_T(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Timer Capture0 Handler for Timer Capture0 interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_cap0_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_TC0(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_TC0(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_TC0(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Timer Capture1 Handler for Timer Capture1 interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_cap1_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_TC1(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_TC1(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_TC1(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Calculate timer value to set timer register. + * @param p_value: time value store pointer. + * @param time: The require period which the uint is us. + * @param prescaler: System Clock Freq + * @param prscl: Select the division for source clock @ref T32A_PRSCLx. + * @retval the value set to Tmrb timer register. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl) +{ + TXZ_Result result = TXZ_SUCCESS; + uint64_t denominator; + uint64_t numerator; + uint32_t div; + + /* div */ + switch (prscl) { + case T32A_PRSCLx_1: + div = 1; + break; + case T32A_PRSCLx_2: + div = 2; + break; + case T32A_PRSCLx_8: + div = 8; + break; + case T32A_PRSCLx_32: + div = 32; + break; + case T32A_PRSCLx_128: + div = 128; + break; + case T32A_PRSCLx_256: + div = 256; + break; + case T32A_PRSCLx_512: + div = 512; + break; + case T32A_PRSCLx_1024: + div = 1024; + break; + default: + div = 1; + break; + } + /*-----------------------------------------------*/ + /* "1"counter (s) = 1 / fs */ + /* "1"counter (s) = 1 / (prescaler / div) */ + /* "1"counter (us) = (10^6) / (prescaler / div) */ + /* "1"counter (us) = ((10^6) * div)/prescaler */ + /* "x"counter (us) = time */ + /*-----------------------------------------------*/ + /* x : time = 1 : ((10^6) * div)/prescaler */ + /*-----------------------------------------------*/ + /* x = time / (((10^6) * div)/prescaler) */ + /* = (prescaler * time) / ((10^6) * div) */ + /*-----------------------------------------------*/ + denominator = (uint64_t)((uint64_t)(prescaler) * (uint64_t)(time)); + numerator = (uint64_t)((uint64_t)(1000000) * (uint64_t)div); + denominator = (uint64_t)(denominator / numerator); + /* result */ + if ((denominator == (uint64_t)(0)) || (denominator > (uint64_t)(0xFFFF))) { + result = TXZ_ERROR; + } else { + *p_value = (uint32_t)denominator; + } + + return (result); +} + +/** + * @} + */ /* End of group T32A_Exported_functions */ + +/** + * @} + */ /* End of group T32A */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__T32A_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_tspi.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_tspi.c new file mode 100644 index 00000000000..63deabf5232 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_tspi.c @@ -0,0 +1,2645 @@ +/** + ******************************************************************************* + * @file txzp_tspi.c + * @brief This file provides API functions for TSPI driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_tspi.h" + +#if defined(__TSPI_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup TSPI + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ +/** + * @name TSPI NULL Pointer + * @brief Null Pointer for TSPI + * @{ + */ +#define TSPI_NULL ((void *)0) /*!< NULL pointer. */ +/** + * @} + */ /* End of name TSPI NULL Pointer */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name FIFO Max Num. + * @brief Transfer's/Receive's FIFO Max Num. + * @{ + */ +#define TRANSFER_FIFO_MAX_NUM ((uint32_t)8) /*!< Transfer's FIFO Max Num. */ +#define RECEIVE_FIFO_MAX_NUM ((uint32_t)8) /*!< Receive's FIFO Max Num. */ +/** + * @} + */ /* End of name FIFO Max Num */ + +/** + * @name TSPIxDR_MASK Macro Definition. + * @brief TSPIxDR_MASK Macro Definition. + * @{ + */ +/* DR */ +#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_31BIT_MASK ((uint32_t)0x7FFFFFFF) /*!< DR :Mask for 8bit */ +/** + * @} + */ /* End of name TSPIxDR_MASK Macro Definition */ + +/** + * @name TSPI _DATA_LENGTH Macro Definition. + * @brief TSPI DATA LENGTH Macro Definition. + * @{ + */ +#define DATA_LENGTH_8 ((uint32_t)0x08) /*!< 8 bit */ +#define DATA_LENGTH_9 ((uint32_t)0x09) /*!< 9 bit */ +#define DATA_LENGTH_10 ((uint32_t)0x0a) /*!< 10 bit */ +#define DATA_LENGTH_11 ((uint32_t)0x0b) /*!< 11 bit */ +#define DATA_LENGTH_12 ((uint32_t)0x0c) /*!< 12 bit */ +#define DATA_LENGTH_13 ((uint32_t)0x0d) /*!< 13 bit */ +#define DATA_LENGTH_14 ((uint32_t)0x0e) /*!< 14 bit */ +#define DATA_LENGTH_15 ((uint32_t)0x0f) /*!< 15 bit */ +#define DATA_LENGTH_16 ((uint32_t)0x10) /*!< 16 bit */ +#define DATA_LENGTH_17 ((uint32_t)0x11) /*!< 17 bit */ +#define DATA_LENGTH_18 ((uint32_t)0x12) /*!< 18 bit */ +#define DATA_LENGTH_19 ((uint32_t)0x13) /*!< 19 bit */ +#define DATA_LENGTH_20 ((uint32_t)0x14) /*!< 20 bit */ +#define DATA_LENGTH_21 ((uint32_t)0x15) /*!< 21 bit */ +#define DATA_LENGTH_22 ((uint32_t)0x16) /*!< 22 bit */ +#define DATA_LENGTH_23 ((uint32_t)0x17) /*!< 23 bit */ +#define DATA_LENGTH_24 ((uint32_t)0x18) /*!< 24 bit */ +#define DATA_LENGTH_25 ((uint32_t)0x19) /*!< 25 bit */ +#define DATA_LENGTH_26 ((uint32_t)0x1a) /*!< 26 bit */ +#define DATA_LENGTH_27 ((uint32_t)0x1b) /*!< 27 bit */ +#define DATA_LENGTH_28 ((uint32_t)0x1c) /*!< 28 bit */ +#define DATA_LENGTH_29 ((uint32_t)0x1d) /*!< 29 bit */ +#define DATA_LENGTH_30 ((uint32_t)0x1e) /*!< 30 bit */ +#define DATA_LENGTH_31 ((uint32_t)0x1f) /*!< 31 bit */ +#define DATA_LENGTH_32 ((uint32_t)0x20) /*!< 32 bit */ +/** + * @} + */ /* End of name TSPI _DATA_LENGTH Macro Definition */ +/** + * @} + */ /* End of group TSPI_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group TSPI_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_typedef TSPI Private Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief TSPI mask array. +*/ +/*----------------------------------*/ +static uint32_t mask[32] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TSPI_DR_8BIT_MASK, + TSPI_DR_9BIT_MASK, + TSPI_DR_10BIT_MASK, + TSPI_DR_11BIT_MASK, + TSPI_DR_12BIT_MASK, + TSPI_DR_13BIT_MASK, + TSPI_DR_14BIT_MASK, + TSPI_DR_15BIT_MASK, + TSPI_DR_16BIT_MASK, + TSPI_DR_17BIT_MASK, + TSPI_DR_18BIT_MASK, + TSPI_DR_19BIT_MASK, + TSPI_DR_20BIT_MASK, + TSPI_DR_21BIT_MASK, + TSPI_DR_22BIT_MASK, + TSPI_DR_23BIT_MASK, + TSPI_DR_24BIT_MASK, + TSPI_DR_25BIT_MASK, + TSPI_DR_26BIT_MASK, + TSPI_DR_27BIT_MASK, + TSPI_DR_28BIT_MASK, + TSPI_DR_29BIT_MASK, + TSPI_DR_30BIT_MASK, + TSPI_DR_31BIT_MASK +}; + +/** + * @} + */ /* End of group TSPI_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_fuctions TSPI Private Fuctions + * @{ + */ + +#ifdef DEBUG +__INLINE static int32_t check_param_frameinf_enable(uint32_t param); +__INLINE static int32_t check_param_transmit_enable(uint32_t param); +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param); +__INLINE static int32_t check_param_transmit_master(uint32_t param); +__INLINE static int32_t check_param_transmit_mode(uint32_t param); +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param); +__INLINE static int32_t check_param_frame_range(uint32_t param); +__INLINE static int32_t check_param_idle_imp(uint32_t param); +__INLINE static int32_t check_param_underrun_imp(uint32_t param); +__INLINE static int32_t check_param_rxdly_value(uint32_t param); +__INLINE static int32_t check_param_tx_fill_level(uint32_t param); +__INLINE static int32_t check_param_rx_fill_level(uint32_t param); +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param); +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param); +__INLINE static int32_t check_param_err_int(uint32_t param); +__INLINE static int32_t check_param_tx_dma_int(uint32_t param); +__INLINE static int32_t check_param_rx_dma_int(uint32_t param); +__INLINE static int32_t check_param_input_clock(uint32_t param); +__INLINE static int32_t check_param_input_divider(uint32_t param); +__INLINE static int32_t check_param_data_direction(uint32_t param); +__INLINE static int32_t check_param_frame_length(uint32_t param); +__INLINE static int32_t check_param_frame_interval(uint32_t param); +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param); +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param); +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param); +__INLINE static int32_t check_param_min_idle_time(uint32_t param); +__INLINE static int32_t check_param_clock_delay(uint32_t param); +__INLINE static int32_t check_param_negate_delay(uint32_t param); +__INLINE static int32_t check_param_parity_enable(uint32_t param); +__INLINE static int32_t check_param_parity_bit(uint32_t param); +__INLINE static int32_t check_param_sect_mode(uint32_t param); +__INLINE static int32_t check_param_sectl0_value(uint32_t param); +__INLINE static int32_t check_param_sectl1_value(uint32_t param); +__INLINE static int32_t check_param_sectl2_value(uint32_t param); +__INLINE static int32_t check_param_sectl3_value(uint32_t param); +#endif + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit frame infinity Enable's parameter. + * @param param :Transmit frame infinity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Infinity_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frameinf_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_INF_DISABLE: + case TSPI_INF_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Enable's parameter. + * @param param :Transmit Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TRXE_DISABLE: + case TSPI_TRXE_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Mode's parameter. + * @param param :Transmit Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SPI_MODE: + case TSPI_SIO_MODE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Master/Slave parameter. + * @param param :Transmit Master/Slave parameter (Only support Master mode) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Operation_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_master(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_MASTER_OPERATION: + case TSPI_SLAVE_OPERATION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transfer Mode's parameter. + * @param param :Transfer Mode's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TWO_WAY: + case TSPI_TX_ONLY: + case TSPI_RX_ONLY: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Sel Select's parameter. + * @param param :Transmit Sel Select's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_CSSEL_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS0_ENABLE: + case TSPI_TSPIxCS1_ENABLE: + case TSPI_TSPIxCS2_ENABLE: + case TSPI_TSPIxCS3_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Frame Range's parameter. + * @param param :TransmitFrame Range's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Frame_Range + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_range(uint32_t param) + +{ + int32_t result = PARAM_NG; + + if ((TSPI_TRANS_RANGE_CONTINUE == param) || (param <= TSPI_TRANS_RANGE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the IDLE Output Value's parameter. + * @param param :IDLE Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_IDLE_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TIDLE_Hiz: + case TSPI_TIDLE_LAST_DATA: + case TSPI_TIDLE_LOW: + case TSPI_TIDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_underrun_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TXDEMP_LOW: + case TSPI_TXDEMP_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rxdly_value(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RXDLY_FSYS_FSCK_2: + case TSPI_RXDLY_FSYS_FSCK_4: + case TSPI_RXDLY_FSYS_FSCK_6: + case TSPI_RXDLY_FSYS_FSCK_8: + case TSPI_RXDLY_FSYS_FSCK_10: + case TSPI_RXDLY_FSYS_FSCK_12: + case TSPI_RXDLY_FSYS_FSCK_14: + case TSPI_RXDLY_FSYS_FSCK_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level's parameter. + * @param param :Tx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_FILL_LEVEL_0: + case TSPI_TX_FILL_LEVEL_1: + case TSPI_TX_FILL_LEVEL_2: + case TSPI_TX_FILL_LEVEL_3: + case TSPI_TX_FILL_LEVEL_4: + case TSPI_TX_FILL_LEVEL_5: + case TSPI_TX_FILL_LEVEL_6: + case TSPI_TX_FILL_LEVEL_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_FILL_LEVEL_0: + case TSPI_RX_FILL_LEVEL_1: + case TSPI_RX_FILL_LEVEL_2: + case TSPI_RX_FILL_LEVEL_3: + case TSPI_RX_FILL_LEVEL_4: + case TSPI_RX_FILL_LEVEL_5: + case TSPI_RX_FILL_LEVEL_6: + case TSPI_RX_FILL_LEVEL_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_FIFO_INT_DISABLE: + case TSPI_TX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_INT_DISABLE: + case TSPI_TX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFIFOInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_FIFO_INT_DISABLE: + case TSPI_RX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_INT_DISABLE: + case TSPI_RX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ErrorInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_err_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_ERR_INT_DISABLE: + case TSPI_ERR_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx DMA Interrupt's parameter. + * @param param :Tx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_DMA_INT_DISABLE: + case TSPI_TX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx DMA Interrupt's parameter. + * @param param :Rx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_DMA_INT_DISABLE: + case TSPI_RX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Input Clock's parameter. + * @param param :Input Clock's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_clock(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_BR_CLOCK_0: + case TSPI_BR_CLOCK_1: + case TSPI_BR_CLOCK_2: + case TSPI_BR_CLOCK_4: + case TSPI_BR_CLOCK_8: + case TSPI_BR_CLOCK_16: + case TSPI_BR_CLOCK_32: + case TSPI_BR_CLOCK_64: + case TSPI_BR_CLOCK_128: + case TSPI_BR_CLOCK_256: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Baudrate Divider's parameter. + * @param param :Baudrate Divider's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_divider(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_BR_DIVIDER_16: + case TSPI_BR_DIVIDER_1: + case TSPI_BR_DIVIDER_2: + case TSPI_BR_DIVIDER_3: + case TSPI_BR_DIVIDER_4: + case TSPI_BR_DIVIDER_5: + case TSPI_BR_DIVIDER_6: + case TSPI_BR_DIVIDER_7: + case TSPI_BR_DIVIDER_8: + case TSPI_BR_DIVIDER_9: + case TSPI_BR_DIVIDER_10: + case TSPI_BR_DIVIDER_11: + case TSPI_BR_DIVIDER_12: + case TSPI_BR_DIVIDER_13: + case TSPI_BR_DIVIDER_14: + case TSPI_BR_DIVIDER_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataDirection"TSPI_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_DATA_DIRECTION_LSB: + case TSPI_DATA_DIRECTION_MSB: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter (Only support 8bit DATA) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataLength"TSPI_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_length(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_DATA_LENGTH_8: + case TSPI_DATA_LENGTH_9: + case TSPI_DATA_LENGTH_10: + case TSPI_DATA_LENGTH_11: + case TSPI_DATA_LENGTH_12: + case TSPI_DATA_LENGTH_13: + case TSPI_DATA_LENGTH_14: + case TSPI_DATA_LENGTH_15: + case TSPI_DATA_LENGTH_16: + case TSPI_DATA_LENGTH_17: + case TSPI_DATA_LENGTH_18: + case TSPI_DATA_LENGTH_19: + case TSPI_DATA_LENGTH_20: + case TSPI_DATA_LENGTH_21: + case TSPI_DATA_LENGTH_22: + case TSPI_DATA_LENGTH_23: + case TSPI_DATA_LENGTH_24: + case TSPI_DATA_LENGTH_25: + case TSPI_DATA_LENGTH_26: + case TSPI_DATA_LENGTH_27: + case TSPI_DATA_LENGTH_28: + case TSPI_DATA_LENGTH_29: + case TSPI_DATA_LENGTH_30: + case TSPI_DATA_LENGTH_31: + case TSPI_DATA_LENGTH_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Frame Interval's parameter. + * @param param :Frame Interval's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Frame_Interval_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_interval(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_INTERVAL_TIME_0: + case TSPI_INTERVAL_TIME_1: + case TSPI_INTERVAL_TIME_2: + case TSPI_INTERVAL_TIME_3: + case TSPI_INTERVAL_TIME_4: + case TSPI_INTERVAL_TIME_5: + case TSPI_INTERVAL_TIME_6: + case TSPI_INTERVAL_TIME_7: + case TSPI_INTERVAL_TIME_8: + case TSPI_INTERVAL_TIME_9: + case TSPI_INTERVAL_TIME_10: + case TSPI_INTERVAL_TIME_11: + case TSPI_INTERVAL_TIME_12: + case TSPI_INTERVAL_TIME_13: + case TSPI_INTERVAL_TIME_14: + case TSPI_INTERVAL_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS3 Polarity's parameter. + * @param param :TTSPIxCS3 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS3_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS3_NEGATIVE: + case TSPI_TSPIxCS3_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS2 Polarity's parameter. + * @param param :TTSPIxCS2 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS2_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS2_NEGATIVE: + case TSPI_TSPIxCS2_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS1 Polarity's parameter. + * @param param :TTSPIxCS1 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS1_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS1_NEGATIVE: + case TSPI_TSPIxCS1_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS0 Polarity's parameter. + * @param param :TTSPIxCS0 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS0_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS0_NEGATIVE: + case TSPI_TSPIxCS0_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Polarity's parameter. + * @param param :Serial Clock Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_1ST_EDGE: + case TSPI_SERIAL_CK_2ND_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock IDLE Polarity's parameter. + * @param param :Serial Clock IDLE Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_IDLE_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_IDLE_LOW: + case TSPI_SERIAL_CK_IDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Minimum IDLE Time's parameter. + * @param param :Minimum IDLE Time's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Minimum_IDLE_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_min_idle_time(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_MIN_IDLE_TIME_1: + case TSPI_MIN_IDLE_TIME_2: + case TSPI_MIN_IDLE_TIME_3: + case TSPI_MIN_IDLE_TIME_4: + case TSPI_MIN_IDLE_TIME_5: + case TSPI_MIN_IDLE_TIME_6: + case TSPI_MIN_IDLE_TIME_7: + case TSPI_MIN_IDLE_TIME_8: + case TSPI_MIN_IDLE_TIME_9: + case TSPI_MIN_IDLE_TIME_10: + case TSPI_MIN_IDLE_TIME_11: + case TSPI_MIN_IDLE_TIME_12: + case TSPI_MIN_IDLE_TIME_13: + case TSPI_MIN_IDLE_TIME_14: + case TSPI_MIN_IDLE_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Delay's parameter. + * @param param :Serial Clock Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_DELAY_1: + case TSPI_SERIAL_CK_DELAY_2: + case TSPI_SERIAL_CK_DELAY_3: + case TSPI_SERIAL_CK_DELAY_4: + case TSPI_SERIAL_CK_DELAY_5: + case TSPI_SERIAL_CK_DELAY_6: + case TSPI_SERIAL_CK_DELAY_7: + case TSPI_SERIAL_CK_DELAY_8: + case TSPI_SERIAL_CK_DELAY_9: + case TSPI_SERIAL_CK_DELAY_10: + case TSPI_SERIAL_CK_DELAY_11: + case TSPI_SERIAL_CK_DELAY_12: + case TSPI_SERIAL_CK_DELAY_13: + case TSPI_SERIAL_CK_DELAY_14: + case TSPI_SERIAL_CK_DELAY_15: + case TSPI_SERIAL_CK_DELAY_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Negate Delay's parameter. + * @param param :Negate Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Negate_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_negate_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_NEGATE_1: + case TSPI_NEGATE_2: + case TSPI_NEGATE_3: + case TSPI_NEGATE_4: + case TSPI_NEGATE_5: + case TSPI_NEGATE_6: + case TSPI_NEGATE_7: + case TSPI_NEGATE_8: + case TSPI_NEGATE_9: + case TSPI_NEGATE_10: + case TSPI_NEGATE_11: + case TSPI_NEGATE_12: + case TSPI_NEGATE_13: + case TSPI_NEGATE_14: + case TSPI_NEGATE_15: + case TSPI_NEGATE_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityEnable"TSPI_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_PARITY_DISABLE: + case TSPI_PARITY_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityBit"TSPI_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_PARITY_BIT_ODD: + case TSPI_PARITY_BIT_EVEN: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sect Mode's parameter. + * @param param :Sect Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_MODE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sect_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SECTCR0_SECT_FRAME_MODE: + case TSPI_SECTCR0_SECT_SECTOR_MODE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl0 bit length's parameter. + * @param param :Sectl0 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl0_value(uint32_t param) +{ + int32_t result = PARAM_NG; + + /* 1~32:setting enable */ + if ((param >= TSPI_SECTCR1_SECTL0_1) && (param <= TSPI_SECTCR1_SECTL0_32)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl1 bit length's parameter. + * @param param :Sectl1 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl1_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl1_value = (param >> 8); + + /* 1~32:setting enable */ + if ((sectl1_value >= TSPI_SECTCR1_SECTL1_1) && (sectl1_value <= TSPI_SECTCR1_SECTL1_32)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl2 bit length's parameter. + * @param param :Sectl2 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl2_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl2_value = (param >> 16); + + /* 0~32:setting enable */ + if (sectl2_value <= TSPI_SECTCR1_SECTL2_32) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl3 bit length's parameter. + * @param param :Sectl3 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl3_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl3_value = (param >> 24); + + /* 0~32:setting enable */ + if (sectl3_value <= TSPI_SECTCR1_SECTL3_32) { + result = PARAM_OK; + } + + return (result); +} +#endif +/** + * @} + */ /* End of group TSPI_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_init(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxCR1. */ + assert_param(check_param_frameinf_enable(p_obj->init.cnt1.inf)); + assert_param(check_param_transmit_enable(p_obj->init.cnt1.trxe)); + assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims)); + assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr)); + assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd)); + assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel)); + assert_param(check_param_frame_range(p_obj->init.cnt1.fc)); + /* Check the parameter of TTSPIxCR2 */ + assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle)); + assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp)); + assert_param(check_param_rxdly_value(p_obj->init.cnt2.rxdly)); + assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til)); + assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril)); + assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe)); + assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe)); + assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe)); + assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe)); + assert_param(check_param_err_int(p_obj->init.cnt2.interr)); + assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate)); + assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare)); + /* Check the parameter of TTSPIxBR */ + assert_param(check_param_input_clock(p_obj->init.brd.brck)); + assert_param(check_param_input_divider(p_obj->init.brd.brs)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); + /* Check the parameter of TSPISECTCR0 */ + assert_param(check_param_sect_mode(p_obj->init.sectcr0.sect)); + /* Check the parameter of TSPISECTCR1 */ + assert_param(check_param_sectl0_value(p_obj->init.sectcr1.sectl0)); + assert_param(check_param_sectl1_value(p_obj->init.sectcr1.sectl1)); + assert_param(check_param_sectl2_value(p_obj->init.sectcr1.sectl2)); + assert_param(check_param_sectl3_value(p_obj->init.sectcr1.sectl3)); +#endif + + + /* TSPI Software Reset */ + p_obj->p_instance->CR0 = TSPI_ENABLE; + p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE); + p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE); + + /* Wait for 2 clocks of reset completion */ + __NOP(); + __NOP(); + + /* Control1 Register1 Set*/ + p_obj->p_instance->CR1 = 0x00001C01U; + p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \ + p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims | p_obj->init.cnt1.trgen | p_obj->init.cnt1.inf); + /* Control2 Register Set */ + p_obj->p_instance->CR2 = 0x00E10100U; + p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \ + p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe | p_obj->init.cnt2.inttxwe | \ + p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare); + + /* Control3 Register is FIFO clear, do nothing */ + + /* Baudrate Register Set */ + p_obj->p_instance->BR = 0U; + p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs); + + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = 0x8800C400U; + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl); + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = 0U; + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + + /* Sect control0 Register Set*/ + p_obj->p_instance->SECTCR0 = 0U; + p_obj->p_instance->SECTCR0 = p_obj->init.sectcr0.sect; + + /* Sect control1 Register Set*/ + p_obj->p_instance->SECTCR1 = 0x00000101U; + p_obj->p_instance->SECTCR1 = (p_obj->init.sectcr1.sectl3 | p_obj->init.sectcr1.sectl2 | p_obj->init.sectcr1.sectl1 | p_obj->init.sectcr1.sectl0); + + /* not created */ + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_deinit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Disable the selected TSPI peripheral */ + p_obj->p_instance->CR0 |= TSPI_DISABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data.. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err = 0; + uint32_t length = 0; + + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + + /* Transmit data check*/ + if ((p_info->tx8.p_data == TSPI_NULL) || (p_info->tx8.num == 0)) { + p_obj->errcode = DATABUFEMPERR; + result = TXZ_ERROR; + return (result); + } + + /* FIFO Cear */ + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8; + } else { + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + /* Transmit Data write to D ata Register */ + while (p_info->tx8.num > 0) { + /* Check the current fill level */ + if (((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) { + *((__IO uint8_t *)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK); + p_info->tx8.num--; + /* check complete transmit */ + if ((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) { + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } else { + /* Enable TSPI Transmission Control */ + if (p_info->tx8.num == 0) { + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + return (result); + } else { + /* Next transmit data sending */ + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + } + } else { + p_obj->errcode = FIFOFULLERR; + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + + } + /* check complete transmit */ + while ((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) { + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + /* Check Error Flag */ + (void)tspi_get_error(p_obj, &err); + if (((err) & TSPI_UNDERRUN_ERR) == TSPI_UNDERRUN_ERR) { + p_obj->errcode = UNDERRUNERR; + } else if (((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) { + p_obj->errcode = OVERRUNERR; + } else if (((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) { + p_obj->errcode = PARITYERR; + } + + if (p_obj->errcode == NOERROR) { + //p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err = 0; + uint32_t length = 0; + uint32_t count = 0; + uint32_t index = 0; +// uint32_t level = 0; + + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + /* Transmit data check*/ + if ((p_info->rx8.p_data == TSPI_NULL) || (p_info->rx8.num == 0)) { + result = TXZ_ERROR; + return (result); + } + count = p_info->rx8.num; + + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8; + } else { + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + while (timeout > 0) { + /* Wait until Receive Complete Flag is set to receive data */ + if ((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) { + while (count > 0) { + /* Check the remain data exist */ + if ((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0) { + p_info->rx8.p_data[index] = (*((__IO uint8_t *)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK); + count--; + index++; + } else { + p_obj->errcode = FIFOFULLERR; + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + } + /* Receive Complete Flag is clear */ + p_obj->p_instance->SR |= TSPI_RX_DONE_CLR; + /* FIFO Cear */ + p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } else { + timeout--; + } + } + /* Timeout management */ + p_obj->errcode = TIMEOUTERR; + + /* Check Error Flag set */ + (void)tspi_get_error(p_obj, &err); + if (((err) & TSPI_UNDERRUN_ERR) == TSPI_UNDERRUN_ERR) { + p_obj->errcode = UNDERRUNERR; + } else if (((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) { + p_obj->errcode = OVERRUNERR; + } else if (((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) { + p_obj->errcode = PARITYERR; + } + + result = TXZ_ERROR; + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); + } +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + p_obj->transmit.tx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + p_obj->transmit.tx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; + p_obj->transmit.info.tx32.num = p_info->tx32.num; + p_obj->transmit.tx_allign = 32; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /* transmit data length set */ + + /*--- TSPIxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Empty FIFO Num */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + /*--- TSPIxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + return (result); +} + + + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); + } +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + //p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + p_obj->receive.rx_allign = 8; + + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; + p_obj->receive.info.rx32.num = p_info->rx32.num; + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_transmit(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + //p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_TX_FIFO_INT_CLR); + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + /* Check the transmit's end flag. */ + if (((status & TSPI_TX_DONE_FLAG) == TSPI_TX_DONE) || + ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til)) { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Get the empty num in FIFO. */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + if (tlvl == TRANSFER_FIFO_MAX_NUM) { + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.tx_allign = 8; + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.tx_allign = 16; + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } else { + /* 17 - 32 bit */ + p_obj->transmit.tx_allign = 32; + if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } + } + if (txDone == TXZ_DONE) { + /*=== Transmit Done!! ===*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) { + /* Call the transmit handler with SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } +#if 0 + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; +#endif + } + } +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_receive(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + //p_obj->p_instance->SR = (TSPI_RX_DONE_CLR | TSPI_RX_FIFO_INT_CLR); + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.rx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + /* Check the receive's end flag. */ + if (((status & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) || + ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril)) { + /* Read FIFO fill level. */ + __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK); + //__IO uint32_t rlvl = 7; + /* FIFO Max = RECEIVE_FIFO_MAX_NUM */ + if (rlvl > RECEIVE_FIFO_MAX_NUM) { + rlvl = RECEIVE_FIFO_MAX_NUM; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) { + uint32_t i; + for (i = 0; i < rlvl; i++) { + switch (p_obj->receive.rx_allign) { + case 8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK); + break; + case 16: + *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + case 32: + *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) { + tspi_receive_t param; + + switch (p_obj->receive.rx_allign) { + case 8: + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + break; + case 16: + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + break; + case 32: + param.rx32.p_data = p_obj->receive.info.rx32.p_data; + param.rx32.num = rlvl; + break; + default: + /* no process */ + break; + } + /* Call the receive handler with SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_error_irq_handler(tspi_t *p_obj) +{ + __IO uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current TSPIxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- TSPIxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) { + /* Call the transmit handler with FAILURE. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* UNDERERR */ + if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR) { + err = TXZ_ERROR; + } + /* OVRERR */ + if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR) { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR) { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) { + /* Call the receive handler with FAILURE. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL); + } + } + } +} + + +/*--------------------------------------------------*/ +/** + * @brief Data Format setting + * @param p_obj :TSPI object. + * @retval - + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_format(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); +#endif + + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. | + * | 30-24 | - | - | + * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. | + * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. | + * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. | + * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. | + * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. | + * | 15-8 | - | - | + * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. | + * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. | + * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag | + * + * @param p_obj :TSPI object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_status is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI state */ + *p_status = p_obj->p_instance->SR; + if (p_status != TSPI_NULL) { + return (result); + } else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI ERROR */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Error information clear. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 3 | TRGERR | Trigger Error. Use @ref TSPI_TRGErr. | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_error_clear(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_transmit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_receive(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + + +/** + * @} + */ /* End of group TSPI_Exported_functions */ + +/** + * @} + */ /* End of group TSPI */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__TSPI_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_uart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_uart.c new file mode 100644 index 00000000000..a4688870388 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_uart.c @@ -0,0 +1,1805 @@ +/** + ******************************************************************************* + * @file txzp_uart.c + * @brief This file provides API functions for UART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_uart_include.h" +#include "txzp_uart.h" + +#if defined(__UART_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/** + * @defgroup UART_BourateConfig Bourate Setting Configuration + * @brief Bourate Setting Configuration. + * @{ + */ +#define UART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ +#define UART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ +#define UART_CFG_GET_BOUDRATE UART_CFG_GET_BOUDRATE_ENABLE /* Disable/Enable Get Bourate Setting */ + +#define UART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ +#define UART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ +#define UART_CFG_GET_BOUDRATE_TYPE UART_CFG_GET_BOUDRATE_TYPE_ALL + +#define UART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)3) /*!< Error Margin(%). */ +#define UART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ +/** + * @} + */ /* End of group UART_BourateConfig */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_typedef UART Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_fuctions UART Private Fuctions + * @{ + */ +#ifdef DEBUG +__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param); +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param); +__STATIC_INLINE int32_t check_param_data_direction(uint32_t param); +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); +__STATIC_INLINE int32_t check_param_data_length(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_err_int(uint32_t param); +__STATIC_INLINE int32_t check_param_prescaler(uint32_t param); +__STATIC_INLINE int32_t check_param_division(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); +#endif /* #ifdef DEBUG */ +__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level); +__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level); +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) +static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); +#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Noize Fileter's parameter. + * @param param :Noize fileter's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_NoiseFilter"UART_NOISE_FILTER_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_NOISE_FILTER_NON: + case UART_NOISE_FILTER_2_T0: + case UART_NOISE_FILTER_4_T0: + case UART_NOISE_FILTER_8_T0: + case UART_NOISE_FILTER_2_CLOCK: + case UART_NOISE_FILTER_3_CLOCK: + case UART_NOISE_FILTER_4_CLOCK: + case UART_NOISE_FILTER_5_CLOCK: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the CTS Handshake's parameter. + * @param param :CTS Handshake's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_CTSHandshake"UART_CTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_CTS_DISABLE: + case UART_CTS_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the RTS Handshake's parameter. + * @param param :RTS Handshake's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RTSHandshake"UART_RTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RTS_DISABLE: + case UART_RTS_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Complementation's parameter. + * @param param :Data Complementation's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataComplementation"UART_DATA_COMPLEMENTION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_COMPLEMENTION_DISABLE: + case UART_DATA_COMPLEMENTION_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataDirection"UART_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_DIRECTION_LSB: + case UART_DATA_DIRECTION_MSB: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Stop Bit's parameter. + * @param param :Stop Bit's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_StopBit"UART_STOP_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_STOP_BIT_1: + case UART_STOP_BIT_2: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ParityBit"UART_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PARITY_BIT_ODD: + case UART_PARITY_BIT_EVEN: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ParityEnable"UART_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PARITY_DISABLE: + case UART_PARITY_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataLength"UART_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_length(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_LENGTH_7: + case UART_DATA_LENGTH_8: + case UART_DATA_LENGTH_9: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level Range's parameter. + * @param param :Tx Fill Level Range's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + /*--- Now, UART_TX_FILL_RANGE_MIN is 0. ---*/ +#if 0 + if ((UART_TX_FILL_RANGE_MIN <= param) && (param <= UART_TX_FILL_RANGE_MAX)) +#else + if (param <= UART_TX_FILL_RANGE_MAX) +#endif + { + result = UART_PARAM_OK; + } + + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if ((UART_RX_FILL_RANGE_MIN <= param) && (param <= UART_RX_FILL_RANGE_MAX)) { + result = UART_PARAM_OK; + } + + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxFIFOInterrupt"UART_TX_FIFO_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_TX_FIFO_INT_DISABLE: + case UART_TX_FIFO_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_TX_INT_DISABLE: + case UART_TX_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxFIFOInterrupt"UART_RX_FIFO_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RX_FIFO_INT_DISABLE: + case UART_RX_FIFO_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxInterrupt"UART_RX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RX_INT_DISABLE: + case UART_RX_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ErrorInterrupt"UART_ERR_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_err_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_ERR_INT_DISABLE: + case UART_ERR_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Prescaler's parameter. + * @param param :Prescaler's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_Prescaler"UART_PLESCALER_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_prescaler(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PLESCALER_1: + case UART_PLESCALER_2: + case UART_PLESCALER_4: + case UART_PLESCALER_8: + case UART_PLESCALER_16: + case UART_PLESCALER_32: + case UART_PLESCALER_64: + case UART_PLESCALER_128: + case UART_PLESCALER_256: + case UART_PLESCALER_512: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Division's parameter. + * @param param :Division's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_Division"UART_DIVISION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_division(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DIVISION_DISABLE: + case UART_DIVISION_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range K's parameter. + * @param param :Range K's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RangeK"UART_RANGE_K_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + /*--- Now, UART_RANGE_K_MIN is 0. ---*/ +#if 0 + if ((UART_RANGE_K_MIN <= param) && (param <= UART_RANGE_K_MAX)) +#else + if (param <= UART_RANGE_K_MAX) +#endif + { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range N's parameter. + * @param param :Range N's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RangeN"UART_RANGE_N_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if ((UART_RANGE_N_MIN <= param) && (param <= UART_RANGE_N_MAX)) { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for transmit. + * @param param :Num of buff. + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if (param != 0) { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for receive. + * @param param :Num of buff. + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if (param >= 8) { + result = UART_PARAM_OK; + } + + return (result); +} +#endif /* #ifdef DEBUG */ + +/*--------------------------------------------------*/ +/** + * @brief Convert Tx FIFO fill level to register. + * @param level :Fill Level. + * @retval Register value. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level) +{ + uint32_t result = (level << 12); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Convert Rx FIFO fill level to register. + * @param level :Fill Level. + * @retval Register value. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level) +{ + uint32_t result; + + if (level < 8) { + result = (level << 8); + } else { + result = 0; + } + + return (result); +} + +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) +/*--------------------------------------------------*/ +/** + * @brief Check the within error margin. + * @param boudrate :Boudrate(bps). + * @param clock :Clock(hz). + * @param p_clk :Select Clock Setting. + * @param boudrate :Boudrate(bps). + * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" + * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" + * @param p_range64 :Error range(after fixed point bit shift). + * @retval TXZ_SUCCESS :Within error margin. + * @retval TXZ_ERROR :Without error margin. + * @note For N+(64-K)/64 division. + */ +/*--------------------------------------------------*/ +static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) +{ + TXZ_Result result = TXZ_ERROR; + uint64_t boud64 = 0; + uint64_t tx64 = 0; + uint64_t work64 = 0; + + /* phi Tx */ + uint32_t prescaler = (p_clk->prsel >> 4); + + work64 = (uint64_t)((uint64_t)1 << prescaler); + tx64 = (uint64_t)((uint64_t)clock << (UART_CFG_BOUDRATE_FIXED_POINT_BIT + 2)); + tx64 /= work64; + + /* Bourate */ + boud64 = (uint64_t)((uint64_t)boudrate << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + *p_range64 = ((boud64 / 100) * UART_CFG_BOUDRATE_ERROR_RANGE); + /* BourateX */ + work64 = (uint64_t)((uint64_t)n << 6); + work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); + work64 = (tx64 / work64); + if (boud64 >= *p_range64) { + if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) { + if (boud64 < work64) { + *p_range64 = (work64 - boud64); + } else { + *p_range64 = (boud64 - work64); + } + result = TXZ_SUCCESS; + } + } + + return (result); +} +#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + +/** + * @} + */ /* End of group UART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the UART object. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_init(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(check_param_prescaler(p_obj->init.clock.prsel)); + assert_param(check_param_division(p_obj->init.boudrate.ken)); + assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); + assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); + assert_param(check_param_tx_int(p_obj->init.inttx)); + assert_param(check_param_rx_int(p_obj->init.intrx)); + assert_param(check_param_err_int(p_obj->init.interr)); + assert_param(check_param_tx_fifo_int(p_obj->init.txfifo.inttx)); + assert_param(check_param_tx_fill_level_range(p_obj->init.txfifo.level)); + assert_param(check_param_rx_fifo_int(p_obj->init.rxfifo.intrx)); + assert_param(check_param_rx_fill_level_range(p_obj->init.rxfifo.level)); + assert_param(check_param_noize_filter(p_obj->init.nf)); + assert_param(check_param_cts_handshake(p_obj->init.ctse)); + assert_param(check_param_rts_handshake(p_obj->init.rtse)); + assert_param(check_param_data_complemention(p_obj->init.iv)); + assert_param(check_param_data_direction(p_obj->init.dir)); + assert_param(check_param_stop_bit(p_obj->init.sblen)); + assert_param(check_param_parity_bit(p_obj->init.even)); + assert_param(check_param_parity_enable(p_obj->init.pe)); + assert_param(check_param_data_length(p_obj->init.sm)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* SW Reset */ + /*------------------------------*/ + /*--- UARTxSWRST ---*/ + /* SW Reset initializes UARTxTRANS, UARTxDR, UARTxSR, UARTxERR. */ + /* Wait to "SWRSTF = 0". */ + while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + /* no process */ + } + /* Write to SWRST(=10). */ + p_obj->p_instance->SWRST = UARTxSWRST_SWRST_10; + /* Write to SWRST(=01). */ + p_obj->p_instance->SWRST = UARTxSWRST_SWRST_01; + /* Wait to "SWRSTF = 0". */ + while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + /* no process */ + } + /*------------------------------*/ + /* FIFO Clear */ + /*------------------------------*/ + /*--- UARTxFIFOCLR ---*/ + /* Write to TFCLR(=1), and RFCLR(=1) */ + p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- UARTxCLK ---*/ + /* Reflecting "p_obj->init.clk" */ + p_obj->p_instance->CLK = (p_obj->init.clock.prsel & UART_UARTxCLK_MASK); + /*--- UARTxBRD ---*/ + /* Reflecting "p_obj->init.brd" */ + /* Be careful, BRK needs to bit shit. */ + { + uint32_t brk = (p_obj->init.boudrate.brk << 16); + p_obj->p_instance->BRD = (p_obj->init.boudrate.ken | brk | p_obj->init.boudrate.brn); + } + /*--- UARTxCR0 ---*/ + /* Reflecting "p_obj->init.cnt0" */ + p_obj->p_instance->CR0 = (p_obj->init.hct | p_obj->init.hcm | + p_obj->init.hcc | p_obj->init.lbc | + p_obj->init.nf | p_obj->init.ctse | + p_obj->init.rtse | p_obj->init.iv | + p_obj->init.dir | p_obj->init.sblen | + p_obj->init.even | p_obj->init.pe | + p_obj->init.sm); + /*--- UARTxCR1 ---*/ + /* Reflecting "p_obj->init.cnt1" */ + /* Fixed: "DMATE=0", "DMARE=0". */ + /* Be careful, "TIL", "RIL" need to bit shit. */ + p_obj->p_instance->CR1 = (convert_tx_fifo_fill_level_to_reg(p_obj->init.txfifo.level) | + convert_rx_fifo_fill_level_to_reg(p_obj->init.rxfifo.level) | + p_obj->init.txfifo.inttx | p_obj->init.inttx | + p_obj->init.rxfifo.intrx | p_obj->init.intrx | + p_obj->init.interr); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the UART object. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_deinit(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*--- UARTxCR1 ---*/ + p_obj->p_instance->CR1 = 0; + /*--- UARTxCR0 ---*/ + p_obj->p_instance->CR0 = 0; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_discard_transmit(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t trans = 0; + uint32_t count = 10000000; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Read current UARTxTRANS value. */ + trans = p_obj->p_instance->TRANS; + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); + while ((p_obj->p_instance->SR & UART_TX_STATE_MASK) == UART_TX_STATE_RUN) { + if (--count == 0) { + break; + } + } + /*--- UARTxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR); + /*--- UARTxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (UARTxERR_TRGERR_W_CLEAR); + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /* Return RXE setting to UARTxTRANS */ + p_obj->p_instance->TRANS = (trans & UARTxTRANS_RXE_MASK); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_discard_receive(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t trans = 0; + uint32_t count = 10000000; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Read current UARTxTRANS value. */ + trans = p_obj->p_instance->TRANS; + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Clear the receive's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); + while ((p_obj->p_instance->SR & UART_RX_STATE_MASK) == UART_RX_STATE_RUN) { + if (--count == 0) { + break; + } + } + /*--- UARTxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to OVRERR(=1), PERR(=1), and FERR(=1), BERR(=1) */ + p_obj->p_instance->ERR = (UARTxERR_OVRERR_W_CLEAR | UARTxERR_PERR_W_CLEAR | + UARTxERR_FERR_W_CLEAR | UARTxERR_BERR_W_CLEAR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /* Return TXE setting to UARTxTRANS */ + p_obj->p_instance->TRANS = (trans & (UARTxTRANS_BK_MASK | UARTxTRANS_TXTRG_MASK | UARTxTRANS_TXE_MASK)); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :UART object. + * @param p_info :The information of transmit data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + assert_param(check_param_tx_buff_num(p_info->tx16.num)); + } else { + /* 7/8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + assert_param(check_param_tx_buff_num(p_info->tx8.num)); + } +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + } else { + /* 7/8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /*--- UARTxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + uint32_t tlvl = (p_obj->p_instance->SR & UARTxSR_TLVL_MASK); + tlvl >>= 8; + /* FIFO Max = UART_TX_FIFO_MAX */ + if (tlvl > UART_TX_FIFO_MAX) { + tlvl = UART_TX_FIFO_MAX; + } + /* Empty FIFO Num */ + { + uint32_t work = tlvl; + tlvl = (UART_TX_FIFO_MAX - work); + } + /*--- UARTxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_7: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=1). */ + /* Bitband Access. */ + enable_UARTxTRANS_TXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :UART object. + * @param p_info :The information of receive buffer. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref UART_FifoMax) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + assert_param(check_param_rx_buff_num(p_info->rx16.num)); + } else { + /* 7/8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + assert_param(check_param_rx_buff_num(p_info->rx8.num)); + } +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + } else { + /* 7/8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to RXE(=1). */ + /* Bitband Access. */ + enable_UARTxTRANS_RXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_transmit_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current UARTxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) { + /*---- UARTxSR ---*/ + /* Check the transmit's end flag. */ + if (((status & UARTxSR_TXEND_MASK) == UARTxSR_TXEND_R_END) || + ((status & UARTxSR_TXFF_MASK) == UARTxSR_TXFF_R_REACHED)) { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + uint32_t tlvl = (status & UARTxSR_TLVL_MASK); + tlvl >>= 8; + /* FIFO Max = UART_TX_FIFO_MAX */ + if (tlvl > UART_TX_FIFO_MAX) { + tlvl = UART_TX_FIFO_MAX; + } + /* Get the empty num in FIFO. */ + { + uint32_t work = tlvl; + tlvl = (UART_TX_FIFO_MAX - work); + } + if (tlvl == UART_TX_FIFO_MAX) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + break; + default: + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + break; + } + } + if (txDone == TXZ_DONE) { + /*=== Transmit Done!! ===*/ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != UART_NULL) { + /* Call the transmit handler with TXZ_SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- UARTxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_7: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_receive_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current UARTxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) { + /* Check the receive's end flag. */ + if (((status & UARTxSR_RXEND_MASK) == UARTxSR_RXEND_R_END) || + ((status & UARTxSR_RXFF_MASK) == UARTxSR_RXFF_R_REACHED)) { + /* Read FIFO fill level. */ + uint32_t rlvl = (status & UARTxSR_RLVL_MASK); + /* FIFO Max = UART_RX_FIFO_MAX */ + if (rlvl > UART_RX_FIFO_MAX) { + rlvl = UART_RX_FIFO_MAX; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) { + uint32_t i; + for (i = 0; i < rlvl; i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + *(p_obj->receive.info.rx16.p_data + i) = (uint16_t)(p_obj->p_instance->DR & UARTxDR_DR_9BIT_MASK); + break; + case UART_DATA_LENGTH_8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_8BIT_MASK); + break; + case UART_DATA_LENGTH_7: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_7BIT_MASK); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != UART_NULL) { + uart_receive_t param; + + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + } else { + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + } + /* Call the receive handler with TXZ_SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_error_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current UARTxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- UARTxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & UARTxERR_TRGERR_MASK) == UARTxERR_TRGERR_R_ERR) { + /*------------------------------*/ + /* Transmit Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) { + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != UART_NULL) { + /* Call the transmit handler with TXZ_ERROR. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* OVRERR */ + if ((error & UARTxERR_OVRERR_MASK) == UARTxERR_OVRERR_R_ERR) { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & UARTxERR_PERR_MASK) == UARTxERR_PERR_R_ERR) { + err = TXZ_ERROR; + } + /* FERR */ + if ((error & UARTxERR_FERR_MASK) == UARTxERR_FERR_R_ERR) { + err = TXZ_ERROR; + } + /* BERR */ + if ((error & UARTxERR_BERR_MASK) == UARTxERR_BERR_R_ERR) { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != UART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, UART_NULL); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref UART_SettingEnable. | + * | 30-16 | - | - | + * | 15 | TXRUN | Transmitting State Flag. Use @ref UART_TxState. | + * | 14 | TXEND | Transmitting Done Flag. Use @ref UART_TxDone. | + * | 13 | TXFF | Reach Transmitting Fill Level Flag. Use @ref UART_TxReachFillLevel. | + * | 12 | - | - | + * | 11-8 | TLVL | Current Transmitting FIFO Level. Use @ref UART_TxFifoLevel | + * | 7 | RXRUN | Receive State Flag. Use @ref UART_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref UART_RxDone. | + * | 5 | RXFF | Reach Receive Fill Level Flag. Use @ref UART_RxReachFillLevel | + * | 4 | - | - | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref UART_RxFifoLevel | + * + * @param p_obj :UART object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Read current UARTxSR. */ + *p_status = p_obj->p_instance->SR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-5 | - | - | + * | 4 | TRGERR | Transmitting Trigger Error. Use @ref UART_TriggerErr. | + * | 3 | OVRERR | Overrun Error. Use @ref UART_OverrunErr. | + * | 2 | PERR | Parity Error. Use @ref UART_ParityErr. | + * | 1 | FERR | Framing Error. Use @ref UART_FramingErr. | + * | 0 | BERR | Break Error Flag. Use @ref UART_BreakErr. | + * + * @param p_obj :UART object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_error)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Error Read */ + /*------------------------------*/ + /*--- UARTxERR ---*/ + /* Read current UARTxERR. */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get the setting of boudrate. + * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". + * @param p_clk :Select Clock Setting. + * @param boudrate :Boudrate(bps). + * @param p_brd :Save area for Division Setting. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Not support setting. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_brd) +{ + TXZ_Result result = TXZ_ERROR; +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) + uint64_t tx = 0; + uint64_t work = 0; + uint64_t range64 = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_clk)); + assert_param(IS_POINTER_NOT_NULL(p_brd)); + /* Check the parameter of UARTxCLK. */ +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Calculate Division Setting */ + /*------------------------------*/ + if ((clock > 0) && (boudrate > 0)) { + /*--- phi Tx ---*/ + uint32_t prescaler = (p_clk->prsel >> 4); + + work = (uint64_t)((uint64_t)1 << prescaler); + tx = (uint64_t)((uint64_t)clock << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + tx /= work; + + /*--- N+(64-K)/64 division ---*/ + { + uint8_t k = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + + work = ((uint64_t)boudrate); + tx /= work; + tx >>= 4; + for (k = UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) { + work = tx + (uint64_t)k; + if (work >= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT)) { + work -= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + work >>= UART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ + if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { + uint64_t workRange = 0; + + /* Verification */ + if (verification_boudrate64(clock, p_clk, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) { +#if (UART_CFG_GET_BOUDRATE_TYPE == UART_CFG_GET_BOUDRATE_TYPE_ALL) + /* Compare the previous range. */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + } else { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + result = TXZ_SUCCESS; +#else + /* Finish!! */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + } else { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + result = TXZ_SUCCESS; + loopBreak = TXZ_DONE; +#endif + } + } + } + } + } + } +#endif /* (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + + return (result); +} + +/** + * @} + */ /* End of group UART_Exported_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PeripheralNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PeripheralNames.h new file mode 100644 index 00000000000..652ec491ab7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PeripheralNames.h @@ -0,0 +1,151 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SERIAL_0 = 0, + SERIAL_1, + SERIAL_2, + SERIAL_3, + INVALID_SERIAL = (int)NC +} UARTName; + + +typedef enum { + PWM_0 = 0, + PWM_1, + PWM_2, + PWM_3, + PWM_4, + INVALID_PWM = (int)NC +} PWMName; + +typedef enum { + ADC_A0 = 0, + ADC_A1, + ADC_A2, + ADC_A3, + ADC_A4, + ADC_A5, + ADC_A6, + ADC_A7, + ADC_A8, + ADC_A9, + ADC_A10, + ADC_A11, + ADC_A12, + ADC_A13, + ADC_A14, + ADC_A15, + ADC_A16, + ADC_A17, + ADC_A18, + INVALID_ADC = (int)NC +} ADCName; + +typedef enum { + I2C_0 = 0, + I2C_1, + INVALID_I2C = (int)NC +} I2CName; + +typedef enum { + SPI_0 = 0, + SPI_1, + INVALID_SPI = (int)NC +} SPIName; + +typedef enum { + GPIO_IRQ_0 = 0, + GPIO_IRQ_1, + GPIO_IRQ_2, + GPIO_IRQ_3, + GPIO_IRQ_4, + GPIO_IRQ_5, + GPIO_IRQ_6, + GPIO_IRQ_7, + GPIO_IRQ_8, + GPIO_IRQ_9, + GPIO_IRQ_A, + GPIO_IRQ_B, + GPIO_IRQ_C, + GPIO_IRQ_D, + GPIO_IRQ_E, + GPIO_IRQ_F, + GPIO_IRQ_10, + GPIO_IRQ_11, + GPIO_IRQ_12, + GPIO_IRQ_13, + GPIO_IRQ_14, + GPIO_IRQ_15, + INVALID_GPIO_IRQ = (int)NC +} GPIO_IRQName; + +// DAP UART +#if defined(MBED_CONF_TARGET_STDIO_UART_TX) +#define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX +#else +#define STDIO_UART_TX CONSOLE_TX +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART_RX) +#define STDIO_UART_RX MBED_CONF_TARGET_STDIO_UART_RX +#else +#define STDIO_UART_RX CONSOLE_RX +#endif + +#define SERIAL_TX CONSOLE_TX +#define SERIAL_RX CONSOLE_RX + +#define STDIO_UART SERIAL_0 + +// TxD RxD +#define MBED_UART0 PC0, PC1 +#define MBED_UART1 PC4, PC5 +#define MBED_UART2 PU0, PU1 +#define MBED_UART3 PF6, PF7 +#define MBED_UARTUSB CONSOLE_TX, CONSOLE_RX + +// SDA SCK +#define MBED_I2C0 PD3, PD4 + +// MOSI, MISO, SCLK SS +#define MBED_SPI0 PA3, PA2, PA4, PA1 +#define MBED_SPI1 PG5, PG4, PG6, PG1 + +#define MBED_ANALOGIN0 A0 +#define MBED_ANALOGIN1 A1 +#define MBED_ANALOGIN2 A2 +#define MBED_ANALOGIN3 A3 +#define MBED_ANALOGIN4 A4 +#define MBED_ANALOGIN5 A5 + +#define MBED_PWMOUT0 PF4 +#define MBED_PWMOUT2 PU2 +#define MBED_PWMOUT3 PC2 +#define MBED_PWMOUT4 PN1 + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PinNames.h new file mode 100644 index 00000000000..b332f7ddda9 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PinNames.h @@ -0,0 +1,146 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xFF) +#define PIN_POS(X) ((uint32_t)(X) & 0x7) + +// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction +#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0)) +#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) +#define PIN_DIR(X) ((X) & 0xffff) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INOUT +} PinDirection; + +typedef enum { + // TMPM4KN Pin Names + PA0 = 0 << 3, PA1, PA2, PA3, PA4, + PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, + PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, + PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, + PH0 = 7 << 3, PH1, + PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, + PK0 = 9 << 3, PK1, PK2, PK3, PK4, + PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, + PM0 = 11 << 3, PM1, PM2, + PN0 = 12 << 3, PN1, PN2, + PU0 = 13 << 3, PU1, PU2, PU3, PU4, PU5, PU6, PU7, + PV0 = 14 << 3, PV1, + + // External data bus Pin Names + D0 = PF7, + D1 = PF6, + D2 = PD4, + D3 = PD5, + D4 = PC6, + D5 = PC7, + D6 = PA0, + D7 = PC3, + D8 = PD0, + D9 = PD1, + D10 = PG1, + D11 = PG5, + D12 = PG4, + D13 = PG6, + D14 = PC0, + D15 = PC1, + + // Analogue in pins + A0 = PM2, + A1 = PM1, + A2 = PM0, + A3 = PL3, + A4 = PL1, + + // DAP_UART + CONSOLE_TX = PC0, + CONSOLE_RX = PC1, + MBEDIF_TXD = CONSOLE_TX, + MBEDIF_RXD = CONSOLE_RX, + + // Push buttons + SW1 = PG3, + SW2 = PG4, + SW3 = PG5, + SW4 = PG6, + + + // TSPI2 + MOSI = D11, + MISO = D12, + SCLK = D13, + CS = D10, + + // SD Shield TSPI2 + SD_SEL = CS, // Chip select + SD_CLK = SCLK, // SPI clock + SD_MISO = MISO, // Master in Salve out + SD_MOSI = MOSI, // Master out Salve in + + // I2C pins + SDA = D14, + SCL = D15, + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + +// LED definitions +#define LED1 PB0 +#define LED2 PB2 +#define LED3 PB4 +#define LED4 PV0 +#define LED5 PV1 +#define LED6 PB6 + +// Standardized button names +#define BUTTON1 SW1 +#define BUTTON2 SW2 +#define BUTTON3 SW3 +#define BUTTON4 SW4 + +//I2C +#define I2C_SDA SDA +#define I2C_SCL SCL + +typedef enum { + PullUp = 0, + PullDown, + PullNone, + OpenDrain, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PortNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PortNames.h new file mode 100644 index 00000000000..6cc712c1a80 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PortNames.h @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB, + PortC, + PortD, + PortE, + PortF, + PortG, + PortH, + PortJ, + PortK, + PortL, + PortM, + PortN, + PortU, + PortV, +} PortName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/analogin_api.c new file mode 100644 index 00000000000..de8fa0fd85e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/analogin_api.c @@ -0,0 +1,128 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogin_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_wait_api.h" +#include "mbed_error.h" +#include "txzp_adc_include.h" + +#define ADC_12BIT_RANGE 0xFFF +#define CONVERSION_FLAG 0x4 +#define SINGLE_CONVERSION 0xF + +static const PinMap PinMap_ADC[] = { + {PM2, ADC_A5, PIN_DATA(0, 0)}, + {PM1, ADC_A6, PIN_DATA(0, 0)}, + {PM0, ADC_A7, PIN_DATA(0, 0)}, + {PL7, ADC_A8, PIN_DATA(0, 0)}, + {PL6, ADC_A9, PIN_DATA(0, 0)}, + {PL5, ADC_A13, PIN_DATA(0, 0)}, + {PL3, ADC_A14, PIN_DATA(0, 0)}, + {PL1, ADC_A15, PIN_DATA(0, 0)}, + {PL0, ADC_A16, PIN_DATA(0, 0)}, + {PL2, ADC_A17, PIN_DATA(0, 0)}, + {PL4, ADC_A18, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +void analogin_init(analogin_t *obj, PinName pin) +{ + // Check that pin belong to ADC module + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + + MBED_ASSERT(obj->adc != (ADCName)NC); + + // Enable ADC clock supply + TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; + TSB_CG_SPCLKEN_ADCKEN0 = TXZ_ENABLE; + TSB_CG_SPCLKEN_TRCKEN = TXZ_ENABLE; + + // Enable clock for GPIO + if (obj->adc <= ADC_A7) { + // Enable clock for GPIO port M + TSB_CG_FSYSMENA_IPMENA11 = TXZ_ENABLE; + } else if (obj->adc <= ADC_A18) { + // Enable clock for GPIO port L + TSB_CG_FSYSMENA_IPMENA10 = TXZ_ENABLE; + } else { + // Nothing when its NC + } + + // Set pin function as ADC + pinmap_pinout(pin, PinMap_ADC); + + // Initialize + obj->p_adc.p_instance = TSB_ADA; + obj->p_adc.init.id = SINGLE_CONVERSION; + obj->p_adc.init.convert_time = ADC_CONVERT_TIME_0_96_AVDD_4_5; + obj->p_adc.init.rcut = ADC_RCUT_NORMAL; + obj->p_adc.handler = NULL; + obj->pin = pin; + + if (adc_init(&obj->p_adc) != TXZ_SUCCESS) { + error("Failed : ADC Initialization"); + } + + // ADC channel setting + obj->param.ain = obj->adc; + + if (adc_channel_setting(&obj->p_adc, obj->param.ain, &obj->param) != TXZ_SUCCESS) { + error("Failed : ADC channel setting"); + } +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint32_t adc_result = 0; + + // Assert that ADC channel is valid + MBED_ASSERT(obj->adc != (ADCName)NC); + + if (adc_start(&obj->p_adc) == TXZ_SUCCESS) { + // adc started + } + + // Wait until AD conversion complete + while ((obj->p_adc.p_instance->ST & CONVERSION_FLAG)) { + // Do nothing + } + + if (adc_channel_get_value(&obj->p_adc, obj->param.ain, &adc_result) != TXZ_SUCCESS) { + error("Failed : To read ADC converted result"); + } + + if (adc_stop(&obj->p_adc) != TXZ_SUCCESS) { + error("Failed : To Stop ADC Conversion"); + } + + return (uint16_t)adc_result; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = 0; + + value = analogin_read_u16(obj); + + return (float)(value * (1.0f / (float)ADC_12BIT_RANGE)); +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/crc_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/crc_api.c new file mode 100644 index 00000000000..2ced07a8cd8 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/crc_api.c @@ -0,0 +1,80 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "crc_api.h" +#include "device.h" + +#ifdef DEVICE_CRC + +static bool reflect_in; +static bool reflect_out; +static uint32_t final_xor; + +bool hal_crc_is_supported(const crc_mbed_config_t *config) +{ + return (config != NULL); +} + +void hal_crc_compute_partial_start(const crc_mbed_config_t *config) +{ + TSB_CG_FSYSENA_IPENA00 = TXZ_ENABLE; + + // Intial Value as initial_xor + TSB_CRC->CLC = config->initial_xor; + reflect_in = config->reflect_in; + reflect_out = config->reflect_out; + final_xor = config->final_xor; + + // Data width setting CRC data width is 8 bits (--01) + // Form setting CRC form is CRC16 (00--) or CRC32 (11--) + TSB_CRC->TYP = config->width == 16 ? 0x01 : 0x0D; +} + +void hal_crc_compute_partial(const uint8_t *data, const size_t size) +{ + if (data && size) { + uint32_t index = 0U; + bool reflect = reflect_in; + for (index = 0U; index < size; index++) { + unsigned int byte = data[index]; + if (reflect) { + byte = __RBIT(byte) >> 24; + } + TSB_CRC->DIN = byte; + } + } +} + +uint32_t hal_crc_get_result(void) +{ + uint32_t result; + + // Note: Please read [CRCCLC] twice and use the result of the 2nd time + result = TSB_CRC->CLC; + result = TSB_CRC->CLC; + if (reflect_out) { + result = __RBIT(result); + if ((TSB_CRC->TYP & 0x0C) == 0) { + result >>= 16; + } + } + result ^= final_xor; + + return (result); +} +#endif // DEVICE_CRC diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device.h new file mode 100644 index 00000000000..7fd26fc35e5 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device.h @@ -0,0 +1,25 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 32 + +#include +#include "objects.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TMPM4KNA.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TMPM4KNA.h new file mode 100644 index 00000000000..69e34cc37e8 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TMPM4KNA.h @@ -0,0 +1,4157 @@ +/** + ******************************************************************************* + * @file TMPM4KNA.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4KNA' Device Series + * @version V1.0.0.0 + * $Date:: #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER + * @{ + */ + +/** @addtogroup TMPM4KNA + * @{ + */ + +#ifndef __TMPM4KNA_H__ +#define __TMPM4KNA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** TMPM4KNA Specific Interrupt Numbers *******************************************************************/ + INT00_IRQn = 0, /*!< Interrupt pin 00 */ + INT01_IRQn = 1, /*!< Interrupt pin 01a/00b */ + INT02_IRQn = 2, /*!< Interrupt pin 02a/00b */ + INT03_IRQn = 3, /*!< Interrupt pin 03a/03b */ + INT04_IRQn = 4, /*!< Interrupt pin 04a/04b */ + INT05_IRQn = 5, /*!< Interrupt pin 05a/05b */ + INT06_IRQn = 6, /*!< Interrupt pin 06a/06b */ + INT07_IRQn = 7, /*!< Interrupt pin 07a/07b */ + INT08_IRQn = 8, /*!< Interrupt pin 08a/08b */ + INT09_IRQn = 9, /*!< Interrupt pin 09 */ + INT10_IRQn = 10, /*!< Interrupt pin 10 */ + INT11_IRQn = 11, /*!< Interrupt pin 11a/11b */ + INT12_IRQn = 12, /*!< Interrupt pin 12 */ + INT13_IRQn = 13, /*!< Interrupt pin 13 */ + INT14_IRQn = 14, /*!< Interrupt pin 14a/14b */ + INT15_IRQn = 15, /*!< Interrupt pin 15 */ + INT16_IRQn = 16, /*!< Interrupt pin 16a/16b */ + INT17_IRQn = 17, /*!< Interrupt pin 17a/17b */ + INT18_IRQn = 18, /*!< Interrupt pin 18a/18b */ + INT21_IRQn = 21, /*!< Interrupt pin 21 */ + INTVCN0_IRQn = 22, /*!< A-VE+ ch0 Interrupt */ + INTVCT0_IRQn = 23, /*!< A-VE+ ch0 Task termination interrupt */ + INTEMG0_IRQn = 24, /*!< A-PMD ch0 EMG interrupt */ + INTEMG1_IRQn = 25, /*!< A-PMD ch1 EMG interrupt */ + INTEMG2_IRQn = 26, /*!< A-PMD ch2 EMG interrupt */ + INTOVV0_IRQn = 27, /*!< A-PMD ch0 OVV interrupt */ + INTOVV1_IRQn = 28, /*!< A-PMD ch1 OVV interrupt */ + INTOVV2_IRQn = 29, /*!< A-PMD ch2 OVV interrupt */ + INTPWM0_IRQn = 30, /*!< A-PMD ch0 PWM interrupt */ + INTPWM1_IRQn = 31, /*!< A-PMD ch1 PWM interrupt */ + INTPWM2_IRQn = 32, /*!< A-PMD ch2 PWM interrupt */ + INTENC00_IRQn = 33, /*!< A-ENC32 ch0 Encoder interrupt 0 */ + INTENC01_IRQn = 34, /*!< A-ENC32 ch0 Encoder interrupt 1 */ + INTENC10_IRQn = 35, /*!< A-ENC32 ch1 Encoder interrupt 0 */ + INTENC11_IRQn = 36, /*!< A-ENC32 ch1 Encoder interrupt 1 */ + INTENC20_IRQn = 37, /*!< A-ENC32 ch2 Encoder interrupt 0 */ + INTENC21_IRQn = 38, /*!< A-ENC32 ch2 Encoder interrupt 1 */ + INTADAPDA_IRQn = 39, /*!< ADC unit A PMD trigger program interrupt A */ + INTADAPDB_IRQn = 40, /*!< ADC unit A PMD trigger program interrupt B */ + INTADACP0_IRQn = 41, /*!< ADC unit A Monitor function 0 interrupt */ + INTADACP1_IRQn = 42, /*!< ADC unit A Monitor function 1 interrupt */ + INTADATRG_IRQn = 43, /*!< ADC unit A General purpose trigger program interrupt */ + INTADASGL_IRQn = 44, /*!< ADC unit A Single program interrupt */ + INTADACNT_IRQn = 45, /*!< ADC unit A Continuity program interrupt */ + INTADBPDA_IRQn = 46, /*!< ADC unit B PMD trigger program interrupt A */ + INTADBPDB_IRQn = 47, /*!< ADC unit B PMD trigger program interrupt B */ + INTADBCP0_IRQn = 48, /*!< ADC unit B Monitor function 0 interrupt */ + INTADBCP1_IRQn = 49, /*!< ADC unit B Monitor function 1 interrupt */ + INTADBTRG_IRQn = 50, /*!< ADC unit B General purpose trigger program interrupt */ + INTADBSGL_IRQn = 51, /*!< ADC unit B Single program interrupt */ + INTADBCNT_IRQn = 52, /*!< ADC unit B Continuity program interrupt */ + INTADCPDA_IRQn = 53, /*!< ADC unit C PMD trigger program interrupt A */ + INTADCPDB_IRQn = 54, /*!< ADC unit C PMD trigger program interrupt B */ + INTADCCP0_IRQn = 55, /*!< ADC unit C Monitor function 0 interrupt */ + INTADCCP1_IRQn = 56, /*!< ADC unit C Monitor function 1 interrupt */ + INTADCTRG_IRQn = 57, /*!< ADC unit C General purpose trigger program interrupt */ + INTADCSGL_IRQn = 58, /*!< ADC unit C Single program interrupt */ + INTADCCNT_IRQn = 59, /*!< ADC unit C Continuity program interrupt */ + INTSC0RX_IRQn = 60, /*!< TSPI/UART ch0 Reception interrupt */ + INTSC0TX_IRQn = 61, /*!< TSPI/UART ch0 Transmit interrupt */ + INTSC0ERR_IRQn = 62, /*!< TSPI/UART ch0 Error interrupt */ + INTSC1RX_IRQn = 63, /*!< TSPI/UART ch1 Reception interrupt */ + INTSC1TX_IRQn = 64, /*!< TSPI/UART ch1 Transmit interrupt */ + INTSC1ERR_IRQn = 65, /*!< TSPI/UART ch1 Error interrupt */ + INTSC2RX_IRQn = 66, /*!< UART ch2 Reception interrupt */ + INTSC2TX_IRQn = 67, /*!< UART ch2 Transmit interrupt */ + INTSC2ERR_IRQn = 68, /*!< UART ch2 Error interrupt */ + INTSC3RX_IRQn = 69, /*!< UART ch3 Reception interrupt */ + INTSC3TX_IRQn = 70, /*!< UART ch3 Transmit interrupt */ + INTSC3ERR_IRQn = 71, /*!< UART ch3 Error interrupt */ + INTI2C0NST_IRQn = 72, /*!< I2C ch0 Interrupt / EI2C ch0 Status interrupt */ + INTI2C0ATX_IRQn = 73, /*!< I2C ch0 Arbitration lost detection interrupt / EI2C ch0 Transmission buffer empty interrupt*/ + INTI2C0BRX_IRQn = 74, /*!< I2C ch0 Bus free detection interrupt / EI2C ch0 Reception buffer full interrupt*/ + INTI2C0NA_IRQn = 75, /*!< I2C ch0 NACK detection interrupt */ + INTI2C1NST_IRQn = 76, /*!< I2C ch1 Interrupt / EI2C ch1 Status interrupt */ + INTI2C1ATX_IRQn = 77, /*!< I2C ch1 Arbitration lost detection interrupt / EI2C ch1 Transmission buffer empty interrupt*/ + INTI2C1BRX_IRQn = 78, /*!< I2C ch1 Bus free detection interrupt / EI2C ch1 Reception buffer full interrupt*/ + INTI2C1NA_IRQn = 79, /*!< I2C ch1 NACK detection interrupt */ + INTT32A00AC_IRQn = 83, /*!< T32A ch0 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A00ACCAP0_IRQn = 84, /*!< T32A ch0 Timer A/C Input capture 0 */ + INTT32A00ACCAP1_IRQn = 85, /*!< T32A ch0 Timer A/C Input capture 1 */ + INTT32A00B_IRQn = 86, /*!< T32A ch0 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A00BCAP0_IRQn = 87, /*!< T32A ch0 Timer B Input capture 0 */ + INTT32A00BCAP1_IRQn = 88, /*!< T32A ch0 Timer B Input capture 1 */ + INTT32A01AC_IRQn = 89, /*!< T32A ch1 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A01ACCAP0_IRQn = 90, /*!< T32A ch1 Timer A/C Input capture 0 */ + INTT32A01ACCAP1_IRQn = 91, /*!< T32A ch1 Timer A/C Input capture 1 */ + INTT32A01B_IRQn = 92, /*!< T32A ch1 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A01BCAP0_IRQn = 93, /*!< T32A ch1 Timer B Input capture 0 */ + INTT32A01BCAP1_IRQn = 94, /*!< T32A ch1 Timer B Input capture 1 */ + INTT32A02AC_IRQn = 95, /*!< T32A ch2 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A02ACCAP0_IRQn = 96, /*!< T32A ch2 Timer A/C Input capture 0 */ + INTT32A02ACCAP1_IRQn = 97, /*!< T32A ch2 Timer A/C Input capture 1 */ + INTT32A02B_IRQn = 98, /*!< T32A ch2 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A02BCAP0_IRQn = 99, /*!< T32A ch2 Timer B Input capture 0 */ + INTT32A02BCAP1_IRQn = 100, /*!< T32A ch2 Timer B Input capture 1 */ + INTT32A03AC_IRQn = 101, /*!< T32A ch3 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A03ACCAP0_IRQn = 102, /*!< T32A ch3 Timer A/C Input capture 0 */ + INTT32A03ACCAP1_IRQn = 103, /*!< T32A ch3 Timer A/C Input capture 1 */ + INTT32A03B_IRQn = 104, /*!< T32A ch3 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A03BCAP0_IRQn = 105, /*!< T32A ch3 Timer B Input capture 0 */ + INTT32A03BCAP1_IRQn = 106, /*!< T32A ch3 Timer B Input capture 1 */ + INTT32A04AC_IRQn = 107, /*!< T32A ch4 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A04ACCAP0_IRQn = 108, /*!< T32A ch4 Timer A/C Input capture 0 */ + INTT32A04ACCAP1_IRQn = 109, /*!< T32A ch4 Timer A/C Input capture 1 */ + INTT32A04B_IRQn = 110, /*!< T32A ch4 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A04BCAP0_IRQn = 111, /*!< T32A ch4 Timer B Input capture 0 */ + INTT32A04BCAP1_IRQn = 112, /*!< T32A ch4 Timer B Input capture 1 */ + INTT32A05AC_IRQn = 113, /*!< T32A ch5 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A05ACCAP0_IRQn = 114, /*!< T32A ch5 Timer A/C Input capture 0 */ + INTT32A05ACCAP1_IRQn = 115, /*!< T32A ch5 Timer A/C Input capture 1 */ + INTT32A05B_IRQn = 116, /*!< T32A ch5 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A05BCAP0_IRQn = 117, /*!< T32A ch5 Timer B Input capture 0 */ + INTT32A05BCAP1_IRQn = 118, /*!< T32A ch5 Timer B Input capture 1 */ + INTPARI0_IRQn = 119, /*!< RAMP ch0 Parity error interrupt */ + INTPARI1_IRQn = 120, /*!< RAMP ch1 Parity error interrupt */ + INTDMAATC_IRQn = 121, /*!< DMAC unit A End of transfer (ch0 - 31) */ + INTDMAAERR_IRQn = 122, /*!< DMAC unit A Transfer error */ + INTFLCRDY_IRQn = 123, /*!< Code FLASH Ready interrupt */ + INTFLDRDY_IRQn = 124 /*!< Data FLASH Ready interrupt */ +} IRQn_Type; + +/** Processor and Core Peripheral Section */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_TMPM4KyA.h" /* TMPM4KNA System */ + +/** @addtogroup Device_Peripheral_registers + * @{ + */ + +/** Device Specific Peripheral registers structures */ + +/** + * @brief Interrupt control A Register (IA) + */ +typedef struct { + __IO uint8_t NIC00; /*!< Non Maskable Interrupt Control Register(A) 00*/ +} TSB_IA_TypeDef; + +/** + * @brief Reset Low power Management Register (RLM) + */ +typedef struct { + uint8_t RESERVED0[2]; + __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ + __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ +} TSB_RLM_TypeDef; + +/** + * @brief Voltage detection circuit (LVD) + */ +typedef struct { + __IO uint8_t CR; /*!< LVD Control register */ +} TSB_LVD_TypeDef; + +/** + * @brief RAM Parity (RAMP) + */ +typedef struct { + __IO uint32_t CTL; /*!< RAM Parity control register */ + __I uint32_t ST; /*!< RAM Parity status register */ + __O uint32_t CLR; /*!< RAM Parity status clear register */ + __I uint32_t EAD0; /*!< RAM Parity Error address register 0 */ + __I uint32_t EAD1; /*!< RAM Parity Error address register 1 */ +} TSB_RPAR_TypeDef; + +/** + * @brief CRC Calculation Circuit (CRC) + */ +typedef struct { + __IO uint32_t DIN; /*!< CRC input data register */ + uint32_t RESERVED0[4]; + __IO uint32_t TYP; /*!< CRC data type register */ + uint32_t RESERVED1[5]; + __IO uint32_t CLC; /*!< CRC calculation result register */ +} TSB_CRC_TypeDef; + +/** + * @brief Clock Control and Operation Mode (CG) + */ +typedef struct { + __IO uint32_t PROTECT; /*!< Protect Register */ + __IO uint32_t OSCCR; /*!< Oscillation Control Register */ + __IO uint32_t SYSCR; /*!< System Clock Control Register */ + __IO uint32_t STBYCR; /*!< Standby Control Register */ + uint32_t RESERVED0[4]; + __IO uint32_t PLL0SEL; /*!< PLL Selection Register 0 */ + uint32_t RESERVED1[3]; + __IO uint32_t WUPHCR; /*!< High speed OSC Warming-up Register */ + uint32_t RESERVED2[5]; + __IO uint32_t FSYSMENA; /*!< Middle fsys Supply Stop Register A */ + __IO uint32_t FSYSMENB; /*!< Middle fsys Supply Stop Register B */ + __IO uint32_t FSYSENA; /*!< High fsys Supply Stop Register A */ + uint32_t RESERVED3; + __IO uint32_t FCEN; /*!< FC Supply Stop Register */ + __IO uint32_t SPCLKEN; /*!< ADC/TRACE Clock Supply Stop Register */ +} TSB_CG_TypeDef; + +/** + * @brief Interrupt Control B Register (IB) + */ +typedef struct { + uint8_t RESERVED0[16]; + __IO uint8_t NIC00; /*!< Non maskable Interrupt Control Register(B) 00*/ + uint8_t RESERVED1[79]; + __IO uint8_t IMC000; /*!< Interrupt Mode Control Register(B) 000 */ + __IO uint8_t IMC001; /*!< Interrupt Mode Control Register(B) 001 */ + __IO uint8_t IMC002; /*!< Interrupt Mode Control Register(B) 002 */ + __IO uint8_t IMC003; /*!< Interrupt Mode Control Register(B) 003 */ + __IO uint8_t IMC004; /*!< Interrupt Mode Control Register(B) 004 */ + __IO uint8_t IMC005; /*!< Interrupt Mode Control Register(B) 005 */ + __IO uint8_t IMC006; /*!< Interrupt Mode Control Register(B) 006 */ + __IO uint8_t IMC007; /*!< Interrupt Mode Control Register(B) 007 */ + __IO uint8_t IMC008; /*!< Interrupt Mode Control Register(B) 008 */ + __IO uint8_t IMC009; /*!< Interrupt Mode Control Register(B) 009 */ + __IO uint8_t IMC010; /*!< Interrupt Mode Control Register(B) 010 */ + __IO uint8_t IMC011; /*!< Interrupt Mode Control Register(B) 011 */ + __IO uint8_t IMC012; /*!< Interrupt Mode Control Register(B) 012 */ + __IO uint8_t IMC013; /*!< Interrupt Mode Control Register(B) 013 */ + __IO uint8_t IMC014; /*!< Interrupt Mode Control Register(B) 014 */ + __IO uint8_t IMC015; /*!< Interrupt Mode Control Register(B) 015 */ + __IO uint8_t IMC016; /*!< Interrupt Mode Control Register(B) 016 */ + __IO uint8_t IMC017; /*!< Interrupt Mode Control Register(B) 017 */ + __IO uint8_t IMC018; /*!< Interrupt Mode Control Register(B) 018 */ + __IO uint8_t IMC019; /*!< Interrupt Mode Control Register(B) 019 */ + __IO uint8_t IMC020; /*!< Interrupt Mode Control Register(B) 020 */ + __IO uint8_t IMC021; /*!< Interrupt Mode Control Register(B) 021 */ + __IO uint8_t IMC022; /*!< Interrupt Mode Control Register(B) 022 */ + __IO uint8_t IMC023; /*!< Interrupt Mode Control Register(B) 023 */ + __IO uint8_t IMC024; /*!< Interrupt Mode Control Register(B) 024 */ + __IO uint8_t IMC025; /*!< Interrupt Mode Control Register(B) 025 */ + __IO uint8_t IMC026; /*!< Interrupt Mode Control Register(B) 026 */ + __IO uint8_t IMC027; /*!< Interrupt Mode Control Register(B) 027 */ + __IO uint8_t IMC028; /*!< Interrupt Mode Control Register(B) 028 */ + __IO uint8_t IMC029; /*!< Interrupt Mode Control Register(B) 029 */ + __IO uint8_t IMC030; /*!< Interrupt Mode Control Register(B) 030 */ + __IO uint8_t IMC031; /*!< Interrupt Mode Control Register(B) 031 */ + __IO uint8_t IMC032; /*!< Interrupt Mode Control Register(B) 032 */ + __IO uint8_t IMC033; /*!< Interrupt Mode Control Register(B) 033 */ + __IO uint8_t IMC034; /*!< Interrupt Mode Control Register(B) 034 */ + __IO uint8_t IMC035; /*!< Interrupt Mode Control Register(B) 035 */ + __IO uint8_t IMC036; /*!< Interrupt Mode Control Register(B) 036 */ + __IO uint8_t IMC037; /*!< Interrupt Mode Control Register(B) 037 */ + __IO uint8_t IMC038; /*!< Interrupt Mode Control Register(B) 038 */ + __IO uint8_t IMC039; /*!< Interrupt Mode Control Register(B) 039 */ + __IO uint8_t IMC040; /*!< Interrupt Mode Control Register(B) 040 */ + __IO uint8_t IMC041; /*!< Interrupt Mode Control Register(B) 041 */ + __IO uint8_t IMC042; /*!< Interrupt Mode Control Register(B) 042 */ + __IO uint8_t IMC043; /*!< Interrupt Mode Control Register(B) 043 */ + __IO uint8_t IMC044; /*!< Interrupt Mode Control Register(B) 044 */ + __IO uint8_t IMC045; /*!< Interrupt Mode Control Register(B) 045 */ + __IO uint8_t IMC046; /*!< Interrupt Mode Control Register(B) 046 */ + __IO uint8_t IMC047; /*!< Interrupt Mode Control Register(B) 047 */ + __IO uint8_t IMC048; /*!< Interrupt Mode Control Register(B) 048 */ + __IO uint8_t IMC049; /*!< Interrupt Mode Control Register(B) 049 */ + __IO uint8_t IMC050; /*!< Interrupt Mode Control Register(B) 050 */ + __IO uint8_t IMC051; /*!< Interrupt Mode Control Register(B) 051 */ + __IO uint8_t IMC052; /*!< Interrupt Mode Control Register(B) 052 */ + __IO uint8_t IMC053; /*!< Interrupt Mode Control Register(B) 053 */ + __IO uint8_t IMC054; /*!< Interrupt Mode Control Register(B) 054 */ + __IO uint8_t IMC055; /*!< Interrupt Mode Control Register(B) 055 */ + __IO uint8_t IMC056; /*!< Interrupt Mode Control Register(B) 056 */ + __IO uint8_t IMC057; /*!< Interrupt Mode Control Register(B) 057 */ + __IO uint8_t IMC058; /*!< Interrupt Mode Control Register(B) 058 */ + __IO uint8_t IMC059; /*!< Interrupt Mode Control Register(B) 059 */ + __IO uint8_t IMC060; /*!< Interrupt Mode Control Register(B) 060 */ + __IO uint8_t IMC061; /*!< Interrupt Mode Control Register(B) 061 */ + __IO uint8_t IMC062; /*!< Interrupt Mode Control Register(B) 062 */ + __IO uint8_t IMC063; /*!< Interrupt Mode Control Register(B) 063 */ + __IO uint8_t IMC064; /*!< Interrupt Mode Control Register(B) 064 */ + uint8_t RESERVED2[4]; + __IO uint8_t IMC069; /*!< Interrupt Mode Control Register(B) 069 */ +} TSB_IB_TypeDef; + +/** + * @brief Interrupt Monitor Register (IMN) + */ +typedef struct { + __I uint32_t FLGNMI; /*!< NMI Interrupt Monitor Flag */ + uint32_t RESERVED0[2]; + __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 (096 - 127) */ + __I uint32_t FLG4; /*!< Interrupt Monitor Flag 4 (128 - 159) */ + __I uint32_t FLG5; /*!< Interrupt Monitor Flag 5 (160 - 191) */ +} TSB_IMN_TypeDef; + +/** + * @brief Digital Noise Filter (DNF) + */ +typedef struct { + __IO uint32_t CKCR; /*!< DNF clock Control register */ + __IO uint32_t ENCR; /*!< DNF Enable register */ +} TSB_DNF_TypeDef; + +/** + * @brief Trigger Selection circuit (TSEL) + */ +typedef struct { + __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ + __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ + __IO uint32_t CR2; /*!< TRGSEL Control register 2 */ + __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ + __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ + __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ + __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ + __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ + __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ + __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ + __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ +} TSB_TSEL_TypeDef; + +/** + * @brief Watchdog Timer (SIWD) + */ +typedef struct { + __IO uint32_t PRO; /*!< SIWD Protect Register */ + __IO uint32_t EN; /*!< SIWD Enable Register */ + __O uint32_t CR; /*!< SIWD Control Register */ + __IO uint32_t MOD; /*!< SIWD Mode Register */ + __I uint32_t MONI; /*!< SIWD Count Monitor Register */ + __IO uint32_t OSCCR; /*!< SIWD Oscillator Control Register */ +} TSB_SIWD_TypeDef; + +/** + * @brief Non-Break Debug Interface (NBD) + */ +typedef struct { + __IO uint32_t CR0; /*!< NBD control register 0 */ + __IO uint32_t CR1; /*!< NBD control register 1 */ +} TSB_NBD_TypeDef; + +/** + * @brief Direct Memory Access Controller (DMAC) + */ +typedef struct { + __I uint32_t STATUS; /*!< DMA Status Register */ + __O uint32_t CFG; /*!< DMA Configuration Register */ + __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */ + __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base +Pointer Register*/ + uint32_t RESERVED0; + __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */ + __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */ + __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */ + __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */ + __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */ + __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */ + __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */ + __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */ + __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */ + __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */ + __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */ + uint32_t RESERVED1[3]; + __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */ +} TSB_DMA_TypeDef; + +/** + * @brief 12-bit Analog to Digital Converter(ADC) + */ +typedef struct { + __IO uint32_t CR0; /*!< AD Control Register 0 */ + __IO uint32_t CR1; /*!< AD Control Register 1 */ + __I uint32_t ST; /*!< AD Status Register */ + __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ + __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ + __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ + __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ + uint32_t RESERVED0; + __IO uint32_t CMPEN; /*!< AD Monitor function interrupt permission register*/ + __IO uint32_t CMPCR0; /*!< AD Monitor function Setting Register 0 */ + __IO uint32_t CMPCR1; /*!< AD Monitor function Setting Register 1 */ + __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ + __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ + uint32_t RESERVED1[3]; + __IO uint32_t PSEL0; /*!< AD PMD Trigger Program Number Select Register 0*/ + __IO uint32_t PSEL1; /*!< AD PMD Trigger Program Number Select Register 1*/ + __IO uint32_t PSEL2; /*!< AD PMD Trigger Program Number Select Register 2*/ + __IO uint32_t PSEL3; /*!< AD PMD Trigger Program Number Select Register 3*/ + __IO uint32_t PSEL4; /*!< AD PMD Trigger Program Number Select Register 4*/ + __IO uint32_t PSEL5; /*!< AD PMD Trigger Program Number Select Register 5*/ + __IO uint32_t PSEL6; /*!< AD PMD Trigger Program Number Select Register 6*/ + __IO uint32_t PSEL7; /*!< AD PMD Trigger Program Number Select Register 7*/ + __IO uint32_t PSEL8; /*!< AD PMD Trigger Program Number Select Register 8*/ + __IO uint32_t PSEL9; /*!< AD PMD Trigger Program Number Select Register 9*/ + __IO uint32_t PSEL10; /*!< AD PMD Trigger Program Number Select Register 10*/ + __IO uint32_t PSEL11; /*!< AD PMD Trigger Program Number Select Register 11*/ + __IO uint32_t PINTS0; /*!< AD PMD Trigger Interrupt Select Register 0 */ + __IO uint32_t PINTS1; /*!< AD PMD Trigger Interrupt Select Register 1 */ + __IO uint32_t PINTS2; /*!< AD PMD Trigger Interrupt Select Register 2 */ + __IO uint32_t PINTS3; /*!< AD PMD Trigger Interrupt Select Register 3 */ + __IO uint32_t PINTS4; /*!< AD PMD Trigger Interrupt Select Register 4 */ + __IO uint32_t PINTS5; /*!< AD PMD Trigger Interrupt Select Register 5 */ + __IO uint32_t PINTS6; /*!< AD PMD Trigger Interrupt Select Register 6 */ + __IO uint32_t PINTS7; /*!< AD PMD Trigger Interrupt Select Register 7 */ + __IO uint32_t PREGS; /*!< AD PMD Trigger Conversion Result Storage Select Register 1*/ + uint32_t RESERVED2[2]; + __IO uint32_t EXAZSEL; /*!< AD Sampling Time Select Register */ + __IO uint32_t PSET0; /*!< AD PMD Trigger Program Register 0 */ + __IO uint32_t PSET1; /*!< AD PMD Trigger Program Register 1 */ + __IO uint32_t PSET2; /*!< AD PMD Trigger Program Register 2 */ + __IO uint32_t PSET3; /*!< AD PMD Trigger Program Register 3 */ + __IO uint32_t PSET4; /*!< AD PMD Trigger Program Register 4 */ + __IO uint32_t PSET5; /*!< AD PMD Trigger Program Register 5 */ + __IO uint32_t PSET6; /*!< AD PMD Trigger Program Register 6 */ + __IO uint32_t PSET7; /*!< AD PMD Trigger Program Register 7 */ + __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/ + __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/ + __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/ + __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/ + __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/ + __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/ + __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/ + __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/ + __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/ + __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/ + __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/ + __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/ + __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/ + __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/ + __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/ + __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/ + __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/ + __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/ + __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/ + __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/ + __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/ + __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/ + __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/ + __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/ + uint32_t RESERVED3[8]; + __I uint32_t REG0; /*!< AD Conversion Result Register 0 */ + __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ + __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ + __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ + __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ + __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ + __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ + __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ + __I uint32_t REG8; /*!< AD Conversion Result Register 8 */ + __I uint32_t REG9; /*!< AD Conversion Result Register 9 */ + __I uint32_t REG10; /*!< AD Conversion Result Register 10 */ + __I uint32_t REG11; /*!< AD Conversion Result Register 11 */ + __I uint32_t REG12; /*!< AD Conversion Result Register 12 */ + __I uint32_t REG13; /*!< AD Conversion Result Register 13 */ + __I uint32_t REG14; /*!< AD Conversion Result Register 14 */ + __I uint32_t REG15; /*!< AD Conversion Result Register 15 */ + __I uint32_t REG16; /*!< AD Conversion Result Register 16 */ + __I uint32_t REG17; /*!< AD Conversion Result Register 17 */ + __I uint32_t REG18; /*!< AD Conversion Result Register 18 */ + __I uint32_t REG19; /*!< AD Conversion Result Register 19 */ + __I uint32_t REG20; /*!< AD Conversion Result Register 20 */ + __I uint32_t REG21; /*!< AD Conversion Result Register 21 */ + __I uint32_t REG22; /*!< AD Conversion Result Register 22 */ + __I uint32_t REG23; /*!< AD Conversion Result Register 23 */ +} TSB_AD_TypeDef; + +/** + * @brief Gain Op-AMP (AMP) + */ +typedef struct { + __IO uint32_t CTLA; /*!< AMP control register A */ + __IO uint32_t CTLB; /*!< AMP control register B */ + __IO uint32_t CTLC; /*!< AMP control register C */ +} TSB_AMP_TypeDef; + +/** + * @brief 32-bit Timer Event Counter (T32A) + */ +typedef struct { + __IO uint32_t MOD; /*!< T32A Mode Register */ + uint32_t RESERVED0[15]; + __IO uint32_t RUNA; /*!< T32A Run Register A */ + __IO uint32_t CRA; /*!< T32A Control Register A */ + __IO uint32_t CAPCRA; /*!< T32A Capture Control Register A */ + __O uint32_t OUTCRA0; /*!< T32A Output Control Register A0 */ + __IO uint32_t OUTCRA1; /*!< T32A Output Control Register A1 */ + __IO uint32_t STA; /*!< T32A Status Register A */ + __IO uint32_t IMA; /*!< T32A Interrupt Mask Register A */ + __I uint32_t TMRA; /*!< T32A Counter Capture Register A */ + __IO uint32_t RELDA; /*!< T32A Reload Register A */ + __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ + __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ + __I uint32_t CAPA0; /*!< T32A Capture Register A0 */ + __I uint32_t CAPA1; /*!< T32A Capture Register A1 */ + __IO uint32_t DMAA; /*!< T32A DMA Request Enable Register A */ + __I uint32_t CPA0; /*!< T32A Compare Register A0 */ + __I uint32_t CPA1; /*!< T32A Compare Register A1 */ + __IO uint32_t RUNB; /*!< T32A Run Register B */ + __IO uint32_t CRB; /*!< T32A Control Register B */ + __IO uint32_t CAPCRB; /*!< T32A Capture Control Register B */ + __O uint32_t OUTCRB0; /*!< T32A Output Control Register B0 */ + __IO uint32_t OUTCRB1; /*!< T32A Output Control Register B1 */ + __IO uint32_t STB; /*!< T32A Status Register B */ + __IO uint32_t IMB; /*!< T32A Interrupt Mask Register B */ + __I uint32_t TMRB; /*!< T32A Counter Capture Register B */ + __IO uint32_t RELDB; /*!< T32A Reload Register B */ + __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ + __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ + __I uint32_t CAPB0; /*!< T32A Capture Register B0 */ + __I uint32_t CAPB1; /*!< T32A Capture Register B1 */ + __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ + __I uint32_t CPB0; /*!< T32A Compare Register B0 */ + __I uint32_t CPB1; /*!< T32A Compare Register B1 */ + __IO uint32_t RUNC; /*!< T32A Run Register C */ + __IO uint32_t CRC; /*!< T32A Control Register C */ + __IO uint32_t CAPCRC; /*!< T32A Capture Control Register C */ + __O uint32_t OUTCRC0; /*!< T32A Output Control Register C0 */ + __IO uint32_t OUTCRC1; /*!< T32A Output Control Register C1 */ + __IO uint32_t STC; /*!< T32A Status Register C */ + __IO uint32_t IMC; /*!< T32A Interrupt Mask Register C */ + __I uint32_t TMRC; /*!< T32A Counter Capture Register C */ + __IO uint32_t RELDC; /*!< T32A Reload Register C */ + __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ + __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ + __I uint32_t CAPC0; /*!< T32A Capture Register C0 */ + __I uint32_t CAPC1; /*!< T32A Capture Register C1 */ + __IO uint32_t DMAC; /*!< T32A DMA Request Enable Register C */ + __IO uint32_t PLSCR; /*!< T32A Pulse Count Control Register */ + __I uint32_t CPC0; /*!< T32A Compare Register C0 */ + __I uint32_t CPC1; /*!< T32A Compare Register C1 */ +} TSB_T32A_TypeDef; + +/** + * @brief Serial Peripheral Interface (TSPI) + */ +typedef struct { + __IO uint32_t CR0; /*!< TSPI Control Register 0 */ + __IO uint32_t CR1; /*!< TSPI Control Register 1 */ + __IO uint32_t CR2; /*!< TSPI Control Register 2 */ + __IO uint32_t CR3; /*!< TSPI Control Register 3 */ + __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ + __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ + __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ + __IO uint32_t SECTCR0; /*!< TSPI Sector Mode Control Register 0 */ + __IO uint32_t SECTCR1; /*!< TSPI Sector Mode Control Register 1 */ + uint32_t RESERVED0[55]; + __IO uint32_t DR; /*!< TSPI Data Register */ + uint32_t RESERVED1[63]; + __IO uint32_t SR; /*!< TSPI Status Register */ + __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ +} TSB_TSPI_TypeDef; + +/** + * @brief Asynchronous Serial Communication Circuit (UART) + */ +typedef struct { + __IO uint32_t SWRST; /*!< UART Software Reset Register */ + __IO uint32_t CR0; /*!< UART Control Register 0 */ + __IO uint32_t CR1; /*!< UART Control Register 1 */ + __IO uint32_t CLK; /*!< UART Clock Control Register */ + __IO uint32_t BRD; /*!< UART Baud Rate Register */ + __IO uint32_t TRANS; /*!< UART Transfer Enable Register */ + __IO uint32_t DR; /*!< UART Data Register */ + __IO uint32_t SR; /*!< UART Status Register */ + __O uint32_t FIFOCLR; /*!< UART FIFO Clear Register */ + __IO uint32_t ERR; /*!< UART Error Register */ +} TSB_UART_TypeDef; + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#pragma anon_unions +#elif (defined (__ICCARM__)) /* ICC Compiler */ +#pragma language=extended +#endif + +/** + * @brief I2C Interface (I2C) + */ +typedef struct { + __IO uint32_t CR1; /*!< I2C Control Register 1 */ + __IO uint32_t DBR; /*!< Data Buffer Register */ + __IO uint32_t AR; /*!< Bus address Register */ + union { + __O uint32_t CR2; /*!< Control Register 2 */ + __I uint32_t SR; /*!< Status Register */ + }; + __IO uint32_t PRS; /*!< Prescaler clock setting Register */ + __IO uint32_t IE; /*!< Interrupt Enable Register */ + __IO uint32_t ST; /*!< Interrupt Register */ + __IO uint32_t OP; /*!< Optional Function register */ + __I uint32_t PM; /*!< Bus Monitor register */ + __IO uint32_t AR2; /*!< Second Slave address register */ +} TSB_I2C_TypeDef; + +/** + * @brief I2C Interface Version A (EI2C) + */ +typedef struct { + __IO uint32_t ARST; /*!< EI2C Reset Register */ + __IO uint32_t AEN; /*!< EI2C Enable Register */ + __IO uint32_t ACR0; /*!< EI2C Control Register 0 */ + __IO uint32_t ACR1; /*!< EI2C Control Register 1 */ + __IO uint32_t ADBRT; /*!< EI2C Transmit Data Buffer Register */ + __I uint32_t ADBRR; /*!< EI2C Receive Data Buffer Register */ + __I uint32_t ASR0; /*!< EI2C Status Register 0 */ + __IO uint32_t ASR1; /*!< EI2C Status Register 1 */ + __IO uint32_t APRS; /*!< EI2C Prescaler Clock Setting Register */ + __IO uint32_t ASCL; /*!< EI2C SCL Width Setting Register */ + __IO uint32_t AAR1; /*!< EI2C First Slave Address Register */ + __IO uint32_t AAR2; /*!< EI2C Second Slave Address Register */ + __IO uint32_t AIE; /*!< EI2C Interrupt/DMA Setting Register */ + __I uint32_t APM; /*!< EI2C Bus Terminal Monitor Register */ +} TSB_EI2C_TypeDef; + +/** + * @brief Port A + */ +typedef struct { + __IO uint32_t DATA; /*!< Port A Data Register */ + __IO uint32_t CR; /*!< Port A Output Control Register */ + __IO uint32_t FR1; /*!< Port A Function Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR4; /*!< Port A Function Register 4 */ + __IO uint32_t FR5; /*!< Port A Function Register 5 */ + __IO uint32_t FR6; /*!< Port A Function Register 6 */ + __IO uint32_t FR7; /*!< Port A Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port A Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port A Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port A Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port A Input Control Register */ +} TSB_PA_TypeDef; + +/** + * @brief Port B + */ +typedef struct { + __IO uint32_t DATA; /*!< Port B Data Register */ + __IO uint32_t CR; /*!< Port B Output Control Register */ + uint32_t RESERVED0[3]; + __IO uint32_t FR4; /*!< Port B Function Register 4 */ + __IO uint32_t FR5; /*!< Port B Function Register 5 */ + uint32_t RESERVED1[3]; + __IO uint32_t OD; /*!< Port B Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port B Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port B Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port B Input Control Register */ +} TSB_PB_TypeDef; + +/** + * @brief Port C + */ +typedef struct { + __IO uint32_t DATA; /*!< Port C Data Register */ + __IO uint32_t CR; /*!< Port C Output Control Register */ + __IO uint32_t FR1; /*!< Port C Function Register 1 */ + __IO uint32_t FR2; /*!< Port C Function Register 2 */ + __IO uint32_t FR3; /*!< Port C Function Register 3 */ + __IO uint32_t FR4; /*!< Port C Function Register 4 */ + __IO uint32_t FR5; /*!< Port C Function Register 5 */ + __IO uint32_t FR6; /*!< Port C Function Register 6 */ + __IO uint32_t FR7; /*!< Port C Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port C Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port C Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port C Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port C Input Control Register */ +} TSB_PC_TypeDef; + +/** + * @brief Port D + */ +typedef struct { + __IO uint32_t DATA; /*!< Port D Data Register */ + __IO uint32_t CR; /*!< Port D Output Control Register */ + __IO uint32_t FR1; /*!< Port D Function Register 1 */ + __IO uint32_t FR2; /*!< Port D Function Register 2 */ + __IO uint32_t FR3; /*!< Port D Function Register 3 */ + __IO uint32_t FR4; /*!< Port D Function Register 4 */ + __IO uint32_t FR5; /*!< Port D Function Register 5 */ + __IO uint32_t FR6; /*!< Port D Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< Port D Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port D Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port D Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port D Input Control Register */ +} TSB_PD_TypeDef; + +/** + * @brief Port E + */ +typedef struct { + __IO uint32_t DATA; /*!< Port E Data Register */ + __IO uint32_t CR; /*!< Port E Output Control Register */ + uint32_t RESERVED0[3]; + __IO uint32_t FR4; /*!< Port E Function Register 4 */ + __IO uint32_t FR5; /*!< Port E Function Register 5 */ + __IO uint32_t FR6; /*!< Port E Function Register 6 */ + __IO uint32_t FR7; /*!< Port E Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port E Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port E Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port E Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port E Input Control Register */ +} TSB_PE_TypeDef; + +/** + * @brief Port F + */ +typedef struct { + __IO uint32_t DATA; /*!< Port F Data Register */ + __IO uint32_t CR; /*!< Port F Output Control Register */ + __IO uint32_t FR1; /*!< Port F Function Register 1 */ + __IO uint32_t FR2; /*!< Port F Function Register 2 */ + __IO uint32_t FR3; /*!< Port F Function Register 3 */ + __IO uint32_t FR4; /*!< Port F Function Register 4 */ + __IO uint32_t FR5; /*!< Port F Function Register 5 */ + __IO uint32_t FR6; /*!< Port F Function Register 6 */ + __IO uint32_t FR7; /*!< Port F Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port F Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port F Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port F Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port F Input Control Register */ +} TSB_PF_TypeDef; + +/** + * @brief Port G + */ +typedef struct { + __IO uint32_t DATA; /*!< Port G Data Register */ + __IO uint32_t CR; /*!< Port G Output Control Register */ + __IO uint32_t FR1; /*!< Port G Function Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR4; /*!< Port G Function Register 4 */ + __IO uint32_t FR5; /*!< Port G Function Register 5 */ + uint32_t RESERVED1[3]; + __IO uint32_t OD; /*!< Port G Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port G Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port G Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port G Input Control Register */ +} TSB_PG_TypeDef; + +/** + * @brief Port H + */ +typedef struct { + __IO uint32_t DATA; /*!< Port H Data Register */ + uint32_t RESERVED0[11]; + __IO uint32_t PDN; /*!< Port H Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port H Input Control Register */ +} TSB_PH_TypeDef; + +/** + * @brief Port J + */ +typedef struct { + __IO uint32_t DATA; /*!< Port J Data Register */ + __IO uint32_t CR; /*!< Port J Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port J Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port J Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port J Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port J Input Control Register */ +} TSB_PJ_TypeDef; + +/** + * @brief Port K + */ +typedef struct { + __IO uint32_t DATA; /*!< Port K Data Register */ + __IO uint32_t CR; /*!< Port K Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port K Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port K Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port K Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port K Input Control Register */ +} TSB_PK_TypeDef; + +/** + * @brief Port L + */ +typedef struct { + __IO uint32_t DATA; /*!< Port L Data Register */ + __IO uint32_t CR; /*!< Port L Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port L Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port L Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port L Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port L Input Control Register */ +} TSB_PL_TypeDef; + +/** + * @brief Port M + */ +typedef struct { + __IO uint32_t DATA; /*!< Port M Data Register */ + __IO uint32_t CR; /*!< Port M Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port M Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port M Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port M Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port M Input Control Register */ +} TSB_PM_TypeDef; + +/** + * @brief Port N + */ +typedef struct { + __IO uint32_t DATA; /*!< Port N Data Register */ + __IO uint32_t CR; /*!< Port N Output Control Register */ + __IO uint32_t FR1; /*!< Port N Function Register 1 */ + __IO uint32_t FR2; /*!< Port N Function Register 2 */ + __IO uint32_t FR3; /*!< Port N Function Register 3 */ + __IO uint32_t FR4; /*!< Port N Function Register 4 */ + __IO uint32_t FR5; /*!< Port N Function Register 5 */ + __IO uint32_t FR6; /*!< Port N Function Register 6 */ + __IO uint32_t FR7; /*!< Port N Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port N Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port N Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port N Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port N Input Control Register */ +} TSB_PN_TypeDef; + +/** + * @brief Port U + */ +typedef struct { + __IO uint32_t DATA; /*!< Port U Data Register */ + __IO uint32_t CR; /*!< Port U Output Control Register */ + __IO uint32_t FR1; /*!< Port U Function Register 1 */ + __IO uint32_t FR2; /*!< Port U Function Register 2 */ + __IO uint32_t FR3; /*!< Port U Function Register 3 */ + __IO uint32_t FR4; /*!< Port U Function Register 4 */ + __IO uint32_t FR5; /*!< Port U Function Register 5 */ + __IO uint32_t FR6; /*!< Port U Function Register 6 */ + __IO uint32_t FR7; /*!< Port U Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port U Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port U Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port U Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port U Input Control Register */ +} TSB_PU_TypeDef; + +/** + * @brief Port V + */ +typedef struct { + __IO uint32_t DATA; /*!< Port V Data Register */ + __IO uint32_t CR; /*!< Port V Output Control Register */ + __IO uint32_t FR1; /*!< Port V Function Register 1 */ + __IO uint32_t FR2; /*!< Port V Function Register 2 */ + uint32_t RESERVED0; + __IO uint32_t FR4; /*!< Port V Function Register 4 */ + uint32_t RESERVED1[4]; + __IO uint32_t OD; /*!< Port V Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port V Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port V Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port V Input Control Register */ +} TSB_PV_TypeDef; + +/** + * @brief Trimming Circuit (TRM) + */ +typedef struct { + __IO uint32_t OSCPRO; /*!< Protection Register */ + __IO uint32_t OSCEN; /*!< TRM Enable Register */ + uint32_t RESERVED0[2]; + __I uint32_t OSCINIT0; /*!< TRM Initial Trimming Value Monitor Register0 */ + __I uint32_t OSCINIT1; /*!< TRM Initial Trimming Value Monitor Register1 */ + __I uint32_t OSCINIT2; /*!< TRM Initial Trimming Value Monitor Register2 */ + uint32_t RESERVED1; + __IO uint32_t OSCSET0; /*!< TRM User Trimming Value Setting Register0 */ + __IO uint32_t OSCSET1; /*!< TRM User Trimming Value Setting Register1 */ + __IO uint32_t OSCSET2; /*!< TRM User Trimming Value Setting Register2 */ +} TSB_TRM_TypeDef; + +/** + * @brief Oscillation Frequency Detector (OFD) + */ +typedef struct { + __IO uint32_t CR1; /*!< OFD Control Register 1 */ + __IO uint32_t CR2; /*!< OFD Control Register 2 */ + __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/ + __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/ + __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/ + __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/ + __IO uint32_t RST; /*!< OFD Reset Enable Control Register */ + __I uint32_t STAT; /*!< OFD Status Register */ + __IO uint32_t MON; /*!< OFD External high frequency oscillation clock monitor register */ +} TSB_OFD_TypeDef; + +/** + * @brief Advanced Programmable Motor Control Circuit (A-PMD) + */ +typedef struct { + __IO uint32_t MDEN; /*!< PMD Enable Register */ + __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ + __IO uint32_t MDCR; /*!< PMD Control Register */ + __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ + __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ + __IO uint32_t RATE; /*!< PWM Frequency Register */ + __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */ + __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */ + __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */ + __IO uint32_t MODESEL; /*!< PMD Mode Select Register */ + __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ + __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ + __O uint32_t EMGREL; /*!< PMD EMG Release Register */ + __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ + __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ + __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ + __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ + __IO uint32_t DTR; /*!< PMD Dead Time Register */ + __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */ + __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */ + __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */ + __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */ + __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ + __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ + __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ + __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ + __IO uint32_t VPWMPH; /*!< PMD Phase difference setting of the V-phase PWM*/ + __IO uint32_t WPWMPH; /*!< PMD Phase difference setting of the W-phase PWM*/ + __IO uint32_t MBUFCR; /*!< PMD Update timing of the triple buffer */ + __IO uint32_t SYNCCR; /*!< PMD Synchronization control between the PMD channel*/ + __IO uint32_t DBGOUTCR; /*!< PMD Debug output control */ +} TSB_PMD_TypeDef; + +/** + * @brief Advanced Encoder Input (A-ENC32) + */ +typedef struct { + __IO uint32_t TNCR; /*!< ENC Control Register */ + __IO uint32_t RELOAD; /*!< ENC Reload Compare Register */ + __IO uint32_t INT; /*!< ENC INT Compare Register */ + __I uint32_t CNT; /*!< ENC Counter/Capture Register */ + __IO uint32_t MCMP; /*!< ENC MCMP Compare Register */ + __IO uint32_t RATE; /*!< ENC Phase Count Rate Register */ + __I uint32_t STS; /*!< ENC Status Register */ + __IO uint32_t INPCR; /*!< ENC Input Process Control Register */ + __IO uint32_t SMPDLY; /*!< ENC Sample Delay Register */ + __I uint32_t INPMON; /*!< ENC Input Monitor Register */ + __IO uint32_t CLKCR; /*!< ENC Sample Clock Control Register */ + __IO uint32_t INTCR; /*!< ENC Interrupt Control Register */ + __I uint32_t INTF; /*!< ENC Interrupt Event Flag Register */ +} TSB_EN_TypeDef; + +/** + * @brief Advanced Vector Engine Plus (A-VE+) + */ +typedef struct { + __IO uint32_t EN; /*!< VE enable/disable */ + __O uint32_t CPURUNTRG; /*!< CPU start trigger selection */ + __IO uint32_t TASKAPP; /*!< Task selection */ + __IO uint32_t ACTSCH; /*!< Operation schedule selection */ + __IO uint32_t REPTIME; /*!< Schedule repeat count */ + __IO uint32_t TRGMODE; /*!< Start trigger mode */ + __IO uint32_t ERRINTEN; /*!< Error interrupt enable/disable */ + __O uint32_t COMPEND; /*!< VE forced termination */ + __I uint32_t ERRDET; /*!< Error detection */ + __I uint32_t SCHTASKRUN; /*!< Schedule executing flag/executing task */ + uint32_t RESERVED0; + __IO uint32_t TMPREG0; /*!< Temporary register */ + __IO uint32_t TMPREG1; /*!< Temporary register */ + __IO uint32_t TMPREG2; /*!< Temporary register */ + __IO uint32_t TMPREG3; /*!< Temporary register */ + __IO uint32_t TMPREG4; /*!< Temporary register */ + __IO uint32_t TMPREG5; /*!< Temporary register */ + __IO uint32_t MCTLF; /*!< Status flags */ + __IO uint32_t MODE; /*!< Task control mode */ + __IO uint32_t FMODE; /*!< Flow control */ + __IO uint32_t TPWM; /*!< PWM period rate (PWM period [s] * maximum speed * 2^16) setting*/ + __IO uint32_t OMEGA; /*!< Rotation speed (speed [Hz] / maximum speed * 2^15) setting*/ + __IO uint32_t THETA; /*!< Motor phase (motor phase [deg] / 360 * 2^16) setting*/ + __IO uint32_t IDREF; /*!< d-axis reference value (current [A] / maximum current * 2^15)*/ + __IO uint32_t IQREF; /*!< q-axis reference value (current [A] / maximum current * 2^15)*/ + __IO uint32_t VD; /*!< d-axis voltage (voltage [V] / maximum voltage * 2^31)*/ + __IO uint32_t VQ; /*!< q-axis voltage (voltage [V] / maximum voltage * 2^31)*/ + __IO uint32_t CIDKI; /*!< Integral coefficient for PI control of d-axis*/ + __IO uint32_t CIDKP; /*!< Proportional coefficient for PI control of d-axis*/ + __IO uint32_t CIQKI; /*!< Integral coefficient for PI control of q-axis*/ + __IO uint32_t CIQKP; /*!< Proportional coefficient for PI control of q-axis*/ + __IO uint32_t VDIH; /*!< Upper 32 bits of integral term (VDI ) of d-axis voltage*/ + __IO uint32_t VDILH; /*!< Lower 32 bits of integral term (VDI) of d-axis voltage*/ + __IO uint32_t VQIH; /*!< Upper 32 bits of integral term (VQI) of q-axis voltage*/ + __IO uint32_t VQILH; /*!< Lower 32 bits of integral term (VQI) of q-axis voltage*/ + __IO uint32_t FPWMCHG; /*!< Switching speed (for 2-phase modulation and shift PWM)*/ + __IO uint32_t PWMOFS; /*!< SHIFT2 PWM Offset register */ + __IO uint32_t MINPLS; /*!< Minimum pulse width */ + __IO uint32_t TRGCRC; /*!< Synchronizing trigger correction value */ + __IO uint32_t VDCL; /*!< Cosine value at THETA for output conversion (Q15 data)*/ + __IO uint32_t COS; /*!< Cosine value at THETA for output conversion (Q15 data)*/ + __IO uint32_t SIN; /*!< Sine value at THETA for output conversion (Q15 data)*/ + __IO uint32_t COSM; /*!< Previous cosine value for input processing (Q15 data)*/ + __IO uint32_t SINM; /*!< Previous sine value for input processing (Q15 data)*/ + __IO uint32_t SECTOR; /*!< Sector information (0-11) */ + __IO uint32_t SECTORM; /*!< Previous sector information for input processing (0-11)*/ + __IO uint32_t IAO; /*!< AD conversion result of a-phase zero-current */ + __IO uint32_t IBO; /*!< AD conversion result of b-phase zero-current */ + __IO uint32_t ICO; /*!< AD conversion result of c-phase zero-current */ + __IO uint32_t IAADC; /*!< AD conversion result of a-phase current */ + __IO uint32_t IBADC; /*!< AD conversion result of b-phase current */ + __IO uint32_t ICADC; /*!< AD conversion result of c-phase current */ + __IO uint32_t VDC; /*!< DC supply voltage (voltage [V] / maximum voltage * 2^15)*/ + __IO uint32_t ID; /*!< d-axis current (current [A] / maximum current * 2^31)*/ + __IO uint32_t IQ; /*!< q-axis current (current [A] / maximum current * 2^31)*/ + uint32_t RESERVED1[39]; + __IO uint32_t TADC; /*!< ADC start wait setting */ + __IO uint32_t CMPU; /*!< PMD control: CMPU setting */ + __IO uint32_t CMPV; /*!< PMD control: CMPV setting */ + __IO uint32_t CMPW; /*!< PMD control: CMPW setting */ + __IO uint32_t OUTCR; /*!< PMD control: Output control (MDOUT) */ + __IO uint32_t TRGCMP0; /*!< PMD control: TRGCMP0 setting */ + __IO uint32_t TRGCMP1; /*!< PMD control: TRGCMP1 setting */ + __IO uint32_t TRGSEL; /*!< PMD control: Trigger selection */ + __O uint32_t EMGRS; /*!< PMD control: EMG return (EMGCR[EMGRS]) */ + uint32_t RESERVED2[8]; + __IO uint32_t PIOLIM; /*!< PI controlled output limit value setting */ + __IO uint32_t CIDKG; /*!< PI controlled d-axis coefficient range setting*/ + __IO uint32_t CIQKG; /*!< PI controlled q-axis coefficient range setting*/ + __IO uint32_t VSLIM; /*!< Voltage scalar limits */ + __IO uint32_t VDQ; /*!< Voltage scalar */ + __IO uint32_t DELTA; /*!< Declination angle */ + __IO uint32_t CPHI; /*!< Motor interlinkage magnetic flux */ + __IO uint32_t CLD; /*!< Motor q-axis inductance */ + __IO uint32_t CLQ; /*!< Motor d-axis inductance */ + __IO uint32_t CR; /*!< Motor resistance value */ + __IO uint32_t CPHIG; /*!< Motor magnetic flux range setting */ + __IO uint32_t CLG; /*!< Motor inductance range setting */ + __IO uint32_t CRG; /*!< Motor resistance range setting */ + __IO uint32_t VDE; /*!< Non-interference controlled d-axis voltage */ + __IO uint32_t VQE; /*!< Non-interference controlled q-axis voltage */ + __IO uint32_t DTC; /*!< Dead time compensation */ + __IO uint32_t HYS; /*!< Hysteresis width for current discrimination */ + __IO uint32_t DTCS; /*!< Dead time compensation control / status */ + __IO uint32_t PWMMAX; /*!< PWM upper limit setting */ + __IO uint32_t PWMMIN; /*!< PWM lower limit setting */ + __IO uint32_t THTCLP; /*!< Clipped phase value setting */ + __IO uint32_t HYS2; /*!< The second threshold value for determining the current polarity*/ + __IO uint32_t VALPHA; /*!< ALPHA-phase voltage */ + __IO uint32_t VBETA; /*!< BETA-phase voltage */ + __IO uint32_t VDUTYA; /*!< A-phase duty */ + __IO uint32_t VDUTYB; /*!< B-phase duty */ + __IO uint32_t VDUTYC; /*!< C-phase duty */ + __IO uint32_t IALPHA; /*!< ALPHA-phase current */ + __IO uint32_t IBETA; /*!< BETA-phase current */ + __IO uint32_t IA; /*!< A-phase current */ + __IO uint32_t IB; /*!< B-phase current */ + __IO uint32_t IC; /*!< C-phase current */ + __IO uint32_t VDELTA; /*!< VDQ Declination angle */ + __IO uint32_t VDCRC; /*!< d-axis voltage correction value */ + __IO uint32_t VQCRC; /*!< q-axis voltage correction value */ +} TSB_VE_TypeDef; + +/** + * @brief Flash Memory Interface (FC) + */ +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ + __I uint32_t SSR; /*!< Flash Security Status Register */ + __O uint32_t KCR; /*!< Flash Key Code Register */ + uint32_t RESERVED1; + __I uint32_t SR0; /*!< Flash Status Register 0 */ + uint32_t RESERVED2[3]; + __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ + __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ + uint32_t RESERVED3[4]; + __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ + uint32_t RESERVED4; + __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ + __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ + uint32_t RESERVED5[4]; + __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ + uint32_t RESERVED6[37]; + __I uint32_t SR1; /*!< Flash Status Register 1 */ + __I uint32_t SWPSR; /*!< Flash Memory SWAP Status Register */ + uint32_t RESERVED7[14]; + __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ + uint32_t RESERVED8; + __IO uint32_t CR; /*!< Flash Control Register */ + __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ + __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ + __IO uint32_t FCACCR; /*!< Flash Access Control Register */ + __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ +} TSB_FC_TypeDef; + + +/* Memory map */ +#define FLASH_BASE (0x00000000UL) +#define RAM_BASE (0x20000000UL) +#define PERI_BASE (0x40000000UL) + + +#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) +#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) +#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) +#define TSB_RPAR0_BASE (PERI_BASE + 0x0043000UL) +#define TSB_RPAR1_BASE (PERI_BASE + 0x00A3000UL) +#define TSB_CRC_BASE (PERI_BASE + 0x0043100UL) +#define TSB_CG_BASE (PERI_BASE + 0x0083000UL) +#define TSB_IB_BASE (PERI_BASE + 0x0083200UL) +#define TSB_IMN_BASE (PERI_BASE + 0x0083300UL) +#define TSB_DNFA_BASE (PERI_BASE + 0x00A0200UL) +#define TSB_DNFB_BASE (PERI_BASE + 0x00A0300UL) +#define TSB_DNFC_BASE (PERI_BASE + 0x00A0800UL) +#define TSB_TSEL0_BASE (PERI_BASE + 0x00A0400UL) +#define TSB_SIWD0_BASE (PERI_BASE + 0x00A0600UL) +#define TSB_NBD_BASE (PERI_BASE + 0x00A2000UL) +#define TSB_DMAA_BASE (PERI_BASE + 0x00A4000UL) +#define TSB_ADA_BASE (PERI_BASE + 0x00BA000UL) +#define TSB_ADB_BASE (PERI_BASE + 0x00BA400UL) +#define TSB_ADC_BASE (PERI_BASE + 0x00BA800UL) +#define TSB_AMP_BASE (PERI_BASE + 0x00BD000UL) +#define TSB_T32A0_BASE (PERI_BASE + 0x00C1000UL) +#define TSB_T32A1_BASE (PERI_BASE + 0x00C1400UL) +#define TSB_T32A2_BASE (PERI_BASE + 0x00C1800UL) +#define TSB_T32A3_BASE (PERI_BASE + 0x00C1C00UL) +#define TSB_T32A4_BASE (PERI_BASE + 0x00C2000UL) +#define TSB_T32A5_BASE (PERI_BASE + 0x00C2400UL) +#define TSB_TSPI0_BASE (PERI_BASE + 0x00CA000UL) +#define TSB_TSPI1_BASE (PERI_BASE + 0x00CA400UL) +#define TSB_UART0_BASE (PERI_BASE + 0x00CE000UL) +#define TSB_UART1_BASE (PERI_BASE + 0x00CE400UL) +#define TSB_UART2_BASE (PERI_BASE + 0x00CE800UL) +#define TSB_UART3_BASE (PERI_BASE + 0x00CEC00UL) +#define TSB_I2C0_BASE (PERI_BASE + 0x00D1000UL) +#define TSB_I2C1_BASE (PERI_BASE + 0x00D2000UL) +#define TSB_EI2C0_BASE (PERI_BASE + 0x00D8000UL) +#define TSB_EI2C1_BASE (PERI_BASE + 0x00D9000UL) +#define TSB_PA_BASE (PERI_BASE + 0x00E0000UL) +#define TSB_PB_BASE (PERI_BASE + 0x00E0100UL) +#define TSB_PC_BASE (PERI_BASE + 0x00E0200UL) +#define TSB_PD_BASE (PERI_BASE + 0x00E0300UL) +#define TSB_PE_BASE (PERI_BASE + 0x00E0400UL) +#define TSB_PF_BASE (PERI_BASE + 0x00E0500UL) +#define TSB_PG_BASE (PERI_BASE + 0x00E0600UL) +#define TSB_PH_BASE (PERI_BASE + 0x00E0700UL) +#define TSB_PJ_BASE (PERI_BASE + 0x00E0800UL) +#define TSB_PK_BASE (PERI_BASE + 0x00E0900UL) +#define TSB_PL_BASE (PERI_BASE + 0x00E0A00UL) +#define TSB_PM_BASE (PERI_BASE + 0x00E0B00UL) +#define TSB_PN_BASE (PERI_BASE + 0x00E0C00UL) +#define TSB_PU_BASE (PERI_BASE + 0x00E1000UL) +#define TSB_PV_BASE (PERI_BASE + 0x00E1100UL) +#define TSB_TRM_BASE (PERI_BASE + 0x00E3100UL) +#define TSB_OFD_BASE (PERI_BASE + 0x00E4000UL) +#define TSB_PMD0_BASE (PERI_BASE + 0x00E9000UL) +#define TSB_PMD1_BASE (PERI_BASE + 0x00E9400UL) +#define TSB_PMD2_BASE (PERI_BASE + 0x00E9800UL) +#define TSB_EN0_BASE (PERI_BASE + 0x00EA000UL) +#define TSB_EN1_BASE (PERI_BASE + 0x00EA400UL) +#define TSB_EN2_BASE (PERI_BASE + 0x00EA800UL) +#define TSB_VE0_BASE (PERI_BASE + 0x00EB000UL) +#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) + + +/* Peripheral declaration */ +#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) +#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) +#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) +#define TSB_RPAR0 (( TSB_RPAR_TypeDef *) TSB_RPAR0_BASE) +#define TSB_RPAR1 (( TSB_RPAR_TypeDef *) TSB_RPAR1_BASE) +#define TSB_CRC (( TSB_CRC_TypeDef *) TSB_CRC_BASE) +#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) +#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) +#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) +#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) +#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) +#define TSB_DNFC (( TSB_DNF_TypeDef *) TSB_DNFC_BASE) +#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) +#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) +#define TSB_NBD (( TSB_NBD_TypeDef *) TSB_NBD_BASE) +#define TSB_DMAA (( TSB_DMA_TypeDef *) TSB_DMAA_BASE) +#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) +#define TSB_ADB (( TSB_AD_TypeDef *) TSB_ADB_BASE) +#define TSB_ADC (( TSB_AD_TypeDef *) TSB_ADC_BASE) +#define TSB_AMP (( TSB_AMP_TypeDef *) TSB_AMP_BASE) +#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) +#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) +#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) +#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) +#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) +#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) +#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) +#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) +#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) +#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) +#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) +#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) +#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) +#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) +#define TSB_EI2C0 (( TSB_EI2C_TypeDef *) TSB_EI2C0_BASE) +#define TSB_EI2C1 (( TSB_EI2C_TypeDef *) TSB_EI2C1_BASE) +#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) +#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) +#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) +#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) +#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) +#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) +#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) +#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) +#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) +#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) +#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) +#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) +#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) +#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) +#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) +#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) +#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) +#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) +#define TSB_PMD1 (( TSB_PMD_TypeDef *) TSB_PMD1_BASE) +#define TSB_PMD2 (( TSB_PMD_TypeDef *) TSB_PMD2_BASE) +#define TSB_EN0 (( TSB_EN_TypeDef *) TSB_EN0_BASE) +#define TSB_EN1 (( TSB_EN_TypeDef *) TSB_EN1_BASE) +#define TSB_EN2 (( TSB_EN_TypeDef *) TSB_EN2_BASE) +#define TSB_VE0 (( TSB_VE_TypeDef *) TSB_VE0_BASE) +#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) + + +/* Bit-Band for Device Specific Peripheral Registers */ +#define BITBAND_OFFSET (0x02000000UL) +#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) +#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) + + + + + + +/* RAM Parity (RAMP) */ +#define TSB_RPAR0_CTL_RPAREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR0->CTL,0))) +#define TSB_RPAR0_CTL_RPARF (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR0->CTL,1))) +#define TSB_RPAR0_ST_RPARFG0 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR0->ST,0))) +#define TSB_RPAR0_ST_RPARFG1 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR0->ST,1))) +#define TSB_RPAR0_CLR_RPARCLR0 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR0->CLR,0))) +#define TSB_RPAR0_CLR_RPARCLR1 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR0->CLR,1))) + +#define TSB_RPAR1_CTL_RPAREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR1->CTL,0))) +#define TSB_RPAR1_CTL_RPARF (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR1->CTL,1))) +#define TSB_RPAR1_ST_RPARFG0 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR1->ST,0))) +#define TSB_RPAR1_ST_RPARFG1 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR1->ST,1))) +#define TSB_RPAR1_CLR_RPARCLR0 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR1->CLR,0))) +#define TSB_RPAR1_CLR_RPARCLR1 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR1->CLR,1))) + + + +/* Clock Control and Operation Mode (CG) */ +#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) +#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) +#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) +#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) +#define TSB_CG_OSCCR_IHOSC2F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,19))) +#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) +#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) +#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) +#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) +#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) +#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) +#define TSB_CG_FSYSMENA_IPMENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,0))) +#define TSB_CG_FSYSMENA_IPMENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,1))) +#define TSB_CG_FSYSMENA_IPMENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,2))) +#define TSB_CG_FSYSMENA_IPMENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,3))) +#define TSB_CG_FSYSMENA_IPMENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,4))) +#define TSB_CG_FSYSMENA_IPMENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,5))) +#define TSB_CG_FSYSMENA_IPMENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,6))) +#define TSB_CG_FSYSMENA_IPMENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,7))) +#define TSB_CG_FSYSMENA_IPMENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,8))) +#define TSB_CG_FSYSMENA_IPMENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,9))) +#define TSB_CG_FSYSMENA_IPMENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,10))) +#define TSB_CG_FSYSMENA_IPMENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,11))) +#define TSB_CG_FSYSMENA_IPMENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,12))) +#define TSB_CG_FSYSMENA_IPMENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,16))) +#define TSB_CG_FSYSMENA_IPMENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,17))) +#define TSB_CG_FSYSMENA_IPMENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,19))) +#define TSB_CG_FSYSMENA_IPMENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,20))) +#define TSB_CG_FSYSMENA_IPMENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,21))) +#define TSB_CG_FSYSMENA_IPMENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,22))) +#define TSB_CG_FSYSMENA_IPMENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,23))) +#define TSB_CG_FSYSMENA_IPMENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,24))) +#define TSB_CG_FSYSMENA_IPMENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,25))) +#define TSB_CG_FSYSMENA_IPMENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,26))) +#define TSB_CG_FSYSMENA_IPMENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,28))) +#define TSB_CG_FSYSMENA_IPMENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,29))) +#define TSB_CG_FSYSMENA_IPMENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,30))) +#define TSB_CG_FSYSMENA_IPMENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,31))) +#define TSB_CG_FSYSMENB_IPMENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,0))) +#define TSB_CG_FSYSMENB_IPMENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,1))) +#define TSB_CG_FSYSMENB_IPMENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,2))) +#define TSB_CG_FSYSMENB_IPMENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,3))) +#define TSB_CG_FSYSMENB_IPMENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,4))) +#define TSB_CG_FSYSMENB_IPMENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,5))) +#define TSB_CG_FSYSMENB_IPMENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,6))) +#define TSB_CG_FSYSMENB_IPMENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,7))) +#define TSB_CG_FSYSMENB_IPMENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,8))) +#define TSB_CG_FSYSMENB_IPMENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,9))) +#define TSB_CG_FSYSMENB_IPMENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,10))) +#define TSB_CG_FSYSMENB_IPMENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,11))) +#define TSB_CG_FSYSMENB_IPMENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,12))) +#define TSB_CG_FSYSMENB_IPMENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,13))) +#define TSB_CG_FSYSMENB_IPMENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,14))) +#define TSB_CG_FSYSMENB_IPMENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,15))) +#define TSB_CG_FSYSMENB_IPMENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,16))) +#define TSB_CG_FSYSMENB_IPMENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,17))) +#define TSB_CG_FSYSMENB_IPMENB25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,25))) +#define TSB_CG_FSYSMENB_IPMENB26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,26))) +#define TSB_CG_FSYSMENB_IPMENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,29))) +#define TSB_CG_FSYSMENB_IPMENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,30))) +#define TSB_CG_FSYSMENB_IPMENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,31))) +#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) +#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) +#define TSB_CG_FCEN_FCIPEN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,23))) +#define TSB_CG_FCEN_FCIPEN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,26))) +#define TSB_CG_FCEN_FCIPEN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,27))) +#define TSB_CG_FCEN_FCIPEN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,28))) +#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) +#define TSB_CG_SPCLKEN_ADCKEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) +#define TSB_CG_SPCLKEN_ADCKEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,17))) +#define TSB_CG_SPCLKEN_ADCKEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,18))) + + + +/* Interrupt Monitor Register (IMN) */ +#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) +#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) +#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) +#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) +#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) +#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) +#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) +#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) +#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) +#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) +#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) +#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) +#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) +#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) +#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) +#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) +#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) +#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) +#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) +#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) +#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) +#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) +#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) +#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) +#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) +#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) +#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) +#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) +#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) +#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) +#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) +#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) +#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) +#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) +#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) +#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) +#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) +#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) +#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) +#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) +#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) +#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) +#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) +#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) +#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) +#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) +#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) +#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) +#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) +#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) +#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) +#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) +#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) +#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) +#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) +#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) +#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) +#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) +#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) +#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) +#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) +#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) +#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) +#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) +#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) +#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) +#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) +#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) + + +/* Digital Noise Filter (DNF) */ +#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) +#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) +#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) +#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) +#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) +#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) +#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) +#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) +#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) +#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) +#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) +#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) +#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) +#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) +#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) +#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) + +#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) +#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) +#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) +#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) +#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) +#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) +#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) +#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) +#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) +#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) +#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) +#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) +#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) +#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) +#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) +#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) + +#define TSB_DNFC_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,0))) +#define TSB_DNFC_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,1))) +#define TSB_DNFC_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,2))) +#define TSB_DNFC_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,3))) +#define TSB_DNFC_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,4))) +#define TSB_DNFC_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,5))) +#define TSB_DNFC_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,6))) +#define TSB_DNFC_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,7))) +#define TSB_DNFC_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,8))) +#define TSB_DNFC_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,9))) +#define TSB_DNFC_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,10))) +#define TSB_DNFC_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,11))) +#define TSB_DNFC_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,12))) +#define TSB_DNFC_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,13))) +#define TSB_DNFC_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,14))) +#define TSB_DNFC_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,15))) + + +/* Trigger Selection circuit (TSEL) */ +#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) +#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) +#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) +#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) +#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) +#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) +#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) +#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) +#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) +#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) +#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) +#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) +#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) +#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) +#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) +#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) +#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) +#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) +#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) +#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) +#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) +#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) +#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) +#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) +#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) +#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) +#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) +#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) +#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) +#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) +#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) +#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) +#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) +#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) +#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) +#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) +#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) +#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) +#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) +#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) +#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) +#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) +#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) +#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) +#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) +#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) +#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) +#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) +#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) +#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) +#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) +#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) +#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) +#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) +#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) +#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) +#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) +#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) +#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) +#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) +#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) +#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) +#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) +#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) +#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) +#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) +#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) +#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) +#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) +#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) +#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) +#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) +#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) +#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) +#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) +#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) +#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) +#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) +#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) +#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) +#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) +#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) +#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) +#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) +#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) +#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) +#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) +#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) +#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) +#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) +#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) +#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) +#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) +#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) +#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) +#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) +#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) +#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) +#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) +#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) +#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) +#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) +#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) +#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) +#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) +#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) +#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) +#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) +#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) +#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) +#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) +#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) +#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) +#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) +#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) +#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) +#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) +#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) +#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) +#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) +#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) +#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) +#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) +#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) +#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) +#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) +#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) +#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) +#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) + + +/* Watchdog Timer (SIWD) */ +#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) +#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) +#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) +#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) +#define TSB_SIWD0_OSCCR_OSCPRO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->OSCCR,0))) + + +/* Non-Break Debug Interface (NBD) */ +#define TSB_NBD_CR0_NBDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_NBD->CR0,0))) + + +/* Direct Memory Access Controller (DMAC) */ +#define TSB_DMAA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAA->STATUS,0))) +#define TSB_DMAA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAA->CFG,0))) +#define TSB_DMAA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAA->ERRCLR,0))) + + +/* 12-bit Analog to Digital Converter(ADC) */ +#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) +#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) +#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) +#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) +#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) +#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) +#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) +#define TSB_ADA_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) +#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) +#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) +#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) +#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) +#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) +#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) +#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) +#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) +#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) +#define TSB_ADA_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) +#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) +#define TSB_ADA_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) +#define TSB_ADA_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL0,7))) +#define TSB_ADA_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL1,7))) +#define TSB_ADA_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL2,7))) +#define TSB_ADA_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL3,7))) +#define TSB_ADA_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL4,7))) +#define TSB_ADA_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL5,7))) +#define TSB_ADA_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL6,7))) +#define TSB_ADA_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL7,7))) +#define TSB_ADA_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL8,7))) +#define TSB_ADA_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL9,7))) +#define TSB_ADA_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL10,7))) +#define TSB_ADA_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL11,7))) +#define TSB_ADA_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,7))) +#define TSB_ADA_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,15))) +#define TSB_ADA_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,23))) +#define TSB_ADA_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,31))) +#define TSB_ADA_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,7))) +#define TSB_ADA_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,15))) +#define TSB_ADA_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,23))) +#define TSB_ADA_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,31))) +#define TSB_ADA_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,7))) +#define TSB_ADA_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,15))) +#define TSB_ADA_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,23))) +#define TSB_ADA_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,31))) +#define TSB_ADA_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,7))) +#define TSB_ADA_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,15))) +#define TSB_ADA_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,23))) +#define TSB_ADA_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,31))) +#define TSB_ADA_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,7))) +#define TSB_ADA_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,15))) +#define TSB_ADA_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,23))) +#define TSB_ADA_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,31))) +#define TSB_ADA_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,7))) +#define TSB_ADA_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,15))) +#define TSB_ADA_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,23))) +#define TSB_ADA_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,31))) +#define TSB_ADA_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,7))) +#define TSB_ADA_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,15))) +#define TSB_ADA_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,23))) +#define TSB_ADA_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,31))) +#define TSB_ADA_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,7))) +#define TSB_ADA_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,15))) +#define TSB_ADA_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,23))) +#define TSB_ADA_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,31))) +#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) +#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) +#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) +#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) +#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) +#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) +#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) +#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) +#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) +#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) +#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) +#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) +#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) +#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) +#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) +#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) +#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) +#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) +#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) +#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) +#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) +#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) +#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) +#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) +#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) +#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) +#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) +#define TSB_ADA_REG0_ADOVRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) +#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) +#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) +#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) +#define TSB_ADA_REG1_ADOVRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) +#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) +#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) +#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) +#define TSB_ADA_REG2_ADOVRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) +#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) +#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) +#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) +#define TSB_ADA_REG3_ADOVRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) +#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) +#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) +#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) +#define TSB_ADA_REG4_ADOVRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) +#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) +#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) +#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) +#define TSB_ADA_REG5_ADOVRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) +#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) +#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) +#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) +#define TSB_ADA_REG6_ADOVRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) +#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) +#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) +#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) +#define TSB_ADA_REG7_ADOVRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) +#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) +#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) +#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) +#define TSB_ADA_REG8_ADOVRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) +#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) +#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) +#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) +#define TSB_ADA_REG9_ADOVRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) +#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) +#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) +#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) +#define TSB_ADA_REG10_ADOVRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) +#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) +#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) +#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) +#define TSB_ADA_REG11_ADOVRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) +#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) +#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) +#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) +#define TSB_ADA_REG12_ADOVRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) +#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) +#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) +#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) +#define TSB_ADA_REG13_ADOVRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) +#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) +#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) +#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) +#define TSB_ADA_REG14_ADOVRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) +#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) +#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) +#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) +#define TSB_ADA_REG15_ADOVRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) +#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) +#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) +#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) +#define TSB_ADA_REG16_ADOVRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) +#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) +#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) +#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) +#define TSB_ADA_REG17_ADOVRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) +#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) +#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) +#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) +#define TSB_ADA_REG18_ADOVRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) +#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) +#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) +#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) +#define TSB_ADA_REG19_ADOVRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) +#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) +#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) +#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) +#define TSB_ADA_REG20_ADOVRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) +#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) +#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) +#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) +#define TSB_ADA_REG21_ADOVRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) +#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) +#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) +#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) +#define TSB_ADA_REG22_ADOVRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) +#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) +#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) +#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) +#define TSB_ADA_REG23_ADOVRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) + +#define TSB_ADB_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR0,0))) +#define TSB_ADB_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADB->CR0,1))) +#define TSB_ADB_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR0,7))) +#define TSB_ADB_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR1,0))) +#define TSB_ADB_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR1,4))) +#define TSB_ADB_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR1,5))) +#define TSB_ADB_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR1,6))) +#define TSB_ADB_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->ST,0))) +#define TSB_ADB_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->ST,1))) +#define TSB_ADB_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->ST,2))) +#define TSB_ADB_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->ST,3))) +#define TSB_ADB_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->ST,7))) +#define TSB_ADB_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->MOD0,0))) +#define TSB_ADB_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->MOD0,1))) +#define TSB_ADB_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPEN,0))) +#define TSB_ADB_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPEN,1))) +#define TSB_ADB_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPCR0,5))) +#define TSB_ADB_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPCR0,6))) +#define TSB_ADB_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPCR1,5))) +#define TSB_ADB_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPCR1,6))) +#define TSB_ADB_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL0,7))) +#define TSB_ADB_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL1,7))) +#define TSB_ADB_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL2,7))) +#define TSB_ADB_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL3,7))) +#define TSB_ADB_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL4,7))) +#define TSB_ADB_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL5,7))) +#define TSB_ADB_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL6,7))) +#define TSB_ADB_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL7,7))) +#define TSB_ADB_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL8,7))) +#define TSB_ADB_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL9,7))) +#define TSB_ADB_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL10,7))) +#define TSB_ADB_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL11,7))) +#define TSB_ADB_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET0,7))) +#define TSB_ADB_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET0,15))) +#define TSB_ADB_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET0,23))) +#define TSB_ADB_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET0,31))) +#define TSB_ADB_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET1,7))) +#define TSB_ADB_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET1,15))) +#define TSB_ADB_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET1,23))) +#define TSB_ADB_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET1,31))) +#define TSB_ADB_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET2,7))) +#define TSB_ADB_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET2,15))) +#define TSB_ADB_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET2,23))) +#define TSB_ADB_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET2,31))) +#define TSB_ADB_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET3,7))) +#define TSB_ADB_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET3,15))) +#define TSB_ADB_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET3,23))) +#define TSB_ADB_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET3,31))) +#define TSB_ADB_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET4,7))) +#define TSB_ADB_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET4,15))) +#define TSB_ADB_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET4,23))) +#define TSB_ADB_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET4,31))) +#define TSB_ADB_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET5,7))) +#define TSB_ADB_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET5,15))) +#define TSB_ADB_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET5,23))) +#define TSB_ADB_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET5,31))) +#define TSB_ADB_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET6,7))) +#define TSB_ADB_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET6,15))) +#define TSB_ADB_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET6,23))) +#define TSB_ADB_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET6,31))) +#define TSB_ADB_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET7,7))) +#define TSB_ADB_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET7,15))) +#define TSB_ADB_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET7,23))) +#define TSB_ADB_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET7,31))) +#define TSB_ADB_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET0,7))) +#define TSB_ADB_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET1,7))) +#define TSB_ADB_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET2,7))) +#define TSB_ADB_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET3,7))) +#define TSB_ADB_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET4,7))) +#define TSB_ADB_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET5,7))) +#define TSB_ADB_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET6,7))) +#define TSB_ADB_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET7,7))) +#define TSB_ADB_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET8,7))) +#define TSB_ADB_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET9,7))) +#define TSB_ADB_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET10,7))) +#define TSB_ADB_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET11,7))) +#define TSB_ADB_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET12,7))) +#define TSB_ADB_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET13,7))) +#define TSB_ADB_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET14,7))) +#define TSB_ADB_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET15,7))) +#define TSB_ADB_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET16,7))) +#define TSB_ADB_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET17,7))) +#define TSB_ADB_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET18,7))) +#define TSB_ADB_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET19,7))) +#define TSB_ADB_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET20,7))) +#define TSB_ADB_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET21,7))) +#define TSB_ADB_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET22,7))) +#define TSB_ADB_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET23,7))) +#define TSB_ADB_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG0,0))) +#define TSB_ADB_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG0,1))) +#define TSB_ADB_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG0,28))) +#define TSB_ADB_REG0_ADOVRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG0,29))) +#define TSB_ADB_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG1,0))) +#define TSB_ADB_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG1,1))) +#define TSB_ADB_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG1,28))) +#define TSB_ADB_REG1_ADOVRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG1,29))) +#define TSB_ADB_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG2,0))) +#define TSB_ADB_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG2,1))) +#define TSB_ADB_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG2,28))) +#define TSB_ADB_REG2_ADOVRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG2,29))) +#define TSB_ADB_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG3,0))) +#define TSB_ADB_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG3,1))) +#define TSB_ADB_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG3,28))) +#define TSB_ADB_REG3_ADOVRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG3,29))) +#define TSB_ADB_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG4,0))) +#define TSB_ADB_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG4,1))) +#define TSB_ADB_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG4,28))) +#define TSB_ADB_REG4_ADOVRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG4,29))) +#define TSB_ADB_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG5,0))) +#define TSB_ADB_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG5,1))) +#define TSB_ADB_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG5,28))) +#define TSB_ADB_REG5_ADOVRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG5,29))) +#define TSB_ADB_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG6,0))) +#define TSB_ADB_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG6,1))) +#define TSB_ADB_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG6,28))) +#define TSB_ADB_REG6_ADOVRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG6,29))) +#define TSB_ADB_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG7,0))) +#define TSB_ADB_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG7,1))) +#define TSB_ADB_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG7,28))) +#define TSB_ADB_REG7_ADOVRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG7,29))) +#define TSB_ADB_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG8,0))) +#define TSB_ADB_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG8,1))) +#define TSB_ADB_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG8,28))) +#define TSB_ADB_REG8_ADOVRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG8,29))) +#define TSB_ADB_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG9,0))) +#define TSB_ADB_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG9,1))) +#define TSB_ADB_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG9,28))) +#define TSB_ADB_REG9_ADOVRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG9,29))) +#define TSB_ADB_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG10,0))) +#define TSB_ADB_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG10,1))) +#define TSB_ADB_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG10,28))) +#define TSB_ADB_REG10_ADOVRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG10,29))) +#define TSB_ADB_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG11,0))) +#define TSB_ADB_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG11,1))) +#define TSB_ADB_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG11,28))) +#define TSB_ADB_REG11_ADOVRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG11,29))) +#define TSB_ADB_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG12,0))) +#define TSB_ADB_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG12,1))) +#define TSB_ADB_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG12,28))) +#define TSB_ADB_REG12_ADOVRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG12,29))) +#define TSB_ADB_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG13,0))) +#define TSB_ADB_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG13,1))) +#define TSB_ADB_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG13,28))) +#define TSB_ADB_REG13_ADOVRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG13,29))) +#define TSB_ADB_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG14,0))) +#define TSB_ADB_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG14,1))) +#define TSB_ADB_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG14,28))) +#define TSB_ADB_REG14_ADOVRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG14,29))) +#define TSB_ADB_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG15,0))) +#define TSB_ADB_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG15,1))) +#define TSB_ADB_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG15,28))) +#define TSB_ADB_REG15_ADOVRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG15,29))) +#define TSB_ADB_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG16,0))) +#define TSB_ADB_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG16,1))) +#define TSB_ADB_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG16,28))) +#define TSB_ADB_REG16_ADOVRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG16,29))) +#define TSB_ADB_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG17,0))) +#define TSB_ADB_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG17,1))) +#define TSB_ADB_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG17,28))) +#define TSB_ADB_REG17_ADOVRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG17,29))) +#define TSB_ADB_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG18,0))) +#define TSB_ADB_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG18,1))) +#define TSB_ADB_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG18,28))) +#define TSB_ADB_REG18_ADOVRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG18,29))) +#define TSB_ADB_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG19,0))) +#define TSB_ADB_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG19,1))) +#define TSB_ADB_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG19,28))) +#define TSB_ADB_REG19_ADOVRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG19,29))) +#define TSB_ADB_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG20,0))) +#define TSB_ADB_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG20,1))) +#define TSB_ADB_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG20,28))) +#define TSB_ADB_REG20_ADOVRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG20,29))) +#define TSB_ADB_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG21,0))) +#define TSB_ADB_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG21,1))) +#define TSB_ADB_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG21,28))) +#define TSB_ADB_REG21_ADOVRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG21,29))) +#define TSB_ADB_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG22,0))) +#define TSB_ADB_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG22,1))) +#define TSB_ADB_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG22,28))) +#define TSB_ADB_REG22_ADOVRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG22,29))) +#define TSB_ADB_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG23,0))) +#define TSB_ADB_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG23,1))) +#define TSB_ADB_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG23,28))) +#define TSB_ADB_REG23_ADOVRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG23,29))) + +#define TSB_ADC_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR0,0))) +#define TSB_ADC_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADC->CR0,1))) +#define TSB_ADC_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR0,7))) +#define TSB_ADC_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR1,0))) +#define TSB_ADC_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR1,4))) +#define TSB_ADC_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR1,5))) +#define TSB_ADC_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR1,6))) +#define TSB_ADC_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->ST,0))) +#define TSB_ADC_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->ST,1))) +#define TSB_ADC_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->ST,2))) +#define TSB_ADC_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->ST,3))) +#define TSB_ADC_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->ST,7))) +#define TSB_ADC_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->MOD0,0))) +#define TSB_ADC_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->MOD0,1))) +#define TSB_ADC_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPEN,0))) +#define TSB_ADC_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPEN,1))) +#define TSB_ADC_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPCR0,5))) +#define TSB_ADC_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPCR0,6))) +#define TSB_ADC_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPCR1,5))) +#define TSB_ADC_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPCR1,6))) +#define TSB_ADC_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL0,7))) +#define TSB_ADC_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL1,7))) +#define TSB_ADC_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL2,7))) +#define TSB_ADC_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL3,7))) +#define TSB_ADC_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL4,7))) +#define TSB_ADC_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL5,7))) +#define TSB_ADC_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL6,7))) +#define TSB_ADC_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL7,7))) +#define TSB_ADC_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL8,7))) +#define TSB_ADC_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL9,7))) +#define TSB_ADC_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL10,7))) +#define TSB_ADC_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL11,7))) +#define TSB_ADC_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET0,7))) +#define TSB_ADC_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET0,15))) +#define TSB_ADC_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET0,23))) +#define TSB_ADC_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET0,31))) +#define TSB_ADC_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET1,7))) +#define TSB_ADC_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET1,15))) +#define TSB_ADC_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET1,23))) +#define TSB_ADC_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET1,31))) +#define TSB_ADC_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET2,7))) +#define TSB_ADC_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET2,15))) +#define TSB_ADC_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET2,23))) +#define TSB_ADC_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET2,31))) +#define TSB_ADC_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET3,7))) +#define TSB_ADC_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET3,15))) +#define TSB_ADC_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET3,23))) +#define TSB_ADC_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET3,31))) +#define TSB_ADC_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET4,7))) +#define TSB_ADC_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET4,15))) +#define TSB_ADC_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET4,23))) +#define TSB_ADC_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET4,31))) +#define TSB_ADC_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET5,7))) +#define TSB_ADC_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET5,15))) +#define TSB_ADC_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET5,23))) +#define TSB_ADC_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET5,31))) +#define TSB_ADC_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET6,7))) +#define TSB_ADC_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET6,15))) +#define TSB_ADC_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET6,23))) +#define TSB_ADC_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET6,31))) +#define TSB_ADC_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET7,7))) +#define TSB_ADC_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET7,15))) +#define TSB_ADC_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET7,23))) +#define TSB_ADC_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET7,31))) +#define TSB_ADC_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET0,7))) +#define TSB_ADC_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET1,7))) +#define TSB_ADC_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET2,7))) +#define TSB_ADC_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET3,7))) +#define TSB_ADC_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET4,7))) +#define TSB_ADC_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET5,7))) +#define TSB_ADC_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET6,7))) +#define TSB_ADC_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET7,7))) +#define TSB_ADC_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET8,7))) +#define TSB_ADC_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET9,7))) +#define TSB_ADC_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET10,7))) +#define TSB_ADC_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET11,7))) +#define TSB_ADC_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET12,7))) +#define TSB_ADC_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET13,7))) +#define TSB_ADC_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET14,7))) +#define TSB_ADC_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET15,7))) +#define TSB_ADC_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET16,7))) +#define TSB_ADC_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET17,7))) +#define TSB_ADC_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET18,7))) +#define TSB_ADC_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET19,7))) +#define TSB_ADC_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET20,7))) +#define TSB_ADC_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET21,7))) +#define TSB_ADC_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET22,7))) +#define TSB_ADC_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET23,7))) +#define TSB_ADC_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG0,0))) +#define TSB_ADC_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG0,1))) +#define TSB_ADC_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG0,28))) +#define TSB_ADC_REG0_ADOVRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG0,29))) +#define TSB_ADC_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG1,0))) +#define TSB_ADC_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG1,1))) +#define TSB_ADC_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG1,28))) +#define TSB_ADC_REG1_ADOVRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG1,29))) +#define TSB_ADC_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG2,0))) +#define TSB_ADC_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG2,1))) +#define TSB_ADC_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG2,28))) +#define TSB_ADC_REG2_ADOVRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG2,29))) +#define TSB_ADC_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG3,0))) +#define TSB_ADC_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG3,1))) +#define TSB_ADC_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG3,28))) +#define TSB_ADC_REG3_ADOVRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG3,29))) +#define TSB_ADC_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG4,0))) +#define TSB_ADC_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG4,1))) +#define TSB_ADC_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG4,28))) +#define TSB_ADC_REG4_ADOVRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG4,29))) +#define TSB_ADC_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG5,0))) +#define TSB_ADC_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG5,1))) +#define TSB_ADC_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG5,28))) +#define TSB_ADC_REG5_ADOVRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG5,29))) +#define TSB_ADC_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG6,0))) +#define TSB_ADC_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG6,1))) +#define TSB_ADC_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG6,28))) +#define TSB_ADC_REG6_ADOVRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG6,29))) +#define TSB_ADC_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG7,0))) +#define TSB_ADC_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG7,1))) +#define TSB_ADC_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG7,28))) +#define TSB_ADC_REG7_ADOVRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG7,29))) +#define TSB_ADC_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG8,0))) +#define TSB_ADC_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG8,1))) +#define TSB_ADC_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG8,28))) +#define TSB_ADC_REG8_ADOVRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG8,29))) +#define TSB_ADC_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG9,0))) +#define TSB_ADC_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG9,1))) +#define TSB_ADC_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG9,28))) +#define TSB_ADC_REG9_ADOVRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG9,29))) +#define TSB_ADC_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG10,0))) +#define TSB_ADC_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG10,1))) +#define TSB_ADC_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG10,28))) +#define TSB_ADC_REG10_ADOVRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG10,29))) +#define TSB_ADC_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG11,0))) +#define TSB_ADC_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG11,1))) +#define TSB_ADC_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG11,28))) +#define TSB_ADC_REG11_ADOVRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG11,29))) +#define TSB_ADC_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG12,0))) +#define TSB_ADC_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG12,1))) +#define TSB_ADC_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG12,28))) +#define TSB_ADC_REG12_ADOVRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG12,29))) +#define TSB_ADC_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG13,0))) +#define TSB_ADC_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG13,1))) +#define TSB_ADC_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG13,28))) +#define TSB_ADC_REG13_ADOVRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG13,29))) +#define TSB_ADC_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG14,0))) +#define TSB_ADC_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG14,1))) +#define TSB_ADC_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG14,28))) +#define TSB_ADC_REG14_ADOVRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG14,29))) +#define TSB_ADC_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG15,0))) +#define TSB_ADC_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG15,1))) +#define TSB_ADC_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG15,28))) +#define TSB_ADC_REG15_ADOVRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG15,29))) +#define TSB_ADC_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG16,0))) +#define TSB_ADC_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG16,1))) +#define TSB_ADC_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG16,28))) +#define TSB_ADC_REG16_ADOVRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG16,29))) +#define TSB_ADC_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG17,0))) +#define TSB_ADC_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG17,1))) +#define TSB_ADC_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG17,28))) +#define TSB_ADC_REG17_ADOVRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG17,29))) +#define TSB_ADC_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG18,0))) +#define TSB_ADC_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG18,1))) +#define TSB_ADC_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG18,28))) +#define TSB_ADC_REG18_ADOVRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG18,29))) +#define TSB_ADC_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG19,0))) +#define TSB_ADC_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG19,1))) +#define TSB_ADC_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG19,28))) +#define TSB_ADC_REG19_ADOVRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG19,29))) +#define TSB_ADC_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG20,0))) +#define TSB_ADC_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG20,1))) +#define TSB_ADC_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG20,28))) +#define TSB_ADC_REG20_ADOVRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG20,29))) +#define TSB_ADC_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG21,0))) +#define TSB_ADC_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG21,1))) +#define TSB_ADC_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG21,28))) +#define TSB_ADC_REG21_ADOVRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG21,29))) +#define TSB_ADC_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG22,0))) +#define TSB_ADC_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG22,1))) +#define TSB_ADC_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG22,28))) +#define TSB_ADC_REG22_ADOVRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG22,29))) +#define TSB_ADC_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG23,0))) +#define TSB_ADC_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG23,1))) +#define TSB_ADC_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG23,28))) +#define TSB_ADC_REG23_ADOVRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG23,29))) + + +/* Gain Op-AMP (AMP) */ +#define TSB_AMP_CTLA_AMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_AMP->CTLA,0))) +#define TSB_AMP_CTLB_AMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_AMP->CTLB,0))) +#define TSB_AMP_CTLC_AMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_AMP->CTLC,0))) + + +/* 32-bit Timer Event Counter (T32A) */ +#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) +#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) +#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) +#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) +#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) +#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) +#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) +#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) +#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) +#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) +#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) +#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) +#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) +#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) +#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) +#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) +#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) +#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) +#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) +#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) +#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) +#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) +#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) +#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) +#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) +#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) +#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) +#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) +#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) +#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) +#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) +#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) +#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) +#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) +#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) +#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) +#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) +#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) +#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) +#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) +#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) +#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) +#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) +#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) +#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) +#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) +#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) +#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) +#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) +#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) +#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) +#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) +#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) +#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) + +#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) +#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) +#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) +#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) +#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) +#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) +#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) +#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) +#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) +#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) +#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) +#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) +#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) +#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) +#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) +#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) +#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) +#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) +#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) +#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) +#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) +#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) +#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) +#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) +#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) +#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) +#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) +#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) +#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) +#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) +#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) +#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) +#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) +#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) +#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) +#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) +#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) +#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) +#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) +#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) +#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) +#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) +#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) +#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) +#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) +#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) +#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) +#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) +#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) +#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) +#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) +#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) +#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) +#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) + +#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) +#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) +#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) +#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) +#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) +#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) +#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) +#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) +#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) +#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) +#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) +#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) +#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) +#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) +#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) +#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) +#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) +#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) +#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) +#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) +#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) +#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) +#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) +#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) +#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) +#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) +#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) +#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) +#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) +#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) +#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) +#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) +#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) +#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) +#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) +#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) +#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) +#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) +#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) +#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) +#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) +#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) +#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) +#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) +#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) +#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) +#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) +#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) +#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) +#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) +#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) +#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) +#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) +#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) + +#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) +#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) +#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) +#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) +#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) +#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) +#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) +#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) +#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) +#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) +#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) +#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) +#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) +#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) +#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) +#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) +#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) +#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) +#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) +#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) +#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) +#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) +#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) +#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) +#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) +#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) +#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) +#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) +#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) +#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) +#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) +#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) +#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) +#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) +#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) +#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) +#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) +#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) +#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) +#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) +#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) +#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) +#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) +#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) +#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) +#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) +#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) +#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) +#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) +#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) +#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) +#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) +#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) +#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) + +#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) +#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) +#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) +#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) +#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) +#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) +#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) +#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) +#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) +#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) +#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) +#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) +#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) +#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) +#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) +#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) +#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) +#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) +#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) +#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) +#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) +#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) +#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) +#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) +#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) +#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) +#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) +#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) +#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) +#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) +#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) +#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) +#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) +#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) +#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) +#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) +#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) +#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) +#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) +#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) +#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) +#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) +#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) +#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) +#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) +#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) +#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) +#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) +#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) +#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) +#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) +#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) +#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) +#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) + +#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) +#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) +#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) +#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) +#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) +#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) +#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) +#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) +#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) +#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) +#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) +#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) +#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) +#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) +#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) +#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) +#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) +#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) +#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) +#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) +#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) +#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) +#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) +#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) +#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) +#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) +#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) +#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) +#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) +#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) +#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) +#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) +#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) +#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) +#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) +#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) +#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) +#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) +#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) +#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) +#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) +#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) +#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) +#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) +#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) +#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) +#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) +#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) +#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) +#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) +#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) +#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) +#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) +#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) + + +/* Serial Peripheral Interface (TSPI) */ +#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) +#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) +#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) +#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) +#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) +#define TSB_TSPI0_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,16))) +#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) +#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) +#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) +#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) +#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) +#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) +#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) +#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) +#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) +#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) +#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) +#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) +#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) +#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) +#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) +#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) +#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) +#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) +#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) +#define TSB_TSPI0_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SECTCR0,0))) +#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) +#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) +#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) +#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) +#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) +#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) +#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) +#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) +#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) +#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) +#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) +#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) +#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) + +#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) +#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) +#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) +#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) +#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) +#define TSB_TSPI1_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,16))) +#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) +#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) +#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) +#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) +#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) +#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) +#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) +#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) +#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) +#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) +#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) +#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) +#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) +#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) +#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) +#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) +#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) +#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) +#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) +#define TSB_TSPI1_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SECTCR0,0))) +#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) +#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) +#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) +#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) +#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) +#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) +#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) +#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) +#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) +#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) +#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) +#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) +#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) + + +/* Asynchronous Serial Communication Circuit (UART) */ +#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) +#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) +#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) +#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) +#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) +#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) +#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) +#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) +#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) +#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) +#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) +#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) +#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) +#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) +#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) +#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) +#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) +#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) +#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) +#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) +#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) +#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) +#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) +#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) +#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) +#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) +#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) +#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) +#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) +#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) +#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) +#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) +#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) +#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) +#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) +#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) +#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) +#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) +#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) +#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) +#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) +#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) + +#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) +#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) +#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) +#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) +#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) +#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) +#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) +#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) +#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) +#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) +#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) +#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) +#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) +#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) +#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) +#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) +#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) +#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) +#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) +#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) +#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) +#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) +#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) +#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) +#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) +#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) +#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) +#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) +#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) +#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) +#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) +#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) +#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) +#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) +#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) +#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) +#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) +#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) +#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) +#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) +#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) +#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) + +#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) +#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) +#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) +#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) +#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) +#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) +#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) +#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) +#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) +#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) +#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) +#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) +#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) +#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) +#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) +#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) +#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) +#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) +#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) +#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) +#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) +#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) +#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) +#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) +#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) +#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) +#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) +#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) +#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) +#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) +#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) +#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) +#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) +#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) +#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) +#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) +#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) +#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) +#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) +#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) +#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) +#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) + +#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) +#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) +#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) +#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) +#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) +#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) +#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) +#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) +#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) +#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) +#define TSB_UART3_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,16))) +#define TSB_UART3_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,17))) +#define TSB_UART3_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,18))) +#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) +#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) +#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) +#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) +#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) +#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) +#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) +#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) +#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) +#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) +#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) +#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) +#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) +#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) +#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) +#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) +#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) +#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) +#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) +#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) +#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) +#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) +#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) +#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) +#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) +#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) +#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) +#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) +#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) + + +/* I2C Interface (I2C) */ +#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) +#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) +#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) +#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) +#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) +#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) +#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) +#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) +#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) +#define TSB_I2C0_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) +#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) +#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) +#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) +#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) +#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) +#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) +#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) +#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) +#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) +#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) +#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) +#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) +#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) +#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) +#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) +#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) +#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) +#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) +#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) +#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) +#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) +#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) +#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) +#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) +#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) +#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) +#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) +#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) + +#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) +#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) +#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) +#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) +#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) +#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) +#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) +#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) +#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) +#define TSB_I2C1_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) +#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) +#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) +#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) +#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) +#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) +#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) +#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) +#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) +#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) +#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) +#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) +#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) +#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) +#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) +#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) +#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) +#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) +#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) +#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) +#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) +#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) +#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) +#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) +#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) +#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) +#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) +#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) +#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) + + +/* I2C Interface Version A (EI2C) */ +#define TSB_EI2C0_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AEN,0))) +#define TSB_EI2C0_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,0))) +#define TSB_EI2C0_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,1))) +#define TSB_EI2C0_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,2))) +#define TSB_EI2C0_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,3))) +#define TSB_EI2C0_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,4))) +#define TSB_EI2C0_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,8))) +#define TSB_EI2C0_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,11))) +#define TSB_EI2C0_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,0))) +#define TSB_EI2C0_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,1))) +#define TSB_EI2C0_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,2))) +#define TSB_EI2C0_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,3))) +#define TSB_EI2C0_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,4))) +#define TSB_EI2C0_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,10))) +#define TSB_EI2C0_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,0))) +#define TSB_EI2C0_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,1))) +#define TSB_EI2C0_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,2))) +#define TSB_EI2C0_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,3))) +#define TSB_EI2C0_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,0))) +#define TSB_EI2C0_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,1))) +#define TSB_EI2C0_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,2))) +#define TSB_EI2C0_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,3))) +#define TSB_EI2C0_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,4))) +#define TSB_EI2C0_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,5))) +#define TSB_EI2C0_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,6))) +#define TSB_EI2C0_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,7))) +#define TSB_EI2C0_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,8))) +#define TSB_EI2C0_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,9))) +#define TSB_EI2C0_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,10))) +#define TSB_EI2C0_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,11))) +#define TSB_EI2C0_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,12))) +#define TSB_EI2C0_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,13))) +#define TSB_EI2C0_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR1,0))) +#define TSB_EI2C0_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR1,15))) +#define TSB_EI2C0_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR2,0))) +#define TSB_EI2C0_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR2,15))) +#define TSB_EI2C0_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,0))) +#define TSB_EI2C0_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,1))) +#define TSB_EI2C0_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,2))) +#define TSB_EI2C0_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,6))) +#define TSB_EI2C0_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,7))) +#define TSB_EI2C0_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,8))) +#define TSB_EI2C0_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,9))) +#define TSB_EI2C0_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,11))) +#define TSB_EI2C0_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,12))) +#define TSB_EI2C0_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,13))) +#define TSB_EI2C0_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,14))) +#define TSB_EI2C0_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,15))) +#define TSB_EI2C0_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,0))) +#define TSB_EI2C0_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,1))) +#define TSB_EI2C0_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,2))) +#define TSB_EI2C0_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,3))) + +#define TSB_EI2C1_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AEN,0))) +#define TSB_EI2C1_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,0))) +#define TSB_EI2C1_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,1))) +#define TSB_EI2C1_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,2))) +#define TSB_EI2C1_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,3))) +#define TSB_EI2C1_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,4))) +#define TSB_EI2C1_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,8))) +#define TSB_EI2C1_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,11))) +#define TSB_EI2C1_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,0))) +#define TSB_EI2C1_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,1))) +#define TSB_EI2C1_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,2))) +#define TSB_EI2C1_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,3))) +#define TSB_EI2C1_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,4))) +#define TSB_EI2C1_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,10))) +#define TSB_EI2C1_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,0))) +#define TSB_EI2C1_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,1))) +#define TSB_EI2C1_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,2))) +#define TSB_EI2C1_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,3))) +#define TSB_EI2C1_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,0))) +#define TSB_EI2C1_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,1))) +#define TSB_EI2C1_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,2))) +#define TSB_EI2C1_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,3))) +#define TSB_EI2C1_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,4))) +#define TSB_EI2C1_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,5))) +#define TSB_EI2C1_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,6))) +#define TSB_EI2C1_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,7))) +#define TSB_EI2C1_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,8))) +#define TSB_EI2C1_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,9))) +#define TSB_EI2C1_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,10))) +#define TSB_EI2C1_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,11))) +#define TSB_EI2C1_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,12))) +#define TSB_EI2C1_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,13))) +#define TSB_EI2C1_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR1,0))) +#define TSB_EI2C1_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR1,15))) +#define TSB_EI2C1_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR2,0))) +#define TSB_EI2C1_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR2,15))) +#define TSB_EI2C1_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,0))) +#define TSB_EI2C1_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,1))) +#define TSB_EI2C1_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,2))) +#define TSB_EI2C1_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,6))) +#define TSB_EI2C1_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,7))) +#define TSB_EI2C1_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,8))) +#define TSB_EI2C1_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,9))) +#define TSB_EI2C1_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,11))) +#define TSB_EI2C1_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,12))) +#define TSB_EI2C1_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,13))) +#define TSB_EI2C1_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,14))) +#define TSB_EI2C1_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,15))) +#define TSB_EI2C1_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,0))) +#define TSB_EI2C1_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,1))) +#define TSB_EI2C1_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,2))) +#define TSB_EI2C1_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,3))) + + +/* Port A */ +#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) +#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) +#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) +#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) +#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) +#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) +#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) +#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) +#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) +#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) +#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) +#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) +#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) +#define TSB_PA_FR1_PA3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,3))) +#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) +#define TSB_PA_FR4_PA0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,0))) +#define TSB_PA_FR4_PA1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,1))) +#define TSB_PA_FR4_PA2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,2))) +#define TSB_PA_FR4_PA3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,3))) +#define TSB_PA_FR4_PA4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,4))) +#define TSB_PA_FR5_PA2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,2))) +#define TSB_PA_FR5_PA3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,3))) +#define TSB_PA_FR6_PA2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,2))) +#define TSB_PA_FR7_PA2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,2))) +#define TSB_PA_FR7_PA3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,3))) +#define TSB_PA_FR7_PA4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,4))) +#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) +#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) +#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) +#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) +#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) +#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) +#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) +#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) +#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) +#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) +#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) +#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) +#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) +#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) +#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) +#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) +#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) +#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) +#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) +#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) + + +/* Port B */ +#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) +#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) +#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) +#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) +#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) +#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) +#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) +#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) +#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) +#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) +#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) +#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) +#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) +#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) +#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) +#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) +#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) +#define TSB_PB_FR4_PB1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,1))) +#define TSB_PB_FR4_PB2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,2))) +#define TSB_PB_FR4_PB3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,3))) +#define TSB_PB_FR4_PB4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,4))) +#define TSB_PB_FR4_PB5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,5))) +#define TSB_PB_FR4_PB6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,6))) +#define TSB_PB_FR4_PB7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,7))) +#define TSB_PB_FR5_PB7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,7))) +#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) +#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) +#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) +#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) +#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) +#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) +#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) +#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) +#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) +#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) +#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) +#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) +#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) +#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) +#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) +#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) +#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) +#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) +#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) +#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) +#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) +#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) +#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) +#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) +#define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0))) +#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) +#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) +#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) +#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) +#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) +#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) +#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) + + +/* Port C */ +#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) +#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) +#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) +#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) +#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) +#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) +#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) +#define TSB_PC_DATA_PC7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,7))) +#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) +#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) +#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) +#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) +#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) +#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) +#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) +#define TSB_PC_CR_PC7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,7))) +#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) +#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) +#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) +#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) +#define TSB_PC_FR2_PC0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,0))) +#define TSB_PC_FR2_PC1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,1))) +#define TSB_PC_FR2_PC4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,4))) +#define TSB_PC_FR2_PC5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,5))) +#define TSB_PC_FR3_PC0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,0))) +#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) +#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) +#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) +#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) +#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) +#define TSB_PC_FR3_PC6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,6))) +#define TSB_PC_FR3_PC7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,7))) +#define TSB_PC_FR4_PC0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,0))) +#define TSB_PC_FR4_PC1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,1))) +#define TSB_PC_FR5_PC0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,0))) +#define TSB_PC_FR5_PC1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,1))) +#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) +#define TSB_PC_FR5_PC3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,3))) +#define TSB_PC_FR5_PC6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,6))) +#define TSB_PC_FR5_PC7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,7))) +#define TSB_PC_FR6_PC0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR6,0))) +#define TSB_PC_FR6_PC1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR6,1))) +#define TSB_PC_FR6_PC2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR6,2))) +#define TSB_PC_FR6_PC6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR6,6))) +#define TSB_PC_FR7_PC2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR7,2))) +#define TSB_PC_FR7_PC3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR7,3))) +#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) +#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) +#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) +#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) +#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) +#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) +#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) +#define TSB_PC_OD_PC7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,7))) +#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) +#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) +#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) +#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) +#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) +#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) +#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) +#define TSB_PC_PUP_PC7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,7))) +#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) +#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) +#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) +#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) +#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) +#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) +#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) +#define TSB_PC_PDN_PC7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,7))) +#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) +#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) +#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) +#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) +#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) +#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) +#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) +#define TSB_PC_IE_PC7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,7))) + + +/* Port D */ +#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) +#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) +#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) +#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) +#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) +#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) +#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) +#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) +#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) +#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) +#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) +#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) +#define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2))) +#define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3))) +#define TSB_PD_FR2_PD3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,3))) +#define TSB_PD_FR2_PD4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,4))) +#define TSB_PD_FR3_PD3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,3))) +#define TSB_PD_FR3_PD4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,4))) +#define TSB_PD_FR4_PD0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,0))) +#define TSB_PD_FR4_PD1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,1))) +#define TSB_PD_FR4_PD2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,2))) +#define TSB_PD_FR4_PD3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,3))) +#define TSB_PD_FR4_PD4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,4))) +#define TSB_PD_FR4_PD5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,5))) +#define TSB_PD_FR5_PD2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,2))) +#define TSB_PD_FR5_PD3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,3))) +#define TSB_PD_FR6_PD3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,3))) +#define TSB_PD_FR6_PD4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,4))) +#define TSB_PD_FR6_PD5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,5))) +#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) +#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) +#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) +#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) +#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) +#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) +#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) +#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) +#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) +#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) +#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) +#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) +#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) +#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) +#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) +#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) +#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) +#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) +#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) +#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) +#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) +#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) +#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) +#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) + + +/* Port E */ +#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) +#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) +#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) +#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) +#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) +#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) +#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) +#define TSB_PE_DATA_PE7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,7))) +#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) +#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) +#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) +#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) +#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) +#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) +#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) +#define TSB_PE_CR_PE7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,7))) +#define TSB_PE_FR4_PE1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,1))) +#define TSB_PE_FR4_PE2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,2))) +#define TSB_PE_FR4_PE3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,3))) +#define TSB_PE_FR4_PE4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,4))) +#define TSB_PE_FR4_PE5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,5))) +#define TSB_PE_FR4_PE6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,6))) +#define TSB_PE_FR5_PE1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,1))) +#define TSB_PE_FR5_PE2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,2))) +#define TSB_PE_FR5_PE3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,3))) +#define TSB_PE_FR6_PE0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,0))) +#define TSB_PE_FR6_PE1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,1))) +#define TSB_PE_FR6_PE2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,2))) +#define TSB_PE_FR6_PE3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,3))) +#define TSB_PE_FR6_PE4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,4))) +#define TSB_PE_FR6_PE5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,5))) +#define TSB_PE_FR6_PE6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,6))) +#define TSB_PE_FR6_PE7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,7))) +#define TSB_PE_FR7_PE7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,7))) +#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) +#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) +#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) +#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) +#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) +#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) +#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) +#define TSB_PE_OD_PE7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,7))) +#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) +#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) +#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) +#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) +#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) +#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) +#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) +#define TSB_PE_PUP_PE7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,7))) +#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) +#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) +#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) +#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) +#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) +#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) +#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) +#define TSB_PE_PDN_PE7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,7))) +#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) +#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) +#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) +#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) +#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) +#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) +#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) +#define TSB_PE_IE_PE7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,7))) + + +/* Port F */ +#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) +#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) +#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) +#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) +#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) +#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) +#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) +#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) +#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) +#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) +#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) +#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) +#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) +#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) +#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) +#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) +#define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0))) +#define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1))) +#define TSB_PF_FR1_PF3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,3))) +#define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4))) +#define TSB_PF_FR1_PF6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,6))) +#define TSB_PF_FR1_PF7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,7))) +#define TSB_PF_FR2_PF0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,0))) +#define TSB_PF_FR2_PF1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,1))) +#define TSB_PF_FR2_PF3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,3))) +#define TSB_PF_FR2_PF4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,4))) +#define TSB_PF_FR2_PF6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,6))) +#define TSB_PF_FR2_PF7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,7))) +#define TSB_PF_FR3_PF4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,4))) +#define TSB_PF_FR3_PF5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,5))) +#define TSB_PF_FR3_PF6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,6))) +#define TSB_PF_FR3_PF7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,7))) +#define TSB_PF_FR4_PF0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,0))) +#define TSB_PF_FR4_PF1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,1))) +#define TSB_PF_FR4_PF2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,2))) +#define TSB_PF_FR4_PF3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,3))) +#define TSB_PF_FR4_PF4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,4))) +#define TSB_PF_FR4_PF5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,5))) +#define TSB_PF_FR4_PF6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,6))) +#define TSB_PF_FR4_PF7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,7))) +#define TSB_PF_FR5_PF0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,0))) +#define TSB_PF_FR5_PF1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,1))) +#define TSB_PF_FR5_PF2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,2))) +#define TSB_PF_FR5_PF3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,3))) +#define TSB_PF_FR5_PF4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,4))) +#define TSB_PF_FR5_PF5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,5))) +#define TSB_PF_FR6_PF3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,3))) +#define TSB_PF_FR6_PF4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,4))) +#define TSB_PF_FR6_PF5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,5))) +#define TSB_PF_FR7_PF0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,0))) +#define TSB_PF_FR7_PF1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,1))) +#define TSB_PF_FR7_PF2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,2))) +#define TSB_PF_FR7_PF3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,3))) +#define TSB_PF_FR7_PF4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,4))) +#define TSB_PF_FR7_PF5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,5))) +#define TSB_PF_FR7_PF6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,6))) +#define TSB_PF_FR7_PF7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,7))) +#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) +#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) +#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) +#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) +#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) +#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) +#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) +#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) +#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) +#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) +#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) +#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) +#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) +#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) +#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) +#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) +#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) +#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) +#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) +#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) +#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) +#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) +#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) +#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) +#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) +#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) +#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) +#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) +#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) +#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) +#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) +#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) + + +/* Port G */ +#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) +#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) +#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) +#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) +#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) +#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) +#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) +#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) +#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) +#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) +#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) +#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) +#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) +#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) +#define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1))) +#define TSB_PG_FR1_PG2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,2))) +#define TSB_PG_FR1_PG3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,3))) +#define TSB_PG_FR1_PG4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,4))) +#define TSB_PG_FR1_PG5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,5))) +#define TSB_PG_FR1_PG6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,6))) +#define TSB_PG_FR4_PG0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,0))) +#define TSB_PG_FR4_PG1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,1))) +#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) +#define TSB_PG_FR4_PG3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) +#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) +#define TSB_PG_FR4_PG5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,5))) +#define TSB_PG_FR5_PG0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,0))) +#define TSB_PG_FR5_PG1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,1))) +#define TSB_PG_FR5_PG2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,2))) +#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) +#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) +#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) +#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) +#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) +#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) +#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) +#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) +#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) +#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) +#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) +#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) +#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) +#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) +#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) +#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) +#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) +#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) +#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) +#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) +#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) +#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) +#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) +#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) +#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) +#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) +#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) +#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) + + +/* Port H */ +#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) +#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) +#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) +#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) +#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) +#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) + + +/* Port J */ +#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) +#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) +#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) +#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) +#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) +#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) +#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) +#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) +#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) +#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) +#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) +#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) +#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) +#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) +#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) +#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) +#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) +#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) +#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) +#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) +#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) +#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) +#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) +#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) +#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) +#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) +#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) +#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) +#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) +#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) +#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) +#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) +#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) +#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) +#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) +#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) + + +/* Port K */ +#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) +#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) +#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) +#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) +#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) +#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) +#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) +#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) +#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) +#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) +#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) +#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) +#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) +#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) +#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) +#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) +#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) +#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) +#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) +#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) +#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) +#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) +#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) +#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) +#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) +#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) +#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) +#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) +#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) +#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) + + +/* Port L */ +#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) +#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) +#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) +#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) +#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) +#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) +#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) +#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) +#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) +#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) +#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) +#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) +#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) +#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) +#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) +#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) +#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) +#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) +#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) +#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) +#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) +#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) +#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) +#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) +#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) +#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) +#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) +#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) +#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) +#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) +#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) +#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) +#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) +#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) +#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) +#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) +#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) +#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) +#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) +#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) +#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) +#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) +#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) +#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) +#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) +#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) +#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) +#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) + + +/* Port M */ +#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) +#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) +#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) +#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) +#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) +#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) +#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) +#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) +#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) +#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) +#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) +#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) +#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) +#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) +#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) +#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) +#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) +#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) + + +/* Port N */ +#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) +#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) +#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) +#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) +#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) +#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) +#define TSB_PN_FR1_PN0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,0))) +#define TSB_PN_FR1_PN1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,1))) +#define TSB_PN_FR1_PN2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,2))) +#define TSB_PN_FR2_PN0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,0))) +#define TSB_PN_FR2_PN1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,1))) +#define TSB_PN_FR3_PN0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,0))) +#define TSB_PN_FR3_PN1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,1))) +#define TSB_PN_FR4_PN0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,0))) +#define TSB_PN_FR4_PN1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,1))) +#define TSB_PN_FR4_PN2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,2))) +#define TSB_PN_FR5_PN0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,0))) +#define TSB_PN_FR5_PN1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,1))) +#define TSB_PN_FR5_PN2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,2))) +#define TSB_PN_FR6_PN0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR6,0))) +#define TSB_PN_FR6_PN1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR6,1))) +#define TSB_PN_FR6_PN2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR6,2))) +#define TSB_PN_FR7_PN0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR7,0))) +#define TSB_PN_FR7_PN1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR7,1))) +#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) +#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) +#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) +#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) +#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) +#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) +#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) +#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) +#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) +#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) +#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) +#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) + + +/* Port U */ +#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) +#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1))) +#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) +#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) +#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) +#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) +#define TSB_PU_DATA_PU6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,6))) +#define TSB_PU_DATA_PU7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,7))) +#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) +#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1))) +#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) +#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) +#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) +#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) +#define TSB_PU_CR_PU6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,6))) +#define TSB_PU_CR_PU7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,7))) +#define TSB_PU_FR1_PU0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,0))) +#define TSB_PU_FR1_PU1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,1))) +#define TSB_PU_FR1_PU3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,3))) +#define TSB_PU_FR1_PU4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,4))) +#define TSB_PU_FR1_PU5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,5))) +#define TSB_PU_FR1_PU6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,6))) +#define TSB_PU_FR2_PU0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,0))) +#define TSB_PU_FR2_PU1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,1))) +#define TSB_PU_FR2_PU5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,5))) +#define TSB_PU_FR2_PU6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,6))) +#define TSB_PU_FR3_PU0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,0))) +#define TSB_PU_FR3_PU1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,1))) +#define TSB_PU_FR4_PU0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,0))) +#define TSB_PU_FR4_PU1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,1))) +#define TSB_PU_FR4_PU2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,2))) +#define TSB_PU_FR4_PU3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,3))) +#define TSB_PU_FR4_PU4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,4))) +#define TSB_PU_FR4_PU5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,5))) +#define TSB_PU_FR5_PU1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,1))) +#define TSB_PU_FR5_PU2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,2))) +#define TSB_PU_FR5_PU3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,3))) +#define TSB_PU_FR5_PU4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,4))) +#define TSB_PU_FR5_PU5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,5))) +#define TSB_PU_FR5_PU6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,6))) +#define TSB_PU_FR6_PU0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,0))) +#define TSB_PU_FR6_PU1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,1))) +#define TSB_PU_FR6_PU2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,2))) +#define TSB_PU_FR6_PU3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,3))) +#define TSB_PU_FR6_PU4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,4))) +#define TSB_PU_FR6_PU5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,5))) +#define TSB_PU_FR6_PU6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,6))) +#define TSB_PU_FR6_PU7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,7))) +#define TSB_PU_FR7_PU0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,0))) +#define TSB_PU_FR7_PU1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,1))) +#define TSB_PU_FR7_PU7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,7))) +#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) +#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1))) +#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) +#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) +#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) +#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) +#define TSB_PU_OD_PU6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,6))) +#define TSB_PU_OD_PU7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,7))) +#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) +#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1))) +#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) +#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) +#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) +#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) +#define TSB_PU_PUP_PU6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,6))) +#define TSB_PU_PUP_PU7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,7))) +#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) +#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1))) +#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) +#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) +#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) +#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) +#define TSB_PU_PDN_PU6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,6))) +#define TSB_PU_PDN_PU7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,7))) +#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) +#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1))) +#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) +#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) +#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) +#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) +#define TSB_PU_IE_PU6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,6))) +#define TSB_PU_IE_PU7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,7))) + + +/* Port V */ +#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) +#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) +#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) +#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) +#define TSB_PV_FR1_PV1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,1))) +#define TSB_PV_FR2_PV0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,0))) +#define TSB_PV_FR2_PV1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,1))) +#define TSB_PV_FR4_PV0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,0))) +#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) +#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) +#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) +#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) +#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) +#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) +#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) +#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) + + +/* Trimming Circuit (TRM) */ +#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) + + +/* Oscillation Frequency Detector (OFD) */ +#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) +#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) +#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) +#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) + + +/* Advanced Programmable Motor Control Circuit (A-PMD) */ +#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) +#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) +#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) +#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) +#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) +#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) +#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) +#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) +#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) +#define TSB_PMD0_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,0))) +#define TSB_PMD0_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,1))) +#define TSB_PMD0_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,2))) +#define TSB_PMD0_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,3))) +#define TSB_PMD0_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,7))) +#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) +#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) +#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) +#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) +#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) +#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) +#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) +#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) +#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) +#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) +#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) +#define TSB_PMD0_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,14))) +#define TSB_PMD0_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,15))) +#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) +#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) +#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) +#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) +#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) +#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) +#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) +#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) +#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) +#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) +#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) +#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) +#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) +#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) +#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) +#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) +#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) +#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) +#define TSB_PMD0_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->SYNCCR,0))) +#define TSB_PMD0_DBGOUTCR_DBGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,0))) +#define TSB_PMD0_DBGOUTCR_IADAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,3))) +#define TSB_PMD0_DBGOUTCR_IADBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,4))) +#define TSB_PMD0_DBGOUTCR_IADCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,5))) +#define TSB_PMD0_DBGOUTCR_IADDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,6))) +#define TSB_PMD0_DBGOUTCR_IADEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,7))) +#define TSB_PMD0_DBGOUTCR_IPMDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,8))) +#define TSB_PMD0_DBGOUTCR_IEMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,9))) +#define TSB_PMD0_DBGOUTCR_IOVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,10))) +#define TSB_PMD0_DBGOUTCR_IVEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,11))) +#define TSB_PMD0_DBGOUTCR_IENCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,12))) +#define TSB_PMD0_DBGOUTCR_TRG0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,16))) +#define TSB_PMD0_DBGOUTCR_TRG1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,17))) +#define TSB_PMD0_DBGOUTCR_TRG2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,18))) +#define TSB_PMD0_DBGOUTCR_TRG3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,19))) +#define TSB_PMD0_DBGOUTCR_TRG4EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,20))) +#define TSB_PMD0_DBGOUTCR_TRG5EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,21))) +#define TSB_PMD0_DBGOUTCR_INIFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,31))) + +#define TSB_PMD1_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDEN,0))) +#define TSB_PMD1_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDCR,3))) +#define TSB_PMD1_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDCR,4))) +#define TSB_PMD1_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDCR,5))) +#define TSB_PMD1_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDCR,6))) +#define TSB_PMD1_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDCR,7))) +#define TSB_PMD1_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->CARSTA,0))) +#define TSB_PMD1_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->CARSTA,1))) +#define TSB_PMD1_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->CARSTA,2))) +#define TSB_PMD1_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MODESEL,0))) +#define TSB_PMD1_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MODESEL,1))) +#define TSB_PMD1_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MODESEL,2))) +#define TSB_PMD1_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MODESEL,3))) +#define TSB_PMD1_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MODESEL,7))) +#define TSB_PMD1_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDOUT,8))) +#define TSB_PMD1_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDOUT,9))) +#define TSB_PMD1_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDOUT,10))) +#define TSB_PMD1_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDPOT,2))) +#define TSB_PMD1_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDPOT,3))) +#define TSB_PMD1_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,0))) +#define TSB_PMD1_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,1))) +#define TSB_PMD1_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,2))) +#define TSB_PMD1_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,5))) +#define TSB_PMD1_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,7))) +#define TSB_PMD1_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,13))) +#define TSB_PMD1_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,14))) +#define TSB_PMD1_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,15))) +#define TSB_PMD1_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGSTA,0))) +#define TSB_PMD1_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGSTA,1))) +#define TSB_PMD1_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,0))) +#define TSB_PMD1_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,1))) +#define TSB_PMD1_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,2))) +#define TSB_PMD1_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,5))) +#define TSB_PMD1_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,6))) +#define TSB_PMD1_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,7))) +#define TSB_PMD1_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,15))) +#define TSB_PMD1_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVSTA,0))) +#define TSB_PMD1_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVSTA,1))) +#define TSB_PMD1_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGCR,3))) +#define TSB_PMD1_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGCR,7))) +#define TSB_PMD1_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGCR,11))) +#define TSB_PMD1_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGCR,15))) +#define TSB_PMD1_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGCR,16))) +#define TSB_PMD1_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGMD,0))) +#define TSB_PMD1_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGMD,1))) +#define TSB_PMD1_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->SYNCCR,0))) +#define TSB_PMD1_DBGOUTCR_DBGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,0))) +#define TSB_PMD1_DBGOUTCR_IADAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,3))) +#define TSB_PMD1_DBGOUTCR_IADBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,4))) +#define TSB_PMD1_DBGOUTCR_IADCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,5))) +#define TSB_PMD1_DBGOUTCR_IADDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,6))) +#define TSB_PMD1_DBGOUTCR_IADEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,7))) +#define TSB_PMD1_DBGOUTCR_IPMDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,8))) +#define TSB_PMD1_DBGOUTCR_IEMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,9))) +#define TSB_PMD1_DBGOUTCR_IOVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,10))) +#define TSB_PMD1_DBGOUTCR_IVEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,11))) +#define TSB_PMD1_DBGOUTCR_IENCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,12))) +#define TSB_PMD1_DBGOUTCR_TRG0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,16))) +#define TSB_PMD1_DBGOUTCR_TRG1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,17))) +#define TSB_PMD1_DBGOUTCR_TRG2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,18))) +#define TSB_PMD1_DBGOUTCR_TRG3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,19))) +#define TSB_PMD1_DBGOUTCR_TRG4EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,20))) +#define TSB_PMD1_DBGOUTCR_TRG5EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,21))) +#define TSB_PMD1_DBGOUTCR_INIFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,31))) + +#define TSB_PMD2_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDEN,0))) +#define TSB_PMD2_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDCR,3))) +#define TSB_PMD2_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDCR,4))) +#define TSB_PMD2_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDCR,5))) +#define TSB_PMD2_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDCR,6))) +#define TSB_PMD2_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDCR,7))) +#define TSB_PMD2_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->CARSTA,0))) +#define TSB_PMD2_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->CARSTA,1))) +#define TSB_PMD2_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->CARSTA,2))) +#define TSB_PMD2_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MODESEL,0))) +#define TSB_PMD2_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MODESEL,1))) +#define TSB_PMD2_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MODESEL,2))) +#define TSB_PMD2_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MODESEL,3))) +#define TSB_PMD2_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MODESEL,7))) +#define TSB_PMD2_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDOUT,8))) +#define TSB_PMD2_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDOUT,9))) +#define TSB_PMD2_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDOUT,10))) +#define TSB_PMD2_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDPOT,2))) +#define TSB_PMD2_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDPOT,3))) +#define TSB_PMD2_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,0))) +#define TSB_PMD2_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,1))) +#define TSB_PMD2_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,2))) +#define TSB_PMD2_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,5))) +#define TSB_PMD2_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,7))) +#define TSB_PMD2_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,13))) +#define TSB_PMD2_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,14))) +#define TSB_PMD2_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,15))) +#define TSB_PMD2_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGSTA,0))) +#define TSB_PMD2_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGSTA,1))) +#define TSB_PMD2_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,0))) +#define TSB_PMD2_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,1))) +#define TSB_PMD2_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,2))) +#define TSB_PMD2_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,5))) +#define TSB_PMD2_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,6))) +#define TSB_PMD2_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,7))) +#define TSB_PMD2_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,15))) +#define TSB_PMD2_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVSTA,0))) +#define TSB_PMD2_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVSTA,1))) +#define TSB_PMD2_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGCR,3))) +#define TSB_PMD2_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGCR,7))) +#define TSB_PMD2_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGCR,11))) +#define TSB_PMD2_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGCR,15))) +#define TSB_PMD2_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGCR,16))) +#define TSB_PMD2_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGMD,0))) +#define TSB_PMD2_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGMD,1))) +#define TSB_PMD2_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->SYNCCR,0))) +#define TSB_PMD2_DBGOUTCR_DBGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,0))) +#define TSB_PMD2_DBGOUTCR_IADAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,3))) +#define TSB_PMD2_DBGOUTCR_IADBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,4))) +#define TSB_PMD2_DBGOUTCR_IADCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,5))) +#define TSB_PMD2_DBGOUTCR_IADDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,6))) +#define TSB_PMD2_DBGOUTCR_IADEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,7))) +#define TSB_PMD2_DBGOUTCR_IPMDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,8))) +#define TSB_PMD2_DBGOUTCR_IEMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,9))) +#define TSB_PMD2_DBGOUTCR_IOVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,10))) +#define TSB_PMD2_DBGOUTCR_IVEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,11))) +#define TSB_PMD2_DBGOUTCR_IENCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,12))) +#define TSB_PMD2_DBGOUTCR_TRG0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,16))) +#define TSB_PMD2_DBGOUTCR_TRG1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,17))) +#define TSB_PMD2_DBGOUTCR_TRG2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,18))) +#define TSB_PMD2_DBGOUTCR_TRG3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,19))) +#define TSB_PMD2_DBGOUTCR_TRG4EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,20))) +#define TSB_PMD2_DBGOUTCR_TRG5EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,21))) +#define TSB_PMD2_DBGOUTCR_INIFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,31))) + + +/* Advanced Encoder Input (A-ENC32) */ +#define TSB_EN0_TNCR_ZEACT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,5))) +#define TSB_EN0_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,6))) +#define TSB_EN0_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,7))) +#define TSB_EN0_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,10))) +#define TSB_EN0_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,11))) +#define TSB_EN0_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,12))) +#define TSB_EN0_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,16))) +#define TSB_EN0_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,21))) +#define TSB_EN0_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,24))) +#define TSB_EN0_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,25))) +#define TSB_EN0_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,28))) +#define TSB_EN0_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,0))) +#define TSB_EN0_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,1))) +#define TSB_EN0_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,2))) +#define TSB_EN0_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,12))) +#define TSB_EN0_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,13))) +#define TSB_EN0_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,14))) +#define TSB_EN0_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,0))) +#define TSB_EN0_INPCR_SYNCSPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,1))) +#define TSB_EN0_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,2))) +#define TSB_EN0_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,6))) +#define TSB_EN0_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,7))) +#define TSB_EN0_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,0))) +#define TSB_EN0_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,1))) +#define TSB_EN0_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,2))) +#define TSB_EN0_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,4))) +#define TSB_EN0_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,5))) +#define TSB_EN0_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,6))) +#define TSB_EN0_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,0))) +#define TSB_EN0_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,1))) +#define TSB_EN0_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,2))) +#define TSB_EN0_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,3))) +#define TSB_EN0_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,4))) +#define TSB_EN0_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,5))) +#define TSB_EN0_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,0))) +#define TSB_EN0_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,1))) +#define TSB_EN0_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,2))) +#define TSB_EN0_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,3))) +#define TSB_EN0_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,4))) +#define TSB_EN0_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,5))) + +#define TSB_EN1_TNCR_ZEACT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,5))) +#define TSB_EN1_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,6))) +#define TSB_EN1_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,7))) +#define TSB_EN1_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,10))) +#define TSB_EN1_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,11))) +#define TSB_EN1_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,12))) +#define TSB_EN1_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,16))) +#define TSB_EN1_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,21))) +#define TSB_EN1_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,24))) +#define TSB_EN1_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,25))) +#define TSB_EN1_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,28))) +#define TSB_EN1_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,0))) +#define TSB_EN1_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,1))) +#define TSB_EN1_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,2))) +#define TSB_EN1_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,12))) +#define TSB_EN1_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,13))) +#define TSB_EN1_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,14))) +#define TSB_EN1_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INPCR,0))) +#define TSB_EN1_INPCR_SYNCSPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INPCR,1))) +#define TSB_EN1_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INPCR,2))) +#define TSB_EN1_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN1->INPCR,6))) +#define TSB_EN1_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN1->INPCR,7))) +#define TSB_EN1_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,0))) +#define TSB_EN1_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,1))) +#define TSB_EN1_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,2))) +#define TSB_EN1_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,4))) +#define TSB_EN1_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,5))) +#define TSB_EN1_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,6))) +#define TSB_EN1_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,0))) +#define TSB_EN1_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,1))) +#define TSB_EN1_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,2))) +#define TSB_EN1_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,3))) +#define TSB_EN1_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,4))) +#define TSB_EN1_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,5))) +#define TSB_EN1_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,0))) +#define TSB_EN1_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,1))) +#define TSB_EN1_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,2))) +#define TSB_EN1_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,3))) +#define TSB_EN1_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,4))) +#define TSB_EN1_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,5))) + +#define TSB_EN2_TNCR_ZEACT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,5))) +#define TSB_EN2_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,6))) +#define TSB_EN2_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,7))) +#define TSB_EN2_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,10))) +#define TSB_EN2_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,11))) +#define TSB_EN2_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,12))) +#define TSB_EN2_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,16))) +#define TSB_EN2_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,21))) +#define TSB_EN2_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,24))) +#define TSB_EN2_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,25))) +#define TSB_EN2_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,28))) +#define TSB_EN2_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,0))) +#define TSB_EN2_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,1))) +#define TSB_EN2_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,2))) +#define TSB_EN2_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,12))) +#define TSB_EN2_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,13))) +#define TSB_EN2_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,14))) +#define TSB_EN2_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INPCR,0))) +#define TSB_EN2_INPCR_SYNCSPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INPCR,1))) +#define TSB_EN2_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INPCR,2))) +#define TSB_EN2_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN2->INPCR,6))) +#define TSB_EN2_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN2->INPCR,7))) +#define TSB_EN2_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,0))) +#define TSB_EN2_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,1))) +#define TSB_EN2_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,2))) +#define TSB_EN2_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,4))) +#define TSB_EN2_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,5))) +#define TSB_EN2_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,6))) +#define TSB_EN2_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,0))) +#define TSB_EN2_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,1))) +#define TSB_EN2_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,2))) +#define TSB_EN2_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,3))) +#define TSB_EN2_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,4))) +#define TSB_EN2_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,5))) +#define TSB_EN2_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,0))) +#define TSB_EN2_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,1))) +#define TSB_EN2_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,2))) +#define TSB_EN2_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,3))) +#define TSB_EN2_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,4))) +#define TSB_EN2_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,5))) + + +/* Advanced Vector Engine Plus (A-VE+) */ +#define TSB_VE0_EN_VEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->EN,0))) +#define TSB_VE0_ERRINTEN_VERREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->ERRINTEN,0))) +#define TSB_VE0_ERRINTEN_INTTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->ERRINTEN,2))) +#define TSB_VE0_SCHTASKRUN_VRSCH (*((__I uint32_t *)BITBAND_PERI(&TSB_VE0->SCHTASKRUN,0))) +#define TSB_VE0_MCTLF_LAVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,0))) +#define TSB_VE0_MCTLF_LAVFM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,1))) +#define TSB_VE0_MCTLF_LVTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,2))) +#define TSB_VE0_MCTLF_PLSLF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,4))) +#define TSB_VE0_MCTLF_PLSLFM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,5))) +#define TSB_VE0_MCTLF_PIDOVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,8))) +#define TSB_VE0_MCTLF_PIQOVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,9))) +#define TSB_VE0_MCTLF_VSOVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,10))) +#define TSB_VE0_MCTLF_PWMOVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,11))) +#define TSB_VE0_MCTLF_SFT2ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,14))) +#define TSB_VE0_MCTLF_SFT2STM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,15))) +#define TSB_VE0_MODE_PVIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,0))) +#define TSB_VE0_MODE_ZIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,1))) +#define TSB_VE0_MODE_VDCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,4))) +#define TSB_VE0_MODE_CLPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,7))) +#define TSB_VE0_MODE_T5ECEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,10))) +#define TSB_VE0_MODE_NICEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,11))) +#define TSB_VE0_MODE_PWMBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,12))) +#define TSB_VE0_MODE_PWMFLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,13))) +#define TSB_VE0_MODE_PMDDTCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,14))) +#define TSB_VE0_MODE_IPDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,15))) +#define TSB_VE0_FMODE_C2PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,0))) +#define TSB_VE0_FMODE_SPWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,1))) +#define TSB_VE0_FMODE_IDQSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,4))) +#define TSB_VE0_FMODE_IAPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,5))) +#define TSB_VE0_FMODE_IBPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,6))) +#define TSB_VE0_FMODE_ICPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,7))) +#define TSB_VE0_FMODE_CRCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,8))) +#define TSB_VE0_FMODE_MREGDIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,9))) +#define TSB_VE0_FMODE_PHCVDIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,12))) +#define TSB_VE0_FMODE_CCVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,13))) +#define TSB_VE0_OUTCR_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->OUTCR,6))) +#define TSB_VE0_OUTCR_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->OUTCR,7))) +#define TSB_VE0_OUTCR_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->OUTCR,8))) + +/** @} */ /* End of group Device_Peripheral_registers */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TMPM4KNA_H__ */ + +/** @} */ /* End of group TMPM4KNA */ +/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/startup_TMPM4KNA.S b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/startup_TMPM4KNA.S new file mode 100644 index 00000000000..7e9e346e649 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/startup_TMPM4KNA.S @@ -0,0 +1,484 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM4KNA.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for the +; * TOSHIBA 'TMPM4KNA' Device Series +; * @version V1.0.0.0 +; * $Date:: #$ +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 +; ******************************************************************************* +; */ + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt pin 00 + DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b + DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b + DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b + DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b + DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b + DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b + DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b + DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b + DCD INT09_IRQHandler ; 9: Interrupt pin 09 + DCD INT10_IRQHandler ; 10: Interrupt pin 10 + DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b + DCD INT12_IRQHandler ; 12: Interrupt pin 12 + DCD INT13_IRQHandler ; 13: Interrupt pin 13 + DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b + DCD INT15_IRQHandler ; 15: Interrupt pin 15 + DCD INT16_IRQHandler ; 16: Interrupt pin 16a/16b + DCD INT17_IRQHandler ; 17: Interrupt pin 17a/17b + DCD INT18_IRQHandler ; 18: Interrupt pin 18a/18b + DCD 0 ; 19: Reserved + DCD 0 ; 20: Reserved + DCD INT21_IRQHandler ; 21: Interrupt pin 21 + DCD INTVCN0_IRQHandler ; 22: A-VE+ ch0 Interrupt + DCD INTVCT0_IRQHandler ; 23: A-VE+ ch0 Task termination interrupt + DCD INTEMG0_IRQHandler ; 24: A-PMD ch0 EMG interrupt + DCD INTEMG1_IRQHandler ; 25: A-PMD ch1 EMG interrupt + DCD INTEMG2_IRQHandler ; 26: A-PMD ch2 EMG interrupt + DCD INTOVV0_IRQHandler ; 27: A-PMD ch0 OVV interrupt + DCD INTOVV1_IRQHandler ; 28: A-PMD ch1 OVV interrupt + DCD INTOVV2_IRQHandler ; 29: A-PMD ch2 OVV interrupt + DCD INTPWM0_IRQHandler ; 30: A-PMD ch0 PWM interrupt + DCD INTPWM1_IRQHandler ; 31: A-PMD ch1 PWM interrupt + DCD INTPWM2_IRQHandler ; 32: A-PMD ch2 PWM interrupt + DCD INTENC00_IRQHandler ; 33: A-ENC32 ch0 Encoder interrupt 0 + DCD INTENC01_IRQHandler ; 34: A-ENC32 ch0 Encoder interrupt 1 + DCD INTENC10_IRQHandler ; 35: A-ENC32 ch1 Encoder interrupt 0 + DCD INTENC11_IRQHandler ; 36: A-ENC32 ch1 Encoder interrupt 1 + DCD INTENC20_IRQHandler ; 37: A-ENC32 ch2 Encoder interrupt 0 + DCD INTENC21_IRQHandler ; 38: A-ENC32 ch2 Encoder interrupt 1 + DCD INTADAPDA_IRQHandler ; 39: ADC unit A PMD trigger program interrupt A + DCD INTADAPDB_IRQHandler ; 40: ADC unit A PMD trigger program interrupt B + DCD INTADACP0_IRQHandler ; 41: ADC unit A Monitor function 0 interrupt + DCD INTADACP1_IRQHandler ; 42: ADC unit A Monitor function 1 interrupt + DCD INTADATRG_IRQHandler ; 43: ADC unit A General purpose trigger program interrupt + DCD INTADASGL_IRQHandler ; 44: ADC unit A Single program interrupt + DCD INTADACNT_IRQHandler ; 45: ADC unit A Continuity program interrupt + DCD INTADBPDA_IRQHandler ; 46: ADC unit B PMD trigger program interrupt A + DCD INTADBPDB_IRQHandler ; 47: ADC unit B PMD trigger program interrupt B + DCD INTADBCP0_IRQHandler ; 48: ADC unit B Monitor function 0 interrupt + DCD INTADBCP1_IRQHandler ; 49: ADC unit B Monitor function 1 interrupt + DCD INTADBTRG_IRQHandler ; 50: ADC unit B General purpose trigger program interrupt + DCD INTADBSGL_IRQHandler ; 51: ADC unit B Single program interrupt + DCD INTADBCNT_IRQHandler ; 52: ADC unit B Continuity program interrupt + DCD INTADCPDA_IRQHandler ; 53: ADC unit C PMD trigger program interrupt A + DCD INTADCPDB_IRQHandler ; 54: ADC unit C PMD trigger program interrupt B + DCD INTADCCP0_IRQHandler ; 55: ADC unit C Monitor function 0 interrupt + DCD INTADCCP1_IRQHandler ; 56: ADC unit C Monitor function 1 interrupt + DCD INTADCTRG_IRQHandler ; 57: ADC unit C General purpose trigger program interrupt + DCD INTADCSGL_IRQHandler ; 58: ADC unit C Single program interrupt + DCD INTADCCNT_IRQHandler ; 59: ADC unit C Continuity program interrupt + DCD INTSC0RX_IRQHandler ; 60: TSPI/UART ch0 Reception interrupt + DCD INTSC0TX_IRQHandler ; 61: TSPI/UART ch0 Transmit interrupt + DCD INTSC0ERR_IRQHandler ; 62: TSPI/UART ch0 Error interrupt + DCD INTSC1RX_IRQHandler ; 63: TSPI/UART ch1 Reception interrupt + DCD INTSC1TX_IRQHandler ; 64: TSPI/UART ch1 Transmit interrupt + DCD INTSC1ERR_IRQHandler ; 65: TSPI/UART ch1 Error interrupt + DCD INTSC2RX_IRQHandler ; 66: UART ch2 Reception interrupt + DCD INTSC2TX_IRQHandler ; 67: UART ch2 Transmit interrupt + DCD INTSC2ERR_IRQHandler ; 68: UART ch2 Error interrupt + DCD INTSC3RX_IRQHandler ; 69: UART ch3 Reception interrupt + DCD INTSC3TX_IRQHandler ; 70: UART ch3 Transmit interrupt + DCD INTSC3ERR_IRQHandler ; 71: UART ch3 Error interrupt + DCD INTI2C0NST_IRQHandler ; 72: I2C ch0 Interrupt / EI2C ch0 Status interrupt + DCD INTI2C0ATX_IRQHandler ; 73: I2C ch0 Arbitration lost detection interrupt / EI2C ch0 Transmission buffer empty interrupt + DCD INTI2C0BRX_IRQHandler ; 74: I2C ch0 Bus free detection interrupt / EI2C ch0 Reception buffer full interrupt + DCD INTI2C0NA_IRQHandler ; 75: I2C ch0 NACK detection interrupt + DCD INTI2C1NST_IRQHandler ; 76: I2C ch1 Interrupt / EI2C ch1 Status interrupt + DCD INTI2C1ATX_IRQHandler ; 77: I2C ch1 Arbitration lost detection interrupt / EI2C ch1 Transmission buffer empty interrupt + DCD INTI2C1BRX_IRQHandler ; 78: I2C ch1 Bus free detection interrupt / EI2C ch1 Reception buffer full interrupt + DCD INTI2C1NA_IRQHandler ; 79: I2C ch1 NACK detection interrupt + DCD 0 ; 80: Reserved + DCD 0 ; 81: Reserved + DCD 0 ; 82: Reserved + DCD INTT32A00AC_IRQHandler ; 83: T32A ch0 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A00ACCAP0_IRQHandler; 84: T32A ch0 Timer A/C Input capture 0 + DCD INTT32A00ACCAP1_IRQHandler; 85: T32A ch0 Timer A/C Input capture 1 + DCD INTT32A00B_IRQHandler ; 86: T32A ch0 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A00BCAP0_IRQHandler ; 87: T32A ch0 Timer B Input capture 0 + DCD INTT32A00BCAP1_IRQHandler ; 88: T32A ch0 Timer B Input capture 1 + DCD INTT32A01AC_IRQHandler ; 89: T32A ch1 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A01ACCAP0_IRQHandler; 90: T32A ch1 Timer A/C Input capture 0 + DCD INTT32A01ACCAP1_IRQHandler; 91: T32A ch1 Timer A/C Input capture 1 + DCD INTT32A01B_IRQHandler ; 92: T32A ch1 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A01BCAP0_IRQHandler ; 93: T32A ch1 Timer B Input capture 0 + DCD INTT32A01BCAP1_IRQHandler ; 94: T32A ch1 Timer B Input capture 1 + DCD INTT32A02AC_IRQHandler ; 95: T32A ch2 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A02ACCAP0_IRQHandler; 96: T32A ch2 Timer A/C Input capture 0 + DCD INTT32A02ACCAP1_IRQHandler; 97: T32A ch2 Timer A/C Input capture 1 + DCD INTT32A02B_IRQHandler ; 98: T32A ch2 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A02BCAP0_IRQHandler ; 99: T32A ch2 Timer B Input capture 0 + DCD INTT32A02BCAP1_IRQHandler ; 100: T32A ch2 Timer B Input capture 1 + DCD INTT32A03AC_IRQHandler ; 101: T32A ch3 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A03ACCAP0_IRQHandler; 102: T32A ch3 Timer A/C Input capture 0 + DCD INTT32A03ACCAP1_IRQHandler; 103: T32A ch3 Timer A/C Input capture 1 + DCD INTT32A03B_IRQHandler ; 104: T32A ch3 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A03BCAP0_IRQHandler ; 105: T32A ch3 Timer B Input capture 0 + DCD INTT32A03BCAP1_IRQHandler ; 106: T32A ch3 Timer B Input capture 1 + DCD INTT32A04AC_IRQHandler ; 107: T32A ch4 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A04ACCAP0_IRQHandler; 108: T32A ch4 Timer A/C Input capture 0 + DCD INTT32A04ACCAP1_IRQHandler; 109: T32A ch4 Timer A/C Input capture 1 + DCD INTT32A04B_IRQHandler ; 110: T32A ch4 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A04BCAP0_IRQHandler ; 111: T32A ch4 Timer B Input capture 0 + DCD INTT32A04BCAP1_IRQHandler ; 112: T32A ch4 Timer B Input capture 1 + DCD INTT32A05AC_IRQHandler ; 113: T32A ch5 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A05ACCAP0_IRQHandler; 114: T32A ch5 Timer A/C Input capture 0 + DCD INTT32A05ACCAP1_IRQHandler; 115: T32A ch5 Timer A/C Input capture 1 + DCD INTT32A05B_IRQHandler ; 116: T32A ch5 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A05BCAP0_IRQHandler ; 117: T32A ch5 Timer B Input capture 0 + DCD INTT32A05BCAP1_IRQHandler ; 118: T32A ch5 Timer B Input capture 1 + DCD INTPARI0_IRQHandler ; 119: RAMP ch0 Parity error interrupt + DCD INTPARI1_IRQHandler ; 120: RAMP ch1 Parity error interrupt + DCD INTDMAATC_IRQHandler ; 121: DMAC unit A End of transfer (ch0 - 31) + DCD INTDMAAERR_IRQHandler ; 122: DMAC unit A Transfer error + DCD INTFLCRDY_IRQHandler ; 123: Code FLASH Ready interrupt + DCD INTFLDRDY_IRQHandler ; 124: Data FLASH Ready interrupt + + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT INT00_IRQHandler [WEAK] + EXPORT INT01_IRQHandler [WEAK] + EXPORT INT02_IRQHandler [WEAK] + EXPORT INT03_IRQHandler [WEAK] + EXPORT INT04_IRQHandler [WEAK] + EXPORT INT05_IRQHandler [WEAK] + EXPORT INT06_IRQHandler [WEAK] + EXPORT INT07_IRQHandler [WEAK] + EXPORT INT08_IRQHandler [WEAK] + EXPORT INT09_IRQHandler [WEAK] + EXPORT INT10_IRQHandler [WEAK] + EXPORT INT11_IRQHandler [WEAK] + EXPORT INT12_IRQHandler [WEAK] + EXPORT INT13_IRQHandler [WEAK] + EXPORT INT14_IRQHandler [WEAK] + EXPORT INT15_IRQHandler [WEAK] + EXPORT INT16_IRQHandler [WEAK] + EXPORT INT17_IRQHandler [WEAK] + EXPORT INT18_IRQHandler [WEAK] + EXPORT INT21_IRQHandler [WEAK] + EXPORT INTVCN0_IRQHandler [WEAK] + EXPORT INTVCT0_IRQHandler [WEAK] + EXPORT INTEMG0_IRQHandler [WEAK] + EXPORT INTEMG1_IRQHandler [WEAK] + EXPORT INTEMG2_IRQHandler [WEAK] + EXPORT INTOVV0_IRQHandler [WEAK] + EXPORT INTOVV1_IRQHandler [WEAK] + EXPORT INTOVV2_IRQHandler [WEAK] + EXPORT INTPWM0_IRQHandler [WEAK] + EXPORT INTPWM1_IRQHandler [WEAK] + EXPORT INTPWM2_IRQHandler [WEAK] + EXPORT INTENC00_IRQHandler [WEAK] + EXPORT INTENC01_IRQHandler [WEAK] + EXPORT INTENC10_IRQHandler [WEAK] + EXPORT INTENC11_IRQHandler [WEAK] + EXPORT INTENC20_IRQHandler [WEAK] + EXPORT INTENC21_IRQHandler [WEAK] + EXPORT INTADAPDA_IRQHandler [WEAK] + EXPORT INTADAPDB_IRQHandler [WEAK] + EXPORT INTADACP0_IRQHandler [WEAK] + EXPORT INTADACP1_IRQHandler [WEAK] + EXPORT INTADATRG_IRQHandler [WEAK] + EXPORT INTADASGL_IRQHandler [WEAK] + EXPORT INTADACNT_IRQHandler [WEAK] + EXPORT INTADBPDA_IRQHandler [WEAK] + EXPORT INTADBPDB_IRQHandler [WEAK] + EXPORT INTADBCP0_IRQHandler [WEAK] + EXPORT INTADBCP1_IRQHandler [WEAK] + EXPORT INTADBTRG_IRQHandler [WEAK] + EXPORT INTADBSGL_IRQHandler [WEAK] + EXPORT INTADBCNT_IRQHandler [WEAK] + EXPORT INTADCPDA_IRQHandler [WEAK] + EXPORT INTADCPDB_IRQHandler [WEAK] + EXPORT INTADCCP0_IRQHandler [WEAK] + EXPORT INTADCCP1_IRQHandler [WEAK] + EXPORT INTADCTRG_IRQHandler [WEAK] + EXPORT INTADCSGL_IRQHandler [WEAK] + EXPORT INTADCCNT_IRQHandler [WEAK] + EXPORT INTSC0RX_IRQHandler [WEAK] + EXPORT INTSC0TX_IRQHandler [WEAK] + EXPORT INTSC0ERR_IRQHandler [WEAK] + EXPORT INTSC1RX_IRQHandler [WEAK] + EXPORT INTSC1TX_IRQHandler [WEAK] + EXPORT INTSC1ERR_IRQHandler [WEAK] + EXPORT INTSC2RX_IRQHandler [WEAK] + EXPORT INTSC2TX_IRQHandler [WEAK] + EXPORT INTSC2ERR_IRQHandler [WEAK] + EXPORT INTSC3RX_IRQHandler [WEAK] + EXPORT INTSC3TX_IRQHandler [WEAK] + EXPORT INTSC3ERR_IRQHandler [WEAK] + EXPORT INTI2C0NST_IRQHandler [WEAK] + EXPORT INTI2C0ATX_IRQHandler [WEAK] + EXPORT INTI2C0BRX_IRQHandler [WEAK] + EXPORT INTI2C0NA_IRQHandler [WEAK] + EXPORT INTI2C1NST_IRQHandler [WEAK] + EXPORT INTI2C1ATX_IRQHandler [WEAK] + EXPORT INTI2C1BRX_IRQHandler [WEAK] + EXPORT INTI2C1NA_IRQHandler [WEAK] + EXPORT INTT32A00AC_IRQHandler [WEAK] + EXPORT INTT32A00ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A00ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A00B_IRQHandler [WEAK] + EXPORT INTT32A00BCAP0_IRQHandler [WEAK] + EXPORT INTT32A00BCAP1_IRQHandler [WEAK] + EXPORT INTT32A01AC_IRQHandler [WEAK] + EXPORT INTT32A01ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A01ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A01B_IRQHandler [WEAK] + EXPORT INTT32A01BCAP0_IRQHandler [WEAK] + EXPORT INTT32A01BCAP1_IRQHandler [WEAK] + EXPORT INTT32A02AC_IRQHandler [WEAK] + EXPORT INTT32A02ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A02ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A02B_IRQHandler [WEAK] + EXPORT INTT32A02BCAP0_IRQHandler [WEAK] + EXPORT INTT32A02BCAP1_IRQHandler [WEAK] + EXPORT INTT32A03AC_IRQHandler [WEAK] + EXPORT INTT32A03ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A03ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A03B_IRQHandler [WEAK] + EXPORT INTT32A03BCAP0_IRQHandler [WEAK] + EXPORT INTT32A03BCAP1_IRQHandler [WEAK] + EXPORT INTT32A04AC_IRQHandler [WEAK] + EXPORT INTT32A04ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A04ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A04B_IRQHandler [WEAK] + EXPORT INTT32A04BCAP0_IRQHandler [WEAK] + EXPORT INTT32A04BCAP1_IRQHandler [WEAK] + EXPORT INTT32A05AC_IRQHandler [WEAK] + EXPORT INTT32A05ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A05ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A05B_IRQHandler [WEAK] + EXPORT INTT32A05BCAP0_IRQHandler [WEAK] + EXPORT INTT32A05BCAP1_IRQHandler [WEAK] + EXPORT INTPARI0_IRQHandler [WEAK] + EXPORT INTPARI1_IRQHandler [WEAK] + EXPORT INTDMAATC_IRQHandler [WEAK] + EXPORT INTDMAAERR_IRQHandler [WEAK] + EXPORT INTFLCRDY_IRQHandler [WEAK] + EXPORT INTFLDRDY_IRQHandler [WEAK] + +INT00_IRQHandler +INT01_IRQHandler +INT02_IRQHandler +INT03_IRQHandler +INT04_IRQHandler +INT05_IRQHandler +INT06_IRQHandler +INT07_IRQHandler +INT08_IRQHandler +INT09_IRQHandler +INT10_IRQHandler +INT11_IRQHandler +INT12_IRQHandler +INT13_IRQHandler +INT14_IRQHandler +INT15_IRQHandler +INT16_IRQHandler +INT17_IRQHandler +INT18_IRQHandler +INT21_IRQHandler +INTVCN0_IRQHandler +INTVCT0_IRQHandler +INTEMG0_IRQHandler +INTEMG1_IRQHandler +INTEMG2_IRQHandler +INTOVV0_IRQHandler +INTOVV1_IRQHandler +INTOVV2_IRQHandler +INTPWM0_IRQHandler +INTPWM1_IRQHandler +INTPWM2_IRQHandler +INTENC00_IRQHandler +INTENC01_IRQHandler +INTENC10_IRQHandler +INTENC11_IRQHandler +INTENC20_IRQHandler +INTENC21_IRQHandler +INTADAPDA_IRQHandler +INTADAPDB_IRQHandler +INTADACP0_IRQHandler +INTADACP1_IRQHandler +INTADATRG_IRQHandler +INTADASGL_IRQHandler +INTADACNT_IRQHandler +INTADBPDA_IRQHandler +INTADBPDB_IRQHandler +INTADBCP0_IRQHandler +INTADBCP1_IRQHandler +INTADBTRG_IRQHandler +INTADBSGL_IRQHandler +INTADBCNT_IRQHandler +INTADCPDA_IRQHandler +INTADCPDB_IRQHandler +INTADCCP0_IRQHandler +INTADCCP1_IRQHandler +INTADCTRG_IRQHandler +INTADCSGL_IRQHandler +INTADCCNT_IRQHandler +INTSC0RX_IRQHandler +INTSC0TX_IRQHandler +INTSC0ERR_IRQHandler +INTSC1RX_IRQHandler +INTSC1TX_IRQHandler +INTSC1ERR_IRQHandler +INTSC2RX_IRQHandler +INTSC2TX_IRQHandler +INTSC2ERR_IRQHandler +INTSC3RX_IRQHandler +INTSC3TX_IRQHandler +INTSC3ERR_IRQHandler +INTI2C0NST_IRQHandler +INTI2C0ATX_IRQHandler +INTI2C0BRX_IRQHandler +INTI2C0NA_IRQHandler +INTI2C1NST_IRQHandler +INTI2C1ATX_IRQHandler +INTI2C1BRX_IRQHandler +INTI2C1NA_IRQHandler +INTT32A00AC_IRQHandler +INTT32A00ACCAP0_IRQHandler +INTT32A00ACCAP1_IRQHandler +INTT32A00B_IRQHandler +INTT32A00BCAP0_IRQHandler +INTT32A00BCAP1_IRQHandler +INTT32A01AC_IRQHandler +INTT32A01ACCAP0_IRQHandler +INTT32A01ACCAP1_IRQHandler +INTT32A01B_IRQHandler +INTT32A01BCAP0_IRQHandler +INTT32A01BCAP1_IRQHandler +INTT32A02AC_IRQHandler +INTT32A02ACCAP0_IRQHandler +INTT32A02ACCAP1_IRQHandler +INTT32A02B_IRQHandler +INTT32A02BCAP0_IRQHandler +INTT32A02BCAP1_IRQHandler +INTT32A03AC_IRQHandler +INTT32A03ACCAP0_IRQHandler +INTT32A03ACCAP1_IRQHandler +INTT32A03B_IRQHandler +INTT32A03BCAP0_IRQHandler +INTT32A03BCAP1_IRQHandler +INTT32A04AC_IRQHandler +INTT32A04ACCAP0_IRQHandler +INTT32A04ACCAP1_IRQHandler +INTT32A04B_IRQHandler +INTT32A04BCAP0_IRQHandler +INTT32A04BCAP1_IRQHandler +INTT32A05AC_IRQHandler +INTT32A05ACCAP0_IRQHandler +INTT32A05ACCAP1_IRQHandler +INTT32A05B_IRQHandler +INTT32A05BCAP0_IRQHandler +INTT32A05BCAP1_IRQHandler +INTPARI0_IRQHandler +INTPARI1_IRQHandler +INTDMAATC_IRQHandler +INTDMAAERR_IRQHandler +INTFLCRDY_IRQHandler +INTFLDRDY_IRQHandler + + B . + + ENDP + + + ALIGN + END + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/tmpm4knfyafg.sct b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/tmpm4knfyafg.sct new file mode 100644 index 00000000000..84d7b3a34d4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/tmpm4knfyafg.sct @@ -0,0 +1,74 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +/* + * Copyright(C) 2020, Toshiba Electronic Device Solutions Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +;; TMPM4KNA scatter file + +;; Vector table starts at 0 +;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) +;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) +;; Initial PC == &__main (with LSB set to indicate Thumb) +;; These two values are provided by the library +;; Other vectors must be provided by the user +;; Code starts after the last possible vector +;; Data starts at 0x20000000 +;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) +;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) + +;; Compatible with ISSM model + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x00040000 +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +# if defined(MBED_BOOT_STACK_SIZE) +# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +# else +# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +# endif +#endif + +#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE + +; TMPM4KNA: 256 KB FLASH (0x40000) + 24 KB SRAM (0x6000) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region +{ + ER_IROM1 MBED_APP_START MBED_APP_SIZE + { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 0x20000238 (0x6000 - 0x238 - Stack_Size) + { + .ANY (+RW, +ZI) + rda_flash512ud32_b.o(+RO) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000+0x6000 - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (0x20000000+0x6000) EMPTY -Stack_Size { ; stack + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/startup_TMPM4KNA.S b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/startup_TMPM4KNA.S new file mode 100644 index 00000000000..e8f894d2e04 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/startup_TMPM4KNA.S @@ -0,0 +1,496 @@ +/** + ******************************************************************************* + * @file startup_TMPM4KNA.s + * @brief CMSIS Cortex-M4F Core Device Startup File for the + * TOSHIBA 'TMPM4KNA' Device Series + * @version + * @date + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 All rights reserved + ******************************************************************************* + */ + +.syntax unified +.arch armv7-m + +.section .stack +.align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.if Heap_Size +.space Heap_Size +.endif +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + // External Interrupts + .long INT00_IRQHandler // 0: Interrupt pin 00 + .long INT01_IRQHandler // 1: Interrupt pin 01a/00b + .long INT02_IRQHandler // 2: Interrupt pin 02a/00b + .long INT03_IRQHandler // 3: Interrupt pin 03a/03b + .long INT04_IRQHandler // 4: Interrupt pin 04a/04b + .long INT05_IRQHandler // 5: Interrupt pin 05a/05b + .long INT06_IRQHandler // 6: Interrupt pin 06a/06b + .long INT07_IRQHandler // 7: Interrupt pin 07a/07b + .long INT08_IRQHandler // 8: Interrupt pin 08a/08b + .long INT09_IRQHandler // 9: Interrupt pin 09 + .long INT10_IRQHandler // 10: Interrupt pin 10 + .long INT11_IRQHandler // 11: Interrupt pin 11a/11b + .long INT12_IRQHandler // 12: Interrupt pin 12 + .long INT13_IRQHandler // 13: Interrupt pin 13 + .long INT14_IRQHandler // 14: Interrupt pin 14a/14b + .long INT15_IRQHandler // 15: Interrupt pin 15 + .long INT16_IRQHandler // 16: Interrupt pin 16a/16b + .long INT17_IRQHandler // 17: Interrupt pin 17a/17b + .long INT18_IRQHandler // 18: Interrupt pin 18a/18b + .long 0 // 19: Reserved + .long 0 // 20: Reserved + .long INT21_IRQHandler // 21: Interrupt pin 21 + .long INTVCN0_IRQHandler // 22: A-VE+ ch0 Interrupt + .long INTVCT0_IRQHandler // 23: A-VE+ ch0 Task termination interrupt + .long INTEMG0_IRQHandler // 24: A-PMD ch0 EMG interrupt + .long INTEMG1_IRQHandler // 25: A-PMD ch1 EMG interrupt + .long INTEMG2_IRQHandler // 26: A-PMD ch2 EMG interrupt + .long INTOVV0_IRQHandler // 27: A-PMD ch0 OVV interrupt + .long INTOVV1_IRQHandler // 28: A-PMD ch1 OVV interrupt + .long INTOVV2_IRQHandler // 29: A-PMD ch2 OVV interrupt + .long INTPWM0_IRQHandler // 30: A-PMD ch0 PWM interrupt + .long INTPWM1_IRQHandler // 31: A-PMD ch1 PWM interrupt + .long INTPWM2_IRQHandler // 32: A-PMD ch2 PWM interrupt + .long INTENC00_IRQHandler // 33: A-ENC32 ch0 Encoder interrupt 0 + .long INTENC01_IRQHandler // 34: A-ENC32 ch0 Encoder interrupt 1 + .long INTENC10_IRQHandler // 35: A-ENC32 ch1 Encoder interrupt 0 + .long INTENC11_IRQHandler // 36: A-ENC32 ch1 Encoder interrupt 1 + .long INTENC20_IRQHandler // 37: A-ENC32 ch2 Encoder interrupt 0 + .long INTENC21_IRQHandler // 38: A-ENC32 ch2 Encoder interrupt 1 + .long INTADAPDA_IRQHandler // 39: ADC unit A PMD trigger program interrupt A + .long INTADAPDB_IRQHandler // 40: ADC unit A PMD trigger program interrupt B + .long INTADACP0_IRQHandler // 41: ADC unit A Monitor function 0 interrupt + .long INTADACP1_IRQHandler // 42: ADC unit A Monitor function 1 interrupt + .long INTADATRG_IRQHandler // 43: ADC unit A General purpose trigger program interrupt + .long INTADASGL_IRQHandler // 44: ADC unit A Single program interrupt + .long INTADACNT_IRQHandler // 45: ADC unit A Continuity program interrupt + .long INTADBPDA_IRQHandler // 46: ADC unit B PMD trigger program interrupt A + .long INTADBPDB_IRQHandler // 47: ADC unit B PMD trigger program interrupt B + .long INTADBCP0_IRQHandler // 48: ADC unit B Monitor function 0 interrupt + .long INTADBCP1_IRQHandler // 49: ADC unit B Monitor function 1 interrupt + .long INTADBTRG_IRQHandler // 50: ADC unit B General purpose trigger program interrupt + .long INTADBSGL_IRQHandler // 51: ADC unit B Single program interrupt + .long INTADBCNT_IRQHandler // 52: ADC unit B Continuity program interrupt + .long INTADCPDA_IRQHandler // 53: ADC unit C PMD trigger program interrupt A + .long INTADCPDB_IRQHandler // 54: ADC unit C PMD trigger program interrupt B + .long INTADCCP0_IRQHandler // 55: ADC unit C Monitor function 0 interrupt + .long INTADCCP1_IRQHandler // 56: ADC unit C Monitor function 1 interrupt + .long INTADCTRG_IRQHandler // 57: ADC unit C General purpose trigger program interrupt + .long INTADCSGL_IRQHandler // 58: ADC unit C Single program interrupt + .long INTADCCNT_IRQHandler // 59: ADC unit C Continuity program interrupt + .long INTSC0RX_IRQHandler // 60: TSPI/UART ch0 Reception interrupt + .long INTSC0TX_IRQHandler // 61: TSPI/UART ch0 Transmit interrupt + .long INTSC0ERR_IRQHandler // 62: TSPI/UART ch0 Error interrupt + .long INTSC1RX_IRQHandler // 63: TSPI/UART ch1 Reception interrupt + .long INTSC1TX_IRQHandler // 64: TSPI/UART ch1 Transmit interrupt + .long INTSC1ERR_IRQHandler // 65: TSPI/UART ch1 Error interrupt + .long INTSC2RX_IRQHandler // 66: UART ch2 Reception interrupt + .long INTSC2TX_IRQHandler // 67: UART ch2 Transmit interrupt + .long INTSC2ERR_IRQHandler // 68: UART ch2 Error interrupt + .long INTSC3RX_IRQHandler // 69: UART ch3 Reception interrupt + .long INTSC3TX_IRQHandler // 70: UART ch3 Transmit interrupt + .long INTSC3ERR_IRQHandler // 71: UART ch3 Error interrupt + .long INTI2C0NST_IRQHandler // 72: I2C ch0 Interrupt / EI2C ch0 Status interrupt + .long INTI2C0ATX_IRQHandler // 73: I2C ch0 Arbitration lost detection interrupt / EI2C ch0 Transmission buffer empty interrupt + .long INTI2C0BRX_IRQHandler // 74: I2C ch0 Bus free detection interrupt / EI2C ch0 Reception buffer full interrupt + .long INTI2C0NA_IRQHandler // 75: I2C ch0 NACK detection interrupt + .long INTI2C1NST_IRQHandler // 76: I2C ch1 Interrupt / EI2C ch1 Status interrupt + .long INTI2C1ATX_IRQHandler // 77: I2C ch1 Arbitration lost detection interrupt / EI2C ch1 Transmission buffer empty interrupt + .long INTI2C1BRX_IRQHandler // 78: I2C ch1 Bus free detection interrupt / EI2C ch1 Reception buffer full interrupt + .long INTI2C1NA_IRQHandler // 79: I2C ch1 NACK detection interrupt + .long 0 // 80: Reserved + .long 0 // 81: Reserved + .long 0 // 82: Reserved + .long INTT32A00AC_IRQHandler // 83: T32A ch0 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A00ACCAP0_IRQHandler// 84: T32A ch0 Timer A/C Input capture 0 + .long INTT32A00ACCAP1_IRQHandler// 85: T32A ch0 Timer A/C Input capture 1 + .long INTT32A00B_IRQHandler // 86: T32A ch0 Timer B Compare match detection / Over flow / Under flow + .long INTT32A00BCAP0_IRQHandler // 87: T32A ch0 Timer B Input capture 0 + .long INTT32A00BCAP1_IRQHandler // 88: T32A ch0 Timer B Input capture 1 + .long INTT32A01AC_IRQHandler // 89: T32A ch1 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A01ACCAP0_IRQHandler// 90: T32A ch1 Timer A/C Input capture 0 + .long INTT32A01ACCAP1_IRQHandler// 91: T32A ch1 Timer A/C Input capture 1 + .long INTT32A01B_IRQHandler // 92: T32A ch1 Timer B Compare match detection / Over flow / Under flow + .long INTT32A01BCAP0_IRQHandler // 93: T32A ch1 Timer B Input capture 0 + .long INTT32A01BCAP1_IRQHandler // 94: T32A ch1 Timer B Input capture 1 + .long INTT32A02AC_IRQHandler // 95: T32A ch2 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A02ACCAP0_IRQHandler// 96: T32A ch2 Timer A/C Input capture 0 + .long INTT32A02ACCAP1_IRQHandler// 97: T32A ch2 Timer A/C Input capture 1 + .long INTT32A02B_IRQHandler // 98: T32A ch2 Timer B Compare match detection / Over flow / Under flow + .long INTT32A02BCAP0_IRQHandler // 99: T32A ch2 Timer B Input capture 0 + .long INTT32A02BCAP1_IRQHandler // 100: T32A ch2 Timer B Input capture 1 + .long INTT32A03AC_IRQHandler // 101: T32A ch3 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A03ACCAP0_IRQHandler// 102: T32A ch3 Timer A/C Input capture 0 + .long INTT32A03ACCAP1_IRQHandler// 103: T32A ch3 Timer A/C Input capture 1 + .long INTT32A03B_IRQHandler // 104: T32A ch3 Timer B Compare match detection / Over flow / Under flow + .long INTT32A03BCAP0_IRQHandler // 105: T32A ch3 Timer B Input capture 0 + .long INTT32A03BCAP1_IRQHandler // 106: T32A ch3 Timer B Input capture 1 + .long INTT32A04AC_IRQHandler // 107: T32A ch4 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A04ACCAP0_IRQHandler// 108: T32A ch4 Timer A/C Input capture 0 + .long INTT32A04ACCAP1_IRQHandler// 109: T32A ch4 Timer A/C Input capture 1 + .long INTT32A04B_IRQHandler // 110: T32A ch4 Timer B Compare match detection / Over flow / Under flow + .long INTT32A04BCAP0_IRQHandler // 111: T32A ch4 Timer B Input capture 0 + .long INTT32A04BCAP1_IRQHandler // 112: T32A ch4 Timer B Input capture 1 + .long INTT32A05AC_IRQHandler // 113: T32A ch5 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A05ACCAP0_IRQHandler// 114: T32A ch5 Timer A/C Input capture 0 + .long INTT32A05ACCAP1_IRQHandler// 115: T32A ch5 Timer A/C Input capture 1 + .long INTT32A05B_IRQHandler // 116: T32A ch5 Timer B Compare match detection / Over flow / Under flow + .long INTT32A05BCAP0_IRQHandler // 117: T32A ch5 Timer B Input capture 0 + .long INTT32A05BCAP1_IRQHandler // 118: T32A ch5 Timer B Input capture 1 + .long INTPARI0_IRQHandler // 119: RAMP ch0 Parity error interrupt + .long INTPARI1_IRQHandler // 120: RAMP ch1 Parity error interrupt + .long INTDMAATC_IRQHandler // 121: DMAC unit A End of transfer (ch0 - 31) + .long INTDMAAERR_IRQHandler // 122: DMAC unit A Transfer error + .long INTFLCRDY_IRQHandler // 123: Code FLASH Ready interrupt + .long INTFLDRDY_IRQHandler // 124: Data FLASH Ready interrupt + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler INT00_IRQHandler + def_irq_handler INT01_IRQHandler + def_irq_handler INT02_IRQHandler + def_irq_handler INT03_IRQHandler + def_irq_handler INT04_IRQHandler + def_irq_handler INT05_IRQHandler + def_irq_handler INT06_IRQHandler + def_irq_handler INT07_IRQHandler + def_irq_handler INT08_IRQHandler + def_irq_handler INT09_IRQHandler + def_irq_handler INT10_IRQHandler + def_irq_handler INT11_IRQHandler + def_irq_handler INT12_IRQHandler + def_irq_handler INT13_IRQHandler + def_irq_handler INT14_IRQHandler + def_irq_handler INT15_IRQHandler + def_irq_handler INT16_IRQHandler + def_irq_handler INT17_IRQHandler + def_irq_handler INT18_IRQHandler + def_irq_handler INT21_IRQHandler + def_irq_handler INTVCN0_IRQHandler + def_irq_handler INTVCT0_IRQHandler + def_irq_handler INTEMG0_IRQHandler + def_irq_handler INTEMG1_IRQHandler + def_irq_handler INTEMG2_IRQHandler + def_irq_handler INTOVV0_IRQHandler + def_irq_handler INTOVV1_IRQHandler + def_irq_handler INTOVV2_IRQHandler + def_irq_handler INTPWM0_IRQHandler + def_irq_handler INTPWM1_IRQHandler + def_irq_handler INTPWM2_IRQHandler + def_irq_handler INTENC00_IRQHandler + def_irq_handler INTENC01_IRQHandler + def_irq_handler INTENC10_IRQHandler + def_irq_handler INTENC11_IRQHandler + def_irq_handler INTENC20_IRQHandler + def_irq_handler INTENC21_IRQHandler + def_irq_handler INTADAPDA_IRQHandler + def_irq_handler INTADAPDB_IRQHandler + def_irq_handler INTADACP0_IRQHandler + def_irq_handler INTADACP1_IRQHandler + def_irq_handler INTADATRG_IRQHandler + def_irq_handler INTADASGL_IRQHandler + def_irq_handler INTADACNT_IRQHandler + def_irq_handler INTADBPDA_IRQHandler + def_irq_handler INTADBPDB_IRQHandler + def_irq_handler INTADBCP0_IRQHandler + def_irq_handler INTADBCP1_IRQHandler + def_irq_handler INTADBTRG_IRQHandler + def_irq_handler INTADBSGL_IRQHandler + def_irq_handler INTADBCNT_IRQHandler + def_irq_handler INTADCPDA_IRQHandler + def_irq_handler INTADCPDB_IRQHandler + def_irq_handler INTADCCP0_IRQHandler + def_irq_handler INTADCCP1_IRQHandler + def_irq_handler INTADCTRG_IRQHandler + def_irq_handler INTADCSGL_IRQHandler + def_irq_handler INTADCCNT_IRQHandler + def_irq_handler INTSC0RX_IRQHandler + def_irq_handler INTSC0TX_IRQHandler + def_irq_handler INTSC0ERR_IRQHandler + def_irq_handler INTSC1RX_IRQHandler + def_irq_handler INTSC1TX_IRQHandler + def_irq_handler INTSC1ERR_IRQHandler + def_irq_handler INTSC2RX_IRQHandler + def_irq_handler INTSC2TX_IRQHandler + def_irq_handler INTSC2ERR_IRQHandler + def_irq_handler INTSC3RX_IRQHandler + def_irq_handler INTSC3TX_IRQHandler + def_irq_handler INTSC3ERR_IRQHandler + def_irq_handler INTI2C0NST_IRQHandler + def_irq_handler INTI2C0ATX_IRQHandler + def_irq_handler INTI2C0BRX_IRQHandler + def_irq_handler INTI2C0NA_IRQHandler + def_irq_handler INTI2C1NST_IRQHandler + def_irq_handler INTI2C1ATX_IRQHandler + def_irq_handler INTI2C1BRX_IRQHandler + def_irq_handler INTI2C1NA_IRQHandler + def_irq_handler INTT32A00AC_IRQHandler + def_irq_handler INTT32A00ACCAP0_IRQHandler + def_irq_handler INTT32A00ACCAP1_IRQHandler + def_irq_handler INTT32A00B_IRQHandler + def_irq_handler INTT32A00BCAP0_IRQHandler + def_irq_handler INTT32A00BCAP1_IRQHandler + def_irq_handler INTT32A01AC_IRQHandler + def_irq_handler INTT32A01ACCAP0_IRQHandler + def_irq_handler INTT32A01ACCAP1_IRQHandler + def_irq_handler INTT32A01B_IRQHandler + def_irq_handler INTT32A01BCAP0_IRQHandler + def_irq_handler INTT32A01BCAP1_IRQHandler + def_irq_handler INTT32A02AC_IRQHandler + def_irq_handler INTT32A02ACCAP0_IRQHandler + def_irq_handler INTT32A02ACCAP1_IRQHandler + def_irq_handler INTT32A02B_IRQHandler + def_irq_handler INTT32A02BCAP0_IRQHandler + def_irq_handler INTT32A02BCAP1_IRQHandler + def_irq_handler INTT32A03AC_IRQHandler + def_irq_handler INTT32A03ACCAP0_IRQHandler + def_irq_handler INTT32A03ACCAP1_IRQHandler + def_irq_handler INTT32A03B_IRQHandler + def_irq_handler INTT32A03BCAP0_IRQHandler + def_irq_handler INTT32A03BCAP1_IRQHandler + def_irq_handler INTT32A04AC_IRQHandler + def_irq_handler INTT32A04ACCAP0_IRQHandler + def_irq_handler INTT32A04ACCAP1_IRQHandler + def_irq_handler INTT32A04B_IRQHandler + def_irq_handler INTT32A04BCAP0_IRQHandler + def_irq_handler INTT32A04BCAP1_IRQHandler + def_irq_handler INTT32A05AC_IRQHandler + def_irq_handler INTT32A05ACCAP0_IRQHandler + def_irq_handler INTT32A05ACCAP1_IRQHandler + def_irq_handler INTT32A05B_IRQHandler + def_irq_handler INTT32A05BCAP0_IRQHandler + def_irq_handler INTT32A05BCAP1_IRQHandler + def_irq_handler INTPARI0_IRQHandler + def_irq_handler INTPARI1_IRQHandler + def_irq_handler INTDMAATC_IRQHandler + def_irq_handler INTDMAAERR_IRQHandler + def_irq_handler INTFLCRDY_IRQHandler + def_irq_handler INTFLDRDY_IRQHandler + + .end diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/tmpm4knfyafg.ld b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/tmpm4knfyafg.ld new file mode 100644 index 00000000000..b7d924e6e0b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/tmpm4knfyafg.ld @@ -0,0 +1,195 @@ +/* + * Copyright(C) 2021, Toshiba Electronic Device Solutions Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* Linker script for Toshiba TMPM4KNA */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 256K +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + /* 8_byte_aligned((125 + 16) vect * 4 bytes) = 8_byte_aligned(0x238) = 0x238 */ + RAM (rwx) : ORIGIN = 0x20000238, LENGTH = (24K - 0x238) +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + *(.ram_func*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis.h new file mode 100644 index 00000000000..f31080ae6b7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis.h @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "TMPM4KNA.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis_nvic.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis_nvic.h new file mode 100644 index 00000000000..0c48bbd1051 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + + +#if defined(__ICCARM__) +#pragma section=".intvec" +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) +#elif defined(__CC_ARM) +extern uint32_t Load$$LR$$LR_IROM1$$Base[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) +#elif defined(__GNUC__) +extern uint32_t vectors[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors) +#else +#error "Flash vector address not set for this toolchain" +#endif + + +#define NVIC_NUM_VECTORS (141) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.c new file mode 100644 index 00000000000..dc1993538bf --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.c @@ -0,0 +1,389 @@ +/** + ******************************************************************************* + * @file system_TMPM4KyA.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the + * TOSHIBA 'TMPM4ky' Device Series + * @version V1.0.0.0 + * $Date:: 2020-09-17 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#include "TMPM4KNA.h" + + +/*-------- <<< Start of configuration section >>> ----------------------------*/ + +/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ +#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ +#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ +#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ + +/* Clock Generator (CG) Configuration */ +#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ + +#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U) +#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U) +#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U) + +#define CG_6M_MUL_26_656_FPLL (0x001C1535UL<<8U) /* fPLL = 6MHz * 26.656 */ +#define CG_8M_MUL_20_FPLL (0x00245028UL<<8U) /* fPLL = 8MHz * 20 */ +#define CG_10M_MUL_16_FPLL (0x002E9020UL<<8U) /* fPLL = 10MHz * 16 */ +#define CG_12M_MUL_13_312_FPLL (0x0036DA1AUL<<8U) /* fPLL = 12MHz * 13.312 */ + +#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL) +#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL) +#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL) +#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL) + +#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL) +#define CG_OSCCR_EOSCEN_SET (0x00000002UL) +#define CG_OSCCR_OSCSEL_SET (0x00000100UL) + +#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */ +#define SYSCR_PRCK_Val (0x00000000UL) /* phiT0 = fc */ +#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */ + +#define STBYCR_Val (0x00000000UL) + +#define CG_WUPHCR_WUON_START_SET (0x00000001UL) +#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */ + +#if (CLOCK_SETUP) +#define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */ +#define PLL0SEL_Ready CG_10M_MUL_16_FPLL +#else +#define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */ +#define PLL0SEL_Ready CG_10M_MUL_16_FPLL +#endif + +#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) +#define PLL0SEL_MASK (0xFFFFFF00UL) + +/*-------- <<< End of configuration section >>> ------------------------------*/ + +/*-------- DEFINES -----------------------------------------------------------*/ +/* Define clocks */ +#define IOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ +#define IOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ +#define IOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ + +#define EOSC_6M (6000000UL) +#define EOSC_8M (8000000UL) +#define EOSC_10M (10000000UL) +#define EOSC_12M (12000000UL) +#define IOSC_10M (10000000UL) +#define EXTALH EOSC_10M /* External high-speed oscillator freq */ +#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ +#define EOSC_6M_DIV4_PLLON (79970000UL) /* 6.00MHz * 53.3125 / 4 */ +#define EOSC_8M_DIV4_PLLON (80000000UL) /* 8.00MHz * 40.0000 / 4 */ +#define EOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ +#define EOSC_12M_DIV4_PLLON (79880000UL) /* 12.00MHz * 26.6250 / 4 */ +#define EOSC_6M_DIV8_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */ +#define EOSC_8M_DIV8_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */ +#define EOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ +#define EOSC_12M_DIV8_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */ +#define EOSC_6M_DIV2_PLLON (160000000UL) /* 6.00MHz * 53.3125 / 2 */ +#define EOSC_8M_DIV2_PLLON (160000000UL) /* 8.00MHz * 40.0000 / 2 */ +#define EOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ +#define EOSC_12M_DIV2_PLLON (160000000UL) /* 12.00MHz * 26.6250 / 2 */ + +/* Configure Warm-up time */ +#define HZ_1M (1000000UL) +#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ +#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ +#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ + +#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = (warm-up time(us) * IXTALH - 16) / 16 */ +#if (CLOCK_SETUP) +#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#else +#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#endif +/* Determine core clock frequency according to settings */ +/* System clock is high-speed clock*/ +#if (CLOCK_SETUP) +#define CORE_TALH (EXTALH) +#else +#define CORE_TALH (IXTALH) +#endif + +#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ +#if (CORE_TALH == EOSC_6M) /* If input is 6MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_26_656_FPLL)) +#define __CORE_CLK EOSC_6M_DIV2_PLLON /* output clock is 159.938MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 6MHz */ +#elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_20_FPLL)) +#define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 160MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 8MHz */ +#elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) +#define __CORE_CLK EOSC_10M_DIV2_PLLON /* output clock is 160MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 10MHz */ +#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_13_312_FPLL) +#define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 159.75MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 12MHz */ +#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) +#define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 160MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 12MHz */ +#else /* input clock not known */ +#define __CORE_CLK (0U) +#error "Core Oscillator Frequency invalid!" +#endif /* End switch input clock */ +#else /* If PLL not used */ +#define __CORE_CLK (CORE_TALH) +#endif + +#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */ +#define __CORE_SYS (__CORE_CLK) +#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */ +#define __CORE_SYS (__CORE_CLK / 2U) +#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */ +#define __CORE_SYS (__CORE_CLK / 4U ) +#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */ +#define __CORE_SYS (__CORE_CLK / 8U) +#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */ +#define __CORE_SYS (__CORE_CLK / 16U) +#else /* Gear -> reserved */ +#define __CORE_SYS (0U) +#endif + + +/* Clock Variable definitions */ +uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Private_define Flash Private Define + * @{ + */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */ +#define FC_MAX_PAGES (uint8_t)(0x80) /*!< Maxmum pages */ +#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */ +#define FC_MAX_AREAS (uint8_t)(0x1) /*!< Maxmum areas */ +#define FC_MAX_DATA_PAGES (uint8_t)(0x21) /*!< Maxmum pages */ +#define FC_MAX_DATA_BLOCKS (uint8_t)(0x8) /*!< Maxmum blocks */ +#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */ +#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */ +#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */ +#define FC_BANK_USER_INFO (0x00000007UL) /*!< Bank Change User Information Area */ +#define FC_BANK_CODE_FLASH (0x00000000UL) /*!< Bank Change Code Flash */ +#define FC_BUFFER_DISABLE (0x00000007UL) /*!< Flash Buffer Disable nad Clear */ +#define FC_BUFFER_ENABLE (0x00000000UL) /*!< Flash Buffer Enable */ + +#define FC_ACCR_FDLC_4 (0x00000300UL) /*!< Data Flash read clock 4clock */ +#define FC_ACCR_FDLC_5 (0x00000400UL) /*!< Data Flash read clock 5clock */ +#define FC_ACCR_FDLC_6 (0x00000500UL) /*!< Data Flash read clock 6clock */ +#define FC_ACCR_FCLC_1 (0x00000000UL) /*!< Code Flash read clock 1clock */ +#define FC_ACCR_FCLC_2 (0x00000001UL) /*!< Code Flash read clock 2clock */ +#define FC_ACCR_FCLC_3 (0x00000002UL) /*!< Code Flash read clock 3clock */ +#define FC_ACCR_FCLC_4 (0x00000003UL) /*!< Code Flash read clock 4clock */ +#define FC_ACCR_FCLC_5 (0x00000004UL) /*!< Code Flash read clock 5clock */ +#define FC_ACCR_FCLC_6 (0x00000005UL) /*!< Code Flash read clock 6clock */ +#define SYSCORECLOCK_80M (80000000UL) /*!< 80MHz */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Update SystemCoreClock according register values. + */ +void SystemCoreClockUpdate(void) +{ + /* Get Core Clock Frequency */ + + uint32_t CoreClock = 0U; + uint32_t CoreClockInput = 0U; + uint32_t regval = 0U; + uint32_t oscsel = 0U; + uint32_t pll0sel = 0U; + uint32_t pll0on = 0U; + /* Determine clock frequency according to clock register values */ + /* System clock is high-speed clock */ + regval = TSB_CG->OSCCR; + oscsel = regval & CG_OSCCR_OSCSEL_SET; + if (oscsel) { /* If system clock is External high-speed oscillator freq */ + CoreClock = EXTALH; + } else { /* If system clock is Internal high-speed oscillator freq */ + CoreClock = IXTALH; + } + regval = TSB_CG->PLL0SEL; + pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; + pll0on = regval & CG_PLL0SEL_PLL0ON_SET; + if (pll0sel && pll0on) { /* If PLL enabled */ + if (CoreClock == EOSC_6M) { /* If input is 6MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_26_656_FPLL) { + CoreClockInput = EOSC_6M_DIV2_PLLON; /* output clock is 159.938MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_8M) { /* If input is 8MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_20_FPLL) { + CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 160MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) { + CoreClockInput = EOSC_10M_DIV2_PLLON; /* output clock is 160MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_13_312_FPLL) { + CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 159.75MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else { + CoreClockInput = 0U; + } + } else { /* If PLL not used */ + CoreClockInput = CoreClock; + } + + switch (TSB_CG->SYSCR & 7U) { + case 0U: /* Gear -> fc */ + SystemCoreClock = CoreClockInput; + break; + case 1U: /* Gear -> fc/2 */ + SystemCoreClock = CoreClockInput / 2U; + break; + case 2U: /* Gear -> fc/4 */ + SystemCoreClock = CoreClockInput / 4U; + break; + case 3U: /* Gear -> fc/8 */ + if (CoreClockInput >= EOSC_8M) { + SystemCoreClock = CoreClockInput / 8U; + } else { + SystemCoreClock = 0U; + } + break; + case 4U: /* Gear -> fc/16 */ + if (CoreClockInput >= EOSC_12M) { + SystemCoreClock = CoreClockInput / 16U; + } else { + SystemCoreClock = 0U; + } + break; + case 5U: + case 6U: + case 7U: + SystemCoreClock = 0U; + break; + default: + SystemCoreClock = 0U; + break; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit(void) +{ +#if (SIWD_SETUP) /* Watchdog Setup */ + /* SIWD Disable */ + TSB_SIWD0->EN = SIWDEN_Val; + TSB_SIWD0->CR = SIWDCR_Val; +#else + /* SIWD Enable (Setting after a Reset) */ +#endif + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + +#if (CLOCK_SETUP) /* Clock(external) Setup */ + TSB_CG->SYSCR = (SYSCR_GEAR_Val | (SYSCR_PRCK_Val << 8)); /* set */ + + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET); + TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; + while (!TSB_CG_OSCCR_OSCF) { + ; + } /* Confirm CGOSCCR="1" */ + TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; +#else + /* Internal HOSC Enable (Setting after a Reset) */ +#endif + + /* PLL Setup */ + TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set */ + while ((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val)) + != ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))) { + ; + } + + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; + TSB_CG->PLL0SEL = PLL0SEL_Ready; + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ + TSB_CG->STBYCR = STBYCR_Val; + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Lockup */ + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; + while (!TSB_CG_PLL0SEL_PLL0ST) { + ; + } /*Confirm CGPLL0SEL = "1" */ + +} + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.h new file mode 100644 index 00000000000..56987ea3298 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.h @@ -0,0 +1,65 @@ +/** + ***************************************************************************** + * @file system_TMPM4KyA.h + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4KyA' Device Series + * @version V1.0.0.0 + * $Date:: 2020-09-09 14:33:28 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ***************************************************************************** + */ + +#include + +#ifndef __SYSTEM_TMPM4KYA_H +#define __SYSTEM_TMPM4KYA_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/flash_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/flash_api.c new file mode 100644 index 00000000000..a2edf53b058 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/flash_api.c @@ -0,0 +1,172 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "flash_api.h" +#include "mbed_critical.h" +#include "flash.h" + +#define PROGRAM_WRITE_MAX (16U) // Page program could be written 16 bytes/4 words once +#define SECTOR_SIZE (0x8000) // 32KB each sectors or block +#define FLASH_CHIP_SIZE (0x00040000) // Flash chip size is 2048 KByte +#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL) +#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */ + +#define SUCCESS (0U) +#define FAIL (-1) +// IHOSC1EN +#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask +#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable +#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable + +static void internal_hosc_enable(void); +static int16_t flash_get_block_no(const flash_t *obj, uint32_t address); + +static uint32_t flash_block_address[FC_MAX_BLOCKS] = { + (0x5E000000UL), /*!< CODE FLASH Block0 */ + (0x5E008000UL), /*!< CODE FLASH Block1 */ + (0x5E010000UL), /*!< CODE FLASH Block2 */ + (0x5E018000UL), /*!< CODE FLASH Block3 */ + (0x5E020000UL), /*!< CODE FLASH Block4 */ + (0x5E028000UL), /*!< CODE FLASH Block5 */ + (0x5E030000UL), /*!< CODE FLASH Block6 */ + (0x5E038000UL), /*!< CODE FLASH Block7 */ + (0x5E040000UL), /*!< CODE FLASH Block8 */ + (0x5E048000UL), /*!< CODE FLASH Block9 */ + (0x5E050000UL), /*!< CODE FLASH Block10 */ + (0x5E058000UL), /*!< CODE FLASH Block11 */ + (0x5E060000UL), /*!< CODE FLASH Block12 */ + (0x5E068000UL), /*!< CODE FLASH Block13 */ + (0x5E070000UL), /*!< CODE FLASH Block14 */ + (0x5E078000UL) /*!< CODE FLASH Block15 */ +}; + + +int32_t flash_init(flash_t *obj) +{ + obj->flash_inited = 0; + obj->flash_inited = 1; + internal_hosc_enable(); // Internal HOSC enable + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + obj->flash_inited = 0; + + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + int status = FAIL; + int16_t block_no; + + if (obj->flash_inited == 0) { + flash_init(obj); + } + + // We need to prevent flash accesses during erase operation + core_util_critical_section_enter(); + + block_no = flash_get_block_no(obj, address); + if (block_no == FAIL) { + return status; + } else { + //Continue + } + + if (TXZ_SUCCESS == fc_erase_block_code_flash(block_no, 1)) { + status = SUCCESS; + } else { + // Do nothing + } + + core_util_critical_section_exit(); + + return status; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + int status = SUCCESS; + + address &= MASK_CHIP_ID_FROM_ADD; + + // We need to prevent flash accesses during program operation + core_util_critical_section_enter(); + + if (TXZ_SUCCESS == fc_write_code_flash((uint32_t *)data, (uint32_t *)address, size)) { + // Do nothing + } else { + status = FAIL; + } + + core_util_critical_section_exit(); + + return status; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) { + return SECTOR_SIZE; + } else { + // Do nothing + } + + return MBED_FLASH_INVALID_SIZE; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return PROGRAM_WRITE_MAX; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FC_CODE_FLASH_ADDRESS_TOP; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_CHIP_SIZE; +} + +static void internal_hosc_enable(void) +{ + uint32_t work; + work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK); + TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE); +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + +static int16_t flash_get_block_no(const flash_t *obj, uint32_t address) +{ + (void)obj; + for (int i = 0 ; i < FC_MAX_BLOCKS; i++) { + if (flash_block_address[i] == address) { + return i; + } + } + return FAIL; + +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_api.c new file mode 100644 index 00000000000..6ffe26e5bdb --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_api.c @@ -0,0 +1,126 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "txzp_gpio.h" + +#define GPIO_DATA PIN_DATA(0, 2) +#define ALT_FUNC_GPIO 0 + +_gpio_t gpio_port_add = { + .p_pa_instance = TSB_PA, + .p_pb_instance = TSB_PB, + .p_pc_instance = TSB_PC, + .p_pd_instance = TSB_PD, + .p_pe_instance = TSB_PE, + .p_pf_instance = TSB_PF, + .p_pg_instance = TSB_PG, + .p_ph_instance = TSB_PH, + .p_pj_instance = TSB_PJ, + .p_pk_instance = TSB_PK, + .p_pl_instance = TSB_PL, + .p_pm_instance = TSB_PM, + .p_pn_instance = TSB_PN, + .p_pu_instance = TSB_PU, + .p_pv_instance = TSB_PV +}; + +uint32_t gpio_set(PinName pin) +{ + // Check that pin is valid + MBED_ASSERT(pin != (PinName)NC); + + // Set pin function as GPIO pin + pin_function(pin, GPIO_DATA); + + // Return pin mask + return (1 << (pin & 0x07)); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + // Store above pin mask, pin name into GPIO object + obj->pin = pin; + if (pin == (PinName)NC) { + return; + } + obj->pin_num = PIN_POS(pin); + obj->mask = gpio_set(pin); + obj->port = (PortName) PIN_PORT(pin); + // Enable clock for particular port + if (obj->port <= 12) { + TSB_CG->FSYSMENA |= (1 << (obj->port)); + } else { + TSB_CG->FSYSMENA |= (1 << (obj->port + 3)); + } +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + // Set pin mode + pin_mode(obj->pin, mode); +} + +// Set gpio object pin direction +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + // Set direction + switch (direction) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_INOUT); + break; + default: + break; + } +} + +void gpio_write(gpio_t *obj, int value) +{ + // Write gpio object pin data + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, value); +} + +int gpio_read(gpio_t *obj) +{ + // Read gpio object pin data + gpio_pinstate_t val = GPIO_PIN_SET; // To initialize local variable + gpio_read_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, &val); + return val; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_irq_api.c new file mode 100644 index 00000000000..f4d91248ab7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_irq_api.c @@ -0,0 +1,335 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_irq_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_critical.h" +#include "txzp_gpio.h" + +#define CHANNEL_NUM (22) +#define DISABLE (0) +#define ENABLE (1) +#define CLR_INT_FLAG (0xC0) + +const PinMap PinMap_GPIO_IRQ[] = { + {PA2, GPIO_IRQ_0, PIN_DATA(0, 0)}, + {PA4, GPIO_IRQ_1, PIN_DATA(0, 0)}, + {PC3, GPIO_IRQ_3, PIN_DATA(0, 0)}, + {PE3, GPIO_IRQ_4, PIN_DATA(0, 0)}, + {PE5, GPIO_IRQ_5, PIN_DATA(0, 0)}, + {PU1, GPIO_IRQ_7, PIN_DATA(0, 0)}, + {PU3, GPIO_IRQ_8, PIN_DATA(0, 0)}, + {PU6, GPIO_IRQ_9, PIN_DATA(0, 0)}, + {PC2, GPIO_IRQ_A, PIN_DATA(0, 0)}, + {PE4, GPIO_IRQ_B, PIN_DATA(0, 0)}, + {PU0, GPIO_IRQ_C, PIN_DATA(0, 0)}, + {PU5, GPIO_IRQ_D, PIN_DATA(0, 0)}, + {PA1, GPIO_IRQ_F, PIN_DATA(0, 0)}, + {PN1, GPIO_IRQ_10, PIN_DATA(0, 0)}, + {PD1, GPIO_IRQ_11, PIN_DATA(0, 0)}, + {PD5, GPIO_IRQ_12, PIN_DATA(0, 0)}, + {PG3, GPIO_IRQ_15, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + + +extern _gpio_t gpio_port_add; +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; +static CG_INTActiveState CurrentState; + +static void CG_SetSTBYReleaseINTSrc(CG_INTSrc, CG_INTActiveState, uint8_t); +static void INT_IRQHandler(PinName, uint32_t); + +void INT00_IRQHandler(void) +{ + INT_IRQHandler(PA2, 0); +} + +void INT01_IRQHandler(void) +{ + INT_IRQHandler(PA4, 1); +} + +void INT03_IRQHandler(void) +{ + INT_IRQHandler(PC3, 3); +} + +void INT04_IRQHandler(void) +{ + INT_IRQHandler(PE3, 4); +} + +void INT05_IRQHandler(void) +{ + INT_IRQHandler(PE5, 5); +} + +void INT07_IRQHandler(void) +{ + INT_IRQHandler(PU1, 7); +} + +void INT08_IRQHandler(void) +{ + INT_IRQHandler(PU3, 8); +} + +void INT09_IRQHandler(void) +{ + INT_IRQHandler(PU6, 9); +} + +void INT10_IRQHandler(void) +{ + INT_IRQHandler(PC2, 10); +} + +void INT11_IRQHandler(void) +{ + INT_IRQHandler(PE4, 11); +} + +void INT12_IRQHandler(void) +{ + INT_IRQHandler(PU0, 12); +} + +void INT13_IRQHandler(void) +{ + INT_IRQHandler(PU5, 13); +} + +void INT15_IRQHandler(void) +{ + INT_IRQHandler(PA1, 15); +} + +void INT16_IRQHandler(void) +{ + INT_IRQHandler(PN1, 16); +} + +void INT17_IRQHandler(void) +{ + INT_IRQHandler(PD1, 17); +} + +void INT18_IRQHandler(void) +{ + INT_IRQHandler(PD5, 18); +} + +void INT21_IRQHandler(void) +{ + INT_IRQHandler(PG3, 21); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + // Get gpio interrupt ID + obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); + core_util_critical_section_enter(); + // Get GPIO port and pin num + obj->port = (PortName)PIN_PORT(pin); + obj->pin_num = PIN_POS(pin); + // Set pin level as LOW + gpio_write_bit(&gpio_port_add, obj->port, obj->pin_num, GPIO_Mode_DATA, 0); + // Enable gpio interrupt function + pinmap_pinout(pin, PinMap_GPIO_IRQ); + // Get GPIO irq source + obj->irq_src = (CG_INTSrc)obj->irq_id; + // Save irq handler + hal_irq_handler[obj->irq_src] = handler; + // Save irq id + channel_ids[obj->irq_src] = id; + // Initialize interrupt event as both edges detection + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Set interrupt event and enable INTx clear + CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); + core_util_critical_section_exit(); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + // Clear gpio_irq + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Reset interrupt handler + hal_irq_handler[obj->irq_src] = NULL; + // Reset interrupt id + channel_ids[obj->irq_src] = 0; + + // Disable GPIO interrupt on obj + gpio_irq_disable(obj); +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + // Disable GPIO interrupt on obj + gpio_irq_disable(obj); + + if (enable) { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || + (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || + (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else { + error("Not supported event\n"); + } + } else { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || + (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || + (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else { + error("Not supported event\n"); + } + } + + CurrentState = obj->event; + if (obj->event != CG_INT_ACTIVE_STATE_INVALID) { + // Set interrupt event and enable INTx clear + CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 0); + } else { + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 1); + } + + // Clear interrupt request + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Enable GPIO interrupt on obj + gpio_irq_enable(obj); +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + // Clear and Enable gpio_irq object + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + NVIC_EnableIRQ((IRQn_Type)obj->irq_id); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + // Disable gpio_irq object + NVIC_DisableIRQ((IRQn_Type)obj->irq_id); +} + +static void INT_IRQHandler(PinName pin, uint32_t index) +{ + PortName port; + uint8_t pin_num; + gpio_pinstate_t data = GPIO_PIN_RESET; + pin_num = PIN_POS(pin); + port = (PortName)PIN_PORT(pin); + + // Clear interrupt request + CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, DISABLE); + // Get pin value + gpio_read_bit(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)pin_num, GPIO_Mode_DATA, &data); + + switch (data) { + // Falling edge detection + case 0: + hal_irq_handler[index](channel_ids[index], IRQ_FALL); + break; + // Rising edge detection + case 1: + hal_irq_handler[index](channel_ids[index], IRQ_RISE); + break; + default: + break; + } + + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_0 + index)); + // Enable interrupt request + CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, ENABLE); +} + +static void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource, CG_INTActiveState ActiveState, uint8_t NewState) +{ + uint8_t *ptr = NULL; + if (INTSource == 0) { + ptr = (uint8_t *)(&(TSB_IB->IMC033)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource <= 8) { + ptr = ((uint8_t *)(&(TSB_IB->IMC034)) + ((INTSource - 1) * 2)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource <= 10) { + ptr = ((uint8_t *)(&(TSB_IB->IMC050)) + ((INTSource - 9))); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource == 11) { + ptr = (uint8_t *)(&(TSB_IB->IMC052)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource <= 13) { + ptr = ((uint8_t *)(&(TSB_IB->IMC054)) + ((INTSource - 12))); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource == 14) { + ptr = (uint8_t *)(&(TSB_IB->IMC056)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource == 15) { + ptr = (uint8_t *)(&(TSB_IB->IMC058)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource <= 18) { + ptr = ((uint8_t *)(&(TSB_IB->IMC059)) + ((INTSource - 16) * 2)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource == 21) { + ptr = (uint8_t *)(&(TSB_IB->IMC069)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } + { + uint8_t regval = *ptr; + (void)regval; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_object.h new file mode 100644 index 00000000000..1d3816cd7a2 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_object.h @@ -0,0 +1,77 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" +#include "txzp_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t pin_num; + uint32_t mask; + PinName pin; + PortName port; +} gpio_t; + +typedef enum { + CG_INT_SRC_0 = 0U, + CG_INT_SRC_1, + CG_INT_SRC_2, + CG_INT_SRC_3, + CG_INT_SRC_4, + CG_INT_SRC_5, + CG_INT_SRC_6, + CG_INT_SRC_7, + CG_INT_SRC_8, + CG_INT_SRC_9, + CG_INT_SRC_A, + CG_INT_SRC_B, + CG_INT_SRC_C, + CG_INT_SRC_D, + CG_INT_SRC_E, + CG_INT_SRC_F, + CG_INT_SRC_10, + CG_INT_SRC_11, + CG_INT_SRC_12, + CG_INT_SRC_13, + CG_INT_SRC_14, + CG_INT_SRC_15 +} CG_INTSrc; + +typedef enum { + CG_INT_ACTIVE_STATE_L = 0x00U, + CG_INT_ACTIVE_STATE_H = 0x02U, + CG_INT_ACTIVE_STATE_FALLING = 0x04U, + CG_INT_ACTIVE_STATE_RISING = 0x06U, + CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U, + CG_INT_ACTIVE_STATE_INVALID = 0x0AU +} CG_INTActiveState; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName)NC); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/i2c_api.c new file mode 100644 index 00000000000..b1e503538b9 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/i2c_api.c @@ -0,0 +1,193 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include "i2c_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "txzp_i2c_api.h" + +#define MAX_I2C_FREQ 400000 + +static const PinMap PinMap_I2C_SDA[] = { + {PD3, I2C_1, PIN_DATA(2, 2)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {PD4, I2C_1, PIN_DATA(2, 2)}, + {NC, NC, 0} +}; + +// Initialize the I2C peripheral. It sets the default parameters for I2C +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + MBED_ASSERT(obj != NULL); + + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + + MBED_ASSERT((int)i2c_name != NC); + + switch (i2c_name) { + case I2C_1: + TSB_CG_FSYSMENA_IPMENA26 = TXZ_ENABLE; // Enable clock for I2C_1 + TSB_CG_FSYSMENA_IPMENA03 = TXZ_ENABLE; // Enable clock for GPIO D + obj->my_i2c.i2c.p_instance = TSB_I2C1; + obj->my_i2c.info.irqn = INTI2C1NST_IRQn; + break; + default: + error("I2C is not available"); + break; + } + + + pinmap_pinout(sda, PinMap_I2C_SDA); + pin_mode(sda, OpenDrain); + pin_mode(sda, PullUp); + + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(scl, OpenDrain); + pin_mode(scl, PullUp); + + i2c_reset(obj); + i2c_frequency(obj, 100000); + I2C_init(&obj->my_i2c.i2c); +} + +// Configure the I2C frequency +void i2c_frequency(i2c_t *obj, int hz) +{ + if (hz <= MAX_I2C_FREQ) { + i2c_frequency_t(&obj->my_i2c, hz); + } else { + error("Failed : Max I2C frequency is 400000"); + } +} + +int i2c_start(i2c_t *obj) +{ + i2c_start_t(&obj->my_i2c); + return TXZ_SUCCESS; +} + +int i2c_stop(i2c_t *obj) +{ + i2c_stop_t(&obj->my_i2c); + return TXZ_SUCCESS; +} + +void i2c_reset(i2c_t *obj) +{ + // Software reset + i2c_reset_t(&obj->my_i2c); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int32_t count = 0; + + count = i2c_read_t(&obj->my_i2c, address, (uint8_t *)data, length, stop); + + return count; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int32_t count = 0; + + count = i2c_write_t(&obj->my_i2c, address, (uint8_t *)data, length, stop); + + return count; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + int32_t data = 0; + + data = i2c_byte_read_t(&obj->my_i2c, last); + + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int32_t result = 0; + + result = i2c_byte_write_t(&obj->my_i2c, data); + + return result; +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + i2c_slave_mode_t(&obj->my_i2c, enable_slave); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + i2c_slave_address_t(&obj->my_i2c, address); +} + +int i2c_slave_receive(i2c_t *obj) +{ + int32_t result = 0; + + result = i2c_slave_receive_t(&obj->my_i2c); + + return result; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + int32_t count = 0; + + count = i2c_slave_read_t(&obj->my_i2c, (uint8_t *)data, length); + + return count; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + int32_t count = 0; + + count = i2c_slave_write_t(&obj->my_i2c, (uint8_t *)data, length); + + return count; +} + +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/objects.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/objects.h new file mode 100644 index 00000000000..e8e13768940 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/objects.h @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include +#include "PortNames.h" +#include "PeripheralNames.h" +#include "gpio_object.h" +#include "txzp_gpio.h" +#include "txzp_uart.h" +#include "txzp_tspi.h" +#include "txzp_t32a.h" +#include "txzp_cg.h" +#include "txzp_driver_def.h" +#include "txzp_adc.h" +#include "txzp_i2c_api.h" +#include "txzp_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct port_s { + uint32_t mask; + PortName port; +}; + + +struct serial_s { + uint32_t index; + uint32_t mode; + TSB_UART_TypeDef *UARTx; + uart_boudrate_t boud_obj; +}; + +struct pwmout_s { + uint32_t divisor; + uint32_t type; + uint32_t trailing_timing; + uint32_t leading_timing; + float period; + t32a_t p_t32a; + PinName pin; +}; + +struct spi_s { + uint8_t bits; + tspi_t p_obj; + SPIName module; + PinName clk_pin; + PinName ssel_pin; + IRQn_Type rxirqn; + IRQn_Type txirqn; + IRQn_Type errirqn; +#ifdef DEVICE_SPI_ASYNCH + uint32_t event_mask; + uint8_t state; +#endif +}; + +struct gpio_irq_s { + PortName port; + uint8_t pin_num; + uint32_t irq_id; + CG_INTSrc irq_src; + CG_INTActiveState event; +}; + +struct analogin_s { + adc_t p_adc; + PinName pin; + ADCName adc; + adc_channel_setting_t param; +}; + +struct i2c_s { + int address; + uint32_t index; + _i2c_t my_i2c; +}; + +struct flash_s { + int flash_inited; +}; + +#include "gpio_object.h" + +#define HAL_CRC_IS_SUPPORTED(polynomial, width) (((width) == 16 && (polynomial) == 0x1021) || \ + ((width) == 32 && (polynomial) == 0x04C11DB7)) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pinmap.c new file mode 100644 index 00000000000..a48eeb9d856 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pinmap.c @@ -0,0 +1,106 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "txzp_gpio.h" + +#define PIN_FUNC_MAX 7 + +extern _gpio_t gpio_port_add; + + +void pin_function(PinName pin, int function) +{ + uint32_t port = 0; + uint8_t bit = 0; + uint8_t func = 0; + uint8_t dir = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Calculate pin function and pin direction + func = PIN_FUNC(function); + dir = PIN_DIR(function); + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Find function is in range or not + if (func <= PIN_FUNC_MAX) { + // Set pin function and direction if direction is in range + switch (dir) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INOUT); + break; + default: + break; + } + } else { + // Do nothing + } +} + +void pin_mode(PinName pin, PinMode mode) +{ + uint32_t port = 0; + uint8_t bit = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Check if function is in range + if (mode > OpenDrain) { + return; + } + + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Set pin mode + switch (mode) { + case PullNone: + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PUP, GPIO_PIN_RESET); + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PDN, GPIO_PIN_RESET); + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_OD, GPIO_PIN_RESET); + + break; + case PullUp: + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PUP, GPIO_PIN_SET); + break; + case PullDown: + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PDN, GPIO_PIN_SET); + break; + case OpenDrain: + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_OD, GPIO_PIN_SET); + break; + default: + break; + } +} + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/port_api.c new file mode 100644 index 00000000000..dca3b31a1f1 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/port_api.c @@ -0,0 +1,145 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "txzp_gpio.h" +#include "pinmap.h" + +#define PORT_PIN_NUM (8) +#define ALT_FUNC_GPIO (0) + +extern _gpio_t gpio_port_add; +typedef struct port_s port_t; +static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num); + +PinName port_pin(PortName port, int pin_n) +{ + PinName pin = NC; + pin = (PinName)((port << 3) | pin_n); + return pin; +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(port <= PortV); + + // Store port and port mask for future use + obj->port = port; + obj->mask = mask; + + // Enable the clock for particular port + _gpio_init(&gpio_port_add, obj->port); + + // Set port function and port direction + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_function(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + + // Set mode for masked pins + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + + for (i = 0; i < PORT_PIN_NUM; i++) { + // Set direction for masked pins + if (obj->mask & (1 << i)) { + gpio_pin_dir(obj, dir, i); + } + } +} + +void port_write(port_t *obj, int value) +{ + uint32_t port_data = 0; + uint32_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + + // Get current data of port + gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); + + // Calculate data to write to masked pins + data = (port_data & ~obj->mask) | (value & obj->mask); + + // Write data to masked pins of the port + gpio_write_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, data); +} + +int port_read(port_t *obj) +{ + uint32_t port_data = 0; + uint32_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + + // Get current data of port + gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); + + // Calculate data of masked pins + data = port_data & obj->mask; + + return data; +} + +static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num) +{ + switch (dir) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INOUT); + break; + default: + // error("Invalid direction\n"); + break; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pwmout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pwmout_api.c new file mode 100644 index 00000000000..a83bd9be192 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pwmout_api.c @@ -0,0 +1,191 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pwmout_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" + +#define DUTY_CYCLE_INIT_VALUE 1 +#define CALCULATE_RGC1_VAL 2.4 + +static const PinMap PinMap_PWM[] = { + {PF4, PWM_0, PIN_DATA(5, 1)}, + {PU2, PWM_1, PIN_DATA(5, 1)}, + {PC2, PWM_2, PIN_DATA(6, 1)}, + {PN1, PWM_3, PIN_DATA(5, 1)}, + {NC, NC, 0} +}; + +void pwmout_init(pwmout_t *obj, PinName pin) +{ + // Determine the pwm channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + + // Assert input is valid + MBED_ASSERT(pwm != (PWMName)NC); + + switch (pwm) { + case PWM_0: + obj->p_t32a.p_instance = TSB_T32A1; + // Clock enable of T32A ch01 + TSB_CG_FSYSMENA_IPMENA29 = TXZ_ENABLE; + break; + case PWM_1: + obj->p_t32a.p_instance = TSB_T32A2; + // Clock enable of T32A ch02 + TSB_CG_FSYSMENA_IPMENA30 = TXZ_ENABLE; + break; + case PWM_2: + obj->p_t32a.p_instance = TSB_T32A3; + // Clock enable of T32A ch03 + TSB_CG_FSYSMENA_IPMENA31 = TXZ_ENABLE; + break; + case PWM_3: + obj->p_t32a.p_instance = TSB_T32A5; + // Clock enable of T32A ch05 + TSB_CG_FSYSMENB_IPMENB01 = TXZ_ENABLE; + break; + default: + obj->p_t32a.p_instance = NULL; + break; + } + + if (obj->p_t32a.p_instance == NULL) { + return; + } + + // Enable clock for GPIO port. + if (pwm == PWM_1) { + TSB_CG->FSYSMENA |= (TXZ_ENABLE << (PIN_PORT(pin) + 3)); + } else { + TSB_CG->FSYSMENA |= (TXZ_ENABLE << (PIN_PORT(pin))); + } + + // Set pin function as PWM + pinmap_pinout(pin, PinMap_PWM); + + // Default to 20ms, 0% duty cycle + // Assign same init value to trailing and leading timing duty cycle is zero. + pwmout_period_ms(obj, 20); +} + +void pwmout_free(pwmout_t *obj) +{ + // Stop PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + obj->trailing_timing = TXZ_DISABLE; + obj->leading_timing = TXZ_DISABLE; + obj->p_t32a.p_instance = NULL; +} + +void pwmout_write(pwmout_t *obj, float value) +{ + // Stop PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + + if (value <= 0.0f) { + value = TXZ_DISABLE; + } else if (value >= 1.0f) { + value = TXZ_ENABLE; + } + + // Store the new leading_timing value + obj->leading_timing = obj->trailing_timing - (obj->trailing_timing * value); + + // Setting T32A_RGA0 register + obj->p_t32a.p_instance->RGC0 = obj->leading_timing; + + // Start PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +float pwmout_read(pwmout_t *obj) +{ + float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing; + return duty_cycle; +} + +void pwmout_period(pwmout_t *obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0f)); +} + +void pwmout_period_ms(pwmout_t *obj, int ms) +{ + pwmout_period_us(obj, (ms * 1000)); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t *obj, int us) +{ + uint32_t prscl = 0; + float duty_cycle = 0; + float seconds = (float)((us) / 1000000.0f); + + obj->period = seconds; + // Restore the duty-cycle + duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing); + prscl = T32A_PRSCLx_32; + + obj->trailing_timing = (us * CALCULATE_RGC1_VAL); + obj->leading_timing = ((obj->trailing_timing) - (obj->trailing_timing * duty_cycle)); + + obj->p_t32a.p_instance->MOD = T32A_MODE_32; + obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + obj->p_t32a.p_instance->CRC = (prscl | T32A_RELOAD_TREGx); + obj->p_t32a.p_instance->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ | + T32A_IMx1_MASK_REQ | T32A_IMx0_MASK_REQ); + obj->p_t32a.p_instance->RGC0 = obj->leading_timing; + obj->p_t32a.p_instance->RGC1 = obj->trailing_timing; + obj->p_t32a.p_instance->OUTCRC0 = T32A_OCR_DISABLE; + obj->p_t32a.p_instance->OUTCRC1 = (T32A_OCRCMPx1_CLR | T32A_OCRCMPx0_SET); + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +int pwmout_read_period_us(pwmout_t *obj) +{ + return obj->trailing_timing; +} + +void pwmout_pulsewidth(pwmout_t *obj, float seconds) +{ + pwmout_pulsewidth_us(obj, (seconds * 1000000.0f)); +} + +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ + pwmout_pulsewidth_us(obj, (ms * 1000)); +} + +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + float seconds = 0; + float value = 0; + + seconds = (float)(us / 1000000.0f); + value = (((seconds / obj->period) * 100.0f) / 100.0f); + pwmout_write(obj, value); +} + +int pwmout_read_pulsewidth_us(pwmout_t *obj) +{ + return obj->trailing_timing - obj->leading_timing; +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/reset_reason_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/reset_reason_api.c new file mode 100644 index 00000000000..9786d3ca91a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/reset_reason_api.c @@ -0,0 +1,114 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2020 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "device.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "reset_reason_api.h" + +#define CLEAR_FLAGS (0) +//reset reason flag bit positions +#define PORSTF_FLAG (1<<0) +#define PINRSTF_FLAG (1<<3) +#define LVDRSTF_FLAG (1<<5) + +#define SYSRSTF_FLAG (1<<0) +#define LOCKRSTF_FLAG (1<<1) +#define WDTRSTF_FLAG (1<<2) +#define OFDRSTF_FLAG (1<<3) + + +reset_reason_t hal_reset_reason_get(void) +{ + reset_reason_t reason = RESET_REASON_UNKNOWN; + + //check if its power on reset, as it clears other flags to 0 or undefined state. + if (TSB_RLM->RSTFLG0 & PORSTF_FLAG) { + //set PINRSTF_FLAG and LVDRSTF_FLAG flags to 0 as they may be in undefined state after POR + TSB_RLM->RSTFLG0 &= ~(PINRSTF_FLAG | LVDRSTF_FLAG); + reason = RESET_REASON_POWER_ON; + } else { + //multiple reset reasons might occur if flags are not cleared in previous reset + //hence check all flags. + + if (TSB_RLM->RSTFLG0 & PINRSTF_FLAG) { + reason = RESET_REASON_PIN_RESET; + } + + if (TSB_RLM->RSTFLG0 & LVDRSTF_FLAG) { + reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_BROWN_OUT : RESET_REASON_MULTIPLE; + } + + // check 2nd reset reason register + + if (TSB_RLM->RSTFLG1 & SYSRSTF_FLAG) { + reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_SOFTWARE : RESET_REASON_MULTIPLE; + } + + if (TSB_RLM->RSTFLG1 & LOCKRSTF_FLAG) { + reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_LOCKUP : RESET_REASON_MULTIPLE; + } + + if (TSB_RLM->RSTFLG1 & WDTRSTF_FLAG) { + reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_WATCHDOG : RESET_REASON_MULTIPLE; + } + + if (TSB_RLM->RSTFLG1 & OFDRSTF_FLAG) { + reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_PLATFORM : RESET_REASON_MULTIPLE; + } + } + + return reason; +} + +void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap) +{ + cap->reasons = 1 << RESET_REASON_UNKNOWN; + cap->reasons |= 1 << RESET_REASON_POWER_ON; + cap->reasons |= 1 << RESET_REASON_PIN_RESET; + cap->reasons |= 1 << RESET_REASON_BROWN_OUT; + cap->reasons |= 1 << RESET_REASON_SOFTWARE; + cap->reasons |= 1 << RESET_REASON_LOCKUP; + cap->reasons |= 1 << RESET_REASON_WATCHDOG; + cap->reasons |= 1 << RESET_REASON_PLATFORM; + cap->reasons |= 1 << RESET_REASON_MULTIPLE; +} + +uint32_t hal_reset_reason_get_raw(void) +{ + uint32_t reason_raw = 0; + //check if its power on reset, as it clears other flags to 0 or undefined state. + if (TSB_RLM->RSTFLG0 & PORSTF_FLAG) { + //set PINRSTF_FLAG and LVDRSTF_FLAG flags to 0 as they may be in undefined state after POR + TSB_RLM->RSTFLG0 &= ~(PINRSTF_FLAG | LVDRSTF_FLAG); + } + + //concatenating RSTFLG1 and RSTFLG0 register contents + reason_raw = ((TSB_RLM->RSTFLG1) << 8) | TSB_RLM->RSTFLG0 ; + return reason_raw; +} + + + +void hal_reset_reason_clear(void) +{ + //clear both reset reason registers RSTFLG1 and RSTFLG0 + TSB_RLM->RSTFLG0 = CLEAR_FLAGS; + TSB_RLM->RSTFLG1 = CLEAR_FLAGS; +} + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/serial_api.c new file mode 100644 index 00000000000..42fec3034ff --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/serial_api.c @@ -0,0 +1,363 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "mbed_error.h" +#include "serial_api.h" +#include "pinmap.h" +#include "txzp_cg.h" +#include "uart_spi_interrupts.h" + +#define UART_NUM 4 +#define UART_ENABLE_RX ((uint32_t)0x00000001) +#define UART_ENABLE_TX ((uint32_t)0x00000002) +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) +#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) +#define BAUDRATE_DEFAULT (9600) +#define CLR_REGISTER (0x00) + + +serial_t stdio_uart; +int stdio_uart_inited = 0; +static int serial_irq_ids[UART_NUM] = {0}; +static void uart_swreset(TSB_UART_TypeDef *UARTx); +static uart_irq_handler irq_handler; +void invoke_serial_irq_handler(UARTName uart_name, SerialIrq event); + + +static const PinMap PinMap_UART_TX[] = { + {PC0, SERIAL_0, PIN_DATA(1, 1)}, + {PC4, SERIAL_1, PIN_DATA(1, 1)}, + {PU0, SERIAL_2, PIN_DATA(1, 1)}, + {PF6, SERIAL_3, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {PC1, SERIAL_0, PIN_DATA(1, 0)}, + {PC5, SERIAL_1, PIN_DATA(1, 0)}, + {PU1, SERIAL_2, PIN_DATA(1, 0)}, + {PF7, SERIAL_3, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + int is_stdio_uart = 0; + obj->mode = 0; + cg_t paramCG; + paramCG.p_instance = TSB_CG; + uart_clock_t prescal = {0}; + + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); + + MBED_ASSERT((int)uart_name != NC); + obj->index = uart_name; + + switch (uart_name) { + case SERIAL_0: + obj->UARTx = TSB_UART0; + // Enable clock for UART0 and Port N + TSB_CG_FSYSMENA_IPMENA21 = TXZ_ENABLE;//for uart + TSB_CG_FSYSMENA_IPMENA02 = TXZ_ENABLE; + break; + case SERIAL_1: + obj->UARTx = TSB_UART1; + // Enable clock for UART1 and Port C + TSB_CG_FSYSMENA_IPMENA22 = TXZ_ENABLE; + TSB_CG_FSYSMENA_IPMENA02 = TXZ_ENABLE; + break; + case SERIAL_2: + obj->UARTx = TSB_UART2; + // Enable clock for UART2 and Port U + TSB_CG_FSYSMENA_IPMENA23 = TXZ_ENABLE; + TSB_CG_FSYSMENA_IPMENA16 = TXZ_ENABLE; + break; + case SERIAL_3: + obj->UARTx = TSB_UART3; + // Enable clock for UART3 and Port F + TSB_CG_FSYSMENA_IPMENA24 = TXZ_ENABLE; + TSB_CG_FSYSMENA_IPMENA05 = TXZ_ENABLE; + break; + default: + break; + } +// Set alternate function + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC && rx != NC) { + obj->mode = UART_ENABLE_RX | UART_ENABLE_TX; + } else { + if (tx != NC) { + obj->mode = UART_ENABLE_TX; + } else { + if (rx != NC) { + obj->mode = UART_ENABLE_RX; + } + } + } + // Software reset + uart_swreset(obj->UARTx); + + obj->UARTx->CR0 |= (1U); // Data lengh 8 bit No parity one stop bit + prescal.prsel = UART_PLESCALER_1; + uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, BAUDRATE_DEFAULT, &obj->boud_obj); + + obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn));// buad rate register(ken is from 23 but not shifted??) + obj->UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); // Clear FIFO + obj->UARTx->TRANS |= obj->mode; // Enable TX RX block. + obj->UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL); + + is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } + +} + +void serial_free(serial_t *obj) +{ + obj->UARTx->TRANS = CLR_REGISTER; + obj->UARTx->CR0 = CLR_REGISTER; + obj->UARTx->CR1 = CLR_REGISTER; + obj->UARTx = CLR_REGISTER; + uart_swreset(obj->UARTx); + obj->index = (uint32_t)NC; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + cg_t paramCG; + paramCG.p_instance = TSB_CG; + uart_clock_t prescal; + prescal.prsel = UART_PLESCALER_1; + uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, baudrate, &obj->boud_obj); + obj->UARTx->BRD = CLR_REGISTER; // Clear BRD register + obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + uint32_t parity_check = 0; + uint32_t data_length = 0; + uint32_t tmp = 0; + uint32_t sblen = 0; + + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); + MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits + + parity_check = ((parity == ParityOdd) ? 1 : ((parity == ParityEven) ? 3 : 0)); + data_length = (data_bits == 8 ? 1 : ((data_bits == 7) ? 0 : 2)); + sblen = (stop_bits == 1) ? 0 : 1; // 0: 1 stop bits, 1: 2 stop bits + tmp = ((sblen << 4) | (parity_check << 2) | data_length); + obj->UARTx->CR0 = tmp; +} + + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + + +void invoke_serial_irq_handler(UARTName uart_name, SerialIrq event) +{ + irq_handler(serial_irq_ids[uart_name], event); +} + + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + IRQn_Type irq_n = (IRQn_Type)0; + + if (enable) { + obj->UARTx->CR1 |= ((irq == RxIrq) ? UART_RX_INT_ENABLE : UART_TX_INT_ENABLE); + } else { + obj->UARTx->CR1 &= ((irq == RxIrq) ? (~(UART_RX_INT_ENABLE)) : (~(UART_TX_INT_ENABLE))); + } + + switch (obj->index) { + case SERIAL_0: + if (irq == RxIrq) { + irq_n = INTSC0RX_IRQn; + } else { + irq_n = INTSC0TX_IRQn; + } + break; + case SERIAL_1: + if (irq == RxIrq) { + irq_n = INTSC1RX_IRQn; + } else { + irq_n = INTSC1TX_IRQn; + } + break; + case SERIAL_2: + if (irq == RxIrq) { + irq_n = INTSC2RX_IRQn; + } else { + irq_n = INTSC2TX_IRQn; + } + break; + case SERIAL_3: + if (irq == RxIrq) { + irq_n = INTSC3RX_IRQn; + } else { + irq_n = INTSC3TX_IRQn; + } + break; + + default: + break; + } + + //NVIC_ClearPendingIRQ(irq_n); + uart_spi_clear_pending_irq(irq_n); + + if (enable) { + //NVIC_EnableIRQ(irq_n); + uart_spi_enable_irq(irq_n, UART_PERIPH); + } else { + //NVIC_DisableIRQ(irq_n); + uart_spi_disable_irq(irq_n, UART_PERIPH); + } +} + + +int serial_getc(serial_t *obj) +{ + int data = 0; + + while (!serial_readable(obj)) { // Wait until Rx buffer is full + // Do nothing + } + + // Read Data Register + data = (obj->UARTx->DR & 0xFFU); + obj->UARTx->SR |= (1U << 6); // Clear RXEND flag + + return data; +} + +void serial_putc(serial_t *obj, int c) +{ + while (!serial_writable(obj)) { + // Do nothing + } + + // Write Data Register + obj->UARTx->DR = (c & 0xFF); + + while ((obj->UARTx->SR & (1U << 14)) == 0) { + // Do nothing + } + + obj->UARTx->SR |= (1U << 14); // Clear TXEND flag +} + + +int serial_readable(serial_t *obj) +{ + int ret = 0; + + if ((obj->UARTx->SR & 0x000F) != 0) { + ret = 1; + } + + return ret; +} + +int serial_writable(serial_t *obj) +{ + int ret = 0; + + if ((obj->UARTx->SR & 0x8000) == 0) { + ret = 1; + } + + return ret; +} + +// Pause transmission +void serial_break_set(serial_t *obj) +{ + obj->UARTx->TRANS |= 0x08; +} + +// Switch to normal transmission +void serial_break_clear(serial_t *obj) +{ + obj->UARTx->TRANS &= ~(0x08); +} + +static void uart_swreset(TSB_UART_TypeDef *UARTx) +{ + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } + + UARTx->SWRST = UARTxSWRST_SWRST_10; + UARTx->SWRST = UARTxSWRST_SWRST_01; + + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } + +} +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ +#if !DEVICE_SERIAL_FC + static const PinMap PinMap_UART_CTS[] = { + {NC, NC, 0} + }; +#endif + + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ +#if !DEVICE_SERIAL_FC + static const PinMap PinMap_UART_RTS[] = { + {NC, NC, 0} + }; +#endif + + return PinMap_UART_RTS; +} + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/sleep.c new file mode 100644 index 00000000000..c62b062d808 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/sleep.c @@ -0,0 +1,128 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" + +// Number of warm-up cycle in EHOSC = (warming up time (s) / clock period (s)) - 16 +#define CG_WUODR_EXT_5MS ((uint16_t)0xC340) +// Number of warm-up cycle in IHOSC = ((warming up time (s) – 63.3(μs) / clock period (s)) - 41 +#define CG_WUODR_INT_67_4us ((uint16_t)0x0000) +#define CG_STBY_MODE_IDLE 0x0 +#define CG_STBY_MODE_STOP1 0x1 +#define EXTERNEL_OSC_MASK 0xFFFFFFF1 +#define SIWDT_DISABLE 0xB1 +#define WUPT_LOWER_MASK 0x000F +#define WUPT_UPPER_MASK 0xFFF0 + +static void external_hosc_enable(void); + +void hal_sleep(void) +{ + // Set low power consumption mode IDLE + TSB_CG->STBYCR = CG_STBY_MODE_IDLE; + + // Enter idle mode + __DSB(); + __WFI(); +} + +void hal_deepsleep(void) +{ + uint32_t wupt_lower = 0; + uint32_t wupt_upper = 0; + uint32_t tmp = 0; + + TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE; + + TSB_SIWD0->EN = TXZ_DISABLE; + TSB_SIWD0->CR = SIWDT_DISABLE; + + + while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) { + // Flash wait + } + + while (TSB_CG_WUPHCR_WUEF) { + // Wait for end of Warming-up for IHOSC1 + } + + TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE; + wupt_lower = ((CG_WUODR_INT_67_4us & WUPT_LOWER_MASK) << 16U); + wupt_upper = ((CG_WUODR_INT_67_4us & WUPT_UPPER_MASK) << 16U); + TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); + TSB_CG->STBYCR = CG_STBY_MODE_STOP1; + TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE; + + + while (TSB_CG_PLL0SEL_PLL0ST) { + // Wait for PLL status of fsys until off state(fosc=0) + } + + // Stop PLL of fsys + TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE; + TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE; + TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE; + + while (TSB_CG_OSCCR_OSCF) { + // Wait for fosc status until IHOSC1 = 0 + } + + tmp = TSB_CG->OSCCR; + tmp &= EXTERNEL_OSC_MASK; + TSB_CG->OSCCR = tmp; + + + // Enter stop1 mode + __DSB(); + __WFI(); + + // Switch over from IHOSC to EHOSC + // After coming out off sleep mode, Restore the clock setting to EHOSC. + external_hosc_enable(); +} + +static void external_hosc_enable(void) +{ + uint32_t wupt_lower = 0; + uint32_t wupt_upper = 0; + + // Enable high-speed oscillator + TSB_CG->OSCCR |= (TXZ_ENABLE << 1); + + // Select internal(fIHOSC) as warm-up clock + wupt_lower = ((CG_WUODR_EXT_5MS & WUPT_LOWER_MASK) << 16U); + wupt_upper = ((CG_WUODR_EXT_5MS & WUPT_UPPER_MASK) << 16U); + TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); + + // Start warm-up + TSB_CG->WUPHCR |= TXZ_ENABLE; + + // Wait until EHOSC become stable + while ((TSB_CG->WUPHCR & 0x0002)) { + // Do nothing + } + + // Set fosc source + TSB_CG->OSCCR |= (1 << 8); + + // Wait for to become "1" + while (!((TSB_CG->OSCCR & 0x200) >> 9)) { + // Do nothing + } + + // Stop IHOSC + TSB_CG->OSCCR &= ~TXZ_ENABLE; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/spi_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/spi_api.c new file mode 100644 index 00000000000..d0a7220fa68 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/spi_api.c @@ -0,0 +1,356 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "spi_api.h" +#include "mbed_error.h" +#include "txzp_tspi.h" +#include "pinmap.h" + +#define TIMEOUT (5000) + +static const PinMap PinMap_SPI_MOSI[] = { + {PA3, SPI_0, PIN_DATA(1, 1)}, + {PG5, SPI_1, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {PA2, SPI_0, PIN_DATA(1, 0)}, + {PG4, SPI_1, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SCLK[] = { + {PA4, SPI_0, PIN_DATA(1, 1)}, + {PG6, SPI_1, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SLAVE_SCLK[] = { + {PA4, SPI_0, PIN_DATA(1, 0)}, + {PG6, SPI_1, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {PA1, SPI_0, PIN_DATA(1, 1)}, + {PG1, SPI_1, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SLAVE_SSEL[] = { + {PA0, SPI_0, PIN_DATA(1, 0)}, + {PG3, SPI_1, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Check pin parameters + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + obj->module = (SPIName)pinmap_merge(spi_mosi, spi_miso); + + MBED_ASSERT((int)obj->module != NC); + + obj->clk_pin = sclk; + obj->ssel_pin = ssel; + + // Identify SPI module to use + switch ((int)obj->module) { + case SPI_0: + obj->p_obj.p_instance = TSB_TSPI0; + // Enable clock for particular Port and SPI + TSB_CG_FSYSMENA_IPMENA00 = TXZ_ENABLE; + TSB_CG_FSYSMENA_IPMENA19 = TXZ_ENABLE; + break; + case SPI_1: + obj->p_obj.p_instance = TSB_TSPI1; + // Enable clock for particular Port and SPI + TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE; + TSB_CG_FSYSMENA_IPMENA20 = TXZ_ENABLE; + break; + default: + obj->p_obj.p_instance = NULL; + obj->module = (SPIName)NC; + error("Cannot found SPI module corresponding with input pins."); + break; + } + + // Pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + + // Default configurations 8 bit, 1Mhz frequency + // Control 1 configurations + obj->p_obj.init.id = (uint32_t)obj->module; + obj->p_obj.init.cnt1.inf = TSPI_INF_DISABLE; // Infinite Transfer Control disabled + obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled + obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication + obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode + obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPERATION; // Master mode operation + obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive) + obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_CONTINUE; // Transfer single frame at a time continously + + // Control 2 configurations + obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI; + obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // When slave underruns TxD fixed to low + obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_FSYS_FSCK_16; + obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // Transmit FIFO Level + obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // Receive FIFO Level + obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE; + obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE; + obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE; + obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE; + obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE; + obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE; + obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE; + + // Control 3 configurations + obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // Transmit buffer clear + obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // Receive buffer clear + + // Baudrate settings - 1 Mhz default + obj->p_obj.init.brd.brck = TSPI_BR_CLOCK_4; + obj->p_obj.init.brd.brs = TSPI_BR_DIVIDER_10; + + // Format Control 0 settings + obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first + obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8; + obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0; + + // Special control on polarity of signal and generation timing + obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE; + obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE; + obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE; + obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE; + + obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1; + obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1; + obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1; + + // Format Control 1 settings tspi_fmtr1_t + obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE; + obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD; + + obj->p_obj.init.sectcr0.sect = TSPI_SECTCR0_SECT_FRAME_MODE; + + obj->bits = (uint8_t)TSPI_DATA_LENGTH_8; + + // Initialize SPI + tspi_init(&obj->p_obj); +} + +void spi_free(spi_t *obj) +{ + tspi_deinit(&obj->p_obj); + obj->module = (SPIName)NC; +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode + MBED_ASSERT((bits >= 8) && (bits <= 32)); + + obj->bits = bits; + obj->p_obj.init.fmr0.fl = (bits << 24); + + if (slave) { + pinmap_pinout(obj->clk_pin, PinMap_SPI_SLAVE_SCLK); + pinmap_pinout(obj->ssel_pin, PinMap_SPI_SLAVE_SSEL); + obj->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation + } else { + pinmap_pinout(obj->clk_pin, PinMap_SPI_SCLK); + pinmap_pinout(obj->ssel_pin, PinMap_SPI_SSEL); + obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPERATION; // Master mode operation + } + + if ((mode >> 1) & 0x1) { + obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI; + } else { + obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + } + + if (mode & 0x1) { + obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE; + } else { + obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + } + + tspi_init(&obj->p_obj); +} + +void spi_frequency(spi_t *obj, int hz) +{ + SystemCoreClockUpdate(); + uint8_t brs = 0; + uint8_t brck = 0; + uint16_t prsck = 1; + uint64_t fscl = 0; + uint64_t tmp_fscl = 0; + uint64_t fx = 0; + uint64_t tmpvar = SystemCoreClock / 2; + + for (prsck = 1; prsck <= 512; prsck *= 2) { + fx = ((uint64_t)tmpvar / prsck); + for (brs = 1; brs <= 16; brs++) { + fscl = fx / brs; + if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + obj->p_obj.init.brd.brck = (brck << 4); + if (brs == 16) { + obj->p_obj.init.brd.brs = 0; + } else { + obj->p_obj.init.brd.brs = brs; + } + } + } + brck ++; + } + + tspi_init(&obj->p_obj); +} + +int spi_master_write(spi_t *obj, int value) +{ + uint8_t ret_value = 0; + + tspi_transmit_t send_obj; + tspi_receive_t rec_obj; + + // Transmit data + send_obj.tx8.p_data = (uint8_t *)&value; + send_obj.tx8.num = 1; + tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT); + + // Read received data + rec_obj.rx8.p_data = &ret_value; + rec_obj.rx8.num = 1; + tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT); + + return ret_value; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) +{ + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +int spi_slave_receive(spi_t *obj) +{ + if ((obj->p_obj.p_instance->SR & 0x0F) != 0) { + return 1; + } + + return 0; +} + +int spi_slave_read(spi_t *obj) +{ + + uint8_t ret_value = 0; + + ret_value = obj->p_obj.p_instance->DR & 0xFF; + obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + + return ret_value; +} + +void spi_slave_write(spi_t *obj, int value) +{ + if ((obj->p_obj.p_instance->CR1 & TSPI_TX_ONLY) != TSPI_TX_ONLY) { //Enable TX if not Enabled + obj->p_obj.p_instance->CR1 |= TSPI_TX_ONLY; + } + + obj->p_obj.p_instance->DR = (uint8_t)(value * 0xFF); + + obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + +} + +int spi_busy(spi_t *obj) +{ + int ret = 1; + uint32_t status = 0; + + tspi_get_status(&obj->p_obj, &status); + + if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) { + ret = 0; + } + + return ret; +} + + +uint8_t spi_get_module(spi_t *obj) +{ + return (uint8_t)(obj->module); +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SLAVE_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SLAVE_SSEL; +} + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.c new file mode 100644 index 00000000000..ee0640cec87 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.c @@ -0,0 +1,281 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "serial_api.h" +#include "uart_spi_interrupts.h" + +//The UART and TSPI in M4KNA target have shared irq lines. For this reason we have to maintain shared irq handlers. +// Also enable/disable of these shared IRQ lines from NVIC need to be controlled carefully to avoid loss of interrupt when +// any one peripheral disables/enables interrupt. For this reason IRQ related code is seperated from peripheral driver apis and +// maintained separately in this source file. + +#define CHANNEL_COUNT (4) + +extern void invoke_serial_irq_handler(UARTName uart_name, SerialIrq event); +typedef struct { + int ch0_tx_uart: 1; + int ch0_tx_spi: 1; + int ch0_rx_uart: 1; + int ch0_rx_spi: 1; + + int ch1_tx_uart: 1; + int ch1_tx_spi: 1; + int ch1_rx_uart: 1; + int ch1_rx_spi: 1; + + int ch2_tx_uart: 1; + int ch2_tx_spi: 1; + int ch2_rx_uart: 1; + int ch2_rx_spi: 1; + + int ch3_tx_uart: 1; + int ch3_tx_spi: 1; + int ch3_rx_uart: 1; + int ch3_rx_spi: 1; +} shared_nvic_irq_status; + +shared_nvic_irq_status shared_irqs; + +// IRQ Handlers shared by both SPI and UART + +void INTSC0RX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_0, RxIrq); +} + +void INTSC0TX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_0, TxIrq); +} + +void INTSC1RX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_1, RxIrq); +} + +void INTSC1TX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_1, TxIrq); +} + +void INTSC2RX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_2, RxIrq); +} + +void INTSC2TX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_2, TxIrq); +} + +void INTSC3RX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_3, RxIrq); +} + +void INTSC3TX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_3, TxIrq); +} + + + +void uart_spi_clear_pending_irq(IRQn_Type irq) +{ + if (NVIC_GetEnableIRQ(irq) == 0) { + NVIC_ClearPendingIRQ(irq); + } +} + + + +void uart_spi_enable_irq(IRQn_Type irq, int uart_spi_device) +{ + if (NVIC_GetEnableIRQ(irq) == 0) { + NVIC_EnableIRQ(irq); + } + + switch (irq) { + case INTSC0RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch0_rx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch0_rx_spi = TXZ_ENABLE; + } + break; + case INTSC0TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch0_tx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch0_tx_spi = TXZ_ENABLE; + } + break; + case INTSC1RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch1_rx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch1_rx_spi = TXZ_ENABLE; + } + break; + case INTSC1TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch1_tx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch1_tx_spi = TXZ_ENABLE; + } + break; + case INTSC2RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch2_rx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch2_rx_spi = TXZ_ENABLE; + } + break; + case INTSC2TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch2_tx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch2_tx_spi = TXZ_ENABLE; + } + break; + case INTSC3RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch3_rx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch3_rx_spi = TXZ_ENABLE; + } + break; + case INTSC3TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch3_tx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch3_tx_spi = TXZ_ENABLE; + } + break; + + default: + break; + + } +} + + + + +void uart_spi_disable_irq(IRQn_Type irq, int uart_spi_device) +{ + int disable_flag = 0; + + switch (irq) { + case INTSC0RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch0_rx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch0_rx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch0_rx_uart || shared_irqs.ch0_rx_spi)) { + disable_flag = 1; + } + break; + case INTSC0TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch0_tx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch0_tx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch0_tx_uart || shared_irqs.ch0_tx_spi)) { + disable_flag = 1; + } + break; + case INTSC1RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch1_rx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch1_rx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch1_rx_uart || shared_irqs.ch1_rx_spi)) { + disable_flag = 1; + } + break; + case INTSC1TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch1_tx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch1_tx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch1_tx_uart || shared_irqs.ch1_tx_spi)) { + disable_flag = 1; + } + break; + case INTSC2RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch2_rx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch2_rx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch2_rx_uart || shared_irqs.ch2_rx_spi)) { + disable_flag = 1; + } + break; + case INTSC2TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch2_tx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch2_tx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch2_tx_uart || shared_irqs.ch2_tx_spi)) { + disable_flag = 1; + } + break; + case INTSC3RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch3_rx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch3_rx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch3_rx_uart || shared_irqs.ch3_rx_spi)) { + disable_flag = 1; + } + break; + case INTSC3TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch3_tx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch3_tx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch3_tx_uart || shared_irqs.ch3_tx_spi)) { + disable_flag = 1; + } + break; + + default: + break; + } + + if (disable_flag) { + NVIC_DisableIRQ(irq); + } +} + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.h new file mode 100644 index 00000000000..51962b6c594 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.h @@ -0,0 +1,29 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef TARGETS_TARGET_TOSHIBA_TARGET_TMPM4KNA_UART_SPI_INTERRUPTS_H_ +#define TARGETS_TARGET_TOSHIBA_TARGET_TMPM4KNA_UART_SPI_INTERRUPTS_H_ + +#define SPI_PEPIRH (0) +#define UART_PERIPH (1) + +void uart_spi_clear_pending_irq(IRQn_Type irq); +void uart_spi_enable_irq(IRQn_Type irq, int uart_spi_device); +void uart_spi_disable_irq(IRQn_Type irq, int uart_spi_device); + + +#endif /* TARGETS_TARGET_TOSHIBA_TARGET_TMPM4KNA_UART_SPI_INTERRUPTS_H_ */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/us_ticker.c new file mode 100644 index 00000000000..52478673b5b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/us_ticker.c @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "us_ticker_api.h" +#include "txzp_t32a.h" +#include "TMPM4KNA.h" + + +static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? + + +const ticker_info_t *us_ticker_get_info() +{ + static const ticker_info_t info = { + 2500000, + 32 + }; + return &info; +} +// Initialize us_ticker +void us_ticker_init(void) +{ + if (us_ticker_inited) { + us_ticker_disable_interrupt(); + return; + } + us_ticker_inited = 1; + TSB_CG_FSYSMENA_IPMENA28 = TXZ_ENABLE; + + // Configure Timer T32A0 + TSB_T32A0->MOD = T32A_MODE_32; + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->CRC = T32A_PRSCLx_32; + TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); + + NVIC_SetVector(INTT32A00AC_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(INTT32A00AC_IRQn); +} + +uint32_t us_ticker_read(void) +{ + uint32_t ret_val = 0; + + if (!us_ticker_inited) { + us_ticker_init(); + } + + ret_val = (TSB_T32A0->TMRC); + return ret_val; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + NVIC_DisableIRQ(INTT32A00AC_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->RGC1 = timestamp ; + NVIC_EnableIRQ(INTT32A00AC_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(INTT32A00AC_IRQn); + NVIC_EnableIRQ(INTT32A00AC_IRQn); +} + +void us_ticker_disable_interrupt(void) +{ + NVIC_ClearPendingIRQ(INTT32A00AC_IRQn); + NVIC_DisableIRQ(INTT32A00AC_IRQn); +} + +void us_ticker_clear_interrupt(void) +{ + NVIC_ClearPendingIRQ(INTT32A00AC_IRQn); +} + +void us_ticker_free(void) +{ + TSB_T32A0->RUNC = T32A_RUN_DISABLE; + NVIC_ClearPendingIRQ(INTT32A00AC_IRQn); + NVIC_DisableIRQ(INTT32A00AC_IRQn); + TSB_CG_FSYSMENA_IPMENA28 = TXZ_DISABLE; +} diff --git a/targets/TARGET_TOSHIBA/mbed_rtx.h b/targets/TARGET_TOSHIBA/mbed_rtx.h index 2110efe8dea..3c62f5be8d7 100644 --- a/targets/TARGET_TOSHIBA/mbed_rtx.h +++ b/targets/TARGET_TOSHIBA/mbed_rtx.h @@ -36,4 +36,12 @@ #endif +#if defined(TARGET_TMPM4KN) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20006000UL) +#endif + +#endif + #endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index f4d4055553f..3527f802dde 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8945,5 +8945,46 @@ "__build_tools_metadata__": { "version": "1", "public": false + }, + "TMPM4KN": { + "inherits": ["Target"], + "core": "Cortex-M4F", + "is_disk_virtual": true, + "extra_labels": ["TOSHIBA"], + "macros": ["__TMPM4KN__"], + "supported_toolchains": ["GCC_ARM","ARMC6"], + "device_has": [ + "ANALOGIN", + "INTERRUPTIN", + "CRC", + "I2C", + "I2CSLAVE", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "RESET_REASON", + "SERIAL", + "SLEEP", + "SPI", + "SPISLAVE", + "USTICKER", + "STDIO_MESSAGES", + "MPU", + "FLASH" + ], + "device_name": "TMPM4KNFYAFG", + "detect_code": ["7020"], + "release_versions": ["5"], + "bootloader_supported": true, + "supported_application_profiles" : ["full"], + "supported_c_libs": { + "arm": [ + "std" + ], + "gcc_arm": [ + "std" + ] + } } } diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index 1a37a0aee90..24be21c5376 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -504913,7 +504913,83 @@ ], "sub_family": "M4K(1)", "vendor": "Toshiba:92" - }, + }, + "TMPM4KNFYAFG": { + "name": "TMPM4KNFYAFG", + "memories": { + "IROM1": { + "access": { + "read": true, + "write": false, + "execute": true, + "peripheral": false, + "secure": false, + "non_secure": false, + "non_secure_callable": false + }, + "start": 0, + "size": 262144, + "startup": true, + "default": true + }, + "IRAM1": { + "access": { + "read": true, + "write": true, + "execute": false, + "peripheral": false, + "secure": false, + "non_secure": false, + "non_secure_callable": false + }, + "start": 536870912, + "size": 24576, + "startup": false, + "default": true + } + }, + "algorithms": [ + { + "file_name": "Flash/TMPM4Kx_code_256.FLM", + "start": 0, + "size": 262144, + "default": true, + "ram_start": 536870912, + "ram_size": 8192 + }, + { + "file_name": "Flash/TMPM4Kx_data_32.FLM", + "start": 805306368, + "size": 32768, + "default": true, + "ram_start": 536870912, + "ram_size": 8192 + } + ], + "processor": { + "Symmetric": { + "units": 1, + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present" + } + }, + "from_pack": { + "vendor": "Toshiba", + "pack": "TXZ4Aplus-M4K2_DFP", + "version": "1.0.0", + "url": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/" + }, + "sectors": [ + [ + 0, + 32768 + ] + ], + "vendor": "Toshiba:92", + "family": "TXZ4A+ Series", + "sub_family": "M4K(2)" + }, "XMC1100-Q024x0008": { "algorithms": [ {