@@ -3571,6 +3571,20 @@ typedef struct
35713571 tmpreg = READ_BIT (RCC -> AHB1ENR , RCC_AHB1ENR_GPIOEEN );\
35723572 UNUSED (tmpreg ); \
35733573 } while (0U )
3574+ #define __HAL_RCC_GPIOF_CLK_ENABLE () do { \
3575+ __IO uint32_t tmpreg = 0x00U; \
3576+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
3577+ /* Delay after an RCC peripheral clock enabling */ \
3578+ tmpreg = READ_BIT (RCC -> AHB1ENR , RCC_AHB1ENR_GPIOFEN );\
3579+ UNUSED (tmpreg ); \
3580+ } while (0U )
3581+ #define __HAL_RCC_GPIOG_CLK_ENABLE () do { \
3582+ __IO uint32_t tmpreg = 0x00U; \
3583+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
3584+ /* Delay after an RCC peripheral clock enabling */ \
3585+ tmpreg = READ_BIT (RCC -> AHB1ENR , RCC_AHB1ENR_GPIOGEN );\
3586+ UNUSED (tmpreg ); \
3587+ } while (0U )
35743588#define __HAL_RCC_CRC_CLK_ENABLE () do { \
35753589 __IO uint32_t tmpreg = 0x00U; \
35763590 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
@@ -4722,7 +4736,7 @@ typedef struct
47224736/*----------------------------------------------------------------------------*/
47234737
47244738/*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/
4725- #if defined(STM32F412Zx ) || defined(STM32F412Vx ) || defined(STM32F412Rx ) || defined(STM32F412Cx ) || defined(STM32F413xx ) || defined(STM32F423xx )
4739+ #if defined(STM32F412Zx ) || defined(STM32F412Vx ) || defined(STM32F412Rx ) || defined(STM32F412Cx ) || defined(STM32F413xx ) || defined(STM32F423xx )
47264740/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
47274741 * @brief Enables or disables the AHB1 peripheral clock.
47284742 * @note After reset, the peripheral clock (used for registers read/write access)
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