- whitespace

Author: mbs-octoml

python/tvm/target/compilation_config.py

@@ -23,5 +23,5 @@ def make_compilation_config(ctxt, target, target_host=None):
     """Returns a CompilationConfig appropriate for target and target_host, using the same
     representation conventions as for the standard build interfaces. Intended only for unit
     testing."""
-    raw_targets=tvm.target.Target.canonicalize_target_and_host(target, target_host)
+    raw_targets = tvm.target.Target.canonicalize_target_and_host(target, target_host)
     return _ffi_api.MakeCompilationConfig(ctxt, raw_targets)

python/tvm/target/target.py

@@ -619,7 +619,7 @@ def get_arch_version(cpu_ver):
     # Check for valid codegen cpu
     valid_hex = ["v65", "v66", "v67", "v67t", "v68", "v69"]
     try:
-        cpu_ver = cpu_ver[cpu_ver.index("v"):].lower()
+        cpu_ver = cpu_ver[cpu_ver.index("v") :].lower()
         assert cpu_ver in valid_hex
     except:
         msg = "{} is not a valid Hexagon version\nvalid versions include {}"
@@ -687,7 +687,7 @@ def validate_hvx_length(codegen_hvx, sim_options):
                 # If --hvx_length was specified, check HVX length of sim
                 # vs codegen
                 i = sim_options.index("hvx_length") + len("hvx_length") + 1
-                sim_hvx = sim_options[i: i + 3]
+                sim_hvx = sim_options[i : i + 3]
                 if sim_hvx != str(codegen_hvx):
                     msg = "sim hvx {} and codegen hvx {} mismatch!".format(sim_hvx, codegen_hvx)
                     # Set the stacklevel to the tvm.target.hexagon() call.
@@ -715,9 +715,9 @@ def validate_hvx_length(codegen_hvx, sim_options):
 
             # Regex match for allowed cpus
             valid_cpu_str_regex = (
-                    r"(?P<pre>--.*\s)?(--m)?"
-                    + r"(?P<base_version>v6[25678])(?P<sub_version>[a-z])?"
-                    + r"(?P<l2_size>_[0-9]+)?(?P<rev>_rev[0-9])?\s?(?P<post>--.*)?"
+                r"(?P<pre>--.*\s)?(--m)?"
+                + r"(?P<base_version>v6[25678])(?P<sub_version>[a-z])?"
+                + r"(?P<l2_size>_[0-9]+)?(?P<rev>_rev[0-9])?\s?(?P<post>--.*)?"
             )
             m = re.match(valid_cpu_str_regex, sim_options.lower())
             if not m:
@@ -726,13 +726,13 @@ def validate_hvx_length(codegen_hvx, sim_options):
             # Parse options into correct order
             cpu_attr = {x: str(m.groupdict()[x] or "") for x in m.groupdict()}
             sim_options = (
-                    cpu_attr["base_version"]
-                    + cpu_attr["sub_version"]
-                    + cpu_attr["l2_size"]
-                    + cpu_attr["rev"]
-                    + " "
-                    + cpu_attr["pre"]
-                    + cpu_attr["post"]
+                cpu_attr["base_version"]
+                + cpu_attr["sub_version"]
+                + cpu_attr["l2_size"]
+                + cpu_attr["rev"]
+                + " "
+                + cpu_attr["pre"]
+                + cpu_attr["post"]
             )
 
         return sim_cpu + " " + validate_hvx_length(hvx, sim_options)

tests/python/relay/aot/test_crt_aot_usmp.py

@@ -642,4 +642,3 @@ def test_u4_usecase_incompatible_interface_api_errors():
     import pytest
 
     sys.exit(pytest.main([__file__] + sys.argv[1:]))
-

tests/python/relay/test_pass_annotate_spans_defuse.py

@@ -42,7 +42,9 @@ def test_annotate_spans_compatibility():
 
     # Apply some simple passes to legalize the IR.
     with tvm.transform.PassContext(opt_level=0):
-        module, params = relay.optimize(module, target=tvm.testing.enabled_targets()[0][0], params=params)
+        module, params = relay.optimize(
+            module, target=tvm.testing.enabled_targets()[0][0], params=params
+        )
 
     seq = tvm.transform.Sequential([relay.transform.AnnotateSpans(), relay.transform.DefuseOps()])
     with tvm.transform.PassContext(opt_level=3):
@@ -54,4 +56,3 @@ def test_annotate_spans_compatibility():
     import pytest
 
     sys.exit(pytest.main([__file__] + sys.argv[1:]))
-