怎么书写批量的条件选择when的块，使得生成的verilog不是一个个独立的if块而是if-else串(Translated:How to structure Chisel's when blocks to generate if-else cascades in Verilog rather than discrete if statements.)

[msuadOf]

怎么书写批量的条件选择when的块，使得生成的verilog不是一个个独立的if块而是if-else串?
如代码所示，生成的verilog是一堆if，我希望生成的是if-else串，这样在后端的情况应该不一样。

for(i <-0 until setsize) {
  for(j<-0 until waySize){
    when(i.asUInt === index && j.asUInt === Way2Write) {
      cacheData(i)(j).write(data)
    }
  }
}

How should I structure multiple chisel when block to generate Verilog with if-else cascades instead of parallel if blocks? As the code, the current output produces discrete if statements, but I require an if-else chain for better backend characteristics.

[unlsycn]

just use elsewhen and you may need to pass WhenContext between the iterations.

For this case, however, I suggest using muxes instead of when statements.

[msuadOf]

好的，谢谢你。但是用mux的话意味着很多信号需要拆分开来赋值，但如果WhenContext里面运行了一个函数，这个函数包含了复杂的行为用以抽象复杂的微架构行为，使得我在修改微架构的时候不必管每一个具体指令的形式，只需要提供可以使用的操作就好：

Alright, thank you. However, using mux means that many signals need to be split and assigned individually. But if a function is run inside WhenContext, and this function encapsulates complex behavior to abstract intricate microarchitectural actions, it allows me to modify the microarchitecture without worrying about the specific form of each instruction—only the operations that can be used

object RVInstrs {
  def ADDI  = BitPat("b???????_?????_?????_000_?????_0010011")
  def ADDIExec  = (e: ExecEnv) => e.Rrd := e.src1 + e.immI
  // ... other riscv instructions
  
  val table = Array(
    ADDI  -> ADDIExec ,
    // ... other riscv instructions
  )
  val tabelWithIndex = table.zipWithIndex
}

EX stage:

RVIInstrs.tabelWithIndex.foreach((t) => {
      val (elem, inst_index) = t
      val (bitpat -> exec) = elem
      when( env.inst_id === inst_index.U ) { // 'env.inst_id' decoded from ID stage
        exec(env)
      }
    })

虽然说EX阶段本质上是一堆信号经过组合逻辑输出出去，用Mux完全有理论依据，但是这种情况下我认为对行为进行一定程度的抽象会更好。并且，如果想要在EX阶段加入一些时序逻辑时，如果能按命令式的方式调函数会更加简单和方便。那么这种情况，有什么建议吗?

Even though the EX stage is essentially a collection of signals passing through combinational logic—so using a Mux is perfectly defensible. I still think a certain amount of behavioral abstraction pays off here.
If, later on, we need to slip some sequential logic into EX, being able to “just call a function” in an imperative style is noticeably simpler and more convenient.
Given that, any recommendations on it?