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Adding the Vector512 and Vector512<T> types (#76642)
* Adding the Vector512 and Vector512<T> types * Support properly packing Vector512<T> * Responding to PR feedback and ensure Vector512 is treated as an HFA for Arm64 * Bring Vector512 inline with the new Vector64/128/256 APIs * Adding support for generating the Vector512 tests * Generate the Vector512 tests * Ensure the ref assembly is up to date * Fixing a couple JIT asserts * Fixing tests to pass the right number of constructor parameters * Ensure the HWIntrinsic test templates support 64-byte alignment * Ensure the vector Dot tests correctly sum using pairs * Ensure the Dot test computes the result pairs correctly * Simplify the alignment check to avoid future churn * Don't churn the Vector64/128/256 tests on the Vector512 PR * Do update the Dot tests to have the updated validation * Fix Vector128 divide by scalar * Ensure field layout tests exist for Vector256 and Vector512 * Updating the R2R version from 8.0 to 9.0 * Ensure Vector512 tests are disabled in the same place as the Vector64/128/256 tests * Remove a stray . * Fixing the NativeAOT field layout tests * Update an addition location where the R2R version is defined * Disable Vector512 tests for llvmfullaot due to #80467 * Increase the value of ngsharedvt-trampolines * Move various HWIntrinsics to outerloop for unaccelerated platforms * Ensure the HardwareIntrinsics tests are being filtered to outerloop where appropriate Co-authored-by: Fan Yang <[email protected]>
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‎src/coreclr/inc/readytorun.h‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,11 +14,13 @@
1414

1515
#define READYTORUN_SIGNATURE 0x00525452 // 'RTR'
1616

17-
// Keep these in sync with src/coreclr/tools/Common/Internal/Runtime/ModuleHeaders.cs
18-
#define READYTORUN_MAJOR_VERSION 0x0008
17+
// Keep these in sync with
18+
// src/coreclr/tools/Common/Internal/Runtime/ModuleHeaders.cs
19+
// src/coreclr/nativeaot/Runtime/inc/ModuleHeaders.h
20+
#define READYTORUN_MAJOR_VERSION 0x0009
1921
#define READYTORUN_MINOR_VERSION 0x0000
2022

21-
#define MINIMUM_READYTORUN_MAJOR_VERSION 0x008
23+
#define MINIMUM_READYTORUN_MAJOR_VERSION 0x009
2224

2325
// R2R Version 2.1 adds the InliningInfo section
2426
// R2R Version 2.2 adds the ProfileDataInfo section
@@ -27,6 +29,7 @@
2729
// R2R Version 6.0 changes managed layout for sequential types with any unmanaged non-blittable fields.
2830
// R2R 6.0 is not backward compatible with 5.x or earlier.
2931
// R2R Version 8.0 Changes the alignment of the Int128 type
32+
// R2R Version 9.0 adds support for the Vector512 type
3033

3134
struct READYTORUN_CORE_HEADER
3235
{

‎src/coreclr/jit/hwintrinsicarm64.cpp‎

Lines changed: 15 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -762,22 +762,25 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
762762
{
763763
assert(sig->numArgs == 2);
764764

765-
if (varTypeIsFloating(simdBaseType))
765+
if (!varTypeIsFloating(simdBaseType))
766766
{
767-
CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
768-
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
769-
var_types argType = TYP_UNKNOWN;
770-
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;
767+
// We can't trivially handle division for integral types using SIMD
768+
break;
769+
}
770+
771+
CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
772+
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
773+
var_types argType = TYP_UNKNOWN;
774+
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;
771775

772-
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
773-
op2 = getArgForHWIntrinsic(argType, argClass);
776+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
777+
op2 = getArgForHWIntrinsic(argType, argClass);
774778

775-
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
776-
op1 = getArgForHWIntrinsic(argType, argClass);
779+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
780+
op1 = getArgForHWIntrinsic(argType, argClass);
777781

778-
retNode = gtNewSimdBinOpNode(GT_DIV, retType, op1, op2, simdBaseJitType, simdSize,
779-
/* isSimdAsHWIntrinsic */ false);
780-
}
782+
retNode = gtNewSimdBinOpNode(GT_DIV, retType, op1, op2, simdBaseJitType, simdSize,
783+
/* isSimdAsHWIntrinsic */ false);
781784
break;
782785
}
783786

‎src/coreclr/jit/hwintrinsicxarch.cpp‎

Lines changed: 16 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1145,23 +1145,25 @@ GenTree* Compiler::impBaseIntrinsic(NamedIntrinsic intrinsic,
11451145
{
11461146
assert(sig->numArgs == 2);
11471147

1148-
if (varTypeIsFloating(simdBaseType))
1148+
if (!varTypeIsFloating(simdBaseType))
11491149
{
1150-
CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
1151-
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
1152-
var_types argType = TYP_UNKNOWN;
1153-
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;
1150+
// We can't trivially handle division for integral types using SIMD
1151+
break;
1152+
}
11541153

1155-
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
1156-
op2 = getArgForHWIntrinsic(argType, argClass);
1154+
CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
1155+
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
1156+
var_types argType = TYP_UNKNOWN;
1157+
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;
11571158

1158-
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
1159-
op1 = getArgForHWIntrinsic(argType, argClass);
1159+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
1160+
op2 = getArgForHWIntrinsic(argType, argClass);
11601161

1161-
retNode = gtNewSimdBinOpNode(GT_DIV, retType, op1, op2, simdBaseJitType, simdSize,
1162-
/* isSimdAsHWIntrinsic */ false);
1163-
break;
1164-
}
1162+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
1163+
op1 = getArgForHWIntrinsic(argType, argClass);
1164+
1165+
retNode = gtNewSimdBinOpNode(GT_DIV, retType, op1, op2, simdBaseJitType, simdSize,
1166+
/* isSimdAsHWIntrinsic */ false);
11651167
break;
11661168
}
11671169

@@ -2061,7 +2063,7 @@ GenTree* Compiler::impBaseIntrinsic(NamedIntrinsic intrinsic,
20612063
{
20622064
assert(sig->numArgs == 2);
20632065

2064-
if (varTypeIsByte(simdBaseType) || varTypeIsLong(simdBaseType))
2066+
if (varTypeIsByte(simdBaseType) || varTypeIsLong(simdBaseType) || (simdBaseType == TYP_DOUBLE))
20652067
{
20662068
// byte, sbyte, long, and ulong would require more work to support
20672069
break;

‎src/coreclr/nativeaot/Runtime/inc/ModuleHeaders.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,14 @@
44
//
55
// Please keep the data structures in this file in sync with the managed version at
66
// src/Common/src/Internal/Runtime/ModuleHeaders.cs
7-
//
7+
// src/coreclr/inc/readytorun.h
8+
89

910
struct ReadyToRunHeaderConstants
1011
{
1112
static const uint32_t Signature = 0x00525452; // 'RTR'
1213

13-
static const uint32_t CurrentMajorVersion = 8;
14+
static const uint32_t CurrentMajorVersion = 9;
1415
static const uint32_t CurrentMinorVersion = 0;
1516
};
1617

‎src/coreclr/tools/Common/Compiler/VectorFieldLayoutAlgorithm.cs‎

Lines changed: 26 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -44,9 +44,28 @@ public override ComputedInstanceFieldLayout ComputeInstanceLayout(DefType defTyp
4444
alignment = new LayoutInt(16);
4545
}
4646
}
47+
else if (name == "Vector256`1")
48+
{
49+
if (defType.Context.Target.Architecture == TargetArchitecture.ARM)
50+
{
51+
// No such type exists for the Procedure Call Standard for ARM. We will default
52+
// to the same alignment as __m128, which is supported by the ABI.
53+
alignment = new LayoutInt(8);
54+
}
55+
else if (defType.Context.Target.Architecture == TargetArchitecture.ARM64)
56+
{
57+
// The Procedure Call Standard for ARM 64-bit (with SVE support) defaults to
58+
// 16-byte alignment for __m256.
59+
alignment = new LayoutInt(16);
60+
}
61+
else
62+
{
63+
alignment = new LayoutInt(32);
64+
}
65+
}
4766
else
4867
{
49-
Debug.Assert(name == "Vector256`1");
68+
Debug.Assert(name == "Vector512`1");
5069

5170
if (defType.Context.Target.Architecture == TargetArchitecture.ARM)
5271
{
@@ -62,7 +81,7 @@ public override ComputedInstanceFieldLayout ComputeInstanceLayout(DefType defTyp
6281
}
6382
else
6483
{
65-
alignment = new LayoutInt(32);
84+
alignment = new LayoutInt(64);
6685
}
6786
}
6887

@@ -106,6 +125,7 @@ public override ValueTypeShapeCharacteristics ComputeValueTypeShapeCharacteristi
106125
8 => ValueTypeShapeCharacteristics.Vector64Aggregate,
107126
16 => ValueTypeShapeCharacteristics.Vector128Aggregate,
108127
32 => ValueTypeShapeCharacteristics.Vector128Aggregate,
128+
64 => ValueTypeShapeCharacteristics.Vector128Aggregate,
109129
_ => ValueTypeShapeCharacteristics.None
110130
};
111131
}
@@ -116,9 +136,10 @@ public static bool IsVectorType(DefType type)
116136
{
117137
return type.IsIntrinsic &&
118138
type.Namespace == "System.Runtime.Intrinsics" &&
119-
(type.Name == "Vector64`1" ||
120-
type.Name == "Vector128`1" ||
121-
type.Name == "Vector256`1");
139+
((type.Name == "Vector64`1") ||
140+
(type.Name == "Vector128`1") ||
141+
(type.Name == "Vector256`1") ||
142+
(type.Name == "Vector512`1"));
122143
}
123144
}
124145
}

‎src/coreclr/tools/Common/Internal/Runtime/ModuleHeaders.cs‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,14 @@ namespace Internal.Runtime
88
//
99
// Please keep the data structures in this file in sync with the native version at
1010
// src/coreclr/inc/readytorun.h
11+
// src/coreclr/nativeaot/Runtime/inc/ModuleHeaders.h
1112
//
1213

1314
internal struct ReadyToRunHeaderConstants
1415
{
1516
public const uint Signature = 0x00525452; // 'RTR'
1617

17-
public const ushort CurrentMajorVersion = 8;
18+
public const ushort CurrentMajorVersion = 9;
1819
public const ushort CurrentMinorVersion = 0;
1920
}
2021
#if READYTORUN

‎src/coreclr/tools/Common/TypeSystem/CodeGen/TargetDetails.CodeGen.cs‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,5 +40,10 @@ public enum SimdVectorLength
4040
/// Specifies that native vectors are 256 bit (e.g. AVX on x86).
4141
/// </summary>
4242
Vector256Bit,
43+
44+
/// <summary>
45+
/// Specifies that native vectors are 512 bit (e.g. AVX512 on x86).
46+
/// </summary>
47+
Vector512Bit,
4348
}
4449
}

‎src/coreclr/tools/Common/TypeSystem/Common/TargetDetails.cs‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -109,21 +109,21 @@ public int MaximumAlignment
109109
{
110110
if (Architecture == TargetArchitecture.ARM)
111111
{
112-
// Corresponds to alignment required for __m128 (there's no __m256)
112+
// Corresponds to alignment required for __m128 (there's no __m256/__m512)
113113
return 8;
114114
}
115115
else if (Architecture == TargetArchitecture.ARM64)
116116
{
117-
// Corresponds to alignmet required for __m256
117+
// Corresponds to alignmet required for __m128 (there's no __m256/__m512)
118118
return 16;
119119
}
120120
else if (Architecture == TargetArchitecture.LoongArch64)
121121
{
122122
return 16;
123123
}
124124

125-
// 256-bit vector is the type with the highest alignment we support
126-
return 32;
125+
// 512-bit vector is the type with the highest alignment we support
126+
return 64;
127127
}
128128
}
129129

@@ -136,8 +136,8 @@ public int DefaultPackingSize
136136
{
137137
get
138138
{
139-
// We use default packing size of 32 irrespective of the platform.
140-
return 32;
139+
// We use default packing size of 64 irrespective of the platform.
140+
return 64;
141141
}
142142
}
143143

‎src/coreclr/tools/Common/TypeSystem/Interop/IL/MarshalHelpers.cs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -874,13 +874,15 @@ private static bool IsValidForGenericMarshalling(
874874
// * Vector64<T>: Represents the __m64 ABI primitive which requires currently unimplemented handling
875875
// * Vector128<T>: Represents the __m128 ABI primitive which requires currently unimplemented handling
876876
// * Vector256<T>: Represents the __m256 ABI primitive which requires currently unimplemented handling
877+
// * Vector512<T>: Represents the __m512 ABI primitive which requires currently unimplemented handling
877878
// * Vector<T>: Has a variable size (either __m128 or __m256) and isn't readily usable for interop scenarios
878879
return !InteropTypes.IsSystemNullable(type.Context, type)
879880
&& !InteropTypes.IsSystemSpan(type.Context, type)
880881
&& !InteropTypes.IsSystemReadOnlySpan(type.Context, type)
881882
&& !InteropTypes.IsSystemRuntimeIntrinsicsVector64T(type.Context, type)
882883
&& !InteropTypes.IsSystemRuntimeIntrinsicsVector128T(type.Context, type)
883884
&& !InteropTypes.IsSystemRuntimeIntrinsicsVector256T(type.Context, type)
885+
&& !InteropTypes.IsSystemRuntimeIntrinsicsVector512T(type.Context, type)
884886
&& !InteropTypes.IsSystemNumericsVectorT(type.Context, type);
885887
}
886888

‎src/coreclr/tools/Common/TypeSystem/Interop/InteropTypes.cs‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,11 @@ public static bool IsSystemRuntimeIntrinsicsVector256T(TypeSystemContext context
145145
return IsCoreNamedType(context, type, "System.Runtime.Intrinsics", "Vector256`1");
146146
}
147147

148+
public static bool IsSystemRuntimeIntrinsicsVector512T(TypeSystemContext context, TypeDesc type)
149+
{
150+
return IsCoreNamedType(context, type, "System.Runtime.Intrinsics", "Vector512`1");
151+
}
152+
148153
public static bool IsSystemNumericsVectorT(TypeSystemContext context, TypeDesc type)
149154
{
150155
return IsCoreNamedType(context, type, "System.Numerics", "Vector`1");

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