@@ -7652,26 +7652,47 @@ bool Lowering::IsContainableHWIntrinsicOp(GenTreeHWIntrinsic* parentNode, GenTre
76527652 }
76537653
76547654 case NI_SSE2_ConvertToVector128Double:
7655- case NI_SSE3_MoveAndDuplicate:
76567655 case NI_AVX_ConvertToVector256Double:
7656+ case NI_AVX512F_ConvertToVector512Double:
7657+ case NI_AVX512F_VL_ConvertToVector128Double:
7658+ case NI_AVX512F_VL_ConvertToVector256Double:
76577659 {
76587660 assert (!supportsSIMDScalarLoads);
76597661
76607662 // Most instructions under the non-VEX encoding require aligned operands.
76617663 // Those used for Sse2.ConvertToVector128Double (CVTDQ2PD and CVTPS2PD)
7662- // and Sse3.MoveAndDuplicate (MOVDDUP) are exceptions and don't fail for
7663- // unaligned inputs as they read mem64 (half the vector width) instead
7664+ // are exceptions and don't fail for unaligned inputs as they read half
7665+ // the vector width instead
76647666
76657667 supportsAlignedSIMDLoads = !comp->opts .MinOpts ();
76667668 supportsUnalignedSIMDLoads = true ;
76677669
76687670 const unsigned expectedSize = genTypeSize (parentNode->TypeGet ()) / 2 ;
76697671 const unsigned operandSize = genTypeSize (childNode->TypeGet ());
76707672
7671- // For broadcasts we can only optimize constants and memory operands
7672- const bool broadcastIsContainable = childNode->OperIsConst () || childNode->isMemoryOp ();
7673- supportsGeneralLoads =
7674- broadcastIsContainable && supportsUnalignedSIMDLoads && (operandSize >= expectedSize);
7673+ if (childNode->OperIsConst () || childNode->isMemoryOp ())
7674+ {
7675+ // For broadcasts we can only optimize constants and memory operands
7676+ // since we're going from a smaller base type to a larger base type
7677+ supportsGeneralLoads = supportsUnalignedSIMDLoads && (operandSize >= expectedSize);
7678+ }
7679+ break ;
7680+ }
7681+
7682+ case NI_SSE3_MoveAndDuplicate:
7683+ {
7684+ // Most instructions under the non-VEX encoding require aligned operands.
7685+ // Those used for Sse3.MoveAndDuplicate (MOVDDUP) are exceptions and don't
7686+ // fail for unaligned inputs as they read half the vector width instead
7687+
7688+ supportsAlignedSIMDLoads = !comp->opts .MinOpts ();
7689+ supportsUnalignedSIMDLoads = true ;
7690+
7691+ const unsigned expectedSize = genTypeSize (parentNode->TypeGet ()) / 2 ;
7692+ const unsigned operandSize = genTypeSize (childNode->TypeGet ());
7693+
7694+ supportsGeneralLoads = supportsUnalignedSIMDLoads && (operandSize >= expectedSize);
7695+ supportsSIMDScalarLoads = true ;
76757696 break ;
76767697 }
76777698
@@ -7697,8 +7718,6 @@ bool Lowering::IsContainableHWIntrinsicOp(GenTreeHWIntrinsic* parentNode, GenTre
76977718 break ;
76987719 }
76997720 }
7700-
7701- assert (supportsSIMDScalarLoads == false );
77027721 break ;
77037722 }
77047723
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