@@ -16248,6 +16248,12 @@ bool emitter::ReplaceLdrStrWithPairInstr(
1624816248// ldr w1, [x20, #0x14]
1624916249// ldr w2, [x20, #0x10] => ldp w2, w1, [x20, #0x10]
1625016250//
16251+ // ldr w1, [x20]
16252+ // ldr w2, [x20, #0x04] => ldp w1, w2, [x20]
16253+ //
16254+ // ldr q1, [x0, #0x20]
16255+ // ldr q2, [x0, #0x30] => ldp q1, q2, [x0, #0x20]
16256+ //
1625116257// Arguments:
1625216258// ins - The instruction code
1625316259// reg1 - Register 1 number
@@ -16291,16 +16297,21 @@ emitter::RegisterOrder emitter::IsOptimizableLdrStrWithPair(
1629116297 return eRO_none;
1629216298 }
1629316299
16294- if ((!isGeneralRegisterOrZR( reg1) ) || (! isGeneralRegisterOrZR(prevReg1)))
16300+ if ((reg1 == REG_SP) || (prevReg1 == REG_SP ) || (isGeneralRegisterOrZR(reg1) != isGeneralRegisterOrZR(prevReg1)))
1629516301 {
16296- // Either register 1 is not a general register or previous register 1 is not a general register
16297- // or the zero register, so we cannot optimise.
16302+ // We cannot optimise when one of the following conditions are met
16303+ // 1. reg1 or prevReg1 is SP
16304+ // 2. both reg1 and prevReg1 are not of the same type (SIMD or non-SIMD)
1629816305 return eRO_none;
1629916306 }
1630016307
16301- if (lastInsFmt != fmt)
16308+ const bool compatibleFmt = (lastInsFmt == fmt) || (lastInsFmt == IF_LS_2B && fmt == IF_LS_2A) ||
16309+ (lastInsFmt == IF_LS_2A && fmt == IF_LS_2B);
16310+ if (!compatibleFmt)
1630216311 {
16303- // The formats of the two instructions differ.
16312+ // We cannot optimise when all of the following conditions are met
16313+ // 1. instruction formats differ
16314+ // 2. instructions are not using "base" or "base plus immediate offset" addressing modes
1630416315 return eRO_none;
1630516316 }
1630616317
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