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Commit 8ccc15e

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Clean up
1 parent ff1a219 commit 8ccc15e

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2 files changed

+7
-17
lines changed

2 files changed

+7
-17
lines changed

src/coreclr/jit/emitarm64.cpp

Lines changed: 5 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -13483,24 +13483,13 @@ void emitter::emitInsLoadStoreOp(instruction ins, emitAttr attr, regNumber dataR
1348313483
{
1348413484
if (index->OperIs(GT_BFIZ) && index->isContained())
1348513485
{
13486+
// Then load/store dataReg from/to [memBase + index*scale with sign/zero extension]
1348613487
GenTreeCast* cast = index->gtGetOp1()->AsCast();
13487-
assert(cast->isContained());
13488+
assert(cast->isContained() && varTypeToSigned(cast->CastFromType()) == TYP_INT);
1348813489
const bool isZeroExtended = cast->IsUnsigned() || varTypeIsUnsigned(cast->CastToType());
13489-
insOpts opts = INS_OPTS_NONE;
13490-
int shift = (int)index->gtGetOp2()->AsIntCon()->IconValue();
13491-
switch (shift)
13492-
{
13493-
case 2:
13494-
opts = isZeroExtended ? INS_OPTS_UXTW : INS_OPTS_SXTW;
13495-
break;
13496-
case 3:
13497-
opts = isZeroExtended ? INS_OPTS_UXTX : INS_OPTS_SXTX;
13498-
break;
13499-
default:
13500-
unreached();
13501-
}
13502-
emitIns_R_R_R_Ext(ins, attr, dataReg, memBase->GetRegNum(), cast->CastOp()->GetRegNum(), opts,
13503-
shift);
13490+
emitIns_R_R_R_Ext(ins, attr, dataReg, memBase->GetRegNum(), cast->CastOp()->GetRegNum(),
13491+
isZeroExtended ? INS_OPTS_UXTW : INS_OPTS_SXTW,
13492+
(int)index->gtGetOp2()->AsIntCon()->IconValue());
1350413493
}
1350513494
else
1350613495
{

src/coreclr/jit/lower.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5046,7 +5046,8 @@ bool Lowering::TryCreateAddrMode(GenTree* addr, bool isContainable, var_types ta
50465046
unsigned castFrom = genTypeSize(cast->CastFromType());
50475047
unsigned target = genTypeSize(targetType);
50485048

5049-
// For now only two the most popular cases are handled. TODO: extend
5049+
// For now we only handle the most popular case for indices 32 -> 64 sign/zero extension
5050+
// Where target is 32 or 64. TODO: enable for 8 and 16
50505051
if ((castFrom == 4) && (castTo == 8) && (target == (1U << shiftBy)) && (target >= 4) && (scale == 1) &&
50515052
(offset == 0))
50525053
{

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