[JIT] Always transform AND(X, CNS(-1)) to X (#82276)

* Always skip emitting 'and reg0, -1' on x86

* Formatting

* Wrapping AreUpper32BitsZero and AreUpper32BitsSignExtended to be 64-bit only

* Added TryLowerAndNegativeOne

* minor tweak

* Update lowerxarch.cpp

* Remove peephole in favor of lowering opt

* Feedback and moved 'TryLowerAndNegativeOne' to lower.cpp

Author: TIHan

src/coreclr/jit/codegenxarch.cpp

@@ -998,17 +998,6 @@ void CodeGen::genCodeForBinary(GenTreeOp* treeNode)
         src = op2;
     }
 
-    // We can skip emitting 'and reg0, -1` if we know that the upper 32bits of 'reg0' are zero'ed.
-    if (compiler->opts.OptimizationEnabled())
-    {
-        if ((oper == GT_AND) && (targetType == TYP_INT) && !treeNode->gtSetFlags() && op2->IsIntegralConst(-1) &&
-            emit->AreUpper32BitsZero(targetReg))
-        {
-            genProduceReg(treeNode);
-            return;
-        }
-    }
-
     // try to use an inc or dec
     if (oper == GT_ADD && !varTypeIsFloating(treeNode) && src->isContainedIntOrIImmed() && !treeNode->gtOverflowEx())
     {

src/coreclr/jit/emitxarch.cpp

@@ -476,6 +476,7 @@ bool emitter::IsFlagsAlwaysModified(instrDesc* id)
     return true;
 }
 
+#ifdef TARGET_64BIT
 //------------------------------------------------------------------------
 // AreUpper32BitsZero: check if some previously emitted
 //     instruction set the upper 32 bits of reg to zero.
@@ -594,12 +595,10 @@ bool emitter::AreUpper32BitsZero(regNumber reg)
                 return false;
             }
 
-#ifdef TARGET_AMD64
             if (id->idIns() == INS_movsxd)
             {
                 return false;
             }
-#endif
 
             // movzx always zeroes the upper 32 bits.
             if (id->idIns() == INS_movzx)
@@ -655,16 +654,15 @@ bool emitter::AreUpper32BitsSignExtended(regNumber reg)
         return true;
     }
 
-#ifdef TARGET_AMD64
     // movsxd is always an 8 byte operation. W-bit is set.
     if (id->idIns() == INS_movsxd)
     {
         return true;
     }
-#endif
 
     return false;
 }
+#endif // TARGET_64BIT
 
 //------------------------------------------------------------------------
 // AreFlagsSetToZeroCmp: Checks if the previous instruction set the SZ, and optionally OC, flags to

src/coreclr/jit/emitxarch.h

@@ -127,8 +127,10 @@ bool IsRedundantStackMov(instruction ins, insFormat fmt, emitAttr size, regNumbe
 static bool IsJccInstruction(instruction ins);
 static bool IsJmpInstruction(instruction ins);
 
+#ifdef TARGET_64BIT
 bool AreUpper32BitsZero(regNumber reg);
 bool AreUpper32BitsSignExtended(regNumber reg);
+#endif // TARGET_64BIT
 
 bool AreFlagsSetToZeroCmp(regNumber reg, emitAttr opSize, GenCondition cond);
 bool AreFlagsSetForSignJumpOpt(regNumber reg, emitAttr opSize, GenCondition cond);

src/coreclr/jit/lower.cpp

@@ -366,7 +366,18 @@ GenTree* Lowering::LowerNode(GenTree* node)
         case GT_AND:
         case GT_OR:
         case GT_XOR:
+        {
+            if (comp->opts.OptimizationEnabled() && node->OperIs(GT_AND))
+            {
+                GenTree* replacementNode = TryLowerAndNegativeOne(node->AsOp());
+                if (replacementNode != nullptr)
+                {
+                    return replacementNode->gtNext;
+                }
+            }
+
             return LowerBinaryArithmetic(node->AsOp());
+        }
 
         case GT_MUL:
         case GT_MULHI:
@@ -7784,6 +7795,51 @@ void Lowering::TryRetypingFloatingPointStoreToIntegerStore(GenTree* store)
     }
 }
 
+//----------------------------------------------------------------------------------------------
+// Lowering::TryLowerAndNegativeOne:
+//    If safe, lowers a tree AND(X, CNS(-1)) to X.
+//
+// Arguments:
+//    node - GT_AND node of integral type
+//
+// Return Value:
+//    Returns the replacement node if one is created else nullptr indicating no replacement
+GenTree* Lowering::TryLowerAndNegativeOne(GenTreeOp* node)
+{
+    assert(node->OperIs(GT_AND));
+
+    if (!varTypeIsIntegral(node))
+        return nullptr;
+
+    if (node->gtSetFlags())
+        return nullptr;
+
+    if (node->isContained())
+        return nullptr;
+
+    GenTree* op2 = node->gtGetOp2();
+
+    if (!op2->IsIntegralConst(-1))
+        return nullptr;
+
+#ifndef TARGET_64BIT
+    assert(op2->TypeIs(TYP_INT));
+#endif // !TARGET_64BIT
+
+    LIR::Use use;
+    if (!BlockRange().TryGetUse(node, &use))
+        return nullptr;
+
+    GenTree* op1 = node->gtGetOp1();
+
+    use.ReplaceWith(op1);
+
+    BlockRange().Remove(op2);
+    BlockRange().Remove(node);
+
+    return op1;
+}
+
 #if defined(FEATURE_HW_INTRINSICS)
 //----------------------------------------------------------------------------------------------
 // Lowering::InsertNewSimdCreateScalarUnsafeNode: Inserts a new simd CreateScalarUnsafe node

src/coreclr/jit/lower.h

@@ -307,6 +307,7 @@ class Lowering final : public Phase
     void LowerStoreIndir(GenTreeStoreInd* node);
     GenTree* LowerAdd(GenTreeOp* node);
     GenTree* LowerMul(GenTreeOp* mul);
+    GenTree* TryLowerAndNegativeOne(GenTreeOp* node);
     GenTree* LowerBinaryArithmetic(GenTreeOp* binOp);
     bool LowerUnsignedDivOrMod(GenTreeOp* divMod);
     GenTree* LowerConstIntDivOrMod(GenTree* node);