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SwapnilGaikwadSwapnilGaikwad
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Add Arm64 encodings for SVE IF_SVE_CX_4A_A to IF_SVE_HT_4A group (#96214)
* Add SVE IF_SVE_CQ_4A_A group * Fix format issues * Add Arm64 encodings for IF_SVE_GE_4A group * Fix build issue * Add Arm64 encodings for case IF_SVE_HT_4A group * Fix build and formatting * Remove redundant asserts
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-23
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3 files changed

+189
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‎src/coreclr/jit/codegenarm64test.cpp‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4772,6 +4772,28 @@ void CodeGen::genArm64EmitterUnitTestsSve()
47724772
theEmitter->emitIns_R_R_R_R(INS_sve_cmpne, EA_SCALABLE, REG_P3, REG_P1, REG_V15, REG_V20,
47734773
INS_OPTS_SCALABLE_H); // CMPNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
47744774

4775+
// IF_SVE_CX_4A_A
4776+
theEmitter->emitIns_R_R_R_R(INS_sve_cmpeq, EA_SCALABLE, REG_P15, REG_P7, REG_V31, REG_V3, INS_OPTS_SCALABLE_B,
4777+
INS_SCALABLE_OPTS_WIDE); /* CMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D */
4778+
theEmitter->emitIns_R_R_R_R(INS_sve_cmpge, EA_SCALABLE, REG_P14, REG_P6, REG_V21, REG_V13, INS_OPTS_SCALABLE_H,
4779+
INS_SCALABLE_OPTS_WIDE); /* CMPGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D */
4780+
theEmitter->emitIns_R_R_R_R(INS_sve_cmpgt, EA_SCALABLE, REG_P13, REG_P5, REG_V11, REG_V23, INS_OPTS_SCALABLE_S,
4781+
INS_SCALABLE_OPTS_WIDE); /* CMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D */
4782+
theEmitter->emitIns_R_R_R_R(INS_sve_cmphi, EA_SCALABLE, REG_P12, REG_P4, REG_V1, REG_V31, INS_OPTS_SCALABLE_B,
4783+
INS_SCALABLE_OPTS_WIDE); /* CMPHI <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D */
4784+
theEmitter->emitIns_R_R_R_R(INS_sve_cmphs, EA_SCALABLE, REG_P11, REG_P3, REG_V0, REG_V30, INS_OPTS_SCALABLE_H,
4785+
INS_SCALABLE_OPTS_WIDE); /* CMPHS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D */
4786+
theEmitter->emitIns_R_R_R_R(INS_sve_cmple, EA_SCALABLE, REG_P4, REG_P2, REG_V10, REG_V0, INS_OPTS_SCALABLE_S,
4787+
INS_SCALABLE_OPTS_WIDE); /* CMPLE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D */
4788+
theEmitter->emitIns_R_R_R_R(INS_sve_cmplo, EA_SCALABLE, REG_P3, REG_P1, REG_V20, REG_V1, INS_OPTS_SCALABLE_B,
4789+
INS_SCALABLE_OPTS_WIDE); /* CMPLO <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D */
4790+
theEmitter->emitIns_R_R_R_R(INS_sve_cmpls, EA_SCALABLE, REG_P2, REG_P0, REG_V30, REG_V2, INS_OPTS_SCALABLE_H,
4791+
INS_SCALABLE_OPTS_WIDE); /* CMPLS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D */
4792+
theEmitter->emitIns_R_R_R_R(INS_sve_cmplt, EA_SCALABLE, REG_P1, REG_P7, REG_V24, REG_V8, INS_OPTS_SCALABLE_S,
4793+
INS_SCALABLE_OPTS_WIDE); /* CMPLT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D */
4794+
theEmitter->emitIns_R_R_R_R(INS_sve_cmpne, EA_SCALABLE, REG_P0, REG_P0, REG_V14, REG_V28, INS_OPTS_SCALABLE_B,
4795+
INS_SCALABLE_OPTS_WIDE); /* CMPNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D */
4796+
47754797
// IF_SVE_EP_3A
47764798
theEmitter->emitIns_R_R_R(INS_sve_shadd, EA_SCALABLE, REG_V15, REG_P0, REG_V10,
47774799
INS_OPTS_SCALABLE_B); // SHADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
@@ -4846,6 +4868,12 @@ void CodeGen::genArm64EmitterUnitTestsSve()
48464868
theEmitter->emitIns_R_R_R(INS_sve_urshlr, EA_SCALABLE, REG_V15, REG_P2, REG_V20,
48474869
INS_OPTS_SCALABLE_D); // URSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
48484870

4871+
// IF_SVE_GE_4A
4872+
theEmitter->emitIns_R_R_R_R(INS_sve_match, EA_SCALABLE, REG_P15, REG_P0, REG_V21, REG_V0,
4873+
INS_OPTS_SCALABLE_B); // MATCH <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
4874+
theEmitter->emitIns_R_R_R_R(INS_sve_nmatch, EA_SCALABLE, REG_P0, REG_P7, REG_V11, REG_V31,
4875+
INS_OPTS_SCALABLE_H); // NMATCH <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
4876+
48494877
// IF_SVE_GR_3A
48504878
theEmitter->emitIns_R_R_R(INS_sve_faddp, EA_SCALABLE, REG_V16, REG_P3, REG_V19,
48514879
INS_OPTS_SCALABLE_H); // FADDP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
@@ -4900,6 +4928,30 @@ void CodeGen::genArm64EmitterUnitTestsSve()
49004928
theEmitter->emitIns_R_R_R(INS_sve_fsubr, EA_SCALABLE, REG_V6, REG_P4, REG_V29,
49014929
INS_OPTS_SCALABLE_D); // FSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
49024930

4931+
// IF_SVE_HT_4A
4932+
theEmitter->emitIns_R_R_R_R(INS_sve_facge, EA_SCALABLE, REG_P0, REG_P0, REG_V10, REG_V31,
4933+
INS_OPTS_SCALABLE_H); // FACGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
4934+
theEmitter->emitIns_R_R_R_R(INS_sve_facgt, EA_SCALABLE, REG_P15, REG_P1, REG_V20, REG_V21,
4935+
INS_OPTS_SCALABLE_S); // FACGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
4936+
theEmitter->emitIns_R_R_R_R(INS_sve_facle, EA_SCALABLE, REG_P1, REG_P2, REG_V0, REG_V11,
4937+
INS_OPTS_SCALABLE_D); // FACLE <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
4938+
theEmitter->emitIns_R_R_R_R(INS_sve_faclt, EA_SCALABLE, REG_P14, REG_P3, REG_V30, REG_V1,
4939+
INS_OPTS_SCALABLE_H); // FACLT <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
4940+
theEmitter->emitIns_R_R_R_R(INS_sve_fcmeq, EA_SCALABLE, REG_P2, REG_P4, REG_V28, REG_V8,
4941+
INS_OPTS_SCALABLE_S); // FCMEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
4942+
theEmitter->emitIns_R_R_R_R(INS_sve_fcmge, EA_SCALABLE, REG_P13, REG_P5, REG_V8, REG_V18,
4943+
INS_OPTS_SCALABLE_D); // FCMGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
4944+
theEmitter->emitIns_R_R_R_R(INS_sve_fcmgt, EA_SCALABLE, REG_P3, REG_P6, REG_V18, REG_V28,
4945+
INS_OPTS_SCALABLE_H); // FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
4946+
theEmitter->emitIns_R_R_R_R(INS_sve_fcmle, EA_SCALABLE, REG_P12, REG_P7, REG_V1, REG_V30,
4947+
INS_OPTS_SCALABLE_S); // FCMLE <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
4948+
theEmitter->emitIns_R_R_R_R(INS_sve_fcmlt, EA_SCALABLE, REG_P4, REG_P0, REG_V11, REG_V0,
4949+
INS_OPTS_SCALABLE_D); // FCMLT <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
4950+
theEmitter->emitIns_R_R_R_R(INS_sve_fcmne, EA_SCALABLE, REG_P11, REG_P1, REG_V21, REG_V10,
4951+
INS_OPTS_SCALABLE_H); // FCMNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
4952+
theEmitter->emitIns_R_R_R_R(INS_sve_fcmuo, EA_SCALABLE, REG_P5, REG_P2, REG_V31, REG_V20,
4953+
INS_OPTS_SCALABLE_S); // FCMUO <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
4954+
49034955
// IF_SVE_AF_3A
49044956
theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0,
49054957
INS_OPTS_SCALABLE_B); // ANDV <V><d>, <Pg>, <Zn>.<T>

‎src/coreclr/jit/emitarm64.cpp‎

Lines changed: 123 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1058,12 +1058,42 @@ void emitter::emitInsSanityCheck(instrDesc* id)
10581058
// Scalable, 4 regs, to predicate register.
10591059
case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
10601060
elemsize = id->idOpSize();
1061+
assert(isScalableVectorSize(elemsize));
10611062
assert(insOptsScalableStandard(id->idInsOpt())); // xx
10621063
assert(isPredicateRegister(id->idReg1())); // DDDD
10631064
assert(isLowPredicateRegister(id->idReg2())); // ggg
1064-
assert(isVectorRegister(id->idReg3())); // mmmmm
1065-
assert(isVectorRegister(id->idReg4())); // nnnnn
1065+
assert(isVectorRegister(id->idReg3())); // nnnnn
1066+
assert(isVectorRegister(id->idReg4())); // mmmmm
1067+
break;
1068+
1069+
case IF_SVE_CX_4A_A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
1070+
elemsize = id->idOpSize();
1071+
assert(isScalableVectorSize(elemsize));
1072+
assert(insOptsScalableWide(id->idInsOpt())); // xx
1073+
assert(isPredicateRegister(id->idReg1())); // DDDD
1074+
assert(isLowPredicateRegister(id->idReg2())); // ggg
1075+
assert(isVectorRegister(id->idReg3())); // mmmmm
1076+
assert(isVectorRegister(id->idReg4())); // nnnnn
1077+
break;
1078+
1079+
case IF_SVE_GE_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE2 character match
1080+
elemsize = id->idOpSize();
1081+
assert(isScalableVectorSize(elemsize));
1082+
assert(insOptsScalableAtMaxHalf(id->idInsOpt()));
1083+
assert(isPredicateRegister(id->idReg1())); // DDDD
1084+
assert(isLowPredicateRegister(id->idReg2())); // ggg
1085+
assert(isVectorRegister(id->idReg3())); // nnnnn
1086+
assert(isVectorRegister(id->idReg4())); // mmmmm
1087+
break;
1088+
1089+
case IF_SVE_HT_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE floating-point compare vectors
1090+
elemsize = id->idOpSize();
10661091
assert(isScalableVectorSize(elemsize));
1092+
assert(insOptsScalableFloat(id->idInsOpt()));
1093+
assert(isPredicateRegister(id->idReg1())); // DDDD
1094+
assert(isLowPredicateRegister(id->idReg2())); // ggg
1095+
assert(isVectorRegister(id->idReg3())); // nnnnn
1096+
assert(isVectorRegister(id->idReg4())); // mmmmm
10671097
break;
10681098

10691099
// Scalable FP.
@@ -10614,13 +10644,14 @@ void emitter::emitIns_R_R_I_I(
1061410644
* Add an instruction referencing four registers.
1061510645
*/
1061610646

10617-
void emitter::emitIns_R_R_R_R(instruction ins,
10618-
emitAttr attr,
10619-
regNumber reg1,
10620-
regNumber reg2,
10621-
regNumber reg3,
10622-
regNumber reg4,
10623-
insOpts opt /* = INS_OPT_NONE*/)
10647+
void emitter::emitIns_R_R_R_R(instruction ins,
10648+
emitAttr attr,
10649+
regNumber reg1,
10650+
regNumber reg2,
10651+
regNumber reg3,
10652+
regNumber reg4,
10653+
insOpts opt /* = INS_OPT_NONE*/,
10654+
insScalableOpts sopt /* = INS_SCALABLE_OPTS_NONE */)
1062410655
{
1062510656
emitAttr size = EA_SIZE(attr);
1062610657
insFormat fmt = IF_NONE;
@@ -10669,13 +10700,53 @@ void emitter::emitIns_R_R_R_R(instruction ins,
1066910700
case INS_sve_cmplo:
1067010701
case INS_sve_cmpls:
1067110702
case INS_sve_cmplt:
10672-
assert(insOptsScalableStandard(opt));
1067310703
assert(isPredicateRegister(reg1)); // DDDD
1067410704
assert(isLowPredicateRegister(reg2)); // ggg
10675-
assert(isVectorRegister(reg3)); // mmmmm
10676-
assert(isVectorRegister(reg4)); // nnnnn
10705+
assert(isVectorRegister(reg3)); // nnnnn
10706+
assert(isVectorRegister(reg4)); // mmmmm
10707+
assert(isScalableVectorSize(attr)); // xx
10708+
if (sopt == INS_SCALABLE_OPTS_WIDE)
10709+
{
10710+
assert(insOptsScalableWide(opt));
10711+
fmt = IF_SVE_CX_4A_A;
10712+
}
10713+
else
10714+
{
10715+
assert(insScalableOptsNone(sopt));
10716+
assert(insOptsScalableStandard(opt));
10717+
fmt = IF_SVE_CX_4A;
10718+
}
10719+
break;
10720+
10721+
case INS_sve_fcmeq:
10722+
case INS_sve_fcmge:
10723+
case INS_sve_facge:
10724+
case INS_sve_fcmgt:
10725+
case INS_sve_facgt:
10726+
case INS_sve_fcmlt:
10727+
case INS_sve_fcmle:
10728+
case INS_sve_fcmne:
10729+
case INS_sve_fcmuo:
10730+
case INS_sve_facle:
10731+
case INS_sve_faclt:
10732+
assert(insOptsScalableFloat(opt));
10733+
assert(isVectorRegister(reg3)); // nnnnn
10734+
assert(isVectorRegister(reg4)); // mmmmm
10735+
assert(isPredicateRegister(reg1)); // DDDD
10736+
assert(isLowPredicateRegister(reg2)); // ggg
1067710737
assert(isScalableVectorSize(attr)); // xx
10678-
fmt = IF_SVE_CX_4A;
10738+
fmt = IF_SVE_HT_4A;
10739+
break;
10740+
10741+
case INS_sve_match:
10742+
case INS_sve_nmatch:
10743+
assert(insOptsScalableAtMaxHalf(opt));
10744+
assert(isPredicateRegister(reg1)); // DDDD
10745+
assert(isLowPredicateRegister(reg2)); // ggg
10746+
assert(isVectorRegister(reg3)); // nnnnn
10747+
assert(isVectorRegister(reg4)); // mmmmm
10748+
assert(isScalableVectorSize(attr)); // xx
10749+
fmt = IF_SVE_GE_4A;
1067910750
break;
1068010751

1068110752
case INS_sve_mla:
@@ -10725,6 +10796,22 @@ void emitter::emitIns_R_R_R_R(instruction ins,
1072510796
std::swap(reg3, reg4);
1072610797
ins = INS_sve_cmpgt;
1072710798
break;
10799+
case INS_sve_facle:
10800+
std::swap(reg3, reg4);
10801+
ins = INS_sve_facge;
10802+
break;
10803+
case INS_sve_faclt:
10804+
std::swap(reg3, reg4);
10805+
ins = INS_sve_facgt;
10806+
break;
10807+
case INS_sve_fcmle:
10808+
std::swap(reg3, reg4);
10809+
ins = INS_sve_fcmge;
10810+
break;
10811+
case INS_sve_fcmlt:
10812+
std::swap(reg3, reg4);
10813+
ins = INS_sve_fcmgt;
10814+
break;
1072810815
default:
1072910816
break;
1073010817
}
@@ -16171,7 +16258,10 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
1617116258
dst += emitOutput_Instr(dst, code);
1617216259
break;
1617316260

16174-
case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
16261+
case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
16262+
case IF_SVE_CX_4A_A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
16263+
case IF_SVE_GE_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE2 character match
16264+
case IF_SVE_HT_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE floating-point compare vectors
1617516265
code = emitInsCodeSve(ins, fmt);
1617616266
code |= insEncodeReg_P_3_to_0(id->idReg1()); // DDDD
1617716267
code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg
@@ -18742,10 +18832,20 @@ void emitter::emitDispInsHelp(
1874218832

1874318833
// <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
1874418834
case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
18835+
case IF_SVE_GE_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE2 character match
18836+
case IF_SVE_HT_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE floating-point compare vectors
18837+
emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), true); // DDDD
18838+
emitDispPredicateReg(id->idReg2(), PREDICATE_ZERO, id->idInsOpt(), true); // ggg
18839+
emitDispSveReg(id->idReg3(), id->idInsOpt(), true); // nnnnn
18840+
emitDispSveReg(id->idReg4(), id->idInsOpt(), false); // mmmmm
18841+
break;
18842+
18843+
// <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
18844+
case IF_SVE_CX_4A_A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
1874518845
emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), true); // DDDD
1874618846
emitDispPredicateReg(id->idReg2(), PREDICATE_ZERO, id->idInsOpt(), true); // ggg
1874718847
emitDispSveReg(id->idReg3(), id->idInsOpt(), true); // mmmmm
18748-
emitDispSveReg(id->idReg4(), id->idInsOpt(), false); // nnnnn
18848+
emitDispSveReg(id->idReg4(), INS_OPTS_SCALABLE_D, false); // nnnnn
1874918849
break;
1875018850

1875118851
// <Zda>.<T>, <Pg>/M, <Zn>.<Tb>
@@ -21276,11 +21376,18 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
2127621376
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
2127721377
break;
2127821378

21279-
case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
21379+
case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
21380+
case IF_SVE_CX_4A_A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
2128021381
result.insLatency = PERFSCORE_LATENCY_4C;
2128121382
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
2128221383
break;
2128321384

21385+
case IF_SVE_GE_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE2 character match
21386+
case IF_SVE_HT_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE floating-point compare vectors
21387+
result.insLatency = PERFSCORE_LATENCY_2C;
21388+
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
21389+
break;
21390+
2128421391
// Extract/insert operation, SIMD and FP scalar form
2128521392
case IF_SVE_CR_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to SIMD&FP scalar register
2128621393
result.insLatency = PERFSCORE_LATENCY_3C;

‎src/coreclr/jit/emitarm64.h‎

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -995,6 +995,12 @@ inline static bool insOptsScalableAtLeastHalf(insOpts opt)
995995
return ((opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_S) || (opt == INS_OPTS_SCALABLE_D));
996996
}
997997

998+
inline static bool insOptsScalableAtMaxHalf(insOpts opt)
999+
{
1000+
// `opt` is any of the standard half and below scalable types.
1001+
return ((opt == INS_OPTS_SCALABLE_B) || (opt == INS_OPTS_SCALABLE_H));
1002+
}
1003+
9981004
inline static bool insOptsScalableFloat(insOpts opt)
9991005
{
10001006
// `opt` is any of the scalable types that are valid for FP.
@@ -1100,13 +1106,14 @@ void emitIns_R_R_R_Ext(instruction ins,
11001106
void emitIns_R_R_I_I(
11011107
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int imm1, int imm2, insOpts opt = INS_OPTS_NONE);
11021108

1103-
void emitIns_R_R_R_R(instruction ins,
1104-
emitAttr attr,
1105-
regNumber reg1,
1106-
regNumber reg2,
1107-
regNumber reg3,
1108-
regNumber reg4,
1109-
insOpts opt = INS_OPTS_NONE);
1109+
void emitIns_R_R_R_R(instruction ins,
1110+
emitAttr attr,
1111+
regNumber reg1,
1112+
regNumber reg2,
1113+
regNumber reg3,
1114+
regNumber reg4,
1115+
insOpts opt = INS_OPTS_NONE,
1116+
insScalableOpts sopt = INS_SCALABLE_OPTS_NONE);
11101117

11111118
void emitIns_R_COND(instruction ins, emitAttr attr, regNumber reg, insCond cond);
11121119

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