JIT: Avoid comparing regnums in GenTreeHWIntrinsic::Equals (#110535)

jakobbotsch · web-flow · commit f377332dfd3e · 2024-12-10T17:42:46.000+01:00
Register numbers are not part of the syntax of JIT IR, so it does not need to be compared for the purpose of this function. At the same time we can hit asserts for nodes that aren't multi-reg nodes. Fix #110316
diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
@@ -27624,8 +27624,7 @@ void GenTreeHWIntrinsic::SetHWIntrinsicId(NamedIntrinsic intrinsicId)
 {
     return (op1->TypeGet() == op2->TypeGet()) && (op1->GetHWIntrinsicId() == op2->GetHWIntrinsicId()) &&
            (op1->GetSimdBaseType() == op2->GetSimdBaseType()) && (op1->GetSimdSize() == op2->GetSimdSize()) &&
-           (op1->GetAuxiliaryType() == op2->GetAuxiliaryType()) && (op1->GetRegByIndex(1) == op2->GetRegByIndex(1)) &&
-           OperandsAreEqual(op1, op2);
+           (op1->GetAuxiliaryType() == op2->GetAuxiliaryType()) && OperandsAreEqual(op1, op2);
 }
 
 void GenTreeHWIntrinsic::Initialize(NamedIntrinsic intrinsicId)

Original file line number	Diff line number	Diff line change
`@@ -27624,8 +27624,7 @@ void GenTreeHWIntrinsic::SetHWIntrinsicId(NamedIntrinsic intrinsicId)`
`27624`	`27624`	`{`
`27625`	`27625`	`return (op1->TypeGet() == op2->TypeGet()) && (op1->GetHWIntrinsicId() == op2->GetHWIntrinsicId()) &&`
`27626`	`27626`	`(op1->GetSimdBaseType() == op2->GetSimdBaseType()) && (op1->GetSimdSize() == op2->GetSimdSize()) &&`
`27627`		`- (op1->GetAuxiliaryType() == op2->GetAuxiliaryType()) && (op1->GetRegByIndex(1) == op2->GetRegByIndex(1)) &&`
`27628`		`- OperandsAreEqual(op1, op2);`
	`27627`	`+ (op1->GetAuxiliaryType() == op2->GetAuxiliaryType()) && OperandsAreEqual(op1, op2);`
`27629`	`27628`	`}`
`27630`	`27629`
`27631`	`27630`	`void GenTreeHWIntrinsic::Initialize(NamedIntrinsic intrinsicId)`