diff --git a/src/coreclr/inc/clrconfigvalues.h b/src/coreclr/inc/clrconfigvalues.h index c556d45c495894..8be4aaa8eeef4f 100644 --- a/src/coreclr/inc/clrconfigvalues.h +++ b/src/coreclr/inc/clrconfigvalues.h @@ -798,6 +798,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha1, W("EnableArm64Sh RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha256, W("EnableArm64Sha256"), 1, "Allows Arm64 Sha256+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc, W("EnableArm64Rcpc"), 1, "Allows Arm64 Rcpc+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc2, W("EnableArm64Rcpc2"), 1, "Allows Arm64 Rcpc2+ hardware intrinsics to be disabled") +RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sve, W("EnableArm64Sve"), 1, "Allows Arm64 SVE hardware intrinsics to be disabled") #endif /// diff --git a/src/coreclr/inc/corinfoinstructionset.h b/src/coreclr/inc/corinfoinstructionset.h index 2ffd9bf6873201..e24bfab038ce0a 100644 --- a/src/coreclr/inc/corinfoinstructionset.h +++ b/src/coreclr/inc/corinfoinstructionset.h @@ -31,14 +31,16 @@ enum CORINFO_InstructionSet InstructionSet_Rcpc=13, InstructionSet_VectorT128=14, InstructionSet_Rcpc2=15, - InstructionSet_ArmBase_Arm64=16, - InstructionSet_AdvSimd_Arm64=17, - InstructionSet_Aes_Arm64=18, - InstructionSet_Crc32_Arm64=19, - InstructionSet_Dp_Arm64=20, - InstructionSet_Rdm_Arm64=21, - InstructionSet_Sha1_Arm64=22, - InstructionSet_Sha256_Arm64=23, + InstructionSet_Sve=16, + InstructionSet_ArmBase_Arm64=17, + InstructionSet_AdvSimd_Arm64=18, + InstructionSet_Aes_Arm64=19, + InstructionSet_Crc32_Arm64=20, + InstructionSet_Dp_Arm64=21, + InstructionSet_Rdm_Arm64=22, + InstructionSet_Sha1_Arm64=23, + InstructionSet_Sha256_Arm64=24, + InstructionSet_Sve_Arm64=25, #endif // TARGET_ARM64 #ifdef TARGET_AMD64 InstructionSet_X86Base=1, @@ -282,6 +284,8 @@ struct CORINFO_InstructionSetFlags AddInstructionSet(InstructionSet_Sha1_Arm64); if (HasInstructionSet(InstructionSet_Sha256)) AddInstructionSet(InstructionSet_Sha256_Arm64); + if (HasInstructionSet(InstructionSet_Sve)) + AddInstructionSet(InstructionSet_Sve_Arm64); #endif // TARGET_ARM64 #ifdef TARGET_AMD64 if (HasInstructionSet(InstructionSet_X86Base)) @@ -394,6 +398,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_Sha256); if (resultflags.HasInstructionSet(InstructionSet_Sha256_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sha256)) resultflags.RemoveInstructionSet(InstructionSet_Sha256_Arm64); + if (resultflags.HasInstructionSet(InstructionSet_Sve) && !resultflags.HasInstructionSet(InstructionSet_Sve_Arm64)) + resultflags.RemoveInstructionSet(InstructionSet_Sve); + if (resultflags.HasInstructionSet(InstructionSet_Sve_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sve)) + resultflags.RemoveInstructionSet(InstructionSet_Sve_Arm64); if (resultflags.HasInstructionSet(InstructionSet_AdvSimd) && !resultflags.HasInstructionSet(InstructionSet_ArmBase)) resultflags.RemoveInstructionSet(InstructionSet_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet_Aes) && !resultflags.HasInstructionSet(InstructionSet_ArmBase)) @@ -414,6 +422,8 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_Vector128); if (resultflags.HasInstructionSet(InstructionSet_VectorT128) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd)) resultflags.RemoveInstructionSet(InstructionSet_VectorT128); + if (resultflags.HasInstructionSet(InstructionSet_Sve) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd)) + resultflags.RemoveInstructionSet(InstructionSet_Sve); #endif // TARGET_ARM64 #ifdef TARGET_AMD64 if (resultflags.HasInstructionSet(InstructionSet_X86Base) && !resultflags.HasInstructionSet(InstructionSet_X86Base_X64)) @@ -764,6 +774,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet) return "VectorT128"; case InstructionSet_Rcpc2 : return "Rcpc2"; + case InstructionSet_Sve : + return "Sve"; + case InstructionSet_Sve_Arm64 : + return "Sve_Arm64"; #endif // TARGET_ARM64 #ifdef TARGET_AMD64 case InstructionSet_X86Base : @@ -998,6 +1012,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst case READYTORUN_INSTRUCTION_Rcpc: return InstructionSet_Rcpc; case READYTORUN_INSTRUCTION_VectorT128: return InstructionSet_VectorT128; case READYTORUN_INSTRUCTION_Rcpc2: return InstructionSet_Rcpc2; + case READYTORUN_INSTRUCTION_Sve: return InstructionSet_Sve; #endif // TARGET_ARM64 #ifdef TARGET_AMD64 case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base; diff --git a/src/coreclr/inc/jiteeversionguid.h b/src/coreclr/inc/jiteeversionguid.h index 70960ff577ee8a..139ec31efae5d4 100644 --- a/src/coreclr/inc/jiteeversionguid.h +++ b/src/coreclr/inc/jiteeversionguid.h @@ -43,13 +43,13 @@ typedef const GUID *LPCGUID; #define GUID_DEFINED #endif // !GUID_DEFINED -constexpr GUID JITEEVersionIdentifier = { /* a2974440-e8ee-4d95-9e6e-799a330be1a0 */ - 0xa2974440, - 0xe8ee, - 0x4d95, - {0x9e, 0x6e, 0x79, 0x9a, 0x33, 0x0b, 0xe1, 0xa0} +constexpr GUID JITEEVersionIdentifier = { /* e15e62ce-d9c6-418a-a5a7-26ad17fcf4bf */ + 0xe15e62ce, + 0xd9c6, + 0x418a, + {0xa5, 0xa7, 0x26, 0xad, 0x17, 0xfc, 0xf4, 0xbf} }; - + ////////////////////////////////////////////////////////////////////////////////////////////////////////// // // END JITEEVersionIdentifier diff --git a/src/coreclr/inc/readytoruninstructionset.h b/src/coreclr/inc/readytoruninstructionset.h index 190fe4b516617e..4ec3b030ae5bbb 100644 --- a/src/coreclr/inc/readytoruninstructionset.h +++ b/src/coreclr/inc/readytoruninstructionset.h @@ -51,6 +51,7 @@ enum ReadyToRunInstructionSet READYTORUN_INSTRUCTION_VectorT256=40, READYTORUN_INSTRUCTION_VectorT512=41, READYTORUN_INSTRUCTION_Rcpc2=42, + READYTORUN_INSTRUCTION_Sve=43, }; diff --git a/src/coreclr/jit/CMakeLists.txt b/src/coreclr/jit/CMakeLists.txt index 30e9ad972dab62..a1b8cbb9a249de 100644 --- a/src/coreclr/jit/CMakeLists.txt +++ b/src/coreclr/jit/CMakeLists.txt @@ -398,8 +398,11 @@ set( JIT_I386_HEADERS ${JIT_AMD64_HEADERS} ) set( JIT_ARM64_HEADERS emitarm64.h emitfmtsarm64.h + emitfmtsarm64sve.h hwintrinsiclistarm64.h + hwintrinsiclistarm64sve.h instrsarm64.h + instrsarm64sve.h registerarm64.h simdashwintrinsiclistarm64.h ) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 4d1a2fd36f43fd..0650ab9ded57c1 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -6702,6 +6702,14 @@ void CodeGen::genArm64EmitterUnitTests() theEmitter->emitIns_R_R_R(INS_asrv, EA_4BYTE, REG_R8, REG_R9, REG_R10); theEmitter->emitIns_R_R_R(INS_rorv, EA_4BYTE, REG_R8, REG_R9, REG_R10); + // TODO-SVE: Fix once we add predicate registers + theEmitter->emitIns_R_R_R(INS_sve_uzp1, EA_8BYTE, REG_R0, REG_R1, REG_R2, + INS_OPTS_8B); // UZP1 ., ., . + theEmitter->emitIns_R_R_R(INS_sve_uzp1, EA_8BYTE, REG_R0, REG_R1, REG_R2, + INS_OPTS_8B); // UZP1 .Q, .Q, .Q + theEmitter->emitIns_R_R_R(INS_sve_uzp1, EA_8BYTE, REG_R0, REG_R1, REG_R2, + INS_OPTS_8B); // UZP1 ., ., . + #endif // ALL_ARM64_EMITTER_UNIT_TESTS #ifdef ALL_ARM64_EMITTER_UNIT_TESTS diff --git a/src/coreclr/jit/compiler.cpp b/src/coreclr/jit/compiler.cpp index 435f9d5e1cafc3..ca3342c99d0cab 100644 --- a/src/coreclr/jit/compiler.cpp +++ b/src/coreclr/jit/compiler.cpp @@ -6013,6 +6013,11 @@ int Compiler::compCompile(CORINFO_MODULE_HANDLE classPtr, { instructionSetFlags.AddInstructionSet(InstructionSet_Dczva); } + + if (JitConfig.EnableArm64Sve() != 0) + { + instructionSetFlags.AddInstructionSet(InstructionSet_Sve); + } #elif defined(TARGET_XARCH) if (JitConfig.EnableHWIntrinsic() != 0) { diff --git a/src/coreclr/jit/emit.cpp b/src/coreclr/jit/emit.cpp index 2de959b0872479..ae337cb76c9ebc 100644 --- a/src/coreclr/jit/emit.cpp +++ b/src/coreclr/jit/emit.cpp @@ -130,6 +130,10 @@ const char* emitter::emitIfName(unsigned f) static const char* const ifNames[] = { #define IF_DEF(en, op1, op2) "IF_" #en, #include "emitfmts.h" +#if defined(TARGET_ARM64) +#define IF_DEF(en, op1, op2) "IF_" #en, +#include "emitfmtsarm64sve.h" +#endif }; static char errBuff[32]; @@ -3767,6 +3771,10 @@ emitter::instrDesc* emitter::emitNewInstrCallDir(int argCnt, const BYTE emitter::emitFmtToOps[] = { #define IF_DEF(en, op1, op2) ID_OP_##op2, #include "emitfmts.h" +#if defined(TARGET_ARM64) +#define IF_DEF(en, op1, op2) ID_OP_##op2, +#include "emitfmtsarm64sve.h" +#endif }; #ifdef DEBUG diff --git a/src/coreclr/jit/emit.h b/src/coreclr/jit/emit.h index 94ded1df85fcdf..d7fb0f31e4f2c2 100644 --- a/src/coreclr/jit/emit.h +++ b/src/coreclr/jit/emit.h @@ -565,7 +565,10 @@ class emitter { #define IF_DEF(en, op1, op2) IF_##en, #include "emitfmts.h" - +#if defined(TARGET_ARM64) +#define IF_DEF(en, op1, op2) IF_##en, +#include "emitfmtsarm64sve.h" +#endif IF_COUNT }; @@ -628,8 +631,8 @@ class emitter #define MAX_ENCODED_SIZE 15 #elif defined(TARGET_ARM64) #define INSTR_ENCODED_SIZE 4 - static_assert_no_msg(INS_count <= 1024); - instruction _idIns : 10; + static_assert_no_msg(INS_count <= 2048); + instruction _idIns : 11; #elif defined(TARGET_LOONGARCH64) // TODO-LoongArch64: not include SIMD-vector. static_assert_no_msg(INS_count <= 512); @@ -647,6 +650,9 @@ class emitter unsigned _idCodeSize : 5; // the instruction(s) size of this instrDesc described. #elif defined(TARGET_RISCV64) unsigned _idCodeSize : 6; // the instruction(s) size of this instrDesc described. +#elif defined(TARGET_ARM64) + static_assert_no_msg(IF_COUNT <= 1024); + insFormat _idInsFmt : 10; #else static_assert_no_msg(IF_COUNT <= 256); insFormat _idInsFmt : 8; @@ -712,7 +718,7 @@ class emitter // x86: 17 bits // amd64: 17 bits // arm: 16 bits - // arm64: 18 bits + // arm64: 21 bits // loongarch64: 14 bits // risc-v: 14 bits @@ -722,10 +728,13 @@ class emitter opSize _idOpSize : 3; // operand size: 0=1 , 1=2 , 2=4 , 3=8, 4=16, 5=32 // At this point we have fully consumed first DWORD so that next field // doesn't cross a byte boundary. -#elif defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64) +#elif defined(TARGET_ARM64) + opSize _idOpSize : 3; // operand size: 0=1 , 1=2 , 2=4 , 3=8, 4=16 + insOpts _idInsOpt : 6; // options for instructions +#elif defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64) /* _idOpSize defined below. */ #else - opSize _idOpSize : 2; // operand size: 0=1 , 1=2 , 2=4 , 3=8 + opSize _idOpSize : 2; // operand size: 0=1 , 1=2 , 2=4 , 3=8 #endif // TARGET_ARM64 || TARGET_LOONGARCH64 || TARGET_RISCV64 // On Amd64, this is where the second DWORD begins @@ -754,7 +763,7 @@ class emitter // x86: 38 bits // amd64: 38 bits // arm: 32 bits - // arm64: 32 bits + // arm64: 44 bits // loongarch64: 28 bits // risc-v: 28 bits @@ -774,8 +783,7 @@ class emitter #endif // TARGET_XARCH #ifdef TARGET_ARM64 - opSize _idOpSize : 3; // operand size: 0=1 , 1=2 , 2=4 , 3=8, 4=16 - insOpts _idInsOpt : 6; // options for instructions + unsigned _idLclVar : 1; // access a local on stack unsigned _idLclVarPair : 1 // carries information for 2 GC lcl vars. #endif @@ -808,7 +816,7 @@ class emitter // x86: 47 bits // amd64: 47 bits // arm: 48 bits - // arm64: 50 bits + // arm64: 53 bits // loongarch64: 46 bits // risc-v: 46 bits @@ -821,7 +829,7 @@ class emitter #if defined(TARGET_ARM) #define ID_EXTRA_BITFIELD_BITS (16) #elif defined(TARGET_ARM64) -#define ID_EXTRA_BITFIELD_BITS (18) +#define ID_EXTRA_BITFIELD_BITS (21) #elif defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64) #define ID_EXTRA_BITFIELD_BITS (14) #elif defined(TARGET_XARCH) @@ -863,7 +871,7 @@ class emitter // x86: 53/49 bits // amd64: 54/49 bits // arm: 54/50 bits - // arm64: 57/52 bits + // arm64: 60/55 bits // loongarch64: 53/48 bits // risc-v: 53/48 bits CLANG_FORMAT_COMMENT_ANCHOR; @@ -880,7 +888,7 @@ class emitter // x86: 11/15 bits // amd64: 10/15 bits // arm: 10/14 bits - // arm64: 7/12 bits + // arm64: 4/9 bits // loongarch64: 11/16 bits // risc-v: 11/16 bits CLANG_FORMAT_COMMENT_ANCHOR; @@ -1132,7 +1140,7 @@ class emitter _idCodeSize = sz; } #elif defined(TARGET_RISCV64) - unsigned idCodeSize() const + unsigned idCodeSize() const { return _idCodeSize; } diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 5e0b4f2e78a959..b1c3b538d9ff98 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -943,6 +943,31 @@ void emitter::emitInsSanityCheck(instrDesc* id) assert(datasize == EA_8BYTE); break; + case IF_SVE_BR_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments + elemsize = id->idOpSize(); + assert(insOptsNone(id->idInsOpt())); + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isVectorRegister(id->idReg2())); // nnnnn + assert(isVectorRegister(id->idReg3())); // mmmmm + assert(isValidVectorElemsize(elemsize)); // xx + break; + + case IF_SVE_BR_3B: // ...........mmmmm ......nnnnnddddd -- SVE permute vector segments + assert(insOptsNone(id->idInsOpt())); + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isVectorRegister(id->idReg2())); // nnnnn + assert(isVectorRegister(id->idReg3())); // mmmmm + break; + + case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements + elemsize = id->idOpSize(); + assert(insOptsNone(id->idInsOpt())); + assert(isPredicateRegister(id->idReg1())); // DDDD + assert(isPredicateRegister(id->idReg2())); // NNNN + assert(isPredicateRegister(id->idReg3())); // MMMM + assert(isValidVectorElemsize(elemsize)); // xx + break; + default: printf("unexpected format %s\n", emitIfName(id->idInsFmt())); assert(!"Unexpected format"); @@ -1021,6 +1046,10 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id) case IF_DV_3F: // DV_3F .Q......XX.mmmmm ......nnnnnddddd Vd Vn Vm (vector) case IF_DV_3G: // DV_3G .Q.........mmmmm .iiii.nnnnnddddd Vd Vn Vm imm (vector) case IF_DV_4A: // DV_4A .........X.mmmmm .aaaaannnnnddddd Vd Va Vn Vm (scalar) + + case IF_SVE_BR_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments + case IF_SVE_EF_3A: // ...........mmmmm ......nnnnnddddd -- SVE two-way dot product + case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements // Tracked GC pointers cannot be placed into the SIMD registers. return false; @@ -1420,6 +1449,25 @@ const char* emitter::emitVectorRegName(regNumber reg) return vRegNames[index]; } +//------------------------------------------------------------------------ +// emitPredicateRegName: Returns a predicate register name. +// +// Arguments: +// reg - A predicate register. +// +// Return value: +// A string that represents a predicate register name. +// +const char* emitter::emitPredicateRegName(regNumber reg) +{ + // TODO-SVE: Fix once we add predicate registers + assert((reg >= REG_V0) && (reg <= REG_V31)); + + int index = (int)reg - (int)REG_V0; + + return vRegNames[index]; +} + /***************************************************************************** * * Returns the base encoding of the given CPU instruction. @@ -1438,6 +1486,18 @@ emitter::insFormat emitter::emitInsFormat(instruction ins) #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) fmt, #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) fmt, #include "instrs.h" + #define INST1(id, nm, info, fmt, e1 ) fmt, + #define INST2(id, nm, info, fmt, e1, e2 ) fmt, + #define INST3(id, nm, info, fmt, e1, e2, e3 ) fmt, + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) fmt, + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) fmt, + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) fmt, + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) fmt, + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) fmt, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) fmt, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10,e11 ) fmt, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13) fmt, + #include "instrsarm64sve.h" }; // clang-format on @@ -1764,476 +1824,1924 @@ emitter::code_t emitter::emitInsCode(instruction ins, insFormat fmt) case IF_EN6A: for (index = 0; index < 6; index++) { - if (fmt == formatEncode6A[index]) + if (fmt == formatEncode6A[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN6B: + for (index = 0; index < 6; index++) + { + if (fmt == formatEncode6B[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN5A: + for (index = 0; index < 5; index++) + { + if (fmt == formatEncode5A[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN5B: + for (index = 0; index < 5; index++) + { + if (fmt == formatEncode5B[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN5C: + for (index = 0; index < 5; index++) + { + if (fmt == formatEncode5C[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4A: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4A[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4B: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4B[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4C: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4C[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4D: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4D[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4E: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4E[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4F: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4F[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4G: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4G[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4H: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4H[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4I: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4I[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4J: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4J[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN4K: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4K[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN3A: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3A[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN3B: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3B[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN3C: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3C[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN3D: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3D[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN3E: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3E[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN3F: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3F[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN3G: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3G[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN3H: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3H[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN3I: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3I[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN3J: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3J[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2A: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2A[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2B: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2B[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2C: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2C[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2D: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2D[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2E: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2E[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2F: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2F[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2G: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2G[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2H: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2H[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2I: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2I[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2J: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2J[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2K: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2K[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2L: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2L[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2M: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2M[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2N: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2N[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2O: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2O[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2P: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2P[index]) + { + encoding_found = true; + break; + } + } + break; + + case IF_EN2Q: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2Q[index]) + { + encoding_found = true; + break; + } + } + break; + + default: + if (fmt == insFmt) + { + encoding_found = true; + index = 0; + } + else + { + encoding_found = false; + } + break; + } + + assert(encoding_found); + + switch (index) + { + case 0: + assert(ins < ArrLen(insCodes1)); + code = insCodes1[ins]; + break; + case 1: + assert(ins < ArrLen(insCodes2)); + code = insCodes2[ins]; + break; + case 2: + assert(ins < ArrLen(insCodes3)); + code = insCodes3[ins]; + break; + case 3: + assert(ins < ArrLen(insCodes4)); + code = insCodes4[ins]; + break; + case 4: + assert(ins < ArrLen(insCodes5)); + code = insCodes5[ins]; + break; + case 5: + assert(ins < ArrLen(insCodes6)); + code = insCodes6[ins]; + break; + case 6: + assert(ins < ArrLen(insCodes7)); + code = insCodes7[ins]; + break; + case 7: + assert(ins < ArrLen(insCodes8)); + code = insCodes8[ins]; + break; + case 8: + assert(ins < ArrLen(insCodes9)); + code = insCodes9[ins]; + break; + } + + assert((code != BAD_CODE)); + + return code; +} + +/***************************************************************************** + * + * Returns the specific encoding of the given CPU instruction and format + */ + +emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt) +{ + // clang-format off + const static code_t insCodes1[] = + { + #define INST1(id, nm, info, fmt, e1 ) e1, + #define INST2(id, nm, info, fmt, e1, e2 ) e1, + #define INST3(id, nm, info, fmt, e1, e2, e3 ) e1, + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) e1, + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) e1, + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) e1, + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) e1, + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e1, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) e1, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e1, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e1, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes2[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) e2, + #define INST3(id, nm, info, fmt, e1, e2, e3 ) e2, + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) e2, + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) e2, + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) e2, + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) e2, + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e2, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) e2, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e2, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e2, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes3[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) e3, + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) e3, + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) e3, + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) e3, + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) e3, + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e3, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) e3, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e3, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e3, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes4[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) e4, + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) e4, + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) e4, + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) e4, + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e4, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) e4, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e4, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e4, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes5[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) e5, + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) e5, + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) e5, + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e5, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) e5, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e5, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e5, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes6[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) e6, + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) e6, + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e6, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) e6, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e6, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e6, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes7[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) e7, + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e7, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) e7, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e7, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e7, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes8[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e8, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) e8, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e8, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e8, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes9[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) e9, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e9, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e9, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes10[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e10, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e10, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes11[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) e11, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e11, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes12[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e12, + #include "instrsarm64sve.h" + }; + + const static code_t insCodes13[] = + { + #define INST1(id, nm, info, fmt, e1 ) + #define INST2(id, nm, info, fmt, e1, e2 ) + #define INST3(id, nm, info, fmt, e1, e2, e3 ) + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11 ) + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13 ) e13, + #include "instrsarm64sve.h" + }; + + // clang-format on + const static insFormat formatEncode13A[13] = {IF_SVE_AU_3A, IF_SVE_BT_1A, IF_SVE_BV_2A, IF_SVE_BV_2A_J, + IF_SVE_BW_2A, IF_SVE_CB_2A, IF_SVE_CP_3A, IF_SVE_CQ_3A, + IF_SVE_CW_4A, IF_SVE_CZ_4A, IF_SVE_CZ_4A_K, IF_SVE_CZ_4A_L, + IF_SVE_EB_1A}; + const static insFormat formatEncode11A[11] = {IF_SVE_JD_4B, IF_SVE_JD_4C, IF_SVE_JI_3A_A, IF_SVE_JJ_4A, + IF_SVE_JJ_4A_B, IF_SVE_JJ_4A_C, IF_SVE_JJ_4A_D, IF_SVE_JJ_4B, + IF_SVE_JJ_4B_E, IF_SVE_JN_3B, IF_SVE_JN_3C}; + const static insFormat formatEncode9A[9] = {IF_SVE_HW_4A, IF_SVE_HW_4A_A, IF_SVE_HW_4A_B, + IF_SVE_HW_4A_C, IF_SVE_HW_4B, IF_SVE_HW_4B_D, + IF_SVE_HX_3A_E, IF_SVE_IJ_3A_F, IF_SVE_IK_4A_G}; + const static insFormat formatEncode9B[9] = {IF_SVE_HW_4A, IF_SVE_HW_4A_A, IF_SVE_HW_4A_B, + IF_SVE_HW_4A_C, IF_SVE_HW_4B, IF_SVE_HW_4B_D, + IF_SVE_HX_3A_E, IF_SVE_IJ_3A_G, IF_SVE_IK_4A_I}; + const static insFormat formatEncode9C[9] = {IF_SVE_HW_4A, IF_SVE_HW_4A_A, IF_SVE_HW_4A_B, + IF_SVE_HW_4A_C, IF_SVE_HW_4B, IF_SVE_HW_4B_D, + IF_SVE_HX_3A_E, IF_SVE_IH_3A_F, IF_SVE_II_4A_H}; + const static insFormat formatEncode9D[9] = {IF_SVE_IH_3A, IF_SVE_IH_3A_A, IF_SVE_II_4A, + IF_SVE_II_4A_B, IF_SVE_IU_4A, IF_SVE_IU_4A_C, + IF_SVE_IU_4B, IF_SVE_IU_4B_D, IF_SVE_IV_3A}; + const static insFormat formatEncode9E[9] = {IF_SVE_JD_4A, IF_SVE_JI_3A_A, IF_SVE_JJ_4A, + IF_SVE_JJ_4A_B, IF_SVE_JJ_4A_C, IF_SVE_JJ_4A_D, + IF_SVE_JJ_4B, IF_SVE_JJ_4B_E, IF_SVE_JN_3A}; + const static insFormat formatEncode9F[9] = {IF_SVE_JD_4C, IF_SVE_JD_4C_A, IF_SVE_JJ_4A, + IF_SVE_JJ_4A_B, IF_SVE_JJ_4B, IF_SVE_JJ_4B_C, + IF_SVE_JL_3A, IF_SVE_JN_3C, IF_SVE_JN_3C_D}; + const static insFormat formatEncode8A[8] = {IF_SVE_CE_2A, IF_SVE_CE_2B, IF_SVE_CE_2C, IF_SVE_CE_2D, + IF_SVE_CF_2A, IF_SVE_CF_2B, IF_SVE_CF_2C, IF_SVE_CF_2D}; + const static insFormat formatEncode8B[8] = {IF_SVE_HW_4A, IF_SVE_HW_4A_A, IF_SVE_HW_4A_B, IF_SVE_HW_4A_C, + IF_SVE_HW_4B, IF_SVE_HW_4B_D, IF_SVE_HX_3A_E, IF_SVE_IG_4A_F}; + const static insFormat formatEncode8C[8] = {IF_SVE_HW_4A, IF_SVE_HW_4A_A, IF_SVE_HW_4A_B, IF_SVE_HW_4A_C, + IF_SVE_HW_4B, IF_SVE_HW_4B_D, IF_SVE_HX_3A_E, IF_SVE_IG_4A_G}; + const static insFormat formatEncode7A[7] = {IF_SVE_IJ_3A, IF_SVE_IK_4A, IF_SVE_IU_4A, IF_SVE_IU_4A_A, + IF_SVE_IU_4B, IF_SVE_IU_4B_B, IF_SVE_IV_3A}; + const static insFormat formatEncode6A[6] = {IF_SVE_AE_3A, IF_SVE_BD_3A, IF_SVE_EE_1A, + IF_SVE_FD_3A, IF_SVE_FD_3B, IF_SVE_FD_3C}; + const static insFormat formatEncode6B[6] = {IF_SVE_GY_3A, IF_SVE_GY_3B, IF_SVE_GY_3B_D, + IF_SVE_HA_3A, IF_SVE_HA_3A_E, IF_SVE_HA_3A_F}; + const static insFormat formatEncode6C[6] = {IF_SVE_HW_4A, IF_SVE_HW_4A_A, IF_SVE_HW_4B, + IF_SVE_HX_3A_B, IF_SVE_IJ_3A_D, IF_SVE_IK_4A_F}; + const static insFormat formatEncode6D[6] = {IF_SVE_HW_4A, IF_SVE_HW_4A_A, IF_SVE_HW_4B, + IF_SVE_HX_3A_B, IF_SVE_IJ_3A_E, IF_SVE_IK_4A_H}; + const static insFormat formatEncode6E[6] = {IF_SVE_HY_3A, IF_SVE_HY_3A_A, IF_SVE_HY_3B, + IF_SVE_HZ_2A_B, IF_SVE_IA_2A, IF_SVE_IB_3A}; + const static insFormat formatEncode6F[6] = {IF_SVE_IG_4A, IF_SVE_IU_4A, IF_SVE_IU_4A_A, + IF_SVE_IU_4B, IF_SVE_IU_4B_B, IF_SVE_IV_3A}; + const static insFormat formatEncode6G[6] = {IF_SVE_JD_4A, IF_SVE_JI_3A_A, IF_SVE_JK_4A, + IF_SVE_JK_4A_B, IF_SVE_JK_4B, IF_SVE_JN_3A}; + const static insFormat formatEncode5A[5] = {IF_SVE_AM_2A, IF_SVE_AN_3A, IF_SVE_AO_3A, IF_SVE_BF_2A, IF_SVE_BG_3A}; + const static insFormat formatEncode5B[5] = {IF_SVE_GX_3A, IF_SVE_GX_3B, IF_SVE_HK_3A, IF_SVE_HL_3A, IF_SVE_HM_2A}; + const static insFormat formatEncode5C[5] = {IF_SVE_EF_3A, IF_SVE_EG_3A, IF_SVE_EH_3A, IF_SVE_EY_3A, IF_SVE_EY_3B}; + const static insFormat formatEncode5D[5] = {IF_SVE_HW_4A, IF_SVE_HW_4A_A, IF_SVE_HW_4B, IF_SVE_HX_3A_B, + IF_SVE_IG_4A_D}; + const static insFormat formatEncode5E[5] = {IF_SVE_HW_4A, IF_SVE_HW_4A_A, IF_SVE_HW_4B, IF_SVE_HX_3A_B, + IF_SVE_IG_4A_E}; + const static insFormat formatEncode4A[4] = {IF_SVE_AA_3A, IF_SVE_AU_3A, IF_SVE_BS_1A, IF_SVE_CZ_4A}; + const static insFormat formatEncode4B[4] = {IF_SVE_BU_2A, IF_SVE_BV_2B, IF_SVE_EA_1A, IF_SVE_EB_1B}; + const static insFormat formatEncode4C[4] = {IF_SVE_HS_3A, IF_SVE_HS_3A_H, IF_SVE_HS_3A_I, IF_SVE_HS_3A_J}; + const static insFormat formatEncode4D[4] = {IF_SVE_HP_3B, IF_SVE_HP_3B_H, IF_SVE_HP_3B_I, IF_SVE_HP_3B_J}; + const static insFormat formatEncode4E[4] = {IF_SVE_BE_3A, IF_SVE_FI_3A, IF_SVE_FI_3B, IF_SVE_FI_3C}; + const static insFormat formatEncode4F[4] = {IF_SVE_EM_3A, IF_SVE_FK_3A, IF_SVE_FK_3B, IF_SVE_FK_3C}; + const static insFormat formatEncode4G[4] = {IF_SVE_AR_4A, IF_SVE_FF_3A, IF_SVE_FF_3B, IF_SVE_FF_3C}; + const static insFormat formatEncode4H[4] = {IF_SVE_GM_3A, IF_SVE_GN_3A, IF_SVE_GZ_3A, IF_SVE_HB_3A}; + const static insFormat formatEncode4I[4] = {IF_SVE_AX_1A, IF_SVE_AY_2A, IF_SVE_AZ_2A, IF_SVE_BA_3A}; + const static insFormat formatEncode4J[4] = {IF_SVE_BV_2A, IF_SVE_BV_2A_A, IF_SVE_CP_3A, IF_SVE_CQ_3A}; + const static insFormat formatEncode4K[4] = {IF_SVE_IF_4A, IF_SVE_IF_4A_A, IF_SVE_IM_3A, IF_SVE_IN_4A}; + const static insFormat formatEncode4L[4] = {IF_SVE_IZ_4A, IF_SVE_IZ_4A_A, IF_SVE_JB_4A, IF_SVE_JM_3A}; + const static insFormat formatEncode3A[3] = {IF_SVE_AB_3A, IF_SVE_AT_3A, IF_SVE_EC_1A}; + const static insFormat formatEncode3B[3] = {IF_SVE_BH_3A, IF_SVE_BH_3B, IF_SVE_BH_3B_A}; + const static insFormat formatEncode3C[3] = {IF_SVE_BW_2A, IF_SVE_CB_2A, IF_SVE_EB_1A}; + const static insFormat formatEncode3D[3] = {IF_SVE_BR_3A, IF_SVE_BR_3B, IF_SVE_CI_3A}; + const static insFormat formatEncode3E[3] = {IF_SVE_AT_3A, IF_SVE_EC_1A, IF_SVE_ET_3A}; + const static insFormat formatEncode3F[3] = {IF_SVE_GU_3A, IF_SVE_GU_3B, IF_SVE_HU_4A}; + const static insFormat formatEncode3G[3] = {IF_SVE_GH_3A, IF_SVE_GH_3B, IF_SVE_GH_3B_B}; + const static insFormat formatEncode3H[3] = {IF_SVE_HK_3A, IF_SVE_HL_3A, IF_SVE_HM_2A}; + const static insFormat formatEncode3I[3] = {IF_SVE_CM_3A, IF_SVE_CN_3A, IF_SVE_CO_3A}; + const static insFormat formatEncode3J[3] = {IF_SVE_CX_4A, IF_SVE_CX_4A_A, IF_SVE_CY_3A}; + const static insFormat formatEncode3K[3] = {IF_SVE_CX_4A, IF_SVE_CX_4A_A, IF_SVE_CY_3B}; + const static insFormat formatEncode3L[3] = {IF_SVE_DT_3A, IF_SVE_DX_3A, IF_SVE_DY_3A}; + const static insFormat formatEncode3M[3] = {IF_SVE_EJ_3A, IF_SVE_FA_3A, IF_SVE_FA_3B}; + const static insFormat formatEncode3N[3] = {IF_SVE_EK_3A, IF_SVE_FB_3A, IF_SVE_FB_3B}; + const static insFormat formatEncode3O[3] = {IF_SVE_EK_3A, IF_SVE_FC_3A, IF_SVE_FC_3B}; + const static insFormat formatEncode3P[3] = {IF_SVE_EL_3A, IF_SVE_FG_3A, IF_SVE_FG_3B}; + const static insFormat formatEncode3Q[3] = {IF_SVE_EO_3A, IF_SVE_FJ_3A, IF_SVE_FJ_3B}; + const static insFormat formatEncode3R[3] = {IF_SVE_FE_3A, IF_SVE_FE_3B, IF_SVE_FN_3A}; + const static insFormat formatEncode3S[3] = {IF_SVE_FH_3A, IF_SVE_FH_3B, IF_SVE_FN_3A}; + const static insFormat formatEncode3T[3] = {IF_SVE_GX_3C, IF_SVE_HK_3B, IF_SVE_HL_3B}; + const static insFormat formatEncode3U[3] = {IF_SVE_IM_3A, IF_SVE_IN_4A, IF_SVE_IX_4A}; + const static insFormat formatEncode3V[3] = {IF_SVE_JA_4A, IF_SVE_JB_4A, IF_SVE_JM_3A}; + const static insFormat formatEncode2AA[2] = {IF_SVE_ID_2A, IF_SVE_IE_2A}; + const static insFormat formatEncode2AB[2] = {IF_SVE_JG_2A, IF_SVE_JH_2A}; + const static insFormat formatEncode2AC[2] = {IF_SVE_AD_3A, IF_SVE_ED_1A}; + const static insFormat formatEncode2AD[2] = {IF_SVE_AB_3B, IF_SVE_AT_3B}; + const static insFormat formatEncode2AE[2] = {IF_SVE_CG_2A, IF_SVE_CJ_2A}; + const static insFormat formatEncode2AF[2] = {IF_SVE_AE_3A, IF_SVE_BD_3A}; + const static insFormat formatEncode2AG[2] = {IF_SVE_BS_1A, IF_SVE_CZ_4A}; + const static insFormat formatEncode2AH[2] = {IF_SVE_BQ_2A, IF_SVE_BQ_2B}; + const static insFormat formatEncode2AI[2] = {IF_SVE_AM_2A, IF_SVE_EU_3A}; + const static insFormat formatEncode2AJ[2] = {IF_SVE_HI_3A, IF_SVE_HT_4A}; + const static insFormat formatEncode2AK[2] = {IF_SVE_BZ_3A, IF_SVE_BZ_3A_A}; + const static insFormat formatEncode2AL[2] = {IF_SVE_GG_3A, IF_SVE_GG_3B}; + const static insFormat formatEncode2AM[2] = {IF_SVE_HL_3A, IF_SVE_HM_2A}; + const static insFormat formatEncode2AN[2] = {IF_SVE_EI_3A, IF_SVE_EZ_3A}; + const static insFormat formatEncode2AO[2] = {IF_SVE_GT_4A, IF_SVE_GV_3A}; + const static insFormat formatEncode2AP[2] = {IF_SVE_GY_3B, IF_SVE_HA_3A}; + const static insFormat formatEncode2AQ[2] = {IF_SVE_GO_3A, IF_SVE_HC_3A}; + const static insFormat formatEncode2AR[2] = {IF_SVE_AP_3A, IF_SVE_CZ_4A}; + const static insFormat formatEncode2AS[2] = {IF_SVE_HO_3A, IF_SVE_HO_3A_B}; + const static insFormat formatEncode2AT[2] = {IF_SVE_AB_3A, IF_SVE_EC_1A}; + const static insFormat formatEncode2AU[2] = {IF_SVE_AH_3A, IF_SVE_BI_2A}; + const static insFormat formatEncode2AV[2] = {IF_SVE_BM_1A, IF_SVE_BN_1A}; + const static insFormat formatEncode2AW[2] = {IF_SVE_BO_1A, IF_SVE_BP_1A}; + const static insFormat formatEncode2AX[2] = {IF_SVE_CC_2A, IF_SVE_CD_2A}; + const static insFormat formatEncode2AY[2] = {IF_SVE_CR_3A, IF_SVE_CS_3A}; + const static insFormat formatEncode2AZ[2] = {IF_SVE_CV_3A, IF_SVE_CV_3B}; + const static insFormat formatEncode2BA[2] = {IF_SVE_CW_4A, IF_SVE_CZ_4A}; + const static insFormat formatEncode2BB[2] = {IF_SVE_CZ_4A, IF_SVE_CZ_4A_A}; + const static insFormat formatEncode2BC[2] = {IF_SVE_DE_1A, IF_SVE_DZ_1A}; + const static insFormat formatEncode2BD[2] = {IF_SVE_DG_2A, IF_SVE_DH_1A}; + const static insFormat formatEncode2BE[2] = {IF_SVE_DK_3A, IF_SVE_DL_2A}; + const static insFormat formatEncode2BF[2] = {IF_SVE_DM_2A, IF_SVE_DN_2A}; + const static insFormat formatEncode2BG[2] = {IF_SVE_DO_2A, IF_SVE_DP_2A}; + const static insFormat formatEncode2BH[2] = {IF_SVE_DW_2A, IF_SVE_DW_2B}; + const static insFormat formatEncode2BI[2] = {IF_SVE_FN_3A, IF_SVE_FN_3B}; + const static insFormat formatEncode2BJ[2] = {IF_SVE_GQ_3A, IF_SVE_HG_2A}; + const static insFormat formatEncode2BK[2] = {IF_SVE_GU_3C, IF_SVE_HU_4B}; + const static insFormat formatEncode2BL[2] = {IF_SVE_GZ_3A, IF_SVE_HB_3A}; + const static insFormat formatEncode2BM[2] = {IF_SVE_HK_3B, IF_SVE_HL_3B}; + const static insFormat formatEncode2BN[2] = {IF_SVE_IF_4A, IF_SVE_IF_4A_A}; + const static insFormat formatEncode2BO[2] = {IF_SVE_IO_3A, IF_SVE_IP_4A}; + const static insFormat formatEncode2BP[2] = {IF_SVE_IQ_3A, IF_SVE_IR_4A}; + const static insFormat formatEncode2BQ[2] = {IF_SVE_IS_3A, IF_SVE_IT_4A}; + const static insFormat formatEncode2BR[2] = {IF_SVE_JC_4A, IF_SVE_JO_3A}; + const static insFormat formatEncode2BS[2] = {IF_SVE_JE_3A, IF_SVE_JF_4A}; + + code_t code = BAD_CODE; + insFormat insFmt = emitInsFormat(ins); + bool encoding_found = false; + int index = -1; + + switch (insFmt) + { + case IF_SVE_13A: + for (index = 0; index < 13; index++) + { + if (fmt == formatEncode13A[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_11A: + for (index = 0; index < 11; index++) + { + if (fmt == formatEncode11A[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_9A: + for (index = 0; index < 9; index++) + { + if (fmt == formatEncode9A[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_9B: + for (index = 0; index < 9; index++) + { + if (fmt == formatEncode9B[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_9C: + for (index = 0; index < 9; index++) + { + if (fmt == formatEncode9C[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_9D: + for (index = 0; index < 9; index++) + { + if (fmt == formatEncode9D[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_9E: + for (index = 0; index < 9; index++) + { + if (fmt == formatEncode9E[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_9F: + for (index = 0; index < 9; index++) + { + if (fmt == formatEncode9F[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_8A: + for (index = 0; index < 8; index++) + { + if (fmt == formatEncode8A[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_8B: + for (index = 0; index < 8; index++) + { + if (fmt == formatEncode8B[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_8C: + for (index = 0; index < 8; index++) + { + if (fmt == formatEncode8C[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_7A: + for (index = 0; index < 7; index++) + { + if (fmt == formatEncode7A[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_6A: + for (index = 0; index < 6; index++) + { + if (fmt == formatEncode6A[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_6B: + for (index = 0; index < 6; index++) + { + if (fmt == formatEncode6B[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_6C: + for (index = 0; index < 6; index++) + { + if (fmt == formatEncode6C[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_6D: + for (index = 0; index < 6; index++) + { + if (fmt == formatEncode6D[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_6E: + for (index = 0; index < 6; index++) + { + if (fmt == formatEncode6E[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_6F: + for (index = 0; index < 6; index++) + { + if (fmt == formatEncode6F[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_6G: + for (index = 0; index < 6; index++) + { + if (fmt == formatEncode6G[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_5A: + for (index = 0; index < 5; index++) + { + if (fmt == formatEncode5A[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_5B: + for (index = 0; index < 5; index++) + { + if (fmt == formatEncode5B[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_5C: + for (index = 0; index < 5; index++) + { + if (fmt == formatEncode5C[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_5D: + for (index = 0; index < 5; index++) + { + if (fmt == formatEncode5D[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_5E: + for (index = 0; index < 5; index++) + { + if (fmt == formatEncode5E[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4A: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4A[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4B: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4B[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4C: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4C[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4D: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4D[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4E: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4E[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4F: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4F[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4G: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4G[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4H: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4H[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4I: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4I[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4J: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4J[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4K: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4K[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_4L: + for (index = 0; index < 4; index++) + { + if (fmt == formatEncode4L[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3A: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3A[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3B: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3B[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3C: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3C[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3D: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3D[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3E: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3E[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3F: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3F[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3G: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3G[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3H: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3H[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3I: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3I[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3J: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3J[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3K: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3K[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3L: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3L[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3M: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3M[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3N: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3N[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3O: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3O[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3P: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3P[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3Q: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3Q[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3R: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3R[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3S: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3S[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3T: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3T[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3U: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3U[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_3V: + for (index = 0; index < 3; index++) + { + if (fmt == formatEncode3V[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_2AA: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2AA[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_2AB: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2AB[index]) + { + encoding_found = true; + break; + } + } + break; + case IF_SVE_2AC: + for (index = 0; index < 2; index++) + { + if (fmt == formatEncode2AC[index]) { encoding_found = true; break; } } break; - - case IF_EN6B: - for (index = 0; index < 6; index++) + case IF_SVE_2AD: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode6B[index]) + if (fmt == formatEncode2AD[index]) { encoding_found = true; break; } } break; - - case IF_EN5A: - for (index = 0; index < 5; index++) + case IF_SVE_2AE: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode5A[index]) + if (fmt == formatEncode2AE[index]) { encoding_found = true; break; } } break; - - case IF_EN5B: - for (index = 0; index < 5; index++) + case IF_SVE_2AF: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode5B[index]) + if (fmt == formatEncode2AF[index]) { encoding_found = true; break; } } break; - - case IF_EN5C: - for (index = 0; index < 5; index++) + case IF_SVE_2AG: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode5C[index]) + if (fmt == formatEncode2AG[index]) { encoding_found = true; break; } } break; - - case IF_EN4A: - for (index = 0; index < 4; index++) + case IF_SVE_2AH: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4A[index]) + if (fmt == formatEncode2AH[index]) { encoding_found = true; break; } } break; - - case IF_EN4B: - for (index = 0; index < 4; index++) + case IF_SVE_2AI: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4B[index]) + if (fmt == formatEncode2AI[index]) { encoding_found = true; break; } } break; - - case IF_EN4C: - for (index = 0; index < 4; index++) + case IF_SVE_2AJ: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4C[index]) + if (fmt == formatEncode2AJ[index]) { encoding_found = true; break; } } break; - - case IF_EN4D: - for (index = 0; index < 4; index++) + case IF_SVE_2AK: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4D[index]) + if (fmt == formatEncode2AK[index]) { encoding_found = true; break; } } break; - - case IF_EN4E: - for (index = 0; index < 4; index++) + case IF_SVE_2AL: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4E[index]) + if (fmt == formatEncode2AL[index]) { encoding_found = true; break; } } break; - - case IF_EN4F: - for (index = 0; index < 4; index++) + case IF_SVE_2AM: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4F[index]) + if (fmt == formatEncode2AM[index]) { encoding_found = true; break; } } break; - - case IF_EN4G: - for (index = 0; index < 4; index++) + case IF_SVE_2AN: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4G[index]) + if (fmt == formatEncode2AN[index]) { encoding_found = true; break; } } break; - - case IF_EN4H: - for (index = 0; index < 4; index++) + case IF_SVE_2AO: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4H[index]) + if (fmt == formatEncode2AO[index]) { encoding_found = true; break; } } break; - - case IF_EN4I: - for (index = 0; index < 4; index++) + case IF_SVE_2AP: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4I[index]) + if (fmt == formatEncode2AP[index]) { encoding_found = true; break; } } break; - - case IF_EN4J: - for (index = 0; index < 4; index++) + case IF_SVE_2AQ: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4J[index]) + if (fmt == formatEncode2AQ[index]) { encoding_found = true; break; } } break; - - case IF_EN4K: - for (index = 0; index < 4; index++) + case IF_SVE_2AR: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode4K[index]) + if (fmt == formatEncode2AR[index]) { encoding_found = true; break; } } break; - - case IF_EN3A: - for (index = 0; index < 3; index++) + case IF_SVE_2AS: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode3A[index]) + if (fmt == formatEncode2AS[index]) { encoding_found = true; break; } } break; - - case IF_EN3B: - for (index = 0; index < 3; index++) + case IF_SVE_2AT: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode3B[index]) + if (fmt == formatEncode2AT[index]) { encoding_found = true; break; } } break; - - case IF_EN3C: - for (index = 0; index < 3; index++) + case IF_SVE_2AU: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode3C[index]) + if (fmt == formatEncode2AU[index]) { encoding_found = true; break; } } break; - - case IF_EN3D: - for (index = 0; index < 3; index++) + case IF_SVE_2AV: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode3D[index]) + if (fmt == formatEncode2AV[index]) { encoding_found = true; break; } } break; - - case IF_EN3E: - for (index = 0; index < 3; index++) + case IF_SVE_2AW: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode3E[index]) + if (fmt == formatEncode2AW[index]) { encoding_found = true; break; } } break; - - case IF_EN3F: - for (index = 0; index < 3; index++) + case IF_SVE_2AX: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode3F[index]) + if (fmt == formatEncode2AX[index]) { encoding_found = true; break; } } break; - - case IF_EN3G: - for (index = 0; index < 3; index++) + case IF_SVE_2AY: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode3G[index]) + if (fmt == formatEncode2AY[index]) { encoding_found = true; break; } } break; - - case IF_EN3H: - for (index = 0; index < 3; index++) + case IF_SVE_2AZ: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode3H[index]) + if (fmt == formatEncode2AZ[index]) { encoding_found = true; break; } } break; - - case IF_EN3I: - for (index = 0; index < 3; index++) + case IF_SVE_2BA: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode3I[index]) + if (fmt == formatEncode2BA[index]) { encoding_found = true; break; } } break; - - case IF_EN3J: - for (index = 0; index < 3; index++) + case IF_SVE_2BB: + for (index = 0; index < 2; index++) { - if (fmt == formatEncode3J[index]) + if (fmt == formatEncode2BB[index]) { encoding_found = true; break; } } break; - - case IF_EN2A: + case IF_SVE_2BC: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2A[index]) + if (fmt == formatEncode2BC[index]) { encoding_found = true; break; } } break; - - case IF_EN2B: + case IF_SVE_2BD: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2B[index]) + if (fmt == formatEncode2BD[index]) { encoding_found = true; break; } } break; - - case IF_EN2C: + case IF_SVE_2BE: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2C[index]) + if (fmt == formatEncode2BE[index]) { encoding_found = true; break; } } break; - - case IF_EN2D: + case IF_SVE_2BF: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2D[index]) + if (fmt == formatEncode2BF[index]) { encoding_found = true; break; } } break; - - case IF_EN2E: + case IF_SVE_2BG: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2E[index]) + if (fmt == formatEncode2BG[index]) { encoding_found = true; break; } } break; - - case IF_EN2F: + case IF_SVE_2BH: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2F[index]) + if (fmt == formatEncode2BH[index]) { encoding_found = true; break; } } break; - - case IF_EN2G: + case IF_SVE_2BI: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2G[index]) + if (fmt == formatEncode2BI[index]) { encoding_found = true; break; } } break; - - case IF_EN2H: + case IF_SVE_2BJ: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2H[index]) + if (fmt == formatEncode2BJ[index]) { encoding_found = true; break; } } break; - - case IF_EN2I: + case IF_SVE_2BK: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2I[index]) + if (fmt == formatEncode2BK[index]) { encoding_found = true; break; } } break; - - case IF_EN2J: + case IF_SVE_2BL: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2J[index]) + if (fmt == formatEncode2BL[index]) { encoding_found = true; break; } } break; - - case IF_EN2K: + case IF_SVE_2BM: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2K[index]) + if (fmt == formatEncode2BM[index]) { encoding_found = true; break; } } break; - - case IF_EN2L: + case IF_SVE_2BN: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2L[index]) + if (fmt == formatEncode2BN[index]) { encoding_found = true; break; } } break; - - case IF_EN2M: + case IF_SVE_2BO: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2M[index]) + if (fmt == formatEncode2BO[index]) { encoding_found = true; break; } } break; - - case IF_EN2N: + case IF_SVE_2BP: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2N[index]) + if (fmt == formatEncode2BP[index]) { encoding_found = true; break; } } break; - - case IF_EN2O: + case IF_SVE_2BQ: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2O[index]) + if (fmt == formatEncode2BQ[index]) { encoding_found = true; break; } } break; - - case IF_EN2P: + case IF_SVE_2BR: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2P[index]) + if (fmt == formatEncode2BR[index]) { encoding_found = true; break; } } break; - - case IF_EN2Q: + case IF_SVE_2BS: for (index = 0; index < 2; index++) { - if (fmt == formatEncode2Q[index]) + if (fmt == formatEncode2BS[index]) { encoding_found = true; break; } } break; - default: if (fmt == insFmt) { @@ -2287,6 +3795,22 @@ emitter::code_t emitter::emitInsCode(instruction ins, insFormat fmt) assert(ins < ArrLen(insCodes9)); code = insCodes9[ins]; break; + case 9: + assert(ins < ArrLen(insCodes10)); + code = insCodes10[ins]; + break; + case 10: + assert(ins < ArrLen(insCodes11)); + code = insCodes11[ins]; + break; + case 11: + assert(ins < ArrLen(insCodes12)); + code = insCodes12[ins]; + break; + case 12: + assert(ins < ArrLen(insCodes13)); + code = insCodes13[ins]; + break; } assert((code != BAD_CODE)); @@ -9095,6 +10619,47 @@ void emitter::emitIns_Call(EmitCallType callType, return ureg << 10; } +/***************************************************************************** + * + * Returns an encoding for the specified register used in the 'Vd' position + */ + +/*static*/ emitter::code_t emitter::insEncodeReg_Pd(regNumber reg) +{ + // TODO-SVE: Fix once we add predicate registers + assert(emitter::isPredicateRegister(reg)); + emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0; + assert((ureg >= 0) && (ureg <= 15)); + return ureg; +} + +/***************************************************************************** + * + * Returns an encoding for the specified register used in the 'Vn' position + */ + +/*static*/ emitter::code_t emitter::insEncodeReg_Pn(regNumber reg) +{ + // TODO-SVE: Fix once we add predicate registers + assert(emitter::isPredicateRegister(reg)); + emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0; + assert((ureg >= 0) && (ureg <= 15)); + return ureg << 5; +} + +/***************************************************************************** + * + * Returns an encoding for the specified register used in the 'Vm' position + */ + +/*static*/ emitter::code_t emitter::insEncodeReg_Pm(regNumber reg) +{ + // TODO-SVE: Fix once we add predicate registers + assert(emitter::isPredicateRegister(reg)); + emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0; + assert((ureg >= 0) && (ureg <= 15)); + return ureg << 16; +} /***************************************************************************** * * Returns an encoding for the specified condition code. @@ -11835,6 +13400,34 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp) dst += emitOutput_Instr(dst, code); break; + case IF_SVE_BR_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments + code = emitInsCodeSve(ins, fmt); + elemsize = id->idOpSize(); + code |= insEncodeReg_Vd(id->idReg1()); // ddddd + code |= insEncodeReg_Vn(id->idReg2()); // nnnnn + code |= insEncodeReg_Vm(id->idReg3()); // mmmmm + code |= insEncodeElemsize(elemsize); // xx + dst += emitOutput_Instr(dst, code); + break; + + case IF_SVE_BR_3B: // ...........mmmmm ......nnnnnddddd -- SVE permute vector segments + code = emitInsCodeSve(ins, fmt); + code |= insEncodeReg_Vd(id->idReg1()); // ddddd + code |= insEncodeReg_Vn(id->idReg2()); // nnnnn + code |= insEncodeReg_Vm(id->idReg3()); // mmmmm + dst += emitOutput_Instr(dst, code); + break; + + case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements + code = emitInsCodeSve(ins, fmt); + elemsize = id->idOpSize(); + code |= insEncodeReg_Pd(id->idReg1()); // DDDD + code |= insEncodeReg_Pn(id->idReg2()); // NNNN + code |= insEncodeReg_Pm(id->idReg3()); // MMMM + code |= insEncodeElemsize(elemsize); // xx + dst += emitOutput_Instr(dst, code); + break; + default: assert(!"Unexpected format"); break; @@ -12373,6 +13966,20 @@ void emitter::emitDispVectorElemList( } } +//------------------------------------------------------------------------ +// emitDispPredicateReg: Display a predicate register name with with an arrangement suffix +// +void emitter::emitDispPredicateReg(regNumber reg, insOpts opt, bool addComma) +{ + // TODO-SVE: Fix once we add predicate registers + assert(isPredicateRegister(reg)); + printf(emitVectorRegName(reg)); + emitDispArrangement(opt); + + if (addComma) + emitDispComma(); +} + //------------------------------------------------------------------------ // emitDispArrangement: Display a SIMD vector arrangement suffix // @@ -13968,6 +15575,24 @@ void emitter::emitDispInsHelp( } break; + case IF_SVE_BR_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments + emitDispVectorReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispVectorReg(id->idReg2(), id->idInsOpt(), true); // nnnnn + emitDispVectorReg(id->idReg3(), id->idInsOpt(), true); // mmmmm + break; + + case IF_SVE_BR_3B: // ...........mmmmm ......nnnnnddddd -- SVE permute vector segments + emitDispVectorReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispVectorReg(id->idReg2(), id->idInsOpt(), true); // nnnnn + emitDispVectorReg(id->idReg3(), id->idInsOpt(), true); // mmmmm + break; + + case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements + emitDispPredicateReg(id->idReg1(), id->idInsOpt(), true); // DDDD + emitDispPredicateReg(id->idReg2(), id->idInsOpt(), true); // NNNN + emitDispPredicateReg(id->idReg3(), id->idInsOpt(), true); // MMMM + break; + default: printf("unexpected format %s", emitIfName(id->idInsFmt())); assert(!"unexpectedFormat"); @@ -16153,6 +17778,21 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins } break; + case IF_SVE_BR_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments + result.insThroughput = PERFSCORE_THROUGHPUT_2X; + result.insLatency = PERFSCORE_LATENCY_2C; + break; + + case IF_SVE_BR_3B: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments + result.insThroughput = PERFSCORE_THROUGHPUT_2X; + result.insLatency = PERFSCORE_LATENCY_2C; + break; + + case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements + result.insThroughput = PERFSCORE_THROUGHPUT_2X; + result.insLatency = PERFSCORE_LATENCY_2C; + break; + default: // all other instructions perfScoreUnhandledInstruction(id, &result); diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index a971f56f9d2884..0c6b15698cc097 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -20,6 +20,7 @@ static bool strictArmAsm; /************************************************************************/ const char* emitVectorRegName(regNumber reg); +const char* emitPredicateRegName(regNumber reg); void emitDispInsHelp( instrDesc* id, bool isNew, bool doffs, bool asmfm, unsigned offset, BYTE* pCode, size_t sz, insGroup* ig); @@ -42,6 +43,7 @@ void emitDispVectorReg(regNumber reg, insOpts opt, bool addComma); void emitDispVectorRegIndex(regNumber reg, emitAttr elemsize, ssize_t index, bool addComma); void emitDispVectorRegList(regNumber firstReg, unsigned listSize, insOpts opt, bool addComma); void emitDispVectorElemList(regNumber firstReg, unsigned listSize, emitAttr elemsize, unsigned index, bool addComma); +void emitDispPredicateReg(regNumber reg, insOpts opt, bool addComma); void emitDispArrangement(insOpts opt); void emitDispElemsize(emitAttr elemsize); void emitDispShiftedReg(regNumber reg, insOpts opt, ssize_t imm, emitAttr attr); @@ -99,6 +101,7 @@ emitAttr emitInsLoadStoreSize(instrDesc* id); emitter::insFormat emitInsFormat(instruction ins); emitter::code_t emitInsCode(instruction ins, insFormat fmt); +emitter::code_t emitInsCodeSve(instruction ins, insFormat fmt); // Generate code for a load or store operation and handle the case of contained GT_LEA op1 with [base + index<= REG_FP_FIRST && reg <= REG_FP_LAST); +} + inline static bool insOptsNone(insOpts opt) { return (opt == INS_OPTS_NONE); diff --git a/src/coreclr/jit/emitfmtsarm64sve.h b/src/coreclr/jit/emitfmtsarm64sve.h new file mode 100644 index 00000000000000..13137166b7d72a --- /dev/null +++ b/src/coreclr/jit/emitfmtsarm64sve.h @@ -0,0 +1,522 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. +////////////////////////////////////////////////////////////////////////////// + +// clang-format off +#if !defined(TARGET_ARM64) +#error Unexpected target type +#endif + +#ifndef IF_DEF +#error Must define IF_DEF macro before including this file +#endif + +////////////////////////////////////////////////////////////////////////////// +// +// enum insFormat instruction enum ID_OPS +// scheduling +// (unused) +////////////////////////////////////////////////////////////////////////////// +IF_DEF(SVE_13A, IS_NONE, NONE) // Instruction has 13 possible encoding types, type A +IF_DEF(SVE_11A, IS_NONE, NONE) // Instruction has 11 possible encoding types, type A +IF_DEF(SVE_9A, IS_NONE, NONE) // Instruction has 9 possible encoding types, type A +IF_DEF(SVE_9B, IS_NONE, NONE) // Instruction has 9 possible encoding types, type B +IF_DEF(SVE_9C, IS_NONE, NONE) // Instruction has 9 possible encoding types, type C +IF_DEF(SVE_9D, IS_NONE, NONE) // Instruction has 9 possible encoding types, type D +IF_DEF(SVE_9E, IS_NONE, NONE) // Instruction has 9 possible encoding types, type E +IF_DEF(SVE_9F, IS_NONE, NONE) // Instruction has 9 possible encoding types, type F +IF_DEF(SVE_8A, IS_NONE, NONE) // Instruction has 8 possible encoding types, type A +IF_DEF(SVE_8B, IS_NONE, NONE) // Instruction has 8 possible encoding types, type B +IF_DEF(SVE_8C, IS_NONE, NONE) // Instruction has 8 possible encoding types, type C +IF_DEF(SVE_7A, IS_NONE, NONE) // Instruction has 7 possible encoding types, type A +IF_DEF(SVE_6A, IS_NONE, NONE) // Instruction has 6 possible encoding types, type A +IF_DEF(SVE_6B, IS_NONE, NONE) // Instruction has 6 possible encoding types, type B +IF_DEF(SVE_6C, IS_NONE, NONE) // Instruction has 6 possible encoding types, type C +IF_DEF(SVE_6D, IS_NONE, NONE) // Instruction has 6 possible encoding types, type D +IF_DEF(SVE_6E, IS_NONE, NONE) // Instruction has 6 possible encoding types, type E +IF_DEF(SVE_6F, IS_NONE, NONE) // Instruction has 6 possible encoding types, type F +IF_DEF(SVE_6G, IS_NONE, NONE) // Instruction has 6 possible encoding types, type G +IF_DEF(SVE_5A, IS_NONE, NONE) // Instruction has 5 possible encoding types, type A +IF_DEF(SVE_5B, IS_NONE, NONE) // Instruction has 5 possible encoding types, type B +IF_DEF(SVE_5C, IS_NONE, NONE) // Instruction has 5 possible encoding types, type C +IF_DEF(SVE_5D, IS_NONE, NONE) // Instruction has 5 possible encoding types, type D +IF_DEF(SVE_5E, IS_NONE, NONE) // Instruction has 5 possible encoding types, type E +IF_DEF(SVE_4A, IS_NONE, NONE) // Instruction has 4 possible encoding types, type A +IF_DEF(SVE_4B, IS_NONE, NONE) // Instruction has 4 possible encoding types, type B +IF_DEF(SVE_4C, IS_NONE, NONE) // Instruction has 4 possible encoding types, type C +IF_DEF(SVE_4D, IS_NONE, NONE) // Instruction has 4 possible encoding types, type D +IF_DEF(SVE_4E, IS_NONE, NONE) // Instruction has 4 possible encoding types, type E +IF_DEF(SVE_4F, IS_NONE, NONE) // Instruction has 4 possible encoding types, type F +IF_DEF(SVE_4G, IS_NONE, NONE) // Instruction has 4 possible encoding types, type G +IF_DEF(SVE_4H, IS_NONE, NONE) // Instruction has 4 possible encoding types, type H +IF_DEF(SVE_4I, IS_NONE, NONE) // Instruction has 4 possible encoding types, type I +IF_DEF(SVE_4J, IS_NONE, NONE) // Instruction has 4 possible encoding types, type J +IF_DEF(SVE_4K, IS_NONE, NONE) // Instruction has 4 possible encoding types, type K +IF_DEF(SVE_4L, IS_NONE, NONE) // Instruction has 4 possible encoding types, type L +IF_DEF(SVE_3A, IS_NONE, NONE) // Instruction has 3 possible encoding types, type A +IF_DEF(SVE_3B, IS_NONE, NONE) // Instruction has 3 possible encoding types, type B +IF_DEF(SVE_3C, IS_NONE, NONE) // Instruction has 3 possible encoding types, type C +IF_DEF(SVE_3D, IS_NONE, NONE) // Instruction has 3 possible encoding types, type D +IF_DEF(SVE_3E, IS_NONE, NONE) // Instruction has 3 possible encoding types, type E +IF_DEF(SVE_3F, IS_NONE, NONE) // Instruction has 3 possible encoding types, type F +IF_DEF(SVE_3G, IS_NONE, NONE) // Instruction has 3 possible encoding types, type G +IF_DEF(SVE_3H, IS_NONE, NONE) // Instruction has 3 possible encoding types, type H +IF_DEF(SVE_3I, IS_NONE, NONE) // Instruction has 3 possible encoding types, type I +IF_DEF(SVE_3J, IS_NONE, NONE) // Instruction has 3 possible encoding types, type J +IF_DEF(SVE_3K, IS_NONE, NONE) // Instruction has 3 possible encoding types, type K +IF_DEF(SVE_3L, IS_NONE, NONE) // Instruction has 3 possible encoding types, type L +IF_DEF(SVE_3M, IS_NONE, NONE) // Instruction has 3 possible encoding types, type M +IF_DEF(SVE_3N, IS_NONE, NONE) // Instruction has 3 possible encoding types, type N +IF_DEF(SVE_3O, IS_NONE, NONE) // Instruction has 3 possible encoding types, type O +IF_DEF(SVE_3P, IS_NONE, NONE) // Instruction has 3 possible encoding types, type P +IF_DEF(SVE_3Q, IS_NONE, NONE) // Instruction has 3 possible encoding types, type Q +IF_DEF(SVE_3R, IS_NONE, NONE) // Instruction has 3 possible encoding types, type R +IF_DEF(SVE_3S, IS_NONE, NONE) // Instruction has 3 possible encoding types, type S +IF_DEF(SVE_3T, IS_NONE, NONE) // Instruction has 3 possible encoding types, type T +IF_DEF(SVE_3U, IS_NONE, NONE) // Instruction has 3 possible encoding types, type U +IF_DEF(SVE_3V, IS_NONE, NONE) // Instruction has 3 possible encoding types, type V +IF_DEF(SVE_2AA, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AA +IF_DEF(SVE_2AB, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AB +IF_DEF(SVE_2AC, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AC +IF_DEF(SVE_2AD, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AD +IF_DEF(SVE_2AE, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AE +IF_DEF(SVE_2AF, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AF +IF_DEF(SVE_2AG, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AG +IF_DEF(SVE_2AH, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AH +IF_DEF(SVE_2AI, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AI +IF_DEF(SVE_2AJ, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AJ +IF_DEF(SVE_2AK, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AK +IF_DEF(SVE_2AL, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AL +IF_DEF(SVE_2AM, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AM +IF_DEF(SVE_2AN, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AN +IF_DEF(SVE_2AO, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AO +IF_DEF(SVE_2AP, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AP +IF_DEF(SVE_2AQ, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AQ +IF_DEF(SVE_2AR, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AR +IF_DEF(SVE_2AS, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AS +IF_DEF(SVE_2AT, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AT +IF_DEF(SVE_2AU, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AU +IF_DEF(SVE_2AV, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AV +IF_DEF(SVE_2AW, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AW +IF_DEF(SVE_2AX, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AX +IF_DEF(SVE_2AY, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AY +IF_DEF(SVE_2AZ, IS_NONE, NONE) // Instruction has 2 possible encoding types, type AZ +IF_DEF(SVE_2BA, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BA +IF_DEF(SVE_2BB, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BB +IF_DEF(SVE_2BC, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BC +IF_DEF(SVE_2BD, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BD +IF_DEF(SVE_2BE, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BE +IF_DEF(SVE_2BF, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BF +IF_DEF(SVE_2BG, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BG +IF_DEF(SVE_2BH, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BH +IF_DEF(SVE_2BI, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BI +IF_DEF(SVE_2BJ, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BJ +IF_DEF(SVE_2BK, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BK +IF_DEF(SVE_2BL, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BL +IF_DEF(SVE_2BM, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BM +IF_DEF(SVE_2BN, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BN +IF_DEF(SVE_2BO, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BO +IF_DEF(SVE_2BP, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BP +IF_DEF(SVE_2BQ, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BQ +IF_DEF(SVE_2BR, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BR +IF_DEF(SVE_2BS, IS_NONE, NONE) // Instruction has 2 possible encoding types, type BS + +/***************************************************************************** +* SVE_WW_XY +* WW -- code +* X -- register count +* Y -- unique id +* +* ggg, DDD, TTT, MMM, NNN, VVV -- various predicate register specifications +* mmmmm -- Xm, Vm or Zm registers +* nnnnn -- Xn, Vn or Zn registers +* ttttt -- Xt, Vt or Zt registers +* ddddd -- Xd, Xdn, Vd, Vdn or Zd, Zdn, Zda registers +* i* -- immediates +* X -- vector size +* x -- element size +*****************************************************************************/ + +IF_DEF(SVE_AA_3A, IS_NONE, NONE) // SVE_AA_3A ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated) +IF_DEF(SVE_AB_3A, IS_NONE, NONE) // SVE_AB_3A ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated) +IF_DEF(SVE_AB_3B, IS_NONE, NONE) // SVE_AB_3B ................ ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated) +IF_DEF(SVE_AC_3A, IS_NONE, NONE) // SVE_AC_3A ........xx...... ...gggmmmmmddddd -- SVE integer divide vectors (predicated) +IF_DEF(SVE_AD_3A, IS_NONE, NONE) // SVE_AD_3A ........xx...... ...gggmmmmmddddd -- SVE integer min/max/difference (predicated) +IF_DEF(SVE_AE_3A, IS_NONE, NONE) // SVE_AE_3A ........xx...... ...gggmmmmmddddd -- SVE integer multiply vectors (predicated) +IF_DEF(SVE_AF_3A, IS_NONE, NONE) // SVE_AF_3A ........xx...... ...gggnnnnnddddd -- SVE bitwise logical reduction (predicated) +IF_DEF(SVE_AG_3A, IS_NONE, NONE) // SVE_AG_3A ........xx...... ...gggnnnnnddddd -- SVE bitwise logical reduction (quadwords) +IF_DEF(SVE_AH_3A, IS_NONE, NONE) // SVE_AH_3A ........xx.....M ...gggnnnnnddddd -- SVE constructive prefix (predicated) +IF_DEF(SVE_AI_3A, IS_NONE, NONE) // SVE_AI_3A ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (predicated) +IF_DEF(SVE_AJ_3A, IS_NONE, NONE) // SVE_AJ_3A ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (quadwords) +IF_DEF(SVE_AK_3A, IS_NONE, NONE) // SVE_AK_3A ........xx...... ...gggnnnnnddddd -- SVE integer min/max reduction (predicated) +IF_DEF(SVE_AL_3A, IS_NONE, NONE) // SVE_AL_3A ........xx...... ...gggnnnnnddddd -- SVE integer min/max reduction (quadwords) +IF_DEF(SVE_AM_2A, IS_NONE, NONE) // SVE_AM_2A ........xx...... ...gggxxiiiddddd -- SVE bitwise shift by immediate (predicated) +IF_DEF(SVE_AN_3A, IS_NONE, NONE) // SVE_AN_3A ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by vector (predicated) +IF_DEF(SVE_AO_3A, IS_NONE, NONE) // SVE_AO_3A ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated) +IF_DEF(SVE_AP_3A, IS_NONE, NONE) // SVE_AP_3A ........xx...... ...gggnnnnnddddd -- SVE bitwise unary operations (predicated) +IF_DEF(SVE_AQ_3A, IS_NONE, NONE) // SVE_AQ_3A ........xx...... ...gggnnnnnddddd -- SVE integer unary operations (predicated) +IF_DEF(SVE_AR_4A, IS_NONE, NONE) // SVE_AR_4A ........xx.mmmmm ...gggnnnnnddddd -- SVE integer multiply-accumulate writing addend (predicated) +IF_DEF(SVE_AS_4A, IS_NONE, NONE) // SVE_AS_4A ........xx.mmmmm ...gggaaaaaddddd -- SVE integer multiply-add writing multiplicand (predicated) +IF_DEF(SVE_AT_3A, IS_NONE, NONE) // SVE_AT_3A ........xx.mmmmm ......nnnnnddddd -- SVE integer add/subtract vectors (unpredicated) +IF_DEF(SVE_AT_3B, IS_NONE, NONE) // SVE_AT_3B ...........mmmmm ......nnnnnddddd -- SVE integer add/subtract vectors (unpredicated) +IF_DEF(SVE_AU_3A, IS_NONE, NONE) // SVE_AU_3A ...........mmmmm ......nnnnnddddd -- SVE bitwise logical operations (unpredicated) +IF_DEF(SVE_AV_3A, IS_NONE, NONE) // SVE_AV_3A ...........mmmmm ......kkkkkddddd -- SVE2 bitwise ternary operations +IF_DEF(SVE_AW_2A, IS_NONE, NONE) // SVE_AW_2A ........xx.xxiii ......mmmmmddddd -- sve_int_rotate_imm +IF_DEF(SVE_AX_1A, IS_NONE, NONE) // SVE_AX_1A ........xx.iiiii ......iiiiiddddd -- SVE index generation (immediate start, immediate increment) +IF_DEF(SVE_AY_2A, IS_NONE, NONE) // SVE_AY_2A ........xx.mmmmm ......iiiiiddddd -- SVE index generation (immediate start, register increment) +IF_DEF(SVE_AZ_2A, IS_NONE, NONE) // SVE_AZ_2A ........xx.iiiii ......nnnnnddddd -- SVE index generation (register start, immediate increment) +IF_DEF(SVE_BA_3A, IS_NONE, NONE) // SVE_BA_3A ........xx.mmmmm ......nnnnnddddd -- SVE index generation (register start, register increment) +IF_DEF(SVE_BB_2A, IS_NONE, NONE) // SVE_BB_2A ...........nnnnn .....iiiiiiddddd -- SVE stack frame adjustment +IF_DEF(SVE_BC_1A, IS_NONE, NONE) // SVE_BC_1A ................ .....iiiiiiddddd -- SVE stack frame size +IF_DEF(SVE_BD_3A, IS_NONE, NONE) // SVE_BD_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply vectors (unpredicated) +IF_DEF(SVE_BD_3B, IS_NONE, NONE) // SVE_BD_3B ...........mmmmm ......nnnnnddddd -- SVE2 integer multiply vectors (unpredicated) +IF_DEF(SVE_BE_3A, IS_NONE, NONE) // SVE_BE_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 signed saturating doubling multiply high (unpredicated) +IF_DEF(SVE_BF_2A, IS_NONE, NONE) // SVE_BF_2A ........xx.xxiii ......nnnnnddddd -- SVE bitwise shift by immediate (unpredicated) +IF_DEF(SVE_BG_3A, IS_NONE, NONE) // SVE_BG_3A ........xx.mmmmm ......nnnnnddddd -- SVE bitwise shift by wide elements (unpredicated) +IF_DEF(SVE_BH_3A, IS_NONE, NONE) // SVE_BH_3A .........x.mmmmm ....hhnnnnnddddd -- SVE address generation +IF_DEF(SVE_BH_3B, IS_NONE, NONE) // SVE_BH_3B ...........mmmmm ....hhnnnnnddddd -- SVE address generation +IF_DEF(SVE_BH_3B_A, IS_NONE, NONE) // SVE_BH_3B_A ...........mmmmm ....hhnnnnnddddd -- +IF_DEF(SVE_BI_2A, IS_NONE, NONE) // SVE_BI_2A ................ ......nnnnnddddd -- SVE constructive prefix (unpredicated) +IF_DEF(SVE_BJ_2A, IS_NONE, NONE) // SVE_BJ_2A ........xx...... ......nnnnnddddd -- SVE floating-point exponential accelerator +IF_DEF(SVE_BK_3A, IS_NONE, NONE) // SVE_BK_3A ........xx.mmmmm ......nnnnnddddd -- SVE floating-point trig select coefficient +IF_DEF(SVE_BL_1A, IS_NONE, NONE) // SVE_BL_1A ............iiii ......pppppddddd -- SVE element count +IF_DEF(SVE_BM_1A, IS_NONE, NONE) // SVE_BM_1A ............iiii ......pppppddddd -- SVE inc/dec register by element count +IF_DEF(SVE_BN_1A, IS_NONE, NONE) // SVE_BN_1A ............iiii ......pppppddddd -- SVE inc/dec vector by element count +IF_DEF(SVE_BO_1A, IS_NONE, NONE) // SVE_BO_1A ...........Xiiii ......pppppddddd -- SVE saturating inc/dec register by element count +IF_DEF(SVE_BO_1A_A, IS_NONE, NONE) // SVE_BO_1A_A ...........Xiiii ......pppppddddd -- +IF_DEF(SVE_BP_1A, IS_NONE, NONE) // SVE_BP_1A ............iiii ......pppppddddd -- SVE saturating inc/dec vector by element count +IF_DEF(SVE_BQ_2A, IS_NONE, NONE) // SVE_BQ_2A ...........iiiii ...iiinnnnnddddd -- SVE extract vector (immediate offset, destructive) +IF_DEF(SVE_BQ_2B, IS_NONE, NONE) // SVE_BQ_2B ...........iiiii ...iiimmmmmddddd -- SVE extract vector (immediate offset, destructive) +IF_DEF(SVE_BR_3A, IS_NONE, NONE) // SVE_BR_3A ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments +IF_DEF(SVE_BR_3B, IS_NONE, NONE) // SVE_BR_3B ...........mmmmm ......nnnnnddddd -- SVE permute vector segments +IF_DEF(SVE_BS_1A, IS_NONE, NONE) // SVE_BS_1A ..............ii iiiiiiiiiiiddddd -- SVE bitwise logical with immediate (unpredicated) +IF_DEF(SVE_BT_1A, IS_NONE, NONE) // SVE_BT_1A ..............ii iiiiiiiiiiiddddd -- SVE broadcast bitmask immediate +IF_DEF(SVE_BU_2A, IS_NONE, NONE) // SVE_BU_2A ........xx..gggg ...iiiiiiiiddddd -- SVE copy floating-point immediate (predicated) +IF_DEF(SVE_BV_2A, IS_NONE, NONE) // SVE_BV_2A ........xx..gggg ..hiiiiiiiiddddd -- SVE copy integer immediate (predicated) +IF_DEF(SVE_BV_2A_A, IS_NONE, NONE) // SVE_BV_2A_A ........xx..gggg ..hiiiiiiiiddddd -- +IF_DEF(SVE_BV_2B, IS_NONE, NONE) // SVE_BV_2B ........xx..gggg ...........ddddd -- SVE copy integer immediate (predicated) +IF_DEF(SVE_BV_2A_J, IS_NONE, NONE) // SVE_BV_2A_J ........xx..gggg ..hiiiiiiiiddddd -- +IF_DEF(SVE_BW_2A, IS_NONE, NONE) // SVE_BW_2A ........ii.xxxxx ......nnnnnddddd -- SVE broadcast indexed element +IF_DEF(SVE_BX_2A, IS_NONE, NONE) // SVE_BX_2A ...........ixxxx ......nnnnnddddd -- sve_int_perm_dupq_i +IF_DEF(SVE_BY_2A, IS_NONE, NONE) // SVE_BY_2A ............iiii ......mmmmmddddd -- sve_int_perm_extq +IF_DEF(SVE_BZ_3A, IS_NONE, NONE) // SVE_BZ_3A ........xx.mmmmm ......nnnnnddddd -- SVE table lookup (three sources) +IF_DEF(SVE_BZ_3A_A, IS_NONE, NONE) // SVE_BZ_3A_A ........xx.mmmmm ......nnnnnddddd -- +IF_DEF(SVE_CA_3A, IS_NONE, NONE) // SVE_CA_3A ........xx.mmmmm ......nnnnnddddd -- sve_int_perm_tbxquads +IF_DEF(SVE_CB_2A, IS_NONE, NONE) // SVE_CB_2A ........xx...... ......nnnnnddddd -- SVE broadcast general register +IF_DEF(SVE_CC_2A, IS_NONE, NONE) // SVE_CC_2A ........xx...... ......mmmmmddddd -- SVE insert SIMD&FP scalar register +IF_DEF(SVE_CD_2A, IS_NONE, NONE) // SVE_CD_2A ........xx...... ......mmmmmddddd -- SVE insert general register +IF_DEF(SVE_CE_2A, IS_NONE, NONE) // SVE_CE_2A ................ ......nnnnn.DDDD -- SVE move predicate from vector +IF_DEF(SVE_CE_2B, IS_NONE, NONE) // SVE_CE_2B .........i...ii. ......nnnnn.DDDD -- SVE move predicate from vector +IF_DEF(SVE_CE_2C, IS_NONE, NONE) // SVE_CE_2C ..............i. ......nnnnn.DDDD -- SVE move predicate from vector +IF_DEF(SVE_CE_2D, IS_NONE, NONE) // SVE_CE_2D .............ii. ......nnnnn.DDDD -- SVE move predicate from vector +IF_DEF(SVE_CF_2A, IS_NONE, NONE) // SVE_CF_2A ................ .......NNNNddddd -- SVE move predicate into vector +IF_DEF(SVE_CF_2B, IS_NONE, NONE) // SVE_CF_2B .........i...ii. .......NNNNddddd -- SVE move predicate into vector +IF_DEF(SVE_CF_2C, IS_NONE, NONE) // SVE_CF_2C ..............i. .......NNNNddddd -- SVE move predicate into vector +IF_DEF(SVE_CF_2D, IS_NONE, NONE) // SVE_CF_2D .............ii. .......NNNNddddd -- SVE move predicate into vector +IF_DEF(SVE_CG_2A, IS_NONE, NONE) // SVE_CG_2A ........xx...... ......nnnnnddddd -- SVE reverse vector elements +IF_DEF(SVE_CH_2A, IS_NONE, NONE) // SVE_CH_2A ........xx...... ......nnnnnddddd -- SVE unpack vector elements +IF_DEF(SVE_CI_3A, IS_NONE, NONE) // SVE_CI_3A ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements +IF_DEF(SVE_CJ_2A, IS_NONE, NONE) // SVE_CJ_2A ........xx...... .......NNNN.DDDD -- SVE reverse predicate elements +IF_DEF(SVE_CK_2A, IS_NONE, NONE) // SVE_CK_2A ................ .......NNNN.DDDD -- SVE unpack predicate elements +IF_DEF(SVE_CL_3A, IS_NONE, NONE) // SVE_CL_3A ........xx...... ...gggnnnnnddddd -- SVE compress active elements +IF_DEF(SVE_CM_3A, IS_NONE, NONE) // SVE_CM_3A ........xx...... ...gggmmmmmddddd -- SVE conditionally broadcast element to vector +IF_DEF(SVE_CN_3A, IS_NONE, NONE) // SVE_CN_3A ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to SIMD&FP scalar +IF_DEF(SVE_CO_3A, IS_NONE, NONE) // SVE_CO_3A ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register +IF_DEF(SVE_CP_3A, IS_NONE, NONE) // SVE_CP_3A ........xx...... ...gggnnnnnddddd -- SVE copy SIMD&FP scalar register to vector (predicated) +IF_DEF(SVE_CQ_3A, IS_NONE, NONE) // SVE_CQ_3A ........xx...... ...gggnnnnnddddd -- SVE copy general register to vector (predicated) +IF_DEF(SVE_CR_3A, IS_NONE, NONE) // SVE_CR_3A ........xx...... ...gggnnnnnddddd -- SVE extract element to SIMD&FP scalar register +IF_DEF(SVE_CS_3A, IS_NONE, NONE) // SVE_CS_3A ........xx...... ...gggnnnnnddddd -- SVE extract element to general register +IF_DEF(SVE_CT_3A, IS_NONE, NONE) // SVE_CT_3A ................ ...gggnnnnnddddd -- SVE reverse doublewords +IF_DEF(SVE_CU_3A, IS_NONE, NONE) // SVE_CU_3A ........xx...... ...gggnnnnnddddd -- SVE reverse within elements +IF_DEF(SVE_CV_3A, IS_NONE, NONE) // SVE_CV_3A ........xx...... ...VVVnnnnnddddd -- SVE vector splice (destructive) +IF_DEF(SVE_CV_3B, IS_NONE, NONE) // SVE_CV_3B ........xx...... ...VVVmmmmmddddd -- SVE vector splice (destructive) +IF_DEF(SVE_CW_4A, IS_NONE, NONE) // SVE_CW_4A ........xx.mmmmm ..VVVVnnnnnddddd -- SVE select vector elements (predicated) +IF_DEF(SVE_CX_4A, IS_NONE, NONE) // SVE_CX_4A ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors +IF_DEF(SVE_CX_4A_A, IS_NONE, NONE) // SVE_CX_4A_A ........xx.mmmmm ...gggnnnnn.DDDD -- +IF_DEF(SVE_CY_3A, IS_NONE, NONE) // SVE_CY_3A ........xx.iiiii ...gggnnnnn.DDDD -- SVE integer compare with unsigned immediate +IF_DEF(SVE_CY_3B, IS_NONE, NONE) // SVE_CY_3B ........xx.iiiii ii.gggnnnnn.DDDD -- SVE integer compare with unsigned immediate +IF_DEF(SVE_CZ_4A, IS_NONE, NONE) // SVE_CZ_4A ............MMMM ..gggg.NNNN.DDDD -- SVE predicate logical operations +IF_DEF(SVE_CZ_4A_K, IS_NONE, NONE) // SVE_CZ_4A_K ............MMMM ..gggg.NNNN.DDDD -- +IF_DEF(SVE_CZ_4A_L, IS_NONE, NONE) // SVE_CZ_4A_L ............MMMM ..gggg.NNNN.DDDD -- +IF_DEF(SVE_CZ_4A_A, IS_NONE, NONE) // SVE_CZ_4A_A ............MMMM ..gggg.NNNN.DDDD -- +IF_DEF(SVE_DA_4A, IS_NONE, NONE) // SVE_DA_4A ............MMMM ..gggg.NNNN.DDDD -- SVE propagate break from previous partition +IF_DEF(SVE_DB_3A, IS_NONE, NONE) // SVE_DB_3A ................ ..gggg.NNNNMDDDD -- SVE partition break condition +IF_DEF(SVE_DB_3B, IS_NONE, NONE) // SVE_DB_3B ................ ..gggg.NNNN.DDDD -- SVE partition break condition +IF_DEF(SVE_DC_3A, IS_NONE, NONE) // SVE_DC_3A ................ ..gggg.NNNN.MMMM -- SVE propagate break to next partition +IF_DEF(SVE_DD_2A, IS_NONE, NONE) // SVE_DD_2A ................ .......gggg.DDDD -- SVE predicate first active +IF_DEF(SVE_DE_1A, IS_NONE, NONE) // SVE_DE_1A ........xx...... ......ppppp.DDDD -- SVE predicate initialize +IF_DEF(SVE_DF_2A, IS_NONE, NONE) // SVE_DF_2A ........xx...... .......VVVV.DDDD -- SVE predicate next active +IF_DEF(SVE_DG_2A, IS_NONE, NONE) // SVE_DG_2A ................ .......gggg.DDDD -- SVE predicate read from FFR (predicated) +IF_DEF(SVE_DH_1A, IS_NONE, NONE) // SVE_DH_1A ................ ............DDDD -- SVE predicate read from FFR (unpredicated) +IF_DEF(SVE_DI_2A, IS_NONE, NONE) // SVE_DI_2A ................ ..gggg.NNNN..... -- SVE predicate test +IF_DEF(SVE_DJ_1A, IS_NONE, NONE) // SVE_DJ_1A ................ ............DDDD -- SVE predicate zero +IF_DEF(SVE_DK_3A, IS_NONE, NONE) // SVE_DK_3A ........xx...... ..gggg.NNNNddddd -- SVE predicate count +IF_DEF(SVE_DL_2A, IS_NONE, NONE) // SVE_DL_2A ........xx...... .....l.NNNNddddd -- SVE predicate count (predicate-as-counter) +IF_DEF(SVE_DM_2A, IS_NONE, NONE) // SVE_DM_2A ........xx...... .......MMMMddddd -- SVE inc/dec register by predicate count +IF_DEF(SVE_DN_2A, IS_NONE, NONE) // SVE_DN_2A ........xx...... .......MMMMddddd -- SVE inc/dec vector by predicate count +IF_DEF(SVE_DO_2A, IS_NONE, NONE) // SVE_DO_2A ........xx...... .....X.MMMMddddd -- SVE saturating inc/dec register by predicate count +IF_DEF(SVE_DO_2A_A, IS_NONE, NONE) // SVE_DO_2A_A ........xx...... .....X.MMMMddddd -- +IF_DEF(SVE_DP_2A, IS_NONE, NONE) // SVE_DP_2A ........xx...... .......MMMMddddd -- SVE saturating inc/dec vector by predicate count +IF_DEF(SVE_DQ_0A, IS_NONE, NONE) // SVE_DQ_0A ................ ................ -- SVE FFR initialise +IF_DEF(SVE_DR_1A, IS_NONE, NONE) // SVE_DR_1A ................ .......NNNN..... -- SVE FFR write from predicate +IF_DEF(SVE_DS_2A, IS_NONE, NONE) // SVE_DS_2A .........x.mmmmm ......nnnnn..... -- SVE conditionally terminate scalars +IF_DEF(SVE_DT_3A, IS_NONE, NONE) // SVE_DT_3A ........xx.mmmmm ...X..nnnnn.DDDD -- SVE integer compare scalar count and limit +IF_DEF(SVE_DU_3A, IS_NONE, NONE) // SVE_DU_3A ........xx.mmmmm ......nnnnn.DDDD -- SVE pointer conflict compare +IF_DEF(SVE_DV_4A, IS_NONE, NONE) // SVE_DV_4A ........ix.xxxvv ..NNNN.MMMM.DDDD -- SVE broadcast predicate element +IF_DEF(SVE_DW_2A, IS_NONE, NONE) // SVE_DW_2A ........xx...... ......iiNNN.DDDD -- SVE extract mask predicate from predicate-as-counter +IF_DEF(SVE_DW_2B, IS_NONE, NONE) // SVE_DW_2B ........xx...... .......iNNN.DDDD -- SVE extract mask predicate from predicate-as-counter +IF_DEF(SVE_DX_3A, IS_NONE, NONE) // SVE_DX_3A ........xx.mmmmm ......nnnnn.DDD. -- SVE integer compare scalar count and limit (predicate pair) +IF_DEF(SVE_DY_3A, IS_NONE, NONE) // SVE_DY_3A ........xx.mmmmm ..l...nnnnn..DDD -- SVE integer compare scalar count and limit (predicate-as-counter) +IF_DEF(SVE_DZ_1A, IS_NONE, NONE) // SVE_DZ_1A ........xx...... .............DDD -- sve_int_pn_ptrue +IF_DEF(SVE_EA_1A, IS_NONE, NONE) // SVE_EA_1A ........xx...... ...iiiiiiiiddddd -- SVE broadcast floating-point immediate (unpredicated) +IF_DEF(SVE_EB_1A, IS_NONE, NONE) // SVE_EB_1A ........xx...... ..hiiiiiiiiddddd -- SVE broadcast integer immediate (unpredicated) +IF_DEF(SVE_EB_1B, IS_NONE, NONE) // SVE_EB_1B ........xx...... ...........ddddd -- SVE broadcast integer immediate (unpredicated) +IF_DEF(SVE_EC_1A, IS_NONE, NONE) // SVE_EC_1A ........xx...... ..hiiiiiiiiddddd -- SVE integer add/subtract immediate (unpredicated) +IF_DEF(SVE_ED_1A, IS_NONE, NONE) // SVE_ED_1A ........xx...... ...iiiiiiiiddddd -- SVE integer min/max immediate (unpredicated) +IF_DEF(SVE_EE_1A, IS_NONE, NONE) // SVE_EE_1A ........xx...... ...iiiiiiiiddddd -- SVE integer multiply immediate (unpredicated) +IF_DEF(SVE_EF_3A, IS_NONE, NONE) // SVE_EF_3A ...........mmmmm ......nnnnnddddd -- SVE two-way dot product +IF_DEF(SVE_EG_3A, IS_NONE, NONE) // SVE_EG_3A ...........iimmm ......nnnnnddddd -- SVE two-way dot product (indexed) +IF_DEF(SVE_EH_3A, IS_NONE, NONE) // SVE_EH_3A ........xx.mmmmm ......nnnnnddddd -- SVE integer dot product (unpredicated) +IF_DEF(SVE_EI_3A, IS_NONE, NONE) // SVE_EI_3A ...........mmmmm ......nnnnnddddd -- SVE mixed sign dot product +IF_DEF(SVE_EJ_3A, IS_NONE, NONE) // SVE_EJ_3A ........xx.mmmmm ....rrnnnnnddddd -- SVE2 complex integer dot product +IF_DEF(SVE_EK_3A, IS_NONE, NONE) // SVE_EK_3A ........xx.mmmmm ....rrnnnnnddddd -- SVE2 complex integer multiply-add +IF_DEF(SVE_EL_3A, IS_NONE, NONE) // SVE_EL_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply-add long +IF_DEF(SVE_EM_3A, IS_NONE, NONE) // SVE_EM_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add high +IF_DEF(SVE_EN_3A, IS_NONE, NONE) // SVE_EN_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add interleaved long +IF_DEF(SVE_EO_3A, IS_NONE, NONE) // SVE_EO_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add long +IF_DEF(SVE_EP_3A, IS_NONE, NONE) // SVE_EP_3A ........xx...... ...gggmmmmmddddd -- SVE2 integer halving add/subtract (predicated) +IF_DEF(SVE_EQ_3A, IS_NONE, NONE) // SVE_EQ_3A ........xx...... ...gggnnnnnddddd -- SVE2 integer pairwise add and accumulate long +IF_DEF(SVE_ER_3A, IS_NONE, NONE) // SVE_ER_3A ........xx...... ...gggmmmmmddddd -- SVE2 integer pairwise arithmetic +IF_DEF(SVE_ES_3A, IS_NONE, NONE) // SVE_ES_3A ........xx...... ...gggnnnnnddddd -- SVE2 integer unary operations (predicated) +IF_DEF(SVE_ET_3A, IS_NONE, NONE) // SVE_ET_3A ........xx...... ...gggmmmmmddddd -- SVE2 saturating add/subtract +IF_DEF(SVE_EU_3A, IS_NONE, NONE) // SVE_EU_3A ........xx...... ...gggmmmmmddddd -- SVE2 saturating/rounding bitwise shift left (predicated) +IF_DEF(SVE_EV_3A, IS_NONE, NONE) // SVE_EV_3A ........xx.mmmmm ......nnnnnddddd -- SVE integer clamp +IF_DEF(SVE_EW_3A, IS_NONE, NONE) // SVE_EW_3A ...........mmmmm ......nnnnnddddd -- SVE2 multiply-add (checked pointer) +IF_DEF(SVE_EW_3B, IS_NONE, NONE) // SVE_EW_3B ...........mmmmm ......aaaaaddddd -- SVE2 multiply-add (checked pointer) +IF_DEF(SVE_EX_3A, IS_NONE, NONE) // SVE_EX_3A ........xx.mmmmm ......nnnnnddddd -- SVE permute vector elements (quadwords) +IF_DEF(SVE_EY_3A, IS_NONE, NONE) // SVE_EY_3A ...........iimmm ......nnnnnddddd -- SVE integer dot product (indexed) +IF_DEF(SVE_EY_3B, IS_NONE, NONE) // SVE_EY_3B ...........immmm ......nnnnnddddd -- SVE integer dot product (indexed) +IF_DEF(SVE_EZ_3A, IS_NONE, NONE) // SVE_EZ_3A ...........iimmm ......nnnnnddddd -- SVE mixed sign dot product (indexed) +IF_DEF(SVE_FA_3A, IS_NONE, NONE) // SVE_FA_3A ...........iimmm ....rrnnnnnddddd -- SVE2 complex integer dot product (indexed) +IF_DEF(SVE_FA_3B, IS_NONE, NONE) // SVE_FA_3B ...........immmm ....rrnnnnnddddd -- SVE2 complex integer dot product (indexed) +IF_DEF(SVE_FB_3A, IS_NONE, NONE) // SVE_FB_3A ...........iimmm ....rrnnnnnddddd -- SVE2 complex integer multiply-add (indexed) +IF_DEF(SVE_FB_3B, IS_NONE, NONE) // SVE_FB_3B ...........immmm ....rrnnnnnddddd -- SVE2 complex integer multiply-add (indexed) +IF_DEF(SVE_FC_3A, IS_NONE, NONE) // SVE_FC_3A ...........iimmm ....rrnnnnnddddd -- SVE2 complex saturating multiply-add (indexed) +IF_DEF(SVE_FC_3B, IS_NONE, NONE) // SVE_FC_3B ...........immmm ....rrnnnnnddddd -- SVE2 complex saturating multiply-add (indexed) +IF_DEF(SVE_FD_3A, IS_NONE, NONE) // SVE_FD_3A .........i.iimmm ......nnnnnddddd -- SVE2 integer multiply (indexed) +IF_DEF(SVE_FD_3B, IS_NONE, NONE) // SVE_FD_3B ...........iimmm ......nnnnnddddd -- SVE2 integer multiply (indexed) +IF_DEF(SVE_FD_3C, IS_NONE, NONE) // SVE_FD_3C ...........immmm ......nnnnnddddd -- SVE2 integer multiply (indexed) +IF_DEF(SVE_FE_3A, IS_NONE, NONE) // SVE_FE_3A ...........iimmm ....i.nnnnnddddd -- SVE2 integer multiply long (indexed) +IF_DEF(SVE_FE_3B, IS_NONE, NONE) // SVE_FE_3B ...........immmm ....i.nnnnnddddd -- SVE2 integer multiply long (indexed) +IF_DEF(SVE_FF_3A, IS_NONE, NONE) // SVE_FF_3A .........i.iimmm ......nnnnnddddd -- SVE2 integer multiply-add (indexed) +IF_DEF(SVE_FF_3B, IS_NONE, NONE) // SVE_FF_3B ...........iimmm ......nnnnnddddd -- SVE2 integer multiply-add (indexed) +IF_DEF(SVE_FF_3C, IS_NONE, NONE) // SVE_FF_3C ...........immmm ......nnnnnddddd -- SVE2 integer multiply-add (indexed) +IF_DEF(SVE_FG_3A, IS_NONE, NONE) // SVE_FG_3A ...........iimmm ....i.nnnnnddddd -- SVE2 integer multiply-add long (indexed) +IF_DEF(SVE_FG_3B, IS_NONE, NONE) // SVE_FG_3B ...........immmm ....i.nnnnnddddd -- SVE2 integer multiply-add long (indexed) +IF_DEF(SVE_FH_3A, IS_NONE, NONE) // SVE_FH_3A ...........iimmm ....i.nnnnnddddd -- SVE2 saturating multiply (indexed) +IF_DEF(SVE_FH_3B, IS_NONE, NONE) // SVE_FH_3B ...........immmm ....i.nnnnnddddd -- SVE2 saturating multiply (indexed) +IF_DEF(SVE_FI_3A, IS_NONE, NONE) // SVE_FI_3A .........i.iimmm ......nnnnnddddd -- SVE2 saturating multiply high (indexed) +IF_DEF(SVE_FI_3B, IS_NONE, NONE) // SVE_FI_3B ...........iimmm ......nnnnnddddd -- SVE2 saturating multiply high (indexed) +IF_DEF(SVE_FI_3C, IS_NONE, NONE) // SVE_FI_3C ...........immmm ......nnnnnddddd -- SVE2 saturating multiply high (indexed) +IF_DEF(SVE_FJ_3A, IS_NONE, NONE) // SVE_FJ_3A ...........iimmm ....i.nnnnnddddd -- SVE2 saturating multiply-add (indexed) +IF_DEF(SVE_FJ_3B, IS_NONE, NONE) // SVE_FJ_3B ...........immmm ....i.nnnnnddddd -- SVE2 saturating multiply-add (indexed) +IF_DEF(SVE_FK_3A, IS_NONE, NONE) // SVE_FK_3A .........i.iimmm ......nnnnnddddd -- SVE2 saturating multiply-add high (indexed) +IF_DEF(SVE_FK_3B, IS_NONE, NONE) // SVE_FK_3B ...........iimmm ......nnnnnddddd -- SVE2 saturating multiply-add high (indexed) +IF_DEF(SVE_FK_3C, IS_NONE, NONE) // SVE_FK_3C ...........immmm ......nnnnnddddd -- SVE2 saturating multiply-add high (indexed) +IF_DEF(SVE_FL_3A, IS_NONE, NONE) // SVE_FL_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract long +IF_DEF(SVE_FM_3A, IS_NONE, NONE) // SVE_FM_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract wide +IF_DEF(SVE_FN_3A, IS_NONE, NONE) // SVE_FN_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply long +IF_DEF(SVE_FN_3B, IS_NONE, NONE) // SVE_FN_3B ...........mmmmm ......nnnnnddddd -- SVE2 integer multiply long +IF_DEF(SVE_FO_3A, IS_NONE, NONE) // SVE_FO_3A ...........mmmmm ......nnnnnddddd -- SVE integer matrix multiply accumulate +IF_DEF(SVE_FP_3A, IS_NONE, NONE) // SVE_FP_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 bitwise exclusive-or interleaved +IF_DEF(SVE_FQ_3A, IS_NONE, NONE) // SVE_FQ_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 bitwise permute +IF_DEF(SVE_FR_2A, IS_NONE, NONE) // SVE_FR_2A .........x.xxiii ......nnnnnddddd -- SVE2 bitwise shift left long +IF_DEF(SVE_FS_3A, IS_NONE, NONE) // SVE_FS_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract interleaved long +IF_DEF(SVE_FT_2A, IS_NONE, NONE) // SVE_FT_2A ........xx.xxiii ......nnnnnddddd -- SVE2 bitwise shift and insert +IF_DEF(SVE_FU_2A, IS_NONE, NONE) // SVE_FU_2A ........xx.xxiii ......nnnnnddddd -- SVE2 bitwise shift right and accumulate +IF_DEF(SVE_FV_2A, IS_NONE, NONE) // SVE_FV_2A ........xx...... .....rmmmmmddddd -- SVE2 complex integer add +IF_DEF(SVE_FW_3A, IS_NONE, NONE) // SVE_FW_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate +IF_DEF(SVE_FX_3A, IS_NONE, NONE) // SVE_FX_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate long +IF_DEF(SVE_FY_3A, IS_NONE, NONE) // SVE_FY_3A .........x.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract long with carry +IF_DEF(SVE_FZ_2A, IS_NONE, NONE) // SVE_FZ_2A ................ ......nnnn.ddddd -- SME2 multi-vec extract narrow +IF_DEF(SVE_GA_2A, IS_NONE, NONE) // SVE_GA_2A ............iiii ......nnnn.ddddd -- SME2 multi-vec shift narrow +IF_DEF(SVE_GB_2A, IS_NONE, NONE) // SVE_GB_2A .........x.xxiii ......nnnnnddddd -- SVE2 bitwise shift right narrow +IF_DEF(SVE_GC_3A, IS_NONE, NONE) // SVE_GC_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract narrow high part +IF_DEF(SVE_GD_2A, IS_NONE, NONE) // SVE_GD_2A .........x.xx... ......nnnnnddddd -- SVE2 saturating extract narrow +IF_DEF(SVE_GE_4A, IS_NONE, NONE) // SVE_GE_4A ........xx.mmmmm ...gggnnnnn.DDDD -- SVE2 character match +IF_DEF(SVE_GF_3A, IS_NONE, NONE) // SVE_GF_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 histogram generation (segment) +IF_DEF(SVE_GG_3A, IS_NONE, NONE) // SVE_GG_3A ........ii.mmmmm ......nnnnnddddd -- SVE2 lookup table with 2-bit indices and 16-bit element size +IF_DEF(SVE_GG_3B, IS_NONE, NONE) // SVE_GG_3B ........ii.mmmmm ...i..nnnnnddddd -- SVE2 lookup table with 2-bit indices and 16-bit element size +IF_DEF(SVE_GH_3A, IS_NONE, NONE) // SVE_GH_3A ........i..mmmmm ......nnnnnddddd -- SVE2 lookup table with 4-bit indices and 16-bit element size +IF_DEF(SVE_GH_3B, IS_NONE, NONE) // SVE_GH_3B ........ii.mmmmm ......nnnnnddddd -- SVE2 lookup table with 4-bit indices and 16-bit element size +IF_DEF(SVE_GH_3B_B, IS_NONE, NONE) // SVE_GH_3B_B ........ii.mmmmm ......nnnnnddddd -- +IF_DEF(SVE_GI_4A, IS_NONE, NONE) // SVE_GI_4A ........xx.mmmmm ...gggnnnnnddddd -- SVE2 histogram generation (vector) +IF_DEF(SVE_GJ_3A, IS_NONE, NONE) // SVE_GJ_3A ...........mmmmm ......nnnnnddddd -- SVE2 crypto constructive binary operations +IF_DEF(SVE_GK_2A, IS_NONE, NONE) // SVE_GK_2A ................ ......mmmmmddddd -- SVE2 crypto destructive binary operations +IF_DEF(SVE_GL_1A, IS_NONE, NONE) // SVE_GL_1A ................ ...........ddddd -- SVE2 crypto unary operations +IF_DEF(SVE_GM_3A, IS_NONE, NONE) // SVE_GM_3A ...........iimmm ....iinnnnnddddd -- SVE2 FP8 multiply-add long (indexed) +IF_DEF(SVE_GN_3A, IS_NONE, NONE) // SVE_GN_3A ...........mmmmm ......nnnnnddddd -- SVE2 FP8 multiply-add long +IF_DEF(SVE_GO_3A, IS_NONE, NONE) // SVE_GO_3A ...........mmmmm ......nnnnnddddd -- SVE2 FP8 multiply-add long long +IF_DEF(SVE_GP_3A, IS_NONE, NONE) // SVE_GP_3A ........xx.....r ...gggmmmmmddddd -- SVE floating-point complex add (predicated) +IF_DEF(SVE_GQ_3A, IS_NONE, NONE) // SVE_GQ_3A ................ ...gggnnnnnddddd -- SVE floating-point convert precision odd elements +IF_DEF(SVE_GR_3A, IS_NONE, NONE) // SVE_GR_3A ........xx...... ...gggmmmmmddddd -- SVE2 floating-point pairwise operations +IF_DEF(SVE_GS_3A, IS_NONE, NONE) // SVE_GS_3A ........xx...... ...gggnnnnnddddd -- SVE floating-point recursive reduction (quadwords) +IF_DEF(SVE_GT_4A, IS_NONE, NONE) // SVE_GT_4A ........xx.mmmmm .rrgggnnnnnddddd -- SVE floating-point complex multiply-add (predicated) +IF_DEF(SVE_GU_3A, IS_NONE, NONE) // SVE_GU_3A ...........iimmm ......nnnnnddddd -- SVE floating-point multiply-add (indexed) +IF_DEF(SVE_GU_3B, IS_NONE, NONE) // SVE_GU_3B ...........immmm ......nnnnnddddd -- SVE floating-point multiply-add (indexed) +IF_DEF(SVE_GU_3C, IS_NONE, NONE) // SVE_GU_3C .........i.iimmm ......nnnnnddddd -- SVE floating-point multiply-add (indexed) +IF_DEF(SVE_GV_3A, IS_NONE, NONE) // SVE_GV_3A ...........immmm ....rrnnnnnddddd -- SVE floating-point complex multiply-add (indexed) +IF_DEF(SVE_GW_3A, IS_NONE, NONE) // SVE_GW_3A ........xx.mmmmm ......nnnnnddddd -- SVE FP clamp +IF_DEF(SVE_GW_3B, IS_NONE, NONE) // SVE_GW_3B ...........mmmmm ......nnnnnddddd -- SVE FP clamp +IF_DEF(SVE_GX_3A, IS_NONE, NONE) // SVE_GX_3A ...........iimmm ......nnnnnddddd -- SVE floating-point multiply (indexed) +IF_DEF(SVE_GX_3B, IS_NONE, NONE) // SVE_GX_3B ...........immmm ......nnnnnddddd -- SVE floating-point multiply (indexed) +IF_DEF(SVE_GX_3C, IS_NONE, NONE) // SVE_GX_3C .........i.iimmm ......nnnnnddddd -- SVE floating-point multiply (indexed) +IF_DEF(SVE_GY_3A, IS_NONE, NONE) // SVE_GY_3A ...........iimmm ....i.nnnnnddddd -- SVE BFloat16 floating-point dot product (indexed) +IF_DEF(SVE_GY_3B, IS_NONE, NONE) // SVE_GY_3B ...........iimmm ......nnnnnddddd -- SVE BFloat16 floating-point dot product (indexed) +IF_DEF(SVE_GY_3B_D, IS_NONE, NONE) // SVE_GY_3B_D ...........iimmm ......nnnnnddddd -- +IF_DEF(SVE_GZ_3A, IS_NONE, NONE) // SVE_GZ_3A ...........iimmm ....i.nnnnnddddd -- SVE floating-point multiply-add long (indexed) +IF_DEF(SVE_HA_3A, IS_NONE, NONE) // SVE_HA_3A ...........mmmmm ......nnnnnddddd -- SVE BFloat16 floating-point dot product +IF_DEF(SVE_HA_3A_E, IS_NONE, NONE) // SVE_HA_3A_E ...........mmmmm ......nnnnnddddd -- +IF_DEF(SVE_HA_3A_F, IS_NONE, NONE) // SVE_HA_3A_F ...........mmmmm ......nnnnnddddd -- +IF_DEF(SVE_HB_3A, IS_NONE, NONE) // SVE_HB_3A ...........mmmmm ......nnnnnddddd -- SVE floating-point multiply-add long +IF_DEF(SVE_HC_3A, IS_NONE, NONE) // SVE_HC_3A ...........iimmm ....iinnnnnddddd -- SVE2 FP8 multiply-add long long (indexed) +IF_DEF(SVE_HD_3A, IS_NONE, NONE) // SVE_HD_3A ...........mmmmm ......nnnnnddddd -- SVE floating point matrix multiply accumulate +IF_DEF(SVE_HD_3A_A, IS_NONE, NONE) // SVE_HD_3A_A ...........mmmmm ......nnnnnddddd -- +IF_DEF(SVE_HE_3A, IS_NONE, NONE) // SVE_HE_3A ........xx...... ...gggnnnnnddddd -- SVE floating-point recursive reduction +IF_DEF(SVE_HF_2A, IS_NONE, NONE) // SVE_HF_2A ........xx...... ......nnnnnddddd -- SVE floating-point reciprocal estimate (unpredicated) +IF_DEF(SVE_HG_2A, IS_NONE, NONE) // SVE_HG_2A ................ ......nnnn.ddddd -- SVE2 FP8 downconverts +IF_DEF(SVE_HH_2A, IS_NONE, NONE) // SVE_HH_2A ................ ......nnnnnddddd -- SVE2 FP8 upconverts +IF_DEF(SVE_HI_3A, IS_NONE, NONE) // SVE_HI_3A ........xx...... ...gggnnnnn.DDDD -- SVE floating-point compare with zero +IF_DEF(SVE_HJ_3A, IS_NONE, NONE) // SVE_HJ_3A ........xx...... ...gggmmmmmddddd -- SVE floating-point serial reduction (predicated) +IF_DEF(SVE_HK_3A, IS_NONE, NONE) // SVE_HK_3A ........xx.mmmmm ......nnnnnddddd -- SVE floating-point arithmetic (unpredicated) +IF_DEF(SVE_HK_3B, IS_NONE, NONE) // SVE_HK_3B ...........mmmmm ......nnnnnddddd -- SVE floating-point arithmetic (unpredicated) +IF_DEF(SVE_HL_3A, IS_NONE, NONE) // SVE_HL_3A ........xx...... ...gggmmmmmddddd -- SVE floating-point arithmetic (predicated) +IF_DEF(SVE_HL_3B, IS_NONE, NONE) // SVE_HL_3B ................ ...gggmmmmmddddd -- SVE floating-point arithmetic (predicated) +IF_DEF(SVE_HM_2A, IS_NONE, NONE) // SVE_HM_2A ........xx...... ...ggg....iddddd -- SVE floating-point arithmetic with immediate (predicated) +IF_DEF(SVE_HN_2A, IS_NONE, NONE) // SVE_HN_2A ........xx...iii ......mmmmmddddd -- SVE floating-point trig multiply-add coefficient +IF_DEF(SVE_HO_3A, IS_NONE, NONE) // SVE_HO_3A ................ ...gggnnnnnddddd -- SVE floating-point convert precision +IF_DEF(SVE_HO_3A_B, IS_NONE, NONE) // SVE_HO_3A_B ................ ...gggnnnnnddddd -- +IF_DEF(SVE_HP_3A, IS_NONE, NONE) // SVE_HP_3A .............xx. ...gggnnnnnddddd -- SVE floating-point convert to integer +IF_DEF(SVE_HP_3B, IS_NONE, NONE) // SVE_HP_3B ................ ...gggnnnnnddddd -- SVE floating-point convert to integer +IF_DEF(SVE_HP_3B_H, IS_NONE, NONE) // SVE_HP_3B_H ................ ...gggnnnnnddddd -- +IF_DEF(SVE_HP_3B_I, IS_NONE, NONE) // SVE_HP_3B_I ................ ...gggnnnnnddddd -- +IF_DEF(SVE_HP_3B_J, IS_NONE, NONE) // SVE_HP_3B_J ................ ...gggnnnnnddddd -- +IF_DEF(SVE_HQ_3A, IS_NONE, NONE) // SVE_HQ_3A ........xx...... ...gggnnnnnddddd -- SVE floating-point round to integral value +IF_DEF(SVE_HR_3A, IS_NONE, NONE) // SVE_HR_3A ........xx...... ...gggnnnnnddddd -- SVE floating-point unary operations +IF_DEF(SVE_HS_3A, IS_NONE, NONE) // SVE_HS_3A ................ ...gggnnnnnddddd -- SVE integer convert to floating-point +IF_DEF(SVE_HS_3A_H, IS_NONE, NONE) // SVE_HS_3A_H ................ ...gggnnnnnddddd -- +IF_DEF(SVE_HS_3A_I, IS_NONE, NONE) // SVE_HS_3A_I ................ ...gggnnnnnddddd -- +IF_DEF(SVE_HS_3A_J, IS_NONE, NONE) // SVE_HS_3A_J ................ ...gggnnnnnddddd -- +IF_DEF(SVE_HT_4A, IS_NONE, NONE) // SVE_HT_4A ........xx.mmmmm ...gggnnnnn.DDDD -- SVE floating-point compare vectors +IF_DEF(SVE_HU_4A, IS_NONE, NONE) // SVE_HU_4A ........xx.mmmmm ...gggnnnnnddddd -- SVE floating-point multiply-accumulate writing addend +IF_DEF(SVE_HU_4B, IS_NONE, NONE) // SVE_HU_4B ...........mmmmm ...gggnnnnnddddd -- SVE floating-point multiply-accumulate writing addend +IF_DEF(SVE_HV_4A, IS_NONE, NONE) // SVE_HV_4A ........xx.aaaaa ...gggmmmmmddddd -- SVE floating-point multiply-accumulate writing multiplicand +IF_DEF(SVE_HW_4A, IS_NONE, NONE) // SVE_HW_4A .........h.mmmmm ...gggnnnnnttttt -- SVE 32-bit gather load (scalar plus 32-bit unscaled offsets) +IF_DEF(SVE_HW_4A_A, IS_NONE, NONE) // SVE_HW_4A_A .........h.mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_HW_4B, IS_NONE, NONE) // SVE_HW_4B ...........mmmmm ...gggnnnnnttttt -- SVE 32-bit gather load (scalar plus 32-bit unscaled offsets) +IF_DEF(SVE_HW_4A_B, IS_NONE, NONE) // SVE_HW_4A_B .........h.mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_HW_4A_C, IS_NONE, NONE) // SVE_HW_4A_C .........h.mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_HW_4B_D, IS_NONE, NONE) // SVE_HW_4B_D ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_HX_3A, IS_NONE, NONE) // SVE_HX_3A ...........iiiii ...gggnnnnnttttt -- SVE 32-bit gather load (vector plus immediate) +IF_DEF(SVE_HX_3A_B, IS_NONE, NONE) // SVE_HX_3A_B ...........iiiii ...gggnnnnnttttt -- +IF_DEF(SVE_HX_3A_E, IS_NONE, NONE) // SVE_HX_3A_E ...........iiiii ...gggnnnnnttttt -- +IF_DEF(SVE_HY_3A, IS_NONE, NONE) // SVE_HY_3A .........h.mmmmm ...gggnnnnn.oooo -- SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) +IF_DEF(SVE_HY_3A_A, IS_NONE, NONE) // SVE_HY_3A_A .........h.mmmmm ...gggnnnnn.oooo -- +IF_DEF(SVE_HY_3B, IS_NONE, NONE) // SVE_HY_3B ...........mmmmm ...gggnnnnn.oooo -- SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) +IF_DEF(SVE_HZ_2A, IS_NONE, NONE) // SVE_HZ_2A ...........iiiii ...gggnnnnn.oooo -- SVE 32-bit gather prefetch (vector plus immediate) +IF_DEF(SVE_HZ_2A_B, IS_NONE, NONE) // SVE_HZ_2A_B ...........iiiii ...gggnnnnn.oooo -- +IF_DEF(SVE_IA_2A, IS_NONE, NONE) // SVE_IA_2A ..........iiiiii ...gggnnnnn.oooo -- SVE contiguous prefetch (scalar plus immediate) +IF_DEF(SVE_IB_3A, IS_NONE, NONE) // SVE_IB_3A ...........mmmmm ...gggnnnnn.oooo -- SVE contiguous prefetch (scalar plus scalar) +IF_DEF(SVE_IC_3A, IS_NONE, NONE) // SVE_IC_3A ..........iiiiii ...gggnnnnnttttt -- SVE load and broadcast element +IF_DEF(SVE_IC_3A_A, IS_NONE, NONE) // SVE_IC_3A_A ..........iiiiii ...gggnnnnnttttt -- +IF_DEF(SVE_IC_3A_B, IS_NONE, NONE) // SVE_IC_3A_B ..........iiiiii ...gggnnnnnttttt -- +IF_DEF(SVE_IC_3A_C, IS_NONE, NONE) // SVE_IC_3A_C ..........iiiiii ...gggnnnnnttttt -- +IF_DEF(SVE_ID_2A, IS_NONE, NONE) // SVE_ID_2A ..........iiiiii ...iiinnnnn.TTTT -- SVE load predicate register +IF_DEF(SVE_IE_2A, IS_NONE, NONE) // SVE_IE_2A ..........iiiiii ...iiinnnnnttttt -- SVE load vector register +IF_DEF(SVE_IF_4A, IS_NONE, NONE) // SVE_IF_4A ...........mmmmm ...gggnnnnnttttt -- SVE2 32-bit gather non-temporal load (vector plus scalar) +IF_DEF(SVE_IF_4A_A, IS_NONE, NONE) // SVE_IF_4A_A ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IG_4A, IS_NONE, NONE) // SVE_IG_4A ...........mmmmm ...gggnnnnnttttt -- SVE contiguous first-fault load (scalar plus scalar) +IF_DEF(SVE_IG_4A_C, IS_NONE, NONE) // SVE_IG_4A_C ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IG_4A_D, IS_NONE, NONE) // SVE_IG_4A_D ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IG_4A_E, IS_NONE, NONE) // SVE_IG_4A_E ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IG_4A_F, IS_NONE, NONE) // SVE_IG_4A_F ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IG_4A_G, IS_NONE, NONE) // SVE_IG_4A_G ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IH_3A, IS_NONE, NONE) // SVE_IH_3A ............iiii ...gggnnnnnttttt -- SVE contiguous load (quadwords, scalar plus immediate) +IF_DEF(SVE_IH_3A_F, IS_NONE, NONE) // SVE_IH_3A_F ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_IH_3A_G, IS_NONE, NONE) // SVE_IH_3A_G ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_IH_3A_A, IS_NONE, NONE) // SVE_IH_3A_A ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_II_4A, IS_NONE, NONE) // SVE_II_4A ...........mmmmm ...gggnnnnnttttt -- SVE contiguous load (quadwords, scalar plus scalar) +IF_DEF(SVE_II_4A_H, IS_NONE, NONE) // SVE_II_4A_H ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_II_4A_I, IS_NONE, NONE) // SVE_II_4A_I ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_II_4A_B, IS_NONE, NONE) // SVE_II_4A_B ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IJ_3A, IS_NONE, NONE) // SVE_IJ_3A ............iiii ...gggnnnnnttttt -- SVE contiguous load (scalar plus immediate) +IF_DEF(SVE_IJ_3A_C, IS_NONE, NONE) // SVE_IJ_3A_C ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_IJ_3A_D, IS_NONE, NONE) // SVE_IJ_3A_D ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_IJ_3A_E, IS_NONE, NONE) // SVE_IJ_3A_E ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_IJ_3A_F, IS_NONE, NONE) // SVE_IJ_3A_F ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_IJ_3A_G, IS_NONE, NONE) // SVE_IJ_3A_G ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_IK_4A, IS_NONE, NONE) // SVE_IK_4A ...........mmmmm ...gggnnnnnttttt -- SVE contiguous load (scalar plus scalar) +IF_DEF(SVE_IK_4A_F, IS_NONE, NONE) // SVE_IK_4A_F ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IK_4A_G, IS_NONE, NONE) // SVE_IK_4A_G ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IK_4A_H, IS_NONE, NONE) // SVE_IK_4A_H ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IK_4A_I, IS_NONE, NONE) // SVE_IK_4A_I ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IK_4A_E, IS_NONE, NONE) // SVE_IK_4A_E ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IL_3A, IS_NONE, NONE) // SVE_IL_3A ............iiii ...gggnnnnnttttt -- SVE contiguous non-fault load (scalar plus immediate) +IF_DEF(SVE_IL_3A_A, IS_NONE, NONE) // SVE_IL_3A_A ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_IL_3A_B, IS_NONE, NONE) // SVE_IL_3A_B ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_IL_3A_C, IS_NONE, NONE) // SVE_IL_3A_C ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_IM_3A, IS_NONE, NONE) // SVE_IM_3A ............iiii ...gggnnnnnttttt -- SVE contiguous non-temporal load (scalar plus immediate) +IF_DEF(SVE_IN_4A, IS_NONE, NONE) // SVE_IN_4A ...........mmmmm ...gggnnnnnttttt -- SVE contiguous non-temporal load (scalar plus scalar) +IF_DEF(SVE_IO_3A, IS_NONE, NONE) // SVE_IO_3A ............iiii ...gggnnnnnttttt -- SVE load and broadcast quadword (scalar plus immediate) +IF_DEF(SVE_IP_4A, IS_NONE, NONE) // SVE_IP_4A ...........mmmmm ...gggnnnnnttttt -- SVE load and broadcast quadword (scalar plus scalar) +IF_DEF(SVE_IQ_3A, IS_NONE, NONE) // SVE_IQ_3A ............iiii ...gggnnnnnttttt -- SVE load multiple structures (quadwords, scalar plus immediate) +IF_DEF(SVE_IR_4A, IS_NONE, NONE) // SVE_IR_4A ...........mmmmm ...gggnnnnnttttt -- SVE load multiple structures (quadwords, scalar plus scalar) +IF_DEF(SVE_IS_3A, IS_NONE, NONE) // SVE_IS_3A ............iiii ...gggnnnnnttttt -- SVE load multiple structures (scalar plus immediate) +IF_DEF(SVE_IT_4A, IS_NONE, NONE) // SVE_IT_4A ...........mmmmm ...gggnnnnnttttt -- SVE load multiple structures (scalar plus scalar) +IF_DEF(SVE_IU_4A, IS_NONE, NONE) // SVE_IU_4A .........h.mmmmm ...gggnnnnnttttt -- SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets) +IF_DEF(SVE_IU_4A_A, IS_NONE, NONE) // SVE_IU_4A_A .........h.mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IU_4B, IS_NONE, NONE) // SVE_IU_4B ...........mmmmm ...gggnnnnnttttt -- SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets) +IF_DEF(SVE_IU_4B_B, IS_NONE, NONE) // SVE_IU_4B_B ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IU_4A_C, IS_NONE, NONE) // SVE_IU_4A_C .........h.mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IU_4B_D, IS_NONE, NONE) // SVE_IU_4B_D ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_IV_3A, IS_NONE, NONE) // SVE_IV_3A ...........iiiii ...gggnnnnnttttt -- SVE 64-bit gather load (vector plus immediate) +IF_DEF(SVE_IW_4A, IS_NONE, NONE) // SVE_IW_4A ...........mmmmm ...gggnnnnnttttt -- SVE2 128-bit gather load (vector plus scalar) +IF_DEF(SVE_IX_4A, IS_NONE, NONE) // SVE_IX_4A ...........mmmmm ...gggnnnnnttttt -- SVE2 64-bit gather non-temporal load (vector plus scalar) +IF_DEF(SVE_IY_4A, IS_NONE, NONE) // SVE_IY_4A ...........mmmmm ...gggnnnnnttttt -- SVE2 128-bit scatter store (vector plus scalar) +IF_DEF(SVE_IZ_4A, IS_NONE, NONE) // SVE_IZ_4A ...........mmmmm ...gggnnnnnttttt -- SVE2 32-bit scatter non-temporal store (vector plus scalar) +IF_DEF(SVE_IZ_4A_A, IS_NONE, NONE) // SVE_IZ_4A_A ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_JA_4A, IS_NONE, NONE) // SVE_JA_4A ...........mmmmm ...gggnnnnnttttt -- SVE2 64-bit scatter non-temporal store (vector plus scalar) +IF_DEF(SVE_JB_4A, IS_NONE, NONE) // SVE_JB_4A ...........mmmmm ...gggnnnnnttttt -- SVE contiguous non-temporal store (scalar plus scalar) +IF_DEF(SVE_JC_4A, IS_NONE, NONE) // SVE_JC_4A ...........mmmmm ...gggnnnnnttttt -- SVE store multiple structures (scalar plus scalar) +IF_DEF(SVE_JD_4A, IS_NONE, NONE) // SVE_JD_4A .........xxmmmmm ...gggnnnnnttttt -- SVE contiguous store (scalar plus scalar) +IF_DEF(SVE_JD_4B, IS_NONE, NONE) // SVE_JD_4B ..........xmmmmm ...gggnnnnnttttt -- SVE contiguous store (scalar plus scalar) +IF_DEF(SVE_JD_4C, IS_NONE, NONE) // SVE_JD_4C ...........mmmmm ...gggnnnnnttttt -- SVE contiguous store (scalar plus scalar) +IF_DEF(SVE_JD_4C_A, IS_NONE, NONE) // SVE_JD_4C_A ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_JE_3A, IS_NONE, NONE) // SVE_JE_3A ............iiii ...gggnnnnnttttt -- SVE store multiple structures (quadwords, scalar plus immediate) +IF_DEF(SVE_JF_4A, IS_NONE, NONE) // SVE_JF_4A ...........mmmmm ...gggnnnnnttttt -- SVE store multiple structures (quadwords, scalar plus scalar) +IF_DEF(SVE_JG_2A, IS_NONE, NONE) // SVE_JG_2A ..........iiiiii ...iiinnnnn.TTTT -- SVE store predicate register +IF_DEF(SVE_JH_2A, IS_NONE, NONE) // SVE_JH_2A ..........iiiiii ...iiinnnnnttttt -- SVE store vector register +IF_DEF(SVE_JI_3A, IS_NONE, NONE) // SVE_JI_3A ...........iiiii ...gggnnnnnttttt -- SVE 32-bit scatter store (vector plus immediate) +IF_DEF(SVE_JI_3A_A, IS_NONE, NONE) // SVE_JI_3A_A ...........iiiii ...gggnnnnnttttt -- +IF_DEF(SVE_JJ_4A, IS_NONE, NONE) // SVE_JJ_4A ...........mmmmm .h.gggnnnnnttttt -- SVE 64-bit scatter store (scalar plus 64-bit scaled offsets) +IF_DEF(SVE_JJ_4A_B, IS_NONE, NONE) // SVE_JJ_4A_B ...........mmmmm .h.gggnnnnnttttt -- +IF_DEF(SVE_JJ_4A_C, IS_NONE, NONE) // SVE_JJ_4A_C ...........mmmmm .h.gggnnnnnttttt -- +IF_DEF(SVE_JJ_4A_D, IS_NONE, NONE) // SVE_JJ_4A_D ...........mmmmm .h.gggnnnnnttttt -- +IF_DEF(SVE_JJ_4B, IS_NONE, NONE) // SVE_JJ_4B ...........mmmmm ...gggnnnnnttttt -- SVE 64-bit scatter store (scalar plus 64-bit scaled offsets) +IF_DEF(SVE_JJ_4B_E, IS_NONE, NONE) // SVE_JJ_4B_E ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_JJ_4B_C, IS_NONE, NONE) // SVE_JJ_4B_C ...........mmmmm ...gggnnnnnttttt -- +IF_DEF(SVE_JK_4A, IS_NONE, NONE) // SVE_JK_4A ...........mmmmm .h.gggnnnnnttttt -- SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets) +IF_DEF(SVE_JK_4A_B, IS_NONE, NONE) // SVE_JK_4A_B ...........mmmmm .h.gggnnnnnttttt -- +IF_DEF(SVE_JK_4B, IS_NONE, NONE) // SVE_JK_4B ...........mmmmm ...gggnnnnnttttt -- SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets) +IF_DEF(SVE_JL_3A, IS_NONE, NONE) // SVE_JL_3A ...........iiiii ...gggnnnnnttttt -- SVE 64-bit scatter store (vector plus immediate) +IF_DEF(SVE_JM_3A, IS_NONE, NONE) // SVE_JM_3A ............iiii ...gggnnnnnttttt -- SVE contiguous non-temporal store (scalar plus immediate) +IF_DEF(SVE_JN_3A, IS_NONE, NONE) // SVE_JN_3A .........xx.iiii ...gggnnnnnttttt -- SVE contiguous store (scalar plus immediate) +IF_DEF(SVE_JN_3B, IS_NONE, NONE) // SVE_JN_3B ..........x.iiii ...gggnnnnnttttt -- SVE contiguous store (scalar plus immediate) +IF_DEF(SVE_JN_3C, IS_NONE, NONE) // SVE_JN_3C ............iiii ...gggnnnnnttttt -- SVE contiguous store (scalar plus immediate) +IF_DEF(SVE_JN_3C_D, IS_NONE, NONE) // SVE_JN_3C_D ............iiii ...gggnnnnnttttt -- +IF_DEF(SVE_JO_3A, IS_NONE, NONE) // SVE_JO_3A ............iiii ...gggnnnnnttttt -- SVE store multiple structures (scalar plus immediate) + +////////////////////////////////////////////////////////////////////////////// +#undef IF_DEF +////////////////////////////////////////////////////////////////////////////// +// clang-format on diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp index 287b214d0f40b8..726ecc9a29bd86 100644 --- a/src/coreclr/jit/hwintrinsic.cpp +++ b/src/coreclr/jit/hwintrinsic.cpp @@ -1391,8 +1391,8 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, { case 0: { - assert(!isScalar); - retNode = gtNewSimdHWIntrinsicNode(retType, intrinsic, simdBaseJitType, simdSize); + retNode = isScalar ? gtNewScalarHWIntrinsicNode(retType, intrinsic) + : gtNewSimdHWIntrinsicNode(retType, intrinsic, simdBaseJitType, simdSize); break; } diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index 15b9510b0f4b60..c55fdafcbd307e 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -34,6 +34,8 @@ static CORINFO_InstructionSet Arm64VersionOfIsa(CORINFO_InstructionSet isa) return InstructionSet_Sha256_Arm64; case InstructionSet_Rdm: return InstructionSet_Rdm_Arm64; + case InstructionSet_Sve: + return InstructionSet_Sve_Arm64; default: return InstructionSet_NONE; } @@ -97,6 +99,10 @@ static CORINFO_InstructionSet lookupInstructionSet(const char* className) { return InstructionSet_Sha256; } + if (strcmp(className, "Sve") == 0) + { + return InstructionSet_Sve; + } } else if (className[0] == 'V') { @@ -166,6 +172,8 @@ bool HWIntrinsicInfo::isFullyImplementedIsa(CORINFO_InstructionSet isa) case InstructionSet_Sha1_Arm64: case InstructionSet_Sha256: case InstructionSet_Sha256_Arm64: + case InstructionSet_Sve: + case InstructionSet_Sve_Arm64: case InstructionSet_Vector64: case InstructionSet_Vector128: return true; diff --git a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp index 57df941c5fe685..408f8fb8334ffb 100644 --- a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp +++ b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp @@ -419,6 +419,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, opt); break; + case 0: + GetEmitter()->emitIns_R(ins, emitSize, targetReg); + break; + default: unreached(); } diff --git a/src/coreclr/jit/hwintrinsiclistarm64.h b/src/coreclr/jit/hwintrinsiclistarm64.h index f0a0529e5e64c3..f04b7f9006e6df 100644 --- a/src/coreclr/jit/hwintrinsiclistarm64.h +++ b/src/coreclr/jit/hwintrinsiclistarm64.h @@ -785,6 +785,8 @@ HARDWARE_INTRINSIC(Sha256, ScheduleUpdate1, #endif // FEATURE_HW_INTRINSIC +#include "hwintrinsiclistarm64sve.h" + #undef HARDWARE_INTRINSIC // clang-format on diff --git a/src/coreclr/jit/hwintrinsiclistarm64sve.h b/src/coreclr/jit/hwintrinsiclistarm64sve.h new file mode 100644 index 00000000000000..17039fc6f4105c --- /dev/null +++ b/src/coreclr/jit/hwintrinsiclistarm64sve.h @@ -0,0 +1,25 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +/*****************************************************************************/ +#ifndef HARDWARE_INTRINSIC +#error Define HARDWARE_INTRINSIC before including this file +#endif +/*****************************************************************************/ + +// clang-format off + +#ifdef FEATURE_HW_INTRINSICS +// *************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************** +// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags +// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE} +// *************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************** +// SVE Intrinsics + +HARDWARE_INTRINSIC(Sve, Count16BitElements, 8, 0, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_mrs_tpid0, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_NoFlag) + +#endif // FEATURE_HW_INTRINSIC + +#undef HARDWARE_INTRINSIC + +// clang-format on diff --git a/src/coreclr/jit/instr.cpp b/src/coreclr/jit/instr.cpp index 0205217a3fcbb3..809545936d986b 100644 --- a/src/coreclr/jit/instr.cpp +++ b/src/coreclr/jit/instr.cpp @@ -65,6 +65,19 @@ const char* CodeGen::genInsName(instruction ins) #define INST9(id, nm, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) nm, #include "instrs.h" + #define INST1(id, nm, info, fmt, e1 ) nm, + #define INST2(id, nm, info, fmt, e1, e2 ) nm, + #define INST3(id, nm, info, fmt, e1, e2, e3 ) nm, + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) nm, + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) nm, + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) nm, + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) nm, + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) nm, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) nm, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10,e11 ) nm, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13) nm, + #include "instrsarm64sve.h" + #elif defined(TARGET_LOONGARCH64) #define INST(id, nm, ldst, e1) nm, #include "instrs.h" diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h index bbc8089376ae58..4ee2a249a489e7 100644 --- a/src/coreclr/jit/instr.h +++ b/src/coreclr/jit/instr.h @@ -49,6 +49,19 @@ enum instruction : uint32_t #define INST9(id, nm, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) INS_##id, #include "instrs.h" + #define INST1(id, nm, info, fmt, e1 ) INS_sve_##id, + #define INST2(id, nm, info, fmt, e1, e2 ) INS_sve_##id, + #define INST3(id, nm, info, fmt, e1, e2, e3 ) INS_sve_##id, + #define INST4(id, nm, info, fmt, e1, e2, e3, e4 ) INS_sve_##id, + #define INST5(id, nm, info, fmt, e1, e2, e3, e4, e5 ) INS_sve_##id, + #define INST6(id, nm, info, fmt, e1, e2, e3, e4, e5, e6 ) INS_sve_##id, + #define INST7(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7 ) INS_sve_##id, + #define INST8(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) INS_sve_##id, + #define INST9(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9 ) INS_sve_##id, + #define INST11(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10,e11 ) INS_sve_##id, + #define INST13(id, nm, info, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13) INS_sve_##id, + #include "instrsarm64sve.h" + INS_lea, // Not a real instruction. It is used for load the address of stack locals #elif defined(TARGET_LOONGARCH64) diff --git a/src/coreclr/jit/instrsarm64sve.h b/src/coreclr/jit/instrsarm64sve.h new file mode 100644 index 00000000000000..d10b075ad09467 --- /dev/null +++ b/src/coreclr/jit/instrsarm64sve.h @@ -0,0 +1,2873 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +/***************************************************************************** + * Arm64 instructions for JIT compiler + * + * id -- the enum name for the instruction + * nm -- textual name (for assembly dipslay) + * info -- miscellaneous instruction info (load/store/compare/ASIMD right shift) + * fmt -- encoding format used by this instruction +* e1 -- encoding 1 +* e2 -- encoding 2 +* e3 -- encoding 3 +* e4 -- encoding 4 +* e5 -- encoding 5 +* e6 -- encoding 6 +* e7 -- encoding 7 +* e8 -- encoding 8 +* e9 -- encoding 9 +* e10 -- encoding 10 +* e11 -- encoding 11 +* e12 -- encoding 12 +* e13 -- encoding 13 +*****************************************************************************/ +#if !defined(TARGET_ARM64) +#error Unexpected target type +#endif + +#ifndef INST1 +#error INST1 must be defined before including this file. +#endif +#ifndef INST2 +#error INST2 must be defined before including this file. +#endif +#ifndef INST3 +#error INST3 must be defined before including this file. +#endif +#ifndef INST4 +#error INST4 must be defined before including this file. +#endif +#ifndef INST5 +#error INST5 must be defined before including this file. +#endif +#ifndef INST6 +#error INST6 must be defined before including this file. +#endif +#ifndef INST7 +#error INST7 must be defined before including this file. +#endif +#ifndef INST8 +#error INST8 must be defined before including this file. +#endif +#ifndef INST9 +#error INST9 must be defined before including this file. +#endif +#ifndef INST11 +#error INST11 must be defined before including this file. +#endif +#ifndef INST13 +#error INST13 must be defined before including this file. +#endif + +/*****************************************************************************/ +/* The following is ARM64-specific */ +/*****************************************************************************/ + +// If you're adding a new instruction: +// You need not only to fill in one of these macros describing the instruction, but also: +// * If the instruction writes to more than one destination register, update the function +// emitInsMayWriteMultipleRegs in emitArm64.cpp. + +// clang-format off +INST13(invalid, "INVALID", 0, IF_NONE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE) + + +// enum name info SVE_AU_3A SVE_BT_1A SVE_BV_2A SVE_BV_2A_J SVE_BW_2A SVE_CB_2A SVE_CP_3A SVE_CQ_3A SVE_CW_4A SVE_CZ_4A SVE_CZ_4A_K SVE_CZ_4A_L SVE_EB_1A +INST13(mov, "mov", 0, IF_SVE_13A, 0x04603000, 0x05C00000, 0x05100000, 0x05104000, 0x05202000, 0x05203800, 0x05208000, 0x0528A000, 0x0520C000, 0x25004000, 0x25004210, 0x25804000, 0x2538C000 ) + // MOV .D, .D SVE_AU_3A 00000100011mmmmm 001100nnnnnddddd 0460 3000 + // MOV ., # SVE_BT_1A 00000101110000ii iiiiiiiiiiiddddd 05C0 0000 + // MOV ., /Z, #{, } SVE_BV_2A 00000101xx01gggg 00hiiiiiiiiddddd 0510 0000 + // MOV ., /M, #{, } SVE_BV_2A_J 00000101xx01gggg 01hiiiiiiiiddddd 0510 4000 + // MOV ., .[] SVE_BW_2A 00000101ii1xxxxx 001000nnnnnddddd 0520 2000 + // MOV ., SVE_CB_2A 00000101xx100000 001110nnnnnddddd 0520 3800 + // MOV ., /M, SVE_CP_3A 00000101xx100000 100gggnnnnnddddd 0520 8000 + // MOV ., /M, SVE_CQ_3A 00000101xx101000 101gggnnnnnddddd 0528 A000 + // MOV ., /M, . SVE_CW_4A 00000101xx1mmmmm 11VVVVnnnnnddddd 0520 C000 + // MOV .B, /Z, .B SVE_CZ_4A 001001010000MMMM 01gggg0NNNN0DDDD 2500 4000 + // MOV .B, /M, .B SVE_CZ_4A_K 001001010000MMMM 01gggg1NNNN1DDDD 2500 4210 + // MOV .B, .B SVE_CZ_4A_L 001001011000MMMM 01gggg0NNNN0DDDD 2580 4000 + // MOV ., #{, } SVE_EB_1A 00100101xx111000 11hiiiiiiiiddddd 2538 C000 + + +// enum name info SVE_JD_4B SVE_JD_4C SVE_JI_3A_A SVE_JJ_4A SVE_JJ_4A_B SVE_JJ_4A_C SVE_JJ_4A_D SVE_JJ_4B SVE_JJ_4B_E SVE_JN_3B SVE_JN_3C +INST11(st1w, "st1w", 0, IF_SVE_11A, 0xE5404000, 0xE5004000, 0xE540A000, 0xE5608000, 0xE5208000, 0xE5008000, 0xE5408000, 0xE520A000, 0xE500A000, 0xE540E000, 0xE500E000 ) + // ST1W {.}, , [, , LSL #2] SVE_JD_4B 1110010101xmmmmm 010gggnnnnnttttt E540 4000 + // ST1W {.Q }, , [, , LSL #2] SVE_JD_4C 11100101000mmmmm 010gggnnnnnttttt E500 4000 + // ST1W {.D }, , [.D{, #}] SVE_JI_3A_A 11100101010iiiii 101gggnnnnnttttt E540 A000 + // ST1W {.S }, , [, .S, #2] SVE_JJ_4A 11100101011mmmmm 1h0gggnnnnnttttt E560 8000 + // ST1W {.D }, , [, .D, #2] SVE_JJ_4A_B 11100101001mmmmm 1h0gggnnnnnttttt E520 8000 + // ST1W {.D }, , [, .D, ] SVE_JJ_4A_C 11100101000mmmmm 1h0gggnnnnnttttt E500 8000 + // ST1W {.S }, , [, .S, ] SVE_JJ_4A_D 11100101010mmmmm 1h0gggnnnnnttttt E540 8000 + // ST1W {.D }, , [, .D, LSL #2] SVE_JJ_4B 11100101001mmmmm 101gggnnnnnttttt E520 A000 + // ST1W {.D }, , [, .D] SVE_JJ_4B_E 11100101000mmmmm 101gggnnnnnttttt E500 A000 + // ST1W {.}, , [{, #, MUL VL}] SVE_JN_3B 1110010101x0iiii 111gggnnnnnttttt E540 E000 + // ST1W {.Q }, , [{, #, MUL VL}] SVE_JN_3C 111001010000iiii 111gggnnnnnttttt E500 E000 + + +// enum name info SVE_HW_4A SVE_HW_4A_A SVE_HW_4A_B SVE_HW_4A_C SVE_HW_4B SVE_HW_4B_D SVE_HX_3A_E SVE_IJ_3A_F SVE_IK_4A_G +INST9(ld1sh, "ld1sh", 0, IF_SVE_9A, 0x84A00000, 0xC4A00000, 0xC4800000, 0x84800000, 0xC4E08000, 0xC4C08000, 0x84A08000, 0xA500A000, 0xA5004000 ) + // LD1SH {.S }, /Z, [, .S, #1] SVE_HW_4A 100001001h1mmmmm 000gggnnnnnttttt 84A0 0000 + // LD1SH {.D }, /Z, [, .D, #1] SVE_HW_4A_A 110001001h1mmmmm 000gggnnnnnttttt C4A0 0000 + // LD1SH {.D }, /Z, [, .D, ] SVE_HW_4A_B 110001001h0mmmmm 000gggnnnnnttttt C480 0000 + // LD1SH {.S }, /Z, [, .S, ] SVE_HW_4A_C 100001001h0mmmmm 000gggnnnnnttttt 8480 0000 + // LD1SH {.D }, /Z, [, .D, LSL #1] SVE_HW_4B 11000100111mmmmm 100gggnnnnnttttt C4E0 8000 + // LD1SH {.D }, /Z, [, .D] SVE_HW_4B_D 11000100110mmmmm 100gggnnnnnttttt C4C0 8000 + // LD1SH {.D }, /Z, [.D{, #}] SVE_HX_3A_E 10000100101iiiii 100gggnnnnnttttt 84A0 8000 + // LD1SH {.D }, /Z, [{, #, MUL VL}] SVE_IJ_3A_F 101001010000iiii 101gggnnnnnttttt A500 A000 + // LD1SH {.D }, /Z, [, , LSL #1] SVE_IK_4A_G 10100101000mmmmm 010gggnnnnnttttt A500 4000 + + +// enum name info SVE_HW_4A SVE_HW_4A_A SVE_HW_4A_B SVE_HW_4A_C SVE_HW_4B SVE_HW_4B_D SVE_HX_3A_E SVE_IJ_3A_G SVE_IK_4A_I +INST9(ld1h, "ld1h", 0, IF_SVE_9B, 0x84A04000, 0xC4A04000, 0xC4804000, 0x84804000, 0xC4E0C000, 0xC4C0C000, 0x84A0C000, 0xA480A000, 0xA4804000 ) + // LD1H {.S }, /Z, [, .S, #1] SVE_HW_4A 100001001h1mmmmm 010gggnnnnnttttt 84A0 4000 + // LD1H {.D }, /Z, [, .D, #1] SVE_HW_4A_A 110001001h1mmmmm 010gggnnnnnttttt C4A0 4000 + // LD1H {.D }, /Z, [, .D, ] SVE_HW_4A_B 110001001h0mmmmm 010gggnnnnnttttt C480 4000 + // LD1H {.S }, /Z, [, .S, ] SVE_HW_4A_C 100001001h0mmmmm 010gggnnnnnttttt 8480 4000 + // LD1H {.D }, /Z, [, .D, LSL #1] SVE_HW_4B 11000100111mmmmm 110gggnnnnnttttt C4E0 C000 + // LD1H {.D }, /Z, [, .D] SVE_HW_4B_D 11000100110mmmmm 110gggnnnnnttttt C4C0 C000 + // LD1H {.D }, /Z, [.D{, #}] SVE_HX_3A_E 10000100101iiiii 110gggnnnnnttttt 84A0 C000 + // LD1H {.D }, /Z, [{, #, MUL VL}] SVE_IJ_3A_G 101001001000iiii 101gggnnnnnttttt A480 A000 + // LD1H {.D }, /Z, [, , LSL #1] SVE_IK_4A_I 10100100100mmmmm 010gggnnnnnttttt A480 4000 + + +// enum name info SVE_HW_4A SVE_HW_4A_A SVE_HW_4A_B SVE_HW_4A_C SVE_HW_4B SVE_HW_4B_D SVE_HX_3A_E SVE_IH_3A_F SVE_II_4A_H +INST9(ld1w, "ld1w", 0, IF_SVE_9C, 0x85204000, 0xC5204000, 0xC5004000, 0x85004000, 0xC560C000, 0xC540C000, 0x8520C000, 0xA5002000, 0xA5000000 ) + // LD1W {.S }, /Z, [, .S, #2] SVE_HW_4A 100001010h1mmmmm 010gggnnnnnttttt 8520 4000 + // LD1W {.D }, /Z, [, .D, #2] SVE_HW_4A_A 110001010h1mmmmm 010gggnnnnnttttt C520 4000 + // LD1W {.D }, /Z, [, .D, ] SVE_HW_4A_B 110001010h0mmmmm 010gggnnnnnttttt C500 4000 + // LD1W {.S }, /Z, [, .S, ] SVE_HW_4A_C 100001010h0mmmmm 010gggnnnnnttttt 8500 4000 + // LD1W {.D }, /Z, [, .D, LSL #2] SVE_HW_4B 11000101011mmmmm 110gggnnnnnttttt C560 C000 + // LD1W {.D }, /Z, [, .D] SVE_HW_4B_D 11000101010mmmmm 110gggnnnnnttttt C540 C000 + // LD1W {.D }, /Z, [.D{, #}] SVE_HX_3A_E 10000101001iiiii 110gggnnnnnttttt 8520 C000 + // LD1W {.D }, /Z, [{, #, MUL VL}] SVE_IH_3A_F 101001010000iiii 001gggnnnnnttttt A500 2000 + // LD1W {.D }, /Z, [, , LSL #2] SVE_II_4A_H 10100101000mmmmm 000gggnnnnnttttt A500 0000 + + +// enum name info SVE_IH_3A SVE_IH_3A_A SVE_II_4A SVE_II_4A_B SVE_IU_4A SVE_IU_4A_C SVE_IU_4B SVE_IU_4B_D SVE_IV_3A +INST9(ld1d, "ld1d", 0, IF_SVE_9D, 0xA5E0A000, 0xA5902000, 0xA5E04000, 0xA5808000, 0xC5A04000, 0xC5804000, 0xC5E0C000, 0xC5C0C000, 0xC5A0C000 ) + // LD1D {.D }, /Z, [{, #, MUL VL}] SVE_IH_3A 101001011110iiii 101gggnnnnnttttt A5E0 A000 + // LD1D {.Q }, /Z, [{, #, MUL VL}] SVE_IH_3A_A 101001011001iiii 001gggnnnnnttttt A590 2000 + // LD1D {.D }, /Z, [, , LSL #3] SVE_II_4A 10100101111mmmmm 010gggnnnnnttttt A5E0 4000 + // LD1D {.Q }, /Z, [, , LSL #3] SVE_II_4A_B 10100101100mmmmm 100gggnnnnnttttt A580 8000 + // LD1D {.D }, /Z, [, .D, #3] SVE_IU_4A 110001011h1mmmmm 010gggnnnnnttttt C5A0 4000 + // LD1D {.D }, /Z, [, .D, ] SVE_IU_4A_C 110001011h0mmmmm 010gggnnnnnttttt C580 4000 + // LD1D {.D }, /Z, [, .D, LSL #3] SVE_IU_4B 11000101111mmmmm 110gggnnnnnttttt C5E0 C000 + // LD1D {.D }, /Z, [, .D] SVE_IU_4B_D 11000101110mmmmm 110gggnnnnnttttt C5C0 C000 + // LD1D {.D }, /Z, [.D{, #}] SVE_IV_3A 11000101101iiiii 110gggnnnnnttttt C5A0 C000 + + +// enum name info SVE_JD_4A SVE_JI_3A_A SVE_JJ_4A SVE_JJ_4A_B SVE_JJ_4A_C SVE_JJ_4A_D SVE_JJ_4B SVE_JJ_4B_E SVE_JN_3A +INST9(st1h, "st1h", 0, IF_SVE_9E, 0xE4804000, 0xE4C0A000, 0xE4E08000, 0xE4A08000, 0xE4808000, 0xE4C08000, 0xE4A0A000, 0xE480A000, 0xE480E000 ) + // ST1H {.}, , [, , LSL #1] SVE_JD_4A 111001001xxmmmmm 010gggnnnnnttttt E480 4000 + // ST1H {.D }, , [.D{, #}] SVE_JI_3A_A 11100100110iiiii 101gggnnnnnttttt E4C0 A000 + // ST1H {.S }, , [, .S, #1] SVE_JJ_4A 11100100111mmmmm 1h0gggnnnnnttttt E4E0 8000 + // ST1H {.D }, , [, .D, #1] SVE_JJ_4A_B 11100100101mmmmm 1h0gggnnnnnttttt E4A0 8000 + // ST1H {.D }, , [, .D, ] SVE_JJ_4A_C 11100100100mmmmm 1h0gggnnnnnttttt E480 8000 + // ST1H {.S }, , [, .S, ] SVE_JJ_4A_D 11100100110mmmmm 1h0gggnnnnnttttt E4C0 8000 + // ST1H {.D }, , [, .D, LSL #1] SVE_JJ_4B 11100100101mmmmm 101gggnnnnnttttt E4A0 A000 + // ST1H {.D }, , [, .D] SVE_JJ_4B_E 11100100100mmmmm 101gggnnnnnttttt E480 A000 + // ST1H {.}, , [{, #, MUL VL}] SVE_JN_3A 111001001xx0iiii 111gggnnnnnttttt E480 E000 + + +// enum name info SVE_JD_4C SVE_JD_4C_A SVE_JJ_4A SVE_JJ_4A_B SVE_JJ_4B SVE_JJ_4B_C SVE_JL_3A SVE_JN_3C SVE_JN_3C_D +INST9(st1d, "st1d", 0, IF_SVE_9F, 0xE5E04000, 0xE5C04000, 0xE5A08000, 0xE5808000, 0xE5A0A000, 0xE580A000, 0xE5C0A000, 0xE5E0E000, 0xE5C0E000 ) + // ST1D {.D }, , [, , LSL #3] SVE_JD_4C 11100101111mmmmm 010gggnnnnnttttt E5E0 4000 + // ST1D {.Q }, , [, , LSL #3] SVE_JD_4C_A 11100101110mmmmm 010gggnnnnnttttt E5C0 4000 + // ST1D {.D }, , [, .D, #3] SVE_JJ_4A 11100101101mmmmm 1h0gggnnnnnttttt E5A0 8000 + // ST1D {.D }, , [, .D, ] SVE_JJ_4A_B 11100101100mmmmm 1h0gggnnnnnttttt E580 8000 + // ST1D {.D }, , [, .D, LSL #3] SVE_JJ_4B 11100101101mmmmm 101gggnnnnnttttt E5A0 A000 + // ST1D {.D }, , [, .D] SVE_JJ_4B_C 11100101100mmmmm 101gggnnnnnttttt E580 A000 + // ST1D {.D }, , [.D{, #}] SVE_JL_3A 11100101110iiiii 101gggnnnnnttttt E5C0 A000 + // ST1D {.D }, , [{, #, MUL VL}] SVE_JN_3C 111001011110iiii 111gggnnnnnttttt E5E0 E000 + // ST1D {.Q }, , [{, #, MUL VL}] SVE_JN_3C_D 111001011100iiii 111gggnnnnnttttt E5C0 E000 + + +// enum name info SVE_CE_2A SVE_CE_2B SVE_CE_2C SVE_CE_2D SVE_CF_2A SVE_CF_2B SVE_CF_2C SVE_CF_2D +INST8(pmov, "pmov", 0, IF_SVE_8A, 0x052A3800, 0x05A83800, 0x052C3800, 0x05683800, 0x052B3800, 0x05A93800, 0x052D3800, 0x05693800 ) + // PMOV .B, SVE_CE_2A 0000010100101010 001110nnnnn0DDDD 052A 3800 + // PMOV .D, [] SVE_CE_2B 000001011i101ii0 001110nnnnn0DDDD 05A8 3800 + // PMOV .H, [] SVE_CE_2C 00000101001011i0 001110nnnnn0DDDD 052C 3800 + // PMOV .S, [] SVE_CE_2D 0000010101101ii0 001110nnnnn0DDDD 0568 3800 + // PMOV , .B SVE_CF_2A 0000010100101011 0011100NNNNddddd 052B 3800 + // PMOV [], .D SVE_CF_2B 000001011i101ii1 0011100NNNNddddd 05A9 3800 + // PMOV [], .H SVE_CF_2C 00000101001011i1 0011100NNNNddddd 052D 3800 + // PMOV [], .S SVE_CF_2D 0000010101101ii1 0011100NNNNddddd 0569 3800 + + +// enum name info SVE_HW_4A SVE_HW_4A_A SVE_HW_4A_B SVE_HW_4A_C SVE_HW_4B SVE_HW_4B_D SVE_HX_3A_E SVE_IG_4A_F +INST8(ldff1sh, "ldff1sh", 0, IF_SVE_8B, 0x84A02000, 0xC4A02000, 0xC4802000, 0x84802000, 0xC4E0A000, 0xC4C0A000, 0x84A0A000, 0xA5006000 ) + // LDFF1SH {.S }, /Z, [, .S, #1] SVE_HW_4A 100001001h1mmmmm 001gggnnnnnttttt 84A0 2000 + // LDFF1SH {.D }, /Z, [, .D, #1] SVE_HW_4A_A 110001001h1mmmmm 001gggnnnnnttttt C4A0 2000 + // LDFF1SH {.D }, /Z, [, .D, ] SVE_HW_4A_B 110001001h0mmmmm 001gggnnnnnttttt C480 2000 + // LDFF1SH {.S }, /Z, [, .S, ] SVE_HW_4A_C 100001001h0mmmmm 001gggnnnnnttttt 8480 2000 + // LDFF1SH {.D }, /Z, [, .D, LSL #1] SVE_HW_4B 11000100111mmmmm 101gggnnnnnttttt C4E0 A000 + // LDFF1SH {.D }, /Z, [, .D] SVE_HW_4B_D 11000100110mmmmm 101gggnnnnnttttt C4C0 A000 + // LDFF1SH {.D }, /Z, [.D{, #}] SVE_HX_3A_E 10000100101iiiii 101gggnnnnnttttt 84A0 A000 + // LDFF1SH {.D }, /Z, [{, , LSL #1}] SVE_IG_4A_F 10100101000mmmmm 011gggnnnnnttttt A500 6000 + +INST8(ldff1w, "ldff1w", 0, IF_SVE_8B, 0x85206000, 0xC5206000, 0xC5006000, 0x85006000, 0xC560E000, 0xC540E000, 0x8520E000, 0xA5406000 ) + // LDFF1W {.S }, /Z, [, .S, #2] SVE_HW_4A 100001010h1mmmmm 011gggnnnnnttttt 8520 6000 + // LDFF1W {.D }, /Z, [, .D, #2] SVE_HW_4A_A 110001010h1mmmmm 011gggnnnnnttttt C520 6000 + // LDFF1W {.D }, /Z, [, .D, ] SVE_HW_4A_B 110001010h0mmmmm 011gggnnnnnttttt C500 6000 + // LDFF1W {.S }, /Z, [, .S, ] SVE_HW_4A_C 100001010h0mmmmm 011gggnnnnnttttt 8500 6000 + // LDFF1W {.D }, /Z, [, .D, LSL #2] SVE_HW_4B 11000101011mmmmm 111gggnnnnnttttt C560 E000 + // LDFF1W {.D }, /Z, [, .D] SVE_HW_4B_D 11000101010mmmmm 111gggnnnnnttttt C540 E000 + // LDFF1W {.D }, /Z, [.D{, #}] SVE_HX_3A_E 10000101001iiiii 111gggnnnnnttttt 8520 E000 + // LDFF1W {.D }, /Z, [{, , LSL #2}] SVE_IG_4A_F 10100101010mmmmm 011gggnnnnnttttt A540 6000 + + +// enum name info SVE_HW_4A SVE_HW_4A_A SVE_HW_4A_B SVE_HW_4A_C SVE_HW_4B SVE_HW_4B_D SVE_HX_3A_E SVE_IG_4A_G +INST8(ldff1h, "ldff1h", 0, IF_SVE_8C, 0x84A06000, 0xC4A06000, 0xC4806000, 0x84806000, 0xC4E0E000, 0xC4C0E000, 0x84A0E000, 0xA4806000 ) + // LDFF1H {.S }, /Z, [, .S, #1] SVE_HW_4A 100001001h1mmmmm 011gggnnnnnttttt 84A0 6000 + // LDFF1H {.D }, /Z, [, .D, #1] SVE_HW_4A_A 110001001h1mmmmm 011gggnnnnnttttt C4A0 6000 + // LDFF1H {.D }, /Z, [, .D, ] SVE_HW_4A_B 110001001h0mmmmm 011gggnnnnnttttt C480 6000 + // LDFF1H {.S }, /Z, [, .S, ] SVE_HW_4A_C 100001001h0mmmmm 011gggnnnnnttttt 8480 6000 + // LDFF1H {.D }, /Z, [, .D, LSL #1] SVE_HW_4B 11000100111mmmmm 111gggnnnnnttttt C4E0 E000 + // LDFF1H {.D }, /Z, [, .D] SVE_HW_4B_D 11000100110mmmmm 111gggnnnnnttttt C4C0 E000 + // LDFF1H {.D }, /Z, [.D{, #}] SVE_HX_3A_E 10000100101iiiii 111gggnnnnnttttt 84A0 E000 + // LDFF1H {.D }, /Z, [{, , LSL #1}] SVE_IG_4A_G 10100100100mmmmm 011gggnnnnnttttt A480 6000 + + +// enum name info SVE_IJ_3A SVE_IK_4A SVE_IU_4A SVE_IU_4A_A SVE_IU_4B SVE_IU_4B_B SVE_IV_3A +INST7(ld1sw, "ld1sw", 0, IF_SVE_7A, 0xA480A000, 0xA4804000, 0xC5200000, 0xC5000000, 0xC5608000, 0xC5408000, 0xC5208000 ) + // LD1SW {.D }, /Z, [{, #, MUL VL}] SVE_IJ_3A 101001001000iiii 101gggnnnnnttttt A480 A000 + // LD1SW {.D }, /Z, [, , LSL #2] SVE_IK_4A 10100100100mmmmm 010gggnnnnnttttt A480 4000 + // LD1SW {.D }, /Z, [, .D, #2] SVE_IU_4A 110001010h1mmmmm 000gggnnnnnttttt C520 0000 + // LD1SW {.D }, /Z, [, .D, ] SVE_IU_4A_A 110001010h0mmmmm 000gggnnnnnttttt C500 0000 + // LD1SW {.D }, /Z, [, .D, LSL #2] SVE_IU_4B 11000101011mmmmm 100gggnnnnnttttt C560 8000 + // LD1SW {.D }, /Z, [, .D] SVE_IU_4B_B 11000101010mmmmm 100gggnnnnnttttt C540 8000 + // LD1SW {.D }, /Z, [.D{, #}] SVE_IV_3A 11000101001iiiii 100gggnnnnnttttt C520 8000 + + +// enum name info SVE_AE_3A SVE_BD_3A SVE_EE_1A SVE_FD_3A SVE_FD_3B SVE_FD_3C +INST6(mul, "mul", 0, IF_SVE_6A, 0x04100000, 0x04206000, 0x2530C000, 0x4420F800, 0x44A0F800, 0x44E0F800 ) + // MUL ., /M, ., . SVE_AE_3A 00000100xx010000 000gggmmmmmddddd 0410 0000 + // MUL ., ., . SVE_BD_3A 00000100xx1mmmmm 011000nnnnnddddd 0420 6000 + // MUL ., ., # SVE_EE_1A 00100101xx110000 110iiiiiiiiddddd 2530 C000 + // MUL .H, .H, .H[] SVE_FD_3A 010001000i1iimmm 111110nnnnnddddd 4420 F800 + // MUL .S, .S, .S[] SVE_FD_3B 01000100101iimmm 111110nnnnnddddd 44A0 F800 + // MUL .D, .D, .D[] SVE_FD_3C 01000100111immmm 111110nnnnnddddd 44E0 F800 + + +// enum name info SVE_GY_3A SVE_GY_3B SVE_GY_3B_D SVE_HA_3A SVE_HA_3A_E SVE_HA_3A_F +INST6(fdot, "fdot", 0, IF_SVE_6B, 0x64204400, 0x64204000, 0x64604400, 0x64208000, 0x64208400, 0x64608400 ) + // FDOT .H, .B, .B[] SVE_GY_3A 01100100001iimmm 0100i1nnnnnddddd 6420 4400 + // FDOT .S, .H, .H[] SVE_GY_3B 01100100001iimmm 010000nnnnnddddd 6420 4000 + // FDOT .S, .B, .B[] SVE_GY_3B_D 01100100011iimmm 010001nnnnnddddd 6460 4400 + // FDOT .S, .H, .H SVE_HA_3A 01100100001mmmmm 100000nnnnnddddd 6420 8000 + // FDOT .H, .B, .B SVE_HA_3A_E 01100100001mmmmm 100001nnnnnddddd 6420 8400 + // FDOT .S, .B, .B SVE_HA_3A_F 01100100011mmmmm 100001nnnnnddddd 6460 8400 + + +// enum name info SVE_HW_4A SVE_HW_4A_A SVE_HW_4B SVE_HX_3A_B SVE_IJ_3A_D SVE_IK_4A_F +INST6(ld1sb, "ld1sb", 0, IF_SVE_6C, 0xC4000000, 0x84000000, 0xC4408000, 0x84208000, 0xA580A000, 0xA5804000 ) + // LD1SB {.D }, /Z, [, .D, ] SVE_HW_4A 110001000h0mmmmm 000gggnnnnnttttt C400 0000 + // LD1SB {.S }, /Z, [, .S, ] SVE_HW_4A_A 100001000h0mmmmm 000gggnnnnnttttt 8400 0000 + // LD1SB {.D }, /Z, [, .D] SVE_HW_4B 11000100010mmmmm 100gggnnnnnttttt C440 8000 + // LD1SB {.D }, /Z, [.D{, #}] SVE_HX_3A_B 10000100001iiiii 100gggnnnnnttttt 8420 8000 + // LD1SB {.D }, /Z, [{, #, MUL VL}] SVE_IJ_3A_D 101001011000iiii 101gggnnnnnttttt A580 A000 + // LD1SB {.D }, /Z, [, ] SVE_IK_4A_F 10100101100mmmmm 010gggnnnnnttttt A580 4000 + + +// enum name info SVE_HW_4A SVE_HW_4A_A SVE_HW_4B SVE_HX_3A_B SVE_IJ_3A_E SVE_IK_4A_H +INST6(ld1b, "ld1b", 0, IF_SVE_6D, 0xC4004000, 0x84004000, 0xC440C000, 0x8420C000, 0xA400A000, 0xA4004000 ) + // LD1B {.D }, /Z, [, .D, ] SVE_HW_4A 110001000h0mmmmm 010gggnnnnnttttt C400 4000 + // LD1B {.S }, /Z, [, .S, ] SVE_HW_4A_A 100001000h0mmmmm 010gggnnnnnttttt 8400 4000 + // LD1B {.D }, /Z, [, .D] SVE_HW_4B 11000100010mmmmm 110gggnnnnnttttt C440 C000 + // LD1B {.D }, /Z, [.D{, #}] SVE_HX_3A_B 10000100001iiiii 110gggnnnnnttttt 8420 C000 + // LD1B {.D }, /Z, [{, #, MUL VL}] SVE_IJ_3A_E 101001000000iiii 101gggnnnnnttttt A400 A000 + // LD1B {.D }, /Z, [, ] SVE_IK_4A_H 10100100000mmmmm 010gggnnnnnttttt A400 4000 + + +// enum name info SVE_HY_3A SVE_HY_3A_A SVE_HY_3B SVE_HZ_2A_B SVE_IA_2A SVE_IB_3A +INST6(prfb, "prfb", 0, IF_SVE_6E, 0x84200000, 0xC4200000, 0xC4608000, 0x8400E000, 0x85C00000, 0x8400C000 ) + // PRFB , , [, .S, ] SVE_HY_3A 100001000h1mmmmm 000gggnnnnn0oooo 8420 0000 + // PRFB , , [, .D, ] SVE_HY_3A_A 110001000h1mmmmm 000gggnnnnn0oooo C420 0000 + // PRFB , , [, .D] SVE_HY_3B 11000100011mmmmm 100gggnnnnn0oooo C460 8000 + // PRFB , , [.D{, #}] SVE_HZ_2A_B 10000100000iiiii 111gggnnnnn0oooo 8400 E000 + // PRFB , , [{, #, MUL VL}] SVE_IA_2A 1000010111iiiiii 000gggnnnnn0oooo 85C0 0000 + // PRFB , , [, ] SVE_IB_3A 10000100000mmmmm 110gggnnnnn0oooo 8400 C000 + +INST6(prfd, "prfd", 0, IF_SVE_6E, 0x84206000, 0xC4206000, 0xC460E000, 0x8580E000, 0x85C06000, 0x8580C000 ) + // PRFD , , [, .S, #3] SVE_HY_3A 100001000h1mmmmm 011gggnnnnn0oooo 8420 6000 + // PRFD , , [, .D, #3] SVE_HY_3A_A 110001000h1mmmmm 011gggnnnnn0oooo C420 6000 + // PRFD , , [, .D, LSL #3] SVE_HY_3B 11000100011mmmmm 111gggnnnnn0oooo C460 E000 + // PRFD , , [.D{, #}] SVE_HZ_2A_B 10000101100iiiii 111gggnnnnn0oooo 8580 E000 + // PRFD , , [{, #, MUL VL}] SVE_IA_2A 1000010111iiiiii 011gggnnnnn0oooo 85C0 6000 + // PRFD , , [, , LSL #3] SVE_IB_3A 10000101100mmmmm 110gggnnnnn0oooo 8580 C000 + +INST6(prfh, "prfh", 0, IF_SVE_6E, 0x84202000, 0xC4202000, 0xC460A000, 0x8480E000, 0x85C02000, 0x8480C000 ) + // PRFH , , [, .S, #1] SVE_HY_3A 100001000h1mmmmm 001gggnnnnn0oooo 8420 2000 + // PRFH , , [, .D, #1] SVE_HY_3A_A 110001000h1mmmmm 001gggnnnnn0oooo C420 2000 + // PRFH , , [, .D, LSL #1] SVE_HY_3B 11000100011mmmmm 101gggnnnnn0oooo C460 A000 + // PRFH , , [.D{, #}] SVE_HZ_2A_B 10000100100iiiii 111gggnnnnn0oooo 8480 E000 + // PRFH , , [{, #, MUL VL}] SVE_IA_2A 1000010111iiiiii 001gggnnnnn0oooo 85C0 2000 + // PRFH , , [, , LSL #1] SVE_IB_3A 10000100100mmmmm 110gggnnnnn0oooo 8480 C000 + +INST6(prfw, "prfw", 0, IF_SVE_6E, 0x84204000, 0xC4204000, 0xC460C000, 0x8500E000, 0x85C04000, 0x8500C000 ) + // PRFW , , [, .S, #2] SVE_HY_3A 100001000h1mmmmm 010gggnnnnn0oooo 8420 4000 + // PRFW , , [, .D, #2] SVE_HY_3A_A 110001000h1mmmmm 010gggnnnnn0oooo C420 4000 + // PRFW , , [, .D, LSL #2] SVE_HY_3B 11000100011mmmmm 110gggnnnnn0oooo C460 C000 + // PRFW , , [.D{, #}] SVE_HZ_2A_B 10000101000iiiii 111gggnnnnn0oooo 8500 E000 + // PRFW , , [{, #, MUL VL}] SVE_IA_2A 1000010111iiiiii 010gggnnnnn0oooo 85C0 4000 + // PRFW , , [, , LSL #2] SVE_IB_3A 10000101000mmmmm 110gggnnnnn0oooo 8500 C000 + + +// enum name info SVE_IG_4A SVE_IU_4A SVE_IU_4A_A SVE_IU_4B SVE_IU_4B_B SVE_IV_3A +INST6(ldff1d, "ldff1d", 0, IF_SVE_6F, 0xA5E06000, 0xC5A06000, 0xC5806000, 0xC5E0E000, 0xC5C0E000, 0xC5A0E000 ) + // LDFF1D {.D }, /Z, [{, , LSL #3}] SVE_IG_4A 10100101111mmmmm 011gggnnnnnttttt A5E0 6000 + // LDFF1D {.D }, /Z, [, .D, #3] SVE_IU_4A 110001011h1mmmmm 011gggnnnnnttttt C5A0 6000 + // LDFF1D {.D }, /Z, [, .D, ] SVE_IU_4A_A 110001011h0mmmmm 011gggnnnnnttttt C580 6000 + // LDFF1D {.D }, /Z, [, .D, LSL #3] SVE_IU_4B 11000101111mmmmm 111gggnnnnnttttt C5E0 E000 + // LDFF1D {.D }, /Z, [, .D] SVE_IU_4B_B 11000101110mmmmm 111gggnnnnnttttt C5C0 E000 + // LDFF1D {.D }, /Z, [.D{, #}] SVE_IV_3A 11000101101iiiii 111gggnnnnnttttt C5A0 E000 + +INST6(ldff1sw, "ldff1sw", 0, IF_SVE_6F, 0xA4806000, 0xC5202000, 0xC5002000, 0xC560A000, 0xC540A000, 0xC520A000 ) + // LDFF1SW {.D }, /Z, [{, , LSL #2}] SVE_IG_4A 10100100100mmmmm 011gggnnnnnttttt A480 6000 + // LDFF1SW {.D }, /Z, [, .D, #2] SVE_IU_4A 110001010h1mmmmm 001gggnnnnnttttt C520 2000 + // LDFF1SW {.D }, /Z, [, .D, ] SVE_IU_4A_A 110001010h0mmmmm 001gggnnnnnttttt C500 2000 + // LDFF1SW {.D }, /Z, [, .D, LSL #2] SVE_IU_4B 11000101011mmmmm 101gggnnnnnttttt C560 A000 + // LDFF1SW {.D }, /Z, [, .D] SVE_IU_4B_B 11000101010mmmmm 101gggnnnnnttttt C540 A000 + // LDFF1SW {.D }, /Z, [.D{, #}] SVE_IV_3A 11000101001iiiii 101gggnnnnnttttt C520 A000 + + +// enum name info SVE_JD_4A SVE_JI_3A_A SVE_JK_4A SVE_JK_4A_B SVE_JK_4B SVE_JN_3A +INST6(st1b, "st1b", 0, IF_SVE_6G, 0xE4004000, 0xE440A000, 0xE4008000, 0xE4408000, 0xE400A000, 0xE400E000 ) + // ST1B {.}, , [, ] SVE_JD_4A 111001000xxmmmmm 010gggnnnnnttttt E400 4000 + // ST1B {.D }, , [.D{, #}] SVE_JI_3A_A 11100100010iiiii 101gggnnnnnttttt E440 A000 + // ST1B {.D }, , [, .D, ] SVE_JK_4A 11100100000mmmmm 1h0gggnnnnnttttt E400 8000 + // ST1B {.S }, , [, .S, ] SVE_JK_4A_B 11100100010mmmmm 1h0gggnnnnnttttt E440 8000 + // ST1B {.D }, , [, .D] SVE_JK_4B 11100100000mmmmm 101gggnnnnnttttt E400 A000 + // ST1B {.}, , [{, #, MUL VL}] SVE_JN_3A 111001000xx0iiii 111gggnnnnnttttt E400 E000 + + +// enum name info SVE_AM_2A SVE_AN_3A SVE_AO_3A SVE_BF_2A SVE_BG_3A +INST5(asr, "asr", 0, IF_SVE_5A, 0x04008000, 0x04108000, 0x04188000, 0x04209000, 0x04208000 ) + // ASR ., /M, ., # SVE_AM_2A 00000100xx000000 100gggxxiiiddddd 0400 8000 + // ASR ., /M, ., . SVE_AN_3A 00000100xx010000 100gggmmmmmddddd 0410 8000 + // ASR ., /M, ., .D SVE_AO_3A 00000100xx011000 100gggmmmmmddddd 0418 8000 + // ASR ., ., # SVE_BF_2A 00000100xx1xxiii 100100nnnnnddddd 0420 9000 + // ASR ., ., .D SVE_BG_3A 00000100xx1mmmmm 100000nnnnnddddd 0420 8000 + +INST5(lsl, "lsl", 0, IF_SVE_5A, 0x04038000, 0x04138000, 0x041B8000, 0x04209C00, 0x04208C00 ) + // LSL ., /M, ., # SVE_AM_2A 00000100xx000011 100gggxxiiiddddd 0403 8000 + // LSL ., /M, ., . SVE_AN_3A 00000100xx010011 100gggmmmmmddddd 0413 8000 + // LSL ., /M, ., .D SVE_AO_3A 00000100xx011011 100gggmmmmmddddd 041B 8000 + // LSL ., ., # SVE_BF_2A 00000100xx1xxiii 100111nnnnnddddd 0420 9C00 + // LSL ., ., .D SVE_BG_3A 00000100xx1mmmmm 100011nnnnnddddd 0420 8C00 + +INST5(lsr, "lsr", 0, IF_SVE_5A, 0x04018000, 0x04118000, 0x04198000, 0x04209400, 0x04208400 ) + // LSR ., /M, ., # SVE_AM_2A 00000100xx000001 100gggxxiiiddddd 0401 8000 + // LSR ., /M, ., . SVE_AN_3A 00000100xx010001 100gggmmmmmddddd 0411 8000 + // LSR ., /M, ., .D SVE_AO_3A 00000100xx011001 100gggmmmmmddddd 0419 8000 + // LSR ., ., # SVE_BF_2A 00000100xx1xxiii 100101nnnnnddddd 0420 9400 + // LSR ., ., .D SVE_BG_3A 00000100xx1mmmmm 100001nnnnnddddd 0420 8400 + + +// enum name info SVE_GX_3A SVE_GX_3B SVE_HK_3A SVE_HL_3A SVE_HM_2A +INST5(fmul, "fmul", 0, IF_SVE_5B, 0x64A02000, 0x64E02000, 0x65000800, 0x65028000, 0x651A8000 ) + // FMUL .S, .S, .S[] SVE_GX_3A 01100100101iimmm 001000nnnnnddddd 64A0 2000 + // FMUL .D, .D, .D[] SVE_GX_3B 01100100111immmm 001000nnnnnddddd 64E0 2000 + // FMUL ., ., . SVE_HK_3A 01100101xx0mmmmm 000010nnnnnddddd 6500 0800 + // FMUL ., /M, ., . SVE_HL_3A 01100101xx000010 100gggmmmmmddddd 6502 8000 + // FMUL ., /M, ., SVE_HM_2A 01100101xx011010 100ggg0000iddddd 651A 8000 + + +// enum name info SVE_EF_3A SVE_EG_3A SVE_EH_3A SVE_EY_3A SVE_EY_3B +INST5(sdot, "sdot", 0, IF_SVE_5C, 0x4400C800, 0x4480C800, 0x44000000, 0x44A00000, 0x44E00000 ) + // SDOT .S, .H, .H SVE_EF_3A 01000100000mmmmm 110010nnnnnddddd 4400 C800 + // SDOT .S, .H, .H[] SVE_EG_3A 01000100100iimmm 110010nnnnnddddd 4480 C800 + // SDOT ., ., . SVE_EH_3A 01000100xx0mmmmm 000000nnnnnddddd 4400 0000 + // SDOT .S, .B, .B[] SVE_EY_3A 01000100101iimmm 000000nnnnnddddd 44A0 0000 + // SDOT .D, .H, .H[] SVE_EY_3B 01000100111immmm 000000nnnnnddddd 44E0 0000 + +INST5(udot, "udot", 0, IF_SVE_5C, 0x4400CC00, 0x4480CC00, 0x44000400, 0x44A00400, 0x44E00400 ) + // UDOT .S, .H, .H SVE_EF_3A 01000100000mmmmm 110011nnnnnddddd 4400 CC00 + // UDOT .S, .H, .H[] SVE_EG_3A 01000100100iimmm 110011nnnnnddddd 4480 CC00 + // UDOT ., ., . SVE_EH_3A 01000100xx0mmmmm 000001nnnnnddddd 4400 0400 + // UDOT .S, .B, .B[] SVE_EY_3A 01000100101iimmm 000001nnnnnddddd 44A0 0400 + // UDOT .D, .H, .H[] SVE_EY_3B 01000100111immmm 000001nnnnnddddd 44E0 0400 + + +// enum name info SVE_HW_4A SVE_HW_4A_A SVE_HW_4B SVE_HX_3A_B SVE_IG_4A_D +INST5(ldff1sb, "ldff1sb", 0, IF_SVE_5D, 0xC4002000, 0x84002000, 0xC440A000, 0x8420A000, 0xA5806000 ) + // LDFF1SB {.D }, /Z, [, .D, ] SVE_HW_4A 110001000h0mmmmm 001gggnnnnnttttt C400 2000 + // LDFF1SB {.S }, /Z, [, .S, ] SVE_HW_4A_A 100001000h0mmmmm 001gggnnnnnttttt 8400 2000 + // LDFF1SB {.D }, /Z, [, .D] SVE_HW_4B 11000100010mmmmm 101gggnnnnnttttt C440 A000 + // LDFF1SB {.D }, /Z, [.D{, #}] SVE_HX_3A_B 10000100001iiiii 101gggnnnnnttttt 8420 A000 + // LDFF1SB {.D }, /Z, [{, }] SVE_IG_4A_D 10100101100mmmmm 011gggnnnnnttttt A580 6000 + + +// enum name info SVE_HW_4A SVE_HW_4A_A SVE_HW_4B SVE_HX_3A_B SVE_IG_4A_E +INST5(ldff1b, "ldff1b", 0, IF_SVE_5E, 0xC4006000, 0x84006000, 0xC440E000, 0x8420E000, 0xA4006000 ) + // LDFF1B {.D }, /Z, [, .D, ] SVE_HW_4A 110001000h0mmmmm 011gggnnnnnttttt C400 6000 + // LDFF1B {.S }, /Z, [, .S, ] SVE_HW_4A_A 100001000h0mmmmm 011gggnnnnnttttt 8400 6000 + // LDFF1B {.D }, /Z, [, .D] SVE_HW_4B 11000100010mmmmm 111gggnnnnnttttt C440 E000 + // LDFF1B {.D }, /Z, [.D{, #}] SVE_HX_3A_B 10000100001iiiii 111gggnnnnnttttt 8420 E000 + // LDFF1B {.D }, /Z, [{, }] SVE_IG_4A_E 10100100000mmmmm 011gggnnnnnttttt A400 6000 + + +// enum name info SVE_AA_3A SVE_AU_3A SVE_BS_1A SVE_CZ_4A +INST4(and, "and", 0, IF_SVE_4A, 0x041A0000, 0x04203000, 0x05800000, 0x25004000 ) + // AND ., /M, ., . SVE_AA_3A 00000100xx011010 000gggmmmmmddddd 041A 0000 + // AND .D, .D, .D SVE_AU_3A 00000100001mmmmm 001100nnnnnddddd 0420 3000 + // AND ., ., # SVE_BS_1A 00000101100000ii iiiiiiiiiiiddddd 0580 0000 + // AND .B, /Z, .B, .B SVE_CZ_4A 001001010000MMMM 01gggg0NNNN0DDDD 2500 4000 + +INST4(bic, "bic", 0, IF_SVE_4A, 0x041B0000, 0x04E03000, 0x05800000, 0x25004010 ) + // BIC ., /M, ., . SVE_AA_3A 00000100xx011011 000gggmmmmmddddd 041B 0000 + // BIC .D, .D, .D SVE_AU_3A 00000100111mmmmm 001100nnnnnddddd 04E0 3000 + // BIC ., ., # SVE_BS_1A 00000101100000ii iiiiiiiiiiiddddd 0580 0000 + // BIC .B, /Z, .B, .B SVE_CZ_4A 001001010000MMMM 01gggg0NNNN1DDDD 2500 4010 + +INST4(eor, "eor", 0, IF_SVE_4A, 0x04190000, 0x04A03000, 0x05400000, 0x25004200 ) + // EOR ., /M, ., . SVE_AA_3A 00000100xx011001 000gggmmmmmddddd 0419 0000 + // EOR .D, .D, .D SVE_AU_3A 00000100101mmmmm 001100nnnnnddddd 04A0 3000 + // EOR ., ., # SVE_BS_1A 00000101010000ii iiiiiiiiiiiddddd 0540 0000 + // EOR .B, /Z, .B, .B SVE_CZ_4A 001001010000MMMM 01gggg1NNNN0DDDD 2500 4200 + +INST4(orr, "orr", 0, IF_SVE_4A, 0x04180000, 0x04603000, 0x05000000, 0x25804000 ) + // ORR ., /M, ., . SVE_AA_3A 00000100xx011000 000gggmmmmmddddd 0418 0000 + // ORR .D, .D, .D SVE_AU_3A 00000100011mmmmm 001100nnnnnddddd 0460 3000 + // ORR ., ., # SVE_BS_1A 00000101000000ii iiiiiiiiiiiddddd 0500 0000 + // ORR .B, /Z, .B, .B SVE_CZ_4A 001001011000MMMM 01gggg0NNNN0DDDD 2580 4000 + + +// enum name info SVE_BU_2A SVE_BV_2B SVE_EA_1A SVE_EB_1B +INST4(fmov, "fmov", 0, IF_SVE_4B, 0x0510C000, 0x05104000, 0x2539C000, 0x2538C000 ) + // FMOV ., /M, # SVE_BU_2A 00000101xx01gggg 110iiiiiiiiddddd 0510 C000 + // FMOV ., /M, #0.0 SVE_BV_2B 00000101xx01gggg 01000000000ddddd 0510 4000 + // FMOV ., # SVE_EA_1A 00100101xx111001 110iiiiiiiiddddd 2539 C000 + // FMOV ., #0.0 SVE_EB_1B 00100101xx111000 11000000000ddddd 2538 C000 + + +// enum name info SVE_HS_3A SVE_HS_3A_H SVE_HS_3A_I SVE_HS_3A_J +INST4(scvtf, "scvtf", 0, IF_SVE_4C, 0x6594A000, 0x65D0A000, 0x65D4A000, 0x65D6A000 ) + // SCVTF .S, /M, .S SVE_HS_3A 0110010110010100 101gggnnnnnddddd 6594 A000 + // SCVTF .D, /M, .S SVE_HS_3A_H 0110010111010000 101gggnnnnnddddd 65D0 A000 + // SCVTF .S, /M, .D SVE_HS_3A_I 0110010111010100 101gggnnnnnddddd 65D4 A000 + // SCVTF .D, /M, .D SVE_HS_3A_J 0110010111010110 101gggnnnnnddddd 65D6 A000 + +INST4(ucvtf, "ucvtf", 0, IF_SVE_4C, 0x6595A000, 0x65D1A000, 0x65D5A000, 0x65D7A000 ) + // UCVTF .S, /M, .S SVE_HS_3A 0110010110010101 101gggnnnnnddddd 6595 A000 + // UCVTF .D, /M, .S SVE_HS_3A_H 0110010111010001 101gggnnnnnddddd 65D1 A000 + // UCVTF .S, /M, .D SVE_HS_3A_I 0110010111010101 101gggnnnnnddddd 65D5 A000 + // UCVTF .D, /M, .D SVE_HS_3A_J 0110010111010111 101gggnnnnnddddd 65D7 A000 + + +// enum name info SVE_HP_3B SVE_HP_3B_H SVE_HP_3B_I SVE_HP_3B_J +INST4(fcvtzs, "fcvtzs", 0, IF_SVE_4D, 0x659CA000, 0x65DCA000, 0x65D8A000, 0x65DEA000 ) + // FCVTZS .S, /M, .S SVE_HP_3B 0110010110011100 101gggnnnnnddddd 659C A000 + // FCVTZS .D, /M, .S SVE_HP_3B_H 0110010111011100 101gggnnnnnddddd 65DC A000 + // FCVTZS .S, /M, .D SVE_HP_3B_I 0110010111011000 101gggnnnnnddddd 65D8 A000 + // FCVTZS .D, /M, .D SVE_HP_3B_J 0110010111011110 101gggnnnnnddddd 65DE A000 + +INST4(fcvtzu, "fcvtzu", 0, IF_SVE_4D, 0x659DA000, 0x65DDA000, 0x65D9A000, 0x65DFA000 ) + // FCVTZU .S, /M, .S SVE_HP_3B 0110010110011101 101gggnnnnnddddd 659D A000 + // FCVTZU .D, /M, .S SVE_HP_3B_H 0110010111011101 101gggnnnnnddddd 65DD A000 + // FCVTZU .S, /M, .D SVE_HP_3B_I 0110010111011001 101gggnnnnnddddd 65D9 A000 + // FCVTZU .D, /M, .D SVE_HP_3B_J 0110010111011111 101gggnnnnnddddd 65DF A000 + + +// enum name info SVE_BE_3A SVE_FI_3A SVE_FI_3B SVE_FI_3C +INST4(sqdmulh, "sqdmulh", 0, IF_SVE_4E, 0x04207000, 0x4420F000, 0x44A0F000, 0x44E0F000 ) + // SQDMULH ., ., . SVE_BE_3A 00000100xx1mmmmm 011100nnnnnddddd 0420 7000 + // SQDMULH .H, .H, .H[] SVE_FI_3A 010001000i1iimmm 111100nnnnnddddd 4420 F000 + // SQDMULH .S, .S, .S[] SVE_FI_3B 01000100101iimmm 111100nnnnnddddd 44A0 F000 + // SQDMULH .D, .D, .D[] SVE_FI_3C 01000100111immmm 111100nnnnnddddd 44E0 F000 + +INST4(sqrdmulh, "sqrdmulh", 0, IF_SVE_4E, 0x04207400, 0x4420F400, 0x44A0F400, 0x44E0F400 ) + // SQRDMULH ., ., . SVE_BE_3A 00000100xx1mmmmm 011101nnnnnddddd 0420 7400 + // SQRDMULH .H, .H, .H[] SVE_FI_3A 010001000i1iimmm 111101nnnnnddddd 4420 F400 + // SQRDMULH .S, .S, .S[] SVE_FI_3B 01000100101iimmm 111101nnnnnddddd 44A0 F400 + // SQRDMULH .D, .D, .D[] SVE_FI_3C 01000100111immmm 111101nnnnnddddd 44E0 F400 + + +// enum name info SVE_EM_3A SVE_FK_3A SVE_FK_3B SVE_FK_3C +INST4(sqrdmlah, "sqrdmlah", 0, IF_SVE_4F, 0x44007000, 0x44201000, 0x44A01000, 0x44E01000 ) + // SQRDMLAH ., ., . SVE_EM_3A 01000100xx0mmmmm 011100nnnnnddddd 4400 7000 + // SQRDMLAH .H, .H, .H[] SVE_FK_3A 010001000i1iimmm 000100nnnnnddddd 4420 1000 + // SQRDMLAH .S, .S, .S[] SVE_FK_3B 01000100101iimmm 000100nnnnnddddd 44A0 1000 + // SQRDMLAH .D, .D, .D[] SVE_FK_3C 01000100111immmm 000100nnnnnddddd 44E0 1000 + +INST4(sqrdmlsh, "sqrdmlsh", 0, IF_SVE_4F, 0x44007400, 0x44201400, 0x44A01400, 0x44E01400 ) + // SQRDMLSH ., ., . SVE_EM_3A 01000100xx0mmmmm 011101nnnnnddddd 4400 7400 + // SQRDMLSH .H, .H, .H[] SVE_FK_3A 010001000i1iimmm 000101nnnnnddddd 4420 1400 + // SQRDMLSH .S, .S, .S[] SVE_FK_3B 01000100101iimmm 000101nnnnnddddd 44A0 1400 + // SQRDMLSH .D, .D, .D[] SVE_FK_3C 01000100111immmm 000101nnnnnddddd 44E0 1400 + + +// enum name info SVE_AR_4A SVE_FF_3A SVE_FF_3B SVE_FF_3C +INST4(mla, "mla", 0, IF_SVE_4G, 0x04004000, 0x44200800, 0x44A00800, 0x44E00800 ) + // MLA ., /M, ., . SVE_AR_4A 00000100xx0mmmmm 010gggnnnnnddddd 0400 4000 + // MLA .H, .H, .H[] SVE_FF_3A 010001000i1iimmm 000010nnnnnddddd 4420 0800 + // MLA .S, .S, .S[] SVE_FF_3B 01000100101iimmm 000010nnnnnddddd 44A0 0800 + // MLA .D, .D, .D[] SVE_FF_3C 01000100111immmm 000010nnnnnddddd 44E0 0800 + +INST4(mls, "mls", 0, IF_SVE_4G, 0x04006000, 0x44200C00, 0x44A00C00, 0x44E00C00 ) + // MLS ., /M, ., . SVE_AR_4A 00000100xx0mmmmm 011gggnnnnnddddd 0400 6000 + // MLS .H, .H, .H[] SVE_FF_3A 010001000i1iimmm 000011nnnnnddddd 4420 0C00 + // MLS .S, .S, .S[] SVE_FF_3B 01000100101iimmm 000011nnnnnddddd 44A0 0C00 + // MLS .D, .D, .D[] SVE_FF_3C 01000100111immmm 000011nnnnnddddd 44E0 0C00 + + +// enum name info SVE_GM_3A SVE_GN_3A SVE_GZ_3A SVE_HB_3A +INST4(fmlalb, "fmlalb", 0, IF_SVE_4H, 0x64205000, 0x64A08800, 0x64A04000, 0x64A08000 ) + // FMLALB .H, .B, .B[] SVE_GM_3A 01100100001iimmm 0101iinnnnnddddd 6420 5000 + // FMLALB .H, .B, .B SVE_GN_3A 01100100101mmmmm 100010nnnnnddddd 64A0 8800 + // FMLALB .S, .H, .H[] SVE_GZ_3A 01100100101iimmm 0100i0nnnnnddddd 64A0 4000 + // FMLALB .S, .H, .H SVE_HB_3A 01100100101mmmmm 100000nnnnnddddd 64A0 8000 + +INST4(fmlalt, "fmlalt", 0, IF_SVE_4H, 0x64A05000, 0x64A09800, 0x64A04400, 0x64A08400 ) + // FMLALT .H, .B, .B[] SVE_GM_3A 01100100101iimmm 0101iinnnnnddddd 64A0 5000 + // FMLALT .H, .B, .B SVE_GN_3A 01100100101mmmmm 100110nnnnnddddd 64A0 9800 + // FMLALT .S, .H, .H[] SVE_GZ_3A 01100100101iimmm 0100i1nnnnnddddd 64A0 4400 + // FMLALT .S, .H, .H SVE_HB_3A 01100100101mmmmm 100001nnnnnddddd 64A0 8400 + + +// enum name info SVE_AX_1A SVE_AY_2A SVE_AZ_2A SVE_BA_3A +INST4(index, "index", 0, IF_SVE_4I, 0x04204000, 0x04204800, 0x04204400, 0x04204C00 ) + // INDEX ., #, # SVE_AX_1A 00000100xx1iiiii 010000iiiiiddddd 0420 4000 + // INDEX ., #, SVE_AY_2A 00000100xx1mmmmm 010010iiiiiddddd 0420 4800 + // INDEX ., , # SVE_AZ_2A 00000100xx1iiiii 010001nnnnnddddd 0420 4400 + // INDEX ., , SVE_BA_3A 00000100xx1mmmmm 010011nnnnnddddd 0420 4C00 + + +// enum name info SVE_BV_2A SVE_BV_2A_A SVE_CP_3A SVE_CQ_3A +INST4(cpy, "cpy", 0, IF_SVE_4J, 0x05100000, 0x05104000, 0x05208000, 0x0528A000 ) + // CPY ., /Z, #{, } SVE_BV_2A 00000101xx01gggg 00hiiiiiiiiddddd 0510 0000 + // CPY ., /M, #{, } SVE_BV_2A_A 00000101xx01gggg 01hiiiiiiiiddddd 0510 4000 + // CPY ., /M, SVE_CP_3A 00000101xx100000 100gggnnnnnddddd 0520 8000 + // CPY ., /M, SVE_CQ_3A 00000101xx101000 101gggnnnnnddddd 0528 A000 + + +// enum name info SVE_IF_4A SVE_IF_4A_A SVE_IM_3A SVE_IN_4A +INST4(ldnt1b, "ldnt1b", 0, IF_SVE_4K, 0x8400A000, 0xC400C000, 0xA400E000, 0xA400C000 ) + // LDNT1B {.S }, /Z, [.S{, }] SVE_IF_4A 10000100000mmmmm 101gggnnnnnttttt 8400 A000 + // LDNT1B {.D }, /Z, [.D{, }] SVE_IF_4A_A 11000100000mmmmm 110gggnnnnnttttt C400 C000 + // LDNT1B {.B }, /Z, [{, #, MUL VL}] SVE_IM_3A 101001000000iiii 111gggnnnnnttttt A400 E000 + // LDNT1B {.B }, /Z, [, ] SVE_IN_4A 10100100000mmmmm 110gggnnnnnttttt A400 C000 + +INST4(ldnt1h, "ldnt1h", 0, IF_SVE_4K, 0x8480A000, 0xC480C000, 0xA480E000, 0xA480C000 ) + // LDNT1H {.S }, /Z, [.S{, }] SVE_IF_4A 10000100100mmmmm 101gggnnnnnttttt 8480 A000 + // LDNT1H {.D }, /Z, [.D{, }] SVE_IF_4A_A 11000100100mmmmm 110gggnnnnnttttt C480 C000 + // LDNT1H {.H }, /Z, [{, #, MUL VL}] SVE_IM_3A 101001001000iiii 111gggnnnnnttttt A480 E000 + // LDNT1H {.H }, /Z, [, , LSL #1] SVE_IN_4A 10100100100mmmmm 110gggnnnnnttttt A480 C000 + +INST4(ldnt1w, "ldnt1w", 0, IF_SVE_4K, 0x8500A000, 0xC500C000, 0xA500E000, 0xA500C000 ) + // LDNT1W {.S }, /Z, [.S{, }] SVE_IF_4A 10000101000mmmmm 101gggnnnnnttttt 8500 A000 + // LDNT1W {.D }, /Z, [.D{, }] SVE_IF_4A_A 11000101000mmmmm 110gggnnnnnttttt C500 C000 + // LDNT1W {.S }, /Z, [{, #, MUL VL}] SVE_IM_3A 101001010000iiii 111gggnnnnnttttt A500 E000 + // LDNT1W {.S }, /Z, [, , LSL #2] SVE_IN_4A 10100101000mmmmm 110gggnnnnnttttt A500 C000 + + +// enum name info SVE_IZ_4A SVE_IZ_4A_A SVE_JB_4A SVE_JM_3A +INST4(stnt1b, "stnt1b", 0, IF_SVE_4L, 0xE4402000, 0xE4002000, 0xE4006000, 0xE410E000 ) + // STNT1B {.S }, , [.S{, }] SVE_IZ_4A 11100100010mmmmm 001gggnnnnnttttt E440 2000 + // STNT1B {.D }, , [.D{, }] SVE_IZ_4A_A 11100100000mmmmm 001gggnnnnnttttt E400 2000 + // STNT1B {.B }, , [, ] SVE_JB_4A 11100100000mmmmm 011gggnnnnnttttt E400 6000 + // STNT1B {.B }, , [{, #, MUL VL}] SVE_JM_3A 111001000001iiii 111gggnnnnnttttt E410 E000 + +INST4(stnt1h, "stnt1h", 0, IF_SVE_4L, 0xE4C02000, 0xE4802000, 0xE4806000, 0xE490E000 ) + // STNT1H {.S }, , [.S{, }] SVE_IZ_4A 11100100110mmmmm 001gggnnnnnttttt E4C0 2000 + // STNT1H {.D }, , [.D{, }] SVE_IZ_4A_A 11100100100mmmmm 001gggnnnnnttttt E480 2000 + // STNT1H {.H }, , [, , LSL #1] SVE_JB_4A 11100100100mmmmm 011gggnnnnnttttt E480 6000 + // STNT1H {.H }, , [{, #, MUL VL}] SVE_JM_3A 111001001001iiii 111gggnnnnnttttt E490 E000 + +INST4(stnt1w, "stnt1w", 0, IF_SVE_4L, 0xE5402000, 0xE5002000, 0xE5006000, 0xE510E000 ) + // STNT1W {.S }, , [.S{, }] SVE_IZ_4A 11100101010mmmmm 001gggnnnnnttttt E540 2000 + // STNT1W {.D }, , [.D{, }] SVE_IZ_4A_A 11100101000mmmmm 001gggnnnnnttttt E500 2000 + // STNT1W {.S }, , [, , LSL #2] SVE_JB_4A 11100101000mmmmm 011gggnnnnnttttt E500 6000 + // STNT1W {.S }, , [{, #, MUL VL}] SVE_JM_3A 111001010001iiii 111gggnnnnnttttt E510 E000 + + +// enum name info SVE_AB_3A SVE_AT_3A SVE_EC_1A +INST3(add, "add", 0, IF_SVE_3A, 0x04000000, 0x04200000, 0x2520C000 ) + // ADD ., /M, ., . SVE_AB_3A 00000100xx000000 000gggmmmmmddddd 0400 0000 + // ADD ., ., . SVE_AT_3A 00000100xx1mmmmm 000000nnnnnddddd 0420 0000 + // ADD ., ., #{, } SVE_EC_1A 00100101xx100000 11hiiiiiiiiddddd 2520 C000 + +INST3(sub, "sub", 0, IF_SVE_3A, 0x04010000, 0x04200400, 0x2521C000 ) + // SUB ., /M, ., . SVE_AB_3A 00000100xx000001 000gggmmmmmddddd 0401 0000 + // SUB ., ., . SVE_AT_3A 00000100xx1mmmmm 000001nnnnnddddd 0420 0400 + // SUB ., ., #{, } SVE_EC_1A 00100101xx100001 11hiiiiiiiiddddd 2521 C000 + + +// enum name info SVE_BH_3A SVE_BH_3B SVE_BH_3B_A +INST3(adr, "adr", 0, IF_SVE_3B, 0x04A0A000, 0x0420A000, 0x0460A000 ) + // ADR ., [., .{, }] SVE_BH_3A 000001001x1mmmmm 1010hhnnnnnddddd 04A0 A000 + // ADR .D, [.D, .D, SXTW{}] SVE_BH_3B 00000100001mmmmm 1010hhnnnnnddddd 0420 A000 + // ADR .D, [.D, .D, UXTW{}] SVE_BH_3B_A 00000100011mmmmm 1010hhnnnnnddddd 0460 A000 + + +// enum name info SVE_BW_2A SVE_CB_2A SVE_EB_1A +INST3(dup, "dup", 0, IF_SVE_3C, 0x05202000, 0x05203800, 0x2538C000 ) + // DUP ., .[] SVE_BW_2A 00000101ii1xxxxx 001000nnnnnddddd 0520 2000 + // DUP ., SVE_CB_2A 00000101xx100000 001110nnnnnddddd 0520 3800 + // DUP ., #{, } SVE_EB_1A 00100101xx111000 11hiiiiiiiiddddd 2538 C000 + + +// enum name info SVE_BR_3A SVE_BR_3B SVE_CI_3A +INST3(trn1, "trn1", 0, IF_SVE_3D, 0x05207000, 0x05A01800, 0x05205000 ) + // TRN1 ., ., . SVE_BR_3A 00000101xx1mmmmm 011100nnnnnddddd 0520 7000 + // TRN1 .Q, .Q, .Q SVE_BR_3B 00000101101mmmmm 000110nnnnnddddd 05A0 1800 + // TRN1 ., ., . SVE_CI_3A 00000101xx10MMMM 0101000NNNN0DDDD 0520 5000 + +INST3(trn2, "trn2", 0, IF_SVE_3D, 0x05207400, 0x05A01C00, 0x05205400 ) + // TRN2 ., ., . SVE_BR_3A 00000101xx1mmmmm 011101nnnnnddddd 0520 7400 + // TRN2 .Q, .Q, .Q SVE_BR_3B 00000101101mmmmm 000111nnnnnddddd 05A0 1C00 + // TRN2 ., ., . SVE_CI_3A 00000101xx10MMMM 0101010NNNN0DDDD 0520 5400 + +INST3(uzp1, "uzp1", 0, IF_SVE_3D, 0x05206800, 0x05A00800, 0x05204800 ) + // UZP1 ., ., . SVE_BR_3A 00000101xx1mmmmm 011010nnnnnddddd 0520 6800 + // UZP1 .Q, .Q, .Q SVE_BR_3B 00000101101mmmmm 000010nnnnnddddd 05A0 0800 + // UZP1 ., ., . SVE_CI_3A 00000101xx10MMMM 0100100NNNN0DDDD 0520 4800 + +INST3(uzp2, "uzp2", 0, IF_SVE_3D, 0x05206C00, 0x05A00C00, 0x05204C00 ) + // UZP2 ., ., . SVE_BR_3A 00000101xx1mmmmm 011011nnnnnddddd 0520 6C00 + // UZP2 .Q, .Q, .Q SVE_BR_3B 00000101101mmmmm 000011nnnnnddddd 05A0 0C00 + // UZP2 ., ., . SVE_CI_3A 00000101xx10MMMM 0100110NNNN0DDDD 0520 4C00 + +INST3(zip1, "zip1", 0, IF_SVE_3D, 0x05206000, 0x05A00000, 0x05204000 ) + // ZIP1 ., ., . SVE_BR_3A 00000101xx1mmmmm 011000nnnnnddddd 0520 6000 + // ZIP1 .Q, .Q, .Q SVE_BR_3B 00000101101mmmmm 000000nnnnnddddd 05A0 0000 + // ZIP1 ., ., . SVE_CI_3A 00000101xx10MMMM 0100000NNNN0DDDD 0520 4000 + +INST3(zip2, "zip2", 0, IF_SVE_3D, 0x05206400, 0x05A00400, 0x05204400 ) + // ZIP2 ., ., . SVE_BR_3A 00000101xx1mmmmm 011001nnnnnddddd 0520 6400 + // ZIP2 .Q, .Q, .Q SVE_BR_3B 00000101101mmmmm 000001nnnnnddddd 05A0 0400 + // ZIP2 ., ., . SVE_CI_3A 00000101xx10MMMM 0100010NNNN0DDDD 0520 4400 + + +// enum name info SVE_AT_3A SVE_EC_1A SVE_ET_3A +INST3(sqadd, "sqadd", 0, IF_SVE_3E, 0x04201000, 0x2524C000, 0x44188000 ) + // SQADD ., ., . SVE_AT_3A 00000100xx1mmmmm 000100nnnnnddddd 0420 1000 + // SQADD ., ., #{, } SVE_EC_1A 00100101xx100100 11hiiiiiiiiddddd 2524 C000 + // SQADD ., /M, ., . SVE_ET_3A 01000100xx011000 100gggmmmmmddddd 4418 8000 + +INST3(sqsub, "sqsub", 0, IF_SVE_3E, 0x04201800, 0x2526C000, 0x441A8000 ) + // SQSUB ., ., . SVE_AT_3A 00000100xx1mmmmm 000110nnnnnddddd 0420 1800 + // SQSUB ., ., #{, } SVE_EC_1A 00100101xx100110 11hiiiiiiiiddddd 2526 C000 + // SQSUB ., /M, ., . SVE_ET_3A 01000100xx011010 100gggmmmmmddddd 441A 8000 + +INST3(uqadd, "uqadd", 0, IF_SVE_3E, 0x04201400, 0x2525C000, 0x44198000 ) + // UQADD ., ., . SVE_AT_3A 00000100xx1mmmmm 000101nnnnnddddd 0420 1400 + // UQADD ., ., #{, } SVE_EC_1A 00100101xx100101 11hiiiiiiiiddddd 2525 C000 + // UQADD ., /M, ., . SVE_ET_3A 01000100xx011001 100gggmmmmmddddd 4419 8000 + +INST3(uqsub, "uqsub", 0, IF_SVE_3E, 0x04201C00, 0x2527C000, 0x441B8000 ) + // UQSUB ., ., . SVE_AT_3A 00000100xx1mmmmm 000111nnnnnddddd 0420 1C00 + // UQSUB ., ., #{, } SVE_EC_1A 00100101xx100111 11hiiiiiiiiddddd 2527 C000 + // UQSUB ., /M, ., . SVE_ET_3A 01000100xx011011 100gggmmmmmddddd 441B 8000 + + +// enum name info SVE_GU_3A SVE_GU_3B SVE_HU_4A +INST3(fmla, "fmla", 0, IF_SVE_3F, 0x64A00000, 0x64E00000, 0x65200000 ) + // FMLA .S, .S, .S[] SVE_GU_3A 01100100101iimmm 000000nnnnnddddd 64A0 0000 + // FMLA .D, .D, .D[] SVE_GU_3B 01100100111immmm 000000nnnnnddddd 64E0 0000 + // FMLA ., /M, ., . SVE_HU_4A 01100101xx1mmmmm 000gggnnnnnddddd 6520 0000 + +INST3(fmls, "fmls", 0, IF_SVE_3F, 0x64A00400, 0x64E00400, 0x65202000 ) + // FMLS .S, .S, .S[] SVE_GU_3A 01100100101iimmm 000001nnnnnddddd 64A0 0400 + // FMLS .D, .D, .D[] SVE_GU_3B 01100100111immmm 000001nnnnnddddd 64E0 0400 + // FMLS ., /M, ., . SVE_HU_4A 01100101xx1mmmmm 001gggnnnnnddddd 6520 2000 + + +// enum name info SVE_GH_3A SVE_GH_3B SVE_GH_3B_B +INST3(luti4, "luti4", 0, IF_SVE_3G, 0x4560A400, 0x4520B400, 0x4520BC00 ) + // LUTI4 .B, {.B }, [] SVE_GH_3A 01000101i11mmmmm 101001nnnnnddddd 4560 A400 + // LUTI4 .H, {.H, .H }, [] SVE_GH_3B 01000101ii1mmmmm 101101nnnnnddddd 4520 B400 + // LUTI4 .H, {.H }, [] SVE_GH_3B_B 01000101ii1mmmmm 101111nnnnnddddd 4520 BC00 + + +// enum name info SVE_HK_3A SVE_HL_3A SVE_HM_2A +INST3(fadd, "fadd", 0, IF_SVE_3H, 0x65000000, 0x65008000, 0x65188000 ) + // FADD ., ., . SVE_HK_3A 01100101xx0mmmmm 000000nnnnnddddd 6500 0000 + // FADD ., /M, ., . SVE_HL_3A 01100101xx000000 100gggmmmmmddddd 6500 8000 + // FADD ., /M, ., SVE_HM_2A 01100101xx011000 100ggg0000iddddd 6518 8000 + +INST3(fsub, "fsub", 0, IF_SVE_3H, 0x65000400, 0x65018000, 0x65198000 ) + // FSUB ., ., . SVE_HK_3A 01100101xx0mmmmm 000001nnnnnddddd 6500 0400 + // FSUB ., /M, ., . SVE_HL_3A 01100101xx000001 100gggmmmmmddddd 6501 8000 + // FSUB ., /M, ., SVE_HM_2A 01100101xx011001 100ggg0000iddddd 6519 8000 + + +// enum name info SVE_CM_3A SVE_CN_3A SVE_CO_3A +INST3(clasta, "clasta", 0, IF_SVE_3I, 0x05288000, 0x052A8000, 0x0530A000 ) + // CLASTA ., , ., . SVE_CM_3A 00000101xx101000 100gggmmmmmddddd 0528 8000 + // CLASTA , , , . SVE_CN_3A 00000101xx101010 100gggmmmmmddddd 052A 8000 + // CLASTA , , , . SVE_CO_3A 00000101xx110000 101gggmmmmmddddd 0530 A000 + +INST3(clastb, "clastb", 0, IF_SVE_3I, 0x05298000, 0x052B8000, 0x0531A000 ) + // CLASTB ., , ., . SVE_CM_3A 00000101xx101001 100gggmmmmmddddd 0529 8000 + // CLASTB , , , . SVE_CN_3A 00000101xx101011 100gggmmmmmddddd 052B 8000 + // CLASTB , , , . SVE_CO_3A 00000101xx110001 101gggmmmmmddddd 0531 A000 + + +// enum name info SVE_CX_4A SVE_CX_4A_A SVE_CY_3A +INST3(cmpeq, "cmpeq", 0, IF_SVE_3J, 0x2400A000, 0x24002000, 0x25008000 ) + // CMPEQ ., /Z, ., . SVE_CX_4A 00100100xx0mmmmm 101gggnnnnn0DDDD 2400 A000 + // CMPEQ ., /Z, ., .D SVE_CX_4A_A 00100100xx0mmmmm 001gggnnnnn0DDDD 2400 2000 + // CMPEQ ., /Z, ., # SVE_CY_3A 00100101xx0iiiii 100gggnnnnn0DDDD 2500 8000 + +INST3(cmpge, "cmpge", 0, IF_SVE_3J, 0x24008000, 0x24004000, 0x25000000 ) + // CMPGE ., /Z, ., . SVE_CX_4A 00100100xx0mmmmm 100gggnnnnn0DDDD 2400 8000 + // CMPGE ., /Z, ., .D SVE_CX_4A_A 00100100xx0mmmmm 010gggnnnnn0DDDD 2400 4000 + // CMPGE ., /Z, ., # SVE_CY_3A 00100101xx0iiiii 000gggnnnnn0DDDD 2500 0000 + +INST3(cmpgt, "cmpgt", 0, IF_SVE_3J, 0x24008010, 0x24004010, 0x25000010 ) + // CMPGT ., /Z, ., . SVE_CX_4A 00100100xx0mmmmm 100gggnnnnn1DDDD 2400 8010 + // CMPGT ., /Z, ., .D SVE_CX_4A_A 00100100xx0mmmmm 010gggnnnnn1DDDD 2400 4010 + // CMPGT ., /Z, ., # SVE_CY_3A 00100101xx0iiiii 000gggnnnnn1DDDD 2500 0010 + +INST3(cmple, "cmple", 0, IF_SVE_3J, 0x24008000, 0x24006010, 0x25002010 ) + // CMPLE ., /Z, ., . SVE_CX_4A 00100100xx0mmmmm 100gggnnnnn0DDDD 2400 8000 + // CMPLE ., /Z, ., .D SVE_CX_4A_A 00100100xx0mmmmm 011gggnnnnn1DDDD 2400 6010 + // CMPLE ., /Z, ., # SVE_CY_3A 00100101xx0iiiii 001gggnnnnn1DDDD 2500 2010 + +INST3(cmplt, "cmplt", 0, IF_SVE_3J, 0x24008010, 0x24006000, 0x25002000 ) + // CMPLT ., /Z, ., . SVE_CX_4A 00100100xx0mmmmm 100gggnnnnn1DDDD 2400 8010 + // CMPLT ., /Z, ., .D SVE_CX_4A_A 00100100xx0mmmmm 011gggnnnnn0DDDD 2400 6000 + // CMPLT ., /Z, ., # SVE_CY_3A 00100101xx0iiiii 001gggnnnnn0DDDD 2500 2000 + +INST3(cmpne, "cmpne", 0, IF_SVE_3J, 0x2400A010, 0x24002010, 0x25008010 ) + // CMPNE ., /Z, ., . SVE_CX_4A 00100100xx0mmmmm 101gggnnnnn1DDDD 2400 A010 + // CMPNE ., /Z, ., .D SVE_CX_4A_A 00100100xx0mmmmm 001gggnnnnn1DDDD 2400 2010 + // CMPNE ., /Z, ., # SVE_CY_3A 00100101xx0iiiii 100gggnnnnn1DDDD 2500 8010 + + +// enum name info SVE_CX_4A SVE_CX_4A_A SVE_CY_3B +INST3(cmphi, "cmphi", 0, IF_SVE_3K, 0x24000010, 0x2400C010, 0x24200010 ) + // CMPHI ., /Z, ., . SVE_CX_4A 00100100xx0mmmmm 000gggnnnnn1DDDD 2400 0010 + // CMPHI ., /Z, ., .D SVE_CX_4A_A 00100100xx0mmmmm 110gggnnnnn1DDDD 2400 C010 + // CMPHI ., /Z, ., # SVE_CY_3B 00100100xx1iiiii ii0gggnnnnn1DDDD 2420 0010 + +INST3(cmphs, "cmphs", 0, IF_SVE_3K, 0x24000000, 0x2400C000, 0x24200000 ) + // CMPHS ., /Z, ., . SVE_CX_4A 00100100xx0mmmmm 000gggnnnnn0DDDD 2400 0000 + // CMPHS ., /Z, ., .D SVE_CX_4A_A 00100100xx0mmmmm 110gggnnnnn0DDDD 2400 C000 + // CMPHS ., /Z, ., # SVE_CY_3B 00100100xx1iiiii ii0gggnnnnn0DDDD 2420 0000 + +INST3(cmplo, "cmplo", 0, IF_SVE_3K, 0x24000010, 0x2400E000, 0x24202000 ) + // CMPLO ., /Z, ., . SVE_CX_4A 00100100xx0mmmmm 000gggnnnnn1DDDD 2400 0010 + // CMPLO ., /Z, ., .D SVE_CX_4A_A 00100100xx0mmmmm 111gggnnnnn0DDDD 2400 E000 + // CMPLO ., /Z, ., # SVE_CY_3B 00100100xx1iiiii ii1gggnnnnn0DDDD 2420 2000 + +INST3(cmpls, "cmpls", 0, IF_SVE_3K, 0x24000000, 0x2400E010, 0x24202010 ) + // CMPLS ., /Z, ., . SVE_CX_4A 00100100xx0mmmmm 000gggnnnnn0DDDD 2400 0000 + // CMPLS ., /Z, ., .D SVE_CX_4A_A 00100100xx0mmmmm 111gggnnnnn1DDDD 2400 E010 + // CMPLS ., /Z, ., # SVE_CY_3B 00100100xx1iiiii ii1gggnnnnn1DDDD 2420 2010 + + +// enum name info SVE_DT_3A SVE_DX_3A SVE_DY_3A +INST3(whilege, "whilege", 0, IF_SVE_3L, 0x25200000, 0x25205010, 0x25204010 ) + // WHILEGE ., , SVE_DT_3A 00100101xx1mmmmm 000X00nnnnn0DDDD 2520 0000 + // WHILEGE {., .}, , SVE_DX_3A 00100101xx1mmmmm 010100nnnnn1DDD0 2520 5010 + // WHILEGE ., , , SVE_DY_3A 00100101xx1mmmmm 01l000nnnnn10DDD 2520 4010 + +INST3(whilegt, "whilegt", 0, IF_SVE_3L, 0x25200010, 0x25205011, 0x25204018 ) + // WHILEGT ., , SVE_DT_3A 00100101xx1mmmmm 000X00nnnnn1DDDD 2520 0010 + // WHILEGT {., .}, , SVE_DX_3A 00100101xx1mmmmm 010100nnnnn1DDD1 2520 5011 + // WHILEGT ., , , SVE_DY_3A 00100101xx1mmmmm 01l000nnnnn11DDD 2520 4018 + +INST3(whilehi, "whilehi", 0, IF_SVE_3L, 0x25200810, 0x25205811, 0x25204818 ) + // WHILEHI ., , SVE_DT_3A 00100101xx1mmmmm 000X10nnnnn1DDDD 2520 0810 + // WHILEHI {., .}, , SVE_DX_3A 00100101xx1mmmmm 010110nnnnn1DDD1 2520 5811 + // WHILEHI ., , , SVE_DY_3A 00100101xx1mmmmm 01l010nnnnn11DDD 2520 4818 + +INST3(whilehs, "whilehs", 0, IF_SVE_3L, 0x25200800, 0x25205810, 0x25204810 ) + // WHILEHS ., , SVE_DT_3A 00100101xx1mmmmm 000X10nnnnn0DDDD 2520 0800 + // WHILEHS {., .}, , SVE_DX_3A 00100101xx1mmmmm 010110nnnnn1DDD0 2520 5810 + // WHILEHS ., , , SVE_DY_3A 00100101xx1mmmmm 01l010nnnnn10DDD 2520 4810 + +INST3(whilele, "whilele", 0, IF_SVE_3L, 0x25200410, 0x25205411, 0x25204418 ) + // WHILELE ., , SVE_DT_3A 00100101xx1mmmmm 000X01nnnnn1DDDD 2520 0410 + // WHILELE {., .}, , SVE_DX_3A 00100101xx1mmmmm 010101nnnnn1DDD1 2520 5411 + // WHILELE ., , , SVE_DY_3A 00100101xx1mmmmm 01l001nnnnn11DDD 2520 4418 + +INST3(whilelo, "whilelo", 0, IF_SVE_3L, 0x25200C00, 0x25205C10, 0x25204C10 ) + // WHILELO ., , SVE_DT_3A 00100101xx1mmmmm 000X11nnnnn0DDDD 2520 0C00 + // WHILELO {., .}, , SVE_DX_3A 00100101xx1mmmmm 010111nnnnn1DDD0 2520 5C10 + // WHILELO ., , , SVE_DY_3A 00100101xx1mmmmm 01l011nnnnn10DDD 2520 4C10 + +INST3(whilels, "whilels", 0, IF_SVE_3L, 0x25200C10, 0x25205C11, 0x25204C18 ) + // WHILELS ., , SVE_DT_3A 00100101xx1mmmmm 000X11nnnnn1DDDD 2520 0C10 + // WHILELS {., .}, , SVE_DX_3A 00100101xx1mmmmm 010111nnnnn1DDD1 2520 5C11 + // WHILELS ., , , SVE_DY_3A 00100101xx1mmmmm 01l011nnnnn11DDD 2520 4C18 + +INST3(whilelt, "whilelt", 0, IF_SVE_3L, 0x25200400, 0x25205410, 0x25204410 ) + // WHILELT ., , SVE_DT_3A 00100101xx1mmmmm 000X01nnnnn0DDDD 2520 0400 + // WHILELT {., .}, , SVE_DX_3A 00100101xx1mmmmm 010101nnnnn1DDD0 2520 5410 + // WHILELT ., , , SVE_DY_3A 00100101xx1mmmmm 01l001nnnnn10DDD 2520 4410 + + +// enum name info SVE_EJ_3A SVE_FA_3A SVE_FA_3B +INST3(cdot, "cdot", 0, IF_SVE_3M, 0x44001000, 0x44A04000, 0x44E04000 ) + // CDOT ., ., ., SVE_EJ_3A 01000100xx0mmmmm 0001rrnnnnnddddd 4400 1000 + // CDOT .S, .B, .B[], SVE_FA_3A 01000100101iimmm 0100rrnnnnnddddd 44A0 4000 + // CDOT .D, .H, .H[], SVE_FA_3B 01000100111immmm 0100rrnnnnnddddd 44E0 4000 + + +// enum name info SVE_EK_3A SVE_FB_3A SVE_FB_3B +INST3(cmla, "cmla", 0, IF_SVE_3N, 0x44002000, 0x44A06000, 0x44E06000 ) + // CMLA ., ., ., SVE_EK_3A 01000100xx0mmmmm 0010rrnnnnnddddd 4400 2000 + // CMLA .H, .H, .H[], SVE_FB_3A 01000100101iimmm 0110rrnnnnnddddd 44A0 6000 + // CMLA .S, .S, .S[], SVE_FB_3B 01000100111immmm 0110rrnnnnnddddd 44E0 6000 + + +// enum name info SVE_EK_3A SVE_FC_3A SVE_FC_3B +INST3(sqrdcmlah, "sqrdcmlah", 0, IF_SVE_3O, 0x44003000, 0x44A07000, 0x44E07000 ) + // SQRDCMLAH ., ., ., SVE_EK_3A 01000100xx0mmmmm 0011rrnnnnnddddd 4400 3000 + // SQRDCMLAH .H, .H, .H[], SVE_FC_3A 01000100101iimmm 0111rrnnnnnddddd 44A0 7000 + // SQRDCMLAH .S, .S, .S[], SVE_FC_3B 01000100111immmm 0111rrnnnnnddddd 44E0 7000 + + +// enum name info SVE_EL_3A SVE_FG_3A SVE_FG_3B +INST3(smlalb, "smlalb", 0, IF_SVE_3P, 0x44004000, 0x44A08000, 0x44E08000 ) + // SMLALB ., ., . SVE_EL_3A 01000100xx0mmmmm 010000nnnnnddddd 4400 4000 + // SMLALB .S, .H, .H[] SVE_FG_3A 01000100101iimmm 1000i0nnnnnddddd 44A0 8000 + // SMLALB .D, .S, .S[] SVE_FG_3B 01000100111immmm 1000i0nnnnnddddd 44E0 8000 + +INST3(smlalt, "smlalt", 0, IF_SVE_3P, 0x44004400, 0x44A08400, 0x44E08400 ) + // SMLALT ., ., . SVE_EL_3A 01000100xx0mmmmm 010001nnnnnddddd 4400 4400 + // SMLALT .S, .H, .H[] SVE_FG_3A 01000100101iimmm 1000i1nnnnnddddd 44A0 8400 + // SMLALT .D, .S, .S[] SVE_FG_3B 01000100111immmm 1000i1nnnnnddddd 44E0 8400 + +INST3(smlslb, "smlslb", 0, IF_SVE_3P, 0x44005000, 0x44A0A000, 0x44E0A000 ) + // SMLSLB ., ., . SVE_EL_3A 01000100xx0mmmmm 010100nnnnnddddd 4400 5000 + // SMLSLB .S, .H, .H[] SVE_FG_3A 01000100101iimmm 1010i0nnnnnddddd 44A0 A000 + // SMLSLB .D, .S, .S[] SVE_FG_3B 01000100111immmm 1010i0nnnnnddddd 44E0 A000 + +INST3(smlslt, "smlslt", 0, IF_SVE_3P, 0x44005400, 0x44A0A400, 0x44E0A400 ) + // SMLSLT ., ., . SVE_EL_3A 01000100xx0mmmmm 010101nnnnnddddd 4400 5400 + // SMLSLT .S, .H, .H[] SVE_FG_3A 01000100101iimmm 1010i1nnnnnddddd 44A0 A400 + // SMLSLT .D, .S, .S[] SVE_FG_3B 01000100111immmm 1010i1nnnnnddddd 44E0 A400 + +INST3(umlalb, "umlalb", 0, IF_SVE_3P, 0x44004800, 0x44A09000, 0x44E09000 ) + // UMLALB ., ., . SVE_EL_3A 01000100xx0mmmmm 010010nnnnnddddd 4400 4800 + // UMLALB .S, .H, .H[] SVE_FG_3A 01000100101iimmm 1001i0nnnnnddddd 44A0 9000 + // UMLALB .D, .S, .S[] SVE_FG_3B 01000100111immmm 1001i0nnnnnddddd 44E0 9000 + +INST3(umlalt, "umlalt", 0, IF_SVE_3P, 0x44004C00, 0x44A09400, 0x44E09400 ) + // UMLALT ., ., . SVE_EL_3A 01000100xx0mmmmm 010011nnnnnddddd 4400 4C00 + // UMLALT .S, .H, .H[] SVE_FG_3A 01000100101iimmm 1001i1nnnnnddddd 44A0 9400 + // UMLALT .D, .S, .S[] SVE_FG_3B 01000100111immmm 1001i1nnnnnddddd 44E0 9400 + +INST3(umlslb, "umlslb", 0, IF_SVE_3P, 0x44005800, 0x44A0B000, 0x44E0B000 ) + // UMLSLB ., ., . SVE_EL_3A 01000100xx0mmmmm 010110nnnnnddddd 4400 5800 + // UMLSLB .S, .H, .H[] SVE_FG_3A 01000100101iimmm 1011i0nnnnnddddd 44A0 B000 + // UMLSLB .D, .S, .S[] SVE_FG_3B 01000100111immmm 1011i0nnnnnddddd 44E0 B000 + +INST3(umlslt, "umlslt", 0, IF_SVE_3P, 0x44005C00, 0x44A0B400, 0x44E0B400 ) + // UMLSLT ., ., . SVE_EL_3A 01000100xx0mmmmm 010111nnnnnddddd 4400 5C00 + // UMLSLT .S, .H, .H[] SVE_FG_3A 01000100101iimmm 1011i1nnnnnddddd 44A0 B400 + // UMLSLT .D, .S, .S[] SVE_FG_3B 01000100111immmm 1011i1nnnnnddddd 44E0 B400 + + +// enum name info SVE_EO_3A SVE_FJ_3A SVE_FJ_3B +INST3(sqdmlalb, "sqdmlalb", 0, IF_SVE_3Q, 0x44006000, 0x44A02000, 0x44E02000 ) + // SQDMLALB ., ., . SVE_EO_3A 01000100xx0mmmmm 011000nnnnnddddd 4400 6000 + // SQDMLALB .S, .H, .H[] SVE_FJ_3A 01000100101iimmm 0010i0nnnnnddddd 44A0 2000 + // SQDMLALB .D, .S, .S[] SVE_FJ_3B 01000100111immmm 0010i0nnnnnddddd 44E0 2000 + +INST3(sqdmlalt, "sqdmlalt", 0, IF_SVE_3Q, 0x44006400, 0x44A02400, 0x44E02400 ) + // SQDMLALT ., ., . SVE_EO_3A 01000100xx0mmmmm 011001nnnnnddddd 4400 6400 + // SQDMLALT .S, .H, .H[] SVE_FJ_3A 01000100101iimmm 0010i1nnnnnddddd 44A0 2400 + // SQDMLALT .D, .S, .S[] SVE_FJ_3B 01000100111immmm 0010i1nnnnnddddd 44E0 2400 + +INST3(sqdmlslb, "sqdmlslb", 0, IF_SVE_3Q, 0x44006800, 0x44A03000, 0x44E03000 ) + // SQDMLSLB ., ., . SVE_EO_3A 01000100xx0mmmmm 011010nnnnnddddd 4400 6800 + // SQDMLSLB .S, .H, .H[] SVE_FJ_3A 01000100101iimmm 0011i0nnnnnddddd 44A0 3000 + // SQDMLSLB .D, .S, .S[] SVE_FJ_3B 01000100111immmm 0011i0nnnnnddddd 44E0 3000 + +INST3(sqdmlslt, "sqdmlslt", 0, IF_SVE_3Q, 0x44006C00, 0x44A03400, 0x44E03400 ) + // SQDMLSLT ., ., . SVE_EO_3A 01000100xx0mmmmm 011011nnnnnddddd 4400 6C00 + // SQDMLSLT .S, .H, .H[] SVE_FJ_3A 01000100101iimmm 0011i1nnnnnddddd 44A0 3400 + // SQDMLSLT .D, .S, .S[] SVE_FJ_3B 01000100111immmm 0011i1nnnnnddddd 44E0 3400 + + +// enum name info SVE_FE_3A SVE_FE_3B SVE_FN_3A +INST3(smullb, "smullb", 0, IF_SVE_3R, 0x44A0C000, 0x44E0C000, 0x45007000 ) + // SMULLB .S, .H, .H[] SVE_FE_3A 01000100101iimmm 1100i0nnnnnddddd 44A0 C000 + // SMULLB .D, .S, .S[] SVE_FE_3B 01000100111immmm 1100i0nnnnnddddd 44E0 C000 + // SMULLB ., ., . SVE_FN_3A 01000101xx0mmmmm 011100nnnnnddddd 4500 7000 + +INST3(smullt, "smullt", 0, IF_SVE_3R, 0x44A0C400, 0x44E0C400, 0x45007400 ) + // SMULLT .S, .H, .H[] SVE_FE_3A 01000100101iimmm 1100i1nnnnnddddd 44A0 C400 + // SMULLT .D, .S, .S[] SVE_FE_3B 01000100111immmm 1100i1nnnnnddddd 44E0 C400 + // SMULLT ., ., . SVE_FN_3A 01000101xx0mmmmm 011101nnnnnddddd 4500 7400 + +INST3(umullb, "umullb", 0, IF_SVE_3R, 0x44A0D000, 0x44E0D000, 0x45007800 ) + // UMULLB .S, .H, .H[] SVE_FE_3A 01000100101iimmm 1101i0nnnnnddddd 44A0 D000 + // UMULLB .D, .S, .S[] SVE_FE_3B 01000100111immmm 1101i0nnnnnddddd 44E0 D000 + // UMULLB ., ., . SVE_FN_3A 01000101xx0mmmmm 011110nnnnnddddd 4500 7800 + +INST3(umullt, "umullt", 0, IF_SVE_3R, 0x44A0D400, 0x44E0D400, 0x45007C00 ) + // UMULLT .S, .H, .H[] SVE_FE_3A 01000100101iimmm 1101i1nnnnnddddd 44A0 D400 + // UMULLT .D, .S, .S[] SVE_FE_3B 01000100111immmm 1101i1nnnnnddddd 44E0 D400 + // UMULLT ., ., . SVE_FN_3A 01000101xx0mmmmm 011111nnnnnddddd 4500 7C00 + + +// enum name info SVE_FH_3A SVE_FH_3B SVE_FN_3A +INST3(sqdmullb, "sqdmullb", 0, IF_SVE_3S, 0x44A0E000, 0x44E0E000, 0x45006000 ) + // SQDMULLB .S, .H, .H[] SVE_FH_3A 01000100101iimmm 1110i0nnnnnddddd 44A0 E000 + // SQDMULLB .D, .S, .S[] SVE_FH_3B 01000100111immmm 1110i0nnnnnddddd 44E0 E000 + // SQDMULLB ., ., . SVE_FN_3A 01000101xx0mmmmm 011000nnnnnddddd 4500 6000 + +INST3(sqdmullt, "sqdmullt", 0, IF_SVE_3S, 0x44A0E400, 0x44E0E400, 0x45006400 ) + // SQDMULLT .S, .H, .H[] SVE_FH_3A 01000100101iimmm 1110i1nnnnnddddd 44A0 E400 + // SQDMULLT .D, .S, .S[] SVE_FH_3B 01000100111immmm 1110i1nnnnnddddd 44E0 E400 + // SQDMULLT ., ., . SVE_FN_3A 01000101xx0mmmmm 011001nnnnnddddd 4500 6400 + + +// enum name info SVE_GX_3C SVE_HK_3B SVE_HL_3B +INST3(bfmul, "bfmul", 0, IF_SVE_3T, 0x64202800, 0x65000800, 0x65028000 ) + // BFMUL .H, .H, .H[] SVE_GX_3C 011001000i1iimmm 001010nnnnnddddd 6420 2800 + // BFMUL .H, .H, .H SVE_HK_3B 01100101000mmmmm 000010nnnnnddddd 6500 0800 + // BFMUL .H, /M, .H, .H SVE_HL_3B 0110010100000010 100gggmmmmmddddd 6502 8000 + + +// enum name info SVE_IM_3A SVE_IN_4A SVE_IX_4A +INST3(ldnt1d, "ldnt1d", 0, IF_SVE_3U, 0xA580E000, 0xA580C000, 0xC580C000 ) + // LDNT1D {.D }, /Z, [{, #, MUL VL}] SVE_IM_3A 101001011000iiii 111gggnnnnnttttt A580 E000 + // LDNT1D {.D }, /Z, [, , LSL #3] SVE_IN_4A 10100101100mmmmm 110gggnnnnnttttt A580 C000 + // LDNT1D {.D }, /Z, [.D{, }] SVE_IX_4A 11000101100mmmmm 110gggnnnnnttttt C580 C000 + + +// enum name info SVE_JA_4A SVE_JB_4A SVE_JM_3A +INST3(stnt1d, "stnt1d", 0, IF_SVE_3V, 0xE5802000, 0xE5806000, 0xE590E000 ) + // STNT1D {.D }, , [.D{, }] SVE_JA_4A 11100101100mmmmm 001gggnnnnnttttt E580 2000 + // STNT1D {.D }, , [, , LSL #3] SVE_JB_4A 11100101100mmmmm 011gggnnnnnttttt E580 6000 + // STNT1D {.D }, , [{, #, MUL VL}] SVE_JM_3A 111001011001iiii 111gggnnnnnttttt E590 E000 + + +// enum name info SVE_ID_2A SVE_IE_2A +INST2(ldr, "ldr", LD, IF_SVE_2AA, 0x85800000, 0x85804000 ) + // LDR , [{, #, MUL VL}] SVE_ID_2A 1000010110iiiiii 000iiinnnnn0TTTT 8580 0000 + // LDR , [{, #, MUL VL}] SVE_IE_2A 1000010110iiiiii 010iiinnnnnttttt 8580 4000 + + +// enum name info SVE_JG_2A SVE_JH_2A +INST2(str, "str", ST, IF_SVE_2AB, 0xE5800000, 0xE5804000 ) + // STR , [{, #, MUL VL}] SVE_JG_2A 1110010110iiiiii 000iiinnnnn0TTTT E580 0000 + // STR , [{, #, MUL VL}] SVE_JH_2A 1110010110iiiiii 010iiinnnnnttttt E580 4000 + + +// enum name info SVE_AD_3A SVE_ED_1A +INST2(smax, "smax", 0, IF_SVE_2AC, 0x04080000, 0x2528C000 ) + // SMAX ., /M, ., . SVE_AD_3A 00000100xx001000 000gggmmmmmddddd 0408 0000 + // SMAX ., ., # SVE_ED_1A 00100101xx101000 110iiiiiiiiddddd 2528 C000 + +INST2(smin, "smin", 0, IF_SVE_2AC, 0x040A0000, 0x252AC000 ) + // SMIN ., /M, ., . SVE_AD_3A 00000100xx001010 000gggmmmmmddddd 040A 0000 + // SMIN ., ., # SVE_ED_1A 00100101xx101010 110iiiiiiiiddddd 252A C000 + +INST2(umax, "umax", 0, IF_SVE_2AC, 0x04090000, 0x2529C000 ) + // UMAX ., /M, ., . SVE_AD_3A 00000100xx001001 000gggmmmmmddddd 0409 0000 + // UMAX ., ., # SVE_ED_1A 00100101xx101001 110iiiiiiiiddddd 2529 C000 + +INST2(umin, "umin", 0, IF_SVE_2AC, 0x040B0000, 0x252BC000 ) + // UMIN ., /M, ., . SVE_AD_3A 00000100xx001011 000gggmmmmmddddd 040B 0000 + // UMIN ., ., # SVE_ED_1A 00100101xx101011 110iiiiiiiiddddd 252B C000 + + +// enum name info SVE_AB_3B SVE_AT_3B +INST2(addpt, "addpt", 0, IF_SVE_2AD, 0x04C40000, 0x04E00800 ) + // ADDPT .D, /M, .D, .D SVE_AB_3B 0000010011000100 000gggmmmmmddddd 04C4 0000 + // ADDPT .D, .D, .D SVE_AT_3B 00000100111mmmmm 000010nnnnnddddd 04E0 0800 + +INST2(subpt, "subpt", 0, IF_SVE_2AD, 0x04C50000, 0x04E00C00 ) + // SUBPT .D, /M, .D, .D SVE_AB_3B 0000010011000101 000gggmmmmmddddd 04C5 0000 + // SUBPT .D, .D, .D SVE_AT_3B 00000100111mmmmm 000011nnnnnddddd 04E0 0C00 + + +// enum name info SVE_CG_2A SVE_CJ_2A +INST2(rev, "rev", 0, IF_SVE_2AE, 0x05383800, 0x05344000 ) + // REV ., . SVE_CG_2A 00000101xx111000 001110nnnnnddddd 0538 3800 + // REV ., . SVE_CJ_2A 00000101xx110100 0100000NNNN0DDDD 0534 4000 + + +// enum name info SVE_AE_3A SVE_BD_3A +INST2(smulh, "smulh", 0, IF_SVE_2AF, 0x04120000, 0x04206800 ) + // SMULH ., /M, ., . SVE_AE_3A 00000100xx010010 000gggmmmmmddddd 0412 0000 + // SMULH ., ., . SVE_BD_3A 00000100xx1mmmmm 011010nnnnnddddd 0420 6800 + +INST2(umulh, "umulh", 0, IF_SVE_2AF, 0x04130000, 0x04206C00 ) + // UMULH ., /M, ., . SVE_AE_3A 00000100xx010011 000gggmmmmmddddd 0413 0000 + // UMULH ., ., . SVE_BD_3A 00000100xx1mmmmm 011011nnnnnddddd 0420 6C00 + + +// enum name info SVE_BS_1A SVE_CZ_4A +INST2(orn, "orn", 0, IF_SVE_2AG, 0x05000000, 0x25804010 ) + // ORN ., ., # SVE_BS_1A 00000101000000ii iiiiiiiiiiiddddd 0500 0000 + // ORN .B, /Z, .B, .B SVE_CZ_4A 001001011000MMMM 01gggg0NNNN1DDDD 2580 4010 + + +// enum name info SVE_BQ_2A SVE_BQ_2B +INST2(ext, "ext", 0, IF_SVE_2AH, 0x05600000, 0x05200000 ) + // EXT .B, {.B, .B }, # SVE_BQ_2A 00000101011iiiii 000iiinnnnnddddd 0560 0000 + // EXT .B, .B, .B, # SVE_BQ_2B 00000101001iiiii 000iiimmmmmddddd 0520 0000 + + +// enum name info SVE_AM_2A SVE_EU_3A +INST2(sqshl, "sqshl", 0, IF_SVE_2AI, 0x04068000, 0x44088000 ) + // SQSHL ., /M, ., # SVE_AM_2A 00000100xx000110 100gggxxiiiddddd 0406 8000 + // SQSHL ., /M, ., . SVE_EU_3A 01000100xx001000 100gggmmmmmddddd 4408 8000 + +INST2(uqshl, "uqshl", 0, IF_SVE_2AI, 0x04078000, 0x44098000 ) + // UQSHL ., /M, ., # SVE_AM_2A 00000100xx000111 100gggxxiiiddddd 0407 8000 + // UQSHL ., /M, ., . SVE_EU_3A 01000100xx001001 100gggmmmmmddddd 4409 8000 + + +// enum name info SVE_HI_3A SVE_HT_4A +INST2(fcmeq, "fcmeq", 0, IF_SVE_2AJ, 0x65122000, 0x65006000 ) + // FCMEQ ., /Z, ., #0.0 SVE_HI_3A 01100101xx010010 001gggnnnnn0DDDD 6512 2000 + // FCMEQ ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 011gggnnnnn0DDDD 6500 6000 + +INST2(fcmge, "fcmge", 0, IF_SVE_2AJ, 0x65102000, 0x65004000 ) + // FCMGE ., /Z, ., #0.0 SVE_HI_3A 01100101xx010000 001gggnnnnn0DDDD 6510 2000 + // FCMGE ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 010gggnnnnn0DDDD 6500 4000 + +INST2(fcmgt, "fcmgt", 0, IF_SVE_2AJ, 0x65102010, 0x65004010 ) + // FCMGT ., /Z, ., #0.0 SVE_HI_3A 01100101xx010000 001gggnnnnn1DDDD 6510 2010 + // FCMGT ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 010gggnnnnn1DDDD 6500 4010 + +INST2(fcmle, "fcmle", 0, IF_SVE_2AJ, 0x65112010, 0x65004000 ) + // FCMLE ., /Z, ., #0.0 SVE_HI_3A 01100101xx010001 001gggnnnnn1DDDD 6511 2010 + // FCMLE ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 010gggnnnnn0DDDD 6500 4000 + +INST2(fcmlt, "fcmlt", 0, IF_SVE_2AJ, 0x65112000, 0x65004010 ) + // FCMLT ., /Z, ., #0.0 SVE_HI_3A 01100101xx010001 001gggnnnnn0DDDD 6511 2000 + // FCMLT ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 010gggnnnnn1DDDD 6500 4010 + +INST2(fcmne, "fcmne", 0, IF_SVE_2AJ, 0x65132000, 0x65006010 ) + // FCMNE ., /Z, ., #0.0 SVE_HI_3A 01100101xx010011 001gggnnnnn0DDDD 6513 2000 + // FCMNE ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 011gggnnnnn1DDDD 6500 6010 + + +// enum name info SVE_BZ_3A SVE_BZ_3A_A +INST2(tbl, "tbl", 0, IF_SVE_2AK, 0x05203000, 0x05202800 ) + // TBL ., {.}, . SVE_BZ_3A 00000101xx1mmmmm 001100nnnnnddddd 0520 3000 + // TBL ., {., .}, . SVE_BZ_3A_A 00000101xx1mmmmm 001010nnnnnddddd 0520 2800 + + +// enum name info SVE_GG_3A SVE_GG_3B +INST2(luti2, "luti2", 0, IF_SVE_2AL, 0x4520B000, 0x4520A800 ) + // LUTI2 .B, {.B }, [] SVE_GG_3A 01000101ii1mmmmm 101100nnnnnddddd 4520 B000 + // LUTI2 .H, {.H }, [] SVE_GG_3B 01000101ii1mmmmm 101i10nnnnnddddd 4520 A800 + + +// enum name info SVE_HL_3A SVE_HM_2A +INST2(fmax, "fmax", 0, IF_SVE_2AM, 0x65068000, 0x651E8000 ) + // FMAX ., /M, ., . SVE_HL_3A 01100101xx000110 100gggmmmmmddddd 6506 8000 + // FMAX ., /M, ., SVE_HM_2A 01100101xx011110 100ggg0000iddddd 651E 8000 + +INST2(fmaxnm, "fmaxnm", 0, IF_SVE_2AM, 0x65048000, 0x651C8000 ) + // FMAXNM ., /M, ., . SVE_HL_3A 01100101xx000100 100gggmmmmmddddd 6504 8000 + // FMAXNM ., /M, ., SVE_HM_2A 01100101xx011100 100ggg0000iddddd 651C 8000 + +INST2(fmin, "fmin", 0, IF_SVE_2AM, 0x65078000, 0x651F8000 ) + // FMIN ., /M, ., . SVE_HL_3A 01100101xx000111 100gggmmmmmddddd 6507 8000 + // FMIN ., /M, ., SVE_HM_2A 01100101xx011111 100ggg0000iddddd 651F 8000 + +INST2(fminnm, "fminnm", 0, IF_SVE_2AM, 0x65058000, 0x651D8000 ) + // FMINNM ., /M, ., . SVE_HL_3A 01100101xx000101 100gggmmmmmddddd 6505 8000 + // FMINNM ., /M, ., SVE_HM_2A 01100101xx011101 100ggg0000iddddd 651D 8000 + +INST2(fsubr, "fsubr", 0, IF_SVE_2AM, 0x65038000, 0x651B8000 ) + // FSUBR ., /M, ., . SVE_HL_3A 01100101xx000011 100gggmmmmmddddd 6503 8000 + // FSUBR ., /M, ., SVE_HM_2A 01100101xx011011 100ggg0000iddddd 651B 8000 + + +// enum name info SVE_EI_3A SVE_EZ_3A +INST2(usdot, "usdot", 0, IF_SVE_2AN, 0x44807800, 0x44A01800 ) + // USDOT .S, .B, .B SVE_EI_3A 01000100100mmmmm 011110nnnnnddddd 4480 7800 + // USDOT .S, .B, .B[] SVE_EZ_3A 01000100101iimmm 000110nnnnnddddd 44A0 1800 + + +// enum name info SVE_GT_4A SVE_GV_3A +INST2(fcmla, "fcmla", 0, IF_SVE_2AO, 0x64000000, 0x64E01000 ) + // FCMLA ., /M, ., ., SVE_GT_4A 01100100xx0mmmmm 0rrgggnnnnnddddd 6400 0000 + // FCMLA .S, .S, .S[], SVE_GV_3A 01100100111immmm 0001rrnnnnnddddd 64E0 1000 + + +// enum name info SVE_GY_3B SVE_HA_3A +INST2(bfdot, "bfdot", 0, IF_SVE_2AP, 0x64604000, 0x64608000 ) + // BFDOT .S, .H, .H[] SVE_GY_3B 01100100011iimmm 010000nnnnnddddd 6460 4000 + // BFDOT .S, .H, .H SVE_HA_3A 01100100011mmmmm 100000nnnnnddddd 6460 8000 + + +// enum name info SVE_GO_3A SVE_HC_3A +INST2(fmlallbb, "fmlallbb", 0, IF_SVE_2AQ, 0x64208800, 0x6420C000 ) + // FMLALLBB .S, .B, .B SVE_GO_3A 01100100001mmmmm 100010nnnnnddddd 6420 8800 + // FMLALLBB .S, .B, .B[] SVE_HC_3A 01100100001iimmm 1100iinnnnnddddd 6420 C000 + +INST2(fmlallbt, "fmlallbt", 0, IF_SVE_2AQ, 0x64209800, 0x6460C000 ) + // FMLALLBT .S, .B, .B SVE_GO_3A 01100100001mmmmm 100110nnnnnddddd 6420 9800 + // FMLALLBT .S, .B, .B[] SVE_HC_3A 01100100011iimmm 1100iinnnnnddddd 6460 C000 + +INST2(fmlalltb, "fmlalltb", 0, IF_SVE_2AQ, 0x6420A800, 0x64A0C000 ) + // FMLALLTB .S, .B, .B SVE_GO_3A 01100100001mmmmm 101010nnnnnddddd 6420 A800 + // FMLALLTB .S, .B, .B[] SVE_HC_3A 01100100101iimmm 1100iinnnnnddddd 64A0 C000 + +INST2(fmlalltt, "fmlalltt", 0, IF_SVE_2AQ, 0x6420B800, 0x64E0C000 ) + // FMLALLTT .S, .B, .B SVE_GO_3A 01100100001mmmmm 101110nnnnnddddd 6420 B800 + // FMLALLTT .S, .B, .B[] SVE_HC_3A 01100100111iimmm 1100iinnnnnddddd 64E0 C000 + + +// enum name info SVE_AP_3A SVE_CZ_4A +INST2(not, "not", 0, IF_SVE_2AR, 0x041EA000, 0x25004200 ) + // NOT ., /M, . SVE_AP_3A 00000100xx011110 101gggnnnnnddddd 041E A000 + // NOT .B, /Z, .B SVE_CZ_4A 001001010000MMMM 01gggg1NNNN0DDDD 2500 4200 + + +// enum name info SVE_HO_3A SVE_HO_3A_B +INST2(fcvt, "fcvt", 0, IF_SVE_2AS, 0x65CBA000, 0x65CAA000 ) + // FCVT .D, /M, .S SVE_HO_3A 0110010111001011 101gggnnnnnddddd 65CB A000 + // FCVT .S, /M, .D SVE_HO_3A_B 0110010111001010 101gggnnnnnddddd 65CA A000 + + +// enum name info SVE_AB_3A SVE_EC_1A +INST2(subr, "subr", 0, IF_SVE_2AT, 0x04030000, 0x2523C000 ) + // SUBR ., /M, ., . SVE_AB_3A 00000100xx000011 000gggmmmmmddddd 0403 0000 + // SUBR ., ., #{, } SVE_EC_1A 00100101xx100011 11hiiiiiiiiddddd 2523 C000 + + +// enum name info SVE_AH_3A SVE_BI_2A +INST2(movprfx, "movprfx", 0, IF_SVE_2AU, 0x04102000, 0x0420BC00 ) + // MOVPRFX ., /, . SVE_AH_3A 00000100xx01000M 001gggnnnnnddddd 0410 2000 + // MOVPRFX , SVE_BI_2A 0000010000100000 101111nnnnnddddd 0420 BC00 + + +// enum name info SVE_BM_1A SVE_BN_1A +INST2(decd, "decd", 0, IF_SVE_2AV, 0x04F0E400, 0x04F0C400 ) + // DECD {, {, MUL #}} SVE_BM_1A 000001001111iiii 111001pppppddddd 04F0 E400 + // DECD .D{, {, MUL #}} SVE_BN_1A 000001001111iiii 110001pppppddddd 04F0 C400 + +INST2(dech, "dech", 0, IF_SVE_2AV, 0x0470E400, 0x0470C400 ) + // DECH {, {, MUL #}} SVE_BM_1A 000001000111iiii 111001pppppddddd 0470 E400 + // DECH .H{, {, MUL #}} SVE_BN_1A 000001000111iiii 110001pppppddddd 0470 C400 + +INST2(decw, "decw", 0, IF_SVE_2AV, 0x04B0E400, 0x04B0C400 ) + // DECW {, {, MUL #}} SVE_BM_1A 000001001011iiii 111001pppppddddd 04B0 E400 + // DECW .S{, {, MUL #}} SVE_BN_1A 000001001011iiii 110001pppppddddd 04B0 C400 + +INST2(incd, "incd", 0, IF_SVE_2AV, 0x04F0E000, 0x04F0C000 ) + // INCD {, {, MUL #}} SVE_BM_1A 000001001111iiii 111000pppppddddd 04F0 E000 + // INCD .D{, {, MUL #}} SVE_BN_1A 000001001111iiii 110000pppppddddd 04F0 C000 + +INST2(inch, "inch", 0, IF_SVE_2AV, 0x0470E000, 0x0470C000 ) + // INCH {, {, MUL #}} SVE_BM_1A 000001000111iiii 111000pppppddddd 0470 E000 + // INCH .H{, {, MUL #}} SVE_BN_1A 000001000111iiii 110000pppppddddd 0470 C000 + +INST2(incw, "incw", 0, IF_SVE_2AV, 0x04B0E000, 0x04B0C000 ) + // INCW {, {, MUL #}} SVE_BM_1A 000001001011iiii 111000pppppddddd 04B0 E000 + // INCW .S{, {, MUL #}} SVE_BN_1A 000001001011iiii 110000pppppddddd 04B0 C000 + + +// enum name info SVE_BO_1A SVE_BP_1A +INST2(sqdecd, "sqdecd", 0, IF_SVE_2AW, 0x04E0F800, 0x04E0C800 ) + // SQDECD , {, {, MUL #}} SVE_BO_1A 00000100111Xiiii 111110pppppddddd 04E0 F800 + // SQDECD .D{, {, MUL #}} SVE_BP_1A 000001001110iiii 110010pppppddddd 04E0 C800 + +INST2(sqdech, "sqdech", 0, IF_SVE_2AW, 0x0460F800, 0x0460C800 ) + // SQDECH , {, {, MUL #}} SVE_BO_1A 00000100011Xiiii 111110pppppddddd 0460 F800 + // SQDECH .H{, {, MUL #}} SVE_BP_1A 000001000110iiii 110010pppppddddd 0460 C800 + +INST2(sqdecw, "sqdecw", 0, IF_SVE_2AW, 0x04A0F800, 0x04A0C800 ) + // SQDECW , {, {, MUL #}} SVE_BO_1A 00000100101Xiiii 111110pppppddddd 04A0 F800 + // SQDECW .S{, {, MUL #}} SVE_BP_1A 000001001010iiii 110010pppppddddd 04A0 C800 + +INST2(sqincd, "sqincd", 0, IF_SVE_2AW, 0x04E0F000, 0x04E0C000 ) + // SQINCD , {, {, MUL #}} SVE_BO_1A 00000100111Xiiii 111100pppppddddd 04E0 F000 + // SQINCD .D{, {, MUL #}} SVE_BP_1A 000001001110iiii 110000pppppddddd 04E0 C000 + +INST2(sqinch, "sqinch", 0, IF_SVE_2AW, 0x0460F000, 0x0460C000 ) + // SQINCH , {, {, MUL #}} SVE_BO_1A 00000100011Xiiii 111100pppppddddd 0460 F000 + // SQINCH .H{, {, MUL #}} SVE_BP_1A 000001000110iiii 110000pppppddddd 0460 C000 + +INST2(sqincw, "sqincw", 0, IF_SVE_2AW, 0x04A0F000, 0x04A0C000 ) + // SQINCW , {, {, MUL #}} SVE_BO_1A 00000100101Xiiii 111100pppppddddd 04A0 F000 + // SQINCW .S{, {, MUL #}} SVE_BP_1A 000001001010iiii 110000pppppddddd 04A0 C000 + +INST2(uqdecd, "uqdecd", 0, IF_SVE_2AW, 0x04E0FC00, 0x04E0CC00 ) + // UQDECD {, {, MUL #}} SVE_BO_1A 00000100111Xiiii 111111pppppddddd 04E0 FC00 + // UQDECD .D{, {, MUL #}} SVE_BP_1A 000001001110iiii 110011pppppddddd 04E0 CC00 + +INST2(uqdech, "uqdech", 0, IF_SVE_2AW, 0x0460FC00, 0x0460CC00 ) + // UQDECH {, {, MUL #}} SVE_BO_1A 00000100011Xiiii 111111pppppddddd 0460 FC00 + // UQDECH .H{, {, MUL #}} SVE_BP_1A 000001000110iiii 110011pppppddddd 0460 CC00 + +INST2(uqdecw, "uqdecw", 0, IF_SVE_2AW, 0x04A0FC00, 0x04A0CC00 ) + // UQDECW {, {, MUL #}} SVE_BO_1A 00000100101Xiiii 111111pppppddddd 04A0 FC00 + // UQDECW .S{, {, MUL #}} SVE_BP_1A 000001001010iiii 110011pppppddddd 04A0 CC00 + +INST2(uqincd, "uqincd", 0, IF_SVE_2AW, 0x04E0F400, 0x04E0C400 ) + // UQINCD {, {, MUL #}} SVE_BO_1A 00000100111Xiiii 111101pppppddddd 04E0 F400 + // UQINCD .D{, {, MUL #}} SVE_BP_1A 000001001110iiii 110001pppppddddd 04E0 C400 + +INST2(uqinch, "uqinch", 0, IF_SVE_2AW, 0x0460F400, 0x0460C400 ) + // UQINCH {, {, MUL #}} SVE_BO_1A 00000100011Xiiii 111101pppppddddd 0460 F400 + // UQINCH .H{, {, MUL #}} SVE_BP_1A 000001000110iiii 110001pppppddddd 0460 C400 + +INST2(uqincw, "uqincw", 0, IF_SVE_2AW, 0x04A0F400, 0x04A0C400 ) + // UQINCW {, {, MUL #}} SVE_BO_1A 00000100101Xiiii 111101pppppddddd 04A0 F400 + // UQINCW .S{, {, MUL #}} SVE_BP_1A 000001001010iiii 110001pppppddddd 04A0 C400 + + +// enum name info SVE_CC_2A SVE_CD_2A +INST2(insr, "insr", 0, IF_SVE_2AX, 0x05343800, 0x05243800 ) + // INSR ., SVE_CC_2A 00000101xx110100 001110mmmmmddddd 0534 3800 + // INSR ., SVE_CD_2A 00000101xx100100 001110mmmmmddddd 0524 3800 + + +// enum name info SVE_CR_3A SVE_CS_3A +INST2(lasta, "lasta", 0, IF_SVE_2AY, 0x05228000, 0x0520A000 ) + // LASTA , , . SVE_CR_3A 00000101xx100010 100gggnnnnnddddd 0522 8000 + // LASTA , , . SVE_CS_3A 00000101xx100000 101gggnnnnnddddd 0520 A000 + +INST2(lastb, "lastb", 0, IF_SVE_2AY, 0x05238000, 0x0521A000 ) + // LASTB , , . SVE_CR_3A 00000101xx100011 100gggnnnnnddddd 0523 8000 + // LASTB , , . SVE_CS_3A 00000101xx100001 101gggnnnnnddddd 0521 A000 + + +// enum name info SVE_CV_3A SVE_CV_3B +INST2(splice, "splice", 0, IF_SVE_2AZ, 0x052D8000, 0x052C8000 ) + // SPLICE ., , {., .} SVE_CV_3A 00000101xx101101 100VVVnnnnnddddd 052D 8000 + // SPLICE ., , ., . SVE_CV_3B 00000101xx101100 100VVVmmmmmddddd 052C 8000 + + +// enum name info SVE_CW_4A SVE_CZ_4A +INST2(sel, "sel", 0, IF_SVE_2BA, 0x0520C000, 0x25004210 ) + // SEL ., , ., . SVE_CW_4A 00000101xx1mmmmm 11VVVVnnnnnddddd 0520 C000 + // SEL .B, , .B, .B SVE_CZ_4A 001001010000MMMM 01gggg1NNNN1DDDD 2500 4210 + + +// enum name info SVE_CZ_4A SVE_CZ_4A_A +INST2(movs, "movs", 0, IF_SVE_2BB, 0x25404000, 0x25C04000 ) + // MOVS .B, /Z, .B SVE_CZ_4A 001001010100MMMM 01gggg0NNNN0DDDD 2540 4000 + // MOVS .B, .B SVE_CZ_4A_A 001001011100MMMM 01gggg0NNNN0DDDD 25C0 4000 + + +// enum name info SVE_DE_1A SVE_DZ_1A +INST2(ptrue, "ptrue", 0, IF_SVE_2BC, 0x2518E000, 0x25207810 ) + // PTRUE .{, } SVE_DE_1A 00100101xx011000 111000ppppp0DDDD 2518 E000 + // PTRUE . SVE_DZ_1A 00100101xx100000 0111100000010DDD 2520 7810 + + +// enum name info SVE_DG_2A SVE_DH_1A +INST2(rdffr, "rdffr", 0, IF_SVE_2BD, 0x2518F000, 0x2519F000 ) + // RDFFR .B, /Z SVE_DG_2A 0010010100011000 1111000gggg0DDDD 2518 F000 + // RDFFR .B SVE_DH_1A 0010010100011001 111100000000DDDD 2519 F000 + + +// enum name info SVE_DK_3A SVE_DL_2A +INST2(cntp, "cntp", 0, IF_SVE_2BE, 0x25208000, 0x25208200 ) + // CNTP , , . SVE_DK_3A 00100101xx100000 10gggg0NNNNddddd 2520 8000 + // CNTP , ., SVE_DL_2A 00100101xx100000 10000l1NNNNddddd 2520 8200 + + +// enum name info SVE_DM_2A SVE_DN_2A +INST2(decp, "decp", 0, IF_SVE_2BF, 0x252D8800, 0x252D8000 ) + // DECP , . SVE_DM_2A 00100101xx101101 1000100MMMMddddd 252D 8800 + // DECP ., . SVE_DN_2A 00100101xx101101 1000000MMMMddddd 252D 8000 + +INST2(incp, "incp", 0, IF_SVE_2BF, 0x252C8800, 0x252C8000 ) + // INCP , . SVE_DM_2A 00100101xx101100 1000100MMMMddddd 252C 8800 + // INCP ., . SVE_DN_2A 00100101xx101100 1000000MMMMddddd 252C 8000 + + +// enum name info SVE_DO_2A SVE_DP_2A +INST2(sqdecp, "sqdecp", 0, IF_SVE_2BG, 0x252A8800, 0x252A8000 ) + // SQDECP , ., SVE_DO_2A 00100101xx101010 10001X0MMMMddddd 252A 8800 + // SQDECP ., . SVE_DP_2A 00100101xx101010 1000000MMMMddddd 252A 8000 + +INST2(sqincp, "sqincp", 0, IF_SVE_2BG, 0x25288800, 0x25288000 ) + // SQINCP , ., SVE_DO_2A 00100101xx101000 10001X0MMMMddddd 2528 8800 + // SQINCP ., . SVE_DP_2A 00100101xx101000 1000000MMMMddddd 2528 8000 + +INST2(uqdecp, "uqdecp", 0, IF_SVE_2BG, 0x252B8800, 0x252B8000 ) + // UQDECP , . SVE_DO_2A 00100101xx101011 10001X0MMMMddddd 252B 8800 + // UQDECP ., . SVE_DP_2A 00100101xx101011 1000000MMMMddddd 252B 8000 + +INST2(uqincp, "uqincp", 0, IF_SVE_2BG, 0x25298800, 0x25298000 ) + // UQINCP , . SVE_DO_2A 00100101xx101001 10001X0MMMMddddd 2529 8800 + // UQINCP ., . SVE_DP_2A 00100101xx101001 1000000MMMMddddd 2529 8000 + + +// enum name info SVE_DW_2A SVE_DW_2B +INST2(pext, "pext", 0, IF_SVE_2BH, 0x25207010, 0x25207410 ) + // PEXT ., [] SVE_DW_2A 00100101xx100000 011100iiNNN1DDDD 2520 7010 + // PEXT {., .}, [] SVE_DW_2B 00100101xx100000 0111010iNNN1DDDD 2520 7410 + + +// enum name info SVE_FN_3A SVE_FN_3B +INST2(pmullb, "pmullb", 0, IF_SVE_2BI, 0x45006800, 0x45006800 ) + // PMULLB ., ., . SVE_FN_3A 01000101xx0mmmmm 011010nnnnnddddd 4500 6800 + // PMULLB .Q, .D, .D SVE_FN_3B 01000101000mmmmm 011010nnnnnddddd 4500 6800 + +INST2(pmullt, "pmullt", 0, IF_SVE_2BI, 0x45006C00, 0x45006C00 ) + // PMULLT ., ., . SVE_FN_3A 01000101xx0mmmmm 011011nnnnnddddd 4500 6C00 + // PMULLT .Q, .D, .D SVE_FN_3B 01000101000mmmmm 011011nnnnnddddd 4500 6C00 + + +// enum name info SVE_GQ_3A SVE_HG_2A +INST2(fcvtnt, "fcvtnt", 0, IF_SVE_2BJ, 0x64CAA000, 0x650A3C00 ) + // FCVTNT .S, /M, .D SVE_GQ_3A 0110010011001010 101gggnnnnnddddd 64CA A000 + // FCVTNT .B, {.S-.S } SVE_HG_2A 0110010100001010 001111nnnn0ddddd 650A 3C00 + + +// enum name info SVE_GU_3C SVE_HU_4B +INST2(bfmla, "bfmla", 0, IF_SVE_2BK, 0x64200800, 0x65200000 ) + // BFMLA .H, .H, .H[] SVE_GU_3C 011001000i1iimmm 000010nnnnnddddd 6420 0800 + // BFMLA .H, /M, .H, .H SVE_HU_4B 01100101001mmmmm 000gggnnnnnddddd 6520 0000 + +INST2(bfmls, "bfmls", 0, IF_SVE_2BK, 0x64200C00, 0x65202000 ) + // BFMLS .H, .H, .H[] SVE_GU_3C 011001000i1iimmm 000011nnnnnddddd 6420 0C00 + // BFMLS .H, /M, .H, .H SVE_HU_4B 01100101001mmmmm 001gggnnnnnddddd 6520 2000 + + +// enum name info SVE_GZ_3A SVE_HB_3A +INST2(bfmlalb, "bfmlalb", 0, IF_SVE_2BL, 0x64E04000, 0x64E08000 ) + // BFMLALB .S, .H, .H[] SVE_GZ_3A 01100100111iimmm 0100i0nnnnnddddd 64E0 4000 + // BFMLALB .S, .H, .H SVE_HB_3A 01100100111mmmmm 100000nnnnnddddd 64E0 8000 + +INST2(bfmlalt, "bfmlalt", 0, IF_SVE_2BL, 0x64E04400, 0x64E08400 ) + // BFMLALT .S, .H, .H[] SVE_GZ_3A 01100100111iimmm 0100i1nnnnnddddd 64E0 4400 + // BFMLALT .S, .H, .H SVE_HB_3A 01100100111mmmmm 100001nnnnnddddd 64E0 8400 + +INST2(bfmlslb, "bfmlslb", 0, IF_SVE_2BL, 0x64E06000, 0x64E0A000 ) + // BFMLSLB .S, .H, .H[] SVE_GZ_3A 01100100111iimmm 0110i0nnnnnddddd 64E0 6000 + // BFMLSLB .S, .H, .H SVE_HB_3A 01100100111mmmmm 101000nnnnnddddd 64E0 A000 + +INST2(bfmlslt, "bfmlslt", 0, IF_SVE_2BL, 0x64E06400, 0x64E0A400 ) + // BFMLSLT .S, .H, .H[] SVE_GZ_3A 01100100111iimmm 0110i1nnnnnddddd 64E0 6400 + // BFMLSLT .S, .H, .H SVE_HB_3A 01100100111mmmmm 101001nnnnnddddd 64E0 A400 + +INST2(fmlslb, "fmlslb", 0, IF_SVE_2BL, 0x64A06000, 0x64A0A000 ) + // FMLSLB .S, .H, .H[] SVE_GZ_3A 01100100101iimmm 0110i0nnnnnddddd 64A0 6000 + // FMLSLB .S, .H, .H SVE_HB_3A 01100100101mmmmm 101000nnnnnddddd 64A0 A000 + +INST2(fmlslt, "fmlslt", 0, IF_SVE_2BL, 0x64A06400, 0x64A0A400 ) + // FMLSLT .S, .H, .H[] SVE_GZ_3A 01100100101iimmm 0110i1nnnnnddddd 64A0 6400 + // FMLSLT .S, .H, .H SVE_HB_3A 01100100101mmmmm 101001nnnnnddddd 64A0 A400 + + +// enum name info SVE_HK_3B SVE_HL_3B +INST2(bfadd, "bfadd", 0, IF_SVE_2BM, 0x65000000, 0x65008000 ) + // BFADD .H, .H, .H SVE_HK_3B 01100101000mmmmm 000000nnnnnddddd 6500 0000 + // BFADD .H, /M, .H, .H SVE_HL_3B 0110010100000000 100gggmmmmmddddd 6500 8000 + +INST2(bfsub, "bfsub", 0, IF_SVE_2BM, 0x65000400, 0x65018000 ) + // BFSUB .H, .H, .H SVE_HK_3B 01100101000mmmmm 000001nnnnnddddd 6500 0400 + // BFSUB .H, /M, .H, .H SVE_HL_3B 0110010100000001 100gggmmmmmddddd 6501 8000 + + +// enum name info SVE_IF_4A SVE_IF_4A_A +INST2(ldnt1sb, "ldnt1sb", 0, IF_SVE_2BN, 0x84008000, 0xC4008000 ) + // LDNT1SB {.S }, /Z, [.S{, }] SVE_IF_4A 10000100000mmmmm 100gggnnnnnttttt 8400 8000 + // LDNT1SB {.D }, /Z, [.D{, }] SVE_IF_4A_A 11000100000mmmmm 100gggnnnnnttttt C400 8000 + +INST2(ldnt1sh, "ldnt1sh", 0, IF_SVE_2BN, 0x84808000, 0xC4808000 ) + // LDNT1SH {.S }, /Z, [.S{, }] SVE_IF_4A 10000100100mmmmm 100gggnnnnnttttt 8480 8000 + // LDNT1SH {.D }, /Z, [.D{, }] SVE_IF_4A_A 11000100100mmmmm 100gggnnnnnttttt C480 8000 + + +// enum name info SVE_IO_3A SVE_IP_4A +INST2(ld1rob, "ld1rob", 0, IF_SVE_2BO, 0xA4202000, 0xA4200000 ) + // LD1ROB {.B }, /Z, [{, #}] SVE_IO_3A 101001000010iiii 001gggnnnnnttttt A420 2000 + // LD1ROB {.B }, /Z, [, ] SVE_IP_4A 10100100001mmmmm 000gggnnnnnttttt A420 0000 + +INST2(ld1rod, "ld1rod", 0, IF_SVE_2BO, 0xA5A02000, 0xA5A00000 ) + // LD1ROD {.D }, /Z, [{, #}] SVE_IO_3A 101001011010iiii 001gggnnnnnttttt A5A0 2000 + // LD1ROD {.D }, /Z, [, , LSL #3] SVE_IP_4A 10100101101mmmmm 000gggnnnnnttttt A5A0 0000 + +INST2(ld1roh, "ld1roh", 0, IF_SVE_2BO, 0xA4A02000, 0xA4A00000 ) + // LD1ROH {.H }, /Z, [{, #}] SVE_IO_3A 101001001010iiii 001gggnnnnnttttt A4A0 2000 + // LD1ROH {.H }, /Z, [, , LSL #1] SVE_IP_4A 10100100101mmmmm 000gggnnnnnttttt A4A0 0000 + +INST2(ld1row, "ld1row", 0, IF_SVE_2BO, 0xA5202000, 0xA5200000 ) + // LD1ROW {.S }, /Z, [{, #}] SVE_IO_3A 101001010010iiii 001gggnnnnnttttt A520 2000 + // LD1ROW {.S }, /Z, [, , LSL #2] SVE_IP_4A 10100101001mmmmm 000gggnnnnnttttt A520 0000 + +INST2(ld1rqb, "ld1rqb", 0, IF_SVE_2BO, 0xA4002000, 0xA4000000 ) + // LD1RQB {.B }, /Z, [{, #}] SVE_IO_3A 101001000000iiii 001gggnnnnnttttt A400 2000 + // LD1RQB {.B }, /Z, [, ] SVE_IP_4A 10100100000mmmmm 000gggnnnnnttttt A400 0000 + +INST2(ld1rqd, "ld1rqd", 0, IF_SVE_2BO, 0xA5802000, 0xA5800000 ) + // LD1RQD {.D }, /Z, [{, #}] SVE_IO_3A 101001011000iiii 001gggnnnnnttttt A580 2000 + // LD1RQD {.D }, /Z, [, , LSL #3] SVE_IP_4A 10100101100mmmmm 000gggnnnnnttttt A580 0000 + +INST2(ld1rqh, "ld1rqh", 0, IF_SVE_2BO, 0xA4802000, 0xA4800000 ) + // LD1RQH {.H }, /Z, [{, #}] SVE_IO_3A 101001001000iiii 001gggnnnnnttttt A480 2000 + // LD1RQH {.H }, /Z, [, , LSL #1] SVE_IP_4A 10100100100mmmmm 000gggnnnnnttttt A480 0000 + +INST2(ld1rqw, "ld1rqw", 0, IF_SVE_2BO, 0xA5002000, 0xA5000000 ) + // LD1RQW {.S }, /Z, [{, #}] SVE_IO_3A 101001010000iiii 001gggnnnnnttttt A500 2000 + // LD1RQW {.S }, /Z, [, , LSL #2] SVE_IP_4A 10100101000mmmmm 000gggnnnnnttttt A500 0000 + + +// enum name info SVE_IQ_3A SVE_IR_4A +INST2(ld2q, "ld2q", 0, IF_SVE_2BP, 0xA490E000, 0xA4A08000 ) + // LD2Q {.Q, .Q }, /Z, [{, #, MUL VL}] SVE_IQ_3A 101001001001iiii 111gggnnnnnttttt A490 E000 + // LD2Q {.Q, .Q }, /Z, [, , LSL #4] SVE_IR_4A 10100100101mmmmm 100gggnnnnnttttt A4A0 8000 + +INST2(ld3q, "ld3q", 0, IF_SVE_2BP, 0xA510E000, 0xA5208000 ) + // LD3Q {.Q, .Q, .Q }, /Z, [{, #, MUL VL}] SVE_IQ_3A 101001010001iiii 111gggnnnnnttttt A510 E000 + // LD3Q {.Q, .Q, .Q }, /Z, [, , LSL #4] SVE_IR_4A 10100101001mmmmm 100gggnnnnnttttt A520 8000 + +INST2(ld4q, "ld4q", 0, IF_SVE_2BP, 0xA590E000, 0xA5A08000 ) + // LD4Q {.Q, .Q, .Q, .Q }, /Z, [{, #, MUL VL}]SVE_IQ_3A 101001011001iiii 111gggnnnnnttttt A590 E000 + // LD4Q {.Q, .Q, .Q, .Q }, /Z, [, , LSL #4] SVE_IR_4A 10100101101mmmmm 100gggnnnnnttttt A5A0 8000 + + +// enum name info SVE_IS_3A SVE_IT_4A +INST2(ld2b, "ld2b", 0, IF_SVE_2BQ, 0xA420E000, 0xA420C000 ) + // LD2B {.B, .B }, /Z, [{, #, MUL VL}] SVE_IS_3A 101001000010iiii 111gggnnnnnttttt A420 E000 + // LD2B {.B, .B }, /Z, [, ] SVE_IT_4A 10100100001mmmmm 110gggnnnnnttttt A420 C000 + +INST2(ld2d, "ld2d", 0, IF_SVE_2BQ, 0xA5A0E000, 0xA5A0C000 ) + // LD2D {.D, .D }, /Z, [{, #, MUL VL}] SVE_IS_3A 101001011010iiii 111gggnnnnnttttt A5A0 E000 + // LD2D {.D, .D }, /Z, [, , LSL #3] SVE_IT_4A 10100101101mmmmm 110gggnnnnnttttt A5A0 C000 + +INST2(ld2h, "ld2h", 0, IF_SVE_2BQ, 0xA4A0E000, 0xA4A0C000 ) + // LD2H {.H, .H }, /Z, [{, #, MUL VL}] SVE_IS_3A 101001001010iiii 111gggnnnnnttttt A4A0 E000 + // LD2H {.H, .H }, /Z, [, , LSL #1] SVE_IT_4A 10100100101mmmmm 110gggnnnnnttttt A4A0 C000 + +INST2(ld2w, "ld2w", 0, IF_SVE_2BQ, 0xA520E000, 0xA520C000 ) + // LD2W {.S, .S }, /Z, [{, #, MUL VL}] SVE_IS_3A 101001010010iiii 111gggnnnnnttttt A520 E000 + // LD2W {.S, .S }, /Z, [, , LSL #2] SVE_IT_4A 10100101001mmmmm 110gggnnnnnttttt A520 C000 + +INST2(ld3b, "ld3b", 0, IF_SVE_2BQ, 0xA440E000, 0xA440C000 ) + // LD3B {.B, .B, .B }, /Z, [{, #, MUL VL}] SVE_IS_3A 101001000100iiii 111gggnnnnnttttt A440 E000 + // LD3B {.B, .B, .B }, /Z, [, ] SVE_IT_4A 10100100010mmmmm 110gggnnnnnttttt A440 C000 + +INST2(ld3d, "ld3d", 0, IF_SVE_2BQ, 0xA5C0E000, 0xA5C0C000 ) + // LD3D {.D, .D, .D }, /Z, [{, #, MUL VL}] SVE_IS_3A 101001011100iiii 111gggnnnnnttttt A5C0 E000 + // LD3D {.D, .D, .D }, /Z, [, , LSL #3] SVE_IT_4A 10100101110mmmmm 110gggnnnnnttttt A5C0 C000 + +INST2(ld3h, "ld3h", 0, IF_SVE_2BQ, 0xA4C0E000, 0xA4C0C000 ) + // LD3H {.H, .H, .H }, /Z, [{, #, MUL VL}] SVE_IS_3A 101001001100iiii 111gggnnnnnttttt A4C0 E000 + // LD3H {.H, .H, .H }, /Z, [, , LSL #1] SVE_IT_4A 10100100110mmmmm 110gggnnnnnttttt A4C0 C000 + +INST2(ld3w, "ld3w", 0, IF_SVE_2BQ, 0xA540E000, 0xA540C000 ) + // LD3W {.S, .S, .S }, /Z, [{, #, MUL VL}] SVE_IS_3A 101001010100iiii 111gggnnnnnttttt A540 E000 + // LD3W {.S, .S, .S }, /Z, [, , LSL #2] SVE_IT_4A 10100101010mmmmm 110gggnnnnnttttt A540 C000 + +INST2(ld4b, "ld4b", 0, IF_SVE_2BQ, 0xA460E000, 0xA460C000 ) + // LD4B {.B, .B, .B, .B }, /Z, [{, #, MUL VL}]SVE_IS_3A 101001000110iiii 111gggnnnnnttttt A460 E000 + // LD4B {.B, .B, .B, .B }, /Z, [, ] SVE_IT_4A 10100100011mmmmm 110gggnnnnnttttt A460 C000 + +INST2(ld4d, "ld4d", 0, IF_SVE_2BQ, 0xA5E0E000, 0xA5E0C000 ) + // LD4D {.D, .D, .D, .D }, /Z, [{, #, MUL VL}]SVE_IS_3A 101001011110iiii 111gggnnnnnttttt A5E0 E000 + // LD4D {.D, .D, .D, .D }, /Z, [, , LSL #3] SVE_IT_4A 10100101111mmmmm 110gggnnnnnttttt A5E0 C000 + +INST2(ld4h, "ld4h", 0, IF_SVE_2BQ, 0xA4E0E000, 0xA4E0C000 ) + // LD4H {.H, .H, .H, .H }, /Z, [{, #, MUL VL}]SVE_IS_3A 101001001110iiii 111gggnnnnnttttt A4E0 E000 + // LD4H {.H, .H, .H, .H }, /Z, [, , LSL #1] SVE_IT_4A 10100100111mmmmm 110gggnnnnnttttt A4E0 C000 + +INST2(ld4w, "ld4w", 0, IF_SVE_2BQ, 0xA560E000, 0xA560C000 ) + // LD4W {.S, .S, .S, .S }, /Z, [{, #, MUL VL}]SVE_IS_3A 101001010110iiii 111gggnnnnnttttt A560 E000 + // LD4W {.S, .S, .S, .S }, /Z, [, , LSL #2] SVE_IT_4A 10100101011mmmmm 110gggnnnnnttttt A560 C000 + + +// enum name info SVE_JC_4A SVE_JO_3A +INST2(st2b, "st2b", 0, IF_SVE_2BR, 0xE4206000, 0xE430E000 ) + // ST2B {.B, .B }, , [, ] SVE_JC_4A 11100100001mmmmm 011gggnnnnnttttt E420 6000 + // ST2B {.B, .B }, , [{, #, MUL VL}] SVE_JO_3A 111001000011iiii 111gggnnnnnttttt E430 E000 + +INST2(st2d, "st2d", 0, IF_SVE_2BR, 0xE5A06000, 0xE5B0E000 ) + // ST2D {.D, .D }, , [, , LSL #3] SVE_JC_4A 11100101101mmmmm 011gggnnnnnttttt E5A0 6000 + // ST2D {.D, .D }, , [{, #, MUL VL}] SVE_JO_3A 111001011011iiii 111gggnnnnnttttt E5B0 E000 + +INST2(st2h, "st2h", 0, IF_SVE_2BR, 0xE4A06000, 0xE4B0E000 ) + // ST2H {.H, .H }, , [, , LSL #1] SVE_JC_4A 11100100101mmmmm 011gggnnnnnttttt E4A0 6000 + // ST2H {.H, .H }, , [{, #, MUL VL}] SVE_JO_3A 111001001011iiii 111gggnnnnnttttt E4B0 E000 + +INST2(st2w, "st2w", 0, IF_SVE_2BR, 0xE5206000, 0xE530E000 ) + // ST2W {.S, .S }, , [, , LSL #2] SVE_JC_4A 11100101001mmmmm 011gggnnnnnttttt E520 6000 + // ST2W {.S, .S }, , [{, #, MUL VL}] SVE_JO_3A 111001010011iiii 111gggnnnnnttttt E530 E000 + +INST2(st3b, "st3b", 0, IF_SVE_2BR, 0xE4406000, 0xE450E000 ) + // ST3B {.B, .B, .B }, , [, ] SVE_JC_4A 11100100010mmmmm 011gggnnnnnttttt E440 6000 + // ST3B {.B, .B, .B }, , [{, #, MUL VL}] SVE_JO_3A 111001000101iiii 111gggnnnnnttttt E450 E000 + +INST2(st3d, "st3d", 0, IF_SVE_2BR, 0xE5C06000, 0xE5D0E000 ) + // ST3D {.D, .D, .D }, , [, , LSL #3] SVE_JC_4A 11100101110mmmmm 011gggnnnnnttttt E5C0 6000 + // ST3D {.D, .D, .D }, , [{, #, MUL VL}] SVE_JO_3A 111001011101iiii 111gggnnnnnttttt E5D0 E000 + +INST2(st3h, "st3h", 0, IF_SVE_2BR, 0xE4C06000, 0xE4D0E000 ) + // ST3H {.H, .H, .H }, , [, , LSL #1] SVE_JC_4A 11100100110mmmmm 011gggnnnnnttttt E4C0 6000 + // ST3H {.H, .H, .H }, , [{, #, MUL VL}] SVE_JO_3A 111001001101iiii 111gggnnnnnttttt E4D0 E000 + +INST2(st3w, "st3w", 0, IF_SVE_2BR, 0xE5406000, 0xE550E000 ) + // ST3W {.S, .S, .S }, , [, , LSL #2] SVE_JC_4A 11100101010mmmmm 011gggnnnnnttttt E540 6000 + // ST3W {.S, .S, .S }, , [{, #, MUL VL}] SVE_JO_3A 111001010101iiii 111gggnnnnnttttt E550 E000 + +INST2(st4b, "st4b", 0, IF_SVE_2BR, 0xE4606000, 0xE470E000 ) + // ST4B {.B, .B, .B, .B }, , [, ] SVE_JC_4A 11100100011mmmmm 011gggnnnnnttttt E460 6000 + // ST4B {.B, .B, .B, .B }, , [{, #, MUL VL}] SVE_JO_3A 111001000111iiii 111gggnnnnnttttt E470 E000 + +INST2(st4d, "st4d", 0, IF_SVE_2BR, 0xE5E06000, 0xE5F0E000 ) + // ST4D {.D, .D, .D, .D }, , [, , LSL #3] SVE_JC_4A 11100101111mmmmm 011gggnnnnnttttt E5E0 6000 + // ST4D {.D, .D, .D, .D }, , [{, #, MUL VL}] SVE_JO_3A 111001011111iiii 111gggnnnnnttttt E5F0 E000 + +INST2(st4h, "st4h", 0, IF_SVE_2BR, 0xE4E06000, 0xE4F0E000 ) + // ST4H {.H, .H, .H, .H }, , [, , LSL #1] SVE_JC_4A 11100100111mmmmm 011gggnnnnnttttt E4E0 6000 + // ST4H {.H, .H, .H, .H }, , [{, #, MUL VL}] SVE_JO_3A 111001001111iiii 111gggnnnnnttttt E4F0 E000 + +INST2(st4w, "st4w", 0, IF_SVE_2BR, 0xE5606000, 0xE570E000 ) + // ST4W {.S, .S, .S, .S }, , [, , LSL #2] SVE_JC_4A 11100101011mmmmm 011gggnnnnnttttt E560 6000 + // ST4W {.S, .S, .S, .S }, , [{, #, MUL VL}] SVE_JO_3A 111001010111iiii 111gggnnnnnttttt E570 E000 + + +// enum name info SVE_JE_3A SVE_JF_4A +INST2(st2q, "st2q", 0, IF_SVE_2BS, 0xE4400000, 0xE4600000 ) + // ST2Q {.Q, .Q }, , [{, #, MUL VL}] SVE_JE_3A 111001000100iiii 000gggnnnnnttttt E440 0000 + // ST2Q {.Q, .Q }, , [, , LSL #4] SVE_JF_4A 11100100011mmmmm 000gggnnnnnttttt E460 0000 + +INST2(st3q, "st3q", 0, IF_SVE_2BS, 0xE4800000, 0xE4A00000 ) + // ST3Q {.Q, .Q, .Q }, , [{, #, MUL VL}] SVE_JE_3A 111001001000iiii 000gggnnnnnttttt E480 0000 + // ST3Q {.Q, .Q, .Q }, , [, , LSL #4] SVE_JF_4A 11100100101mmmmm 000gggnnnnnttttt E4A0 0000 + +INST2(st4q, "st4q", 0, IF_SVE_2BS, 0xE4C00000, 0xE4E00000 ) + // ST4Q {.Q, .Q, .Q, .Q }, , [{, #, MUL VL}] SVE_JE_3A 111001001100iiii 000gggnnnnnttttt E4C0 0000 + // ST4Q {.Q, .Q, .Q, .Q }, , [, , LSL #4] SVE_JF_4A 11100100111mmmmm 000gggnnnnnttttt E4E0 0000 + + +// enum name info SVE_AQ_3A +INST1(abs, "abs", 0, IF_SVE_AQ_3A, 0x0416A000 ) + // ABS ., /M, . SVE_AQ_3A 00000100xx010110 101gggnnnnnddddd 0416 A000 + +INST1(neg, "neg", 0, IF_SVE_AQ_3A, 0x0417A000 ) + // NEG ., /M, . SVE_AQ_3A 00000100xx010111 101gggnnnnnddddd 0417 A000 + +INST1(sxtb, "sxtb", 0, IF_SVE_AQ_3A, 0x0410A000 ) + // SXTB ., /M, . SVE_AQ_3A 00000100xx010000 101gggnnnnnddddd 0410 A000 + +INST1(sxth, "sxth", 0, IF_SVE_AQ_3A, 0x0412A000 ) + // SXTH ., /M, . SVE_AQ_3A 00000100xx010010 101gggnnnnnddddd 0412 A000 + +INST1(sxtw, "sxtw", 0, IF_SVE_AQ_3A, 0x0414A000 ) + // SXTW .D, /M, .D SVE_AQ_3A 00000100xx010100 101gggnnnnnddddd 0414 A000 + +INST1(uxtb, "uxtb", 0, IF_SVE_AQ_3A, 0x0411A000 ) + // UXTB ., /M, . SVE_AQ_3A 00000100xx010001 101gggnnnnnddddd 0411 A000 + +INST1(uxth, "uxth", 0, IF_SVE_AQ_3A, 0x0413A000 ) + // UXTH ., /M, . SVE_AQ_3A 00000100xx010011 101gggnnnnnddddd 0413 A000 + +INST1(uxtw, "uxtw", 0, IF_SVE_AQ_3A, 0x0415A000 ) + // UXTW .D, /M, .D SVE_AQ_3A 00000100xx010101 101gggnnnnnddddd 0415 A000 + + +// enum name info SVE_CZ_4A +INST1(ands, "ands", 0, IF_SVE_CZ_4A, 0x25404000 ) + // ANDS .B, /Z, .B, .B SVE_CZ_4A 001001010100MMMM 01gggg0NNNN0DDDD 2540 4000 + +INST1(bics, "bics", 0, IF_SVE_CZ_4A, 0x25404010 ) + // BICS .B, /Z, .B, .B SVE_CZ_4A 001001010100MMMM 01gggg0NNNN1DDDD 2540 4010 + +INST1(eors, "eors", 0, IF_SVE_CZ_4A, 0x25404200 ) + // EORS .B, /Z, .B, .B SVE_CZ_4A 001001010100MMMM 01gggg1NNNN0DDDD 2540 4200 + +INST1(nand, "nand", 0, IF_SVE_CZ_4A, 0x25804210 ) + // NAND .B, /Z, .B, .B SVE_CZ_4A 001001011000MMMM 01gggg1NNNN1DDDD 2580 4210 + +INST1(nands, "nands", 0, IF_SVE_CZ_4A, 0x25C04210 ) + // NANDS .B, /Z, .B, .B SVE_CZ_4A 001001011100MMMM 01gggg1NNNN1DDDD 25C0 4210 + +INST1(nor, "nor", 0, IF_SVE_CZ_4A, 0x25804200 ) + // NOR .B, /Z, .B, .B SVE_CZ_4A 001001011000MMMM 01gggg1NNNN0DDDD 2580 4200 + +INST1(nors, "nors", 0, IF_SVE_CZ_4A, 0x25C04200 ) + // NORS .B, /Z, .B, .B SVE_CZ_4A 001001011100MMMM 01gggg1NNNN0DDDD 25C0 4200 + +INST1(nots, "nots", 0, IF_SVE_CZ_4A, 0x25404200 ) + // NOTS .B, /Z, .B SVE_CZ_4A 001001010100MMMM 01gggg1NNNN0DDDD 2540 4200 + +INST1(orns, "orns", 0, IF_SVE_CZ_4A, 0x25C04010 ) + // ORNS .B, /Z, .B, .B SVE_CZ_4A 001001011100MMMM 01gggg0NNNN1DDDD 25C0 4010 + +INST1(orrs, "orrs", 0, IF_SVE_CZ_4A, 0x25C04000 ) + // ORRS .B, /Z, .B, .B SVE_CZ_4A 001001011100MMMM 01gggg0NNNN0DDDD 25C0 4000 + + +// enum name info SVE_CU_3A +INST1(rbit, "rbit", 0, IF_SVE_CU_3A, 0x05278000 ) + // RBIT ., /M, . SVE_CU_3A 00000101xx100111 100gggnnnnnddddd 0527 8000 + +INST1(revb, "revb", 0, IF_SVE_CU_3A, 0x05248000 ) + // REVB ., /M, . SVE_CU_3A 00000101xx100100 100gggnnnnnddddd 0524 8000 + +INST1(revh, "revh", 0, IF_SVE_CU_3A, 0x05258000 ) + // REVH ., /M, . SVE_CU_3A 00000101xx100101 100gggnnnnnddddd 0525 8000 + +INST1(revw, "revw", 0, IF_SVE_CU_3A, 0x05268000 ) + // REVW .D, /M, .D SVE_CU_3A 00000101xx100110 100gggnnnnnddddd 0526 8000 + + +// enum name info SVE_AP_3A +INST1(cls, "cls", 0, IF_SVE_AP_3A, 0x0418A000 ) + // CLS ., /M, . SVE_AP_3A 00000100xx011000 101gggnnnnnddddd 0418 A000 + +INST1(clz, "clz", 0, IF_SVE_AP_3A, 0x0419A000 ) + // CLZ ., /M, . SVE_AP_3A 00000100xx011001 101gggnnnnnddddd 0419 A000 + +INST1(cnot, "cnot", 0, IF_SVE_AP_3A, 0x041BA000 ) + // CNOT ., /M, . SVE_AP_3A 00000100xx011011 101gggnnnnnddddd 041B A000 + +INST1(cnt, "cnt", 0, IF_SVE_AP_3A, 0x041AA000 ) + // CNT ., /M, . SVE_AP_3A 00000100xx011010 101gggnnnnnddddd 041A A000 + +INST1(fabs, "fabs", 0, IF_SVE_AP_3A, 0x041CA000 ) + // FABS ., /M, . SVE_AP_3A 00000100xx011100 101gggnnnnnddddd 041C A000 + +INST1(fneg, "fneg", 0, IF_SVE_AP_3A, 0x041DA000 ) + // FNEG ., /M, . SVE_AP_3A 00000100xx011101 101gggnnnnnddddd 041D A000 + + +// enum name info SVE_AC_3A +INST1(sdiv, "sdiv", 0, IF_SVE_AC_3A, 0x04140000 ) + // SDIV ., /M, ., . SVE_AC_3A 00000100xx010100 000gggmmmmmddddd 0414 0000 + +INST1(sdivr, "sdivr", 0, IF_SVE_AC_3A, 0x04160000 ) + // SDIVR ., /M, ., . SVE_AC_3A 00000100xx010110 000gggmmmmmddddd 0416 0000 + +INST1(udiv, "udiv", 0, IF_SVE_AC_3A, 0x04150000 ) + // UDIV ., /M, ., . SVE_AC_3A 00000100xx010101 000gggmmmmmddddd 0415 0000 + +INST1(udivr, "udivr", 0, IF_SVE_AC_3A, 0x04170000 ) + // UDIVR ., /M, ., . SVE_AC_3A 00000100xx010111 000gggmmmmmddddd 0417 0000 + + +// enum name info SVE_BS_1A +INST1(eon, "eon", 0, IF_SVE_BS_1A, 0x05400000 ) + // EON ., ., # SVE_BS_1A 00000101010000ii iiiiiiiiiiiddddd 0540 0000 + + +// enum name info SVE_AK_3A +INST1(smaxv, "smaxv", 0, IF_SVE_AK_3A, 0x04082000 ) + // SMAXV , , . SVE_AK_3A 00000100xx001000 001gggnnnnnddddd 0408 2000 + +INST1(sminv, "sminv", 0, IF_SVE_AK_3A, 0x040A2000 ) + // SMINV , , . SVE_AK_3A 00000100xx001010 001gggnnnnnddddd 040A 2000 + +INST1(umaxv, "umaxv", 0, IF_SVE_AK_3A, 0x04092000 ) + // UMAXV , , . SVE_AK_3A 00000100xx001001 001gggnnnnnddddd 0409 2000 + +INST1(uminv, "uminv", 0, IF_SVE_AK_3A, 0x040B2000 ) + // UMINV , , . SVE_AK_3A 00000100xx001011 001gggnnnnnddddd 040B 2000 + + +// enum name info SVE_HE_3A +INST1(faddv, "faddv", 0, IF_SVE_HE_3A, 0x65002000 ) + // FADDV , , . SVE_HE_3A 01100101xx000000 001gggnnnnnddddd 6500 2000 + +INST1(fmaxnmv, "fmaxnmv", 0, IF_SVE_HE_3A, 0x65042000 ) + // FMAXNMV , , . SVE_HE_3A 01100101xx000100 001gggnnnnnddddd 6504 2000 + +INST1(fmaxv, "fmaxv", 0, IF_SVE_HE_3A, 0x65062000 ) + // FMAXV , , . SVE_HE_3A 01100101xx000110 001gggnnnnnddddd 6506 2000 + +INST1(fminnmv, "fminnmv", 0, IF_SVE_HE_3A, 0x65052000 ) + // FMINNMV , , . SVE_HE_3A 01100101xx000101 001gggnnnnnddddd 6505 2000 + +INST1(fminv, "fminv", 0, IF_SVE_HE_3A, 0x65072000 ) + // FMINV , , . SVE_HE_3A 01100101xx000111 001gggnnnnnddddd 6507 2000 + + +// enum name info SVE_ER_3A +INST1(addp, "addp", 0, IF_SVE_ER_3A, 0x4411A000 ) + // ADDP ., /M, ., . SVE_ER_3A 01000100xx010001 101gggmmmmmddddd 4411 A000 + +INST1(smaxp, "smaxp", 0, IF_SVE_ER_3A, 0x4414A000 ) + // SMAXP ., /M, ., . SVE_ER_3A 01000100xx010100 101gggmmmmmddddd 4414 A000 + +INST1(sminp, "sminp", 0, IF_SVE_ER_3A, 0x4416A000 ) + // SMINP ., /M, ., . SVE_ER_3A 01000100xx010110 101gggmmmmmddddd 4416 A000 + +INST1(umaxp, "umaxp", 0, IF_SVE_ER_3A, 0x4415A000 ) + // UMAXP ., /M, ., . SVE_ER_3A 01000100xx010101 101gggmmmmmddddd 4415 A000 + +INST1(uminp, "uminp", 0, IF_SVE_ER_3A, 0x4417A000 ) + // UMINP ., /M, ., . SVE_ER_3A 01000100xx010111 101gggmmmmmddddd 4417 A000 + + +// enum name info SVE_GR_3A +INST1(faddp, "faddp", 0, IF_SVE_GR_3A, 0x64108000 ) + // FADDP ., /M, ., . SVE_GR_3A 01100100xx010000 100gggmmmmmddddd 6410 8000 + +INST1(fmaxnmp, "fmaxnmp", 0, IF_SVE_GR_3A, 0x64148000 ) + // FMAXNMP ., /M, ., . SVE_GR_3A 01100100xx010100 100gggmmmmmddddd 6414 8000 + +INST1(fmaxp, "fmaxp", 0, IF_SVE_GR_3A, 0x64168000 ) + // FMAXP ., /M, ., . SVE_GR_3A 01100100xx010110 100gggmmmmmddddd 6416 8000 + +INST1(fminnmp, "fminnmp", 0, IF_SVE_GR_3A, 0x64158000 ) + // FMINNMP ., /M, ., . SVE_GR_3A 01100100xx010101 100gggmmmmmddddd 6415 8000 + +INST1(fminp, "fminp", 0, IF_SVE_GR_3A, 0x64178000 ) + // FMINP ., /M, ., . SVE_GR_3A 01100100xx010111 100gggmmmmmddddd 6417 8000 + + +// enum name info SVE_FU_2A +INST1(srsra, "srsra", RSH, IF_SVE_FU_2A, 0x4500E800 ) + // SRSRA ., ., # SVE_FU_2A 01000101xx0xxiii 111010nnnnnddddd 4500 E800 + +INST1(ssra, "ssra", RSH, IF_SVE_FU_2A, 0x4500E000 ) + // SSRA ., ., # SVE_FU_2A 01000101xx0xxiii 111000nnnnnddddd 4500 E000 + +INST1(ursra, "ursra", RSH, IF_SVE_FU_2A, 0x4500EC00 ) + // URSRA ., ., # SVE_FU_2A 01000101xx0xxiii 111011nnnnnddddd 4500 EC00 + +INST1(usra, "usra", RSH, IF_SVE_FU_2A, 0x4500E400 ) + // USRA ., ., # SVE_FU_2A 01000101xx0xxiii 111001nnnnnddddd 4500 E400 + + +// enum name info SVE_AM_2A +INST1(asrd, "asrd", 0, IF_SVE_AM_2A, 0x04048000 ) + // ASRD ., /M, ., # SVE_AM_2A 00000100xx000100 100gggxxiiiddddd 0404 8000 + +INST1(sqshlu, "sqshlu", 0, IF_SVE_AM_2A, 0x040F8000 ) + // SQSHLU ., /M, ., # SVE_AM_2A 00000100xx001111 100gggxxiiiddddd 040F 8000 + +INST1(srshr, "srshr", RSH, IF_SVE_AM_2A, 0x040C8000 ) + // SRSHR ., /M, ., # SVE_AM_2A 00000100xx001100 100gggxxiiiddddd 040C 8000 + +INST1(urshr, "urshr", RSH, IF_SVE_AM_2A, 0x040D8000 ) + // URSHR ., /M, ., # SVE_AM_2A 00000100xx001101 100gggxxiiiddddd 040D 8000 + + +// enum name info SVE_GA_2A +INST1(sqrshrn, "sqrshrn", RSH, IF_SVE_GA_2A, 0x45B02800 ) + // SQRSHRN .H, {.S-.S }, # SVE_GA_2A 010001011011iiii 001010nnnn0ddddd 45B0 2800 + +INST1(sqrshrun, "sqrshrun", RSH, IF_SVE_GA_2A, 0x45B00800 ) + // SQRSHRUN .H, {.S-.S }, # SVE_GA_2A 010001011011iiii 000010nnnn0ddddd 45B0 0800 + +INST1(uqrshrn, "uqrshrn", RSH, IF_SVE_GA_2A, 0x45B03800 ) + // UQRSHRN .H, {.S-.S }, # SVE_GA_2A 010001011011iiii 001110nnnn0ddddd 45B0 3800 + + +// enum name info SVE_FT_2A +INST1(sli, "sli", 0, IF_SVE_FT_2A, 0x4500F400 ) + // SLI ., ., # SVE_FT_2A 01000101xx0xxiii 111101nnnnnddddd 4500 F400 + +INST1(sri, "sri", RSH, IF_SVE_FT_2A, 0x4500F000 ) + // SRI ., ., # SVE_FT_2A 01000101xx0xxiii 111100nnnnnddddd 4500 F000 + + +// enum name info SVE_EU_3A +INST1(sqrshl, "sqrshl", 0, IF_SVE_EU_3A, 0x440A8000 ) + // SQRSHL ., /M, ., . SVE_EU_3A 01000100xx001010 100gggmmmmmddddd 440A 8000 + +INST1(sqrshlr, "sqrshlr", 0, IF_SVE_EU_3A, 0x440E8000 ) + // SQRSHLR ., /M, ., . SVE_EU_3A 01000100xx001110 100gggmmmmmddddd 440E 8000 + +INST1(sqshlr, "sqshlr", 0, IF_SVE_EU_3A, 0x440C8000 ) + // SQSHLR ., /M, ., . SVE_EU_3A 01000100xx001100 100gggmmmmmddddd 440C 8000 + +INST1(srshl, "srshl", 0, IF_SVE_EU_3A, 0x44028000 ) + // SRSHL ., /M, ., . SVE_EU_3A 01000100xx000010 100gggmmmmmddddd 4402 8000 + +INST1(srshlr, "srshlr", 0, IF_SVE_EU_3A, 0x44068000 ) + // SRSHLR ., /M, ., . SVE_EU_3A 01000100xx000110 100gggmmmmmddddd 4406 8000 + +INST1(uqrshl, "uqrshl", 0, IF_SVE_EU_3A, 0x440B8000 ) + // UQRSHL ., /M, ., . SVE_EU_3A 01000100xx001011 100gggmmmmmddddd 440B 8000 + +INST1(uqrshlr, "uqrshlr", 0, IF_SVE_EU_3A, 0x440F8000 ) + // UQRSHLR ., /M, ., . SVE_EU_3A 01000100xx001111 100gggmmmmmddddd 440F 8000 + +INST1(uqshlr, "uqshlr", 0, IF_SVE_EU_3A, 0x440D8000 ) + // UQSHLR ., /M, ., . SVE_EU_3A 01000100xx001101 100gggmmmmmddddd 440D 8000 + +INST1(urshl, "urshl", 0, IF_SVE_EU_3A, 0x44038000 ) + // URSHL ., /M, ., . SVE_EU_3A 01000100xx000011 100gggmmmmmddddd 4403 8000 + +INST1(urshlr, "urshlr", 0, IF_SVE_EU_3A, 0x44078000 ) + // URSHLR ., /M, ., . SVE_EU_3A 01000100xx000111 100gggmmmmmddddd 4407 8000 + + +// enum name info SVE_HL_3A +INST1(fabd, "fabd", 0, IF_SVE_HL_3A, 0x65088000 ) + // FABD ., /M, ., . SVE_HL_3A 01100101xx001000 100gggmmmmmddddd 6508 8000 + +INST1(famax, "famax", 0, IF_SVE_HL_3A, 0x650E8000 ) + // FAMAX ., /M, ., . SVE_HL_3A 01100101xx001110 100gggmmmmmddddd 650E 8000 + +INST1(famin, "famin", 0, IF_SVE_HL_3A, 0x650F8000 ) + // FAMIN ., /M, ., . SVE_HL_3A 01100101xx001111 100gggmmmmmddddd 650F 8000 + +INST1(fdiv, "fdiv", 0, IF_SVE_HL_3A, 0x650D8000 ) + // FDIV ., /M, ., . SVE_HL_3A 01100101xx001101 100gggmmmmmddddd 650D 8000 + +INST1(fdivr, "fdivr", 0, IF_SVE_HL_3A, 0x650C8000 ) + // FDIVR ., /M, ., . SVE_HL_3A 01100101xx001100 100gggmmmmmddddd 650C 8000 + +INST1(fmulx, "fmulx", 0, IF_SVE_HL_3A, 0x650A8000 ) + // FMULX ., /M, ., . SVE_HL_3A 01100101xx001010 100gggmmmmmddddd 650A 8000 + +INST1(fscale, "fscale", 0, IF_SVE_HL_3A, 0x65098000 ) + // FSCALE ., /M, ., . SVE_HL_3A 01100101xx001001 100gggmmmmmddddd 6509 8000 + + +// enum name info SVE_HK_3A +INST1(frecps, "frecps", 0, IF_SVE_HK_3A, 0x65001800 ) + // FRECPS ., ., . SVE_HK_3A 01100101xx0mmmmm 000110nnnnnddddd 6500 1800 + +INST1(frsqrts, "frsqrts", 0, IF_SVE_HK_3A, 0x65001C00 ) + // FRSQRTS ., ., . SVE_HK_3A 01100101xx0mmmmm 000111nnnnnddddd 6500 1C00 + +INST1(ftsmul, "ftsmul", 0, IF_SVE_HK_3A, 0x65000C00 ) + // FTSMUL ., ., . SVE_HK_3A 01100101xx0mmmmm 000011nnnnnddddd 6500 0C00 + + +// enum name info SVE_HT_4A +INST1(facge, "facge", 0, IF_SVE_HT_4A, 0x6500C010 ) + // FACGE ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 110gggnnnnn1DDDD 6500 C010 + +INST1(facgt, "facgt", 0, IF_SVE_HT_4A, 0x6500E010 ) + // FACGT ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 111gggnnnnn1DDDD 6500 E010 + +INST1(facle, "facle", 0, IF_SVE_HT_4A, 0x6500C010 ) + // FACLE ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 110gggnnnnn1DDDD 6500 C010 + +INST1(faclt, "faclt", 0, IF_SVE_HT_4A, 0x6500E010 ) + // FACLT ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 111gggnnnnn1DDDD 6500 E010 + +INST1(fcmuo, "fcmuo", 0, IF_SVE_HT_4A, 0x6500C000 ) + // FCMUO ., /Z, ., . SVE_HT_4A 01100101xx0mmmmm 110gggnnnnn0DDDD 6500 C000 + + +// enum name info SVE_ET_3A +INST1(sqsubr, "sqsubr", 0, IF_SVE_ET_3A, 0x441E8000 ) + // SQSUBR ., /M, ., . SVE_ET_3A 01000100xx011110 100gggmmmmmddddd 441E 8000 + +INST1(suqadd, "suqadd", 0, IF_SVE_ET_3A, 0x441C8000 ) + // SUQADD ., /M, ., . SVE_ET_3A 01000100xx011100 100gggmmmmmddddd 441C 8000 + +INST1(uqsubr, "uqsubr", 0, IF_SVE_ET_3A, 0x441F8000 ) + // UQSUBR ., /M, ., . SVE_ET_3A 01000100xx011111 100gggmmmmmddddd 441F 8000 + +INST1(usqadd, "usqadd", 0, IF_SVE_ET_3A, 0x441D8000 ) + // USQADD ., /M, ., . SVE_ET_3A 01000100xx011101 100gggmmmmmddddd 441D 8000 + + +// enum name info SVE_ES_3A +INST1(sqabs, "sqabs", 0, IF_SVE_ES_3A, 0x4408A000 ) + // SQABS ., /M, . SVE_ES_3A 01000100xx001000 101gggnnnnnddddd 4408 A000 + +INST1(sqneg, "sqneg", 0, IF_SVE_ES_3A, 0x4409A000 ) + // SQNEG ., /M, . SVE_ES_3A 01000100xx001001 101gggnnnnnddddd 4409 A000 + +INST1(urecpe, "urecpe", 0, IF_SVE_ES_3A, 0x4400A000 ) + // URECPE .S, /M, .S SVE_ES_3A 01000100xx000000 101gggnnnnnddddd 4400 A000 + +INST1(ursqrte, "ursqrte", 0, IF_SVE_ES_3A, 0x4401A000 ) + // URSQRTE .S, /M, .S SVE_ES_3A 01000100xx000001 101gggnnnnnddddd 4401 A000 + + +// enum name info SVE_HF_2A +INST1(frecpe, "frecpe", 0, IF_SVE_HF_2A, 0x650E3000 ) + // FRECPE ., . SVE_HF_2A 01100101xx001110 001100nnnnnddddd 650E 3000 + +INST1(frsqrte, "frsqrte", 0, IF_SVE_HF_2A, 0x650F3000 ) + // FRSQRTE ., . SVE_HF_2A 01100101xx001111 001100nnnnnddddd 650F 3000 + + +// enum name info SVE_HR_3A +INST1(frecpx, "frecpx", 0, IF_SVE_HR_3A, 0x650CA000 ) + // FRECPX ., /M, . SVE_HR_3A 01100101xx001100 101gggnnnnnddddd 650C A000 + +INST1(fsqrt, "fsqrt", 0, IF_SVE_HR_3A, 0x650DA000 ) + // FSQRT ., /M, . SVE_HR_3A 01100101xx001101 101gggnnnnnddddd 650D A000 + + +// enum name info SVE_BZ_3A +INST1(tbx, "tbx", 0, IF_SVE_BZ_3A, 0x05202C00 ) + // TBX ., ., . SVE_BZ_3A 00000101xx1mmmmm 001011nnnnnddddd 0520 2C00 + + +// enum name info SVE_EP_3A +INST1(shadd, "shadd", 0, IF_SVE_EP_3A, 0x44108000 ) + // SHADD ., /M, ., . SVE_EP_3A 01000100xx010000 100gggmmmmmddddd 4410 8000 + +INST1(shsub, "shsub", 0, IF_SVE_EP_3A, 0x44128000 ) + // SHSUB ., /M, ., . SVE_EP_3A 01000100xx010010 100gggmmmmmddddd 4412 8000 + +INST1(shsubr, "shsubr", 0, IF_SVE_EP_3A, 0x44168000 ) + // SHSUBR ., /M, ., . SVE_EP_3A 01000100xx010110 100gggmmmmmddddd 4416 8000 + +INST1(srhadd, "srhadd", 0, IF_SVE_EP_3A, 0x44148000 ) + // SRHADD ., /M, ., . SVE_EP_3A 01000100xx010100 100gggmmmmmddddd 4414 8000 + +INST1(uhadd, "uhadd", 0, IF_SVE_EP_3A, 0x44118000 ) + // UHADD ., /M, ., . SVE_EP_3A 01000100xx010001 100gggmmmmmddddd 4411 8000 + +INST1(uhsub, "uhsub", 0, IF_SVE_EP_3A, 0x44138000 ) + // UHSUB ., /M, ., . SVE_EP_3A 01000100xx010011 100gggmmmmmddddd 4413 8000 + +INST1(uhsubr, "uhsubr", 0, IF_SVE_EP_3A, 0x44178000 ) + // UHSUBR ., /M, ., . SVE_EP_3A 01000100xx010111 100gggmmmmmddddd 4417 8000 + +INST1(urhadd, "urhadd", 0, IF_SVE_EP_3A, 0x44158000 ) + // URHADD ., /M, ., . SVE_EP_3A 01000100xx010101 100gggmmmmmddddd 4415 8000 + + +// enum name info SVE_AD_3A +INST1(sabd, "sabd", 0, IF_SVE_AD_3A, 0x040C0000 ) + // SABD ., /M, ., . SVE_AD_3A 00000100xx001100 000gggmmmmmddddd 040C 0000 + +INST1(uabd, "uabd", 0, IF_SVE_AD_3A, 0x040D0000 ) + // UABD ., /M, ., . SVE_AD_3A 00000100xx001101 000gggmmmmmddddd 040D 0000 + + +// enum name info SVE_FW_3A +INST1(saba, "saba", 0, IF_SVE_FW_3A, 0x4500F800 ) + // SABA ., ., . SVE_FW_3A 01000101xx0mmmmm 111110nnnnnddddd 4500 F800 + +INST1(uaba, "uaba", 0, IF_SVE_FW_3A, 0x4500FC00 ) + // UABA ., ., . SVE_FW_3A 01000101xx0mmmmm 111111nnnnnddddd 4500 FC00 + + +// enum name info SVE_BD_3B +INST1(pmul, "pmul", 0, IF_SVE_BD_3B, 0x04206400 ) + // PMUL .B, .B, .B SVE_BD_3B 00000100001mmmmm 011001nnnnnddddd 0420 6400 + + +// enum name info SVE_AV_3A +INST1(bcax, "bcax", 0, IF_SVE_AV_3A, 0x04603800 ) + // BCAX .D, .D, .D, .D SVE_AV_3A 00000100011mmmmm 001110kkkkkddddd 0460 3800 + +INST1(bsl, "bsl", 0, IF_SVE_AV_3A, 0x04203C00 ) + // BSL .D, .D, .D, .D SVE_AV_3A 00000100001mmmmm 001111kkkkkddddd 0420 3C00 + +INST1(bsl1n, "bsl1n", 0, IF_SVE_AV_3A, 0x04603C00 ) + // BSL1N .D, .D, .D, .D SVE_AV_3A 00000100011mmmmm 001111kkkkkddddd 0460 3C00 + +INST1(bsl2n, "bsl2n", 0, IF_SVE_AV_3A, 0x04A03C00 ) + // BSL2N .D, .D, .D, .D SVE_AV_3A 00000100101mmmmm 001111kkkkkddddd 04A0 3C00 + +INST1(eor3, "eor3", 0, IF_SVE_AV_3A, 0x04203800 ) + // EOR3 .D, .D, .D, .D SVE_AV_3A 00000100001mmmmm 001110kkkkkddddd 0420 3800 + +INST1(nbsl, "nbsl", 0, IF_SVE_AV_3A, 0x04E03C00 ) + // NBSL .D, .D, .D, .D SVE_AV_3A 00000100111mmmmm 001111kkkkkddddd 04E0 3C00 + + +// enum name info SVE_HG_2A +INST1(bfcvtn, "bfcvtn", 0, IF_SVE_HG_2A, 0x650A3800 ) + // BFCVTN .B, {.H-.H } SVE_HG_2A 0110010100001010 001110nnnn0ddddd 650A 3800 + +INST1(fcvtn, "fcvtn", NRW, IF_SVE_HG_2A, 0x650A3000 ) + // FCVTN .B, {.H-.H } SVE_HG_2A 0110010100001010 001100nnnn0ddddd 650A 3000 + +INST1(fcvtnb, "fcvtnb", 0, IF_SVE_HG_2A, 0x650A3400 ) + // FCVTNB .B, {.S-.S } SVE_HG_2A 0110010100001010 001101nnnn0ddddd 650A 3400 + + +// enum name info SVE_GP_3A +INST1(fcadd, "fcadd", 0, IF_SVE_GP_3A, 0x64008000 ) + // FCADD ., /M, ., ., SVE_GP_3A 01100100xx00000r 100gggmmmmmddddd 6400 8000 + + +// enum name info SVE_FO_3A +INST1(smmla, "smmla", 0, IF_SVE_FO_3A, 0x45009800 ) + // SMMLA .S, .B, .B SVE_FO_3A 01000101000mmmmm 100110nnnnnddddd 4500 9800 + +INST1(ummla, "ummla", 0, IF_SVE_FO_3A, 0x45C09800 ) + // UMMLA .S, .B, .B SVE_FO_3A 01000101110mmmmm 100110nnnnnddddd 45C0 9800 + +INST1(usmmla, "usmmla", 0, IF_SVE_FO_3A, 0x45809800 ) + // USMMLA .S, .B, .B SVE_FO_3A 01000101100mmmmm 100110nnnnnddddd 4580 9800 + + +// enum name info SVE_HD_3A +INST1(bfmmla, "bfmmla", 0, IF_SVE_HD_3A, 0x6460E400 ) + // BFMMLA .S, .H, .H SVE_HD_3A 01100100011mmmmm 111001nnnnnddddd 6460 E400 + + +// enum name info SVE_EQ_3A +INST1(sadalp, "sadalp", LNG, IF_SVE_EQ_3A, 0x4404A000 ) + // SADALP ., /M, . SVE_EQ_3A 01000100xx000100 101gggnnnnnddddd 4404 A000 + +INST1(uadalp, "uadalp", LNG, IF_SVE_EQ_3A, 0x4405A000 ) + // UADALP ., /M, . SVE_EQ_3A 01000100xx000101 101gggnnnnnddddd 4405 A000 + + +// enum name info SVE_HQ_3A +INST1(frinta, "frinta", 0, IF_SVE_HQ_3A, 0x6504A000 ) + // FRINTA ., /M, . SVE_HQ_3A 01100101xx000100 101gggnnnnnddddd 6504 A000 + +INST1(frinti, "frinti", 0, IF_SVE_HQ_3A, 0x6507A000 ) + // FRINTI ., /M, . SVE_HQ_3A 01100101xx000111 101gggnnnnnddddd 6507 A000 + +INST1(frintm, "frintm", 0, IF_SVE_HQ_3A, 0x6502A000 ) + // FRINTM ., /M, . SVE_HQ_3A 01100101xx000010 101gggnnnnnddddd 6502 A000 + +INST1(frintn, "frintn", 0, IF_SVE_HQ_3A, 0x6500A000 ) + // FRINTN ., /M, . SVE_HQ_3A 01100101xx000000 101gggnnnnnddddd 6500 A000 + +INST1(frintp, "frintp", 0, IF_SVE_HQ_3A, 0x6501A000 ) + // FRINTP ., /M, . SVE_HQ_3A 01100101xx000001 101gggnnnnnddddd 6501 A000 + +INST1(frintx, "frintx", 0, IF_SVE_HQ_3A, 0x6506A000 ) + // FRINTX ., /M, . SVE_HQ_3A 01100101xx000110 101gggnnnnnddddd 6506 A000 + +INST1(frintz, "frintz", 0, IF_SVE_HQ_3A, 0x6503A000 ) + // FRINTZ ., /M, . SVE_HQ_3A 01100101xx000011 101gggnnnnnddddd 6503 A000 + + +// enum name info SVE_EZ_3A +INST1(sudot, "sudot", 0, IF_SVE_EZ_3A, 0x44A01C00 ) + // SUDOT .S, .B, .B[] SVE_EZ_3A 01000100101iimmm 000111nnnnnddddd 44A0 1C00 + + +// enum name info SVE_GK_2A +INST1(aesd, "aesd", 0, IF_SVE_GK_2A, 0x4522E400 ) + // AESD .B, .B, .B SVE_GK_2A 0100010100100010 111001mmmmmddddd 4522 E400 + +INST1(aese, "aese", 0, IF_SVE_GK_2A, 0x4522E000 ) + // AESE .B, .B, .B SVE_GK_2A 0100010100100010 111000mmmmmddddd 4522 E000 + +INST1(sm4e, "sm4e", 0, IF_SVE_GK_2A, 0x4523E000 ) + // SM4E .S, .S, .S SVE_GK_2A 0100010100100011 111000mmmmmddddd 4523 E000 + + +// enum name info SVE_GL_1A +INST1(aesimc, "aesimc", 0, IF_SVE_GL_1A, 0x4520E400 ) + // AESIMC .B, .B SVE_GL_1A 0100010100100000 11100100000ddddd 4520 E400 + +INST1(aesmc, "aesmc", 0, IF_SVE_GL_1A, 0x4520E000 ) + // AESMC .B, .B SVE_GL_1A 0100010100100000 11100000000ddddd 4520 E000 + + +// enum name info SVE_GJ_3A +INST1(rax1, "rax1", 0, IF_SVE_GJ_3A, 0x4520F400 ) + // RAX1 .D, .D, .D SVE_GJ_3A 01000101001mmmmm 111101nnnnnddddd 4520 F400 + +INST1(sm4ekey, "sm4ekey", 0, IF_SVE_GJ_3A, 0x4520F000 ) + // SM4EKEY .S, .S, .S SVE_GJ_3A 01000101001mmmmm 111100nnnnnddddd 4520 F000 + + +// enum name info SVE_AW_2A +INST1(xar, "xar", 0, IF_SVE_AW_2A, 0x04203400 ) + // XAR ., ., ., # SVE_AW_2A 00000100xx1xxiii 001101mmmmmddddd 0420 3400 + + +// enum name info SVE_HO_3A +INST1(bfcvt, "bfcvt", 0, IF_SVE_HO_3A, 0x658AA000 ) + // BFCVT .H, /M, .S SVE_HO_3A 0110010110001010 101gggnnnnnddddd 658A A000 + +INST1(fcvtx, "fcvtx", 0, IF_SVE_HO_3A, 0x650AA000 ) + // FCVTX .S, /M, .D SVE_HO_3A 0110010100001010 101gggnnnnnddddd 650A A000 + + +// enum name info SVE_AF_3A +INST1(andv, "andv", 0, IF_SVE_AF_3A, 0x041A2000 ) + // ANDV , , . SVE_AF_3A 00000100xx011010 001gggnnnnnddddd 041A 2000 + +INST1(eorv, "eorv", 0, IF_SVE_AF_3A, 0x04192000 ) + // EORV , , . SVE_AF_3A 00000100xx011001 001gggnnnnnddddd 0419 2000 + +INST1(orv, "orv", 0, IF_SVE_AF_3A, 0x04182000 ) + // ORV , , . SVE_AF_3A 00000100xx011000 001gggnnnnnddddd 0418 2000 + + +// enum name info SVE_AG_3A +INST1(andqv, "andqv", 0, IF_SVE_AG_3A, 0x041E2000 ) + // ANDQV ., , . SVE_AG_3A 00000100xx011110 001gggnnnnnddddd 041E 2000 + +INST1(eorqv, "eorqv", 0, IF_SVE_AG_3A, 0x041D2000 ) + // EORQV ., , . SVE_AG_3A 00000100xx011101 001gggnnnnnddddd 041D 2000 + +INST1(orqv, "orqv", 0, IF_SVE_AG_3A, 0x041C2000 ) + // ORQV ., , . SVE_AG_3A 00000100xx011100 001gggnnnnnddddd 041C 2000 + + +// enum name info SVE_AI_3A +INST1(saddv, "saddv", 0, IF_SVE_AI_3A, 0x04002000 ) + // SADDV
, , . SVE_AI_3A 00000100xx000000 001gggnnnnnddddd 0400 2000 + +INST1(uaddv, "uaddv", 0, IF_SVE_AI_3A, 0x04012000 ) + // UADDV
, , . SVE_AI_3A 00000100xx000001 001gggnnnnnddddd 0401 2000 + + +// enum name info SVE_AJ_3A +INST1(addqv, "addqv", 0, IF_SVE_AJ_3A, 0x04052000 ) + // ADDQV ., , . SVE_AJ_3A 00000100xx000101 001gggnnnnnddddd 0405 2000 + + +// enum name info SVE_AL_3A +INST1(smaxqv, "smaxqv", 0, IF_SVE_AL_3A, 0x040C2000 ) + // SMAXQV ., , . SVE_AL_3A 00000100xx001100 001gggnnnnnddddd 040C 2000 + +INST1(sminqv, "sminqv", 0, IF_SVE_AL_3A, 0x040E2000 ) + // SMINQV ., , . SVE_AL_3A 00000100xx001110 001gggnnnnnddddd 040E 2000 + +INST1(umaxqv, "umaxqv", 0, IF_SVE_AL_3A, 0x040D2000 ) + // UMAXQV ., , . SVE_AL_3A 00000100xx001101 001gggnnnnnddddd 040D 2000 + +INST1(uminqv, "uminqv", 0, IF_SVE_AL_3A, 0x040F2000 ) + // UMINQV ., , . SVE_AL_3A 00000100xx001111 001gggnnnnnddddd 040F 2000 + + +// enum name info SVE_AN_3A +INST1(asrr, "asrr", 0, IF_SVE_AN_3A, 0x04148000 ) + // ASRR ., /M, ., . SVE_AN_3A 00000100xx010100 100gggmmmmmddddd 0414 8000 + +INST1(lslr, "lslr", 0, IF_SVE_AN_3A, 0x04178000 ) + // LSLR ., /M, ., . SVE_AN_3A 00000100xx010111 100gggmmmmmddddd 0417 8000 + +INST1(lsrr, "lsrr", 0, IF_SVE_AN_3A, 0x04158000 ) + // LSRR ., /M, ., . SVE_AN_3A 00000100xx010101 100gggmmmmmddddd 0415 8000 + + +// enum name info SVE_AS_4A +INST1(mad, "mad", 0, IF_SVE_AS_4A, 0x0400C000 ) + // MAD ., /M, ., . SVE_AS_4A 00000100xx0mmmmm 110gggaaaaaddddd 0400 C000 + +INST1(msb, "msb", 0, IF_SVE_AS_4A, 0x0400E000 ) + // MSB ., /M, ., . SVE_AS_4A 00000100xx0mmmmm 111gggaaaaaddddd 0400 E000 + + +// enum name info SVE_BB_2A +INST1(addpl, "addpl", 0, IF_SVE_BB_2A, 0x04605000 ) + // ADDPL , , # SVE_BB_2A 00000100011nnnnn 01010iiiiiiddddd 0460 5000 + +INST1(addvl, "addvl", 0, IF_SVE_BB_2A, 0x04205000 ) + // ADDVL , , # SVE_BB_2A 00000100001nnnnn 01010iiiiiiddddd 0420 5000 + + +// enum name info SVE_BC_1A +INST1(rdvl, "rdvl", 0, IF_SVE_BC_1A, 0x04BF5000 ) + // RDVL , # SVE_BC_1A 0000010010111111 01010iiiiiiddddd 04BF 5000 + + +// enum name info SVE_BJ_2A +INST1(fexpa, "fexpa", 0, IF_SVE_BJ_2A, 0x0420B800 ) + // FEXPA ., . SVE_BJ_2A 00000100xx100000 101110nnnnnddddd 0420 B800 + + +// enum name info SVE_BK_3A +INST1(ftssel, "ftssel", 0, IF_SVE_BK_3A, 0x0420B000 ) + // FTSSEL ., ., . SVE_BK_3A 00000100xx1mmmmm 101100nnnnnddddd 0420 B000 + + +// enum name info SVE_BL_1A +INST1(cntb, "cntb", 0, IF_SVE_BL_1A, 0x0420E000 ) + // CNTB {, {, MUL #}} SVE_BL_1A 000001000010iiii 111000pppppddddd 0420 E000 + +INST1(cntd, "cntd", 0, IF_SVE_BL_1A, 0x04E0E000 ) + // CNTD {, {, MUL #}} SVE_BL_1A 000001001110iiii 111000pppppddddd 04E0 E000 + +INST1(cnth, "cnth", 0, IF_SVE_BL_1A, 0x0460E000 ) + // CNTH {, {, MUL #}} SVE_BL_1A 000001000110iiii 111000pppppddddd 0460 E000 + +INST1(cntw, "cntw", 0, IF_SVE_BL_1A, 0x04A0E000 ) + // CNTW {, {, MUL #}} SVE_BL_1A 000001001010iiii 111000pppppddddd 04A0 E000 + + +// enum name info SVE_BM_1A +INST1(decb, "decb", 0, IF_SVE_BM_1A, 0x0430E400 ) + // DECB {, {, MUL #}} SVE_BM_1A 000001000011iiii 111001pppppddddd 0430 E400 + +INST1(incb, "incb", 0, IF_SVE_BM_1A, 0x0430E000 ) + // INCB {, {, MUL #}} SVE_BM_1A 000001000011iiii 111000pppppddddd 0430 E000 + + +// enum name info SVE_BO_1A +INST1(sqdecb, "sqdecb", 0, IF_SVE_BO_1A, 0x0420F800 ) + // SQDECB , {, {, MUL #}} SVE_BO_1A 00000100001Xiiii 111110pppppddddd 0420 F800 + +INST1(sqincb, "sqincb", 0, IF_SVE_BO_1A, 0x0420F000 ) + // SQINCB , {, {, MUL #}} SVE_BO_1A 00000100001Xiiii 111100pppppddddd 0420 F000 + +INST1(uqdecb, "uqdecb", 0, IF_SVE_BO_1A, 0x0420FC00 ) + // UQDECB {, {, MUL #}} SVE_BO_1A 00000100001Xiiii 111111pppppddddd 0420 FC00 + +INST1(uqincb, "uqincb", 0, IF_SVE_BO_1A, 0x0420F400 ) + // UQINCB {, {, MUL #}} SVE_BO_1A 00000100001Xiiii 111101pppppddddd 0420 F400 + + +// enum name info SVE_BT_1A +INST1(dupm, "dupm", 0, IF_SVE_BT_1A, 0x05C00000 ) + // DUPM ., # SVE_BT_1A 00000101110000ii iiiiiiiiiiiddddd 05C0 0000 + + +// enum name info SVE_BU_2A +INST1(fcpy, "fcpy", 0, IF_SVE_BU_2A, 0x0510C000 ) + // FCPY ., /M, # SVE_BU_2A 00000101xx01gggg 110iiiiiiiiddddd 0510 C000 + + +// enum name info SVE_BX_2A +INST1(dupq, "dupq", 0, IF_SVE_BX_2A, 0x05202400 ) + // DUPQ ., .[] SVE_BX_2A 00000101001ixxxx 001001nnnnnddddd 0520 2400 + + +// enum name info SVE_BY_2A +INST1(extq, "extq", 0, IF_SVE_BY_2A, 0x05602400 ) + // EXTQ .B, .B, .B, # SVE_BY_2A 000001010110iiii 001001mmmmmddddd 0560 2400 + + +// enum name info SVE_CA_3A +INST1(tbxq, "tbxq", 0, IF_SVE_CA_3A, 0x05203400 ) + // TBXQ ., ., . SVE_CA_3A 00000101xx1mmmmm 001101nnnnnddddd 0520 3400 + + +// enum name info SVE_CH_2A +INST1(sunpkhi, "sunpkhi", 0, IF_SVE_CH_2A, 0x05313800 ) + // SUNPKHI ., . SVE_CH_2A 00000101xx110001 001110nnnnnddddd 0531 3800 + +INST1(sunpklo, "sunpklo", 0, IF_SVE_CH_2A, 0x05303800 ) + // SUNPKLO ., . SVE_CH_2A 00000101xx110000 001110nnnnnddddd 0530 3800 + +INST1(uunpkhi, "uunpkhi", 0, IF_SVE_CH_2A, 0x05333800 ) + // UUNPKHI ., . SVE_CH_2A 00000101xx110011 001110nnnnnddddd 0533 3800 + +INST1(uunpklo, "uunpklo", 0, IF_SVE_CH_2A, 0x05323800 ) + // UUNPKLO ., . SVE_CH_2A 00000101xx110010 001110nnnnnddddd 0532 3800 + + +// enum name info SVE_CK_2A +INST1(punpkhi, "punpkhi", 0, IF_SVE_CK_2A, 0x05314000 ) + // PUNPKHI .H, .B SVE_CK_2A 0000010100110001 0100000NNNN0DDDD 0531 4000 + +INST1(punpklo, "punpklo", 0, IF_SVE_CK_2A, 0x05304000 ) + // PUNPKLO .H, .B SVE_CK_2A 0000010100110000 0100000NNNN0DDDD 0530 4000 + + +// enum name info SVE_CL_3A +INST1(compact, "compact", 0, IF_SVE_CL_3A, 0x05218000 ) + // COMPACT ., , . SVE_CL_3A 00000101xx100001 100gggnnnnnddddd 0521 8000 + + +// enum name info SVE_CT_3A +INST1(revd, "revd", 0, IF_SVE_CT_3A, 0x052E8000 ) + // REVD .Q, /M, .Q SVE_CT_3A 0000010100101110 100gggnnnnnddddd 052E 8000 + + +// enum name info SVE_DA_4A +INST1(brkpa, "brkpa", 0, IF_SVE_DA_4A, 0x2500C000 ) + // BRKPA .B, /Z, .B, .B SVE_DA_4A 001001010000MMMM 11gggg0NNNN0DDDD 2500 C000 + +INST1(brkpas, "brkpas", 0, IF_SVE_DA_4A, 0x2540C000 ) + // BRKPAS .B, /Z, .B, .B SVE_DA_4A 001001010100MMMM 11gggg0NNNN0DDDD 2540 C000 + +INST1(brkpb, "brkpb", 0, IF_SVE_DA_4A, 0x2500C010 ) + // BRKPB .B, /Z, .B, .B SVE_DA_4A 001001010000MMMM 11gggg0NNNN1DDDD 2500 C010 + +INST1(brkpbs, "brkpbs", 0, IF_SVE_DA_4A, 0x2540C010 ) + // BRKPBS .B, /Z, .B, .B SVE_DA_4A 001001010100MMMM 11gggg0NNNN1DDDD 2540 C010 + + +// enum name info SVE_DB_3A +INST1(brka, "brka", 0, IF_SVE_DB_3A, 0x25104000 ) + // BRKA .B, /, .B SVE_DB_3A 0010010100010000 01gggg0NNNNMDDDD 2510 4000 + +INST1(brkb, "brkb", 0, IF_SVE_DB_3A, 0x25904000 ) + // BRKB .B, /, .B SVE_DB_3A 0010010110010000 01gggg0NNNNMDDDD 2590 4000 + + +// enum name info SVE_DB_3B +INST1(brkas, "brkas", 0, IF_SVE_DB_3B, 0x25504000 ) + // BRKAS .B, /Z, .B SVE_DB_3B 0010010101010000 01gggg0NNNN0DDDD 2550 4000 + +INST1(brkbs, "brkbs", 0, IF_SVE_DB_3B, 0x25D04000 ) + // BRKBS .B, /Z, .B SVE_DB_3B 0010010111010000 01gggg0NNNN0DDDD 25D0 4000 + + +// enum name info SVE_DC_3A +INST1(brkn, "brkn", 0, IF_SVE_DC_3A, 0x25184000 ) + // BRKN .B, /Z, .B, .B SVE_DC_3A 0010010100011000 01gggg0NNNN0MMMM 2518 4000 + +INST1(brkns, "brkns", 0, IF_SVE_DC_3A, 0x25584000 ) + // BRKNS .B, /Z, .B, .B SVE_DC_3A 0010010101011000 01gggg0NNNN0MMMM 2558 4000 + + +// enum name info SVE_DD_2A +INST1(pfirst, "pfirst", 0, IF_SVE_DD_2A, 0x2558C000 ) + // PFIRST .B, , .B SVE_DD_2A 0010010101011000 1100000gggg0DDDD 2558 C000 + + +// enum name info SVE_DE_1A +INST1(ptrues, "ptrues", 0, IF_SVE_DE_1A, 0x2519E000 ) + // PTRUES .{, } SVE_DE_1A 00100101xx011001 111000ppppp0DDDD 2519 E000 + + +// enum name info SVE_DF_2A +INST1(pnext, "pnext", 0, IF_SVE_DF_2A, 0x2519C400 ) + // PNEXT ., , . SVE_DF_2A 00100101xx011001 1100010VVVV0DDDD 2519 C400 + + +// enum name info SVE_DG_2A +INST1(rdffrs, "rdffrs", 0, IF_SVE_DG_2A, 0x2558F000 ) + // RDFFRS .B, /Z SVE_DG_2A 0010010101011000 1111000gggg0DDDD 2558 F000 + + +// enum name info SVE_DI_2A +INST1(ptest, "ptest", 0, IF_SVE_DI_2A, 0x2550C000 ) + // PTEST , .B SVE_DI_2A 0010010101010000 11gggg0NNNN00000 2550 C000 + + +// enum name info SVE_DJ_1A +INST1(pfalse, "pfalse", 0, IF_SVE_DJ_1A, 0x2518E400 ) + // PFALSE .B SVE_DJ_1A 0010010100011000 111001000000DDDD 2518 E400 + + +// enum name info SVE_DQ_0A +INST1(setffr, "setffr", 0, IF_SVE_DQ_0A, 0x252C9000 ) + // SETFFR SVE_DQ_0A 0010010100101100 1001000000000000 252C 9000 + + +// enum name info SVE_DR_1A +INST1(wrffr, "wrffr", 0, IF_SVE_DR_1A, 0x25289000 ) + // WRFFR .B SVE_DR_1A 0010010100101000 1001000NNNN00000 2528 9000 + + +// enum name info SVE_DS_2A +INST1(ctermeq, "ctermeq", 0, IF_SVE_DS_2A, 0x25A02000 ) + // CTERMEQ , SVE_DS_2A 001001011x1mmmmm 001000nnnnn00000 25A0 2000 + +INST1(ctermne, "ctermne", 0, IF_SVE_DS_2A, 0x25A02010 ) + // CTERMNE , SVE_DS_2A 001001011x1mmmmm 001000nnnnn10000 25A0 2010 + + +// enum name info SVE_DU_3A +INST1(whilerw, "whilerw", 0, IF_SVE_DU_3A, 0x25203010 ) + // WHILERW ., , SVE_DU_3A 00100101xx1mmmmm 001100nnnnn1DDDD 2520 3010 + +INST1(whilewr, "whilewr", 0, IF_SVE_DU_3A, 0x25203000 ) + // WHILEWR ., , SVE_DU_3A 00100101xx1mmmmm 001100nnnnn0DDDD 2520 3000 + + +// enum name info SVE_DV_4A +INST1(psel, "psel", 0, IF_SVE_DV_4A, 0x25204000 ) + // PSEL , , .[, ] SVE_DV_4A 00100101ix1xxxvv 01NNNN0MMMM0DDDD 2520 4000 + + +// enum name info SVE_EA_1A +INST1(fdup, "fdup", 0, IF_SVE_EA_1A, 0x2539C000 ) + // FDUP ., # SVE_EA_1A 00100101xx111001 110iiiiiiiiddddd 2539 C000 + + +// enum name info SVE_EN_3A +INST1(sqdmlalbt, "sqdmlalbt", 0, IF_SVE_EN_3A, 0x44000800 ) + // SQDMLALBT ., ., . SVE_EN_3A 01000100xx0mmmmm 000010nnnnnddddd 4400 0800 + +INST1(sqdmlslbt, "sqdmlslbt", 0, IF_SVE_EN_3A, 0x44000C00 ) + // SQDMLSLBT ., ., . SVE_EN_3A 01000100xx0mmmmm 000011nnnnnddddd 4400 0C00 + + +// enum name info SVE_EV_3A +INST1(sclamp, "sclamp", 0, IF_SVE_EV_3A, 0x4400C000 ) + // SCLAMP ., ., . SVE_EV_3A 01000100xx0mmmmm 110000nnnnnddddd 4400 C000 + +INST1(uclamp, "uclamp", 0, IF_SVE_EV_3A, 0x4400C400 ) + // UCLAMP ., ., . SVE_EV_3A 01000100xx0mmmmm 110001nnnnnddddd 4400 C400 + + +// enum name info SVE_EW_3A +INST1(mlapt, "mlapt", 0, IF_SVE_EW_3A, 0x44C0D000 ) + // MLAPT .D, .D, .D SVE_EW_3A 01000100110mmmmm 110100nnnnnddddd 44C0 D000 + + +// enum name info SVE_EW_3B +INST1(madpt, "madpt", 0, IF_SVE_EW_3B, 0x44C0D800 ) + // MADPT .D, .D, .D SVE_EW_3B 01000100110mmmmm 110110aaaaaddddd 44C0 D800 + + +// enum name info SVE_EX_3A +INST1(tblq, "tblq", 0, IF_SVE_EX_3A, 0x4400F800 ) + // TBLQ ., {.}, . SVE_EX_3A 01000100xx0mmmmm 111110nnnnnddddd 4400 F800 + +INST1(uzpq1, "uzpq1", 0, IF_SVE_EX_3A, 0x4400E800 ) + // UZPQ1 ., ., . SVE_EX_3A 01000100xx0mmmmm 111010nnnnnddddd 4400 E800 + +INST1(uzpq2, "uzpq2", 0, IF_SVE_EX_3A, 0x4400EC00 ) + // UZPQ2 ., ., . SVE_EX_3A 01000100xx0mmmmm 111011nnnnnddddd 4400 EC00 + +INST1(zipq1, "zipq1", 0, IF_SVE_EX_3A, 0x4400E000 ) + // ZIPQ1 ., ., . SVE_EX_3A 01000100xx0mmmmm 111000nnnnnddddd 4400 E000 + +INST1(zipq2, "zipq2", 0, IF_SVE_EX_3A, 0x4400E400 ) + // ZIPQ2 ., ., . SVE_EX_3A 01000100xx0mmmmm 111001nnnnnddddd 4400 E400 + + +// enum name info SVE_FL_3A +INST1(sabdlb, "sabdlb", 0, IF_SVE_FL_3A, 0x45003000 ) + // SABDLB ., ., . SVE_FL_3A 01000101xx0mmmmm 001100nnnnnddddd 4500 3000 + +INST1(sabdlt, "sabdlt", 0, IF_SVE_FL_3A, 0x45003400 ) + // SABDLT ., ., . SVE_FL_3A 01000101xx0mmmmm 001101nnnnnddddd 4500 3400 + +INST1(saddlb, "saddlb", 0, IF_SVE_FL_3A, 0x45000000 ) + // SADDLB ., ., . SVE_FL_3A 01000101xx0mmmmm 000000nnnnnddddd 4500 0000 + +INST1(saddlt, "saddlt", 0, IF_SVE_FL_3A, 0x45000400 ) + // SADDLT ., ., . SVE_FL_3A 01000101xx0mmmmm 000001nnnnnddddd 4500 0400 + +INST1(ssublb, "ssublb", 0, IF_SVE_FL_3A, 0x45001000 ) + // SSUBLB ., ., . SVE_FL_3A 01000101xx0mmmmm 000100nnnnnddddd 4500 1000 + +INST1(ssublt, "ssublt", 0, IF_SVE_FL_3A, 0x45001400 ) + // SSUBLT ., ., . SVE_FL_3A 01000101xx0mmmmm 000101nnnnnddddd 4500 1400 + +INST1(uabdlb, "uabdlb", 0, IF_SVE_FL_3A, 0x45003800 ) + // UABDLB ., ., . SVE_FL_3A 01000101xx0mmmmm 001110nnnnnddddd 4500 3800 + +INST1(uabdlt, "uabdlt", 0, IF_SVE_FL_3A, 0x45003C00 ) + // UABDLT ., ., . SVE_FL_3A 01000101xx0mmmmm 001111nnnnnddddd 4500 3C00 + +INST1(uaddlb, "uaddlb", 0, IF_SVE_FL_3A, 0x45000800 ) + // UADDLB ., ., . SVE_FL_3A 01000101xx0mmmmm 000010nnnnnddddd 4500 0800 + +INST1(uaddlt, "uaddlt", 0, IF_SVE_FL_3A, 0x45000C00 ) + // UADDLT ., ., . SVE_FL_3A 01000101xx0mmmmm 000011nnnnnddddd 4500 0C00 + +INST1(usublb, "usublb", 0, IF_SVE_FL_3A, 0x45001800 ) + // USUBLB ., ., . SVE_FL_3A 01000101xx0mmmmm 000110nnnnnddddd 4500 1800 + +INST1(usublt, "usublt", 0, IF_SVE_FL_3A, 0x45001C00 ) + // USUBLT ., ., . SVE_FL_3A 01000101xx0mmmmm 000111nnnnnddddd 4500 1C00 + + +// enum name info SVE_FM_3A +INST1(saddwb, "saddwb", 0, IF_SVE_FM_3A, 0x45004000 ) + // SADDWB ., ., . SVE_FM_3A 01000101xx0mmmmm 010000nnnnnddddd 4500 4000 + +INST1(saddwt, "saddwt", 0, IF_SVE_FM_3A, 0x45004400 ) + // SADDWT ., ., . SVE_FM_3A 01000101xx0mmmmm 010001nnnnnddddd 4500 4400 + +INST1(ssubwb, "ssubwb", 0, IF_SVE_FM_3A, 0x45005000 ) + // SSUBWB ., ., . SVE_FM_3A 01000101xx0mmmmm 010100nnnnnddddd 4500 5000 + +INST1(ssubwt, "ssubwt", 0, IF_SVE_FM_3A, 0x45005400 ) + // SSUBWT ., ., . SVE_FM_3A 01000101xx0mmmmm 010101nnnnnddddd 4500 5400 + +INST1(uaddwb, "uaddwb", 0, IF_SVE_FM_3A, 0x45004800 ) + // UADDWB ., ., . SVE_FM_3A 01000101xx0mmmmm 010010nnnnnddddd 4500 4800 + +INST1(uaddwt, "uaddwt", 0, IF_SVE_FM_3A, 0x45004C00 ) + // UADDWT ., ., . SVE_FM_3A 01000101xx0mmmmm 010011nnnnnddddd 4500 4C00 + +INST1(usubwb, "usubwb", 0, IF_SVE_FM_3A, 0x45005800 ) + // USUBWB ., ., . SVE_FM_3A 01000101xx0mmmmm 010110nnnnnddddd 4500 5800 + +INST1(usubwt, "usubwt", 0, IF_SVE_FM_3A, 0x45005C00 ) + // USUBWT ., ., . SVE_FM_3A 01000101xx0mmmmm 010111nnnnnddddd 4500 5C00 + + +// enum name info SVE_FP_3A +INST1(eorbt, "eorbt", 0, IF_SVE_FP_3A, 0x45009000 ) + // EORBT ., ., . SVE_FP_3A 01000101xx0mmmmm 100100nnnnnddddd 4500 9000 + +INST1(eortb, "eortb", 0, IF_SVE_FP_3A, 0x45009400 ) + // EORTB ., ., . SVE_FP_3A 01000101xx0mmmmm 100101nnnnnddddd 4500 9400 + + +// enum name info SVE_FQ_3A +INST1(bdep, "bdep", 0, IF_SVE_FQ_3A, 0x4500B400 ) + // BDEP ., ., . SVE_FQ_3A 01000101xx0mmmmm 101101nnnnnddddd 4500 B400 + +INST1(bext, "bext", 0, IF_SVE_FQ_3A, 0x4500B000 ) + // BEXT ., ., . SVE_FQ_3A 01000101xx0mmmmm 101100nnnnnddddd 4500 B000 + +INST1(bgrp, "bgrp", 0, IF_SVE_FQ_3A, 0x4500B800 ) + // BGRP ., ., . SVE_FQ_3A 01000101xx0mmmmm 101110nnnnnddddd 4500 B800 + + +// enum name info SVE_FR_2A +INST1(sshllb, "sshllb", 0, IF_SVE_FR_2A, 0x4500A000 ) + // SSHLLB ., ., # SVE_FR_2A 010001010x0xxiii 101000nnnnnddddd 4500 A000 + +INST1(sshllt, "sshllt", 0, IF_SVE_FR_2A, 0x4500A400 ) + // SSHLLT ., ., # SVE_FR_2A 010001010x0xxiii 101001nnnnnddddd 4500 A400 + +INST1(ushllb, "ushllb", 0, IF_SVE_FR_2A, 0x4500A800 ) + // USHLLB ., ., # SVE_FR_2A 010001010x0xxiii 101010nnnnnddddd 4500 A800 + +INST1(ushllt, "ushllt", 0, IF_SVE_FR_2A, 0x4500AC00 ) + // USHLLT ., ., # SVE_FR_2A 010001010x0xxiii 101011nnnnnddddd 4500 AC00 + + +// enum name info SVE_FS_3A +INST1(saddlbt, "saddlbt", 0, IF_SVE_FS_3A, 0x45008000 ) + // SADDLBT ., ., . SVE_FS_3A 01000101xx0mmmmm 100000nnnnnddddd 4500 8000 + +INST1(ssublbt, "ssublbt", 0, IF_SVE_FS_3A, 0x45008800 ) + // SSUBLBT ., ., . SVE_FS_3A 01000101xx0mmmmm 100010nnnnnddddd 4500 8800 + +INST1(ssubltb, "ssubltb", 0, IF_SVE_FS_3A, 0x45008C00 ) + // SSUBLTB ., ., . SVE_FS_3A 01000101xx0mmmmm 100011nnnnnddddd 4500 8C00 + + +// enum name info SVE_FV_2A +INST1(cadd, "cadd", 0, IF_SVE_FV_2A, 0x4500D800 ) + // CADD ., ., ., SVE_FV_2A 01000101xx000000 11011rmmmmmddddd 4500 D800 + +INST1(sqcadd, "sqcadd", 0, IF_SVE_FV_2A, 0x4501D800 ) + // SQCADD ., ., ., SVE_FV_2A 01000101xx000001 11011rmmmmmddddd 4501 D800 + + +// enum name info SVE_FX_3A +INST1(sabalb, "sabalb", 0, IF_SVE_FX_3A, 0x4500C000 ) + // SABALB ., ., . SVE_FX_3A 01000101xx0mmmmm 110000nnnnnddddd 4500 C000 + +INST1(sabalt, "sabalt", 0, IF_SVE_FX_3A, 0x4500C400 ) + // SABALT ., ., . SVE_FX_3A 01000101xx0mmmmm 110001nnnnnddddd 4500 C400 + +INST1(uabalb, "uabalb", 0, IF_SVE_FX_3A, 0x4500C800 ) + // UABALB ., ., . SVE_FX_3A 01000101xx0mmmmm 110010nnnnnddddd 4500 C800 + +INST1(uabalt, "uabalt", 0, IF_SVE_FX_3A, 0x4500CC00 ) + // UABALT ., ., . SVE_FX_3A 01000101xx0mmmmm 110011nnnnnddddd 4500 CC00 + + +// enum name info SVE_FY_3A +INST1(adclb, "adclb", 0, IF_SVE_FY_3A, 0x4500D000 ) + // ADCLB ., ., . SVE_FY_3A 010001010x0mmmmm 110100nnnnnddddd 4500 D000 + +INST1(adclt, "adclt", 0, IF_SVE_FY_3A, 0x4500D400 ) + // ADCLT ., ., . SVE_FY_3A 010001010x0mmmmm 110101nnnnnddddd 4500 D400 + +INST1(sbclb, "sbclb", 0, IF_SVE_FY_3A, 0x4580D000 ) + // SBCLB ., ., . SVE_FY_3A 010001011x0mmmmm 110100nnnnnddddd 4580 D000 + +INST1(sbclt, "sbclt", 0, IF_SVE_FY_3A, 0x4580D400 ) + // SBCLT ., ., . SVE_FY_3A 010001011x0mmmmm 110101nnnnnddddd 4580 D400 + + +// enum name info SVE_FZ_2A +INST1(sqcvtn, "sqcvtn", 0, IF_SVE_FZ_2A, 0x45314000 ) + // SQCVTN .H, {.S-.S } SVE_FZ_2A 0100010100110001 010000nnnn0ddddd 4531 4000 + +INST1(sqcvtun, "sqcvtun", 0, IF_SVE_FZ_2A, 0x45315000 ) + // SQCVTUN .H, {.S-.S } SVE_FZ_2A 0100010100110001 010100nnnn0ddddd 4531 5000 + +INST1(uqcvtn, "uqcvtn", 0, IF_SVE_FZ_2A, 0x45314800 ) + // UQCVTN .H, {.S-.S } SVE_FZ_2A 0100010100110001 010010nnnn0ddddd 4531 4800 + + +// enum name info SVE_GB_2A +INST1(rshrnb, "rshrnb", 0, IF_SVE_GB_2A, 0x45201800 ) + // RSHRNB ., ., # SVE_GB_2A 010001010x1xxiii 000110nnnnnddddd 4520 1800 + +INST1(rshrnt, "rshrnt", 0, IF_SVE_GB_2A, 0x45201C00 ) + // RSHRNT ., ., # SVE_GB_2A 010001010x1xxiii 000111nnnnnddddd 4520 1C00 + +INST1(shrnb, "shrnb", 0, IF_SVE_GB_2A, 0x45201000 ) + // SHRNB ., ., # SVE_GB_2A 010001010x1xxiii 000100nnnnnddddd 4520 1000 + +INST1(shrnt, "shrnt", 0, IF_SVE_GB_2A, 0x45201400 ) + // SHRNT ., ., # SVE_GB_2A 010001010x1xxiii 000101nnnnnddddd 4520 1400 + +INST1(sqrshrnb, "sqrshrnb", 0, IF_SVE_GB_2A, 0x45202800 ) + // SQRSHRNB ., ., # SVE_GB_2A 010001010x1xxiii 001010nnnnnddddd 4520 2800 + +INST1(sqrshrnt, "sqrshrnt", 0, IF_SVE_GB_2A, 0x45202C00 ) + // SQRSHRNT ., ., # SVE_GB_2A 010001010x1xxiii 001011nnnnnddddd 4520 2C00 + +INST1(sqrshrunb, "sqrshrunb", 0, IF_SVE_GB_2A, 0x45200800 ) + // SQRSHRUNB ., ., # SVE_GB_2A 010001010x1xxiii 000010nnnnnddddd 4520 0800 + +INST1(sqrshrunt, "sqrshrunt", 0, IF_SVE_GB_2A, 0x45200C00 ) + // SQRSHRUNT ., ., # SVE_GB_2A 010001010x1xxiii 000011nnnnnddddd 4520 0C00 + +INST1(sqshrnb, "sqshrnb", 0, IF_SVE_GB_2A, 0x45202000 ) + // SQSHRNB ., ., # SVE_GB_2A 010001010x1xxiii 001000nnnnnddddd 4520 2000 + +INST1(sqshrnt, "sqshrnt", 0, IF_SVE_GB_2A, 0x45202400 ) + // SQSHRNT ., ., # SVE_GB_2A 010001010x1xxiii 001001nnnnnddddd 4520 2400 + +INST1(sqshrunb, "sqshrunb", 0, IF_SVE_GB_2A, 0x45200000 ) + // SQSHRUNB ., ., # SVE_GB_2A 010001010x1xxiii 000000nnnnnddddd 4520 0000 + +INST1(sqshrunt, "sqshrunt", 0, IF_SVE_GB_2A, 0x45200400 ) + // SQSHRUNT ., ., # SVE_GB_2A 010001010x1xxiii 000001nnnnnddddd 4520 0400 + +INST1(uqrshrnb, "uqrshrnb", 0, IF_SVE_GB_2A, 0x45203800 ) + // UQRSHRNB ., ., # SVE_GB_2A 010001010x1xxiii 001110nnnnnddddd 4520 3800 + +INST1(uqrshrnt, "uqrshrnt", 0, IF_SVE_GB_2A, 0x45203C00 ) + // UQRSHRNT ., ., # SVE_GB_2A 010001010x1xxiii 001111nnnnnddddd 4520 3C00 + +INST1(uqshrnb, "uqshrnb", 0, IF_SVE_GB_2A, 0x45203000 ) + // UQSHRNB ., ., # SVE_GB_2A 010001010x1xxiii 001100nnnnnddddd 4520 3000 + +INST1(uqshrnt, "uqshrnt", 0, IF_SVE_GB_2A, 0x45203400 ) + // UQSHRNT ., ., # SVE_GB_2A 010001010x1xxiii 001101nnnnnddddd 4520 3400 + + +// enum name info SVE_GC_3A +INST1(addhnb, "addhnb", 0, IF_SVE_GC_3A, 0x45206000 ) + // ADDHNB ., ., . SVE_GC_3A 01000101xx1mmmmm 011000nnnnnddddd 4520 6000 + +INST1(addhnt, "addhnt", 0, IF_SVE_GC_3A, 0x45206400 ) + // ADDHNT ., ., . SVE_GC_3A 01000101xx1mmmmm 011001nnnnnddddd 4520 6400 + +INST1(raddhnb, "raddhnb", 0, IF_SVE_GC_3A, 0x45206800 ) + // RADDHNB ., ., . SVE_GC_3A 01000101xx1mmmmm 011010nnnnnddddd 4520 6800 + +INST1(raddhnt, "raddhnt", 0, IF_SVE_GC_3A, 0x45206C00 ) + // RADDHNT ., ., . SVE_GC_3A 01000101xx1mmmmm 011011nnnnnddddd 4520 6C00 + +INST1(rsubhnb, "rsubhnb", 0, IF_SVE_GC_3A, 0x45207800 ) + // RSUBHNB ., ., . SVE_GC_3A 01000101xx1mmmmm 011110nnnnnddddd 4520 7800 + +INST1(rsubhnt, "rsubhnt", 0, IF_SVE_GC_3A, 0x45207C00 ) + // RSUBHNT ., ., . SVE_GC_3A 01000101xx1mmmmm 011111nnnnnddddd 4520 7C00 + +INST1(subhnb, "subhnb", 0, IF_SVE_GC_3A, 0x45207000 ) + // SUBHNB ., ., . SVE_GC_3A 01000101xx1mmmmm 011100nnnnnddddd 4520 7000 + +INST1(subhnt, "subhnt", 0, IF_SVE_GC_3A, 0x45207400 ) + // SUBHNT ., ., . SVE_GC_3A 01000101xx1mmmmm 011101nnnnnddddd 4520 7400 + + +// enum name info SVE_GD_2A +INST1(sqxtnb, "sqxtnb", 0, IF_SVE_GD_2A, 0x45204000 ) + // SQXTNB ., . SVE_GD_2A 010001010x1xx000 010000nnnnnddddd 4520 4000 + +INST1(sqxtnt, "sqxtnt", 0, IF_SVE_GD_2A, 0x45204400 ) + // SQXTNT ., . SVE_GD_2A 010001010x1xx000 010001nnnnnddddd 4520 4400 + +INST1(sqxtunb, "sqxtunb", 0, IF_SVE_GD_2A, 0x45205000 ) + // SQXTUNB ., . SVE_GD_2A 010001010x1xx000 010100nnnnnddddd 4520 5000 + +INST1(sqxtunt, "sqxtunt", 0, IF_SVE_GD_2A, 0x45205400 ) + // SQXTUNT ., . SVE_GD_2A 010001010x1xx000 010101nnnnnddddd 4520 5400 + +INST1(uqxtnb, "uqxtnb", 0, IF_SVE_GD_2A, 0x45204800 ) + // UQXTNB ., . SVE_GD_2A 010001010x1xx000 010010nnnnnddddd 4520 4800 + +INST1(uqxtnt, "uqxtnt", 0, IF_SVE_GD_2A, 0x45204C00 ) + // UQXTNT ., . SVE_GD_2A 010001010x1xx000 010011nnnnnddddd 4520 4C00 + + +// enum name info SVE_GE_4A +INST1(match, "match", 0, IF_SVE_GE_4A, 0x45208000 ) + // MATCH ., /Z, ., . SVE_GE_4A 01000101xx1mmmmm 100gggnnnnn0DDDD 4520 8000 + +INST1(nmatch, "nmatch", 0, IF_SVE_GE_4A, 0x45208010 ) + // NMATCH ., /Z, ., . SVE_GE_4A 01000101xx1mmmmm 100gggnnnnn1DDDD 4520 8010 + + +// enum name info SVE_GF_3A +INST1(histseg, "histseg", 0, IF_SVE_GF_3A, 0x4520A000 ) + // HISTSEG .B, .B, .B SVE_GF_3A 01000101xx1mmmmm 101000nnnnnddddd 4520 A000 + + +// enum name info SVE_GI_4A +INST1(histcnt, "histcnt", 0, IF_SVE_GI_4A, 0x4520C000 ) + // HISTCNT ., /Z, ., . SVE_GI_4A 01000101xx1mmmmm 110gggnnnnnddddd 4520 C000 + + +// enum name info SVE_GQ_3A +INST1(bfcvtnt, "bfcvtnt", 0, IF_SVE_GQ_3A, 0x648AA000 ) + // BFCVTNT .H, /M, .S SVE_GQ_3A 0110010010001010 101gggnnnnnddddd 648A A000 + +INST1(fcvtlt, "fcvtlt", 0, IF_SVE_GQ_3A, 0x64CBA000 ) + // FCVTLT .D, /M, .S SVE_GQ_3A 0110010011001011 101gggnnnnnddddd 64CB A000 + +INST1(fcvtxnt, "fcvtxnt", 0, IF_SVE_GQ_3A, 0x640AA000 ) + // FCVTXNT .S, /M, .D SVE_GQ_3A 0110010000001010 101gggnnnnnddddd 640A A000 + + +// enum name info SVE_GS_3A +INST1(faddqv, "faddqv", 0, IF_SVE_GS_3A, 0x6410A000 ) + // FADDQV ., , . SVE_GS_3A 01100100xx010000 101gggnnnnnddddd 6410 A000 + +INST1(fmaxnmqv, "fmaxnmqv", 0, IF_SVE_GS_3A, 0x6414A000 ) + // FMAXNMQV ., , . SVE_GS_3A 01100100xx010100 101gggnnnnnddddd 6414 A000 + +INST1(fmaxqv, "fmaxqv", 0, IF_SVE_GS_3A, 0x6416A000 ) + // FMAXQV ., , . SVE_GS_3A 01100100xx010110 101gggnnnnnddddd 6416 A000 + +INST1(fminnmqv, "fminnmqv", 0, IF_SVE_GS_3A, 0x6415A000 ) + // FMINNMQV ., , . SVE_GS_3A 01100100xx010101 101gggnnnnnddddd 6415 A000 + +INST1(fminqv, "fminqv", 0, IF_SVE_GS_3A, 0x6417A000 ) + // FMINQV ., , . SVE_GS_3A 01100100xx010111 101gggnnnnnddddd 6417 A000 + + +// enum name info SVE_GW_3A +INST1(fclamp, "fclamp", 0, IF_SVE_GW_3A, 0x64202400 ) + // FCLAMP ., ., . SVE_GW_3A 01100100xx1mmmmm 001001nnnnnddddd 6420 2400 + + +// enum name info SVE_GW_3B +INST1(bfclamp, "bfclamp", 0, IF_SVE_GW_3B, 0x64202400 ) + // BFCLAMP .H, .H, .H SVE_GW_3B 01100100001mmmmm 001001nnnnnddddd 6420 2400 + + +// enum name info SVE_HD_3A_A +INST1(fmmla, "fmmla", 0, IF_SVE_HD_3A_A, 0x64A0E400 ) + // FMMLA .D, .D, .D SVE_HD_3A_A 01100100101mmmmm 111001nnnnnddddd 64A0 E400 + + +// enum name info SVE_HH_2A +INST1(bf1cvt, "bf1cvt", 0, IF_SVE_HH_2A, 0x65083800 ) + // BF1CVT .H, .B SVE_HH_2A 0110010100001000 001110nnnnnddddd 6508 3800 + +INST1(bf1cvtlt, "bf1cvtlt", 0, IF_SVE_HH_2A, 0x65093800 ) + // BF1CVTLT .H, .B SVE_HH_2A 0110010100001001 001110nnnnnddddd 6509 3800 + +INST1(bf2cvt, "bf2cvt", 0, IF_SVE_HH_2A, 0x65083C00 ) + // BF2CVT .H, .B SVE_HH_2A 0110010100001000 001111nnnnnddddd 6508 3C00 + +INST1(bf2cvtlt, "bf2cvtlt", 0, IF_SVE_HH_2A, 0x65093C00 ) + // BF2CVTLT .H, .B SVE_HH_2A 0110010100001001 001111nnnnnddddd 6509 3C00 + +INST1(f1cvt, "f1cvt", 0, IF_SVE_HH_2A, 0x65083000 ) + // F1CVT .H, .B SVE_HH_2A 0110010100001000 001100nnnnnddddd 6508 3000 + +INST1(f1cvtlt, "f1cvtlt", 0, IF_SVE_HH_2A, 0x65093000 ) + // F1CVTLT .H, .B SVE_HH_2A 0110010100001001 001100nnnnnddddd 6509 3000 + +INST1(f2cvt, "f2cvt", 0, IF_SVE_HH_2A, 0x65083400 ) + // F2CVT .H, .B SVE_HH_2A 0110010100001000 001101nnnnnddddd 6508 3400 + +INST1(f2cvtlt, "f2cvtlt", 0, IF_SVE_HH_2A, 0x65093400 ) + // F2CVTLT .H, .B SVE_HH_2A 0110010100001001 001101nnnnnddddd 6509 3400 + + +// enum name info SVE_HJ_3A +INST1(fadda, "fadda", 0, IF_SVE_HJ_3A, 0x65182000 ) + // FADDA , , , . SVE_HJ_3A 01100101xx011000 001gggmmmmmddddd 6518 2000 + + +// enum name info SVE_HL_3B +INST1(bfmax, "bfmax", 0, IF_SVE_HL_3B, 0x65068000 ) + // BFMAX .H, /M, .H, .H SVE_HL_3B 0110010100000110 100gggmmmmmddddd 6506 8000 + +INST1(bfmaxnm, "bfmaxnm", 0, IF_SVE_HL_3B, 0x65048000 ) + // BFMAXNM .H, /M, .H, .H SVE_HL_3B 0110010100000100 100gggmmmmmddddd 6504 8000 + +INST1(bfmin, "bfmin", 0, IF_SVE_HL_3B, 0x65078000 ) + // BFMIN .H, /M, .H, .H SVE_HL_3B 0110010100000111 100gggmmmmmddddd 6507 8000 + +INST1(bfminnm, "bfminnm", 0, IF_SVE_HL_3B, 0x65058000 ) + // BFMINNM .H, /M, .H, .H SVE_HL_3B 0110010100000101 100gggmmmmmddddd 6505 8000 + + +// enum name info SVE_HN_2A +INST1(ftmad, "ftmad", 0, IF_SVE_HN_2A, 0x65108000 ) + // FTMAD ., ., ., # SVE_HN_2A 01100101xx010iii 100000mmmmmddddd 6510 8000 + + +// enum name info SVE_HP_3A +INST1(flogb, "flogb", 0, IF_SVE_HP_3A, 0x6518A000 ) + // FLOGB ., /M, . SVE_HP_3A 0110010100011xx0 101gggnnnnnddddd 6518 A000 + + +// enum name info SVE_HU_4A +INST1(fnmla, "fnmla", 0, IF_SVE_HU_4A, 0x65204000 ) + // FNMLA ., /M, ., . SVE_HU_4A 01100101xx1mmmmm 010gggnnnnnddddd 6520 4000 + +INST1(fnmls, "fnmls", 0, IF_SVE_HU_4A, 0x65206000 ) + // FNMLS ., /M, ., . SVE_HU_4A 01100101xx1mmmmm 011gggnnnnnddddd 6520 6000 + + +// enum name info SVE_HV_4A +INST1(fmad, "fmad", 0, IF_SVE_HV_4A, 0x65208000 ) + // FMAD ., /M, ., . SVE_HV_4A 01100101xx1aaaaa 100gggmmmmmddddd 6520 8000 + +INST1(fmsb, "fmsb", 0, IF_SVE_HV_4A, 0x6520A000 ) + // FMSB ., /M, ., . SVE_HV_4A 01100101xx1aaaaa 101gggmmmmmddddd 6520 A000 + +INST1(fnmad, "fnmad", 0, IF_SVE_HV_4A, 0x6520C000 ) + // FNMAD ., /M, ., . SVE_HV_4A 01100101xx1aaaaa 110gggmmmmmddddd 6520 C000 + +INST1(fnmsb, "fnmsb", 0, IF_SVE_HV_4A, 0x6520E000 ) + // FNMSB ., /M, ., . SVE_HV_4A 01100101xx1aaaaa 111gggmmmmmddddd 6520 E000 + + +// enum name info SVE_IC_3A_C +INST1(ld1rb, "ld1rb", 0, IF_SVE_IC_3A_C, 0x84408000 ) + // LD1RB {.D }, /Z, [{, #}] SVE_IC_3A_C 1000010001iiiiii 100gggnnnnnttttt 8440 8000 + + +// enum name info SVE_IC_3A +INST1(ld1rd, "ld1rd", 0, IF_SVE_IC_3A, 0x85C0E000 ) + // LD1RD {.D }, /Z, [{, #}] SVE_IC_3A 1000010111iiiiii 111gggnnnnnttttt 85C0 E000 + +INST1(ld1rsw, "ld1rsw", 0, IF_SVE_IC_3A, 0x84C08000 ) + // LD1RSW {.D }, /Z, [{, #}] SVE_IC_3A 1000010011iiiiii 100gggnnnnnttttt 84C0 8000 + + +// enum name info SVE_IC_3A_B +INST1(ld1rh, "ld1rh", 0, IF_SVE_IC_3A_B, 0x84C08000 ) + // LD1RH {.D }, /Z, [{, #}] SVE_IC_3A_B 1000010011iiiiii 100gggnnnnnttttt 84C0 8000 + +INST1(ld1rsb, "ld1rsb", 0, IF_SVE_IC_3A_B, 0x85C08000 ) + // LD1RSB {.D }, /Z, [{, #}] SVE_IC_3A_B 1000010111iiiiii 100gggnnnnnttttt 85C0 8000 + + +// enum name info SVE_IC_3A_A +INST1(ld1rsh, "ld1rsh", 0, IF_SVE_IC_3A_A, 0x85408000 ) + // LD1RSH {.D }, /Z, [{, #}] SVE_IC_3A_A 1000010101iiiiii 100gggnnnnnttttt 8540 8000 + +INST1(ld1rw, "ld1rw", 0, IF_SVE_IC_3A_A, 0x8540C000 ) + // LD1RW {.D }, /Z, [{, #}] SVE_IC_3A_A 1000010101iiiiii 110gggnnnnnttttt 8540 C000 + + +// enum name info SVE_IL_3A_C +INST1(ldnf1b, "ldnf1b", 0, IF_SVE_IL_3A_C, 0xA410A000 ) + // LDNF1B {.D }, /Z, [{, #, MUL VL}] SVE_IL_3A_C 101001000001iiii 101gggnnnnnttttt A410 A000 + + +// enum name info SVE_IL_3A +INST1(ldnf1d, "ldnf1d", 0, IF_SVE_IL_3A, 0xA5F0A000 ) + // LDNF1D {.D }, /Z, [{, #, MUL VL}] SVE_IL_3A 101001011111iiii 101gggnnnnnttttt A5F0 A000 + +INST1(ldnf1sw, "ldnf1sw", 0, IF_SVE_IL_3A, 0xA490A000 ) + // LDNF1SW {.D }, /Z, [{, #, MUL VL}] SVE_IL_3A 101001001001iiii 101gggnnnnnttttt A490 A000 + + +// enum name info SVE_IL_3A_B +INST1(ldnf1h, "ldnf1h", 0, IF_SVE_IL_3A_B, 0xA490A000 ) + // LDNF1H {.D }, /Z, [{, #, MUL VL}] SVE_IL_3A_B 101001001001iiii 101gggnnnnnttttt A490 A000 + +INST1(ldnf1sb, "ldnf1sb", 0, IF_SVE_IL_3A_B, 0xA590A000 ) + // LDNF1SB {.D }, /Z, [{, #, MUL VL}] SVE_IL_3A_B 101001011001iiii 101gggnnnnnttttt A590 A000 + + +// enum name info SVE_IL_3A_A +INST1(ldnf1sh, "ldnf1sh", 0, IF_SVE_IL_3A_A, 0xA510A000 ) + // LDNF1SH {.D }, /Z, [{, #, MUL VL}] SVE_IL_3A_A 101001010001iiii 101gggnnnnnttttt A510 A000 + +INST1(ldnf1w, "ldnf1w", 0, IF_SVE_IL_3A_A, 0xA550A000 ) + // LDNF1W {.D }, /Z, [{, #, MUL VL}] SVE_IL_3A_A 101001010101iiii 101gggnnnnnttttt A550 A000 + + +// enum name info SVE_IW_4A +INST1(ld1q, "ld1q", 0, IF_SVE_IW_4A, 0xC400A000 ) + // LD1Q {.Q }, /Z, [.D{, }] SVE_IW_4A 11000100000mmmmm 101gggnnnnnttttt C400 A000 + + +// enum name info SVE_IX_4A +INST1(ldnt1sw, "ldnt1sw", 0, IF_SVE_IX_4A, 0xC5008000 ) + // LDNT1SW {.D }, /Z, [.D{, }] SVE_IX_4A 11000101000mmmmm 100gggnnnnnttttt C500 8000 + + +// enum name info SVE_IY_4A +INST1(st1q, "st1q", 0, IF_SVE_IY_4A, 0xE4202000 ) + // ST1Q {.Q }, , [.D{, }] SVE_IY_4A 11100100001mmmmm 001gggnnnnnttttt E420 2000 + +// clang-format on + +/*****************************************************************************/ +#undef INST1 +#undef INST2 +#undef INST3 +#undef INST4 +#undef INST5 +#undef INST6 +#undef INST7 +#undef INST8 +#undef INST9 +#undef INST11 +#undef INST13 diff --git a/src/coreclr/jit/jitconfigvalues.h b/src/coreclr/jit/jitconfigvalues.h index f6460feddec126..d0a422549dcc11 100644 --- a/src/coreclr/jit/jitconfigvalues.h +++ b/src/coreclr/jit/jitconfigvalues.h @@ -351,6 +351,7 @@ CONFIG_INTEGER(EnableArm64Dp, W("EnableArm64Dp"), 1) / CONFIG_INTEGER(EnableArm64Rdm, W("EnableArm64Rdm"), 1) // Allows Arm64 Rdm+ hardware intrinsics to be disabled CONFIG_INTEGER(EnableArm64Sha1, W("EnableArm64Sha1"), 1) // Allows Arm64 Sha1+ hardware intrinsics to be disabled CONFIG_INTEGER(EnableArm64Sha256, W("EnableArm64Sha256"), 1) // Allows Arm64 Sha256+ hardware intrinsics to be disabled +CONFIG_INTEGER(EnableArm64Sve, W("EnableArm64Sve"), 1) // Allows Arm64 Sve+ hardware intrinsics to be disabled #endif // clang-format on diff --git a/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs index 1e778e97c67f3e..c30736fcb6019d 100644 --- a/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs +++ b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs @@ -221,6 +221,7 @@ private static class Arm64IntrinsicConstants public const int Rcpc = 0x0100; public const int VectorT128 = 0x0200; public const int Rcpc2 = 0x0400; + public const int Sve = 0x0800; public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags) { @@ -244,6 +245,8 @@ public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags) builder.AddSupportedInstructionSet("rcpc"); if ((flags & Rcpc2) != 0) builder.AddSupportedInstructionSet("rcpc2"); + if ((flags & Sve) != 0) + builder.AddSupportedInstructionSet("sve"); } public static int FromInstructionSet(InstructionSet instructionSet) @@ -273,6 +276,8 @@ public static int FromInstructionSet(InstructionSet instructionSet) InstructionSet.ARM64_Atomics => Atomics, InstructionSet.ARM64_Rcpc => Rcpc, InstructionSet.ARM64_Rcpc2 => Rcpc2, + InstructionSet.ARM64_Sve => Sve, + InstructionSet.ARM64_Sve_Arm64 => Sve, // Vector Sizes InstructionSet.ARM64_VectorT128 => VectorT128, diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs index 51c1a4854d71f4..284131d1641acc 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs @@ -54,6 +54,7 @@ public enum ReadyToRunInstructionSet VectorT256=40, VectorT512=41, Rcpc2=42, + Sve=43, } } diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs index 57629f66b9c6f5..7000b482ec604a 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs @@ -46,6 +46,8 @@ public static class ReadyToRunInstructionSetHelper case InstructionSet.ARM64_Rcpc: return ReadyToRunInstructionSet.Rcpc; case InstructionSet.ARM64_VectorT128: return ReadyToRunInstructionSet.VectorT128; case InstructionSet.ARM64_Rcpc2: return ReadyToRunInstructionSet.Rcpc2; + case InstructionSet.ARM64_Sve: return ReadyToRunInstructionSet.Sve; + case InstructionSet.ARM64_Sve_Arm64: return ReadyToRunInstructionSet.Sve; default: throw new Exception("Unknown instruction set"); } diff --git a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs index d7bc2e56ebd2a4..a5398c85ca0758 100644 --- a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs +++ b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs @@ -31,6 +31,7 @@ public enum InstructionSet ARM64_Rcpc = InstructionSet_ARM64.Rcpc, ARM64_VectorT128 = InstructionSet_ARM64.VectorT128, ARM64_Rcpc2 = InstructionSet_ARM64.Rcpc2, + ARM64_Sve = InstructionSet_ARM64.Sve, ARM64_ArmBase_Arm64 = InstructionSet_ARM64.ArmBase_Arm64, ARM64_AdvSimd_Arm64 = InstructionSet_ARM64.AdvSimd_Arm64, ARM64_Aes_Arm64 = InstructionSet_ARM64.Aes_Arm64, @@ -39,6 +40,7 @@ public enum InstructionSet ARM64_Rdm_Arm64 = InstructionSet_ARM64.Rdm_Arm64, ARM64_Sha1_Arm64 = InstructionSet_ARM64.Sha1_Arm64, ARM64_Sha256_Arm64 = InstructionSet_ARM64.Sha256_Arm64, + ARM64_Sve_Arm64 = InstructionSet_ARM64.Sve_Arm64, X64_X86Base = InstructionSet_X64.X86Base, X64_SSE = InstructionSet_X64.SSE, X64_SSE2 = InstructionSet_X64.SSE2, @@ -187,14 +189,16 @@ public enum InstructionSet_ARM64 Rcpc = 13, VectorT128 = 14, Rcpc2 = 15, - ArmBase_Arm64 = 16, - AdvSimd_Arm64 = 17, - Aes_Arm64 = 18, - Crc32_Arm64 = 19, - Dp_Arm64 = 20, - Rdm_Arm64 = 21, - Sha1_Arm64 = 22, - Sha256_Arm64 = 23, + Sve = 16, + ArmBase_Arm64 = 17, + AdvSimd_Arm64 = 18, + Aes_Arm64 = 19, + Crc32_Arm64 = 20, + Dp_Arm64 = 21, + Rdm_Arm64 = 22, + Sha1_Arm64 = 23, + Sha256_Arm64 = 24, + Sve_Arm64 = 25, } public enum InstructionSet_X64 @@ -525,6 +529,10 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sha256_Arm64)) resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) resultflags.AddInstructionSet(InstructionSet.ARM64_ArmBase); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Aes)) @@ -545,6 +553,8 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet.ARM64_VectorT128)) resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve)) + resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); break; case TargetArchitecture.X64: @@ -874,6 +884,8 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.ARM64_Sha1); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sha256_Arm64)) resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase)) resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase)) @@ -894,6 +906,8 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.ARM64_Vector128); if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) resultflags.AddInstructionSet(InstructionSet.ARM64_VectorT128); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); break; case TargetArchitecture.X64: @@ -1198,6 +1212,7 @@ public static IEnumerable ArchitectureToValidInstructionSets yield return new InstructionSetInfo("rcpc", "", InstructionSet.ARM64_Rcpc, true); yield return new InstructionSetInfo("vectort128", "VectorT128", InstructionSet.ARM64_VectorT128, true); yield return new InstructionSetInfo("rcpc2", "", InstructionSet.ARM64_Rcpc2, true); + yield return new InstructionSetInfo("sve", "Sve", InstructionSet.ARM64_Sve, true); break; case TargetArchitecture.X64: @@ -1300,6 +1315,8 @@ public void Set64BitInstructionSetVariants(TargetArchitecture architecture) AddInstructionSet(InstructionSet.ARM64_Sha1_Arm64); if (HasInstructionSet(InstructionSet.ARM64_Sha256)) AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); + if (HasInstructionSet(InstructionSet.ARM64_Sve)) + AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); break; case TargetArchitecture.X64: @@ -1382,6 +1399,7 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc AddInstructionSet(InstructionSet.ARM64_Rdm_Arm64); AddInstructionSet(InstructionSet.ARM64_Sha1_Arm64); AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); + AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); break; case TargetArchitecture.X64: @@ -1551,6 +1569,12 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite case "VectorT128": { return InstructionSet.ARM64_VectorT128; } + case "Sve": + if (nestedTypeName == "Arm64") + { return InstructionSet.ARM64_Sve_Arm64; } + else + { return InstructionSet.ARM64_Sve; } + } break; diff --git a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt index ba4db589c81a0f..7b6e15b87bd84a 100644 --- a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt +++ b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt @@ -168,6 +168,7 @@ instructionset ,ARM64 , , , ,Dczva instructionset ,ARM64 , ,Rcpc ,26 ,Rcpc ,rcpc instructionset ,ARM64 ,VectorT128 , ,39 ,VectorT128 ,vectort128 instructionset ,ARM64 , ,Rcpc2 ,42 ,Rcpc2 ,rcpc2 +instructionset ,ARM64 ,Sve , ,43 ,Sve ,sve instructionset64bit,ARM64 ,ArmBase instructionset64bit,ARM64 ,AdvSimd @@ -177,6 +178,7 @@ instructionset64bit,ARM64 ,Dp instructionset64bit,ARM64 ,Rdm instructionset64bit,ARM64 ,Sha1 instructionset64bit,ARM64 ,Sha256 +instructionset64bit,ARM64 ,Sve vectorinstructionset,ARM64,Vector64 vectorinstructionset,ARM64,Vector128 @@ -191,6 +193,7 @@ implication ,ARM64 ,Sha256 ,ArmBase implication ,ARM64 ,Vector64 ,AdvSimd implication ,ARM64 ,Vector128 ,AdvSimd implication ,ARM64 ,VectorT128 ,AdvSimd +implication ,ARM64 ,Sve ,AdvSimd ; ,name and aliases ,archs ,lower baselines included by implication ; diff --git a/src/coreclr/vm/codeman.cpp b/src/coreclr/vm/codeman.cpp index 4dddb619675568..35c1f0cfebc044 100644 --- a/src/coreclr/vm/codeman.cpp +++ b/src/coreclr/vm/codeman.cpp @@ -1511,6 +1511,11 @@ void EEJitManager::SetCpuInfo() CPUCompileFlags.Set(InstructionSet_Sha256); } + if (((cpuFeatures & ARM64IntrinsicConstants_Sve) != 0) && CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableArm64Sve)) + { + CPUCompileFlags.Set(InstructionSet_Sve); + } + // DCZID_EL0<4> (DZP) indicates whether use of DC ZVA instructions is permitted (0) or prohibited (1). // DCZID_EL0<3:0> (BS) specifies Log2 of the block size in words. // diff --git a/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml b/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml index 1da6f6d57d26e3..7d05d2b47a61fe 100644 --- a/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml +++ b/src/libraries/System.Private.CoreLib/src/ILLink/ILLink.Substitutions.NoArmIntrinsics.xml @@ -51,5 +51,11 @@ + + + + + + diff --git a/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems b/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems index 5f1ef83c4d026a..27027b572e3408 100644 --- a/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems +++ b/src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems @@ -2624,6 +2624,7 @@ + @@ -2634,6 +2635,7 @@ + diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs new file mode 100644 index 00000000000000..b57859227ab855 --- /dev/null +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs @@ -0,0 +1,33 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +#pragma warning disable IDE0060 // unused parameters +using System.Diagnostics.CodeAnalysis; +using System.Runtime.CompilerServices; + +namespace System.Runtime.Intrinsics.Arm +{ + /// + /// This class provides access to the ARM SVE hardware instructions via intrinsics + /// + [CLSCompliant(false)] + public abstract class Sve : AdvSimd + { + internal Sve() { } + + public static new bool IsSupported { [Intrinsic] get => false; } + + [Intrinsic] + public new abstract class Arm64 : AdvSimd.Arm64 + { + internal Arm64() { } + + public static new bool IsSupported { [Intrinsic] get => false; } + } + + /// Count16BitElements : Count the number of 16-bit elements in a vector + + /// uint64_t svcnth() : "CNTH Xresult, ALL" + public static unsafe ulong Count16BitElements() { throw new PlatformNotSupportedException(); } + } +} diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs new file mode 100644 index 00000000000000..e961c61514dcd2 --- /dev/null +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs @@ -0,0 +1,35 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +using System.Diagnostics.CodeAnalysis; +using System.Runtime.CompilerServices; +using System.Runtime.Intrinsics; +using System.Numerics; + +namespace System.Runtime.Intrinsics.Arm +{ + /// + /// This class provides access to the ARM SVE hardware instructions via intrinsics + /// + [Intrinsic] + [CLSCompliant(false)] + public abstract class Sve : AdvSimd + { + internal Sve() { } + + public static new bool IsSupported { get => IsSupported; } + + [Intrinsic] + public new abstract class Arm64 : AdvSimd.Arm64 + { + internal Arm64() { } + + public static new bool IsSupported { get => IsSupported; } + } + + /// Count16BitElements : Count the number of 16-bit elements in a vector + + /// uint64_t svcnth() : "CNTH Xresult, ALL" + public static unsafe ulong Count16BitElements() => Count16BitElements(); + } +} diff --git a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs index e0f07a1441e248..6990b3abb34b8a 100644 --- a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs +++ b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs @@ -3958,6 +3958,18 @@ internal Arm64() { } public static new bool IsSupported { get { throw null; } } } } + [System.CLSCompliantAttribute(false)] + public abstract partial class Sve : System.Runtime.Intrinsics.Arm.AdvSimd + { + internal Sve() { } + public static new bool IsSupported { get { throw null; } } + public new abstract partial class Arm64 : System.Runtime.Intrinsics.Arm.AdvSimd.Arm64 + { + internal Arm64() { } + public static new bool IsSupported { get { throw null; } } + } + public static ulong Count16BitElements() { throw null; } + } } namespace System.Runtime.Intrinsics.X86 { diff --git a/src/native/minipal/cpufeatures.c b/src/native/minipal/cpufeatures.c index db7e7acf3b80e0..aeb7686dbec761 100644 --- a/src/native/minipal/cpufeatures.c +++ b/src/native/minipal/cpufeatures.c @@ -34,6 +34,9 @@ #ifndef HWCAP_ASIMDDP #define HWCAP_ASIMDDP (1 << 20) #endif +#ifndef HWCAP_SVE +#define HWCAP_SVE (1 << 22) +#endif #endif @@ -356,6 +359,9 @@ int minipal_getcpufeatures(void) if (hwCap & HWCAP_ASIMDRDM) result |= ARM64IntrinsicConstants_Rdm; + if (hwCap & HWCAP_SVE) + result |= ARM64IntrinsicConstants_Sve; + #else // !HAVE_AUXV_HWCAP_H #if HAVE_SYSCTLBYNAME diff --git a/src/native/minipal/cpufeatures.h b/src/native/minipal/cpufeatures.h index d0f615d293d59f..3b8d0de8aa8656 100644 --- a/src/native/minipal/cpufeatures.h +++ b/src/native/minipal/cpufeatures.h @@ -57,6 +57,7 @@ enum ARM64IntrinsicConstants ARM64IntrinsicConstants_Rcpc = 0x0100, ARM64IntrinsicConstants_VectorT128 = 0x0200, ARM64IntrinsicConstants_Rcpc2 = 0x0400, + ARM64IntrinsicConstants_Sve = 0x0800, }; #include diff --git a/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs b/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs new file mode 100644 index 00000000000000..82c7d92a86d8b6 --- /dev/null +++ b/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Program.cs @@ -0,0 +1,66 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +/****************************************************************************** + * This file is auto-generated from a template file by the GenerateTests.csx * + * script in tests\src\JIT\HardwareIntrinsics.Arm\Shared. In order to make * + * changes, please update the corresponding template and run according to the * + * directions listed in the file. * + ******************************************************************************/ + +using System; +using System.Reflection; +using System.Runtime.CompilerServices; +using System.Runtime.InteropServices; +using System.Runtime.Intrinsics; +using System.Runtime.Intrinsics.Arm; +using System.Numerics; +using Xunit; + +namespace JIT.HardwareIntrinsics.Arm._AdvSimd +{ + public static partial class Program + { + [Fact] + public static void SveTest() + { + var test = new SveTest__SveTest(); + + if (test.IsSupported) + { + Console.WriteLine("SVE is supported."); + test.RunBasicScenario_Count16(); + } + else + { + Console.WriteLine("SVE is not supported."); + test.Succeeded = true; + } + + if (!test.Succeeded) + { + throw new Exception("One or more scenarios did not complete as expected."); + } + } + } + + public sealed unsafe class SveTest__SveTest + { + public bool IsSupported => Sve.IsSupported && Sve.Arm64.IsSupported; + + public bool Succeeded { get; set; } + + [MethodImpl(MethodImplOptions.NoInlining)] + public ulong Count16() + { + return Sve.Count16BitElements(); + } + + public void RunBasicScenario_Count16() + { + Count16(); + Console.WriteLine("Done"); + Succeeded = true; + } + } +} diff --git a/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj b/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj new file mode 100644 index 00000000000000..9edcdffb8d6bb3 --- /dev/null +++ b/src/tests/JIT/HardwareIntrinsics/Arm/Sve/Sve.csproj @@ -0,0 +1,15 @@ + + + + Exe + net8.0 + true + ARM64 + true + + + + + + + \ No newline at end of file