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[AArch64][GlobalISel] Make G_DUP immediate 32-bits or larger
Immediate operand gets extended in RegBankSelect to allow for better pattern matching in TableGen
1 parent fd8b2d2 commit 2563474

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6 files changed

+96
-122
lines changed

6 files changed

+96
-122
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5536,7 +5536,8 @@ AArch64InstructionSelector::emitConstantVector(Register Dst, Constant *CV,
55365536
}
55375537

55385538
if (CV->getSplatValue()) {
5539-
APInt DefBits = APInt::getSplat(DstSize, CV->getUniqueInteger());
5539+
APInt DefBits = APInt::getSplat(
5540+
DstSize, CV->getUniqueInteger().trunc(DstTy.getScalarSizeInBits()));
55405541
auto TryMOVIWithBits = [&](APInt DefBits) -> MachineInstr * {
55415542
MachineInstr *NewOp;
55425543
bool Inv = false;

‎llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp‎

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -420,6 +420,25 @@ void AArch64RegisterBankInfo::applyMappingImpl(
420420
MI.getOperand(2).setReg(Ext.getReg(0));
421421
return applyDefaultMapping(OpdMapper);
422422
}
423+
case AArch64::G_DUP: {
424+
// Extend smaller gpr to 32-bits
425+
Builder.setInsertPt(*MI.getParent(), MI.getIterator());
426+
427+
Register ConstReg;
428+
auto ConstMI = MRI.getVRegDef(MI.getOperand(1).getReg());
429+
if (ConstMI->getOpcode() == TargetOpcode::G_CONSTANT) {
430+
auto CstVal = ConstMI->getOperand(1).getCImm()->getValue();
431+
ConstReg =
432+
Builder.buildConstant(LLT::scalar(32), CstVal.sext(32)).getReg(0);
433+
ConstMI->eraseFromParent();
434+
} else {
435+
ConstReg = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(1).getReg())
436+
.getReg(0);
437+
}
438+
MRI.setRegBank(ConstReg, getRegBank(AArch64::GPRRegBankID));
439+
MI.getOperand(1).setReg(ConstReg);
440+
return applyDefaultMapping(OpdMapper);
441+
}
423442
default:
424443
llvm_unreachable("Don't know how to handle that operation");
425444
}
@@ -774,8 +793,12 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
774793
(getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank ||
775794
onlyDefinesFP(*ScalarDef, MRI, TRI)))
776795
OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
777-
else
796+
else {
797+
if (ScalarTy.getSizeInBits() < 32 &&
798+
getRegBank(ScalarReg, MRI, TRI) == &AArch64::GPRRegBank)
799+
MappingID = 1;
778800
OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
801+
}
779802
break;
780803
}
781804
case TargetOpcode::G_TRUNC: {

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,8 @@ define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {
1818
;
1919
; GISEL-LABEL: combine_vec_udiv_uniform:
2020
; GISEL: // %bb.0:
21-
; GISEL-NEXT: adrp x8, .LCPI0_0
22-
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
21+
; GISEL-NEXT: mov w8, #25645 // =0x642d
22+
; GISEL-NEXT: dup v1.8h, w8
2323
; GISEL-NEXT: umull2 v2.4s, v0.8h, v1.8h
2424
; GISEL-NEXT: umull v1.4s, v0.4h, v1.4h
2525
; GISEL-NEXT: uzp2 v1.8h, v1.8h, v2.8h

‎llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir‎

Lines changed: 42 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -16,10 +16,11 @@ body: |
1616
1717
; CHECK-LABEL: name: v4s32_gpr
1818
; CHECK: liveins: $w0
19-
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
20-
; CHECK: [[DUP:%[0-9]+]]:fpr(<4 x s32>) = G_DUP [[COPY]](s32)
21-
; CHECK: $q0 = COPY [[DUP]](<4 x s32>)
22-
; CHECK: RET_ReallyLR implicit $q0
19+
; CHECK-NEXT: {{ $}}
20+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
21+
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<4 x s32>) = G_DUP [[COPY]](s32)
22+
; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x s32>)
23+
; CHECK-NEXT: RET_ReallyLR implicit $q0
2324
%0:_(s32) = COPY $w0
2425
%4:_(<4 x s32>) = G_DUP %0(s32)
2526
$q0 = COPY %4(<4 x s32>)
@@ -37,10 +38,11 @@ body: |
3738
3839
; CHECK-LABEL: name: v4s64_gpr
3940
; CHECK: liveins: $x0
40-
; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
41-
; CHECK: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
42-
; CHECK: $q0 = COPY [[DUP]](<2 x s64>)
43-
; CHECK: RET_ReallyLR implicit $q0
41+
; CHECK-NEXT: {{ $}}
42+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
43+
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
44+
; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
45+
; CHECK-NEXT: RET_ReallyLR implicit $q0
4446
%0:_(s64) = COPY $x0
4547
%4:_(<2 x s64>) = G_DUP %0(s64)
4648
$q0 = COPY %4(<2 x s64>)
@@ -58,10 +60,11 @@ body: |
5860
5961
; CHECK-LABEL: name: v2s32_gpr
6062
; CHECK: liveins: $w0
61-
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
62-
; CHECK: [[DUP:%[0-9]+]]:fpr(<2 x s32>) = G_DUP [[COPY]](s32)
63-
; CHECK: $d0 = COPY [[DUP]](<2 x s32>)
64-
; CHECK: RET_ReallyLR implicit $d0
63+
; CHECK-NEXT: {{ $}}
64+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
65+
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s32>) = G_DUP [[COPY]](s32)
66+
; CHECK-NEXT: $d0 = COPY [[DUP]](<2 x s32>)
67+
; CHECK-NEXT: RET_ReallyLR implicit $d0
6568
%0:_(s32) = COPY $w0
6669
%4:_(<2 x s32>) = G_DUP %0(s32)
6770
$d0 = COPY %4(<2 x s32>)
@@ -79,10 +82,11 @@ body: |
7982
8083
; CHECK-LABEL: name: v4s32_fpr
8184
; CHECK: liveins: $s0
82-
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
83-
; CHECK: [[DUP:%[0-9]+]]:fpr(<4 x s32>) = G_DUP [[COPY]](s32)
84-
; CHECK: $q0 = COPY [[DUP]](<4 x s32>)
85-
; CHECK: RET_ReallyLR implicit $q0
85+
; CHECK-NEXT: {{ $}}
86+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
87+
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<4 x s32>) = G_DUP [[COPY]](s32)
88+
; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x s32>)
89+
; CHECK-NEXT: RET_ReallyLR implicit $q0
8690
%0:_(s32) = COPY $s0
8791
%4:_(<4 x s32>) = G_DUP %0(s32)
8892
$q0 = COPY %4(<4 x s32>)
@@ -100,10 +104,11 @@ body: |
100104
101105
; CHECK-LABEL: name: v2s64_fpr
102106
; CHECK: liveins: $d0
103-
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
104-
; CHECK: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
105-
; CHECK: $q0 = COPY [[DUP]](<2 x s64>)
106-
; CHECK: RET_ReallyLR implicit $q0
107+
; CHECK-NEXT: {{ $}}
108+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
109+
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
110+
; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
111+
; CHECK-NEXT: RET_ReallyLR implicit $q0
107112
%0:_(s64) = COPY $d0
108113
%4:_(<2 x s64>) = G_DUP %0(s64)
109114
$q0 = COPY %4(<2 x s64>)
@@ -121,10 +126,11 @@ body: |
121126
122127
; CHECK-LABEL: name: v2s32_fpr
123128
; CHECK: liveins: $s0
124-
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
125-
; CHECK: [[DUP:%[0-9]+]]:fpr(<2 x s32>) = G_DUP [[COPY]](s32)
126-
; CHECK: $d0 = COPY [[DUP]](<2 x s32>)
127-
; CHECK: RET_ReallyLR implicit $d0
129+
; CHECK-NEXT: {{ $}}
130+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
131+
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s32>) = G_DUP [[COPY]](s32)
132+
; CHECK-NEXT: $d0 = COPY [[DUP]](<2 x s32>)
133+
; CHECK-NEXT: RET_ReallyLR implicit $d0
128134
%0:_(s32) = COPY $s0
129135
%4:_(<2 x s32>) = G_DUP %0(s32)
130136
$d0 = COPY %4(<2 x s32>)
@@ -142,10 +148,11 @@ body: |
142148
143149
; CHECK-LABEL: name: v2s64_fpr_copy
144150
; CHECK: liveins: $d0
145-
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
146-
; CHECK: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
147-
; CHECK: $q0 = COPY [[DUP]](<2 x s64>)
148-
; CHECK: RET_ReallyLR implicit $q0
151+
; CHECK-NEXT: {{ $}}
152+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
153+
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
154+
; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
155+
; CHECK-NEXT: RET_ReallyLR implicit $q0
149156
%0:_(s64) = COPY $d0
150157
%6:_(<2 x s64>) = G_DUP %0(s64)
151158
$q0 = COPY %6(<2 x s64>)
@@ -163,11 +170,13 @@ body: |
163170
164171
; CHECK-LABEL: name: v416s8_gpr
165172
; CHECK: liveins: $w0
166-
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
167-
; CHECK: %trunc:gpr(s8) = G_TRUNC [[COPY]](s32)
168-
; CHECK: [[DUP:%[0-9]+]]:fpr(<16 x s8>) = G_DUP %trunc(s8)
169-
; CHECK: $q0 = COPY [[DUP]](<16 x s8>)
170-
; CHECK: RET_ReallyLR implicit $q0
173+
; CHECK-NEXT: {{ $}}
174+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
175+
; CHECK-NEXT: %trunc:gpr(s8) = G_TRUNC [[COPY]](s32)
176+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gpr(s32) = G_ANYEXT %trunc(s8)
177+
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<16 x s8>) = G_DUP [[ANYEXT]](s32)
178+
; CHECK-NEXT: $q0 = COPY [[DUP]](<16 x s8>)
179+
; CHECK-NEXT: RET_ReallyLR implicit $q0
171180
%0:_(s32) = COPY $w0
172181
%trunc:_(s8) = G_TRUNC %0(s32)
173182
%1:_(<16 x s8>) = G_DUP %trunc(s8)

‎llvm/test/CodeGen/AArch64/aarch64-smull.ll‎

Lines changed: 9 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -994,9 +994,9 @@ define <8 x i16> @smull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
994994
;
995995
; CHECK-GI-LABEL: smull_noextvec_v8i8_v8i16:
996996
; CHECK-GI: // %bb.0:
997-
; CHECK-GI-NEXT: adrp x8, .LCPI34_0
997+
; CHECK-GI-NEXT: mov w8, #-999 // =0xfffffc19
998998
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
999-
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI34_0]
999+
; CHECK-GI-NEXT: dup v1.8h, w8
10001000
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
10011001
; CHECK-GI-NEXT: ret
10021002
%tmp3 = sext <8 x i8> %arg to <8 x i16>
@@ -1088,29 +1088,13 @@ define <8 x i16> @umull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
10881088

10891089
define <8 x i16> @umull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
10901090
; Do not use SMULL if the BUILD_VECTOR element values are too big.
1091-
; CHECK-NEON-LABEL: umull_noextvec_v8i8_v8i16:
1092-
; CHECK-NEON: // %bb.0:
1093-
; CHECK-NEON-NEXT: mov w8, #999 // =0x3e7
1094-
; CHECK-NEON-NEXT: ushll v0.8h, v0.8b, #0
1095-
; CHECK-NEON-NEXT: dup v1.8h, w8
1096-
; CHECK-NEON-NEXT: mul v0.8h, v0.8h, v1.8h
1097-
; CHECK-NEON-NEXT: ret
1098-
;
1099-
; CHECK-SVE-LABEL: umull_noextvec_v8i8_v8i16:
1100-
; CHECK-SVE: // %bb.0:
1101-
; CHECK-SVE-NEXT: mov w8, #999 // =0x3e7
1102-
; CHECK-SVE-NEXT: ushll v0.8h, v0.8b, #0
1103-
; CHECK-SVE-NEXT: dup v1.8h, w8
1104-
; CHECK-SVE-NEXT: mul v0.8h, v0.8h, v1.8h
1105-
; CHECK-SVE-NEXT: ret
1106-
;
1107-
; CHECK-GI-LABEL: umull_noextvec_v8i8_v8i16:
1108-
; CHECK-GI: // %bb.0:
1109-
; CHECK-GI-NEXT: adrp x8, .LCPI38_0
1110-
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
1111-
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI38_0]
1112-
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
1113-
; CHECK-GI-NEXT: ret
1091+
; CHECK-LABEL: umull_noextvec_v8i8_v8i16:
1092+
; CHECK: // %bb.0:
1093+
; CHECK-NEXT: mov w8, #999 // =0x3e7
1094+
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
1095+
; CHECK-NEXT: dup v1.8h, w8
1096+
; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h
1097+
; CHECK-NEXT: ret
11141098
%tmp3 = zext <8 x i8> %arg to <8 x i16>
11151099
%tmp4 = mul <8 x i16> %tmp3, <i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999>
11161100
ret <8 x i16> %tmp4

‎llvm/test/CodeGen/AArch64/neon-mov.ll‎

Lines changed: 17 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -109,29 +109,11 @@ define <4 x i32> @movi4s_lsl16() {
109109
}
110110

111111
define <4 x i32> @movi4s_fneg() {
112-
; CHECK-NOFP16-SD-LABEL: movi4s_fneg:
113-
; CHECK-NOFP16-SD: // %bb.0:
114-
; CHECK-NOFP16-SD-NEXT: movi v0.4s, #240, lsl #8
115-
; CHECK-NOFP16-SD-NEXT: fneg v0.4s, v0.4s
116-
; CHECK-NOFP16-SD-NEXT: ret
117-
;
118-
; CHECK-FP16-SD-LABEL: movi4s_fneg:
119-
; CHECK-FP16-SD: // %bb.0:
120-
; CHECK-FP16-SD-NEXT: movi v0.4s, #240, lsl #8
121-
; CHECK-FP16-SD-NEXT: fneg v0.4s, v0.4s
122-
; CHECK-FP16-SD-NEXT: ret
123-
;
124-
; CHECK-NOFP16-GI-LABEL: movi4s_fneg:
125-
; CHECK-NOFP16-GI: // %bb.0:
126-
; CHECK-NOFP16-GI-NEXT: movi v0.4s, #240, lsl #8
127-
; CHECK-NOFP16-GI-NEXT: fneg v0.4s, v0.4s
128-
; CHECK-NOFP16-GI-NEXT: ret
129-
;
130-
; CHECK-FP16-GI-LABEL: movi4s_fneg:
131-
; CHECK-FP16-GI: // %bb.0:
132-
; CHECK-FP16-GI-NEXT: movi v0.4s, #240, lsl #8
133-
; CHECK-FP16-GI-NEXT: fneg v0.4s, v0.4s
134-
; CHECK-FP16-GI-NEXT: ret
112+
; CHECK-LABEL: movi4s_fneg:
113+
; CHECK: // %bb.0:
114+
; CHECK-NEXT: movi v0.4s, #240, lsl #8
115+
; CHECK-NEXT: fneg v0.4s, v0.4s
116+
; CHECK-NEXT: ret
135117
ret <4 x i32> <i32 2147545088, i32 2147545088, i32 2147545088, i32 2147545088>
136118
}
137119

@@ -308,23 +290,17 @@ define <8 x i16> @mvni8h_neg() {
308290
; CHECK-NOFP16-SD-NEXT: dup v0.8h, w8
309291
; CHECK-NOFP16-SD-NEXT: ret
310292
;
311-
; CHECK-FP16-SD-LABEL: mvni8h_neg:
312-
; CHECK-FP16-SD: // %bb.0:
313-
; CHECK-FP16-SD-NEXT: movi v0.8h, #240
314-
; CHECK-FP16-SD-NEXT: fneg v0.8h, v0.8h
315-
; CHECK-FP16-SD-NEXT: ret
293+
; CHECK-FP16-LABEL: mvni8h_neg:
294+
; CHECK-FP16: // %bb.0:
295+
; CHECK-FP16-NEXT: movi v0.8h, #240
296+
; CHECK-FP16-NEXT: fneg v0.8h, v0.8h
297+
; CHECK-FP16-NEXT: ret
316298
;
317299
; CHECK-NOFP16-GI-LABEL: mvni8h_neg:
318300
; CHECK-NOFP16-GI: // %bb.0:
319-
; CHECK-NOFP16-GI-NEXT: adrp x8, .LCPI32_0
320-
; CHECK-NOFP16-GI-NEXT: ldr q0, [x8, :lo12:.LCPI32_0]
301+
; CHECK-NOFP16-GI-NEXT: mov w8, #-32528 // =0xffff80f0
302+
; CHECK-NOFP16-GI-NEXT: dup v0.8h, w8
321303
; CHECK-NOFP16-GI-NEXT: ret
322-
;
323-
; CHECK-FP16-GI-LABEL: mvni8h_neg:
324-
; CHECK-FP16-GI: // %bb.0:
325-
; CHECK-FP16-GI-NEXT: movi v0.8h, #240
326-
; CHECK-FP16-GI-NEXT: fneg v0.8h, v0.8h
327-
; CHECK-FP16-GI-NEXT: ret
328304
ret <8 x i16> <i16 33008, i16 33008, i16 33008, i16 33008, i16 33008, i16 33008, i16 33008, i16 33008>
329305
}
330306

@@ -494,29 +470,11 @@ define <2 x double> @fmov2d() {
494470
}
495471

496472
define <2 x double> @fmov2d_neg0() {
497-
; CHECK-NOFP16-SD-LABEL: fmov2d_neg0:
498-
; CHECK-NOFP16-SD: // %bb.0:
499-
; CHECK-NOFP16-SD-NEXT: movi v0.2d, #0000000000000000
500-
; CHECK-NOFP16-SD-NEXT: fneg v0.2d, v0.2d
501-
; CHECK-NOFP16-SD-NEXT: ret
502-
;
503-
; CHECK-FP16-SD-LABEL: fmov2d_neg0:
504-
; CHECK-FP16-SD: // %bb.0:
505-
; CHECK-FP16-SD-NEXT: movi v0.2d, #0000000000000000
506-
; CHECK-FP16-SD-NEXT: fneg v0.2d, v0.2d
507-
; CHECK-FP16-SD-NEXT: ret
508-
;
509-
; CHECK-NOFP16-GI-LABEL: fmov2d_neg0:
510-
; CHECK-NOFP16-GI: // %bb.0:
511-
; CHECK-NOFP16-GI-NEXT: movi v0.2d, #0000000000000000
512-
; CHECK-NOFP16-GI-NEXT: fneg v0.2d, v0.2d
513-
; CHECK-NOFP16-GI-NEXT: ret
514-
;
515-
; CHECK-FP16-GI-LABEL: fmov2d_neg0:
516-
; CHECK-FP16-GI: // %bb.0:
517-
; CHECK-FP16-GI-NEXT: movi v0.2d, #0000000000000000
518-
; CHECK-FP16-GI-NEXT: fneg v0.2d, v0.2d
519-
; CHECK-FP16-GI-NEXT: ret
473+
; CHECK-LABEL: fmov2d_neg0:
474+
; CHECK: // %bb.0:
475+
; CHECK-NEXT: movi v0.2d, #0000000000000000
476+
; CHECK-NEXT: fneg v0.2d, v0.2d
477+
; CHECK-NEXT: ret
520478
ret <2 x double> <double -0.0, double -0.0>
521479
}
522480

@@ -581,5 +539,4 @@ define <2 x i32> @movi1d() {
581539
ret <2 x i32> %1
582540
}
583541
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
584-
; CHECK-FP16: {{.*}}
585542
; CHECK-NOFP16: {{.*}}

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