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davemgreendavemgreen
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[AArch64] Regenerate s/urem-seteq-* tests. NFC
1 parent 6a4779c commit 2bb7272

12 files changed

+153
-153
lines changed

‎llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,12 @@
44
define i1 @test_srem_odd(i29 %X) nounwind {
55
; CHECK-LABEL: test_srem_odd:
66
; CHECK: // %bb.0:
7-
; CHECK-NEXT: mov w8, #33099
8-
; CHECK-NEXT: mov w9, #24493
7+
; CHECK-NEXT: mov w8, #33099 // =0x814b
8+
; CHECK-NEXT: mov w9, #24493 // =0x5fad
99
; CHECK-NEXT: movk w8, #8026, lsl #16
1010
; CHECK-NEXT: movk w9, #41, lsl #16
1111
; CHECK-NEXT: madd w8, w0, w8, w9
12-
; CHECK-NEXT: mov w9, #48987
12+
; CHECK-NEXT: mov w9, #48987 // =0xbf5b
1313
; CHECK-NEXT: movk w9, #82, lsl #16
1414
; CHECK-NEXT: and w8, w8, #0x1fffffff
1515
; CHECK-NEXT: cmp w8, w9
@@ -24,7 +24,7 @@ define i1 @test_srem_even(i4 %X) nounwind {
2424
; CHECK-LABEL: test_srem_even:
2525
; CHECK: // %bb.0:
2626
; CHECK-NEXT: sbfx w9, w0, #0, #4
27-
; CHECK-NEXT: mov w8, #6
27+
; CHECK-NEXT: mov w8, #6 // =0x6
2828
; CHECK-NEXT: add w9, w9, w9, lsl #1
2929
; CHECK-NEXT: ubfx w10, w9, #7, #1
3030
; CHECK-NEXT: add w9, w10, w9, lsr #4
@@ -57,10 +57,10 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
5757
define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
5858
; CHECK-LABEL: test_srem_vec:
5959
; CHECK: // %bb.0:
60-
; CHECK-NEXT: mov x8, #7282
60+
; CHECK-NEXT: mov x8, #7282 // =0x1c72
6161
; CHECK-NEXT: sbfx x9, x0, #0, #33
6262
; CHECK-NEXT: movk x8, #29127, lsl #16
63-
; CHECK-NEXT: mov x11, #7281
63+
; CHECK-NEXT: mov x11, #7281 // =0x1c71
6464
; CHECK-NEXT: movk x8, #50972, lsl #32
6565
; CHECK-NEXT: movk x11, #29127, lsl #16
6666
; CHECK-NEXT: movk x8, #7281, lsl #48
@@ -83,7 +83,7 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
8383
; CHECK-NEXT: add x11, x11, x11, lsl #3
8484
; CHECK-NEXT: fmov d0, x9
8585
; CHECK-NEXT: add x10, x10, x11
86-
; CHECK-NEXT: mov x9, #8589934591
86+
; CHECK-NEXT: mov x9, #8589934591 // =0x1ffffffff
8787
; CHECK-NEXT: adrp x11, .LCPI3_0
8888
; CHECK-NEXT: adrp x12, .LCPI3_1
8989
; CHECK-NEXT: mov v0.d[1], x8

‎llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,12 @@
44
define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone {
55
; CHECK-LABEL: test_minsize:
66
; CHECK: // %bb.0:
7-
; CHECK-NEXT: mov w8, #5
8-
; CHECK-NEXT: mov w9, #42
7+
; CHECK-NEXT: mov w8, #5 // =0x5
8+
; CHECK-NEXT: mov w9, #42 // =0x2a
99
; CHECK-NEXT: sdiv w8, w0, w8
1010
; CHECK-NEXT: add w8, w8, w8, lsl #2
1111
; CHECK-NEXT: cmp w0, w8
12-
; CHECK-NEXT: mov w8, #-10
12+
; CHECK-NEXT: mov w8, #-10 // =0xfffffff6
1313
; CHECK-NEXT: csel w0, w9, w8, eq
1414
; CHECK-NEXT: ret
1515
%rem = srem i32 %X, 5
@@ -21,15 +21,15 @@ define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone {
2121
define i32 @test_optsize(i32 %X) optsize nounwind readnone {
2222
; CHECK-LABEL: test_optsize:
2323
; CHECK: // %bb.0:
24-
; CHECK-NEXT: mov w8, #52429
25-
; CHECK-NEXT: mov w9, #39321
24+
; CHECK-NEXT: mov w8, #52429 // =0xcccd
25+
; CHECK-NEXT: mov w9, #39321 // =0x9999
2626
; CHECK-NEXT: movk w8, #52428, lsl #16
2727
; CHECK-NEXT: movk w9, #6553, lsl #16
2828
; CHECK-NEXT: madd w8, w0, w8, w9
29-
; CHECK-NEXT: mov w9, #858993459
29+
; CHECK-NEXT: mov w9, #858993459 // =0x33333333
3030
; CHECK-NEXT: cmp w8, w9
31-
; CHECK-NEXT: mov w8, #-10
32-
; CHECK-NEXT: mov w9, #42
31+
; CHECK-NEXT: mov w8, #-10 // =0xfffffff6
32+
; CHECK-NEXT: mov w9, #42 // =0x2a
3333
; CHECK-NEXT: csel w0, w9, w8, lo
3434
; CHECK-NEXT: ret
3535
%rem = srem i32 %X, 5

‎llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,8 @@ define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
3535
define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
3636
; CHECK-LABEL: test_srem_odd_allones_eq:
3737
; CHECK: // %bb.0:
38-
; CHECK-NEXT: mov w8, #52429
39-
; CHECK-NEXT: mov w9, #39321
38+
; CHECK-NEXT: mov w8, #52429 // =0xcccd
39+
; CHECK-NEXT: mov w9, #39321 // =0x9999
4040
; CHECK-NEXT: movk w8, #52428, lsl #16
4141
; CHECK-NEXT: movk w9, #6553, lsl #16
4242
; CHECK-NEXT: dup v1.4s, w8
@@ -56,8 +56,8 @@ define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
5656
define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
5757
; CHECK-LABEL: test_srem_odd_allones_ne:
5858
; CHECK: // %bb.0:
59-
; CHECK-NEXT: mov w8, #52429
60-
; CHECK-NEXT: mov w9, #39321
59+
; CHECK-NEXT: mov w8, #52429 // =0xcccd
60+
; CHECK-NEXT: mov w9, #39321 // =0x9999
6161
; CHECK-NEXT: movk w8, #52428, lsl #16
6262
; CHECK-NEXT: movk w9, #6553, lsl #16
6363
; CHECK-NEXT: dup v1.4s, w8
@@ -79,8 +79,8 @@ define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
7979
define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
8080
; CHECK-LABEL: test_srem_even_allones_eq:
8181
; CHECK: // %bb.0:
82-
; CHECK-NEXT: mov w8, #28087
83-
; CHECK-NEXT: mov w9, #9362
82+
; CHECK-NEXT: mov w8, #28087 // =0x6db7
83+
; CHECK-NEXT: mov w9, #9362 // =0x2492
8484
; CHECK-NEXT: movk w8, #46811, lsl #16
8585
; CHECK-NEXT: movk w9, #4681, lsl #16
8686
; CHECK-NEXT: movi v3.4s, #1
@@ -103,8 +103,8 @@ define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
103103
define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
104104
; CHECK-LABEL: test_srem_even_allones_ne:
105105
; CHECK: // %bb.0:
106-
; CHECK-NEXT: mov w8, #28087
107-
; CHECK-NEXT: mov w9, #9362
106+
; CHECK-NEXT: mov w8, #28087 // =0x6db7
107+
; CHECK-NEXT: mov w9, #9362 // =0x2492
108108
; CHECK-NEXT: movk w8, #46811, lsl #16
109109
; CHECK-NEXT: movk w9, #4681, lsl #16
110110
; CHECK-NEXT: movi v3.4s, #1
@@ -271,8 +271,8 @@ define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
271271
define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
272272
; CHECK-LABEL: test_srem_odd_one:
273273
; CHECK: // %bb.0:
274-
; CHECK-NEXT: mov w8, #52429
275-
; CHECK-NEXT: mov w9, #39321
274+
; CHECK-NEXT: mov w8, #52429 // =0xcccd
275+
; CHECK-NEXT: mov w9, #39321 // =0x9999
276276
; CHECK-NEXT: movk w8, #52428, lsl #16
277277
; CHECK-NEXT: movk w9, #6553, lsl #16
278278
; CHECK-NEXT: dup v1.4s, w8
@@ -294,8 +294,8 @@ define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
294294
define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
295295
; CHECK-LABEL: test_srem_even_one:
296296
; CHECK: // %bb.0:
297-
; CHECK-NEXT: mov w8, #28087
298-
; CHECK-NEXT: mov w9, #9362
297+
; CHECK-NEXT: mov w8, #28087 // =0x6db7
298+
; CHECK-NEXT: mov w9, #9362 // =0x2492
299299
; CHECK-NEXT: movk w8, #46811, lsl #16
300300
; CHECK-NEXT: movk w9, #4681, lsl #16
301301
; CHECK-NEXT: movi v3.4s, #1
@@ -525,8 +525,8 @@ define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwi
525525
define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
526526
; CHECK-LABEL: test_srem_odd_allones_and_one:
527527
; CHECK: // %bb.0:
528-
; CHECK-NEXT: mov w8, #52429
529-
; CHECK-NEXT: mov w9, #39321
528+
; CHECK-NEXT: mov w8, #52429 // =0xcccd
529+
; CHECK-NEXT: mov w9, #39321 // =0x9999
530530
; CHECK-NEXT: movk w8, #52428, lsl #16
531531
; CHECK-NEXT: movk w9, #6553, lsl #16
532532
; CHECK-NEXT: dup v1.4s, w8
@@ -548,8 +548,8 @@ define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
548548
define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
549549
; CHECK-LABEL: test_srem_even_allones_and_one:
550550
; CHECK: // %bb.0:
551-
; CHECK-NEXT: mov w8, #28087
552-
; CHECK-NEXT: mov w9, #9362
551+
; CHECK-NEXT: mov w8, #28087 // =0x6db7
552+
; CHECK-NEXT: mov w9, #9362 // =0x2492
553553
; CHECK-NEXT: movk w8, #46811, lsl #16
554554
; CHECK-NEXT: movk w9, #4681, lsl #16
555555
; CHECK-NEXT: movi v3.4s, #1

‎llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -5,13 +5,13 @@
55
define <4 x i32> @test_srem_odd_25(<4 x i32> %X) nounwind {
66
; CHECK-LABEL: test_srem_odd_25:
77
; CHECK: // %bb.0:
8-
; CHECK-NEXT: mov w8, #23593
9-
; CHECK-NEXT: mov w9, #47185
8+
; CHECK-NEXT: mov w8, #23593 // =0x5c29
9+
; CHECK-NEXT: mov w9, #47185 // =0xb851
1010
; CHECK-NEXT: movk w8, #49807, lsl #16
1111
; CHECK-NEXT: movk w9, #1310, lsl #16
1212
; CHECK-NEXT: dup v1.4s, w8
1313
; CHECK-NEXT: dup v2.4s, w9
14-
; CHECK-NEXT: mov w8, #28834
14+
; CHECK-NEXT: mov w8, #28834 // =0x70a2
1515
; CHECK-NEXT: movk w8, #2621, lsl #16
1616
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
1717
; CHECK-NEXT: movi v1.4s, #1
@@ -29,14 +29,14 @@ define <4 x i32> @test_srem_odd_25(<4 x i32> %X) nounwind {
2929
define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {
3030
; CHECK-LABEL: test_srem_even_100:
3131
; CHECK: // %bb.0:
32-
; CHECK-NEXT: mov w8, #23593
33-
; CHECK-NEXT: mov w9, #47184
32+
; CHECK-NEXT: mov w8, #23593 // =0x5c29
33+
; CHECK-NEXT: mov w9, #47184 // =0xb850
3434
; CHECK-NEXT: movk w8, #49807, lsl #16
3535
; CHECK-NEXT: movk w9, #1310, lsl #16
3636
; CHECK-NEXT: movi v3.4s, #1
3737
; CHECK-NEXT: dup v1.4s, w8
3838
; CHECK-NEXT: dup v2.4s, w9
39-
; CHECK-NEXT: mov w8, #23592
39+
; CHECK-NEXT: mov w8, #23592 // =0x5c28
4040
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
4141
; CHECK-NEXT: movk w8, #655, lsl #16
4242
; CHECK-NEXT: shl v0.4s, v2.4s, #30
@@ -58,13 +58,13 @@ define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {
5858
define <4 x i32> @test_srem_odd_neg25(<4 x i32> %X) nounwind {
5959
; CHECK-LABEL: test_srem_odd_neg25:
6060
; CHECK: // %bb.0:
61-
; CHECK-NEXT: mov w8, #23593
62-
; CHECK-NEXT: mov w9, #47185
61+
; CHECK-NEXT: mov w8, #23593 // =0x5c29
62+
; CHECK-NEXT: mov w9, #47185 // =0xb851
6363
; CHECK-NEXT: movk w8, #49807, lsl #16
6464
; CHECK-NEXT: movk w9, #1310, lsl #16
6565
; CHECK-NEXT: dup v1.4s, w8
6666
; CHECK-NEXT: dup v2.4s, w9
67-
; CHECK-NEXT: mov w8, #28834
67+
; CHECK-NEXT: mov w8, #28834 // =0x70a2
6868
; CHECK-NEXT: movk w8, #2621, lsl #16
6969
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
7070
; CHECK-NEXT: movi v1.4s, #1
@@ -82,14 +82,14 @@ define <4 x i32> @test_srem_odd_neg25(<4 x i32> %X) nounwind {
8282
define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {
8383
; CHECK-LABEL: test_srem_even_neg100:
8484
; CHECK: // %bb.0:
85-
; CHECK-NEXT: mov w8, #23593
86-
; CHECK-NEXT: mov w9, #47184
85+
; CHECK-NEXT: mov w8, #23593 // =0x5c29
86+
; CHECK-NEXT: mov w9, #47184 // =0xb850
8787
; CHECK-NEXT: movk w8, #49807, lsl #16
8888
; CHECK-NEXT: movk w9, #1310, lsl #16
8989
; CHECK-NEXT: movi v3.4s, #1
9090
; CHECK-NEXT: dup v1.4s, w8
9191
; CHECK-NEXT: dup v2.4s, w9
92-
; CHECK-NEXT: mov w8, #23592
92+
; CHECK-NEXT: mov w8, #23592 // =0x5c28
9393
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
9494
; CHECK-NEXT: movk w8, #655, lsl #16
9595
; CHECK-NEXT: shl v0.4s, v2.4s, #30
@@ -112,7 +112,7 @@ define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {
112112
define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind {
113113
; CHECK-LABEL: test_srem_odd_undef1:
114114
; CHECK: // %bb.0:
115-
; CHECK-NEXT: mov w8, #34079
115+
; CHECK-NEXT: mov w8, #34079 // =0x851f
116116
; CHECK-NEXT: movk w8, #20971, lsl #16
117117
; CHECK-NEXT: movi v3.4s, #25
118118
; CHECK-NEXT: dup v1.4s, w8
@@ -135,7 +135,7 @@ define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind {
135135
define <4 x i32> @test_srem_even_undef1(<4 x i32> %X) nounwind {
136136
; CHECK-LABEL: test_srem_even_undef1:
137137
; CHECK: // %bb.0:
138-
; CHECK-NEXT: mov w8, #34079
138+
; CHECK-NEXT: mov w8, #34079 // =0x851f
139139
; CHECK-NEXT: movk w8, #20971, lsl #16
140140
; CHECK-NEXT: movi v3.4s, #100
141141
; CHECK-NEXT: dup v1.4s, w8

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