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llvm/test/CodeGen/RISCV/GlobalISel/instruction-select Expand file tree Collapse file tree 4 files changed +124
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lines changed Original file line number Diff line number Diff line change 1+ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+ # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
3+ # RUN: -simplify-mir -verify-machineinstrs %s -o - \
4+ # RUN: | FileCheck -check-prefix=RV32I %s
5+
6+ ---
7+ name : ctlz_s32
8+ legalized : true
9+ regBankSelected : true
10+ body : |
11+ bb.0.entry:
12+ ; RV32I-LABEL: name: ctlz_s32
13+ ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
14+ ; RV32I-NEXT: [[CLZ:%[0-9]+]]:gpr = CLZ [[COPY]]
15+ ; RV32I-NEXT: $x10 = COPY [[CLZ]]
16+ ; RV32I-NEXT: PseudoRET implicit $x10
17+ %0:gprb(s32) = COPY $x10
18+ %1:gprb(s32) = G_CTLZ %0
19+ $x10 = COPY %1(s32)
20+ PseudoRET implicit $x10
21+
22+ ...
Original file line number Diff line number Diff line change 1+ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+ # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
3+ # RUN: -simplify-mir -verify-machineinstrs %s -o - \
4+ # RUN: | FileCheck -check-prefix=RV64I %s
5+
6+ ---
7+ name : ctlz_s32
8+ legalized : true
9+ regBankSelected : true
10+ body : |
11+ bb.0.entry:
12+ ; RV64I-LABEL: name: ctlz_s32
13+ ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
14+ ; RV64I-NEXT: [[CLZW:%[0-9]+]]:gpr = CLZW [[COPY]]
15+ ; RV64I-NEXT: $x10 = COPY [[CLZW]]
16+ ; RV64I-NEXT: PseudoRET implicit $x10
17+ %0:gprb(s64) = COPY $x10
18+ %1:gprb(s32) = G_TRUNC %0
19+ %2:gprb(s32) = G_CTLZ %1
20+ %3:gprb(s64) = G_ANYEXT %2
21+ $x10 = COPY %3(s64)
22+ PseudoRET implicit $x10
23+
24+ ...
25+ ---
26+ name : ctlz_s64
27+ legalized : true
28+ regBankSelected : true
29+ body : |
30+ bb.0.entry:
31+ ; RV64I-LABEL: name: ctlz_s64
32+ ; RV64I: [[CLZ:%[0-9]+]]:gpr = CLZ [[CLZ]]
33+ ; RV64I-NEXT: $x10 = COPY [[CLZ]]
34+ ; RV64I-NEXT: PseudoRET implicit $x10
35+ %0:gprb(s64) = COPY $x10
36+ %1:gprb(s64) = G_CTLZ %1
37+ $x10 = COPY %1(s64)
38+ PseudoRET implicit $x10
39+
40+ ...
Original file line number Diff line number Diff line change 1+ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+ # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
3+ # RUN: -simplify-mir -verify-machineinstrs %s -o - \
4+ # RUN: | FileCheck -check-prefix=RV32I %s
5+
6+ ---
7+ name : cttz_s32
8+ legalized : true
9+ regBankSelected : true
10+ body : |
11+ bb.0.entry:
12+ ; RV32I-LABEL: name: cttz_s32
13+ ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
14+ ; RV32I-NEXT: [[CTZ:%[0-9]+]]:gpr = CTZ [[COPY]]
15+ ; RV32I-NEXT: $x10 = COPY [[CTZ]]
16+ ; RV32I-NEXT: PseudoRET implicit $x10
17+ %0:gprb(s32) = COPY $x10
18+ %1:gprb(s32) = G_CTTZ %0
19+ $x10 = COPY %1(s32)
20+ PseudoRET implicit $x10
21+
22+ ...
Original file line number Diff line number Diff line change 1+ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+ # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
3+ # RUN: -simplify-mir -verify-machineinstrs %s -o - \
4+ # RUN: | FileCheck -check-prefix=RV64I %s
5+
6+ ---
7+ name : cttz_s32
8+ legalized : true
9+ regBankSelected : true
10+ body : |
11+ bb.0.entry:
12+ ; RV64I-LABEL: name: cttz_s32
13+ ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
14+ ; RV64I-NEXT: [[CTZW:%[0-9]+]]:gpr = CTZW [[COPY]]
15+ ; RV64I-NEXT: $x10 = COPY [[CTZW]]
16+ ; RV64I-NEXT: PseudoRET implicit $x10
17+ %0:gprb(s64) = COPY $x10
18+ %1:gprb(s32) = G_TRUNC %0
19+ %2:gprb(s32) = G_CTTZ %1
20+ %3:gprb(s64) = G_ANYEXT %2
21+ $x10 = COPY %3(s64)
22+ PseudoRET implicit $x10
23+
24+ ...
25+ ---
26+ name : cttz_s64
27+ legalized : true
28+ regBankSelected : true
29+ body : |
30+ bb.0.entry:
31+ ; RV64I-LABEL: name: cttz_s64
32+ ; RV64I: [[CTZ:%[0-9]+]]:gpr = CTZ [[CTZ]]
33+ ; RV64I-NEXT: $x10 = COPY [[CTZ]]
34+ ; RV64I-NEXT: PseudoRET implicit $x10
35+ %0:gprb(s64) = COPY $x10
36+ %1:gprb(s64) = G_CTTZ %1
37+ $x10 = COPY %1(s64)
38+ PseudoRET implicit $x10
39+
40+ ...
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