[RISCV][GlobalISel] Select ALU GPR instructions

Some instruction selection patterns required for ALU GPR instructions have
already been automatically imported from existing TableGen descriptions -
this patch simply adds testing for them. The first of the GIComplexPatternEquiv
definitions required to select the shiftMaskXLen ComplexPattern has been added.

Some instructions require special handling due to i32 not being a legal
type on RV64 in SelectionDAG so we can't reuse SelectionDAG patterns.

Co-authored-by: Lewis Revill <[email protected]>

Reviewed By: nitinjohnraj

Differential Revision: https://reviews.llvm.org/D76445

Author: topperc

llvm/lib/Target/RISCV/CMakeLists.txt

@@ -7,7 +7,6 @@ tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
 tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
@@ -16,6 +15,9 @@ tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
 
+set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
+tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
+
 add_public_tablegen_target(RISCVCommonTableGen)
 
 add_llvm_target(RISCVCodeGen

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

@@ -50,6 +50,15 @@ class RISCVInstructionSelector : public InstructionSelector {
   bool selectConstant(MachineInstr &MI, MachineIRBuilder &MIB,
                       MachineRegisterInfo &MRI) const;
 
+  bool earlySelectShift(unsigned Opc, MachineInstr &I, MachineIRBuilder &MIB,
+                        const MachineRegisterInfo &MRI);
+
+  ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
+
+  // Custom renderers for tablegen
+  void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
+                    int OpIdx) const;
+
   const RISCVSubtarget &STI;
   const RISCVInstrInfo &TII;
   const RISCVRegisterInfo &TRI;
@@ -89,12 +98,43 @@ RISCVInstructionSelector::RISCVInstructionSelector(
 {
 }
 
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const {
+  // TODO: Also check if we are seeing the result of an AND operation which
+  // could be bypassed since we only check the lower log2(xlen) bits.
+  return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
+}
+
+// Tablegen doesn't allow us to write SRLIW/SRAIW/SLLIW patterns because the
+// immediate Operand has type XLenVT. GlobalISel wants it to be i32.
+bool RISCVInstructionSelector::earlySelectShift(
+    unsigned Opc, MachineInstr &I, MachineIRBuilder &MIB,
+    const MachineRegisterInfo &MRI) {
+  if (!Subtarget->is64Bit())
+    return false;
+
+  LLT Ty = MRI.getType(I.getOperand(0).getReg());
+  if (!Ty.isScalar() || Ty.getSizeInBits() != 32)
+    return false;
+
+  std::optional<int64_t> CstVal =
+      getIConstantVRegSExtVal(I.getOperand(2).getReg(), MRI);
+  if (!CstVal || !isUInt<5>(*CstVal))
+    return false;
+
+  auto NewI = MIB.buildInstr(Opc, {I.getOperand(0).getReg()},
+                             {I.getOperand(1).getReg()})
+                  .addImm(*CstVal);
+  I.eraseFromParent();
+  return constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI);
+}
+
 bool RISCVInstructionSelector::select(MachineInstr &MI) {
   unsigned Opc = MI.getOpcode();
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
-  MachineIRBuilder MIB(MF);
+  MachineIRBuilder MIB(MI);
 
   if (!isPreISelGenericOpcode(Opc)) {
     // Certain non-generic instructions also need some special handling.
@@ -104,13 +144,61 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     return true;
   }
 
+  switch (Opc) {
+  case TargetOpcode::G_ADD: {
+    // Tablegen doesn't pick up the ADDIW pattern because i32 isn't a legal
+    // type for RV64 in SelectionDAG. Manually select it here.
+    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+    if (Subtarget->is64Bit() && Ty.isScalar() && Ty.getSizeInBits() == 32) {
+      std::optional<int64_t> CstVal =
+          getIConstantVRegSExtVal(MI.getOperand(2).getReg(), MRI);
+      if (CstVal && isInt<12>(*CstVal)) {
+        auto NewI = MIB.buildInstr(RISCV::ADDIW, {MI.getOperand(0).getReg()},
+                                   {MI.getOperand(1).getReg()})
+                        .addImm(*CstVal);
+        MI.eraseFromParent();
+        return constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI);
+      }
+    }
+    break;
+  }
+  case TargetOpcode::G_SUB: {
+    // Tablegen doesn't pick up the ADDIW pattern because i32 isn't a legal
+    // type for RV64 in SelectionDAG. Manually select it here.
+    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+    if (Subtarget->is64Bit() && Ty.isScalar() && Ty.getSizeInBits() == 32) {
+      std::optional<int64_t> CstVal =
+          getIConstantVRegSExtVal(MI.getOperand(2).getReg(), MRI);
+      if (CstVal && ((isInt<12>(*CstVal) && *CstVal != -2048) || *CstVal == 2048)) {
+        auto NewI = MIB.buildInstr(RISCV::ADDIW, {MI.getOperand(0).getReg()},
+                                   {MI.getOperand(1).getReg()})
+                        .addImm(-*CstVal);
+        MI.eraseFromParent();
+        return constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI);
+      }
+    }
+    break;
+  }
+  case TargetOpcode::G_ASHR:
+    if (earlySelectShift(RISCV::SRAIW, MI, MIB, MRI))
+      return true;
+    break;
+  case TargetOpcode::G_LSHR:
+    if (earlySelectShift(RISCV::SRLIW, MI, MIB, MRI))
+      return true;
+    break;
+  case TargetOpcode::G_SHL:
+    if (earlySelectShift(RISCV::SLLIW, MI, MIB, MRI))
+      return true;
+    break;
+  }
+
   if (selectImpl(MI, *CoverageInfo))
     return true;
 
-  MIB.setInstrAndDebugLoc(MI);
-
   switch (Opc) {
   case TargetOpcode::G_ANYEXT:
+  case TargetOpcode::G_TRUNC:
     MI.setDesc(TII.get(TargetOpcode::COPY));
     return true;
   case TargetOpcode::G_CONSTANT:
@@ -126,10 +214,19 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   return true;
 }
 
+void RISCVInstructionSelector::renderNegImm(MachineInstrBuilder &MIB,
+                                            const MachineInstr &MI,
+                                            int OpIdx) const {
+  assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
+         "Expected G_CONSTANT");
+  int64_t CstVal = MI.getOperand(1).getCImm()->getSExtValue();
+  MIB.addImm(-CstVal);
+}
+
 const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
     LLT Ty, const RegisterBank &RB, bool GetAllRegSet) const {
   if (RB.getID() == RISCV::GPRRegBankID) {
-    if (Ty.getSizeInBits() == (STI.is64Bit() ? 64 : 32))
+    if (Ty.getSizeInBits() <= 32 || (STI.is64Bit() && Ty.getSizeInBits() == 64))
       return &RISCV::GPRRegClass;
   }
 

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

@@ -47,7 +47,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
       .lowerFor({{XLenLLT, s1}});
 
   getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
-      .legalFor({{s32, s32}, {s32, XLenLLT}, {XLenLLT, XLenLLT}})
+      .legalFor({{s32, s32}, {XLenLLT, XLenLLT}})
       .widenScalarToNextPow2(0)
       .clampScalar(1, s32, XLenLLT)
       .clampScalar(0, s32, XLenLLT);

llvm/lib/Target/RISCV/RISCVGISel.td

@@ -0,0 +1,55 @@
+//===-- RISCVGIsel.td - RISCV GlobalISel Patterns ----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// This file contains patterns that are relevant to GlobalISel, including
+/// GIComplexOperandMatcher definitions for equivalent SelectionDAG
+/// ComplexPatterns.
+//
+//===----------------------------------------------------------------------===//
+
+include "RISCV.td"
+
+def simm12Plus1 : ImmLeaf<XLenVT, [{
+    return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
+
+def GINegImm : GICustomOperandRenderer<"renderNegImm">,
+  GISDNodeXFormEquiv<NegImm>;
+
+// FIXME: This is labelled as handling 's32', however the ComplexPattern it
+// refers to handles both i32 and i64 based on the HwMode. Currently this LLT
+// parameter appears to be ignored so this pattern works for both, however we
+// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
+// here.
+def ShiftMaskGI :
+    GIComplexOperandMatcher<s32, "selectShiftMask">,
+    GIComplexPatternEquiv<shiftMaskXLen>;
+
+// FIXME: Canonicalize (sub X, C) -> (add X, -C) earlier.
+def : Pat<(XLenVT (sub GPR:$rs1, simm12Plus1:$imm)),
+          (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm))>;
+
+let Predicates = [IsRV64] in {
+def : Pat<(i32 (add GPR:$rs1, GPR:$rs2)), (ADDW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (sub GPR:$rs1, GPR:$rs2)), (SUBW GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(i32 (shl GPR:$rs1, (i32 GPR:$rs2))), (SLLW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (sra GPR:$rs1, (i32 GPR:$rs2))), (SRAW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (srl GPR:$rs1, (i32 GPR:$rs2))), (SRLW GPR:$rs1, GPR:$rs2)>;
+}
+
+let Predicates = [HasStdExtMOrZmmul, IsRV64] in {
+def : Pat<(i32 (mul GPR:$rs1, GPR:$rs2)), (MULW GPR:$rs1, GPR:$rs2)>;
+}
+
+let Predicates = [HasStdExtM, IsRV64] in {
+def : Pat<(i32 (sdiv GPR:$rs1, GPR:$rs2)), (DIVW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (srem GPR:$rs1, GPR:$rs2)), (REMW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (udiv GPR:$rs1, GPR:$rs2)), (DIVUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (urem GPR:$rs1, GPR:$rs2)), (REMUW GPR:$rs1, GPR:$rs2)>;
+}

llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip-rv64.ll

@@ -0,0 +1,103 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+m -global-isel -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64IM
+
+define i64 @sll_i64(i64 %a, i64 %b) {
+; RV64IM-LABEL: sll_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    sll a0, a0, a1
+; RV64IM-NEXT:    ret
+entry:
+  %0 = shl i64 %a, %b
+  ret i64 %0
+}
+
+define i64 @slli_i64(i64 %a) {
+; RV64IM-LABEL: slli_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    slli a0, a0, 33
+; RV64IM-NEXT:    ret
+entry:
+  %0 = shl i64 %a, 33
+  ret i64 %0
+}
+
+define i64 @sra_i64(i64 %a, i64 %b) {
+; RV64IM-LABEL: sra_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    sra a0, a0, a1
+; RV64IM-NEXT:    ret
+entry:
+  %0 = ashr i64 %a, %b
+  ret i64 %0
+}
+
+define i64 @srai_i64(i64 %a) {
+; RV64IM-LABEL: srai_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    srai a0, a0, 47
+; RV64IM-NEXT:    ret
+entry:
+  %0 = ashr i64 %a, 47
+  ret i64 %0
+}
+
+define i64 @srl_i64(i64 %a, i64 %b) {
+; RV64IM-LABEL: srl_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    srl a0, a0, a1
+; RV64IM-NEXT:    ret
+entry:
+  %0 = lshr i64 %a, %b
+  ret i64 %0
+}
+
+define i64 @srli_i64(i64 %a, i64 %b) {
+; RV64IM-LABEL: srli_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    srli a0, a0, 55
+; RV64IM-NEXT:    ret
+entry:
+  %0 = lshr i64 %a, 55
+  ret i64 %0
+}
+
+define i64 @sdiv_i64(i64 %a, i64 %b) {
+; RV64IM-LABEL: sdiv_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    div a0, a0, a1
+; RV64IM-NEXT:    ret
+entry:
+  %0 = sdiv i64 %a, %b
+  ret i64 %0
+}
+
+define i64 @srem_i64(i64 %a, i64 %b) {
+; RV64IM-LABEL: srem_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    rem a0, a0, a1
+; RV64IM-NEXT:    ret
+entry:
+  %0 = srem i64 %a, %b
+  ret i64 %0
+}
+
+define i64 @udiv_i64(i64 %a, i64 %b) {
+; RV64IM-LABEL: udiv_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    divu a0, a0, a1
+; RV64IM-NEXT:    ret
+entry:
+  %0 = udiv i64 %a, %b
+  ret i64 %0
+}
+
+define i64 @urem_i64(i64 %a, i64 %b) {
+; RV64IM-LABEL: urem_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    remu a0, a0, a1
+; RV64IM-NEXT:    ret
+entry:
+  %0 = urem i64 %a, %b
+  ret i64 %0
+}