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tex3dtex3d
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[aarch64] atan2 intrinsic lowering (p5) (#112611)
This change is part of this proposal: https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294 - `VecFuncs.def`: define intrinsic to sleef/armpl mapping - `LegalizerHelper.cpp`: add missing fewerElementsVector handling for the new atan2 intrinsic - `AArch64ISelLowering.cpp`: Add arch64 specializations for lowering like neon instructions - `AArch64LegalizerInfo.cpp`: Legalize atan2. Part 5 for Implement the atan2 HLSL Function #70096.
1 parent b1be213 commit c03d09c

19 files changed

+698
-22
lines changed

‎llvm/include/llvm/Analysis/VecFuncs.def‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,9 @@ TLI_DEFINE_VECFUNC("llvm.atan.f64", "_simd_atan_d2", FIXED(2), "_ZGV_LLVM_N2v")
9292
TLI_DEFINE_VECFUNC("atanf", "_simd_atan_f4", FIXED(4), "_ZGV_LLVM_N4v")
9393
TLI_DEFINE_VECFUNC("llvm.atan.f32", "_simd_atan_f4", FIXED(4), "_ZGV_LLVM_N4v")
9494
TLI_DEFINE_VECFUNC("atan2", "_simd_atan2_d2", FIXED(2), "_ZGV_LLVM_N2vv")
95+
TLI_DEFINE_VECFUNC("llvm.atan2.f64", "_simd_atan2_d2", FIXED(2), "_ZGV_LLVM_N2vv")
9596
TLI_DEFINE_VECFUNC("atan2f", "_simd_atan2_f4", FIXED(4), "_ZGV_LLVM_N4vv")
97+
TLI_DEFINE_VECFUNC("llvm.atan2.f32", "_simd_atan2_f4", FIXED(4), "_ZGV_LLVM_N4vv")
9698

9799
TLI_DEFINE_VECFUNC("cos", "_simd_cos_d2", FIXED(2), "_ZGV_LLVM_N2v")
98100
TLI_DEFINE_VECFUNC("llvm.cos.f64", "_simd_cos_d2", FIXED(2), "_ZGV_LLVM_N2v")
@@ -531,6 +533,7 @@ TLI_DEFINE_VECFUNC("atan", "_ZGVnN2v_atan", FIXED(2), "_ZGV_LLVM_N2v")
531533
TLI_DEFINE_VECFUNC("llvm.atan.f64", "_ZGVnN2v_atan", FIXED(2), "_ZGV_LLVM_N2v")
532534

533535
TLI_DEFINE_VECFUNC("atan2", "_ZGVnN2vv_atan2", FIXED(2), "_ZGV_LLVM_N2vv")
536+
TLI_DEFINE_VECFUNC("llvm.atan2.f64", "_ZGVnN2vv_atan2", FIXED(2), "_ZGV_LLVM_N2vv")
534537

535538
TLI_DEFINE_VECFUNC("atanh", "_ZGVnN2v_atanh", FIXED(2), "_ZGV_LLVM_N2v")
536539

@@ -635,6 +638,7 @@ TLI_DEFINE_VECFUNC("atanf", "_ZGVnN4v_atanf", FIXED(4), "_ZGV_LLVM_N4v")
635638
TLI_DEFINE_VECFUNC("llvm.atan.f32", "_ZGVnN4v_atanf", FIXED(4), "_ZGV_LLVM_N4v")
636639

637640
TLI_DEFINE_VECFUNC("atan2f", "_ZGVnN4vv_atan2f", FIXED(4), "_ZGV_LLVM_N4vv")
641+
TLI_DEFINE_VECFUNC("llvm.atan2.f32", "_ZGVnN4vv_atan2f", FIXED(4), "_ZGV_LLVM_N4vv")
638642

639643
TLI_DEFINE_VECFUNC("atanhf", "_ZGVnN4v_atanhf", FIXED(4), "_ZGV_LLVM_N4v")
640644

@@ -748,6 +752,8 @@ TLI_DEFINE_VECFUNC("llvm.atan.f32", "_ZGVsMxv_atanf", SCALABLE(4), MASKED, "_ZGV
748752

749753
TLI_DEFINE_VECFUNC("atan2", "_ZGVsMxvv_atan2", SCALABLE(2), MASKED, "_ZGVsMxvv")
750754
TLI_DEFINE_VECFUNC("atan2f", "_ZGVsMxvv_atan2f", SCALABLE(4), MASKED, "_ZGVsMxvv")
755+
TLI_DEFINE_VECFUNC("llvm.atan2.f64", "_ZGVsMxvv_atan2", SCALABLE(2), MASKED, "_ZGVsMxvv")
756+
TLI_DEFINE_VECFUNC("llvm.atan2.f32", "_ZGVsMxvv_atan2f", SCALABLE(4), MASKED, "_ZGVsMxvv")
751757

752758
TLI_DEFINE_VECFUNC("atanh", "_ZGVsMxv_atanh", SCALABLE(2), MASKED, "_ZGVsMxv")
753759
TLI_DEFINE_VECFUNC("atanhf", "_ZGVsMxv_atanhf", SCALABLE(4), MASKED, "_ZGVsMxv")
@@ -933,6 +939,11 @@ TLI_DEFINE_VECFUNC("atan2f", "armpl_vatan2q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N
933939
TLI_DEFINE_VECFUNC("atan2", "armpl_svatan2_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvv")
934940
TLI_DEFINE_VECFUNC("atan2f", "armpl_svatan2_f32_x", SCALABLE(4), MASKED, "_ZGVsMxvv")
935941

942+
TLI_DEFINE_VECFUNC("llvm.atan2.f64", "armpl_vatan2q_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2vv")
943+
TLI_DEFINE_VECFUNC("llvm.atan2.f32", "armpl_vatan2q_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4vv")
944+
TLI_DEFINE_VECFUNC("llvm.atan2.f64", "armpl_svatan2_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvv")
945+
TLI_DEFINE_VECFUNC("llvm.atan2.f32", "armpl_svatan2_f32_x", SCALABLE(4), MASKED, "_ZGVsMxvv")
946+
936947
TLI_DEFINE_VECFUNC("atanh", "armpl_vatanhq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v")
937948
TLI_DEFINE_VECFUNC("atanhf", "armpl_vatanhq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v")
938949
TLI_DEFINE_VECFUNC("atanh", "armpl_svatanh_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv")

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,7 @@ def : GINodeEquiv<G_FTAN, ftan>;
155155
def : GINodeEquiv<G_FACOS, facos>;
156156
def : GINodeEquiv<G_FASIN, fasin>;
157157
def : GINodeEquiv<G_FATAN, fatan>;
158+
def : GINodeEquiv<G_FATAN2, fatan2>;
158159
def : GINodeEquiv<G_FCOSH, fcosh>;
159160
def : GINodeEquiv<G_FSINH, fsinh>;
160161
def : GINodeEquiv<G_FTANH, ftanh>;

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -457,6 +457,8 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
457457
RTLIBCASE(ACOS_F);
458458
case TargetOpcode::G_FATAN:
459459
RTLIBCASE(ATAN_F);
460+
case TargetOpcode::G_FATAN2:
461+
RTLIBCASE(ATAN2_F);
460462
case TargetOpcode::G_FSINH:
461463
RTLIBCASE(SINH_F);
462464
case TargetOpcode::G_FCOSH:
@@ -1202,6 +1204,7 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
12021204
case TargetOpcode::G_FACOS:
12031205
case TargetOpcode::G_FASIN:
12041206
case TargetOpcode::G_FATAN:
1207+
case TargetOpcode::G_FATAN2:
12051208
case TargetOpcode::G_FCOSH:
12061209
case TargetOpcode::G_FSINH:
12071210
case TargetOpcode::G_FTANH:
@@ -3122,6 +3125,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
31223125
case TargetOpcode::G_FACOS:
31233126
case TargetOpcode::G_FASIN:
31243127
case TargetOpcode::G_FATAN:
3128+
case TargetOpcode::G_FATAN2:
31253129
case TargetOpcode::G_FCOSH:
31263130
case TargetOpcode::G_FSINH:
31273131
case TargetOpcode::G_FTANH:
@@ -5141,6 +5145,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
51415145
case G_FACOS:
51425146
case G_FASIN:
51435147
case G_FATAN:
5148+
case G_FATAN2:
51445149
case G_FCOSH:
51455150
case G_FSINH:
51465151
case G_FTANH:

‎llvm/lib/CodeGen/GlobalISel/Utils.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -828,6 +828,7 @@ bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
828828
case TargetOpcode::G_FACOS:
829829
case TargetOpcode::G_FASIN:
830830
case TargetOpcode::G_FATAN:
831+
case TargetOpcode::G_FATAN2:
831832
case TargetOpcode::G_FCOSH:
832833
case TargetOpcode::G_FSINH:
833834
case TargetOpcode::G_FTANH:
@@ -1715,6 +1716,7 @@ bool llvm::isPreISelGenericFloatingPointOpcode(unsigned Opc) {
17151716
case TargetOpcode::G_FACOS:
17161717
case TargetOpcode::G_FASIN:
17171718
case TargetOpcode::G_FATAN:
1719+
case TargetOpcode::G_FATAN2:
17181720
case TargetOpcode::G_FCOSH:
17191721
case TargetOpcode::G_FSINH:
17201722
case TargetOpcode::G_FTANH:

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 16 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -734,18 +734,19 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
734734
setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Promote);
735735
}
736736

737-
for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI,
738-
ISD::FCOS, ISD::FSIN, ISD::FSINCOS,
739-
ISD::FACOS, ISD::FASIN, ISD::FATAN,
740-
ISD::FCOSH, ISD::FSINH, ISD::FTANH,
741-
ISD::FTAN, ISD::FEXP, ISD::FEXP2,
742-
ISD::FEXP10, ISD::FLOG, ISD::FLOG2,
743-
ISD::FLOG10, ISD::STRICT_FREM, ISD::STRICT_FPOW,
744-
ISD::STRICT_FPOWI, ISD::STRICT_FCOS, ISD::STRICT_FSIN,
745-
ISD::STRICT_FACOS, ISD::STRICT_FASIN, ISD::STRICT_FATAN,
746-
ISD::STRICT_FCOSH, ISD::STRICT_FSINH, ISD::STRICT_FTANH,
747-
ISD::STRICT_FEXP, ISD::STRICT_FEXP2, ISD::STRICT_FLOG,
748-
ISD::STRICT_FLOG2, ISD::STRICT_FLOG10, ISD::STRICT_FTAN}) {
737+
for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI,
738+
ISD::FCOS, ISD::FSIN, ISD::FSINCOS,
739+
ISD::FACOS, ISD::FASIN, ISD::FATAN,
740+
ISD::FATAN2, ISD::FCOSH, ISD::FSINH,
741+
ISD::FTANH, ISD::FTAN, ISD::FEXP,
742+
ISD::FEXP2, ISD::FEXP10, ISD::FLOG,
743+
ISD::FLOG2, ISD::FLOG10, ISD::STRICT_FREM,
744+
ISD::STRICT_FPOW, ISD::STRICT_FPOWI, ISD::STRICT_FCOS,
745+
ISD::STRICT_FSIN, ISD::STRICT_FACOS, ISD::STRICT_FASIN,
746+
ISD::STRICT_FATAN, ISD::STRICT_FATAN2, ISD::STRICT_FCOSH,
747+
ISD::STRICT_FSINH, ISD::STRICT_FTANH, ISD::STRICT_FEXP,
748+
ISD::STRICT_FEXP2, ISD::STRICT_FLOG, ISD::STRICT_FLOG2,
749+
ISD::STRICT_FLOG10, ISD::STRICT_FTAN}) {
749750
setOperationAction(Op, MVT::f16, Promote);
750751
setOperationAction(Op, MVT::v4f16, Expand);
751752
setOperationAction(Op, MVT::v8f16, Expand);
@@ -1190,7 +1191,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
11901191
// silliness like this:
11911192
// clang-format off
11921193
for (auto Op :
1193-
{ISD::SELECT, ISD::SELECT_CC,
1194+
{ISD::SELECT, ISD::SELECT_CC, ISD::FATAN2,
11941195
ISD::BR_CC, ISD::FADD, ISD::FSUB,
11951196
ISD::FMUL, ISD::FDIV, ISD::FMA,
11961197
ISD::FNEG, ISD::FABS, ISD::FCEIL,
@@ -1649,6 +1650,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
16491650
setOperationAction(ISD::FACOS, VT, Expand);
16501651
setOperationAction(ISD::FASIN, VT, Expand);
16511652
setOperationAction(ISD::FATAN, VT, Expand);
1653+
setOperationAction(ISD::FATAN2, VT, Expand);
16521654
setOperationAction(ISD::FCOSH, VT, Expand);
16531655
setOperationAction(ISD::FSINH, VT, Expand);
16541656
setOperationAction(ISD::FTANH, VT, Expand);
@@ -1904,6 +1906,7 @@ void AArch64TargetLowering::addTypeForNEON(MVT VT) {
19041906
setOperationAction(ISD::FASIN, VT, Expand);
19051907
setOperationAction(ISD::FACOS, VT, Expand);
19061908
setOperationAction(ISD::FATAN, VT, Expand);
1909+
setOperationAction(ISD::FATAN2, VT, Expand);
19071910
setOperationAction(ISD::FSINH, VT, Expand);
19081911
setOperationAction(ISD::FCOSH, VT, Expand);
19091912
setOperationAction(ISD::FTANH, VT, Expand);

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -269,9 +269,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
269269
.libcallFor({{s64, s128}})
270270
.minScalarOrElt(1, MinFPScalar);
271271

272-
getActionDefinitionsBuilder(
273-
{G_FCOS, G_FSIN, G_FPOW, G_FLOG, G_FLOG2, G_FLOG10, G_FTAN, G_FEXP,
274-
G_FEXP2, G_FEXP10, G_FACOS, G_FASIN, G_FATAN, G_FCOSH, G_FSINH, G_FTANH})
272+
getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FPOW, G_FLOG, G_FLOG2,
273+
G_FLOG10, G_FTAN, G_FEXP, G_FEXP2, G_FEXP10,
274+
G_FACOS, G_FASIN, G_FATAN, G_FATAN2, G_FCOSH,
275+
G_FSINH, G_FTANH})
275276
// We need a call for these, so we always need to scalarize.
276277
.scalarize(0)
277278
// Regardless of FP16 support, widen 16-bit elements to 32-bits.

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2345,6 +2345,14 @@ define float @test_atan_f32(float %x) {
23452345
ret float %y
23462346
}
23472347

2348+
declare float @llvm.atan2.f32(float, float)
2349+
define float @test_atan2_f32(float %x, float %y) {
2350+
; CHECK-LABEL: name: test_atan2_f32
2351+
; CHECK: %{{[0-9]+}}:_(s32) = G_FATAN2 %{{[0-9]+}}
2352+
%z = call float @llvm.atan2.f32(float %x, float %y)
2353+
ret float %z
2354+
}
2355+
23482356
declare float @llvm.cosh.f32(float)
23492357
define float @test_cosh_f32(float %x) {
23502358
; CHECK-LABEL: name: test_cosh_f32

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