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[RISCV] Add B extension
It seems that we have `B` extension again: https://github.com/riscv/riscv-b According to the spec, `B` extension represents the collection of the `Zba`, `Zbb`, `Zbs` extensions. Though it hasn't been ratified, I set its version to `1.0`.
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‎clang/test/Driver/riscv-arch.c‎

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@@ -233,11 +233,6 @@
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// RV32-STD: error: invalid arch name 'rv32imqc',
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// RV32-STD: unsupported standard user-level extension 'q'
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// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
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// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
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// RV32-B: error: invalid arch name 'rv32ib',
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// RV32-B: unsupported standard user-level extension 'b'
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// RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
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// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
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// RV32X: error: invalid arch name 'rv32xabc',

‎clang/test/Preprocessor/riscv-target-features.c‎

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@@ -7,6 +7,7 @@
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// CHECK-NOT: __riscv_64e {{.*$}}
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// CHECK-NOT: __riscv_a {{.*$}}
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// CHECK-NOT: __riscv_atomic
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// CHECK-NOT: __riscv_b {{.*$}}
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// CHECK-NOT: __riscv_c {{.*$}}
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// CHECK-NOT: __riscv_compressed {{.*$}}
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// CHECK-NOT: __riscv_d {{.*$}}
@@ -159,6 +160,17 @@
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// CHECK-A-EXT: __riscv_a 2001000{{$}}
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// CHECK-A-EXT: __riscv_atomic 1
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ib -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64ib -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
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// CHECK-B-EXT: __riscv_b 1000000{{$}}
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// CHECK-B-EXT: __riscv_zba 1000000{{$}}
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// CHECK-B-EXT: __riscv_zbb 1000000{{$}}
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// CHECK-B-EXT: __riscv_zbs 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ic -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s

‎llvm/docs/RISCVUsage.rst‎

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@@ -85,6 +85,7 @@ on support follow.
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Extension Status
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=============== =========================================================
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``A`` Supported
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``B`` Supported
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``C`` Supported
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``D`` Supported
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``F`` Supported

‎llvm/lib/Support/RISCVISAInfo.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ static const char *RISCVGImplications[] = {
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// NOTE: This table should be sorted alphabetically by extension name.
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static const RISCVSupportedExtension SupportedExtensions[] = {
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{"a", {2, 1}},
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{"b", {1, 0}},
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{"c", {2, 0}},
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{"d", {2, 2}},
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{"e", {2, 0}},
@@ -848,7 +849,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
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}
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// The order is OK, then push it into features.
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// Currently LLVM supports only "mafdcvh".
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// Currently LLVM supports only "mafdcbvh".
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if (!isSupportedExtension(StringRef(&C, 1))) {
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if (IgnoreUnknown) {
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GoToNextExt(I, ConsumeLength, Exts.end());
@@ -998,6 +999,7 @@ Error RISCVISAInfo::checkDependency() {
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return Error::success();
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}
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static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
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static const char *ImpliedExtsD[] = {"f"};
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static const char *ImpliedExtsF[] = {"zicsr"};
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static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1072,6 +1074,7 @@ struct ImpliedExtsEntry {
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// Note: The table needs to be sorted by name.
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static constexpr ImpliedExtsEntry ImpliedExts[] = {
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{{"b"}, {ImpliedExtsB}},
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{{"d"}, {ImpliedExtsD}},
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{{"f"}, {ImpliedExtsF}},
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{{"v"}, {ImpliedExtsV}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -225,6 +225,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
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AssemblerPredicate<(all_of FeatureStdExtZbs),
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"'Zbs' (Single-Bit Instructions)">;
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228+
def FeatureStdExtB
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: SubtargetFeature<"b", "HasStdExtB", "true",
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"'B' (the collection of the Zba, Zbb, Zbs extensions)",
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[FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
232+
def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
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AssemblerPredicate<(all_of FeatureStdExtB),
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"'B' (the collection of the Zba, Zbb, Zbs extensions)">;
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def FeatureStdExtZbkb
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: SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
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"'Zbkb' (Bitmanip instructions for Cryptography)">;

‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -5,6 +5,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32ZMMUL %s
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; RUN: llc -mtriple=riscv32 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32MZMMUL %s
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; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV32A %s
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; RUN: llc -mtriple=riscv32 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV32B %s
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; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV32F %s
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; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV32D %s
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; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV32C %s
@@ -100,6 +101,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
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; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s
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; RUN: llc -mtriple=riscv64 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV64B %s
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; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
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; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s
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; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s
@@ -202,6 +204,7 @@
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; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0"
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; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
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; RV32A: .attribute 5, "rv32i2p1_a2p1"
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; RV32B: .attribute 5, "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
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; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
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; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
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; RV32C: .attribute 5, "rv32i2p1_c2p0"
@@ -296,6 +299,7 @@
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; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
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; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
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; RV64A: .attribute 5, "rv64i2p1_a2p1"
302+
; RV64B: .attribute 5, "rv64i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
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; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
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; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
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; RV64C: .attribute 5, "rv64i2p1_c2p0"

‎llvm/unittests/Support/RISCVISAInfoTest.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -222,8 +222,6 @@ TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
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}
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224224
TEST(ParseArchString, RejectsUnrecognizedExtensionNamesByDefault) {
225-
EXPECT_EQ(toString(RISCVISAInfo::parseArchString("rv64ib", true).takeError()),
226-
"unsupported standard user-level extension 'b'");
227225
EXPECT_EQ(
228226
toString(
229227
RISCVISAInfo::parseArchString("rv32i_zmadeup", true).takeError()),
@@ -239,8 +237,7 @@ TEST(ParseArchString, RejectsUnrecognizedExtensionNamesByDefault) {
239237
}
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241239
TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) {
242-
for (StringRef Input : {"rv32ib", "rv32i_zmadeup",
243-
"rv64i_smadeup", "rv64i_xmadeup"}) {
240+
for (StringRef Input : {"rv32i_zmadeup", "rv64i_smadeup", "rv64i_xmadeup"}) {
244241
auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true);
245242
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
246243
RISCVISAInfo &Info = **MaybeISAInfo;
@@ -673,6 +670,7 @@ R"(All available -march extensions for RISC-V
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f 2.2
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d 2.2
675672
c 2.0
673+
b 1.0
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v 1.0
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h 1.0
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zic64b 1.0

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