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PPC: Split 64bit target feature into 64bit and 64bit-support (#157206)
This was being used for 2 different purposes. The TargetMachine constructor prepends +64bit based on isPPC64 triples as a mode switch. The same feature name was also explicitly added to different processors, making it impossible to perform a pure feature check for whether 64-bit mode is enabled ir not. i.e., checkFeatures("+64bit") would be true even for ppc32 triples. The comment in tablegen suggests it's relevant to track which processors support 64-bit mode independently of whether that's the active compile target, so replace that with a new feature.
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‎llvm/lib/Target/PowerPC/PPC.td‎

Lines changed: 19 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -58,8 +58,13 @@ def DirectivePwrFuture
5858

5959
// Specifies that the selected CPU supports 64-bit instructions, regardless of
6060
// whether we are in 32-bit or 64-bit mode.
61-
def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
62-
"Enable 64-bit instructions">;
61+
def Feature64BitSupport : SubtargetFeature<"64bit-support", "Has64BitSupport", "true",
62+
"Supports 64-bit instructions">;
63+
// 64-bit is enabled.
64+
def Feature64Bit : SubtargetFeature<"64bit", "IsPPC64", "true",
65+
"Enable 64-bit mode",
66+
[Feature64BitSupport]>;
67+
6368
def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
6469
def FeatureModernAIXAs
6570
: SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
@@ -85,7 +90,7 @@ def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
8590
def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
8691
"Enable SPE instructions",
8792
[FeatureHardFloat]>;
88-
def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
93+
def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
8994
"Enable Embedded Floating-Point APU 2 instructions",
9095
[FeatureSPE]>;
9196
def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
@@ -429,7 +434,7 @@ def ProcessorFeatures {
429434
FeaturePOPCNTD,
430435
FeatureCMPB,
431436
FeatureLDBRX,
432-
Feature64Bit,
437+
Feature64BitSupport,
433438
/* Feature64BitRegs, */
434439
FeatureBPERMD,
435440
FeatureExtDiv,
@@ -667,13 +672,13 @@ def : ProcessorModel<"970", G5Model,
667672
[Directive970, FeatureAltivec,
668673
FeatureMFOCRF, FeatureFSqrt,
669674
FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
670-
Feature64Bit /*, Feature64BitRegs */,
675+
Feature64BitSupport /*, Feature64BitRegs */,
671676
FeatureMFTB]>;
672677
def : ProcessorModel<"g5", G5Model,
673678
[Directive970, FeatureAltivec,
674679
FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
675680
FeatureFRES, FeatureFRSQRTE,
676-
Feature64Bit /*, Feature64BitRegs */,
681+
Feature64BitSupport /*, Feature64BitRegs */,
677682
FeatureMFTB, DeprecatedDST]>;
678683
def : ProcessorModel<"e500", PPCE500Model,
679684
[DirectiveE500,
@@ -694,41 +699,41 @@ def : ProcessorModel<"a2", PPCA2Model,
694699
FeatureSTFIWX, FeatureLFIWAX,
695700
FeatureFPRND, FeatureFPCVT, FeatureISEL,
696701
FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
697-
Feature64Bit /*, Feature64BitRegs */, FeatureMFTB,
702+
Feature64BitSupport /*, Feature64BitRegs */, FeatureMFTB,
698703
FeatureISA2_06]>;
699704
def : ProcessorModel<"pwr3", G5Model,
700705
[DirectivePwr3, FeatureAltivec,
701706
FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
702-
FeatureSTFIWX, Feature64Bit]>;
707+
FeatureSTFIWX, Feature64BitSupport]>;
703708
def : ProcessorModel<"pwr4", G5Model,
704709
[DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
705710
FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
706-
FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
711+
FeatureSTFIWX, Feature64BitSupport, FeatureMFTB]>;
707712
def : ProcessorModel<"pwr5", G5Model,
708713
[DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
709714
FeatureFSqrt, FeatureFRE, FeatureFRES,
710715
FeatureFRSQRTE, FeatureFRSQRTES,
711-
FeatureSTFIWX, Feature64Bit,
716+
FeatureSTFIWX, Feature64BitSupport,
712717
FeatureMFTB, DeprecatedDST]>;
713718
def : ProcessorModel<"pwr5x", G5Model,
714719
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
715720
FeatureFSqrt, FeatureFRE, FeatureFRES,
716721
FeatureFRSQRTE, FeatureFRSQRTES,
717-
FeatureSTFIWX, FeatureFPRND, Feature64Bit,
722+
FeatureSTFIWX, FeatureFPRND, Feature64BitSupport,
718723
FeatureMFTB, DeprecatedDST]>;
719724
def : ProcessorModel<"pwr6", G5Model,
720725
[DirectivePwr6, FeatureAltivec,
721726
FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
722727
FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
723728
FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
724-
FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
729+
FeatureFPRND, Feature64BitSupport /*, Feature64BitRegs */,
725730
FeatureMFTB, DeprecatedDST]>;
726731
def : ProcessorModel<"pwr6x", G5Model,
727732
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
728733
FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
729734
FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
730735
FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
731-
FeatureFPRND, Feature64Bit,
736+
FeatureFPRND, Feature64BitSupport,
732737
FeatureMFTB, DeprecatedDST]>;
733738
def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
734739
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
@@ -746,7 +751,7 @@ def : ProcessorModel<"ppc64", G5Model,
746751
[Directive64, FeatureAltivec,
747752
FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
748753
FeatureFRSQRTE, FeatureSTFIWX,
749-
Feature64Bit /*, Feature64BitRegs */,
754+
Feature64BitSupport /*, Feature64BitRegs */,
750755
FeatureMFTB]>;
751756
def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
752757

‎llvm/lib/Target/PowerPC/PPCSubtarget.cpp‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -54,10 +54,8 @@ PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
5454

5555
PPCSubtarget::PPCSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
5656
StringRef FS, const PPCTargetMachine &TM)
57-
: PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS),
58-
IsPPC64(getTargetTriple().getArch() == Triple::ppc64 ||
59-
getTargetTriple().getArch() == Triple::ppc64le),
60-
TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
57+
: PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS), TM(TM),
58+
FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
6159
InstrInfo(*this), TLInfo(TM, *this) {
6260
TSInfo = std::make_unique<PPCSelectionDAGInfo>();
6361

@@ -247,7 +245,6 @@ CodeModel::Model PPCSubtarget::getCodeModel(const TargetMachine &TM,
247245
}
248246

249247
bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
250-
bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
251248

252249
bool PPCSubtarget::isUsingPCRelativeCalls() const {
253250
return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&

‎llvm/lib/Target/PowerPC/PPCSubtarget.h‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,6 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
9393
/// Which cpu directive was used.
9494
unsigned CPUDirective;
9595

96-
bool IsPPC64;
9796
bool IsLittleEndian;
9897

9998
POPCNTDKind HasPOPCNTD;
@@ -167,10 +166,6 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
167166
void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
168167

169168
public:
170-
/// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
171-
///
172-
bool isPPC64() const;
173-
174169
// useSoftFloat - Return true if soft-float option is turned on.
175170
bool useSoftFloat() const {
176171
if (isAIXABI() && !HasHardFloat)

‎llvm/test/CodeGen/PowerPC/i64_fp.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,17 @@
11
; fcfid and fctid should be generated when the 64bit feature is enabled, but not
22
; otherwise.
33

4-
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit | \
4+
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit-support | \
55
; RUN: grep fcfid
6-
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit | \
6+
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit-support | \
77
; RUN: grep fctidz
88
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g5 | \
99
; RUN: grep fcfid
1010
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g5 | \
1111
; RUN: grep fctidz
12-
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit | \
12+
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit-support | \
1313
; RUN: not grep fcfid
14-
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit | \
14+
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit-support | \
1515
; RUN: not grep fctidz
1616
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g4 | \
1717
; RUN: not grep fcfid

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