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[DAG] Remove OneUse restriction on sext when folding (shl (sext (add_nsw x, c1)), c2)
This patch remove the restriction for folding (shl (sext (add_nsw x, c1)), c2) -> (add (shl (sext x), c2), c1 << c2), and test case from dhrystone , see this link: https://godbolt.org/z/8zfa3rnad
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5 files changed

+24
-14
lines changed

5 files changed

+24
-14
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10054,8 +10054,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
1005410054
// TODO: Should we limit this with isLegalAddImmediate?
1005510055
if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1005610056
N0.getOperand(0).getOpcode() == ISD::ADD &&
10057-
N0.getOperand(0)->getFlags().hasNoSignedWrap() && N0->hasOneUse() &&
10058-
N0.getOperand(0)->hasOneUse() &&
10057+
N0.getOperand(0)->getFlags().hasNoSignedWrap() &&
1005910058
TLI.isDesirableToCommuteWithShift(N, Level)) {
1006010059
SDValue Add = N0.getOperand(0);
1006110060
SDLoc DL(N0);

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3370,6 +3370,17 @@ X86TargetLowering::preferredShiftLegalizationStrategy(
33703370
ExpansionFactor);
33713371
}
33723372

3373+
bool X86TargetLowering::isDesirableToCommuteWithShift(
3374+
const SDNode *N, CombineLevel Level) const {
3375+
assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
3376+
N->getOpcode() == ISD::SRL) &&
3377+
"Expected shift op");
3378+
SDValue N0 = N->getOperand(0).getOpcode() == ISD::SIGN_EXTEND
3379+
? N->getOperand(0)->getOperand(0)
3380+
: N->getOperand(0);
3381+
return N0.hasOneUse();
3382+
}
3383+
33733384
bool X86TargetLowering::shouldSplatInsEltVarIndex(EVT VT) const {
33743385
// Any legal vector type can be splatted more efficiently than
33753386
// loading/spilling from memory.

llvm/lib/Target/X86/X86ISelLowering.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1172,6 +1172,9 @@ namespace llvm {
11721172
preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
11731173
unsigned ExpansionFactor) const override;
11741174

1175+
bool isDesirableToCommuteWithShift(const SDNode *N,
1176+
CombineLevel Level) const override;
1177+
11751178
bool shouldSplatInsEltVarIndex(EVT VT) const override;
11761179

11771180
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override {

llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll

Lines changed: 7 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5,12 +5,10 @@
55
define void @test(ptr nocapture noundef writeonly %array1, i32 noundef signext %a, i32 noundef signext %b) {
66
; RV64-LABEL: test:
77
; RV64: # %bb.0: # %entry
8-
; RV64-NEXT: addiw a3, a1, 5
9-
; RV64-NEXT: slli a4, a3, 2
10-
; RV64-NEXT: add a4, a0, a4
11-
; RV64-NEXT: sw a2, 0(a4)
8+
; RV64-NEXT: addi a3, a1, 5
129
; RV64-NEXT: slli a1, a1, 2
1310
; RV64-NEXT: add a0, a1, a0
11+
; RV64-NEXT: sw a2, 20(a0)
1412
; RV64-NEXT: sw a2, 24(a0)
1513
; RV64-NEXT: sw a3, 140(a0)
1614
; RV64-NEXT: ret
@@ -34,18 +32,16 @@ entry:
3432
define void @test1(ptr nocapture noundef %array1, i32 noundef signext %a, i32 noundef signext %b, i32 noundef signext %x) {
3533
; RV64-LABEL: test1:
3634
; RV64: # %bb.0: # %entry
37-
; RV64-NEXT: addiw a4, a1, 5
38-
; RV64-NEXT: slli a5, a4, 2
39-
; RV64-NEXT: add a5, a0, a5
40-
; RV64-NEXT: mv a6, a4
35+
; RV64-NEXT: addi a4, a1, 5
36+
; RV64-NEXT: mv a5, a4
4137
; RV64-NEXT: bgtz a3, .LBB1_2
4238
; RV64-NEXT: # %bb.1: # %entry
43-
; RV64-NEXT: mv a6, a2
39+
; RV64-NEXT: mv a5, a2
4440
; RV64-NEXT: .LBB1_2: # %entry
45-
; RV64-NEXT: sw a6, 0(a5)
4641
; RV64-NEXT: slli a1, a1, 2
4742
; RV64-NEXT: add a0, a1, a0
48-
; RV64-NEXT: sw a6, 24(a0)
43+
; RV64-NEXT: sw a5, 20(a0)
44+
; RV64-NEXT: sw a5, 24(a0)
4945
; RV64-NEXT: sw a4, 140(a0)
5046
; RV64-NEXT: ret
5147
entry:

llvm/test/CodeGen/X86/pr65895.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,10 +21,11 @@ define i32 @PR65895() {
2121
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
2222
; CHECK-NEXT: jmp .LBB0_2
2323
; CHECK-NEXT: .LBB0_3: # %for.end
24+
; CHECK-NEXT: movzbl %al, %ecx
2425
; CHECK-NEXT: addb $-3, %al
2526
; CHECK-NEXT: movsbl %al, %eax
2627
; CHECK-NEXT: movl %eax, d(%rip)
27-
; CHECK-NEXT: leal 247(%rax,%rax,2), %eax
28+
; CHECK-NEXT: leal 241(%rax,%rcx,2), %eax
2829
; CHECK-NEXT: movb $1, c(%rip)
2930
; CHECK-NEXT: movsbq %al, %rax
3031
; CHECK-NEXT: movq %rax, e(%rip)

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