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[AMDGPU] Disable inline constants for pseudo scalar transcendentals (#104395)
Prevent operand folding from inlining constants into pseudo scalar transcendental f16 instructions. However still allow literal constants.
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‎llvm/lib/Target/AMDGPU/GCNSubtarget.h‎

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@@ -1289,6 +1289,12 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
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/// and STOREcnt rather than VMcnt, LGKMcnt and VScnt respectively.
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bool hasExtendedWaitCounts() const { return getGeneration() >= GFX12; }
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/// \returns true if inline constants are not supported for F16 pseudo
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/// scalar transcendentals.
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bool hasNoF16PseudoScalarTransInlineConstants() const {
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return getGeneration() == GFX12;
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}
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/// \returns The maximum number of instructions that can be enclosed in an
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/// S_CLAUSE on the given subtarget, or 0 for targets that do not support that
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/// instruction.

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

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@@ -5776,6 +5776,10 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
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return false;
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}
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}
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} else if (ST.hasNoF16PseudoScalarTransInlineConstants() && !MO->isReg() &&
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isF16PseudoScalarTrans(MI.getOpcode()) &&
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isInlineConstant(*MO, OpInfo)) {
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return false;
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}
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if (MO->isReg()) {

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

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@@ -946,6 +946,14 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
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Opcode == AMDGPU::DS_GWS_BARRIER;
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}
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static bool isF16PseudoScalarTrans(unsigned Opcode) {
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return Opcode == AMDGPU::V_S_EXP_F16_e64 ||
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Opcode == AMDGPU::V_S_LOG_F16_e64 ||
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Opcode == AMDGPU::V_S_RCP_F16_e64 ||
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Opcode == AMDGPU::V_S_RSQ_F16_e64 ||
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Opcode == AMDGPU::V_S_SQRT_F16_e64;
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}
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static bool doesNotReadTiedSource(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
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}

‎llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
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# Do not use inline constants for f16 pseudo scalar transcendentals.
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# But allow literal constants.
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---
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name: exp_f16_imm
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: exp_f16_imm
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
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; GCN-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
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%0:sgpr_32 = S_MOV_B32 15360
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%1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
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...
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---
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name: exp_f16_literal
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: exp_f16_literal
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; GCN: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
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%0:sgpr_32 = S_MOV_B32 16960
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%1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
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...
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---
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name: log_f16_imm
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: log_f16_imm
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
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; GCN-NEXT: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
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%0:sgpr_32 = S_MOV_B32 15360
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%1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
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...
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---
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name: log_f16_literal
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: log_f16_literal
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; GCN: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
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%0:sgpr_32 = S_MOV_B32 16960
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%1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
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...
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---
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name: rcp_f16_imm
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: rcp_f16_imm
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
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; GCN-NEXT: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
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%0:sgpr_32 = S_MOV_B32 15360
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%1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
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...
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---
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name: rcp_f16_literal
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: rcp_f16_literal
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; GCN: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
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%0:sgpr_32 = S_MOV_B32 16960
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%1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
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...
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---
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name: rsq_f16_imm
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: rsq_f16_imm
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
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; GCN-NEXT: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
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%0:sgpr_32 = S_MOV_B32 15360
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%1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
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...
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---
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name: rsq_f16_literal
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: rsq_f16_literal
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; GCN: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
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%0:sgpr_32 = S_MOV_B32 16960
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%1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
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...
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---
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name: sqrt_f16_imm
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: sqrt_f16_imm
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
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; GCN-NEXT: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
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%0:sgpr_32 = S_MOV_B32 15360
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%1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
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...
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---
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name: sqrt_f16_literal
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: sqrt_f16_literal
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; GCN: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
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%0:sgpr_32 = S_MOV_B32 16960
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%1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
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...

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