[RISCV][SiFive7] Change Latency of VCIX to the default

[michalt]

Currently we multiply the default (SiFive7GetCyclesDefault) by 10, but this turns out to be both surprising to our users and leads to worse codegen in most cases. I think it's more natural to just keep the default.

In the end the right solution is probably to have a separate scheduling model for a particular VCIX coprocessor.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Michal Terepeta (michalt)

Changes

Currently we multiply the default (SiFive7GetCyclesDefault) by 10, but this turns out to be both surprising to our users and leads to worse codegen in most cases. I think it's more natural to just keep the default.

In the end the right solution is probably to have a separate scheduling model for a particular VCIX coprocessor.

---

Full diff: https://github.com/llvm/llvm-project/pull/106497.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (+1-1)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 0b0ac0c368d070..72560284dde2f5 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -973,7 +973,7 @@ def : InstRW<[WriteIALU], (instrs COPY)>;
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = !mul(Cycles, 10),
+  let Latency = Cycles,
       AcquireAtCycles = [0, 1],
       ReleaseAtCycles = [1, !add(1, Cycles)] in {
     defm "" : LMULWriteResMX<"WriteVC_V_I",   [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;

[michalt]

@topperc @michaelmaitland Would you be ok with this change?

[michaelmaitland]

I think this is reasonable. Left a small nit.

[michaelmaitland]

LGTM

[michalt]

@michaelmaitland Thank you for the review! 😀 Could I also ask you to merge? (I don't have commit access)

[michalt]

Thanks! 😄