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[AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (llvm#86972)
Fixes llvm#86917 `FCMP_TRUE` and `FCMP_FALSE` were previously not considered and we ended up in an llvm_unreachable assertion.
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‎llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,12 @@ void AArch64GISelUtils::changeFCMPPredToAArch64CC(
147147
case CmpInst::FCMP_UNE:
148148
CondCode = AArch64CC::NE;
149149
break;
150+
case CmpInst::FCMP_TRUE:
151+
CondCode = AArch64CC::AL;
152+
break;
153+
case CmpInst::FCMP_FALSE:
154+
CondCode = AArch64CC::NV;
155+
break;
150156
}
151157
}
152158

‎llvm/test/CodeGen/AArch64/GlobalISel/select.mir‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,14 @@ registers:
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
185185
- { id: 7, class: gpr }
186+
- { id: 8, class: fpr }
187+
- { id: 9, class: gpr }
188+
- { id: 10, class: fpr }
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- { id: 11, class: gpr }
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- { id: 12, class: gpr }
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- { id: 13, class: gpr }
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- { id: 14, class: gpr }
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- { id: 15, class: gpr }
186194

187195
# CHECK: body:
188196
# CHECK: nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
@@ -209,6 +217,18 @@ body: |
209217
%7(s32) = G_ANYEXT %5
210218
$w0 = COPY %7(s32)
211219
220+
%8(s32) = COPY $s0
221+
%9(s32) = G_FCMP floatpred(true), %8, %8
222+
%12(s8) = G_TRUNC %9(s32)
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%14(s32) = G_ANYEXT %12
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$w0 = COPY %14(s32)
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226+
%10(s64) = COPY $d0
227+
%11(s32) = G_FCMP floatpred(false), %10, %10
228+
%13(s8) = G_TRUNC %11(s32)
229+
%15(s32) = G_ANYEXT %13
230+
$w0 = COPY %15(s32)
231+
212232
...
213233

214234
---

‎llvm/test/CodeGen/AArch64/neon-compare-instructions.ll‎

Lines changed: 101 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2870,6 +2870,107 @@ define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) {
28702870
ret <2 x i64> %tmp4
28712871
}
28722872

2873+
define <2 x i32> @fcmal2xfloat(<2 x float> %A, <2 x float> %B) {
2874+
; CHECK-SD-LABEL: fcmal2xfloat:
2875+
; CHECK-SD: // %bb.0:
2876+
; CHECK-SD-NEXT: movi v0.2d, #0xffffffffffffffff
2877+
; CHECK-SD-NEXT: ret
2878+
;
2879+
; CHECK-GI-LABEL: fcmal2xfloat:
2880+
; CHECK-GI: // %bb.0:
2881+
; CHECK-GI-NEXT: movi v0.2s, #1
2882+
; CHECK-GI-NEXT: shl v0.2s, v0.2s, #31
2883+
; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #31
2884+
; CHECK-GI-NEXT: ret
2885+
%tmp3 = fcmp true <2 x float> %A, %B
2886+
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2887+
ret <2 x i32> %tmp4
2888+
}
2889+
2890+
define <4 x i32> @fcmal4xfloat(<4 x float> %A, <4 x float> %B) {
2891+
; CHECK-SD-LABEL: fcmal4xfloat:
2892+
; CHECK-SD: // %bb.0:
2893+
; CHECK-SD-NEXT: movi v0.2d, #0xffffffffffffffff
2894+
; CHECK-SD-NEXT: ret
2895+
;
2896+
; CHECK-GI-LABEL: fcmal4xfloat:
2897+
; CHECK-GI: // %bb.0:
2898+
; CHECK-GI-NEXT: mov w8, #1 // =0x1
2899+
; CHECK-GI-NEXT: fmov s0, w8
2900+
; CHECK-GI-NEXT: mov v1.16b, v0.16b
2901+
; CHECK-GI-NEXT: mov v1.h[1], v0.h[0]
2902+
; CHECK-GI-NEXT: mov v0.h[1], v0.h[0]
2903+
; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
2904+
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
2905+
; CHECK-GI-NEXT: mov v1.d[1], v0.d[0]
2906+
; CHECK-GI-NEXT: shl v0.4s, v1.4s, #31
2907+
; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31
2908+
; CHECK-GI-NEXT: ret
2909+
%tmp3 = fcmp true <4 x float> %A, %B
2910+
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2911+
ret <4 x i32> %tmp4
2912+
}
2913+
define <2 x i64> @fcmal2xdouble(<2 x double> %A, <2 x double> %B) {
2914+
; CHECK-SD-LABEL: fcmal2xdouble:
2915+
; CHECK-SD: // %bb.0:
2916+
; CHECK-SD-NEXT: movi v0.2d, #0xffffffffffffffff
2917+
; CHECK-SD-NEXT: ret
2918+
;
2919+
; CHECK-GI-LABEL: fcmal2xdouble:
2920+
; CHECK-GI: // %bb.0:
2921+
; CHECK-GI-NEXT: adrp x8, .LCPI221_0
2922+
; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI221_0]
2923+
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #63
2924+
; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #63
2925+
; CHECK-GI-NEXT: ret
2926+
%tmp3 = fcmp true <2 x double> %A, %B
2927+
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2928+
ret <2 x i64> %tmp4
2929+
}
2930+
2931+
define <2 x i32> @fcmnv2xfloat(<2 x float> %A, <2 x float> %B) {
2932+
; CHECK-LABEL: fcmnv2xfloat:
2933+
; CHECK: // %bb.0:
2934+
; CHECK-NEXT: movi v0.2d, #0000000000000000
2935+
; CHECK-NEXT: ret
2936+
%tmp3 = fcmp false <2 x float> %A, %B
2937+
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2938+
ret <2 x i32> %tmp4
2939+
}
2940+
2941+
define <4 x i32> @fcmnv4xfloat(<4 x float> %A, <4 x float> %B) {
2942+
; CHECK-SD-LABEL: fcmnv4xfloat:
2943+
; CHECK-SD: // %bb.0:
2944+
; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
2945+
; CHECK-SD-NEXT: ret
2946+
;
2947+
; CHECK-GI-LABEL: fcmnv4xfloat:
2948+
; CHECK-GI: // %bb.0:
2949+
; CHECK-GI-NEXT: mov w8, #0 // =0x0
2950+
; CHECK-GI-NEXT: fmov s0, w8
2951+
; CHECK-GI-NEXT: mov v1.16b, v0.16b
2952+
; CHECK-GI-NEXT: mov v1.h[1], v0.h[0]
2953+
; CHECK-GI-NEXT: mov v0.h[1], v0.h[0]
2954+
; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
2955+
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
2956+
; CHECK-GI-NEXT: mov v1.d[1], v0.d[0]
2957+
; CHECK-GI-NEXT: shl v0.4s, v1.4s, #31
2958+
; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31
2959+
; CHECK-GI-NEXT: ret
2960+
%tmp3 = fcmp false <4 x float> %A, %B
2961+
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2962+
ret <4 x i32> %tmp4
2963+
}
2964+
define <2 x i64> @fcmnv2xdouble(<2 x double> %A, <2 x double> %B) {
2965+
; CHECK-LABEL: fcmnv2xdouble:
2966+
; CHECK: // %bb.0:
2967+
; CHECK-NEXT: movi v0.2d, #0000000000000000
2968+
; CHECK-NEXT: ret
2969+
%tmp3 = fcmp false <2 x double> %A, %B
2970+
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2971+
ret <2 x i64> %tmp4
2972+
}
2973+
28732974
define <2 x i32> @fcmoeqz2xfloat(<2 x float> %A) {
28742975
; CHECK-LABEL: fcmoeqz2xfloat:
28752976
; CHECK: // %bb.0:

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