@@ -2586,7 +2586,7 @@ int foobar() {
25862586// SIMD1-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4
25872587// SIMD1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
25882588// SIMD1-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4
2589- // SIMD1-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4
2589+ // SIMD1-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([ 2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0 , i64 1), align 4
25902590// SIMD1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4
25912591// SIMD1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
25922592// SIMD1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4
@@ -2663,7 +2663,7 @@ int foobar() {
26632663// SIMD1-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4
26642664// SIMD1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
26652665// SIMD1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4
2666- // SIMD1-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4
2666+ // SIMD1-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([ 2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0 , i64 1), align 4
26672667// SIMD1-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4
26682668// SIMD1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
26692669// SIMD1-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4
@@ -3052,7 +3052,7 @@ int foobar() {
30523052// SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG187:![0-9]+]]
30533053// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG187]]
30543054// SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG187]]
3055- // SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG188:![0-9]+]]
3055+ // SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([ 2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0 , i64 1), align 4, !dbg [[DBG188:![0-9]+]]
30563056// SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG189:![0-9]+]]
30573057// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG189]]
30583058// SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG189]]
@@ -3133,7 +3133,7 @@ int foobar() {
31333133// SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG222:![0-9]+]]
31343134// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG222]]
31353135// SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG222]]
3136- // SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG223:![0-9]+]]
3136+ // SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([ 2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0 , i64 1), align 4, !dbg [[DBG223:![0-9]+]]
31373137// SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]]
31383138// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG224]]
31393139// SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG224]]
@@ -5707,7 +5707,7 @@ int foobar() {
57075707// SIMD3-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4
57085708// SIMD3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
57095709// SIMD3-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4
5710- // SIMD3-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4
5710+ // SIMD3-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([ 2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0 , i64 1), align 4
57115711// SIMD3-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4
57125712// SIMD3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
57135713// SIMD3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4
@@ -5784,7 +5784,7 @@ int foobar() {
57845784// SIMD3-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4
57855785// SIMD3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
57865786// SIMD3-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4
5787- // SIMD3-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4
5787+ // SIMD3-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([ 2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0 , i64 1), align 4
57885788// SIMD3-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4
57895789// SIMD3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
57905790// SIMD3-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4
@@ -6173,7 +6173,7 @@ int foobar() {
61736173// SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG187:![0-9]+]]
61746174// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG187]]
61756175// SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG187]]
6176- // SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG188:![0-9]+]]
6176+ // SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([ 2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0 , i64 1), align 4, !dbg [[DBG188:![0-9]+]]
61776177// SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG189:![0-9]+]]
61786178// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG189]]
61796179// SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG189]]
@@ -6254,7 +6254,7 @@ int foobar() {
62546254// SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG222:![0-9]+]]
62556255// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG222]]
62566256// SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG222]]
6257- // SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG223:![0-9]+]]
6257+ // SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([ 2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0 , i64 1), align 4, !dbg [[DBG223:![0-9]+]]
62586258// SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]]
62596259// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG224]]
62606260// SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG224]]
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