@@ -53,13 +53,13 @@ pub(crate) fn detect_features() -> cache::Initializer {
5353 ) ;
5454 }
5555
56- parse_system_registers ( aa64isar0, aa64isar1, aa64pfr0)
56+ parse_system_registers ( aa64isar0, aa64isar1, Some ( aa64pfr0) )
5757}
5858
5959pub ( crate ) fn parse_system_registers (
6060 aa64isar0 : u64 ,
6161 aa64isar1 : u64 ,
62- aa64pfr0 : u64 ,
62+ aa64pfr0 : Option < u64 > ,
6363) -> cache:: Initializer {
6464 let mut value = cache:: Initializer :: default ( ) ;
6565
@@ -76,26 +76,28 @@ pub(crate) fn parse_system_registers(
7676 enable_feature ( Feature :: crc, bits_shift ( aa64isar0, 19 , 16 ) >= 1 ) ;
7777
7878 // ID_AA64PFR0_EL1 - Processor Feature Register 0
79- let fp = bits_shift ( aa64pfr0, 19 , 16 ) < 0xF ;
80- let fphp = bits_shift ( aa64pfr0, 19 , 16 ) >= 1 ;
81- let asimd = bits_shift ( aa64pfr0, 23 , 20 ) < 0xF ;
82- let asimdhp = bits_shift ( aa64pfr0, 23 , 20 ) >= 1 ;
83- enable_feature ( Feature :: fp, fp) ;
84- enable_feature ( Feature :: fp16, fphp) ;
85- // SIMD support requires float support - if half-floats are
86- // supported, it also requires half-float support:
87- enable_feature ( Feature :: asimd, fp && asimd && ( !fphp | asimdhp) ) ;
88- // SIMD extensions require SIMD support:
89- enable_feature ( Feature :: aes, asimd && bits_shift ( aa64isar0, 7 , 4 ) >= 1 ) ;
90- let sha1 = bits_shift ( aa64isar0, 11 , 8 ) >= 1 ;
91- let sha2 = bits_shift ( aa64isar0, 15 , 12 ) >= 1 ;
92- enable_feature ( Feature :: sha2, asimd && sha1 && sha2) ;
93- enable_feature ( Feature :: rdm, asimd && bits_shift ( aa64isar0, 31 , 28 ) >= 1 ) ;
94- enable_feature (
95- Feature :: dotprod,
96- asimd && bits_shift ( aa64isar0, 47 , 44 ) >= 1 ,
97- ) ;
98- enable_feature ( Feature :: sve, asimd && bits_shift ( aa64pfr0, 35 , 32 ) >= 1 ) ;
79+ if let Some ( aa64pfr0) = aa64pfr0 {
80+ let fp = bits_shift ( aa64pfr0, 19 , 16 ) < 0xF ;
81+ let fphp = bits_shift ( aa64pfr0, 19 , 16 ) >= 1 ;
82+ let asimd = bits_shift ( aa64pfr0, 23 , 20 ) < 0xF ;
83+ let asimdhp = bits_shift ( aa64pfr0, 23 , 20 ) >= 1 ;
84+ enable_feature ( Feature :: fp, fp) ;
85+ enable_feature ( Feature :: fp16, fphp) ;
86+ // SIMD support requires float support - if half-floats are
87+ // supported, it also requires half-float support:
88+ enable_feature ( Feature :: asimd, fp && asimd && ( !fphp | asimdhp) ) ;
89+ // SIMD extensions require SIMD support:
90+ enable_feature ( Feature :: aes, asimd && bits_shift ( aa64isar0, 7 , 4 ) >= 1 ) ;
91+ let sha1 = bits_shift ( aa64isar0, 11 , 8 ) >= 1 ;
92+ let sha2 = bits_shift ( aa64isar0, 15 , 12 ) >= 1 ;
93+ enable_feature ( Feature :: sha2, asimd && sha1 && sha2) ;
94+ enable_feature ( Feature :: rdm, asimd && bits_shift ( aa64isar0, 31 , 28 ) >= 1 ) ;
95+ enable_feature (
96+ Feature :: dotprod,
97+ asimd && bits_shift ( aa64isar0, 47 , 44 ) >= 1 ,
98+ ) ;
99+ enable_feature ( Feature :: sve, asimd && bits_shift ( aa64pfr0, 35 , 32 ) >= 1 ) ;
100+ }
99101
100102 // ID_AA64PFR0_EL1 - Processor Feature Register 0
101103 // Check for either APA or API field
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