Merge branch 'master' into fixed_channel_parse_fix

Author: AmirhosseinPoolad

libs/libarchfpga/src/logic_types.h

@@ -62,10 +62,8 @@ struct t_model {
     bool never_prune = false;               ///< Don't remove from the netlist even if a block of this type has no output ports used and, therefore, unconnected to the rest of the netlist
 };
 
-// Tag for the logical model ID
-struct logical_model_id_tag;
 // A unique ID that represents a logical model in the architecture.
-typedef vtr::StrongId<logical_model_id_tag, size_t> LogicalModelId;
+typedef vtr::StrongId<struct logical_model_id_tag, size_t> LogicalModelId;
 
 /**
  * @brief A storage class containing all of the logical models in an FPGA

libs/librrgraph/src/base/rr_graph_fwd.h

@@ -15,16 +15,9 @@ class t_rr_graph_storage;
 
 class RRGraph;
 
-struct rr_node_id_tag;
-struct rr_edge_id_tag;
-struct rr_indexed_data_id_tag;
-struct rr_switch_id_tag;
-struct rr_segment_id_tag;
-struct rc_index_tag;
-
-typedef vtr::StrongId<rr_node_id_tag, uint32_t> RRNodeId;
-typedef vtr::StrongId<rr_edge_id_tag, uint32_t> RREdgeId;
-typedef vtr::StrongId<rr_indexed_data_id_tag, uint32_t> RRIndexedDataId;
-typedef vtr::StrongId<rr_switch_id_tag, uint16_t> RRSwitchId;
-typedef vtr::StrongId<rr_segment_id_tag, uint16_t> RRSegmentId;
-typedef vtr::StrongId<rc_index_tag, uint16_t> NodeRCIndex;
+typedef vtr::StrongId<struct rr_node_id_tag, uint32_t> RRNodeId;
+typedef vtr::StrongId<struct rr_edge_id_tag, uint32_t> RREdgeId;
+typedef vtr::StrongId<struct rr_indexed_data_id_tag, uint32_t> RRIndexedDataId;
+typedef vtr::StrongId<struct rr_switch_id_tag, uint16_t> RRSwitchId;
+typedef vtr::StrongId<struct rr_segment_id_tag, uint16_t> RRSegmentId;
+typedef vtr::StrongId<struct rc_index_tag, uint16_t> NodeRCIndex;

libs/libvtrutil/test/test_vector.cpp

@@ -5,8 +5,7 @@
 
 #include <ostream>
 
-struct test_tag;
-typedef vtr::StrongId<test_tag> TestId;
+typedef vtr::StrongId<struct test_tag> TestId;
 
 std::ostream& operator<<(std::ostream& os, const TestId id);
 

vpr/src/analytical_place/analytical_solver.h

@@ -39,8 +39,7 @@ class PreClusterTimingManager;
  * This gives a linearized ID for each of the moveable blocks from 0 to the
  * number of moveable blocks.
  */
-struct ap_row_id_tag {};
-typedef vtr::StrongId<ap_row_id_tag, size_t> APRowId;
+typedef vtr::StrongId<struct ap_row_id_tag, size_t> APRowId;
 
 /**
  * @brief The Analytical Solver base class

vpr/src/analytical_place/flat_placement_bins.h

@@ -19,13 +19,10 @@
 #include "vtr_vector.h"
 #include "vtr_vector_map.h"
 
-// The tag for the flat placement bin.
-struct flat_placement_bin_tag {};
-
 /**
  * @brief A unique ID to a flat placement bin.
  */
-typedef vtr::StrongId<flat_placement_bin_tag, size_t> FlatPlacementBinId;
+typedef vtr::StrongId<struct flat_placement_bin_tag, size_t> FlatPlacementBinId;
 
 /**
  * @brief A container of bins which hold AP blocks and take up space on the FPGA.

vpr/src/analytical_place/full_legalizer.cpp

@@ -98,8 +98,7 @@ namespace {
 /// This is used for putting the molecules in bins for packing.
 // FIXME: Bring this into the device_grid.
 //  - Maybe this can be called DeviceRootTileId or something.
-struct device_tile_id_tag {};
-typedef vtr::StrongId<device_tile_id_tag, size_t> DeviceTileId;
+typedef vtr::StrongId<struct device_tile_id_tag, size_t> DeviceTileId;
 
 /**
  * @brief Helper class to place cluster in the AP context.

vpr/src/analytical_place/global_placer.cpp

@@ -127,7 +127,8 @@ static void print_placement_stats(const PartialPlacement& p_placement,
                                   FlatPlacementDensityManager& density_manager,
                                   const PreClusterTimingManager& pre_cluster_timing_manager) {
     // Print the placement HPWL
-    VTR_LOG("\tPlacement HPWL: %f\n", p_placement.get_hpwl(ap_netlist));
+    VTR_LOG("\tPlacement objective HPWL: %f\n", p_placement.get_hpwl(ap_netlist));
+    VTR_LOG("\tPlacement estimated wirelength: %u\n", p_placement.estimate_post_placement_wirelength(ap_netlist));
 
     // Print the timing information.
     if (pre_cluster_timing_manager.is_valid()) {

vpr/src/analytical_place/model_grouper.h

@@ -18,11 +18,8 @@
 // Forward declarations.
 class Prepacker;
 
-/// @brief Tag for the ModelGroupId
-struct model_group_id_tag;
-
 /// @brief A unique ID of a group of models created by the ModelGrouper class.
-typedef vtr::StrongId<model_group_id_tag, size_t> ModelGroupId;
+typedef vtr::StrongId<struct model_group_id_tag, size_t> ModelGroupId;
 
 /**
  * @brief A manager class for grouping together models that must be legalized

vpr/src/analytical_place/partial_legalizer.h

@@ -340,11 +340,8 @@ class PerPrimitiveDimPrefixSum2D {
     vtr::vector<PrimitiveVectorDim, vtr::PrefixSum2D<float>> dim_prefix_sum_;
 };
 
-/// @brief Tag for the PrimitiveGroupId
-struct primitive_group_id_tag;
-
 /// @brief A unique ID of a group of primitive dims created by the PrimitiveDimGrouper class.
-typedef vtr::StrongId<primitive_group_id_tag, size_t> PrimitiveGroupId;
+typedef vtr::StrongId<struct primitive_group_id_tag, size_t> PrimitiveGroupId;
 
 /**
  * @brief A manager class for grouping together dimensions of the primitive

vpr/src/analytical_place/partial_placement.cpp

@@ -33,6 +33,48 @@ double PartialPlacement::get_hpwl(const APNetlist& netlist) const {
     return hpwl;
 }
 
+double PartialPlacement::estimate_post_placement_wirelength(const APNetlist& netlist) const {
+    // Go through each net and calculate the half-perimeter wirelength. Since
+    // we want to estimate the post-placement wirelength, we do not want the
+    // flat placement positions of the blocks. Instead we compute the HPWL over
+    // the tiles that the flat placement is placing the blocks over.
+    unsigned total_hpwl = 0;
+    for (APNetId net_id : netlist.nets()) {
+        // Note: Other wirelength estimates in VTR ignore global nets; however
+        //       it is not known if a net is global or not until packing is
+        //       complete. For now, we just approximate post-placement wirelength
+        //       using the HPWL (in tile space).
+        // TODO: The reason we do not know what nets are ignored / global is
+        //       because the pin on the tile that the net connects to is what
+        //       decides if a net is global / ignored for place and route. Since
+        //       we have not packed anything yet, we do not know what pin each
+        //       net will go to; however, we can probably get a good idea based
+        //       on some properties of the net and the tile its going to / from.
+        //       Should investigate this to get a better estimate of wirelength.
+        double min_x = std::numeric_limits<unsigned>::max();
+        double max_x = std::numeric_limits<unsigned>::lowest();
+        double min_y = std::numeric_limits<unsigned>::max();
+        double max_y = std::numeric_limits<unsigned>::lowest();
+        for (APPinId pin_id : netlist.net_pins(net_id)) {
+            APBlockId blk_id = netlist.pin_block(pin_id);
+            min_x = std::min(min_x, block_x_locs[blk_id]);
+            max_x = std::max(max_x, block_x_locs[blk_id]);
+            min_y = std::min(min_y, block_y_locs[blk_id]);
+            max_y = std::max(max_y, block_y_locs[blk_id]);
+        }
+        VTR_ASSERT_SAFE(max_x >= min_x && max_y >= min_y);
+
+        // Floor the positions to get the x and y coordinates of the tiles each
+        // block belongs to.
+        unsigned tile_dx = std::floor(max_x) - std::floor(min_x);
+        unsigned tile_dy = std::floor(max_y) - std::floor(min_y);
+
+        total_hpwl += tile_dx + tile_dy;
+    }
+
+    return total_hpwl;
+}
+
 bool PartialPlacement::verify_locs(const APNetlist& netlist,
                                    size_t grid_width,
                                    size_t grid_height) const {