diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt index cb40c2de73c..a1a02980315 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt @@ -1,5 +1,6 @@ regression_tests/vtr_reg_nightly_test7/ap_titan regression_tests/vtr_reg_nightly_test7/titan_other_run_flat +regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_run_flat #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_depop_run_flat #regression_tests/vtr_reg_nightly_test7/verify_router_lookahead_run_flat diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/config.txt new file mode 100644 index 00000000000..8d63b3eccc6 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/config.txt @@ -0,0 +1,58 @@ +############################################## +# Configuration file for running experiments +############################################## +# +# These are only the Titanium benchmarks which +# could be run in under around 2 hours. +# +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/titan_new/stratix10 + +# Path to directory of SDCs to use +sdc_dir=benchmarks/titan_blif/titan_new/stratix10 + +# Path to directory of architectures to use +archs_dir=arch/titan + +# Add circuits to list to sweep +circuit_list_add=ASU_LRN_stratix10_arch_timing.blif +# circuit_list_add=ChainNN_LRN_LG_stratix10_arch_timing.blif +# circuit_list_add=ChainNN_ELT_LG_stratix10_arch_timing.blif +# circuit_list_add=ChainNN_BSC_LG_stratix10_arch_timing.blif +circuit_list_add=ASU_ELT_stratix10_arch_timing.blif +circuit_list_add=ASU_BSC_stratix10_arch_timing.blif +circuit_list_add=tdfir_stratix10_arch_timing.blif +# circuit_list_add=pricing_stratix10_arch_timing.blif +circuit_list_add=mem_tester_stratix10_arch_timing.blif +circuit_list_add=mandelbrot_stratix10_arch_timing.blif +circuit_list_add=channelizer_stratix10_arch_timing.blif +circuit_list_add=fft1d_offchip_stratix10_arch_timing.blif +circuit_list_add=DLA_LRN_stratix10_arch_timing.blif +# circuit_list_add=matrix_mult_stratix10_arch_timing.blif +circuit_list_add=fft1d_stratix10_arch_timing.blif +circuit_list_add=fft2d_stratix10_arch_timing.blif +circuit_list_add=DLA_ELT_stratix10_arch_timing.blif +circuit_list_add=DLA_BSC_stratix10_arch_timing.blif +circuit_list_add=jpeg_deco_stratix10_arch_timing.blif +circuit_list_add=nyuzi_stratix10_arch_timing.blif +circuit_list_add=sobel_stratix10_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=stratix10_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan_s10.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan_s10.txt + +# The Titanium benchmarks are run at a fixed channel width of 400 to simulate a +# Stratix 10-like routing architecture. A large number of routing iterations is +# set to ensure the router doesn't give up too easily on the larger benchmarks. +script_params=-starting_stage vpr --route_chan_width 400 --max_router_iterations 400 --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/golden_results.txt new file mode 100644 index 00000000000..ba4e2b6719a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/golden_results.txt @@ -0,0 +1,17 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay 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