boards: Add Microchip CEC SoC family and SecureIoT1702 board

fabled · fabled · commit 4d09a30a23a6 · 2017-12-13T19:54:22.000+02:00
Adds minimal support for CEC1702 with support to communicate
via serial port.

Signed-off-by: Timo Teräs &lt;timo.teras@iki.fi&gt;
diff --git a/arch/arm/soc/microchip_cec/CMakeLists.txt b/arch/arm/soc/microchip_cec/CMakeLists.txt
@@ -0,0 +1,3 @@
+zephyr_sources(
+  soc_config.c
+  )
diff --git a/arch/arm/soc/microchip_cec/Kconfig b/arch/arm/soc/microchip_cec/Kconfig
@@ -0,0 +1,19 @@
+config SOC_FAMILY_CEC
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
+
+if SOC_FAMILY_CEC
+config SOC_FAMILY
+	string
+	default "microchip_cec"
+endif
+
+choice
+	prompt "Microchip CECxxxx MCU Selection"
+	depends on SOC_FAMILY_CEC
+
+config SOC_CEC1702
+	bool "CEC1702"
+
+endchoice
diff --git a/arch/arm/soc/microchip_cec/Kconfig.defconfig b/arch/arm/soc/microchip_cec/Kconfig.defconfig
@@ -0,0 +1,16 @@
+if SOC_FAMILY_CEC
+
+config SOC
+	default microchip_cec
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	# - include the UART interrupts
+	default 34
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 48000000
+
+endif
diff --git a/arch/arm/soc/microchip_cec/Kconfig.soc b/arch/arm/soc/microchip_cec/Kconfig.soc
@@ -0,0 +1,8 @@
+config SOC_FAMILY_CEC
+	bool "Microchip CECxxxx MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M4
+	select CPU_HAS_SYSTICK
+	select HAS_CEC_HAL
+	help
+	  Enable support for Micochip CEC Cortex-M4 microcontrollers.
diff --git a/arch/arm/soc/microchip_cec/linker.ld b/arch/arm/soc/microchip_cec/linker.ld
@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>
diff --git a/arch/arm/soc/microchip_cec/soc.h b/arch/arm/soc/microchip_cec/soc.h
@@ -0,0 +1,8 @@
+#ifndef CEC_SOC_H
+#define CEC_SOC_H
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(48)
+
+#include "MEC2016_INTERNAL.h"
+
+#endif
diff --git a/arch/arm/soc/microchip_cec/soc_config.c b/arch/arm/soc/microchip_cec/soc_config.c
@@ -0,0 +1,35 @@
+/**
+ * @file Board config file
+ */
+
+#include <device.h>
+#include <init.h>
+
+#include <kernel.h>
+
+#include "soc.h"
+
+static int soc_init(struct device *dev)
+{
+	__enable_irq();					/* Enable IRQs as ROM loader does PRIMASK=1 */
+	PCR->CLK_REQ_1 |= 1 << 0;			/* Clock: Interrupt block */
+	PCR->CLK_REQ_1 |= 1 << 8;			/* Clock: Processor */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	PCR->CLK_REQ_2 |= 1 << 1;			/* Clock: UART0 */
+	GPIO_100_137->GPIO_104_PIN_CONTROL = 1 << 12;	/* GPIO104 Alt1 = UART0_TX */
+	GPIO_100_137->GPIO_105_PIN_CONTROL = 1 << 12;	/* GPIO105 Alt1 = UART0_RX */
+	UART0->CONFIG = 0;				/* Reset on RESET_SYS */
+	UART0->ACTIVATE = 1;				/* Power up UART0 */
+#endif
+#ifdef CONFIG_UART_NS16550_PORT_1
+	PCR->CLK_REQ_2 |= 1 << 2;			/* Clock: UART1 */
+	GPIO_140_176->GPIO_170_PIN_CONTROL = 2 << 12;	/* GPIO170 Alt2 = UART1_TX */
+	GPIO_140_176->GPIO_171_PIN_CONTROL = 2 << 12;	/* GPIO171 Alt2 = UART1_RX */
+	GPIO_100_137->GPIO_113_PIN_CONTROL = 1 << 9;	/* GPIO113 drives UART1_RX_EN on secureiot1702 board */
+	UART1->CONFIG = 0;				/* Reset on RESET_SYS */
+	UART1->ACTIVATE = 1;				/* Power up UART1 */
+#endif
+	return 0;
+}
+
+SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/boards/arm/secureiot1702/Kconfig.board b/boards/arm/secureiot1702/Kconfig.board
@@ -0,0 +1,5 @@
+config BOARD_SECUREIOT1702
+	bool "Microchip SecureIoT1702"
+	depends on SOC_FAMILY_CEC
+	select HAS_DTS
+	select SOC_PART_NUMBER_CEC1702
diff --git a/boards/arm/secureiot1702/Kconfig.defconfig b/boards/arm/secureiot1702/Kconfig.defconfig
@@ -0,0 +1,6 @@
+if BOARD_SECUREIOT1702
+
+config BOARD
+	default secureiot1702
+
+endif
diff --git a/boards/arm/secureiot1702/board.h b/boards/arm/secureiot1702/board.h
diff --git a/boards/arm/secureiot1702/dts.fixup b/boards/arm/secureiot1702/dts.fixup
@@ -0,0 +1,19 @@
+/* This file is a temporary workaround for mapping of the generated information
+ * to the current driver definitions.  This will be removed when the drivers
+ * are modified to handle the generated information, or the mapping of
+ * generated data matches the driver definitions.
+ */
+
+
+#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_NS16550_REG_SHIFT		NS16550_400F2400_REG_SHIFT
+#define UART_NS16550_PORT_0_BASE_ADDR		NS16550_400F2400_BASE_ADDRESS_0
+#define UART_NS16550_PORT_0_CLK_FREQ		1843200
+#define CONFIG_UART_NS16550_PORT_0_NAME		NS16550_400F2400_LABEL
+#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE	NS16550_400F2400_CURRENT_SPEED
+
+#define UART_NS16550_PORT_1_BASE_ADDR		NS16550_400F2800_BASE_ADDRESS_0
+#define UART_NS16550_PORT_1_CLK_FREQ		1843200
+#define CONFIG_UART_NS16550_PORT_1_NAME		NS16550_400F2800_LABEL
+#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE	NS16550_400F2800_CURRENT_SPEED
diff --git a/boards/arm/secureiot1702/secureiot1702.dts b/boards/arm/secureiot1702/secureiot1702.dts
@@ -0,0 +1,27 @@
+/dts-v1/;
+
+#include "microchip/cec1702.dtsi"
+
+/ {
+	model = "Microchip SecureIoT1702 board";
+	compatible = "microchip,secureiot1702", "microchip,cec1702";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,flash = &flash0;
+	};
+
+	/*
+	GPIO054 = LED Red
+	GPIO053 = LED Green
+	GPIO001 = LED Blue
+	GPIO157 = LED White
+	*/
+};
+
+&uart0 {
+	status = "ok";
+	current-speed = <115200>;
+};
+
diff --git a/boards/arm/secureiot1702/secureiot1702_defconfig b/boards/arm/secureiot1702/secureiot1702_defconfig
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_SOC_FAMILY_CEC=y
+CONFIG_SOC_CEC1702=y
+CONFIG_BOARD_SECUREIOT1702=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
+CONFIG_HAS_DTS=y
+
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# No DT support for these yet
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_PORT_0=y
+CONFIG_UART_NS16550_PORT_1=y
+
diff --git a/dts/arm/microchip/cec1702.dtsi b/dts/arm/microchip/cec1702.dtsi
@@ -0,0 +1,45 @@
+/dts-v1/;
+
+#include "armv7-m.dtsi"
+
+/ {
+	compatible = "microchip,cec1702";
+
+	cpus {
+		cpu0 {
+			compatible = "arm,cortex-m4";
+		};
+	};
+
+	flash0: flash@000B0000 {
+		reg = <0x000B0000 0x68000>;
+	};
+
+	sram0: memory@00118000 {
+		compatible = "sram";
+		reg = <0x00118000 0x10000>;
+	};
+
+	soc {
+		uart0: uart@400f2400 {
+			compatible = "ns16550";
+			reg = <0x400f2400 0x400>;
+			interrupts = <40 0>;
+			current-speed = <115200>;
+			label = "UART_0";
+			reg-shift = <0>;
+		};
+		uart1: uart@400f2800 {
+			compatible = "ns16550";
+			reg = <0x400f2800 0x400>;
+			interrupts = <41 0>;
+			current-speed = <115200>;
+			label = "UART_1";
+			reg-shift = <0>;
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/ext/hal/CMakeLists.txt b/ext/hal/CMakeLists.txt
@@ -8,3 +8,4 @@ add_subdirectory(ti)
 add_subdirectory(silabs)
 add_subdirectory(esp)
 add_subdirectory_ifdef(CONFIG_HAS_ALTERA_HAL altera)
+add_subdirectory_ifdef(CONFIG_HAS_CEC_HAL cec)
diff --git a/ext/hal/Kconfig b/ext/hal/Kconfig
@@ -14,6 +14,8 @@ source "ext/hal/atmel/asf/Kconfig"
 
 source "ext/hal/altera/Kconfig"
 
+source "ext/hal/cec/Kconfig"
+
 source "ext/hal/cmsis/Kconfig"
 
 source "ext/hal/nordic/Kconfig"
diff --git a/ext/hal/cec/CMakeLists.txt b/ext/hal/cec/CMakeLists.txt
@@ -0,0 +1,3 @@
+zephyr_include_directories(
+  include
+  )
diff --git a/ext/hal/cec/Kconfig b/ext/hal/cec/Kconfig
@@ -0,0 +1,7 @@
+# Kconfig - Microchip CEC HAL drivers configuration
+#
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig HAS_CEC_HAL
+	bool "Microchip CEC HAL drivers support"
+	default n
diff --git a/ext/hal/cec/include/MEC2016_CMSIS.h b/ext/hal/cec/include/MEC2016_CMSIS.h
diff --git a/ext/hal/cec/include/MEC2016_INTERNAL.h b/ext/hal/cec/include/MEC2016_INTERNAL.h
diff --git a/ext/hal/cec/include/mec2016_rom_api.h b/ext/hal/cec/include/mec2016_rom_api.h
diff --git a/ext/hal/cec/include/system_MEC2016.h b/ext/hal/cec/include/system_MEC2016.h

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,3 @@`
	`1`	`+zephyr_sources(`
	`2`	`+ soc_config.c`
	`3`	`+ )`