@@ -837,12 +837,15 @@ typedef struct
837837#define NT_ARM_ZT 0x40d /* ARM SME ZT registers. */
838838#define NT_ARM_FPMR 0x40e /* ARM floating point mode register. */
839839#define NT_ARM_POE 0x40f /* ARM POE registers. */
840+ #define NT_ARM_GCS 0x410 /* ARM GCS state. */
840841#define NT_VMCOREDD 0x700 /* Vmcore Device Dump Note. */
841842#define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers. */
842843#define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode. */
843844#define NT_MIPS_MSA 0x802 /* MIPS SIMD registers. */
844845#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
845846#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
847+ #define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged
848+ address control */
846849#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers. */
847850#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and
848851 status registers. */
@@ -2906,19 +2909,6 @@ enum
29062909
29072910#define R_AARCH64_NONE 0 /* No relocation. */
29082911
2909- /* ILP32 AArch64 relocs. */
2910- #define R_AARCH64_P32_ABS32 1 /* Direct 32 bit. */
2911- #define R_AARCH64_P32_COPY 180 /* Copy symbol at runtime. */
2912- #define R_AARCH64_P32_GLOB_DAT 181 /* Create GOT entry. */
2913- #define R_AARCH64_P32_JUMP_SLOT 182 /* Create PLT entry. */
2914- #define R_AARCH64_P32_RELATIVE 183 /* Adjust by program base. */
2915- #define R_AARCH64_P32_TLS_DTPMOD 184 /* Module number, 32 bit. */
2916- #define R_AARCH64_P32_TLS_DTPREL 185 /* Module-relative offset, 32 bit. */
2917- #define R_AARCH64_P32_TLS_TPREL 186 /* TP-relative offset, 32 bit. */
2918- #define R_AARCH64_P32_TLSDESC 187 /* TLS Descriptor. */
2919- #define R_AARCH64_P32_IRELATIVE 188 /* STT_GNU_IFUNC relocation. */
2920-
2921- /* LP64 AArch64 relocs. */
29222912#define R_AARCH64_ABS64 257 /* Direct 64 bit. */
29232913#define R_AARCH64_ABS32 258 /* Direct 32 bit. */
29242914#define R_AARCH64_ABS16 259 /* Direct 16-bit. */
@@ -4091,6 +4081,7 @@ enum
40914081#define R_RISCV_TLS_DTPREL64 9
40924082#define R_RISCV_TLS_TPREL32 10
40934083#define R_RISCV_TLS_TPREL64 11
4084+ #define R_RISCV_TLSDESC 12
40944085#define R_RISCV_BRANCH 16
40954086#define R_RISCV_JAL 17
40964087#define R_RISCV_CALL 18
@@ -4116,16 +4107,10 @@ enum
41164107#define R_RISCV_SUB16 38
41174108#define R_RISCV_SUB32 39
41184109#define R_RISCV_SUB64 40
4119- #define R_RISCV_GNU_VTINHERIT 41
4120- #define R_RISCV_GNU_VTENTRY 42
4110+ #define R_RISCV_GOT32_PCREL 41
41214111#define R_RISCV_ALIGN 43
41224112#define R_RISCV_RVC_BRANCH 44
41234113#define R_RISCV_RVC_JUMP 45
4124- #define R_RISCV_RVC_LUI 46
4125- #define R_RISCV_GPREL_I 47
4126- #define R_RISCV_GPREL_S 48
4127- #define R_RISCV_TPREL_I 49
4128- #define R_RISCV_TPREL_S 50
41294114#define R_RISCV_RELAX 51
41304115#define R_RISCV_SUB6 52
41314116#define R_RISCV_SET6 53
@@ -4137,8 +4122,12 @@ enum
41374122#define R_RISCV_PLT32 59
41384123#define R_RISCV_SET_ULEB128 60
41394124#define R_RISCV_SUB_ULEB128 61
4125+ #define R_RISCV_TLSDESC_HI20 62
4126+ #define R_RISCV_TLSDESC_LOAD_LO12 63
4127+ #define R_RISCV_TLSDESC_ADD_LO12 64
4128+ #define R_RISCV_TLSDESC_CALL 65
41404129
4141- #define R_RISCV_NUM 62
4130+ #define R_RISCV_NUM 66
41424131
41434132/* RISC-V specific values for the st_other field. */
41444133#define STO_RISCV_VARIANT_CC 0x80 /* Function uses variant calling
@@ -4147,7 +4136,7 @@ enum
41474136/* RISC-V specific values for the sh_type field. */
41484137#define SHT_RISCV_ATTRIBUTES (SHT_LOPROC + 3)
41494138
4150- /* RISC-V specific values for the p_type field. */
4139+ /* RISC-V specific values for the p_type field (deprecated) . */
41514140#define PT_RISCV_ATTRIBUTES (PT_LOPROC + 3)
41524141
41534142/* RISC-V specific values for the d_tag field. */
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